diff --git a/db/.cmp.kpt b/db/.cmp.kpt index 8142717..8d7e5c6 100644 Binary files a/db/.cmp.kpt and b/db/.cmp.kpt differ diff --git a/db/altsyncram_q7c2.tdf b/db/altsyncram_q7c2.tdf new file mode 100644 index 0000000..382a535 --- /dev/null +++ b/db/altsyncram_q7c2.tdf @@ -0,0 +1,766 @@ +--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_REG_B="CLOCK1" LOW_POWER_MODE="AUTO" NUMWORDS_A=16384 NUMWORDS_B=16384 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="CLOCK1" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=14 WIDTHAD_B=14 WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 data_a data_b q_a q_b wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION decode_jsa (data[0..0], enable) +RETURNS ( eq[1..0]); +FUNCTION decode_c8a (data[0..0]) +RETURNS ( eq[1..0]); +FUNCTION mux_3nb (data[15..0], sel[0..0]) +RETURNS ( result[7..0]); +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 16 reg 4 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_q7c2 +( + address_a[13..0] : input; + address_b[13..0] : input; + clock0 : input; + clock1 : input; + data_a[7..0] : input; + data_b[7..0] : input; + q_a[7..0] : output; + q_b[7..0] : output; + wren_a : input; + wren_b : input; +) +VARIABLE + address_reg_a[0..0] : dffe; + address_reg_b[0..0] : dffe; + out_address_reg_a[0..0] : dffe; + out_address_reg_b[0..0] : dffe; + decode2 : decode_jsa; + decode3 : decode_jsa; + rden_decode_a : decode_c8a; + rden_decode_b : decode_c8a; + mux4 : mux_3nb; + mux5 : mux_3nb; + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_sel[0..0] : WIRE; + address_a_wire[13..0] : WIRE; + address_b_sel[0..0] : WIRE; + address_b_wire[13..0] : WIRE; + w_addr_val_a2w[0..0] : WIRE; + w_addr_val_a7w[0..0] : WIRE; + w_addr_val_b4w[0..0] : WIRE; + w_addr_val_b8w[0..0] : WIRE; + wren_decode_addr_sel_a[0..0] : WIRE; + wren_decode_addr_sel_b[0..0] : WIRE; + +BEGIN + address_reg_a[].clk = clock0; + address_reg_a[].d = address_a_sel[]; + address_reg_b[].clk = clock1; + address_reg_b[].d = address_b_sel[]; + out_address_reg_a[].clk = clock0; + out_address_reg_a[].d = address_reg_a[].q; + out_address_reg_b[].clk = clock1; + out_address_reg_b[].d = address_reg_b[].q; + decode2.data[] = w_addr_val_a2w[]; + decode2.enable = wren_a; + decode3.data[] = w_addr_val_b4w[]; + decode3.enable = wren_b; + rden_decode_a.data[] = w_addr_val_a7w[]; + rden_decode_b.data[] = w_addr_val_b8w[]; + mux4.data[] = ( ram_block1a[15..0].portadataout[0..0]); + mux4.sel[] = out_address_reg_a[].q; + mux5.data[] = ( ram_block1a[15..0].portbdataout[0..0]); + mux5.sel[] = out_address_reg_b[].q; + ram_block1a[15..0].clk0 = clock0; + ram_block1a[15..0].clk1 = clock1; + ram_block1a[15..0].ena0 = ( rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0]); + ram_block1a[15..0].ena1 = ( rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0]); + ram_block1a[15..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[0..0]); + ram_block1a[9].portadatain[] = ( data_a[1..1]); + ram_block1a[10].portadatain[] = ( data_a[2..2]); + ram_block1a[11].portadatain[] = ( data_a[3..3]); + ram_block1a[12].portadatain[] = ( data_a[4..4]); + ram_block1a[13].portadatain[] = ( data_a[5..5]); + ram_block1a[14].portadatain[] = ( data_a[6..6]); + ram_block1a[15].portadatain[] = ( data_a[7..7]); + ram_block1a[15..0].portare = B"1111111111111111"; + ram_block1a[15..0].portawe = ( decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]); + ram_block1a[15..0].portbaddr[] = ( address_b_wire[12..0]); + ram_block1a[0].portbdatain[] = ( data_b[0..0]); + ram_block1a[1].portbdatain[] = ( data_b[1..1]); + ram_block1a[2].portbdatain[] = ( data_b[2..2]); + ram_block1a[3].portbdatain[] = ( data_b[3..3]); + ram_block1a[4].portbdatain[] = ( data_b[4..4]); + ram_block1a[5].portbdatain[] = ( data_b[5..5]); + ram_block1a[6].portbdatain[] = ( data_b[6..6]); + ram_block1a[7].portbdatain[] = ( data_b[7..7]); + ram_block1a[8].portbdatain[] = ( data_b[0..0]); + ram_block1a[9].portbdatain[] = ( data_b[1..1]); + ram_block1a[10].portbdatain[] = ( data_b[2..2]); + ram_block1a[11].portbdatain[] = ( data_b[3..3]); + ram_block1a[12].portbdatain[] = ( data_b[4..4]); + ram_block1a[13].portbdatain[] = ( data_b[5..5]); + ram_block1a[14].portbdatain[] = ( data_b[6..6]); + ram_block1a[15].portbdatain[] = ( data_b[7..7]); + ram_block1a[15..0].portbre = B"1111111111111111"; + ram_block1a[15..0].portbwe = ( decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]); + address_a_sel[0..0] = address_a[13..13]; + address_a_wire[] = address_a[]; + address_b_sel[0..0] = address_b[13..13]; + address_b_wire[] = address_b[]; + q_a[] = mux4.result[]; + q_b[] = mux5.result[]; + w_addr_val_a2w[0..0] = address_a_wire[13..13]; + w_addr_val_a7w[] = wren_decode_addr_sel_a[]; + w_addr_val_b4w[0..0] = address_b_wire[13..13]; + w_addr_val_b8w[] = wren_decode_addr_sel_b[]; + wren_decode_addr_sel_a[0..0] = address_a_wire[13..13]; + wren_decode_addr_sel_b[0..0] = address_b_wire[13..13]; +END; +--VALID FILE diff --git a/db/logic_util_heursitic.dat b/db/logic_util_heursitic.dat index 9333e18..e1be902 100644 Binary files a/db/logic_util_heursitic.dat and b/db/logic_util_heursitic.dat differ diff --git a/db/pll_altpll.v b/db/pll_altpll.v index 56990bd..c0accd2 100644 --- a/db/pll_altpll.v +++ b/db/pll_altpll.v @@ -1,4 +1,4 @@ -//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=143 clk0_duty_cycle=50 clk0_multiply_by=72 clk0_phase_shift="0" clk1_divide_by=25 clk1_duty_cycle=50 clk1_multiply_by=7 clk1_phase_shift="0" clk2_divide_by=25 clk2_duty_cycle=50 clk2_multiply_by=12 clk2_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" width_clock=5 clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=2000 clk0_duty_cycle=50 clk0_multiply_by=1007 clk0_phase_shift="0" clk1_divide_by=25 clk1_duty_cycle=50 clk1_multiply_by=7 clk1_phase_shift="0" clk2_divide_by=25 clk2_duty_cycle=50 clk2_multiply_by=12 clk2_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" width_clock=5 clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 //VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:17:09:48:19:SJ cbx_altiobuf_bidir 2013:10:17:09:48:19:SJ cbx_altiobuf_in 2013:10:17:09:48:19:SJ cbx_altiobuf_out 2013:10:17:09:48:19:SJ cbx_altpll 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END //CBXI_INSTANCE_NAME="spectrum_ula_ula_pll_pll_altpll_altpll_component" // synthesis VERILOG_INPUT_VERSION VERILOG_2001 @@ -80,9 +80,9 @@ module pll_altpll ); defparam pll1.bandwidth_type = "auto", - pll1.clk0_divide_by = 143, + pll1.clk0_divide_by = 2000, pll1.clk0_duty_cycle = 50, - pll1.clk0_multiply_by = 72, + pll1.clk0_multiply_by = 1007, pll1.clk0_phase_shift = "0", pll1.clk1_divide_by = 25, pll1.clk1_duty_cycle = 50, diff --git a/db/prev_cmp_spectrum.qmsg b/db/prev_cmp_spectrum.qmsg index 059b40a..950cfe7 100644 --- a/db/prev_cmp_spectrum.qmsg +++ b/db/prev_cmp_spectrum.qmsg @@ -1,321 +1,65 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648724225148 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648724225149 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 31 13:57:05 2022 " "Processing started: Thu Mar 31 13:57:05 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648724225149 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648724225149 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648724225149 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648724225338 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225412 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225412 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225413 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225413 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225414 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225414 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225415 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225415 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225416 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225416 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225418 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225418 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225418 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225418 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225419 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225419 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225420 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225421 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225421 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225422 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225422 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225423 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225423 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225423 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225423 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225424 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225424 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225425 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225425 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225426 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225426 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225426 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225426 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225427 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225427 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225428 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225428 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225429 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225429 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225430 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225430 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225456 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225456 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225457 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225457 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225458 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225458 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225459 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225461 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225462 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225462 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225463 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225464 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225464 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225465 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225465 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225466 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225466 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225467 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225467 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225468 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225468 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225469 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225469 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225470 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225471 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225471 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225471 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225471 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648724225474 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648724225474 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225474 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225474 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225475 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225475 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225477 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225477 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225478 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225478 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225478 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225478 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225479 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225479 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225481 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225481 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225482 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225482 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225482 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225482 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225784 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225784 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225784 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225785 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225785 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225785 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225788 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724225790 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724225790 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648724225947 ""} -{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "buzzer_out spectrum.sv(95) " "Verilog HDL Always Construct warning at spectrum.sv(95): inferring latch(es) for variable \"buzzer_out\", which holds its previous value in one or more paths through the always construct" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 95 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1648724225950 "|spectrum"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[7..3\] spectrum.sv(1) " "Output port \"LED\[7..3\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648724225952 "|spectrum"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[1\] spectrum.sv(1) " "Output port \"LED\[1\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648724225952 "|spectrum"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1\[33..32\] spectrum.sv(20) " "Output port \"GPIO_1\[33..32\]\" at spectrum.sv(20) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648724225952 "|spectrum"} -{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "buzzer_out spectrum.sv(95) " "Inferred latch for \"buzzer_out\" at spectrum.sv(95)" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 95 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1648724225952 "|spectrum"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.sv" "rom" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 145 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724225965 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226024 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226025 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648724226025 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724226080 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724226080 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226080 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724226126 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724226126 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226127 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724226173 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724226173 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226174 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.sv" "ram0" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226179 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226185 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ula/test_scr.hex " "Parameter \"init_file\" = \"ula/test_scr.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226186 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648724226186 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7ti2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7ti2 " "Found entity 1: altsyncram_7ti2" { } { { "db/altsyncram_7ti2.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724226236 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724226236 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7ti2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated " "Elaborating entity \"altsyncram_7ti2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226237 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724226286 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724226286 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_7ti2.tdf" "decode2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226287 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.sv" "ram1" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226294 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226298 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226299 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648724226299 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724226350 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724226350 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226350 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724226403 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724226403 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226404 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724226447 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724226447 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226448 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724226490 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724226490 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226491 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ula ula:ula_ " "Elaborating entity \"ula\" for hierarchy \"ula:ula_\"" { } { { "spectrum.sv" "ula_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 236 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226494 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll ula:ula_\|pll:pll_ " "Elaborating entity \"pll\" for hierarchy \"ula:ula_\|pll:pll_\"" { } { { "ula/ula.sv" "pll_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226496 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226524 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborated megafunction instantiation \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724226527 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Instantiated megafunction \"ula:ula_\|pll:pll_\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 143 " "Parameter \"clk0_divide_by\" = \"143\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 72 " "Parameter \"clk0_multiply_by\" = \"72\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 25 " "Parameter \"clk1_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 7 " "Parameter \"clk1_multiply_by\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 25 " "Parameter \"clk2_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 12 " "Parameter \"clk2_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226528 ""} } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648724226528 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_altpll " "Found entity 1: pll_altpll" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724226578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724226578 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_altpll ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated " "Elaborating entity \"pll_altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226579 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clocks ula:ula_\|clocks:clocks_ " "Elaborating entity \"clocks\" for hierarchy \"ula:ula_\|clocks:clocks_\"" { } { { "ula/ula.sv" "clocks_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226581 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_loader ula:ula_\|i2c_loader:i2c_loader_ " "Elaborating entity \"i2c_loader\" for hierarchy \"ula:ula_\|i2c_loader:i2c_loader_\"" { } { { "ula/ula.sv" "i2c_loader_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 121 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226581 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2s_intf ula:ula_\|i2s_intf:i2s_intf_ " "Elaborating entity \"i2s_intf\" for hierarchy \"ula:ula_\|i2s_intf:i2s_intf_\"" { } { { "ula/ula.sv" "i2s_intf_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 141 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226583 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video ula:ula_\|video:video_ " "Elaborating entity \"video\" for hierarchy \"ula:ula_\|video:video_\"" { } { { "ula/ula.sv" "video_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 155 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226585 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ula:ula_\|ps2_keyboard:ps2_keyboard_ " "Elaborating entity \"ps2_keyboard\" for hierarchy \"ula:ula_\|ps2_keyboard:ps2_keyboard_\"" { } { { "ula/ula.sv" "ps2_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 164 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226586 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx_keyboard ula:ula_\|zx_keyboard:zx_keyboard_ " "Elaborating entity \"zx_keyboard\" for hierarchy \"ula:ula_\|zx_keyboard:zx_keyboard_\"" { } { { "ula/ula.sv" "zx_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226587 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "z80_top_direct_n z80_top_direct_n:z80_ " "Elaborating entity \"z80_top_direct_n\" for hierarchy \"z80_top_direct_n:z80_\"" { } { { "spectrum.sv" "z80_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 280 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226591 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_delay z80_top_direct_n:z80_\|clk_delay:clk_delay_ " "Elaborating entity \"clk_delay\" for hierarchy \"z80_top_direct_n:z80_\|clk_delay:clk_delay_\"" { } { { "cpu/toplevel/coremodules.vh" "clk_delay_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226594 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_state z80_top_direct_n:z80_\|decode_state:decode_state_ " "Elaborating entity \"decode_state\" for hierarchy \"z80_top_direct_n:z80_\|decode_state:decode_state_\"" { } { { "cpu/toplevel/coremodules.vh" "decode_state_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226594 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "execute z80_top_direct_n:z80_\|execute:execute_ " "Elaborating entity \"execute\" for hierarchy \"z80_top_direct_n:z80_\|execute:execute_\"" { } { { "cpu/toplevel/coremodules.vh" "execute_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226595 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interrupts z80_top_direct_n:z80_\|interrupts:interrupts_ " "Elaborating entity \"interrupts\" for hierarchy \"z80_top_direct_n:z80_\|interrupts:interrupts_\"" { } { { "cpu/toplevel/coremodules.vh" "interrupts_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 199 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226610 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir z80_top_direct_n:z80_\|ir:ir_ " "Elaborating entity \"ir\" for hierarchy \"z80_top_direct_n:z80_\|ir:ir_\"" { } { { "cpu/toplevel/coremodules.vh" "ir_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226611 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin_control z80_top_direct_n:z80_\|pin_control:pin_control_ " "Elaborating entity \"pin_control\" for hierarchy \"z80_top_direct_n:z80_\|pin_control:pin_control_\"" { } { { "cpu/toplevel/coremodules.vh" "pin_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226612 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pla_decode z80_top_direct_n:z80_\|pla_decode:pla_decode_ " "Elaborating entity \"pla_decode\" for hierarchy \"z80_top_direct_n:z80_\|pla_decode:pla_decode_\"" { } { { "cpu/toplevel/coremodules.vh" "pla_decode_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226613 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resets z80_top_direct_n:z80_\|resets:resets_ " "Elaborating entity \"resets\" for hierarchy \"z80_top_direct_n:z80_\|resets:resets_\"" { } { { "cpu/toplevel/coremodules.vh" "resets_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 240 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226615 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_ifc z80_top_direct_n:z80_\|memory_ifc:memory_ifc_ " "Elaborating entity \"memory_ifc\" for hierarchy \"z80_top_direct_n:z80_\|memory_ifc:memory_ifc_\"" { } { { "cpu/toplevel/coremodules.vh" "memory_ifc_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226615 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer z80_top_direct_n:z80_\|sequencer:sequencer_ " "Elaborating entity \"sequencer\" for hierarchy \"z80_top_direct_n:z80_\|sequencer:sequencer_\"" { } { { "cpu/toplevel/coremodules.vh" "sequencer_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226616 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control z80_top_direct_n:z80_\|alu_control:alu_control_ " "Elaborating entity \"alu_control\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226617 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_4 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux " "Elaborating entity \"alu_mux_4\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_cond_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226618 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_8 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux " "Elaborating entity \"alu_mux_8\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_shift_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 227 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226619 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_select z80_top_direct_n:z80_\|alu_select:alu_select_ " "Elaborating entity \"alu_select\" for hierarchy \"z80_top_direct_n:z80_\|alu_select:alu_select_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_select_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 363 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226620 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_flags z80_top_direct_n:z80_\|alu_flags:alu_flags_ " "Elaborating entity \"alu_flags\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_flags_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 405 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226621 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2 z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf " "Elaborating entity \"alu_mux_2\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf\"" { } { { "cpu/alu/alu_flags.v" "b2v_inst_mux_cf" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 344 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226622 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu z80_top_direct_n:z80_\|alu:alu_ " "Elaborating entity \"alu\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226623 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_core z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core " "Elaborating entity \"alu_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\"" { } { { "cpu/alu/alu.v" "b2v_core" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226624 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_slice z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0 " "Elaborating entity \"alu_slice\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0\"" { } { { "cpu/alu/alu_core.v" "b2v_alu_slice_bit_0" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226625 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_bit_select z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select " "Elaborating entity \"alu_bit_select\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\"" { } { { "cpu/alu/alu.v" "b2v_input_bit_select" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 186 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226627 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_shifter_core z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift " "Elaborating entity \"alu_shifter_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\"" { } { { "cpu/alu/alu.v" "b2v_input_shift" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 197 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226628 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high " "Elaborating entity \"alu_mux_2z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_high" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 318 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226629 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_3z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low " "Elaborating entity \"alu_mux_3z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_low" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226629 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_prep_daa z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa " "Elaborating entity \"alu_prep_daa\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa\"" { } { { "cpu/alu/alu.v" "b2v_prep_daa" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 364 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226631 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_file z80_top_direct_n:z80_\|reg_file:reg_file_ " "Elaborating entity \"reg_file\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_file_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226632 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_latch z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi " "Elaborating entity \"reg_latch\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\"" { } { { "cpu/registers/reg_file.v" "b2v_latch_af2_hi" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226634 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_control z80_top_direct_n:z80_\|reg_control:reg_control_ " "Elaborating entity \"reg_control\" for hierarchy \"z80_top_direct_n:z80_\|reg_control:reg_control_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 531 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226646 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_latch z80_top_direct_n:z80_\|address_latch:address_latch_ " "Elaborating entity \"address_latch\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\"" { } { { "cpu/toplevel/coremodules.vh" "address_latch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 547 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226647 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_mux z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7 " "Elaborating entity \"address_mux\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7\"" { } { { "cpu/bus/address_latch.v" "b2v_inst7" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 106 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226648 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec " "Elaborating entity \"inc_dec\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\"" { } { { "cpu/bus/address_latch.v" "b2v_inst_inc_dec" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226649 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec_2bit z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0 " "Elaborating entity \"inc_dec_2bit\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0\"" { } { { "cpu/bus/inc_dec.v" "b2v_dual_adder_0" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226650 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_control z80_top_direct_n:z80_\|bus_control:bus_control_ " "Elaborating entity \"bus_control\" for hierarchy \"z80_top_direct_n:z80_\|bus_control:bus_control_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226654 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_switch z80_top_direct_n:z80_\|bus_switch:bus_switch_ " "Elaborating entity \"bus_switch\" for hierarchy \"z80_top_direct_n:z80_\|bus_switch:bus_switch_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_switch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 566 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226655 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch z80_top_direct_n:z80_\|data_switch:sw2_ " "Elaborating entity \"data_switch\" for hierarchy \"z80_top_direct_n:z80_\|data_switch:sw2_\"" { } { { "cpu/toplevel/core.vh" "sw2_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226655 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch_mask z80_top_direct_n:z80_\|data_switch_mask:sw1_ " "Elaborating entity \"data_switch_mask\" for hierarchy \"z80_top_direct_n:z80_\|data_switch_mask:sw1_\"" { } { { "cpu/toplevel/core.vh" "sw1_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226656 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_pins z80_top_direct_n:z80_\|address_pins:address_pins_ " "Elaborating entity \"address_pins\" for hierarchy \"z80_top_direct_n:z80_\|address_pins:address_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "address_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226657 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_pins z80_top_direct_n:z80_\|data_pins:data_pins_ " "Elaborating entity \"data_pins\" for hierarchy \"z80_top_direct_n:z80_\|data_pins:data_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "data_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226658 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_pins_n z80_top_direct_n:z80_\|control_pins_n:control_pins_ " "Elaborating entity \"control_pins_n\" for hierarchy \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "control_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724226659 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648724231350 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\] ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\]\" to the node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\] ExtRamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\]\" to the node \"ExtRamWE\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 77 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD Equal3 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD\" to the node \"Equal3\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ Equal3 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ\" to the node \"Equal3\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231449 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648724231449 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[7\] z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[0\] z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[6\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[0\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"D\[0\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[1\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1 " "Converted the fan-out from the tri-state buffer \"D\[1\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[2\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2 " "Converted the fan-out from the tri-state buffer \"D\[2\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[3\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3 " "Converted the fan-out from the tri-state buffer \"D\[3\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[4\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4 " "Converted the fan-out from the tri-state buffer \"D\[4\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[5\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5 " "Converted the fan-out from the tri-state buffer \"D\[5\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[6\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6 " "Converted the fan-out from the tri-state buffer \"D\[6\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[7\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7 " "Converted the fan-out from the tri-state buffer \"D\[7\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724231455 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648724231455 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 127 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 201 -1 0 } } { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 93 -1 0 } } { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 97 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 108 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 109 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 33 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 59 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1648724231481 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1648724231481 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[1\] GND " "Pin \"LED\[1\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724234765 "|spectrum|LED[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[3\] GND " "Pin \"LED\[3\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724234765 "|spectrum|LED[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[4\] GND " "Pin \"LED\[4\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724234765 "|spectrum|LED[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[5\] GND " "Pin \"LED\[5\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724234765 "|spectrum|LED[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724234765 "|spectrum|LED[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724234765 "|spectrum|LED[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[24\] VCC " "Pin \"GPIO_1\[24\]\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724234765 "|spectrum|GPIO_1[24]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[32\] GND " "Pin \"GPIO_1\[32\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724234765 "|spectrum|GPIO_1[32]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[33\] GND " "Pin \"GPIO_1\[33\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724234765 "|spectrum|GPIO_1[33]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648724234765 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648724235169 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648724237998 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648724238089 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648724238349 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724238349 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724238599 "|spectrum|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724238599 "|spectrum|SW[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1648724238599 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "2738 " "Implemented 2738 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648724238599 ""} { "Info" "ICUT_CUT_TM_OPINS" "62 " "Implemented 62 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648724238599 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "2 " "Implemented 2 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1648724238599 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2599 " "Implemented 2599 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648724238599 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648724238599 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1648724238599 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648724238599 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 112 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 112 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "453 " "Peak virtual memory: 453 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648724238619 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 31 13:57:18 2022 " "Processing ended: Thu Mar 31 13:57:18 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648724238619 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648724238619 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648724238619 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648724238619 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648724239994 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648724239994 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 31 13:57:19 2022 " "Processing started: Thu Mar 31 13:57:19 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648724239994 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1648724239994 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1648724239995 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1648724240019 ""} -{ "Info" "0" "" "Project = spectrum" { } { } 0 0 "Project = spectrum" 0 0 "Fitter" 0 0 1648724240020 ""} -{ "Info" "0" "" "Revision = spectrum" { } { } 0 0 "Revision = spectrum" 0 0 "Fitter" 0 0 1648724240020 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648724240114 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648724240131 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648724240179 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648724240180 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648724240180 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1224 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648724240254 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1225 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648724240254 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1226 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648724240254 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1224 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648724240254 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648724240338 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648724240351 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648724240573 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648724240573 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648724240573 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648724240573 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5272 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724240580 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5274 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724240580 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5276 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724240580 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5278 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724240580 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5280 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724240580 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648724240580 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648724240584 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648724240590 ""} -{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1648724241787 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724241795 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648724241796 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648724241796 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 13 ula:ula_\|beep register " "Ignored filter at spectrum.sdc(13): ula:ula_\|beep could not be matched with a register" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 13 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724241796 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 13 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(13): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name beep -period 10.000 \[get_registers \{ula:ula_\|beep\}\] " "create_clock -name beep -period 10.000 \[get_registers \{ula:ula_\|beep\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 13 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648724241796 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 13 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648724241796 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724241797 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724241797 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724241797 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1648724241797 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724241798 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648724241798 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648724241798 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1648724241798 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724241799 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724241799 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 58 beep clock " "Ignored filter at spectrum.sdc(58): beep could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 58 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724241799 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724241799 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724241799 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724241799 ""} -{ "Warning" "WSTA_SCC_LOOP" "511 " "Found combinational loop of 511 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~17\|combout " "Node \"z80_\|bus_control_\|db\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~21\|datab " "Node \"z80_\|alu_\|db_high\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~21\|combout " "Node \"z80_\|alu_\|db_high\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~23\|combout " "Node \"z80_\|alu_\|db_high\[3\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~24\|combout " "Node \"z80_\|alu_\|db_high\[3\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datab " "Node \"z80_\|alu_\|db\[7\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_shift\|out_high\[3\]~0\|dataa " "Node \"z80_\|alu_\|b2v_input_shift\|out_high\[3\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_shift\|out_high\[3\]~0\|combout " "Node \"z80_\|alu_\|b2v_input_shift\|out_high\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~23\|datab " "Node \"z80_\|alu_\|db_high\[3\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|combout " "Node \"z80_\|alu_\|db_high\[2\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~5\|combout " "Node \"z80_\|alu_\|db_high\[2\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~6\|datab " "Node \"z80_\|alu_\|db_high\[2\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~6\|combout " "Node \"z80_\|alu_\|db_high\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~7\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~7\|combout " "Node \"z80_\|alu_\|db_high\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~24\|datab " "Node \"z80_\|alu_\|db\[6\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~24\|combout " "Node \"z80_\|alu_\|db\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~22\|datac " "Node \"z80_\|alu_\|db_high\[3\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~22\|combout " "Node \"z80_\|alu_\|db_high\[3\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~23\|datac " "Node \"z80_\|alu_\|db_high\[3\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~5\|datab " "Node \"z80_\|alu_\|db_high\[2\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~10\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~10\|combout " "Node \"z80_\|alu_\|db_high\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~11\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~11\|combout " "Node \"z80_\|alu_\|db_high\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|datac " "Node \"z80_\|alu_\|db_high\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|combout " "Node \"z80_\|alu_\|db_high\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~13\|combout " "Node \"z80_\|alu_\|db_high\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~22\|datab " "Node \"z80_\|alu_\|db\[5\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~22\|combout " "Node \"z80_\|alu_\|db\[5\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|datab " "Node \"z80_\|alu_\|db_high\[2\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~16\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~16\|combout " "Node \"z80_\|alu_\|db_high\[0\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~17\|combout " "Node \"z80_\|alu_\|db_high\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|datac " "Node \"z80_\|alu_\|db_high\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|combout " "Node \"z80_\|alu_\|db_high\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~19\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~19\|combout " "Node \"z80_\|alu_\|db_high\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datab " "Node \"z80_\|alu_\|db\[4\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|combout " "Node \"z80_\|alu_\|db\[4\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datac " "Node \"z80_\|alu_control_\|db\[4\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datab " "Node \"z80_\|alu_\|db\[4\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|combout " "Node \"z80_\|alu_\|db\[4\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|dataa " "Node \"z80_\|alu_\|db\[4\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datac " "Node \"z80_\|alu_\|db_low\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datab " "Node \"z80_\|alu_\|db\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|combout " "Node \"z80_\|alu_\|db\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|combout " "Node \"z80_\|alu_\|db_low\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datab " "Node \"z80_\|alu_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|dataa " "Node \"z80_\|sw2_\|db_up\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|combout " "Node \"z80_\|alu_control_\|db\[0\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|combout " "Node \"z80_\|alu_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datac " "Node \"z80_\|alu_control_\|db\[0\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~15\|datab " "Node \"z80_\|bus_control_\|db\[0\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~15\|combout " "Node \"z80_\|bus_control_\|db\[0\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|datab " "Node \"z80_\|alu_control_\|db\[0\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|combout " "Node \"z80_\|alu_control_\|db\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datab " "Node \"z80_\|alu_control_\|db\[0\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~22\|datab " "Node \"z80_\|alu_\|db_high\[3\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|datab " "Node \"z80_\|alu_\|db_low\[0\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~47\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~47\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~12\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datab " "Node \"z80_\|alu_\|db_low\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datab " "Node \"z80_\|alu_\|db_low\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|datab " "Node \"z80_\|alu_\|db_low\[2\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|combout " "Node \"z80_\|alu_\|db_low\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|combout " "Node \"z80_\|alu_\|db_low\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|datab " "Node \"z80_\|alu_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|combout " "Node \"z80_\|alu_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~64\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~64\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datab " "Node \"z80_\|alu_\|db\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|combout " "Node \"z80_\|alu_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|dataa " "Node \"z80_\|alu_\|db\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datab " "Node \"z80_\|alu_\|db_low\[2\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|datab " "Node \"z80_\|alu_\|db_low\[3\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|combout " "Node \"z80_\|alu_\|db_low\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|combout " "Node \"z80_\|alu_\|db_low\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|datab " "Node \"z80_\|alu_\|db\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|combout " "Node \"z80_\|alu_\|db\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|dataa " "Node \"z80_\|alu_\|db\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|combout " "Node \"z80_\|alu_\|db\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~16\|datab " "Node \"z80_\|alu_\|db_high\[0\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~14\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|dataa " "Node \"z80_\|alu_\|db\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datab " "Node \"z80_\|alu_control_\|db\[3\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datab " "Node \"z80_\|bus_control_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datac " "Node \"z80_\|alu_\|db_low\[0\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~14\|datac " "Node \"z80_\|alu_\|db_high\[0\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~14\|combout " "Node \"z80_\|alu_\|db_high\[0\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|datac " "Node \"z80_\|alu_\|db_high\[2\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|combout " "Node \"z80_\|alu_\|db_high\[2\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datab " "Node \"z80_\|alu_\|db_low\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|combout " "Node \"z80_\|alu_\|db_low\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datab " "Node \"z80_\|alu_\|db_low\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|datab " "Node \"z80_\|alu_\|db_high\[1\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|combout " "Node \"z80_\|alu_\|db_high\[1\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~2\|dataa " "Node \"z80_\|sw1_\|db_down\[3\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~2\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~21\|datac " "Node \"z80_\|alu_\|db_high\[3\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datab " "Node \"z80_\|alu_\|db_low\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|combout " "Node \"z80_\|alu_\|db_low\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datab " "Node \"z80_\|alu_\|db_low\[3\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datac " "Node \"z80_\|alu_control_\|db\[3\]~34\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datab " "Node \"z80_\|alu_\|db\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datab " "Node \"z80_\|alu_\|db_low\[3\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~21\|datac " "Node \"z80_\|alu_control_\|db\[2\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~21\|combout " "Node \"z80_\|alu_control_\|db\[2\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~23\|datac " "Node \"z80_\|alu_control_\|db\[2\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~23\|combout " "Node \"z80_\|alu_control_\|db\[2\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~10\|datab " "Node \"z80_\|bus_control_\|db\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~10\|combout " "Node \"z80_\|bus_control_\|db\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~11\|dataa " "Node \"z80_\|bus_control_\|db\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~11\|combout " "Node \"z80_\|bus_control_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|combout " "Node \"z80_\|alu_control_\|db\[2\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~23\|datad " "Node \"z80_\|alu_control_\|db\[2\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|dataa " "Node \"z80_\|alu_\|db\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|datad " "Node \"z80_\|alu_control_\|db\[2\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~37\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~37\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datab " "Node \"z80_\|alu_\|db\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|combout " "Node \"z80_\|alu_\|db\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|dataa " "Node \"z80_\|alu_\|db\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~9\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|datab " "Node \"z80_\|alu_\|db_low\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datac " "Node \"z80_\|alu_control_\|db\[1\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|combout " "Node \"z80_\|alu_control_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datac " "Node \"z80_\|alu_control_\|db\[1\]~26\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~12\|datab " "Node \"z80_\|bus_control_\|db\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~12\|combout " "Node \"z80_\|bus_control_\|db\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~13\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~13\|combout " "Node \"z80_\|bus_control_\|db\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datad " "Node \"z80_\|alu_control_\|db\[1\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|dataa " "Node \"z80_\|alu_\|db\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datad " "Node \"z80_\|alu_control_\|db\[1\]~25\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datab " "Node \"z80_\|alu_\|db_low\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~14\|datab " "Node \"z80_\|alu_\|db_high\[0\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|datac " "Node \"z80_\|alu_\|db_high\[1\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~24\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|dataa " "Node \"z80_\|alu_\|db\[4\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~10\|datab " "Node \"z80_\|alu_\|db_high\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~17\|datab " "Node \"z80_\|alu_\|db_high\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~11\|datab " "Node \"z80_\|alu_\|db_high\[1\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~74\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~74\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~21\|dataa " "Node \"z80_\|alu_\|db\[5\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~21\|combout " "Node \"z80_\|alu_\|db\[5\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~22\|dataa " "Node \"z80_\|alu_\|db\[5\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~29\|datab " "Node \"z80_\|alu_control_\|db\[5\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~29\|combout " "Node \"z80_\|alu_control_\|db\[5\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~28\|datac " "Node \"z80_\|alu_control_\|db\[5\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~28\|combout " "Node \"z80_\|alu_control_\|db\[5\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~29\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~21\|datab " "Node \"z80_\|alu_\|db\[5\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~17\|datab " "Node \"z80_\|bus_control_\|db\[5\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~14\|combout " "Node \"z80_\|alu_control_\|db\[6\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|datad " "Node \"z80_\|alu_control_\|db\[6\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|combout " "Node \"z80_\|alu_control_\|db\[6\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~16\|datad " "Node \"z80_\|alu_control_\|db\[6\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~16\|combout " "Node \"z80_\|alu_control_\|db\[6\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~5\|datab " "Node \"z80_\|bus_control_\|db\[6\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~5\|combout " "Node \"z80_\|bus_control_\|db\[6\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|combout " "Node \"z80_\|bus_control_\|db\[6\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~16\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|dataa " "Node \"z80_\|alu_\|db\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|combout " "Node \"z80_\|alu_\|db\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~24\|dataa " "Node \"z80_\|alu_\|db\[6\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~14\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|datab " "Node \"z80_\|alu_\|db\[6\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~1\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|combout " "Node \"z80_\|alu_control_\|db\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datad " "Node \"z80_\|alu_control_\|db\[7\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|datab " "Node \"z80_\|alu_control_\|db\[7\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|combout " "Node \"z80_\|alu_control_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~8\|datab " "Node \"z80_\|bus_control_\|db\[7\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~8\|combout " "Node \"z80_\|bus_control_\|db\[7\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~9\|combout " "Node \"z80_\|bus_control_\|db\[7\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[7\]~0\|dataa " "Node \"z80_\|sw1_\|db_down\[7\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[7\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[7\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datab " "Node \"z80_\|alu_control_\|db\[7\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|combout " "Node \"z80_\|alu_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~28\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|datab " "Node \"z80_\|alu_\|db\[7\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|datab " "Node \"z80_\|alu_\|db_high\[2\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datac " "Node \"z80_\|alu_\|db_low\[3\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datac " "Node \"z80_\|alu_\|db_low\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724241806 ""} } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 37 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Fitter" 0 -1 1648724241806 ""} -{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "511 " "Design contains combinational loop of 511 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1648724241823 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648724241854 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648724241854 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1648724241867 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1648724241870 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 4 clocks " "Found 4 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724241870 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724241870 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724241870 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724241870 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724241870 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724241870 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1648724241870 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724242053 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5260 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724242053 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724242053 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1224 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724242053 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724242053 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1224 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724242053 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724242053 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1224 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724242053 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2623 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648724242054 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724242054 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3835 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648724242054 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 61 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1379 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724242054 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3868 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3841 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3842 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3843 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3844 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3845 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[5\]~output " "Destination node GPIO_1\[5\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3846 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[6\]~output " "Destination node GPIO_1\[6\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3847 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[7\]~output " "Destination node GPIO_1\[7\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3848 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[8\]~output " "Destination node GPIO_1\[8\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3849 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724242054 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Quartus II" 0 -1 1648724242054 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648724242054 ""} } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 676 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724242054 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724242055 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 913 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724242055 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724242055 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 750 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724242055 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648724242829 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648724242832 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648724242833 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648724242837 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648724242841 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648724242845 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648724242845 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648724242848 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648724243607 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "9 I/O Output Buffer " "Packed 9 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648724243611 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "8 " "Created 8 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1648724243611 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648724243611 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724243737 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648724243737 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724243740 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648724245236 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724245979 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648724246001 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648724248895 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724248895 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648724249760 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X43_Y11 X53_Y22 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X43_Y11 to location X53_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X43_Y11 to location X53_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X43_Y11 to location X53_Y22"} 43 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648724252371 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648724252371 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Fitter routing operations ending: elapsed time is 00:00:05" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724255415 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648724255417 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648724255417 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "1.82 " "Total time spent on timing analysis during the Fitter is 1.82 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648724255562 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648724255623 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648724256374 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648724256426 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648724257105 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724258255 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648724258769 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "40 Cyclone IV E " "40 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 141 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 144 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 145 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 146 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at T14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 147 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL T13 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at T13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 148 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL R13 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at R13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 149 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL T12 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at T12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 150 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL R12 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at R12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 151 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL T11 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at T11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL T10 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at T10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL R11 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at R11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL P11 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at P11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 155 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL R10 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at R10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL N12 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at N12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 157 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL P9 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at P9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL N9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at N9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 159 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL N11 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at N11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 160 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL L16 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at L16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 161 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL K16 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at K16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 162 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL R16 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at R16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 163 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL L15 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at L15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 164 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL P15 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at P15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 165 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL P16 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at P16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 166 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R14 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 167 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL N16 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at N16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 168 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL N14 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at N14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 172 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL M10 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at M10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 173 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL L13 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at L13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 174 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL J16 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at J16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 175 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SCLK 3.3-V LVTTL F2 " "Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SCLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 183 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL F1 " "Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 7 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 184 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL T8 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at T8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 142 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL B9 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at B9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 143 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL J15 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at J15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 127 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 180 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL E1 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at E1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 128 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL B7 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_DAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 5 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 182 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL D6 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_CLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 4 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 181 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D8 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 13 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 190 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724258784 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648724258784 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648724259133 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 613 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 613 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "638 " "Peak virtual memory: 638 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648724259940 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 31 13:57:39 2022 " "Processing ended: Thu Mar 31 13:57:39 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648724259940 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Elapsed time: 00:00:20" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648724259940 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648724259940 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648724259940 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1648724261525 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648724261526 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 31 13:57:41 2022 " "Processing started: Thu Mar 31 13:57:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648724261526 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648724261526 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648724261526 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648724262742 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648724262772 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "379 " "Peak virtual memory: 379 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648724263092 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 31 13:57:43 2022 " "Processing ended: Thu Mar 31 13:57:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648724263092 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648724263092 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648724263092 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648724263092 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1648724263226 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1648724264555 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648724264556 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 31 13:57:44 2022 " "Processing started: Thu Mar 31 13:57:44 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648724264556 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648724264556 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648724264556 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648724264584 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648724264789 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648724264791 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648724264840 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648724264841 ""} -{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1648724265254 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724265263 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265264 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648724265264 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 13 ula:ula_\|beep register " "Ignored filter at spectrum.sdc(13): ula:ula_\|beep could not be matched with a register" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 13 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724265264 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 13 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(13): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name beep -period 10.000 \[get_registers \{ula:ula_\|beep\}\] " "create_clock -name beep -period 10.000 \[get_registers \{ula:ula_\|beep\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 13 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265265 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 13 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648724265265 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265266 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265266 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265266 ""} } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265266 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724265267 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265267 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648724265267 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Quartus II" 0 -1 1648724265267 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724265269 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724265269 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 58 beep clock " "Ignored filter at spectrum.sdc(58): beep could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 58 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724265269 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724265270 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724265270 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724265270 ""} -{ "Warning" "WSTA_SCC_LOOP" "511 " "Found combinational loop of 511 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~13\|combout " "Node \"z80_\|bus_control_\|db\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datac " "Node \"z80_\|alu_control_\|db\[1\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datad " "Node \"z80_\|alu_control_\|db\[1\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|dataa " "Node \"z80_\|alu_\|db\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|combout " "Node \"z80_\|alu_\|db\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|dataa " "Node \"z80_\|alu_\|db\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|combout " "Node \"z80_\|alu_\|db\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|datac " "Node \"z80_\|alu_\|db_low\[1\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datac " "Node \"z80_\|alu_\|db\[1\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datad " "Node \"z80_\|alu_\|db_low\[0\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|datad " "Node \"z80_\|alu_\|db_low\[0\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|combout " "Node \"z80_\|alu_\|db_low\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datac " "Node \"z80_\|alu_\|db_low\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datad " "Node \"z80_\|alu_\|db\[0\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|datac " "Node \"z80_\|alu_\|db_low\[0\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~22\|datac " "Node \"z80_\|alu_\|db_high\[3\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~22\|combout " "Node \"z80_\|alu_\|db_high\[3\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~23\|combout " "Node \"z80_\|alu_\|db_high\[3\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~24\|datab " "Node \"z80_\|alu_\|db_high\[3\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~24\|combout " "Node \"z80_\|alu_\|db_high\[3\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|datab " "Node \"z80_\|alu_\|db_high\[2\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|combout " "Node \"z80_\|alu_\|db_high\[2\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~5\|datac " "Node \"z80_\|alu_\|db_high\[2\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~5\|combout " "Node \"z80_\|alu_\|db_high\[2\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~6\|datad " "Node \"z80_\|alu_\|db_high\[2\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~6\|combout " "Node \"z80_\|alu_\|db_high\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~7\|datab " "Node \"z80_\|alu_\|db_high\[2\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~7\|combout " "Node \"z80_\|alu_\|db_high\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~24\|dataa " "Node \"z80_\|alu_\|db\[6\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~24\|combout " "Node \"z80_\|alu_\|db\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~10\|datad " "Node \"z80_\|alu_\|db_high\[1\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~10\|combout " "Node \"z80_\|alu_\|db_high\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~11\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~11\|combout " "Node \"z80_\|alu_\|db_high\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|combout " "Node \"z80_\|alu_\|db_high\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~13\|combout " "Node \"z80_\|alu_\|db_high\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~22\|datac " "Node \"z80_\|alu_\|db\[5\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~22\|combout " "Node \"z80_\|alu_\|db\[5\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~29\|datac " "Node \"z80_\|alu_control_\|db\[5\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~29\|combout " "Node \"z80_\|alu_control_\|db\[5\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~21\|dataa " "Node \"z80_\|alu_\|db\[5\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~21\|combout " "Node \"z80_\|alu_\|db\[5\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~22\|dataa " "Node \"z80_\|alu_\|db\[5\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~28\|combout " "Node \"z80_\|alu_control_\|db\[5\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~29\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~17\|datad " "Node \"z80_\|bus_control_\|db\[5\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~17\|combout " "Node \"z80_\|bus_control_\|db\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~28\|datac " "Node \"z80_\|alu_control_\|db\[5\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|combout " "Node \"z80_\|alu_\|db_high\[2\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datac " "Node \"z80_\|alu_\|db_low\[1\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~21\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~21\|combout " "Node \"z80_\|alu_\|db_high\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~23\|datab " "Node \"z80_\|alu_\|db_high\[3\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|combout " "Node \"z80_\|alu_\|db_low\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datab " "Node \"z80_\|alu_\|db_low\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|dataa " "Node \"z80_\|alu_\|db\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|combout " "Node \"z80_\|alu_\|db\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|dataa " "Node \"z80_\|alu_\|db\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|combout " "Node \"z80_\|alu_\|db\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datad " "Node \"z80_\|alu_control_\|db\[3\]~34\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datac " "Node \"z80_\|alu_control_\|db\[3\]~35\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datac " "Node \"z80_\|alu_\|db\[3\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datad " "Node \"z80_\|bus_control_\|db\[3\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~2\|datad " "Node \"z80_\|sw1_\|db_down\[3\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~2\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datac " "Node \"z80_\|alu_control_\|db\[3\]~34\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datac " "Node \"z80_\|alu_\|db_low\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~21\|datad " "Node \"z80_\|alu_\|db_high\[3\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datad " "Node \"z80_\|alu_\|db_low\[3\]~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~14\|datac " "Node \"z80_\|alu_\|db_high\[0\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~14\|combout " "Node \"z80_\|alu_\|db_high\[0\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|combout " "Node \"z80_\|alu_\|db_high\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~19\|datad " "Node \"z80_\|alu_\|db_high\[0\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~19\|combout " "Node \"z80_\|alu_\|db_high\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datab " "Node \"z80_\|alu_\|db\[4\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|combout " "Node \"z80_\|alu_\|db\[4\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~10\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~84\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~84\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~22\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~24\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datab " "Node \"z80_\|alu_\|db\[4\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|combout " "Node \"z80_\|alu_\|db\[4\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|dataa " "Node \"z80_\|alu_\|db\[4\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datad " "Node \"z80_\|alu_control_\|db\[4\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datac " "Node \"z80_\|alu_control_\|db\[4\]~31\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datac " "Node \"z80_\|alu_control_\|db\[4\]~32\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|dataa " "Node \"z80_\|bus_control_\|db\[4\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datad " "Node \"z80_\|alu_\|db_low\[1\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~14\|datad " "Node \"z80_\|alu_\|db_high\[0\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datad " "Node \"z80_\|alu_\|db_low\[0\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datab " "Node \"z80_\|alu_\|db_low\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datad " "Node \"z80_\|alu_\|db_low\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|datad " "Node \"z80_\|alu_\|db_high\[1\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|combout " "Node \"z80_\|alu_\|db_high\[1\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|datac " "Node \"z80_\|alu_\|db_high\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|datad " "Node \"z80_\|alu_\|db_high\[2\]~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datab " "Node \"z80_\|alu_\|db_low\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|combout " "Node \"z80_\|alu_\|db_low\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datad " "Node \"z80_\|alu_\|db_low\[2\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|combout " "Node \"z80_\|alu_\|db_low\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|datac " "Node \"z80_\|alu_\|db\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|combout " "Node \"z80_\|alu_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~21\|combout " "Node \"z80_\|alu_control_\|db\[2\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~23\|datab " "Node \"z80_\|alu_control_\|db\[2\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~23\|combout " "Node \"z80_\|alu_control_\|db\[2\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~10\|datab " "Node \"z80_\|bus_control_\|db\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~10\|combout " "Node \"z80_\|bus_control_\|db\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~11\|datab " "Node \"z80_\|bus_control_\|db\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~11\|combout " "Node \"z80_\|bus_control_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|datad " "Node \"z80_\|alu_control_\|db\[2\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|combout " "Node \"z80_\|alu_control_\|db\[2\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~23\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~0\|datab " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|datab " "Node \"z80_\|alu_control_\|db\[2\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|dataa " "Node \"z80_\|alu_\|db\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|combout " "Node \"z80_\|alu_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|dataa " "Node \"z80_\|alu_\|db\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datac " "Node \"z80_\|alu_\|db_low\[2\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|combout " "Node \"z80_\|alu_\|db_low\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datab " "Node \"z80_\|alu_\|db_low\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datab " "Node \"z80_\|alu_\|db_low\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~64\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~64\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~65\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~65\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~16\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~17\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~18\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datab " "Node \"z80_\|alu_\|db\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|datab " "Node \"z80_\|alu_\|db_low\[3\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|combout " "Node \"z80_\|alu_\|db_low\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datad " "Node \"z80_\|alu_\|db_low\[3\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|combout " "Node \"z80_\|alu_\|db_low\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datab " "Node \"z80_\|alu_\|db_low\[3\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|dataa " "Node \"z80_\|alu_\|db\[4\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~17\|combout " "Node \"z80_\|alu_\|db_high\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|datad " "Node \"z80_\|alu_\|db_high\[0\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datac " "Node \"z80_\|alu_\|db_low\[0\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|datac " "Node \"z80_\|alu_\|db_high\[1\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datad " "Node \"z80_\|alu_\|db_low\[2\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datac " "Node \"z80_\|alu_\|db_low\[3\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~55\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~55\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~56\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~56\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~13\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~14\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~15\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|datab " "Node \"z80_\|alu_\|db\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~16\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~16\|combout " "Node \"z80_\|alu_\|db_high\[0\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~17\|datad " "Node \"z80_\|alu_\|db_high\[0\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~14\|datab " "Node \"z80_\|alu_\|db_high\[0\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datab " "Node \"z80_\|alu_\|db_low\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|datab " "Node \"z80_\|alu_\|db_high\[1\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|datac " "Node \"z80_\|alu_\|db_high\[2\]~4\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~73\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~73\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~74\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~74\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~19\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~75\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~75\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~21\|datad " "Node \"z80_\|alu_\|db\[5\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~16\|datab " "Node \"z80_\|alu_\|db_high\[0\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~11\|datab " "Node \"z80_\|alu_\|db_high\[1\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~14\|datab " "Node \"z80_\|alu_control_\|db\[6\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~14\|combout " "Node \"z80_\|alu_control_\|db\[6\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|datab " "Node \"z80_\|alu_control_\|db\[6\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|combout " "Node \"z80_\|alu_control_\|db\[6\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~16\|datad " "Node \"z80_\|alu_control_\|db\[6\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~16\|combout " "Node \"z80_\|alu_control_\|db\[6\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~5\|datac " "Node \"z80_\|bus_control_\|db\[6\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~5\|combout " "Node \"z80_\|bus_control_\|db\[6\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|datab " "Node \"z80_\|bus_control_\|db\[6\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|combout " "Node \"z80_\|bus_control_\|db\[6\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~16\|datac " "Node \"z80_\|alu_control_\|db\[6\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|datab " "Node \"z80_\|alu_\|db\[6\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|combout " "Node \"z80_\|alu_\|db\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~24\|datad " "Node \"z80_\|alu_\|db\[6\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~22\|datad " "Node \"z80_\|alu_\|db_high\[3\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~14\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~15\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|dataa " "Node \"z80_\|alu_\|db\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~0\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~1\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~3\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_shift\|out_high\[3\]~0\|datac " "Node \"z80_\|alu_\|b2v_input_shift\|out_high\[3\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_shift\|out_high\[3\]~0\|combout " "Node \"z80_\|alu_\|b2v_input_shift\|out_high\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~23\|datac " "Node \"z80_\|alu_\|db_high\[3\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~28\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~4\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~5\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~6\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|combout " "Node \"z80_\|alu_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datad " "Node \"z80_\|alu_\|db\[7\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|datad " "Node \"z80_\|alu_control_\|db\[7\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|combout " "Node \"z80_\|alu_control_\|db\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|combout " "Node \"z80_\|alu_control_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~8\|datac " "Node \"z80_\|bus_control_\|db\[7\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~8\|combout " "Node \"z80_\|bus_control_\|db\[7\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~9\|datab " "Node \"z80_\|bus_control_\|db\[7\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~9\|combout " "Node \"z80_\|bus_control_\|db\[7\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[7\]~0\|datad " "Node \"z80_\|sw1_\|db_down\[7\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[7\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[7\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|datad " "Node \"z80_\|alu_control_\|db\[7\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|datab " "Node \"z80_\|alu_\|db\[7\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datad " "Node \"z80_\|alu_control_\|db\[7\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datac " "Node \"z80_\|alu_\|db_low\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~10\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~11\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~12\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~48\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~48\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datad " "Node \"z80_\|alu_\|db\[0\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|datac " "Node \"z80_\|sw2_\|db_up\[0\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datab " "Node \"z80_\|alu_control_\|db\[0\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|combout " "Node \"z80_\|alu_control_\|db\[0\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|datad " "Node \"z80_\|alu_control_\|db\[0\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|combout " "Node \"z80_\|alu_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~15\|datac " "Node \"z80_\|bus_control_\|db\[0\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~15\|combout " "Node \"z80_\|bus_control_\|db\[0\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|datac " "Node \"z80_\|alu_control_\|db\[0\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|combout " "Node \"z80_\|alu_control_\|db\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datac " "Node \"z80_\|alu_control_\|db\[0\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datac " "Node \"z80_\|alu_control_\|db\[1\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|combout " "Node \"z80_\|alu_control_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~37\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~37\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~38\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~38\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datab " "Node \"z80_\|alu_\|db\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~7\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~8\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~9\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~39\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~39\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|datac " "Node \"z80_\|alu_\|db_low\[2\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|datab " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~12\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~12\|combout " "Node \"z80_\|bus_control_\|db\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~13\|datab " "Node \"z80_\|bus_control_\|db\[1\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724265280 ""} } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 37 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1648724265280 ""} -{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "511 " "Design contains combinational loop of 511 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1648724265301 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648724265331 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648724265331 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265470 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648724265474 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648724265502 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648724265526 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648724265526 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.317 " "Worst-case setup slack is -18.317" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265526 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265526 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.317 -337.959 CLOCK_50 " " -18.317 -337.959 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265526 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.726 -40.948 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.726 -40.948 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265526 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.727 -49.356 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -3.727 -49.356 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265526 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.917 -2.917 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.917 -2.917 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265526 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724265526 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.973 " "Worst-case hold slack is -0.973" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265530 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265530 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.973 -14.722 CLOCK_50 " " -0.973 -14.722 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265530 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265530 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265530 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265530 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724265530 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.276 " "Worst-case recovery slack is -6.276" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.276 -458.770 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -6.276 -458.770 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265531 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724265531 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.680 " "Worst-case removal slack is 3.680" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.680 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.680 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265532 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724265532 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.488 " "Worst-case minimum pulse width slack is 9.488" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.594 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.594 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724265533 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724265533 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648724265649 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648724265686 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648724266614 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648724266783 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648724266783 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266785 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648724266798 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648724266798 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -17.485 " "Worst-case setup slack is -17.485" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266801 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266801 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.485 -327.998 CLOCK_50 " " -17.485 -327.998 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266801 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.418 -38.318 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.418 -38.318 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266801 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.294 -43.251 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -3.294 -43.251 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266801 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.787 -2.787 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.787 -2.787 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266801 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724266801 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.793 " "Worst-case hold slack is -0.793" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266807 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266807 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.793 -11.491 CLOCK_50 " " -0.793 -11.491 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266807 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266807 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266807 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266807 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724266807 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.783 " "Worst-case recovery slack is -5.783" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266810 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266810 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.783 -422.358 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -5.783 -422.358 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266810 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724266810 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.364 " "Worst-case removal slack is 3.364" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266813 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266813 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.364 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.364 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266813 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724266813 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.489 " "Worst-case minimum pulse width slack is 9.489" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.489 0.000 CLOCK_50 " " 9.489 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.594 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.594 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.588 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.588 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724266816 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724266816 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648724266949 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648724267227 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648724267227 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267229 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648724267235 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648724267235 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -15.103 " "Worst-case setup slack is -15.103" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267240 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267240 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.103 -288.220 CLOCK_50 " " -15.103 -288.220 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267240 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.766 -34.591 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -3.766 -34.591 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267240 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267240 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.189 -28.941 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -2.189 -28.941 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267240 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724267240 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.702 " "Worst-case hold slack is -0.702" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.702 -10.752 CLOCK_50 " " -0.702 -10.752 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267248 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724267248 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.737 " "Worst-case recovery slack is -4.737" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.737 -359.276 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.737 -359.276 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267253 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724267253 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.514 " "Worst-case removal slack is 2.514" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267258 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267258 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.514 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 2.514 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267258 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724267258 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.208 " "Worst-case minimum pulse width slack is 9.208" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267263 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267263 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.208 0.000 CLOCK_50 " " 9.208 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267263 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.640 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.640 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267263 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267263 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724267263 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724267263 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648724267798 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648724267798 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 535 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 535 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "442 " "Peak virtual memory: 442 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648724268028 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 31 13:57:48 2022 " "Processing ended: Thu Mar 31 13:57:48 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648724268028 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648724268028 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648724268028 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648724268028 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648724269918 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648724269919 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 31 13:57:49 2022 " "Processing started: Thu Mar 31 13:57:49 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648724269919 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648724269919 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648724269919 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724270827 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724271147 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724271470 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724271792 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724272052 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724272310 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724272564 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724272821 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648724272918 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 31 13:57:52 2022 " "Processing ended: Thu Mar 31 13:57:52 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648724272918 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648724272918 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648724272918 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648724272918 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 1260 s " "Quartus II Full Compilation was successful. 0 errors, 1260 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648724273071 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828489178 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:54:49 2022 " "Processing started: Fri Apr 1 18:54:49 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648828489379 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\".\"; expecting a direction spectrum.sv(6) " "Verilog HDL syntax error at spectrum.sv(6) near text \".\"; expecting a direction" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "Quartus II" 0 -1 1648828489447 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "spectrum spectrum.sv(1) " "Ignored design unit \"spectrum\" at spectrum.sv(1) due to previous errors" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1648828489448 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 0 0 " "Found 0 design units, including 0 entities, in source file spectrum.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489449 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489454 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489454 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489455 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489455 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489456 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489456 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489457 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489460 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489460 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489461 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489462 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489462 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489463 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489465 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489465 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489467 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489468 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489468 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489469 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489469 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489470 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489471 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489471 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489497 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489497 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489498 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489498 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489499 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489499 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489500 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489500 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489501 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489501 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489502 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489502 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489503 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489503 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489504 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489504 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489505 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489505 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489507 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489507 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489508 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489508 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489509 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489509 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489511 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489511 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489512 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489512 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489513 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489513 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828489515 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828489515 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489515 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489515 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489516 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489516 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489518 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489518 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489520 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489520 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489521 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489521 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489522 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489522 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489523 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489523 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489823 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489823 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489823 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489824 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489824 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489824 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489827 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489827 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489828 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489828 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489829 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489829 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648828489902 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "397 " "Peak virtual memory: 397 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828489948 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Apr 1 18:54:49 2022 " "Processing ended: Fri Apr 1 18:54:49 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 1 " "Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828490035 ""} diff --git a/db/spectrum.(0).cnf.cdb b/db/spectrum.(0).cnf.cdb index 03663d3..b7d6ba3 100644 Binary files a/db/spectrum.(0).cnf.cdb and b/db/spectrum.(0).cnf.cdb differ diff --git a/db/spectrum.(0).cnf.hdb b/db/spectrum.(0).cnf.hdb index 99c8ba4..9fe7f0d 100644 Binary files a/db/spectrum.(0).cnf.hdb and b/db/spectrum.(0).cnf.hdb differ diff --git a/db/spectrum.(16).cnf.cdb b/db/spectrum.(16).cnf.cdb index a4dbd0f..738a2bd 100644 Binary files a/db/spectrum.(16).cnf.cdb and b/db/spectrum.(16).cnf.cdb differ diff --git a/db/spectrum.(16).cnf.hdb b/db/spectrum.(16).cnf.hdb index 60dfb21..3eedbc9 100644 Binary files a/db/spectrum.(16).cnf.hdb and b/db/spectrum.(16).cnf.hdb differ diff --git a/db/spectrum.(17).cnf.cdb b/db/spectrum.(17).cnf.cdb index 5013390..906222e 100644 Binary files a/db/spectrum.(17).cnf.cdb and b/db/spectrum.(17).cnf.cdb differ diff --git a/db/spectrum.(17).cnf.hdb b/db/spectrum.(17).cnf.hdb index b00aef6..79efb08 100644 Binary files a/db/spectrum.(17).cnf.hdb and b/db/spectrum.(17).cnf.hdb differ diff --git a/db/spectrum.(19).cnf.cdb b/db/spectrum.(19).cnf.cdb index 352b3ca..a80c9be 100644 Binary files a/db/spectrum.(19).cnf.cdb and b/db/spectrum.(19).cnf.cdb differ diff --git a/db/spectrum.(19).cnf.hdb b/db/spectrum.(19).cnf.hdb index ab9f311..e0c7b19 100644 Binary files a/db/spectrum.(19).cnf.hdb and b/db/spectrum.(19).cnf.hdb differ diff --git a/db/spectrum.(73).cnf.cdb b/db/spectrum.(73).cnf.cdb new file mode 100644 index 0000000..94f70c1 Binary files /dev/null and b/db/spectrum.(73).cnf.cdb differ diff --git a/db/spectrum.(73).cnf.hdb b/db/spectrum.(73).cnf.hdb new file mode 100644 index 0000000..27654b9 Binary files /dev/null and b/db/spectrum.(73).cnf.hdb differ diff --git a/db/spectrum.(74).cnf.cdb b/db/spectrum.(74).cnf.cdb new file mode 100644 index 0000000..58c982b Binary files /dev/null and b/db/spectrum.(74).cnf.cdb differ diff --git a/db/spectrum.(74).cnf.hdb b/db/spectrum.(74).cnf.hdb new file mode 100644 index 0000000..f9d8648 Binary files /dev/null and b/db/spectrum.(74).cnf.hdb differ diff --git a/db/spectrum.(75).cnf.cdb b/db/spectrum.(75).cnf.cdb new file mode 100644 index 0000000..dbcbac6 Binary files /dev/null and b/db/spectrum.(75).cnf.cdb differ diff --git a/db/spectrum.(75).cnf.hdb b/db/spectrum.(75).cnf.hdb new file mode 100644 index 0000000..ffb5701 Binary files /dev/null and b/db/spectrum.(75).cnf.hdb differ diff --git a/db/spectrum.(76).cnf.cdb b/db/spectrum.(76).cnf.cdb new file mode 100644 index 0000000..a80c9be Binary files /dev/null and b/db/spectrum.(76).cnf.cdb differ diff --git a/db/spectrum.(76).cnf.hdb b/db/spectrum.(76).cnf.hdb new file mode 100644 index 0000000..c0a71b1 Binary files /dev/null and b/db/spectrum.(76).cnf.hdb differ diff --git a/db/spectrum.(77).cnf.cdb b/db/spectrum.(77).cnf.cdb new file mode 100644 index 0000000..a80c9be Binary files /dev/null and b/db/spectrum.(77).cnf.cdb differ diff --git a/db/spectrum.(77).cnf.hdb b/db/spectrum.(77).cnf.hdb new file mode 100644 index 0000000..65b21b3 Binary files /dev/null and b/db/spectrum.(77).cnf.hdb differ diff --git a/db/spectrum.(78).cnf.cdb b/db/spectrum.(78).cnf.cdb new file mode 100644 index 0000000..8f18762 Binary files /dev/null and b/db/spectrum.(78).cnf.cdb differ diff --git a/db/spectrum.(78).cnf.hdb b/db/spectrum.(78).cnf.hdb new file mode 100644 index 0000000..e0c7b19 Binary files /dev/null and b/db/spectrum.(78).cnf.hdb differ diff --git a/db/spectrum.(79).cnf.cdb b/db/spectrum.(79).cnf.cdb new file mode 100644 index 0000000..a5c3d30 Binary files /dev/null and b/db/spectrum.(79).cnf.cdb differ diff --git a/db/spectrum.(79).cnf.hdb b/db/spectrum.(79).cnf.hdb new file mode 100644 index 0000000..ddb7af8 Binary files /dev/null and b/db/spectrum.(79).cnf.hdb differ diff --git a/db/spectrum.asm.qmsg b/db/spectrum.asm.qmsg index 8c3a362..efa6ad6 100644 --- a/db/spectrum.asm.qmsg +++ b/db/spectrum.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648724654189 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648724654190 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 31 14:04:14 2022 " "Processing started: Thu Mar 31 14:04:14 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648724654190 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648724654190 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648724654190 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648724655397 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648724655426 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "375 " "Peak virtual memory: 375 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648724655745 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 31 14:04:15 2022 " "Processing ended: Thu Mar 31 14:04:15 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648724655745 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648724655745 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648724655745 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648724655745 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828541709 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:41 2022 " "Processing started: Fri Apr 1 18:55:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648828542963 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648828542993 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:43 2022 " "Processing ended: Fri Apr 1 18:55:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648828543318 ""} diff --git a/db/spectrum.asm.rdb b/db/spectrum.asm.rdb index 74be6af..efa9242 100644 Binary files a/db/spectrum.asm.rdb and b/db/spectrum.asm.rdb differ diff --git a/db/spectrum.asm_labs.ddb b/db/spectrum.asm_labs.ddb index bc64afa..2d8a18e 100644 Binary files a/db/spectrum.asm_labs.ddb and b/db/spectrum.asm_labs.ddb differ diff --git a/db/spectrum.cmp.bpm b/db/spectrum.cmp.bpm index 270ffe6..e4349f1 100644 Binary files a/db/spectrum.cmp.bpm and b/db/spectrum.cmp.bpm differ diff --git a/db/spectrum.cmp.cdb b/db/spectrum.cmp.cdb index f435414..decd773 100644 Binary files a/db/spectrum.cmp.cdb and b/db/spectrum.cmp.cdb differ diff --git a/db/spectrum.cmp.hdb b/db/spectrum.cmp.hdb index 8db035b..8694cf0 100644 Binary files a/db/spectrum.cmp.hdb and b/db/spectrum.cmp.hdb differ diff --git a/db/spectrum.cmp.idb b/db/spectrum.cmp.idb index 510ea5a..756f6f1 100644 Binary files a/db/spectrum.cmp.idb and b/db/spectrum.cmp.idb differ diff --git a/db/spectrum.cmp.logdb b/db/spectrum.cmp.logdb index c073ff4..c19a906 100644 --- a/db/spectrum.cmp.logdb +++ b/db/spectrum.cmp.logdb @@ -30,9 +30,9 @@ IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000 IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, -IO_RULES_MATRIX,Total Pass,74;9;74;0;0;74;74;0;74;74;0;0;0;0;40;0;0;40;0;0;2;0;0;0;0;0;0;74;0;0, +IO_RULES_MATRIX,Total Pass,75;9;75;0;0;75;75;0;75;75;0;0;0;0;41;0;0;41;0;0;2;0;0;0;0;0;0;75;0;0, IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,Total Inapplicable,0;65;0;74;74;0;0;74;0;0;74;74;74;74;34;74;74;34;74;74;72;74;74;74;74;74;74;0;74;74, +IO_RULES_MATRIX,Total Inapplicable,0;66;0;75;75;0;0;75;0;0;75;75;75;75;34;75;75;34;75;75;73;75;75;75;75;75;75;0;75;75, IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, IO_RULES_MATRIX,LED[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,LED[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, @@ -102,10 +102,11 @@ IO_RULES_MATRIX,I2C_SCLK,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inap IO_RULES_MATRIX,I2C_SDAT,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,raw_loader_in,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,PS2_DAT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,PS2_CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,AUD_ADCDAT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_SUMMARY,Total I/O Rules,30, diff --git a/db/spectrum.cmp.rdb b/db/spectrum.cmp.rdb index 445cd90..5f8f53f 100644 Binary files a/db/spectrum.cmp.rdb and b/db/spectrum.cmp.rdb differ diff --git a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd index 549f4fb..2f59583 100644 Binary files a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd and b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd differ diff --git a/db/spectrum.eda.qmsg b/db/spectrum.eda.qmsg index 78bbd6d..0d8b1e0 100644 --- a/db/spectrum.eda.qmsg +++ b/db/spectrum.eda.qmsg @@ -1,12 +1,12 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648724662545 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648724662545 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 31 14:04:22 2022 " "Processing started: Thu Mar 31 14:04:22 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648724662545 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648724662545 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648724662546 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724663449 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724663768 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724664086 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724664404 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724664660 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724664912 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724665163 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724665416 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648724665513 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 31 14:04:25 2022 " "Processing ended: Thu Mar 31 14:04:25 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648724665513 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648724665513 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648724665513 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648724665513 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828550447 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:50 2022 " "Processing started: Fri Apr 1 18:55:50 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551371 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551694 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552017 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552344 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552617 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552883 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553143 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553404 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:53 2022 " "Processing ended: Fri Apr 1 18:55:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} diff --git a/db/spectrum.fit.qmsg b/db/spectrum.fit.qmsg index 4295ba9..db1e7f9 100644 --- a/db/spectrum.fit.qmsg +++ b/db/spectrum.fit.qmsg @@ -1,71 +1,72 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648724632438 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648724632454 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648724632498 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648724632499 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648724632499 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648724632565 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648724632565 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1224 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648724632565 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648724632565 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648724632644 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648724632657 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648724632881 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648724632881 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648724632881 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648724632881 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5271 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724632888 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5273 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724632888 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5275 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724632888 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5277 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724632888 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5279 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648724632888 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648724632888 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648724632891 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648724632897 ""} -{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1648724634095 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634103 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634103 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648724634103 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634105 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634105 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634105 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1648724634105 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634105 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634106 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648724634106 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1648724634106 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634106 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634106 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634107 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634107 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648724634107 ""} -{ "Warning" "WSTA_SCC_LOOP" "514 " "Found combinational loop of 514 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~11\|combout " "Node \"z80_\|bus_control_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~21\|combout " "Node \"z80_\|alu_control_\|db\[2\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|datad " "Node \"z80_\|alu_control_\|db\[2\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|combout " "Node \"z80_\|alu_control_\|db\[2\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|dataa " "Node \"z80_\|alu_\|db\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|combout " "Node \"z80_\|alu_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|dataa " "Node \"z80_\|alu_\|db\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|combout " "Node \"z80_\|alu_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~64\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~64\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datab " "Node \"z80_\|alu_\|db\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|combout " "Node \"z80_\|alu_\|db_low\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datab " "Node \"z80_\|alu_\|db_low\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datab " "Node \"z80_\|alu_\|db\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|combout " "Node \"z80_\|alu_\|db\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~5\|datab " "Node \"z80_\|alu_\|db_low\[2\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~5\|combout " "Node \"z80_\|alu_\|db_low\[2\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|combout " "Node \"z80_\|alu_\|db_low\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~22\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~22\|combout " "Node \"z80_\|alu_\|db_low\[2\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|datab " "Node \"z80_\|alu_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~16\|combout " "Node \"z80_\|alu_\|db_low\[0\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~17\|combout " "Node \"z80_\|alu_\|db_low\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datab " "Node \"z80_\|alu_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|dataa " "Node \"z80_\|sw2_\|db_up\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|combout " "Node \"z80_\|alu_control_\|db\[0\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|combout " "Node \"z80_\|alu_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datac " "Node \"z80_\|alu_control_\|db\[0\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~15\|datab " "Node \"z80_\|bus_control_\|db\[0\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~15\|combout " "Node \"z80_\|bus_control_\|db\[0\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|datab " "Node \"z80_\|alu_control_\|db\[0\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|combout " "Node \"z80_\|alu_control_\|db\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datab " "Node \"z80_\|alu_control_\|db\[0\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|combout " "Node \"z80_\|alu_\|db_high\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~15\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~15\|combout " "Node \"z80_\|alu_\|db_high\[3\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~18\|combout " "Node \"z80_\|alu_\|db_high\[3\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~19\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~19\|combout " "Node \"z80_\|alu_\|db_high\[3\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datab " "Node \"z80_\|alu_\|db\[7\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~20\|combout " "Node \"z80_\|alu_\|db_high\[2\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~21\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~21\|combout " "Node \"z80_\|alu_\|db_high\[2\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~24\|combout " "Node \"z80_\|alu_\|db_high\[2\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~25\|combout " "Node \"z80_\|alu_\|db_high\[2\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datab " "Node \"z80_\|alu_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~21\|datab " "Node \"z80_\|alu_\|db_high\[2\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|datab " "Node \"z80_\|alu_\|db_high\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~14\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datab " "Node \"z80_\|alu_\|db\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|combout " "Node \"z80_\|alu_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~1\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~4\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~4\|combout " "Node \"z80_\|alu_\|db_high\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|combout " "Node \"z80_\|alu_\|db_high\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|datac " "Node \"z80_\|alu_\|db_high\[1\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|combout " "Node \"z80_\|alu_\|db_high\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~7\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~7\|combout " "Node \"z80_\|alu_\|db_high\[1\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~29\|datab " "Node \"z80_\|alu_control_\|db\[5\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~29\|combout " "Node \"z80_\|alu_control_\|db\[5\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~28\|datac " "Node \"z80_\|alu_control_\|db\[5\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~28\|combout " "Node \"z80_\|alu_control_\|db\[5\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~29\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datab " "Node \"z80_\|alu_\|db\[5\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|combout " "Node \"z80_\|alu_\|db\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|dataa " "Node \"z80_\|alu_\|db\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~17\|datab " "Node \"z80_\|bus_control_\|db\[5\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~17\|combout " "Node \"z80_\|bus_control_\|db\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~23\|datab " "Node \"z80_\|alu_\|db_high\[2\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~23\|combout " "Node \"z80_\|alu_\|db_high\[2\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~24\|datab " "Node \"z80_\|alu_\|db_high\[2\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|combout " "Node \"z80_\|alu_\|db_high\[3\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~18\|datac " "Node \"z80_\|alu_\|db_high\[3\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|datab " "Node \"z80_\|alu_\|db_low\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|combout " "Node \"z80_\|alu_\|db_low\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datab " "Node \"z80_\|alu_\|db_low\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~8\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~8\|combout " "Node \"z80_\|alu_\|db_high\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~12\|combout " "Node \"z80_\|alu_\|db_high\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~13\|combout " "Node \"z80_\|alu_\|db_high\[0\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datab " "Node \"z80_\|alu_\|db\[4\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|combout " "Node \"z80_\|alu_\|db\[4\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datac " "Node \"z80_\|alu_control_\|db\[4\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datab " "Node \"z80_\|alu_\|db\[4\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|combout " "Node \"z80_\|alu_\|db\[4\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|dataa " "Node \"z80_\|alu_\|db\[4\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|datab " "Node \"z80_\|alu_\|db_high\[3\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|datac " "Node \"z80_\|alu_\|db_low\[1\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~8\|datab " "Node \"z80_\|alu_\|db_high\[0\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~2\|datac " "Node \"z80_\|alu_\|db_high\[1\]~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~2\|combout " "Node \"z80_\|alu_\|db_high\[1\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datab " "Node \"z80_\|alu_\|db_low\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|combout " "Node \"z80_\|alu_\|db_low\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~23\|datab " "Node \"z80_\|alu_\|db_low\[3\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~23\|combout " "Node \"z80_\|alu_\|db_low\[3\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|datab " "Node \"z80_\|alu_\|db\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|combout " "Node \"z80_\|alu_\|db\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|dataa " "Node \"z80_\|alu_\|db\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|combout " "Node \"z80_\|alu_\|db\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~5\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~10\|datab " "Node \"z80_\|alu_\|db_high\[0\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~10\|combout " "Node \"z80_\|alu_\|db_high\[0\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~11\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~11\|combout " "Node \"z80_\|alu_\|db_high\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~12\|datac " "Node \"z80_\|alu_\|db_high\[0\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datab " "Node \"z80_\|alu_\|db_low\[3\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|combout " "Node \"z80_\|alu_\|db_low\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datab " "Node \"z80_\|alu_control_\|db\[3\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datab " "Node \"z80_\|bus_control_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|datac " "Node \"z80_\|alu_\|db_high\[3\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datac " "Node \"z80_\|alu_\|db_low\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~8\|datac " "Node \"z80_\|alu_\|db_high\[0\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~2\|datab " "Node \"z80_\|alu_\|db_high\[1\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~2\|dataa " "Node \"z80_\|sw1_\|db_down\[3\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~2\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~23\|datac " "Node \"z80_\|alu_\|db_high\[2\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|datab " "Node \"z80_\|alu_\|db_low\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|combout " "Node \"z80_\|alu_\|db_low\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datab " "Node \"z80_\|alu_\|db_low\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datac " "Node \"z80_\|alu_control_\|db\[3\]~34\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datab " "Node \"z80_\|alu_\|db\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~56\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~56\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|dataa " "Node \"z80_\|alu_\|db\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~14\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~24\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|dataa " "Node \"z80_\|alu_\|db\[4\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~4\|datab " "Node \"z80_\|alu_\|db_high\[1\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|combout " "Node \"z80_\|alu_\|db_low\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~11\|datab " "Node \"z80_\|alu_\|db_high\[0\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~2\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datac " "Node \"z80_\|alu_\|db_low\[3\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|datac " "Node \"z80_\|alu_\|db_low\[2\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~20\|datab " "Node \"z80_\|alu_\|db_high\[2\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~10\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|datab " "Node \"z80_\|alu_\|db_high\[1\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|dataa " "Node \"z80_\|alu_\|db\[5\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~14\|datab " "Node \"z80_\|alu_control_\|db\[6\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~14\|combout " "Node \"z80_\|alu_control_\|db\[6\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|datac " "Node \"z80_\|alu_control_\|db\[6\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|combout " "Node \"z80_\|alu_control_\|db\[6\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~5\|datab " "Node \"z80_\|bus_control_\|db\[6\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~5\|combout " "Node \"z80_\|bus_control_\|db\[6\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|combout " "Node \"z80_\|bus_control_\|db\[6\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~0\|dataa " "Node \"z80_\|sw1_\|db_down\[6\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|datab " "Node \"z80_\|alu_control_\|db\[6\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~15\|datab " "Node \"z80_\|alu_\|db_high\[3\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|datac " "Node \"z80_\|alu_control_\|db\[7\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|combout " "Node \"z80_\|alu_control_\|db\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datac " "Node \"z80_\|alu_control_\|db\[7\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~8\|datab " "Node \"z80_\|bus_control_\|db\[7\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~8\|combout " "Node \"z80_\|bus_control_\|db\[7\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~9\|combout " "Node \"z80_\|bus_control_\|db\[7\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|combout " "Node \"z80_\|alu_control_\|db\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datad " "Node \"z80_\|alu_control_\|db\[7\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|datad " "Node \"z80_\|alu_control_\|db\[7\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|combout " "Node \"z80_\|alu_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~28\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~29\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|datab " "Node \"z80_\|alu_\|db\[7\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~16\|datab " "Node \"z80_\|alu_\|db_low\[0\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~17\|datab " "Node \"z80_\|alu_\|db_low\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~12\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|datab " "Node \"z80_\|alu_\|db_low\[1\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~37\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~37\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datab " "Node \"z80_\|alu_\|db\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|combout " "Node \"z80_\|alu_\|db\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|dataa " "Node \"z80_\|alu_\|db\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~9\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datab " "Node \"z80_\|alu_\|db_low\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|datac " "Node \"z80_\|alu_control_\|db\[1\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|combout " "Node \"z80_\|alu_control_\|db\[1\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datad " "Node \"z80_\|alu_control_\|db\[1\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|combout " "Node \"z80_\|alu_control_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datad " "Node \"z80_\|alu_control_\|db\[1\]~25\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~12\|datab " "Node \"z80_\|bus_control_\|db\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~12\|combout " "Node \"z80_\|bus_control_\|db\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~13\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~13\|combout " "Node \"z80_\|bus_control_\|db\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|dataa " "Node \"z80_\|alu_\|db\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datab " "Node \"z80_\|alu_control_\|db\[1\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~20\|datac " "Node \"z80_\|alu_control_\|db\[2\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~20\|combout " "Node \"z80_\|alu_control_\|db\[2\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|datac " "Node \"z80_\|alu_control_\|db\[2\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|datab " "Node \"z80_\|alu_\|db_low\[3\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|datab " "Node \"z80_\|alu_\|db_low\[2\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~10\|datab " "Node \"z80_\|bus_control_\|db\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~10\|combout " "Node \"z80_\|bus_control_\|db\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~11\|dataa " "Node \"z80_\|bus_control_\|db\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~21\|datad " "Node \"z80_\|alu_control_\|db\[2\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724634113 ""} } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Fitter" 0 -1 1648724634113 ""} -{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "514 " "Design contains combinational loop of 514 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1648724634131 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648724634163 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648724634163 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1648724634177 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1648724634179 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 beep " " 10.000 beep" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648724634179 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1648724634179 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634362 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5259 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634362 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634362 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634362 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634362 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634362 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634362 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634362 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634362 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2628 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634362 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648724634362 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1220 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634362 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3834 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648724634363 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 61 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1377 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634363 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3867 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3840 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3841 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3842 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3843 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3844 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[5\]~output " "Destination node GPIO_1\[5\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3845 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[6\]~output " "Destination node GPIO_1\[6\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3846 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[7\]~output " "Destination node GPIO_1\[7\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3847 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[8\]~output " "Destination node GPIO_1\[8\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3848 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Quartus II" 0 -1 1648724634363 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648724634363 ""} } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 674 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634363 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634363 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 911 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634363 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648724634364 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 746 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648724634364 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648724635145 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648724635148 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648724635149 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648724635153 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648724635158 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648724635161 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648724635161 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648724635164 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648724635927 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "9 I/O Output Buffer " "Packed 9 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648724635931 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "8 " "Created 8 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1648724635931 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648724635931 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648724636053 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648724636053 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Fitter preparation operations ending: elapsed time is 00:00:04" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724636057 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648724637543 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724638279 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648724638301 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648724641101 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724641101 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648724641951 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "21 X43_Y11 X53_Y22 " "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X43_Y11 to location X53_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X43_Y11 to location X53_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X43_Y11 to location X53_Y22"} 43 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648724644603 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648724644603 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Fitter routing operations ending: elapsed time is 00:00:06" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724648077 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648724648079 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648724648079 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "2.36 " "Total time spent on timing analysis during the Fitter is 2.36 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648724648234 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648724648294 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648724649040 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648724649092 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648724649775 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648724650913 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648724651413 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "40 Cyclone IV E " "40 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 141 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 144 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 145 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 146 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at T14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 147 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL T13 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at T13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 148 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL R13 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at R13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 149 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL T12 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at T12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 150 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL R12 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at R12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 151 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL T11 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at T11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL T10 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at T10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL R11 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at R11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL P11 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at P11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 155 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL R10 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at R10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL N12 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at N12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 157 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL P9 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at P9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL N9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at N9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 159 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL N11 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at N11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 160 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL L16 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at L16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 161 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL K16 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at K16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 162 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL R16 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at R16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 163 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL L15 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at L15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 164 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL P15 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at P15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 165 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL P16 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at P16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 166 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R14 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 167 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL N16 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at N16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 168 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL N14 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at N14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 172 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL M10 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at M10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 173 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL L13 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at L13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 174 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL J16 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at J16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 175 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SCLK 3.3-V LVTTL F2 " "Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SCLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 182 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL F1 " "Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 7 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 183 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL T8 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at T8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 142 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL B9 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at B9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 143 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL J15 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at J15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 127 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 179 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL E1 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at E1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 128 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL B7 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_DAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 5 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 181 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL D6 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_CLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 4 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 180 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D8 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 13 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 189 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648724651428 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648724651428 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648724651780 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 613 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 613 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "633 " "Peak virtual memory: 633 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648724652593 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 31 14:04:12 2022 " "Processing ended: Thu Mar 31 14:04:12 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648724652593 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Elapsed time: 00:00:21" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648724652593 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648724652593 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648724652593 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648828519240 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648828519256 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648828519297 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648828519298 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648828519298 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648828519365 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648828519365 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648828519365 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648828519365 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648828519447 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648828519460 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648828519687 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648828519687 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648828519687 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648828519687 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5274 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5276 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5278 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5280 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5282 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648828519694 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648828519697 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648828519704 ""} +{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1648828520881 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520890 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520890 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648828520890 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520892 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520892 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520892 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1648828520892 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520892 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520892 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648828520892 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1648828520893 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520893 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520893 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520894 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520894 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520894 ""} +{ "Warning" "WSTA_SCC_LOOP" "511 " "Found combinational loop of 511 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datac " "Node \"z80_\|alu_control_\|db\[0\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|combout " "Node \"z80_\|alu_control_\|db\[0\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|combout " "Node \"z80_\|alu_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|datab " "Node \"z80_\|alu_\|db\[0\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|combout " "Node \"z80_\|alu_\|db\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|dataa " "Node \"z80_\|sw2_\|db_up\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|datac " "Node \"z80_\|alu_\|db_high\[3\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~8\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~8\|combout " "Node \"z80_\|alu_\|db_high\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|datab " "Node \"z80_\|alu_\|db\[7\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|combout " "Node \"z80_\|alu_\|db\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|combout " "Node \"z80_\|alu_\|db_high\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datac " "Node \"z80_\|alu_\|db_high\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~14\|combout " "Node \"z80_\|alu_\|db_high\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|datab " "Node \"z80_\|alu_\|db\[6\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|combout " "Node \"z80_\|alu_\|db\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datab " "Node \"z80_\|alu_\|db_high\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|combout " "Node \"z80_\|alu_control_\|db\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|datad " "Node \"z80_\|alu_control_\|db\[6\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|combout " "Node \"z80_\|alu_control_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datad " "Node \"z80_\|alu_control_\|db\[6\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|combout " "Node \"z80_\|alu_control_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datab " "Node \"z80_\|bus_control_\|db\[6\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|dataa " "Node \"z80_\|alu_\|db\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datab " "Node \"z80_\|alu_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|datac " "Node \"z80_\|alu_\|db_high\[1\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~20\|combout " "Node \"z80_\|alu_\|db_high\[1\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|datab " "Node \"z80_\|alu_\|db\[5\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|combout " "Node \"z80_\|alu_\|db\[5\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datab " "Node \"z80_\|alu_\|db_high\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|datac " "Node \"z80_\|alu_\|db_high\[0\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~26\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~26\|combout " "Node \"z80_\|alu_\|db_high\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|datab " "Node \"z80_\|alu_\|db\[4\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|combout " "Node \"z80_\|alu_\|db\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|combout " "Node \"z80_\|alu_\|db_low\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|combout " "Node \"z80_\|alu_\|db_low\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|combout " "Node \"z80_\|alu_\|db_low\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|datac " "Node \"z80_\|alu_\|db_low\[3\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|combout " "Node \"z80_\|alu_\|db_low\[3\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|datab " "Node \"z80_\|alu_\|db\[3\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|combout " "Node \"z80_\|alu_\|db\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|dataa " "Node \"z80_\|alu_\|db\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|combout " "Node \"z80_\|alu_\|db\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|datab " "Node \"z80_\|alu_\|db_low\[3\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datab " "Node \"z80_\|alu_\|db_high\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|dataa " "Node \"z80_\|alu_\|db\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|combout " "Node \"z80_\|alu_\|db_low\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|combout " "Node \"z80_\|alu_\|db_low\[2\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|combout " "Node \"z80_\|alu_\|db_low\[2\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|datab " "Node \"z80_\|alu_\|db\[2\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|combout " "Node \"z80_\|alu_\|db\[2\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datab " "Node \"z80_\|alu_\|db_low\[3\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datac " "Node \"z80_\|alu_control_\|db\[2\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datac " "Node \"z80_\|alu_control_\|db\[2\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datab " "Node \"z80_\|bus_control_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|dataa " "Node \"z80_\|bus_control_\|db\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datad " "Node \"z80_\|alu_control_\|db\[2\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|dataa " "Node \"z80_\|alu_\|db\[2\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|combout " "Node \"z80_\|alu_\|db\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|dataa " "Node \"z80_\|alu_\|db\[2\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|datab " "Node \"z80_\|alu_\|db\[2\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|datab " "Node \"z80_\|alu_\|db_low\[2\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datab " "Node \"z80_\|alu_\|db_low\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|datab " "Node \"z80_\|alu_\|db\[1\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|combout " "Node \"z80_\|alu_\|db\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|dataa " "Node \"z80_\|alu_\|db\[0\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|datab " "Node \"z80_\|alu_\|db\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|combout " "Node \"z80_\|alu_\|db\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|dataa " "Node \"z80_\|alu_\|db\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|datab " "Node \"z80_\|alu_\|db_low\[2\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|datab " "Node \"z80_\|alu_\|db_low\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datac " "Node \"z80_\|alu_control_\|db\[1\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|combout " "Node \"z80_\|alu_control_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datac " "Node \"z80_\|alu_control_\|db\[1\]~26\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datab " "Node \"z80_\|bus_control_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datad " "Node \"z80_\|alu_control_\|db\[1\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|dataa " "Node \"z80_\|alu_\|db\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datad " "Node \"z80_\|alu_control_\|db\[1\]~25\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datab " "Node \"z80_\|alu_control_\|db\[3\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datac " "Node \"z80_\|alu_control_\|db\[3\]~34\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|datab " "Node \"z80_\|alu_\|db\[3\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datab " "Node \"z80_\|bus_control_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datac " "Node \"z80_\|alu_\|db_high\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datab " "Node \"z80_\|alu_\|db_high\[3\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|combout " "Node \"z80_\|alu_\|db_high\[3\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datac " "Node \"z80_\|alu_\|db_high\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datac " "Node \"z80_\|alu_\|db_low\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datab " "Node \"z80_\|alu_\|db_high\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|combout " "Node \"z80_\|alu_\|db_high\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datac " "Node \"z80_\|alu_\|db_low\[2\]~4\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|combout " "Node \"z80_\|alu_\|db_low\[2\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|datab " "Node \"z80_\|alu_\|db_low\[2\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|datab " "Node \"z80_\|alu_\|db_low\[3\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|combout " "Node \"z80_\|alu_\|db_low\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|datab " "Node \"z80_\|alu_\|db_low\[3\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datab " "Node \"z80_\|alu_\|db_high\[0\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datab " "Node \"z80_\|alu_\|db_high\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|dataa " "Node \"z80_\|alu_\|db\[4\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|combout " "Node \"z80_\|alu_\|db\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|dataa " "Node \"z80_\|alu_\|db\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datab " "Node \"z80_\|alu_\|db_high\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~27\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datab " "Node \"z80_\|alu_\|db_high\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datac " "Node \"z80_\|alu_\|db_low\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datac " "Node \"z80_\|alu_\|db_high\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datab " "Node \"z80_\|alu_\|db\[4\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datac " "Node \"z80_\|alu_control_\|db\[4\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|dataa " "Node \"z80_\|alu_\|db\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|dataa " "Node \"z80_\|alu_\|db\[5\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|datab " "Node \"z80_\|alu_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|combout " "Node \"z80_\|alu_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datab " "Node \"z80_\|bus_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|datac " "Node \"z80_\|alu_\|db_low\[3\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datac " "Node \"z80_\|alu_\|db_high\[3\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|combout " "Node \"z80_\|alu_control_\|db\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datab " "Node \"z80_\|alu_\|db_low\[2\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|datac " "Node \"z80_\|alu_control_\|db\[5\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datab " "Node \"z80_\|alu_\|db_high\[1\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datab " "Node \"z80_\|alu_\|db\[7\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|dataa " "Node \"z80_\|alu_\|db\[7\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|datac " "Node \"z80_\|alu_control_\|db\[7\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|combout " "Node \"z80_\|alu_control_\|db\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datac " "Node \"z80_\|alu_control_\|db\[7\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datab " "Node \"z80_\|bus_control_\|db\[7\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|combout " "Node \"z80_\|alu_control_\|db\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datad " "Node \"z80_\|alu_control_\|db\[7\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|datad " "Node \"z80_\|alu_control_\|db\[7\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datab " "Node \"z80_\|alu_\|db_high\[3\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datab " "Node \"z80_\|alu_\|db_low\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datab " "Node \"z80_\|alu_\|db_low\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datab " "Node \"z80_\|alu_\|db_low\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|datab " "Node \"z80_\|alu_control_\|db\[0\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|combout " "Node \"z80_\|alu_control_\|db\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datab " "Node \"z80_\|alu_control_\|db\[0\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Fitter" 0 -1 1648828520900 ""} +{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "511 " "Design contains combinational loop of 511 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1648828520917 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648828520949 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648828520949 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1648828520963 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1648828520965 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 beep " " 10.000 beep" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1648828520966 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5262 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2620 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1219 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3836 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 62 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1372 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3869 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3842 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3843 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3844 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3845 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3846 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[5\]~output " "Destination node GPIO_1\[5\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3847 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[6\]~output " "Destination node GPIO_1\[6\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3848 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[7\]~output " "Destination node GPIO_1\[7\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3849 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[8\]~output " "Destination node GPIO_1\[8\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3850 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Quartus II" 0 -1 1648828521151 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648828521151 ""} } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 675 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521151 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 909 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521151 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521152 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 747 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521152 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648828521943 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648828521946 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648828521947 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648828521951 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648828521956 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648828521959 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648828521959 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648828521962 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648828522730 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "9 I/O Output Buffer " "Packed 9 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648828522734 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "8 " "Created 8 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1648828522734 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648828522734 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648828522858 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828522862 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648828524399 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828525162 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648828525183 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648828528419 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828528419 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648828529288 ""} +{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "7e+02 ns 1.5% " "7e+02 ns of routing delay (approximately 1.5% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1648828531514 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "26 X32_Y11 X42_Y22 " "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22"} 32 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648828532126 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648828532126 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Fitter routing operations ending: elapsed time is 00:00:06" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828535524 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648828535527 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648828535527 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "1.92 " "Total time spent on timing analysis during the Fitter is 1.92 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648828535674 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648828535735 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648828536500 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648828536554 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648828537249 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828538397 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648828538877 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "41 Cyclone IV E " "41 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 141 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 144 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 145 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 146 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at T14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 147 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL T13 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at T13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 148 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL R13 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at R13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 149 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL T12 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at T12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 150 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL R12 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at R12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 151 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL T11 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at T11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL T10 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at T10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL R11 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at R11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL P11 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at P11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 155 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL R10 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at R10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL N12 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at N12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 157 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL P9 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at P9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL N9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at N9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 159 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL N11 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at N11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 160 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL L16 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at L16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 161 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL K16 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at K16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 162 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL R16 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at R16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 163 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL L15 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at L15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 164 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL P15 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at P15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 165 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL P16 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at P16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 166 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R14 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 167 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL N16 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at N16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 168 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL N14 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at N14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 172 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL M10 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at M10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 173 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL L13 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at L13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 174 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL J16 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at J16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 175 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SCLK 3.3-V LVTTL F2 " "Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SCLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 182 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL F1 " "Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 7 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 183 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL T8 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at T8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 142 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL B9 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at B9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 143 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "raw_loader_in 3.3-V LVTTL B6 " "Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { raw_loader_in } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "raw_loader_in" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 23 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { raw_loader_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 193 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL J15 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at J15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 127 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 179 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL B7 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_DAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 5 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 181 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL E1 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at E1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 128 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL D6 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_CLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 4 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 180 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D8 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 13 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 189 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648828538892 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648828539248 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 609 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 609 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "639 " "Peak virtual memory: 639 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828540068 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:40 2022 " "Processing ended: Fri Apr 1 18:55:40 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828540068 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:22 " "Elapsed time: 00:00:22" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828540068 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828540068 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648828540068 ""} diff --git a/db/spectrum.hier_info b/db/spectrum.hier_info index 88117bb..92a74a1 100644 --- a/db/spectrum.hier_info +++ b/db/spectrum.hier_info @@ -1,12 +1,12 @@ |spectrum -LED[0] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE -LED[1] <= -LED[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE -LED[3] <= -LED[4] <= -LED[5] <= -LED[6] <= -LED[7] <= +LED[0] << SW[1].DB_MAX_OUTPUT_PORT_TYPE +LED[1] << +LED[2] << SW[2].DB_MAX_OUTPUT_PORT_TYPE +LED[3] << raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE +LED[4] << +LED[5] << +LED[6] << +LED[7] << CLOCK_50 => CLOCK_50.IN3 KEY[0] => reset.IN1 KEY[1] => nNMI.IN1 @@ -14,66 +14,67 @@ PS2_CLK => PS2_CLK.IN1 PS2_DAT => PS2_DAT.IN1 I2C_SCLK <> ula:ula_.I2C_SCLK I2C_SDAT <> ula:ula_.I2C_SDAT -AUD_XCK <= ula:ula_.AUD_XCK -AUD_ADCLRCK <= ula:ula_.AUD_ADCLRCK -AUD_DACLRCK <= ula:ula_.AUD_DACLRCK -AUD_BCLK <= ula:ula_.AUD_BCLK -AUD_DACDAT <= ula:ula_.AUD_DACDAT +AUD_XCK << ula:ula_.AUD_XCK +AUD_ADCLRCK << ula:ula_.AUD_ADCLRCK +AUD_DACLRCK << ula:ula_.AUD_DACLRCK +AUD_BCLK << ula:ula_.AUD_BCLK +AUD_DACDAT << ula:ula_.AUD_DACDAT AUD_ADCDAT => AUD_ADCDAT.IN1 -VGA_R[0] <= ula:ula_.VGA_R -VGA_R[1] <= ula:ula_.VGA_R -VGA_R[2] <= ula:ula_.VGA_R -VGA_R[3] <= ula:ula_.VGA_R -VGA_G[0] <= ula:ula_.VGA_G -VGA_G[1] <= ula:ula_.VGA_G -VGA_G[2] <= ula:ula_.VGA_G -VGA_G[3] <= ula:ula_.VGA_G -VGA_B[0] <= ula:ula_.VGA_B -VGA_B[1] <= ula:ula_.VGA_B -VGA_B[2] <= ula:ula_.VGA_B -VGA_B[3] <= ula:ula_.VGA_B -VGA_HS <= ula:ula_.VGA_HS -VGA_VS <= ula:ula_.VGA_VS +VGA_R[0] << ula:ula_.VGA_R +VGA_R[1] << ula:ula_.VGA_R +VGA_R[2] << ula:ula_.VGA_R +VGA_R[3] << ula:ula_.VGA_R +VGA_G[0] << ula:ula_.VGA_G +VGA_G[1] << ula:ula_.VGA_G +VGA_G[2] << ula:ula_.VGA_G +VGA_G[3] << ula:ula_.VGA_G +VGA_B[0] << ula:ula_.VGA_B +VGA_B[1] << ula:ula_.VGA_B +VGA_B[2] << ula:ula_.VGA_B +VGA_B[3] << ula:ula_.VGA_B +VGA_HS << ula:ula_.VGA_HS +VGA_VS << ula:ula_.VGA_VS SW[0] => ~NO_FANOUT~ SW[1] => LED[0].DATAIN SW[1] => comb.OUTPUTSELECT SW[2] => SW[2].IN1 SW[3] => ~NO_FANOUT~ -GPIO_1[0] <= A[0].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[1] <= A[1].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[2] <= A[2].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[3] <= A[3].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[4] <= A[4].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[5] <= A[5].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[6] <= A[6].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[7] <= A[7].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[8] <= A[8].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[9] <= A[9].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[10] <= A[10].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[11] <= A[11].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[12] <= A[12].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[13] <= A[13].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[14] <= A[14].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[15] <= A[15].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[16] <= D[0].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[17] <= D[1].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[18] <= D[2].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[19] <= D[3].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[20] <= D[4].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[21] <= D[5].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[22] <= D[6].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[23] <= D[7].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[24] <= z80_top_direct_n:z80_.nBUSACK -GPIO_1[25] <= z80_top_direct_n:z80_.nHALT -GPIO_1[26] <= z80_top_direct_n:z80_.nRFSH -GPIO_1[27] <= z80_top_direct_n:z80_.nWR -GPIO_1[28] <= z80_top_direct_n:z80_.nRD -GPIO_1[29] <= z80_top_direct_n:z80_.nIORQ -GPIO_1[30] <= z80_top_direct_n:z80_.nMREQ -GPIO_1[31] <= z80_top_direct_n:z80_.nM1 -GPIO_1[32] <= -GPIO_1[33] <= -buzzer_out <= ula:ula_.beep +GPIO_1[0] << A[0].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[1] << A[1].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[2] << A[2].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[3] << A[3].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[4] << A[4].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[5] << A[5].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[6] << A[6].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[7] << A[7].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[8] << A[8].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[9] << A[9].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[10] << A[10].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[11] << A[11].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[12] << A[12].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[13] << A[13].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[14] << A[14].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[15] << A[15].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[16] << D[0].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[17] << D[1].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[18] << D[2].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[19] << D[3].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[20] << D[4].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[21] << D[5].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[22] << D[6].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[23] << D[7].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[24] << z80_top_direct_n:z80_.nBUSACK +GPIO_1[25] << z80_top_direct_n:z80_.nHALT +GPIO_1[26] << z80_top_direct_n:z80_.nRFSH +GPIO_1[27] << z80_top_direct_n:z80_.nWR +GPIO_1[28] << z80_top_direct_n:z80_.nRD +GPIO_1[29] << z80_top_direct_n:z80_.nIORQ +GPIO_1[30] << z80_top_direct_n:z80_.nMREQ +GPIO_1[31] << z80_top_direct_n:z80_.nM1 +GPIO_1[32] << +GPIO_1[33] << +buzzer_out << ula:ula_.beep +raw_loader_in => raw_loader_in.IN1 |spectrum|rom0:rom @@ -2027,7 +2028,7 @@ D[2] => border[2].DATAIN D[3] => beep.IN1 D[3] => pcm_outl.DATAB D[3] => pcm_outr.DATAB -D[4] => beep.IN1 +D[4] => beep.IN0 D[4] => pcm_outl.DATAB D[4] => pcm_outr.DATAB D[5] => ~NO_FANOUT~ @@ -2076,6 +2077,8 @@ AUD_DACDAT <= i2s_intf:i2s_intf_.I2S_DOUT AUD_ADCDAT => AUD_ADCDAT.IN1 beeper <= beeper~reg0.DB_MAX_OUTPUT_PORT_TYPE beep <= beep~reg0.DB_MAX_OUTPUT_PORT_TYPE +raw_loader_in => beep.IN1 +raw_loader_in => ula_data.DATAB VGA_R[0] <= video:video_.VGA_R[0] VGA_R[1] <= video:video_.VGA_R[1] VGA_R[2] <= video:video_.VGA_R[2] diff --git a/db/spectrum.hif b/db/spectrum.hif index e771031..1ef198c 100644 Binary files a/db/spectrum.hif and b/db/spectrum.hif differ diff --git a/db/spectrum.ipinfo b/db/spectrum.ipinfo index 2938339..22d055f 100644 Binary files a/db/spectrum.ipinfo and b/db/spectrum.ipinfo differ diff --git a/db/spectrum.lpc.html b/db/spectrum.lpc.html index 04e1267..d9c37b6 100644 --- a/db/spectrum.lpc.html +++ b/db/spectrum.lpc.html @@ -1409,7 +1409,7 @@ ula_ -39 +40 2 3 2 diff --git a/db/spectrum.lpc.rdb b/db/spectrum.lpc.rdb index 588b630..3423430 100644 Binary files a/db/spectrum.lpc.rdb and b/db/spectrum.lpc.rdb differ diff --git a/db/spectrum.lpc.txt b/db/spectrum.lpc.txt index 23322b1..f3098a2 100644 --- a/db/spectrum.lpc.txt +++ b/db/spectrum.lpc.txt @@ -1307,7 +1307,7 @@ Input only Bidir : 0 Output only Bidir : 0 Hierarchy : ula_ -Input : 39 +Input : 40 Constant Input : 2 Unused Input : 3 Floating Input : 2 diff --git a/db/spectrum.map.bpm b/db/spectrum.map.bpm index b43c144..2eeb07a 100644 Binary files a/db/spectrum.map.bpm and b/db/spectrum.map.bpm differ diff --git a/db/spectrum.map.cdb b/db/spectrum.map.cdb index 3ac7764..0aaf4b3 100644 Binary files a/db/spectrum.map.cdb and b/db/spectrum.map.cdb differ diff --git a/db/spectrum.map.hdb b/db/spectrum.map.hdb index 10a5c6e..e01f3b5 100644 Binary files a/db/spectrum.map.hdb and b/db/spectrum.map.hdb differ diff --git a/db/spectrum.map.kpt b/db/spectrum.map.kpt index 3d54533..ca4b38c 100644 Binary files a/db/spectrum.map.kpt and b/db/spectrum.map.kpt differ diff --git a/db/spectrum.map.qmsg b/db/spectrum.map.qmsg index 4714300..5e06b04 100644 --- a/db/spectrum.map.qmsg +++ b/db/spectrum.map.qmsg @@ -1,158 +1,159 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648724617687 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648724617688 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 31 14:03:37 2022 " "Processing started: Thu Mar 31 14:03:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648724617688 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648724617688 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648724617688 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648724617885 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617955 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617955 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617957 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617957 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617958 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617958 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617958 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617958 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617960 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617960 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617961 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617961 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617962 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617962 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617963 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617963 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617963 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617963 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617965 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617965 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617965 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617965 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617966 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617966 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617967 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617967 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617967 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617967 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617968 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617968 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617969 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617969 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617970 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617970 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617971 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617971 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617971 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617971 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617972 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617972 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617973 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617973 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617998 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617998 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724617999 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724617999 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618000 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618000 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618001 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618001 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618002 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618002 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618004 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618004 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618004 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618004 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618005 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618005 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618006 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618006 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618007 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618007 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618008 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618008 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618009 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618009 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618009 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618009 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618010 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618010 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618011 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618011 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618012 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618012 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618013 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618013 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618013 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618013 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618014 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618014 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648724618017 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648724618017 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618017 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618017 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618018 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618018 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618019 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618019 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618020 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618020 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618021 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618021 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618022 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618022 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618023 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618023 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618024 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618024 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618025 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618025 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618322 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618322 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618322 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618323 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618323 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618323 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618326 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618326 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618327 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618327 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648724618488 ""} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[7..3\] spectrum.sv(1) " "Output port \"LED\[7..3\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648724618492 "|spectrum"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[1\] spectrum.sv(1) " "Output port \"LED\[1\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648724618493 "|spectrum"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1\[33..32\] spectrum.sv(20) " "Output port \"GPIO_1\[33..32\]\" at spectrum.sv(20) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648724618493 "|spectrum"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.sv" "rom" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 131 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618504 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618556 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618557 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648724618557 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618607 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618607 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618608 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618651 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618651 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618652 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618695 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618695 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618695 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.sv" "ram0" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618699 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618704 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ula/test_scr.hex " "Parameter \"init_file\" = \"ula/test_scr.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618705 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648724618705 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7ti2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7ti2 " "Found entity 1: altsyncram_7ti2" { } { { "db/altsyncram_7ti2.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618755 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618755 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7ti2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated " "Elaborating entity \"altsyncram_7ti2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618755 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618798 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618798 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_7ti2.tdf" "decode2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618799 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.sv" "ram1" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 166 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618805 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618809 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618810 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648724618810 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618861 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618861 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618862 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618905 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618905 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618905 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618948 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618948 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618948 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724618991 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724618991 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618991 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ula ula:ula_ " "Elaborating entity \"ula\" for hierarchy \"ula:ula_\"" { } { { "spectrum.sv" "ula_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724618994 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll ula:ula_\|pll:pll_ " "Elaborating entity \"pll\" for hierarchy \"ula:ula_\|pll:pll_\"" { } { { "ula/ula.sv" "pll_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 82 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619001 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619030 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborated megafunction instantiation \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724619033 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Instantiated megafunction \"ula:ula_\|pll:pll_\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 143 " "Parameter \"clk0_divide_by\" = \"143\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 72 " "Parameter \"clk0_multiply_by\" = \"72\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 25 " "Parameter \"clk1_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 7 " "Parameter \"clk1_multiply_by\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 25 " "Parameter \"clk2_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 12 " "Parameter \"clk2_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619034 ""} } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648724619034 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_altpll " "Found entity 1: pll_altpll" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648724619084 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648724619084 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_altpll ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated " "Elaborating entity \"pll_altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619085 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clocks ula:ula_\|clocks:clocks_ " "Elaborating entity \"clocks\" for hierarchy \"ula:ula_\|clocks:clocks_\"" { } { { "ula/ula.sv" "clocks_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 84 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619087 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_loader ula:ula_\|i2c_loader:i2c_loader_ " "Elaborating entity \"i2c_loader\" for hierarchy \"ula:ula_\|i2c_loader:i2c_loader_\"" { } { { "ula/ula.sv" "i2c_loader_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 122 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619087 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2s_intf ula:ula_\|i2s_intf:i2s_intf_ " "Elaborating entity \"i2s_intf\" for hierarchy \"ula:ula_\|i2s_intf:i2s_intf_\"" { } { { "ula/ula.sv" "i2s_intf_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 142 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619089 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video ula:ula_\|video:video_ " "Elaborating entity \"video\" for hierarchy \"ula:ula_\|video:video_\"" { } { { "ula/ula.sv" "video_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 156 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619091 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ula:ula_\|ps2_keyboard:ps2_keyboard_ " "Elaborating entity \"ps2_keyboard\" for hierarchy \"ula:ula_\|ps2_keyboard:ps2_keyboard_\"" { } { { "ula/ula.sv" "ps2_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619092 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx_keyboard ula:ula_\|zx_keyboard:zx_keyboard_ " "Elaborating entity \"zx_keyboard\" for hierarchy \"ula:ula_\|zx_keyboard:zx_keyboard_\"" { } { { "ula/ula.sv" "zx_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 168 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619093 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "z80_top_direct_n z80_top_direct_n:z80_ " "Elaborating entity \"z80_top_direct_n\" for hierarchy \"z80_top_direct_n:z80_\"" { } { { "spectrum.sv" "z80_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 267 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619096 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_delay z80_top_direct_n:z80_\|clk_delay:clk_delay_ " "Elaborating entity \"clk_delay\" for hierarchy \"z80_top_direct_n:z80_\|clk_delay:clk_delay_\"" { } { { "cpu/toplevel/coremodules.vh" "clk_delay_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619099 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_state z80_top_direct_n:z80_\|decode_state:decode_state_ " "Elaborating entity \"decode_state\" for hierarchy \"z80_top_direct_n:z80_\|decode_state:decode_state_\"" { } { { "cpu/toplevel/coremodules.vh" "decode_state_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619100 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "execute z80_top_direct_n:z80_\|execute:execute_ " "Elaborating entity \"execute\" for hierarchy \"z80_top_direct_n:z80_\|execute:execute_\"" { } { { "cpu/toplevel/coremodules.vh" "execute_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619101 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interrupts z80_top_direct_n:z80_\|interrupts:interrupts_ " "Elaborating entity \"interrupts\" for hierarchy \"z80_top_direct_n:z80_\|interrupts:interrupts_\"" { } { { "cpu/toplevel/coremodules.vh" "interrupts_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 199 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619115 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir z80_top_direct_n:z80_\|ir:ir_ " "Elaborating entity \"ir\" for hierarchy \"z80_top_direct_n:z80_\|ir:ir_\"" { } { { "cpu/toplevel/coremodules.vh" "ir_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619116 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin_control z80_top_direct_n:z80_\|pin_control:pin_control_ " "Elaborating entity \"pin_control\" for hierarchy \"z80_top_direct_n:z80_\|pin_control:pin_control_\"" { } { { "cpu/toplevel/coremodules.vh" "pin_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619117 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pla_decode z80_top_direct_n:z80_\|pla_decode:pla_decode_ " "Elaborating entity \"pla_decode\" for hierarchy \"z80_top_direct_n:z80_\|pla_decode:pla_decode_\"" { } { { "cpu/toplevel/coremodules.vh" "pla_decode_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619117 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resets z80_top_direct_n:z80_\|resets:resets_ " "Elaborating entity \"resets\" for hierarchy \"z80_top_direct_n:z80_\|resets:resets_\"" { } { { "cpu/toplevel/coremodules.vh" "resets_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 240 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619119 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_ifc z80_top_direct_n:z80_\|memory_ifc:memory_ifc_ " "Elaborating entity \"memory_ifc\" for hierarchy \"z80_top_direct_n:z80_\|memory_ifc:memory_ifc_\"" { } { { "cpu/toplevel/coremodules.vh" "memory_ifc_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619120 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer z80_top_direct_n:z80_\|sequencer:sequencer_ " "Elaborating entity \"sequencer\" for hierarchy \"z80_top_direct_n:z80_\|sequencer:sequencer_\"" { } { { "cpu/toplevel/coremodules.vh" "sequencer_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619121 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control z80_top_direct_n:z80_\|alu_control:alu_control_ " "Elaborating entity \"alu_control\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619122 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_4 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux " "Elaborating entity \"alu_mux_4\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_cond_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619123 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_8 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux " "Elaborating entity \"alu_mux_8\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_shift_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 227 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619124 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_select z80_top_direct_n:z80_\|alu_select:alu_select_ " "Elaborating entity \"alu_select\" for hierarchy \"z80_top_direct_n:z80_\|alu_select:alu_select_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_select_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 363 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619125 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_flags z80_top_direct_n:z80_\|alu_flags:alu_flags_ " "Elaborating entity \"alu_flags\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_flags_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 405 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619125 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2 z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf " "Elaborating entity \"alu_mux_2\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf\"" { } { { "cpu/alu/alu_flags.v" "b2v_inst_mux_cf" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 344 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619126 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu z80_top_direct_n:z80_\|alu:alu_ " "Elaborating entity \"alu\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619127 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_core z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core " "Elaborating entity \"alu_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\"" { } { { "cpu/alu/alu.v" "b2v_core" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619129 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_slice z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0 " "Elaborating entity \"alu_slice\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0\"" { } { { "cpu/alu/alu_core.v" "b2v_alu_slice_bit_0" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619130 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_bit_select z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select " "Elaborating entity \"alu_bit_select\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\"" { } { { "cpu/alu/alu.v" "b2v_input_bit_select" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 186 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619132 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_shifter_core z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift " "Elaborating entity \"alu_shifter_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\"" { } { { "cpu/alu/alu.v" "b2v_input_shift" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 197 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619132 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high " "Elaborating entity \"alu_mux_2z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_high" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 318 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619133 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_3z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low " "Elaborating entity \"alu_mux_3z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_low" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619134 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_prep_daa z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa " "Elaborating entity \"alu_prep_daa\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa\"" { } { { "cpu/alu/alu.v" "b2v_prep_daa" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 364 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619136 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_file z80_top_direct_n:z80_\|reg_file:reg_file_ " "Elaborating entity \"reg_file\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_file_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619137 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_latch z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi " "Elaborating entity \"reg_latch\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\"" { } { { "cpu/registers/reg_file.v" "b2v_latch_af2_hi" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619138 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_control z80_top_direct_n:z80_\|reg_control:reg_control_ " "Elaborating entity \"reg_control\" for hierarchy \"z80_top_direct_n:z80_\|reg_control:reg_control_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 531 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619151 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_latch z80_top_direct_n:z80_\|address_latch:address_latch_ " "Elaborating entity \"address_latch\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\"" { } { { "cpu/toplevel/coremodules.vh" "address_latch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 547 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619152 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_mux z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7 " "Elaborating entity \"address_mux\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7\"" { } { { "cpu/bus/address_latch.v" "b2v_inst7" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 106 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619154 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec " "Elaborating entity \"inc_dec\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\"" { } { { "cpu/bus/address_latch.v" "b2v_inst_inc_dec" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619155 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec_2bit z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0 " "Elaborating entity \"inc_dec_2bit\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0\"" { } { { "cpu/bus/inc_dec.v" "b2v_dual_adder_0" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619155 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_control z80_top_direct_n:z80_\|bus_control:bus_control_ " "Elaborating entity \"bus_control\" for hierarchy \"z80_top_direct_n:z80_\|bus_control:bus_control_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619159 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_switch z80_top_direct_n:z80_\|bus_switch:bus_switch_ " "Elaborating entity \"bus_switch\" for hierarchy \"z80_top_direct_n:z80_\|bus_switch:bus_switch_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_switch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 566 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619160 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch z80_top_direct_n:z80_\|data_switch:sw2_ " "Elaborating entity \"data_switch\" for hierarchy \"z80_top_direct_n:z80_\|data_switch:sw2_\"" { } { { "cpu/toplevel/core.vh" "sw2_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619161 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch_mask z80_top_direct_n:z80_\|data_switch_mask:sw1_ " "Elaborating entity \"data_switch_mask\" for hierarchy \"z80_top_direct_n:z80_\|data_switch_mask:sw1_\"" { } { { "cpu/toplevel/core.vh" "sw1_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619162 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_pins z80_top_direct_n:z80_\|address_pins:address_pins_ " "Elaborating entity \"address_pins\" for hierarchy \"z80_top_direct_n:z80_\|address_pins:address_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "address_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619163 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_pins z80_top_direct_n:z80_\|data_pins:data_pins_ " "Elaborating entity \"data_pins\" for hierarchy \"z80_top_direct_n:z80_\|data_pins:data_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "data_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619164 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_pins_n z80_top_direct_n:z80_\|control_pins_n:control_pins_ " "Elaborating entity \"control_pins_n\" for hierarchy \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "control_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648724619164 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648724623777 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\] ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\]\" to the node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\] ExtRamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\]\" to the node \"ExtRamWE\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 77 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD Equal2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD\" to the node \"Equal2\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ Equal2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ\" to the node \"Equal2\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623875 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648724623875 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[7\] z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[0\] z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[6\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[0\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"D\[0\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[1\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1 " "Converted the fan-out from the tri-state buffer \"D\[1\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[2\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2 " "Converted the fan-out from the tri-state buffer \"D\[2\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[3\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3 " "Converted the fan-out from the tri-state buffer \"D\[3\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[4\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4 " "Converted the fan-out from the tri-state buffer \"D\[4\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[5\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5 " "Converted the fan-out from the tri-state buffer \"D\[5\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[6\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6 " "Converted the fan-out from the tri-state buffer \"D\[6\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[7\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7 " "Converted the fan-out from the tri-state buffer \"D\[7\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648724623881 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648724623881 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 127 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 201 -1 0 } } { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 93 -1 0 } } { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 97 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 108 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 109 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 33 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 59 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1648724623907 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1648724623907 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[1\] GND " "Pin \"LED\[1\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724627144 "|spectrum|LED[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[3\] GND " "Pin \"LED\[3\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724627144 "|spectrum|LED[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[4\] GND " "Pin \"LED\[4\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724627144 "|spectrum|LED[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[5\] GND " "Pin \"LED\[5\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724627144 "|spectrum|LED[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724627144 "|spectrum|LED[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724627144 "|spectrum|LED[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[24\] VCC " "Pin \"GPIO_1\[24\]\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724627144 "|spectrum|GPIO_1[24]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[32\] GND " "Pin \"GPIO_1\[32\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724627144 "|spectrum|GPIO_1[32]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[33\] GND " "Pin \"GPIO_1\[33\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648724627144 "|spectrum|GPIO_1[33]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648724627144 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648724627535 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648724630305 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648724630393 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648724630645 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724630645 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724630893 "|spectrum|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724630893 "|spectrum|SW[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1648724630893 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "2739 " "Implemented 2739 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648724630894 ""} { "Info" "ICUT_CUT_TM_OPINS" "62 " "Implemented 62 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648724630894 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "2 " "Implemented 2 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1648724630894 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2600 " "Implemented 2600 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648724630894 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648724630894 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1648724630894 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648724630894 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 111 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 111 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "442 " "Peak virtual memory: 442 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648724630917 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 31 14:03:50 2022 " "Processing ended: Thu Mar 31 14:03:50 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648724630917 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648724630917 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648724630917 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648724630917 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828504365 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828504366 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:04 2022 " "Processing started: Fri Apr 1 18:55:04 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828504366 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828504366 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828504367 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648828504551 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504625 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504625 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504626 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504626 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504627 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504627 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504628 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504628 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504629 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504629 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504630 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504630 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504631 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504631 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504632 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504633 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504633 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504634 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504634 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504635 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504635 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504635 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504635 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504636 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504636 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504637 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504637 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504638 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504638 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504639 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504639 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504639 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504639 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504640 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504640 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504641 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504641 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504642 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504642 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504643 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504643 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504669 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504669 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504670 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504670 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504671 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504671 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504672 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504672 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504673 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504673 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504675 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504675 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504675 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504675 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504676 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504676 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504677 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504677 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504678 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504678 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504679 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504679 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504680 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504680 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504680 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504680 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504681 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504681 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504682 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504682 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504683 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504683 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504684 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504684 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504685 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504685 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828504688 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828504688 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504688 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504688 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504689 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504689 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504691 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504691 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504692 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504692 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504692 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504692 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504693 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504693 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504695 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504695 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504695 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504695 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504696 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504696 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505020 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505020 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505020 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505021 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505021 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505021 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505024 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505024 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505025 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505025 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505026 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505026 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648828505193 ""} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[7..4\] spectrum.sv(1) " "Output port \"LED\[7..4\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648828505195 "|spectrum"} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[1\] spectrum.sv(1) " "Output port \"LED\[1\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648828505195 "|spectrum"} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1\[33..32\] spectrum.sv(20) " "Output port \"GPIO_1\[33..32\]\" at spectrum.sv(20) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648828505195 "|spectrum"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.sv" "rom" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 135 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505197 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505251 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648828505252 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505305 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505305 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505305 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505350 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505350 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505350 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505395 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505395 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505396 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.sv" "ram0" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505400 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505404 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828505405 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ula/test_scr.hex " "Parameter \"init_file\" = \"ula/test_scr.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648828505406 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7ti2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7ti2 " "Found entity 1: altsyncram_7ti2" { } { { "db/altsyncram_7ti2.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505460 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505460 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7ti2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated " "Elaborating entity \"altsyncram_7ti2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505460 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505507 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505507 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_7ti2.tdf" "decode2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505508 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.sv" "ram1" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505514 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505518 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648828505519 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505573 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505573 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505573 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505618 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505619 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505662 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505662 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505662 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505706 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505706 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505707 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ula ula:ula_ " "Elaborating entity \"ula\" for hierarchy \"ula:ula_\"" { } { { "spectrum.sv" "ula_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505709 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll ula:ula_\|pll:pll_ " "Elaborating entity \"pll\" for hierarchy \"ula:ula_\|pll:pll_\"" { } { { "ula/ula.sv" "pll_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505711 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505739 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborated megafunction instantiation \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Instantiated megafunction \"ula:ula_\|pll:pll_\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2000 " "Parameter \"clk0_divide_by\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1007 " "Parameter \"clk0_multiply_by\" = \"1007\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 25 " "Parameter \"clk1_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 7 " "Parameter \"clk1_multiply_by\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 25 " "Parameter \"clk2_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 12 " "Parameter \"clk2_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648828505744 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_altpll " "Found entity 1: pll_altpll" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505797 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505797 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_altpll ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated " "Elaborating entity \"pll_altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505798 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clocks ula:ula_\|clocks:clocks_ " "Elaborating entity \"clocks\" for hierarchy \"ula:ula_\|clocks:clocks_\"" { } { { "ula/ula.sv" "clocks_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505800 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_loader ula:ula_\|i2c_loader:i2c_loader_ " "Elaborating entity \"i2c_loader\" for hierarchy \"ula:ula_\|i2c_loader:i2c_loader_\"" { } { { "ula/ula.sv" "i2c_loader_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505801 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2s_intf ula:ula_\|i2s_intf:i2s_intf_ " "Elaborating entity \"i2s_intf\" for hierarchy \"ula:ula_\|i2s_intf:i2s_intf_\"" { } { { "ula/ula.sv" "i2s_intf_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505803 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video ula:ula_\|video:video_ " "Elaborating entity \"video\" for hierarchy \"ula:ula_\|video:video_\"" { } { { "ula/ula.sv" "video_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505805 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ula:ula_\|ps2_keyboard:ps2_keyboard_ " "Elaborating entity \"ps2_keyboard\" for hierarchy \"ula:ula_\|ps2_keyboard:ps2_keyboard_\"" { } { { "ula/ula.sv" "ps2_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505806 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx_keyboard ula:ula_\|zx_keyboard:zx_keyboard_ " "Elaborating entity \"zx_keyboard\" for hierarchy \"ula:ula_\|zx_keyboard:zx_keyboard_\"" { } { { "ula/ula.sv" "zx_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505807 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "z80_top_direct_n z80_top_direct_n:z80_ " "Elaborating entity \"z80_top_direct_n\" for hierarchy \"z80_top_direct_n:z80_\"" { } { { "spectrum.sv" "z80_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505811 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_delay z80_top_direct_n:z80_\|clk_delay:clk_delay_ " "Elaborating entity \"clk_delay\" for hierarchy \"z80_top_direct_n:z80_\|clk_delay:clk_delay_\"" { } { { "cpu/toplevel/coremodules.vh" "clk_delay_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505814 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_state z80_top_direct_n:z80_\|decode_state:decode_state_ " "Elaborating entity \"decode_state\" for hierarchy \"z80_top_direct_n:z80_\|decode_state:decode_state_\"" { } { { "cpu/toplevel/coremodules.vh" "decode_state_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505814 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "execute z80_top_direct_n:z80_\|execute:execute_ " "Elaborating entity \"execute\" for hierarchy \"z80_top_direct_n:z80_\|execute:execute_\"" { } { { "cpu/toplevel/coremodules.vh" "execute_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505815 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interrupts z80_top_direct_n:z80_\|interrupts:interrupts_ " "Elaborating entity \"interrupts\" for hierarchy \"z80_top_direct_n:z80_\|interrupts:interrupts_\"" { } { { "cpu/toplevel/coremodules.vh" "interrupts_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 199 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505830 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir z80_top_direct_n:z80_\|ir:ir_ " "Elaborating entity \"ir\" for hierarchy \"z80_top_direct_n:z80_\|ir:ir_\"" { } { { "cpu/toplevel/coremodules.vh" "ir_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505830 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin_control z80_top_direct_n:z80_\|pin_control:pin_control_ " "Elaborating entity \"pin_control\" for hierarchy \"z80_top_direct_n:z80_\|pin_control:pin_control_\"" { } { { "cpu/toplevel/coremodules.vh" "pin_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505831 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pla_decode z80_top_direct_n:z80_\|pla_decode:pla_decode_ " "Elaborating entity \"pla_decode\" for hierarchy \"z80_top_direct_n:z80_\|pla_decode:pla_decode_\"" { } { { "cpu/toplevel/coremodules.vh" "pla_decode_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505832 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resets z80_top_direct_n:z80_\|resets:resets_ " "Elaborating entity \"resets\" for hierarchy \"z80_top_direct_n:z80_\|resets:resets_\"" { } { { "cpu/toplevel/coremodules.vh" "resets_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 240 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505834 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_ifc z80_top_direct_n:z80_\|memory_ifc:memory_ifc_ " "Elaborating entity \"memory_ifc\" for hierarchy \"z80_top_direct_n:z80_\|memory_ifc:memory_ifc_\"" { } { { "cpu/toplevel/coremodules.vh" "memory_ifc_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505835 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer z80_top_direct_n:z80_\|sequencer:sequencer_ " "Elaborating entity \"sequencer\" for hierarchy \"z80_top_direct_n:z80_\|sequencer:sequencer_\"" { } { { "cpu/toplevel/coremodules.vh" "sequencer_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505836 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control z80_top_direct_n:z80_\|alu_control:alu_control_ " "Elaborating entity \"alu_control\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505836 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_4 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux " "Elaborating entity \"alu_mux_4\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_cond_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505837 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_8 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux " "Elaborating entity \"alu_mux_8\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_shift_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 227 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505839 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_select z80_top_direct_n:z80_\|alu_select:alu_select_ " "Elaborating entity \"alu_select\" for hierarchy \"z80_top_direct_n:z80_\|alu_select:alu_select_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_select_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 363 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505839 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_flags z80_top_direct_n:z80_\|alu_flags:alu_flags_ " "Elaborating entity \"alu_flags\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_flags_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 405 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505840 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2 z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf " "Elaborating entity \"alu_mux_2\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf\"" { } { { "cpu/alu/alu_flags.v" "b2v_inst_mux_cf" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 344 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505841 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu z80_top_direct_n:z80_\|alu:alu_ " "Elaborating entity \"alu\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505842 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_core z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core " "Elaborating entity \"alu_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\"" { } { { "cpu/alu/alu.v" "b2v_core" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505844 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_slice z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0 " "Elaborating entity \"alu_slice\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0\"" { } { { "cpu/alu/alu_core.v" "b2v_alu_slice_bit_0" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505845 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_bit_select z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select " "Elaborating entity \"alu_bit_select\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\"" { } { { "cpu/alu/alu.v" "b2v_input_bit_select" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 186 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505847 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_shifter_core z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift " "Elaborating entity \"alu_shifter_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\"" { } { { "cpu/alu/alu.v" "b2v_input_shift" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 197 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505848 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high " "Elaborating entity \"alu_mux_2z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_high" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 318 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505848 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_3z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low " "Elaborating entity \"alu_mux_3z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_low" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505849 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_prep_daa z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa " "Elaborating entity \"alu_prep_daa\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa\"" { } { { "cpu/alu/alu.v" "b2v_prep_daa" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 364 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505851 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_file z80_top_direct_n:z80_\|reg_file:reg_file_ " "Elaborating entity \"reg_file\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_file_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505852 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_latch z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi " "Elaborating entity \"reg_latch\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\"" { } { { "cpu/registers/reg_file.v" "b2v_latch_af2_hi" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505853 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_control z80_top_direct_n:z80_\|reg_control:reg_control_ " "Elaborating entity \"reg_control\" for hierarchy \"z80_top_direct_n:z80_\|reg_control:reg_control_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 531 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505866 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_latch z80_top_direct_n:z80_\|address_latch:address_latch_ " "Elaborating entity \"address_latch\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\"" { } { { "cpu/toplevel/coremodules.vh" "address_latch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 547 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505867 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_mux z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7 " "Elaborating entity \"address_mux\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7\"" { } { { "cpu/bus/address_latch.v" "b2v_inst7" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 106 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505869 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec " "Elaborating entity \"inc_dec\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\"" { } { { "cpu/bus/address_latch.v" "b2v_inst_inc_dec" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505870 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec_2bit z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0 " "Elaborating entity \"inc_dec_2bit\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0\"" { } { { "cpu/bus/inc_dec.v" "b2v_dual_adder_0" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505871 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_control z80_top_direct_n:z80_\|bus_control:bus_control_ " "Elaborating entity \"bus_control\" for hierarchy \"z80_top_direct_n:z80_\|bus_control:bus_control_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505875 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_switch z80_top_direct_n:z80_\|bus_switch:bus_switch_ " "Elaborating entity \"bus_switch\" for hierarchy \"z80_top_direct_n:z80_\|bus_switch:bus_switch_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_switch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 566 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505876 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch z80_top_direct_n:z80_\|data_switch:sw2_ " "Elaborating entity \"data_switch\" for hierarchy \"z80_top_direct_n:z80_\|data_switch:sw2_\"" { } { { "cpu/toplevel/core.vh" "sw2_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505876 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch_mask z80_top_direct_n:z80_\|data_switch_mask:sw1_ " "Elaborating entity \"data_switch_mask\" for hierarchy \"z80_top_direct_n:z80_\|data_switch_mask:sw1_\"" { } { { "cpu/toplevel/core.vh" "sw1_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505877 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_pins z80_top_direct_n:z80_\|address_pins:address_pins_ " "Elaborating entity \"address_pins\" for hierarchy \"z80_top_direct_n:z80_\|address_pins:address_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "address_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505878 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_pins z80_top_direct_n:z80_\|data_pins:data_pins_ " "Elaborating entity \"data_pins\" for hierarchy \"z80_top_direct_n:z80_\|data_pins:data_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "data_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505879 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_pins_n z80_top_direct_n:z80_\|control_pins_n:control_pins_ " "Elaborating entity \"control_pins_n\" for hierarchy \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "control_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505880 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648828510554 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\] ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\]\" to the node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\] ExtRamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\]\" to the node \"ExtRamWE\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 77 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD Equal2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD\" to the node \"Equal2\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ Equal2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ\" to the node \"Equal2\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648828510655 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[7\] z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[0\] z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[6\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[0\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"D\[0\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[1\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1 " "Converted the fan-out from the tri-state buffer \"D\[1\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[2\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2 " "Converted the fan-out from the tri-state buffer \"D\[2\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[3\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3 " "Converted the fan-out from the tri-state buffer \"D\[3\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[4\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4 " "Converted the fan-out from the tri-state buffer \"D\[4\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[5\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5 " "Converted the fan-out from the tri-state buffer \"D\[5\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[6\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6 " "Converted the fan-out from the tri-state buffer \"D\[6\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[7\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7 " "Converted the fan-out from the tri-state buffer \"D\[7\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648828510661 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 127 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 201 -1 0 } } { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 93 -1 0 } } { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 97 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 108 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 109 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 33 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 59 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1648828510688 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1648828510688 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[1\] GND " "Pin \"LED\[1\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[4\] GND " "Pin \"LED\[4\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[5\] GND " "Pin \"LED\[5\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[24\] VCC " "Pin \"GPIO_1\[24\]\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|GPIO_1[24]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[32\] GND " "Pin \"GPIO_1\[32\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|GPIO_1[32]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[33\] GND " "Pin \"GPIO_1\[33\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|GPIO_1[33]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648828513991 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648828514385 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648828517029 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648828517124 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648828517378 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828517378 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828517630 "|spectrum|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828517630 "|spectrum|SW[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1648828517630 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "2747 " "Implemented 2747 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_OPINS" "62 " "Implemented 62 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "2 " "Implemented 2 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2607 " "Implemented 2607 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1648828517630 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648828517630 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 110 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 110 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "441 " "Peak virtual memory: 441 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828517650 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:17 2022 " "Processing ended: Fri Apr 1 18:55:17 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828517650 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828517650 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828517650 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828517650 ""} diff --git a/db/spectrum.map.rdb b/db/spectrum.map.rdb index ec6253f..354cdc8 100644 Binary files a/db/spectrum.map.rdb and b/db/spectrum.map.rdb differ diff --git a/db/spectrum.map_bb.cdb b/db/spectrum.map_bb.cdb index 8f1b7e4..ae2f98f 100644 Binary files a/db/spectrum.map_bb.cdb and b/db/spectrum.map_bb.cdb differ diff --git a/db/spectrum.map_bb.hdb b/db/spectrum.map_bb.hdb index 4603f28..49a27df 100644 Binary files a/db/spectrum.map_bb.hdb and b/db/spectrum.map_bb.hdb differ diff --git a/db/spectrum.pplq.rdb b/db/spectrum.pplq.rdb index 9ea6ac9..9e9f17c 100644 Binary files a/db/spectrum.pplq.rdb and b/db/spectrum.pplq.rdb differ diff --git a/db/spectrum.pre_map.hdb b/db/spectrum.pre_map.hdb index 2413a9b..ff19523 100644 Binary files a/db/spectrum.pre_map.hdb and b/db/spectrum.pre_map.hdb differ diff --git a/db/spectrum.root_partition.map.reg_db.cdb b/db/spectrum.root_partition.map.reg_db.cdb index c9d0d39..923edc0 100644 Binary files a/db/spectrum.root_partition.map.reg_db.cdb and b/db/spectrum.root_partition.map.reg_db.cdb differ diff --git a/db/spectrum.routing.rdb b/db/spectrum.routing.rdb index 8cd88c5..c862e9f 100644 Binary files a/db/spectrum.routing.rdb and b/db/spectrum.routing.rdb differ diff --git a/db/spectrum.rtlv.hdb b/db/spectrum.rtlv.hdb index cab88a3..2740a45 100644 Binary files a/db/spectrum.rtlv.hdb and b/db/spectrum.rtlv.hdb differ diff --git a/db/spectrum.rtlv_sg.cdb b/db/spectrum.rtlv_sg.cdb index 06e7c51..ec5faa5 100644 Binary files a/db/spectrum.rtlv_sg.cdb and b/db/spectrum.rtlv_sg.cdb differ diff --git a/db/spectrum.rtlv_sg_swap.cdb b/db/spectrum.rtlv_sg_swap.cdb index 8522220..b2ef264 100644 Binary files a/db/spectrum.rtlv_sg_swap.cdb and b/db/spectrum.rtlv_sg_swap.cdb differ diff --git a/db/spectrum.sgdiff.cdb b/db/spectrum.sgdiff.cdb index bf47037..6061989 100644 Binary files a/db/spectrum.sgdiff.cdb and b/db/spectrum.sgdiff.cdb differ diff --git a/db/spectrum.sgdiff.hdb b/db/spectrum.sgdiff.hdb index d0f15ec..5eedc1c 100644 Binary files a/db/spectrum.sgdiff.hdb and b/db/spectrum.sgdiff.hdb differ diff --git a/db/spectrum.sta.qmsg b/db/spectrum.sta.qmsg index 87bb78d..cd2bc04 100644 --- a/db/spectrum.sta.qmsg +++ b/db/spectrum.sta.qmsg @@ -1,58 +1,58 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648724657192 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648724657193 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 31 14:04:16 2022 " "Processing started: Thu Mar 31 14:04:16 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648724657193 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648724657193 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648724657193 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648724657221 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648724657419 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648724657420 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648724657469 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648724657469 ""} -{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1648724657877 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724657885 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648724657886 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648724657886 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724657887 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724657887 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724657887 ""} } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648724657887 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724657887 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648724657887 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648724657887 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Quartus II" 0 -1 1648724657888 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724657889 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724657889 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724657889 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724657889 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648724657889 ""} -{ "Warning" "WSTA_SCC_LOOP" "514 " "Found combinational loop of 514 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~84\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~84\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datab " "Node \"z80_\|alu_\|db\[4\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|combout " "Node \"z80_\|alu_\|db\[4\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|dataa " "Node \"z80_\|alu_\|db\[4\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|combout " "Node \"z80_\|alu_\|db\[4\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~11\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~11\|combout " "Node \"z80_\|alu_\|db_high\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~12\|datad " "Node \"z80_\|alu_\|db_high\[0\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~12\|combout " "Node \"z80_\|alu_\|db_high\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~13\|datab " "Node \"z80_\|alu_\|db_high\[0\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~13\|combout " "Node \"z80_\|alu_\|db_high\[0\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datac " "Node \"z80_\|alu_\|db\[4\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~4\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~4\|combout " "Node \"z80_\|alu_\|db_high\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|datad " "Node \"z80_\|alu_\|db_high\[1\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|combout " "Node \"z80_\|alu_\|db_high\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|datad " "Node \"z80_\|alu_\|db_high\[1\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|combout " "Node \"z80_\|alu_\|db_high\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~7\|datab " "Node \"z80_\|alu_\|db_high\[1\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~7\|combout " "Node \"z80_\|alu_\|db_high\[1\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|dataa " "Node \"z80_\|alu_\|db\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|datab " "Node \"z80_\|alu_\|db_high\[1\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~20\|datab " "Node \"z80_\|alu_\|db_high\[2\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~20\|combout " "Node \"z80_\|alu_\|db_high\[2\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~21\|datad " "Node \"z80_\|alu_\|db_high\[2\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~21\|combout " "Node \"z80_\|alu_\|db_high\[2\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~24\|combout " "Node \"z80_\|alu_\|db_high\[2\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~25\|datad " "Node \"z80_\|alu_\|db_high\[2\]~25\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~25\|combout " "Node \"z80_\|alu_\|db_high\[2\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~14\|datab " "Node \"z80_\|alu_control_\|db\[6\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~14\|combout " "Node \"z80_\|alu_control_\|db\[6\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|datab " "Node \"z80_\|alu_control_\|db\[6\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|combout " "Node \"z80_\|alu_control_\|db\[6\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|datac " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|datac " "Node \"z80_\|alu_control_\|db\[6\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datad " "Node \"z80_\|alu_\|db\[6\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|combout " "Node \"z80_\|alu_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datac " "Node \"z80_\|alu_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~5\|datac " "Node \"z80_\|bus_control_\|db\[6\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~5\|combout " "Node \"z80_\|bus_control_\|db\[6\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|datad " "Node \"z80_\|bus_control_\|db\[6\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|combout " "Node \"z80_\|bus_control_\|db\[6\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~0\|datab " "Node \"z80_\|sw1_\|db_down\[6\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~15\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|datab " "Node \"z80_\|alu_\|db_high\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|combout " "Node \"z80_\|alu_\|db_high\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~15\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~15\|combout " "Node \"z80_\|alu_\|db_high\[3\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~18\|combout " "Node \"z80_\|alu_\|db_high\[3\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~19\|datac " "Node \"z80_\|alu_\|db_high\[3\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~19\|combout " "Node \"z80_\|alu_\|db_high\[3\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datac " "Node \"z80_\|alu_\|db\[7\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~15\|datab " "Node \"z80_\|alu_\|db_high\[3\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~26\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~26\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~28\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~28\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~29\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|datac " "Node \"z80_\|alu_\|db\[7\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|combout " "Node \"z80_\|alu_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~4\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~5\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~6\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~20\|datac " "Node \"z80_\|alu_\|db_high\[2\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|datad " "Node \"z80_\|alu_\|db_high\[3\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~16\|datad " "Node \"z80_\|alu_\|db_low\[0\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~16\|combout " "Node \"z80_\|alu_\|db_low\[0\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~17\|combout " "Node \"z80_\|alu_\|db_low\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datab " "Node \"z80_\|alu_\|db_low\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~44\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~44\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~46\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~46\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~47\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~47\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~48\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~48\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~10\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~11\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~12\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datac " "Node \"z80_\|alu_\|db\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~17\|datac " "Node \"z80_\|alu_\|db_low\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|datac " "Node \"z80_\|sw2_\|db_up\[0\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datad " "Node \"z80_\|alu_control_\|db\[0\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|combout " "Node \"z80_\|alu_control_\|db\[0\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|datab " "Node \"z80_\|alu_control_\|db\[0\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|combout " "Node \"z80_\|alu_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~15\|datad " "Node \"z80_\|bus_control_\|db\[0\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~15\|combout " "Node \"z80_\|bus_control_\|db\[0\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|datab " "Node \"z80_\|alu_control_\|db\[0\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|combout " "Node \"z80_\|alu_control_\|db\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datac " "Node \"z80_\|alu_control_\|db\[0\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datac " "Node \"z80_\|alu_\|db\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|datab " "Node \"z80_\|alu_\|db_low\[1\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|combout " "Node \"z80_\|alu_\|db_low\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datad " "Node \"z80_\|alu_\|db_low\[1\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datab " "Node \"z80_\|alu_\|db_low\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|dataa " "Node \"z80_\|alu_\|db\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|combout " "Node \"z80_\|alu_\|db\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~16\|datac " "Node \"z80_\|alu_\|db_low\[0\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|datab " "Node \"z80_\|alu_control_\|db\[1\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|combout " "Node \"z80_\|alu_control_\|db\[1\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datac " "Node \"z80_\|alu_control_\|db\[1\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|combout " "Node \"z80_\|alu_control_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datab " "Node \"z80_\|alu_control_\|db\[1\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datac " "Node \"z80_\|alu_control_\|db\[1\]~26\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~12\|datac " "Node \"z80_\|bus_control_\|db\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~12\|combout " "Node \"z80_\|bus_control_\|db\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~13\|datab " "Node \"z80_\|bus_control_\|db\[1\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~13\|combout " "Node \"z80_\|bus_control_\|db\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datab " "Node \"z80_\|alu_\|db\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|combout " "Node \"z80_\|alu_\|db\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datac " "Node \"z80_\|alu_\|db\[1\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datad " "Node \"z80_\|alu_control_\|db\[1\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~35\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~37\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~37\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~38\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~38\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~39\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~39\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~9\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~39\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~39\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datac " "Node \"z80_\|alu_\|db\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~5\|datab " "Node \"z80_\|alu_\|db_low\[2\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~5\|combout " "Node \"z80_\|alu_\|db_low\[2\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|datab " "Node \"z80_\|alu_\|db_low\[2\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datac " "Node \"z80_\|alu_\|db_low\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|combout " "Node \"z80_\|alu_\|db_low\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~22\|datac " "Node \"z80_\|alu_\|db_low\[2\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~22\|combout " "Node \"z80_\|alu_\|db_low\[2\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|datac " "Node \"z80_\|alu_\|db\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|combout " "Node \"z80_\|alu_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~20\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~20\|combout " "Node \"z80_\|alu_control_\|db\[2\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|datab " "Node \"z80_\|alu_control_\|db\[2\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|combout " "Node \"z80_\|alu_control_\|db\[2\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~10\|datac " "Node \"z80_\|bus_control_\|db\[2\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~10\|combout " "Node \"z80_\|bus_control_\|db\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~11\|dataa " "Node \"z80_\|bus_control_\|db\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~11\|combout " "Node \"z80_\|bus_control_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~21\|combout " "Node \"z80_\|alu_control_\|db\[2\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~22\|datac " "Node \"z80_\|alu_control_\|db\[2\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|datac " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~21\|datab " "Node \"z80_\|alu_control_\|db\[2\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|dataa " "Node \"z80_\|alu_\|db\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|combout " "Node \"z80_\|alu_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|dataa " "Node \"z80_\|alu_\|db\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|combout " "Node \"z80_\|alu_\|db_low\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datab " "Node \"z80_\|alu_\|db_low\[3\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|combout " "Node \"z80_\|alu_\|db_low\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~23\|combout " "Node \"z80_\|alu_\|db_low\[3\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|dataa " "Node \"z80_\|alu_\|db\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|combout " "Node \"z80_\|alu_\|db\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datab " "Node \"z80_\|alu_\|db\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|combout " "Node \"z80_\|alu_\|db\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~53\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~53\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~55\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~55\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~56\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~56\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|datac " "Node \"z80_\|alu_\|db\[3\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~13\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~14\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~10\|datac " "Node \"z80_\|alu_\|db_high\[0\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~10\|combout " "Node \"z80_\|alu_\|db_high\[0\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~11\|datad " "Node \"z80_\|alu_\|db_high\[0\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~5\|datac " "Node \"z80_\|alu_\|db_low\[2\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datac " "Node \"z80_\|alu_control_\|db\[3\]~35\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datac " "Node \"z80_\|alu_\|db\[3\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datac " "Node \"z80_\|alu_control_\|db\[3\]~34\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datab " "Node \"z80_\|alu_control_\|db\[3\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datad " "Node \"z80_\|bus_control_\|db\[3\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~2\|datac " "Node \"z80_\|sw1_\|db_down\[3\]~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~2\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datad " "Node \"z80_\|alu_control_\|db\[3\]~34\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~8\|datac " "Node \"z80_\|alu_\|db_high\[0\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~8\|combout " "Node \"z80_\|alu_\|db_high\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~2\|datac " "Node \"z80_\|alu_\|db_high\[1\]~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~2\|combout " "Node \"z80_\|alu_\|db_high\[1\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|datab " "Node \"z80_\|alu_\|db_high\[1\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|datac " "Node \"z80_\|alu_\|db_low\[1\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|combout " "Node \"z80_\|alu_\|db_low\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|datab " "Node \"z80_\|alu_\|db_low\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|combout " "Node \"z80_\|alu_\|db_low\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datab " "Node \"z80_\|alu_\|db_low\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~23\|datab " "Node \"z80_\|alu_\|db_high\[2\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~23\|combout " "Node \"z80_\|alu_\|db_high\[2\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~24\|datab " "Node \"z80_\|alu_\|db_high\[2\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datac " "Node \"z80_\|alu_\|db_low\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datad " "Node \"z80_\|alu_\|db_low\[0\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datac " "Node \"z80_\|alu_\|db_low\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|datab " "Node \"z80_\|alu_\|db_high\[3\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|combout " "Node \"z80_\|alu_\|db_high\[3\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~18\|datad " "Node \"z80_\|alu_\|db_high\[3\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datad " "Node \"z80_\|alu_\|db_low\[3\]~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|combout " "Node \"z80_\|alu_\|db_low\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~23\|datad " "Node \"z80_\|alu_\|db_low\[3\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~64\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~64\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~65\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~65\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datab " "Node \"z80_\|alu_\|db\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~18\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~66\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~66\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|datab " "Node \"z80_\|alu_control_\|db\[7\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|combout " "Node \"z80_\|alu_control_\|db\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~8\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~8\|combout " "Node \"z80_\|bus_control_\|db\[7\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~9\|datac " "Node \"z80_\|bus_control_\|db\[7\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~9\|combout " "Node \"z80_\|bus_control_\|db\[7\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|datad " "Node \"z80_\|alu_control_\|db\[7\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|combout " "Node \"z80_\|alu_control_\|db\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datac " "Node \"z80_\|alu_control_\|db\[7\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~1\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|datab " "Node \"z80_\|alu_control_\|db\[7\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~4\|datab " "Node \"z80_\|alu_\|db_high\[1\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~12\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~14\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~15\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~21\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~0\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~1\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datac " "Node \"z80_\|alu_\|db\[6\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~21\|datab " "Node \"z80_\|alu_\|db_high\[2\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~29\|datac " "Node \"z80_\|alu_control_\|db\[5\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~29\|combout " "Node \"z80_\|alu_control_\|db\[5\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~17\|datab " "Node \"z80_\|bus_control_\|db\[5\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~17\|combout " "Node \"z80_\|bus_control_\|db\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datab " "Node \"z80_\|alu_\|db_low\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~8\|datad " "Node \"z80_\|alu_\|db_high\[0\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~28\|datab " "Node \"z80_\|alu_control_\|db\[5\]~28\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~28\|combout " "Node \"z80_\|alu_control_\|db\[5\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~29\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~2\|datad " "Node \"z80_\|alu_\|db_high\[1\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|datad " "Node \"z80_\|alu_\|db_low\[1\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datad " "Node \"z80_\|alu_\|db_low\[0\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|datad " "Node \"z80_\|alu_\|db_high\[3\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~28\|datac " "Node \"z80_\|alu_control_\|db\[5\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datac " "Node \"z80_\|alu_\|db\[5\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|combout " "Node \"z80_\|alu_\|db\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datac " "Node \"z80_\|alu_\|db\[5\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~71\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~71\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~74\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~74\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~75\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~75\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~19\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datad " "Node \"z80_\|alu_\|db\[5\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~10\|datab " "Node \"z80_\|alu_\|db_high\[0\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datab " "Node \"z80_\|alu_control_\|db\[4\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~8\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~2\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datac " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datac " "Node \"z80_\|alu_control_\|db\[4\]~32\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|datac " "Node \"z80_\|alu_\|db_high\[3\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datac " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datac " "Node \"z80_\|alu_\|db\[4\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datac " "Node \"z80_\|alu_control_\|db\[4\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~80\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~80\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~84\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~84\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|datad " "Node \"z80_\|alu_\|db_low\[3\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~22\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~23\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~24\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648724657896 ""} } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1648724657896 ""} -{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "514 " "Design contains combinational loop of 514 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1648724657913 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648724657945 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648724657945 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658078 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648724658081 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648724658109 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648724658133 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648724658133 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.442 " "Worst-case setup slack is -18.442" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.442 -343.502 CLOCK_50 " " -18.442 -343.502 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.732 -41.482 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.732 -41.482 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.760 -51.393 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -3.760 -51.393 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658134 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724658134 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.980 " "Worst-case hold slack is -0.980" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658138 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658138 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.980 -15.725 CLOCK_50 " " -0.980 -15.725 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658138 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658138 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658138 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658138 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724658138 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.277 " "Worst-case recovery slack is -6.277" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.277 -463.435 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -6.277 -463.435 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658139 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724658139 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.683 " "Worst-case removal slack is 3.683" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.683 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.683 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658140 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724658140 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.489 " "Worst-case minimum pulse width slack is 9.489" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658141 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658141 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.489 0.000 CLOCK_50 " " 9.489 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658141 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658141 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.595 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.595 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658141 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724658141 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724658141 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648724658258 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648724658295 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648724659212 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648724659406 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648724659406 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659408 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648724659423 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648724659423 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -17.588 " "Worst-case setup slack is -17.588" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.588 -332.785 CLOCK_50 " " -17.588 -332.785 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.423 -38.803 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.423 -38.803 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.309 -45.165 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -3.309 -45.165 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659426 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724659426 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.780 " "Worst-case hold slack is -0.780" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659433 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659433 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.780 -12.413 CLOCK_50 " " -0.780 -12.413 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659433 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659433 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659433 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659433 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724659433 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.784 " "Worst-case recovery slack is -5.784" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.784 -426.554 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -5.784 -426.554 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659436 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724659436 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.369 " "Worst-case removal slack is 3.369" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.369 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.369 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659439 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724659439 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.488 " "Worst-case minimum pulse width slack is 9.488" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.594 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.594 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.588 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.588 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659441 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724659441 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648724659585 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648724659868 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648724659868 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659870 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648724659876 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648724659876 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -15.171 " "Worst-case setup slack is -15.171" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659881 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659881 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.171 -291.784 CLOCK_50 " " -15.171 -291.784 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659881 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.800 -34.909 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -3.800 -34.909 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659881 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659881 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.194 -30.204 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -2.194 -30.204 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659881 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724659881 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.698 " "Worst-case hold slack is -0.698" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659890 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659890 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.698 -11.143 CLOCK_50 " " -0.698 -11.143 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659890 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659890 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.179 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.179 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659890 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659890 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724659890 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.738 " "Worst-case recovery slack is -4.738" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659895 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659895 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.738 -361.836 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.738 -361.836 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659895 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724659895 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.515 " "Worst-case removal slack is 2.515" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659900 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659900 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.515 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 2.515 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659900 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724659900 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.208 " "Worst-case minimum pulse width slack is 9.208" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659905 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659905 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.208 0.000 CLOCK_50 " " 9.208 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659905 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.640 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.640 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659905 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659905 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648724659905 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648724659905 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648724660456 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648724660456 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 535 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 535 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "451 " "Peak virtual memory: 451 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648724660693 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 31 14:04:20 2022 " "Processing ended: Thu Mar 31 14:04:20 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648724660693 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648724660693 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648724660693 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648724660693 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828544821 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828544822 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:44 2022 " "Processing started: Fri Apr 1 18:55:44 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828544822 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828544822 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828544822 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648828544853 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648828545066 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648828545068 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648828545118 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648828545118 ""} +{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1648828545540 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545549 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545549 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648828545549 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545551 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648828545551 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Quartus II" 0 -1 1648828545551 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} +{ "Warning" "WSTA_SCC_LOOP" "511 " "Found combinational loop of 511 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datab " "Node \"z80_\|alu_control_\|db\[0\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|combout " "Node \"z80_\|alu_control_\|db\[0\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|datac " "Node \"z80_\|alu_control_\|db\[0\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|combout " "Node \"z80_\|alu_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|datac " "Node \"z80_\|alu_control_\|db\[0\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|combout " "Node \"z80_\|alu_control_\|db\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|datac " "Node \"z80_\|alu_\|db\[0\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|combout " "Node \"z80_\|alu_\|db\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datac " "Node \"z80_\|alu_\|db_low\[1\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|datac " "Node \"z80_\|alu_\|db\[1\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|combout " "Node \"z80_\|alu_\|db\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|datac " "Node \"z80_\|alu_\|db_low\[1\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datac " "Node \"z80_\|alu_\|db_low\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datab " "Node \"z80_\|alu_\|db_low\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|dataa " "Node \"z80_\|alu_\|db\[0\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|datac " "Node \"z80_\|alu_\|db\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|combout " "Node \"z80_\|alu_\|db\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|dataa " "Node \"z80_\|alu_\|db\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|datac " "Node \"z80_\|alu_\|db_low\[2\]~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|combout " "Node \"z80_\|alu_\|db_low\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|datac " "Node \"z80_\|alu_\|db_low\[2\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|combout " "Node \"z80_\|alu_\|db_low\[2\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|datab " "Node \"z80_\|alu_\|db_low\[2\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|combout " "Node \"z80_\|alu_\|db_low\[2\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|dataa " "Node \"z80_\|alu_\|db\[2\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|combout " "Node \"z80_\|alu_\|db\[2\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datad " "Node \"z80_\|alu_\|db_low\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|datad " "Node \"z80_\|alu_\|db\[2\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|combout " "Node \"z80_\|alu_\|db\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|datac " "Node \"z80_\|alu_\|db\[2\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datab " "Node \"z80_\|alu_control_\|db\[2\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datad " "Node \"z80_\|alu_control_\|db\[2\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datab " "Node \"z80_\|bus_control_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|datad " "Node \"z80_\|bus_control_\|db\[2\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datac " "Node \"z80_\|alu_control_\|db\[2\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|datac " "Node \"z80_\|alu_\|db\[2\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datad " "Node \"z80_\|alu_\|db_low\[3\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|combout " "Node \"z80_\|alu_\|db_low\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|datac " "Node \"z80_\|alu_\|db_low\[3\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|combout " "Node \"z80_\|alu_\|db_low\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|datad " "Node \"z80_\|alu_\|db_low\[3\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|combout " "Node \"z80_\|alu_\|db_low\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|datac " "Node \"z80_\|alu_\|db_low\[3\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|combout " "Node \"z80_\|alu_\|db_low\[3\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|datad " "Node \"z80_\|alu_\|db\[3\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|combout " "Node \"z80_\|alu_\|db\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|dataa " "Node \"z80_\|alu_\|db\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|combout " "Node \"z80_\|alu_\|db\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datad " "Node \"z80_\|alu_control_\|db\[3\]~35\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|datac " "Node \"z80_\|alu_\|db\[3\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datad " "Node \"z80_\|bus_control_\|db\[3\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datad " "Node \"z80_\|alu_\|db_low\[1\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datad " "Node \"z80_\|alu_\|db_low\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|datad " "Node \"z80_\|alu_\|db_low\[3\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|combout " "Node \"z80_\|alu_\|db_low\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datad " "Node \"z80_\|alu_\|db_high\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|datab " "Node \"z80_\|alu_\|db_high\[0\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~26\|datac " "Node \"z80_\|alu_\|db_high\[0\]~26\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~26\|combout " "Node \"z80_\|alu_\|db_high\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|datac " "Node \"z80_\|alu_\|db\[4\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|combout " "Node \"z80_\|alu_\|db\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datad " "Node \"z80_\|alu_\|db\[4\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|combout " "Node \"z80_\|alu_\|db\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|dataa " "Node \"z80_\|alu_\|db\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datac " "Node \"z80_\|alu_\|db_high\[0\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datad " "Node \"z80_\|alu_\|db_high\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datab " "Node \"z80_\|alu_\|db_high\[1\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|datad " "Node \"z80_\|alu_\|db_high\[1\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~20\|combout " "Node \"z80_\|alu_\|db_high\[1\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|dataa " "Node \"z80_\|alu_\|db\[5\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|combout " "Node \"z80_\|alu_\|db\[5\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|datab " "Node \"z80_\|alu_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|combout " "Node \"z80_\|alu_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datac " "Node \"z80_\|bus_control_\|db\[5\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datac " "Node \"z80_\|alu_\|db_low\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|datab " "Node \"z80_\|sw1_\|db_down\[5\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|combout " "Node \"z80_\|alu_control_\|db\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|datad " "Node \"z80_\|alu_control_\|db\[5\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datac " "Node \"z80_\|alu_\|db_high\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datac " "Node \"z80_\|alu_\|db_low\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datad " "Node \"z80_\|alu_\|db_low\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datac " "Node \"z80_\|alu_\|db_high\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~14\|datad " "Node \"z80_\|alu_\|db_high\[2\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~14\|combout " "Node \"z80_\|alu_\|db_high\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|dataa " "Node \"z80_\|alu_\|db\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|combout " "Node \"z80_\|alu_\|db\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datac " "Node \"z80_\|alu_\|db_high\[3\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datab " "Node \"z80_\|alu_\|db_high\[3\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~8\|datac " "Node \"z80_\|alu_\|db_high\[3\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~8\|combout " "Node \"z80_\|alu_\|db_high\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|datac " "Node \"z80_\|alu_\|db\[7\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|combout " "Node \"z80_\|alu_\|db\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datac " "Node \"z80_\|alu_\|db_high\[3\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datac " "Node \"z80_\|alu_\|db\[7\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|dataa " "Node \"z80_\|alu_\|db\[7\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datad " "Node \"z80_\|alu_\|db_low\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datad " "Node \"z80_\|alu_\|db_high\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|combout " "Node \"z80_\|alu_\|db_high\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datab " "Node \"z80_\|alu_\|db_high\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datac " "Node \"z80_\|alu_\|db_high\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|datac " "Node \"z80_\|alu_control_\|db\[7\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|combout " "Node \"z80_\|alu_control_\|db\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datad " "Node \"z80_\|alu_control_\|db\[7\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datab " "Node \"z80_\|bus_control_\|db\[7\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|datad " "Node \"z80_\|bus_control_\|db\[7\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|datad " "Node \"z80_\|alu_control_\|db\[7\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|combout " "Node \"z80_\|alu_control_\|db\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datad " "Node \"z80_\|alu_\|db\[7\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|datac " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|datab " "Node \"z80_\|alu_control_\|db\[6\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|combout " "Node \"z80_\|alu_control_\|db\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|datac " "Node \"z80_\|alu_control_\|db\[6\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|combout " "Node \"z80_\|alu_control_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datab " "Node \"z80_\|alu_control_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|combout " "Node \"z80_\|alu_control_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datab " "Node \"z80_\|bus_control_\|db\[6\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datac " "Node \"z80_\|alu_control_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datad " "Node \"z80_\|alu_\|db\[6\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|datac " "Node \"z80_\|alu_\|db\[6\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datac " "Node \"z80_\|alu_\|db_high\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datac " "Node \"z80_\|alu_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datac " "Node \"z80_\|alu_\|db_low\[2\]~4\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|combout " "Node \"z80_\|alu_\|db_low\[2\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|datac " "Node \"z80_\|alu_\|db_low\[2\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datac " "Node \"z80_\|alu_\|db_high\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|combout " "Node \"z80_\|alu_\|db_high\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datac " "Node \"z80_\|alu_\|db_high\[3\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|combout " "Node \"z80_\|alu_\|db_high\[3\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|datac " "Node \"z80_\|alu_\|db_high\[3\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|datac " "Node \"z80_\|alu_\|db\[5\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|datac " "Node \"z80_\|alu_control_\|db\[5\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datac " "Node \"z80_\|alu_\|db_high\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datac " "Node \"z80_\|alu_\|db_high\[2\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datac " "Node \"z80_\|alu_\|db\[5\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datac " "Node \"z80_\|alu_\|db_high\[1\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datab " "Node \"z80_\|alu_\|db_high\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datab " "Node \"z80_\|alu_\|db_high\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datab " "Node \"z80_\|alu_\|db_low\[2\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datab " "Node \"z80_\|alu_\|db_high\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datab " "Node \"z80_\|alu_\|db_high\[3\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datac " "Node \"z80_\|alu_\|db\[4\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datac " "Node \"z80_\|alu_control_\|db\[4\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datad " "Node \"z80_\|alu_\|db_low\[0\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datad " "Node \"z80_\|alu_\|db_high\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datad " "Node \"z80_\|alu_\|db_low\[2\]~4\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datad " "Node \"z80_\|alu_\|db_high\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datad " "Node \"z80_\|alu_\|db_high\[3\]~27\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|datad " "Node \"z80_\|sw1_\|db_down\[3\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datad " "Node \"z80_\|alu_control_\|db\[3\]~34\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datab " "Node \"z80_\|alu_\|db_high\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|datac " "Node \"z80_\|alu_\|db\[3\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|datab " "Node \"z80_\|alu_\|db_low\[2\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datad " "Node \"z80_\|alu_control_\|db\[1\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|combout " "Node \"z80_\|alu_control_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datad " "Node \"z80_\|alu_control_\|db\[1\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datab " "Node \"z80_\|bus_control_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|datac " "Node \"z80_\|bus_control_\|db\[1\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|datab " "Node \"z80_\|alu_\|db\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|datac " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datab " "Node \"z80_\|alu_control_\|db\[1\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datac " "Node \"z80_\|alu_\|db_low\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datac " "Node \"z80_\|alu_\|db\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|datad " "Node \"z80_\|sw2_\|db_up\[0\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datad " "Node \"z80_\|alu_control_\|db\[0\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1648828545559 ""} +{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "511 " "Design contains combinational loop of 511 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1648828545577 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828545610 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828545610 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545745 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648828545747 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648828545777 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648828545819 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648828545819 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.123 " "Worst-case setup slack is -18.123" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.123 -549.338 CLOCK_50 " " -18.123 -549.338 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.533 -284.813 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -7.533 -284.813 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.740 -42.810 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.740 -42.810 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.210 " "Worst-case hold slack is 0.210" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.210 0.000 CLOCK_50 " " 0.210 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.344 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.344 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.223 " "Worst-case recovery slack is -6.223" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.223 -459.348 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -6.223 -459.348 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545827 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545827 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.698 " "Worst-case removal slack is 3.698" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.698 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.698 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545828 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545828 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.488 " "Worst-case minimum pulse width slack is 9.488" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.595 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.595 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648828545969 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648828546007 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648828546952 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828547129 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828547129 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547131 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648828547148 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648828547148 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -17.311 " "Worst-case setup slack is -17.311" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.311 -526.609 CLOCK_50 " " -17.311 -526.609 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.686 -253.661 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.686 -253.661 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.428 -40.009 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.428 -40.009 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.298 " "Worst-case hold slack is 0.298" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.300 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.300 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.304 0.000 CLOCK_50 " " 0.304 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.744 " "Worst-case recovery slack is -5.744" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.744 -423.582 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -5.744 -423.582 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547162 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547162 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.374 " "Worst-case removal slack is 3.374" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547165 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547165 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.374 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.374 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547165 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547165 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.489 " "Worst-case minimum pulse width slack is 9.489" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.489 0.000 CLOCK_50 " " 9.489 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.591 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.591 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648828547327 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828547608 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828547608 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547610 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648828547617 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648828547617 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -14.971 " "Worst-case setup slack is -14.971" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.971 -442.545 CLOCK_50 " " -14.971 -442.545 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.979 -171.124 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -4.979 -171.124 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.775 -35.541 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -3.775 -35.541 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.053 " "Worst-case hold slack is -0.053" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.053 -0.089 CLOCK_50 " " -0.053 -0.089 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.693 " "Worst-case recovery slack is -4.693" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.693 -358.284 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.693 -358.284 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547637 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547637 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.518 " "Worst-case removal slack is 2.518" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.518 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 2.518 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547642 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547642 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.208 " "Worst-case minimum pulse width slack is 9.208" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.208 0.000 CLOCK_50 " " 9.208 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648828548217 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648828548217 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 532 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 532 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "437 " "Peak virtual memory: 437 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828548454 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:48 2022 " "Processing ended: Fri Apr 1 18:55:48 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828548454 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828548454 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828548454 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828548454 ""} diff --git a/db/spectrum.sta.rdb b/db/spectrum.sta.rdb index 326ed90..1bbdc89 100644 Binary files a/db/spectrum.sta.rdb and b/db/spectrum.sta.rdb differ diff --git a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb index 56ad160..2eb24bc 100644 Binary files a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb and b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/db/spectrum.tiscmp.fast_1200mv_0c.ddb b/db/spectrum.tiscmp.fast_1200mv_0c.ddb index 7c9c8c5..964cd81 100644 Binary files a/db/spectrum.tiscmp.fast_1200mv_0c.ddb and b/db/spectrum.tiscmp.fast_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_0c.ddb b/db/spectrum.tiscmp.slow_1200mv_0c.ddb index c2532a2..4eb861d 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_0c.ddb and b/db/spectrum.tiscmp.slow_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_85c.ddb b/db/spectrum.tiscmp.slow_1200mv_85c.ddb index 0009514..865cf09 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_85c.ddb and b/db/spectrum.tiscmp.slow_1200mv_85c.ddb differ diff --git a/db/spectrum.vpr.ammdb b/db/spectrum.vpr.ammdb index 5d9b5ec..1f2e0e9 100644 Binary files a/db/spectrum.vpr.ammdb and b/db/spectrum.vpr.ammdb differ diff --git a/greybox_tmp/cbx_args.txt b/greybox_tmp/cbx_args.txt index 43c0e8e..2b81d66 100644 --- a/greybox_tmp/cbx_args.txt +++ b/greybox_tmp/cbx_args.txt @@ -1,16 +1,70 @@ -ADDRESS_ACLR_A=NONE -CLOCK_ENABLE_INPUT_A=BYPASS -CLOCK_ENABLE_OUTPUT_A=BYPASS -INIT_FILE=./rom/gw03.hex +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=143 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=72 +CLK0_PHASE_SHIFT=0 +CLK1_DIVIDE_BY=25 +CLK1_DUTY_CYCLE=50 +CLK1_MULTIPLY_BY=7 +CLK1_PHASE_SHIFT=0 +CLK2_DIVIDE_BY=25 +CLK2_DUTY_CYCLE=50 +CLK2_MULTIPLY_BY=12 +CLK2_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=20000 INTENDED_DEVICE_FAMILY="Cyclone IV E" -NUMWORDS_A=16384 -OPERATION_MODE=ROM -OUTDATA_ACLR_A=NONE -OUTDATA_REG_A=CLOCK0 -WIDTHAD_A=14 -WIDTH_A=8 -WIDTH_BYTEENA_A=1 +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_UNUSED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_USED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_USED +PORT_clk2=PORT_USED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +SELF_RESET_ON_LOSS_LOCK=OFF +WIDTH_CLOCK=5 DEVICE_FAMILY="Cyclone IV E" -address_a -clock0 -q_a +CBX_AUTO_BLACKBOX=ALL +inclk +inclk +clk +clk +clk +locked diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb index cfb65a3..d33caa1 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb index 9375bb8..11d8ad5 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb index 0f5e8dd..25ab810 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb index 0d19a2b..da66c56 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb index 51e5f8a..428a347 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi index 80c8f07..33139a1 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi and b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb index e0fa19a..67df2f3 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb index e81bd17..110b4e6 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb index 48b3b35..9b6563d 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt index ae56832..d4f8b41 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt and b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt differ diff --git a/output_files/greybox_tmp/cbx_args.txt b/output_files/greybox_tmp/cbx_args.txt index 02fbce1..30e3fcd 100644 --- a/output_files/greybox_tmp/cbx_args.txt +++ b/output_files/greybox_tmp/cbx_args.txt @@ -1,60 +1,36 @@ -BANDWIDTH_TYPE=AUTO -CLK0_DIVIDE_BY=2000 -CLK0_DUTY_CYCLE=50 -CLK0_MULTIPLY_BY=1007 -CLK0_PHASE_SHIFT=0 -COMPENSATE_CLOCK=CLK0 -INCLK0_INPUT_FREQUENCY=20000 +ADDRESS_REG_B=CLOCK1 +CLOCK_ENABLE_INPUT_A=BYPASS +CLOCK_ENABLE_INPUT_B=BYPASS +CLOCK_ENABLE_OUTPUT_A=BYPASS +CLOCK_ENABLE_OUTPUT_B=BYPASS +INDATA_REG_B=CLOCK1 INTENDED_DEVICE_FAMILY="Cyclone IV E" -LPM_TYPE=altpll -OPERATION_MODE=NORMAL -PLL_TYPE=AUTO -PORT_ACTIVECLOCK=PORT_UNUSED -PORT_ARESET=PORT_UNUSED -PORT_CLKBAD0=PORT_UNUSED -PORT_CLKBAD1=PORT_UNUSED -PORT_CLKLOSS=PORT_UNUSED -PORT_CLKSWITCH=PORT_UNUSED -PORT_CONFIGUPDATE=PORT_UNUSED -PORT_FBIN=PORT_UNUSED -PORT_INCLK0=PORT_USED -PORT_INCLK1=PORT_UNUSED -PORT_LOCKED=PORT_USED -PORT_PFDENA=PORT_UNUSED -PORT_PHASECOUNTERSELECT=PORT_UNUSED -PORT_PHASEDONE=PORT_UNUSED -PORT_PHASESTEP=PORT_UNUSED -PORT_PHASEUPDOWN=PORT_UNUSED -PORT_PLLENA=PORT_UNUSED -PORT_SCANACLR=PORT_UNUSED -PORT_SCANCLK=PORT_UNUSED -PORT_SCANCLKENA=PORT_UNUSED -PORT_SCANDATA=PORT_UNUSED -PORT_SCANDATAOUT=PORT_UNUSED -PORT_SCANDONE=PORT_UNUSED -PORT_SCANREAD=PORT_UNUSED -PORT_SCANWRITE=PORT_UNUSED -PORT_clk0=PORT_USED -PORT_clk1=PORT_UNUSED -PORT_clk2=PORT_UNUSED -PORT_clk3=PORT_UNUSED -PORT_clk4=PORT_UNUSED -PORT_clk5=PORT_UNUSED -PORT_clkena0=PORT_UNUSED -PORT_clkena1=PORT_UNUSED -PORT_clkena2=PORT_UNUSED -PORT_clkena3=PORT_UNUSED -PORT_clkena4=PORT_UNUSED -PORT_clkena5=PORT_UNUSED -PORT_extclk0=PORT_UNUSED -PORT_extclk1=PORT_UNUSED -PORT_extclk2=PORT_UNUSED -PORT_extclk3=PORT_UNUSED -SELF_RESET_ON_LOSS_LOCK=OFF -WIDTH_CLOCK=5 +LPM_TYPE=altsyncram +NUMWORDS_A=16384 +NUMWORDS_B=16384 +OPERATION_MODE=BIDIR_DUAL_PORT +OUTDATA_ACLR_A=NONE +OUTDATA_ACLR_B=NONE +OUTDATA_REG_A=CLOCK0 +OUTDATA_REG_B=CLOCK1 +POWER_UP_UNINITIALIZED=FALSE +READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ +READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_NO_NBE_READ +WIDTHAD_A=14 +WIDTHAD_B=14 +WIDTH_A=8 +WIDTH_B=8 +WIDTH_BYTEENA_A=1 +WIDTH_BYTEENA_B=1 +WRCONTROL_WRADDRESS_REG_B=CLOCK1 DEVICE_FAMILY="Cyclone IV E" -CBX_AUTO_BLACKBOX=ALL -inclk -inclk -clk -locked +address_a +address_b +clock0 +clock1 +data_a +data_b +wren_a +wren_b +q_a +q_b diff --git a/output_files/ram_video.qip b/output_files/ram_video.qip new file mode 100644 index 0000000..e69de29 diff --git a/output_files/spectrum.asm.rpt b/output_files/spectrum.asm.rpt index e77e944..0b03803 100644 --- a/output_files/spectrum.asm.rpt +++ b/output_files/spectrum.asm.rpt @@ -1,5 +1,5 @@ Assembler report for spectrum -Thu Mar 31 14:04:15 2022 +Fri Apr 1 18:55:43 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Thu Mar 31 14:04:15 2022 ; +; Assembler Status ; Successful - Fri Apr 1 18:55:43 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -162,8 +162,8 @@ Default Value : On ; Option ; Setting ; +----------------+-----------------------+ ; Device ; EP4CE22F17C6 ; -; JTAG usercode ; 0x00559289 ; -; Checksum ; 0x00559289 ; +; JTAG usercode ; 0x0056423F ; +; Checksum ; 0x0056423F ; +----------------+-----------------------+ @@ -173,14 +173,14 @@ Default Value : On Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Thu Mar 31 14:04:14 2022 + Info: Processing started: Fri Apr 1 18:55:41 2022 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 375 megabytes - Info: Processing ended: Thu Mar 31 14:04:15 2022 - Info: Elapsed time: 00:00:01 + Info: Peak virtual memory: 385 megabytes + Info: Processing ended: Fri Apr 1 18:55:43 2022 + Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/output_files/spectrum.done b/output_files/spectrum.done index ec1a5df..a426016 100644 --- a/output_files/spectrum.done +++ b/output_files/spectrum.done @@ -1 +1 @@ -Thu Mar 31 14:04:25 2022 +Fri Apr 1 18:55:53 2022 diff --git a/output_files/spectrum.eda.rpt b/output_files/spectrum.eda.rpt index 40fce66..32ae12e 100644 --- a/output_files/spectrum.eda.rpt +++ b/output_files/spectrum.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for spectrum -Thu Mar 31 14:04:25 2022 +Fri Apr 1 18:55:53 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -36,7 +36,7 @@ applicable agreement for further details. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Thu Mar 31 14:04:25 2022 ; +; EDA Netlist Writer Status ; Successful - Fri Apr 1 18:55:53 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -88,7 +88,7 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit EDA Netlist Writer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Thu Mar 31 14:04:22 2022 + Info: Processing started: Fri Apr 1 18:55:50 2022 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool @@ -99,8 +99,8 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 383 megabytes - Info: Processing ended: Thu Mar 31 14:04:25 2022 + Info: Peak virtual memory: 380 megabytes + Info: Processing ended: Fri Apr 1 18:55:53 2022 Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:03 diff --git a/output_files/spectrum.fit.rpt b/output_files/spectrum.fit.rpt index 9f891cc..21ded4a 100644 --- a/output_files/spectrum.fit.rpt +++ b/output_files/spectrum.fit.rpt @@ -1,5 +1,5 @@ Fitter report for spectrum -Thu Mar 31 14:04:11 2022 +Fri Apr 1 18:55:39 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -77,18 +77,18 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+--------------------------------------------+ -; Fitter Status ; Successful - Thu Mar 31 14:04:11 2022 ; +; Fitter Status ; Successful - Fri Apr 1 18:55:39 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 2,383 / 22,320 ( 11 % ) ; -; Total combinational functions ; 2,265 / 22,320 ( 10 % ) ; +; Total logic elements ; 2,396 / 22,320 ( 11 % ) ; +; Total combinational functions ; 2,272 / 22,320 ( 10 % ) ; ; Dedicated logic registers ; 591 / 22,320 ( 3 % ) ; ; Total registers ; 600 ; -; Total pins ; 74 / 154 ( 48 % ) ; +; Total pins ; 75 / 154 ( 49 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 524,288 / 608,256 ( 86 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; @@ -928,13 +928,6 @@ Ignored To : GPIO_0[0] Ignored Value : PIN_D3 Ignored Source : QSF Assignment -Name : Location -Ignored Entity : -Ignored From : -Ignored To : GPIO_0[10] -Ignored Value : PIN_B6 -Ignored Source : QSF Assignment - Name : Location Ignored Entity : Ignored From : @@ -1488,13 +1481,6 @@ Ignored To : GPIO_0[0] Ignored Value : 3.3-V LVTTL Ignored Source : QSF Assignment -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : GPIO_0[10] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - Name : I/O Standard Ignored Entity : spectrum Ignored From : @@ -1724,14 +1710,14 @@ From Design Partitions [A] : From Rapid Recompile [B] : Type : -- Requested -Total [A + B] : 0.00 % ( 0 / 3088 ) -From Design Partitions [A] : 0.00 % ( 0 / 3088 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 3088 ) +Total [A + B] : 0.00 % ( 0 / 3097 ) +From Design Partitions [A] : 0.00 % ( 0 / 3097 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 3097 ) Type : -- Achieved -Total [A + B] : 0.00 % ( 0 / 3088 ) -From Design Partitions [A] : 0.00 % ( 0 / 3088 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 3088 ) +Total [A + B] : 0.00 % ( 0 / 3097 ) +From Design Partitions [A] : 0.00 % ( 0 / 3097 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 3097 ) Type : Total [A + B] : @@ -1782,7 +1768,7 @@ Contents : hard_block:auto_generated_inst ; Incremental Compilation Placement Preservation ; +--------------------------------------------------------------------------------+ Partition Name : Top -Preservation Achieved : 0.00 % ( 0 / 3074 ) +Preservation Achieved : 0.00 % ( 0 / 3083 ) Preservation Level Used : N/A Netlist Type Used : Source File Preservation Method : N/A @@ -1809,28 +1795,28 @@ The pin-out file can be found in /home/benny/work/fpga/spectrum/output_files/spe +---------------------------------------------+----------------------------+ ; Resource ; Usage ; +---------------------------------------------+----------------------------+ -; Total logic elements ; 2,383 / 22,320 ( 11 % ) ; -; -- Combinational with no register ; 1792 ; -; -- Register only ; 118 ; -; -- Combinational with a register ; 473 ; +; Total logic elements ; 2,396 / 22,320 ( 11 % ) ; +; -- Combinational with no register ; 1805 ; +; -- Register only ; 124 ; +; -- Combinational with a register ; 467 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1645 ; -; -- 3 input functions ; 364 ; -; -- <=2 input functions ; 256 ; -; -- Register only ; 118 ; +; -- 4 input functions ; 1640 ; +; -- 3 input functions ; 385 ; +; -- <=2 input functions ; 247 ; +; -- Register only ; 124 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 2212 ; +; -- normal mode ; 2219 ; ; -- arithmetic mode ; 53 ; ; ; ; ; Total registers* ; 600 / 23,018 ( 3 % ) ; ; -- Dedicated logic registers ; 591 / 22,320 ( 3 % ) ; ; -- I/O registers ; 9 / 698 ( 1 % ) ; ; ; ; -; Total LABs: partially or completely used ; 186 / 1,395 ( 13 % ) ; +; Total LABs: partially or completely used ; 185 / 1,395 ( 13 % ) ; ; Virtual pins ; 0 ; -; I/O pins ; 74 / 154 ( 48 % ) ; +; I/O pins ; 75 / 154 ( 49 % ) ; ; -- Clock pins ; 5 / 7 ( 71 % ) ; ; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; ; ; ; @@ -1845,12 +1831,12 @@ The pin-out file can be found in /home/benny/work/fpga/spectrum/output_files/spe ; CRC blocks ; 0 / 1 ( 0 % ) ; ; ASMI blocks ; 0 / 1 ( 0 % ) ; ; Impedance control blocks ; 0 / 4 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 5% / 4% / 6% ; -; Peak interconnect usage (total/H/V) ; 24% / 21% / 29% ; -; Maximum fan-out ; 471 ; +; Average interconnect usage (total/H/V) ; 5% / 5% / 6% ; +; Peak interconnect usage (total/H/V) ; 29% / 26% / 33% ; +; Maximum fan-out ; 435 ; ; Highest non-global fan-out ; 69 ; -; Total fan-out ; 11594 ; -; Average fan-out ; 3.67 ; +; Total fan-out ; 11636 ; +; Average fan-out ; 3.66 ; +---------------------------------------------+----------------------------+ * Register count does not include registers inside RAM blocks or DSP blocks. @@ -1868,19 +1854,19 @@ Top : hard_block:auto_generated_inst : Statistic : Total logic elements -Top : 2383 / 22320 ( 11 % ) +Top : 2396 / 22320 ( 11 % ) hard_block:auto_generated_inst : 0 / 22320 ( 0 % ) Statistic : -- Combinational with no register -Top : 1792 +Top : 1805 hard_block:auto_generated_inst : 0 Statistic : -- Register only -Top : 118 +Top : 124 hard_block:auto_generated_inst : 0 Statistic : -- Combinational with a register -Top : 473 +Top : 467 hard_block:auto_generated_inst : 0 Statistic : @@ -1892,19 +1878,19 @@ Top : hard_block:auto_generated_inst : Statistic : -- 4 input functions -Top : 1645 +Top : 1640 hard_block:auto_generated_inst : 0 Statistic : -- 3 input functions -Top : 364 +Top : 385 hard_block:auto_generated_inst : 0 Statistic : -- <=2 input functions -Top : 256 +Top : 247 hard_block:auto_generated_inst : 0 Statistic : -- Register only -Top : 118 +Top : 124 hard_block:auto_generated_inst : 0 Statistic : @@ -1916,7 +1902,7 @@ Top : hard_block:auto_generated_inst : Statistic : -- normal mode -Top : 2212 +Top : 2219 hard_block:auto_generated_inst : 0 Statistic : -- arithmetic mode @@ -1944,7 +1930,7 @@ Top : hard_block:auto_generated_inst : Statistic : Total LABs: partially or completely used -Top : 186 / 1395 ( 13 % ) +Top : 185 / 1395 ( 13 % ) hard_block:auto_generated_inst : 0 / 1395 ( 0 % ) Statistic : @@ -1956,7 +1942,7 @@ Top : 0 hard_block:auto_generated_inst : 0 Statistic : I/O pins -Top : 74 +Top : 75 hard_block:auto_generated_inst : 0 Statistic : Embedded Multiplier 9-bit elements @@ -1996,16 +1982,16 @@ Top : hard_block:auto_generated_inst : Statistic : -- Input Connections -Top : 161 +Top : 197 hard_block:auto_generated_inst : 1 Statistic : -- Registered Input Connections -Top : 158 +Top : 194 hard_block:auto_generated_inst : 0 Statistic : -- Output Connections Top : 3 -hard_block:auto_generated_inst : 159 +hard_block:auto_generated_inst : 195 Statistic : -- Registered Output Connections Top : 0 @@ -2020,11 +2006,11 @@ Top : hard_block:auto_generated_inst : Statistic : -- Total Connections -Top : 11601 -hard_block:auto_generated_inst : 169 +Top : 11643 +hard_block:auto_generated_inst : 205 Statistic : -- Registered Connections -Top : 2869 +Top : 2921 hard_block:auto_generated_inst : 0 Statistic : @@ -2037,10 +2023,10 @@ hard_block:auto_generated_inst : Statistic : -- Top Top : 4 -hard_block:auto_generated_inst : 160 +hard_block:auto_generated_inst : 196 Statistic : -- hard_block:auto_generated_inst -Top : 160 +Top : 196 hard_block:auto_generated_inst : 0 Statistic : @@ -2052,7 +2038,7 @@ Top : hard_block:auto_generated_inst : Statistic : -- Input Ports -Top : 10 +Top : 11 hard_block:auto_generated_inst : 1 Statistic : -- Output Ports @@ -2304,6 +2290,24 @@ Weak Pull Up : Off I/O Standard : 3.3-V LVTTL Termination Control Block : -- Location assigned by : User + +Name : raw_loader_in +Pin # : B6 +I/O Bank : 8 +X coordinate : 16 +Y coordinate : 34 +Z coordinate : 7 +Combinational Fan-Out : 3 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User +--------------------------------------------------------------------------------+ @@ -4089,6 +4093,12 @@ Reserved As : Use as regular IO User Signal Name : buzzer_out Pin Type : Dual Purpose Pin +Location : B6 +Pin Name : DIFFIO_T7p, DATA13 +Reserved As : Use as regular IO +User Signal Name : raw_loader_in +Pin Type : Dual Purpose Pin + Location : E7 Pin Name : DATA5 Reserved As : Use as regular IO @@ -4149,7 +4159,7 @@ VCCIO Voltage : 3.3V VREF Voltage : -- I/O Bank : 8 -Usage : 11 / 24 ( 46 % ) +Usage : 12 / 24 ( 50 % ) VCCIO Voltage : 3.3V VREF Voltage : -- +--------------------------------------------------------------------------------+ @@ -4414,14 +4424,14 @@ Weak Pull Up : On Location : B6 Pad Number : 226 I/O Bank : 8 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : raw_loader_in +Dir. : input +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : B7 Pad Number : 221 @@ -7346,7 +7356,7 @@ SDC Pin Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ; Fitter Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -Logic Cells : 2383 (86) +Logic Cells : 2396 (98) Dedicated Logic Registers : 591 (0) I/O Registers : 9 (9) Memory Bits : 524288 @@ -7354,11 +7364,11 @@ M9Ks : 64 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 -Pins : 74 +Pins : 75 Virtual Pins : 0 -LUT-Only LCs : 1792 (84) -Register-Only LCs : 118 (0) -LUT/Register LCs : 473 (3) +LUT-Only LCs : 1805 (96) +Register-Only LCs : 124 (0) +LUT/Register LCs : 467 (2) Full Hierarchy Name : |spectrum Library Name : work @@ -7374,8 +7384,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 2 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 2 (0) +Register-Only LCs : 1 (0) +LUT/Register LCs : 1 (0) Full Hierarchy Name : |spectrum|ram16:ram0 Library Name : work @@ -7391,8 +7401,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 2 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 2 (0) +Register-Only LCs : 1 (0) +LUT/Register LCs : 1 (0) Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component Library Name : work @@ -7408,8 +7418,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 2 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 2 (2) +Register-Only LCs : 1 (1) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated Library Name : work @@ -7431,7 +7441,7 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |ram32:ram1| -Logic Cells : 28 (0) +Logic Cells : 19 (0) Dedicated Logic Registers : 4 (0) I/O Registers : 0 (0) Memory Bits : 262144 @@ -7441,14 +7451,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 24 (0) -Register-Only LCs : 3 (0) -LUT/Register LCs : 1 (0) +LUT-Only LCs : 15 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 4 (0) Full Hierarchy Name : |spectrum|ram32:ram1 Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -Logic Cells : 28 (0) +Logic Cells : 19 (0) Dedicated Logic Registers : 4 (0) I/O Registers : 0 (0) Memory Bits : 262144 @@ -7458,14 +7468,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 24 (0) -Register-Only LCs : 3 (0) -LUT/Register LCs : 1 (0) +LUT-Only LCs : 15 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 4 (0) Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component Library Name : work Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated| -Logic Cells : 28 (4) +Logic Cells : 19 (4) Dedicated Logic Registers : 4 (4) I/O Registers : 0 (0) Memory Bits : 262144 @@ -7475,9 +7485,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 24 (0) -Register-Only LCs : 3 (3) -LUT/Register LCs : 1 (1) +LUT-Only LCs : 15 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 4 (3) Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated Library Name : work @@ -7516,7 +7526,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |mux_6nb:mux2| -Logic Cells : 16 (16) +Logic Cells : 8 (8) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -7526,9 +7536,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 16 (16) +LUT-Only LCs : 7 (7) Register-Only LCs : 0 (0) -LUT/Register LCs : 0 (0) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2 Library Name : work @@ -7584,7 +7594,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component| Library Name : work Compilation Hierarchy Node : |ula:ula_| -Logic Cells : 454 (9) +Logic Cells : 458 (9) Dedicated Logic Registers : 223 (7) I/O Registers : 0 (0) Memory Bits : 0 @@ -7594,9 +7604,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 229 (2) -Register-Only LCs : 33 (3) -LUT/Register LCs : 192 (4) +LUT-Only LCs : 235 (2) +Register-Only LCs : 36 (3) +LUT/Register LCs : 187 (3) Full Hierarchy Name : |spectrum|ula:ula_ Library Name : work @@ -7635,7 +7645,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|i2c_loader:i2c_loader_ Library Name : work Compilation Hierarchy Node : |i2s_intf:i2s_intf_| -Logic Cells : 70 (70) +Logic Cells : 69 (69) Dedicated Logic Registers : 41 (41) I/O Registers : 0 (0) Memory Bits : 0 @@ -7645,9 +7655,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 29 (29) -Register-Only LCs : 2 (2) -LUT/Register LCs : 39 (39) +LUT-Only LCs : 27 (27) +Register-Only LCs : 1 (1) +LUT/Register LCs : 41 (41) Full Hierarchy Name : |spectrum|ula:ula_|i2s_intf:i2s_intf_ Library Name : work @@ -7720,7 +7730,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_ Library Name : work Compilation Hierarchy Node : |video:video_| -Logic Cells : 120 (120) +Logic Cells : 124 (124) Dedicated Logic Registers : 72 (72) I/O Registers : 0 (0) Memory Bits : 0 @@ -7730,14 +7740,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 48 (48) -Register-Only LCs : 21 (21) -LUT/Register LCs : 51 (51) +LUT-Only LCs : 52 (52) +Register-Only LCs : 25 (25) +LUT/Register LCs : 47 (47) Full Hierarchy Name : |spectrum|ula:ula_|video:video_ Library Name : work Compilation Hierarchy Node : |zx_keyboard:zx_keyboard_| -Logic Cells : 148 (148) +Logic Cells : 150 (150) Dedicated Logic Registers : 43 (43) I/O Registers : 0 (0) Memory Bits : 0 @@ -7747,14 +7757,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 95 (95) +LUT-Only LCs : 99 (99) Register-Only LCs : 0 (0) -LUT/Register LCs : 53 (53) +LUT/Register LCs : 51 (51) Full Hierarchy Name : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_ Library Name : work Compilation Hierarchy Node : |z80_top_direct_n:z80_| -Logic Cells : 1815 (2) +Logic Cells : 1822 (2) Dedicated Logic Registers : 362 (1) I/O Registers : 0 (0) Memory Bits : 0 @@ -7764,14 +7774,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 1453 (1) -Register-Only LCs : 82 (0) -LUT/Register LCs : 280 (2) +LUT-Only LCs : 1457 (1) +Register-Only LCs : 87 (0) +LUT/Register LCs : 278 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_ Library Name : work Compilation Hierarchy Node : |address_latch:address_latch_| -Logic Cells : 51 (20) +Logic Cells : 57 (26) Dedicated Logic Registers : 16 (16) I/O Registers : 0 (0) Memory Bits : 0 @@ -7781,14 +7791,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 35 (4) -Register-Only LCs : 4 (4) -LUT/Register LCs : 12 (12) +LUT-Only LCs : 41 (10) +Register-Only LCs : 7 (7) +LUT/Register LCs : 9 (8) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_ Library Name : work Compilation Hierarchy Node : |inc_dec:b2v_inst_inc_dec| -Logic Cells : 31 (14) +Logic Cells : 32 (14) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -7798,14 +7808,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 31 (14) +LUT-Only LCs : 31 (13) Register-Only LCs : 0 (0) -LUT/Register LCs : 0 (0) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec Library Name : work Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_0| -Logic Cells : 3 (3) +Logic Cells : 4 (4) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -7815,7 +7825,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 3 (3) +LUT-Only LCs : 4 (4) Register-Only LCs : 0 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0 @@ -7917,9 +7927,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 16 (16) +LUT-Only LCs : 13 (13) Register-Only LCs : 0 (0) -LUT/Register LCs : 16 (16) +LUT/Register LCs : 19 (19) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_pins:address_pins_ Library Name : work @@ -7934,9 +7944,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 109 (74) +LUT-Only LCs : 107 (74) Register-Only LCs : 0 (0) -LUT/Register LCs : 21 (2) +LUT/Register LCs : 23 (3) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_ Library Name : work @@ -7951,14 +7961,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 2 (2) +LUT-Only LCs : 0 (0) Register-Only LCs : 0 (0) -LUT/Register LCs : 0 (0) +LUT/Register LCs : 2 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select Library Name : work Compilation Hierarchy Node : |alu_core:b2v_core| -Logic Cells : 21 (0) +Logic Cells : 20 (0) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -7970,7 +7980,7 @@ Pins : 0 Virtual Pins : 0 LUT-Only LCs : 18 (0) Register-Only LCs : 0 (0) -LUT/Register LCs : 3 (0) +LUT/Register LCs : 2 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core Library Name : work @@ -8002,9 +8012,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 3 (3) +LUT-Only LCs : 4 (4) Register-Only LCs : 0 (0) -LUT/Register LCs : 1 (1) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1 Library Name : work @@ -8026,7 +8036,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b Library Name : work Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_3| -Logic Cells : 6 (6) +Logic Cells : 5 (5) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8036,7 +8046,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 5 (5) +LUT-Only LCs : 4 (4) Register-Only LCs : 0 (0) LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3 @@ -8162,7 +8172,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_con Library Name : work Compilation Hierarchy Node : |alu_flags:alu_flags_| -Logic Cells : 62 (62) +Logic Cells : 63 (63) Dedicated Logic Registers : 10 (10) I/O Registers : 0 (0) Memory Bits : 0 @@ -8172,7 +8182,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 52 (52) +LUT-Only LCs : 53 (53) Register-Only LCs : 0 (0) LUT/Register LCs : 10 (10) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_flags:alu_flags_ @@ -8189,9 +8199,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 10 (10) +LUT-Only LCs : 14 (14) Register-Only LCs : 0 (0) -LUT/Register LCs : 8 (8) +LUT/Register LCs : 4 (4) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|bus_control:bus_control_ Library Name : work @@ -8247,7 +8257,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_ Library Name : work Compilation Hierarchy Node : |data_switch_mask:sw1_| -Logic Cells : 3 (3) +Logic Cells : 2 (2) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8257,7 +8267,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 3 (3) +LUT-Only LCs : 2 (2) Register-Only LCs : 0 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch_mask:sw1_ @@ -8274,14 +8284,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 8 (8) +LUT-Only LCs : 7 (7) Register-Only LCs : 0 (0) -LUT/Register LCs : 6 (6) +LUT/Register LCs : 7 (7) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|decode_state:decode_state_ Library Name : work Compilation Hierarchy Node : |execute:execute_| -Logic Cells : 931 (931) +Logic Cells : 933 (933) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8291,9 +8301,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 924 (924) +LUT-Only LCs : 923 (923) Register-Only LCs : 0 (0) -LUT/Register LCs : 7 (7) +LUT/Register LCs : 10 (10) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|execute:execute_ Library Name : work @@ -8309,8 +8319,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 7 (7) -Register-Only LCs : 3 (3) -LUT/Register LCs : 5 (5) +Register-Only LCs : 1 (1) +LUT/Register LCs : 7 (7) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|interrupts:interrupts_ Library Name : work @@ -8326,13 +8336,13 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 8 (8) +Register-Only LCs : 3 (3) +LUT/Register LCs : 5 (5) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|ir:ir_ Library Name : work Compilation Hierarchy Node : |memory_ifc:memory_ifc_| -Logic Cells : 24 (24) +Logic Cells : 22 (22) Dedicated Logic Registers : 20 (20) I/O Registers : 0 (0) Memory Bits : 0 @@ -8342,9 +8352,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 4 (4) -Register-Only LCs : 9 (9) -LUT/Register LCs : 11 (11) +LUT-Only LCs : 2 (2) +Register-Only LCs : 6 (6) +LUT/Register LCs : 14 (14) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|memory_ifc:memory_ifc_ Library Name : work @@ -8400,7 +8410,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_control:reg_con Library Name : work Compilation Hierarchy Node : |reg_file:reg_file_| -Logic Cells : 347 (124) +Logic Cells : 350 (128) Dedicated Logic Registers : 224 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8410,9 +8420,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 123 (123) -Register-Only LCs : 64 (0) -LUT/Register LCs : 160 (151) +LUT-Only LCs : 126 (126) +Register-Only LCs : 68 (0) +LUT/Register LCs : 156 (147) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_ Library Name : work @@ -8479,8 +8489,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 8 (8) -LUT/Register LCs : 0 (0) +Register-Only LCs : 6 (6) +LUT/Register LCs : 2 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af_lo Library Name : work @@ -8530,8 +8540,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 6 (6) -LUT/Register LCs : 2 (2) +Register-Only LCs : 7 (7) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc_hi Library Name : work @@ -8615,8 +8625,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 5 (5) -LUT/Register LCs : 3 (3) +Register-Only LCs : 6 (6) +LUT/Register LCs : 2 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de_lo Library Name : work @@ -8666,8 +8676,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 4 (4) -LUT/Register LCs : 4 (4) +Register-Only LCs : 8 (8) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl_hi Library Name : work @@ -8683,8 +8693,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 6 (6) -LUT/Register LCs : 2 (2) +Register-Only LCs : 7 (7) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl_lo Library Name : work @@ -8717,8 +8727,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 1 (1) -LUT/Register LCs : 7 (7) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ir_lo Library Name : work @@ -8785,8 +8795,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 6 (6) -LUT/Register LCs : 2 (2) +Register-Only LCs : 5 (5) +LUT/Register LCs : 3 (3) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_iy_lo Library Name : work @@ -8836,8 +8846,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 8 (8) +Register-Only LCs : 1 (1) +LUT/Register LCs : 7 (7) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_sp_hi Library Name : work @@ -8853,8 +8863,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 2 (2) -LUT/Register LCs : 6 (6) +Register-Only LCs : 3 (3) +LUT/Register LCs : 5 (5) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_sp_lo Library Name : work @@ -8870,8 +8880,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 2 (2) -LUT/Register LCs : 6 (6) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_wz_hi Library Name : work @@ -8887,8 +8897,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 8 (8) +Register-Only LCs : 1 (1) +LUT/Register LCs : 7 (7) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_wz_lo Library Name : work @@ -9456,7 +9466,7 @@ TCOE : -- Name : I2C_SDAT Pin Type : Bidir Pad to Core 0 : (0) 0 ps -Pad to Core 1 : (0) 0 ps +Pad to Core 1 : -- Pad to Input Register : -- TCO : (0) 0 ps TCOE : -- @@ -9477,15 +9487,15 @@ Pad to Input Register : -- TCO : -- TCOE : -- -Name : KEY[0] +Name : raw_loader_in Pin Type : Input -Pad to Core 0 : -- +Pad to Core 0 : (6) 1314 ps Pad to Core 1 : (0) 0 ps Pad to Input Register : -- TCO : -- TCOE : -- -Name : CLOCK_50 +Name : KEY[0] Pin Type : Input Pad to Core 0 : (0) 0 ps Pad to Core 1 : -- @@ -9493,7 +9503,7 @@ Pad to Input Register : -- TCO : -- TCOE : -- -Name : KEY[1] +Name : CLOCK_50 Pin Type : Input Pad to Core 0 : (0) 0 ps Pad to Core 1 : -- @@ -9509,6 +9519,14 @@ Pad to Input Register : -- TCO : -- TCOE : -- +Name : KEY[1] +Pin Type : Input +Pad to Core 0 : (0) 0 ps +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + Name : PS2_CLK Pin Type : Input Pad to Core 0 : (6) 1314 ps @@ -9519,8 +9537,8 @@ TCOE : -- Name : AUD_ADCDAT Pin Type : Input -Pad to Core 0 : -- -Pad to Core 1 : (0) 0 ps +Pad to Core 0 : (0) 0 ps +Pad to Core 1 : -- Pad to Input Register : -- TCO : -- TCOE : -- @@ -9556,7 +9574,7 @@ Pad To Core Index : 0 Setting : 0 Source Pin / Fanout : - ula:ula_|i2c_loader:i2c_loader_|nbyte[1]~5 -Pad To Core Index : 1 +Pad To Core Index : 0 Setting : 0 Source Pin / Fanout : SW[1] @@ -9567,22 +9585,34 @@ Source Pin / Fanout : SW[2] Pad To Core Index : Setting : +Source Pin / Fanout : raw_loader_in +Pad To Core Index : +Setting : + +Source Pin / Fanout : - D[6]~86 +Pad To Core Index : 1 +Setting : 0 + +Source Pin / Fanout : - ula:ula_|beep~0 +Pad To Core Index : 0 +Setting : 6 + +Source Pin / Fanout : - LED[3]~output +Pad To Core Index : 1 +Setting : 0 + Source Pin / Fanout : KEY[0] Pad To Core Index : Setting : Source Pin / Fanout : - reset -Pad To Core Index : 1 +Pad To Core Index : 0 Setting : 0 Source Pin / Fanout : CLOCK_50 Pad To Core Index : Setting : -Source Pin / Fanout : KEY[1] -Pad To Core Index : -Setting : - Source Pin / Fanout : PS2_DAT Pad To Core Index : Setting : @@ -9599,11 +9629,15 @@ Source Pin / Fanout : - ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready Pad To Core Index : 0 Setting : 6 +Source Pin / Fanout : KEY[1] +Pad To Core Index : +Setting : + Source Pin / Fanout : PS2_CLK Pad To Core Index : Setting : -Source Pin / Fanout : - ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[7] +Source Pin / Fanout : - ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[7]~feeder Pad To Core Index : 0 Setting : 6 @@ -9612,7 +9646,7 @@ Pad To Core Index : Setting : Source Pin / Fanout : - ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]~20 -Pad To Core Index : 1 +Pad To Core Index : 0 Setting : 0 +--------------------------------------------------------------------------------+ @@ -9639,9 +9673,9 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : D[0]~30 -Location : LCCOMB_X32_Y15_N30 -Fan-Out : 16 +Name : D[0]~107 +Location : LCCOMB_X31_Y12_N10 +Fan-Out : 10 Usage : Output enable Global : no Global Resource Used : -- @@ -9658,7 +9692,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~0 -Location : LCCOMB_X31_Y16_N14 +Location : LCCOMB_X32_Y14_N2 Fan-Out : 8 Usage : Write enable Global : no @@ -9667,7 +9701,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~1 -Location : LCCOMB_X31_Y16_N12 +Location : LCCOMB_X32_Y14_N10 Fan-Out : 8 Usage : Write enable Global : no @@ -9676,7 +9710,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode|w_anode284w[2]~0 -Location : LCCOMB_X31_Y16_N8 +Location : LCCOMB_X32_Y14_N22 Fan-Out : 8 Usage : Clock enable Global : no @@ -9685,7 +9719,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2] -Location : LCCOMB_X31_Y16_N18 +Location : LCCOMB_X32_Y14_N12 Fan-Out : 8 Usage : Write enable Global : no @@ -9694,7 +9728,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2]~0 -Location : LCCOMB_X31_Y16_N16 +Location : LCCOMB_X32_Y14_N18 Fan-Out : 8 Usage : Clock enable Global : no @@ -9703,7 +9737,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode236w[2] -Location : LCCOMB_X31_Y16_N10 +Location : LCCOMB_X32_Y14_N8 Fan-Out : 8 Usage : Write enable Global : no @@ -9712,7 +9746,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2] -Location : LCCOMB_X31_Y16_N22 +Location : LCCOMB_X32_Y14_N24 Fan-Out : 8 Usage : Write enable Global : no @@ -9721,7 +9755,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2]~0 -Location : LCCOMB_X31_Y16_N28 +Location : LCCOMB_X32_Y14_N26 Fan-Out : 8 Usage : Clock enable Global : no @@ -9730,7 +9764,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2] -Location : LCCOMB_X31_Y16_N6 +Location : LCCOMB_X32_Y14_N20 Fan-Out : 8 Usage : Write enable Global : no @@ -9739,7 +9773,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2]~0 -Location : LCCOMB_X31_Y16_N24 +Location : LCCOMB_X32_Y14_N6 Fan-Out : 8 Usage : Clock enable Global : no @@ -9748,7 +9782,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : reset -Location : LCCOMB_X52_Y17_N6 +Location : LCCOMB_X52_Y14_N4 Fan-Out : 149 Usage : Async. clear, Async. load Global : yes @@ -9756,8 +9790,8 @@ Global Resource Used : Global Clock Global Line Name : GCLK5 Enable Signal Source Name : -- -Name : ula:ula_|always0~1 -Location : LCCOMB_X32_Y15_N2 +Name : ula:ula_|always0~3 +Location : LCCOMB_X31_Y12_N20 Fan-Out : 7 Usage : Clock enable Global : no @@ -9767,15 +9801,15 @@ Enable Signal Source Name : -- Name : ula:ula_|clocks:clocks_|clk_cpu Location : FF_X25_Y33_N11 -Fan-Out : 471 +Fan-Out : 435 Usage : Clock Global : yes Global Resource Used : Global Clock -Global Line Name : GCLK10 +Global Line Name : GCLK14 Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|WideAnd0 -Location : LCCOMB_X1_Y24_N28 +Location : LCCOMB_X4_Y24_N8 Fan-Out : 17 Usage : Clock enable Global : no @@ -9784,7 +9818,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|nbit[0]~4 -Location : LCCOMB_X2_Y23_N18 +Location : LCCOMB_X1_Y24_N4 Fan-Out : 3 Usage : Clock enable Global : no @@ -9793,7 +9827,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~3 -Location : LCCOMB_X2_Y23_N16 +Location : LCCOMB_X1_Y23_N24 Fan-Out : 2 Usage : Clock enable Global : no @@ -9802,7 +9836,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Location : FF_X2_Y24_N3 +Location : FF_X1_Y23_N5 Fan-Out : 23 Usage : Sync. load Global : no @@ -9811,7 +9845,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~8 -Location : LCCOMB_X2_Y23_N20 +Location : LCCOMB_X1_Y24_N10 Fan-Out : 2 Usage : Clock enable Global : no @@ -9820,7 +9854,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~11 -Location : LCCOMB_X2_Y23_N24 +Location : LCCOMB_X2_Y24_N24 Fan-Out : 6 Usage : Clock enable Global : no @@ -9829,7 +9863,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|state.Start -Location : FF_X2_Y24_N17 +Location : FF_X1_Y24_N31 Fan-Out : 20 Usage : Sync. clear, Sync. load Global : no @@ -9838,7 +9872,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]~18 -Location : LCCOMB_X4_Y23_N28 +Location : LCCOMB_X2_Y23_N8 Fan-Out : 5 Usage : Clock enable Global : no @@ -9847,7 +9881,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2s_intf:i2s_intf_|Equal0~2 -Location : LCCOMB_X24_Y16_N30 +Location : LCCOMB_X29_Y23_N30 Fan-Out : 37 Usage : Sync. load Global : no @@ -9856,7 +9890,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]~15 -Location : LCCOMB_X24_Y32_N12 +Location : LCCOMB_X31_Y22_N28 Fan-Out : 5 Usage : Clock enable Global : no @@ -9864,8 +9898,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]~2 -Location : LCCOMB_X24_Y32_N26 +Name : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]~2 +Location : LCCOMB_X31_Y22_N30 Fan-Out : 17 Usage : Clock enable Global : no @@ -9875,7 +9909,7 @@ Enable Signal Source Name : -- Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] Location : PLL_4 -Fan-Out : 74 +Fan-Out : 110 Usage : Clock Global : yes Global Resource Used : Global Clock @@ -9901,7 +9935,7 @@ Global Line Name : GCLK19 Enable Signal Source Name : -- Name : ula:ula_|ps2_keyboard:ps2_keyboard_|clk_edge -Location : FF_X25_Y23_N29 +Location : FF_X20_Y26_N5 Fan-Out : 6 Usage : Clock enable Global : no @@ -9910,8 +9944,8 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready -Location : FF_X26_Y15_N9 -Fan-Out : 6 +Location : FF_X26_Y21_N9 +Fan-Out : 7 Usage : Clock enable Global : no Global Resource Used : -- @@ -9919,7 +9953,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0]~0 -Location : LCCOMB_X26_Y15_N26 +Location : LCCOMB_X26_Y21_N6 Fan-Out : 9 Usage : Clock enable Global : no @@ -9928,7 +9962,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Decoder0~0 -Location : LCCOMB_X36_Y30_N0 +Location : LCCOMB_X34_Y31_N12 Fan-Out : 16 Usage : Clock enable Global : no @@ -9937,7 +9971,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Decoder0~1 -Location : LCCOMB_X35_Y30_N10 +Location : LCCOMB_X34_Y31_N10 Fan-Out : 8 Usage : Clock enable Global : no @@ -9946,7 +9980,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Decoder0~2 -Location : LCCOMB_X35_Y30_N0 +Location : LCCOMB_X34_Y31_N8 Fan-Out : 8 Usage : Clock enable Global : no @@ -9955,7 +9989,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Equal3~1 -Location : LCCOMB_X32_Y31_N16 +Location : LCCOMB_X37_Y33_N18 Fan-Out : 16 Usage : Clock enable Global : no @@ -9964,7 +9998,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|vram_address[9]~1 -Location : LCCOMB_X35_Y30_N28 +Location : LCCOMB_X34_Y31_N14 Fan-Out : 4 Usage : Clock enable Global : no @@ -9973,7 +10007,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|vram_address~0 -Location : LCCOMB_X35_Y30_N2 +Location : LCCOMB_X34_Y31_N4 Fan-Out : 8 Usage : Clock enable Global : no @@ -9981,8 +10015,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~23 -Location : LCCOMB_X31_Y16_N26 +Name : z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~20 +Location : LCCOMB_X32_Y14_N0 Fan-Out : 45 Usage : Clock enable Global : no @@ -9991,7 +10025,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high|ena~0 -Location : LCCOMB_X40_Y17_N14 +Location : LCCOMB_X36_Y10_N2 Fan-Out : 4 Usage : Clock enable Global : no @@ -10000,7 +10034,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|ena -Location : LCCOMB_X40_Y17_N16 +Location : LCCOMB_X36_Y10_N12 Fan-Out : 4 Usage : Clock enable Global : no @@ -10009,7 +10043,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high|ena -Location : LCCOMB_X39_Y17_N26 +Location : LCCOMB_X37_Y10_N16 Fan-Out : 8 Usage : Clock enable Global : no @@ -10018,7 +10052,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_iorq -Location : LCCOMB_X52_Y14_N2 +Location : LCCOMB_X43_Y15_N20 Fan-Out : 24 Usage : Clock enable Global : no @@ -10027,7 +10061,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|data_pins:data_pins_|SYNTHESIZED_WIRE_2 -Location : LCCOMB_X44_Y13_N22 +Location : LCCOMB_X32_Y13_N16 Fan-Out : 8 Usage : Clock enable Global : no @@ -10036,7 +10070,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_al_we~12 -Location : LCCOMB_X47_Y17_N18 +Location : LCCOMB_X41_Y18_N4 Fan-Out : 16 Usage : Clock enable Global : no @@ -10045,8 +10079,8 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low -Location : LCCOMB_X43_Y13_N28 -Fan-Out : 16 +Location : LCCOMB_X39_Y11_N30 +Fan-Out : 17 Usage : Clock enable Global : no Global Resource Used : -- @@ -10054,7 +10088,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux2~0 -Location : LCCOMB_X45_Y13_N22 +Location : LCCOMB_X31_Y16_N0 Fan-Out : 16 Usage : Sync. load Global : no @@ -10063,7 +10097,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~8 -Location : LCCOMB_X40_Y15_N22 +Location : LCCOMB_X37_Y9_N22 Fan-Out : 2 Usage : Clock enable Global : no @@ -10072,7 +10106,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~15 -Location : LCCOMB_X40_Y15_N24 +Location : LCCOMB_X36_Y11_N20 Fan-Out : 2 Usage : Clock enable Global : no @@ -10081,7 +10115,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_im_we -Location : LCCOMB_X46_Y17_N16 +Location : LCCOMB_X35_Y13_N16 Fan-Out : 3 Usage : Clock enable Global : no @@ -10090,7 +10124,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~13 -Location : LCCOMB_X51_Y11_N20 +Location : LCCOMB_X35_Y12_N8 Fan-Out : 8 Usage : Clock enable Global : no @@ -10099,7 +10133,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_state_ixiy_we~2 -Location : LCCOMB_X52_Y17_N0 +Location : LCCOMB_X37_Y15_N0 Fan-Out : 2 Usage : Clock enable Global : no @@ -10108,7 +10142,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_state_tbl_we~8 -Location : LCCOMB_X51_Y15_N14 +Location : LCCOMB_X41_Y17_N2 Fan-Out : 2 Usage : Clock enable Global : no @@ -10126,16 +10160,16 @@ Global Line Name : GCLK12 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 -Location : LCCOMB_X50_Y12_N24 +Location : LCCOMB_X32_Y15_N28 Fan-Out : 2 Usage : Async. clear Global : yes Global Resource Used : Global Clock -Global Line Name : GCLK8 +Global Line Name : GCLK16 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_15 -Location : LCCOMB_X50_Y12_N6 +Location : LCCOMB_X38_Y18_N12 Fan-Out : 1 Usage : Async. clear Global : no @@ -10144,7 +10178,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_9 -Location : LCCOMB_X41_Y15_N14 +Location : LCCOMB_X32_Y15_N2 Fan-Out : 1 Usage : Async. clear Global : no @@ -10153,7 +10187,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|test1~3 -Location : LCCOMB_X49_Y12_N22 +Location : LCCOMB_X43_Y15_N26 Fan-Out : 2 Usage : Clock enable Global : no @@ -10162,7 +10196,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|pin_control:pin_control_|bus_ab_pin_we~3 -Location : LCCOMB_X44_Y13_N10 +Location : LCCOMB_X31_Y16_N2 Fan-Out : 16 Usage : Clock enable Global : no @@ -10171,7 +10205,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_29 -Location : LCCOMB_X35_Y15_N10 +Location : LCCOMB_X28_Y11_N12 Fan-Out : 8 Usage : Clock enable Global : no @@ -10180,7 +10214,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_31 -Location : LCCOMB_X36_Y12_N28 +Location : LCCOMB_X28_Y10_N10 Fan-Out : 8 Usage : Clock enable Global : no @@ -10189,7 +10223,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_33 -Location : LCCOMB_X36_Y17_N18 +Location : LCCOMB_X28_Y14_N26 Fan-Out : 8 Usage : Clock enable Global : no @@ -10198,7 +10232,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_35 -Location : LCCOMB_X36_Y14_N8 +Location : LCCOMB_X28_Y14_N8 Fan-Out : 8 Usage : Clock enable Global : no @@ -10207,7 +10241,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_37~0 -Location : LCCOMB_X37_Y16_N20 +Location : LCCOMB_X29_Y15_N16 Fan-Out : 8 Usage : Clock enable Global : no @@ -10216,7 +10250,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_39~0 -Location : LCCOMB_X37_Y16_N14 +Location : LCCOMB_X30_Y12_N8 Fan-Out : 8 Usage : Clock enable Global : no @@ -10225,7 +10259,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_41~0 -Location : LCCOMB_X37_Y16_N18 +Location : LCCOMB_X29_Y15_N6 Fan-Out : 8 Usage : Clock enable Global : no @@ -10234,7 +10268,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_43~0 -Location : LCCOMB_X37_Y16_N4 +Location : LCCOMB_X30_Y12_N14 Fan-Out : 8 Usage : Clock enable Global : no @@ -10243,7 +10277,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_45 -Location : LCCOMB_X36_Y17_N4 +Location : LCCOMB_X26_Y13_N4 Fan-Out : 8 Usage : Clock enable Global : no @@ -10252,7 +10286,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_47 -Location : LCCOMB_X35_Y15_N20 +Location : LCCOMB_X30_Y13_N14 Fan-Out : 8 Usage : Clock enable Global : no @@ -10261,7 +10295,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_49 -Location : LCCOMB_X35_Y17_N26 +Location : LCCOMB_X26_Y13_N6 Fan-Out : 8 Usage : Clock enable Global : no @@ -10270,7 +10304,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_51 -Location : LCCOMB_X35_Y14_N4 +Location : LCCOMB_X30_Y13_N28 Fan-Out : 8 Usage : Clock enable Global : no @@ -10279,7 +10313,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_53 -Location : LCCOMB_X36_Y14_N4 +Location : LCCOMB_X26_Y13_N16 Fan-Out : 8 Usage : Clock enable Global : no @@ -10288,7 +10322,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_55 -Location : LCCOMB_X35_Y14_N30 +Location : LCCOMB_X26_Y13_N26 Fan-Out : 8 Usage : Clock enable Global : no @@ -10297,7 +10331,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_57 -Location : LCCOMB_X35_Y14_N10 +Location : LCCOMB_X26_Y13_N18 Fan-Out : 8 Usage : Clock enable Global : no @@ -10306,7 +10340,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_59 -Location : LCCOMB_X35_Y14_N16 +Location : LCCOMB_X26_Y13_N0 Fan-Out : 8 Usage : Clock enable Global : no @@ -10315,7 +10349,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_61 -Location : LCCOMB_X38_Y15_N18 +Location : LCCOMB_X28_Y15_N16 Fan-Out : 8 Usage : Clock enable Global : no @@ -10324,7 +10358,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_63 -Location : LCCOMB_X37_Y13_N10 +Location : LCCOMB_X31_Y15_N28 Fan-Out : 8 Usage : Clock enable Global : no @@ -10333,7 +10367,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_65~0 -Location : LCCOMB_X37_Y16_N6 +Location : LCCOMB_X30_Y12_N4 Fan-Out : 8 Usage : Clock enable Global : no @@ -10342,7 +10376,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_67~0 -Location : LCCOMB_X35_Y12_N16 +Location : LCCOMB_X30_Y12_N16 Fan-Out : 8 Usage : Clock enable Global : no @@ -10351,7 +10385,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69 -Location : LCCOMB_X37_Y16_N22 +Location : LCCOMB_X27_Y12_N12 Fan-Out : 8 Usage : Clock enable Global : no @@ -10360,7 +10394,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71 -Location : LCCOMB_X35_Y14_N26 +Location : LCCOMB_X30_Y10_N24 Fan-Out : 8 Usage : Clock enable Global : no @@ -10369,7 +10403,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_73 -Location : LCCOMB_X38_Y15_N20 +Location : LCCOMB_X28_Y15_N10 Fan-Out : 8 Usage : Clock enable Global : no @@ -10378,7 +10412,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_75 -Location : LCCOMB_X37_Y13_N8 +Location : LCCOMB_X31_Y15_N18 Fan-Out : 8 Usage : Clock enable Global : no @@ -10387,7 +10421,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_77~0 -Location : LCCOMB_X37_Y16_N12 +Location : LCCOMB_X30_Y12_N22 Fan-Out : 8 Usage : Clock enable Global : no @@ -10396,7 +10430,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_79~0 -Location : LCCOMB_X39_Y12_N16 +Location : LCCOMB_X30_Y12_N6 Fan-Out : 8 Usage : Clock enable Global : no @@ -10405,7 +10439,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_81 -Location : LCCOMB_X37_Y15_N20 +Location : LCCOMB_X28_Y15_N4 Fan-Out : 8 Usage : Clock enable Global : no @@ -10414,7 +10448,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_83 -Location : LCCOMB_X38_Y12_N30 +Location : LCCOMB_X31_Y15_N30 Fan-Out : 8 Usage : Clock enable Global : no @@ -10423,8 +10457,8 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Location : FF_X52_Y17_N9 -Fan-Out : 65 +Location : FF_X35_Y13_N11 +Fan-Out : 67 Usage : Output enable Global : no Global Resource Used : -- @@ -10432,7 +10466,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Location : FF_X52_Y17_N9 +Location : FF_X35_Y13_N11 Fan-Out : 72 Usage : Async. clear Global : yes @@ -10449,13 +10483,13 @@ Enable Signal Source Name : -- Name : CLOCK_50 Location : PIN_R8 Fan-Out : 34 -Fan-Out Using Intentional Clock Skew : 0 +Fan-Out Using Intentional Clock Skew : 1 Global Resource Used : Global Clock Global Line Name : GCLK15 Enable Signal Source Name : -- Name : reset -Location : LCCOMB_X52_Y17_N6 +Location : LCCOMB_X52_Y14_N4 Fan-Out : 149 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock @@ -10464,16 +10498,16 @@ Enable Signal Source Name : -- Name : ula:ula_|clocks:clocks_|clk_cpu Location : FF_X25_Y33_N11 -Fan-Out : 471 +Fan-Out : 435 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock -Global Line Name : GCLK10 +Global Line Name : GCLK14 Enable Signal Source Name : -- Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] Location : PLL_4 -Fan-Out : 74 -Fan-Out Using Intentional Clock Skew : 16 +Fan-Out : 110 +Fan-Out Using Intentional Clock Skew : 17 Global Resource Used : Global Clock Global Line Name : GCLK18 Enable Signal Source Name : -- @@ -10489,7 +10523,7 @@ Enable Signal Source Name : -- Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] Location : PLL_4 Fan-Out : 82 -Fan-Out Using Intentional Clock Skew : 35 +Fan-Out Using Intentional Clock Skew : 33 Global Resource Used : Global Clock Global Line Name : GCLK19 Enable Signal Source Name : -- @@ -10503,15 +10537,15 @@ Global Line Name : GCLK12 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 -Location : LCCOMB_X50_Y12_N24 +Location : LCCOMB_X32_Y15_N28 Fan-Out : 2 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock -Global Line Name : GCLK8 +Global Line Name : GCLK16 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Location : FF_X52_Y17_N9 +Location : FF_X35_Y13_N11 Fan-Out : 72 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock @@ -10526,14 +10560,15 @@ Enable Signal Source Name : -- +---------------------------------------------------------------------------------------------------------------------------------+---------+ ; Name ; Fan-Out ; +---------------------------------------------------------------------------------------------------------------------------------+---------+ -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]~24 ; 69 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[10]~22 ; 69 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[11]~21 ; 69 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[8]~20 ; 69 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[9]~19 ; 69 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[0]~18 ; 69 ; ; z80_top_direct_n:z80_|ir:ir_|opcode[3] ; 69 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[8]~18 ; 69 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[9]~17 ; 69 ; ; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 68 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[10]~24 ; 68 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]~21 ; 68 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[11]~19 ; 68 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[0]~16 ; 68 ; +; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 66 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[7]~31 ; 64 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[6]~30 ; 64 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[5]~29 ; 64 ; @@ -10541,93 +10576,87 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[3]~27 ; 64 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[2]~26 ; 64 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[1]~25 ; 64 ; -; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 64 ; ; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 59 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[5] ; 57 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff ; 56 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff ; 54 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[0] ; 53 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff ; 59 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[5] ; 58 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff ; 53 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_eval_cond~0 ; 52 ; -; z80_top_direct_n:z80_|nM1_int~2 ; 49 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~4 ; 47 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~7 ; 45 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~23 ; 45 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~8 ; 42 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff ; 41 ; +; z80_top_direct_n:z80_|nM1_int~2 ; 51 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[0] ; 51 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~5 ; 47 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~20 ; 45 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff ; 44 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~7 ; 42 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~6 ; 41 ; ; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff ; 41 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[2] ; 40 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[2] ; 39 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[3] ; 39 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~6 ; 39 ; ; z80_top_direct_n:z80_|ir:ir_|opcode[4] ; 39 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~5 ; 39 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[3] ; 38 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[4] ; 38 ; ; ula:ula_|zx_keyboard:zx_keyboard_|released ; 38 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~0 ; 38 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~2 ; 38 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~14 ; 37 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~0 ; 37 ; ; ula:ula_|i2s_intf:i2s_intf_|Equal0~2 ; 37 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[6] ; 36 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[1] ; 35 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0] ; 34 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[2] ; 34 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_1M1T3_3 ; 33 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff ; 33 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[5] ; 32 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff ; 32 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~0 ; 31 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[1] ; 30 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~38 ; 29 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~0 ; 29 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~4 ; 29 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal55~0 ; 28 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~4 ; 27 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~3 ; 27 ; -; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_11 ; 25 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[1] ; 36 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff ; 36 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~8 ; 36 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~4 ; 36 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0] ; 35 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[4] ; 35 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_1M1T3_3 ; 35 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[2] ; 35 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[6] ; 34 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[5] ; 33 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[1] ; 31 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~36 ; 30 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~0 ; 30 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~4 ; 30 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff ; 30 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~0 ; 29 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~6 ; 27 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~0 ; 25 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal55~0 ; 25 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~2 ; 25 ; ; ~GND ; 24 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~38 ; 24 ; +; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_11 ; 24 ; ; z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_iorq ; 24 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal10~0 ; 24 ; ; ula:ula_|i2c_loader:i2c_loader_|phase[0] ; 23 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~46 ; 23 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~2 ; 23 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~0 ; 23 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|M5 ; 23 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Data ; 23 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~9 ; 22 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal10~0 ; 22 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~14 ; 22 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~1 ; 22 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~29 ; 21 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~31 ; 21 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~1 ; 21 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[7] ; 21 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|M5 ; 21 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Start ; 20 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~33 ; 20 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~1 ; 20 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~3 ; 20 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]~16 ; 20 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[6] ; 20 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal63~0 ; 19 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~1 ; 19 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal47~0 ; 19 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~47 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~5 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~43 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~35 ; 20 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal47~0 ; 20 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~5 ; 20 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[7] ; 20 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[6] ; 19 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]~23 ; 19 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~16 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~6 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~38 ; 18 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_we~7 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~11 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~12 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~41 ; 18 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal63~0 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~10 ; 18 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~1 ; 18 ; +; Equal2~1 ; 18 ; ; ula:ula_|i2c_loader:i2c_loader_|WideAnd0 ; 17 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low ; 17 ; ; ula:ula_|video:video_|vram_address[10] ; 17 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~12 ; 17 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~13 ; 17 ; +; ula:ula_|zx_keyboard:zx_keyboard_|extended ; 17 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~11 ; 17 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~11 ; 17 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~1 ; 17 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|use_ixiy ; 17 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]~17 ; 17 ; -; ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]~2 ; 17 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~1 ; 17 ; +; ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]~2 ; 17 ; ; z80_top_direct_n:z80_|pin_control:pin_control_|bus_ab_pin_we~3 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~16 ; 16 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~12 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low ; 16 ; -; ula:ula_|zx_keyboard:zx_keyboard_|extended ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux2~0 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux~2 ; 16 ; -; z80_top_direct_n:z80_|resets:resets_|clrpc~0 ; 16 ; ; ula:ula_|video:video_|vram_address[12] ; 16 ; ; ula:ula_|video:video_|vram_address[11] ; 16 ; ; ula:ula_|video:video_|vram_address[9] ; 16 ; @@ -10640,25 +10669,29 @@ Enable Signal Source Name : -- ; ula:ula_|video:video_|vram_address[2] ; 16 ; ; ula:ula_|video:video_|vram_address[1] ; 16 ; ; ula:ula_|video:video_|vram_address[0] ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux2~0 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux~2 ; 16 ; +; z80_top_direct_n:z80_|resets:resets_|clrpc~0 ; 16 ; ; z80_top_direct_n:z80_|execute:execute_|setM1~52 ; 16 ; -; D[0]~30 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~12 ; 16 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|use_ixiy ; 16 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal32~0 ; 16 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal34~0 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~3 ; 16 ; ; z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED ; 16 ; ; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] ; 16 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~0 ; 16 ; ; ula:ula_|video:video_|Decoder0~0 ; 16 ; ; ula:ula_|video:video_|Equal3~1 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~14 ; 15 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|bank_exx ; 15 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal41~2 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~6 ; 15 ; +; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_oe~14 ; 15 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~10 ; 15 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~7 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~8 ; 15 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal32~0 ; 15 ; -; Equal2~0 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~2 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~6 ; 15 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~0 ; 15 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]~22 ; 15 ; ; ula:ula_|video:video_|Equal1~0 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_daa ; 14 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~15 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[7]~92 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[6]~82 ; 14 ; @@ -10667,140 +10700,132 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[3]~52 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[2]~42 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[1]~32 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[4]~84 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[5]~75 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[2]~66 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[3]~57 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[0]~48 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[1]~39 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[6]~84 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[7]~75 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[4]~66 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[5]~57 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[3]~48 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[2]~39 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[0]~30 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[1]~21 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]~22 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[7]~30 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[6]~21 ; 14 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~5 ; 14 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~1 ; 14 ; ; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T5_ff ; 14 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~9 ; 14 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~10 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~8 ; 14 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~4 ; 14 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~0 ; 14 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~0 ; 14 ; ; z80_top_direct_n:z80_|decode_state:decode_state_|in_halt ; 14 ; ; ula:ula_|video:video_|vga_hc[2] ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_daa ; 13 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~7 ; 13 ; ; ula:ula_|i2c_loader:i2c_loader_|phase[1] ; 13 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[3]~1 ; 13 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~43 ; 13 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~15 ; 13 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~5 ; 13 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal56~0 ; 13 ; -; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_oe~15 ; 13 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~9 ; 13 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~8 ; 13 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~5 ; 13 ; ; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 ; 13 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~2 ; 13 ; -; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nRD_out~2 ; 13 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~4 ; 13 ; ; ula:ula_|video:video_|vga_hc[1] ; 13 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~14 ; 12 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[3]~21 ; 12 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[4]~19 ; 12 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af~0 ; 12 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal69~0 ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal35~0 ; 12 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~17 ; 12 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~11 ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~0 ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~0 ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~1 ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~1 ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal39~0 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~12 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~2 ; 12 ; +; Equal2~0 ; 12 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~4 ; 12 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ; 12 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] ; 12 ; -; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nWR_out~0 ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~0 ; 12 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB ; 12 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af~0 ; 11 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[5]~17 ; 11 ; -; ula:ula_|zx_keyboard:zx_keyboard_|shifted ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~8 ; 11 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[5]~15 ; 11 ; ; z80_top_direct_n:z80_|execute:execute_|nextM~14 ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~19 ; 11 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal49~0 ; 11 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~1 ; 11 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal39~0 ; 11 ; +; ula:ula_|zx_keyboard:zx_keyboard_|shifted ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~15 ; 11 ; ; z80_top_direct_n:z80_|execute:execute_|nextM~2 ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~18 ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~2 ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~9 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~7 ; 11 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~0 ; 11 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~0 ; 11 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe ; 10 ; +; D[0]~107 ; 10 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~14 ; 10 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[3]~21 ; 10 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[4]~19 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~15 ; 10 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_shift~4 ; 10 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_res_oe~2 ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe ; 10 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1]~19 ; 10 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4d~6 ; 10 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~0 ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~7 ; 10 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED ; 10 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal35~0 ; 10 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal49~0 ; 10 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal24~0 ; 10 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~0 ; 10 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] ; 10 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_28 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_56 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_52 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_48 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_44 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_70 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_34 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_30 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_50 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_28 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_56 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_48 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_44 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_46 ; 9 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Idle ; 9 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Ack ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_zero ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~9 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~8 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_lq ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~14 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~7 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2d~13 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~7 ; 9 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0]~0 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_82 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_78~0 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_42~0 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_66~0 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_lo~8 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_38~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_80 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_76~0 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~12 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_64~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_40~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_36~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_82 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_78~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_42~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_66~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_lo~8 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_38~0 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_oe~2 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~7 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_oe~1 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_oe~0 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~43 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~16 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~15 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe ; 9 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0]~15 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_62 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_74 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~11 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_72 ; 9 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sw_4d_hi~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_60 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe~2 ; 9 ; -; D[4]~79 ; 9 ; -; D[3]~77 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~16 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~8 ; 9 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal24~0 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~17 ; 9 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal20~0 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~5 ; 9 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 ; 9 ; -; z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~6 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_62 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_74 ; 9 ; +; D[4]~98 ; 9 ; +; D[3]~96 ; 9 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal8~0 ; 9 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal25~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~14 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~7 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~8 ; 9 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal20~0 ; 9 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~5 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~4 ; 9 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED ; 9 ; +; z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 ; 9 ; ; ula:ula_|video:video_|vga_hc[3] ; 9 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_31 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_35 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_51 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_55 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_59 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_47 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_29 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_33 ; 8 ; @@ -10808,38 +10833,46 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_57 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_45 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_49 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_46 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_31 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_35 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_59 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_55 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_47 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_51 ; 8 ; +; z80_top_direct_n:z80_|alu:alu_|db[7]~26 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_58 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_54 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel~36 ; 8 ; ; ula:ula_|i2c_loader:i2c_loader_|Mux42~0 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_83 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_79~0 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_67~0 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_43~0 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_39~0 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_77~0 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_81 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_65~0 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_37~0 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_41~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_83 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_79~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_67~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_43~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_39~0 ; 8 ; ; z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high|ena ; 8 ; -; z80_top_direct_n:z80_|alu:alu_|db[7]~9 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_63 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_75 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]~21 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~14 ; 8 ; +; ula:ula_|video:video_|vram_address~0 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_73 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_61 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[0]~20 ; 8 ; -; ula:ula_|video:video_|vram_address~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_63 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_75 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]~21 ; 8 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~11 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~12 ; 8 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus ; 8 ; ; z80_top_direct_n:z80_|data_pins:data_pins_|SYNTHESIZED_WIRE_2 ; 8 ; ; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_re ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~2 ; 8 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~6 ; 8 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~4 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe~2 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~13 ; 8 ; ; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~1 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~2 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~30 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~20 ; 8 ; ; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~0 ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2]~0 ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2] ; 8 ; @@ -10849,86 +10882,92 @@ Enable Signal Source Name : -- ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode236w[2] ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2]~0 ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2] ; 8 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~6 ; 8 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~4 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~13 ; 8 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[7] ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~2 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~2 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~38 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~14 ; 8 ; ; ula:ula_|video:video_|Decoder0~2 ; 8 ; ; ula:ula_|video:video_|Decoder0~1 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~19 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~13 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal48~0 ; 8 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal25~0 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~1 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~7 ; 8 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~3 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal37~0 ; 8 ; -; D[0]~49 ; 8 ; -; D[2]~40 ; 8 ; -; D[1]~31 ; 8 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~1 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~11 ; 8 ; +; D[0]~58 ; 8 ; +; D[2]~46 ; 8 ; +; D[1]~34 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~5 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal77~0 ; 8 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|table_xx~0 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal41~0 ; 8 ; ; ula:ula_|video:video_|vga_hc[0] ; 8 ; ; ula:ula_|video:video_|vga_hc[6] ; 8 ; ; ula:ula_|video:video_|vga_vc[5] ; 8 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] ; 8 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_52 ; 7 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_54 ; 7 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal38~2 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~10 ; 7 ; +; ula:ula_|always0~3 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~11 ; 7 ; ; ula:ula_|i2c_loader:i2c_loader_|nbyte[0] ; 7 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl2~0 ; 7 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~7 ; 7 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[3]~19 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel~5 ; 7 ; -; D[7]~82 ; 7 ; -; D[6]~81 ; 7 ; -; D[5]~80 ; 7 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[7] ; 7 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo ; 7 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|SYNTHESIZED_WIRE_2~0 ; 7 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~8 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~8 ; 7 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~3 ; 7 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~2 ; 7 ; +; D[7]~102 ; 7 ; +; D[6]~101 ; 7 ; +; D[5]~99 ; 7 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1]~23 ; 7 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready ; 7 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~33 ; 7 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~3 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~33 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~5 ; 7 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo ; 7 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|flags_cond_true ; 7 ; -; ula:ula_|always0~1 ; 7 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~1 ; 7 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nWR_out~0 ; 7 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nRD_out~2 ; 7 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|table_xx~0 ; 7 ; ; ula:ula_|video:video_|vga_hc[8] ; 7 ; ; ula:ula_|video:video_|vga_hc[7] ; 7 ; ; ula:ula_|video:video_|vga_vc[9] ; 7 ; ; ula:ula_|video:video_|vga_vc[1] ; 7 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] ; 7 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] ; 7 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] ; 7 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_lo~9 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~3 ; 6 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal61~2 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla77M1T1_3 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~49 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~47 ; 6 ; ; ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~11 ; 6 ; ; ula:ula_|i2c_loader:i2c_loader_|nbyte[1] ; 6 ; -; z80_top_direct_n:z80_|alu:alu_|db[7]~20 ; 6 ; -; z80_top_direct_n:z80_|alu:alu_|db[0]~18 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db[7]~21 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db[0]~19 ; 6 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[3] ; 6 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[1] ; 6 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[2] ; 6 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_edge ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~6 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~8 ; 6 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|SYNTHESIZED_WIRE_2~0 ; 6 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl2~0 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|rsel3 ; 6 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[1]~7 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~11 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~38 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[1]~20 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~27 ; 6 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla82M1T1_16 ; 6 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~36 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~7 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~35 ; 6 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_hi ; 6 ; ; ExtRamWE~0 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~2 ; 6 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_hi ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~6 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~29 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~1 ; 6 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~3 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~10 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~20 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero~4 ; 6 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal44~0 ; 6 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~0 ; 6 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_39 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|fMWrite~1 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|comb~0 ; 6 ; ; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 6 ; ; ula:ula_|video:video_|screen_en~1 ; 6 ; @@ -10941,131 +10980,131 @@ Enable Signal Source Name : -- ; ula:ula_|video:video_|vga_vc[2] ; 6 ; ; ula:ula_|video:video_|vga_vc[0] ; 6 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[13] ; 6 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] ; 6 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]~18 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_high ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla89M1T2_3 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla11M1T1_11 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla77M1T1_3 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_high ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~16 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~48 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~13 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~10 ; 5 ; ; ula:ula_|i2c_loader:i2c_loader_|nbit[0] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[5]~24 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[6]~22 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[5]~25 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[6]~23 ; 5 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|cy_out~0 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[1]~16 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[4]~17 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_low ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[3]~14 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[2]~12 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[4]~10 ; 5 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[0] ; 5 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl~0 ; 5 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68~2 ; 5 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~4 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[2]~15 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[1]~13 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[3]~11 ; 5 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|db[4]~32 ; 5 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[0] ; 5 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68~2 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~7 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~22 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~40 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_mask543_en~0 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|op1_high[2] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|op1_high[3] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[0]~13 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~27 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~15 ; 5 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~4 ; 5 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~2 ; 5 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~19 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~5 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[0]~26 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[2]~14 ; 5 ; ; z80_top_direct_n:z80_|alu:alu_|op1_high[1] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[0]~21 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[1]~15 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~9 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~18 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_high[2] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~23 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~19 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~4 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_high[3] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[0]~23 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[1]~17 ; 5 ; ; z80_top_direct_n:z80_|alu:alu_|op1_low[1] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|op1_low[2] ; 5 ; ; z80_top_direct_n:z80_|alu:alu_|op1_low[3] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT4_2 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~22 ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[11] ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[9] ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[7] ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[4] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[2] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~38 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~15 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~26 ; 5 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[13] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~6 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~4 ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[11] ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[7] ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[1] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~10 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~9 ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[9] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~5 ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[0] ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_ir~1 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|nextM~11 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~7 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~22 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~4 ; 5 ; ; ula:ula_|i2s_intf:i2s_intf_|bitcount[4]~15 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~7 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~18 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~16 ; 5 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~15 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~13 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero~4 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~15 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~8 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~7 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~5 ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~0 ; 5 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal29~0 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~6 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla56M3T3_6 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|fMWrite~3 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~0 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~0 ; 5 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nIORQ_out~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~2 ; 5 ; -; ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]~1 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~9 ; 5 ; +; ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]~1 ; 5 ; ; ula:ula_|i2s_intf:i2s_intf_|Equal1~0 ; 5 ; ; ula:ula_|video:video_|vga_hc[5] ; 5 ; ; ula:ula_|video:video_|vga_hc[4] ; 5 ; ; ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 ; 5 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] ; 5 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~3 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_iy~2 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~6 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~5 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla26M1T4_3 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~34 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~33 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla11M1T1_11 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf2_we ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~8 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~14 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla57M1T4_4 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~40 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~8 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~11 ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal68~2 ; 4 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Pause ; 4 ; ; ula:ula_|i2c_loader:i2c_loader_|nbit[1] ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71~2 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69~2 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71~2 ; 4 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Stop ; 4 ; ; z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high|ena~0 ; 4 ; ; z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|ena ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_70~2 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[3]~35 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~29 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[1]~26 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~22 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[7]~18 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[5]~15 ; 4 ; +; ula:ula_|video:video_|vram_address[9]~1 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~17 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af2~0 ; 4 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de~0 ; 4 ; -; ula:ula_|video:video_|vram_address[9]~1 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[3]~35 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[5]~29 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[1]~26 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~22 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[7]~18 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~15 ; 4 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|db[0]~12 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~5 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~19 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de~0 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_70~2 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~4 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~12 ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[2]~25 ; 4 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|cy_out~0 ; 4 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_cf ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla66npla53M1T1_15 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~32 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~30 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~8 ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~2 ; 4 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_cf ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[3]~4 ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[3]~1 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[3]~11 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[2]~6 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[2]~3 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~24 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~6 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~6 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT2_2 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~3 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~0 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~7 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~5 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~4 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~2 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~1 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[7]~24 ; 4 ; @@ -11076,88 +11115,82 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[2]~9 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[1]~6 ; 4 ; ; ula:ula_|zx_keyboard:zx_keyboard_|Equal0~2 ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~47 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~11 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~6 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[6]~24 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[7]~21 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[14] ; 4 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1]~36 ; 4 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2]~32 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[4]~24 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[5]~21 ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4]~25 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[2]~18 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[3]~15 ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~21 ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|Equal0~1 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~12 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[1]~9 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~3 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[7]~6 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[6]~3 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[4]~18 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[5]~15 ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[12] ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[3]~12 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4]~25 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[2]~9 ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[10] ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~19 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|Equal0~1 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~6 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[1]~3 ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[8] ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[6] ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|carry_borrow_out~0 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~29 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~26 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~25 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~22 ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[0] ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[1] ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[2] ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[3] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[4] ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[5] ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[14] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~7 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~3 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~5 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~85 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~53 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~34 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~31 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_pc ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~1 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~34 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo~24 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo~20 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~8 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_ixy_dT5_7 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~6 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~3 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~1 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~18 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~0 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~3 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~11 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~28 ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~2 ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal50~0 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla42M3T3_6 ; 4 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instNonRep ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~0 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~4 ; 4 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~5 ; 4 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~1 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~2 ; 4 ; -; ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] ; 4 ; -; ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~6 ; 4 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~1 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~0 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~15 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~6 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~8 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~4 ; 4 ; ; ula:ula_|i2s_intf:i2s_intf_|Equal1~1 ; 4 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_16 ; 4 ; ; ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 ; 4 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] ; 4 ; ; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 4 ; ; PS2_DAT~input ; 3 ; +; raw_loader_in~input ; 3 ; ; I2C_SDAT~input ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~39 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~42 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~87 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_use_cf2~13 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~13 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~38 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal73~2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~12 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~19 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~18 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~94 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[3]~25 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~15 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~14 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_im_we ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~9 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~16 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~50 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~19 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~17 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~18 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~17 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~12 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~56 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~36 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~18 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~16 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~38 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~35 ; 3 ; ; ula:ula_|i2c_loader:i2c_loader_|nbit[0]~4 ; 3 ; ; ula:ula_|i2c_loader:i2c_loader_|state~24 ; 3 ; ; ula:ula_|i2c_loader:i2c_loader_|nbit[2] ; 3 ; @@ -11165,142 +11198,141 @@ Enable Signal Source Name : -- ; ula:ula_|i2c_loader:i2c_loader_|divider[0] ; 3 ; ; ula:ula_|i2c_loader:i2c_loader_|scl_out~0 ; 3 ; ; z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_instIFF2 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[3]~23 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[2]~22 ; 3 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|bank_af ; 3 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de1 ; 3 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~28 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~25 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~12 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~17 ; 3 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|out[6]~2 ; 3 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~15 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_oe~1 ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|bank_af ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~9 ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de1 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|rsel0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~5 ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~30 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_oe~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~26 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~20 ; 3 ; +; ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] ; 3 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_pf ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~6 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~11 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|result~0 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|result~1 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op2[2]~2 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|result~0 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|result~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|result~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|result~0 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~5 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op2[1]~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op2[3]~2 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|cy_out~0 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|op2_high[0] ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op1[0]~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op1[0]~1 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|op1_high[0] ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~16 ; 3 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_0~16 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~33 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~31 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~28 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~9 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op2[1]~1 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op2[2]~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT4_2 ; 3 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_sf ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_nop3pla68M3T1_20 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~10 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~8 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~10 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~20 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~13 ; 3 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~11 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~9 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|op2_low[0] ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[2]~9 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~7 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~10 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~28 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~17 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~4 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~0 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~9 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~1 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~0 ; 3 ; -; ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0]~79 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~64 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~20 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~12 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0]~78 ; 3 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~51 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~47 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~10 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[2]~13 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[1]~11 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[6]~9 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[7]~7 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~27 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~9 ; 3 ; ; ula:ula_|zx_keyboard:zx_keyboard_|WideOr16~2 ; 3 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1]~41 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~24 ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[15] ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~36 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla10M5T4_2 ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_9|carry_borrow_out~0 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~24 ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_7|carry_borrow_out~0 ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~80 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~70 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~67 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~47 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~39 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~20 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|carry_borrow_out~0 ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~10 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~9 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~4 ; 3 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~33 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~11 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~19 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~32 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~5 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~17 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_pc~11 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~38 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~10 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~1 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|nextM~6 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~35 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|nextM~4 ; 3 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[1]~13 ; 3 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[2]~11 ; 3 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[7]~9 ; 3 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[6]~7 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~25 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~23 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla10M5T4_2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~77 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~43 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~45 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~36 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~35 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~30 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~1 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~28 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~5 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~27 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~7 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~5 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~29 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~30 ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~22 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~5 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~8 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~42 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|setM1~48 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|setM1~46 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~21 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~5 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~41 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~45 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~19 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~40 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal4~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~37 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~12 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal24~1 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~30 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal50~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~31 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~14 ; 3 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instNonRep ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~36 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~10 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~29 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~29 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~12 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~5 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~2 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal79~0 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~2 ; 3 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_pc~2 ; 3 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[6] ; 3 ; ; z80_top_direct_n:z80_|data_pins:data_pins_|dout[4] ; 3 ; ; z80_top_direct_n:z80_|data_pins:data_pins_|dout[3] ; 3 ; ; z80_top_direct_n:z80_|data_pins:data_pins_|dout[0] ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ; 3 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[2] ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~4 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal46~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~26 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~30 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~24 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~34 ; 3 ; ; z80_top_direct_n:z80_|data_pins:data_pins_|dout[1] ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fIOWrite~5 ; 3 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|fIORead~3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fIOWrite~5 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fIOWrite~0 ; 3 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|iorq~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fIOWrite~4 ; 3 ; ; ula:ula_|i2s_intf:i2s_intf_|LessThan0~0 ; 3 ; ; ula:ula_|i2s_intf:i2s_intf_|lrclk_r~0 ; 3 ; ; ula:ula_|video:video_|VGA_B[0]~1 ; 3 ; @@ -11312,56 +11344,79 @@ Enable Signal Source Name : -- ; ula:ula_|video:video_|Equal2~0 ; 3 ; ; ula:ula_|video:video_|LessThan6~0 ; 3 ; ; ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[12] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[11] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[10] ; 3 ; ; SW[2]~input ; 2 ; ; SW[1]~input ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~41 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_state_tbl_we~8 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~49 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~85 ; 2 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_32 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~52 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~47 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~92 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~53 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~52 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~13 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~9 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~51 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~50 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~18 ; 2 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~9 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~49 ; 2 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_0~22 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~11 ; 2 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal71~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~21 ; 2 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal73~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~46 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~18 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~15 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~11 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~16 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~10 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf_we~7 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~10 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf_we~5 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~49 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla69M2T2_3 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4]~132 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~48 ; 2 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~11 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4]~130 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_state_ixiy_we~2 ; 2 ; ; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_re~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~9 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~32 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~44 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~18 ; 2 ; ; z80_top_direct_n:z80_|interrupts:interrupts_|test1~3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~48 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~45 ; 2 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ; 2 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ; 2 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~17 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~46 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~44 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~91 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla9M1T5_2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_pc~20 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~17 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~82 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~37 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~44 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~19 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~10 ; 2 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal68~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~87 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~9 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~54 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~31 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla6M1T4_4 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~44 ; 2 ; +; D[6]~111 ; 2 ; +; D[4]~109 ; 2 ; +; D[3]~108 ; 2 ; +; D[0]~106 ; 2 ; +; D[2]~105 ; 2 ; +; D[2]~104 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|fMWrite~11 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~43 ; 2 ; +; D[1]~103 ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|shiftreg~14 ; 2 ; +; ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] ; 2 ; +; ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|Mux35~0 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~3 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~8 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Done~1 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Done~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~15 ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|ps2_clk_in ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|Equal0~1 ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[1] ; 2 ; @@ -11372,124 +11427,115 @@ Enable Signal Source Name : -- ; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[6] ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[7] ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[0] ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~15 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|sda_out~4 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|sda_out~1 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|scl_out~2 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_parity_out~0 ; 2 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|DFFE_latch_pf_tmp ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_parity_out ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~9 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_we~1 ; 2 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~8 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_we~3 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf_we~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~13 ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[8] ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|LessThan0~0 ; 2 ; -; z80_top_direct_n:z80_|interrupts:interrupts_|iff1 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~16 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~11 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~7 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~4 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~36 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~34 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~32 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~32 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~30 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~28 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~27 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~10 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~24 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~25 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~14 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~24 ; 2 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~19 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~14 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[2]~24 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~13 ; 2 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~23 ; 2 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_hf2 ; 2 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|out[6]~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~23 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~7 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~21 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~6 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~20 ; 2 ; +; z80_top_direct_n:z80_|interrupts:interrupts_|iff1 ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[8] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|LessThan0~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~16 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~10 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~39 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~6 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~4 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~8 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~5 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~37 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~35 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~33 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~31 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~24 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~34 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~32 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~23 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~27 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~1 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~22 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~7 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~25 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~24 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~22 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~20 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~8 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~7 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 ; 2 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|sel[1]~0 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~8 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~7 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[2]~24 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op1[3]~3 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op2[3]~3 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_op1[2]~2 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op2_high[2] ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op2_high[3] ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op1[1]~1 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ; 2 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|alu_core_cf_in~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~35 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~34 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~20 ; 2 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_hf ; 2 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_hf ; 2 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_cf2 ; 2 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal64~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~29 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~26 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~25 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT2_2 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_nf_we~1 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~14 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~13 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~14 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~10 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~9 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~7 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~4 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~12 ; 2 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~4 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op1[1]~0 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|op2_high[1] ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op1_low[0] ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~17 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~16 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~18 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~13 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~12 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~8 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|op2_high[2] ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~26 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~24 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~22 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~8 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|op2_high[3] ; 2 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux|out~2 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[0] ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|op2_low[1] ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op2_low[2] ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|op2_low[3] ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|op2_low[2] ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~5 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~4 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~3 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf_we~2 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~10 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~41 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~4 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~32 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~9 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~8 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~15 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~5 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~11 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~31 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~14 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla25M1T1_3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~1 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~12 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~11 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~10 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~3 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~2 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~7 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~6 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~5 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~6 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~21 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~2 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla12M1T1_12~0 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~126 ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4]~111 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4]~99 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4]~97 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4]~97 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4]~95 ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[7] ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_7|d0_out ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[6] ; 2 ; @@ -11500,32 +11546,20 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_4|d0_out ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[3] ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|d1_out ; 2 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0|carry_borrow_out~0 ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[2] ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|d0_out ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[1] ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0|d1_out ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~81 ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|shifted~1 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][0]~68 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2]~62 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][0]~67 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~63 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2]~61 ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|Selector13~0 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][2]~53 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][3]~48 ; 2 ; ; ula:ula_|clocks:clocks_|counter[0] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1]~37 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][2]~33 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][1]~31 ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[12] ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_10|d0_out ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[13] ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_10|d1_out ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][1]~29 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][1]~28 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][1]~26 ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[10] ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_9|d1_out ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[11] ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|address[11] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|shifted~0 ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[8] ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~30 ; 2 ; +---------------------------------------------------------------------------------------------------------------------------------+---------+ @@ -11552,7 +11586,7 @@ Implementation Port B Width : 8 Implementation Bits : 131072 M9Ks : 16 MIF : ula/test_scr.hex -Location : M9K_X33_Y29_N0, M9K_X33_Y20_N0, M9K_X33_Y21_N0, M9K_X33_Y18_N0, M9K_X33_Y27_N0, M9K_X33_Y26_N0, M9K_X33_Y31_N0, M9K_X33_Y19_N0, M9K_X33_Y30_N0, M9K_X33_Y28_N0, M9K_X33_Y23_N0, M9K_X33_Y24_N0, M9K_X33_Y17_N0, M9K_X33_Y16_N0, M9K_X33_Y25_N0, M9K_X33_Y22_N0 +Location : M9K_X33_Y22_N0, M9K_X33_Y24_N0, M9K_X33_Y31_N0, M9K_X33_Y28_N0, M9K_X22_Y28_N0, M9K_X22_Y27_N0, M9K_X22_Y31_N0, M9K_X22_Y23_N0, M9K_X22_Y25_N0, M9K_X22_Y22_N0, M9K_X33_Y29_N0, M9K_X22_Y26_N0, M9K_X33_Y27_N0, M9K_X33_Y25_N0, M9K_X33_Y26_N0, M9K_X22_Y24_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -11578,7 +11612,7 @@ Implementation Port B Width : -- Implementation Bits : 262144 M9Ks : 32 MIF : led_patterns.mif -Location : M9K_X22_Y7_N0, M9K_X22_Y29_N0, M9K_X22_Y9_N0, M9K_X22_Y5_N0, M9K_X22_Y23_N0, M9K_X22_Y18_N0, M9K_X22_Y14_N0, M9K_X22_Y19_N0, M9K_X22_Y27_N0, M9K_X22_Y3_N0, M9K_X22_Y8_N0, M9K_X22_Y2_N0, M9K_X22_Y20_N0, M9K_X22_Y31_N0, M9K_X22_Y15_N0, M9K_X22_Y22_N0, M9K_X22_Y32_N0, M9K_X22_Y21_N0, M9K_X22_Y28_N0, M9K_X22_Y26_N0, M9K_X22_Y11_N0, M9K_X33_Y32_N0, M9K_X22_Y30_N0, M9K_X22_Y17_N0, M9K_X22_Y16_N0, M9K_X22_Y4_N0, M9K_X22_Y6_N0, M9K_X33_Y3_N0, M9K_X22_Y12_N0, M9K_X22_Y24_N0, M9K_X22_Y10_N0, M9K_X22_Y25_N0 +Location : M9K_X33_Y19_N0, M9K_X33_Y18_N0, M9K_X33_Y15_N0, M9K_X33_Y20_N0, M9K_X33_Y12_N0, M9K_X33_Y8_N0, M9K_X22_Y12_N0, M9K_X33_Y9_N0, M9K_X22_Y13_N0, M9K_X33_Y16_N0, M9K_X33_Y13_N0, M9K_X33_Y14_N0, M9K_X22_Y11_N0, M9K_X22_Y5_N0, M9K_X22_Y15_N0, M9K_X22_Y18_N0, M9K_X22_Y8_N0, M9K_X22_Y16_N0, M9K_X22_Y3_N0, M9K_X22_Y14_N0, M9K_X22_Y6_N0, M9K_X22_Y7_N0, M9K_X22_Y9_N0, M9K_X33_Y23_N0, M9K_X33_Y11_N0, M9K_X33_Y6_N0, M9K_X33_Y10_N0, M9K_X22_Y10_N0, M9K_X33_Y5_N0, M9K_X33_Y7_N0, M9K_X33_Y4_N0, M9K_X22_Y4_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -11604,7 +11638,7 @@ Implementation Port B Width : -- Implementation Bits : 131072 M9Ks : 16 MIF : ./rom/gw03.hex -Location : M9K_X33_Y33_N0, M9K_X33_Y9_N0, M9K_X33_Y8_N0, M9K_X33_Y11_N0, M9K_X33_Y7_N0, M9K_X33_Y10_N0, M9K_X33_Y14_N0, M9K_X33_Y15_N0, M9K_X33_Y4_N0, M9K_X33_Y12_N0, M9K_X33_Y2_N0, M9K_X33_Y6_N0, M9K_X22_Y13_N0, M9K_X33_Y13_N0, M9K_X33_Y1_N0, M9K_X33_Y5_N0 +Location : M9K_X33_Y32_N0, M9K_X33_Y21_N0, M9K_X22_Y17_N0, M9K_X33_Y17_N0, M9K_X22_Y30_N0, M9K_X22_Y20_N0, M9K_X22_Y19_N0, M9K_X22_Y21_N0, M9K_X22_Y1_N0, M9K_X33_Y3_N0, M9K_X22_Y29_N0, M9K_X33_Y2_N0, M9K_X33_Y33_N0, M9K_X33_Y1_N0, M9K_X33_Y30_N0, M9K_X22_Y2_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -19835,53 +19869,53 @@ RAM content values are presented in the following format: (Binary) (Octal) (Deci +-----------------------+------------------------+ ; Routing Resource Type ; Usage ; +-----------------------+------------------------+ -; Block interconnects ; 5,032 / 71,559 ( 7 % ) ; -; C16 interconnects ; 108 / 2,597 ( 4 % ) ; -; C4 interconnects ; 2,831 / 46,848 ( 6 % ) ; -; Direct links ; 380 / 71,559 ( < 1 % ) ; +; Block interconnects ; 5,027 / 71,559 ( 7 % ) ; +; C16 interconnects ; 124 / 2,597 ( 5 % ) ; +; C4 interconnects ; 2,759 / 46,848 ( 6 % ) ; +; Direct links ; 421 / 71,559 ( < 1 % ) ; ; Global clocks ; 9 / 20 ( 45 % ) ; -; Local interconnects ; 1,230 / 24,624 ( 5 % ) ; -; R24 interconnects ; 93 / 2,496 ( 4 % ) ; -; R4 interconnects ; 2,596 / 62,424 ( 4 % ) ; +; Local interconnects ; 1,200 / 24,624 ( 5 % ) ; +; R24 interconnects ; 107 / 2,496 ( 4 % ) ; +; R4 interconnects ; 2,921 / 62,424 ( 5 % ) ; +-----------------------+------------------------+ +-----------------------------------------------------------------------------+ ; LAB Logic Elements ; +---------------------------------------------+-------------------------------+ -; Number of Logic Elements (Average = 12.81) ; Number of LABs (Total = 186) ; +; Number of Logic Elements (Average = 12.95) ; Number of LABs (Total = 185) ; +---------------------------------------------+-------------------------------+ -; 1 ; 11 ; -; 2 ; 11 ; -; 3 ; 5 ; -; 4 ; 1 ; -; 5 ; 1 ; -; 6 ; 4 ; +; 1 ; 17 ; +; 2 ; 5 ; +; 3 ; 4 ; +; 4 ; 2 ; +; 5 ; 2 ; +; 6 ; 1 ; ; 7 ; 0 ; -; 8 ; 2 ; +; 8 ; 5 ; ; 9 ; 1 ; -; 10 ; 2 ; -; 11 ; 2 ; -; 12 ; 4 ; -; 13 ; 11 ; -; 14 ; 15 ; -; 15 ; 22 ; -; 16 ; 94 ; +; 10 ; 1 ; +; 11 ; 3 ; +; 12 ; 2 ; +; 13 ; 7 ; +; 14 ; 7 ; +; 15 ; 20 ; +; 16 ; 108 ; +---------------------------------------------+-------------------------------+ +--------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+-------------------------------+ -; LAB-wide Signals (Average = 1.17) ; Number of LABs (Total = 186) ; +; LAB-wide Signals (Average = 1.12) ; Number of LABs (Total = 185) ; +------------------------------------+-------------------------------+ -; 1 Async. clear ; 47 ; -; 1 Clock ; 101 ; -; 1 Clock enable ; 34 ; +; 1 Async. clear ; 49 ; +; 1 Clock ; 94 ; +; 1 Clock enable ; 35 ; ; 1 Sync. clear ; 1 ; -; 1 Sync. load ; 5 ; -; 2 Async. clears ; 1 ; -; 2 Clock enables ; 25 ; +; 1 Sync. load ; 4 ; +; 2 Async. clears ; 2 ; +; 2 Clock enables ; 19 ; ; 2 Clocks ; 3 ; +------------------------------------+-------------------------------+ @@ -19889,107 +19923,111 @@ RAM content values are presented in the following format: (Binary) (Octal) (Deci +------------------------------------------------------------------------------+ ; LAB Signals Sourced ; +----------------------------------------------+-------------------------------+ -; Number of Signals Sourced (Average = 15.65) ; Number of LABs (Total = 186) ; +; Number of Signals Sourced (Average = 15.85) ; Number of LABs (Total = 185) ; +----------------------------------------------+-------------------------------+ ; 0 ; 0 ; -; 1 ; 5 ; -; 2 ; 10 ; -; 3 ; 1 ; -; 4 ; 8 ; -; 5 ; 2 ; -; 6 ; 3 ; -; 7 ; 1 ; -; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 2 ; -; 11 ; 2 ; -; 12 ; 4 ; -; 13 ; 8 ; -; 14 ; 9 ; -; 15 ; 7 ; -; 16 ; 52 ; -; 17 ; 8 ; -; 18 ; 6 ; -; 19 ; 10 ; -; 20 ; 8 ; -; 21 ; 8 ; -; 22 ; 3 ; -; 23 ; 2 ; +; 1 ; 11 ; +; 2 ; 9 ; +; 3 ; 2 ; +; 4 ; 1 ; +; 5 ; 3 ; +; 6 ; 2 ; +; 7 ; 0 ; +; 8 ; 4 ; +; 9 ; 2 ; +; 10 ; 1 ; +; 11 ; 1 ; +; 12 ; 2 ; +; 13 ; 6 ; +; 14 ; 5 ; +; 15 ; 8 ; +; 16 ; 55 ; +; 17 ; 7 ; +; 18 ; 8 ; +; 19 ; 6 ; +; 20 ; 5 ; +; 21 ; 6 ; +; 22 ; 8 ; +; 23 ; 5 ; ; 24 ; 9 ; -; 25 ; 2 ; -; 26 ; 5 ; +; 25 ; 8 ; +; 26 ; 1 ; ; 27 ; 4 ; -; 28 ; 3 ; -; 29 ; 2 ; -; 30 ; 1 ; +; 28 ; 1 ; +; 29 ; 1 ; +; 30 ; 3 ; +; 31 ; 0 ; +; 32 ; 1 ; +----------------------------------------------+-------------------------------+ +---------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+-------------------------------+ -; Number of Signals Sourced Out (Average = 8.03) ; Number of LABs (Total = 186) ; +; Number of Signals Sourced Out (Average = 8.41) ; Number of LABs (Total = 185) ; +-------------------------------------------------+-------------------------------+ ; 0 ; 0 ; -; 1 ; 16 ; -; 2 ; 15 ; -; 3 ; 5 ; -; 4 ; 2 ; -; 5 ; 11 ; -; 6 ; 10 ; -; 7 ; 18 ; -; 8 ; 23 ; -; 9 ; 20 ; -; 10 ; 12 ; -; 11 ; 12 ; -; 12 ; 12 ; -; 13 ; 8 ; -; 14 ; 14 ; -; 15 ; 5 ; -; 16 ; 2 ; -; 17 ; 1 ; +; 1 ; 24 ; +; 2 ; 8 ; +; 3 ; 3 ; +; 4 ; 6 ; +; 5 ; 7 ; +; 6 ; 9 ; +; 7 ; 15 ; +; 8 ; 19 ; +; 9 ; 13 ; +; 10 ; 18 ; +; 11 ; 10 ; +; 12 ; 20 ; +; 13 ; 10 ; +; 14 ; 4 ; +; 15 ; 9 ; +; 16 ; 6 ; +; 17 ; 2 ; +; 18 ; 1 ; +; 19 ; 0 ; +; 20 ; 1 ; +-------------------------------------------------+-------------------------------+ +------------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+-------------------------------+ -; Number of Distinct Inputs (Average = 19.41) ; Number of LABs (Total = 186) ; +; Number of Distinct Inputs (Average = 19.44) ; Number of LABs (Total = 185) ; +----------------------------------------------+-------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; -; 2 ; 3 ; -; 3 ; 7 ; -; 4 ; 12 ; -; 5 ; 4 ; +; 2 ; 4 ; +; 3 ; 5 ; +; 4 ; 10 ; +; 5 ; 3 ; ; 6 ; 5 ; -; 7 ; 6 ; -; 8 ; 0 ; +; 7 ; 5 ; +; 8 ; 1 ; ; 9 ; 4 ; -; 10 ; 0 ; -; 11 ; 4 ; -; 12 ; 3 ; -; 13 ; 6 ; -; 14 ; 4 ; -; 15 ; 5 ; +; 10 ; 2 ; +; 11 ; 3 ; +; 12 ; 4 ; +; 13 ; 5 ; +; 14 ; 9 ; +; 15 ; 6 ; ; 16 ; 4 ; -; 17 ; 4 ; -; 18 ; 6 ; -; 19 ; 9 ; -; 20 ; 7 ; -; 21 ; 5 ; -; 22 ; 12 ; +; 17 ; 5 ; +; 18 ; 9 ; +; 19 ; 3 ; +; 20 ; 5 ; +; 21 ; 4 ; +; 22 ; 2 ; ; 23 ; 6 ; -; 24 ; 2 ; -; 25 ; 4 ; -; 26 ; 9 ; -; 27 ; 4 ; -; 28 ; 4 ; +; 24 ; 6 ; +; 25 ; 10 ; +; 26 ; 6 ; +; 27 ; 5 ; +; 28 ; 8 ; ; 29 ; 8 ; -; 30 ; 6 ; -; 31 ; 13 ; -; 32 ; 16 ; -; 33 ; 4 ; +; 30 ; 9 ; +; 31 ; 14 ; +; 32 ; 14 ; +----------------------------------------------+-------------------------------+ @@ -20286,24 +20324,24 @@ Extra Information : ; I/O Rules Matrix ; +--------------------------------------------------------------------------------+ Pin/Rules : Total Pass -IO_000001 : 74 +IO_000001 : 75 IO_000002 : 9 -IO_000003 : 74 +IO_000003 : 75 IO_000004 : 0 IO_000005 : 0 -IO_000006 : 74 -IO_000007 : 74 +IO_000006 : 75 +IO_000007 : 75 IO_000008 : 0 -IO_000009 : 74 -IO_000010 : 74 +IO_000009 : 75 +IO_000010 : 75 IO_000011 : 0 IO_000012 : 0 IO_000013 : 0 IO_000014 : 0 -IO_000015 : 40 +IO_000015 : 41 IO_000018 : 0 IO_000019 : 0 -IO_000020 : 40 +IO_000020 : 41 IO_000021 : 0 IO_000022 : 0 IO_000023 : 2 @@ -20313,7 +20351,7 @@ IO_000027 : 0 IO_000045 : 0 IO_000046 : 0 IO_000047 : 0 -IO_000033 : 74 +IO_000033 : 75 IO_000034 : 0 IO_000042 : 0 @@ -20351,35 +20389,35 @@ IO_000042 : 0 Pin/Rules : Total Inapplicable IO_000001 : 0 -IO_000002 : 65 +IO_000002 : 66 IO_000003 : 0 -IO_000004 : 74 -IO_000005 : 74 +IO_000004 : 75 +IO_000005 : 75 IO_000006 : 0 IO_000007 : 0 -IO_000008 : 74 +IO_000008 : 75 IO_000009 : 0 IO_000010 : 0 -IO_000011 : 74 -IO_000012 : 74 -IO_000013 : 74 -IO_000014 : 74 +IO_000011 : 75 +IO_000012 : 75 +IO_000013 : 75 +IO_000014 : 75 IO_000015 : 34 -IO_000018 : 74 -IO_000019 : 74 +IO_000018 : 75 +IO_000019 : 75 IO_000020 : 34 -IO_000021 : 74 -IO_000022 : 74 -IO_000023 : 72 -IO_000024 : 74 -IO_000026 : 74 -IO_000027 : 74 -IO_000045 : 74 -IO_000046 : 74 -IO_000047 : 74 +IO_000021 : 75 +IO_000022 : 75 +IO_000023 : 73 +IO_000024 : 75 +IO_000026 : 75 +IO_000027 : 75 +IO_000045 : 75 +IO_000046 : 75 +IO_000047 : 75 IO_000033 : 0 -IO_000034 : 74 -IO_000042 : 74 +IO_000034 : 75 +IO_000042 : 75 Pin/Rules : Total Fail IO_000001 : 0 @@ -22589,6 +22627,38 @@ IO_000033 : Pass IO_000034 : Inapplicable IO_000042 : Inapplicable +Pin/Rules : raw_loader_in +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + Pin/Rules : KEY[0] IO_000001 : Pass IO_000002 : Inapplicable @@ -22653,7 +22723,7 @@ IO_000033 : Pass IO_000034 : Inapplicable IO_000042 : Inapplicable -Pin/Rules : KEY[1] +Pin/Rules : PS2_DAT IO_000001 : Pass IO_000002 : Inapplicable IO_000003 : Pass @@ -22685,7 +22755,7 @@ IO_000033 : Pass IO_000034 : Inapplicable IO_000042 : Inapplicable -Pin/Rules : PS2_DAT +Pin/Rules : KEY[1] IO_000001 : Pass IO_000002 : Inapplicable IO_000003 : Pass @@ -22826,7 +22896,11 @@ IO_000042 : Inapplicable +--------------------------------------------------------------------------------+ Source Clock(s) : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Destination Clock(s) : CLOCK_50 -Delay Added in ns : 172.4 +Delay Added in ns : 646.3 + +Source Clock(s) : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Destination Clock(s) : CLOCK_50,ula_|pll_|altpll_component|auto_generated|pll1|clk[0],I/O +Delay Added in ns : 20.5 +--------------------------------------------------------------------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. @@ -22837,263 +22911,407 @@ This will disable optimization of problematic paths and expose them for further ; Estimated Delay Added for Hold Timing Details ; +--------------------------------------------------------------------------------+ Source Register : ula:ula_|video:video_|vram_address[8] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Delay Added in ns : 1.483 - -Source Register : ula:ula_|video:video_|vram_address[11] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Delay Added in ns : 1.483 - -Source Register : ula:ula_|video:video_|vram_address[9] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Delay Added in ns : 1.482 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Delay Added in ns : 3.927 Source Register : ula:ula_|video:video_|vram_address[12] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Delay Added in ns : 1.482 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Delay Added in ns : 3.927 -Source Register : ula:ula_|video:video_|vram_address[5] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Delay Added in ns : 1.428 +Source Register : ula:ula_|video:video_|vram_address[9] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Delay Added in ns : 3.925 -Source Register : ula:ula_|video:video_|vram_address[6] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Delay Added in ns : 1.428 - -Source Register : ula:ula_|video:video_|vram_address[7] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Delay Added in ns : 1.427 +Source Register : ula:ula_|video:video_|vram_address[11] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Delay Added in ns : 3.925 Source Register : ula:ula_|video:video_|vram_address[10] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Delay Added in ns : 1.211 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Delay Added in ns : 3.878 -Source Register : ula:ula_|video:video_|vram_address[1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Delay Added in ns : 1.202 +Source Register : ula:ula_|video:video_|vram_address[5] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Delay Added in ns : 3.683 -Source Register : ula:ula_|video:video_|vram_address[2] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Delay Added in ns : 1.202 +Source Register : ula:ula_|video:video_|vram_address[6] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Delay Added in ns : 3.680 -Source Register : ula:ula_|video:video_|vram_address[3] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Delay Added in ns : 1.202 - -Source Register : ula:ula_|video:video_|vram_address[4] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Delay Added in ns : 1.202 +Source Register : ula:ula_|video:video_|vram_address[7] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Delay Added in ns : 3.680 Source Register : ula:ula_|video:video_|vram_address[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Delay Added in ns : 1.198 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Delay Added in ns : 3.437 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 +Source Register : ula:ula_|video:video_|vram_address[2] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Delay Added in ns : 3.437 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 +Source Register : ula:ula_|video:video_|vram_address[4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Delay Added in ns : 3.437 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 +Source Register : ula:ula_|video:video_|vram_address[1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Delay Added in ns : 3.435 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|data_pins:data_pins_|dout[6] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 +Source Register : ula:ula_|video:video_|vram_address[3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Delay Added in ns : 3.431 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Delay Added in ns : 1.522 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Delay Added in ns : 1.458 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Delay Added in ns : 1.233 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 1.069 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Delay Added in ns : 1.013 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.967 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.882 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.847 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.827 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Delay Added in ns : 0.798 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.755 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.743 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.724 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Delay Added in ns : 0.719 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Delay Added in ns : 0.718 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Delay Added in ns : 0.681 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Delay Added in ns : 0.671 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Delay Added in ns : 0.627 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.613 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Delay Added in ns : 0.597 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.592 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.592 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.592 Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.592 Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.592 -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_intr_ff3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorqinta -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_mrd_ff3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|mwr_wr -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_15 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorq -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_iorq_ff4 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|M5 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|in_halt -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[5] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[4] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[7] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[3] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[6] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[2] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.592 Source Register : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Delay Added in ns : 0.219 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.592 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Delay Added in ns : 0.581 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.581 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.573 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.524 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.524 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.524 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.524 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Delay Added in ns : 0.521 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.518 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.495 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Delay Added in ns : 0.490 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.436 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Delay Added in ns : 0.433 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Delay Added in ns : 0.433 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Delay Added in ns : 0.433 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Delay Added in ns : 0.433 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Delay Added in ns : 0.433 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[0][1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[1][1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[2][1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[3][1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[4][1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[13] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[8] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[9] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[10] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[11] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[12] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_intr_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorqinta +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_mrd_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|mwr_wr +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorq +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_iorq_ff4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[6] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[2] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[7] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[5] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.428 +--------------------------------------------------------------------------------+ -Note: This table only shows the top 64 path(s) that have the largest delay added for hold. +Note: This table only shows the top 100 path(s) that have the largest delay added for hold. +-----------------+ @@ -23139,62 +23357,11 @@ Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock -Warning (332125): Found combinational loop of 514 nodes - Warning (332126): Node "z80_|bus_control_|db[2]~11|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~21|dataa" - Warning (332126): Node "z80_|alu_control_|db[2]~21|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~22|datad" - Warning (332126): Node "z80_|alu_control_|db[2]~22|combout" - Warning (332126): Node "z80_|alu_|db[2]~11|dataa" - Warning (332126): Node "z80_|alu_|db[2]~11|combout" - Warning (332126): Node "z80_|alu_|db[2]~12|dataa" - Warning (332126): Node "z80_|alu_|db[2]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~62|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~62|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~64|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~64|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~65|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~65|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~66|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~66|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~16|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~16|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~17|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~18|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~18|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~66|datab" - Warning (332126): Node "z80_|alu_|db[2]~11|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~13|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~13|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~14|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~14|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~15|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~15|combout" - Warning (332126): Node "z80_|alu_|db[1]~16|datab" - Warning (332126): Node "z80_|alu_|db[1]~16|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~5|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~5|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~6|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~6|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~9|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~9|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~22|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~22|combout" - Warning (332126): Node "z80_|alu_|db[2]~12|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~16|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~16|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~17|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~17|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~21|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" - Warning (332126): Node "z80_|alu_|db[0]~17|datab" - Warning (332126): Node "z80_|alu_|db[0]~17|combout" - Warning (332126): Node "z80_|alu_|db[0]~18|dataa" - Warning (332126): Node "z80_|alu_|db[0]~18|combout" - Warning (332126): Node "z80_|sw2_|db_up[0]~0|dataa" - Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|dataa" +Warning (332125): Found combinational loop of 511 nodes + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~9|datac" Warning (332126): Node "z80_|alu_control_|db[0]~9|combout" Warning (332126): Node "z80_|alu_control_|db[0]~12|dataa" Warning (332126): Node "z80_|alu_control_|db[0]~12|combout" @@ -23203,135 +23370,357 @@ Warning (332125): Found combinational loop of 514 nodes Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datab" - Warning (332126): Node "z80_|alu_|db[0]~18|datab" - Warning (332126): Node "z80_|bus_control_|db[0]~15|datab" - Warning (332126): Node "z80_|bus_control_|db[0]~15|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~8|datab" - Warning (332126): Node "z80_|alu_control_|db[0]~8|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|datab" + Warning (332126): Node "z80_|alu_|db[0]~19|datab" + Warning (332126): Node "z80_|alu_|db[0]~19|combout" + Warning (332126): Node "z80_|sw2_|db_up[0]~0|dataa" + Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~9|dataa" Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac" Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|datab" Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~14|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~14|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~15|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~15|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~18|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~18|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~19|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~19|combout" - Warning (332126): Node "z80_|alu_|db[7]~20|datab" - Warning (332126): Node "z80_|alu_|db[7]~20|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~20|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~20|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~21|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~21|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~24|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~24|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~25|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~25|combout" - Warning (332126): Node "z80_|alu_|db[6]~22|datab" - Warning (332126): Node "z80_|alu_|db[6]~22|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~21|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~14|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~12|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~14|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~14|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~15|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~21|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~21|combout" - Warning (332126): Node "z80_|alu_|db[6]~21|datab" - Warning (332126): Node "z80_|alu_|db[6]~21|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~5|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~6|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~7|datac" + Warning (332126): Node "z80_|alu_|db_high[3]~7|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~8|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~8|combout" + Warning (332126): Node "z80_|alu_|db[7]~21|datab" + Warning (332126): Node "z80_|alu_|db[7]~21|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~11|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~12|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~12|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~13|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~14|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~14|combout" + Warning (332126): Node "z80_|alu_|db[6]~23|datab" + Warning (332126): Node "z80_|alu_|db[6]~23|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~12|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" + Warning (332126): Node "z80_|alu_control_|db[6]~20|dataa" + Warning (332126): Node "z80_|alu_control_|db[6]~20|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~21|datad" + Warning (332126): Node "z80_|alu_control_|db[6]~21|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~22|datad" + Warning (332126): Node "z80_|alu_control_|db[6]~22|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~8|datab" + Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~9|dataa" + Warning (332126): Node "z80_|bus_control_|db[6]~9|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~21|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab" + Warning (332126): Node "z80_|alu_control_|db[6]~22|dataa" Warning (332126): Node "z80_|alu_|db[6]~22|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~0|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~1|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~3|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~3|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~21|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~4|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~4|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~5|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~5|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~6|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~6|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~7|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~7|combout" - Warning (332126): Node "z80_|alu_|db[5]~24|datab" - Warning (332126): Node "z80_|alu_|db[5]~24|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~29|datab" - Warning (332126): Node "z80_|alu_control_|db[5]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~28|datac" - Warning (332126): Node "z80_|alu_control_|db[5]~28|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~29|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datab" - Warning (332126): Node "z80_|alu_|db[5]~23|datab" - Warning (332126): Node "z80_|alu_|db[5]~23|combout" - Warning (332126): Node "z80_|alu_|db[5]~24|dataa" - Warning (332126): Node "z80_|bus_control_|db[5]~17|datab" - Warning (332126): Node "z80_|bus_control_|db[5]~17|combout" - Warning (332126): Node "z80_|sw1_|db_down[5]~1|dataa" - Warning (332126): Node "z80_|sw1_|db_down[5]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~28|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~23|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~23|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~24|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~17|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~17|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~18|datac" - Warning (332126): Node "z80_|alu_|db_low[1]~10|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~10|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~12|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~12|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|combout" + Warning (332126): Node "z80_|alu_|db[6]~23|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datab" + Warning (332126): Node "z80_|alu_|db[6]~22|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~19|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~20|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~20|combout" + Warning (332126): Node "z80_|alu_|db[5]~25|datab" + Warning (332126): Node "z80_|alu_|db[5]~25|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~25|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~26|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~26|combout" + Warning (332126): Node "z80_|alu_|db[4]~17|datab" + Warning (332126): Node "z80_|alu_|db[4]~17|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~7|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~7|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~8|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~8|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~11|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~11|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~25|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~25|combout" + Warning (332126): Node "z80_|alu_|db[3]~10|datab" + Warning (332126): Node "z80_|alu_|db[3]~10|combout" + Warning (332126): Node "z80_|alu_|db[3]~11|dataa" + Warning (332126): Node "z80_|alu_|db[3]~11|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~8|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~23|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|combout" + Warning (332126): Node "z80_|alu_|db[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~2|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~2|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~3|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~3|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~24|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~24|combout" + Warning (332126): Node "z80_|alu_|db[2]~15|datab" + Warning (332126): Node "z80_|alu_|db[2]~15|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~7|datab" + Warning (332126): Node "z80_|alu_control_|db[2]~27|datac" + Warning (332126): Node "z80_|alu_control_|db[2]~27|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~29|datac" + Warning (332126): Node "z80_|alu_control_|db[2]~29|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~12|datab" + Warning (332126): Node "z80_|bus_control_|db[2]~12|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~13|dataa" + Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa" + Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~29|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~28|datad" + Warning (332126): Node "z80_|alu_|db[2]~14|dataa" + Warning (332126): Node "z80_|alu_|db[2]~14|combout" + Warning (332126): Node "z80_|alu_|db[2]~15|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datab" + Warning (332126): Node "z80_|alu_|db[2]~14|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~3|datab" Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~18|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~15|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~16|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~16|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" + Warning (332126): Node "z80_|alu_|db[1]~13|datab" + Warning (332126): Node "z80_|alu_|db[1]~13|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~21|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~22|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~22|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~23|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" + Warning (332126): Node "z80_|alu_|db[0]~18|datab" + Warning (332126): Node "z80_|alu_|db[0]~18|combout" + Warning (332126): Node "z80_|alu_|db[0]~19|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" + Warning (332126): Node "z80_|alu_|db[1]~12|datab" + Warning (332126): Node "z80_|alu_|db[1]~12|combout" + Warning (332126): Node "z80_|alu_|db[1]~13|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~2|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~16|datab" + Warning (332126): Node "z80_|alu_control_|db[1]~24|datac" + Warning (332126): Node "z80_|alu_control_|db[1]~24|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~26|datac" + Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~10|datab" + Warning (332126): Node "z80_|bus_control_|db[1]~10|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~11|dataa" + Warning (332126): Node "z80_|bus_control_|db[1]~11|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~25|dataa" + Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~26|datad" + Warning (332126): Node "z80_|alu_|db[1]~12|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~25|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~35|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~34|datac" + Warning (332126): Node "z80_|alu_control_|db[3]~34|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datab" + Warning (332126): Node "z80_|alu_|db[3]~11|datab" + Warning (332126): Node "z80_|bus_control_|db[3]~21|datab" + Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" + Warning (332126): Node "z80_|sw1_|db_down[3]~1|dataa" + Warning (332126): Node "z80_|sw1_|db_down[3]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~9|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~9|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~27|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~27|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~7|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~21|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~21|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~18|datac" Warning (332126): Node "z80_|alu_|db_low[0]~18|combout" Warning (332126): Node "z80_|alu_|db_low[0]~20|dataa" Warning (332126): Node "z80_|alu_|db_low[0]~20|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~21|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~8|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~8|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~12|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~12|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~13|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~13|combout" - Warning (332126): Node "z80_|alu_|db[4]~10|datab" - Warning (332126): Node "z80_|alu_|db[4]~10|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~12|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~12|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~14|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~14|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~15|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~15|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~4|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~4|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~6|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~6|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~24|datab" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~10|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~10|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~11|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~24|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datab" + Warning (332126): Node "z80_|alu_|db[4]~16|dataa" + Warning (332126): Node "z80_|alu_|db[4]~16|combout" + Warning (332126): Node "z80_|alu_|db[4]~17|dataa" Warning (332126): Node "z80_|alu_control_|db[4]~30|dataa" Warning (332126): Node "z80_|alu_control_|db[4]~30|combout" Warning (332126): Node "z80_|alu_control_|db[4]~31|datad" Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" Warning (332126): Node "z80_|alu_control_|db[4]~32|datad" Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" + Warning (332126): Node "z80_|bus_control_|db[4]~19|datab" + Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~9|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~27|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~21|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~18|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~15|datac" + Warning (332126): Node "z80_|alu_control_|db[4]~32|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~4|dataa" + Warning (332126): Node "z80_|alu_|db[4]~16|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|dataa" @@ -23346,183 +23735,92 @@ Warning (332125): Found combinational loop of 514 nodes Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datab" - Warning (332126): Node "z80_|alu_|db[4]~8|datab" - Warning (332126): Node "z80_|alu_|db[4]~8|combout" - Warning (332126): Node "z80_|alu_|db[4]~10|dataa" - Warning (332126): Node "z80_|bus_control_|db[4]~19|datab" - Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~32|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~17|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~10|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~18|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~8|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~2|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~2|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~6|dataa" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|dataa" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~3|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~3|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~4|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~4|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~23|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~23|combout" - Warning (332126): Node "z80_|alu_|db[3]~13|datab" - Warning (332126): Node "z80_|alu_|db[3]~13|combout" - Warning (332126): Node "z80_|alu_|db[3]~14|dataa" - Warning (332126): Node "z80_|alu_|db[3]~14|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~5|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~10|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~10|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~11|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~11|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~12|datac" - Warning (332126): Node "z80_|alu_|db_low[3]~1|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~1|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~23|dataa" - Warning (332126): Node "z80_|alu_control_|db[3]~35|datab" - Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" - Warning (332126): Node "z80_|bus_control_|db[3]~21|datab" - Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~17|datac" - Warning (332126): Node "z80_|alu_|db_low[1]~10|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~18|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~8|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~2|datab" - Warning (332126): Node "z80_|sw1_|db_down[3]~2|dataa" - Warning (332126): Node "z80_|sw1_|db_down[3]~2|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa" - Warning (332126): Node "z80_|alu_control_|db[3]~34|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datad" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~23|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~8|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~8|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~9|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datab" - Warning (332126): Node "z80_|alu_control_|db[3]~34|datac" - Warning (332126): Node "z80_|alu_|db[3]~14|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~53|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~53|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~55|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~55|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~56|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~56|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~57|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~57|combout" - Warning (332126): Node "z80_|alu_|db[3]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~14|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~14|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~15|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~57|datab" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~80|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~80|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~82|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~82|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~83|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~83|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~84|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~84|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~22|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~23|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~23|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~24|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~84|datab" - Warning (332126): Node "z80_|alu_|db[4]~8|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~4|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~0|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~0|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~1|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~11|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~2|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~3|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~8|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~20|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~10|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~5|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~71|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~71|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~73|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~73|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~74|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~74|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~75|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~75|combout" - Warning (332126): Node "z80_|alu_|db[5]~23|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~19|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~20|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~21|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~75|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~14|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~14|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~15|datac" - Warning (332126): Node "z80_|alu_control_|db[6]~15|combout" - Warning (332126): Node "z80_|bus_control_|db[6]~5|datab" - Warning (332126): Node "z80_|bus_control_|db[6]~5|combout" - Warning (332126): Node "z80_|bus_control_|db[6]~7|dataa" - Warning (332126): Node "z80_|bus_control_|db[6]~7|combout" - Warning (332126): Node "z80_|sw1_|db_down[6]~0|dataa" - Warning (332126): Node "z80_|sw1_|db_down[6]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~15|dataa" - Warning (332126): Node "z80_|alu_|db[6]~21|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~15|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~15|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datab" + Warning (332126): Node "z80_|alu_|db[5]~24|dataa" + Warning (332126): Node "z80_|alu_|db[5]~24|combout" + Warning (332126): Node "z80_|alu_|db[5]~25|dataa" + Warning (332126): Node "z80_|alu_control_|db[5]~15|datab" + Warning (332126): Node "z80_|alu_control_|db[5]~15|combout" + Warning (332126): Node "z80_|bus_control_|db[5]~15|datab" + Warning (332126): Node "z80_|bus_control_|db[5]~15|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~10|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~9|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~27|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~21|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~18|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~15|dataa" + Warning (332126): Node "z80_|sw1_|db_down[5]~0|dataa" + Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~14|dataa" + Warning (332126): Node "z80_|alu_control_|db[5]~14|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~15|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~4|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datab" + Warning (332126): Node "z80_|alu_control_|db[5]~14|datac" + Warning (332126): Node "z80_|alu_|db[5]~24|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~18|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datab" + Warning (332126): Node "z80_|alu_|db[7]~20|datab" + Warning (332126): Node "z80_|alu_|db[7]~20|combout" + Warning (332126): Node "z80_|alu_|db[7]~21|dataa" Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa" Warning (332126): Node "z80_|alu_control_|db[7]~16|datac" Warning (332126): Node "z80_|alu_control_|db[7]~16|combout" Warning (332126): Node "z80_|alu_control_|db[7]~18|datac" Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~8|datab" - Warning (332126): Node "z80_|bus_control_|db[7]~8|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~9|dataa" - Warning (332126): Node "z80_|bus_control_|db[7]~9|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~5|datab" + Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~7|dataa" + Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" Warning (332126): Node "z80_|alu_control_|db[7]~17|dataa" Warning (332126): Node "z80_|alu_control_|db[7]~17|combout" Warning (332126): Node "z80_|alu_control_|db[7]~18|datad" + Warning (332126): Node "z80_|alu_|db[7]~20|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datad" @@ -23531,6 +23829,9 @@ Warning (332125): Found combinational loop of 514 nodes Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~17|datad" Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|dataa" @@ -23538,123 +23839,37 @@ Warning (332125): Found combinational loop of 514 nodes Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~1|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~17|datad" - Warning (332126): Node "z80_|alu_|db[7]~19|dataa" - Warning (332126): Node "z80_|alu_|db[7]~19|combout" - Warning (332126): Node "z80_|alu_|db[7]~20|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~26|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~26|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~28|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~28|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~29|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~30|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~30|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~4|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~4|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~5|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~5|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~6|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~6|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~30|datab" - Warning (332126): Node "z80_|alu_|db[7]~19|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~16|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~17|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~44|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~44|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~46|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~47|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~48|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~48|combout" - Warning (332126): Node "z80_|alu_|db[0]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~10|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~11|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~12|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~48|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~13|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~35|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~35|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~37|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~37|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~38|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~38|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~39|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~39|combout" - Warning (332126): Node "z80_|alu_|db[1]~15|datab" - Warning (332126): Node "z80_|alu_|db[1]~15|combout" - Warning (332126): Node "z80_|alu_|db[1]~16|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~7|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~7|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~8|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~9|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~39|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~14|datab" - Warning (332126): Node "z80_|alu_control_|db[1]~23|datac" - Warning (332126): Node "z80_|alu_control_|db[1]~23|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~24|datad" - Warning (332126): Node "z80_|alu_control_|db[1]~24|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~25|datad" - Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~26|dataa" - Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~12|datab" - Warning (332126): Node "z80_|bus_control_|db[1]~12|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~13|dataa" - Warning (332126): Node "z80_|bus_control_|db[1]~13|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~25|dataa" - Warning (332126): Node "z80_|alu_|db[1]~15|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~24|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab" - Warning (332126): Node "z80_|alu_control_|db[2]~20|datac" - Warning (332126): Node "z80_|alu_control_|db[2]~20|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~22|datac" - Warning (332126): Node "z80_|alu_|db_low[3]~0|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~6|datab" - Warning (332126): Node "z80_|bus_control_|db[2]~10|datab" - Warning (332126): Node "z80_|bus_control_|db[2]~10|combout" - Warning (332126): Node "z80_|bus_control_|db[2]~11|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~21|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datab" -Critical Warning (332081): Design contains combinational loop of 514 nodes. Estimating the delays through the loop. + Warning (332126): Node "z80_|alu_|db_high[3]~6|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~21|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datab" + Warning (332126): Node "z80_|alu_|db[0]~18|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~15|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~22|datab" + Warning (332126): Node "z80_|bus_control_|db[0]~17|datab" + Warning (332126): Node "z80_|bus_control_|db[0]~17|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~8|datab" + Warning (332126): Node "z80_|alu_control_|db[0]~8|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~9|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|dataa" +Critical Warning (332081): Design contains combinational loop of 511 nodes. Estimating the delays through the loop. Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. @@ -23754,7 +23969,6 @@ Warning (15705): Ignored locations or region assignments to the following nodes Warning (15706): Node "EPCS_DCLK" is assigned to location or region, but does not exist in design Warning (15706): Node "EPCS_NCSO" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[10]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[3]" is assigned to location or region, but does not exist in design @@ -23786,26 +24000,27 @@ Warning (15705): Ignored locations or region assignments to the following nodes Warning (15706): Node "GPIO_2_IN[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "G_SENSOR_CS_N" is assigned to location or region, but does not exist in design Warning (15706): Node "G_SENSOR_INT" is assigned to location or region, but does not exist in design -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:04 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:03 Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:03 Info (170193): Fitter routing operations beginning +Info (170089): 7e+02 ns of routing delay (approximately 1.5% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report. Info (170195): Router estimated average interconnect usage is 4% of the available device resources - Info (170196): Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X43_Y11 to location X53_Y22 + Info (170196): Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22 Info (170194): Fitter routing operations ending: elapsed time is 00:00:06 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (11888): Total time spent on timing analysis during the Fitter is 2.36 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 1.92 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02 +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:03 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. -Warning (169177): 40 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. +Warning (169177): 41 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at M1 Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at M15 Info (169178): Pin GPIO_1[0] uses I/O standard 3.3-V LVTTL at F13 @@ -23840,17 +24055,18 @@ Warning (169177): 40 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5- Info (169178): Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1 Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at T8 Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at B9 + Info (169178): Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6 Info (169178): Pin KEY[0] uses I/O standard 3.3-V LVTTL at J15 Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8 - Info (169178): Pin KEY[1] uses I/O standard 3.3-V LVTTL at E1 Info (169178): Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7 + Info (169178): Pin KEY[1] uses I/O standard 3.3-V LVTTL at E1 Info (169178): Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6 Info (169178): Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8 Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg -Info: Quartus II 32-bit Fitter was successful. 0 errors, 613 warnings - Info: Peak virtual memory: 633 megabytes - Info: Processing ended: Thu Mar 31 14:04:12 2022 - Info: Elapsed time: 00:00:21 +Info: Quartus II 32-bit Fitter was successful. 0 errors, 609 warnings + Info: Peak virtual memory: 639 megabytes + Info: Processing ended: Fri Apr 1 18:55:40 2022 + Info: Elapsed time: 00:00:22 Info: Total CPU time (on all processors): 00:00:21 diff --git a/output_files/spectrum.fit.summary b/output_files/spectrum.fit.summary index f2e0e35..8b9bb67 100644 --- a/output_files/spectrum.fit.summary +++ b/output_files/spectrum.fit.summary @@ -1,15 +1,15 @@ -Fitter Status : Successful - Thu Mar 31 14:04:11 2022 +Fitter Status : Successful - Fri Apr 1 18:55:39 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E Device : EP4CE22F17C6 Timing Models : Final -Total logic elements : 2,383 / 22,320 ( 11 % ) - Total combinational functions : 2,265 / 22,320 ( 10 % ) +Total logic elements : 2,396 / 22,320 ( 11 % ) + Total combinational functions : 2,272 / 22,320 ( 10 % ) Dedicated logic registers : 591 / 22,320 ( 3 % ) Total registers : 600 -Total pins : 74 / 154 ( 48 % ) +Total pins : 75 / 154 ( 49 % ) Total virtual pins : 0 Total memory bits : 524,288 / 608,256 ( 86 % ) Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % ) diff --git a/output_files/spectrum.flow.rpt b/output_files/spectrum.flow.rpt index e8329ad..da73600 100644 --- a/output_files/spectrum.flow.rpt +++ b/output_files/spectrum.flow.rpt @@ -1,5 +1,5 @@ Flow report for spectrum -Thu Mar 31 14:04:25 2022 +Fri Apr 1 18:55:53 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -40,18 +40,18 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+--------------------------------------------+ -; Flow Status ; Successful - Thu Mar 31 14:04:25 2022 ; +; Flow Status ; Successful - Fri Apr 1 18:55:53 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 2,383 / 22,320 ( 11 % ) ; -; Total combinational functions ; 2,265 / 22,320 ( 10 % ) ; +; Total logic elements ; 2,396 / 22,320 ( 11 % ) ; +; Total combinational functions ; 2,272 / 22,320 ( 10 % ) ; ; Dedicated logic registers ; 591 / 22,320 ( 3 % ) ; ; Total registers ; 600 ; -; Total pins ; 74 / 154 ( 48 % ) ; +; Total pins ; 75 / 154 ( 49 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 524,288 / 608,256 ( 86 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; @@ -64,7 +64,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/31/2022 14:03:37 ; +; Start date & time ; 04/01/2022 18:55:04 ; ; Main task ; Compilation ; ; Revision Name ; spectrum ; +-------------------+---------------------+ @@ -74,7 +74,7 @@ applicable agreement for further details. ; Flow Non-Default Global Settings ; +--------------------------------------------------------------------------------+ Assignment Name : COMPILER_SIGNATURE_ID -Value : 0.164872461727117 +Value : 0.164882850457192 Default Value : -- Entity Name : -- Section Id : -- @@ -127,6 +127,12 @@ Default Value : -- Entity Name : -- Section Id : -- +Assignment Name : IP_TOOL_NAME +Value : RAM: 2-PORT +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : IP_TOOL_VERSION Value : 13.1 Default Value : -- @@ -163,6 +169,12 @@ Default Value : -- Entity Name : -- Section Id : -- +Assignment Name : IP_TOOL_VERSION +Value : 13.1 +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : MAX_CORE_JUNCTION_TEMP Value : 85 Default Value : -- @@ -223,6 +235,12 @@ Default Value : -- Entity Name : -- Section Id : -- +Assignment Name : MISC_FILE +Value : ram_video_bb.v +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE Value : 1.2V Default Value : -- @@ -262,38 +280,38 @@ Section Id : -- Module Name : Analysis & Synthesis Elapsed Time : 00:00:13 Average Processors Used : 1.0 -Peak Virtual Memory : 442 MB +Peak Virtual Memory : 441 MB Total CPU Time (on all processors) : 00:00:13 Module Name : Fitter -Elapsed Time : 00:00:20 +Elapsed Time : 00:00:21 Average Processors Used : 1.0 -Peak Virtual Memory : 633 MB -Total CPU Time (on all processors) : 00:00:20 +Peak Virtual Memory : 639 MB +Total CPU Time (on all processors) : 00:00:21 Module Name : Assembler -Elapsed Time : 00:00:01 +Elapsed Time : 00:00:02 Average Processors Used : 1.0 -Peak Virtual Memory : 375 MB +Peak Virtual Memory : 385 MB Total CPU Time (on all processors) : 00:00:02 Module Name : TimeQuest Timing Analyzer Elapsed Time : 00:00:04 Average Processors Used : 1.0 -Peak Virtual Memory : 451 MB -Total CPU Time (on all processors) : 00:00:03 +Peak Virtual Memory : 437 MB +Total CPU Time (on all processors) : 00:00:04 Module Name : EDA Netlist Writer Elapsed Time : 00:00:03 Average Processors Used : 1.0 -Peak Virtual Memory : 371 MB +Peak Virtual Memory : 372 MB Total CPU Time (on all processors) : 00:00:03 Module Name : Total -Elapsed Time : 00:00:41 +Elapsed Time : 00:00:43 Average Processors Used : -- Peak Virtual Memory : -- -Total CPU Time (on all processors) : 00:00:41 +Total CPU Time (on all processors) : 00:00:43 +--------------------------------------------------------------------------------+ diff --git a/output_files/spectrum.jdi b/output_files/spectrum.jdi index 8adcd94..72b6f13 100644 --- a/output_files/spectrum.jdi +++ b/output_files/spectrum.jdi @@ -1,6 +1,6 @@ - + diff --git a/output_files/spectrum.map.rpt b/output_files/spectrum.map.rpt index f452a7a..a963b5f 100644 --- a/output_files/spectrum.map.rpt +++ b/output_files/spectrum.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for spectrum -Thu Mar 31 14:03:50 2022 +Fri Apr 1 18:55:17 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -70,16 +70,16 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+--------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Thu Mar 31 14:03:50 2022 ; +; Analysis & Synthesis Status ; Successful - Fri Apr 1 18:55:17 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; -; Total logic elements ; 2,530 ; -; Total combinational functions ; 2,262 ; +; Total logic elements ; 2,537 ; +; Total combinational functions ; 2,269 ; ; Dedicated logic registers ; 592 ; ; Total registers ; 592 ; -; Total pins ; 74 ; +; Total pins ; 75 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 524,288 ; ; Embedded Multiplier 9-bit elements ; 0 ; @@ -935,32 +935,32 @@ Library : +---------------------------------------------+---------------------------------+ ; Resource ; Usage ; +---------------------------------------------+---------------------------------+ -; Estimated Total logic elements ; 2,530 ; +; Estimated Total logic elements ; 2,537 ; ; ; ; -; Total combinational functions ; 2262 ; +; Total combinational functions ; 2269 ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1645 ; -; -- 3 input functions ; 364 ; -; -- <=2 input functions ; 253 ; +; -- 4 input functions ; 1640 ; +; -- 3 input functions ; 385 ; +; -- <=2 input functions ; 244 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 2209 ; +; -- normal mode ; 2216 ; ; -- arithmetic mode ; 53 ; ; ; ; ; Total registers ; 592 ; ; -- Dedicated logic registers ; 592 ; ; -- I/O registers ; 0 ; ; ; ; -; I/O pins ; 74 ; +; I/O pins ; 75 ; ; Total memory bits ; 524288 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 1 ; ; -- PLLs ; 1 ; ; ; ; ; Maximum fan-out node ; ula:ula_|clocks:clocks_|clk_cpu ; -; Maximum fan-out ; 472 ; -; Total fan-out ; 11497 ; -; Average fan-out ; 3.75 ; +; Maximum fan-out ; 436 ; +; Total fan-out ; 11524 ; +; Average fan-out ; 3.74 ; +---------------------------------------------+---------------------------------+ @@ -968,13 +968,13 @@ Library : ; Analysis & Synthesis Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -LC Combinationals : 2262 (87) +LC Combinationals : 2269 (98) LC Registers : 592 (0) Memory Bits : 524288 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 -Pins : 74 +Pins : 75 Virtual Pins : 0 Full Hierarchy Name : |spectrum Library Name : work @@ -1028,7 +1028,7 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |ram32:ram1| -LC Combinationals : 24 (0) +LC Combinationals : 16 (0) LC Registers : 4 (0) Memory Bits : 262144 DSP Elements : 0 @@ -1040,7 +1040,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1 Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -LC Combinationals : 24 (0) +LC Combinationals : 16 (0) LC Registers : 4 (0) Memory Bits : 262144 DSP Elements : 0 @@ -1052,7 +1052,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated| -LC Combinationals : 24 (0) +LC Combinationals : 16 (0) LC Registers : 4 (4) Memory Bits : 262144 DSP Elements : 0 @@ -1088,7 +1088,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |mux_6nb:mux2| -LC Combinationals : 16 (16) +LC Combinationals : 8 (8) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1136,7 +1136,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component| Library Name : work Compilation Hierarchy Node : |ula:ula_| -LC Combinationals : 418 (4) +LC Combinationals : 420 (4) LC Registers : 224 (7) Memory Bits : 0 DSP Elements : 0 @@ -1244,7 +1244,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|video:video_ Library Name : work Compilation Hierarchy Node : |zx_keyboard:zx_keyboard_| -LC Combinationals : 148 (148) +LC Combinationals : 150 (150) LC Registers : 43 (43) Memory Bits : 0 DSP Elements : 0 @@ -1256,7 +1256,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_ Library Name : work Compilation Hierarchy Node : |z80_top_direct_n:z80_| -LC Combinationals : 1731 (2) +LC Combinationals : 1733 (2) LC Registers : 362 (1) Memory Bits : 0 DSP Elements : 0 @@ -1268,7 +1268,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_ Library Name : work Compilation Hierarchy Node : |address_latch:address_latch_| -LC Combinationals : 47 (16) +LC Combinationals : 48 (16) LC Registers : 16 (16) Memory Bits : 0 DSP Elements : 0 @@ -1280,7 +1280,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:addre Library Name : work Compilation Hierarchy Node : |inc_dec:b2v_inst_inc_dec| -LC Combinationals : 31 (14) +LC Combinationals : 32 (14) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1292,7 +1292,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:addre Library Name : work Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_0| -LC Combinationals : 3 (3) +LC Combinationals : 4 (4) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1376,7 +1376,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_pins:addres Library Name : work Compilation Hierarchy Node : |alu:alu_| -LC Combinationals : 130 (76) +LC Combinationals : 130 (77) LC Registers : 20 (20) Memory Bits : 0 DSP Elements : 0 @@ -1400,7 +1400,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_se Library Name : work Compilation Hierarchy Node : |alu_core:b2v_core| -LC Combinationals : 21 (0) +LC Combinationals : 20 (0) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1448,7 +1448,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b Library Name : work Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_3| -LC Combinationals : 6 (6) +LC Combinationals : 5 (5) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1544,7 +1544,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_con Library Name : work Compilation Hierarchy Node : |alu_flags:alu_flags_| -LC Combinationals : 62 (62) +LC Combinationals : 63 (63) LC Registers : 10 (10) Memory Bits : 0 DSP Elements : 0 @@ -1604,7 +1604,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_ Library Name : work Compilation Hierarchy Node : |data_switch_mask:sw1_| -LC Combinationals : 3 (3) +LC Combinationals : 2 (2) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1628,7 +1628,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|decode_state:decode Library Name : work Compilation Hierarchy Node : |execute:execute_| -LC Combinationals : 931 (931) +LC Combinationals : 933 (933) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1712,7 +1712,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_control:reg_con Library Name : work Compilation Hierarchy Node : |reg_file:reg_file_| -LC Combinationals : 283 (274) +LC Combinationals : 282 (273) LC Registers : 224 (0) Memory Bits : 0 DSP Elements : 0 @@ -1748,7 +1748,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_af_hi| -LC Combinationals : 6 (6) +LC Combinationals : 8 (8) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -1832,7 +1832,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_de2_lo| -LC Combinationals : 1 (1) +LC Combinationals : 0 (0) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -1868,7 +1868,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_hl2_hi| -LC Combinationals : 2 (2) +LC Combinationals : 0 (0) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -1880,7 +1880,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_hl2_lo| -LC Combinationals : 0 (0) +LC Combinationals : 1 (1) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -2290,7 +2290,7 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak +----------------------------------------------------------+---------+ ; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 4 ; ; ula:ula_|i2s_intf:i2s_intf_|bitcount[0] ; 2 ; -; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 136 ; +; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 138 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] ; 2 ; @@ -2300,7 +2300,6 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak ; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 6 ; ; ula:ula_|i2s_intf:i2s_intf_|bdivider[4] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|bdivider[2] ; 2 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 59 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][1] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][1] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][1] ; 2 ; @@ -2309,6 +2308,7 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] ; 2 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 59 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][2] ; 2 ; @@ -2331,16 +2331,16 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][3] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][3] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ; ; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 68 ; ; z80_top_direct_n:z80_|resets:resets_|x1 ; 2 ; ; z80_top_direct_n:z80_|fpga_reset ; 2 ; @@ -2378,7 +2378,7 @@ Baseline Area : 4 LEs Area if Restructured : 2 LEs Saving if Restructured : 2 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Multiplexer Inputs : 6:1 Bus Width : 5 bits @@ -2402,7 +2402,7 @@ Baseline Area : 42 LEs Area if Restructured : 14 LEs Saving if Restructured : 28 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] Multiplexer Inputs : 5:1 Bus Width : 3 bits @@ -2434,7 +2434,7 @@ Baseline Area : 10 LEs Area if Restructured : 4 LEs Saving if Restructured : 6 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Multiplexer Inputs : 10:1 Bus Width : 2 bits @@ -2458,7 +2458,7 @@ Baseline Area : 72 LEs Area if Restructured : 52 LEs Saving if Restructured : 20 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Multiplexer Inputs : 3:1 Bus Width : 16 bits @@ -2466,7 +2466,7 @@ Baseline Area : 32 LEs Area if Restructured : 32 LEs Saving if Restructured : 0 LEs Registered : Yes -Example Multiplexer Output : |spectrum|z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[6] +Example Multiplexer Output : |spectrum|z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[5] Multiplexer Inputs : 4:1 Bus Width : 3 bits @@ -2498,7 +2498,7 @@ Baseline Area : 8 LEs Area if Restructured : 6 LEs Saving if Restructured : 2 LEs Registered : No -Example Multiplexer Output : |spectrum|Mux0 +Example Multiplexer Output : |spectrum|Mux2 Multiplexer Inputs : 8:1 Bus Width : 6 bits @@ -2506,7 +2506,7 @@ Baseline Area : 30 LEs Area if Restructured : 24 LEs Saving if Restructured : 6 LEs Registered : No -Example Multiplexer Output : |spectrum|Selector1 +Example Multiplexer Output : |spectrum|Selector3 Multiplexer Inputs : 9:1 Bus Width : 2 bits @@ -2514,7 +2514,7 @@ Baseline Area : 12 LEs Area if Restructured : 6 LEs Saving if Restructured : 6 LEs Registered : No -Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|state.Ack +Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|state.Idle Multiplexer Inputs : 11:1 Bus Width : 2 bits @@ -3357,7 +3357,7 @@ Value : 7 Type : Signed Integer Parameter Name : CLK0_MULTIPLY_BY -Value : 72 +Value : 1007 Type : Signed Integer Parameter Name : CLK9_DIVIDE_BY @@ -3397,7 +3397,7 @@ Value : 25 Type : Signed Integer Parameter Name : CLK0_DIVIDE_BY -Value : 143 +Value : 2000 Type : Signed Integer Parameter Name : CLK9_PHASE_SHIFT @@ -4883,11 +4883,6 @@ Details : Connected to dangling logic. Logic that only feeds a dangling port wi +--------------------------------------------------------------------------------+ ; Port Connectivity Checks: "ula:ula_" ; +--------------------------------------------------------------------------------+ -Port : clk_vram -Type : Output -Severity : Info -Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed. - Port : pressed Type : Output Severity : Info @@ -4953,7 +4948,7 @@ Details : Input port expression (16 bits) is wider than the input port (14 bits Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Thu Mar 31 14:03:37 2022 + Info: Processing started: Fri Apr 1 18:55:04 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file spectrum.sv @@ -5064,8 +5059,10 @@ Info (12021): Found 1 design units, including 1 entities, in source file rom_scr Info (12023): Found entity 1: rom_scr Info (12021): Found 1 design units, including 1 entities, in source file pll_video.v Info (12023): Found entity 1: pll_video +Info (12021): Found 1 design units, including 1 entities, in source file ram_video.v + Info (12023): Found entity 1: ram_video Info (12127): Elaborating entity "spectrum" for the top level hierarchy -Warning (10034): Output port "LED[7..3]" at spectrum.sv(1) has no driver +Warning (10034): Output port "LED[7..4]" at spectrum.sv(1) has no driver Warning (10034): Output port "LED[1]" at spectrum.sv(1) has no driver Warning (10034): Output port "GPIO_1[33..32]" at spectrum.sv(20) has no driver Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom" @@ -5169,9 +5166,9 @@ Info (12128): Elaborating entity "altpll" for hierarchy "ula:ula_|pll:pll_|altpl Info (12130): Elaborated megafunction instantiation "ula:ula_|pll:pll_|altpll:altpll_component" Info (12133): Instantiated megafunction "ula:ula_|pll:pll_|altpll:altpll_component" with the following parameter: Info (12134): Parameter "bandwidth_type" = "AUTO" - Info (12134): Parameter "clk0_divide_by" = "143" + Info (12134): Parameter "clk0_divide_by" = "2000" Info (12134): Parameter "clk0_duty_cycle" = "50" - Info (12134): Parameter "clk0_multiply_by" = "72" + Info (12134): Parameter "clk0_multiply_by" = "1007" Info (12134): Parameter "clk0_phase_shift" = "0" Info (12134): Parameter "clk1_divide_by" = "25" Info (12134): Parameter "clk1_duty_cycle" = "50" @@ -5377,7 +5374,6 @@ Info (13000): Registers with preset signals will power-up high Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "LED[1]" is stuck at GND - Warning (13410): Pin "LED[3]" is stuck at GND Warning (13410): Pin "LED[4]" is stuck at GND Warning (13410): Pin "LED[5]" is stuck at GND Warning (13410): Pin "LED[6]" is stuck at GND @@ -5393,16 +5389,16 @@ Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Warning (21074): Design contains 2 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "SW[0]" Warning (15610): No output dependent on input pin "SW[3]" -Info (21057): Implemented 2739 device resources after synthesis - the final resource count might be different - Info (21058): Implemented 10 input pins +Info (21057): Implemented 2747 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 11 input pins Info (21059): Implemented 62 output pins Info (21060): Implemented 2 bidirectional pins - Info (21061): Implemented 2600 logic cells + Info (21061): Implemented 2607 logic cells Info (21064): Implemented 64 RAM segments Info (21065): Implemented 1 PLLs -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 111 warnings - Info: Peak virtual memory: 442 megabytes - Info: Processing ended: Thu Mar 31 14:03:50 2022 +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 110 warnings + Info: Peak virtual memory: 441 megabytes + Info: Processing ended: Fri Apr 1 18:55:17 2022 Info: Elapsed time: 00:00:13 Info: Total CPU time (on all processors): 00:00:13 diff --git a/output_files/spectrum.map.summary b/output_files/spectrum.map.summary index 7a5406f..24e537b 100644 --- a/output_files/spectrum.map.summary +++ b/output_files/spectrum.map.summary @@ -1,13 +1,13 @@ -Analysis & Synthesis Status : Successful - Thu Mar 31 14:03:50 2022 +Analysis & Synthesis Status : Successful - Fri Apr 1 18:55:17 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E -Total logic elements : 2,530 - Total combinational functions : 2,262 +Total logic elements : 2,537 + Total combinational functions : 2,269 Dedicated logic registers : 592 Total registers : 592 -Total pins : 74 +Total pins : 75 Total virtual pins : 0 Total memory bits : 524,288 Embedded Multiplier 9-bit elements : 0 diff --git a/output_files/spectrum.pin b/output_files/spectrum.pin index 8df130e..265825f 100644 --- a/output_files/spectrum.pin +++ b/output_files/spectrum.pin @@ -89,7 +89,7 @@ GND : B2 : gnd : : RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : +raw_loader_in : B6 : input : 3.3-V LVTTL : : 8 : Y PS2_DAT : B7 : input : 3.3-V LVTTL : : 8 : Y GND+ : B8 : : : : 8 : SW[2] : B9 : input : 3.3-V LVTTL : : 7 : Y diff --git a/output_files/spectrum.sof b/output_files/spectrum.sof index ea3cf6f..7a2f56c 100644 Binary files a/output_files/spectrum.sof and b/output_files/spectrum.sof differ diff --git a/output_files/spectrum.sta.rpt b/output_files/spectrum.sta.rpt index 7983c1a..a84d05a 100644 --- a/output_files/spectrum.sta.rpt +++ b/output_files/spectrum.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for spectrum -Thu Mar 31 14:04:20 2022 +Fri Apr 1 18:55:48 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -19,8 +19,8 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 11. Slow 1200mV 85C Model Removal Summary 12. Slow 1200mV 85C Model Minimum Pulse Width Summary 13. Slow 1200mV 85C Model Setup: 'CLOCK_50' - 14. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 15. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 14. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 15. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 16. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' 17. Slow 1200mV 85C Model Hold: 'CLOCK_50' 18. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' @@ -46,12 +46,12 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 38. Slow 1200mV 0C Model Removal Summary 39. Slow 1200mV 0C Model Minimum Pulse Width Summary 40. Slow 1200mV 0C Model Setup: 'CLOCK_50' - 41. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 42. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 41. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 42. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 43. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 44. Slow 1200mV 0C Model Hold: 'CLOCK_50' - 45. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 46. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 44. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 45. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 46. Slow 1200mV 0C Model Hold: 'CLOCK_50' 47. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' 48. Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 49. Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' @@ -72,9 +72,9 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 64. Fast 1200mV 0C Model Removal Summary 65. Fast 1200mV 0C Model Minimum Pulse Width Summary 66. Fast 1200mV 0C Model Setup: 'CLOCK_50' - 67. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 68. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 69. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 67. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 68. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 69. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' 70. Fast 1200mV 0C Model Hold: 'CLOCK_50' 71. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' 72. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' @@ -163,7 +163,7 @@ Parallel compilation was disabled, but you have multiple processors available. E +--------------------------------------------------------------------------------+ SDC File Path : spectrum.sdc Status : OK -Read at : Thu Mar 31 14:04:17 2022 +Read at : Fri Apr 1 18:55:45 2022 +--------------------------------------------------------------------------------+ @@ -267,18 +267,18 @@ Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[2] } +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 51.21 MHz -Restricted Fmax : 51.21 MHz +Fmax : 49.07 MHz +Restricted Fmax : 49.07 MHz Clock Name : CLOCK_50 Note : -Fmax : 133.4 MHz -Restricted Fmax : 133.4 MHz +Fmax : 124.66 MHz +Restricted Fmax : 124.66 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Note : -Fmax : 211.33 MHz -Restricted Fmax : 211.33 MHz +Fmax : 161.45 MHz +Restricted Fmax : 161.45 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Note : @@ -301,16 +301,16 @@ HTML report is unavailable in plain text report export. ; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -18.442 -End Point TNS : -343.502 - -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -4.732 -End Point TNS : -41.482 +Slack : -18.123 +End Point TNS : -549.338 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : -3.760 -End Point TNS : -51.393 +Slack : -7.533 +End Point TNS : -284.813 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : -4.740 +End Point TNS : -42.810 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Slack : -2.914 @@ -323,15 +323,15 @@ End Point TNS : -2.914 ; Slow 1200mV 85C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -0.980 -End Point TNS : -15.725 +Slack : 0.210 +End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Slack : 0.342 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 0.342 +Slack : 0.344 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -345,8 +345,8 @@ End Point TNS : 0.000 ; Slow 1200mV 85C Model Recovery Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -6.277 -End Point TNS : -463.435 +Slack : -6.223 +End Point TNS : -459.348 +--------------------------------------------------------------------------------+ @@ -355,7 +355,7 @@ End Point TNS : -463.435 ; Slow 1200mV 85C Model Removal Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 3.683 +Slack : 3.698 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -365,11 +365,11 @@ End Point TNS : 0.000 ; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 9.489 +Slack : 9.488 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : 19.600 +Slack : 19.602 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -386,1811 +386,905 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -18.442 +Slack : -18.123 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 7.954 + +Slack : -18.117 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 7.948 + +Slack : -18.075 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 7.905 + +Slack : -18.071 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 7.902 + +Slack : -18.067 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 7.897 + +Slack : -18.052 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 7.883 + +Slack : -18.038 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 7.868 + +Slack : -17.978 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 7.809 + +Slack : -17.977 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.248 +Data Delay : 7.803 + +Slack : -17.957 From Node : ula:ula_|video:video_|vga_hc[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.248 -Data Delay : 8.268 +Data Delay : 7.783 -Slack : -18.294 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.116 - -Slack : -18.256 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.078 - -Slack : -18.234 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 8.060 - -Slack : -18.232 +Slack : -17.929 From Node : ula:ula_|video:video_|vga_vc[6] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 8.058 +Clock Skew : -0.243 +Data Delay : 7.760 -Slack : -18.225 +Slack : -17.924 From Node : ula:ula_|video:video_|vga_vc[4] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 8.051 +Clock Skew : -0.243 +Data Delay : 7.755 -Slack : -18.204 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[0] +Slack : -17.912 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.247 -Data Delay : 8.031 +Clock Skew : -0.514 +Data Delay : 7.472 -Slack : -18.198 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[0] +Slack : -17.909 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 8.024 +Clock Skew : -0.509 +Data Delay : 7.474 -Slack : -18.181 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.246 -Data Delay : 8.009 - -Slack : -18.132 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.954 - -Slack : -18.109 -From Node : ula:ula_|video:video_|bits[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.247 -Data Delay : 7.936 - -Slack : -18.087 -From Node : ula:ula_|video:video_|bits[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.246 -Data Delay : 7.915 - -Slack : -18.068 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.890 - -Slack : -18.065 +Slack : -17.904 From Node : ula:ula_|video:video_|vga_vc[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.891 +Clock Skew : -0.243 +Data Delay : 7.735 -Slack : -18.040 +Slack : -17.882 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 7.712 + +Slack : -17.861 From Node : ula:ula_|video:video_|vga_vc[0] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.866 +Clock Skew : -0.243 +Data Delay : 7.692 -Slack : -18.018 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_B[0] +Slack : -17.852 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.840 +Clock Skew : -0.241 +Data Delay : 7.685 -Slack : -18.002 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[0] +Slack : -17.852 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.828 +Clock Skew : -0.242 +Data Delay : 7.684 -Slack : -17.962 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[0] +Slack : -17.810 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.788 +Clock Skew : -0.518 +Data Delay : 7.366 -Slack : -17.943 -From Node : ula:ula_|video:video_|bits[7] -To Node : VGA_B[0] +Slack : -17.798 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.247 -Data Delay : 7.770 +Clock Skew : -0.241 +Data Delay : 7.631 -Slack : -17.941 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.767 - -Slack : -17.937 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.759 - -Slack : -17.882 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.704 - -Slack : -17.849 +Slack : -17.790 From Node : ula:ula_|video:video_|vga_vc[5] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.249 -Data Delay : 7.674 +Clock Skew : -0.243 +Data Delay : 7.621 -Slack : -17.765 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[0] +Slack : -17.747 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.587 +Clock Skew : -0.524 +Data Delay : 7.297 -Slack : -17.758 +Slack : -17.716 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.266 + +Slack : -17.709 +From Node : ula:ula_|video:video_|bits[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.248 +Data Delay : 7.535 + +Slack : -17.708 From Node : ula:ula_|video:video_|vga_hc[9] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.580 +Clock Skew : -0.247 +Data Delay : 7.535 -Slack : -17.735 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[3] +Slack : -17.700 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.557 +Clock Skew : -0.241 +Data Delay : 7.533 -Slack : -17.720 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.542 - -Slack : -17.699 -From Node : ula:ula_|video:video_|bits[2] +Slack : -17.676 +From Node : ula:ula_|video:video_|vga_hc[8] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.247 -Data Delay : 7.526 - -Slack : -17.693 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.519 - -Slack : -17.663 -From Node : ula:ula_|video:video_|bits[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.247 -Data Delay : 7.490 +Clock Skew : -0.244 +Data Delay : 7.506 Slack : -17.657 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.483 - -Slack : -17.656 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.478 - -Slack : -17.640 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.462 - -Slack : -17.640 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.462 - -Slack : -17.633 -From Node : ula:ula_|video:video_|bits[4] +From Node : ula:ula_|video:video_|vga_hc[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.247 -Data Delay : 7.460 +Clock Skew : -0.244 +Data Delay : 7.487 -Slack : -17.606 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_R[1] +Slack : -17.622 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.428 +Clock Skew : -0.514 +Data Delay : 7.182 -Slack : -17.603 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.425 - -Slack : -17.576 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[0] +Slack : -17.617 +From Node : ula:ula_|video:video_|bits[6] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.248 -Data Delay : 7.402 +Data Delay : 7.443 -Slack : -17.573 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.395 - -Slack : -17.546 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.372 - -Slack : -17.540 +Slack : -17.612 From Node : ula:ula_|video:video_|frame[4] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.247 -Data Delay : 7.367 +Clock Skew : -0.249 +Data Delay : 7.437 -Slack : -17.540 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_R[0] +Slack : -17.578 +From Node : ula:ula_|video:video_|bits[7] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.248 -Data Delay : 7.366 +Data Delay : 7.404 -Slack : -17.539 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[0] +Slack : -17.576 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.361 +Clock Skew : -0.515 +Data Delay : 7.135 -Slack : -17.510 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_R[3] +Slack : -17.567 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.505 +Data Delay : 7.136 + +Slack : -17.554 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 7.113 + +Slack : -17.492 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.520 +Data Delay : 7.046 + +Slack : -17.483 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.041 + +Slack : -17.477 +From Node : ula:ula_|video:video_|bits[2] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.248 -Data Delay : 7.336 +Data Delay : 7.303 -Slack : -17.509 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[3] +Slack : -17.475 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.331 +Clock Skew : -0.518 +Data Delay : 7.031 -Slack : -17.499 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_R[1] +Slack : -17.460 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.241 +Data Delay : 7.293 + +Slack : -17.458 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.511 +Data Delay : 7.021 + +Slack : -17.448 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.241 +Data Delay : 7.281 + +Slack : -17.445 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.242 +Data Delay : 7.277 + +Slack : -17.442 +From Node : ula:ula_|video:video_|bits[3] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.248 -Data Delay : 7.325 +Data Delay : 7.268 -Slack : -17.489 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_R[0] +Slack : -17.441 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.311 +Clock Skew : -0.242 +Data Delay : 7.273 -Slack : -17.484 +Slack : -17.429 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.523 +Data Delay : 6.980 + +Slack : -17.425 From Node : ula:ula_|video:video_|attr[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.247 -Data Delay : 7.311 +Clock Skew : -0.248 +Data Delay : 7.251 -Slack : -17.478 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_G[2] +Slack : -17.393 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.300 +Clock Skew : -0.524 +Data Delay : 6.943 -Slack : -17.478 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_G[3] +Slack : -17.368 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.300 +Clock Skew : -0.524 +Data Delay : 6.918 -Slack : -17.459 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_R[3] +Slack : -17.351 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.281 +Clock Skew : -0.523 +Data Delay : 6.902 -Slack : -17.451 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_G[2] +Slack : -17.350 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.241 +Data Delay : 7.183 + +Slack : -17.328 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.511 +Data Delay : 6.891 + +Slack : -17.322 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.881 + +Slack : -17.316 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.507 +Data Delay : 6.883 + +Slack : -17.314 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.241 +Data Delay : 7.147 + +Slack : -17.300 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.850 + +Slack : -17.296 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.248 -Data Delay : 7.277 +Data Delay : 7.122 -Slack : -17.451 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_G[3] +Slack : -17.274 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.242 +Data Delay : 7.106 + +Slack : -17.267 +From Node : ula:ula_|video:video_|bits[4] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.248 -Data Delay : 7.277 +Data Delay : 7.093 -Slack : -17.448 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_G[1] +Slack : -17.247 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.270 +Clock Skew : -0.513 +Data Delay : 6.808 -Slack : -17.424 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_G[0] +Slack : -17.239 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.246 +Clock Skew : -0.242 +Data Delay : 7.071 -Slack : -17.423 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_R[1] +Slack : -17.229 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.245 +Clock Skew : -0.241 +Data Delay : 7.062 -Slack : -17.415 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_G[2] +Slack : -17.199 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.241 +Clock Skew : -0.522 +Data Delay : 6.751 -Slack : -17.415 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_G[3] +Slack : -17.188 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.241 +Clock Skew : -0.507 +Data Delay : 6.755 -Slack : -17.414 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_G[2] +Slack : -17.162 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.236 +Clock Skew : -0.516 +Data Delay : 6.720 -Slack : -17.414 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.236 - -Slack : -17.400 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.226 - -Slack : -17.382 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.208 - -Slack : -17.364 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.186 - -Slack : -17.364 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.186 - -Slack : -17.362 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.188 - -Slack : -17.352 +Slack : -17.128 From Node : ula:ula_|video:video_|bits[0] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.247 -Data Delay : 7.179 - -Slack : -17.352 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 Clock Skew : -0.248 -Data Delay : 7.178 - -Slack : -17.346 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.168 - -Slack : -17.306 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.128 - -Slack : -17.286 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_G[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.108 - -Slack : -17.283 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.109 - -Slack : -17.276 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.098 - -Slack : -17.262 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_G[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.084 - -Slack : -17.257 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.083 - -Slack : -17.257 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.083 - -Slack : -17.253 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.079 - -Slack : -17.245 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.071 - -Slack : -17.235 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_G[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.061 - -Slack : -17.234 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.249 -Data Delay : 7.059 - -Slack : -17.229 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.051 - -Slack : -17.226 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.052 - -Slack : -17.225 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_G[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.051 - -Slack : -17.222 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_G[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.044 - -Slack : -17.215 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.041 - -Slack : -17.199 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.021 - -Slack : -17.199 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_G[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.025 - -Slack : -17.198 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_G[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.020 - -Slack : -17.189 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_G[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.015 - -Slack : -17.181 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.003 - -Slack : -17.181 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.003 - -Slack : -17.172 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_G[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 6.994 - -Slack : -17.169 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.995 - -Slack : -17.158 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.984 - -Slack : -17.158 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.984 - -Slack : -17.148 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_G[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 6.970 +Data Delay : 6.954 Slack : -17.120 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_G[2] +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.946 +Clock Skew : -0.514 +Data Delay : 6.680 -Slack : -17.120 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_G[3] +Slack : -17.110 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.946 - -Slack : -17.117 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.249 +Clock Skew : -0.242 Data Delay : 6.942 -Slack : -17.107 +Slack : -17.095 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.519 +Data Delay : 6.650 + +Slack : -17.083 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 6.635 + +Slack : -17.035 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.509 +Data Delay : 6.600 + +Slack : -16.837 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.520 +Data Delay : 6.391 + +Slack : -16.833 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 6.394 + +Slack : -16.800 +From Node : ula:ula_|video:video_|attr[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.247 +Data Delay : 6.627 + +Slack : -16.774 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.242 +Data Delay : 6.606 + +Slack : -16.762 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 6.593 + +Slack : -16.756 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 6.587 + +Slack : -16.714 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 6.544 + +Slack : -16.710 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 6.541 + +Slack : -16.706 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 6.536 + +Slack : -16.702 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.260 + +Slack : -16.691 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 6.522 + +Slack : -16.677 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 6.507 + +Slack : -16.617 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 6.448 + +Slack : -16.616 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.248 +Data Delay : 6.442 + +Slack : -16.596 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.248 +Data Delay : 6.422 + +Slack : -16.590 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 6.421 + +Slack : -16.589 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 6.420 + +Slack : -16.568 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 6.399 + +Slack : -16.567 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 6.397 + +Slack : -16.563 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 6.394 + +Slack : -16.549 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 6.379 + +Slack : -16.543 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 6.374 + +Slack : -16.523 From Node : ula:ula_|video:video_|vga_vc[9] To Node : VGA_R[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.933 +Clock Skew : -0.243 +Data Delay : 6.354 -Slack : -17.104 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_G[2] +Slack : -16.521 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 6.926 -+--------------------------------------------------------------------------------+ - - - -+--------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; -+--------------------------------------------------------------------------------+ -Slack : -4.732 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.193 -Data Delay : 2.823 - -Slack : -4.716 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.934 - -Slack : -4.716 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.934 - -Slack : -4.121 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 2.690 - -Slack : -4.121 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 2.690 - -Slack : -4.121 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 2.690 - -Slack : -4.121 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 2.690 - -Slack : -4.121 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 2.690 - -Slack : -3.559 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.228 -Data Delay : 2.166 - -Slack : -3.154 -From Node : AUD_ADCDAT -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.162 -Data Delay : 1.695 - -Slack : 17.103 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.313 - -Slack : 17.103 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.313 - -Slack : 17.103 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.313 - -Slack : 17.103 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.313 - -Slack : 17.103 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.313 - -Slack : 17.108 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.308 - -Slack : 17.108 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.308 - -Slack : 17.108 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.308 - -Slack : 17.108 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.308 - -Slack : 17.108 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.308 - -Slack : 17.173 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.243 - -Slack : 17.173 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.243 - -Slack : 17.178 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.238 - -Slack : 17.178 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.238 - -Slack : 17.251 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.165 - -Slack : 17.251 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.165 - -Slack : 17.251 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.165 - -Slack : 17.251 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.165 - -Slack : 17.251 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.165 - -Slack : 17.299 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.117 - -Slack : 17.304 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.112 - -Slack : 17.321 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.095 - -Slack : 17.321 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.095 - -Slack : 17.347 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.069 - -Slack : 17.347 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.069 - -Slack : 17.347 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.069 - -Slack : 17.347 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.069 - -Slack : 17.347 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.069 - -Slack : 17.377 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.400 - -Slack : 17.377 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.400 - -Slack : 17.377 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.400 - -Slack : 17.380 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.036 - -Slack : 17.380 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.036 - -Slack : 17.380 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.036 - -Slack : 17.380 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.036 - -Slack : 17.380 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.036 - -Slack : 17.382 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.395 - -Slack : 17.382 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.395 - -Slack : 17.382 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.395 - -Slack : 17.398 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.018 - -Slack : 17.398 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.018 - -Slack : 17.403 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.013 - -Slack : 17.403 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.013 - -Slack : 17.417 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.999 - -Slack : 17.417 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.999 - -Slack : 17.447 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.969 - -Slack : 17.450 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.966 - -Slack : 17.450 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.966 - -Slack : 17.525 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.252 - -Slack : 17.525 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.252 - -Slack : 17.525 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.252 - -Slack : 17.543 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.873 - -Slack : 17.546 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.870 - -Slack : 17.546 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.870 - -Slack : 17.555 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.861 - -Slack : 17.555 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.861 - -Slack : 17.555 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.861 - -Slack : 17.555 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.861 - -Slack : 17.555 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.861 - -Slack : 17.576 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.840 - -Slack : 17.621 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.156 - -Slack : 17.621 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.156 - -Slack : 17.621 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.156 - -Slack : 17.625 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.791 - -Slack : 17.625 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.791 - -Slack : 17.642 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.774 - -Slack : 17.642 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.774 - -Slack : 17.654 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.123 - -Slack : 17.654 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.123 - -Slack : 17.654 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 3.123 - -Slack : 17.675 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.741 - -Slack : 17.675 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.741 - -Slack : 17.751 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.665 - -Slack : 17.767 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.000 - -Slack : 17.767 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.000 - -Slack : 17.767 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.000 - -Slack : 17.767 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.000 - -Slack : 17.767 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.000 - -Slack : 17.772 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 2.995 - -Slack : 17.772 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 2.995 - -Slack : 17.772 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 2.995 - -Slack : 17.772 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 2.995 - -Slack : 17.772 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 2.995 - -Slack : 17.829 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 2.948 - -Slack : 17.829 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 2.948 - -Slack : 17.829 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.069 -Data Delay : 2.948 - -Slack : 17.850 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.566 - -Slack : 17.850 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.566 - -Slack : 17.915 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 2.852 - -Slack : 17.915 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 2.852 +Clock Skew : -0.244 +Data Delay : 6.351 + +Slack : -16.500 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 6.331 + +Slack : -16.495 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.243 +Data Delay : 6.326 + +Slack : -16.484 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_G[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 6.314 + +Slack : -16.460 +From Node : ula:ula_|video:video_|attr[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.248 +Data Delay : 6.286 +--------------------------------------------------------------------------------+ @@ -2198,905 +1292,1811 @@ Data Delay : 2.852 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : -3.760 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[3] +Slack : -7.533 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.570 -Data Delay : 1.265 +Clock Skew : -2.293 +Data Delay : 5.348 -Slack : -3.727 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[3] +Slack : -7.427 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.284 +Data Delay : 5.251 + +Slack : -7.365 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.290 +Data Delay : 5.183 + +Slack : -7.307 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.284 +Data Delay : 5.131 + +Slack : -7.245 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.245 +Data Delay : 5.108 + +Slack : -7.233 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.307 +Data Delay : 5.034 + +Slack : -7.228 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.251 +Data Delay : 5.085 + +Slack : -7.218 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.284 +Data Delay : 5.042 + +Slack : -7.217 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.283 +Data Delay : 5.042 + +Slack : -7.215 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.263 +Data Delay : 5.060 + +Slack : -7.206 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.299 +Data Delay : 5.015 + +Slack : -7.130 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.245 +Data Delay : 4.993 + +Slack : -7.122 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.282 +Data Delay : 4.948 + +Slack : -7.122 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.242 +Data Delay : 4.988 + +Slack : -7.092 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.244 +Data Delay : 4.956 + +Slack : -7.063 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.292 +Data Delay : 4.879 + +Slack : -7.057 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.297 +Data Delay : 4.868 + +Slack : -7.054 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.299 +Data Delay : 4.863 + +Slack : -7.052 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.257 +Data Delay : 4.903 + +Slack : -7.042 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.299 +Data Delay : 4.851 + +Slack : -7.025 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.249 +Data Delay : 4.884 + +Slack : -7.023 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.283 +Data Delay : 4.848 + +Slack : -7.020 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.262 +Data Delay : 4.866 + +Slack : -7.020 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.281 +Data Delay : 4.847 + +Slack : -7.017 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.260 +Data Delay : 4.865 + +Slack : -7.009 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.285 +Data Delay : 4.832 + +Slack : -7.002 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.242 +Data Delay : 4.868 + +Slack : -6.982 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.295 +Data Delay : 4.795 + +Slack : -6.955 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.287 +Data Delay : 4.776 + +Slack : -6.943 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.009 +Data Delay : 5.042 + +Slack : -6.934 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.788 + +Slack : -6.930 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.283 +Data Delay : 4.755 + +Slack : -6.927 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.274 +Data Delay : 4.761 + +Slack : -6.927 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.276 +Data Delay : 4.759 + +Slack : -6.914 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.283 +Data Delay : 4.739 + +Slack : -6.912 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.241 +Data Delay : 4.779 + +Slack : -6.876 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.247 +Data Delay : 4.737 + +Slack : -6.862 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.245 +Data Delay : 4.725 + +Slack : -6.861 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.249 +Data Delay : 4.720 + +Slack : -6.857 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.260 +Data Delay : 4.705 + +Slack : -6.837 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.000 +Data Delay : 4.945 + +Slack : -6.836 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.267 +Data Delay : 4.677 + +Slack : -6.834 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.289 +Data Delay : 4.653 + +Slack : -6.811 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.291 +Data Delay : 4.628 + +Slack : -6.810 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.271 +Data Delay : 4.647 + +Slack : -6.806 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.285 +Data Delay : 4.629 + +Slack : -6.804 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.240 +Data Delay : 4.672 + +Slack : -6.798 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.253 +Data Delay : 4.653 + +Slack : -6.792 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.241 +Data Delay : 4.659 + +Slack : -6.791 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.287 +Data Delay : 4.612 + +Slack : -6.789 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.232 +Data Delay : 4.665 + +Slack : -6.789 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.234 +Data Delay : 4.663 + +Slack : -6.781 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.253 +Data Delay : 4.636 + +Slack : -6.770 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.269 +Data Delay : 4.609 + +Slack : -6.768 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.275 +Data Delay : 4.601 + +Slack : -6.765 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.619 + +Slack : -6.761 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.286 +Data Delay : 4.583 + +Slack : -6.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 4.571 + +Slack : -6.756 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.999 +Data Delay : 4.865 + +Slack : -6.751 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.271 +Data Delay : 4.588 + +Slack : -6.748 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.257 +Data Delay : 4.599 + +Slack : -6.745 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.248 +Data Delay : 4.605 + +Slack : -6.745 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -2.250 -Data Delay : 1.552 +Data Delay : 4.603 -Slack : -3.311 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[5] +Slack : -6.741 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.238 -Data Delay : 1.148 +Clock Skew : -2.285 +Data Delay : 4.564 -Slack : -3.310 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[4] +Slack : -6.739 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.212 -Data Delay : 1.173 +Clock Skew : -2.012 +Data Delay : 4.835 -Slack : -3.288 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[6] +Slack : -6.737 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.238 -Data Delay : 1.125 +Clock Skew : -2.292 +Data Delay : 4.553 -Slack : -3.283 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[5] +Slack : -6.727 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.210 -Data Delay : 1.148 +Clock Skew : -2.292 +Data Delay : 4.543 -Slack : -3.282 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[4] +Slack : -6.720 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.184 -Data Delay : 1.173 +Clock Skew : -2.281 +Data Delay : 4.547 -Slack : -3.262 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[6] +Slack : -6.717 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.210 -Data Delay : 1.127 +Clock Skew : -2.000 +Data Delay : 4.825 -Slack : -3.036 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[0] +Slack : -6.714 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.242 -Data Delay : 0.869 +Clock Skew : -2.244 +Data Delay : 4.578 -Slack : -3.036 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[1] +Slack : -6.714 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.242 -Data Delay : 0.869 +Clock Skew : -2.297 +Data Delay : 4.525 -Slack : -3.034 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[7] +Slack : -6.693 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.241 -Data Delay : 0.868 +Clock Skew : -2.009 +Data Delay : 4.792 -Slack : -3.033 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[2] +Slack : -6.692 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.241 -Data Delay : 0.867 +Clock Skew : -2.244 +Data Delay : 4.556 -Slack : -3.009 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[2] +Slack : -6.689 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.213 -Data Delay : 0.871 +Clock Skew : -2.239 +Data Delay : 4.558 -Slack : -3.008 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[0] +Slack : -6.683 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.214 -Data Delay : 0.869 +Clock Skew : -2.280 +Data Delay : 4.511 -Slack : -3.008 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[1] +Slack : -6.681 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.214 -Data Delay : 0.869 +Clock Skew : -2.302 +Data Delay : 4.487 -Slack : -3.006 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[7] +Slack : -6.678 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.213 -Data Delay : 0.868 +Clock Skew : -2.293 +Data Delay : 4.493 -Slack : 34.984 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.678 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.067 -Data Delay : 4.563 +Relationship : 0.120 +Clock Skew : -2.295 +Data Delay : 4.491 -Slack : 34.992 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.674 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.070 -Data Delay : 4.552 +Relationship : 0.120 +Clock Skew : -2.295 +Data Delay : 4.487 -Slack : 35.018 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.658 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.067 -Data Delay : 4.529 +Relationship : 0.120 +Clock Skew : -2.261 +Data Delay : 4.505 -Slack : 35.027 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.655 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.070 -Data Delay : 4.517 +Relationship : 0.120 +Clock Skew : -2.297 +Data Delay : 4.466 -Slack : 35.073 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.646 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 4.576 - -Slack : 35.073 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.070 +Relationship : 0.120 +Clock Skew : -2.283 Data Delay : 4.471 -Slack : 35.128 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.641 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.067 -Data Delay : 4.419 +Relationship : 0.120 +Clock Skew : -2.266 +Data Delay : 4.483 -Slack : 35.134 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.638 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.064 -Data Delay : 4.416 - -Slack : 35.150 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 4.499 - -Slack : 35.215 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.268 -Data Delay : 4.764 - -Slack : 35.292 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 4.357 - -Slack : 35.355 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 4.294 - -Slack : 35.386 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.067 -Data Delay : 4.161 - -Slack : 35.389 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.263 -Data Delay : 4.585 - -Slack : 35.406 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.070 -Data Delay : 4.138 - -Slack : 35.416 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.056 -Data Delay : 4.239 - -Slack : 35.424 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.067 -Data Delay : 4.123 - -Slack : 35.430 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 4.218 - -Slack : 35.443 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.070 -Data Delay : 4.101 - -Slack : 35.489 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.264 -Data Delay : 4.486 - -Slack : 35.499 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.058 -Data Delay : 4.154 - -Slack : 35.508 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 4.141 - -Slack : 35.520 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.291 +Relationship : 0.120 +Clock Skew : -2.264 Data Delay : 4.482 -Slack : 35.530 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.629 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.070 -Data Delay : 4.014 +Relationship : 0.120 +Clock Skew : -2.280 +Data Delay : 4.457 -Slack : 35.548 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.629 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 4.101 +Relationship : 0.120 +Clock Skew : -2.264 +Data Delay : 4.473 -Slack : 35.563 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.627 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.291 -Data Delay : 4.439 +Relationship : 0.120 +Clock Skew : -1.999 +Data Delay : 4.736 -Slack : 35.564 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.620 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.285 -Data Delay : 4.432 +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 4.485 -Slack : 35.580 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.614 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.286 -Data Delay : 4.417 +Relationship : 0.120 +Clock Skew : -2.272 +Data Delay : 4.450 -Slack : 35.587 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|frame[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.604 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 4.062 +Relationship : 0.120 +Clock Skew : -2.279 +Data Delay : 4.433 -Slack : 35.596 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.602 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.270 -Data Delay : 4.385 +Relationship : 0.120 +Clock Skew : -2.256 +Data Delay : 4.454 -Slack : 35.597 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.591 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 4.052 +Relationship : 0.120 +Clock Skew : -2.281 +Data Delay : 4.418 -Slack : 35.627 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.588 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.059 -Data Delay : 4.025 +Relationship : 0.120 +Clock Skew : -2.278 +Data Delay : 4.418 -Slack : 35.645 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.573 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 4.003 +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.427 -Slack : 35.655 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.572 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.067 -Data Delay : 3.892 +Relationship : 0.120 +Clock Skew : -2.244 +Data Delay : 4.436 -Slack : 35.657 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.561 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.067 -Data Delay : 3.890 +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 4.426 -Slack : 35.666 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.546 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.066 -Data Delay : 3.882 +Relationship : 0.120 +Clock Skew : -2.292 +Data Delay : 4.362 -Slack : 35.666 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.533 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.259 -Data Delay : 4.304 +Relationship : 0.120 +Clock Skew : -2.252 +Data Delay : 4.389 -Slack : 35.700 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.514 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.067 -Data Delay : 3.847 +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 4.379 -Slack : 35.707 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|attr_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.514 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.258 -Data Delay : 4.262 +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.368 ++--------------------------------------------------------------------------------+ -Slack : 35.712 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.937 -Slack : 35.734 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 3.914 -Slack : 35.777 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.872 ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : -4.740 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.193 +Data Delay : 2.831 -Slack : 35.788 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|frame[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.861 +Slack : -4.581 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 2.799 -Slack : 35.796 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.265 -Data Delay : 4.180 +Slack : -4.581 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 2.799 -Slack : 35.802 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.286 -Data Delay : 4.195 +Slack : -4.362 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 2.580 -Slack : 35.802 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.287 -Data Delay : 4.196 +Slack : -4.362 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 2.580 -Slack : 35.810 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.839 +Slack : -4.362 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 2.580 -Slack : 35.822 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.067 -Data Delay : 3.725 +Slack : -4.362 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 2.580 -Slack : 35.829 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.820 +Slack : -4.362 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 2.580 -Slack : 35.838 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.811 +Slack : -3.957 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 2.175 -Slack : 35.845 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.804 +Slack : -3.141 +From Node : AUD_ADCDAT +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.170 +Data Delay : 1.690 -Slack : 35.847 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.287 -Data Delay : 4.151 +Slack : 16.840 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.577 -Slack : 35.849 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.281 -Data Delay : 4.143 +Slack : 16.845 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.572 -Slack : 35.854 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.795 +Slack : 16.978 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.439 -Slack : 35.855 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.794 +Slack : 16.978 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.439 -Slack : 35.857 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.070 -Data Delay : 3.687 +Slack : 16.983 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.434 -Slack : 35.871 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.056 -Data Delay : 3.784 +Slack : 16.983 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.434 -Slack : 35.876 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.064 -Data Delay : 3.771 +Slack : 16.986 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.431 -Slack : 35.876 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.064 -Data Delay : 3.771 +Slack : 17.051 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.366 -Slack : 35.877 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|frame[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.772 +Slack : 17.051 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.366 -Slack : 35.907 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.282 -Data Delay : 4.086 +Slack : 17.051 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.366 -Slack : 35.909 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.293 -Data Delay : 4.095 +Slack : 17.051 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.366 -Slack : 35.931 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.067 -Data Delay : 3.616 +Slack : 17.056 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.361 -Slack : 35.939 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|attr_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.258 -Data Delay : 4.030 +Slack : 17.056 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.361 -Slack : 35.947 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.702 +Slack : 17.056 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.361 -Slack : 35.947 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.066 -Data Delay : 3.698 +Slack : 17.056 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.361 -Slack : 35.949 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.700 +Slack : 17.086 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.331 -Slack : 35.949 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.700 +Slack : 17.117 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.300 -Slack : 35.953 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.696 +Slack : 17.117 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.300 -Slack : 35.954 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.695 +Slack : 17.140 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.277 -Slack : 35.954 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.293 -Data Delay : 4.050 +Slack : 17.140 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.277 -Slack : 35.955 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.694 +Slack : 17.145 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.272 -Slack : 35.955 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.694 +Slack : 17.145 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.272 -Slack : 35.955 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.694 +Slack : 17.159 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.256 -Slack : 35.955 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.694 +Slack : 17.159 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.256 -Slack : 35.956 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.287 -Data Delay : 4.042 +Slack : 17.164 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.251 -Slack : 35.964 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.685 +Slack : 17.164 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.251 -Slack : 35.976 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 3.672 +Slack : 17.189 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.228 -Slack : 35.983 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 3.665 +Slack : 17.189 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.228 -Slack : 35.984 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|attr_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.254 -Data Delay : 3.981 +Slack : 17.189 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.228 -Slack : 35.992 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 3.656 +Slack : 17.189 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.228 -Slack : 35.993 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_hc[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.066 -Data Delay : 3.652 +Slack : 17.224 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.193 -Slack : 36.005 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.644 +Slack : 17.224 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.193 -Slack : 36.012 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.059 -Data Delay : 3.640 +Slack : 17.256 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.161 + +Slack : 17.259 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.158 + +Slack : 17.259 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.158 + +Slack : 17.259 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.158 + +Slack : 17.259 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.158 + +Slack : 17.259 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.158 + +Slack : 17.264 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.153 + +Slack : 17.264 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.153 + +Slack : 17.264 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.153 + +Slack : 17.264 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.153 + +Slack : 17.264 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.153 + +Slack : 17.289 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.128 + +Slack : 17.289 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.128 + +Slack : 17.297 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.120 + +Slack : 17.297 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.120 + +Slack : 17.297 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.120 + +Slack : 17.297 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.120 + +Slack : 17.308 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.107 + +Slack : 17.308 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.107 + +Slack : 17.386 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.031 + +Slack : 17.386 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.031 + +Slack : 17.394 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.023 + +Slack : 17.394 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.023 + +Slack : 17.405 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.010 + +Slack : 17.405 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.010 + +Slack : 17.408 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.009 + +Slack : 17.408 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.009 + +Slack : 17.408 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.009 + +Slack : 17.408 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.009 + +Slack : 17.408 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.009 + +Slack : 17.432 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.983 + +Slack : 17.437 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.978 + +Slack : 17.467 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.950 + +Slack : 17.467 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.950 + +Slack : 17.467 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.950 + +Slack : 17.467 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.950 + +Slack : 17.501 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.916 + +Slack : 17.505 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.912 + +Slack : 17.505 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.912 + +Slack : 17.505 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.912 + +Slack : 17.505 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.912 + +Slack : 17.505 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.912 + +Slack : 17.556 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.861 + +Slack : 17.556 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.861 + +Slack : 17.563 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.076 +Data Delay : 3.207 + +Slack : 17.568 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.076 +Data Delay : 3.202 + +Slack : 17.575 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.840 + +Slack : 17.575 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.840 + +Slack : 17.581 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.834 + +Slack : 17.639 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.778 + +Slack : 17.639 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.778 + +Slack : 17.675 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.742 + +Slack : 17.675 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.742 + +Slack : 17.675 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.742 + +Slack : 17.675 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.742 + +Slack : 17.675 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.742 + +Slack : 17.678 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.737 + +Slack : 17.710 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.076 +Data Delay : 3.060 +--------------------------------------------------------------------------------+ @@ -3146,905 +3146,905 @@ Data Delay : 0.659 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -0.980 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Slack : 0.210 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.572 -Data Delay : 1.883 +Clock Skew : 2.627 +Data Delay : 3.128 -Slack : -0.979 +Slack : 0.266 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.628 +Data Delay : 3.185 + +Slack : 1.266 From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.570 -Data Delay : 1.882 - -Slack : -0.965 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.576 -Data Delay : 1.902 - -Slack : -0.947 -From Node : ula:ula_|video:video_|vram_address[5] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 1.905 +Clock Skew : 2.574 +Data Delay : 4.131 -Slack : -0.942 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.915 - -Slack : -0.940 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 1.915 - -Slack : -0.940 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 1.916 - -Slack : -0.939 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.576 -Data Delay : 1.928 - -Slack : -0.935 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.559 -Data Delay : 1.915 - -Slack : -0.927 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.930 - -Slack : -0.927 +Slack : 1.277 From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.930 - -Slack : -0.924 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 1.930 - -Slack : -0.922 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.935 - -Slack : -0.920 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 1.932 - -Slack : -0.919 -From Node : ula:ula_|video:video_|vram_address[6] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 1.936 - -Slack : -0.916 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 1.938 - -Slack : -0.909 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.572 -Data Delay : 1.954 - -Slack : -0.907 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.950 - -Slack : -0.903 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 1.953 - -Slack : -0.903 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.576 -Data Delay : 1.964 - -Slack : -0.902 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.955 - -Slack : -0.900 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 1.956 - -Slack : -0.899 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 Clock Skew : 2.575 -Data Delay : 1.967 +Data Delay : 4.143 -Slack : -0.898 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Slack : 1.289 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 1.957 +Clock Skew : 2.571 +Data Delay : 4.151 -Slack : -0.898 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Slack : 1.310 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.163 + +Slack : 1.311 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.164 + +Slack : 1.311 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.574 +Data Delay : 4.176 + +Slack : 1.313 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.162 + +Slack : 1.318 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.565 +Data Delay : 4.174 + +Slack : 1.328 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 2.575 -Data Delay : 1.968 +Data Delay : 4.194 -Slack : -0.897 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.960 - -Slack : -0.894 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.576 -Data Delay : 1.973 - -Slack : -0.891 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 1.963 - -Slack : -0.891 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.570 -Data Delay : 1.970 - -Slack : -0.890 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.559 -Data Delay : 1.960 - -Slack : -0.889 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 1.966 - -Slack : -0.889 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.968 - -Slack : -0.889 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 1.963 - -Slack : -0.888 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.576 -Data Delay : 1.979 - -Slack : -0.888 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.576 -Data Delay : 1.979 - -Slack : -0.887 +Slack : 1.332 From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 1.968 - -Slack : -0.886 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 1.966 - -Slack : -0.885 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 1.970 - -Slack : -0.885 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.972 - -Slack : -0.883 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.576 -Data Delay : 1.984 - -Slack : -0.883 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.570 -Data Delay : 1.978 - -Slack : -0.879 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 1.977 - -Slack : -0.878 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.979 - -Slack : -0.878 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 1.976 - -Slack : -0.878 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 1.978 - -Slack : -0.878 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.979 - -Slack : -0.876 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 1.978 - -Slack : -0.874 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 1.981 - -Slack : -0.873 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 1.981 - -Slack : -0.873 -From Node : ula:ula_|video:video_|vram_address[5] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.984 +Clock Skew : 2.562 +Data Delay : 4.185 -Slack : -0.872 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Slack : 1.333 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.567 -Data Delay : 1.986 +Clock Skew : 2.565 +Data Delay : 4.189 -Slack : -0.871 -From Node : ula:ula_|video:video_|vram_address[7] +Slack : 1.370 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.565 +Data Delay : 4.226 + +Slack : 1.390 +From Node : ula:ula_|video:video_|vram_address[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.986 - -Slack : -0.869 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.988 - -Slack : -0.869 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.988 - -Slack : -0.868 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.570 -Data Delay : 1.993 - -Slack : -0.868 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.576 -Data Delay : 1.999 - -Slack : -0.866 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 1.988 - -Slack : -0.866 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 1.986 - -Slack : -0.865 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 1.989 - -Slack : -0.864 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.559 -Data Delay : 1.986 - -Slack : -0.860 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 1.995 - -Slack : -0.860 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 1.997 - -Slack : -0.859 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 1.995 - -Slack : -0.859 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 1.993 - -Slack : -0.858 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 1.996 - -Slack : -0.858 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 1.996 - -Slack : -0.857 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.000 - -Slack : -0.857 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 Clock Skew : 2.560 -Data Delay : 1.994 +Data Delay : 4.241 -Slack : -0.857 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.000 - -Slack : -0.856 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 2.000 - -Slack : -0.856 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.001 - -Slack : -0.856 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.001 - -Slack : -0.855 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.575 -Data Delay : 2.011 - -Slack : -0.855 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.002 - -Slack : -0.852 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.572 -Data Delay : 2.011 - -Slack : -0.852 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.005 - -Slack : -0.851 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.006 - -Slack : -0.850 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.007 - -Slack : -0.848 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 2.007 - -Slack : -0.847 -From Node : ula:ula_|video:video_|vram_address[2] +Slack : 1.397 +From Node : ula:ula_|video:video_|vram_address[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.559 -Data Delay : 2.003 +Clock Skew : 2.557 +Data Delay : 4.245 -Slack : -0.846 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Slack : 1.404 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 2.010 +Clock Skew : 2.567 +Data Delay : 4.262 -Slack : -0.846 -From Node : ula:ula_|video:video_|vram_address[4] +Slack : 1.406 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 4.251 + +Slack : 1.412 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.549 +Data Delay : 4.252 + +Slack : 1.417 +From Node : ula:ula_|video:video_|vram_address[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.572 -Data Delay : 2.017 +Clock Skew : 2.553 +Data Delay : 4.261 -Slack : -0.845 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 2.009 - -Slack : -0.845 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.012 - -Slack : -0.843 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 2.013 - -Slack : -0.843 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 2.009 - -Slack : -0.842 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 2.013 - -Slack : -0.839 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 2.015 - -Slack : -0.839 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.018 - -Slack : -0.838 -From Node : ula:ula_|video:video_|vram_address[0] +Slack : 1.418 +From Node : ula:ula_|video:video_|vram_address[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.575 -Data Delay : 2.028 +Clock Skew : 2.562 +Data Delay : 4.271 -Slack : -0.838 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.019 - -Slack : -0.837 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.020 - -Slack : -0.837 -From Node : ula:ula_|video:video_|vram_address[9] +Slack : 1.422 +From Node : ula:ula_|video:video_|vram_address[2] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.570 -Data Delay : 2.024 +Clock Skew : 2.562 +Data Delay : 4.275 -Slack : -0.835 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Slack : 1.426 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 2.017 +Clock Skew : 2.551 +Data Delay : 4.268 -Slack : -0.835 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.556 -Data Delay : 2.012 - -Slack : -0.834 +Slack : 1.427 From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.280 + +Slack : 1.431 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.569 +Data Delay : 4.291 + +Slack : 1.438 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.291 + +Slack : 1.443 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.551 +Data Delay : 4.285 + +Slack : 1.446 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.560 +Data Delay : 4.297 + +Slack : 1.449 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.302 + +Slack : 1.455 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.560 +Data Delay : 4.306 + +Slack : 1.456 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.305 + +Slack : 1.460 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.304 + +Slack : 1.470 +From Node : ula:ula_|video:video_|vram_address[4] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.023 +Clock Skew : 2.571 +Data Delay : 4.332 -Slack : -0.834 +Slack : 1.472 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.551 +Data Delay : 4.314 + +Slack : 1.474 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.549 +Data Delay : 4.314 + +Slack : 1.474 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.318 + +Slack : 1.476 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.625 +Data Delay : 4.392 + +Slack : 1.477 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 4.322 + +Slack : 1.479 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.649 +Data Delay : 4.419 + +Slack : 1.483 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.336 + +Slack : 1.489 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.571 +Data Delay : 4.351 + +Slack : 1.492 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.633 +Data Delay : 4.416 + +Slack : 1.496 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.340 + +Slack : 1.496 From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.555 +Data Delay : 4.342 + +Slack : 1.497 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.567 +Data Delay : 4.355 + +Slack : 1.499 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 4.347 + +Slack : 1.502 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.378 +Data Delay : 4.171 + +Slack : 1.505 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.358 + +Slack : 1.507 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 4.355 + +Slack : 1.508 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.569 +Data Delay : 4.368 + +Slack : 1.509 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 4.354 + +Slack : 1.512 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.365 + +Slack : 1.517 +From Node : ula:ula_|video:video_|vram_address[4] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 2.020 +Clock Skew : 2.560 +Data Delay : 4.368 -Slack : -0.834 +Slack : 1.517 From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 2.023 +Clock Skew : 2.554 +Data Delay : 4.362 -Slack : -0.833 +Slack : 1.519 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.569 +Data Delay : 4.379 + +Slack : 1.522 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.632 +Data Delay : 4.445 + +Slack : 1.523 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.551 +Data Delay : 4.365 + +Slack : 1.525 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.551 +Data Delay : 4.367 + +Slack : 1.525 From Node : ula:ula_|video:video_|vram_address[4] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 2.021 +Clock Skew : 2.549 +Data Delay : 4.365 -Slack : -0.833 +Slack : 1.525 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.565 +Data Delay : 4.381 + +Slack : 1.527 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.380 + +Slack : 1.528 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.563 +Data Delay : 4.382 + +Slack : 1.529 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.571 +Data Delay : 4.391 + +Slack : 1.531 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.645 +Data Delay : 4.467 + +Slack : 1.531 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.552 +Data Delay : 4.374 + +Slack : 1.532 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 4.380 + +Slack : 1.533 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.641 +Data Delay : 4.465 + +Slack : 1.533 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.382 + +Slack : 1.534 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.551 +Data Delay : 4.376 + +Slack : 1.534 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.552 +Data Delay : 4.377 + +Slack : 1.538 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.390 + +Slack : 1.540 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 4.385 + +Slack : 1.542 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.568 +Data Delay : 4.401 + +Slack : 1.543 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.549 +Data Delay : 4.383 + +Slack : 1.544 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.393 + +Slack : 1.545 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.574 +Data Delay : 4.410 + +Slack : 1.547 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.569 +Data Delay : 4.407 + +Slack : 1.547 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.550 +Data Delay : 4.388 + +Slack : 1.547 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 4.392 + +Slack : 1.548 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.397 + +Slack : 1.549 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.565 +Data Delay : 4.405 + +Slack : 1.549 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.398 + +Slack : 1.551 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.563 +Data Delay : 4.405 + +Slack : 1.553 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.574 +Data Delay : 4.418 + +Slack : 1.553 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 4.398 + +Slack : 1.555 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.575 +Data Delay : 4.421 + +Slack : 1.555 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.563 +Data Delay : 4.409 + +Slack : 1.557 From Node : ula:ula_|video:video_|vram_address[7] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 +Clock Skew : 2.549 +Data Delay : 4.397 + +Slack : 1.558 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 Clock Skew : 2.563 -Data Delay : 2.021 +Data Delay : 4.412 + +Slack : 1.562 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.550 +Data Delay : 4.403 + +Slack : 1.563 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.416 + +Slack : 1.565 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 4.413 + +Slack : 1.565 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.367 +Data Delay : 4.223 + +Slack : 1.567 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.416 + +Slack : 1.569 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.422 + +Slack : 1.572 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.566 +Data Delay : 4.429 + +Slack : 1.578 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.563 +Data Delay : 4.432 + +Slack : 1.578 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.431 + +Slack : 1.579 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.428 + +Slack : 1.580 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 4.425 +--------------------------------------------------------------------------------+ @@ -4094,24 +4094,6 @@ Data Delay : 1.190 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 0.342 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.577 - -Slack : 0.342 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.577 - Slack : 0.344 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] @@ -4121,15 +4103,6 @@ Relationship : 0.000 Clock Skew : 0.076 Data Delay : 0.577 -Slack : 0.345 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.580 - Slack : 0.345 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] @@ -4140,26 +4113,26 @@ Clock Skew : 0.078 Data Delay : 0.580 Slack : 0.346 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.580 -Slack : 0.346 +Slack : 0.347 From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.077 +Clock Skew : 0.076 Data Delay : 0.580 Slack : 0.357 -From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -4167,8 +4140,26 @@ Clock Skew : 0.063 Data Delay : 0.577 Slack : 0.357 -From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -4176,8 +4167,8 @@ Clock Skew : 0.063 Data Delay : 0.577 Slack : 0.358 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -4185,8 +4176,8 @@ Clock Skew : 0.062 Data Delay : 0.577 Slack : 0.358 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -4211,24 +4202,6 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.577 -Slack : 0.358 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - Slack : 0.358 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] @@ -4238,6 +4211,33 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.577 +Slack : 0.358 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + Slack : 0.361 From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] @@ -4256,176 +4256,158 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.580 -Slack : 0.369 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.604 - -Slack : 0.372 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Slack : 0.361 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.591 +Data Delay : 0.580 -Slack : 0.373 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.592 - -Slack : 0.374 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.593 - -Slack : 0.374 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.593 - -Slack : 0.374 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.593 - -Slack : 0.375 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.594 - -Slack : 0.375 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.594 - -Slack : 0.375 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.594 - -Slack : 0.395 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.615 - -Slack : 0.397 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.616 - -Slack : 0.405 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.639 - -Slack : 0.408 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.627 - -Slack : 0.418 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.637 - -Slack : 0.420 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.639 - -Slack : 0.534 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.753 - -Slack : 0.544 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.779 - -Slack : 0.545 +Slack : 0.362 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 0.780 +Data Delay : 0.597 -Slack : 0.545 +Slack : 0.374 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.593 + +Slack : 0.384 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.603 + +Slack : 0.384 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.603 + +Slack : 0.386 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.605 + +Slack : 0.399 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.618 + +Slack : 0.401 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.620 + +Slack : 0.463 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.698 + +Slack : 0.463 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.698 + +Slack : 0.464 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.699 + +Slack : 0.464 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.699 + +Slack : 0.466 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.701 + +Slack : 0.513 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.732 + +Slack : 0.515 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.060 +Data Delay : 0.732 + +Slack : 0.542 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.777 + +Slack : 0.544 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 0.780 +Data Delay : 0.779 Slack : 0.547 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] @@ -4436,89 +4418,44 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 0.782 -Slack : 0.552 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Slack : 0.548 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.771 +Clock Skew : 0.106 +Data Delay : 0.811 -Slack : 0.552 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.771 - -Slack : 0.553 +Slack : 0.554 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.772 - -Slack : 0.553 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.772 - -Slack : 0.554 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 Data Delay : 0.773 -Slack : 0.556 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.775 - -Slack : 0.556 +Slack : 0.555 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.775 +Data Delay : 0.774 -Slack : 0.556 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.775 - -Slack : 0.556 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Slack : 0.555 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 0.791 +Data Delay : 0.790 Slack : 0.557 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -4553,59 +4490,131 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.778 -Slack : 0.560 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Slack : 0.561 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.795 +Clock Skew : 0.062 +Data Delay : 0.780 -Slack : 0.568 +Slack : 0.564 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.782 + +Slack : 0.567 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.063 Data Delay : 0.787 -Slack : 0.579 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Slack : 0.574 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.813 +Clock Skew : 0.078 +Data Delay : 0.809 -Slack : 0.579 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Slack : 0.574 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.798 +Clock Skew : 0.078 +Data Delay : 0.809 -Slack : 0.581 +Slack : 0.575 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.810 + +Slack : 0.575 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.432 +Data Delay : 1.164 + +Slack : 0.576 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.811 + +Slack : 0.576 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.811 + +Slack : 0.576 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.811 + +Slack : 0.576 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.811 + +Slack : 0.577 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.812 + +Slack : 0.577 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.800 +Data Delay : 0.796 -Slack : 0.586 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Slack : 0.580 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.820 +Clock Skew : 0.062 +Data Delay : 0.799 Slack : 0.590 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] @@ -4616,293 +4625,221 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.809 -Slack : 0.592 +Slack : 0.590 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.809 + +Slack : 0.597 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.826 +Clock Skew : 0.062 +Data Delay : 0.816 -Slack : 0.595 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.830 - -Slack : 0.600 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Slack : 0.604 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.819 +Data Delay : 0.823 -Slack : 0.608 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.842 - -Slack : 0.610 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.844 - -Slack : 0.655 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.889 - -Slack : 0.667 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.470 -Data Delay : 1.294 - -Slack : 0.681 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Slack : 0.612 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.900 +Data Delay : 0.831 -Slack : 0.684 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Slack : 0.613 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.918 +Clock Skew : 0.062 +Data Delay : 0.832 -Slack : 0.685 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Slack : 0.627 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.919 +Clock Skew : 0.062 +Data Delay : 0.846 -Slack : 0.688 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.922 - -Slack : 0.694 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : -0.260 -Data Delay : 0.591 - -Slack : 0.705 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.076 -Data Delay : 0.938 - -Slack : 0.711 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.470 -Data Delay : 1.338 - -Slack : 0.747 +Slack : 0.636 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.981 +Clock Skew : 0.062 +Data Delay : 0.855 -Slack : 0.754 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Slack : 0.639 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.470 -Data Delay : 1.381 +Clock Skew : 0.062 +Data Delay : 0.858 -Slack : 0.779 +Slack : 0.680 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.899 + +Slack : 0.686 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.905 + +Slack : 0.703 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.922 + +Slack : 0.747 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.293 +Data Delay : 0.611 + +Slack : 0.763 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 0.984 + +Slack : 0.764 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 0.985 + +Slack : 0.771 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 0.992 + +Slack : 0.780 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.999 + +Slack : 0.785 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.004 + +Slack : 0.786 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.005 + +Slack : 0.788 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.008 + +Slack : 0.799 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.998 - -Slack : 0.789 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.023 - -Slack : 0.795 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.441 -Data Delay : 1.393 - -Slack : 0.796 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.441 -Data Delay : 1.394 - -Slack : 0.798 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.441 -Data Delay : 1.396 +Data Delay : 1.018 Slack : 0.808 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.042 +Clock Skew : 0.063 +Data Delay : 1.028 -Slack : 0.818 +Slack : 0.814 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.033 + +Slack : 0.817 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 1.053 +Data Delay : 1.052 -Slack : 0.819 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.053 - -Slack : 0.819 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.053 - -Slack : 0.819 +Slack : 0.818 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 1.054 - -Slack : 0.821 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.406 - -Slack : 0.822 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.407 - -Slack : 0.828 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.076 -Data Delay : 1.061 - -Slack : 0.829 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.048 - -Slack : 0.829 -From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.079 -Data Delay : 1.065 - -Slack : 0.831 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.050 +Data Delay : 1.053 Slack : 0.831 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] @@ -4914,7 +4851,7 @@ Clock Skew : 0.062 Data Delay : 1.050 Slack : 0.831 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -4922,6 +4859,15 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 1.066 +Slack : 0.832 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.051 + Slack : 0.832 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] @@ -4932,7 +4878,16 @@ Clock Skew : 0.062 Data Delay : 1.051 Slack : 0.833 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.291 +Data Delay : 0.699 + +Slack : 0.833 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -4940,6 +4895,15 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 1.068 +Slack : 0.833 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 1.068 + Slack : 0.834 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] @@ -4949,14 +4913,23 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 1.069 -Slack : 0.834 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 0.835 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.069 + +Slack : 0.835 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 1.069 +Data Delay : 1.070 Slack : 0.836 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] @@ -4967,32 +4940,59 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 1.071 -Slack : 0.836 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 0.845 +From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.078 +Clock Skew : 0.062 +Data Delay : 1.064 + +Slack : 0.848 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.067 + +Slack : 0.850 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.069 + +Slack : 0.852 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 Data Delay : 1.071 -Slack : 0.837 +Slack : 0.854 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.073 + +Slack : 0.854 From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.079 +Clock Skew : 0.062 Data Delay : 1.073 - -Slack : 0.843 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.077 +--------------------------------------------------------------------------------+ @@ -5009,15 +5009,6 @@ Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.577 -Slack : 0.357 -From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - Slack : 0.357 From Node : ula:ula_|video:video_|vram_address[10] To Node : ula:ula_|video:video_|vram_address[10] @@ -5036,13 +5027,13 @@ Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.577 -Slack : 0.357 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[5] +Slack : 0.358 +From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 0.577 Slack : 0.358 @@ -5082,8 +5073,8 @@ Clock Skew : 0.062 Data Delay : 0.577 Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vga_vc[3] +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vga_vc[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -5117,788 +5108,797 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.577 -Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vga_vc[8] +Slack : 0.549 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.577 +Data Delay : 0.768 -Slack : 0.686 +Slack : 0.553 From Node : ula:ula_|video:video_|frame[3] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.906 +Clock Skew : 0.062 +Data Delay : 0.772 -Slack : 0.818 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vram_address[10] +Slack : 0.563 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.041 +Clock Skew : 0.062 +Data Delay : 0.782 -Slack : 0.915 -From Node : ula:ula_|video:video_|bits_prefetch[3] -To Node : ula:ula_|video:video_|bits[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.058 -Data Delay : 1.130 - -Slack : 0.955 +Slack : 0.570 From Node : ula:ula_|video:video_|frame[4] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.175 +Clock Skew : 0.062 +Data Delay : 0.789 -Slack : 1.010 +Slack : 0.657 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.876 + +Slack : 0.728 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.948 + +Slack : 0.821 From Node : ula:ula_|video:video_|vga_vc[1] To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.233 +Clock Skew : 0.069 +Data Delay : 1.047 -Slack : 1.020 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.240 - -Slack : 1.075 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.291 - -Slack : 1.078 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.294 - -Slack : 1.078 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.294 - -Slack : 1.163 -From Node : ula:ula_|video:video_|attr_prefetch[3] -To Node : ula:ula_|video:video_|attr[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.263 -Data Delay : 1.057 - -Slack : 1.189 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vram_address[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.405 - -Slack : 1.190 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.410 - -Slack : 1.190 -From Node : ula:ula_|video:video_|frame[0] +Slack : 0.824 +From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.408 +Clock Skew : 0.062 +Data Delay : 1.043 -Slack : 1.194 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vram_address[1] +Slack : 0.840 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.410 +Clock Skew : 0.062 +Data Delay : 1.059 -Slack : 1.215 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vram_address[4] +Slack : 0.841 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.431 +Clock Skew : 0.062 +Data Delay : 1.060 -Slack : 1.218 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.434 - -Slack : 1.222 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.442 - -Slack : 1.242 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.458 - -Slack : 1.249 +Slack : 0.843 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.468 +Data Delay : 1.062 -Slack : 1.263 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Slack : 0.860 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_hc[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.486 +Clock Skew : 0.063 +Data Delay : 1.080 -Slack : 1.293 -From Node : ula:ula_|video:video_|bits_prefetch[1] -To Node : ula:ula_|video:video_|bits[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.270 -Data Delay : 1.180 - -Slack : 1.295 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[6] +Slack : 0.919 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.514 +Data Delay : 1.138 -Slack : 1.298 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[6] +Slack : 0.934 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.517 +Data Delay : 1.153 -Slack : 1.299 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vram_address[11] +Slack : 0.953 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.519 +Clock Skew : 0.062 +Data Delay : 1.172 -Slack : 1.299 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.519 - -Slack : 1.309 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.529 - -Slack : 1.314 +Slack : 0.967 From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.534 - -Slack : 1.322 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.542 - -Slack : 1.352 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vga_hc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.575 - -Slack : 1.371 -From Node : ula:ula_|video:video_|attr_prefetch[1] -To Node : ula:ula_|video:video_|attr[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.298 -Data Delay : 1.230 - -Slack : 1.374 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vga_hc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.597 - -Slack : 1.378 -From Node : ula:ula_|video:video_|vga_vc[1] To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.598 +Clock Skew : 0.069 +Data Delay : 1.193 -Slack : 1.380 -From Node : ula:ula_|video:video_|vga_vc[1] +Slack : 0.980 +From Node : ula:ula_|video:video_|vga_vc[5] To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.600 +Clock Skew : 0.069 +Data Delay : 1.206 -Slack : 1.386 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.606 - -Slack : 1.405 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.628 - -Slack : 1.407 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.626 - -Slack : 1.411 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.631 - -Slack : 1.413 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.633 - -Slack : 1.424 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.644 - -Slack : 1.425 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.645 - -Slack : 1.442 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.662 - -Slack : 1.447 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.666 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.669 - -Slack : 1.452 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.671 - -Slack : 1.455 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.065 -Data Delay : 1.677 - -Slack : 1.460 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_hc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.679 - -Slack : 1.473 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.692 - -Slack : 1.479 -From Node : ula:ula_|video:video_|attr_prefetch[0] -To Node : ula:ula_|video:video_|attr[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.265 -Data Delay : 1.371 - -Slack : 1.481 +Slack : 1.030 From Node : ula:ula_|video:video_|vga_hc[4] To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.700 - -Slack : 1.481 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.700 - -Slack : 1.490 -From Node : ula:ula_|video:video_|bits_prefetch[0] -To Node : ula:ula_|video:video_|bits[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.292 -Data Delay : 1.355 - -Slack : 1.490 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.710 - -Slack : 1.497 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.717 - -Slack : 1.500 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vga_vc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.719 - -Slack : 1.523 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.743 - -Slack : 1.530 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 Clock Skew : 0.066 -Data Delay : 1.753 +Data Delay : 1.253 -Slack : 1.531 +Slack : 1.074 From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vram_address[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.068 -Data Delay : 1.756 +Data Delay : 1.299 -Slack : 1.531 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.065 -Data Delay : 1.753 - -Slack : 1.532 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.751 - -Slack : 1.533 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vga_hc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.752 - -Slack : 1.533 +Slack : 1.074 From Node : ula:ula_|video:video_|vga_hc[2] To Node : ula:ula_|video:video_|vram_address[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.065 -Data Delay : 1.755 +Clock Skew : 0.068 +Data Delay : 1.299 -Slack : 1.542 +Slack : 1.077 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.302 + +Slack : 1.078 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.303 + +Slack : 1.111 +From Node : ula:ula_|video:video_|bits_prefetch[6] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.300 +Data Delay : 0.968 + +Slack : 1.117 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.343 + +Slack : 1.118 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.344 + +Slack : 1.129 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.355 + +Slack : 1.140 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.300 +Data Delay : 0.997 + +Slack : 1.143 +From Node : ula:ula_|video:video_|bits_prefetch[1] +To Node : ula:ula_|video:video_|bits[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.300 +Data Delay : 1.000 + +Slack : 1.151 +From Node : ula:ula_|video:video_|bits_prefetch[5] +To Node : ula:ula_|video:video_|bits[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.300 +Data Delay : 1.008 + +Slack : 1.159 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.385 + +Slack : 1.193 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.412 + +Slack : 1.195 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.414 + +Slack : 1.201 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.427 + +Slack : 1.241 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.467 + +Slack : 1.248 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.474 + +Slack : 1.262 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vga_hc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.482 + +Slack : 1.265 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.485 + +Slack : 1.265 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.485 + +Slack : 1.265 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.485 + +Slack : 1.265 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.485 + +Slack : 1.269 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.495 + +Slack : 1.279 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.505 + +Slack : 1.281 +From Node : ula:ula_|video:video_|bits_prefetch[0] +To Node : ula:ula_|video:video_|bits[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.300 +Data Delay : 1.138 + +Slack : 1.281 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.507 + +Slack : 1.291 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.511 + +Slack : 1.291 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.512 + +Slack : 1.296 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.328 +Data Delay : 1.125 + +Slack : 1.299 From Node : ula:ula_|video:video_|bits_prefetch[4] To Node : ula:ula_|video:video_|bits[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : -0.300 -Data Delay : 1.399 +Data Delay : 1.156 -Slack : 1.550 -From Node : ula:ula_|video:video_|frame[3] +Slack : 1.305 +From Node : ula:ula_|video:video_|frame[0] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.770 - -Slack : 1.556 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.776 - -Slack : 1.557 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.065 -Data Delay : 1.779 - -Slack : 1.559 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.778 +Data Delay : 1.524 -Slack : 1.560 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.780 - -Slack : 1.564 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.783 - -Slack : 1.575 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.794 - -Slack : 1.577 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vga_hc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.796 - -Slack : 1.577 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.796 - -Slack : 1.595 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.814 - -Slack : 1.598 -From Node : ula:ula_|video:video_|vga_hc[6] +Slack : 1.310 +From Node : ula:ula_|video:video_|vga_hc[9] To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.817 +Data Delay : 1.529 -Slack : 1.603 +Slack : 1.312 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|vga_hc[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.531 + +Slack : 1.314 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.540 + +Slack : 1.316 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.542 + +Slack : 1.323 +From Node : ula:ula_|video:video_|attr_prefetch[5] +To Node : ula:ula_|video:video_|attr[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.328 +Data Delay : 1.152 + +Slack : 1.339 +From Node : ula:ula_|video:video_|attr_prefetch[7] +To Node : ula:ula_|video:video_|attr[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.328 +Data Delay : 1.168 + +Slack : 1.342 +From Node : ula:ula_|video:video_|attr_prefetch[4] +To Node : ula:ula_|video:video_|attr[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.329 +Data Delay : 1.170 + +Slack : 1.351 From Node : ula:ula_|video:video_|vga_vc[4] To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.823 +Clock Skew : 0.069 +Data Delay : 1.577 -Slack : 1.609 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[11] +Slack : 1.355 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 1.829 +Data Delay : 1.575 -Slack : 1.609 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[8] +Slack : 1.360 +From Node : ula:ula_|video:video_|attr_prefetch[0] +To Node : ula:ula_|video:video_|attr[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.829 +Clock Skew : -0.329 +Data Delay : 1.188 -Slack : 1.645 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.865 - -Slack : 1.645 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.868 - -Slack : 1.657 +Slack : 1.378 From Node : ula:ula_|video:video_|vga_vc[0] To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.877 +Clock Skew : 0.069 +Data Delay : 1.604 -Slack : 1.659 +Slack : 1.380 From Node : ula:ula_|video:video_|vga_vc[0] To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.879 +Clock Skew : 0.069 +Data Delay : 1.606 -Slack : 1.669 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[8] +Slack : 1.387 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.889 +Clock Skew : 0.066 +Data Delay : 1.610 -Slack : 1.684 +Slack : 1.391 From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.903 +Clock Skew : 0.069 +Data Delay : 1.617 -Slack : 1.684 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[9] +Slack : 1.398 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.903 +Clock Skew : 0.066 +Data Delay : 1.621 -Slack : 1.687 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.906 - -Slack : 1.689 +Slack : 1.405 From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.908 +Clock Skew : 0.069 +Data Delay : 1.631 -Slack : 1.691 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vga_vc[8] +Slack : 1.406 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.910 +Clock Skew : 0.063 +Data Delay : 1.626 + +Slack : 1.407 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.633 + +Slack : 1.426 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.652 + +Slack : 1.450 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.469 +Data Delay : 2.076 + +Slack : 1.450 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.469 +Data Delay : 2.076 + +Slack : 1.450 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.469 +Data Delay : 2.076 + +Slack : 1.450 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.469 +Data Delay : 2.076 + +Slack : 1.450 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.469 +Data Delay : 2.076 + +Slack : 1.450 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.469 +Data Delay : 2.076 + +Slack : 1.450 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.469 +Data Delay : 2.076 + +Slack : 1.450 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.469 +Data Delay : 2.076 + +Slack : 1.479 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.440 +Data Delay : 2.076 + +Slack : 1.479 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.440 +Data Delay : 2.076 + +Slack : 1.479 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.440 +Data Delay : 2.076 + +Slack : 1.479 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.440 +Data Delay : 2.076 + +Slack : 1.479 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.440 +Data Delay : 2.076 + +Slack : 1.479 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.440 +Data Delay : 2.076 + +Slack : 1.479 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.440 +Data Delay : 2.076 + +Slack : 1.479 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.440 +Data Delay : 2.076 + +Slack : 1.490 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.716 + +Slack : 1.500 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.720 + +Slack : 1.509 +From Node : ula:ula_|video:video_|bits_prefetch[7] +To Node : ula:ula_|video:video_|bits[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.300 +Data Delay : 1.366 + +Slack : 1.517 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_hc[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.066 +Data Delay : 1.740 +--------------------------------------------------------------------------------+ @@ -5906,743 +5906,743 @@ Data Delay : 1.910 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -6.277 +Slack : -6.223 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 4.398 +Data Delay : 4.344 -Slack : -6.277 +Slack : -6.223 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.163 -Data Delay : 4.396 +Data Delay : 4.342 -Slack : -6.277 +Slack : -6.223 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.164 -Data Delay : 4.395 +Data Delay : 4.341 -Slack : -6.277 +Slack : -6.223 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.165 -Data Delay : 4.394 +Data Delay : 4.340 -Slack : -6.276 +Slack : -6.222 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.164 -Data Delay : 4.394 +Data Delay : 4.340 -Slack : -6.050 +Slack : -5.985 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.193 -Data Delay : 4.141 +Data Delay : 4.076 -Slack : -6.039 +Slack : -5.971 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.195 -Data Delay : 4.128 +Data Delay : 4.060 -Slack : -5.772 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.990 - -Slack : -5.772 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.990 - -Slack : -5.772 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.990 - -Slack : -5.771 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.989 - -Slack : -5.771 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.989 - -Slack : -5.771 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.989 - -Slack : -5.771 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.989 - -Slack : -5.771 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.989 - -Slack : -5.771 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.989 - -Slack : -5.771 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.989 - -Slack : -5.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.164 -Data Delay : 3.976 - -Slack : -5.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.164 -Data Delay : 3.976 - -Slack : -5.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.164 -Data Delay : 3.976 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.979 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.976 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.976 - -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.976 - -Slack : -5.760 +Slack : -5.707 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.163 -Data Delay : 3.976 +Data Delay : 3.923 -Slack : -5.760 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.976 - -Slack : -5.760 +Slack : -5.707 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.163 -Data Delay : 3.976 +Data Delay : 3.923 -Slack : -5.760 +Slack : -5.707 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.163 -Data Delay : 3.976 +Data Delay : 3.923 -Slack : -5.760 +Slack : -5.707 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.163 -Data Delay : 3.976 +Data Delay : 3.923 -Slack : -5.438 +Slack : -5.706 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.162 -Data Delay : 3.979 +Clock Skew : -0.166 +Data Delay : 3.919 -Slack : -5.438 +Slack : -5.706 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.159 -Data Delay : 3.976 +Clock Skew : -0.166 +Data Delay : 3.919 -Slack : -5.438 +Slack : -5.706 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.159 -Data Delay : 3.976 +Clock Skew : -0.166 +Data Delay : 3.919 -Slack : -5.438 +Slack : -5.706 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.159 -Data Delay : 3.976 +Clock Skew : -0.166 +Data Delay : 3.919 -Slack : -5.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 3.989 - -Slack : -5.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 3.989 - -Slack : -5.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 3.989 - -Slack : -5.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 3.989 - -Slack : -5.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 3.989 - -Slack : -5.411 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.200 -Data Delay : 3.990 - -Slack : -5.411 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.200 -Data Delay : 3.990 - -Slack : -5.411 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.200 -Data Delay : 3.990 - -Slack : -5.410 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.191 -Data Delay : 3.977 - -Slack : -5.410 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.191 -Data Delay : 3.977 - -Slack : -5.410 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.191 -Data Delay : 3.977 - -Slack : -5.410 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.191 -Data Delay : 3.977 - -Slack : -5.410 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.191 -Data Delay : 3.977 - -Slack : -5.410 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.191 -Data Delay : 3.977 - -Slack : -5.409 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.180 -Data Delay : 3.968 - -Slack : -5.409 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.180 -Data Delay : 3.968 - -Slack : -5.409 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.180 -Data Delay : 3.968 - -Slack : -5.409 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.180 -Data Delay : 3.968 - -Slack : -5.409 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.180 -Data Delay : 3.968 - -Slack : -5.409 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.180 -Data Delay : 3.968 - -Slack : -5.409 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.180 -Data Delay : 3.968 - -Slack : -5.409 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.180 -Data Delay : 3.968 - -Slack : -5.409 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 3.978 - -Slack : -5.409 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.180 -Data Delay : 3.968 - -Slack : -5.409 +Slack : -5.706 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.191 -Data Delay : 3.979 +Clock Skew : -0.166 +Data Delay : 3.919 -Slack : -5.409 +Slack : -5.706 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.191 -Data Delay : 3.979 +Clock Skew : -0.166 +Data Delay : 3.919 -Slack : -5.409 +Slack : -5.706 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.191 -Data Delay : 3.979 +Clock Skew : -0.166 +Data Delay : 3.919 -Slack : -5.409 +Slack : -5.706 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.191 -Data Delay : 3.979 +Clock Skew : -0.166 +Data Delay : 3.919 -Slack : -5.409 +Slack : -5.706 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.191 -Data Delay : 3.979 +Clock Skew : -0.166 +Data Delay : 3.919 -Slack : -5.383 +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.166 +Data Delay : 3.919 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.166 +Data Delay : 3.919 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.922 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.922 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.922 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.922 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.228 -Data Delay : 3.990 +Clock Skew : -0.161 +Data Delay : 3.924 -Slack : -5.383 +Slack : -5.706 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.228 -Data Delay : 3.990 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.166 +Data Delay : 3.919 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.166 +Data Delay : 3.919 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.166 +Data Delay : 3.919 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.165 +Data Delay : 3.920 + +Slack : -5.375 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.170 +Data Delay : 3.924 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.190 +Data Delay : 3.922 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.190 +Data Delay : 3.922 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.190 +Data Delay : 3.922 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.190 +Data Delay : 3.922 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.190 +Data Delay : 3.922 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.190 +Data Delay : 3.922 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.918 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.918 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.918 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.918 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.918 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.918 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.918 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.918 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.918 + +Slack : -5.354 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.185 +Data Delay : 3.918 + +Slack : -5.353 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.188 +Data Delay : 3.920 + +Slack : -5.351 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.192 +Data Delay : 3.922 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 + +Slack : -5.347 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.198 +Data Delay : 3.924 +--------------------------------------------------------------------------------+ @@ -6650,77 +6650,275 @@ Data Delay : 3.990 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 3.683 +Slack : 3.698 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.649 -Data Delay : 3.573 +Clock Skew : 0.618 +Data Delay : 3.557 -Slack : 3.683 +Slack : 3.698 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.649 -Data Delay : 3.573 +Clock Skew : 0.618 +Data Delay : 3.557 -Slack : 3.705 +Slack : 3.698 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.618 +Data Delay : 3.557 + +Slack : 3.698 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.618 +Data Delay : 3.557 + +Slack : 3.698 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.618 +Data Delay : 3.557 + +Slack : 3.698 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.618 +Data Delay : 3.557 + +Slack : 3.698 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.618 +Data Delay : 3.557 + +Slack : 3.698 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.618 +Data Delay : 3.557 + +Slack : 3.698 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.618 +Data Delay : 3.557 + +Slack : 3.698 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.618 +Data Delay : 3.557 + +Slack : 3.698 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.618 +Data Delay : 3.557 + +Slack : 3.698 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.618 +Data Delay : 3.557 + +Slack : 3.698 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.618 +Data Delay : 3.557 + +Slack : 3.698 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.618 +Data Delay : 3.557 + +Slack : 3.703 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.610 -Data Delay : 3.559 +Clock Skew : 0.609 +Data Delay : 3.556 -Slack : 3.705 +Slack : 3.703 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.610 -Data Delay : 3.559 +Clock Skew : 0.609 +Data Delay : 3.556 -Slack : 3.705 +Slack : 3.703 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.610 -Data Delay : 3.559 +Clock Skew : 0.609 +Data Delay : 3.556 -Slack : 3.705 +Slack : 3.703 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.610 -Data Delay : 3.559 +Clock Skew : 0.609 +Data Delay : 3.556 -Slack : 3.705 +Slack : 3.703 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.610 -Data Delay : 3.559 +Clock Skew : 0.609 +Data Delay : 3.556 -Slack : 3.705 +Slack : 3.703 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.610 -Data Delay : 3.559 +Clock Skew : 0.609 +Data Delay : 3.556 + +Slack : 3.705 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.611 +Data Delay : 3.557 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.606 +Data Delay : 3.554 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.553 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.553 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.553 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.553 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.553 + +Slack : 3.710 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.554 + +Slack : 3.710 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.554 + +Slack : 3.710 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.554 Slack : 3.710 From Node : KEY[0] @@ -6728,665 +6926,467 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.609 -Data Delay : 3.560 +Clock Skew : 0.603 +Data Delay : 3.554 Slack : 3.710 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.610 -Data Delay : 3.561 - -Slack : 3.710 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.610 -Data Delay : 3.561 - -Slack : 3.710 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.610 -Data Delay : 3.561 - -Slack : 3.710 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.610 -Data Delay : 3.561 - -Slack : 3.710 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.610 -Data Delay : 3.561 - -Slack : 3.711 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.599 -Data Delay : 3.551 - -Slack : 3.711 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.599 -Data Delay : 3.551 - -Slack : 3.711 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.599 -Data Delay : 3.551 - -Slack : 3.711 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.599 -Data Delay : 3.551 - -Slack : 3.711 -From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.599 -Data Delay : 3.551 +Clock Skew : 0.603 +Data Delay : 3.554 -Slack : 3.712 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.598 -Data Delay : 3.551 - -Slack : 3.712 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.598 -Data Delay : 3.551 - -Slack : 3.712 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.598 -Data Delay : 3.551 - -Slack : 3.712 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.598 -Data Delay : 3.551 - -Slack : 3.712 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.620 -Data Delay : 3.573 - -Slack : 3.712 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.620 -Data Delay : 3.573 - -Slack : 3.712 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.620 -Data Delay : 3.573 - -Slack : 3.722 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.609 -Data Delay : 3.572 - -Slack : 3.722 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.609 -Data Delay : 3.572 - -Slack : 3.722 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.609 -Data Delay : 3.572 - -Slack : 3.722 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.609 -Data Delay : 3.572 - -Slack : 3.722 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.609 -Data Delay : 3.572 - -Slack : 3.739 +Slack : 3.728 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.580 -Data Delay : 3.560 +Clock Skew : 0.588 +Data Delay : 3.557 -Slack : 3.740 +Slack : 4.074 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.577 -Data Delay : 3.558 +Clock Skew : 0.238 +Data Delay : 3.553 -Slack : 3.740 +Slack : 4.074 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.577 -Data Delay : 3.558 +Clock Skew : 0.238 +Data Delay : 3.553 -Slack : 3.740 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.577 -Data Delay : 3.558 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.560 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.560 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.560 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.560 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.560 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.560 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.560 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.560 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.560 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.560 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.560 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.560 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.560 - -Slack : 4.076 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.561 - -Slack : 4.076 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.561 - -Slack : 4.076 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.561 - -Slack : 4.076 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.561 - -Slack : 4.076 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.561 - -Slack : 4.076 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.561 - -Slack : 4.076 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.558 - -Slack : 4.076 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.558 - -Slack : 4.076 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.558 - -Slack : 4.077 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.559 - -Slack : 4.077 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.559 - -Slack : 4.077 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.559 - -Slack : 4.077 +Slack : 4.074 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.559 +Clock Skew : 0.242 +Data Delay : 3.557 -Slack : 4.077 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.559 - -Slack : 4.077 +Slack : 4.074 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.559 +Clock Skew : 0.242 +Data Delay : 3.557 -Slack : 4.077 +Slack : 4.074 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.559 +Clock Skew : 0.242 +Data Delay : 3.557 -Slack : 4.077 +Slack : 4.074 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.241 +Clock Skew : 0.242 +Data Delay : 3.557 + +Slack : 4.074 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.238 +Data Delay : 3.553 + +Slack : 4.074 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.238 +Data Delay : 3.553 + +Slack : 4.074 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.238 +Data Delay : 3.553 + +Slack : 4.074 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.239 +Data Delay : 3.554 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.238 +Data Delay : 3.554 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.238 +Data Delay : 3.554 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.238 +Data Delay : 3.554 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.238 +Data Delay : 3.554 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.238 +Data Delay : 3.554 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.238 +Data Delay : 3.554 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.238 +Data Delay : 3.554 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.238 +Data Delay : 3.554 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.238 +Data Delay : 3.554 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 Data Delay : 3.559 -Slack : 4.089 +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.557 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.557 + +Slack : 4.075 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.573 +Data Delay : 3.559 -Slack : 4.089 +Slack : 4.075 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.573 +Data Delay : 3.559 -Slack : 4.089 +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.557 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.573 +Data Delay : 3.559 -Slack : 4.089 +Slack : 4.075 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.573 +Data Delay : 3.559 -Slack : 4.089 +Slack : 4.075 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.573 +Data Delay : 3.559 -Slack : 4.089 +Slack : 4.075 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.573 +Data Delay : 3.559 -Slack : 4.089 +Slack : 4.075 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.573 +Data Delay : 3.559 -Slack : 4.089 +Slack : 4.075 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.573 +Clock Skew : 0.241 +Data Delay : 3.557 -Slack : 4.089 +Slack : 4.075 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.573 +Data Delay : 3.559 -Slack : 4.089 +Slack : 4.075 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.573 +Data Delay : 3.559 -Slack : 4.310 +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.294 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.190 -Data Delay : 3.685 +Data Delay : 3.669 -Slack : 4.322 +Slack : 4.309 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.192 -Data Delay : 3.699 +Data Delay : 3.686 -Slack : 4.521 +Slack : 4.519 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.222 -Data Delay : 3.924 +Data Delay : 3.922 -Slack : 4.522 +Slack : 4.520 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.225 -Data Delay : 3.928 +Data Delay : 3.926 -Slack : 4.522 +Slack : 4.520 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.223 -Data Delay : 3.926 +Data Delay : 3.924 -Slack : 4.522 +Slack : 4.520 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.222 -Data Delay : 3.925 +Data Delay : 3.923 -Slack : 4.522 +Slack : 4.520 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.221 -Data Delay : 3.924 +Data Delay : 3.922 +--------------------------------------------------------------------------------+ @@ -7394,13 +7394,53 @@ Data Delay : 3.924 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 9.489 -Actual Width : 9.719 +Slack : 9.488 +Actual Width : 9.718 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.488 +Actual Width : 9.718 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 + +Slack : 9.488 +Actual Width : 9.718 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg + +Slack : 9.488 +Actual Width : 9.718 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.488 +Actual Width : 9.718 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 + +Slack : 9.488 +Actual Width : 9.718 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -7408,7 +7448,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -7416,7 +7456,39 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -7448,7 +7520,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -7456,7 +7528,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 Slack : 9.489 Actual Width : 9.719 @@ -7464,7 +7536,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -7472,7 +7544,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -7480,7 +7552,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 Slack : 9.489 Actual Width : 9.719 @@ -7488,31 +7560,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -7568,183 +7616,175 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 -Slack : 9.490 -Actual Width : 9.720 +Slack : 9.489 +Actual Width : 9.719 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Slack : 9.490 -Actual Width : 9.720 +Slack : 9.489 +Actual Width : 9.719 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 + Slack : 9.490 Actual Width : 9.720 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg Slack : 9.490 Actual Width : 9.720 @@ -7760,47 +7800,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -7824,112 +7824,144 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 -Slack : 9.490 -Actual Width : 9.720 +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 - Slack : 9.493 Actual Width : 9.723 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -Slack : 9.494 -Actual Width : 9.724 +Slack : 9.493 +Actual Width : 9.723 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 + Slack : 9.494 Actual Width : 9.724 Required Width : 0.230 @@ -7944,39 +7976,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 Slack : 9.494 Actual Width : 9.724 @@ -8000,39 +8000,55 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -Slack : 9.494 -Actual Width : 9.724 +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 + +Slack : 9.495 +Actual Width : 9.725 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -Slack : 9.495 -Actual Width : 9.725 +Slack : 9.498 +Actual Width : 9.728 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -Slack : 9.495 -Actual Width : 9.725 +Slack : 9.498 +Actual Width : 9.728 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 Slack : 9.499 Actual Width : 9.729 @@ -8040,7 +8056,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 Slack : 9.499 Actual Width : 9.729 @@ -8056,7 +8080,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 Slack : 9.499 Actual Width : 9.729 @@ -8064,15 +8088,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 - -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 Slack : 9.499 Actual Width : 9.729 @@ -8090,13 +8106,13 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -Slack : 9.500 -Actual Width : 9.730 +Slack : 9.499 +Actual Width : 9.729 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 Slack : 9.500 Actual Width : 9.730 @@ -8104,7 +8120,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 Slack : 9.500 Actual Width : 9.730 @@ -8112,7 +8128,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 Slack : 9.500 Actual Width : 9.730 @@ -8120,7 +8136,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 Slack : 9.500 Actual Width : 9.730 @@ -8128,7 +8144,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 Slack : 9.500 Actual Width : 9.730 @@ -8136,7 +8152,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 Slack : 9.500 Actual Width : 9.730 @@ -8144,23 +8160,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 - -Slack : 9.500 -Actual Width : 9.730 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 - -Slack : 9.500 -Actual Width : 9.730 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 Slack : 9.500 Actual Width : 9.730 @@ -8170,13 +8170,13 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 -Slack : 9.500 -Actual Width : 9.730 +Slack : 9.501 +Actual Width : 9.731 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 Slack : 9.501 Actual Width : 9.731 @@ -8184,7 +8184,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 Slack : 9.501 Actual Width : 9.731 @@ -8192,7 +8192,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 +--------------------------------------------------------------------------------+ @@ -8200,29 +8200,773 @@ Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[3] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[1] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg Slack : 19.603 -Actual Width : 19.819 -Required Width : 0.216 -Type : High Pulse Width +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[6] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg + +Slack : 19.604 +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 19.604 +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 + +Slack : 19.604 +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg + +Slack : 19.604 +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 19.604 +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 + +Slack : 19.604 +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg Slack : 19.604 Actual Width : 19.820 @@ -8232,14 +8976,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1 - Slack : 19.604 Actual Width : 19.820 Required Width : 0.216 @@ -8263,742 +8999,6 @@ Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|attr[2] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[3] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[4] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[5] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[6] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[7] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[0] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[2] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[5] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[7] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[0] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[1] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[2] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[3] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[4] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[5] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[6] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[7] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[3] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|frame[0] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|frame[1] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|frame[3] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|frame[4] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[0] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[1] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[2] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[3] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[4] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[5] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[6] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[7] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[8] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[9] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[0] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[1] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[2] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[3] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[4] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[5] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[6] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[7] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[8] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[9] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[0] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[10] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[11] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[12] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[1] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[2] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[3] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[4] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[5] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[6] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[7] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[8] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[9] - -Slack : 19.609 -Actual Width : 19.825 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[4] - -Slack : 19.614 -Actual Width : 19.830 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[1] - -Slack : 19.615 -Actual Width : 19.831 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[2] - -Slack : 19.615 -Actual Width : 19.831 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[6] - -Slack : 19.615 -Actual Width : 19.831 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|frame[2] - -Slack : 19.616 -Actual Width : 19.832 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[4] - -Slack : 19.616 -Actual Width : 19.832 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[0] - -Slack : 19.616 -Actual Width : 19.832 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[5] - -Slack : 19.616 -Actual Width : 19.832 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[7] - -Slack : 19.698 -Actual Width : 19.882 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[5] - -Slack : 19.699 -Actual Width : 19.854 -Required Width : 0.155 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_HS - -Slack : 19.699 -Actual Width : 19.854 -Required Width : 0.155 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_VS - -Slack : 19.699 -Actual Width : 19.883 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[4] - -Slack : 19.699 -Actual Width : 19.883 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[0] - -Slack : 19.699 -Actual Width : 19.883 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[2] - -Slack : 19.699 -Actual Width : 19.883 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[6] - -Slack : 19.699 -Actual Width : 19.883 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[7] - -Slack : 19.699 -Actual Width : 19.883 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|frame[2] - -Slack : 19.701 -Actual Width : 19.885 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[1] - -Slack : 19.705 -Actual Width : 19.889 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[4] - -Slack : 19.710 -Actual Width : 19.894 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[5] - -Slack : 19.710 -Actual Width : 19.894 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[3] - -Slack : 19.710 -Actual Width : 19.894 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[4] - -Slack : 19.710 -Actual Width : 19.894 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[5] - -Slack : 19.710 -Actual Width : 19.894 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[6] - -Slack : 19.710 -Actual Width : 19.894 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[7] - -Slack : 19.710 -Actual Width : 19.894 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[8] - -Slack : 19.710 -Actual Width : 19.894 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[9] - -Slack : 19.711 -Actual Width : 19.895 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1 - -Slack : 19.711 -Actual Width : 19.861 -Required Width : 0.150 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_VS - -Slack : 19.711 -Actual Width : 19.895 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1 - -Slack : 19.711 -Actual Width : 19.895 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[0] - -Slack : 19.711 -Actual Width : 19.895 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[1] - -Slack : 19.711 -Actual Width : 19.895 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[2] - -Slack : 19.711 -Actual Width : 19.895 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[3] - -Slack : 19.711 -Actual Width : 19.895 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[4] - -Slack : 19.711 -Actual Width : 19.895 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[5] +--------------------------------------------------------------------------------+ @@ -9014,182 +9014,70 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Slack : 20.595 -Actual Width : 20.811 +Slack : 20.598 +Actual Width : 20.814 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Slack : 20.595 -Actual Width : 20.811 +Slack : 20.598 +Actual Width : 20.814 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Slack : 20.595 -Actual Width : 20.811 +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 + +Slack : 20.598 +Actual Width : 20.814 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] - -Slack : 20.597 -Actual Width : 20.813 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] - Slack : 20.599 Actual Width : 20.815 Required Width : 0.216 @@ -9222,6 +9110,22 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 + Slack : 20.599 Actual Width : 20.815 Required Width : 0.216 @@ -9340,135 +9244,119 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 - -Slack : 20.601 -Actual Width : 20.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Slack : 20.602 -Actual Width : 20.818 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Slack : 20.602 -Actual Width : 20.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] - -Slack : 20.602 -Actual Width : 20.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] - -Slack : 20.607 -Actual Width : 20.823 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] - -Slack : 20.607 -Actual Width : 20.823 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] - -Slack : 20.607 -Actual Width : 20.823 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Slack : 20.607 -Actual Width : 20.823 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] + +Slack : 20.604 +Actual Width : 20.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Slack : 20.607 Actual Width : 20.823 @@ -9476,7 +9364,111 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Slack : 20.608 Actual Width : 20.824 @@ -9492,7 +9484,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] Slack : 20.608 Actual Width : 20.824 @@ -9510,14 +9502,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Slack : 20.608 -Actual Width : 20.824 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] - Slack : 20.608 Actual Width : 20.824 Required Width : 0.216 @@ -9526,14 +9510,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Slack : 20.608 -Actual Width : 20.824 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] - Slack : 20.608 Actual Width : 20.824 Required Width : 0.216 @@ -9548,7 +9524,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] Slack : 20.609 Actual Width : 20.825 @@ -9556,7 +9532,31 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + +Slack : 20.609 +Actual Width : 20.825 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] + +Slack : 20.609 +Actual Width : 20.825 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] + +Slack : 20.615 +Actual Width : 20.831 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] Slack : 20.647 Actual Width : 20.863 @@ -9654,6 +9654,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 20.684 +Actual Width : 20.868 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + Slack : 20.691 Actual Width : 20.846 Required Width : 0.155 @@ -9670,22 +9678,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|sda_out -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 - Slack : 20.692 Actual Width : 20.847 Required Width : 0.155 @@ -9702,6 +9694,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +Slack : 20.692 +Actual Width : 20.876 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] + Slack : 20.692 Actual Width : 20.876 Required Width : 0.184 @@ -9710,6 +9710,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Slack : 20.692 +Actual Width : 20.876 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + Slack : 20.692 Actual Width : 20.876 Required Width : 0.184 @@ -9732,7 +9740,15 @@ Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] + +Slack : 20.692 +Actual Width : 20.876 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Slack : 20.692 Actual Width : 20.847 @@ -9758,46 +9774,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] -Slack : 20.693 -Actual Width : 20.877 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] - -Slack : 20.693 -Actual Width : 20.877 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] - -Slack : 20.693 -Actual Width : 20.877 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] - -Slack : 20.693 -Actual Width : 20.877 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] - -Slack : 20.693 -Actual Width : 20.877 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] - Slack : 20.693 Actual Width : 20.848 Required Width : 0.155 @@ -9805,6 +9781,30 @@ Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r + +Slack : 20.693 +Actual Width : 20.877 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + +Slack : 20.693 +Actual Width : 20.877 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] + +Slack : 20.694 +Actual Width : 20.878 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +--------------------------------------------------------------------------------+ @@ -9930,6 +9930,20 @@ Target : ula:ula_|clocks:clocks_|counter[0] +--------------------------------------------------------------------------------+ ; Setup Times ; +--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 1.981 +Fall : 2.458 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 3.874 +Fall : 4.319 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : SW[*] Clock Port : CLOCK_50 Rise : 1.011 @@ -9946,15 +9960,15 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 1.279 -Fall : 1.518 +Rise : 1.262 +Fall : 1.505 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 2.849 -Fall : 3.096 +Rise : 2.823 +Fall : 3.104 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -9964,6 +9978,20 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Hold Times ; +--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -1.568 +Fall : -2.042 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -2.986 +Fall : -3.436 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : SW[*] Clock Port : CLOCK_50 Rise : -0.397 @@ -9980,15 +10008,15 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.660 -Fall : -0.890 +Rise : -0.645 +Fall : -0.878 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -0.943 -Fall : -1.178 +Rise : -1.355 +Fall : -1.593 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -10000,134 +10028,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 9.508 -Fall : 9.465 +Rise : 10.359 +Fall : 10.359 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 9.508 -Fall : 9.442 +Rise : 10.359 +Fall : 10.359 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 9.432 -Fall : 9.375 +Rise : 9.229 +Fall : 9.317 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 9.271 -Fall : 9.300 +Rise : 10.015 +Fall : 9.971 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 9.328 -Fall : 9.294 +Rise : 9.628 +Fall : 9.644 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 9.450 -Fall : 9.465 +Rise : 9.826 +Fall : 9.843 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 8.840 -Fall : 8.792 +Rise : 9.397 +Fall : 9.318 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 9.421 -Fall : 9.372 +Rise : 9.972 +Fall : 9.975 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 8.746 -Fall : 8.690 +Rise : 9.201 +Fall : 9.152 Clock Edge : Rise Clock Reference : CLOCK_50 +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 7.986 +Fall : 7.983 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 7.696 +Fall : 7.696 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 7.783 +Fall : 7.821 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 7.371 +Fall : 7.388 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 7.739 +Fall : 7.774 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 7.986 +Fall : 7.975 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 7.534 +Fall : 7.528 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 7.914 +Fall : 7.983 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 7.285 +Fall : 7.303 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 8.516 -Fall : 8.160 +Rise : 8.197 +Fall : 7.907 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 8.516 -Fall : 8.160 +Rise : 8.197 +Fall : 7.907 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 6.585 -Fall : 6.515 +Rise : 6.071 +Fall : 5.974 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 6.795 -Fall : 6.701 +Rise : 6.410 +Fall : 6.400 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 7.175 -Fall : 7.075 +Rise : 6.836 +Fall : 6.810 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 7.714 -Fall : 7.667 +Rise : 6.558 +Fall : 6.425 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 7.498 -Fall : 7.427 +Rise : 6.558 +Fall : 6.425 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 7.522 -Fall : 7.480 +Rise : 6.366 +Fall : 6.305 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 7.714 -Fall : 7.667 +Rise : 6.429 +Fall : 6.279 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 7.714 -Fall : 7.667 +Rise : 6.429 +Fall : 6.279 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -10140,36 +10231,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 7.938 -Fall : 7.956 +Rise : 6.621 +Fall : 6.664 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 7.839 -Fall : 7.811 +Rise : 6.621 +Fall : 6.664 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 7.938 -Fall : 7.956 +Rise : 6.426 +Fall : 6.412 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 7.171 -Fall : 7.100 +Rise : 6.231 +Fall : 6.211 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 7.809 -Fall : 7.789 +Rise : 6.443 +Fall : 6.428 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -10215,20 +10306,6 @@ Fall : 2.773 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Data Port : GPIO_1[*] -Clock Port : CLOCK_50 -Rise : 5.405 -Fall : 5.408 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - -Data Port : GPIO_1[22] -Clock Port : CLOCK_50 -Rise : 5.405 -Fall : 5.408 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Data Port : I2C_SCLK Clock Port : CLOCK_50 Rise : 2.951 @@ -10251,134 +10328,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 7.332 -Fall : 7.260 +Rise : 7.669 +Fall : 7.651 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 7.332 -Fall : 7.260 +Rise : 8.267 +Fall : 8.296 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 7.364 -Fall : 7.298 +Rise : 8.307 +Fall : 8.286 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 7.593 -Fall : 7.609 +Rise : 7.669 +Fall : 7.651 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 8.027 -Fall : 8.024 +Rise : 8.069 +Fall : 8.077 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 8.185 -Fall : 8.150 +Rise : 8.420 +Fall : 8.430 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 7.557 -Fall : 7.504 +Rise : 7.905 +Fall : 7.819 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 8.015 -Fall : 7.971 +Rise : 7.716 +Fall : 7.719 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 7.483 -Fall : 7.417 +Rise : 7.805 +Fall : 7.751 Clock Edge : Rise Clock Reference : CLOCK_50 +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 5.460 +Fall : 5.452 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 6.523 +Fall : 6.572 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 6.581 +Fall : 6.660 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 6.318 +Fall : 6.325 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 6.316 +Fall : 6.388 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 5.460 +Fall : 5.452 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 6.325 +Fall : 6.358 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 6.708 +Fall : 6.750 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 6.065 +Fall : 6.060 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 4.001 -Fall : 3.883 +Rise : 3.938 +Fall : 3.816 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 6.050 -Fall : 5.693 +Rise : 5.979 +Fall : 5.590 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 4.001 -Fall : 3.883 +Rise : 3.938 +Fall : 3.816 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 4.317 -Fall : 4.223 +Rise : 4.183 +Fall : 4.073 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 4.682 -Fall : 4.582 +Rise : 4.592 +Fall : 4.467 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 3.944 -Fall : 3.857 +Rise : 4.007 +Fall : 3.940 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 3.944 -Fall : 3.857 +Rise : 4.406 +Fall : 4.287 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 4.047 -Fall : 3.932 +Rise : 4.007 +Fall : 3.940 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 4.152 -Fall : 4.087 +Rise : 4.282 +Fall : 4.147 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 4.152 -Fall : 4.087 +Rise : 4.282 +Fall : 4.147 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -10391,36 +10531,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 3.812 -Fall : 3.740 +Rise : 3.864 +Fall : 3.753 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 4.453 -Fall : 4.423 +Rise : 4.238 +Fall : 4.188 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 4.448 -Fall : 4.390 +Rise : 4.151 +Fall : 4.091 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 3.812 -Fall : 3.740 +Rise : 3.864 +Fall : 3.753 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 4.425 -Fall : 4.402 +Rise : 4.068 +Fall : 3.961 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -10466,20 +10606,6 @@ Fall : 2.371 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Data Port : GPIO_1[*] -Clock Port : CLOCK_50 -Rise : 4.727 -Fall : 4.734 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - -Data Port : GPIO_1[22] -Clock Port : CLOCK_50 -Rise : 4.727 -Fall : 4.734 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Data Port : I2C_SCLK Clock Port : CLOCK_50 Rise : 2.549 @@ -10502,10 +10628,10 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.621 +RR : 4.629 RF : FR : -FF : 4.680 +FF : 4.693 Input Port : SW[2] Output Port : LED[2] @@ -10513,6 +10639,20 @@ RR : 4.044 RF : FR : FF : 4.195 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 6.626 +RF : +FR : +FF : 7.003 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 4.318 +RF : +FR : +FF : 4.517 +--------------------------------------------------------------------------------+ @@ -10522,10 +10662,10 @@ FF : 4.195 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.484 +RR : 4.491 RF : FR : -FF : 4.546 +FF : 4.559 Input Port : SW[2] Output Port : LED[2] @@ -10533,6 +10673,20 @@ RR : 3.930 RF : FR : FF : 4.081 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 6.402 +RF : +FR : +FF : 6.769 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 4.186 +RF : +FR : +FF : 4.384 +--------------------------------------------------------------------------------+ @@ -10546,18 +10700,18 @@ No synchronizer chains to report. +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 53.81 MHz -Restricted Fmax : 53.81 MHz +Fmax : 51.79 MHz +Restricted Fmax : 51.79 MHz Clock Name : CLOCK_50 Note : -Fmax : 147.67 MHz -Restricted Fmax : 147.67 MHz +Fmax : 138.35 MHz +Restricted Fmax : 138.35 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Note : -Fmax : 233.15 MHz -Restricted Fmax : 233.15 MHz +Fmax : 177.12 MHz +Restricted Fmax : 177.12 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Note : @@ -10574,16 +10728,16 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; Slow 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -17.588 -End Point TNS : -332.785 - -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -4.423 -End Point TNS : -38.803 +Slack : -17.311 +End Point TNS : -526.609 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : -3.309 -End Point TNS : -45.165 +Slack : -6.686 +End Point TNS : -253.661 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : -4.428 +End Point TNS : -40.009 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Slack : -2.785 @@ -10595,16 +10749,16 @@ End Point TNS : -2.785 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ -Clock : CLOCK_50 -Slack : -0.780 -End Point TNS : -12.413 - Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Slack : 0.298 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 0.298 +Slack : 0.300 +End Point TNS : 0.000 + +Clock : CLOCK_50 +Slack : 0.304 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -10618,8 +10772,8 @@ End Point TNS : 0.000 ; Slow 1200mV 0C Model Recovery Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -5.784 -End Point TNS : -426.554 +Slack : -5.744 +End Point TNS : -423.582 +--------------------------------------------------------------------------------+ @@ -10628,7 +10782,7 @@ End Point TNS : -426.554 ; Slow 1200mV 0C Model Removal Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 3.369 +Slack : 3.374 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -10638,15 +10792,15 @@ End Point TNS : 0.000 ; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 9.488 +Slack : 9.489 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : 19.594 +Slack : 19.600 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 20.588 +Slack : 20.591 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] @@ -10659,1811 +10813,905 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -17.588 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 7.384 - -Slack : -17.464 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 7.256 - -Slack : -17.460 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 7.252 - -Slack : -17.417 +Slack : -17.311 From Node : ula:ula_|video:video_|vga_vc[2] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 7.213 +Clock Skew : -0.273 +Data Delay : 7.112 -Slack : -17.416 -From Node : ula:ula_|video:video_|vga_vc[6] +Slack : -17.306 +From Node : ula:ula_|video:video_|vga_vc[3] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 7.212 +Clock Skew : -0.273 +Data Delay : 7.107 -Slack : -17.409 -From Node : ula:ula_|video:video_|vga_vc[4] +Slack : -17.281 +From Node : ula:ula_|video:video_|vga_hc[4] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 7.205 +Clock Skew : -0.274 +Data Delay : 7.081 -Slack : -17.386 -From Node : ula:ula_|video:video_|vga_vc[1] +Slack : -17.275 +From Node : ula:ula_|video:video_|vga_hc[6] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 7.182 - -Slack : -17.367 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.276 -Data Delay : 7.165 - -Slack : -17.350 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.276 -Data Delay : 7.148 - -Slack : -17.324 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 7.116 - -Slack : -17.277 -From Node : ula:ula_|video:video_|bits[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.276 +Clock Skew : -0.274 Data Delay : 7.075 -Slack : -17.274 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 7.070 - -Slack : -17.274 -From Node : ula:ula_|video:video_|bits[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.276 -Data Delay : 7.072 - -Slack : -17.252 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 7.048 - -Slack : -17.248 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 7.040 - -Slack : -17.228 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 7.020 - -Slack : -17.207 +Slack : -17.265 From Node : ula:ula_|video:video_|vga_vc[9] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 7.003 +Clock Skew : -0.273 +Data Delay : 7.066 -Slack : -17.183 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.975 - -Slack : -17.179 +Slack : -17.249 From Node : ula:ula_|video:video_|vga_vc[8] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.975 +Clock Skew : -0.273 +Data Delay : 7.050 + +Slack : -17.244 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.274 +Data Delay : 7.044 + +Slack : -17.196 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.755 + +Slack : -17.190 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 6.991 + +Slack : -17.182 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.272 +Data Delay : 6.984 + +Slack : -17.176 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.510 +Data Delay : 6.740 + +Slack : -17.176 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.277 +Data Delay : 6.973 Slack : -17.172 -From Node : ula:ula_|video:video_|vga_hc[8] +From Node : ula:ula_|video:video_|vga_hc[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.964 +Clock Skew : -0.277 +Data Delay : 6.969 -Slack : -17.160 -From Node : ula:ula_|video:video_|vga_vc[3] +Slack : -17.142 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.272 +Data Delay : 6.944 + +Slack : -17.140 +From Node : ula:ula_|video:video_|vga_vc[6] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.956 +Clock Skew : -0.273 +Data Delay : 6.941 -Slack : -17.132 -From Node : ula:ula_|video:video_|bits[7] +Slack : -17.136 +From Node : ula:ula_|video:video_|vga_vc[4] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.276 -Data Delay : 6.930 +Clock Skew : -0.273 +Data Delay : 6.937 -Slack : -17.078 +Slack : -17.114 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 6.915 + +Slack : -17.106 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.274 +Data Delay : 6.906 + +Slack : -17.082 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 6.883 + +Slack : -17.075 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.518 +Data Delay : 6.631 + +Slack : -17.061 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.272 +Data Delay : 6.863 + +Slack : -17.022 From Node : ula:ula_|video:video_|vga_vc[5] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.279 -Data Delay : 6.873 +Clock Skew : -0.273 +Data Delay : 6.823 -Slack : -17.073 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[0] +Slack : -16.969 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.865 +Clock Skew : -0.524 +Data Delay : 6.519 -Slack : -17.047 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.839 - -Slack : -17.043 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.835 - -Slack : -16.987 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.779 - -Slack : -16.977 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.773 - -Slack : -16.964 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.756 - -Slack : -16.964 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.756 - -Slack : -16.955 +Slack : -16.953 From Node : ula:ula_|video:video_|vga_hc[9] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.747 +Clock Skew : -0.277 +Data Delay : 6.750 -Slack : -16.947 +Slack : -16.941 +From Node : ula:ula_|video:video_|bits[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.277 +Data Delay : 6.738 + +Slack : -16.939 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.489 + +Slack : -16.921 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.272 +Data Delay : 6.723 + +Slack : -16.917 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.274 +Data Delay : 6.717 + +Slack : -16.916 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.475 + +Slack : -16.906 From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.739 - -Slack : -16.946 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.742 - -Slack : -16.933 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.725 - -Slack : -16.930 -From Node : ula:ula_|video:video_|bits[2] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.276 -Data Delay : 6.728 +Clock Skew : -0.274 +Data Delay : 6.706 -Slack : -16.907 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_R[3] +Slack : -16.904 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.699 +Clock Skew : -0.516 +Data Delay : 6.462 -Slack : -16.900 -From Node : ula:ula_|video:video_|bits[3] -To Node : VGA_B[0] +Slack : -16.894 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.276 -Data Delay : 6.698 +Clock Skew : -0.504 +Data Delay : 6.464 -Slack : -16.888 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[0] +Slack : -16.865 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.684 - -Slack : -16.877 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.669 - -Slack : -16.862 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.658 +Clock Skew : -0.516 +Data Delay : 6.423 Slack : -16.857 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.653 - -Slack : -16.856 -From Node : ula:ula_|video:video_|bits[4] +From Node : ula:ula_|video:video_|bits[6] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.276 +Clock Skew : -0.277 Data Delay : 6.654 -Slack : -16.851 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.643 - -Slack : -16.837 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.629 - -Slack : -16.831 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.627 - -Slack : -16.824 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.616 - -Slack : -16.824 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.616 - -Slack : -16.812 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.608 - -Slack : -16.811 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.603 - -Slack : -16.796 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_G[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.588 - -Slack : -16.781 +Slack : -16.852 From Node : ula:ula_|video:video_|frame[4] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.276 -Data Delay : 6.579 +Clock Skew : -0.279 +Data Delay : 6.647 -Slack : -16.781 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_G[2] +Slack : -16.821 +From Node : ula:ula_|video:video_|bits[7] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.577 +Clock Skew : -0.277 +Data Delay : 6.618 -Slack : -16.781 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_G[3] +Slack : -16.820 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.577 +Clock Skew : -0.518 +Data Delay : 6.376 -Slack : -16.768 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_G[2] +Slack : -16.761 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.560 +Clock Skew : -0.521 +Data Delay : 6.314 -Slack : -16.768 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_G[3] +Slack : -16.737 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.560 +Clock Skew : -0.272 +Data Delay : 6.539 -Slack : -16.766 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_G[0] +Slack : -16.733 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.558 +Clock Skew : -0.272 +Data Delay : 6.535 -Slack : -16.750 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_G[2] +Slack : -16.727 +From Node : ula:ula_|video:video_|bits[2] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.546 +Clock Skew : -0.277 +Data Delay : 6.524 -Slack : -16.750 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_G[3] +Slack : -16.721 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.546 +Clock Skew : -0.523 +Data Delay : 6.272 -Slack : -16.745 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_R[1] +Slack : -16.719 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.537 +Clock Skew : -0.513 +Data Delay : 6.280 -Slack : -16.729 +Slack : -16.716 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.274 + +Slack : -16.702 +From Node : ula:ula_|video:video_|bits[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.277 +Data Delay : 6.499 + +Slack : -16.700 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.272 +Data Delay : 6.502 + +Slack : -16.698 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.272 +Data Delay : 6.500 + +Slack : -16.679 From Node : ula:ula_|video:video_|attr[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.276 -Data Delay : 6.527 +Clock Skew : -0.277 +Data Delay : 6.476 -Slack : -16.728 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_G[2] +Slack : -16.665 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.520 +Clock Skew : -0.524 +Data Delay : 6.215 -Slack : -16.728 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_G[3] +Slack : -16.650 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.520 +Clock Skew : -0.508 +Data Delay : 6.216 -Slack : -16.723 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_R[0] +Slack : -16.637 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.519 +Clock Skew : -0.523 +Data Delay : 6.188 -Slack : -16.720 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[1] +Slack : -16.629 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.516 +Clock Skew : -0.272 +Data Delay : 6.431 -Slack : -16.697 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_R[3] +Slack : -16.615 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.493 +Clock Skew : -0.524 +Data Delay : 6.165 -Slack : -16.688 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_R[1] +Slack : -16.606 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.484 +Clock Skew : -0.513 +Data Delay : 6.167 -Slack : -16.656 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_G[1] +Slack : -16.595 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.448 +Clock Skew : -0.272 +Data Delay : 6.397 -Slack : -16.648 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_R[1] +Slack : -16.582 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.440 +Clock Skew : -0.514 +Data Delay : 6.142 -Slack : -16.635 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_R[0] +Slack : -16.567 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.427 +Clock Skew : -0.277 +Data Delay : 6.364 -Slack : -16.631 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[0] +Slack : -16.565 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.427 +Clock Skew : -0.516 +Data Delay : 6.123 -Slack : -16.626 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_G[0] +Slack : -16.554 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.418 +Clock Skew : -0.524 +Data Delay : 6.104 -Slack : -16.620 +Slack : -16.544 +From Node : ula:ula_|video:video_|bits[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.277 +Data Delay : 6.341 + +Slack : -16.541 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 6.093 + +Slack : -16.539 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.272 +Data Delay : 6.341 + +Slack : -16.529 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.508 +Data Delay : 6.095 + +Slack : -16.512 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.272 +Data Delay : 6.314 + +Slack : -16.511 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.272 +Data Delay : 6.313 + +Slack : -16.483 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.041 + +Slack : -16.443 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.517 +Data Delay : 6.000 + +Slack : -16.425 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.272 +Data Delay : 6.227 + +Slack : -16.422 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.512 +Data Delay : 5.984 + +Slack : -16.415 From Node : ula:ula_|video:video_|bits[0] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.276 -Data Delay : 6.418 +Clock Skew : -0.277 +Data Delay : 6.212 -Slack : -16.616 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_G[2] +Slack : -16.393 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.412 +Clock Skew : -0.522 +Data Delay : 5.945 -Slack : -16.616 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_G[3] +Slack : -16.347 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.412 +Clock Skew : -0.510 +Data Delay : 5.911 -Slack : -16.609 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_R[3] +Slack : -16.212 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.401 +Clock Skew : -0.514 +Data Delay : 5.772 -Slack : -16.605 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.401 - -Slack : -16.600 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_G[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.392 - -Slack : -16.590 +Slack : -16.157 From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_G[1] +To Node : VGA_B[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.386 +Clock Skew : -0.273 +Data Delay : 5.958 -Slack : -16.583 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_G[0] +Slack : -16.155 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.379 +Clock Skew : -0.521 +Data Delay : 5.708 -Slack : -16.582 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.378 - -Slack : -16.578 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.374 - -Slack : -16.570 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_G[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.362 - -Slack : -16.560 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_G[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.352 - -Slack : -16.559 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_G[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.355 - -Slack : -16.552 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.348 - -Slack : -16.552 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_G[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.348 - -Slack : -16.549 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.341 - -Slack : -16.549 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.279 -Data Delay : 6.344 - -Slack : -16.530 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_G[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.322 - -Slack : -16.526 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.318 - -Slack : -16.526 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.318 - -Slack : -16.524 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.320 - -Slack : -16.524 +Slack : -16.152 From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_G[2] +To Node : VGA_B[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.320 +Clock Skew : -0.273 +Data Delay : 5.953 -Slack : -16.524 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_G[3] +Slack : -16.143 +From Node : ula:ula_|video:video_|attr[0] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.320 +Clock Skew : -0.277 +Data Delay : 5.940 -Slack : -16.523 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.315 - -Slack : -16.472 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.268 - -Slack : -16.469 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.265 - -Slack : -16.469 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 6.265 - -Slack : -16.460 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.279 -Data Delay : 6.255 - -Slack : -16.456 +Slack : -16.127 From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[2] +To Node : VGA_B[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.248 -+--------------------------------------------------------------------------------+ - - - -+--------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; -+--------------------------------------------------------------------------------+ -Slack : -4.423 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.115 -Data Delay : 2.597 - -Slack : -4.388 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 2.680 - -Slack : -4.388 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 2.680 - -Slack : -3.854 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 2.462 - -Slack : -3.854 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 2.462 - -Slack : -3.854 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 2.462 - -Slack : -3.854 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 2.462 - -Slack : -3.854 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 2.462 - -Slack : -3.354 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.264 -Data Delay : 1.997 - -Slack : -2.980 -From Node : AUD_ADCDAT -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.202 -Data Delay : 1.561 - -Slack : 17.465 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 3.012 - -Slack : 17.465 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 3.012 - -Slack : 17.465 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 3.012 - -Slack : 17.465 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 3.012 - -Slack : 17.465 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 3.012 - -Slack : 17.469 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 3.008 - -Slack : 17.469 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 3.008 - -Slack : 17.469 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 3.008 - -Slack : 17.469 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 3.008 - -Slack : 17.469 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 3.008 - -Slack : 17.528 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.949 - -Slack : 17.528 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.949 - -Slack : 17.532 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.945 - -Slack : 17.532 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.945 - -Slack : 17.591 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.886 - -Slack : 17.591 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.886 - -Slack : 17.591 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.886 - -Slack : 17.591 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.886 - -Slack : 17.591 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.886 - -Slack : 17.642 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.835 - -Slack : 17.646 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.831 - -Slack : 17.654 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.823 - -Slack : 17.654 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.823 - -Slack : 17.680 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.797 - -Slack : 17.680 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.797 - -Slack : 17.680 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.797 - -Slack : 17.680 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.797 - -Slack : 17.680 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.797 - -Slack : 17.715 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 3.086 - -Slack : 17.715 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 3.086 - -Slack : 17.715 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 3.086 - -Slack : 17.719 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.758 - -Slack : 17.719 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.758 - -Slack : 17.719 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.758 - -Slack : 17.719 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.758 - -Slack : 17.719 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.758 - -Slack : 17.719 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 3.082 - -Slack : 17.719 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 3.082 - -Slack : 17.719 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 3.082 - -Slack : 17.731 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.746 - -Slack : 17.731 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.746 - -Slack : 17.735 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.742 - -Slack : 17.735 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.742 - -Slack : 17.743 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.734 - -Slack : 17.743 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.734 - -Slack : 17.768 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.709 - -Slack : 17.782 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.695 - -Slack : 17.782 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.695 - -Slack : 17.841 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 2.960 - -Slack : 17.841 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 2.960 - -Slack : 17.841 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 2.960 - -Slack : 17.857 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.620 - -Slack : 17.857 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.620 - -Slack : 17.857 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.620 - -Slack : 17.868 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.609 - -Slack : 17.868 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.609 - -Slack : 17.868 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.609 - -Slack : 17.868 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.609 - -Slack : 17.868 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.609 - -Slack : 17.896 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.581 - -Slack : 17.930 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 2.871 - -Slack : 17.930 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 2.871 - -Slack : 17.930 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 2.871 - -Slack : 17.931 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.546 - -Slack : 17.931 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.546 - -Slack : 17.946 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.531 - -Slack : 17.946 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.531 - -Slack : 17.969 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 2.832 - -Slack : 17.969 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 2.832 - -Slack : 17.969 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 2.832 - -Slack : 17.985 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.492 - -Slack : 17.985 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.492 - -Slack : 18.045 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.432 - -Slack : 18.060 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.733 - -Slack : 18.060 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.733 - -Slack : 18.060 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.733 - -Slack : 18.060 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.733 - -Slack : 18.060 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.733 - -Slack : 18.064 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.729 - -Slack : 18.064 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.729 - -Slack : 18.064 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.729 - -Slack : 18.064 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.729 - -Slack : 18.064 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.729 - -Slack : 18.118 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 2.683 - -Slack : 18.118 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 2.683 - -Slack : 18.118 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.045 -Data Delay : 2.683 - -Slack : 18.134 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.343 - -Slack : 18.134 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.343 - -Slack : 18.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.607 - -Slack : 18.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.607 +Clock Skew : -0.274 +Data Delay : 5.927 + +Slack : -16.121 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.274 +Data Delay : 5.921 + +Slack : -16.113 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.272 +Data Delay : 5.915 + +Slack : -16.111 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 5.912 + +Slack : -16.095 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 5.896 + +Slack : -16.090 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.274 +Data Delay : 5.890 + +Slack : -16.052 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 5.610 + +Slack : -16.036 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 5.837 + +Slack : -16.022 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.277 +Data Delay : 5.819 + +Slack : -16.018 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.277 +Data Delay : 5.815 + +Slack : -15.986 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 5.787 + +Slack : -15.982 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 5.783 + +Slack : -15.961 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 5.762 + +Slack : -15.960 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 5.761 + +Slack : -15.956 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 5.757 + +Slack : -15.952 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.274 +Data Delay : 5.752 + +Slack : -15.931 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.274 +Data Delay : 5.731 + +Slack : -15.928 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 5.729 + +Slack : -15.925 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.274 +Data Delay : 5.725 + +Slack : -15.918 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_G[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.274 +Data Delay : 5.718 + +Slack : -15.915 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 5.716 + +Slack : -15.899 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 5.700 + +Slack : -15.868 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.273 +Data Delay : 5.669 +--------------------------------------------------------------------------------+ @@ -12471,905 +11719,1811 @@ Data Delay : 2.607 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : -3.309 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[3] +Slack : -6.686 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.250 -Data Delay : 1.134 +Clock Skew : -2.012 +Data Delay : 4.774 -Slack : -3.294 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[3] +Slack : -6.590 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.004 +Data Delay : 4.686 + +Slack : -6.554 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.010 +Data Delay : 4.644 + +Slack : -6.499 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.983 +Data Delay : 4.616 + +Slack : -6.497 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.004 +Data Delay : 4.593 + +Slack : -6.479 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.027 +Data Delay : 4.552 + +Slack : -6.476 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.003 +Data Delay : 4.573 + +Slack : -6.457 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.019 +Data Delay : 4.538 + +Slack : -6.451 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -1.965 -Data Delay : 1.404 +Data Delay : 4.586 -Slack : -2.920 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[5] +Slack : -6.417 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.971 +Data Delay : 4.546 + +Slack : -6.411 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.003 +Data Delay : 4.508 + +Slack : -6.338 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.963 +Data Delay : 4.475 + +Slack : -6.321 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.963 +Data Delay : 4.458 + +Slack : -6.320 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.003 +Data Delay : 4.417 + +Slack : -6.306 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.021 +Data Delay : 4.385 + +Slack : -6.299 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.964 +Data Delay : 4.435 + +Slack : -6.296 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.985 +Data Delay : 4.411 + +Slack : -6.294 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.006 +Data Delay : 4.388 + +Slack : -6.293 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.016 +Data Delay : 4.377 + +Slack : -6.292 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.978 +Data Delay : 4.414 + +Slack : -6.291 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.981 +Data Delay : 4.410 + +Slack : -6.289 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.002 +Data Delay : 4.387 + +Slack : -6.278 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.019 +Data Delay : 4.359 + +Slack : -6.270 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.970 +Data Delay : 4.400 + +Slack : -6.264 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.351 + +Slack : -6.253 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.005 +Data Delay : 4.348 + +Slack : -6.237 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.016 +Data Delay : 4.321 + +Slack : -6.215 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.008 +Data Delay : 4.307 + +Slack : -6.207 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.962 +Data Delay : 4.345 + +Slack : -6.203 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.976 +Data Delay : 4.327 + +Slack : -6.198 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.759 +Data Delay : 4.539 + +Slack : -6.179 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.004 +Data Delay : 4.275 + +Slack : -6.173 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.987 +Data Delay : 4.286 + +Slack : -6.161 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.996 +Data Delay : 4.265 + +Slack : -6.145 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.997 +Data Delay : 4.248 + +Slack : -6.145 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.003 +Data Delay : 4.242 + +Slack : -6.142 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.962 +Data Delay : 4.280 + +Slack : -6.128 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.981 +Data Delay : 4.247 + +Slack : -6.124 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.963 +Data Delay : 4.261 + +Slack : -6.106 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.967 +Data Delay : 4.239 + +Slack : -6.102 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.751 +Data Delay : 4.451 + +Slack : -6.091 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.009 +Data Delay : 4.182 + +Slack : -6.091 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.989 +Data Delay : 4.202 + +Slack : -6.091 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.970 +Data Delay : 4.221 + +Slack : -6.072 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.014 +Data Delay : 4.158 + +Slack : -6.065 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.988 +Data Delay : 4.177 + +Slack : -6.064 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.975 +Data Delay : 4.189 + +Slack : -6.063 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.960 +Data Delay : 4.203 + +Slack : -6.062 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.996 +Data Delay : 4.166 + +Slack : -6.055 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.989 +Data Delay : 4.166 + +Slack : -6.051 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.975 +Data Delay : 4.176 + +Slack : -6.051 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.005 +Data Delay : 4.146 + +Slack : -6.040 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.962 +Data Delay : 4.178 + +Slack : -6.039 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.005 +Data Delay : 4.134 + +Slack : -6.036 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.008 +Data Delay : 4.128 + +Slack : -6.026 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.973 +Data Delay : 4.153 + +Slack : -6.022 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -1.954 -Data Delay : 1.041 +Data Delay : 4.168 -Slack : -2.915 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[4] +Slack : -6.019 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.929 -Data Delay : 1.061 +Clock Skew : -1.977 +Data Delay : 4.142 -Slack : -2.903 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[6] +Slack : -6.009 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.954 -Data Delay : 1.024 +Clock Skew : -1.750 +Data Delay : 4.359 -Slack : -2.893 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[5] +Slack : -6.006 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.927 -Data Delay : 1.041 +Clock Skew : -1.955 +Data Delay : 4.151 -Slack : -2.888 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[4] +Slack : -6.004 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.902 -Data Delay : 1.061 +Clock Skew : -2.014 +Data Delay : 4.090 -Slack : -2.877 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[6] +Slack : -6.004 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.927 -Data Delay : 1.025 +Clock Skew : -2.002 +Data Delay : 4.102 -Slack : -2.661 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[0] +Slack : -6.004 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.957 -Data Delay : 0.779 - -Slack : -2.661 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.957 -Data Delay : 0.779 - -Slack : -2.657 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.957 -Data Delay : 0.775 - -Slack : -2.656 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.957 -Data Delay : 0.774 - -Slack : -2.634 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.930 -Data Delay : 0.779 - -Slack : -2.634 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.930 -Data Delay : 0.779 - -Slack : -2.634 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.930 -Data Delay : 0.779 - -Slack : -2.629 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.930 -Data Delay : 0.774 - -Slack : 35.427 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 4.129 - -Slack : 35.439 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.066 -Data Delay : 4.114 - -Slack : 35.461 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 4.095 - -Slack : 35.501 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.066 -Data Delay : 4.052 - -Slack : 35.504 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.066 -Data Delay : 4.049 - -Slack : 35.567 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 4.089 - -Slack : 35.572 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 3.984 - -Slack : 35.580 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.060 -Data Delay : 3.979 - -Slack : 35.606 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.238 +Clock Skew : -1.761 Data Delay : 4.343 -Slack : 35.651 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.001 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 4.005 +Relationship : 0.120 +Clock Skew : -1.969 +Data Delay : 4.132 -Slack : 35.699 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.000 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.957 +Relationship : 0.120 +Clock Skew : -2.008 +Data Delay : 4.092 -Slack : 35.735 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.988 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.921 +Relationship : 0.120 +Clock Skew : -1.964 +Data Delay : 4.124 -Slack : 35.789 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.988 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.066 -Data Delay : 3.764 +Relationship : 0.120 +Clock Skew : -1.750 +Data Delay : 4.338 -Slack : 35.793 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.985 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 3.763 +Relationship : 0.120 +Clock Skew : -1.970 +Data Delay : 4.115 -Slack : 35.811 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.983 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.049 -Data Delay : 3.851 +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.070 -Slack : 35.814 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.978 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.056 -Data Delay : 3.841 +Relationship : 0.120 +Clock Skew : -2.002 +Data Delay : 4.076 -Slack : 35.838 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.973 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 3.718 +Relationship : 0.120 +Clock Skew : -2.021 +Data Delay : 4.052 -Slack : 35.848 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.972 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.066 -Data Delay : 3.705 - -Slack : 35.861 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.234 -Data Delay : 4.084 - -Slack : 35.872 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.784 - -Slack : 35.913 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.234 -Data Delay : 4.032 - -Slack : 35.914 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.261 +Relationship : 0.120 +Clock Skew : -2.014 Data Delay : 4.058 -Slack : 35.943 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.970 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.261 -Data Delay : 4.029 +Relationship : 0.120 +Clock Skew : -1.989 +Data Delay : 4.081 -Slack : 35.944 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.965 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.255 +Relationship : 0.120 +Clock Skew : -1.985 +Data Delay : 4.080 + +Slack : -5.963 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.016 +Data Delay : 4.047 + +Slack : -5.955 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.042 + +Slack : -5.952 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.960 +Data Delay : 4.092 + +Slack : -5.950 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.980 +Data Delay : 4.070 + +Slack : -5.939 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.014 +Data Delay : 4.025 + +Slack : -5.937 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.015 Data Delay : 4.022 -Slack : 35.957 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.933 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.066 -Data Delay : 3.596 +Relationship : 0.120 +Clock Skew : -1.759 +Data Delay : 4.274 -Slack : 35.963 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.931 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.693 +Relationship : 0.120 +Clock Skew : -2.003 +Data Delay : 4.028 -Slack : 35.965 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|frame[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.930 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.691 +Relationship : 0.120 +Clock Skew : -1.965 +Data Delay : 4.065 -Slack : 35.973 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.927 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.051 -Data Delay : 3.687 +Relationship : 0.120 +Clock Skew : -2.016 +Data Delay : 4.011 -Slack : 35.977 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.923 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.256 -Data Delay : 3.990 +Relationship : 0.120 +Clock Skew : -1.750 +Data Delay : 4.273 -Slack : 35.987 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.908 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.056 -Data Delay : 3.668 +Relationship : 0.120 +Clock Skew : -1.994 +Data Delay : 4.014 -Slack : 35.989 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.896 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.667 +Relationship : 0.120 +Clock Skew : -1.984 +Data Delay : 4.012 -Slack : 35.993 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.887 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.240 -Data Delay : 3.958 +Relationship : 0.120 +Clock Skew : -2.002 +Data Delay : 3.985 -Slack : 36.056 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.884 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 3.500 +Relationship : 0.120 +Clock Skew : -2.000 +Data Delay : 3.984 -Slack : 36.063 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.884 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 3.493 +Relationship : 0.120 +Clock Skew : -2.012 +Data Delay : 3.972 -Slack : 36.066 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.877 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.052 -Data Delay : 3.593 +Relationship : 0.120 +Clock Skew : -1.966 +Data Delay : 4.011 -Slack : 36.074 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.874 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.062 -Data Delay : 3.483 +Relationship : 0.120 +Clock Skew : -1.976 +Data Delay : 3.998 -Slack : 36.089 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.870 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 3.467 +Relationship : 0.120 +Clock Skew : -2.000 +Data Delay : 3.970 -Slack : 36.101 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.857 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.230 -Data Delay : 3.840 +Relationship : 0.120 +Clock Skew : -2.002 +Data Delay : 3.955 -Slack : 36.104 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.836 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.056 -Data Delay : 3.551 +Relationship : 0.120 +Clock Skew : -1.963 +Data Delay : 3.973 -Slack : 36.138 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|frame[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.826 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.518 +Relationship : 0.120 +Clock Skew : 0.180 +Data Delay : 4.106 -Slack : 36.164 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.816 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.492 +Relationship : 0.120 +Clock Skew : -1.964 +Data Delay : 3.952 -Slack : 36.167 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|attr_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.814 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.229 -Data Delay : 3.773 +Relationship : 0.120 +Clock Skew : -1.974 +Data Delay : 3.940 -Slack : 36.168 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.804 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.488 +Relationship : 0.120 +Clock Skew : 0.188 +Data Delay : 4.092 -Slack : 36.173 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -5.794 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.254 -Data Delay : 3.792 +Relationship : 0.120 +Clock Skew : -1.993 +Data Delay : 3.901 ++--------------------------------------------------------------------------------+ -Slack : 36.173 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.483 -Slack : 36.183 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.473 -Slack : 36.190 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.466 ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : -4.428 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.115 +Data Delay : 2.602 -Slack : 36.198 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 3.358 +Slack : -4.267 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 2.559 -Slack : 36.202 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.236 -Data Delay : 3.745 +Slack : -4.267 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 2.559 -Slack : 36.202 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.257 -Data Delay : 3.766 +Slack : -4.074 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 2.366 -Slack : 36.220 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.436 +Slack : -4.074 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 2.366 -Slack : 36.230 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.057 -Data Delay : 3.424 +Slack : -4.074 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 2.366 -Slack : 36.230 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.057 -Data Delay : 3.424 +Slack : -4.074 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 2.366 -Slack : 36.231 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.066 -Data Delay : 3.322 +Slack : -4.074 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 2.366 -Slack : 36.239 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.251 -Data Delay : 3.723 +Slack : -3.711 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 2.003 -Slack : 36.239 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.257 -Data Delay : 3.729 +Slack : -2.966 +From Node : AUD_ADCDAT +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.208 +Data Delay : 1.553 -Slack : 36.240 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 +Slack : 17.237 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.241 + +Slack : 17.242 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.236 + +Slack : 17.361 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.117 + +Slack : 17.361 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.117 + +Slack : 17.362 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.116 + +Slack : 17.366 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.112 + +Slack : 17.366 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.112 + +Slack : 17.421 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.057 + +Slack : 17.421 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.057 + +Slack : 17.421 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.057 + +Slack : 17.421 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.057 + +Slack : 17.426 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.052 + +Slack : 17.426 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.052 + +Slack : 17.426 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.052 + +Slack : 17.426 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.052 + +Slack : 17.453 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 3.025 + +Slack : 17.488 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.990 + +Slack : 17.488 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.990 + +Slack : 17.495 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.983 + +Slack : 17.495 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.983 + +Slack : 17.500 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.978 + +Slack : 17.500 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.978 + +Slack : 17.528 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.949 + +Slack : 17.528 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.949 + +Slack : 17.533 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.944 + +Slack : 17.533 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.944 + +Slack : 17.548 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.930 + +Slack : 17.548 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.930 + +Slack : 17.548 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.930 + +Slack : 17.548 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.930 + +Slack : 17.577 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.901 + +Slack : 17.577 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.901 + +Slack : 17.604 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.874 + +Slack : 17.604 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.874 + +Slack : 17.604 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.874 + +Slack : 17.604 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.874 + +Slack : 17.604 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.874 + +Slack : 17.609 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.869 + +Slack : 17.609 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.869 + +Slack : 17.609 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.869 + +Slack : 17.609 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.869 + +Slack : 17.609 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.869 + +Slack : 17.618 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.860 + +Slack : 17.622 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.856 + +Slack : 17.622 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.856 + +Slack : 17.637 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.841 + +Slack : 17.637 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.841 + +Slack : 17.637 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.841 + +Slack : 17.637 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.841 + +Slack : 17.655 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.822 + +Slack : 17.655 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.822 + +Slack : 17.711 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.767 + +Slack : 17.711 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.767 + +Slack : 17.731 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.747 + +Slack : 17.731 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.747 + +Slack : 17.731 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.747 + +Slack : 17.731 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.747 + +Slack : 17.731 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.747 + +Slack : 17.742 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.736 + +Slack : 17.742 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.736 + +Slack : 17.744 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.733 + +Slack : 17.744 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.733 + +Slack : 17.770 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.707 + +Slack : 17.775 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.702 + +Slack : 17.802 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.676 + +Slack : 17.802 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.676 + +Slack : 17.802 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.676 + +Slack : 17.802 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.676 + +Slack : 17.820 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.658 + +Slack : 17.820 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.658 + +Slack : 17.820 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.658 + +Slack : 17.820 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.658 + +Slack : 17.820 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.658 + +Slack : 17.831 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.647 + +Slack : 17.876 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.602 + +Slack : 17.876 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.602 + +Slack : 17.890 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 Clock Skew : -0.049 -Data Delay : 3.422 +Data Delay : 2.907 -Slack : 36.247 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.409 +Slack : 17.895 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.049 +Data Delay : 2.902 -Slack : 36.255 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|frame[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.401 +Slack : 17.897 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.580 -Slack : 36.257 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.252 -Data Delay : 3.706 +Slack : 17.909 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.568 -Slack : 36.288 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.056 -Data Delay : 3.367 +Slack : 17.909 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.568 -Slack : 36.293 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.063 -Data Delay : 3.263 +Slack : 17.955 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.523 -Slack : 36.298 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.056 -Data Delay : 3.357 +Slack : 17.955 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.523 -Slack : 36.300 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.263 -Data Delay : 3.674 +Slack : 17.985 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.493 -Slack : 36.304 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.352 +Slack : 17.985 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.493 -Slack : 36.305 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.056 -Data Delay : 3.350 +Slack : 17.985 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.493 -Slack : 36.306 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.350 +Slack : 17.985 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.493 -Slack : 36.308 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.348 +Slack : 17.985 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.493 -Slack : 36.309 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.347 +Slack : 17.986 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.491 -Slack : 36.310 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.346 - -Slack : 36.311 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.345 - -Slack : 36.312 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.344 - -Slack : 36.312 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.344 - -Slack : 36.312 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.344 - -Slack : 36.312 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.344 - -Slack : 36.325 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.331 - -Slack : 36.326 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.055 -Data Delay : 3.330 - -Slack : 36.330 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.263 -Data Delay : 3.644 - -Slack : 36.331 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.257 -Data Delay : 3.637 - -Slack : 36.333 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_hc[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.059 -Data Delay : 3.319 - -Slack : 36.337 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.059 -Data Delay : 3.315 - -Slack : 36.354 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|attr_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.227 -Data Delay : 3.584 - -Slack : 36.355 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.258 -Data Delay : 3.614 - -Slack : 36.366 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.064 -Data Delay : 3.189 +Slack : 18.007 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.396 +Data Delay : 2.353 +--------------------------------------------------------------------------------+ @@ -13416,912 +13570,6 @@ Data Delay : 0.583 -+--------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; -+--------------------------------------------------------------------------------+ -Slack : -0.780 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.250 -Data Delay : 1.743 - -Slack : -0.772 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.253 -Data Delay : 1.754 - -Slack : -0.769 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.256 -Data Delay : 1.760 - -Slack : -0.757 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.257 -Data Delay : 1.773 - -Slack : -0.754 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 1.759 - -Slack : -0.751 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.769 - -Slack : -0.748 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 1.770 - -Slack : -0.748 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.246 -Data Delay : 1.771 - -Slack : -0.744 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 1.769 - -Slack : -0.739 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.781 - -Slack : -0.734 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.786 - -Slack : -0.733 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.787 - -Slack : -0.731 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.244 -Data Delay : 1.786 - -Slack : -0.729 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 1.784 - -Slack : -0.728 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.253 -Data Delay : 1.798 - -Slack : -0.725 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 1.793 - -Slack : -0.724 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 1.792 - -Slack : -0.719 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.256 -Data Delay : 1.810 - -Slack : -0.717 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.803 - -Slack : -0.717 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.254 -Data Delay : 1.810 - -Slack : -0.713 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.807 - -Slack : -0.713 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.254 -Data Delay : 1.814 - -Slack : -0.712 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.246 -Data Delay : 1.807 - -Slack : -0.711 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.257 -Data Delay : 1.819 - -Slack : -0.710 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.246 -Data Delay : 1.809 - -Slack : -0.709 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 1.809 - -Slack : -0.709 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.811 - -Slack : -0.708 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.250 -Data Delay : 1.815 - -Slack : -0.706 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.256 -Data Delay : 1.823 - -Slack : -0.705 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.257 -Data Delay : 1.825 - -Slack : -0.704 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 1.814 - -Slack : -0.702 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.257 -Data Delay : 1.828 - -Slack : -0.702 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 1.811 - -Slack : -0.701 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 1.812 - -Slack : -0.700 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.820 - -Slack : -0.700 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.250 -Data Delay : 1.823 - -Slack : -0.699 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 1.819 - -Slack : -0.698 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 1.818 - -Slack : -0.697 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.823 - -Slack : -0.697 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 1.816 - -Slack : -0.696 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 1.822 - -Slack : -0.692 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.244 -Data Delay : 1.825 - -Slack : -0.691 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 1.825 - -Slack : -0.691 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.246 -Data Delay : 1.828 - -Slack : -0.690 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.830 - -Slack : -0.690 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 1.828 - -Slack : -0.690 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.246 -Data Delay : 1.829 - -Slack : -0.690 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.830 - -Slack : -0.689 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.831 - -Slack : -0.688 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.246 -Data Delay : 1.831 - -Slack : -0.685 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.835 - -Slack : -0.685 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.256 -Data Delay : 1.844 - -Slack : -0.684 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.244 -Data Delay : 1.833 - -Slack : -0.684 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.250 -Data Delay : 1.839 - -Slack : -0.681 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.839 - -Slack : -0.681 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.839 - -Slack : -0.681 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 1.832 - -Slack : -0.680 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 1.836 - -Slack : -0.680 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.244 -Data Delay : 1.837 - -Slack : -0.680 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 1.833 - -Slack : -0.678 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.250 -Data Delay : 1.845 - -Slack : -0.677 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 1.836 - -Slack : -0.676 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 1.842 - -Slack : -0.676 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.844 - -Slack : -0.674 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.846 - -Slack : -0.674 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 1.839 - -Slack : -0.673 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 1.843 - -Slack : -0.673 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.847 - -Slack : -0.672 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.848 - -Slack : -0.672 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 1.844 - -Slack : -0.672 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.246 -Data Delay : 1.847 - -Slack : -0.672 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.848 - -Slack : -0.670 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.244 -Data Delay : 1.847 - -Slack : -0.670 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.850 - -Slack : -0.669 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.254 -Data Delay : 1.858 - -Slack : -0.668 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.253 -Data Delay : 1.858 - -Slack : -0.667 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.853 - -Slack : -0.666 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 1.852 - -Slack : -0.666 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.854 - -Slack : -0.665 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.241 -Data Delay : 1.849 - -Slack : -0.665 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 1.848 - -Slack : -0.664 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 1.854 - -Slack : -0.664 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.244 -Data Delay : 1.853 - -Slack : -0.664 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.253 -Data Delay : 1.862 - -Slack : -0.662 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.246 -Data Delay : 1.857 - -Slack : -0.662 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.858 - -Slack : -0.661 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 1.855 - -Slack : -0.661 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.859 - -Slack : -0.661 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.859 - -Slack : -0.660 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.246 -Data Delay : 1.859 - -Slack : -0.658 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.862 - -Slack : -0.657 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.236 -Data Delay : 1.852 - -Slack : -0.656 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.254 -Data Delay : 1.871 - -Slack : -0.656 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.236 -Data Delay : 1.853 - -Slack : -0.655 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 1.861 - -Slack : -0.654 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.866 - -Slack : -0.651 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 1.869 - -Slack : -0.651 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 1.862 - -Slack : -0.650 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 1.866 - -Slack : -0.650 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 1.866 -+--------------------------------------------------------------------------------+ - - - +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +--------------------------------------------------------------------------------+ @@ -14367,36 +13615,18 @@ Data Delay : 1.091 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 0.298 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.511 - -Slack : 0.298 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.511 - -Slack : 0.299 +Slack : 0.300 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.068 +Clock Skew : 0.067 Data Delay : 0.511 Slack : 0.306 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -14413,41 +13643,14 @@ Clock Skew : 0.069 Data Delay : 0.519 Slack : 0.307 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.068 Data Delay : 0.519 -Slack : 0.307 -From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.519 - -Slack : 0.311 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.511 - -Slack : 0.311 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.511 - Slack : 0.311 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack @@ -14458,17 +13661,8 @@ Clock Skew : 0.056 Data Delay : 0.511 Slack : 0.311 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.511 - -Slack : 0.311 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -14485,8 +13679,53 @@ Clock Skew : 0.056 Data Delay : 0.511 Slack : 0.312 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -14511,6 +13750,24 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.511 +Slack : 0.312 +From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.319 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.519 + Slack : 0.319 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] @@ -14521,157 +13778,148 @@ Clock Skew : 0.056 Data Delay : 0.519 Slack : 0.320 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.519 -Slack : 0.328 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.541 - -Slack : 0.338 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.537 - -Slack : 0.339 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.538 - -Slack : 0.339 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.538 - -Slack : 0.340 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.539 - -Slack : 0.340 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.539 - -Slack : 0.340 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.539 - -Slack : 0.340 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.539 - -Slack : 0.341 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.540 - -Slack : 0.351 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.551 - -Slack : 0.353 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.552 - -Slack : 0.359 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.571 - -Slack : 0.369 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.569 - -Slack : 0.373 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.573 - -Slack : 0.381 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.581 - -Slack : 0.489 +Slack : 0.322 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.069 -Data Delay : 0.702 +Data Delay : 0.535 + +Slack : 0.339 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.538 + +Slack : 0.342 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.541 + +Slack : 0.342 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.541 + +Slack : 0.344 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.543 + +Slack : 0.361 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.561 + +Slack : 0.363 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.563 + +Slack : 0.418 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.631 + +Slack : 0.418 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.631 + +Slack : 0.419 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.632 + +Slack : 0.419 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.632 + +Slack : 0.421 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.634 + +Slack : 0.469 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.668 + +Slack : 0.474 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.673 + +Slack : 0.487 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.700 Slack : 0.490 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] @@ -14682,203 +13930,203 @@ Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.703 -Slack : 0.490 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 0.491 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.703 +Clock Skew : 0.096 +Data Delay : 0.731 -Slack : 0.491 +Slack : 0.492 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.069 -Data Delay : 0.704 +Data Delay : 0.705 -Slack : 0.492 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.691 - -Slack : 0.495 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.694 - -Slack : 0.496 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.695 - -Slack : 0.497 +Slack : 0.498 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.696 - -Slack : 0.497 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.696 - -Slack : 0.498 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 Data Delay : 0.697 -Slack : 0.500 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.699 - -Slack : 0.500 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.699 - -Slack : 0.500 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.700 - -Slack : 0.501 +Slack : 0.499 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 +Data Delay : 0.698 + +Slack : 0.501 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 Data Delay : 0.700 Slack : 0.501 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.701 - -Slack : 0.502 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.702 - -Slack : 0.502 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.715 - -Slack : 0.503 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.716 - -Slack : 0.503 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.069 +Data Delay : 0.714 + +Slack : 0.502 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.701 + +Slack : 0.503 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.702 + +Slack : 0.503 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 Data Delay : 0.716 -Slack : 0.509 +Slack : 0.507 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.706 + +Slack : 0.508 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.709 +Clock Skew : 0.055 +Data Delay : 0.707 -Slack : 0.517 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Slack : 0.514 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.717 +Clock Skew : 0.069 +Data Delay : 0.727 -Slack : 0.520 +Slack : 0.515 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.728 + +Slack : 0.516 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.720 +Clock Skew : 0.055 +Data Delay : 0.715 -Slack : 0.521 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Slack : 0.518 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.733 +Clock Skew : 0.069 +Data Delay : 0.731 -Slack : 0.528 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Slack : 0.518 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.740 +Clock Skew : 0.069 +Data Delay : 0.731 + +Slack : 0.518 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.731 + +Slack : 0.518 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.731 + +Slack : 0.518 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.731 + +Slack : 0.518 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.717 + +Slack : 0.519 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.732 + +Slack : 0.520 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.719 Slack : 0.529 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] @@ -14889,176 +14137,221 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.728 -Slack : 0.529 +Slack : 0.532 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.387 +Data Delay : 1.063 + +Slack : 0.537 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.736 + +Slack : 0.538 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.737 + +Slack : 0.539 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.738 + +Slack : 0.547 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.741 - -Slack : 0.533 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 +Clock Skew : 0.055 Data Delay : 0.746 -Slack : 0.534 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Slack : 0.548 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.746 - -Slack : 0.535 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 +Clock Skew : 0.055 Data Delay : 0.747 -Slack : 0.538 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Slack : 0.561 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.761 + +Slack : 0.563 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 0.738 +Data Delay : 0.763 -Slack : 0.590 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.802 - -Slack : 0.615 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.181 - -Slack : 0.618 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.830 - -Slack : 0.618 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.830 - -Slack : 0.619 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.818 - -Slack : 0.624 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : -0.231 -Data Delay : 0.537 - -Slack : 0.628 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.840 - -Slack : 0.649 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.067 -Data Delay : 0.860 - -Slack : 0.651 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.217 - -Slack : 0.675 +Slack : 0.565 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.887 +Clock Skew : 0.055 +Data Delay : 0.764 -Slack : 0.698 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Slack : 0.599 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.264 +Clock Skew : 0.056 +Data Delay : 0.799 -Slack : 0.699 +Slack : 0.605 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.805 + +Slack : 0.630 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.829 + +Slack : 0.668 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.265 +Data Delay : 0.547 + +Slack : 0.701 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.901 + +Slack : 0.701 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.901 + +Slack : 0.706 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.905 + +Slack : 0.709 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.908 + +Slack : 0.709 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.907 + +Slack : 0.710 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.908 + +Slack : 0.714 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 0.899 +Data Delay : 0.914 -Slack : 0.713 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Slack : 0.721 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.925 +Clock Skew : 0.056 +Data Delay : 0.921 -Slack : 0.722 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Slack : 0.728 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.934 +Clock Skew : 0.055 +Data Delay : 0.927 + +Slack : 0.729 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.928 + +Slack : 0.731 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.944 Slack : 0.735 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] @@ -15069,62 +14362,8 @@ Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.948 -Slack : 0.735 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.948 - -Slack : 0.736 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.274 - -Slack : 0.736 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.274 - -Slack : 0.737 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.275 - -Slack : 0.737 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.949 - -Slack : 0.737 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.949 - Slack : 0.738 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -15133,8 +14372,8 @@ Clock Skew : 0.069 Data Delay : 0.951 Slack : 0.740 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -15142,52 +14381,34 @@ Clock Skew : 0.069 Data Delay : 0.953 Slack : 0.741 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.954 -Slack : 0.743 +Slack : 0.744 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.943 -Slack : 0.744 +Slack : 0.745 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.944 -Slack : 0.744 -From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.070 -Data Delay : 0.958 - Slack : 0.745 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.945 - -Slack : 0.745 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -15196,26 +14417,17 @@ Clock Skew : 0.069 Data Delay : 0.958 Slack : 0.746 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.382 -Data Delay : 1.272 +Clock Skew : 0.055 +Data Delay : 0.945 Slack : 0.747 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.382 -Data Delay : 1.273 - -Slack : 0.747 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -15223,49 +14435,991 @@ Clock Skew : 0.069 Data Delay : 0.960 Slack : 0.748 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.961 -Slack : 0.752 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.952 - -Slack : 0.752 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.952 - -Slack : 0.757 +Slack : 0.749 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.067 -Data Delay : 0.968 +Clock Skew : -0.261 +Data Delay : 0.632 -Slack : 0.758 +Slack : 0.750 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.962 + +Slack : 0.753 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.952 + +Slack : 0.760 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.959 + +Slack : 0.764 +From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.964 + +Slack : 0.770 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.969 + +Slack : 0.772 From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.070 +Clock Skew : 0.056 Data Delay : 0.972 + +Slack : 0.773 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.972 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : 0.304 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.304 +Data Delay : 2.881 + +Slack : 0.359 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.305 +Data Delay : 2.937 + +Slack : 1.206 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.252 +Data Delay : 3.731 + +Slack : 1.215 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.251 +Data Delay : 3.739 + +Slack : 1.221 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.255 +Data Delay : 3.749 + +Slack : 1.229 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.744 + +Slack : 1.234 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.252 +Data Delay : 3.759 + +Slack : 1.240 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.245 +Data Delay : 3.758 + +Slack : 1.262 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.773 + +Slack : 1.264 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.255 +Data Delay : 3.792 + +Slack : 1.266 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.245 +Data Delay : 3.784 + +Slack : 1.278 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.793 + +Slack : 1.287 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.802 + +Slack : 1.332 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.248 +Data Delay : 3.853 + +Slack : 1.340 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.245 +Data Delay : 3.858 + +Slack : 1.351 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.864 + +Slack : 1.367 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.241 +Data Delay : 3.881 + +Slack : 1.373 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.251 +Data Delay : 3.897 + +Slack : 1.373 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.883 + +Slack : 1.378 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.247 +Data Delay : 3.898 + +Slack : 1.378 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.881 + +Slack : 1.379 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.894 + +Slack : 1.379 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.892 + +Slack : 1.383 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.886 + +Slack : 1.384 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.234 +Data Delay : 3.891 + +Slack : 1.389 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.904 + +Slack : 1.393 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.896 + +Slack : 1.394 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.909 + +Slack : 1.396 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.911 + +Slack : 1.400 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.911 + +Slack : 1.401 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.904 + +Slack : 1.402 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.233 +Data Delay : 3.908 + +Slack : 1.405 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.247 +Data Delay : 3.925 + +Slack : 1.407 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.241 +Data Delay : 3.921 + +Slack : 1.410 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.923 + +Slack : 1.410 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.241 +Data Delay : 3.924 + +Slack : 1.412 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.927 + +Slack : 1.413 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.233 +Data Delay : 3.919 + +Slack : 1.417 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.930 + +Slack : 1.417 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.920 + +Slack : 1.425 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.251 +Data Delay : 3.949 + +Slack : 1.433 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.248 +Data Delay : 3.954 + +Slack : 1.434 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.234 +Data Delay : 3.941 + +Slack : 1.435 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.938 + +Slack : 1.435 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.245 +Data Delay : 3.953 + +Slack : 1.436 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.947 + +Slack : 1.440 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.950 + +Slack : 1.442 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.243 +Data Delay : 3.958 + +Slack : 1.449 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.960 + +Slack : 1.451 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.234 +Data Delay : 3.958 + +Slack : 1.452 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.310 +Data Delay : 4.035 + +Slack : 1.452 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.962 + +Slack : 1.453 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.964 + +Slack : 1.454 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.233 +Data Delay : 3.960 + +Slack : 1.455 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.326 +Data Delay : 4.054 + +Slack : 1.455 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.090 +Data Delay : 3.818 + +Slack : 1.455 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.248 +Data Delay : 3.976 + +Slack : 1.458 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.248 +Data Delay : 3.979 + +Slack : 1.460 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.975 + +Slack : 1.460 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.243 +Data Delay : 3.976 + +Slack : 1.460 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.241 +Data Delay : 3.974 + +Slack : 1.460 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.235 +Data Delay : 3.968 + +Slack : 1.461 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.233 +Data Delay : 3.967 + +Slack : 1.465 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.253 +Data Delay : 3.991 + +Slack : 1.465 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.234 +Data Delay : 3.972 + +Slack : 1.466 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.231 +Data Delay : 3.970 + +Slack : 1.467 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.231 +Data Delay : 3.971 + +Slack : 1.471 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.252 +Data Delay : 3.996 + +Slack : 1.473 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.976 + +Slack : 1.476 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.987 + +Slack : 1.480 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.251 +Data Delay : 4.004 + +Slack : 1.481 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.301 +Data Delay : 4.055 + +Slack : 1.482 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.997 + +Slack : 1.485 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.988 + +Slack : 1.485 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.245 +Data Delay : 4.003 + +Slack : 1.487 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.234 +Data Delay : 3.994 + +Slack : 1.487 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.309 +Data Delay : 4.069 + +Slack : 1.489 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 4.004 + +Slack : 1.490 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.239 +Data Delay : 4.002 + +Slack : 1.492 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.995 + +Slack : 1.493 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 4.008 + +Slack : 1.494 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 4.004 + +Slack : 1.494 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.241 +Data Delay : 4.008 + +Slack : 1.496 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.234 +Data Delay : 4.003 + +Slack : 1.498 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 4.009 + +Slack : 1.498 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 4.009 + +Slack : 1.499 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.322 +Data Delay : 4.094 + +Slack : 1.502 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 4.005 + +Slack : 1.503 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 4.014 + +Slack : 1.504 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.231 +Data Delay : 4.008 + +Slack : 1.505 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.248 +Data Delay : 4.026 + +Slack : 1.507 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.252 +Data Delay : 4.032 + +Slack : 1.508 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.246 +Data Delay : 4.027 + +Slack : 1.509 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 4.024 + +Slack : 1.510 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.252 +Data Delay : 4.035 + +Slack : 1.510 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.081 +Data Delay : 3.864 + +Slack : 1.511 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.233 +Data Delay : 4.017 + +Slack : 1.513 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 4.023 + +Slack : 1.513 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.234 +Data Delay : 4.020 + +Slack : 1.520 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.234 +Data Delay : 4.027 +--------------------------------------------------------------------------------+ @@ -15309,15 +15463,6 @@ Relationship : 0.000 Clock Skew : 0.056 Data Delay : 0.511 -Slack : 0.311 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.511 - Slack : 0.312 From Node : ula:ula_|video:video_|vga_vc[9] To Node : ula:ula_|video:video_|vga_vc[9] @@ -15355,8 +15500,8 @@ Clock Skew : 0.055 Data Delay : 0.511 Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vga_vc[3] +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vga_vc[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -15390,788 +15535,797 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.511 -Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vga_vc[8] +Slack : 0.493 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.511 +Data Delay : 0.692 -Slack : 0.630 +Slack : 0.498 From Node : ula:ula_|video:video_|frame[3] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.829 +Data Delay : 0.697 -Slack : 0.758 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vram_address[10] +Slack : 0.509 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 0.961 +Clock Skew : 0.055 +Data Delay : 0.708 -Slack : 0.846 -From Node : ula:ula_|video:video_|bits_prefetch[3] -To Node : ula:ula_|video:video_|bits[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.050 -Data Delay : 1.040 - -Slack : 0.861 +Slack : 0.512 From Node : ula:ula_|video:video_|frame[4] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.060 +Data Delay : 0.711 -Slack : 0.924 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.127 - -Slack : 0.925 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[6] +Slack : 0.596 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.124 +Data Delay : 0.795 -Slack : 0.984 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.051 -Data Delay : 1.179 - -Slack : 0.988 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.051 -Data Delay : 1.183 - -Slack : 0.988 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.051 -Data Delay : 1.183 - -Slack : 1.060 -From Node : ula:ula_|video:video_|attr_prefetch[3] -To Node : ula:ula_|video:video_|attr[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.235 -Data Delay : 0.969 - -Slack : 1.074 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.271 - -Slack : 1.092 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vram_address[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.051 -Data Delay : 1.287 - -Slack : 1.095 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.294 - -Slack : 1.099 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.051 -Data Delay : 1.294 - -Slack : 1.106 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.051 -Data Delay : 1.301 - -Slack : 1.109 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.051 -Data Delay : 1.304 - -Slack : 1.124 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.323 - -Slack : 1.135 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.333 - -Slack : 1.139 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.051 -Data Delay : 1.334 - -Slack : 1.152 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.355 - -Slack : 1.173 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.372 - -Slack : 1.176 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.375 - -Slack : 1.177 -From Node : ula:ula_|video:video_|bits_prefetch[1] -To Node : ula:ula_|video:video_|bits[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.240 -Data Delay : 1.081 - -Slack : 1.182 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.382 - -Slack : 1.184 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.383 - -Slack : 1.184 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.383 - -Slack : 1.194 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.393 - -Slack : 1.207 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.406 - -Slack : 1.223 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vga_hc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.426 - -Slack : 1.230 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vga_hc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.433 - -Slack : 1.241 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.440 - -Slack : 1.242 -From Node : ula:ula_|video:video_|attr_prefetch[1] -To Node : ula:ula_|video:video_|attr[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.267 -Data Delay : 1.119 - -Slack : 1.248 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.447 - -Slack : 1.258 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.457 - -Slack : 1.267 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.466 - -Slack : 1.270 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.469 - -Slack : 1.278 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.477 - -Slack : 1.284 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.487 - -Slack : 1.297 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.497 - -Slack : 1.305 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.504 - -Slack : 1.306 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.505 - -Slack : 1.306 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.505 - -Slack : 1.316 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.515 - -Slack : 1.319 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.518 - -Slack : 1.322 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.521 - -Slack : 1.330 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.058 -Data Delay : 1.532 - -Slack : 1.337 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.536 - -Slack : 1.338 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.537 - -Slack : 1.346 -From Node : ula:ula_|video:video_|attr_prefetch[0] -To Node : ula:ula_|video:video_|attr[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.236 -Data Delay : 1.254 - -Slack : 1.346 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_hc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.545 - -Slack : 1.351 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.550 - -Slack : 1.352 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vga_vc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.551 - -Slack : 1.354 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.553 - -Slack : 1.359 -From Node : ula:ula_|video:video_|bits_prefetch[0] -To Node : ula:ula_|video:video_|bits[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.263 -Data Delay : 1.240 - -Slack : 1.360 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.559 - -Slack : 1.368 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.567 - -Slack : 1.382 +Slack : 0.652 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|vram_address[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.585 - -Slack : 1.390 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 1.590 +Data Delay : 0.852 -Slack : 1.393 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.599 - -Slack : 1.396 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vga_hc[4] +Slack : 0.737 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.595 +Data Delay : 0.936 -Slack : 1.396 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.058 -Data Delay : 1.598 - -Slack : 1.398 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.058 -Data Delay : 1.600 - -Slack : 1.403 +Slack : 0.747 From Node : ula:ula_|video:video_|frame[3] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.602 +Data Delay : 0.946 -Slack : 1.404 +Slack : 0.748 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.947 + +Slack : 0.751 From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.957 + +Slack : 0.755 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.603 +Data Delay : 0.954 -Slack : 1.407 -From Node : ula:ula_|video:video_|bits_prefetch[4] -To Node : ula:ula_|video:video_|bits[4] +Slack : 0.778 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_hc[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.270 -Data Delay : 1.281 +Clock Skew : 0.056 +Data Delay : 0.978 -Slack : 1.412 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[9] +Slack : 0.826 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.611 +Data Delay : 1.025 -Slack : 1.412 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[9] +Slack : 0.839 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.611 +Data Delay : 1.038 -Slack : 1.413 +Slack : 0.844 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.043 + +Slack : 0.885 From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.612 +Clock Skew : 0.062 +Data Delay : 1.091 -Slack : 1.416 +Slack : 0.901 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.107 + +Slack : 0.911 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.059 +Data Delay : 1.114 + +Slack : 0.986 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.191 + +Slack : 0.987 From Node : ula:ula_|video:video_|vga_hc[2] To Node : ula:ula_|video:video_|vram_address[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.058 -Data Delay : 1.618 +Clock Skew : 0.061 +Data Delay : 1.192 -Slack : 1.423 +Slack : 0.996 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.201 + +Slack : 0.996 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.201 + +Slack : 1.019 +From Node : ula:ula_|video:video_|bits_prefetch[6] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.271 +Data Delay : 0.892 + +Slack : 1.022 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.228 + +Slack : 1.025 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.231 + +Slack : 1.039 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.245 + +Slack : 1.040 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.271 +Data Delay : 0.913 + +Slack : 1.041 +From Node : ula:ula_|video:video_|bits_prefetch[1] +To Node : ula:ula_|video:video_|bits[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.271 +Data Delay : 0.914 + +Slack : 1.050 +From Node : ula:ula_|video:video_|bits_prefetch[5] +To Node : ula:ula_|video:video_|bits[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.271 +Data Delay : 0.923 + +Slack : 1.062 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.268 + +Slack : 1.070 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.269 + +Slack : 1.082 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.281 + +Slack : 1.106 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.312 + +Slack : 1.130 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.336 + +Slack : 1.143 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.349 + +Slack : 1.145 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.345 + +Slack : 1.145 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.345 + +Slack : 1.145 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.345 + +Slack : 1.145 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.345 + +Slack : 1.151 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.357 + +Slack : 1.153 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vga_hc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.353 + +Slack : 1.154 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.360 + +Slack : 1.166 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.365 + +Slack : 1.168 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.374 + +Slack : 1.170 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.057 +Data Delay : 1.371 + +Slack : 1.172 +From Node : ula:ula_|video:video_|bits_prefetch[0] +To Node : ula:ula_|video:video_|bits[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.271 +Data Delay : 1.045 + +Slack : 1.174 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.374 + +Slack : 1.176 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|vga_hc[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.376 + +Slack : 1.176 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.376 + +Slack : 1.182 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.298 +Data Delay : 1.028 + +Slack : 1.183 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.389 + +Slack : 1.184 +From Node : ula:ula_|video:video_|bits_prefetch[4] +To Node : ula:ula_|video:video_|bits[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.271 +Data Delay : 1.057 + +Slack : 1.200 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.406 + +Slack : 1.207 +From Node : ula:ula_|video:video_|attr_prefetch[5] +To Node : ula:ula_|video:video_|attr[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.298 +Data Delay : 1.053 + +Slack : 1.219 From Node : ula:ula_|video:video_|vga_vc[4] To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.622 +Clock Skew : 0.062 +Data Delay : 1.425 -Slack : 1.431 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[6] +Slack : 1.223 +From Node : ula:ula_|video:video_|attr_prefetch[7] +To Node : ula:ula_|video:video_|attr[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.630 +Clock Skew : -0.298 +Data Delay : 1.069 -Slack : 1.436 -From Node : ula:ula_|video:video_|vga_hc[4] +Slack : 1.225 +From Node : ula:ula_|video:video_|attr_prefetch[4] +To Node : ula:ula_|video:video_|attr[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.298 +Data Delay : 1.071 + +Slack : 1.240 +From Node : ula:ula_|video:video_|attr_prefetch[0] +To Node : ula:ula_|video:video_|attr[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.298 +Data Delay : 1.086 + +Slack : 1.242 +From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vga_hc[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.635 - -Slack : 1.449 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.648 - -Slack : 1.456 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.655 - -Slack : 1.456 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.655 - -Slack : 1.462 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 1.662 +Data Delay : 1.442 -Slack : 1.475 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.674 - -Slack : 1.481 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.684 - -Slack : 1.492 +Slack : 1.243 From Node : ula:ula_|video:video_|vga_vc[0] To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.691 +Clock Skew : 0.062 +Data Delay : 1.449 -Slack : 1.503 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.702 - -Slack : 1.507 +Slack : 1.250 From Node : ula:ula_|video:video_|vga_vc[0] To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.706 +Clock Skew : 0.062 +Data Delay : 1.456 -Slack : 1.518 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Slack : 1.250 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.456 + +Slack : 1.257 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.457 + +Slack : 1.261 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.467 + +Slack : 1.264 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.059 -Data Delay : 1.721 +Data Delay : 1.467 -Slack : 1.528 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.727 - -Slack : 1.529 +Slack : 1.268 From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.728 +Clock Skew : 0.062 +Data Delay : 1.474 -Slack : 1.530 +Slack : 1.277 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.059 +Data Delay : 1.480 + +Slack : 1.279 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.485 + +Slack : 1.320 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.422 +Data Delay : 1.886 + +Slack : 1.320 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.422 +Data Delay : 1.886 + +Slack : 1.320 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.422 +Data Delay : 1.886 + +Slack : 1.320 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.422 +Data Delay : 1.886 + +Slack : 1.320 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.422 +Data Delay : 1.886 + +Slack : 1.320 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.422 +Data Delay : 1.886 + +Slack : 1.320 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.422 +Data Delay : 1.886 + +Slack : 1.320 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.422 +Data Delay : 1.886 + +Slack : 1.339 From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[8] +To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.729 +Clock Skew : 0.062 +Data Delay : 1.545 -Slack : 1.531 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vram_address[9] +Slack : 1.345 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_hc[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.730 +Clock Skew : 0.059 +Data Delay : 1.548 + +Slack : 1.349 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.394 +Data Delay : 1.887 + +Slack : 1.349 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.394 +Data Delay : 1.887 + +Slack : 1.349 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.394 +Data Delay : 1.887 + +Slack : 1.349 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.394 +Data Delay : 1.887 + +Slack : 1.349 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.394 +Data Delay : 1.887 + +Slack : 1.349 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.394 +Data Delay : 1.887 + +Slack : 1.349 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.394 +Data Delay : 1.887 + +Slack : 1.349 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.394 +Data Delay : 1.887 + +Slack : 1.357 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.563 + +Slack : 1.362 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.562 +--------------------------------------------------------------------------------+ @@ -16179,743 +16333,743 @@ Data Delay : 1.730 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -5.784 +Slack : -5.744 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.088 -Data Delay : 3.983 +Data Delay : 3.943 -Slack : -5.784 +Slack : -5.744 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.090 -Data Delay : 3.981 +Data Delay : 3.941 -Slack : -5.784 +Slack : -5.744 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.091 -Data Delay : 3.980 +Data Delay : 3.940 -Slack : -5.783 +Slack : -5.743 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.091 -Data Delay : 3.979 +Data Delay : 3.939 -Slack : -5.783 +Slack : -5.743 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.092 -Data Delay : 3.978 +Data Delay : 3.938 -Slack : -5.557 +Slack : -5.507 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.115 -Data Delay : 3.731 +Data Delay : 3.681 -Slack : -5.547 +Slack : -5.494 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.116 -Data Delay : 3.720 +Data Delay : 3.667 -Slack : -5.306 +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.549 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.549 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.549 + +Slack : -5.257 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.598 +Data Delay : 3.549 -Slack : -5.306 +Slack : -5.257 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.598 +Data Delay : 3.549 -Slack : -5.306 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.598 - -Slack : -5.306 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.598 - -Slack : -5.306 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.598 - -Slack : -5.306 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.598 - -Slack : -5.306 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.598 - -Slack : -5.306 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.598 - -Slack : -5.306 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.598 - -Slack : -5.306 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.598 - -Slack : -5.297 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.592 - -Slack : -5.297 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.592 - -Slack : -5.297 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.592 - -Slack : -5.297 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.592 - -Slack : -5.297 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.592 - -Slack : -5.297 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.592 - -Slack : -5.297 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.588 - -Slack : -5.297 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.588 - -Slack : -5.297 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.588 - -Slack : -5.297 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.588 - -Slack : -5.297 +Slack : -5.257 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.088 -Data Delay : 3.588 +Data Delay : 3.548 -Slack : -5.297 +Slack : -5.257 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.088 -Data Delay : 3.588 +Data Delay : 3.548 -Slack : -5.297 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.588 - -Slack : -5.297 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.588 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.588 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.588 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.591 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.591 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.591 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.591 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.591 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.591 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.591 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.591 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.591 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.591 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.591 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.591 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.591 - -Slack : -5.296 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.588 - -Slack : -5.010 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.202 -Data Delay : 3.591 - -Slack : -5.008 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.201 -Data Delay : 3.588 - -Slack : -5.008 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.201 -Data Delay : 3.588 - -Slack : -5.008 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.201 -Data Delay : 3.588 - -Slack : -4.999 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.213 -Data Delay : 3.588 - -Slack : -4.999 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.213 -Data Delay : 3.588 - -Slack : -4.999 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.213 -Data Delay : 3.588 - -Slack : -4.999 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.213 -Data Delay : 3.588 - -Slack : -4.999 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.213 -Data Delay : 3.588 - -Slack : -4.999 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.213 -Data Delay : 3.588 - -Slack : -4.990 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 3.598 - -Slack : -4.990 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 3.598 - -Slack : -4.990 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 3.598 - -Slack : -4.990 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 3.598 - -Slack : -4.990 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 3.598 - -Slack : -4.983 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.219 -Data Delay : 3.581 - -Slack : -4.983 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.219 -Data Delay : 3.581 - -Slack : -4.983 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.219 -Data Delay : 3.581 - -Slack : -4.983 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.219 -Data Delay : 3.581 - -Slack : -4.983 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.219 -Data Delay : 3.581 - -Slack : -4.983 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.230 -Data Delay : 3.592 - -Slack : -4.983 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.230 -Data Delay : 3.592 - -Slack : -4.983 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.230 -Data Delay : 3.592 - -Slack : -4.983 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.230 -Data Delay : 3.592 - -Slack : -4.983 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.230 -Data Delay : 3.592 - -Slack : -4.983 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.237 -Data Delay : 3.599 - -Slack : -4.983 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.237 -Data Delay : 3.599 - -Slack : -4.983 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.237 -Data Delay : 3.599 - -Slack : -4.982 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.219 -Data Delay : 3.580 - -Slack : -4.982 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.219 -Data Delay : 3.580 - -Slack : -4.982 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.219 -Data Delay : 3.580 - -Slack : -4.982 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.219 -Data Delay : 3.580 - -Slack : -4.981 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.230 -Data Delay : 3.590 - -Slack : -4.956 +Slack : -5.257 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.264 -Data Delay : 3.599 +Clock Skew : -0.087 +Data Delay : 3.549 -Slack : -4.956 +Slack : -5.257 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.264 -Data Delay : 3.599 +Clock Skew : -0.087 +Data Delay : 3.549 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.090 +Data Delay : 3.545 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.090 +Data Delay : 3.545 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.090 +Data Delay : 3.545 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.090 +Data Delay : 3.545 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.090 +Data Delay : 3.545 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.091 +Data Delay : 3.544 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.090 +Data Delay : 3.545 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.091 +Data Delay : 3.544 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.090 +Data Delay : 3.545 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.090 +Data Delay : 3.545 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.090 +Data Delay : 3.545 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.088 +Data Delay : 3.547 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.088 +Data Delay : 3.547 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.091 +Data Delay : 3.544 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.091 +Data Delay : 3.544 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.091 +Data Delay : 3.544 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.089 +Data Delay : 3.546 + +Slack : -4.963 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.208 +Data Delay : 3.550 + +Slack : -4.959 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.212 +Data Delay : 3.547 + +Slack : -4.959 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.212 +Data Delay : 3.547 + +Slack : -4.959 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.212 +Data Delay : 3.547 + +Slack : -4.959 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.212 +Data Delay : 3.547 + +Slack : -4.959 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.212 +Data Delay : 3.547 + +Slack : -4.959 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.212 +Data Delay : 3.547 + +Slack : -4.941 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.543 + +Slack : -4.941 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.543 + +Slack : -4.941 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.543 + +Slack : -4.941 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.543 + +Slack : -4.941 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.543 + +Slack : -4.940 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.542 + +Slack : -4.940 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.542 + +Slack : -4.940 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.542 + +Slack : -4.940 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.542 + +Slack : -4.940 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.542 + +Slack : -4.940 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.227 +Data Delay : 3.546 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.547 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 + +Slack : -4.936 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.550 +--------------------------------------------------------------------------------+ @@ -16923,743 +17077,743 @@ Data Delay : 3.599 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 3.369 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.637 -Data Delay : 3.234 - -Slack : 3.369 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.637 -Data Delay : 3.234 - -Slack : 3.392 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.602 -Data Delay : 3.222 - -Slack : 3.394 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.601 -Data Delay : 3.223 - -Slack : 3.394 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.601 -Data Delay : 3.223 - -Slack : 3.394 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.601 -Data Delay : 3.223 - -Slack : 3.394 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.601 -Data Delay : 3.223 - -Slack : 3.394 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.601 -Data Delay : 3.223 - -Slack : 3.395 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.590 -Data Delay : 3.213 - -Slack : 3.396 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.590 -Data Delay : 3.214 - -Slack : 3.396 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.590 -Data Delay : 3.214 - -Slack : 3.396 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.590 -Data Delay : 3.214 - -Slack : 3.396 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.590 -Data Delay : 3.214 - -Slack : 3.396 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.590 -Data Delay : 3.214 - -Slack : 3.396 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.590 -Data Delay : 3.214 - -Slack : 3.396 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.590 -Data Delay : 3.214 - -Slack : 3.396 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.590 -Data Delay : 3.214 - -Slack : 3.397 +Slack : 3.374 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.609 -Data Delay : 3.234 +Clock Skew : 0.603 +Data Delay : 3.205 -Slack : 3.397 +Slack : 3.374 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.609 -Data Delay : 3.234 +Clock Skew : 0.607 +Data Delay : 3.209 -Slack : 3.397 +Slack : 3.374 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.609 -Data Delay : 3.234 +Clock Skew : 0.607 +Data Delay : 3.209 -Slack : 3.404 +Slack : 3.374 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.584 -Data Delay : 3.219 - -Slack : 3.404 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.584 -Data Delay : 3.219 - -Slack : 3.404 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.584 -Data Delay : 3.219 - -Slack : 3.404 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.584 -Data Delay : 3.219 - -Slack : 3.404 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.584 -Data Delay : 3.219 - -Slack : 3.404 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.584 -Data Delay : 3.219 - -Slack : 3.405 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.600 -Data Delay : 3.233 +Clock Skew : 0.607 +Data Delay : 3.209 -Slack : 3.405 +Slack : 3.374 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.600 -Data Delay : 3.233 +Clock Skew : 0.607 +Data Delay : 3.209 -Slack : 3.405 +Slack : 3.374 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.600 -Data Delay : 3.233 +Clock Skew : 0.607 +Data Delay : 3.209 -Slack : 3.405 +Slack : 3.374 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.600 -Data Delay : 3.233 +Clock Skew : 0.607 +Data Delay : 3.209 -Slack : 3.405 +Slack : 3.374 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.600 -Data Delay : 3.233 +Clock Skew : 0.607 +Data Delay : 3.209 -Slack : 3.421 +Slack : 3.374 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.607 +Data Delay : 3.209 + +Slack : 3.374 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.607 +Data Delay : 3.209 + +Slack : 3.374 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.607 +Data Delay : 3.209 + +Slack : 3.374 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.607 +Data Delay : 3.209 + +Slack : 3.374 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.607 +Data Delay : 3.209 + +Slack : 3.374 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.607 +Data Delay : 3.209 + +Slack : 3.374 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.571 -Data Delay : 3.220 +Clock Skew : 0.607 +Data Delay : 3.209 -Slack : 3.421 +Slack : 3.378 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.571 -Data Delay : 3.220 +Clock Skew : 0.599 +Data Delay : 3.205 -Slack : 3.421 +Slack : 3.380 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.571 -Data Delay : 3.220 +Clock Skew : 0.595 +Data Delay : 3.203 -Slack : 3.422 +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.203 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.203 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.203 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.203 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.203 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.203 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.203 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.203 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.203 + +Slack : 3.391 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.583 +Data Delay : 3.205 + +Slack : 3.391 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.583 +Data Delay : 3.205 + +Slack : 3.391 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.583 +Data Delay : 3.205 + +Slack : 3.391 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.583 +Data Delay : 3.205 + +Slack : 3.391 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.583 +Data Delay : 3.205 + +Slack : 3.391 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.583 +Data Delay : 3.205 + +Slack : 3.403 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.573 -Data Delay : 3.223 +Clock Skew : 0.578 +Data Delay : 3.209 -Slack : 3.720 +Slack : 3.707 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.275 -Data Delay : 3.223 +Clock Skew : 0.270 +Data Delay : 3.205 -Slack : 3.720 +Slack : 3.707 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.275 -Data Delay : 3.223 +Clock Skew : 0.270 +Data Delay : 3.205 -Slack : 3.720 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.275 -Data Delay : 3.223 - -Slack : 3.720 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.275 -Data Delay : 3.223 - -Slack : 3.720 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.275 -Data Delay : 3.223 - -Slack : 3.720 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.275 -Data Delay : 3.223 - -Slack : 3.720 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.219 - -Slack : 3.720 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.219 - -Slack : 3.720 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.219 - -Slack : 3.720 +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.271 -Data Delay : 3.219 +Data Delay : 3.206 -Slack : 3.720 +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.271 -Data Delay : 3.219 +Data Delay : 3.206 -Slack : 3.720 +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.271 -Data Delay : 3.219 +Data Delay : 3.206 -Slack : 3.720 +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.271 -Data Delay : 3.219 +Data Delay : 3.206 -Slack : 3.720 +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.271 -Data Delay : 3.219 +Data Delay : 3.206 -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.220 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.220 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.223 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.223 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.223 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.223 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.223 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.223 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.223 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.223 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.223 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.223 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.223 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.223 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.223 - -Slack : 3.721 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.220 - -Slack : 3.734 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.233 - -Slack : 3.734 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.233 - -Slack : 3.734 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.233 - -Slack : 3.734 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.233 - -Slack : 3.734 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.233 - -Slack : 3.734 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.233 - -Slack : 3.734 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.233 - -Slack : 3.734 +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.271 -Data Delay : 3.233 +Data Delay : 3.206 -Slack : 3.734 +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.268 +Data Delay : 3.204 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.268 +Data Delay : 3.204 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.268 +Data Delay : 3.204 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.268 +Data Delay : 3.204 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.268 +Data Delay : 3.204 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.268 +Data Delay : 3.204 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.268 +Data Delay : 3.204 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.268 +Data Delay : 3.204 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.268 +Data Delay : 3.204 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.272 +Data Delay : 3.208 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.272 +Data Delay : 3.208 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.272 +Data Delay : 3.208 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.272 +Data Delay : 3.208 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.272 +Data Delay : 3.208 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.272 +Data Delay : 3.208 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.272 +Data Delay : 3.208 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.269 +Data Delay : 3.205 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.267 +Data Delay : 3.204 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.267 +Data Delay : 3.204 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.271 -Data Delay : 3.233 +Data Delay : 3.208 -Slack : 3.734 +Slack : 3.709 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.271 -Data Delay : 3.233 +Data Delay : 3.208 -Slack : 3.920 +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.267 +Data Delay : 3.204 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.267 +Data Delay : 3.204 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.267 +Data Delay : 3.204 + +Slack : 3.895 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.226 -Data Delay : 3.319 +Data Delay : 3.294 -Slack : 3.934 +Slack : 3.909 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.227 -Data Delay : 3.334 +Data Delay : 3.309 -Slack : 4.130 +Slack : 4.117 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.254 -Data Delay : 3.554 +Data Delay : 3.541 -Slack : 4.130 +Slack : 4.117 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.252 -Data Delay : 3.552 +Data Delay : 3.539 -Slack : 4.130 +Slack : 4.117 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.251 -Data Delay : 3.551 +Data Delay : 3.538 -Slack : 4.130 +Slack : 4.117 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.250 -Data Delay : 3.550 +Data Delay : 3.537 -Slack : 4.131 +Slack : 4.118 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.250 -Data Delay : 3.551 +Data Delay : 3.538 +--------------------------------------------------------------------------------+ @@ -17667,101 +17821,117 @@ Data Delay : 3.551 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 9.488 -Actual Width : 9.718 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 - Slack : 9.489 Actual Width : 9.719 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 -Slack : 9.490 -Actual Width : 9.720 +Slack : 9.489 +Actual Width : 9.719 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg -Slack : 9.490 -Actual Width : 9.720 +Slack : 9.489 +Actual Width : 9.719 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 -Slack : 9.490 -Actual Width : 9.720 +Slack : 9.489 +Actual Width : 9.719 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg -Slack : 9.490 -Actual Width : 9.720 +Slack : 9.489 +Actual Width : 9.719 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 + Slack : 9.490 Actual Width : 9.720 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg Slack : 9.490 Actual Width : 9.720 @@ -17811,6 +17981,54 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg + Slack : 9.490 Actual Width : 9.720 Required Width : 0.230 @@ -17833,7 +18051,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -17841,15 +18059,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -17859,22 +18069,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 - Slack : 9.490 Actual Width : 9.720 Required Width : 0.230 @@ -17883,6 +18077,22 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + Slack : 9.490 Actual Width : 9.720 Required Width : 0.230 @@ -17905,7 +18115,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -17913,7 +18123,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -17921,15 +18131,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -17969,39 +18171,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18025,7 +18195,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18041,15 +18227,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 Slack : 9.492 Actual Width : 9.722 @@ -18057,7 +18235,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 Slack : 9.492 Actual Width : 9.722 @@ -18065,15 +18243,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 - -Slack : 9.492 -Actual Width : 9.722 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 Slack : 9.492 Actual Width : 9.722 @@ -18099,6 +18269,30 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 + Slack : 9.492 Actual Width : 9.722 Required Width : 0.230 @@ -18113,39 +18307,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 - -Slack : 9.492 -Actual Width : 9.722 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 - -Slack : 9.492 -Actual Width : 9.722 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Slack : 9.493 Actual Width : 9.723 @@ -18163,22 +18325,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 - Slack : 9.493 Actual Width : 9.723 Required Width : 0.230 @@ -18193,39 +18339,31 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 - Slack : 9.494 Actual Width : 9.724 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 Slack : 9.494 Actual Width : 9.724 @@ -18241,7 +18379,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 Slack : 9.494 Actual Width : 9.724 @@ -18249,7 +18387,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Slack : 9.494 Actual Width : 9.724 @@ -18273,7 +18419,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 Slack : 9.495 Actual Width : 9.725 @@ -18289,15 +18451,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 Slack : 9.496 Actual Width : 9.726 @@ -18305,7 +18459,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 Slack : 9.497 Actual Width : 9.727 @@ -18313,7 +18467,31 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 + +Slack : 9.497 +Actual Width : 9.727 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 + +Slack : 9.497 +Actual Width : 9.727 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 + +Slack : 9.497 +Actual Width : 9.727 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 Slack : 9.498 Actual Width : 9.728 @@ -18321,7 +18499,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 Slack : 9.498 Actual Width : 9.728 @@ -18337,7 +18523,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 Slack : 9.498 Actual Width : 9.728 @@ -18345,7 +18531,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 Slack : 9.498 Actual Width : 9.728 @@ -18369,7 +18571,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 Slack : 9.498 Actual Width : 9.728 @@ -18377,7 +18579,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 Slack : 9.498 Actual Width : 9.728 @@ -18393,7 +18603,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 Slack : 9.499 Actual Width : 9.729 @@ -18401,7 +18611,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 Slack : 9.499 Actual Width : 9.729 @@ -18409,63 +18619,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 - -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 - -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 - -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 - -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 - -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 - -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 - -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +--------------------------------------------------------------------------------+ @@ -18473,61 +18627,77 @@ Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 19.594 -Actual Width : 19.810 +Slack : 19.600 +Actual Width : 19.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[3] +Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Slack : 19.596 -Actual Width : 19.812 +Slack : 19.600 +Actual Width : 19.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[0] +Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Slack : 19.596 -Actual Width : 19.812 +Slack : 19.600 +Actual Width : 19.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[2] +Target : ula:ula_|video:video_|attr[0] -Slack : 19.596 -Actual Width : 19.812 +Slack : 19.600 +Actual Width : 19.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[6] +Target : ula:ula_|video:video_|attr[1] -Slack : 19.596 -Actual Width : 19.812 +Slack : 19.600 +Actual Width : 19.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[7] +Target : ula:ula_|video:video_|attr[4] -Slack : 19.596 -Actual Width : 19.812 +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[0] + +Slack : 19.600 +Actual Width : 19.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|bits_prefetch[1] -Slack : 19.598 -Actual Width : 19.814 +Slack : 19.600 +Actual Width : 19.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[5] +Target : ula:ula_|video:video_|bits_prefetch[2] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[3] Slack : 19.600 Actual Width : 19.816 @@ -18537,13 +18707,157 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|bits_prefetch[4] -Slack : 19.601 -Actual Width : 19.817 +Slack : 19.600 +Actual Width : 19.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Target : ula:ula_|video:video_|bits_prefetch[5] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[6] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[7] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|frame[0] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[2] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[4] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[5] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[6] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[7] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[8] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[9] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[0] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[1] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[2] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[3] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[4] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[5] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[6] + +Slack : 19.600 +Actual Width : 19.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[7] Slack : 19.601 Actual Width : 19.817 @@ -18551,23 +18865,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1 - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[0] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[1] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] Slack : 19.601 Actual Width : 19.817 @@ -18585,14 +18883,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|attr[3] -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[4] - Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -18681,22 +18971,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|bits[7] -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[3] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|frame[0] - Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -18705,6 +18979,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|frame[1] +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|frame[2] + Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -18737,14 +19019,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|vga_hc[1] -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[2] - Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -18753,54 +19027,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|vga_hc[3] -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[4] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[5] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[6] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[7] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[8] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[9] - Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -18881,14 +19107,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|vga_vc[9] -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[0] - Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -18913,62 +19131,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|vram_address[12] -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[1] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[2] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[3] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[4] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[5] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[6] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[7] - Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -18985,13 +19147,93 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|vram_address[9] +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] + Slack : 19.603 -Actual Width : 19.819 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg + +Slack : 19.604 +Actual Width : 19.820 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|frame[2] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] + +Slack : 19.604 +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 + +Slack : 19.604 +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg + +Slack : 19.604 +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[0] + +Slack : 19.604 +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[1] + +Slack : 19.604 +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[2] + +Slack : 19.604 +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[3] Slack : 19.604 Actual Width : 19.820 @@ -19007,7 +19249,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[2] +Target : ula:ula_|video:video_|attr_prefetch[5] Slack : 19.604 Actual Width : 19.820 @@ -19015,7 +19257,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[6] +Target : ula:ula_|video:video_|attr_prefetch[6] Slack : 19.604 Actual Width : 19.820 @@ -19023,255 +19265,167 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[7] +Target : ula:ula_|video:video_|attr_prefetch[7] Slack : 19.605 -Actual Width : 19.821 -Required Width : 0.216 -Type : High Pulse Width +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[1] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 Slack : 19.605 -Actual Width : 19.821 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[0] - -Slack : 19.606 -Actual Width : 19.822 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[5] - -Slack : 19.704 -Actual Width : 19.859 -Required Width : 0.155 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_VS +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 -Slack : 19.705 -Actual Width : 19.860 -Required Width : 0.155 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_HS +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg -Slack : 19.706 -Actual Width : 19.856 -Required Width : 0.150 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_HS - -Slack : 19.706 -Actual Width : 19.856 -Required Width : 0.150 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_VS - -Slack : 19.709 -Actual Width : 19.893 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[5] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 -Slack : 19.710 -Actual Width : 19.894 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[1] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg -Slack : 19.710 -Actual Width : 19.894 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[0] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0 -Slack : 19.710 -Actual Width : 19.894 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[7] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg -Slack : 19.711 -Actual Width : 19.895 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[4] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 -Slack : 19.711 -Actual Width : 19.895 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[2] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg -Slack : 19.711 -Actual Width : 19.895 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[6] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0 -Slack : 19.712 -Actual Width : 19.896 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|frame[2] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[0] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[1] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[2] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[3] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[4] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[5] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[6] - -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[7] - -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[0] - -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[1] - -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[2] - -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[3] - -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[4] - -Slack : 19.714 -Actual Width : 19.898 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[5] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 +--------------------------------------------------------------------------------+ @@ -19279,78 +19433,14 @@ Target : ula:ula_|video:video_|bits[5] +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 20.588 -Actual Width : 20.804 +Slack : 20.591 +Actual Width : 20.807 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Slack : 20.588 -Actual Width : 20.804 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] - -Slack : 20.588 -Actual Width : 20.804 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] - -Slack : 20.588 -Actual Width : 20.804 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] - -Slack : 20.590 -Actual Width : 20.806 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] - -Slack : 20.590 -Actual Width : 20.806 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] - -Slack : 20.590 -Actual Width : 20.806 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] - -Slack : 20.590 -Actual Width : 20.806 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] - -Slack : 20.590 -Actual Width : 20.806 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] - Slack : 20.592 Actual Width : 20.808 Required Width : 0.216 @@ -19359,16 +19449,16 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Slack : 20.592 -Actual Width : 20.808 +Slack : 20.594 +Actual Width : 20.810 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Slack : 20.592 -Actual Width : 20.808 +Slack : 20.594 +Actual Width : 20.810 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -19381,15 +19471,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] - -Slack : 20.594 -Actual Width : 20.810 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Slack : 20.594 Actual Width : 20.810 @@ -19407,14 +19489,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Data -Slack : 20.594 -Actual Width : 20.810 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle - Slack : 20.594 Actual Width : 20.810 Required Width : 0.216 @@ -19439,53 +19513,61 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Slack : 20.594 -Actual Width : 20.810 +Slack : 20.595 +Actual Width : 20.811 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Slack : 20.594 -Actual Width : 20.810 +Slack : 20.595 +Actual Width : 20.811 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Slack : 20.594 -Actual Width : 20.810 +Slack : 20.595 +Actual Width : 20.811 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Slack : 20.594 -Actual Width : 20.810 +Slack : 20.595 +Actual Width : 20.811 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Slack : 20.594 -Actual Width : 20.810 +Slack : 20.595 +Actual Width : 20.811 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Slack : 20.594 -Actual Width : 20.810 +Slack : 20.595 +Actual Width : 20.811 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle Slack : 20.595 Actual Width : 20.811 @@ -19503,6 +19585,94 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] + Slack : 20.595 Actual Width : 20.811 Required Width : 0.216 @@ -19517,135 +19687,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Slack : 20.596 Actual Width : 20.812 @@ -19687,14 +19729,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] - Slack : 20.596 Actual Width : 20.812 Required Width : 0.216 @@ -19711,13 +19745,45 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Slack : 20.597 -Actual Width : 20.813 +Slack : 20.596 +Actual Width : 20.812 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Slack : 20.598 Actual Width : 20.814 @@ -19725,7 +19791,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] Slack : 20.598 Actual Width : 20.814 @@ -19733,7 +19799,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] Slack : 20.598 Actual Width : 20.814 @@ -19741,7 +19807,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] Slack : 20.598 Actual Width : 20.814 @@ -19749,7 +19815,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] Slack : 20.598 Actual Width : 20.814 @@ -19757,7 +19823,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] Slack : 20.598 Actual Width : 20.814 @@ -19773,7 +19839,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] Slack : 20.599 Actual Width : 20.815 @@ -19789,48 +19855,136 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] - -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] - -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] - -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] - -Slack : 20.600 -Actual Width : 20.816 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] + +Slack : 20.603 +Actual Width : 20.819 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + Slack : 20.633 Actual Width : 20.817 Required Width : 0.184 @@ -19951,6 +20105,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r +Slack : 20.697 +Actual Width : 20.881 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + Slack : 20.698 Actual Width : 20.853 Required Width : 0.155 @@ -20031,14 +20193,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|sda_out -Slack : 20.701 -Actual Width : 20.885 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] - Slack : 20.702 Actual Width : 20.857 Required Width : 0.155 @@ -20053,7 +20207,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] Slack : 20.702 Actual Width : 20.886 @@ -20061,7 +20215,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Slack : 20.702 Actual Width : 20.886 @@ -20069,7 +20223,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Slack : 20.702 Actual Width : 20.886 @@ -20077,7 +20231,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +--------------------------------------------------------------------------------+ @@ -20203,6 +20357,20 @@ Target : ula:ula_|clocks:clocks_|counter[0] +--------------------------------------------------------------------------------+ ; Setup Times ; +--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 1.911 +Fall : 2.250 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 3.553 +Fall : 3.886 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : SW[*] Clock Port : CLOCK_50 Rise : 0.869 @@ -20219,15 +20387,15 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 1.136 -Fall : 1.344 +Rise : 1.127 +Fall : 1.330 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 2.566 -Fall : 2.787 +Rise : 2.508 +Fall : 2.792 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -20237,6 +20405,20 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Hold Times ; +--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -1.524 +Fall : -1.860 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -2.737 +Fall : -3.061 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : SW[*] Clock Port : CLOCK_50 Rise : -0.321 @@ -20253,15 +20435,15 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.583 -Fall : -0.789 +Rise : -0.576 +Fall : -0.776 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -0.824 -Fall : -1.045 +Rise : -1.192 +Fall : -1.416 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -20273,134 +20455,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 8.565 -Fall : 8.442 +Rise : 9.288 +Fall : 9.190 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 8.557 -Fall : 8.433 +Rise : 9.288 +Fall : 9.190 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 8.473 -Fall : 8.323 +Rise : 8.334 +Fall : 8.266 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 8.315 -Fall : 8.259 +Rise : 9.015 +Fall : 8.878 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 8.379 -Fall : 8.255 +Rise : 8.651 +Fall : 8.566 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 8.565 -Fall : 8.442 +Rise : 8.878 +Fall : 8.812 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 7.924 -Fall : 7.821 +Rise : 8.466 +Fall : 8.329 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 8.541 -Fall : 8.434 +Rise : 9.024 +Fall : 8.945 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 7.824 -Fall : 7.685 +Rise : 8.255 +Fall : 8.139 Clock Edge : Rise Clock Reference : CLOCK_50 +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 7.270 +Fall : 7.175 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 6.990 +Fall : 6.892 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 7.043 +Fall : 6.987 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 6.669 +Fall : 6.593 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 6.995 +Fall : 6.959 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 7.270 +Fall : 7.174 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 6.811 +Fall : 6.729 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 7.250 +Fall : 7.175 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 6.586 +Fall : 6.535 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 7.662 -Fall : 7.219 +Rise : 7.385 +Fall : 6.991 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 7.662 -Fall : 7.219 +Rise : 7.385 +Fall : 6.991 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 6.021 -Fall : 5.897 +Rise : 5.536 +Fall : 5.411 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 6.172 -Fall : 6.037 +Rise : 5.836 +Fall : 5.758 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 6.529 -Fall : 6.379 +Rise : 6.231 +Fall : 6.124 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 7.038 -Fall : 6.929 +Rise : 5.992 +Fall : 5.815 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 6.840 -Fall : 6.739 +Rise : 5.992 +Fall : 5.815 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 6.870 -Fall : 6.762 +Rise : 5.802 +Fall : 5.684 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 7.038 -Fall : 6.929 +Rise : 5.868 +Fall : 5.672 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 7.038 -Fall : 6.929 +Rise : 5.868 +Fall : 5.672 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -20413,36 +20658,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 7.257 -Fall : 7.185 +Rise : 6.035 +Fall : 5.996 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 7.147 -Fall : 7.097 +Rise : 6.035 +Fall : 5.996 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 7.257 -Fall : 7.185 +Rise : 5.858 +Fall : 5.798 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 6.530 -Fall : 6.442 +Rise : 5.672 +Fall : 5.600 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 7.121 -Fall : 7.075 +Rise : 5.870 +Fall : 5.793 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -20488,20 +20733,6 @@ Fall : 2.519 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Data Port : GPIO_1[*] -Clock Port : CLOCK_50 -Rise : 4.941 -Fall : 4.893 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - -Data Port : GPIO_1[22] -Clock Port : CLOCK_50 -Rise : 4.941 -Fall : 4.893 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Data Port : I2C_SCLK Clock Port : CLOCK_50 Rise : 2.647 @@ -20524,134 +20755,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 6.575 -Fall : 6.451 +Rise : 6.905 +Fall : 6.797 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 6.575 -Fall : 6.451 +Rise : 7.457 +Fall : 7.377 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 6.611 -Fall : 6.467 +Rise : 7.475 +Fall : 7.384 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 6.827 -Fall : 6.766 +Rise : 6.905 +Fall : 6.797 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 7.214 -Fall : 7.116 +Rise : 7.286 +Fall : 7.208 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 7.419 -Fall : 7.305 +Rise : 7.618 +Fall : 7.567 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 6.797 -Fall : 6.700 +Rise : 7.138 +Fall : 6.996 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 7.229 -Fall : 7.120 +Rise : 6.984 +Fall : 6.911 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 6.740 -Fall : 6.605 +Rise : 7.037 +Fall : 6.924 Clock Edge : Rise Clock Reference : CLOCK_50 +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 5.004 +Fall : 4.912 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 5.924 +Fall : 5.881 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 5.978 +Fall : 5.952 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 5.763 +Fall : 5.676 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 5.765 +Fall : 5.720 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 5.004 +Fall : 4.912 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 5.746 +Fall : 5.674 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 6.140 +Fall : 6.075 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 5.512 +Fall : 5.440 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 3.659 -Fall : 3.525 +Rise : 3.609 +Fall : 3.472 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 5.441 -Fall : 5.000 +Rise : 5.390 +Fall : 4.913 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 3.659 -Fall : 3.525 +Rise : 3.609 +Fall : 3.472 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 3.939 -Fall : 3.807 +Rise : 3.832 +Fall : 3.672 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 4.283 -Fall : 4.136 +Rise : 4.210 +Fall : 4.023 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 3.609 -Fall : 3.502 +Rise : 3.660 +Fall : 3.561 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 3.609 -Fall : 3.502 +Rise : 4.048 +Fall : 3.884 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 3.703 -Fall : 3.555 +Rise : 3.660 +Fall : 3.561 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 3.799 -Fall : 3.684 +Rise : 3.929 +Fall : 3.746 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 3.799 -Fall : 3.684 +Rise : 3.929 +Fall : 3.746 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -20664,36 +20958,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 3.470 -Fall : 3.390 +Rise : 3.534 +Fall : 3.394 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 4.063 -Fall : 4.018 +Rise : 3.882 +Fall : 3.774 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 4.075 -Fall : 3.961 +Rise : 3.799 +Fall : 3.710 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 3.470 -Fall : 3.390 +Rise : 3.534 +Fall : 3.394 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 4.038 -Fall : 3.997 +Rise : 3.723 +Fall : 3.578 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -20739,20 +21033,6 @@ Fall : 2.162 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Data Port : GPIO_1[*] -Clock Port : CLOCK_50 -Rise : 4.326 -Fall : 4.277 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - -Data Port : GPIO_1[22] -Clock Port : CLOCK_50 -Rise : 4.326 -Fall : 4.277 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Data Port : I2C_SCLK Clock Port : CLOCK_50 Rise : 2.290 @@ -20775,10 +21055,10 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.165 +RR : 4.171 RF : FR : -FF : 4.284 +FF : 4.298 Input Port : SW[2] Output Port : LED[2] @@ -20786,6 +21066,20 @@ RR : 3.640 RF : FR : FF : 3.830 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 6.058 +RF : +FR : +FF : 6.293 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 3.926 +RF : +FR : +FF : 4.082 +--------------------------------------------------------------------------------+ @@ -20795,10 +21089,10 @@ FF : 3.830 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.030 +RR : 4.037 RF : FR : -FF : 4.152 +FF : 4.164 Input Port : SW[2] Output Port : LED[2] @@ -20806,6 +21100,20 @@ RR : 3.527 RF : FR : FF : 3.715 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 5.841 +RF : +FR : +FF : 6.076 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 3.796 +RF : +FR : +FF : 3.952 +--------------------------------------------------------------------------------+ @@ -20820,20 +21128,20 @@ No synchronizer chains to report. ; Fast 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -15.171 -End Point TNS : -291.784 +Slack : -14.971 +End Point TNS : -442.545 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -4.979 +End Point TNS : -171.124 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -3.800 -End Point TNS : -34.909 +Slack : -3.775 +End Point TNS : -35.541 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Slack : -2.784 End Point TNS : -2.784 - -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : -2.194 -End Point TNS : -30.204 +--------------------------------------------------------------------------------+ @@ -20842,15 +21150,15 @@ End Point TNS : -30.204 ; Fast 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -0.698 -End Point TNS : -11.143 +Slack : -0.053 +End Point TNS : -0.089 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Slack : 0.177 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 0.179 +Slack : 0.178 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -20864,8 +21172,8 @@ End Point TNS : 0.000 ; Fast 1200mV 0C Model Recovery Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -4.738 -End Point TNS : -361.836 +Slack : -4.693 +End Point TNS : -358.284 +--------------------------------------------------------------------------------+ @@ -20874,7 +21182,7 @@ End Point TNS : -361.836 ; Fast 1200mV 0C Model Removal Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 2.515 +Slack : 2.518 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -20888,7 +21196,7 @@ Slack : 9.208 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : 19.640 +Slack : 19.609 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -20905,905 +21213,1811 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -15.171 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 5.221 - -Slack : -15.109 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 5.154 - -Slack : -15.028 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 5.073 - -Slack : -15.028 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.023 -Data Delay : 5.079 - -Slack : -15.022 +Slack : -14.971 From Node : ula:ula_|video:video_|vga_vc[2] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 5.072 +Clock Skew : -0.021 +Data Delay : 5.024 -Slack : -15.020 +Slack : -14.965 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 5.018 + +Slack : -14.951 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 5.004 + +Slack : -14.940 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 4.993 + +Slack : -14.933 From Node : ula:ula_|video:video_|vga_hc[2] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.023 -Data Delay : 5.071 +Clock Skew : -0.022 +Data Delay : 4.985 -Slack : -15.015 -From Node : ula:ula_|video:video_|vga_vc[6] +Slack : -14.932 +From Node : ula:ula_|video:video_|vga_hc[4] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 5.065 +Clock Skew : -0.022 +Data Delay : 4.984 -Slack : -15.010 -From Node : ula:ula_|video:video_|vga_vc[4] +Slack : -14.927 +From Node : ula:ula_|video:video_|vga_hc[6] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 5.060 +Clock Skew : -0.022 +Data Delay : 4.979 -Slack : -15.009 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 5.054 - -Slack : -15.000 +Slack : -14.893 From Node : ula:ula_|video:video_|vga_vc[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 4.946 + +Slack : -14.893 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 4.942 + +Slack : -14.880 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 4.929 + +Slack : -14.864 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 4.917 + +Slack : -14.860 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 4.913 + +Slack : -14.853 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 4.906 + +Slack : -14.842 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.022 +Data Delay : 4.894 + +Slack : -14.824 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 4.877 + +Slack : -14.800 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 4.853 + +Slack : -14.761 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 Clock Skew : -0.024 -Data Delay : 5.050 +Data Delay : 4.811 -Slack : -14.985 -From Node : ula:ula_|video:video_|bits[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.023 -Data Delay : 5.036 - -Slack : -14.981 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 5.026 - -Slack : -14.970 +Slack : -14.737 From Node : ula:ula_|video:video_|bits[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.023 -Data Delay : 5.021 +Clock Skew : -0.025 +Data Delay : 4.786 -Slack : -14.935 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.980 - -Slack : -14.914 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.964 - -Slack : -14.900 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.950 - -Slack : -14.899 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.949 - -Slack : -14.888 -From Node : ula:ula_|video:video_|bits[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.023 -Data Delay : 4.939 - -Slack : -14.867 +Slack : -14.728 From Node : ula:ula_|video:video_|vga_hc[8] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.912 +Clock Skew : -0.022 +Data Delay : 4.780 -Slack : -14.861 -From Node : ula:ula_|video:video_|vga_vc[8] +Slack : -14.718 +From Node : ula:ula_|video:video_|vga_hc[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.911 +Clock Skew : -0.022 +Data Delay : 4.770 -Slack : -14.848 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.898 - -Slack : -14.822 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.867 - -Slack : -14.811 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.860 - -Slack : -14.749 -From Node : ula:ula_|video:video_|bits[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.023 -Data Delay : 4.800 - -Slack : -14.731 -From Node : ula:ula_|video:video_|bits[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.023 -Data Delay : 4.782 - -Slack : -14.717 -From Node : ula:ula_|video:video_|bits[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.023 -Data Delay : 4.768 - -Slack : -14.658 +Slack : -14.694 From Node : ula:ula_|video:video_|frame[4] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.023 -Data Delay : 4.709 +Clock Skew : -0.025 +Data Delay : 4.743 -Slack : -14.650 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[1] +Slack : -14.690 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.695 +Clock Skew : -0.178 +Data Delay : 4.586 -Slack : -14.631 +Slack : -14.685 +From Node : ula:ula_|video:video_|bits[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 4.734 + +Slack : -14.667 +From Node : ula:ula_|video:video_|bits[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 4.716 + +Slack : -14.623 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.523 + +Slack : -14.609 +From Node : ula:ula_|video:video_|bits[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 4.658 + +Slack : -14.606 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.019 +Data Delay : 4.661 + +Slack : -14.593 +From Node : ula:ula_|video:video_|bits[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 4.642 + +Slack : -14.587 From Node : ula:ula_|video:video_|attr[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.023 -Data Delay : 4.682 +Clock Skew : -0.025 +Data Delay : 4.636 -Slack : -14.579 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[0] +Slack : -14.564 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.624 +Clock Skew : -0.019 +Data Delay : 4.619 -Slack : -14.558 +Slack : -14.561 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.020 +Data Delay : 4.615 + +Slack : -14.543 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.438 + +Slack : -14.517 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.185 +Data Delay : 4.406 + +Slack : -14.515 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 4.564 + +Slack : -14.515 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.405 + +Slack : -14.501 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.396 + +Slack : -14.497 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.169 +Data Delay : 4.402 + +Slack : -14.494 +From Node : ula:ula_|video:video_|bits[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 4.543 + +Slack : -14.474 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.019 +Data Delay : 4.529 + +Slack : -14.462 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.358 + +Slack : -14.459 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.354 + +Slack : -14.425 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.320 + +Slack : -14.420 From Node : ula:ula_|video:video_|bits[0] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.023 -Data Delay : 4.609 - -Slack : -14.554 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.599 - -Slack : -14.550 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.595 - -Slack : -14.517 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.562 - -Slack : -14.515 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.565 - -Slack : -14.493 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.543 - -Slack : -14.479 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.524 - -Slack : -14.476 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.521 - -Slack : -14.454 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.499 - -Slack : -14.451 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.496 - -Slack : -14.451 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.496 - -Slack : -14.446 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.491 - -Slack : -14.444 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.494 - -Slack : -14.422 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.472 - -Slack : -14.421 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.466 - -Slack : -14.419 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 +Clock Skew : -0.025 Data Delay : 4.469 -Slack : -14.408 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_R[1] +Slack : -14.413 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.453 +Clock Skew : -0.176 +Data Delay : 4.311 -Slack : -14.405 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_R[0] +Slack : -14.388 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.450 +Clock Skew : -0.181 +Data Delay : 4.281 -Slack : -14.397 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_R[1] +Slack : -14.372 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.447 - -Slack : -14.397 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.447 - -Slack : -14.380 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.425 - -Slack : -14.363 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.408 - -Slack : -14.358 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.408 - -Slack : -14.351 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.396 - -Slack : -14.351 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.396 - -Slack : -14.350 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_G[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.395 +Clock Skew : -0.178 +Data Delay : 4.268 Slack : -14.341 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[1] +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.391 +Clock Skew : -0.183 +Data Delay : 4.232 + +Slack : -14.340 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.231 Slack : -14.337 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_R[0] +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.382 +Clock Skew : -0.019 +Data Delay : 4.392 -Slack : -14.326 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_R[0] +Slack : -14.335 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.376 +Clock Skew : -0.020 +Data Delay : 4.389 -Slack : -14.318 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_G[2] +Slack : -14.333 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.363 +Clock Skew : -0.020 +Data Delay : 4.387 -Slack : -14.318 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_G[3] +Slack : -14.325 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.363 +Clock Skew : -0.184 +Data Delay : 4.215 -Slack : -14.316 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_G[2] +Slack : -14.310 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.366 +Clock Skew : -0.019 +Data Delay : 4.365 -Slack : -14.316 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_G[3] +Slack : -14.285 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.366 +Clock Skew : -0.019 +Data Delay : 4.340 -Slack : -14.315 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_G[0] +Slack : -14.285 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.360 +Clock Skew : -0.184 +Data Delay : 4.175 -Slack : -14.312 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_R[3] +Slack : -14.284 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.357 - -Slack : -14.301 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.351 - -Slack : -14.294 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.344 - -Slack : -14.294 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.344 - -Slack : -14.292 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.337 - -Slack : -14.287 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.337 +Clock Skew : -0.176 +Data Delay : 4.182 Slack : -14.281 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_R[1] +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.330 +Clock Skew : -0.171 +Data Delay : 4.184 -Slack : -14.277 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_G[2] +Slack : -14.271 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.322 +Clock Skew : -0.019 +Data Delay : 4.326 -Slack : -14.277 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_G[3] +Slack : -14.259 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.322 - -Slack : -14.270 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.320 - -Slack : -14.267 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.312 - -Slack : -14.262 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_R[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.312 +Clock Skew : -0.179 +Data Delay : 4.154 Slack : -14.250 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_G[1] +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.295 +Clock Skew : -0.185 +Data Delay : 4.139 -Slack : -14.245 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[3] +Slack : -14.247 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.295 +Clock Skew : -0.020 +Data Delay : 4.301 -Slack : -14.235 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.285 - -Slack : -14.233 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_R[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.283 - -Slack : -14.217 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_G[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.262 - -Slack : -14.215 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_G[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.265 - -Slack : -14.215 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_G[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.260 - -Slack : -14.210 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.259 - -Slack : -14.209 +Slack : -14.221 From Node : ula:ula_|video:video_|attr[0] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.023 -Data Delay : 4.260 - -Slack : -14.209 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.254 - -Slack : -14.209 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.254 - -Slack : -14.198 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_G[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 Clock Skew : -0.024 -Data Delay : 4.248 +Data Delay : 4.271 -Slack : -14.198 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_G[3] +Slack : -14.206 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.248 +Clock Skew : -0.177 +Data Delay : 4.103 -Slack : -14.193 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_G[1] +Slack : -14.203 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.243 +Clock Skew : -0.171 +Data Delay : 4.106 -Slack : -14.188 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : VGA_R[1] +Slack : -14.195 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.238 +Clock Skew : -0.183 +Data Delay : 4.086 -Slack : -14.185 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_R[3] +Slack : -14.189 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.019 +Data Delay : 4.244 + +Slack : -14.183 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.020 +Data Delay : 4.237 + +Slack : -14.169 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.065 + +Slack : -14.155 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.052 + +Slack : -14.138 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.038 + +Slack : -14.126 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.017 + +Slack : -14.124 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.024 + +Slack : -14.114 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.020 +Data Delay : 4.168 + +Slack : -14.045 +From Node : ula:ula_|video:video_|attr[3] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.025 -Data Delay : 4.234 +Data Delay : 4.094 -Slack : -14.182 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_G[0] +Slack : -14.020 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.227 +Clock Skew : -0.177 +Data Delay : 3.917 -Slack : -14.180 +Slack : -13.997 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.181 +Data Delay : 3.890 + +Slack : -13.949 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.020 +Data Delay : 4.003 + +Slack : -13.888 From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_G[0] +To Node : VGA_B[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.230 +Clock Skew : -0.021 +Data Delay : 3.941 -Slack : -14.176 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_G[1] +Slack : -13.887 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_B[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.221 +Clock Skew : -0.021 +Data Delay : 3.940 -Slack : -14.174 +Slack : -13.882 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.022 +Data Delay : 3.934 + +Slack : -13.881 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 3.778 + +Slack : -13.868 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.022 +Data Delay : 3.920 + +Slack : -13.841 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 3.894 + +Slack : -13.826 From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_R[1] +To Node : VGA_B[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.224 +Clock Skew : -0.021 +Data Delay : 3.879 -Slack : -14.164 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_G[2] +Slack : -13.816 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.209 +Clock Skew : -0.021 +Data Delay : 3.869 -Slack : -14.164 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_G[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.029 -Data Delay : 4.209 - -Slack : -14.164 -From Node : ula:ula_|video:video_|vga_vc[4] +Slack : -13.812 +From Node : ula:ula_|video:video_|vga_vc[2] To Node : VGA_R[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.214 +Clock Skew : -0.021 +Data Delay : 3.865 -Slack : -14.162 +Slack : -13.811 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 3.864 + +Slack : -13.806 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.022 +Data Delay : 3.858 + +Slack : -13.792 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.022 +Data Delay : 3.844 + +Slack : -13.784 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.022 +Data Delay : 3.836 + +Slack : -13.765 From Node : ula:ula_|video:video_|vga_vc[9] To Node : VGA_R[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.212 +Clock Skew : -0.021 +Data Delay : 3.818 + +Slack : -13.750 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 3.803 + +Slack : -13.747 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 3.800 + +Slack : -13.744 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 3.793 + +Slack : -13.742 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 3.795 + +Slack : -13.742 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 3.795 + +Slack : -13.740 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 3.793 + +Slack : -13.738 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.021 +Data Delay : 3.791 + +Slack : -13.731 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.022 +Data Delay : 3.783 + +Slack : -13.731 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : VGA_B[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 3.780 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : -4.979 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.058 +Data Delay : 3.010 + +Slack : -4.977 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.052 +Data Delay : 3.014 + +Slack : -4.861 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.051 +Data Delay : 2.899 + +Slack : -4.849 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.052 +Data Delay : 2.886 + +Slack : -4.418 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.376 +Data Delay : 3.131 + +Slack : -4.378 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.374 +Data Delay : 3.093 + +Slack : -4.335 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.371 +Data Delay : 3.053 + +Slack : -4.297 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.340 +Data Delay : 3.046 + +Slack : -4.275 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.355 +Data Delay : 3.009 + +Slack : -4.272 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.370 +Data Delay : 2.991 + +Slack : -4.269 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.390 +Data Delay : 2.968 + +Slack : -4.267 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.384 +Data Delay : 2.972 + +Slack : -4.253 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.369 +Data Delay : 2.973 + +Slack : -4.232 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.346 +Data Delay : 2.975 + +Slack : -4.230 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.369 +Data Delay : 2.950 + +Slack : -4.220 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.370 +Data Delay : 2.939 + +Slack : -4.204 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.339 +Data Delay : 2.954 + +Slack : -4.200 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.378 +Data Delay : 2.911 + +Slack : -4.196 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.383 +Data Delay : 2.902 + +Slack : -4.194 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.341 +Data Delay : 2.942 + +Slack : -4.159 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.351 +Data Delay : 2.897 + +Slack : -4.157 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.345 +Data Delay : 2.901 + +Slack : -4.153 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.358 +Data Delay : 2.884 + +Slack : -4.152 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.355 +Data Delay : 2.886 + +Slack : -4.151 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.383 +Data Delay : 2.857 + +Slack : -4.149 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.341 +Data Delay : 2.897 + +Slack : -4.139 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.384 +Data Delay : 2.844 + +Slack : -4.131 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.372 +Data Delay : 2.848 + +Slack : -4.130 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.369 +Data Delay : 2.850 + +Slack : -4.126 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.380 +Data Delay : 2.835 + +Slack : -4.124 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.374 +Data Delay : 2.839 + +Slack : -4.115 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.349 +Data Delay : 2.855 + +Slack : -4.109 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.371 +Data Delay : 2.827 + +Slack : -4.086 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.340 +Data Delay : 2.835 + +Slack : -4.073 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.370 +Data Delay : 2.792 + +Slack : -4.071 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.365 +Data Delay : 2.795 + +Slack : -4.071 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.359 +Data Delay : 2.801 + +Slack : -4.061 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.367 +Data Delay : 2.783 + +Slack : -4.059 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.356 +Data Delay : 2.792 + +Slack : -4.056 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.210 +Data Delay : 2.935 + +Slack : -4.055 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.369 +Data Delay : 2.775 + +Slack : -4.048 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.378 +Data Delay : 2.759 + +Slack : -4.044 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.373 +Data Delay : 2.760 + +Slack : -4.041 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.344 +Data Delay : 2.786 + +Slack : -4.035 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.341 +Data Delay : 2.783 + +Slack : -4.034 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.340 +Data Delay : 2.783 + +Slack : -4.029 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.345 +Data Delay : 2.773 + +Slack : -4.022 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.348 +Data Delay : 2.763 + +Slack : -4.021 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.363 +Data Delay : 2.747 + +Slack : -4.018 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.375 +Data Delay : 2.732 + +Slack : -4.010 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.380 +Data Delay : 2.719 + +Slack : -4.008 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.373 +Data Delay : 2.724 + +Slack : -4.003 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.348 +Data Delay : 2.744 + +Slack : -4.002 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.361 +Data Delay : 2.730 + +Slack : -4.001 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.336 +Data Delay : 2.754 + +Slack : -3.999 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.331 +Data Delay : 2.757 + +Slack : -3.999 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.338 +Data Delay : 2.750 + +Slack : -3.996 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.374 +Data Delay : 2.711 + +Slack : -3.994 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.350 +Data Delay : 2.733 + +Slack : -3.993 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.379 +Data Delay : 2.703 + +Slack : -3.989 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.333 +Data Delay : 2.745 + +Slack : -3.985 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.379 +Data Delay : 2.695 + +Slack : -3.985 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.363 +Data Delay : 2.711 + +Slack : -3.982 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.350 +Data Delay : 2.721 + +Slack : -3.980 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.382 +Data Delay : 2.687 + +Slack : -3.980 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.345 +Data Delay : 2.724 + +Slack : -3.975 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.367 +Data Delay : 2.697 + +Slack : -3.973 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.383 +Data Delay : 2.679 + +Slack : -3.973 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.205 +Data Delay : 2.857 + +Slack : -3.972 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.364 +Data Delay : 2.697 + +Slack : -3.971 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.378 +Data Delay : 2.682 + +Slack : -3.970 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.347 +Data Delay : 2.712 + +Slack : -3.963 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.339 +Data Delay : 2.713 + +Slack : -3.961 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.380 +Data Delay : 2.670 + +Slack : -3.961 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.380 +Data Delay : 2.670 + +Slack : -3.960 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.356 +Data Delay : 2.693 + +Slack : -3.954 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.204 +Data Delay : 2.839 + +Slack : -3.953 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.335 +Data Delay : 2.707 + +Slack : -3.950 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.371 +Data Delay : 2.668 + +Slack : -3.949 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.362 +Data Delay : 2.676 + +Slack : -3.948 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.359 +Data Delay : 2.678 + +Slack : -3.944 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.382 +Data Delay : 2.651 + +Slack : -3.936 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.343 +Data Delay : 2.682 + +Slack : -3.932 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.210 +Data Delay : 2.811 + +Slack : -3.926 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.213 +Data Delay : 2.802 + +Slack : -3.920 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.343 +Data Delay : 2.666 + +Slack : -3.916 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.356 +Data Delay : 2.649 + +Slack : -3.914 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.368 +Data Delay : 2.635 + +Slack : -3.914 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.350 +Data Delay : 2.653 + +Slack : -3.910 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.204 +Data Delay : 2.795 + +Slack : -3.898 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.350 +Data Delay : 2.637 + +Slack : -3.896 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.368 +Data Delay : 2.617 + +Slack : -3.896 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.369 +Data Delay : 2.616 + +Slack : -3.892 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.362 +Data Delay : 2.619 + +Slack : -3.879 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.348 +Data Delay : 2.620 + +Slack : -3.878 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.366 +Data Delay : 2.601 + +Slack : -3.875 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.370 +Data Delay : 2.594 + +Slack : -3.870 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.338 +Data Delay : 2.621 + +Slack : -3.862 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.350 +Data Delay : 2.601 + +Slack : -3.860 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.366 +Data Delay : 2.583 +--------------------------------------------------------------------------------+ @@ -21811,905 +23025,905 @@ Data Delay : 4.212 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -3.800 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.945 - -Slack : -3.800 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.945 - -Slack : -3.772 +Slack : -3.775 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.248 -Data Delay : 1.848 +Data Delay : 1.851 -Slack : -3.485 +Slack : -3.717 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 1.862 + +Slack : -3.717 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 1.862 + +Slack : -3.603 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 1.817 +Clock Skew : -0.226 +Data Delay : 1.748 -Slack : -3.485 +Slack : -3.603 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 1.817 +Clock Skew : -0.226 +Data Delay : 1.748 -Slack : -3.485 +Slack : -3.603 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 1.817 +Clock Skew : -0.226 +Data Delay : 1.748 -Slack : -3.485 +Slack : -3.603 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 1.817 +Clock Skew : -0.226 +Data Delay : 1.748 -Slack : -3.485 +Slack : -3.603 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 1.817 +Clock Skew : -0.226 +Data Delay : 1.748 -Slack : -3.150 +Slack : -3.360 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.020 -Data Delay : 1.501 +Clock Skew : -0.226 +Data Delay : 1.505 -Slack : -2.962 +Slack : -2.957 From Node : AUD_ADCDAT To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.047 -Data Delay : 1.286 +Clock Skew : -0.044 +Data Delay : 1.284 -Slack : 18.744 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.819 - -Slack : 18.744 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.819 - -Slack : 18.744 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.819 - -Slack : 18.744 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.819 - -Slack : 18.744 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.819 - -Slack : 18.745 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.818 - -Slack : 18.745 +Slack : 18.580 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.818 +Clock Skew : -0.274 +Data Delay : 1.984 -Slack : 18.745 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Slack : 18.583 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.818 +Clock Skew : -0.274 +Data Delay : 1.981 -Slack : 18.745 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.818 - -Slack : 18.745 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.818 - -Slack : 18.774 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.789 - -Slack : 18.774 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.789 - -Slack : 18.775 +Slack : 18.654 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.788 +Clock Skew : -0.274 +Data Delay : 1.910 -Slack : 18.775 +Slack : 18.654 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.788 +Clock Skew : -0.274 +Data Delay : 1.910 -Slack : 18.815 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.748 - -Slack : 18.815 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.748 - -Slack : 18.815 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.748 - -Slack : 18.815 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.748 - -Slack : 18.815 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.748 - -Slack : 18.840 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.723 - -Slack : 18.841 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.722 - -Slack : 18.845 +Slack : 18.657 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.718 +Clock Skew : -0.274 +Data Delay : 1.907 -Slack : 18.845 +Slack : 18.657 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.718 +Clock Skew : -0.274 +Data Delay : 1.907 -Slack : 18.872 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 18.675 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.889 + +Slack : 18.700 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.691 +Clock Skew : -0.274 +Data Delay : 1.864 -Slack : 18.872 +Slack : 18.700 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.864 + +Slack : 18.700 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.864 + +Slack : 18.700 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.864 + +Slack : 18.703 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.861 + +Slack : 18.703 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.861 + +Slack : 18.703 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.861 + +Slack : 18.703 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.861 + +Slack : 18.725 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.691 +Clock Skew : -0.274 +Data Delay : 1.839 -Slack : 18.872 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.691 - -Slack : 18.872 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.691 - -Slack : 18.872 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.691 - -Slack : 18.890 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.866 - -Slack : 18.890 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.866 - -Slack : 18.890 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.866 - -Slack : 18.893 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.670 - -Slack : 18.893 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.670 - -Slack : 18.893 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.670 - -Slack : 18.893 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.670 - -Slack : 18.893 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.670 - -Slack : 18.893 +Slack : 18.739 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.863 +Clock Skew : -0.274 +Data Delay : 1.825 -Slack : 18.893 +Slack : 18.739 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.863 +Clock Skew : -0.274 +Data Delay : 1.825 -Slack : 18.893 +Slack : 18.740 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.824 + +Slack : 18.740 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.824 + +Slack : 18.750 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.814 + +Slack : 18.750 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.814 + +Slack : 18.769 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.863 +Clock Skew : -0.277 +Data Delay : 1.792 -Slack : 18.902 +Slack : 18.769 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.277 +Data Delay : 1.792 + +Slack : 18.772 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.277 +Data Delay : 1.789 + +Slack : 18.772 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.277 +Data Delay : 1.789 + +Slack : 18.774 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.790 + +Slack : 18.774 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.790 + +Slack : 18.774 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.790 + +Slack : 18.774 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.790 + +Slack : 18.799 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.661 +Clock Skew : -0.274 +Data Delay : 1.765 -Slack : 18.902 +Slack : 18.799 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.661 +Clock Skew : -0.274 +Data Delay : 1.765 -Slack : 18.911 +Slack : 18.803 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.761 + +Slack : 18.811 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.753 + +Slack : 18.811 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.753 + +Slack : 18.823 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.741 + +Slack : 18.823 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.741 + +Slack : 18.823 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.741 + +Slack : 18.823 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.741 + +Slack : 18.823 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.741 + +Slack : 18.824 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.740 + +Slack : 18.824 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.740 + +Slack : 18.824 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.740 + +Slack : 18.824 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.740 + +Slack : 18.824 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.740 + +Slack : 18.831 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.733 + +Slack : 18.831 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.733 + +Slack : 18.831 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.733 + +Slack : 18.831 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.733 + +Slack : 18.865 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.277 +Data Delay : 1.696 + +Slack : 18.865 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.277 +Data Delay : 1.696 + +Slack : 18.868 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.696 + +Slack : 18.868 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.696 + +Slack : 18.877 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.687 + +Slack : 18.877 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.687 + +Slack : 18.895 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.669 + +Slack : 18.895 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.669 + +Slack : 18.895 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.669 + +Slack : 18.895 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.669 + +Slack : 18.895 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.669 + +Slack : 18.909 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 +Clock Skew : -0.277 Data Delay : 1.652 -Slack : 18.925 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.638 - -Slack : 18.925 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.638 - -Slack : 18.925 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.638 - -Slack : 18.925 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.638 - -Slack : 18.928 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.635 - -Slack : 18.928 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.635 - -Slack : 18.968 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 18.910 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.595 +Clock Skew : -0.277 +Data Delay : 1.651 -Slack : 18.969 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.787 - -Slack : 18.969 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.787 - -Slack : 18.969 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Slack : 18.914 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.787 +Clock Skew : -0.277 +Data Delay : 1.647 -Slack : 18.990 +Slack : 18.914 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.277 +Data Delay : 1.647 + +Slack : 18.923 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.573 +Clock Skew : -0.274 +Data Delay : 1.641 -Slack : 18.990 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.573 - -Slack : 18.990 +Slack : 18.923 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.573 +Clock Skew : -0.274 +Data Delay : 1.641 -Slack : 18.990 +Slack : 18.923 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.573 +Clock Skew : -0.274 +Data Delay : 1.641 -Slack : 18.990 +Slack : 18.923 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 +Clock Skew : -0.274 +Data Delay : 1.641 + +Slack : 18.947 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.617 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.612 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.612 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.612 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.612 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.612 + +Slack : 18.981 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.277 +Data Delay : 1.580 + +Slack : 18.989 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.087 +Data Delay : 1.762 + +Slack : 18.991 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 Data Delay : 1.573 Slack : 18.991 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.572 - -Slack : 19.009 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.554 - -Slack : 19.009 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.554 +Clock Skew : -0.274 +Data Delay : 1.573 -Slack : 19.020 +Slack : 18.992 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.277 +Data Delay : 1.569 + +Slack : 18.992 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.277 +Data Delay : 1.569 + +Slack : 18.992 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.087 +Data Delay : 1.759 + +Slack : 19.021 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 +Clock Skew : -0.274 Data Delay : 1.543 -Slack : 19.020 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 19.021 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 +Clock Skew : -0.274 Data Delay : 1.543 -Slack : 19.026 +Slack : 19.038 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.730 - -Slack : 19.026 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.730 - -Slack : 19.026 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.730 - -Slack : 19.033 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.723 - -Slack : 19.033 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.723 - -Slack : 19.033 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.723 - -Slack : 19.066 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.497 - -Slack : 19.066 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.497 - -Slack : 19.068 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.495 - -Slack : 19.068 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.495 - -Slack : 19.086 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.477 +Clock Skew : -0.277 +Data Delay : 1.523 -Slack : 19.113 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 19.067 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.497 + +Slack : 19.067 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.497 + +Slack : 19.067 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.497 + +Slack : 19.067 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.274 +Data Delay : 1.497 + +Slack : 19.074 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.637 +Clock Skew : -0.274 +Data Delay : 1.490 -Slack : 19.113 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 19.074 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.637 - -Slack : 19.113 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.637 - -Slack : 19.113 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.637 - -Slack : 19.113 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.637 - -Slack : 19.116 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.634 - -Slack : 19.116 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.634 - -Slack : 19.116 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.634 - -Slack : 19.116 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.634 - -Slack : 19.116 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.634 - -Slack : 19.144 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.612 - -Slack : 19.144 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.612 - -Slack : 19.144 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.082 -Data Delay : 1.612 - -Slack : 19.180 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.383 - -Slack : 19.180 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.383 - -Slack : 19.199 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.551 - -Slack : 19.199 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.551 +Clock Skew : -0.274 +Data Delay : 1.490 +--------------------------------------------------------------------------------+ @@ -22756,1814 +23970,908 @@ Data Delay : 0.359 -+--------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; -+--------------------------------------------------------------------------------+ -Slack : -2.194 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.522 -Data Delay : 0.739 - -Slack : -2.189 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.351 -Data Delay : 0.905 - -Slack : -1.955 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.330 -Data Delay : 0.692 - -Slack : -1.952 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.342 -Data Delay : 0.677 - -Slack : -1.942 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.316 -Data Delay : 0.693 - -Slack : -1.938 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.342 -Data Delay : 0.663 - -Slack : -1.936 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.327 -Data Delay : 0.676 - -Slack : -1.926 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.328 -Data Delay : 0.665 - -Slack : -1.780 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.346 -Data Delay : 0.501 - -Slack : -1.779 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.345 -Data Delay : 0.501 - -Slack : -1.778 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.346 -Data Delay : 0.499 - -Slack : -1.777 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.346 -Data Delay : 0.498 - -Slack : -1.765 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.331 -Data Delay : 0.501 - -Slack : -1.765 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|attr_prefetch[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.331 -Data Delay : 0.501 - -Slack : -1.765 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.331 -Data Delay : 0.501 - -Slack : -1.763 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.331 -Data Delay : 0.499 - -Slack : 36.994 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.045 -Data Delay : 2.616 - -Slack : 37.014 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.045 -Data Delay : 2.596 - -Slack : 37.020 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.045 -Data Delay : 2.590 - -Slack : 37.024 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.642 - -Slack : 37.045 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.042 -Data Delay : 2.568 - -Slack : 37.057 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.042 -Data Delay : 2.556 - -Slack : 37.059 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.042 -Data Delay : 2.554 - -Slack : 37.078 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.588 - -Slack : 37.079 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.039 -Data Delay : 2.537 - -Slack : 37.088 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.142 -Data Delay : 2.757 - -Slack : 37.098 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.139 -Data Delay : 2.744 - -Slack : 37.149 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.137 -Data Delay : 2.691 - -Slack : 37.156 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.510 - -Slack : 37.194 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.036 -Data Delay : 2.473 - -Slack : 37.209 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.036 -Data Delay : 2.458 - -Slack : 37.215 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.143 -Data Delay : 2.631 - -Slack : 37.235 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.031 -Data Delay : 2.437 - -Slack : 37.252 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.036 -Data Delay : 2.415 - -Slack : 37.268 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.041 -Data Delay : 2.346 - -Slack : 37.269 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.042 -Data Delay : 2.344 - -Slack : 37.269 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.134 -Data Delay : 2.568 - -Slack : 37.273 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.153 -Data Delay : 2.583 - -Slack : 37.277 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.045 -Data Delay : 2.333 - -Slack : 37.280 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.045 -Data Delay : 2.330 - -Slack : 37.284 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.038 -Data Delay : 2.381 - -Slack : 37.299 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.038 -Data Delay : 2.366 - -Slack : 37.299 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.032 -Data Delay : 2.372 - -Slack : 37.304 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.152 -Data Delay : 2.551 - -Slack : 37.304 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.045 -Data Delay : 2.306 - -Slack : 37.306 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.147 -Data Delay : 2.544 - -Slack : 37.310 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.148 -Data Delay : 2.541 - -Slack : 37.320 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|attr_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.133 -Data Delay : 2.516 - -Slack : 37.342 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.148 -Data Delay : 2.509 - -Slack : 37.344 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.140 -Data Delay : 2.499 - -Slack : 37.353 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.313 - -Slack : 37.357 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.038 -Data Delay : 2.308 - -Slack : 37.358 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|frame[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.036 -Data Delay : 2.309 - -Slack : 37.368 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.033 -Data Delay : 2.302 - -Slack : 37.370 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|frame[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.036 -Data Delay : 2.297 - -Slack : 37.376 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.147 -Data Delay : 2.474 - -Slack : 37.380 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.142 -Data Delay : 2.465 - -Slack : 37.388 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.042 -Data Delay : 2.225 - -Slack : 37.388 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.042 -Data Delay : 2.225 - -Slack : 37.397 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.143 -Data Delay : 2.449 - -Slack : 37.407 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.036 -Data Delay : 2.260 - -Slack : 37.408 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.154 -Data Delay : 2.449 - -Slack : 37.409 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.040 -Data Delay : 2.206 - -Slack : 37.416 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|frame[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.036 -Data Delay : 2.251 - -Slack : 37.422 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.244 - -Slack : 37.435 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|bits_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.148 -Data Delay : 2.416 - -Slack : 37.442 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.153 -Data Delay : 2.414 - -Slack : 37.446 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.148 -Data Delay : 2.405 - -Slack : 37.447 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.219 - -Slack : 37.447 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.219 - -Slack : 37.448 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|attr_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.133 -Data Delay : 2.388 - -Slack : 37.454 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.212 - -Slack : 37.457 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.042 -Data Delay : 2.156 - -Slack : 37.463 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|bits_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.149 -Data Delay : 2.389 - -Slack : 37.474 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.042 -Data Delay : 2.139 - -Slack : 37.491 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|attr_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.128 -Data Delay : 2.340 - -Slack : 37.501 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.165 - -Slack : 37.505 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|VGA_HS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.045 -Data Delay : 2.105 - -Slack : 37.506 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.036 -Data Delay : 2.161 - -Slack : 37.506 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.036 -Data Delay : 2.161 - -Slack : 37.512 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.038 -Data Delay : 2.153 - -Slack : 37.529 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.137 - -Slack : 37.529 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.137 - -Slack : 37.529 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|bits_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.143 -Data Delay : 2.317 - -Slack : 37.532 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.031 -Data Delay : 2.140 - -Slack : 37.533 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|VGA_VS -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.042 -Data Delay : 2.080 - -Slack : 37.540 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_hc[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.041 -Data Delay : 2.122 - -Slack : 37.541 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|attr_prefetch[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.139 -Data Delay : 2.301 - -Slack : 37.542 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|attr_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.132 -Data Delay : 2.293 - -Slack : 37.554 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : 0.141 -Data Delay : 2.290 - -Slack : 37.557 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.042 -Data Delay : 2.104 - -Slack : 37.558 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_vc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.042 -Data Delay : 2.103 - -Slack : 37.559 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.107 - -Slack : 37.559 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.107 - -Slack : 37.559 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.042 -Data Delay : 2.102 - -Slack : 37.559 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.107 - -Slack : 37.560 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_vc[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.042 -Data Delay : 2.101 - -Slack : 37.562 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.104 - -Slack : 37.562 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.104 - -Slack : 37.562 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 39.716 -Clock Skew : -0.037 -Data Delay : 2.104 -+--------------------------------------------------------------------------------+ - - - +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -0.698 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Slack : -0.053 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.524 -Data Delay : 1.034 +Clock Skew : 1.556 +Data Delay : 1.711 -Slack : -0.685 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Slack : -0.036 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.528 -Data Delay : 1.051 +Clock Skew : 1.557 +Data Delay : 1.729 -Slack : -0.677 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.527 -Data Delay : 1.058 - -Slack : -0.675 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 1.054 - -Slack : -0.661 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.526 -Data Delay : 1.073 - -Slack : -0.659 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.524 -Data Delay : 1.073 - -Slack : -0.659 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.527 -Data Delay : 1.076 - -Slack : -0.658 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.069 - -Slack : -0.655 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 1.066 - -Slack : -0.651 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.528 -Data Delay : 1.085 - -Slack : -0.648 -From Node : ula:ula_|video:video_|vram_address[6] +Slack : 0.540 +From Node : ula:ula_|video:video_|vram_address[7] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.079 +Clock Skew : 1.522 +Data Delay : 2.270 -Slack : -0.643 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.511 -Data Delay : 1.076 - -Slack : -0.642 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 1.083 - -Slack : -0.642 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 1.084 - -Slack : -0.640 +Slack : 0.548 From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.527 -Data Delay : 1.095 - -Slack : -0.639 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 1.090 - -Slack : -0.638 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.526 -Data Delay : 1.096 - -Slack : -0.638 -From Node : ula:ula_|video:video_|vram_address[6] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 1.083 +Clock Skew : 1.524 +Data Delay : 2.280 -Slack : -0.633 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.515 -Data Delay : 1.090 - -Slack : -0.633 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.528 -Data Delay : 1.103 - -Slack : -0.633 +Slack : 0.558 From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.528 -Data Delay : 1.103 - -Slack : -0.632 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.517 -Data Delay : 1.093 +Data Delay : 2.283 -Slack : -0.632 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Slack : 0.559 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.095 +Clock Skew : 1.514 +Data Delay : 2.281 -Slack : -0.630 +Slack : 0.561 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.524 +Data Delay : 2.293 + +Slack : 0.564 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.526 +Data Delay : 2.298 + +Slack : 0.575 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.526 +Data Delay : 2.309 + +Slack : 0.603 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.327 + +Slack : 0.606 From Node : ula:ula_|video:video_|vram_address[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 1.094 +Clock Skew : 1.517 +Data Delay : 2.331 -Slack : -0.630 -From Node : ula:ula_|video:video_|vram_address[6] +Slack : 0.606 +From Node : ula:ula_|video:video_|vram_address[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 1.096 +Clock Skew : 1.509 +Data Delay : 2.323 -Slack : -0.629 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 1.100 - -Slack : -0.629 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 1.095 - -Slack : -0.627 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 1.098 - -Slack : -0.624 +Slack : 0.610 From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.332 + +Slack : 0.618 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.575 +Data Delay : 2.401 + +Slack : 0.620 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.555 +Data Delay : 2.383 + +Slack : 0.623 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.558 +Data Delay : 2.389 + +Slack : 0.626 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.517 -Data Delay : 1.101 +Data Delay : 2.351 -Slack : -0.623 -From Node : ula:ula_|video:video_|vram_address[6] +Slack : 0.637 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.571 +Data Delay : 2.416 + +Slack : 0.637 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.522 +Data Delay : 2.367 + +Slack : 0.638 +From Node : ula:ula_|video:video_|vram_address[4] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.519 -Data Delay : 1.104 +Data Delay : 2.365 -Slack : -0.623 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Slack : 0.641 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 1.103 +Clock Skew : 1.570 +Data Delay : 2.419 -Slack : -0.622 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 1.104 - -Slack : -0.622 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.527 -Data Delay : 1.113 - -Slack : -0.621 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 1.103 - -Slack : -0.620 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.520 -Data Delay : 1.108 - -Slack : -0.620 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 1.109 - -Slack : -0.619 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 1.105 - -Slack : -0.619 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.108 - -Slack : -0.617 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.515 -Data Delay : 1.106 - -Slack : -0.617 -From Node : ula:ula_|video:video_|vram_address[9] +Slack : 0.646 +From Node : ula:ula_|video:video_|vram_address[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.526 -Data Delay : 1.117 +Clock Skew : 1.513 +Data Delay : 2.367 -Slack : -0.615 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 1.110 - -Slack : -0.615 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.112 - -Slack : -0.615 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.524 -Data Delay : 1.117 - -Slack : -0.614 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.511 -Data Delay : 1.105 - -Slack : -0.614 +Slack : 0.650 From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 1.107 - -Slack : -0.613 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 1.113 - -Slack : -0.612 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 1.117 - -Slack : -0.611 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.520 -Data Delay : 1.117 - -Slack : -0.611 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.520 -Data Delay : 1.117 - -Slack : -0.609 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.118 - -Slack : -0.609 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 1.116 - -Slack : -0.608 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.119 - -Slack : -0.607 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 1.114 - -Slack : -0.606 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 1.123 - -Slack : -0.605 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 1.120 - -Slack : -0.605 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 1.119 - -Slack : -0.605 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 1.121 - -Slack : -0.605 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.506 -Data Delay : 1.109 +Data Delay : 2.364 -Slack : -0.604 -From Node : ula:ula_|video:video_|vram_address[10] +Slack : 0.650 +From Node : ula:ula_|video:video_|vram_address[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.514 -Data Delay : 1.118 +Data Delay : 2.372 -Slack : -0.603 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.512 -Data Delay : 1.117 - -Slack : -0.603 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.124 - -Slack : -0.603 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 1.118 - -Slack : -0.603 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.528 -Data Delay : 1.133 - -Slack : -0.603 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.511 -Data Delay : 1.116 - -Slack : -0.603 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.124 - -Slack : -0.602 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 1.120 - -Slack : -0.601 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.511 -Data Delay : 1.118 - -Slack : -0.601 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 1.120 - -Slack : -0.600 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.127 - -Slack : -0.600 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.520 -Data Delay : 1.128 - -Slack : -0.600 +Slack : 0.651 From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.127 - -Slack : -0.600 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.526 -Data Delay : 1.134 - -Slack : -0.600 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 1.126 - -Slack : -0.599 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.524 -Data Delay : 1.133 - -Slack : -0.598 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 1.127 - -Slack : -0.598 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 1.128 - -Slack : -0.597 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 1.125 - -Slack : -0.596 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.515 -Data Delay : 1.127 - -Slack : -0.596 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 1.130 - -Slack : -0.596 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.527 -Data Delay : 1.139 - -Slack : -0.595 -From Node : ula:ula_|video:video_|vram_address[3] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 1.134 +Clock Skew : 1.516 +Data Delay : 2.375 -Slack : -0.594 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.526 -Data Delay : 1.140 - -Slack : -0.592 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.135 - -Slack : -0.592 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 1.134 - -Slack : -0.591 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.136 - -Slack : -0.591 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 1.135 - -Slack : -0.591 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.528 -Data Delay : 1.145 - -Slack : -0.591 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 1.125 - -Slack : -0.590 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 1.136 - -Slack : -0.590 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 1.131 - -Slack : -0.590 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.137 - -Slack : -0.589 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.515 -Data Delay : 1.134 - -Slack : -0.589 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 1.138 - -Slack : -0.589 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 1.137 - -Slack : -0.589 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 1.132 - -Slack : -0.588 +Slack : 0.651 From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.520 -Data Delay : 1.140 - -Slack : -0.587 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 1.138 - -Slack : -0.586 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.516 -Data Delay : 1.138 +Data Delay : 2.375 -Slack : -0.584 +Slack : 0.651 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.558 +Data Delay : 2.417 + +Slack : 0.653 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.375 + +Slack : 0.654 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.511 +Data Delay : 2.373 + +Slack : 0.655 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.513 +Data Delay : 2.376 + +Slack : 0.660 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.521 +Data Delay : 2.389 + +Slack : 0.661 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.521 +Data Delay : 2.390 + +Slack : 0.662 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.513 +Data Delay : 2.383 + +Slack : 0.665 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.387 + +Slack : 0.665 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.387 + +Slack : 0.666 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.508 +Data Delay : 2.382 + +Slack : 0.667 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.389 + +Slack : 0.669 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.426 +Data Delay : 2.303 + +Slack : 0.669 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.506 +Data Delay : 2.383 + +Slack : 0.669 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.507 +Data Delay : 2.384 + +Slack : 0.669 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.507 +Data Delay : 2.384 + +Slack : 0.671 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.509 +Data Delay : 2.388 + +Slack : 0.675 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.399 + +Slack : 0.675 From Node : ula:ula_|video:video_|vram_address[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.515 -Data Delay : 1.139 +Clock Skew : 1.503 +Data Delay : 2.386 -Slack : -0.584 -From Node : ula:ula_|video:video_|vram_address[10] +Slack : 0.677 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.517 +Data Delay : 2.402 + +Slack : 0.677 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.419 +Data Delay : 2.304 + +Slack : 0.681 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.509 +Data Delay : 2.398 + +Slack : 0.683 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.511 +Data Delay : 2.402 + +Slack : 0.687 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.507 +Data Delay : 2.402 + +Slack : 0.688 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.519 +Data Delay : 2.415 + +Slack : 0.688 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.506 +Data Delay : 2.402 + +Slack : 0.689 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.519 +Data Delay : 2.416 + +Slack : 0.689 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.507 +Data Delay : 2.404 + +Slack : 0.690 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.412 + +Slack : 0.690 +From Node : ula:ula_|video:video_|vram_address[4] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.510 -Data Delay : 1.134 +Clock Skew : 1.503 +Data Delay : 2.401 + +Slack : 0.691 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.522 +Data Delay : 2.421 + +Slack : 0.691 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.503 +Data Delay : 2.402 + +Slack : 0.693 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.427 +Data Delay : 2.328 + +Slack : 0.695 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.563 +Data Delay : 2.466 + +Slack : 0.695 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.522 +Data Delay : 2.425 + +Slack : 0.695 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.507 +Data Delay : 2.410 + +Slack : 0.695 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.508 +Data Delay : 2.411 + +Slack : 0.696 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.418 + +Slack : 0.696 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.415 +Data Delay : 2.319 + +Slack : 0.698 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.517 +Data Delay : 2.423 + +Slack : 0.698 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.421 + +Slack : 0.698 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.508 +Data Delay : 2.414 + +Slack : 0.699 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.562 +Data Delay : 2.469 + +Slack : 0.699 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.506 +Data Delay : 2.413 + +Slack : 0.699 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.504 +Data Delay : 2.411 + +Slack : 0.700 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.508 +Data Delay : 2.416 + +Slack : 0.701 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.565 +Data Delay : 2.474 + +Slack : 0.702 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.509 +Data Delay : 2.419 + +Slack : 0.703 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.506 +Data Delay : 2.417 + +Slack : 0.703 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.512 +Data Delay : 2.423 + +Slack : 0.704 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.406 +Data Delay : 2.318 + +Slack : 0.705 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.525 +Data Delay : 2.438 + +Slack : 0.706 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.524 +Data Delay : 2.438 + +Slack : 0.706 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.509 +Data Delay : 2.423 + +Slack : 0.706 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.509 +Data Delay : 2.423 + +Slack : 0.707 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.509 +Data Delay : 2.424 + +Slack : 0.709 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.506 +Data Delay : 2.423 + +Slack : 0.709 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.513 +Data Delay : 2.430 + +Slack : 0.710 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.503 +Data Delay : 2.421 + +Slack : 0.711 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.517 +Data Delay : 2.436 + +Slack : 0.712 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.511 +Data Delay : 2.431 + +Slack : 0.712 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.512 +Data Delay : 2.432 + +Slack : 0.712 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.423 +Data Delay : 2.343 + +Slack : 0.713 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.511 +Data Delay : 2.432 + +Slack : 0.713 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.575 +Data Delay : 2.496 + +Slack : 0.714 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.508 +Data Delay : 2.430 + +Slack : 0.714 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.508 +Data Delay : 2.430 + +Slack : 0.715 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.438 + +Slack : 0.716 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.522 +Data Delay : 2.446 + +Slack : 0.719 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.441 + +Slack : 0.720 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.442 + +Slack : 0.724 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.524 +Data Delay : 2.456 + +Slack : 0.724 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.424 +Data Delay : 2.356 + +Slack : 0.725 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.421 +Data Delay : 2.354 + +Slack : 0.726 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.421 +Data Delay : 2.355 +--------------------------------------------------------------------------------+ @@ -24613,49 +24921,22 @@ Data Delay : 0.576 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 0.179 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.307 - -Slack : 0.179 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.307 - -Slack : 0.179 +Slack : 0.178 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.044 +Clock Skew : 0.045 Data Delay : 0.307 -Slack : 0.183 +Slack : 0.184 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.047 -Data Delay : 0.314 - -Slack : 0.185 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 +Clock Skew : 0.046 Data Delay : 0.314 Slack : 0.186 @@ -24676,15 +24957,6 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.307 -Slack : 0.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.307 - Slack : 0.186 From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] @@ -24694,6 +24966,15 @@ Relationship : 0.000 Clock Skew : 0.044 Data Delay : 0.314 +Slack : 0.186 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + Slack : 0.186 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start @@ -24713,8 +24994,8 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -24730,22 +25011,22 @@ Relationship : 0.000 Clock Skew : 0.044 Data Delay : 0.314 -Slack : 0.186 -From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.307 -Slack : 0.186 -From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.307 Slack : 0.187 @@ -24757,33 +25038,51 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.307 +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.187 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.187 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.188 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.046 +Data Delay : 0.318 + Slack : 0.193 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.314 -Slack : 0.193 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.313 - -Slack : 0.193 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.321 - Slack : 0.194 From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] @@ -24794,26 +25093,8 @@ Clock Skew : 0.036 Data Delay : 0.314 Slack : 0.194 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.314 - -Slack : 0.194 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.314 - -Slack : 0.194 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -24821,103 +25102,121 @@ Clock Skew : 0.036 Data Delay : 0.314 Slack : 0.195 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.315 - -Slack : 0.195 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.315 - -Slack : 0.196 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.316 +Data Delay : 0.315 -Slack : 0.196 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Slack : 0.200 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.316 +Data Delay : 0.320 -Slack : 0.208 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.329 - -Slack : 0.209 +Slack : 0.201 From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.330 +Clock Skew : 0.036 +Data Delay : 0.321 -Slack : 0.212 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Slack : 0.204 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.333 +Clock Skew : 0.036 +Data Delay : 0.324 -Slack : 0.213 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.341 - -Slack : 0.221 +Slack : 0.208 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.342 +Clock Skew : 0.036 +Data Delay : 0.328 -Slack : 0.225 +Slack : 0.210 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.346 +Clock Skew : 0.036 +Data Delay : 0.330 -Slack : 0.272 +Slack : 0.243 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.372 + +Slack : 0.244 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.373 + +Slack : 0.244 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.373 + +Slack : 0.244 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.373 + +Slack : 0.245 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.374 + +Slack : 0.262 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.382 + +Slack : 0.266 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.392 +Clock Skew : 0.034 +Data Delay : 0.384 Slack : 0.288 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -24925,17 +25224,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.047 -Data Delay : 0.419 - -Slack : 0.289 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.047 -Data Delay : 0.420 +Clock Skew : 0.046 +Data Delay : 0.418 Slack : 0.289 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] @@ -24943,62 +25233,35 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.047 -Data Delay : 0.420 +Clock Skew : 0.046 +Data Delay : 0.419 -Slack : 0.290 +Slack : 0.291 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.047 +Clock Skew : 0.046 Data Delay : 0.421 -Slack : 0.294 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Slack : 0.292 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.060 +Data Delay : 0.436 + +Slack : 0.292 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.414 - -Slack : 0.294 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.414 - -Slack : 0.294 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.047 -Data Delay : 0.425 - -Slack : 0.295 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.415 - -Slack : 0.295 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.047 -Data Delay : 0.426 +Data Delay : 0.412 Slack : 0.296 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] @@ -25010,49 +25273,49 @@ Clock Skew : 0.036 Data Delay : 0.416 Slack : 0.296 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.416 +Clock Skew : 0.046 +Data Delay : 0.426 Slack : 0.296 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.416 +Clock Skew : 0.046 +Data Delay : 0.426 Slack : 0.297 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.417 -Slack : 0.297 +Slack : 0.298 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.034 +Data Delay : 0.416 + +Slack : 0.298 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.418 - -Slack : 0.298 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.418 +Data Delay : 0.419 Slack : 0.298 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] @@ -25072,23 +25335,113 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.419 -Slack : 0.303 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Slack : 0.302 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.431 +Clock Skew : 0.037 +Data Delay : 0.423 -Slack : 0.305 +Slack : 0.303 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.426 +Data Delay : 0.424 + +Slack : 0.305 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.623 + +Slack : 0.307 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.436 + +Slack : 0.307 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.436 + +Slack : 0.307 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.436 + +Slack : 0.307 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.436 + +Slack : 0.308 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.437 + +Slack : 0.308 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.437 + +Slack : 0.308 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.437 + +Slack : 0.308 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.429 + +Slack : 0.309 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.438 Slack : 0.309 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] @@ -25099,33 +25452,6 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.430 -Slack : 0.310 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.431 - -Slack : 0.313 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.441 - -Slack : 0.315 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.443 - Slack : 0.317 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] @@ -25135,221 +25461,194 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.437 -Slack : 0.318 +Slack : 0.320 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.446 - -Slack : 0.321 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.442 - -Slack : 0.323 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.451 - -Slack : 0.324 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.453 +Clock Skew : 0.036 +Data Delay : 0.440 Slack : 0.325 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.454 - -Slack : 0.346 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.474 - -Slack : 0.351 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.255 -Data Delay : 0.690 - -Slack : 0.359 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.479 +Data Delay : 0.445 -Slack : 0.361 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Slack : 0.328 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.490 +Clock Skew : 0.036 +Data Delay : 0.448 -Slack : 0.364 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Slack : 0.332 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.493 +Clock Skew : 0.036 +Data Delay : 0.452 -Slack : 0.364 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.493 - -Slack : 0.367 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : -0.138 -Data Delay : 0.313 - -Slack : 0.367 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.255 -Data Delay : 0.706 - -Slack : 0.371 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.499 - -Slack : 0.398 +Slack : 0.341 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.526 +Clock Skew : 0.036 +Data Delay : 0.461 -Slack : 0.401 +Slack : 0.341 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.461 + +Slack : 0.346 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.466 + +Slack : 0.370 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.490 + +Slack : 0.371 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.491 + +Slack : 0.373 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.493 + +Slack : 0.397 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.154 +Data Delay : 0.327 + +Slack : 0.398 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.255 -Data Delay : 0.740 +Clock Skew : 0.039 +Data Delay : 0.521 -Slack : 0.414 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Slack : 0.402 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.543 +Clock Skew : 0.039 +Data Delay : 0.525 -Slack : 0.416 +Slack : 0.404 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.527 + +Slack : 0.409 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.529 + +Slack : 0.410 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.530 + +Slack : 0.411 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.531 + +Slack : 0.424 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.545 + +Slack : 0.427 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.537 +Data Delay : 0.548 -Slack : 0.425 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Slack : 0.430 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.240 -Data Delay : 0.749 +Clock Skew : 0.037 +Data Delay : 0.551 -Slack : 0.426 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Slack : 0.432 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.240 -Data Delay : 0.750 - -Slack : 0.428 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.240 -Data Delay : 0.752 - -Slack : 0.428 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.556 - -Slack : 0.436 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.754 - -Slack : 0.437 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.755 +Clock Skew : 0.036 +Data Delay : 0.552 Slack : 0.437 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -25357,8 +25656,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.047 -Data Delay : 0.568 +Clock Skew : 0.046 +Data Delay : 0.567 Slack : 0.438 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] @@ -25366,71 +25665,17 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.047 -Data Delay : 0.569 - -Slack : 0.440 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.569 - -Slack : 0.442 -From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 Clock Skew : 0.046 -Data Delay : 0.572 +Data Delay : 0.568 Slack : 0.443 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.572 - -Slack : 0.443 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.572 - -Slack : 0.444 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.565 - -Slack : 0.445 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.566 - -Slack : 0.445 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : -0.138 -Data Delay : 0.391 +Clock Skew : -0.155 +Data Delay : 0.372 Slack : 0.446 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] @@ -25441,6 +25686,15 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.567 +Slack : 0.446 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.567 + Slack : 0.446 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] @@ -25451,67 +25705,121 @@ Clock Skew : 0.037 Data Delay : 0.567 Slack : 0.447 -From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.577 +Clock Skew : 0.036 +Data Delay : 0.567 -Slack : 0.447 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 0.448 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.047 -Data Delay : 0.578 +Clock Skew : 0.036 +Data Delay : 0.568 -Slack : 0.447 +Slack : 0.448 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.571 + +Slack : 0.448 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.047 +Clock Skew : 0.046 Data Delay : 0.578 -Slack : 0.448 +Slack : 0.449 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.577 + +Slack : 0.449 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.047 +Clock Skew : 0.046 Data Delay : 0.579 -Slack : 0.450 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.578 - -Slack : 0.450 +Slack : 0.449 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.047 -Data Delay : 0.581 +Clock Skew : 0.046 +Data Delay : 0.579 -Slack : 0.450 +Slack : 0.451 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.047 +Clock Skew : 0.046 Data Delay : 0.581 + +Slack : 0.452 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.572 + +Slack : 0.452 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.046 +Data Delay : 0.582 + +Slack : 0.452 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.046 +Data Delay : 0.582 + +Slack : 0.457 +From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.577 + +Slack : 0.457 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.577 +--------------------------------------------------------------------------------+ @@ -25592,8 +25900,8 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vga_vc[3] +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vga_vc[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -25609,15 +25917,6 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.307 -Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.307 - Slack : 0.186 From Node : ula:ula_|video:video_|vga_vc[6] To Node : ula:ula_|video:video_|vga_vc[6] @@ -25636,788 +25935,797 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.307 -Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vga_vc[8] +Slack : 0.293 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.307 +Data Delay : 0.414 -Slack : 0.364 +Slack : 0.294 From Node : ula:ula_|video:video_|frame[3] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.484 +Clock Skew : 0.037 +Data Delay : 0.415 -Slack : 0.431 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vram_address[10] +Slack : 0.300 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.557 +Clock Skew : 0.037 +Data Delay : 0.421 -Slack : 0.492 -From Node : ula:ula_|video:video_|bits_prefetch[3] -To Node : ula:ula_|video:video_|bits[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.031 -Data Delay : 0.607 - -Slack : 0.492 +Slack : 0.303 From Node : ula:ula_|video:video_|frame[4] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.612 +Clock Skew : 0.037 +Data Delay : 0.424 -Slack : 0.540 +Slack : 0.336 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.457 + +Slack : 0.400 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.521 + +Slack : 0.442 From Node : ula:ula_|video:video_|vga_vc[1] To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.042 -Data Delay : 0.666 +Data Delay : 0.568 -Slack : 0.546 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.666 - -Slack : 0.586 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.032 -Data Delay : 0.702 - -Slack : 0.589 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.032 -Data Delay : 0.705 - -Slack : 0.593 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.032 -Data Delay : 0.709 - -Slack : 0.611 -From Node : ula:ula_|video:video_|attr_prefetch[3] -To Node : ula:ula_|video:video_|attr[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.140 -Data Delay : 0.555 - -Slack : 0.637 -From Node : ula:ula_|video:video_|frame[0] +Slack : 0.442 +From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.756 +Clock Skew : 0.037 +Data Delay : 0.563 -Slack : 0.638 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vram_address[7] +Slack : 0.452 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.759 +Data Delay : 0.573 -Slack : 0.643 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.032 -Data Delay : 0.759 - -Slack : 0.645 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vram_address[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.032 -Data Delay : 0.761 - -Slack : 0.654 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[5] +Slack : 0.453 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.775 +Data Delay : 0.574 -Slack : 0.656 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.032 -Data Delay : 0.772 - -Slack : 0.661 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.032 -Data Delay : 0.777 - -Slack : 0.670 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.796 - -Slack : 0.672 +Slack : 0.456 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.793 +Data Delay : 0.577 -Slack : 0.678 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.799 - -Slack : 0.682 +Slack : 0.457 From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.032 -Data Delay : 0.798 - -Slack : 0.690 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vram_address[8] +To Node : ula:ula_|video:video_|vga_hc[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.811 +Data Delay : 0.578 -Slack : 0.691 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[6] +Slack : 0.481 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.811 +Data Delay : 0.601 -Slack : 0.692 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vram_address[11] +Slack : 0.505 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.813 +Data Delay : 0.626 -Slack : 0.694 -From Node : ula:ula_|video:video_|bits_prefetch[1] -To Node : ula:ula_|video:video_|bits[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.143 -Data Delay : 0.635 - -Slack : 0.698 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[9] +Slack : 0.519 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.819 +Data Delay : 0.640 -Slack : 0.699 +Slack : 0.524 From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.038 -Data Delay : 0.821 - -Slack : 0.705 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.825 - -Slack : 0.732 -From Node : ula:ula_|video:video_|attr_prefetch[1] -To Node : ula:ula_|video:video_|attr[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.158 -Data Delay : 0.658 - -Slack : 0.737 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vga_hc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.862 - -Slack : 0.742 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.042 -Data Delay : 0.868 +Data Delay : 0.650 -Slack : 0.747 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.868 - -Slack : 0.753 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.874 - -Slack : 0.754 +Slack : 0.534 From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.879 - -Slack : 0.756 -From Node : ula:ula_|video:video_|vga_vc[1] To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.877 +Clock Skew : 0.042 +Data Delay : 0.660 -Slack : 0.756 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.876 - -Slack : 0.756 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.877 - -Slack : 0.757 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.878 - -Slack : 0.759 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.880 - -Slack : 0.759 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.880 - -Slack : 0.762 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vga_hc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.883 - -Slack : 0.768 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.889 - -Slack : 0.769 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.038 -Data Delay : 0.891 - -Slack : 0.770 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.891 - -Slack : 0.771 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.892 - -Slack : 0.775 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.038 -Data Delay : 0.897 - -Slack : 0.781 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.902 - -Slack : 0.784 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vga_hc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.905 - -Slack : 0.791 -From Node : ula:ula_|video:video_|attr_prefetch[0] -To Node : ula:ula_|video:video_|attr[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.139 -Data Delay : 0.736 - -Slack : 0.791 -From Node : ula:ula_|video:video_|bits_prefetch[0] -To Node : ula:ula_|video:video_|bits[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.153 -Data Delay : 0.722 - -Slack : 0.791 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vga_hc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.912 - -Slack : 0.791 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vga_vc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.912 - -Slack : 0.803 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.924 - -Slack : 0.805 +Slack : 0.544 From Node : ula:ula_|video:video_|vga_hc[4] To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.926 +Clock Skew : 0.039 +Data Delay : 0.667 -Slack : 0.817 -From Node : ula:ula_|video:video_|frame[3] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.937 - -Slack : 0.819 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.940 - -Slack : 0.819 +Slack : 0.581 From Node : ula:ula_|video:video_|vga_hc[2] To Node : ula:ula_|video:video_|vram_address[12] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.038 -Data Delay : 0.941 +Clock Skew : 0.040 +Data Delay : 0.705 -Slack : 0.822 +Slack : 0.582 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.040 +Data Delay : 0.706 + +Slack : 0.582 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.040 +Data Delay : 0.706 + +Slack : 0.582 From Node : ula:ula_|video:video_|vga_hc[2] To Node : ula:ula_|video:video_|vram_address[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.038 -Data Delay : 0.944 +Clock Skew : 0.040 +Data Delay : 0.706 -Slack : 0.822 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[7] +Slack : 0.592 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.943 +Clock Skew : 0.041 +Data Delay : 0.717 -Slack : 0.827 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[9] +Slack : 0.595 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.720 + +Slack : 0.597 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.722 + +Slack : 0.598 +From Node : ula:ula_|video:video_|bits_prefetch[6] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.160 +Data Delay : 0.522 + +Slack : 0.610 +From Node : ula:ula_|video:video_|bits_prefetch[1] +To Node : ula:ula_|video:video_|bits[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.160 +Data Delay : 0.534 + +Slack : 0.611 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.736 + +Slack : 0.613 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.160 +Data Delay : 0.537 + +Slack : 0.619 +From Node : ula:ula_|video:video_|bits_prefetch[5] +To Node : ula:ula_|video:video_|bits[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.160 +Data Delay : 0.543 + +Slack : 0.633 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.947 +Data Delay : 0.753 -Slack : 0.829 +Slack : 0.636 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.756 + +Slack : 0.641 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.766 + +Slack : 0.652 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vga_hc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.773 + +Slack : 0.661 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.787 + +Slack : 0.673 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.799 + +Slack : 0.674 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.795 + +Slack : 0.680 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.806 + +Slack : 0.683 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.809 + +Slack : 0.686 +From Node : ula:ula_|video:video_|bits_prefetch[0] +To Node : ula:ula_|video:video_|bits[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.160 +Data Delay : 0.610 + +Slack : 0.691 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.812 + +Slack : 0.691 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.812 + +Slack : 0.691 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.812 + +Slack : 0.691 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.812 + +Slack : 0.693 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.819 + +Slack : 0.694 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.174 +Data Delay : 0.604 + +Slack : 0.695 From Node : ula:ula_|video:video_|bits_prefetch[4] To Node : ula:ula_|video:video_|bits[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : -0.160 -Data Delay : 0.753 +Data Delay : 0.619 -Slack : 0.830 -From Node : ula:ula_|video:video_|vga_hc[0] +Slack : 0.699 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.819 + +Slack : 0.702 +From Node : ula:ula_|video:video_|attr_prefetch[5] +To Node : ula:ula_|video:video_|attr[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.174 +Data Delay : 0.612 + +Slack : 0.703 +From Node : ula:ula_|video:video_|vga_hc[1] To Node : ula:ula_|video:video_|vram_address[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.955 +Clock Skew : 0.037 +Data Delay : 0.824 -Slack : 0.831 -From Node : ula:ula_|video:video_|vga_hc[4] +Slack : 0.707 +From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vga_hc[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.952 +Data Delay : 0.828 -Slack : 0.833 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[3] +Slack : 0.709 +From Node : ula:ula_|video:video_|attr_prefetch[7] +To Node : ula:ula_|video:video_|attr[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.174 +Data Delay : 0.619 + +Slack : 0.709 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|vga_hc[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.954 +Data Delay : 0.830 -Slack : 0.834 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.038 -Data Delay : 0.956 - -Slack : 0.834 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.038 -Data Delay : 0.956 - -Slack : 0.835 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.956 - -Slack : 0.836 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.043 -Data Delay : 0.963 - -Slack : 0.840 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.961 - -Slack : 0.840 +Slack : 0.709 From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.961 +Clock Skew : 0.042 +Data Delay : 0.835 -Slack : 0.842 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.963 - -Slack : 0.846 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.967 - -Slack : 0.861 -From Node : ula:ula_|video:video_|vga_hc[6] +Slack : 0.710 +From Node : ula:ula_|video:video_|vga_hc[9] To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.982 +Data Delay : 0.831 -Slack : 0.863 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[8] +Slack : 0.712 +From Node : ula:ula_|video:video_|attr_prefetch[4] +To Node : ula:ula_|video:video_|attr[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.983 +Clock Skew : -0.175 +Data Delay : 0.621 -Slack : 0.865 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[11] +Slack : 0.712 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.985 +Clock Skew : 0.042 +Data Delay : 0.838 -Slack : 0.866 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vga_vc[5] +Slack : 0.729 +From Node : ula:ula_|video:video_|attr_prefetch[0] +To Node : ula:ula_|video:video_|attr[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.038 -Data Delay : 0.988 +Clock Skew : -0.175 +Data Delay : 0.638 -Slack : 0.866 +Slack : 0.736 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.859 + +Slack : 0.736 From Node : ula:ula_|video:video_|vga_vc[4] To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.987 +Clock Skew : 0.042 +Data Delay : 0.862 -Slack : 0.878 +Slack : 0.744 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.867 + +Slack : 0.746 From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.872 + +Slack : 0.755 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.999 +Data Delay : 0.876 -Slack : 0.887 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 1.008 - -Slack : 0.887 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 1.008 - -Slack : 0.892 +Slack : 0.755 From Node : ula:ula_|video:video_|vga_vc[0] To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 1.013 +Clock Skew : 0.042 +Data Delay : 0.881 -Slack : 0.895 +Slack : 0.758 From Node : ula:ula_|video:video_|vga_vc[0] To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 1.016 +Clock Skew : 0.042 +Data Delay : 0.884 -Slack : 0.900 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Slack : 0.771 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.042 -Data Delay : 1.026 +Data Delay : 0.897 -Slack : 0.902 +Slack : 0.774 From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 1.023 +Clock Skew : 0.042 +Data Delay : 0.900 -Slack : 0.905 +Slack : 0.775 From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 1.026 +Clock Skew : 0.042 +Data Delay : 0.901 -Slack : 0.905 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[6] +Slack : 0.794 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 1.026 +Data Delay : 0.915 + +Slack : 0.803 +From Node : ula:ula_|video:video_|bits_prefetch[7] +To Node : ula:ula_|video:video_|bits[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.160 +Data Delay : 0.727 + +Slack : 0.809 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_hc[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.932 + +Slack : 0.811 +From Node : ula:ula_|video:video_|attr_prefetch[2] +To Node : ula:ula_|video:video_|attr[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.174 +Data Delay : 0.721 + +Slack : 0.821 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.947 + +Slack : 0.824 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.945 + +Slack : 0.828 +From Node : ula:ula_|video:video_|attr_prefetch[6] +To Node : ula:ula_|video:video_|attr[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.178 +Data Delay : 0.734 + +Slack : 0.832 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.953 + +Slack : 0.833 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.958 + +Slack : 0.833 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.958 + +Slack : 0.834 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.957 + +Slack : 0.836 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.957 + +Slack : 0.837 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.963 + +Slack : 0.841 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.964 + +Slack : 0.845 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.257 +Data Delay : 1.186 + +Slack : 0.845 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.257 +Data Delay : 1.186 + +Slack : 0.845 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.257 +Data Delay : 1.186 + +Slack : 0.845 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.257 +Data Delay : 1.186 + +Slack : 0.845 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.257 +Data Delay : 1.186 + +Slack : 0.845 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.257 +Data Delay : 1.186 +--------------------------------------------------------------------------------+ @@ -26425,743 +26733,743 @@ Data Delay : 1.026 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -4.738 +Slack : -4.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.225 -Data Delay : 2.836 +Data Delay : 2.791 -Slack : -4.738 +Slack : -4.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.227 -Data Delay : 2.834 +Data Delay : 2.789 -Slack : -4.738 +Slack : -4.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.230 -Data Delay : 2.831 +Data Delay : 2.786 -Slack : -4.737 +Slack : -4.692 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.834 +Data Delay : 2.789 -Slack : -4.737 +Slack : -4.692 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.228 -Data Delay : 2.832 +Data Delay : 2.787 -Slack : -4.634 +Slack : -4.583 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.248 -Data Delay : 2.710 +Data Delay : 2.659 -Slack : -4.629 +Slack : -4.575 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.251 -Data Delay : 2.702 +Data Delay : 2.648 -Slack : -4.481 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.626 - -Slack : -4.481 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.626 - -Slack : -4.481 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.626 - -Slack : -4.480 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.625 - -Slack : -4.480 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.625 - -Slack : -4.480 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.625 - -Slack : -4.480 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.625 - -Slack : -4.480 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.625 - -Slack : -4.480 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.625 - -Slack : -4.480 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.625 - -Slack : -4.475 +Slack : -4.430 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.625 +Clock Skew : -0.229 +Data Delay : 2.572 -Slack : -4.475 +Slack : -4.430 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.625 +Clock Skew : -0.229 +Data Delay : 2.572 -Slack : -4.475 +Slack : -4.430 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.625 +Clock Skew : -0.229 +Data Delay : 2.572 -Slack : -4.475 +Slack : -4.430 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.625 +Clock Skew : -0.229 +Data Delay : 2.572 -Slack : -4.475 +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.572 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.572 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.572 + +Slack : -4.430 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.625 +Clock Skew : -0.229 +Data Delay : 2.572 -Slack : -4.475 +Slack : -4.430 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.625 - -Slack : -4.475 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.620 - -Slack : -4.475 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.620 - -Slack : -4.475 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.620 - -Slack : -4.475 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 Clock Skew : -0.229 -Data Delay : 2.617 +Data Delay : 2.572 -Slack : -4.475 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.617 - -Slack : -4.475 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.617 - -Slack : -4.475 +Slack : -4.430 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.229 -Data Delay : 2.617 +Data Delay : 2.572 -Slack : -4.475 +Slack : -4.430 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.229 -Data Delay : 2.617 +Data Delay : 2.572 -Slack : -4.475 +Slack : -4.430 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.229 -Data Delay : 2.617 +Data Delay : 2.572 -Slack : -4.475 +Slack : -4.430 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.229 -Data Delay : 2.617 +Data Delay : 2.572 -Slack : -4.475 +Slack : -4.430 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.229 -Data Delay : 2.617 +Data Delay : 2.572 -Slack : -4.474 +Slack : -4.430 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.624 +Clock Skew : -0.229 +Data Delay : 2.572 -Slack : -4.474 +Slack : -4.429 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.624 +Clock Skew : -0.229 +Data Delay : 2.571 -Slack : -4.474 +Slack : -4.429 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.624 +Clock Skew : -0.229 +Data Delay : 2.571 -Slack : -4.474 +Slack : -4.429 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.624 +Clock Skew : -0.226 +Data Delay : 2.574 -Slack : -4.474 +Slack : -4.429 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.624 +Clock Skew : -0.226 +Data Delay : 2.574 -Slack : -4.474 +Slack : -4.429 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.624 +Clock Skew : -0.226 +Data Delay : 2.574 -Slack : -4.474 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.624 - -Slack : -4.474 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.624 - -Slack : -4.474 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.624 - -Slack : -4.474 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.624 - -Slack : -4.474 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.624 - -Slack : -4.474 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.624 - -Slack : -4.474 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.624 - -Slack : -4.300 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.047 -Data Delay : 2.624 - -Slack : -4.300 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.051 -Data Delay : 2.620 - -Slack : -4.300 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.051 -Data Delay : 2.620 - -Slack : -4.300 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.051 -Data Delay : 2.620 - -Slack : -4.293 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 2.625 - -Slack : -4.293 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 2.625 - -Slack : -4.293 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 2.625 - -Slack : -4.293 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 2.625 - -Slack : -4.293 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 2.625 - -Slack : -4.288 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.033 -Data Delay : 2.626 - -Slack : -4.288 +Slack : -4.429 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.033 -Data Delay : 2.626 +Clock Skew : -0.229 +Data Delay : 2.571 -Slack : -4.288 +Slack : -4.429 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.033 -Data Delay : 2.626 +Clock Skew : -0.229 +Data Delay : 2.571 -Slack : -4.286 +Slack : -4.429 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.041 -Data Delay : 2.616 +Clock Skew : -0.226 +Data Delay : 2.574 -Slack : -4.286 +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.571 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.571 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.571 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.228 +Data Delay : 2.572 + +Slack : -4.251 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.044 +Data Delay : 2.578 + +Slack : -4.240 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.041 -Data Delay : 2.616 +Data Delay : 2.570 -Slack : -4.286 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.041 -Data Delay : 2.616 - -Slack : -4.286 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.041 -Data Delay : 2.616 - -Slack : -4.286 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.032 -Data Delay : 2.625 - -Slack : -4.286 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.032 -Data Delay : 2.625 - -Slack : -4.286 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.032 -Data Delay : 2.625 - -Slack : -4.286 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.032 -Data Delay : 2.625 - -Slack : -4.286 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.032 -Data Delay : 2.625 - -Slack : -4.285 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.042 -Data Delay : 2.614 - -Slack : -4.285 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.041 -Data Delay : 2.615 - -Slack : -4.285 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.041 -Data Delay : 2.615 - -Slack : -4.285 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.041 -Data Delay : 2.615 - -Slack : -4.285 +Slack : -4.240 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.041 -Data Delay : 2.615 +Data Delay : 2.570 -Slack : -4.285 +Slack : -4.239 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.040 +Data Delay : 2.570 + +Slack : -4.239 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.040 +Data Delay : 2.570 + +Slack : -4.239 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.040 +Data Delay : 2.570 + +Slack : -4.239 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.040 +Data Delay : 2.570 + +Slack : -4.239 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.040 +Data Delay : 2.570 + +Slack : -4.239 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.040 +Data Delay : 2.570 + +Slack : -4.239 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.034 -Data Delay : 2.622 +Clock Skew : -0.040 +Data Delay : 2.570 -Slack : -4.275 +Slack : -4.239 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.020 -Data Delay : 2.626 +Clock Skew : -0.040 +Data Delay : 2.570 -Slack : -4.275 +Slack : -4.239 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.020 -Data Delay : 2.626 +Clock Skew : -0.039 +Data Delay : 2.571 -Slack : -4.247 +Slack : -4.238 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.037 +Data Delay : 2.572 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.236 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.578 + +Slack : -4.201 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.617 +Data Delay : 2.571 -Slack : -4.247 +Slack : -4.201 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.617 +Data Delay : 2.571 -Slack : -4.247 +Slack : -4.201 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.617 +Data Delay : 2.571 -Slack : -4.247 +Slack : -4.201 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.617 +Data Delay : 2.571 -Slack : -4.247 +Slack : -4.201 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.617 +Data Delay : 2.571 -Slack : -4.247 +Slack : -4.201 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.617 +Data Delay : 2.571 +--------------------------------------------------------------------------------+ @@ -27169,212 +27477,284 @@ Data Delay : 2.617 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 2.515 +Slack : 2.518 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.257 -Data Delay : 1.943 +Clock Skew : 0.256 +Data Delay : 1.945 -Slack : 2.515 +Slack : 2.518 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.257 -Data Delay : 1.943 +Clock Skew : 0.256 +Data Delay : 1.945 -Slack : 2.515 +Slack : 2.518 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.257 -Data Delay : 1.943 +Clock Skew : 0.256 +Data Delay : 1.945 -Slack : 2.515 +Slack : 2.518 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.257 -Data Delay : 1.943 +Clock Skew : 0.256 +Data Delay : 1.945 -Slack : 2.515 +Slack : 2.518 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.257 -Data Delay : 1.943 +Clock Skew : 0.256 +Data Delay : 1.945 -Slack : 2.515 +Slack : 2.518 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.257 -Data Delay : 1.943 +Clock Skew : 0.256 +Data Delay : 1.945 -Slack : 2.550 +Slack : 2.559 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.234 -Data Delay : 1.952 +Clock Skew : 0.224 +Data Delay : 1.951 -Slack : 2.550 +Slack : 2.559 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.234 -Data Delay : 1.952 +Clock Skew : 0.224 +Data Delay : 1.951 -Slack : 2.561 +Slack : 2.559 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.210 -Data Delay : 1.939 +Clock Skew : 0.224 +Data Delay : 1.951 -Slack : 2.561 +Slack : 2.559 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.211 -Data Delay : 1.940 +Clock Skew : 0.224 +Data Delay : 1.951 -Slack : 2.561 +Slack : 2.559 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.211 -Data Delay : 1.940 +Clock Skew : 0.224 +Data Delay : 1.951 -Slack : 2.561 +Slack : 2.559 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.211 -Data Delay : 1.940 +Clock Skew : 0.224 +Data Delay : 1.951 -Slack : 2.561 +Slack : 2.559 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.218 -Data Delay : 1.947 +Clock Skew : 0.224 +Data Delay : 1.951 -Slack : 2.561 +Slack : 2.559 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.221 -Data Delay : 1.950 +Clock Skew : 0.224 +Data Delay : 1.951 -Slack : 2.561 +Slack : 2.559 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.221 -Data Delay : 1.950 +Clock Skew : 0.224 +Data Delay : 1.951 -Slack : 2.561 +Slack : 2.559 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.221 -Data Delay : 1.950 +Clock Skew : 0.224 +Data Delay : 1.951 -Slack : 2.561 +Slack : 2.559 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.221 -Data Delay : 1.950 +Clock Skew : 0.224 +Data Delay : 1.951 -Slack : 2.561 +Slack : 2.559 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.221 -Data Delay : 1.950 +Clock Skew : 0.224 +Data Delay : 1.951 + +Slack : 2.559 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.224 +Data Delay : 1.951 + +Slack : 2.559 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.224 +Data Delay : 1.951 Slack : 2.562 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.211 -Data Delay : 1.941 +Clock Skew : 0.215 +Data Delay : 1.945 -Slack : 2.562 +Slack : 2.563 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.211 -Data Delay : 1.941 +Clock Skew : 0.212 +Data Delay : 1.943 -Slack : 2.562 +Slack : 2.563 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.212 +Data Delay : 1.943 + +Slack : 2.564 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.212 +Data Delay : 1.944 + +Slack : 2.564 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.212 +Data Delay : 1.944 + +Slack : 2.564 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.211 -Data Delay : 1.941 +Clock Skew : 0.212 +Data Delay : 1.944 -Slack : 2.562 +Slack : 2.564 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.211 -Data Delay : 1.941 +Clock Skew : 0.212 +Data Delay : 1.944 -Slack : 2.562 +Slack : 2.564 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.212 +Data Delay : 1.944 + +Slack : 2.564 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.212 +Data Delay : 1.944 + +Slack : 2.564 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.212 +Data Delay : 1.944 + +Slack : 2.564 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.211 -Data Delay : 1.941 +Clock Skew : 0.212 +Data Delay : 1.944 Slack : 2.565 From Node : KEY[0] @@ -27382,530 +27762,458 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.219 -Data Delay : 1.952 - -Slack : 2.565 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.219 -Data Delay : 1.952 - -Slack : 2.565 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.219 -Data Delay : 1.952 - -Slack : 2.570 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 Clock Skew : 0.213 -Data Delay : 1.951 +Data Delay : 1.946 -Slack : 2.570 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.213 -Data Delay : 1.951 - -Slack : 2.570 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.213 -Data Delay : 1.951 - -Slack : 2.570 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.213 -Data Delay : 1.951 - -Slack : 2.570 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.213 -Data Delay : 1.951 - -Slack : 2.576 +Slack : 2.574 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.205 -Data Delay : 1.949 +Clock Skew : 0.209 +Data Delay : 1.951 -Slack : 2.576 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.201 -Data Delay : 1.945 - -Slack : 2.576 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.201 -Data Delay : 1.945 - -Slack : 2.576 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.201 -Data Delay : 1.945 - -Slack : 2.758 +Slack : 2.761 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.024 -Data Delay : 1.950 +Clock Skew : 0.016 +Data Delay : 1.945 -Slack : 2.758 +Slack : 2.761 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.024 -Data Delay : 1.950 +Clock Skew : 0.016 +Data Delay : 1.945 -Slack : 2.758 +Slack : 2.761 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.024 -Data Delay : 1.950 +Clock Skew : 0.016 +Data Delay : 1.945 -Slack : 2.758 +Slack : 2.761 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.024 -Data Delay : 1.950 +Clock Skew : 0.016 +Data Delay : 1.945 -Slack : 2.758 +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.016 +Data Delay : 1.945 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.944 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.016 +Data Delay : 1.945 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.944 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.016 +Data Delay : 1.945 + +Slack : 2.761 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.024 -Data Delay : 1.950 +Clock Skew : 0.016 +Data Delay : 1.945 -Slack : 2.758 +Slack : 2.761 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.024 -Data Delay : 1.950 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.019 +Clock Skew : 0.016 Data Delay : 1.945 -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.019 -Data Delay : 1.945 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.949 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.949 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.949 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.949 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.949 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.949 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.949 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.949 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.949 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.949 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.949 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.949 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.949 - -Slack : 2.758 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.019 -Data Delay : 1.945 - -Slack : 2.759 +Slack : 2.761 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.943 +Clock Skew : 0.018 +Data Delay : 1.947 -Slack : 2.759 +Slack : 2.761 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.943 +Clock Skew : 0.018 +Data Delay : 1.947 -Slack : 2.759 +Slack : 2.761 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.943 - -Slack : 2.759 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.943 - -Slack : 2.759 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.943 - -Slack : 2.759 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.943 - -Slack : 2.759 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.943 - -Slack : 2.759 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.943 - -Slack : 2.765 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.951 +Data Delay : 1.947 -Slack : 2.765 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.951 - -Slack : 2.765 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.951 - -Slack : 2.765 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.951 - -Slack : 2.765 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.951 - -Slack : 2.765 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.951 - -Slack : 2.765 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.951 - -Slack : 2.766 +Slack : 2.761 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.952 +Data Delay : 1.947 -Slack : 2.766 +Slack : 2.761 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.952 +Data Delay : 1.947 -Slack : 2.766 +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.944 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.944 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.944 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.016 +Data Delay : 1.945 + +Slack : 2.762 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.016 +Data Delay : 1.946 + +Slack : 2.762 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.016 +Data Delay : 1.946 + +Slack : 2.762 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.016 +Data Delay : 1.946 + +Slack : 2.762 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.016 +Data Delay : 1.946 + +Slack : 2.762 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.016 +Data Delay : 1.946 + +Slack : 2.762 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.952 +Clock Skew : 0.016 +Data Delay : 1.946 -Slack : 2.901 +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.946 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.946 + +Slack : 2.897 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : -0.019 -Data Delay : 2.024 +Data Delay : 2.020 -Slack : 2.906 +Slack : 2.902 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : -0.016 -Data Delay : 2.032 +Data Delay : 2.028 -Slack : 3.005 +Slack : 3.008 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.009 -Data Delay : 2.154 +Data Delay : 2.157 -Slack : 3.005 +Slack : 3.008 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.007 -Data Delay : 2.152 +Data Delay : 2.155 -Slack : 3.005 +Slack : 3.008 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.007 -Data Delay : 2.152 +Data Delay : 2.155 -Slack : 3.005 +Slack : 3.008 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.004 -Data Delay : 2.149 +Data Delay : 2.152 -Slack : 3.006 +Slack : 3.009 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.005 -Data Delay : 2.151 +Data Delay : 2.154 +--------------------------------------------------------------------------------+ @@ -27913,6 +28221,22 @@ Data Delay : 2.151 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg + Slack : 9.208 Actual Width : 9.438 Required Width : 0.230 @@ -27935,7 +28259,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 Slack : 9.208 Actual Width : 9.438 @@ -27943,7 +28267,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg Slack : 9.208 Actual Width : 9.438 @@ -27951,23 +28275,31 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 -Slack : 9.209 -Actual Width : 9.439 +Slack : 9.208 +Actual Width : 9.438 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg -Slack : 9.209 -Actual Width : 9.439 +Slack : 9.208 +Actual Width : 9.438 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg Slack : 9.209 Actual Width : 9.439 @@ -28039,7 +28371,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -28047,7 +28379,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg Slack : 9.209 Actual Width : 9.439 @@ -28097,22 +28429,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg - Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28151,7 +28467,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -28159,23 +28475,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -28185,6 +28485,22 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 + Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28207,15 +28523,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -28225,14 +28533,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 - Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28247,7 +28547,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -28265,6 +28565,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 + Slack : 9.210 Actual Width : 9.440 Required Width : 0.230 @@ -28279,7 +28587,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28287,7 +28595,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28295,7 +28603,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg Slack : 9.210 Actual Width : 9.440 @@ -28303,7 +28611,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28311,7 +28619,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28327,7 +28643,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 Slack : 9.210 Actual Width : 9.440 @@ -28343,7 +28667,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 Slack : 9.210 Actual Width : 9.440 @@ -28351,7 +28675,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 Slack : 9.210 Actual Width : 9.440 @@ -28367,7 +28691,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28383,7 +28715,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28393,6 +28725,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 + Slack : 9.210 Actual Width : 9.440 Required Width : 0.230 @@ -28409,14 +28749,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -Slack : 9.211 -Actual Width : 9.441 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 - Slack : 9.211 Actual Width : 9.441 Required Width : 0.230 @@ -28455,7 +28787,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 Slack : 9.211 Actual Width : 9.441 @@ -28481,14 +28829,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Slack : 9.211 -Actual Width : 9.441 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 - Slack : 9.211 Actual Width : 9.441 Required Width : 0.230 @@ -28511,7 +28851,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 Slack : 9.211 Actual Width : 9.441 @@ -28519,7 +28859,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 Slack : 9.211 Actual Width : 9.441 @@ -28527,15 +28867,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 - -Slack : 9.211 -Actual Width : 9.441 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Slack : 9.212 Actual Width : 9.442 @@ -28583,7 +28915,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 Slack : 9.212 Actual Width : 9.442 @@ -28591,7 +28923,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 Slack : 9.212 Actual Width : 9.442 @@ -28599,7 +28931,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 Slack : 9.212 Actual Width : 9.442 @@ -28607,7 +28939,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0 Slack : 9.212 Actual Width : 9.442 @@ -28615,15 +28947,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 - -Slack : 9.212 -Actual Width : 9.442 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 Slack : 9.212 Actual Width : 9.442 @@ -28655,7 +28979,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 Slack : 9.212 Actual Width : 9.442 @@ -28663,7 +28987,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 Slack : 9.212 Actual Width : 9.442 @@ -28671,7 +28995,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 Slack : 9.212 Actual Width : 9.442 @@ -28679,39 +29003,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Slack : 9.213 -Actual Width : 9.443 +Slack : 9.212 +Actual Width : 9.442 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -Slack : 9.213 -Actual Width : 9.443 +Slack : 9.212 +Actual Width : 9.442 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 - -Slack : 9.213 -Actual Width : 9.443 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 - -Slack : 9.213 -Actual Width : 9.443 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +--------------------------------------------------------------------------------+ @@ -28719,805 +29027,805 @@ Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1 - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1 - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[0] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[1] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[2] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[3] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[4] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[5] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[7] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[0] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[1] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[2] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[3] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[4] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[5] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[6] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[7] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[3] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|frame[0] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|frame[3] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|frame[4] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[0] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[2] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[3] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[4] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[5] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[6] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[7] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[8] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[9] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[5] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[0] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[10] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[11] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[12] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[1] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[2] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[3] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[4] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[5] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[6] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[7] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[8] - -Slack : 19.640 -Actual Width : 19.856 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[9] - -Slack : 19.641 -Actual Width : 19.857 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[6] - -Slack : 19.641 -Actual Width : 19.857 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|frame[1] - -Slack : 19.641 -Actual Width : 19.857 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[1] - -Slack : 19.641 -Actual Width : 19.857 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[0] - -Slack : 19.641 -Actual Width : 19.857 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[1] - -Slack : 19.641 -Actual Width : 19.857 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[2] - -Slack : 19.641 -Actual Width : 19.857 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[3] - -Slack : 19.641 -Actual Width : 19.857 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[4] - -Slack : 19.641 -Actual Width : 19.857 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[6] - -Slack : 19.641 -Actual Width : 19.857 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[7] - -Slack : 19.641 -Actual Width : 19.857 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[8] - -Slack : 19.641 -Actual Width : 19.857 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_vc[9] - -Slack : 19.647 -Actual Width : 19.831 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[4] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 -Slack : 19.647 -Actual Width : 19.831 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|frame[2] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg -Slack : 19.649 -Actual Width : 19.833 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[0] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 -Slack : 19.649 -Actual Width : 19.833 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[2] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg -Slack : 19.649 -Actual Width : 19.833 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[7] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 -Slack : 19.650 -Actual Width : 19.834 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[1] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg -Slack : 19.650 -Actual Width : 19.834 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[5] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 -Slack : 19.650 -Actual Width : 19.834 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[6] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg -Slack : 19.654 -Actual Width : 19.870 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[2] - -Slack : 19.654 -Actual Width : 19.870 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[3] - -Slack : 19.654 -Actual Width : 19.870 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[6] - -Slack : 19.654 -Actual Width : 19.870 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[1] - -Slack : 19.654 -Actual Width : 19.838 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[4] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0 -Slack : 19.655 -Actual Width : 19.871 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[0] - -Slack : 19.655 -Actual Width : 19.871 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[5] - -Slack : 19.655 -Actual Width : 19.871 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[7] - -Slack : 19.659 -Actual Width : 19.843 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[0] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg -Slack : 19.659 -Actual Width : 19.843 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[5] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0 -Slack : 19.659 -Actual Width : 19.843 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[7] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg -Slack : 19.660 -Actual Width : 19.844 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[2] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 -Slack : 19.660 -Actual Width : 19.844 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[3] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg -Slack : 19.660 -Actual Width : 19.844 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[6] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0 -Slack : 19.660 -Actual Width : 19.844 -Required Width : 0.184 +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[1] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg -Slack : 19.660 -Actual Width : 19.876 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[4] - -Slack : 19.663 -Actual Width : 19.879 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[1] - -Slack : 19.664 -Actual Width : 19.880 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[2] - -Slack : 19.664 -Actual Width : 19.880 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[5] - -Slack : 19.664 -Actual Width : 19.880 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[6] - -Slack : 19.665 -Actual Width : 19.881 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[0] - -Slack : 19.665 -Actual Width : 19.881 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[7] - -Slack : 19.667 -Actual Width : 19.883 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[4] - -Slack : 19.667 -Actual Width : 19.883 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|frame[2] - -Slack : 19.674 -Actual Width : 19.858 -Required Width : 0.184 +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[2] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0 -Slack : 19.674 -Actual Width : 19.858 -Required Width : 0.184 +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[4] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg -Slack : 19.674 -Actual Width : 19.858 -Required Width : 0.184 +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[5] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 -Slack : 19.674 -Actual Width : 19.858 -Required Width : 0.184 +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[6] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg -Slack : 19.674 -Actual Width : 19.858 -Required Width : 0.184 +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[7] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 -Slack : 19.674 -Actual Width : 19.858 -Required Width : 0.184 +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits[0] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg -Slack : 19.674 -Actual Width : 19.858 -Required Width : 0.184 +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits[2] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -Slack : 19.674 -Actual Width : 19.858 -Required Width : 0.184 +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits[3] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -Slack : 19.674 -Actual Width : 19.858 -Required Width : 0.184 +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits[4] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -Slack : 19.674 -Actual Width : 19.858 -Required Width : 0.184 +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits[5] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 -Slack : 19.674 -Actual Width : 19.858 -Required Width : 0.184 +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits[6] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg -Slack : 19.674 -Actual Width : 19.858 -Required Width : 0.184 +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|bits[7] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +--------------------------------------------------------------------------------+ @@ -29589,6 +29897,38 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 + Slack : 20.633 Actual Width : 20.849 Required Width : 0.216 @@ -29629,14 +29969,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] - Slack : 20.633 Actual Width : 20.849 Required Width : 0.216 @@ -29653,6 +29985,54 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] + Slack : 20.633 Actual Width : 20.849 Required Width : 0.216 @@ -29677,6 +30057,46 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] + Slack : 20.633 Actual Width : 20.849 Required Width : 0.216 @@ -29731,103 +30151,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Slack : 20.634 Actual Width : 20.850 @@ -29835,7 +30159,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Slack : 20.634 Actual Width : 20.850 @@ -29843,7 +30167,15 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Slack : 20.634 Actual Width : 20.850 @@ -29861,14 +30193,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Data -Slack : 20.634 -Actual Width : 20.850 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle - Slack : 20.634 Actual Width : 20.850 Required Width : 0.216 @@ -29899,128 +30223,184 @@ Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Slack : 20.639 -Actual Width : 20.823 +Slack : 20.641 +Actual Width : 20.825 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Slack : 20.642 -Actual Width : 20.826 +Slack : 20.641 +Actual Width : 20.825 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Slack : 20.642 -Actual Width : 20.826 +Slack : 20.641 +Actual Width : 20.825 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Slack : 20.642 -Actual Width : 20.826 +Slack : 20.641 +Actual Width : 20.825 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Slack : 20.642 -Actual Width : 20.826 +Slack : 20.641 +Actual Width : 20.825 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Slack : 20.642 -Actual Width : 20.826 +Slack : 20.641 +Actual Width : 20.825 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Slack : 20.642 -Actual Width : 20.826 +Slack : 20.641 +Actual Width : 20.825 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] + +Slack : 20.641 +Actual Width : 20.825 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] + +Slack : 20.641 +Actual Width : 20.825 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.641 +Actual Width : 20.825 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.641 +Actual Width : 20.825 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.641 +Actual Width : 20.825 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.641 +Actual Width : 20.825 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.641 +Actual Width : 20.825 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.641 +Actual Width : 20.825 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] + +Slack : 20.643 +Actual Width : 20.827 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Slack : 20.642 -Actual Width : 20.826 +Slack : 20.643 +Actual Width : 20.827 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Slack : 20.642 -Actual Width : 20.826 +Slack : 20.643 +Actual Width : 20.827 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Slack : 20.642 -Actual Width : 20.826 +Slack : 20.643 +Actual Width : 20.827 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Slack : 20.642 -Actual Width : 20.826 +Slack : 20.643 +Actual Width : 20.827 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Slack : 20.642 -Actual Width : 20.826 +Slack : 20.643 +Actual Width : 20.827 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Slack : 20.642 -Actual Width : 20.826 +Slack : 20.643 +Actual Width : 20.827 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Slack : 20.642 -Actual Width : 20.826 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] - -Slack : 20.642 -Actual Width : 20.826 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 - Slack : 20.643 Actual Width : 20.827 Required Width : 0.184 @@ -30029,197 +30409,77 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Slack : 20.646 -Actual Width : 20.830 +Slack : 20.643 +Actual Width : 20.827 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Slack : 20.646 -Actual Width : 20.830 +Slack : 20.643 +Actual Width : 20.827 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Slack : 20.646 -Actual Width : 20.830 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] - -Slack : 20.646 -Actual Width : 20.862 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] - -Slack : 20.646 -Actual Width : 20.862 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] - -Slack : 20.646 -Actual Width : 20.862 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] - -Slack : 20.647 -Actual Width : 20.831 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] - -Slack : 20.647 -Actual Width : 20.831 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] - -Slack : 20.647 -Actual Width : 20.831 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] - -Slack : 20.647 -Actual Width : 20.831 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] - -Slack : 20.647 -Actual Width : 20.831 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] - -Slack : 20.647 -Actual Width : 20.863 +Slack : 20.649 +Actual Width : 20.865 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Slack : 20.652 -Actual Width : 20.868 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] - -Slack : 20.652 -Actual Width : 20.868 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] - -Slack : 20.652 -Actual Width : 20.868 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] - -Slack : 20.652 -Actual Width : 20.868 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] - -Slack : 20.652 -Actual Width : 20.868 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] - -Slack : 20.653 -Actual Width : 20.869 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] - -Slack : 20.653 -Actual Width : 20.869 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] - -Slack : 20.653 -Actual Width : 20.869 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] - -Slack : 20.653 -Actual Width : 20.837 +Slack : 20.651 +Actual Width : 20.835 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Slack : 20.654 -Actual Width : 20.838 -Required Width : 0.184 -Type : Low Pulse Width +Slack : 20.656 +Actual Width : 20.872 +Required Width : 0.216 +Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Slack : 20.654 -Actual Width : 20.838 -Required Width : 0.184 -Type : Low Pulse Width +Slack : 20.656 +Actual Width : 20.872 +Required Width : 0.216 +Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Slack : 20.654 -Actual Width : 20.838 -Required Width : 0.184 -Type : Low Pulse Width +Slack : 20.656 +Actual Width : 20.872 +Required Width : 0.216 +Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.656 +Actual Width : 20.872 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.656 +Actual Width : 20.872 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] Slack : 20.656 Actual Width : 20.872 @@ -30229,13 +30489,21 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Slack : 20.657 -Actual Width : 20.873 +Slack : 20.656 +Actual Width : 20.872 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] + +Slack : 20.656 +Actual Width : 20.872 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Slack : 20.657 Actual Width : 20.873 @@ -30243,7 +30511,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] Slack : 20.657 Actual Width : 20.873 @@ -30253,77 +30521,117 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Slack : 20.657 -Actual Width : 20.873 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 - Slack : 20.658 Actual Width : 20.874 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Slack : 20.658 -Actual Width : 20.874 +Slack : 20.659 +Actual Width : 20.875 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Slack : 20.658 -Actual Width : 20.874 +Slack : 20.659 +Actual Width : 20.875 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Slack : 20.658 -Actual Width : 20.874 +Slack : 20.659 +Actual Width : 20.875 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Slack : 20.658 -Actual Width : 20.874 +Slack : 20.659 +Actual Width : 20.875 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Slack : 20.658 -Actual Width : 20.874 +Slack : 20.659 +Actual Width : 20.875 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Slack : 20.658 -Actual Width : 20.874 +Slack : 20.659 +Actual Width : 20.875 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Slack : 20.658 -Actual Width : 20.874 +Slack : 20.659 +Actual Width : 20.875 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] + +Slack : 20.659 +Actual Width : 20.875 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.659 +Actual Width : 20.875 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.659 +Actual Width : 20.875 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.659 +Actual Width : 20.875 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.659 +Actual Width : 20.875 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.659 +Actual Width : 20.875 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +--------------------------------------------------------------------------------+ @@ -30449,6 +30757,20 @@ Target : ula:ula_|clocks:clocks_|counter[0] +--------------------------------------------------------------------------------+ ; Setup Times ; +--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 1.079 +Fall : 1.946 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 2.221 +Fall : 3.039 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : SW[*] Clock Port : CLOCK_50 Rise : 0.623 @@ -30465,15 +30787,15 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 0.727 -Fall : 1.326 +Rise : 0.728 +Fall : 1.321 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 1.571 -Fall : 2.164 +Rise : 1.575 +Fall : 2.139 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -30483,6 +30805,20 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Hold Times ; +--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -0.841 +Fall : -1.690 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -1.690 +Fall : -2.493 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : SW[*] Clock Port : CLOCK_50 Rise : -0.259 @@ -30500,14 +30836,14 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 Rise : -0.368 -Fall : -0.958 +Fall : -0.952 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -0.521 -Fall : -1.075 +Rise : -0.742 +Fall : -1.295 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -30519,134 +30855,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 5.580 -Fall : 5.635 +Rise : 6.008 +Fall : 6.095 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 5.580 -Fall : 5.625 +Rise : 6.008 +Fall : 6.095 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 5.505 -Fall : 5.539 +Rise : 5.342 +Fall : 5.537 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 5.404 -Fall : 5.487 +Rise : 5.828 +Fall : 5.903 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 5.446 -Fall : 5.494 +Rise : 5.590 +Fall : 5.692 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 5.520 -Fall : 5.635 +Rise : 5.726 +Fall : 5.854 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 5.202 -Fall : 5.229 +Rise : 5.482 +Fall : 5.521 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 5.518 -Fall : 5.563 +Rise : 5.820 +Fall : 5.903 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 5.123 -Fall : 5.139 +Rise : 5.363 +Fall : 5.393 Clock Edge : Rise Clock Reference : CLOCK_50 +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 4.649 +Fall : 4.764 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 4.449 +Fall : 4.536 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 4.487 +Fall : 4.591 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 4.253 +Fall : 4.359 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 4.439 +Fall : 4.548 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 4.649 +Fall : 4.764 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 4.334 +Fall : 4.411 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 4.547 +Fall : 4.697 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 4.198 +Fall : 4.263 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 5.245 -Fall : 5.016 +Rise : 5.045 +Fall : 4.866 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 5.245 -Fall : 5.016 +Rise : 5.045 +Fall : 4.866 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 3.732 -Fall : 3.798 +Rise : 3.467 +Fall : 3.470 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 3.874 -Fall : 3.906 +Rise : 3.638 +Fall : 3.715 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 4.084 -Fall : 4.133 +Rise : 3.865 +Fall : 3.962 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 4.497 -Fall : 4.525 +Rise : 3.736 +Fall : 3.757 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 4.376 -Fall : 4.389 +Rise : 3.736 +Fall : 3.757 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 4.269 -Fall : 4.424 +Rise : 3.606 +Fall : 3.673 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 4.497 -Fall : 4.525 +Rise : 3.656 +Fall : 3.658 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 4.497 -Fall : 4.525 +Rise : 3.656 +Fall : 3.658 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -30659,36 +31058,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 4.591 -Fall : 4.724 +Rise : 3.764 +Fall : 3.886 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 4.591 -Fall : 4.653 +Rise : 3.764 +Fall : 3.886 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 4.513 -Fall : 4.724 +Rise : 3.693 +Fall : 3.752 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 4.191 -Fall : 4.181 +Rise : 3.523 +Fall : 3.590 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 4.568 -Fall : 4.628 +Rise : 3.653 +Fall : 3.739 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -30734,20 +31133,6 @@ Fall : 1.656 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Data Port : GPIO_1[*] -Clock Port : CLOCK_50 -Rise : 3.116 -Fall : 3.166 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - -Data Port : GPIO_1[22] -Clock Port : CLOCK_50 -Rise : 3.116 -Fall : 3.166 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Data Port : I2C_SCLK Clock Port : CLOCK_50 Rise : 1.755 @@ -30770,134 +31155,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 4.214 -Fall : 4.248 +Rise : 4.404 +Fall : 4.492 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 4.214 -Fall : 4.251 +Rise : 4.714 +Fall : 4.811 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 4.222 -Fall : 4.248 +Rise : 4.756 +Fall : 4.806 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 4.368 -Fall : 4.438 +Rise : 4.404 +Fall : 4.492 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 4.606 -Fall : 4.686 +Rise : 4.619 +Fall : 4.708 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 4.692 -Fall : 4.780 +Rise : 4.805 +Fall : 4.924 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 4.363 -Fall : 4.381 +Rise : 4.528 +Fall : 4.559 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 4.592 -Fall : 4.641 +Rise : 4.418 +Fall : 4.501 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 4.306 -Fall : 4.313 +Rise : 4.478 +Fall : 4.502 Clock Edge : Rise Clock Reference : CLOCK_50 +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 3.074 +Fall : 3.195 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 3.656 +Fall : 3.753 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 3.705 +Fall : 3.857 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 3.537 +Fall : 3.607 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 3.562 +Fall : 3.684 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 3.074 +Fall : 3.195 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 3.587 +Fall : 3.750 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 3.787 +Fall : 3.888 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 3.402 +Fall : 3.449 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 2.273 -Fall : 2.290 +Rise : 2.246 +Fall : 2.250 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 3.835 -Fall : 3.604 +Rise : 3.784 +Fall : 3.550 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 2.273 -Fall : 2.290 +Rise : 2.246 +Fall : 2.250 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 2.458 -Fall : 2.487 +Rise : 2.373 +Fall : 2.393 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 2.659 -Fall : 2.705 +Rise : 2.590 +Fall : 2.631 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 2.264 -Fall : 2.281 +Rise : 2.286 +Fall : 2.308 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 2.264 -Fall : 2.281 +Rise : 2.504 +Fall : 2.535 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 2.302 -Fall : 2.324 +Rise : 2.286 +Fall : 2.308 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 2.380 -Fall : 2.412 +Rise : 2.428 +Fall : 2.440 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 2.380 -Fall : 2.412 +Rise : 2.428 +Fall : 2.440 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -30910,36 +31358,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 2.185 -Fall : 2.188 +Rise : 2.190 +Fall : 2.191 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 2.570 -Fall : 2.641 +Rise : 2.422 +Fall : 2.474 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 2.537 -Fall : 2.614 +Rise : 2.385 +Fall : 2.429 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 2.185 -Fall : 2.188 +Rise : 2.190 +Fall : 2.191 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 2.548 -Fall : 2.617 +Rise : 2.315 +Fall : 2.333 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -30985,20 +31433,6 @@ Fall : 1.414 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Data Port : GPIO_1[*] -Clock Port : CLOCK_50 -Rise : 2.717 -Fall : 2.767 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - -Data Port : GPIO_1[22] -Clock Port : CLOCK_50 -Rise : 2.717 -Fall : 2.767 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Data Port : I2C_SCLK Clock Port : CLOCK_50 Rise : 1.513 @@ -31021,10 +31455,10 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 2.814 +RR : 2.818 RF : FR : -FF : 3.176 +FF : 3.181 Input Port : SW[2] Output Port : LED[2] @@ -31032,6 +31466,20 @@ RR : 2.437 RF : FR : FF : 2.866 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 3.838 +RF : +FR : +FF : 4.613 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 2.537 +RF : +FR : +FF : 3.123 +--------------------------------------------------------------------------------+ @@ -31041,10 +31489,10 @@ FF : 2.866 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 2.728 +RR : 2.732 RF : FR : -FF : 3.095 +FF : 3.100 Input Port : SW[2] Output Port : LED[2] @@ -31052,6 +31500,20 @@ RR : 2.366 RF : FR : FF : 2.798 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 3.707 +RF : +FR : +FF : 4.473 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 2.459 +RF : +FR : +FF : 3.040 +--------------------------------------------------------------------------------+ @@ -31066,25 +31528,25 @@ No synchronizer chains to report. ; Multicorner Timing Analysis Summary ; +--------------------------------------------------------------------------------+ Clock : Worst-case Slack -Setup : -18.442 -Hold : -0.980 -Recovery : -6.277 -Removal : 2.515 +Setup : -18.123 +Hold : -0.053 +Recovery : -6.223 +Removal : 2.518 Minimum Pulse Width : 9.208 Clock : CLOCK_50 -Setup : -18.442 -Hold : -0.980 +Setup : -18.123 +Hold : -0.053 Recovery : N/A Removal : N/A Minimum Pulse Width : 9.208 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Setup : -3.760 +Setup : -7.533 Hold : 0.186 Recovery : N/A Removal : N/A -Minimum Pulse Width : 19.594 +Minimum Pulse Width : 19.600 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Setup : -2.914 @@ -31094,28 +31556,28 @@ Removal : N/A Minimum Pulse Width : 35.491 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Setup : -4.732 -Hold : 0.179 -Recovery : -6.277 -Removal : 2.515 -Minimum Pulse Width : 20.588 +Setup : -4.740 +Hold : 0.178 +Recovery : -6.223 +Removal : 2.518 +Minimum Pulse Width : 20.591 Clock : Design-wide TNS -Setup : -439.291 -Hold : -15.725 -Recovery : -463.435 +Setup : -879.875 +Hold : -0.089 +Recovery : -459.348 Removal : 0.0 Minimum Pulse Width : 0.0 Clock : CLOCK_50 -Setup : -343.502 -Hold : -15.725 +Setup : -549.338 +Hold : -0.089 Recovery : N/A Removal : N/A Minimum Pulse Width : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Setup : -51.393 +Setup : -284.813 Hold : 0.000 Recovery : N/A Removal : N/A @@ -31129,9 +31591,9 @@ Removal : N/A Minimum Pulse Width : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Setup : -41.482 +Setup : -42.810 Hold : 0.000 -Recovery : -463.435 +Recovery : -459.348 Removal : 0.000 Minimum Pulse Width : 0.000 +--------------------------------------------------------------------------------+ @@ -31141,6 +31603,20 @@ Minimum Pulse Width : 0.000 +--------------------------------------------------------------------------------+ ; Setup Times ; +--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 1.981 +Fall : 2.458 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 3.874 +Fall : 4.319 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : SW[*] Clock Port : CLOCK_50 Rise : 1.011 @@ -31157,15 +31633,15 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 1.279 -Fall : 1.518 +Rise : 1.262 +Fall : 1.505 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 2.849 -Fall : 3.096 +Rise : 2.823 +Fall : 3.104 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -31175,6 +31651,20 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Hold Times ; +--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -0.841 +Fall : -1.690 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -1.690 +Fall : -2.493 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : SW[*] Clock Port : CLOCK_50 Rise : -0.259 @@ -31192,14 +31682,14 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 Rise : -0.368 -Fall : -0.789 +Fall : -0.776 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -0.521 -Fall : -1.045 +Rise : -0.742 +Fall : -1.295 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -31211,134 +31701,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 9.508 -Fall : 9.465 +Rise : 10.359 +Fall : 10.359 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 9.508 -Fall : 9.442 +Rise : 10.359 +Fall : 10.359 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 9.432 -Fall : 9.375 +Rise : 9.229 +Fall : 9.317 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 9.271 -Fall : 9.300 +Rise : 10.015 +Fall : 9.971 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 9.328 -Fall : 9.294 +Rise : 9.628 +Fall : 9.644 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 9.450 -Fall : 9.465 +Rise : 9.826 +Fall : 9.843 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 8.840 -Fall : 8.792 +Rise : 9.397 +Fall : 9.318 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 9.421 -Fall : 9.372 +Rise : 9.972 +Fall : 9.975 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 8.746 -Fall : 8.690 +Rise : 9.201 +Fall : 9.152 Clock Edge : Rise Clock Reference : CLOCK_50 +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 7.986 +Fall : 7.983 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 7.696 +Fall : 7.696 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 7.783 +Fall : 7.821 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 7.371 +Fall : 7.388 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 7.739 +Fall : 7.774 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 7.986 +Fall : 7.975 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 7.534 +Fall : 7.528 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 7.914 +Fall : 7.983 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 7.285 +Fall : 7.303 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 8.516 -Fall : 8.160 +Rise : 8.197 +Fall : 7.907 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 8.516 -Fall : 8.160 +Rise : 8.197 +Fall : 7.907 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 6.585 -Fall : 6.515 +Rise : 6.071 +Fall : 5.974 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 6.795 -Fall : 6.701 +Rise : 6.410 +Fall : 6.400 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 7.175 -Fall : 7.075 +Rise : 6.836 +Fall : 6.810 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 7.714 -Fall : 7.667 +Rise : 6.558 +Fall : 6.425 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 7.498 -Fall : 7.427 +Rise : 6.558 +Fall : 6.425 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 7.522 -Fall : 7.480 +Rise : 6.366 +Fall : 6.305 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 7.714 -Fall : 7.667 +Rise : 6.429 +Fall : 6.279 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 7.714 -Fall : 7.667 +Rise : 6.429 +Fall : 6.279 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31351,36 +31904,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 7.938 -Fall : 7.956 +Rise : 6.621 +Fall : 6.664 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 7.839 -Fall : 7.811 +Rise : 6.621 +Fall : 6.664 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 7.938 -Fall : 7.956 +Rise : 6.426 +Fall : 6.412 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 7.171 -Fall : 7.100 +Rise : 6.231 +Fall : 6.211 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 7.809 -Fall : 7.789 +Rise : 6.443 +Fall : 6.428 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31426,20 +31979,6 @@ Fall : 2.773 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Data Port : GPIO_1[*] -Clock Port : CLOCK_50 -Rise : 5.405 -Fall : 5.408 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - -Data Port : GPIO_1[22] -Clock Port : CLOCK_50 -Rise : 5.405 -Fall : 5.408 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Data Port : I2C_SCLK Clock Port : CLOCK_50 Rise : 2.951 @@ -31462,134 +32001,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 4.214 -Fall : 4.248 +Rise : 4.404 +Fall : 4.492 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 4.214 -Fall : 4.251 +Rise : 4.714 +Fall : 4.811 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 4.222 -Fall : 4.248 +Rise : 4.756 +Fall : 4.806 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 4.368 -Fall : 4.438 +Rise : 4.404 +Fall : 4.492 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 4.606 -Fall : 4.686 +Rise : 4.619 +Fall : 4.708 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 4.692 -Fall : 4.780 +Rise : 4.805 +Fall : 4.924 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 4.363 -Fall : 4.381 +Rise : 4.528 +Fall : 4.559 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 4.592 -Fall : 4.641 +Rise : 4.418 +Fall : 4.501 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 4.306 -Fall : 4.313 +Rise : 4.478 +Fall : 4.502 Clock Edge : Rise Clock Reference : CLOCK_50 +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 3.074 +Fall : 3.195 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 3.656 +Fall : 3.753 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 3.705 +Fall : 3.857 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 3.537 +Fall : 3.607 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 3.562 +Fall : 3.684 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 3.074 +Fall : 3.195 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 3.587 +Fall : 3.750 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 3.787 +Fall : 3.888 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 3.402 +Fall : 3.449 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 2.273 -Fall : 2.290 +Rise : 2.246 +Fall : 2.250 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 3.835 -Fall : 3.604 +Rise : 3.784 +Fall : 3.550 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 2.273 -Fall : 2.290 +Rise : 2.246 +Fall : 2.250 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 2.458 -Fall : 2.487 +Rise : 2.373 +Fall : 2.393 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 2.659 -Fall : 2.705 +Rise : 2.590 +Fall : 2.631 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 2.264 -Fall : 2.281 +Rise : 2.286 +Fall : 2.308 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 2.264 -Fall : 2.281 +Rise : 2.504 +Fall : 2.535 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 2.302 -Fall : 2.324 +Rise : 2.286 +Fall : 2.308 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 2.380 -Fall : 2.412 +Rise : 2.428 +Fall : 2.440 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 2.380 -Fall : 2.412 +Rise : 2.428 +Fall : 2.440 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31602,36 +32204,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 2.185 -Fall : 2.188 +Rise : 2.190 +Fall : 2.191 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 2.570 -Fall : 2.641 +Rise : 2.422 +Fall : 2.474 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 2.537 -Fall : 2.614 +Rise : 2.385 +Fall : 2.429 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 2.185 -Fall : 2.188 +Rise : 2.190 +Fall : 2.191 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 2.548 -Fall : 2.617 +Rise : 2.315 +Fall : 2.333 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31677,20 +32279,6 @@ Fall : 1.414 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Data Port : GPIO_1[*] -Clock Port : CLOCK_50 -Rise : 2.717 -Fall : 2.767 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - -Data Port : GPIO_1[22] -Clock Port : CLOCK_50 -Rise : 2.717 -Fall : 2.767 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Data Port : I2C_SCLK Clock Port : CLOCK_50 Rise : 1.513 @@ -31713,10 +32301,10 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.621 +RR : 4.629 RF : FR : -FF : 4.680 +FF : 4.693 Input Port : SW[2] Output Port : LED[2] @@ -31724,6 +32312,20 @@ RR : 4.044 RF : FR : FF : 4.195 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 6.626 +RF : +FR : +FF : 7.003 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 4.318 +RF : +FR : +FF : 4.517 +--------------------------------------------------------------------------------+ @@ -31733,10 +32335,10 @@ FF : 4.195 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 2.728 +RR : 2.732 RF : FR : -FF : 3.095 +FF : 3.100 Input Port : SW[2] Output Port : LED[2] @@ -31744,6 +32346,20 @@ RR : 2.366 RF : FR : FF : 2.798 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 3.707 +RF : +FR : +FF : 4.473 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 2.459 +RF : +FR : +FF : 3.040 +--------------------------------------------------------------------------------+ @@ -33305,6 +33921,11 @@ I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps +Pin : raw_loader_in +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + Pin : KEY[0] I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps @@ -33315,12 +33936,12 @@ I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps -Pin : KEY[1] +Pin : PS2_DAT I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps -Pin : PS2_DAT +Pin : KEY[1] I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps @@ -38340,35 +38961,35 @@ FF Paths : 0 From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 187 +RR Paths : 227 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : CLOCK_50 -RR Paths : 945 +RR Paths : 1125 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] To Clock : CLOCK_50 -RR Paths : 13 +RR Paths : 7 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : CLOCK_50 To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 16 +RR Paths : 260 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 780 +RR Paths : 1054 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -38424,35 +39045,35 @@ FF Paths : 0 From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 187 +RR Paths : 227 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : CLOCK_50 -RR Paths : 945 +RR Paths : 1125 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] To Clock : CLOCK_50 -RR Paths : 13 +RR Paths : 7 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : CLOCK_50 To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 16 +RR Paths : 260 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 780 +RR Paths : 1054 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -38565,7 +39186,7 @@ Hold : 0 Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Thu Mar 31 14:04:16 2022 + Info: Processing started: Fri Apr 1 18:55:44 2022 Info: Command: quartus_sta spectrum -c spectrum Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled @@ -38589,522 +39210,519 @@ Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock -Warning (332125): Found combinational loop of 514 nodes - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~84|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~84|combout" - Warning (332126): Node "z80_|alu_|db[4]~8|datab" - Warning (332126): Node "z80_|alu_|db[4]~8|combout" - Warning (332126): Node "z80_|alu_|db[4]~10|dataa" - Warning (332126): Node "z80_|alu_|db[4]~10|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~11|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~11|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~12|datad" - Warning (332126): Node "z80_|alu_|db_high[0]~12|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~13|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~13|combout" - Warning (332126): Node "z80_|alu_|db[4]~10|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~4|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~4|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~5|datad" - Warning (332126): Node "z80_|alu_|db_high[1]~5|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~6|datad" - Warning (332126): Node "z80_|alu_|db_high[1]~6|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~7|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~7|combout" - Warning (332126): Node "z80_|alu_|db[5]~24|dataa" - Warning (332126): Node "z80_|alu_|db[5]~24|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~5|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~20|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~20|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~21|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~21|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~24|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~24|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~25|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~25|combout" - Warning (332126): Node "z80_|alu_|db[6]~22|dataa" - Warning (332126): Node "z80_|alu_|db[6]~22|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~14|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~14|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~15|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~15|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datad" - Warning (332126): Node "z80_|alu_|db[6]~21|datad" - Warning (332126): Node "z80_|alu_|db[6]~21|combout" - Warning (332126): Node "z80_|alu_|db[6]~22|datac" - Warning (332126): Node "z80_|bus_control_|db[6]~5|datac" - Warning (332126): Node "z80_|bus_control_|db[6]~5|combout" - Warning (332126): Node "z80_|bus_control_|db[6]~7|datad" - Warning (332126): Node "z80_|bus_control_|db[6]~7|combout" - Warning (332126): Node "z80_|sw1_|db_down[6]~0|datab" - Warning (332126): Node "z80_|sw1_|db_down[6]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~15|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~14|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~14|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~15|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~15|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~18|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~18|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~19|datac" - Warning (332126): Node "z80_|alu_|db_high[3]~19|combout" - Warning (332126): Node "z80_|alu_|db[7]~20|datac" - Warning (332126): Node "z80_|alu_|db[7]~20|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~15|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~26|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~26|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~28|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~28|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~29|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~30|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~30|combout" - Warning (332126): Node "z80_|alu_|db[7]~19|datac" - Warning (332126): Node "z80_|alu_|db[7]~19|combout" - Warning (332126): Node "z80_|alu_|db[7]~20|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~4|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~4|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~5|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~5|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~6|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~6|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~30|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~20|datac" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datab" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|datab" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~14|datad" - Warning (332126): Node "z80_|alu_|db_low[0]~16|datad" - Warning (332126): Node "z80_|alu_|db_low[0]~16|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~17|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~17|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~21|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" - Warning (332126): Node "z80_|alu_|db[0]~17|dataa" - Warning (332126): Node "z80_|alu_|db[0]~17|combout" - Warning (332126): Node "z80_|alu_|db[0]~18|datab" - Warning (332126): Node "z80_|alu_|db[0]~18|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~44|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~44|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~46|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~47|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~48|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~48|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~10|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~11|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~12|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~48|dataa" - Warning (332126): Node "z80_|alu_|db[0]~17|datac" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~17|datac" - Warning (332126): Node "z80_|sw2_|db_up[0]~0|datac" - Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|datad" - Warning (332126): Node "z80_|alu_control_|db[0]~9|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~12|datab" - Warning (332126): Node "z80_|alu_control_|db[0]~12|combout" - Warning (332126): Node "z80_|bus_control_|db[0]~15|datad" - Warning (332126): Node "z80_|bus_control_|db[0]~15|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~8|datab" - Warning (332126): Node "z80_|alu_control_|db[0]~8|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|datab" +Warning (332125): Found combinational loop of 511 nodes Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datac" - Warning (332126): Node "z80_|alu_control_|db[0]~9|datac" - Warning (332126): Node "z80_|alu_|db[0]~18|datac" - Warning (332126): Node "z80_|alu_|db_low[1]~13|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~13|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~14|datad" - Warning (332126): Node "z80_|alu_|db_low[1]~14|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~15|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~9|datab" + Warning (332126): Node "z80_|alu_control_|db[0]~9|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~12|datac" + Warning (332126): Node "z80_|alu_control_|db[0]~12|combout" + Warning (332126): Node "z80_|bus_control_|db[0]~17|datab" + Warning (332126): Node "z80_|bus_control_|db[0]~17|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~8|datac" + Warning (332126): Node "z80_|alu_control_|db[0]~8|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~9|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datab" + Warning (332126): Node "z80_|alu_|db[0]~19|datac" + Warning (332126): Node "z80_|alu_|db[0]~19|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa" Warning (332126): Node "z80_|alu_|db_low[1]~15|combout" - Warning (332126): Node "z80_|alu_|db[1]~16|dataa" - Warning (332126): Node "z80_|alu_|db[1]~16|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~14|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~16|datac" - Warning (332126): Node "z80_|alu_control_|db[1]~23|datab" - Warning (332126): Node "z80_|alu_control_|db[1]~23|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~24|datac" - Warning (332126): Node "z80_|alu_control_|db[1]~24|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~25|datab" - Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~26|datac" - Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~12|datac" - Warning (332126): Node "z80_|bus_control_|db[1]~12|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~13|datab" - Warning (332126): Node "z80_|bus_control_|db[1]~13|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~25|dataa" - Warning (332126): Node "z80_|alu_|db[1]~15|datab" - Warning (332126): Node "z80_|alu_|db[1]~15|combout" - Warning (332126): Node "z80_|alu_|db[1]~16|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab" - Warning (332126): Node "z80_|alu_control_|db[1]~24|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~35|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~35|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~37|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~37|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~38|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~38|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~39|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~39|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~7|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~7|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~8|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~9|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~39|datac" - Warning (332126): Node "z80_|alu_|db[1]~15|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~5|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~5|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~6|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~6|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~9|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~9|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~22|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~22|combout" - Warning (332126): Node "z80_|alu_|db[2]~12|datac" - Warning (332126): Node "z80_|alu_|db[2]~12|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~20|dataa" - Warning (332126): Node "z80_|alu_control_|db[2]~20|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~22|datab" - Warning (332126): Node "z80_|alu_control_|db[2]~22|combout" - Warning (332126): Node "z80_|bus_control_|db[2]~10|datac" - Warning (332126): Node "z80_|bus_control_|db[2]~10|combout" - Warning (332126): Node "z80_|bus_control_|db[2]~11|dataa" - Warning (332126): Node "z80_|bus_control_|db[2]~11|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~21|dataa" - Warning (332126): Node "z80_|alu_control_|db[2]~21|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~22|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~16|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~16|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|datac" + Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" + Warning (332126): Node "z80_|alu_|db[1]~13|datac" + Warning (332126): Node "z80_|alu_|db[1]~13|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~16|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~21|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~22|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~22|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" + Warning (332126): Node "z80_|alu_|db[0]~18|datab" + Warning (332126): Node "z80_|alu_|db[0]~18|combout" + Warning (332126): Node "z80_|alu_|db[0]~19|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" + Warning (332126): Node "z80_|alu_|db[1]~12|datac" + Warning (332126): Node "z80_|alu_|db[1]~12|combout" + Warning (332126): Node "z80_|alu_|db[1]~13|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~2|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~2|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~3|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~3|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~24|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~24|combout" + Warning (332126): Node "z80_|alu_|db[2]~15|dataa" + Warning (332126): Node "z80_|alu_|db[2]~15|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~15|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datab" + Warning (332126): Node "z80_|alu_|db[2]~14|datad" + Warning (332126): Node "z80_|alu_|db[2]~14|combout" + Warning (332126): Node "z80_|alu_|db[2]~15|datac" + Warning (332126): Node "z80_|alu_control_|db[2]~27|datab" + Warning (332126): Node "z80_|alu_control_|db[2]~27|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~29|datad" + Warning (332126): Node "z80_|alu_control_|db[2]~29|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~12|datab" + Warning (332126): Node "z80_|bus_control_|db[2]~12|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~13|datad" + Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa" + Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~29|datac" + Warning (332126): Node "z80_|alu_|db[2]~14|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|datad" Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~21|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|datab" + Warning (332126): Node "z80_|alu_control_|db[2]~28|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|datad" Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|datac" Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datab" - Warning (332126): Node "z80_|alu_|db[2]~11|dataa" - Warning (332126): Node "z80_|alu_|db[2]~11|combout" - Warning (332126): Node "z80_|alu_|db[2]~12|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~6|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~0|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~0|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~1|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~1|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~23|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~23|combout" - Warning (332126): Node "z80_|alu_|db[3]~13|dataa" - Warning (332126): Node "z80_|alu_|db[3]~13|combout" - Warning (332126): Node "z80_|alu_|db[3]~14|datab" - Warning (332126): Node "z80_|alu_|db[3]~14|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~53|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~53|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~55|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~55|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~56|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~56|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~57|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~57|combout" - Warning (332126): Node "z80_|alu_|db[3]~13|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~13|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~14|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~14|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~15|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~57|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~1|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~10|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~10|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~11|datad" - Warning (332126): Node "z80_|alu_|db_low[2]~5|datac" - Warning (332126): Node "z80_|alu_control_|db[3]~35|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~3|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~7|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~7|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~8|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~8|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~11|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~11|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~25|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~25|combout" + Warning (332126): Node "z80_|alu_|db[3]~10|datad" + Warning (332126): Node "z80_|alu_|db[3]~10|combout" + Warning (332126): Node "z80_|alu_|db[3]~11|dataa" + Warning (332126): Node "z80_|alu_|db[3]~11|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" - Warning (332126): Node "z80_|alu_|db[3]~14|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~34|datac" + Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa" Warning (332126): Node "z80_|alu_control_|db[3]~34|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~35|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~35|datad" Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|datad" Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|dataa" + Warning (332126): Node "z80_|alu_|db[3]~11|datac" Warning (332126): Node "z80_|bus_control_|db[3]~21|datad" Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" - Warning (332126): Node "z80_|sw1_|db_down[3]~2|datac" - Warning (332126): Node "z80_|sw1_|db_down[3]~2|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~34|datad" - Warning (332126): Node "z80_|alu_|db_high[0]~8|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~8|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~12|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~2|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~2|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~6|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~10|datac" - Warning (332126): Node "z80_|alu_|db_low[1]~10|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~12|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datad" Warning (332126): Node "z80_|alu_|db_low[1]~12|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datab" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~8|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~8|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~9|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~23|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~23|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~24|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~14|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~14|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~10|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~10|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~11|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~21|datad" + Warning (332126): Node "z80_|alu_|db_high[0]~21|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~25|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~26|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~26|combout" + Warning (332126): Node "z80_|alu_|db[4]~17|datac" + Warning (332126): Node "z80_|alu_|db[4]~17|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout" + Warning (332126): Node "z80_|alu_|db[4]~16|datad" + Warning (332126): Node "z80_|alu_|db[4]~16|combout" + Warning (332126): Node "z80_|alu_|db[4]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~7|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~24|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~19|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~20|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~20|combout" + Warning (332126): Node "z80_|alu_|db[5]~25|dataa" + Warning (332126): Node "z80_|alu_|db[5]~25|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~15|datab" + Warning (332126): Node "z80_|alu_control_|db[5]~15|combout" + Warning (332126): Node "z80_|bus_control_|db[5]~15|datac" + Warning (332126): Node "z80_|bus_control_|db[5]~15|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~10|dataa" + Warning (332126): Node "z80_|sw1_|db_down[5]~0|datab" + Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~14|dataa" + Warning (332126): Node "z80_|alu_control_|db[5]~14|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~15|datad" + Warning (332126): Node "z80_|alu_|db_high[0]~21|datac" Warning (332126): Node "z80_|alu_|db_low[0]~18|datac" Warning (332126): Node "z80_|alu_|db_low[0]~18|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~20|datad" + Warning (332126): Node "z80_|alu_|db_low[0]~20|dataa" Warning (332126): Node "z80_|alu_|db_low[0]~20|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~21|datac" - Warning (332126): Node "z80_|alu_|db_high[3]~17|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~17|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~18|datad" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~3|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~3|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~4|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~4|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~23|datad" - Warning (332126): Node "z80_|alu_|db_low[1]~13|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~62|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~62|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~64|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~64|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~65|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~65|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~66|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~66|combout" - Warning (332126): Node "z80_|alu_|db[2]~11|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~16|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~16|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~17|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~18|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~18|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~66|datad" - Warning (332126): Node "z80_|alu_control_|db[7]~16|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~23|datad" + Warning (332126): Node "z80_|alu_|db_high[2]~9|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~9|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~14|datad" + Warning (332126): Node "z80_|alu_|db_high[2]~14|combout" + Warning (332126): Node "z80_|alu_|db[6]~23|dataa" + Warning (332126): Node "z80_|alu_|db[6]~23|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datac" + Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~6|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~7|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~7|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~8|datac" + Warning (332126): Node "z80_|alu_|db_high[3]~8|combout" + Warning (332126): Node "z80_|alu_|db[7]~21|datac" + Warning (332126): Node "z80_|alu_|db[7]~21|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datac" + Warning (332126): Node "z80_|alu_|db[7]~20|datac" + Warning (332126): Node "z80_|alu_|db[7]~20|combout" + Warning (332126): Node "z80_|alu_|db[7]~21|dataa" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|dataa" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~21|datad" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datad" + Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~12|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~12|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~13|datac" + Warning (332126): Node "z80_|alu_control_|db[7]~16|datac" Warning (332126): Node "z80_|alu_control_|db[7]~16|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~18|dataa" + Warning (332126): Node "z80_|alu_control_|db[7]~18|datad" Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~8|dataa" - Warning (332126): Node "z80_|bus_control_|db[7]~8|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~9|datac" - Warning (332126): Node "z80_|bus_control_|db[7]~9|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~5|datab" + Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~7|datad" + Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" Warning (332126): Node "z80_|alu_control_|db[7]~17|datad" Warning (332126): Node "z80_|alu_control_|db[7]~17|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~18|datac" - Warning (332126): Node "z80_|alu_|db[7]~19|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datad" + Warning (332126): Node "z80_|alu_control_|db[7]~18|dataa" + Warning (332126): Node "z80_|alu_|db[7]~20|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~1|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~17|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~17|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|datac" Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|datac" Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~4|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~12|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~14|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~14|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~15|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~21|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~21|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~0|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~0|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~1|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~3|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~3|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~21|dataa" - Warning (332126): Node "z80_|alu_|db[6]~21|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~21|datab" - Warning (332126): Node "z80_|alu_control_|db[5]~29|datac" - Warning (332126): Node "z80_|alu_control_|db[5]~29|combout" - Warning (332126): Node "z80_|bus_control_|db[5]~17|datab" - Warning (332126): Node "z80_|bus_control_|db[5]~17|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~3|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~8|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~8|datad" - Warning (332126): Node "z80_|sw1_|db_down[5]~1|dataa" - Warning (332126): Node "z80_|sw1_|db_down[5]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~28|datab" - Warning (332126): Node "z80_|alu_control_|db[5]~28|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~29|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~2|datad" - Warning (332126): Node "z80_|alu_|db_low[1]~10|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~23|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~18|datad" - Warning (332126): Node "z80_|alu_|db_high[3]~17|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|dataa" + Warning (332126): Node "z80_|alu_control_|db[6]~20|datab" + Warning (332126): Node "z80_|alu_control_|db[6]~20|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~21|datac" + Warning (332126): Node "z80_|alu_control_|db[6]~21|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~22|datab" + Warning (332126): Node "z80_|alu_control_|db[6]~22|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~8|datab" + Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~9|dataa" + Warning (332126): Node "z80_|bus_control_|db[6]~9|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~21|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab" + Warning (332126): Node "z80_|alu_control_|db[6]~22|datac" + Warning (332126): Node "z80_|alu_|db[6]~22|datad" + Warning (332126): Node "z80_|alu_|db[6]~22|combout" + Warning (332126): Node "z80_|alu_|db[6]~23|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~12|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~4|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~4|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~6|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~6|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~24|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~15|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~15|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~27|datac" + Warning (332126): Node "z80_|alu_|db_high[3]~27|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~7|datac" + Warning (332126): Node "z80_|alu_|db[5]~24|datab" + Warning (332126): Node "z80_|alu_|db[5]~24|combout" + Warning (332126): Node "z80_|alu_|db[5]~25|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~28|datac" + Warning (332126): Node "z80_|alu_control_|db[5]~14|datac" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|datac" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|datad" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datac" - Warning (332126): Node "z80_|alu_|db[5]~23|datac" - Warning (332126): Node "z80_|alu_|db[5]~23|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~23|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datac" Warning (332126): Node "z80_|alu_|db[5]~24|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~71|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~71|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~73|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~73|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~74|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~74|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~75|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~75|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~19|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~20|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~21|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~75|dataa" - Warning (332126): Node "z80_|alu_|db[5]~23|datad" - Warning (332126): Node "z80_|alu_|db_high[0]~10|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~18|datac" Warning (332126): Node "z80_|alu_control_|db[4]~30|dataa" Warning (332126): Node "z80_|alu_control_|db[4]~30|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~31|dataa" + Warning (332126): Node "z80_|alu_control_|db[4]~31|datad" Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~32|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~32|datad" Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" Warning (332126): Node "z80_|bus_control_|db[4]~19|datab" Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~8|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~2|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~10|dataa" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~18|dataa" - Warning (332126): Node "z80_|alu_control_|db[4]~32|datac" - Warning (332126): Node "z80_|alu_|db_high[3]~17|datac" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datac" - Warning (332126): Node "z80_|alu_|db[4]~8|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datab" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~32|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~21|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~18|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~9|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~4|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~15|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~27|datab" + Warning (332126): Node "z80_|alu_|db[4]~16|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|combout" Warning (332126): Node "z80_|alu_control_|db[4]~30|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|datab" Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|datad" Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~80|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~80|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~82|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~82|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~83|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~83|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~84|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~0|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~22|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~23|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~23|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~24|datad" -Critical Warning (332081): Design contains combinational loop of 514 nodes. Estimating the delays through the loop. + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~18|datad" + Warning (332126): Node "z80_|alu_|db_high[2]~9|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~4|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~15|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~27|datad" + Warning (332126): Node "z80_|sw1_|db_down[3]~1|datad" + Warning (332126): Node "z80_|sw1_|db_down[3]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~34|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~8|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~23|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datac" + Warning (332126): Node "z80_|alu_|db[3]~10|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~2|datab" + Warning (332126): Node "z80_|alu_control_|db[1]~24|datad" + Warning (332126): Node "z80_|alu_control_|db[1]~24|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~26|datad" + Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~10|datab" + Warning (332126): Node "z80_|bus_control_|db[1]~10|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~11|datac" + Warning (332126): Node "z80_|bus_control_|db[1]~11|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~25|dataa" + Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~26|dataa" + Warning (332126): Node "z80_|alu_|db[1]~12|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~25|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datac" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~22|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa" + Warning (332126): Node "z80_|alu_|db[0]~18|datac" + Warning (332126): Node "z80_|sw2_|db_up[0]~0|datad" + Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~9|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|dataa" +Critical Warning (332081): Design contains combinational loop of 511 nodes. Estimating the delays through the loop. Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. @@ -39112,33 +39730,33 @@ Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -18.442 +Info (332146): Worst-case setup slack is -18.123 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -18.442 -343.502 CLOCK_50 - Info (332119): -4.732 -41.482 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): -3.760 -51.393 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -18.123 -549.338 CLOCK_50 + Info (332119): -7.533 -284.813 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -4.740 -42.810 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): -2.914 -2.914 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Info (332146): Worst-case hold slack is -0.980 +Info (332146): Worst-case hold slack is 0.210 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -0.980 -15.725 CLOCK_50 + Info (332119): 0.210 0.000 CLOCK_50 Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.344 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 0.357 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case recovery slack is -6.277 +Info (332146): Worst-case recovery slack is -6.223 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -6.277 -463.435 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case removal slack is 3.683 + Info (332119): -6.223 -459.348 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 3.698 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 3.683 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case minimum pulse width slack is 9.489 + Info (332119): 3.698 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case minimum pulse width slack is 9.488 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 9.489 0.000 CLOCK_50 - Info (332119): 19.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.488 0.000 CLOCK_50 + Info (332119): 19.602 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Info (332119): 20.595 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 35.503 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info: Analyzing Slow 1200mV 0C Model @@ -39149,34 +39767,34 @@ Warning (332060): Node: KEY[1] was determined to be a clock but was found withou Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -17.588 +Info (332146): Worst-case setup slack is -17.311 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -17.588 -332.785 CLOCK_50 - Info (332119): -4.423 -38.803 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): -3.309 -45.165 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -17.311 -526.609 CLOCK_50 + Info (332119): -6.686 -253.661 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -4.428 -40.009 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): -2.785 -2.785 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Info (332146): Worst-case hold slack is -0.780 +Info (332146): Worst-case hold slack is 0.298 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -0.780 -12.413 CLOCK_50 Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.300 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.304 0.000 CLOCK_50 Info (332119): 0.311 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case recovery slack is -5.784 +Info (332146): Worst-case recovery slack is -5.744 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -5.784 -426.554 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case removal slack is 3.369 + Info (332119): -5.744 -423.582 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 3.374 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 3.369 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case minimum pulse width slack is 9.488 + Info (332119): 3.374 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case minimum pulse width slack is 9.489 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 9.488 0.000 CLOCK_50 - Info (332119): 19.594 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): 20.588 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 9.489 0.000 CLOCK_50 + Info (332119): 19.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 20.591 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 35.491 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info: Analyzing Fast 1200mV 0C Model Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. @@ -39184,40 +39802,40 @@ Warning (332060): Node: KEY[1] was determined to be a clock but was found withou Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -15.171 +Info (332146): Worst-case setup slack is -14.971 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -15.171 -291.784 CLOCK_50 - Info (332119): -3.800 -34.909 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): -14.971 -442.545 CLOCK_50 + Info (332119): -4.979 -171.124 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -3.775 -35.541 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): -2.784 -2.784 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): -2.194 -30.204 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case hold slack is -0.698 +Info (332146): Worst-case hold slack is -0.053 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -0.698 -11.143 CLOCK_50 + Info (332119): -0.053 -0.089 CLOCK_50 Info (332119): 0.177 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 0.179 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.178 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 0.186 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case recovery slack is -4.738 +Info (332146): Worst-case recovery slack is -4.693 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -4.738 -361.836 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case removal slack is 2.515 + Info (332119): -4.693 -358.284 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 2.518 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 2.515 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 2.518 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332146): Worst-case minimum pulse width slack is 9.208 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 9.208 0.000 CLOCK_50 - Info (332119): 19.640 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 19.609 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Info (332119): 20.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 35.535 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 535 warnings - Info: Peak virtual memory: 451 megabytes - Info: Processing ended: Thu Mar 31 14:04:20 2022 +Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 532 warnings + Info: Peak virtual memory: 437 megabytes + Info: Processing ended: Fri Apr 1 18:55:48 2022 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:04 diff --git a/output_files/spectrum.sta.summary b/output_files/spectrum.sta.summary index 2495776..337cec4 100644 --- a/output_files/spectrum.sta.summary +++ b/output_files/spectrum.sta.summary @@ -3,31 +3,31 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1200mV 85C Model Setup 'CLOCK_50' -Slack : -18.442 -TNS : -343.502 - -Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -4.732 -TNS : -41.482 +Slack : -18.123 +TNS : -549.338 Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : -3.760 -TNS : -51.393 +Slack : -7.533 +TNS : -284.813 + +Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : -4.740 +TNS : -42.810 Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' Slack : -2.914 TNS : -2.914 Type : Slow 1200mV 85C Model Hold 'CLOCK_50' -Slack : -0.980 -TNS : -15.725 +Slack : 0.210 +TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' Slack : 0.342 TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 0.342 +Slack : 0.344 TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' @@ -35,19 +35,19 @@ Slack : 0.357 TNS : 0.000 Type : Slow 1200mV 85C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -6.277 -TNS : -463.435 +Slack : -6.223 +TNS : -459.348 Type : Slow 1200mV 85C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 3.683 +Slack : 3.698 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50' -Slack : 9.489 +Slack : 9.488 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : 19.600 +Slack : 19.602 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' @@ -59,31 +59,31 @@ Slack : 35.503 TNS : 0.000 Type : Slow 1200mV 0C Model Setup 'CLOCK_50' -Slack : -17.588 -TNS : -332.785 - -Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -4.423 -TNS : -38.803 +Slack : -17.311 +TNS : -526.609 Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : -3.309 -TNS : -45.165 +Slack : -6.686 +TNS : -253.661 + +Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : -4.428 +TNS : -40.009 Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' Slack : -2.785 TNS : -2.785 -Type : Slow 1200mV 0C Model Hold 'CLOCK_50' -Slack : -0.780 -TNS : -12.413 - Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' Slack : 0.298 TNS : 0.000 Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 0.298 +Slack : 0.300 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'CLOCK_50' +Slack : 0.304 TNS : 0.000 Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' @@ -91,23 +91,23 @@ Slack : 0.311 TNS : 0.000 Type : Slow 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -5.784 -TNS : -426.554 +Slack : -5.744 +TNS : -423.582 Type : Slow 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 3.369 +Slack : 3.374 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' -Slack : 9.488 +Slack : 9.489 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : 19.594 +Slack : 19.600 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 20.588 +Slack : 20.591 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' @@ -115,31 +115,31 @@ Slack : 35.491 TNS : 0.000 Type : Fast 1200mV 0C Model Setup 'CLOCK_50' -Slack : -15.171 -TNS : -291.784 +Slack : -14.971 +TNS : -442.545 + +Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' +Slack : -4.979 +TNS : -171.124 Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -3.800 -TNS : -34.909 +Slack : -3.775 +TNS : -35.541 Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' Slack : -2.784 TNS : -2.784 -Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : -2.194 -TNS : -30.204 - Type : Fast 1200mV 0C Model Hold 'CLOCK_50' -Slack : -0.698 -TNS : -11.143 +Slack : -0.053 +TNS : -0.089 Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' Slack : 0.177 TNS : 0.000 Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 0.179 +Slack : 0.178 TNS : 0.000 Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' @@ -147,11 +147,11 @@ Slack : 0.186 TNS : 0.000 Type : Fast 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -4.738 -TNS : -361.836 +Slack : -4.693 +TNS : -358.284 Type : Fast 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 2.515 +Slack : 2.518 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' @@ -159,7 +159,7 @@ Slack : 9.208 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : 19.640 +Slack : 19.609 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' diff --git a/pll.v b/pll.v index ecea797..c657616 100644 --- a/pll.v +++ b/pll.v @@ -102,9 +102,9 @@ module pll ( .vcounderrange ()); defparam altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 143, + altpll_component.clk0_divide_by = 2000, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 72, + altpll_component.clk0_multiply_by = 1007, altpll_component.clk0_phase_shift = "0", altpll_component.clk1_divide_by = 25, altpll_component.clk1_duty_cycle = 50, diff --git a/ram_video.qip b/ram_video.qip new file mode 100644 index 0000000..f23f917 --- /dev/null +++ b/ram_video.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_video.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_video_bb.v"] diff --git a/ram_video.v b/ram_video.v new file mode 100644 index 0000000..a46640c --- /dev/null +++ b/ram_video.v @@ -0,0 +1,244 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: ram_video.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ram_video ( + address_a, + address_b, + clock_a, + clock_b, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [13:0] address_a; + input [13:0] address_b; + input clock_a; + input clock_b; + input [7:0] data_a; + input [7:0] data_b; + input wren_a; + input wren_b; + output [7:0] q_a; + output [7:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock_a; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] sub_wire1; + wire [7:0] q_a = sub_wire0[7:0]; + wire [7:0] q_b = sub_wire1[7:0]; + + altsyncram altsyncram_component ( + .clock0 (clock_a), + .wren_a (wren_a), + .address_b (address_b), + .clock1 (clock_b), + .data_b (data_b), + .wren_b (wren_b), + .address_a (address_a), + .data_a (data_a), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK1", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK1", + altsyncram_component.intended_device_family = "Cyclone IV E", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 16384, + altsyncram_component.numwords_b = 16384, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.outdata_reg_b = "CLOCK1", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 14, + altsyncram_component.widthad_b = 14, + altsyncram_component.width_a = 8, + altsyncram_component.width_b = 8, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "5" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]" +// Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]" +// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" +// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" +// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" +// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]" +// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" +// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0 +// Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 +// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/ram_video_bb.v b/ram_video_bb.v new file mode 100644 index 0000000..27248ac --- /dev/null +++ b/ram_video_bb.v @@ -0,0 +1,182 @@ +// megafunction wizard: %RAM: 2-PORT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: ram_video.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module ram_video ( + address_a, + address_b, + clock_a, + clock_b, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [13:0] address_a; + input [13:0] address_b; + input clock_a; + input clock_b; + input [7:0] data_a; + input [7:0] data_b; + input wren_a; + input wren_b; + output [7:0] q_a; + output [7:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock_a; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "5" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]" +// Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]" +// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" +// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" +// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" +// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]" +// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" +// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0 +// Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 +// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/simulation/modelsim/spectrum.vo b/simulation/modelsim/spectrum.vo index acde13f..c5a510e 100644 --- a/simulation/modelsim/spectrum.vo +++ b/simulation/modelsim/spectrum.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/31/2022 14:04:24" +// DATE "04/01/2022 18:55:52" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -49,14 +49,15 @@ module spectrum ( VGA_VS, SW, GPIO_1, - buzzer_out); + buzzer_out, + raw_loader_in); output [7:0] LED; input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -inout I2C_SCLK; -inout I2C_SDAT; +output I2C_SCLK; +output I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -71,6 +72,7 @@ output VGA_VS; input [3:0] SW; output [33:0] GPIO_1; output buzzer_out; +input raw_loader_in; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -141,10 +143,11 @@ output buzzer_out; // I2C_SDAT => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[1] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: Default // SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// raw_loader_in => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: Default // KEY[0] => Location: PIN_J15, I/O Standard: 3.3-V LVTTL, Current Strength: Default // CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default -// KEY[1] => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_DAT => Location: PIN_B7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// KEY[1] => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_CLK => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default // AUD_ADCDAT => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -175,7 +178,692 @@ wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; +wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; wire \z80_|sequencer_|ena_M~combout ; +wire \KEY[1]~input_o ; +wire \z80_|interrupts_|nmi_armed~feeder_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; +wire \z80_|interrupts_|nmi_armed~q ; +wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~q ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~q ; +wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal1~7_combout ; +wire \z80_|pla_decode_|Equal2~0_combout ; +wire \z80_|pla_decode_|Equal36~0_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|pla_decode_|Equal2~1_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_sw_1d~8_combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~1_combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; +wire \z80_|execute_|ctl_state_iy_set~2_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|pla_decode_|Equal50~0_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|execute_|ixy_d~17_combout ; +wire \z80_|execute_|ixy_d~5_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~15_combout ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|execute_|ctl_ir_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~14_combout ; +wire \z80_|execute_|ctl_mWrite~2_combout ; +wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|ctl_reg_in_hi~5_combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|pla_decode_|Equal9~0_combout ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|pla_decode_|Equal9~1_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|pla_decode_|Equal1~4_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; +wire \z80_|pla_decode_|Equal24~1_combout ; +wire \z80_|pla_decode_|Equal34~0_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|sequencer_|M5~0_combout ; +wire \z80_|sequencer_|M5~q ; +wire \z80_|execute_|ctl_reg_in_hi~2_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; +wire \z80_|execute_|ctl_ir_we~7_combout ; +wire \z80_|pla_decode_|Equal52~1_combout ; +wire \z80_|execute_|ctl_state_alu~14_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|execute_|fMRead~17_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|fMRead~16_combout ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_flags_alu~6_combout ; +wire \z80_|execute_|ctl_ir_we~6_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_reg_in_hi~3_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; +wire \z80_|execute_|ctl_mRead~36_combout ; +wire \z80_|execute_|ctl_alu_op_low~9_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|execute_|ctl_alu_op_low~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|alu_|db_low[2]~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|pla_decode_|Equal1~5_combout ; +wire \z80_|execute_|ctl_alu_op_low~14_combout ; +wire \z80_|execute_|ctl_alu_op_low~12_combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~11_combout ; +wire \z80_|execute_|nextM~2_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_oe~3_combout ; +wire \z80_|execute_|ctl_alu_op_low~15_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~13_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|ctl_flags_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op_low~13_combout ; +wire \z80_|execute_|ctl_flags_bus~15_combout ; +wire \z80_|execute_|ctl_flags_bus~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|execute_|ctl_flags_bus~12_combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_bus_db_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|execute_|ctl_alu_op_low~10_combout ; +wire \z80_|execute_|fMWrite~11_combout ; +wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|execute_|ctl_alu_op_low~22_combout ; +wire \z80_|execute_|ctl_alu_op_low~16_combout ; +wire \z80_|execute_|ctl_alu_op_low~17_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_gp_sel~36_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_alu_op_low~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~19_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_alu_op_low~20_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~14_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|execute_|ctl_flags_alu~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|pla_decode_|Equal11~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; +wire \z80_|execute_|ctl_alu_oe~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_oe~15_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; +wire \z80_|alu_|db_low[2]~24_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_alu_oe~12_combout ; +wire \z80_|execute_|ctl_alu_oe~13_combout ; +wire \z80_|execute_|ctl_alu_oe~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; +wire \z80_|execute_|ctl_reg_out_hi~8_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|execute_|ctl_sw_2u~1_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_inc_cy~35_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_mWrite~6_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_sw_2u~0_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~7_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|execute_|ctl_inc_cy~34_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~92_combout ; +wire \z80_|pla_decode_|Equal19~1_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_inc_cy~38_combout ; +wire \z80_|execute_|ctl_inc_cy~93_combout ; +wire \z80_|execute_|ctl_inc_cy~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; +wire \z80_|execute_|ctl_reg_gp_we~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|fMRead~3_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; +wire \z80_|execute_|ctl_inc_cy~94_combout ; +wire \z80_|execute_|ctl_inc_cy~87_combout ; +wire \z80_|execute_|ctl_inc_cy~42_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|pla_decode_|Equal1~6_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~12_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~13_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|fMWrite~3_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~7_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_sw_1d~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|execute_|setM1~47_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_al_we~13_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_reg_in_hi~13_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_inc_cy~40_combout ; +wire \z80_|execute_|ctl_inc_dec~2_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_inc_cy~43_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_state_alu~13_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_state_alu~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|reg_control_|reg_sel_de2~5_combout ; +wire \z80_|reg_control_|reg_sel_de2~6_combout ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_al_we~14_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|ctl_flags_bus~13_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|pc_inc_hold~49_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|fMRead~5_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; +wire \z80_|execute_|pc_inc_hold~29_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|execute_|ctl_reg_in_hi~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; +wire \z80_|execute_|fMRead~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; +wire \z80_|execute_|fMRead~1_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|ctl_sw_4d~1_combout ; +wire \z80_|execute_|ctl_sw_4d~0_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|execute_|fMRead~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; wire \KEY[0]~input_o ; wire \reset~combout ; @@ -184,801 +872,92 @@ wire \z80_|fpga_reset~feeder_combout ; wire \z80_|fpga_reset~q ; wire \z80_|fpga_reset~clkctrl_outclk ; wire \z80_|resets_|x1~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \KEY[1]~input_o ; -wire \z80_|interrupts_|nmi_armed~feeder_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; -wire \z80_|interrupts_|nmi_armed~q ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|execute_|ctl_ir_we~4_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|pla_decode_|Equal9~0_combout ; -wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|sequencer_|M5~0_combout ; -wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; -wire \z80_|execute_|ctl_mWrite~3_combout ; -wire \z80_|execute_|ctl_mWrite~16_combout ; -wire \z80_|execute_|ixy_d~4_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|pla_decode_|Equal41~1_combout ; -wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ixy_d~8_combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|pla_decode_|Equal19~0_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|execute_|ctl_state_alu~2_combout ; -wire \z80_|execute_|ctl_inc_cy~36_combout ; -wire \z80_|execute_|ctl_inc_dec~0_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|fMWrite~0_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|pla_decode_|Equal19~1_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; -wire \z80_|execute_|ctl_state_alu~3_combout ; -wire \z80_|execute_|ctl_inc_cy~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|execute_|ctl_inc_cy~30_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|fMWrite~1_combout ; -wire \z80_|execute_|fMWrite~2_combout ; -wire \z80_|execute_|fMWrite~3_combout ; -wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|execute_|ctl_inc_cy~34_combout ; -wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|execute_|ctl_inc_cy~35_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|execute_|ctl_mRead~38_combout ; -wire \z80_|execute_|fIOWrite~1_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|execute_|fMRead~2_combout ; -wire \z80_|execute_|ctl_mWrite~2_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|execute_|ctl_inc_cy~32_combout ; -wire \z80_|execute_|ctl_inc_cy~33_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; -wire \z80_|address_pins_|abus[0]~18_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|WideOr16~5_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|WideOr16~7_combout ; -wire \ula_|zx_keyboard_|WideOr16~6_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|pc_inc_hold~19_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|ctl_inc_cy~37_combout ; -wire \z80_|execute_|ctl_inc_dec~1_combout ; -wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; wire \z80_|resets_|clrpc_int~0_combout ; wire \z80_|resets_|clrpc_int~q ; wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|execute_|ctl_inc_cy~47_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|execute_|ctl_inc_cy~38_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|fMRead~12_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~3_combout ; -wire \z80_|execute_|fMRead~13_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~25_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|nextM~11_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~8_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_reg_in_hi~13_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_we~9_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_we~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~8_combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_sel~5_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|pla_decode_|Equal11~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|ctl_iorw~12_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; -wire \z80_|execute_|ctl_bus_db_oe~2_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|pla_decode_|Equal76~0_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~7_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; -wire \z80_|execute_|setM1~56_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~40_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|pc_inc_hold~18_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ; -wire \z80_|execute_|pc_inc_hold~40_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~11_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|ctl_alu_op_low~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_flags_alu~6_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_flags_alu~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~19_combout ; -wire \z80_|execute_|ctl_flags_alu~7_combout ; -wire \z80_|execute_|ctl_flags_alu~9_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|reg_control_|reg_sel_de2~6_combout ; -wire \z80_|reg_control_|reg_sel_de2~5_combout ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~22_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; -wire \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~23_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~24_combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~26_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~25_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~39_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|fMRead~11_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~28_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~29_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~30_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_bus_db_oe~6_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|fMRead~9_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|alu_|db[7]~19_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~52_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~53_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~56_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_file_|db_hi_as[3]~13_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|db_hi_as[3]~14_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; wire \z80_|execute_|ctl_apin_mux~1_combout ; wire \z80_|execute_|ctl_al_we~6_combout ; wire \z80_|execute_|ctl_al_we~7_combout ; wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; wire \z80_|execute_|ctl_al_we~11_combout ; wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|execute_|ctl_inc_cy~78_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|reg_file_|db_hi_as[3]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~57_combout ; -wire \z80_|alu_|db[3]~13_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_sz_we~5_combout ; -wire \z80_|execute_|ctl_flags_sz_we~6_combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_flags_xy_we~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~14_combout ; -wire \z80_|execute_|ctl_flags_xy_we~15_combout ; -wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[3]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|Add0~15 ; wire \ula_|video_|Add0~16_combout ; wire \ula_|video_|vga_hc~2_combout ; wire \ula_|video_|Add0~17 ; wire \ula_|video_|Add0~18_combout ; wire \ula_|video_|vga_hc~1_combout ; -wire \ula_|video_|Equal0~0_combout ; -wire \ula_|video_|Equal0~1_combout ; -wire \ula_|video_|Equal1~0_combout ; +wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; wire \ula_|video_|Add0~1 ; wire \ula_|video_|Add0~2_combout ; +wire \ula_|video_|vga_hc[1]~feeder_combout ; wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; -wire \ula_|video_|vga_hc[2]~feeder_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; +wire \ula_|video_|vga_hc[3]~feeder_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; +wire \ula_|video_|Equal0~0_combout ; +wire \ula_|video_|Equal0~1_combout ; +wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add0~9 ; wire \ula_|video_|Add0~10_combout ; wire \ula_|video_|vga_hc~0_combout ; @@ -987,8 +966,6 @@ wire \ula_|video_|Add0~12_combout ; wire \ula_|video_|Add0~13 ; wire \ula_|video_|Add0~14_combout ; wire \ula_|video_|Add1~0_combout ; -wire \ula_|video_|vga_vc[0]~0_combout ; -wire \ula_|video_|Add1~1 ; wire \ula_|video_|Add1~3 ; wire \ula_|video_|Add1~4_combout ; wire \ula_|video_|vga_vc[2]~2_combout ; @@ -1010,22 +987,24 @@ wire \ula_|video_|vga_vc[7]~6_combout ; wire \ula_|video_|Add1~15 ; wire \ula_|video_|Add1~16_combout ; wire \ula_|video_|vga_vc[8]~7_combout ; -wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Add1~17 ; wire \ula_|video_|Add1~18_combout ; wire \ula_|video_|vga_vc[9]~9_combout ; +wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~0_combout ; wire \ula_|video_|Equal3~1_combout ; +wire \ula_|video_|vga_vc[0]~0_combout ; +wire \ula_|video_|Add1~1 ; wire \ula_|video_|Add1~2_combout ; wire \ula_|video_|vga_vc[1]~1_combout ; wire \SW[1]~input_o ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|iff1~0_combout ; wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; wire \z80_|interrupts_|DFFE_instIFF2~q ; +wire \z80_|interrupts_|iff1~0_combout ; wire \z80_|interrupts_|iff1~1_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; wire \z80_|interrupts_|iff1~q ; @@ -1033,875 +1012,787 @@ wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|interrupts_|int_armed~q ; -wire \z80_|interrupts_|DFFE_inst44~feeder_combout ; wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_cy~49_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~22_combout ; -wire \z80_|execute_|pc_inc_hold~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~23_combout ; -wire \z80_|execute_|pc_inc_hold~25_combout ; -wire \z80_|execute_|pc_inc_hold~20_combout ; -wire \z80_|execute_|pc_inc_hold~41_combout ; -wire \z80_|execute_|pc_inc_hold~21_combout ; -wire \z80_|execute_|pc_inc_hold~26_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|ctl_inc_cy~43_combout ; -wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~42_combout ; -wire \z80_|execute_|pc_inc_hold~27_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|ctl_inc_cy~40_combout ; -wire \z80_|execute_|ctl_inc_cy~41_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~42_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; -wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|pc_inc_hold~38_combout ; +wire \z80_|execute_|ctl_inc_cy~91_combout ; +wire \z80_|execute_|pc_inc_hold~45_combout ; +wire \z80_|execute_|pc_inc_hold~44_combout ; +wire \z80_|execute_|pc_inc_hold~46_combout ; +wire \z80_|execute_|pc_inc_hold~37_combout ; +wire \z80_|execute_|pc_inc_hold~50_combout ; wire \z80_|execute_|pc_inc_hold~33_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~31_combout ; +wire \z80_|execute_|pc_inc_hold~32_combout ; +wire \z80_|execute_|pc_inc_hold~34_combout ; +wire \z80_|execute_|pc_inc_hold~51_combout ; +wire \z80_|execute_|pc_inc_hold~30_combout ; +wire \z80_|execute_|pc_inc_hold~52_combout ; +wire \z80_|execute_|pc_inc_hold~35_combout ; +wire \z80_|execute_|pc_inc_hold~36_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|pc_inc_hold~43_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_inc_cy~46_combout ; +wire \z80_|execute_|pc_inc_hold~53_combout ; +wire \z80_|execute_|pc_inc_hold~39_combout ; +wire \z80_|execute_|pc_inc_hold~47_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|execute_|ctl_inc_cy~78_combout ; +wire \z80_|execute_|ctl_inc_cy~79_combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~82_combout ; +wire \z80_|execute_|ctl_inc_cy~83_combout ; +wire \z80_|execute_|ctl_inc_cy~84_combout ; +wire \z80_|execute_|pc_inc_hold~42_combout ; +wire \z80_|execute_|ctl_inc_cy~90_combout ; +wire \z80_|execute_|pc_inc_hold~41_combout ; wire \z80_|execute_|ctl_inc_cy~66_combout ; wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~31_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op_low~39_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|pla_decode_|Equal72~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~0_combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; -wire \z80_|execute_|ctl_flags_nf_we~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|execute_|ctl_alu_op_low~38_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_alu_core_R~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~35_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|alu_|db_high[3]~0_combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|alu_|db_high[3]~1_combout ; -wire \z80_|alu_|db_low[3]~2_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|alu_|db_low[3]~3_combout ; -wire \z80_|alu_|db_low[3]~4_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|db_high[2]~25_combout ; -wire \z80_|reg_file_|db_hi_as[6]~0_combout ; -wire \z80_|reg_file_|db_hi_as[6]~1_combout ; -wire \z80_|reg_file_|db_hi_as[6]~3_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~14_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~8_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~21_combout ; -wire \z80_|interrupts_|im2~feeder_combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|sw1_|db_down[6]~0_combout ; -wire \z80_|alu_|db_low[1]~10_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|alu_|db_high[1]~3_combout ; -wire \z80_|alu_|db_high[1]~2_combout ; -wire \z80_|alu_|db[7]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~74_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~75_combout ; -wire \z80_|alu_|db[5]~23_combout ; -wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~22_combout ; -wire \z80_|reg_file_|db_hi_as[4]~23_combout ; -wire \z80_|reg_file_|db_hi_as[4]~24_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~77_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~79_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~82_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~84_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_inc_cy~36_combout ; +wire \z80_|execute_|ctl_inc_cy~37_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~41_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~89_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|execute_|ctl_inc_cy~48_combout ; +wire \z80_|execute_|pc_inc_hold~40_combout ; +wire \z80_|execute_|ctl_inc_cy~61_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|ctl_inc_cy~85_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|address_latch_|Q[0]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_|alu_op1[2]~2_combout ; -wire \z80_|alu_|alu_op1[1]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|db[1]~15_combout ; -wire \z80_|alu_|db[1]~16_combout ; -wire \z80_|reg_file_|db_hi_as[0]~10_combout ; -wire \z80_|reg_file_|db_hi_as[0]~11_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; -wire \z80_|reg_file_|db_lo_as[6]~19_combout ; -wire \z80_|reg_file_|db_lo_as[6]~20_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; -wire \z80_|reg_file_|db_lo_as[5]~16_combout ; -wire \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|db_lo_as[5]~17_combout ; -wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|Q[5]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|db_lo_as[6]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|address_latch_|Q[7]~feeder_combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; +wire \z80_|address_latch_|Q[2]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; +wire \z80_|execute_|ctl_inc_cy~86_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; +wire \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|db_hi_as[1]~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|reg_file_|db_hi_as[0]~2_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~41_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~44_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~45_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~43_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~46_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~40_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~47_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~48_combout ; -wire \z80_|alu_|db[0]~17_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_low[0]~16_combout ; -wire \z80_|alu_|db_low[0]~17_combout ; -wire \z80_|alu_|db_low[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|reg_file_|db_hi_as[0]~4_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[1]~3_combout ; +wire \z80_|address_latch_|Q[9]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; +wire \z80_|reg_file_|db_hi_as[2]~7_combout ; +wire \z80_|reg_file_|db_hi_as[2]~8_combout ; +wire \z80_|reg_file_|db_hi_as[2]~9_combout ; +wire \z80_|address_latch_|Q[10]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|db_hi_as[3]~10_combout ; +wire \z80_|reg_file_|db_hi_as[3]~11_combout ; +wire \z80_|reg_file_|db_hi_as[3]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|alu_|alu_op1[3]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~20_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~21_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_flags_sz_we~4_combout ; +wire \z80_|pla_decode_|Equal71~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; +wire \z80_|pla_decode_|Equal72~2_combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|execute_|ctl_flags_nf_we~1_combout ; +wire \z80_|execute_|ctl_flags_nf_we~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; +wire \z80_|execute_|ctl_flags_sz_we~5_combout ; +wire \z80_|execute_|ctl_flags_sz_we~6_combout ; +wire \z80_|execute_|ctl_flags_nf_we~4_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|ctl_flags_xy_we~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~7_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; +wire \z80_|execute_|ctl_flags_alu~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~19_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|alu_|alu_op2[1]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~38_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~43_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|execute_|ctl_alu_core_hf~42_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~41_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~44_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~39_combout ; +wire \z80_|execute_|ctl_alu_core_hf~40_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ; +wire \z80_|alu_|alu_op2[3]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; wire \z80_|execute_|ctl_flags_hf_we~3_combout ; wire \z80_|execute_|ctl_flags_hf_we~4_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_alu_core_hf~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|execute_|ctl_alu_core_hf~16_combout ; -wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; -wire \z80_|execute_|ctl_flags_nf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~9_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|execute_|ctl_alu_core_hf~15_combout ; -wire \z80_|execute_|ctl_alu_core_hf~17_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|execute_|ctl_alu_core_hf~39_combout ; -wire \z80_|execute_|ctl_alu_core_hf~40_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; -wire \z80_|alu_|db_high[0]~8_combout ; -wire \z80_|alu_|db_high[0]~9_combout ; -wire \z80_|alu_|db_high[0]~10_combout ; -wire \z80_|alu_|db_high[0]~11_combout ; -wire \z80_|alu_|db_high[0]~12_combout ; -wire \z80_|alu_|db_high[0]~13_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|alu_|alu_op2[0]~1_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_low[0]~18_combout ; -wire \z80_|alu_|db_low[0]~20_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|address_latch_|Q[12]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[4]~16_combout ; +wire \z80_|reg_file_|db_hi_as[4]~17_combout ; +wire \z80_|reg_file_|db_hi_as[4]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; +wire \z80_|alu_|db[4]~16_combout ; +wire \z80_|alu_|db[7]~26_combout ; +wire \z80_|alu_|db[4]~17_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|db_high[0]~26_combout ; wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|alu_op1[0]~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|alu_|alu_op1[0]~1_combout ; wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|alu_op1[1]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|alu_|alu_op1[2]~2_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|alu_|db_low[2]~7_combout ; -wire \z80_|alu_|db_low[2]~8_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~63_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~61_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~64_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~58_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~65_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~66_combout ; -wire \z80_|alu_|db[2]~11_combout ; -wire \z80_|alu_|db[2]~12_combout ; -wire \z80_|alu_|db_low[2]~5_combout ; -wire \z80_|alu_|db_low[2]~6_combout ; -wire \z80_|alu_|db_low[2]~9_combout ; -wire \z80_|alu_|db_low[2]~22_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|alu_control_|db[2]~19_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; +wire \z80_|reg_file_|db_hi_as[7]~19_combout ; +wire \z80_|reg_file_|db_hi_as[7]~20_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; +wire \z80_|reg_file_|db_hi_as[5]~13_combout ; +wire \z80_|reg_file_|db_hi_as[5]~14_combout ; +wire \z80_|reg_file_|db_hi_as[5]~15_combout ; +wire \z80_|address_latch_|Q[13]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; +wire \z80_|reg_file_|db_hi_as[6]~22_combout ; +wire \z80_|reg_file_|db_hi_as[6]~23_combout ; +wire \z80_|reg_file_|db_hi_as[6]~24_combout ; +wire \z80_|address_latch_|Q[14]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|reg_file_|db_hi_as[7]~21_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; +wire \z80_|alu_|db[7]~20_combout ; +wire \z80_|alu_|db[7]~21_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~4_combout ; +wire \z80_|alu_|db_high[3]~27_combout ; +wire \z80_|alu_|db_high[3]~7_combout ; +wire \z80_|alu_|db_high[3]~8_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ; +wire \z80_|alu_|db_low[3]~9_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|alu_|db_low[3]~10_combout ; +wire \z80_|alu_|db_low[3]~7_combout ; +wire \z80_|alu_|db_low[3]~8_combout ; +wire \z80_|alu_|db_low[3]~11_combout ; +wire \z80_|alu_|db_low[3]~25_combout ; +wire \z80_|alu_|db[3]~10_combout ; +wire \z80_|alu_|db[3]~11_combout ; wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|alu_control_|db[1]~23_combout ; -wire \z80_|alu_control_|db[1]~24_combout ; -wire \z80_|alu_control_|db[1]~25_combout ; -wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|Q[1]~feeder_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; -wire \z80_|alu_control_|db[4]~30_combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \z80_|alu_|db[4]~8_combout ; -wire \z80_|alu_|db[4]~10_combout ; -wire \z80_|alu_|db_high[1]~4_combout ; -wire \z80_|alu_|db_high[1]~5_combout ; -wire \z80_|alu_|db_high[1]~6_combout ; -wire \z80_|alu_|db_high[1]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|alu_op2[1]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; -wire \z80_|alu_|db_low[1]~11_combout ; -wire \z80_|alu_|db_low[1]~12_combout ; -wire \z80_|alu_|db_low[1]~13_combout ; -wire \z80_|alu_|db_low[1]~14_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_control_|db[6]~13_combout ; -wire \z80_|alu_control_|db[6]~14_combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; +wire \z80_|execute_|ctl_flags_xy_we~13_combout ; +wire \z80_|execute_|ctl_flags_xy_we~14_combout ; +wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|alu_flags_|flags_xf~q ; +wire \z80_|alu_control_|db[3]~33_combout ; wire \z80_|execute_|ctl_reg_out_lo~3_combout ; wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; wire \z80_|execute_|ctl_reg_out_lo~4_combout ; wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; -wire \z80_|alu_control_|db[6]~15_combout ; -wire \z80_|alu_|db[6]~21_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db_high[2]~20_combout ; -wire \z80_|alu_|db_high[2]~21_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout ; -wire \z80_|alu_|db_high[2]~22_combout ; -wire \z80_|alu_|db_high[2]~23_combout ; -wire \z80_|alu_|db_high[2]~24_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|alu_op2[2]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~37_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~11_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|alu_control_|db[0]~8_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~9_combout ; -wire \z80_|alu_control_|db[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|sw1_|db_down[3]~1_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; -wire \z80_|sw1_|db_down[3]~2_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|alu_|db[3]~14_combout ; -wire \z80_|alu_|db_low[3]~0_combout ; -wire \z80_|alu_|db_low[3]~1_combout ; -wire \z80_|alu_|db_low[3]~23_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout ; -wire \z80_|alu_|alu_op2[3]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ; -wire \z80_|alu_|db_high[3]~14_combout ; -wire \z80_|alu_|db_high[3]~15_combout ; -wire \z80_|alu_|db_high[3]~16_combout ; -wire \z80_|alu_|db_high[3]~17_combout ; -wire \z80_|alu_|db_high[3]~18_combout ; -wire \z80_|alu_|db_high[3]~19_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_control_|db[7]~16_combout ; -wire \z80_|reg_file_|db_lo_ds[7]~1_combout ; +wire \z80_|reg_file_|db_lo_as[3]~10_combout ; +wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|reg_file_|db_lo_as[3]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; +wire \z80_|reg_file_|db_lo_as[4]~13_combout ; +wire \z80_|reg_file_|db_lo_as[4]~14_combout ; +wire \z80_|reg_file_|db_lo_as[4]~15_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; +wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; +wire \z80_|reg_file_|db_lo_as[5]~16_combout ; +wire \z80_|reg_file_|db_lo_as[5]~17_combout ; +wire \z80_|reg_file_|db_lo_as[5]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|db_lo_as[6]~19_combout ; +wire \z80_|reg_file_|db_lo_as[6]~20_combout ; +wire \z80_|reg_file_|db_lo_as[6]~21_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; +wire \z80_|reg_file_|db_lo_ds[7]~0_combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; wire \z80_|alu_control_|db[7]~17_combout ; +wire \z80_|alu_control_|db[7]~16_combout ; wire \z80_|alu_control_|db[7]~18_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; -wire \z80_|alu_|alu_parity_out~0_combout ; -wire \z80_|alu_|alu_parity_out~combout ; -wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; wire \z80_|execute_|ctl_flags_pf_we~5_combout ; wire \z80_|execute_|ctl_flags_pf_we~6_combout ; wire \z80_|execute_|ctl_flags_pf_we~7_combout ; wire \z80_|execute_|ctl_flags_pf_we~8_combout ; wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~11_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; wire \z80_|decode_state_|DFFE_instNonRep~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; +wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|alu_parity_out~0_combout ; +wire \z80_|alu_|alu_parity_out~combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~14_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~13_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; +wire \z80_|alu_control_|sel[1]~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; +wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; wire \z80_|alu_control_|flags_cond_true~0_combout ; wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~32_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~33_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~36_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~34_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~35_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~37_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~38_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~39_combout ; -wire \z80_|reg_file_|db_hi_as[1]~7_combout ; -wire \z80_|reg_file_|db_hi_as[1]~8_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~9_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[2]~16_combout ; -wire \z80_|reg_file_|db_hi_as[2]~17_combout ; -wire \z80_|reg_file_|db_hi_as[2]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[5]~19_combout ; -wire \z80_|reg_file_|db_hi_as[5]~20_combout ; -wire \z80_|reg_file_|db_hi_as[5]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~4_combout ; -wire \z80_|reg_file_|db_hi_as[7]~5_combout ; -wire \z80_|reg_file_|db_hi_as[7]~6_combout ; -wire \z80_|execute_|ctl_apin_mux~2_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; -wire \z80_|execute_|ctl_apin_mux2~0_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|fIORead~3_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; -wire \z80_|address_pins_|abus[15]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; -wire \z80_|address_pins_|abus[14]~16_combout ; -wire \D[1]~27_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~19_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; -wire \z80_|address_pins_|abus[10]~22_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; -wire \z80_|address_pins_|abus[11]~21_combout ; -wire \D[1]~25_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~24_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; -wire \z80_|address_pins_|abus[13]~23_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \D[1]~26_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~20_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \ula_|zx_keyboard_|keys[1][1]~20_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~21_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \D[1]~24_combout ; -wire \D[1]~28_combout ; -wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; -wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; -wire \z80_|memory_ifc_|wait_iorqinta~q ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|ctl_iorw~8_combout ; -wire \z80_|execute_|ctl_iorw~9_combout ; -wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; -wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; -wire \z80_|memory_ifc_|wait_iorq~q ; -wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; -wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|memory_ifc_|nIORQ_out~0_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|execute_|setM1~57_combout ; -wire \z80_|execute_|setM1~39_combout ; -wire \z80_|execute_|ctl_mRead~36_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|ctl_mRead~35_combout ; -wire \z80_|execute_|ctl_mRead~40_combout ; -wire \z80_|execute_|ctl_mRead~39_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|nextM~4_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; +wire \z80_|reg_file_|db_lo_ds[1]~1_combout ; +wire \z80_|alu_control_|db[1]~25_combout ; +wire \z80_|alu_control_|db[1]~24_combout ; +wire \z80_|alu_control_|db[1]~26_combout ; +wire \z80_|alu_|db[1]~12_combout ; +wire \z80_|alu_|db[1]~13_combout ; +wire \z80_|alu_|db_low[0]~21_combout ; +wire \z80_|alu_|db_low[0]~22_combout ; +wire \z80_|alu_|db_low[0]~18_combout ; +wire \z80_|alu_|db_low[0]~19_combout ; +wire \z80_|alu_|db_low[0]~20_combout ; +wire \z80_|alu_|db_low[0]~23_combout ; +wire \z80_|alu_|db[0]~18_combout ; +wire \z80_|alu_|db[0]~19_combout ; +wire \z80_|alu_|db_low[1]~15_combout ; +wire \z80_|alu_|db_low[1]~16_combout ; +wire \z80_|alu_|db_low[1]~12_combout ; +wire \z80_|alu_|db_low[1]~13_combout ; +wire \z80_|alu_|db_low[1]~14_combout ; +wire \z80_|alu_|db_low[1]~17_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|db[2]~23_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|alu_control_|db[2]~27_combout ; +wire \z80_|alu_control_|db[2]~29_combout ; +wire \z80_|alu_|db[2]~14_combout ; +wire \z80_|alu_|db[2]~15_combout ; +wire \z80_|alu_|db_low[2]~2_combout ; +wire \z80_|alu_|db_low[2]~3_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ; +wire \z80_|alu_|db_low[2]~5_combout ; +wire \z80_|alu_|db_low[2]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ; +wire \z80_|alu_|alu_op2[2]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|alu_|db_high[2]~14_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|alu_|db[6]~23_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_control_|db[6]~19_combout ; +wire \z80_|alu_control_|db[6]~20_combout ; +wire \z80_|alu_control_|db[6]~21_combout ; +wire \z80_|alu_control_|db[6]~22_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|interrupts_|im1~q ; +wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; +wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; +wire \z80_|bus_control_|db[0]~4_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; wire \z80_|execute_|ctl_mRead~37_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|setM1~55_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|nextM~3_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|execute_|ctl_mRead~35_combout ; wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; wire \z80_|memory_ifc_|wait_mrd~q ; wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|execute_|nextM~4_combout ; +wire \z80_|execute_|ctl_iorw~12_combout ; +wire \z80_|execute_|ctl_iorw~8_combout ; +wire \z80_|execute_|ctl_iorw~9_combout ; +wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; +wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; +wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; +wire \z80_|memory_ifc_|wait_iorq~q ; +wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; +wire \z80_|memory_ifc_|iorq~0_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|fIORead~3_combout ; wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; wire \z80_|memory_ifc_|nRD_out~0_combout ; wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \Equal2~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~0_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|execute_|fMWrite~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; +wire \z80_|execute_|fMWrite~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|execute_|fMWrite~8_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; +wire \z80_|execute_|fMWrite~10_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; +wire \z80_|clk_delay_|DFF_inst5~q ; +wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; +wire \z80_|memory_ifc_|wait_iorqinta~q ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; +wire \z80_|memory_ifc_|nIORQ_out~0_combout ; wire \Equal2~0_combout ; -wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; wire \ExtRamWE~0_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \z80_|execute_|ctl_apin_mux2~0_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; +wire \z80_|address_pins_|abus[13]~20_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; +wire \z80_|address_pins_|abus[14]~23_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; +wire \z80_|address_pins_|abus[15]~22_combout ; wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \z80_|address_pins_|abus[0]~16_combout ; wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|address_pins_|abus[1]~25_combout ; wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; @@ -1916,18 +1807,29 @@ wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; wire \z80_|address_pins_|abus[6]~30_combout ; wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; wire \z80_|address_pins_|abus[7]~31_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~18_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~17_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; +wire \z80_|address_pins_|abus[10]~24_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|address_pins_|abus[11]~19_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~21_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \D[6]~90_combout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \D[6]~91_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; wire \CLOCK_50~inputclkctrl_outclk ; wire \~GND~combout ; +wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; @@ -1940,9 +1842,9 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; wire \ula_|video_|vram_address[9]~1_combout ; wire \ula_|video_|Add4~13 ; @@ -1954,505 +1856,469 @@ wire \ula_|video_|vram_address[10]~2_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \Selector1~0_combout ; -wire \Selector1~1_combout ; -wire \D[1]~22_combout ; -wire \D[1]~23_combout ; -wire \D[1]~29_combout ; -wire \D[1]~31_combout ; -wire \z80_|pin_control_|bus_db_pin_re~2_combout ; -wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[1]~12_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|bus_control_|db[0]~6_combout ; -wire \z80_|bus_control_|db[1]~13_combout ; -wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; -wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~feeder_combout ; -wire \z80_|memory_ifc_|mwr_wr~q ; -wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \D[0]~30_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \D[6]~87_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \Selector6~0_combout ; -wire \D[6]~70_combout ; -wire \D[6]~71_combout ; -wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; -wire \ula_|zx_keyboard_|keys[5][4]~64_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~135_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \D[3]~55_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~95_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~96_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~97_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~99_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~q ; -wire \D[3]~54_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~136_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~109_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~137_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~110_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \ula_|zx_keyboard_|keys[5][3]~106_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \D[3]~56_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~115_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~116_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~139_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~140_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; -wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \D[3]~57_combout ; -wire \D[3]~58_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \Selector3~0_combout ; -wire \Selector3~1_combout ; -wire \D[3]~52_combout ; -wire \D[3]~53_combout ; -wire \D[3]~76_combout ; -wire \D[3]~77_combout ; -wire \ula_|always0~0_combout ; -wire \ula_|always0~1_combout ; -wire \ula_|i2s_intf_|mclk_r~0_combout ; -wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|Add0~1_cout ; -wire \ula_|i2s_intf_|Add0~2_combout ; -wire \ula_|i2s_intf_|lrdivider~2_combout ; -wire \ula_|i2s_intf_|Add0~3 ; -wire \ula_|i2s_intf_|Add0~4_combout ; -wire \ula_|i2s_intf_|lrdivider[2]~8_combout ; -wire \ula_|i2s_intf_|Add0~5 ; -wire \ula_|i2s_intf_|Add0~6_combout ; -wire \ula_|i2s_intf_|lrdivider[3]~7_combout ; -wire \ula_|i2s_intf_|Add0~7 ; -wire \ula_|i2s_intf_|Add0~8_combout ; -wire \ula_|i2s_intf_|lrdivider~1_combout ; -wire \ula_|i2s_intf_|Add0~9 ; -wire \ula_|i2s_intf_|Add0~10_combout ; -wire \ula_|i2s_intf_|lrdivider[5]~6_combout ; -wire \ula_|i2s_intf_|Add0~11 ; -wire \ula_|i2s_intf_|Add0~12_combout ; -wire \ula_|i2s_intf_|lrdivider[6]~5_combout ; -wire \ula_|i2s_intf_|Add0~13 ; -wire \ula_|i2s_intf_|Add0~14_combout ; -wire \ula_|i2s_intf_|lrdivider[7]~4_combout ; -wire \ula_|i2s_intf_|Add0~15 ; -wire \ula_|i2s_intf_|Add0~16_combout ; -wire \ula_|i2s_intf_|lrdivider~0_combout ; -wire \ula_|i2s_intf_|Add0~17 ; -wire \ula_|i2s_intf_|Add0~18_combout ; -wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; -wire \ula_|i2s_intf_|Equal0~0_combout ; -wire \ula_|i2s_intf_|Equal0~1_combout ; -wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|bitcount[0]~5_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; -wire \ula_|i2s_intf_|bclk_r~0_combout ; -wire \ula_|i2s_intf_|Add2~7_cout ; -wire \ula_|i2s_intf_|Add2~8_combout ; -wire \ula_|i2s_intf_|Add2~20_combout ; -wire \ula_|i2s_intf_|Add2~9 ; -wire \ula_|i2s_intf_|Add2~10_combout ; -wire \ula_|i2s_intf_|Add2~17_combout ; -wire \ula_|i2s_intf_|Add2~11 ; -wire \ula_|i2s_intf_|Add2~12_combout ; -wire \ula_|i2s_intf_|Add2~19_combout ; -wire \ula_|i2s_intf_|Add2~13 ; -wire \ula_|i2s_intf_|Add2~14_combout ; -wire \ula_|i2s_intf_|Add2~16_combout ; -wire \ula_|i2s_intf_|Equal1~0_combout ; -wire \ula_|i2s_intf_|shiftreg[8]~1_combout ; -wire \ula_|i2s_intf_|Add2~18_combout ; -wire \ula_|i2s_intf_|Equal1~1_combout ; -wire \ula_|i2s_intf_|bclk_r~1_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|bitcount[4]~15_combout ; -wire \ula_|i2s_intf_|bitcount[0]~6 ; -wire \ula_|i2s_intf_|bitcount[1]~7_combout ; -wire \ula_|i2s_intf_|bitcount[1]~8 ; -wire \ula_|i2s_intf_|bitcount[2]~9_combout ; -wire \ula_|i2s_intf_|bitcount[2]~10 ; -wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|bitcount[3]~12 ; -wire \ula_|i2s_intf_|bitcount[4]~13_combout ; -wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; -wire \AUD_ADCDAT~input_o ; -wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; -wire \ula_|i2s_intf_|shiftreg~18_combout ; -wire \ula_|i2s_intf_|shiftreg[8]~2_combout ; -wire \ula_|i2s_intf_|shiftreg~17_combout ; -wire \ula_|i2s_intf_|shiftreg~16_combout ; -wire \ula_|i2s_intf_|shiftreg~15_combout ; -wire \ula_|i2s_intf_|shiftreg~14_combout ; -wire \ula_|i2s_intf_|shiftreg~13_combout ; -wire \ula_|i2s_intf_|shiftreg~12_combout ; -wire \ula_|i2s_intf_|shiftreg~11_combout ; -wire \ula_|i2s_intf_|shiftreg~10_combout ; -wire \ula_|i2s_intf_|shiftreg~9_combout ; -wire \ula_|i2s_intf_|shiftreg~8_combout ; -wire \ula_|i2s_intf_|shiftreg~7_combout ; -wire \ula_|i2s_intf_|lrclk_r~0_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; -wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; -wire \ula_|ula_data~0_combout ; -wire \ula_|i2s_intf_|shiftreg~6_combout ; -wire \ula_|i2s_intf_|shiftreg~5_combout ; -wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; -wire \D[6]~72_combout ; -wire \D[6]~73_combout ; -wire \D[6]~74_combout ; -wire \D[6]~81_combout ; -wire \z80_|bus_control_|db[6]~5_combout ; -wire \z80_|bus_control_|db[6]~7_combout ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|alu_control_|db[6]~10_combout ; -wire \z80_|alu_control_|db[6]~11_combout ; -wire \z80_|alu_control_|db[2]~20_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; -wire \z80_|alu_control_|db[2]~21_combout ; -wire \z80_|alu_control_|db[2]~22_combout ; -wire \z80_|bus_control_|db[2]~10_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~59_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~133_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~132_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~34_combout ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~55_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \D[2]~33_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~48_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \D[2]~32_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~63_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~67_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \ula_|zx_keyboard_|keys[5][0]~68_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~71_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; -wire \D[2]~35_combout ; -wire \D[2]~36_combout ; -wire \D[2]~83_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \Selector0~0_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \Selector0~1_combout ; -wire \D[2]~37_combout ; -wire \D[2]~38_combout ; -wire \D[2]~39_combout ; -wire \D[2]~40_combout ; -wire \z80_|bus_control_|db[2]~11_combout ; -wire \z80_|pla_decode_|Equal3~1_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|execute_|ctl_bus_db_oe~4_combout ; -wire \z80_|execute_|ctl_bus_db_oe~5_combout ; -wire \z80_|execute_|ctl_bus_db_oe~combout ; -wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \D[0]~45_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \D[0]~44_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~134_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~93_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \D[0]~46_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~77_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~74_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~75_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~76_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~73_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \D[0]~43_combout ; -wire \D[0]~47_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \Selector2~0_combout ; -wire \Selector2~1_combout ; -wire \D[0]~41_combout ; -wire \D[0]~42_combout ; -wire \D[0]~48_combout ; -wire \D[0]~49_combout ; -wire \z80_|bus_control_|db[0]~14_combout ; -wire \z80_|bus_control_|db[0]~15_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|sw1_|db_down[5]~1_combout ; +wire \D[6]~88_combout ; +wire \D[6]~89_combout ; +wire \D[6]~111_combout ; +wire \raw_loader_in~input_o ; +wire \D[6]~86_combout ; +wire \D[6]~100_combout ; +wire \D[6]~101_combout ; +wire \z80_|pin_control_|bus_db_pin_re~2_combout ; +wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; +wire \z80_|bus_control_|db[6]~9_combout ; +wire \z80_|ir_|opcode[6]~feeder_combout ; +wire \z80_|execute_|ctl_ir_we~13_combout ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal41~1_combout ; +wire \z80_|pla_decode_|Equal41~2_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|db_high[1]~20_combout ; +wire \z80_|alu_|db[5]~24_combout ; +wire \z80_|alu_|db[5]~25_combout ; +wire \z80_|sw1_|db_down[5]~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; wire \z80_|alu_flags_|flags_yf~q ; -wire \z80_|alu_control_|db[5]~27_combout ; -wire \z80_|alu_control_|db[5]~28_combout ; -wire \z80_|alu_control_|db[5]~29_combout ; -wire \D[5]~68_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \z80_|alu_control_|db[5]~13_combout ; +wire \z80_|alu_control_|db[5]~14_combout ; +wire \z80_|alu_control_|db[5]~15_combout ; +wire \D[0]~107_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \Mux2~0_combout ; wire \Mux2~1_combout ; -wire \D[5]~88_combout ; -wire \D[5]~69_combout ; -wire \D[5]~80_combout ; -wire \z80_|bus_control_|db[5]~16_combout ; -wire \z80_|bus_control_|db[5]~17_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; -wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|fMRead~28_combout ; -wire \z80_|execute_|fMRead~30_combout ; +wire \D[5]~110_combout ; +wire \D[5]~85_combout ; +wire \D[5]~99_combout ; +wire \z80_|bus_control_|db[5]~14_combout ; +wire \z80_|bus_control_|db[5]~15_combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|fMRead~34_combout ; wire \z80_|execute_|fMRead~31_combout ; wire \z80_|execute_|fMRead~29_combout ; +wire \z80_|execute_|fMRead~30_combout ; +wire \z80_|execute_|fMRead~28_combout ; wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~37_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~35_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; +wire \z80_|execute_|fMRead~14_combout ; wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~11_combout ; +wire \z80_|execute_|fMRead~12_combout ; +wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|fMRead~15_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|pc_inc_hold~48_combout ; wire \z80_|execute_|fMRead~22_combout ; +wire \z80_|execute_|fMRead~21_combout ; wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|pc_inc_hold~39_combout ; wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|fMRead~36_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|fMRead~35_combout ; wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \Mux0~0_combout ; -wire \Mux0~1_combout ; -wire \D[7]~89_combout ; -wire \D[7]~75_combout ; -wire \D[7]~82_combout ; -wire \z80_|bus_control_|db[7]~8_combout ; -wire \z80_|bus_control_|db[7]~9_combout ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; -wire \z80_|interrupts_|im1~q ; -wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; -wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|pla_decode_|Equal21~0_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; -wire \z80_|execute_|ctl_bus_db_we~4_combout ; -wire \z80_|execute_|ctl_bus_db_we~6_combout ; -wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; -wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[4][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~128_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \D[4]~64_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~138_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \Selector1~0_combout ; +wire \Selector1~1_combout ; +wire \D[1]~103_combout ; +wire \PS2_DAT~input_o ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; +wire \ula_|zx_keyboard_|shifted~0_combout ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~23_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \D[1]~30_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \ula_|zx_keyboard_|key_row~0_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~19_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~21_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \D[1]~28_combout ; +wire \D[1]~29_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; +wire \ula_|zx_keyboard_|WideOr16~5_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|WideOr16~7_combout ; +wire \ula_|zx_keyboard_|WideOr16~6_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; +wire \D[1]~31_combout ; +wire \D[1]~32_combout ; +wire \D[1]~33_combout ; +wire \D[1]~34_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; +wire \z80_|bus_control_|db[1]~11_combout ; +wire \z80_|ir_|opcode[1]~feeder_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|execute_|ctl_flags_cf_set~0_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|alu_control_|db[0]~8_combout ; +wire \z80_|sw2_|db_up[0]~0_combout ; +wire \z80_|alu_control_|db[0]~9_combout ; +wire \z80_|alu_control_|db[0]~12_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~67_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \D[0]~49_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys~76_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~73_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~74_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; +wire \ula_|zx_keyboard_|keys[1][0]~71_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \D[0]~47_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \ula_|zx_keyboard_|keys[3][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \ula_|zx_keyboard_|key_row~1_combout ; +wire \D[0]~48_combout ; +wire \ula_|zx_keyboard_|shifted~1_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|keys[5][4]~63_combout ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~132_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \D[0]~50_combout ; +wire \D[0]~51_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~55_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \D[0]~56_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \D[0]~52_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~53_combout ; +wire \D[0]~54_combout ; +wire \D[0]~106_combout ; +wire \D[0]~57_combout ; +wire \D[0]~58_combout ; +wire \z80_|bus_control_|db[0]~16_combout ; +wire \z80_|bus_control_|db[0]~17_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|alu_control_|db[6]~10_combout ; +wire \z80_|alu_control_|db[6]~11_combout ; +wire \z80_|alu_control_|db[4]~30_combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \z80_|alu_control_|db[4]~32_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~95_combout ; wire \ula_|zx_keyboard_|keys[2][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~123_combout ; wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \D[4]~63_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~129_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \ula_|zx_keyboard_|keys[6][4]~130_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~131_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~136_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~130_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \D[4]~78_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~128_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~129_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \ula_|zx_keyboard_|keys[6][4]~127_combout ; wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \D[4]~65_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~118_combout ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \D[4]~79_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \ula_|zx_keyboard_|key_row~3_combout ; +wire \D[4]~80_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~97_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~116_combout ; wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~115_combout ; wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~62_combout ; -wire \D[4]~66_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \D[4]~77_combout ; +wire \D[4]~81_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; wire \Selector4~0_combout ; wire \Selector4~1_combout ; -wire \D[4]~60_combout ; -wire \D[4]~61_combout ; -wire \D[4]~78_combout ; -wire \D[4]~79_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ; +wire \D[4]~109_combout ; +wire \D[4]~97_combout ; +wire \D[4]~98_combout ; wire \z80_|bus_control_|db[4]~18_combout ; wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|pla_decode_|Equal21~0_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_mWrite~13_combout ; +wire \z80_|execute_|ctl_mWrite~14_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; +wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; +wire \z80_|memory_ifc_|wait_mwr~q ; +wire \z80_|memory_ifc_|mwr_wr~q ; +wire \z80_|memory_ifc_|nWR_out~0_combout ; +wire \D[5]~84_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Mux0~0_combout ; +wire \Mux0~1_combout ; +wire \D[7]~112_combout ; +wire \D[7]~94_combout ; +wire \D[7]~102_combout ; +wire \z80_|bus_control_|db[7]~5_combout ; +wire \z80_|bus_control_|db[7]~7_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|execute_|ctl_mWrite~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_bus_db_we~8_combout ; +wire \z80_|execute_|ctl_bus_db_we~2_combout ; +wire \z80_|execute_|ctl_bus_db_we~4_combout ; +wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_bus_db_we~7_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \ula_|zx_keyboard_|keys[3][3]~48_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \D[2]~35_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~131_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \D[2]~37_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \D[2]~36_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \D[2]~38_combout ; +wire \D[2]~39_combout ; +wire \D[2]~104_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \D[2]~43_combout ; +wire \D[2]~44_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \D[2]~40_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \D[2]~41_combout ; +wire \D[2]~42_combout ; +wire \D[2]~105_combout ; +wire \D[2]~45_combout ; +wire \D[2]~46_combout ; +wire \z80_|bus_control_|db[2]~12_combout ; +wire \z80_|bus_control_|db[2]~13_combout ; +wire \z80_|pla_decode_|Equal3~1_combout ; wire \z80_|pla_decode_|Equal43~0_combout ; wire \z80_|interrupts_|test1~2_combout ; wire \z80_|interrupts_|test1~3_combout ; @@ -2463,83 +2329,151 @@ wire \z80_|clk_delay_|hold_clk_iorq~combout ; wire \z80_|sequencer_|DFFE_T1_ff~q ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; -wire \z80_|sequencer_|DFFE_T3_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|setM1~53_combout ; -wire \z80_|execute_|nextM~3_combout ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; +wire \z80_|execute_|ctl_mWrite~3_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|execute_|nextM~8_combout ; wire \z80_|execute_|nextM~9_combout ; wire \z80_|execute_|nextM~10_combout ; wire \z80_|execute_|nextM~12_combout ; wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~5_combout ; +wire \z80_|execute_|nextM~6_combout ; wire \z80_|execute_|nextM~7_combout ; -wire \z80_|execute_|nextM~8_combout ; wire \z80_|execute_|nextM~13_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|nextM~5_combout ; wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; wire \z80_|sequencer_|T6~q ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~41_combout ; wire \z80_|execute_|setM1~42_combout ; wire \z80_|execute_|setM1~43_combout ; wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~16_combout ; wire \z80_|execute_|setM1~50_combout ; wire \z80_|execute_|setM1~51_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~6_combout ; +wire \z80_|execute_|setM1~7_combout ; wire \z80_|execute_|setM1~8_combout ; wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~53_combout ; +wire \z80_|execute_|setM1~23_combout ; wire \z80_|execute_|setM1~18_combout ; wire \z80_|execute_|setM1~19_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~54_combout ; wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~34_combout ; wire \z80_|execute_|setM1~52_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_inc_cy~39_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~37_combout ; -wire \z80_|execute_|pc_inc_hold~38_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; +wire \z80_|sequencer_|DFFE_T3_ff~q ; +wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|execute_|ctl_bus_db_oe~2_combout ; +wire \z80_|execute_|ctl_bus_db_oe~5_combout ; +wire \z80_|execute_|ctl_bus_db_oe~6_combout ; +wire \z80_|execute_|ctl_bus_db_oe~4_combout ; +wire \z80_|execute_|ctl_bus_db_oe~combout ; +wire \z80_|bus_control_|db[0]~6_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~q ; +wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~q ; +wire \D[3]~65_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~133_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \D[3]~66_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~134_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~135_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \D[3]~67_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~q ; +wire \ula_|zx_keyboard_|keys[6][3]~109_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~110_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~137_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~138_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \ula_|zx_keyboard_|key_row~2_combout ; +wire \D[3]~68_combout ; +wire \D[3]~69_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \D[3]~73_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \D[3]~74_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \D[3]~70_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~71_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~72_combout ; +wire \D[3]~108_combout ; +wire \D[3]~95_combout ; +wire \D[3]~96_combout ; +wire \z80_|bus_control_|db[3]~20_combout ; +wire \z80_|bus_control_|db[3]~21_combout ; +wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \z80_|execute_|ctl_apin_mux~2_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~84_combout ; -wire \D[0]~50_combout ; -wire \D[1]~85_combout ; -wire \D[1]~51_combout ; -wire \D[3]~86_combout ; -wire \D[3]~59_combout ; -wire \D[4]~87_combout ; -wire \D[4]~67_combout ; +wire \D[0]~59_combout ; +wire \D[0]~60_combout ; +wire \D[1]~61_combout ; +wire \D[1]~62_combout ; +wire \D[2]~63_combout ; +wire \D[2]~64_combout ; +wire \D[3]~75_combout ; +wire \D[3]~76_combout ; +wire \D[4]~82_combout ; +wire \D[4]~83_combout ; +wire \D[6]~92_combout ; +wire \D[6]~93_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2547,6 +2481,7 @@ wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ; wire \z80_|memory_ifc_|DFFE_mreq_ff2~q ; wire \z80_|memory_ifc_|nMREQ_out~0_combout ; wire \z80_|memory_ifc_|nMREQ_out~1_combout ; +wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|divider[0]~15_combout ; wire \ula_|i2c_loader_|divider[1]~5_combout ; @@ -2563,35 +2498,24 @@ wire \ula_|i2c_loader_|WideAnd0~combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; +wire \ula_|i2c_loader_|nbit~5_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|Mux42~0_combout ; -wire \ula_|i2c_loader_|nbit~6_combout ; -wire \ula_|i2c_loader_|nbyte~0_combout ; +wire \ula_|i2c_loader_|nbyte~4_combout ; wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; wire \I2C_SDAT~input_o ; wire \ula_|i2c_loader_|nbyte[0]~1_combout ; wire \ula_|i2c_loader_|nbyte[0]~2_combout ; wire \ula_|i2c_loader_|nbyte[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~4_combout ; +wire \ula_|i2c_loader_|state.Stop~0_combout ; +wire \ula_|i2c_loader_|state.Stop~1_combout ; +wire \ula_|i2c_loader_|state.Stop~q ; +wire \ula_|i2c_loader_|state.Idle~0_combout ; +wire \ula_|i2c_loader_|nbit~0_combout ; wire \ula_|i2c_loader_|state.Done~0_combout ; wire \ula_|i2c_loader_|state.Ack~0_combout ; wire \ula_|i2c_loader_|state.Ack~1_combout ; -wire \ula_|i2c_loader_|state.Ack~2_combout ; wire \ula_|i2c_loader_|state.Ack~q ; -wire \ula_|i2c_loader_|state~24_combout ; -wire \ula_|i2c_loader_|state~26_combout ; -wire \ula_|i2c_loader_|state~27_combout ; -wire \ula_|i2c_loader_|state.Data~0_combout ; -wire \ula_|i2c_loader_|state.Data~q ; -wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|nbit~0_combout ; -wire \ula_|i2c_loader_|state.Done~1_combout ; -wire \ula_|i2c_loader_|state.Done~2_combout ; -wire \ula_|i2c_loader_|state.Pause~2_combout ; -wire \ula_|i2c_loader_|state.Pause~0_combout ; -wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|nbyte[1]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; @@ -2601,29 +2525,43 @@ wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; wire \ula_|i2c_loader_|Equal2~0_combout ; +wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|state.Done~2_combout ; +wire \ula_|i2c_loader_|state.Pause~2_combout ; wire \ula_|i2c_loader_|state.Pause~3_combout ; wire \ula_|i2c_loader_|state.Pause~q ; wire \ula_|i2c_loader_|state~25_combout ; wire \ula_|i2c_loader_|state.Start~q ; -wire \ula_|i2c_loader_|nbyte~4_combout ; -wire \ula_|i2c_loader_|state.Stop~0_combout ; -wire \ula_|i2c_loader_|state.Stop~1_combout ; -wire \ula_|i2c_loader_|state.Stop~q ; +wire \ula_|i2c_loader_|nbyte~0_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit[0]~4_combout ; +wire \ula_|i2c_loader_|nbit~6_combout ; +wire \ula_|i2c_loader_|state.Done~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; +wire \ula_|i2c_loader_|state~24_combout ; +wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|state.Data~0_combout ; +wire \ula_|i2c_loader_|state.Data~q ; wire \ula_|i2c_loader_|scl_out~0_combout ; wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|scl_out~1_combout ; wire \ula_|i2c_loader_|scl_out~2_combout ; wire \ula_|i2c_loader_|scl_out~q ; wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; +wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|Mux35~0_combout ; +wire \ula_|i2c_loader_|shiftreg~13_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~15_combout ; wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|shiftreg~21_combout ; wire \ula_|i2c_loader_|shiftreg~22_combout ; wire \ula_|i2c_loader_|shiftreg~23_combout ; @@ -2632,12 +2570,9 @@ wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; wire \ula_|i2c_loader_|shiftreg~18_combout ; wire \ula_|i2c_loader_|shiftreg~19_combout ; wire \ula_|i2c_loader_|shiftreg~20_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; wire \ula_|i2c_loader_|shiftreg~16_combout ; wire \ula_|i2c_loader_|shiftreg~17_combout ; wire \ula_|i2c_loader_|shiftreg~26_combout ; -wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~15_combout ; wire \ula_|i2c_loader_|shiftreg~25_combout ; wire \ula_|i2c_loader_|shiftreg~12_combout ; wire \ula_|i2c_loader_|shiftreg~9_combout ; @@ -2648,31 +2583,120 @@ wire \ula_|i2c_loader_|sda_out~2_combout ; wire \ula_|i2c_loader_|sda_out~3_combout ; wire \ula_|i2c_loader_|sda_out~4_combout ; wire \ula_|i2c_loader_|sda_out~q ; +wire \ula_|i2s_intf_|mclk_r~0_combout ; +wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|mclk_r~q ; +wire \ula_|i2s_intf_|Add0~1_cout ; +wire \ula_|i2s_intf_|Add0~2_combout ; +wire \ula_|i2s_intf_|lrdivider~2_combout ; +wire \ula_|i2s_intf_|Add0~3 ; +wire \ula_|i2s_intf_|Add0~4_combout ; +wire \ula_|i2s_intf_|lrdivider[2]~8_combout ; +wire \ula_|i2s_intf_|Add0~5 ; +wire \ula_|i2s_intf_|Add0~6_combout ; +wire \ula_|i2s_intf_|lrdivider[3]~7_combout ; +wire \ula_|i2s_intf_|Add0~7 ; +wire \ula_|i2s_intf_|Add0~8_combout ; +wire \ula_|i2s_intf_|lrdivider~1_combout ; +wire \ula_|i2s_intf_|Add0~9 ; +wire \ula_|i2s_intf_|Add0~10_combout ; +wire \ula_|i2s_intf_|lrdivider[5]~6_combout ; +wire \ula_|i2s_intf_|Equal0~1_combout ; +wire \ula_|i2s_intf_|Add0~11 ; +wire \ula_|i2s_intf_|Add0~12_combout ; +wire \ula_|i2s_intf_|lrdivider[6]~5_combout ; +wire \ula_|i2s_intf_|Add0~13 ; +wire \ula_|i2s_intf_|Add0~14_combout ; +wire \ula_|i2s_intf_|lrdivider[7]~4_combout ; +wire \ula_|i2s_intf_|Add0~15 ; +wire \ula_|i2s_intf_|Add0~16_combout ; +wire \ula_|i2s_intf_|lrdivider~0_combout ; +wire \ula_|i2s_intf_|Add0~17 ; +wire \ula_|i2s_intf_|Add0~18_combout ; +wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; +wire \ula_|i2s_intf_|Equal0~0_combout ; +wire \ula_|i2s_intf_|Equal0~2_combout ; +wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; +wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; +wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|bitcount[0]~5_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|bitcount[4]~15_combout ; +wire \ula_|i2s_intf_|bitcount[0]~6 ; +wire \ula_|i2s_intf_|bitcount[1]~7_combout ; +wire \ula_|i2s_intf_|bitcount[1]~8 ; +wire \ula_|i2s_intf_|bitcount[2]~9_combout ; +wire \ula_|i2s_intf_|bitcount[2]~10 ; +wire \ula_|i2s_intf_|bitcount[3]~11_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|bitcount[3]~12 ; +wire \ula_|i2s_intf_|bitcount[4]~13_combout ; +wire \ula_|i2s_intf_|Add2~7_cout ; +wire \ula_|i2s_intf_|Add2~8_combout ; +wire \ula_|i2s_intf_|Add2~20_combout ; +wire \ula_|i2s_intf_|Add2~9 ; +wire \ula_|i2s_intf_|Add2~10_combout ; +wire \ula_|i2s_intf_|Add2~17_combout ; +wire \ula_|i2s_intf_|Add2~11 ; +wire \ula_|i2s_intf_|Add2~12_combout ; +wire \ula_|i2s_intf_|Add2~19_combout ; +wire \ula_|i2s_intf_|Add2~13 ; +wire \ula_|i2s_intf_|Add2~14_combout ; +wire \ula_|i2s_intf_|Add2~16_combout ; +wire \ula_|i2s_intf_|Equal1~0_combout ; +wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; +wire \ula_|i2s_intf_|Add2~18_combout ; +wire \ula_|i2s_intf_|Equal1~1_combout ; +wire \ula_|i2s_intf_|bclk_r~0_combout ; +wire \ula_|i2s_intf_|bclk_r~1_combout ; wire \ula_|i2s_intf_|bclk_r~q ; +wire \ula_|pcm_outl[13]~feeder_combout ; +wire \ula_|always0~2_combout ; +wire \ula_|always0~3_combout ; +wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; +wire \AUD_ADCDAT~input_o ; +wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; +wire \ula_|i2s_intf_|shiftreg~18_combout ; +wire \ula_|i2s_intf_|shiftreg[4]~2_combout ; +wire \ula_|i2s_intf_|shiftreg~17_combout ; +wire \ula_|i2s_intf_|shiftreg~16_combout ; +wire \ula_|i2s_intf_|shiftreg~15_combout ; +wire \ula_|i2s_intf_|shiftreg~14_combout ; +wire \ula_|i2s_intf_|shiftreg~13_combout ; +wire \ula_|i2s_intf_|shiftreg~12_combout ; +wire \ula_|i2s_intf_|shiftreg~11_combout ; +wire \ula_|i2s_intf_|shiftreg~10_combout ; +wire \ula_|i2s_intf_|shiftreg~9_combout ; +wire \ula_|i2s_intf_|shiftreg~8_combout ; +wire \ula_|i2s_intf_|shiftreg~7_combout ; +wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; +wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; +wire \ula_|pcm_outr~0_combout ; +wire \ula_|i2s_intf_|shiftreg~6_combout ; +wire \ula_|i2s_intf_|shiftreg~5_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|border[1]~feeder_combout ; +wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|video_|LessThan6~0_combout ; +wire \ula_|video_|LessThan2~1_combout ; +wire \ula_|video_|LessThan3~0_combout ; +wire \ula_|video_|LessThan0~0_combout ; +wire \ula_|video_|disp_enable~0_combout ; +wire \ula_|video_|disp_enable~1_combout ; +wire \ula_|video_|LessThan6~1_combout ; +wire \ula_|video_|LessThan4~0_combout ; +wire \ula_|video_|screen_en~0_combout ; +wire \ula_|video_|screen_en~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|Decoder0~1_combout ; -wire \ula_|video_|attr[1]~feeder_combout ; wire \ula_|video_|Decoder0~0_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[4]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[6]~feeder_combout ; -wire \ula_|video_|Decoder0~2_combout ; -wire \ula_|video_|bits_prefetch[4]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[5]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[7]~feeder_combout ; -wire \ula_|video_|Mux0~0_combout ; -wire \ula_|video_|Mux0~1_combout ; wire \ula_|video_|attr_prefetch[7]~feeder_combout ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; @@ -2683,8 +2707,20 @@ wire \ula_|video_|frame[3]~8_combout ; wire \ula_|video_|frame[3]~9 ; wire \ula_|video_|frame[4]~10_combout ; wire \ula_|video_|inverted~combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[6]~feeder_combout ; +wire \ula_|video_|Decoder0~2_combout ; +wire \ula_|video_|bits[6]~feeder_combout ; +wire \ula_|video_|bits_prefetch[4]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[5]~feeder_combout ; +wire \ula_|video_|bits[5]~feeder_combout ; +wire \ula_|video_|bits_prefetch[7]~feeder_combout ; +wire \ula_|video_|Mux0~0_combout ; +wire \ula_|video_|Mux0~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[2]~feeder_combout ; +wire \ula_|video_|bits[2]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[0]~feeder_combout ; wire \ula_|video_|bits_prefetch[1]~feeder_combout ; @@ -2695,17 +2731,6 @@ wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; wire \ula_|video_|cindex[1]~0_combout ; wire \ula_|video_|cindex[1]~1_combout ; -wire \ula_|video_|LessThan6~0_combout ; -wire \ula_|video_|LessThan6~1_combout ; -wire \ula_|video_|LessThan4~0_combout ; -wire \ula_|video_|screen_en~0_combout ; -wire \ula_|video_|screen_en~1_combout ; -wire \ula_|video_|LessThan2~0_combout ; -wire \ula_|video_|LessThan2~1_combout ; -wire \ula_|video_|LessThan3~0_combout ; -wire \ula_|video_|LessThan0~0_combout ; -wire \ula_|video_|disp_enable~0_combout ; -wire \ula_|video_|disp_enable~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; @@ -2715,8 +2740,9 @@ wire \ula_|video_|attr_prefetch[5]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; -wire \ula_|border[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[0]~feeder_combout ; +wire \ula_|video_|attr[0]~feeder_combout ; +wire \ula_|video_|attr_prefetch[3]~feeder_combout ; wire \ula_|video_|cindex[0]~3_combout ; wire \ula_|video_|VGA_B[0]~1_combout ; wire \ula_|video_|VGA_B[1]~2_combout ; @@ -2751,13 +2777,11 @@ wire [4:0] \ula_|video_|frame ; wire [7:0] \ula_|video_|bits_prefetch ; wire [7:0] \ula_|video_|attr_prefetch ; wire [7:0] \ula_|ps2_keyboard_|clk_filter ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; @@ -2768,9 +2792,10 @@ wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; wire [3:0] \z80_|alu_|op2_low ; wire [3:0] \z80_|alu_|op1_low ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; -wire [15:0] \z80_|address_latch_|abusz ; -wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [15:0] \z80_|address_latch_|Q ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; +wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [7:0] \z80_|data_pins_|dout ; wire [7:0] \z80_|ir_|opcode ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; @@ -2790,11 +2815,13 @@ wire [7:0] \ula_|video_|bits ; wire [7:0] \ula_|video_|attr ; wire [8:0] \ula_|ps2_keyboard_|shiftreg ; wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; @@ -2806,10 +2833,9 @@ wire [3:0] \z80_|alu_|result_lo ; wire [3:0] \z80_|alu_|op2_high ; wire [3:0] \z80_|alu_|op1_high ; wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; -wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; -wire [7:0] \z80_|data_pins_|dout ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; +wire [15:0] \z80_|address_latch_|abusz ; +wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; @@ -2821,33 +2847,33 @@ wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_b wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; @@ -2866,15 +2892,15 @@ wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_b wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; @@ -2909,60 +2935,60 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; @@ -2999,24 +3025,24 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; @@ -3245,8 +3271,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~50_combout ), - .oe(\D[0]~30_combout ), + .i(\D[0]~60_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3258,8 +3284,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~51_combout ), - .oe(\D[0]~30_combout ), + .i(\D[1]~62_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3271,8 +3297,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~39_combout ), - .oe(\D[0]~30_combout ), + .i(\D[2]~64_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3284,8 +3310,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~59_combout ), - .oe(\D[0]~30_combout ), + .i(\D[3]~76_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3297,8 +3323,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~67_combout ), - .oe(\D[0]~30_combout ), + .i(\D[4]~83_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3310,8 +3336,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~69_combout ), - .oe(\D[0]~30_combout ), + .i(\D[5]~85_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3323,8 +3349,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~74_combout ), - .oe(\D[0]~30_combout ), + .i(\D[6]~93_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3336,8 +3362,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~75_combout ), - .oe(\D[0]~30_combout ), + .i(\D[7]~94_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -3440,7 +3466,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(gnd), + .i(\raw_loader_in~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -4080,7 +4106,7 @@ defparam \ula_|clocks_|clk_cpu .is_wysiwyg = "true"; defparam \ula_|clocks_|clk_cpu .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G10 +// Location: CLKCTRL_G14 cycloneive_clkctrl \ula_|clocks_|clk_cpu~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\ula_|clocks_|clk_cpu~q }), @@ -4093,7 +4119,24 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N0 +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N12 cycloneive_lcell_comb \z80_|sequencer_|ena_M ( // Equation(s): // \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout ) @@ -4110,6 +4153,11802 @@ defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; // synopsys translate_on +// Location: IOIBUF_X0_Y16_N8 +cycloneive_io_ibuf \KEY[1]~input ( + .i(KEY[1]), + .ibar(gnd), + .o(\KEY[1]~input_o )); +// synopsys translate_off +defparam \KEY[1]~input .bus_hold = "false"; +defparam \KEY[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( +// Equation(s): +// \z80_|interrupts_|nmi_armed~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; +defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N2 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hAAFF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y15_N7 +dffeas \z80_|interrupts_|nmi_armed ( + .clk(!\KEY[1]~input_o ), + .d(\z80_|interrupts_|nmi_armed~feeder_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|nmi_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|nmi_armed .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N12 +cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( +// Equation(s): +// \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|interrupts_|nmi_armed~q ), + .cin(gnd), + .combout(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( +// Equation(s): +// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h1100; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N31 +dffeas \z80_|sequencer_|DFFE_M3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( +// Equation(s): +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hD0D0; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N2 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N3 +dffeas \z80_|sequencer_|DFFE_M4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h00CC; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( +// Equation(s): +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|decode_state_|table_xx~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal36~0_combout )))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|pla_decode_|Equal36~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal36~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hB3A0; +defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EA; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X41_Y17_N29 +dffeas \z80_|decode_state_|DFFE_instCB ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instCB~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X41_Y17_N17 +dffeas \z80_|decode_state_|DFFE_instED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) + + .dataa(\z80_|ir_|opcode [7]), + .datab(gnd), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout )) + + .dataa(gnd), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal49~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [3])) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~8_combout = (((!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h4FFF; +defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N12 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h0055; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hEF00; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( +// Equation(s): +// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal3~2_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( +// Equation(s): +// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( +// Equation(s): +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( +// Equation(s): +// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( +// Equation(s): +// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~8_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( +// Equation(s): +// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal44~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( +// Equation(s): +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( +// Equation(s): +// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|execute_|ixy_d~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(gnd), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal50~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( +// Equation(s): +// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|pla_decode_|Equal50~0_combout & ((!\z80_|pla_decode_|Equal33~2_combout )))) # (!\z80_|decode_state_|DFFE_inst4~q & (((!\z80_|pla_decode_|Equal50~0_combout & +// !\z80_|pla_decode_|Equal33~2_combout )) # (!\z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0537; +defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( +// Equation(s): +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & +// (!\z80_|execute_|ixy_d~13_combout & (\z80_|execute_|ixy_d~17_combout ))) + + .dataa(\z80_|execute_|ixy_d~12_combout ), + .datab(\z80_|execute_|ixy_d~13_combout ), + .datac(\z80_|execute_|ixy_d~17_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h30BA; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( +// Equation(s): +// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( +// Equation(s): +// \z80_|execute_|ixy_d~15_combout = ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|execute_|ixy_d~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & +// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N23 +dffeas \z80_|decode_state_|DFFE_instIY1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_iy_set~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instIY1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0500; +defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_mRead~26_combout & !\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ctl_mRead~27_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h5D00; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal12~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0500; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( +// Equation(s): +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|comb~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|comb~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~17_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~18_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal32~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|reg_control_|reg_sys_we_lo~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|pla_decode_|Equal24~1_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~3_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|reg_control_|reg_sys_we_lo~3_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h153F; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~20_combout ), + .datab(\z80_|execute_|ctl_mRead~21_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~18_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~18_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( +// Equation(s): +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|M5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N17 +dffeas \z80_|sequencer_|M5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|M5~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|M5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|M5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & +// (((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'h0777; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout +// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~29_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~7_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~14_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_state_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~14_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & +// (((!\z80_|execute_|ctl_state_alu~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'h115F; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F3F; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|pla_decode_|Equal29~0_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Equation(s): +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_state_alu~8_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~8_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'h7000; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & +// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mRead~18_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal41~0_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal46~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_flags_alu~17_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0505; +defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~6_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_alu~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~17_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_mWrite~8_combout ))) + + .dataa(\z80_|execute_|fMRead~17_combout ), + .datab(\z80_|execute_|ctl_sw_2d~4_combout ), + .datac(\z80_|execute_|fMRead~16_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_mRead~24_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~18_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~24_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|fMRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~36_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~9_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~3_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h007F; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ixy_d~6_combout & +// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~4_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal46~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & (((!\z80_|execute_|ctl_ir_we~12_combout ) # +// (!\z80_|execute_|ctl_mWrite~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0577; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datab(\z80_|execute_|ctl_sw_2d~7_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|fMRead~19_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|ctl_sw_2d~8_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), + .datab(\z80_|execute_|fMRead~19_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datad(\z80_|execute_|ctl_sw_2d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_sw_2d~9_combout ))) + + .dataa(\z80_|execute_|ctl_im_we~combout ), + .datab(\z80_|execute_|ctl_sw_1d~5_combout ), + .datac(\z80_|execute_|ctl_sw_1d~4_combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout ))) # (!\z80_|execute_|ctl_sw_1d~6_combout ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7333; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0111; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~4 ( +// Equation(s): +// \z80_|alu_|db_low[2]~4_combout = ((\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~4 .lut_mask = 16'h555D; +defparam \z80_|alu_|db_low[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_sw_4u~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # +// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~29_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) + + .dataa(\z80_|ir_|opcode [4]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00AA; +defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~2 ( +// Equation(s): +// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0011; +defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0103; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0D0; +defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~15_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0F3F; +defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_ir_we~7_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~15_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & !\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_mWrite~16_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~13 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_alu_bs_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_alu_bs_oe~13_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~13_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|pla_decode_|Equal68~2_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_flags_bus~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'hAFBF; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~10_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_flags_bus~8_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_flags_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~11_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~14_combout ), + .datab(\z80_|execute_|ctl_flags_bus~11_combout ), + .datac(\z80_|execute_|ctl_flags_bus~10_combout ), + .datad(\z80_|execute_|ctl_flags_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_state_alu~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) # +// (!\z80_|execute_|ctl_mWrite~3_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h3030; +defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|pla_decode_|Equal41~2_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1100; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[2]~14_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N17 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88C8; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~11 ( +// Equation(s): +// \z80_|execute_|fMWrite~11_combout = ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~11 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~21_combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_alu_op_low~9_combout ))) # (!\z80_|execute_|fMWrite~11_combout ) + + .dataa(\z80_|execute_|fMWrite~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~22_combout = ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h7737; +defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~16_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~36 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (\z80_|execute_|ctl_state_alu~8_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datab(\z80_|execute_|ctl_state_alu~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_mWrite~3_combout & +// (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~19_combout = ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'h77F7; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_mRead~36_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op_low~22_combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|execute_|ixy_d~5_combout & +// (\z80_|pla_decode_|Equal40~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hEAE0; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFF08; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = ((\z80_|execute_|ctl_alu_op_low~24_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~26_combout ) # (\z80_|execute_|ctl_mRead~27_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) + + .dataa(\z80_|execute_|ctl_mRead~26_combout ), + .datab(\z80_|execute_|ctl_mRead~27_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hEF0F; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = (\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (((\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = (\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hF200; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3F20; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~22_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0CEC; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h32F0; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h22EA; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~14_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~14 .lut_mask = 16'hC0C8; +defparam \z80_|execute_|ctl_alu_bs_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~14_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00EA; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & +// (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~4_combout +// & (\z80_|execute_|ctl_ir_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEAC8; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|execute_|ctl_alu_bs_oe~10_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (!\z80_|execute_|ctl_alu_bs_oe~11_combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h00CF; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~32_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_alu_shift_oe~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF51; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~7_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # +// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h3F20; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~12_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~26_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|pla_decode_|Equal48~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h1300; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0C00; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & +// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal11~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_alu~9_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~9_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~10_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_ir_we~14_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout ) # +// (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'h0377; +defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~25_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~13_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'h3331; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h5557; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h7000; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|ctl_state_alu~7_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~3_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & +// (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~3_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'h8C88; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~2_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(gnd), + .datac(\z80_|alu_|db_high[3]~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hFAFA; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~24 ( +// Equation(s): +// \z80_|alu_|db_low[2]~24_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~3_combout & (\z80_|alu_|db_low[2]~6_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~3_combout & +// \z80_|alu_|db_low[2]~6_combout )) # (!\z80_|alu_|db_high[3]~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[2]~3_combout ), + .datac(\z80_|alu_|db_low[2]~6_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~24 .lut_mask = 16'hC0D5; +defparam \z80_|alu_|db_low[2]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h0AAA; +defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|reg_control_|reg_sys_we_lo~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~43_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & \z80_|execute_|ctl_bus_inc_oe~25_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|execute_|ctl_alu_oe~8_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~8_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mWrite~16_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & +// (((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (((!\z80_|execute_|ctl_mRead~27_combout & !\z80_|execute_|ctl_mRead~26_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~27_combout ), + .datac(\z80_|execute_|ctl_mRead~26_combout ), + .datad(\z80_|execute_|ctl_alu_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|execute_|ctl_alu_oe~11_combout ) # (((!\z80_|execute_|ctl_alu_oe~7_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|execute_|ctl_alu_oe~5_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_alu_oe~12_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~12_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_oe~13_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hF5F5; +defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & +// (((!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mRead~26_combout ))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|nextM~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'h8C00; +defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( +// Equation(s): +// \z80_|execute_|setM1~54_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'hABFF; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~7_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_alu_oe~3_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout )) # +// (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_alu_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_sw_2u~4_combout )) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~1_combout ), + .datad(\z80_|execute_|ctl_sw_2u~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~36_combout & (\z80_|execute_|comb~0_combout $ ((!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_reg_gp_sel~36_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & +// (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~35_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_inc_cy~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(\z80_|execute_|ctl_sw_2u~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h7878; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & +// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (!\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h5AAA; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h0444; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~14_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~10_combout ), + .datab(\z80_|execute_|ctl_sw_2d~14_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEAA; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~11_combout ), + .datac(\z80_|execute_|ctl_sw_2d~12_combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_alu_oe~2_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|pla_decode_|Equal38~2_combout & ((!\z80_|pla_decode_|Equal37~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|pla_decode_|Equal38~2_combout +// & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~75_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal29~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~48_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|execute_|ctl_bus_inc_oe~48_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & +// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~92_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~38_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal3~1_combout )) # (!\z80_|pla_decode_|Equal19~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal19~1_combout ), + .datac(\z80_|execute_|ctl_sw_4u~0_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~93_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~93_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~93_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~24_combout = (\z80_|execute_|ctl_inc_cy~92_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~39_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~92_combout ), + .datac(\z80_|execute_|ctl_inc_cy~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~1_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (\z80_|execute_|ctl_bus_inc_oe~46_combout & (\z80_|execute_|ctl_inc_cy~53_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~53_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~44_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_sw_4u~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .datad(\z80_|execute_|ctl_sw_4u~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( +// Equation(s): +// \z80_|execute_|fMRead~3_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ctl_state_alu~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # +// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~15_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_state_alu~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_sw_4u~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~94_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~94_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~87_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~94_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ctl_inc_cy~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (\z80_|execute_|fMRead~3_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) + + .dataa(\z80_|execute_|fMRead~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout ))) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~5_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~6_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal1~5_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~6_combout & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal1~6_combout ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N23 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N27 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal2~1_combout ), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hC888; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~12_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal50~0_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( +// Equation(s): +// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFAF; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( +// Equation(s): +// \z80_|execute_|fMRead~2_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_flags_bus~5_combout )) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~14_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h1010; +defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|fMWrite~3_combout & (\z80_|execute_|fMRead~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|fMWrite~3_combout ), + .datac(\z80_|execute_|fMRead~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h00C0; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h50F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hC5CD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout & ((\z80_|execute_|ctl_ir_we~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hCAC0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [4]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~47_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~8_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~47_combout & \z80_|execute_|nextM~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~21_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~5_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_sw_1d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & +// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hAB00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~20_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|pla_decode_|Equal49~0_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .lut_mask = 16'h0101; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~22_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'h0032; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout & \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~36_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00CC; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h20AA; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0505; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|pla_decode_|Equal68~2_combout & (!\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_flags_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~48_combout )))) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|ctl_flags_oe~1_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0070; +defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~40_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (\z80_|execute_|ctl_inc_cy~43_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_inc_cy~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal29~0_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & +// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0357; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & +// !\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h111F; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|fMRead~7_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h10F0; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .datac(\z80_|execute_|fMRead~6_combout ), + .datad(\z80_|execute_|fMRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|execute_|ctl_state_alu~8_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~8_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'h3331; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) # +// (!\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|pla_decode_|Equal52~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (\z80_|execute_|ctl_state_alu~14_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|execute_|ctl_state_alu~14_combout & (\z80_|pla_decode_|Equal52~1_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'hF3A2; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~9_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hFD00; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~4_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h373F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~9_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00FD; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal64~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hEEFF; +defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .datac(\z80_|execute_|ctl_alu_oe~7_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_state_alu~14_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|pla_decode_|Equal52~1_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~15 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|ctl_state_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (\z80_|execute_|ctl_state_alu~15_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )) + + .dataa(\z80_|execute_|ctl_state_alu~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ) # (((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout & \z80_|ir_|opcode [5])) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & +// ((\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hFF70; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hF7F7; +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h22A2; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; +defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h0F0B; +defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N15 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) + + .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hAC00; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_state_alu~15_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_state_alu~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h1100; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout & ((!\z80_|execute_|ctl_iorw~10_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout +// )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|pla_decode_|Equal25~0_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout & !\z80_|execute_|ctl_sw_1d~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), + .datad(\z80_|execute_|ctl_sw_1d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_reg_gp_we~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~5_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .datab(\z80_|execute_|ctl_sw_4u~3_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~7_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; +defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_flags_oe~1_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h1033; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ctl_al_we~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFBF0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h40CC; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (((\z80_|execute_|ctl_ir_we~7_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_iorw~11_combout ) # ((\z80_|execute_|ctl_state_alu~14_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~14_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~25_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & +// (((\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )) # (!\z80_|execute_|setM1~48_combout ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hCD05; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~9_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout )) # +// (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h1357; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h1155; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~40_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h1101; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout +// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_gp_we~5_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_mRead~22_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00B0; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) + + .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N21 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (!\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_control_|bank_af~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h1000; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_control_|bank_af~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout ) # +// (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'h035F; +defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hF8F8; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_bus~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h0777; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~7_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~24_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), + .datab(\z80_|execute_|fMRead~24_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3777; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|fMRead~3_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7757; +defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ixy_d~16_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ixy_d~16_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h557F; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & +// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|execute_|ctl_mRead~17_combout )))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h0222; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sel_pc~10_combout & (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datab(\z80_|execute_|ctl_inc_cy~94_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ctl_inc_cy~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & +// !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|ir_|opcode [5]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h5455; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~49 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~49_combout = (!\z80_|pla_decode_|Equal35~0_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~49 .lut_mask = 16'h00FD; +defparam \z80_|execute_|pc_inc_hold~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) + + .dataa(\z80_|execute_|pc_inc_hold~49_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0A00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|pla_decode_|Equal33~2_combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0515; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'h0003; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( +// Equation(s): +// \z80_|execute_|setM1~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_mRead~9_combout & (\z80_|execute_|pc_inc_hold~28_combout & \z80_|execute_|setM1~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|setM1~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~36 .lut_mask = 16'h2000; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( +// Equation(s): +// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|setM1~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0100; +defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA222; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hC8C8; +defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(gnd), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEE00; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~49_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|pc_inc_hold~49_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hF0B0; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~3_combout = (((\z80_|execute_|ctl_reg_sys_we~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout )) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|execute_|ctl_reg_sys_we~3_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEFFF; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF5D; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~34_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~34_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'h8CCC; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal3~1_combout ) # (!\z80_|pla_decode_|Equal19~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal19~1_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h5777; +defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; +defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h80C0; +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|execute_|ctl_mRead~36_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_al_we~13_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (\z80_|execute_|setM1~52_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datac(\z80_|execute_|setM1~52_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ctl_mRead~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h2022; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~0 ( +// Equation(s): +// \z80_|execute_|fMRead~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~0 .lut_mask = 16'h5D5D; +defparam \z80_|execute_|fMRead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal52~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0030; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h050F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h0FAF; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_reg_sys_hilo~20_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # +// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datac(\z80_|execute_|ctl_inc_dec~4_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hD0DD; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_ir_we~14_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout +// )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00C4; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~49_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~49_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h08CC; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h4455; +defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~0_combout ) # ((!\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|pc_inc_hold~28_combout )))) + + .dataa(\z80_|execute_|fMRead~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00BA; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_al_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4404; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_state_alu~14_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~49_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h0222; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~45_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~1 ( +// Equation(s): +// \z80_|execute_|fMRead~1_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~1 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMRead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMRead~1_combout ))) + + .dataa(\z80_|execute_|fMRead~1_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~46_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~45_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~39_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout ) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_inc_cy~76_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # +// (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~2_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~53_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), + .datab(\z80_|execute_|ctl_inc_cy~77_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & +// (((!\z80_|execute_|ctl_alu_oe~2_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'hA0F3; +defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_sel_wz~10_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & +// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~6_combout ), + .datad(\z80_|execute_|fMRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_reg_sel_wz~11_combout & (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~4_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .datab(\z80_|execute_|ctl_sw_4d~3_combout ), + .datac(\z80_|execute_|ctl_sw_4d~4_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~19_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~19_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~45_combout & !\z80_|execute_|ctl_mWrite~6_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_al_we~13_combout ), + .datac(\z80_|execute_|setM1~45_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h00C0; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~1_combout = ((!\z80_|decode_state_|use_ixiy~combout & ((\z80_|pla_decode_|Equal50~0_combout ) # (\z80_|pla_decode_|Equal49~0_combout )))) # (!\z80_|execute_|setM1~46_combout ) + + .dataa(\z80_|pla_decode_|Equal50~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|setM1~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'h32FF; +defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_al_we~14_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = ((\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout & \z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~5_combout ), + .datab(\z80_|execute_|ctl_sw_4d~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_sw_4d~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( +// Equation(s): +// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; +defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|fMRead~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h5DFF; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & (((\z80_|decode_state_|table_xx~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h00DF; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5010; +defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|setM1~36_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .datad(\z80_|execute_|fMRead~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hF0F7; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((!\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h4FFF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (\z80_|execute_|ctl_reg_sel_pc~18_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0800; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|execute_|ctl_sw_4d~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hF030; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N26 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N27 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N9 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N29 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + // Location: IOIBUF_X53_Y14_N1 cycloneive_io_ibuf \KEY[0]~input ( .i(KEY[0]), @@ -4120,7 +15959,7 @@ defparam \KEY[0]~input .bus_hold = "false"; defparam \KEY[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N6 +// Location: LCCOMB_X52_Y14_N4 cycloneive_lcell_comb reset( // Equation(s): // \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) @@ -4137,7 +15976,7 @@ defparam reset.lut_mask = 16'h0FFF; defparam reset.sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N22 +// Location: LCCOMB_X35_Y13_N26 cycloneive_lcell_comb \z80_|resets_|x1~0 ( // Equation(s): // \z80_|resets_|x1~0_combout = !\reset~combout @@ -4203,7 +16042,7 @@ defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X52_Y17_N23 +// Location: FF_X35_Y13_N27 dffeas \z80_|resets_|x1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|x1~0_combout ), @@ -4222,4021 +16061,25 @@ defparam \z80_|resets_|x1 .is_wysiwyg = "true"; defparam \z80_|resets_|x1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N8 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|x3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hFF44; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y17_N9 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G7 -cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y16_N8 -cycloneive_io_ibuf \KEY[1]~input ( - .i(KEY[1]), - .ibar(gnd), - .o(\KEY[1]~input_o )); -// synopsys translate_off -defparam \KEY[1]~input .bus_hold = "false"; -defparam \KEY[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N12 -cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( -// Equation(s): -// \z80_|interrupts_|nmi_armed~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; -defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N14 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y15_N13 -dffeas \z80_|interrupts_|nmi_armed ( - .clk(!\KEY[1]~input_o ), - .d(\z80_|interrupts_|nmi_armed~feeder_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|nmi_armed~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|nmi_armed .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N26 -cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( -// Equation(s): -// \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|interrupts_|nmi_armed~q ), - .cin(gnd), - .combout(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N24 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h5500; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N20 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N21 -dffeas \z80_|sequencer_|DFFE_M3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N6 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N7 -dffeas \z80_|sequencer_|DFFE_M4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h0303; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0030; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N28 -cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( -// Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|M5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N29 -dffeas \z80_|sequencer_|M5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|M5~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|M5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|M5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~12_combout & -// ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|decode_state_|DFFE_instCB~q & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal46~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [6] & \z80_|ir_|opcode [7]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hC0C0; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0303; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (((!\z80_|execute_|ixy_d~7_combout )) # -// (!\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_alu_core_S~10_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~49_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout )) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|ir_|opcode [7] & (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [6] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ixy_d~4_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ctl_mWrite~16_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_bus_inc_oe~49_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N10 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N11 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|pla_decode_|Equal41~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal33~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC080; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~13_combout & (!\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ixy_d~12_combout ))) # (!\z80_|execute_|ixy_d~13_combout & ((\z80_|execute_|ixy_d~17_combout ) # ((!\z80_|execute_|ixy_d~4_combout -// & \z80_|execute_|ixy_d~12_combout )))) - - .dataa(\z80_|execute_|ixy_d~13_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ixy_d~12_combout ), - .datad(\z80_|execute_|ixy_d~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h7530; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (!\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'h0300; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hC8CC; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h0A00; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|execute_|ixy_d~11_combout & (\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|execute_|ixy_d~14_combout ), - .datab(\z80_|execute_|ixy_d~11_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'hD555; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N4 -cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|ir_|opcode [5] & -// \z80_|pla_decode_|Equal3~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h5530; -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N5 -dffeas \z80_|decode_state_|DFFE_inst4 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_inst4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N20 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( -// Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) - - .dataa(gnd), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFCC; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~9_combout & !\z80_|execute_|ctl_mWrite~4_combout )) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h0011; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hF000; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~36_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~0 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~0_combout = (\z80_|execute_|ctl_inc_cy~36_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_inc_cy~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~0 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_inc_dec~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ctl_inc_dec~0_combout & ((\z80_|execute_|fMWrite~5_combout ) # ((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|fMWrite~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~0_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hFE00; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~12_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout & -// (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~12_combout )) # (!\z80_|execute_|ctl_sw_4u~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|ctl_mRead~12_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hC000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'h007F; -defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( -// Equation(s): -// \z80_|execute_|fIOWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'h5755; -defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( -// Equation(s): -// \z80_|execute_|fMWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h1F1F; -defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal46~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hFF2F; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N8 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|fIOWrite~5_combout & (((\z80_|execute_|fMWrite~0_combout ) # (\z80_|execute_|fMWrite~6_combout )))) # (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|ctl_mWrite~6_combout & -// ((\z80_|execute_|fMWrite~0_combout ) # (\z80_|execute_|fMWrite~6_combout )))) - - .dataa(\z80_|execute_|fIOWrite~5_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|fMWrite~0_combout ), - .datad(\z80_|execute_|fMWrite~6_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'hBBB0; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = ((!\z80_|ir_|opcode [7]) # (!\z80_|execute_|ctl_ir_we~5_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|ir_|opcode [7]), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h3FFF; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal33~1_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N16 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|fMRead~3_combout & ((!\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~8_combout ) # -// (!\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h03AF; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~7_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~1_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal19~1_combout ) # (!\z80_|pla_decode_|Equal3~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h1F3F; -defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N18 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (!\z80_|execute_|fMWrite~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) - - .dataa(\z80_|execute_|fMWrite~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h4000; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (!\z80_|execute_|fMWrite~8_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & \z80_|pin_control_|bus_db_pin_oe~11_combout ))) - - .dataa(\z80_|execute_|fMWrite~8_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h4000; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N12 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h135F; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'hAA2A; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h2A00; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~3_combout = (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~31 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~31_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~31 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|execute_|ctl_inc_cy~31_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|execute_|ctl_inc_cy~31_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h8AAA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~30 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~30_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & -// (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_inc_cy~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_inc_cy~30_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( -// Equation(s): -// \z80_|execute_|fMWrite~1_combout = (!\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = (!\z80_|execute_|fMWrite~1_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|fMWrite~0_combout )))) - - .dataa(\z80_|execute_|fMWrite~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|fMWrite~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h5545; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h3F33; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h3332; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~34_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal19~1_combout )) # (!\z80_|pla_decode_|Equal3~1_combout ) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (((!\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_inc_cy~86_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_inc_cy~85_combout & (\z80_|execute_|ctl_inc_cy~34_combout & \z80_|execute_|ctl_inc_cy~35_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|execute_|ctl_inc_cy~34_combout ), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( -// Equation(s): -// \z80_|execute_|fIOWrite~3_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'hB0B0; -defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal21~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~38 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~38_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~38 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'h7575; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( -// Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|fIOWrite~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|execute_|fIOWrite~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h5F0F; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = (\z80_|execute_|ctl_iorw~10_combout & (((\z80_|execute_|ctl_mWrite~2_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|fMRead~2_combout ))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'hFD00; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( -// Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~0_combout ) # ((\z80_|execute_|fIOWrite~3_combout & \z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|fIOWrite~3_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|fIOWrite~2_combout ), - .datad(\z80_|execute_|fIOWrite~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (!\z80_|execute_|fMWrite~2_combout & (!\z80_|execute_|fMWrite~4_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & !\z80_|execute_|fIOWrite~4_combout ))) - - .dataa(\z80_|execute_|fMWrite~2_combout ), - .datab(\z80_|execute_|fMWrite~4_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h0010; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~32 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~32_combout = ((!\z80_|execute_|ixy_d~4_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~32 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_inc_cy~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~33 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~33_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~32_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_sw_2u~0_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~33 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_inc_cy~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~13_combout & (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~3_combout & \z80_|execute_|ctl_inc_cy~33_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datab(\z80_|execute_|ctl_apin_mux~0_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .datad(\z80_|execute_|ctl_inc_cy~33_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFFAA; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~15_combout = (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|execute_|fIOWrite~4_combout ) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout & \z80_|pin_control_|bus_db_pin_oe~2_combout )))) # (!\z80_|sequencer_|DFFE_T4_ff~q & -// (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|pin_control_|bus_db_pin_oe~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'hBA30; -defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G5 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [2] & !\ula_|ps2_keyboard_|bit_count [1])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0507; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: FF_X25_Y23_N21 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_CLK~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y23_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|clk_filter [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N25 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N7 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [5]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [6]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [4]), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [1] & (!\ula_|ps2_keyboard_|clk_filter [2] & (\ula_|ps2_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|clk_filter [3]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [1]), - .datab(\ula_|ps2_keyboard_|clk_filter [2]), - .datac(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0010; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h00FF; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFA50; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N27 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) - - .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0A00; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N29 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y15_N3 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [0]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1450; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N5 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & -// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N7 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N13 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [2]) # (\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hAAA0; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|always1~0_combout ), - .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h3010; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N27 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N21 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N19 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N15 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N23 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N31 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y15_N3 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~0_combout $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hA55A; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & \ula_|ps2_keyboard_|WideXor0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|clk_edge~q ), - .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N9 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|Equal0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF500; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N15 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~45_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0010; -defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hF830; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [1]) # (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; -defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h1004; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & ((!\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hC0E2; -defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|WideOr16~5_combout & (\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~5_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|WideOr16~7_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF088; -defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N7 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h00C0; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hAA88; -defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|pc_inc_hold~19_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|pc_inc_hold~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hEA00; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~9_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~9_combout )) # -// (!\z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h131F; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & (!\z80_|execute_|ctl_reg_sys_we~0_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~34_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4040; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~13_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~1 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~1_combout = (\z80_|execute_|ctl_inc_cy~37_combout & (((!\z80_|pla_decode_|Equal19~1_combout ) # (!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_inc_cy~37_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~1 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_inc_dec~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_dec~1_combout & (\z80_|execute_|ctl_inc_dec~0_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3F0F; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|fIOWrite~5_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|fIOWrite~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~38_combout ))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|execute_|ctl_mWrite~3_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h1F5F; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_inc_dec~4_combout ) # (((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_inc_dec~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .datad(\z80_|execute_|ctl_inc_dec~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'hCEFF; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (((\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )) # (!\z80_|execute_|ctl_inc_dec~7_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|execute_|ctl_inc_dec~2_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N28 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h00FF; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N29 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N22 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N23 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X51_Y12_N27 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N0 +// Location: LCCOMB_X29_Y17_N18 cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( // Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|resets_|clrpc_int~q & ((!\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|resets_|clrpc_int~q & -// (!\z80_|resets_|x1~q & \z80_|sequencer_|DFFE_T2_ff~q )))) +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # +// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|resets_|x1~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), .datac(\z80_|resets_|clrpc_int~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|resets_|x1~q ), .cin(gnd), .combout(\z80_|resets_|clrpc_int~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hA1F0; +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X51_Y12_N1 +// Location: FF_X29_Y17_N19 dffeas \z80_|resets_|clrpc_int ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|clrpc_int~0_combout ), @@ -8255,13 +16098,13 @@ defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; defparam \z80_|resets_|clrpc_int .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y12_N26 +// Location: LCCOMB_X29_Y17_N28 cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( // Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), .datac(\z80_|resets_|DFFE_intr_ff3~q ), .datad(\z80_|resets_|clrpc_int~q ), .cin(gnd), @@ -8272,9478 +16115,181 @@ defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .lut_mask = 16'h1300; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|pla_decode_|Equal38~2_combout & (!\z80_|execute_|ixy_d~4_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~4_combout & -// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_inc_cy~76_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ixy_d~4_combout ))) # (!\z80_|execute_|ctl_mRead~18_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & -// !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0357; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~50_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hF000; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|ir_|opcode [3]))) - - .dataa(\z80_|execute_|comb~1_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .datab(\z80_|pla_decode_|Equal4~0_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (\z80_|execute_|ctl_inc_cy~47_combout & (\z80_|execute_|ctl_bus_inc_oe~48_combout & \z80_|execute_|ctl_bus_inc_oe~26_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~77_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3])) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|pla_decode_|Equal56~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0101; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~4_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_sw_4u~2_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_sw_4u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (((\z80_|ir_|opcode [5]) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0F07; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~38_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'hAFBF; -defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout = (\z80_|execute_|ctl_inc_cy~82_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~87_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~82_combout ), - .datab(\z80_|execute_|ctl_inc_cy~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~87_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout = (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout -// )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'h040C; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0003; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hC0C0; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~34_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~34 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout & \z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal1~5_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal1~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'hFDDD; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (((\z80_|execute_|ctl_sw_4u~4_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~16_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .datac(\z80_|execute_|ctl_sw_4u~4_combout ), - .datad(\z80_|execute_|ctl_apin_mux~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~19_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( -// Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal29~0_combout & (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|pla_decode_|Equal29~0_combout & -// !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~3_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~13_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~3 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( -// Equation(s): -// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|execute_|ctl_mRead~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( -// Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|fMRead~13_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'h3070; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~25_combout = (\z80_|execute_|fMRead~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~3_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|fMRead~14_combout ))) - - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datad(\z80_|execute_|fMRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_mRead~13_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( -// Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h01FF; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~25_combout )) - - .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hBBFF; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N22 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h0303; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5515; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal12~0_combout ) - - .dataa(\z80_|pla_decode_|Equal12~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h2020; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~16_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0011; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_sw_1d~8_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|decode_state_|DFFE_instCB~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~3_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFBB; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|ir_|opcode [1])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|execute_|ctl_flags_oe~0_combout & \z80_|execute_|ctl_al_we~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_flags_oe~0_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hAFAF; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & !\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~8_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & (!\z80_|pla_decode_|Equal68~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|pla_decode_|Equal68~2_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal46~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|pla_decode_|Equal20~0_combout & !\z80_|execute_|ctl_ir_we~8_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h000F; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_hf_cpl~8_combout & (\z80_|execute_|setM1~47_combout & (\z80_|execute_|nextM~2_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datab(\z80_|execute_|setM1~47_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|setM1~48_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~1_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h004C; -defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_in_hi~8_combout & (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_mRead~19_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout -// & (((!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_mRead~19_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~18_combout & -// (((!\z80_|execute_|ctl_mRead~19_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~2_combout = (\z80_|execute_|ctl_mRead~27_combout & (\z80_|execute_|setM1~30_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|setM1~30_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~2 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & ((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|pla_decode_|Equal21~1_combout -// )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0007; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h035F; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h3233; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & \z80_|execute_|ctl_state_alu~9_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout -// & (\z80_|execute_|ctl_state_alu~5_combout & (\z80_|execute_|ctl_state_alu~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|pla_decode_|Equal52~1_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hF5C4; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal3~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout = ((!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .lut_mask = 16'h337F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h5551; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal64~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hFAFF; -defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal3~1_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_alu_oe~9_combout & (((!\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_mRead~28_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mRead~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & \z80_|execute_|ctl_alu_oe~10_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|execute_|ctl_alu_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_mRead~20_combout ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout & \z80_|execute_|ctl_reg_gp_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_we~5_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~2_combout & \z80_|execute_|ctl_reg_gp_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~8_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~9_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|execute_|setM1~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .lut_mask = 16'h8AFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_alu_op_low~19_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'h3233; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hCC04; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~51_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~51 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ctl_mRead~7_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~4_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .lut_mask = 16'h4C44; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h6A6A; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .lut_mask = 16'hFAFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h3FC0; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~10_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_sw_2u~0_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~50_combout = (\z80_|execute_|ctl_sw_2u~3_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|sequencer_|M5~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_sw_2u~3_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~50 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~5_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_gp_sel~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_2u~5_combout ) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ) # (((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .lut_mask = 16'hBFAF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout ) # -// (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h0757; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|pla_decode_|Equal4~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h030F; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|pla_decode_|Equal2~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|setM1~41_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h0023; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~25_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_state_alu~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h000C; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (!\z80_|execute_|ctl_mRead~15_combout & (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_ir_we~12_combout & \z80_|execute_|fMRead~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|fMWrite~1_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (((\z80_|ir_|opcode [7]) # (!\z80_|decode_state_|DFFE_instED~q )) # (!\z80_|ir_|opcode [6])) # (!\z80_|pla_decode_|Equal1~4_combout ) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_mRead~21_combout & (\z80_|execute_|ctl_iorw~12_combout & (!\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ctl_al_we~13_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~21_combout ), - .datab(\z80_|execute_|ctl_iorw~12_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h0800; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h3BBB; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal44~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~38_combout & !\z80_|execute_|ctl_iorw~11_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (\z80_|execute_|ctl_alu_shift_oe~26_combout & ((!\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal32~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|execute_|ixy_d~10_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_flags_bus~6_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_flags_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal76~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal76~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4])) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal76~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = ((!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|pla_decode_|Equal76~0_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|pla_decode_|Equal76~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|execute_|ctl_alu_op_low~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_flags_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~7_combout & (\z80_|execute_|ctl_flags_bus~8_combout & (\z80_|execute_|ctl_flags_bus~14_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), - .datab(\z80_|execute_|ctl_flags_bus~8_combout ), - .datac(\z80_|execute_|ctl_flags_bus~14_combout ), - .datad(\z80_|execute_|ctl_flags_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout & \z80_|execute_|ctl_flags_bus~10_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_flags_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h1115; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h0111; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~7_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~22_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|execute_|ctl_mRead~22_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~7 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & \z80_|execute_|ctl_reg_gp_sel[0]~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datab(\z80_|execute_|nextM~11_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal21~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # (\z80_|sequencer_|M5~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h0302; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~34_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~34 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((!\z80_|pla_decode_|Equal12~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hB0F5; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & (\z80_|execute_|ctl_ir_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~6_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hF808; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~2_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~34_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h80F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # (\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ))) # -// (!\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal2~1_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal4~0_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'hA8A0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'h0F0E; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # ((\z80_|execute_|ctl_mRead~38_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~56 ( -// Equation(s): -// \z80_|execute_|setM1~56_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~56 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout = (\z80_|execute_|setM1~56_combout & (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|setM1~56_combout ), - .datab(\z80_|execute_|ctl_sw_2u~1_combout ), - .datac(\z80_|execute_|ctl_sw_2u~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|ir_|opcode [2] & !\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~26_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~5_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~26 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~7_combout & (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout & \z80_|execute_|ctl_reg_gp_sel[0]~26_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~25_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_mRead~38_combout ) # ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'h3377; -defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_ir_we~12_combout & \z80_|execute_|fMRead~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|fMWrite~1_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # (!\z80_|execute_|ctl_mRead~29_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_mRead~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hB3F3; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~29 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~24_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~24 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_reg_sys_hilo~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ctl_reg_sys_hilo~24_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h22A2; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~31_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & -// ((\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~31 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~31_combout ) # ((\z80_|ir_|opcode [1] & !\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~31_combout ), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'hAAEE; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~28_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal1~5_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N18 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|pla_decode_|Equal1~6_combout & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|pla_decode_|Equal1~6_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hF078; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N19 -dffeas \z80_|reg_control_|bank_exx ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0200; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0200; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFFEE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N0 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((\z80_|pla_decode_|Equal32~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal21~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N1 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|reg_control_|bank_af~q & (!\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0200; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_control_|bank_af~q & (!\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h0800; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h4400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|pla_decode_|Equal19~0_combout )) # -// (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h07FF; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal29~0_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal38~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~11_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_sel_wz~6_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & \z80_|execute_|ctl_reg_in_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|execute_|ctl_mRead~11_combout & -// ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h45CF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # ((\z80_|execute_|ctl_mRead~19_combout ) # (\z80_|pla_decode_|Equal34~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_mRead~19_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~4_combout ) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal25~0_combout ), - .datac(\z80_|pla_decode_|Equal12~1_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h55F7; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ixy_d~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ixy_d~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|execute_|ixy_d~4_combout & -// (((!\z80_|execute_|ixy_d~16_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (!\z80_|execute_|ctl_reg_sel_pc~9_combout & (\z80_|execute_|ctl_reg_sel_pc~7_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h1050; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout = (\z80_|execute_|ctl_inc_cy~82_combout & (\z80_|execute_|ctl_inc_cy~38_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~87_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~82_combout ), - .datab(\z80_|execute_|ctl_inc_cy~38_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datad(\z80_|execute_|ctl_inc_cy~87_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_mWrite~16_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_sel_pc~11_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ixy_d~16_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ixy_d~16_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~40_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~40 .lut_mask = 16'h4050; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_ir_we~6_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~18_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'h001F; -defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (!\z80_|execute_|ctl_mRead~19_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h00AF; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (!\z80_|execute_|ctl_reg_sel_wz~7_combout & ((\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00FE; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & ((\z80_|execute_|fMRead~2_combout ) # ((!\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|pc_inc_hold~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|fMRead~2_combout ), - .datac(\z80_|execute_|pc_inc_hold~18_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h00DC; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal40~0_combout ) - - .dataa(\z80_|pla_decode_|Equal40~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h57FF; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout = (!\z80_|pla_decode_|Equal24~1_combout & (!\z80_|pla_decode_|Equal19~0_combout & (!\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~1_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .lut_mask = 16'h050F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~40_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h3323; -defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0101; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (\z80_|pla_decode_|Equal33~3_combout & (\z80_|execute_|ctl_inc_dec~3_combout & ((\z80_|execute_|ctl_reg_sys_hilo~24_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )))) # -// (!\z80_|pla_decode_|Equal33~3_combout & (((\z80_|execute_|ctl_reg_sys_hilo~24_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_inc_dec~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'hF531; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4500; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & (((\z80_|execute_|pc_inc_hold~40_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~40_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h3B00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h4500; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~16_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (!\z80_|execute_|ctl_reg_sys_hilo~20_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hA8AA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h8C0C; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (\z80_|execute_|setM1~52_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout & \z80_|execute_|ctl_reg_sel_pc~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~20_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~19_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h5444; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # (((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~10_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_ir_we~4_combout & (((\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~7_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((\z80_|execute_|ctl_reg_sel_wz~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hCF05; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & \z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~19_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'hFFDC; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal38~2_combout ) # (\z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N4 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .datac(\z80_|pla_decode_|Equal24~1_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N4 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|reg_control_|reg_sys_we_lo~1_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h0777; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # (\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~24_combout & !\z80_|execute_|ctl_mRead~23_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~24_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datad(\z80_|execute_|ctl_mRead~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h01FF; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~3_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h2A00; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~25_combout & (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal13~1_combout )) # (!\z80_|pla_decode_|Equal13~0_combout ) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'hEAEA; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~11_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_bus~4_combout ), - .datad(\z80_|execute_|ctl_flags_bus~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'hCC4C; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( -// Equation(s): -// \z80_|execute_|fMRead~27_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_alu_shift_oe~28_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_flags_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~12_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~27_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~12_combout ), - .datab(\z80_|execute_|fMRead~27_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~7_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .lut_mask = 16'hBABB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~36_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & \z80_|execute_|ctl_alu_op_low~36_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_state_alu~7_combout & !\z80_|execute_|ctl_alu_shift_oe~15_combout )) - - .dataa(\z80_|execute_|ctl_sw_2u~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'h0088; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (\z80_|execute_|ctl_alu_op_low~21_combout & (!\z80_|execute_|ctl_reg_gp_sel~5_combout & (\z80_|execute_|setM1~17_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datac(\z80_|execute_|setM1~17_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_mRead~38_combout & (!\z80_|execute_|ctl_mRead~13_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_mRead~38_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~27_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hC8CC; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~2_combout = (\z80_|execute_|ctl_flags_cf_we~7_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_flags_use_cf2~13_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_pf_sel[0]~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & (\z80_|execute_|ctl_alu_oe~6_combout & \z80_|execute_|ctl_flags_pf_we~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~6_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~11_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|ir_|opcode [5] & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mRead~38_combout )))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mWrite~7_combout & ((!\z80_|execute_|ctl_mWrite~2_combout )))) # (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_ir_we~11_combout )) -// # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datad(\z80_|pla_decode_|Equal20~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_xy_we~16_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~13_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ctl_reg_use_sp~1_combout & \z80_|execute_|ctl_flags_alu~14_combout ))) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1010; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T5_ff~q )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal10~0_combout & ((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (((!\z80_|execute_|ixy_d~5_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & \z80_|execute_|ctl_flags_alu~10_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~11_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datab(\z80_|execute_|ctl_flags_alu~11_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~6_combout = (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~8_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|execute_|ctl_flags_alu~6_combout & \z80_|execute_|ctl_flags_alu~17_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_alu~6_combout ), - .datad(\z80_|execute_|ctl_flags_alu~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal56~0_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal1~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal1~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hEFCC; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~19_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~19_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~9_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_flags_alu~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout ))) # (!\z80_|execute_|ctl_flags_alu~8_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .datac(\z80_|execute_|ctl_flags_alu~7_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (((\z80_|execute_|ctl_flags_alu~9_combout ) # (!\z80_|execute_|ctl_flags_alu~12_combout )) # (!\z80_|execute_|ctl_flags_alu~15_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_alu~15_combout ), - .datac(\z80_|execute_|ctl_flags_alu~12_combout ), - .datad(\z80_|execute_|ctl_flags_alu~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFFE0; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~6_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|execute_|ctl_reg_gp_sel~5_combout & (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|execute_|comb~0_combout -// $ (!\z80_|ir_|opcode [0])))) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'hD00D; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout & !\z80_|execute_|ctl_sw_2u~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ), - .datad(\z80_|execute_|ctl_sw_2u~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|execute_|nextM~2_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hC040; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = (((\z80_|execute_|ctl_reg_out_hi~8_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N20 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N21 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~28_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h3323; -defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & !\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; -defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h3120; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h3210; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N12 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N13 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de2~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hC840; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~22_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~22 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de2~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hC480; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_hl2~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~23_combout = (\z80_|reg_file_|gdfx_temp1[7]~22_combout & (\z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~23 .lut_mask = 16'hC400; -defparam \z80_|reg_file_|gdfx_temp1[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_af~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_control_|bank_exx~q & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|reg_control_|bank_exx~q & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~24 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h1115; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_mRead~7_combout -// & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h2020; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (\z80_|execute_|ctl_reg_in_hi~10_combout & (\z80_|execute_|ctl_reg_in_hi~7_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = ((\z80_|execute_|ctl_reg_in_hi~9_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~11_combout ) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~26_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[7]~20_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~26 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|decode_state_|DFFE_inst4~q & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~25_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~25 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (!\z80_|pla_decode_|Equal33~3_combout & (!\z80_|pla_decode_|Equal24~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal6~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|pla_decode_|Equal24~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|execute_|ctl_mWrite~16_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~32_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hBFAF; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~1_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hDDD5; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (!\z80_|execute_|ctl_mRead~16_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~0_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~39_combout = (\z80_|execute_|pc_inc_hold~18_combout & (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|pc_inc_hold~18_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~39 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_reg_sys_hilo~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (\z80_|execute_|setM1~36_combout & (\z80_|execute_|ctl_reg_sys_hilo~39_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ))) - - .dataa(\z80_|execute_|setM1~36_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~39_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h0800; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( -// Equation(s): -// \z80_|execute_|fMRead~11_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~37_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'h0004; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (((\z80_|execute_|ctl_bus_inc_oe~31_combout & \z80_|execute_|fMRead~11_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datac(\z80_|execute_|fMRead~11_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h80AA; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFDFF; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~17_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~27 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[7]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~28_combout = (\z80_|reg_file_|gdfx_temp1[7]~24_combout & (\z80_|reg_file_|gdfx_temp1[7]~26_combout & (\z80_|reg_file_|gdfx_temp1[7]~25_combout & \z80_|reg_file_|gdfx_temp1[7]~27_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~27_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_32 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~29_combout = (\z80_|reg_file_|gdfx_temp1[7]~23_combout & (\z80_|reg_file_|gdfx_temp1[7]~28_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~23_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datac(\z80_|reg_file_|gdfx_temp1[7]~28_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~29 .lut_mask = 16'h80A0; -defparam \z80_|reg_file_|gdfx_temp1[7]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~30_combout = ((\z80_|reg_file_|gdfx_temp1[7]~29_combout & ((\z80_|reg_file_|db_hi_as[7]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~29_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~30 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp1[7]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_shift_oe~15_combout ) # (\z80_|execute_|ctl_alu_op_low~20_combout )))) - - .dataa(\z80_|execute_|rsel3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~16_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h3133; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_iorw~10_combout & \z80_|execute_|rsel3~combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hB030; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_sw_2d~14_combout ), - .datad(\z80_|execute_|ctl_sw_2d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hFF2A; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = (\z80_|execute_|ctl_flags_alu~19_combout & (((!\z80_|execute_|ctl_mRead~28_combout & !\z80_|execute_|ctl_mRead~22_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_mRead~28_combout ), - .datac(\z80_|execute_|ctl_flags_alu~19_combout ), - .datad(\z80_|execute_|ctl_mRead~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~6_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~7_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h7030; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (\z80_|execute_|ixy_d~15_combout & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h070F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~13_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~7_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~7_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_sw_2d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & \z80_|execute_|ctl_sw_2d~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|ctl_sw_2d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~25_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~20_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~25_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h40C0; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_flags_alu~6_combout & \z80_|execute_|ctl_flags_alu~17_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_flags_alu~6_combout ), - .datad(\z80_|execute_|ctl_flags_alu~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|execute_|ctl_mRead~20_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (((!\z80_|execute_|ctl_mRead~20_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|ctl_sw_2d~4_combout ))) - - .dataa(\z80_|execute_|fMRead~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~9_combout ), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|ctl_sw_2d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( -// Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_mRead~26_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~2_combout & \z80_|execute_|fMRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & (\z80_|execute_|ctl_sw_2d~8_combout & \z80_|execute_|fMRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datac(\z80_|execute_|ctl_sw_2d~8_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~12_combout ) # ((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~12_combout ), - .datac(\z80_|execute_|ctl_sw_2d~11_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N0 -cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( -// Equation(s): -// \z80_|alu_|db[7]~19_combout = (\z80_|alu_control_|db[7]~18_combout & (((\z80_|reg_file_|gdfx_temp1[7]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_control_|db[7]~18_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[7]~30_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[7]~18_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_alu_oe~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hCF8F; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_alu_oe~12_combout ) # ((\z80_|execute_|ctl_alu_oe~11_combout ) # (!\z80_|execute_|ctl_alu_oe~10_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_oe~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h3F00; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_reg_in_hi~7_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_mWrite~8_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mRead~22_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_alu_oe~7_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|ctl_bus_db_we~5_combout & \z80_|execute_|ctl_alu_oe~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_alu_oe~8_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~13_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_alu_oe~8_combout ), - .datad(\z80_|execute_|ctl_flags_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout -// & (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_ir_we~7_combout & (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & \z80_|execute_|ctl_flags_sz_we~0_combout -// ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~1_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal1~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal1~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op_low~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_mRead~38_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # -// (!\z80_|execute_|ctl_mRead~38_combout & (((!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~31_combout & (\z80_|execute_|ctl_alu_shift_oe~30_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h0507; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|execute_|ctl_mWrite~2_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout -// & (((!\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~5_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout & \z80_|execute_|ctl_alu_op1_sel_bus~6_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~12_combout & (\z80_|execute_|ctl_flags_xy_we~12_combout & ((!\z80_|pla_decode_|Equal48~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) # (((!\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~4_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_66_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[3]~19_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~19_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00A0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFAA; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N13 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_hl2~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~49_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~49 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~50_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout & (\z80_|reg_file_|gdfx_temp1[3]~49_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datad(\z80_|reg_file_|gdfx_temp1[3]~49_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~50 .lut_mask = 16'hC400; -defparam \z80_|reg_file_|gdfx_temp1[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~52 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~51 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~54 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[3]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~53_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[3]~14_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[3]~14_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~53 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~55_combout = (\z80_|reg_file_|gdfx_temp1[3]~52_combout & (\z80_|reg_file_|gdfx_temp1[3]~51_combout & (\z80_|reg_file_|gdfx_temp1[3]~54_combout & \z80_|reg_file_|gdfx_temp1[3]~53_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~52_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~54_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~56_combout = (\z80_|reg_file_|gdfx_temp1[3]~50_combout & (\z80_|reg_file_|gdfx_temp1[3]~55_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datab(\z80_|reg_file_|gdfx_temp1[3]~50_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~55_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~56 .lut_mask = 16'h80C0; -defparam \z80_|reg_file_|gdfx_temp1[3]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_bus_inc_oe~32_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~11_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal21~1_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'h000F; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|setM1~37_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~15_combout )))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datac(\z80_|execute_|setM1~37_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'hFF15; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_al_we~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sel_wz~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~4_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0C00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h2FFF; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~18_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # (\z80_|execute_|ctl_reg_sel_pc~17_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (\z80_|reg_control_|reg_sel_pc~2_combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h2000; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0200; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|reg_control_|reg_sel_pc~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h0F0A; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = (\z80_|execute_|ctl_reg_sel_ir~0_combout ) # (((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hCFEF; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hF777; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEEFF; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|setM1~46_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|setM1~46_combout ), - .datac(\z80_|execute_|ctl_alu_oe~5_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_flags_bus~5_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h0DDD; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~3_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|fMRead~14_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|fMRead~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|fMRead~14_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|fMRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~4_combout & (\z80_|execute_|ctl_reg_sel_wz~13_combout & (\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datac(\z80_|execute_|ctl_sw_4d~3_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_4d~0_combout ), - .datac(\z80_|execute_|ctl_sw_4d~1_combout ), - .datad(\z80_|execute_|ctl_sw_4d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hF700; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [3] & ((\z80_|reg_file_|gdfx_temp1[3]~57_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[3]~57_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|reg_control_|reg_sel_pc~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~14_combout = (\z80_|reg_file_|db_hi_as[3]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~13_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~14 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~15_combout ) +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) .dataa(gnd), .datab(gnd), .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~15_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), + .combout(\z80_|address_latch_|abusz [7]), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_ir_we~4_combout & (((!\z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_state_alu~4_combout & -// ((!\z80_|execute_|ctl_al_we~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h32FA; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~9_combout ) # (((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) - - .dataa(\z80_|execute_|ctl_al_we~9_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N20 +// Location: LCCOMB_X37_Y17_N14 cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), .combout(\z80_|execute_|ctl_apin_mux~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h3322; +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N2 +// Location: LCCOMB_X37_Y17_N26 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( // Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((!\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )) # (!\z80_|execute_|ctl_al_we~5_combout ))) - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_al_we~5_combout ), - .datad(\z80_|execute_|ctl_apin_mux~1_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|execute_|ctl_al_we~14_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hAA2A; defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y18_N4 +// Location: LCCOMB_X40_Y17_N8 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( // Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = (((!\z80_|execute_|ctl_al_we~4_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) +// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & (\z80_|execute_|ctl_ir_we~4_combout & +// ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datab(\z80_|execute_|ctl_alu_oe~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_al_we~13_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h0EEE; defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y17_N18 +// Location: LCCOMB_X40_Y17_N30 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( // Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_al_we~7_combout ) # (!\z80_|execute_|ctl_iorw~12_combout )) # (!\z80_|execute_|ctl_mRead~21_combout ))) +// \z80_|execute_|ctl_al_we~8_combout = ((\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - .dataa(\z80_|execute_|ctl_mRead~21_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ctl_iorw~12_combout ), - .datad(\z80_|execute_|ctl_al_we~7_combout ), + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_al_we~7_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBF3; defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N16 +// Location: LCCOMB_X34_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = (((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout )) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), + .datab(\z80_|execute_|ctl_al_we~4_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_al_we~9_combout ) # (!\z80_|execute_|setM1~45_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|setM1~45_combout ), + .datad(\z80_|execute_|ctl_al_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEEAE; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N0 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( // Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~10_combout ) # ((\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) +// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - .dataa(\z80_|execute_|ctl_al_we~10_combout ), - .datab(\z80_|execute_|ctl_al_we~6_combout ), + .dataa(\z80_|execute_|ctl_al_we~6_combout ), + .datab(gnd), .datac(\z80_|execute_|ctl_sw_4d~5_combout ), - .datad(\z80_|execute_|ctl_al_we~8_combout ), + .datad(\z80_|execute_|ctl_al_we~10_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFAF; defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N18 +// Location: LCCOMB_X41_Y18_N4 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( // Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = ((\z80_|execute_|ctl_al_we~11_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|setM1~52_combout ) +// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|setM1~52_combout )) - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_al_we~11_combout ), .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hEFCF; defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N5 -dffeas \z80_|address_latch_|Q[11] ( +// Location: FF_X30_Y16_N5 +dffeas \z80_|address_latch_|Q[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), + .d(\z80_|address_latch_|abusz [7]), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -17752,724 +16298,119 @@ dffeas \z80_|address_latch_|Q[11] ( .ena(\z80_|execute_|ctl_al_we~12_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), + .q(\z80_|address_latch_|Q [7]), .prn(vcc)); // synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Location: LCCOMB_X35_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) +// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - .dataa(gnd), - .datab(\z80_|address_latch_|Q [11]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h33CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Location: LCCOMB_X36_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) +// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|execute_|ctl_inc_cy~77_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_inc_cy~47_combout & \z80_|execute_|ctl_inc_cy~78_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_inc_cy~78_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|fMRead~3_combout ))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (\z80_|execute_|ctl_bus_inc_oe~39_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~48_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # (\z80_|execute_|ctl_bus_inc_oe~37_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~45_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFD55; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~46_combout ) # (\z80_|execute_|ctl_bus_inc_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = (((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~15_combout = ((\z80_|reg_file_|db_hi_as[3]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[3]~14_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~15 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_hi_as[3]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~57_combout = ((\z80_|reg_file_|gdfx_temp1[3]~56_combout & ((\z80_|reg_file_|db_hi_as[3]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~56_combout ), - .datab(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~57 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|gdfx_temp1[3]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N28 -cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( -// Equation(s): -// \z80_|alu_|db[3]~13_combout = (\z80_|alu_|db_low[3]~23_combout & (((\z80_|reg_file_|gdfx_temp1[3]~57_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_|db_low[3]~23_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & -// ((\z80_|reg_file_|gdfx_temp1[3]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_|db_low[3]~23_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|setM1~48_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h040C; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_flags_alu~16_combout & ((\z80_|alu_|db_low[3]~23_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[3]~35_combout )))) # -// (!\z80_|execute_|ctl_flags_alu~16_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[3]~35_combout )))) - - .dataa(\z80_|execute_|ctl_flags_alu~16_combout ), - .datab(\z80_|alu_|db_low[3]~23_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .combout(\z80_|execute_|fIOWrite~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFFCF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3373; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Location: LCCOMB_X36_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( // Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & \z80_|execute_|ctl_flags_sz_we~5_combout )))) # -// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_alu_core_R~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout ))) +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_inc_dec~4_combout ))) - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|execute_|ctl_inc_dec~4_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Location: LCCOMB_X36_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( // Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) +// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~0_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_inc_dec~3_combout ), + .datad(\z80_|execute_|ctl_inc_dec~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hFF4F; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF3F3; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( // Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) +// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # (((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout )) # -// (!\z80_|execute_|ctl_flags_xy_we~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_flags_xy_we~13_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~7_combout ) # (!\z80_|execute_|ctl_flags_xy_we~16_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = ((\z80_|execute_|ctl_flags_xy_we~14_combout ) # ((!\z80_|execute_|ctl_flags_pf_we~4_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y15_N19 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N28 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( -// Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( -// Equation(s): -// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_flags_|flags_xf~q ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF300; -defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~30_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|M5~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_inc_cy~30_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal48~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .lut_mask = 16'hBAAA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~35_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout & \z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~35 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~42_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~42 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h55FF; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( +// Location: FF_X31_Y17_N17 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -18478,28 +16419,1319 @@ dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Location: LCCOMB_X26_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N1 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hCA00; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h1000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2A2; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[2]~29_combout & +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|alu_control_|db[2]~29_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datac(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8CAF; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0020; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[2]~42_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N31 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[0]~12_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .datad(\z80_|alu_control_|db[0]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~16_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & \z80_|reg_file_|gdfx_temp0[0]~13_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|reg_file_|gdfx_temp0[0]~22_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; // synopsys translate_on // Location: CLKCTRL_G18 @@ -18515,25 +17747,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N6 -cycloneive_lcell_comb \ula_|video_|Add0~0 ( -// Equation(s): -// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) -// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add0~0_combout ), - .cout(\ula_|video_|Add0~1 )); -// synopsys translate_off -defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; -defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N20 +// Location: LCCOMB_X39_Y33_N16 cycloneive_lcell_comb \ula_|video_|Add0~14 ( // Equation(s): // \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) @@ -18551,50 +17765,50 @@ defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N22 +// Location: LCCOMB_X39_Y33_N18 cycloneive_lcell_comb \ula_|video_|Add0~16 ( // Equation(s): // \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) // \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [8]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~15 ), .combout(\ula_|video_|Add0~16_combout ), .cout(\ula_|video_|Add0~17 )); // synopsys translate_off -defparam \ula_|video_|Add0~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N0 +// Location: LCCOMB_X39_Y33_N26 cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( // Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) - .dataa(\ula_|video_|Add0~16_combout ), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~16_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hAA00; +defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y31_N15 +// Location: FF_X39_Y33_N27 dffeas \ula_|video_|vga_hc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~2_combout ), + .d(\ula_|video_|vga_hc~2_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18605,32 +17819,32 @@ defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N24 +// Location: LCCOMB_X39_Y33_N20 cycloneive_lcell_comb \ula_|video_|Add0~18 ( // Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|vga_hc [9] $ (\ula_|video_|Add0~17 ) +// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) .dataa(gnd), - .datab(\ula_|video_|vga_hc [9]), + .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|vga_hc [9]), .cin(\ula_|video_|Add0~17 ), .combout(\ula_|video_|Add0~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h3C3C; +defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N4 +// Location: LCCOMB_X37_Y33_N20 cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( // Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) .dataa(gnd), - .datab(\ula_|video_|Add0~18_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~18_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~1_combout ), .cout()); @@ -18639,15 +17853,15 @@ defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y31_N29 +// Location: FF_X37_Y33_N21 dffeas \ula_|video_|vga_hc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~1_combout ), + .d(\ula_|video_|vga_hc~1_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18658,58 +17872,25 @@ defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N20 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Location: LCCOMB_X39_Y33_N2 +cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [0] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) +// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) +// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - .dataa(\ula_|video_|vga_hc [2]), + .dataa(gnd), .datab(\ula_|video_|vga_hc [0]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), + .datac(gnd), + .datad(vcc), .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); + .combout(\ula_|video_|Add0~0_combout ), + .cout(\ula_|video_|Add0~1 )); // synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N14 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & (\ula_|video_|vga_hc [5] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [4]), - .datac(\ula_|video_|vga_hc [5]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h1000; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N24 -cycloneive_lcell_comb \ula_|video_|Equal1~0 ( -// Equation(s): -// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|Equal0~1_combout ), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hFF7F; -defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N6 +// Location: LCCOMB_X34_Y31_N0 cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( // Equation(s): // \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) @@ -18726,15 +17907,15 @@ defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N11 +// Location: FF_X34_Y31_N1 dffeas \ula_|video_|vga_hc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~3_combout ), + .d(\ula_|video_|vga_hc~3_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18745,7 +17926,7 @@ defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N8 +// Location: LCCOMB_X39_Y33_N4 cycloneive_lcell_comb \ula_|video_|Add0~2 ( // Equation(s): // \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) @@ -18763,15 +17944,32 @@ defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y31_N17 +// Location: LCCOMB_X36_Y33_N16 +cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( +// Equation(s): +// \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Add0~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N17 dffeas \ula_|video_|vga_hc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~2_combout ), + .d(\ula_|video_|vga_hc[1]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18782,50 +17980,33 @@ defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N10 +// Location: LCCOMB_X39_Y33_N6 cycloneive_lcell_comb \ula_|video_|Add0~4 ( // Equation(s): // \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) // \ula_|video_|Add0~5 = CARRY((\ula_|video_|vga_hc [2] & !\ula_|video_|Add0~3 )) - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~3 ), .combout(\ula_|video_|Add0~4_combout ), .cout(\ula_|video_|Add0~5 )); // synopsys translate_off -defparam \ula_|video_|Add0~4 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N22 -cycloneive_lcell_comb \ula_|video_|vga_hc[2]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[2]~feeder_combout = \ula_|video_|Add0~4_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~4_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y31_N23 +// Location: FF_X39_Y33_N23 dffeas \ula_|video_|vga_hc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[2]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|Add0~4_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18836,7 +18017,7 @@ defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N12 +// Location: LCCOMB_X39_Y33_N8 cycloneive_lcell_comb \ula_|video_|Add0~6 ( // Equation(s): // \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) @@ -18854,10 +18035,27 @@ defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N13 +// Location: LCCOMB_X36_Y33_N8 +cycloneive_lcell_comb \ula_|video_|vga_hc[3]~feeder ( +// Equation(s): +// \ula_|video_|vga_hc[3]~feeder_combout = \ula_|video_|Add0~6_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Add0~6_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vga_hc[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N9 dffeas \ula_|video_|vga_hc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add0~6_combout ), + .d(\ula_|video_|vga_hc[3]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -18873,25 +18071,25 @@ defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N14 +// Location: LCCOMB_X39_Y33_N10 cycloneive_lcell_comb \ula_|video_|Add0~8 ( // Equation(s): // \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) // \ula_|video_|Add0~9 = CARRY((\ula_|video_|vga_hc [4] & !\ula_|video_|Add0~7 )) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [4]), + .dataa(\ula_|video_|vga_hc [4]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~7 ), .combout(\ula_|video_|Add0~8_combout ), .cout(\ula_|video_|Add0~9 )); // synopsys translate_off -defparam \ula_|video_|Add0~8 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N3 +// Location: FF_X39_Y33_N31 dffeas \ula_|video_|vga_hc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18910,7 +18108,58 @@ defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N16 +// Location: LCCOMB_X34_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N30 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( +// Equation(s): +// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) + + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|vga_hc [4]), + .datad(\ula_|video_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0200; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y33_N16 +cycloneive_lcell_comb \ula_|video_|Equal1~0 ( +// Equation(s): +// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; +defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N12 cycloneive_lcell_comb \ula_|video_|Add0~10 ( // Equation(s): // \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) @@ -18928,32 +18177,32 @@ defparam \ula_|video_|Add0~10 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N26 +// Location: LCCOMB_X39_Y33_N0 cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( // Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) - .dataa(\ula_|video_|Add0~10_combout ), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~10_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hAA00; +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y31_N1 +// Location: FF_X39_Y33_N1 dffeas \ula_|video_|vga_hc[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~0_combout ), + .d(\ula_|video_|vga_hc~0_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18964,7 +18213,7 @@ defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N18 +// Location: LCCOMB_X39_Y33_N14 cycloneive_lcell_comb \ula_|video_|Add0~12 ( // Equation(s): // \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) @@ -18982,7 +18231,7 @@ defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N5 +// Location: FF_X39_Y33_N29 dffeas \ula_|video_|vga_hc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -19001,7 +18250,7 @@ defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X31_Y31_N27 +// Location: FF_X39_Y33_N25 dffeas \ula_|video_|vga_hc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -19020,61 +18269,25 @@ defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N2 +// Location: LCCOMB_X35_Y33_N0 cycloneive_lcell_comb \ula_|video_|Add1~0 ( // Equation(s): // \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) // \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) - .dataa(\ula_|video_|vga_vc [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [0]), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\ula_|video_|Add1~0_combout ), .cout(\ula_|video_|Add1~1 )); // synopsys translate_off -defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; +defparam \ula_|video_|Add1~0 .lut_mask = 16'h33CC; defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N8 -cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( -// Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [0])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~0_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Add1~0_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y31_N9 -dffeas \ula_|video_|vga_vc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[0]~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N4 +// Location: LCCOMB_X35_Y33_N2 cycloneive_lcell_comb \ula_|video_|Add1~2 ( // Equation(s): // \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) @@ -19092,42 +18305,42 @@ defparam \ula_|video_|Add1~2 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N6 +// Location: LCCOMB_X35_Y33_N4 cycloneive_lcell_comb \ula_|video_|Add1~4 ( // Equation(s): // \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) // \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), + .dataa(\ula_|video_|vga_vc [2]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~3 ), .combout(\ula_|video_|Add1~4_combout ), .cout(\ula_|video_|Add1~5 )); // synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N24 +// Location: LCCOMB_X38_Y33_N12 cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( // Equation(s): // \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), .datab(\ula_|video_|Add1~4_combout ), .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N25 +// Location: FF_X38_Y33_N13 dffeas \ula_|video_|vga_vc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[2]~2_combout ), @@ -19146,7 +18359,7 @@ defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N8 +// Location: LCCOMB_X35_Y33_N6 cycloneive_lcell_comb \ula_|video_|Add1~6 ( // Equation(s): // \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) @@ -19164,7 +18377,7 @@ defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N2 +// Location: LCCOMB_X35_Y33_N20 cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( // Equation(s): // \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) @@ -19181,15 +18394,15 @@ defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h5140; defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N3 +// Location: FF_X38_Y33_N3 dffeas \ula_|video_|vga_vc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[3]~3_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|vga_vc[3]~3_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -19200,42 +18413,42 @@ defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N10 +// Location: LCCOMB_X35_Y33_N8 cycloneive_lcell_comb \ula_|video_|Add1~8 ( // Equation(s): // \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) // \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - .dataa(\ula_|video_|vga_vc [4]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~7 ), .combout(\ula_|video_|Add1~8_combout ), .cout(\ula_|video_|Add1~9 )); // synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N20 +// Location: LCCOMB_X38_Y33_N20 cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( // Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [4])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~8_combout ))))) +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~8_combout ), .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Add1~8_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[4]~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N21 +// Location: FF_X38_Y33_N21 dffeas \ula_|video_|vga_vc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[4]~5_combout ), @@ -19254,50 +18467,50 @@ defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N12 +// Location: LCCOMB_X35_Y33_N10 cycloneive_lcell_comb \ula_|video_|Add1~10 ( // Equation(s): // \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) // \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~9 ), .combout(\ula_|video_|Add1~10_combout ), .cout(\ula_|video_|Add1~11 )); // synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N0 +// Location: LCCOMB_X35_Y33_N22 cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( // Equation(s): // \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|vga_vc [5]), .datad(\ula_|video_|Add1~10_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[5]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5140; defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N1 +// Location: FF_X38_Y33_N17 dffeas \ula_|video_|vga_vc[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[5]~8_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|vga_vc[5]~8_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -19308,42 +18521,42 @@ defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N14 +// Location: LCCOMB_X35_Y33_N12 cycloneive_lcell_comb \ula_|video_|Add1~12 ( // Equation(s): // \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) // \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~11 ), .combout(\ula_|video_|Add1~12_combout ), .cout(\ula_|video_|Add1~13 )); // synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N6 +// Location: LCCOMB_X38_Y33_N6 cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( // Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [6])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~12_combout ))))) +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~12_combout ), .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Add1~12_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[6]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N7 +// Location: FF_X38_Y33_N7 dffeas \ula_|video_|vga_vc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[6]~4_combout ), @@ -19362,42 +18575,42 @@ defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N16 +// Location: LCCOMB_X35_Y33_N14 cycloneive_lcell_comb \ula_|video_|Add1~14 ( // Equation(s): // \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) // \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) - .dataa(\ula_|video_|vga_vc [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~13 ), .combout(\ula_|video_|Add1~14_combout ), .cout(\ula_|video_|Add1~15 )); // synopsys translate_off -defparam \ula_|video_|Add1~14 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N22 +// Location: LCCOMB_X38_Y33_N14 cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( // Equation(s): // \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), .datab(\ula_|video_|Add1~14_combout ), .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[7]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N23 +// Location: FF_X38_Y33_N15 dffeas \ula_|video_|vga_vc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[7]~6_combout ), @@ -19416,7 +18629,7 @@ defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N18 +// Location: LCCOMB_X35_Y33_N16 cycloneive_lcell_comb \ula_|video_|Add1~16 ( // Equation(s): // \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) @@ -19434,24 +18647,24 @@ defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N0 +// Location: LCCOMB_X38_Y33_N24 cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( // Equation(s): -// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [8])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~16_combout ))))) +// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~16_combout ), .datac(\ula_|video_|vga_vc [8]), - .datad(\ula_|video_|Add1~16_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[8]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N1 +// Location: FF_X38_Y33_N25 dffeas \ula_|video_|vga_vc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[8]~7_combout ), @@ -19470,24 +18683,7 @@ defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N10 -cycloneive_lcell_comb \ula_|video_|Equal2~0 ( -// Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N20 +// Location: LCCOMB_X35_Y33_N18 cycloneive_lcell_comb \ula_|video_|Add1~18 ( // Equation(s): // \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) @@ -19504,24 +18700,24 @@ defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N28 +// Location: LCCOMB_X38_Y33_N10 cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( // Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [9])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~18_combout ))))) +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~18_combout ), .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Add1~18_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[9]~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N29 +// Location: FF_X38_Y33_N11 dffeas \ula_|video_|vga_vc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[9]~9_combout ), @@ -19540,58 +18736,111 @@ defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N26 +// Location: LCCOMB_X38_Y33_N18 +cycloneive_lcell_comb \ula_|video_|Equal2~0 ( +// Equation(s): +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(\ula_|video_|vga_vc [4]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [8]), + .cin(gnd), + .combout(\ula_|video_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N30 cycloneive_lcell_comb \ula_|video_|Equal3~0 ( // Equation(s): -// \ula_|video_|Equal3~0_combout = (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [2] & \ula_|video_|vga_vc [3]))) +// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0]))) - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [0]), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|vga_vc [3]), + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|vga_vc [0]), .cin(gnd), .combout(\ula_|video_|Equal3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h4000; +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0800; defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N16 +// Location: LCCOMB_X37_Y33_N18 cycloneive_lcell_comb \ula_|video_|Equal3~1 ( // Equation(s): -// \ula_|video_|Equal3~1_combout = (\ula_|video_|Equal2~0_combout & (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & \ula_|video_|Equal3~0_combout ))) +// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal2~0_combout & \ula_|video_|Equal3~0_combout ))) - .dataa(\ula_|video_|Equal2~0_combout ), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [9]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|Equal2~0_combout ), .datad(\ula_|video_|Equal3~0_combout ), .cin(gnd), .combout(\ula_|video_|Equal3~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal3~1 .lut_mask = 16'h2000; +defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N30 +// Location: LCCOMB_X38_Y33_N28 +cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( +// Equation(s): +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~0_combout ), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y33_N29 +dffeas \ula_|video_|vga_vc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N22 cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( // Equation(s): // \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), .datab(\ula_|video_|Add1~2_combout ), .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N31 +// Location: FF_X38_Y33_N23 dffeas \ula_|video_|vga_vc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[1]~1_combout ), @@ -19620,14 +18869,14 @@ defparam \SW[1]~input .bus_hold = "false"; defparam \SW[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N16 +// Location: LCCOMB_X34_Y33_N30 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & (!\ula_|video_|vga_hc [8] & !\ula_|video_|vga_hc [9]))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & !\ula_|video_|vga_hc [9]))) - .dataa(\ula_|video_|vga_vc [1]), - .datab(\SW[1]~input_o ), - .datac(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [8]), + .datab(\ula_|video_|vga_vc [1]), + .datac(\SW[1]~input_o ), .datad(\ula_|video_|vga_hc [9]), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), @@ -19637,15 +18886,15 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N0 +// Location: LCCOMB_X35_Y17_N30 cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( // Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [5]), + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), .combout(\z80_|pla_decode_|Equal79~0_combout ), .cout()); @@ -19654,34 +18903,16 @@ defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N26 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( -// Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )) - - .dataa(\z80_|interrupts_|iff1~q ), - .datab(\z80_|pla_decode_|Equal79~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hE2AA; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N16 +// Location: LCCOMB_X35_Y17_N16 cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( // Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|DFFE_instIFF2~q +// ))))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal79~0_combout ), .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .cin(gnd), .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), .cout()); @@ -19690,24 +18921,24 @@ defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N24 +// Location: LCCOMB_X32_Y15_N28 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( // Equation(s): // \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h5F0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h7733; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: CLKCTRL_G8 +// Location: CLKCTRL_G16 cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), @@ -19720,7 +18951,7 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clo defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X46_Y10_N17 +// Location: FF_X35_Y17_N17 dffeas \z80_|interrupts_|DFFE_instIFF2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), @@ -19739,42 +18970,60 @@ defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N10 +// Location: LCCOMB_X35_Y17_N2 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|interrupts_|iff1~q ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hEC4C; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N18 cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( // Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )) +// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|iff1~0_combout ))))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|interrupts_|iff1~0_combout )))) - .dataa(\z80_|interrupts_|iff1~0_combout ), + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|interrupts_|iff1~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|iff1~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hCAAA; +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hDF80; defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N6 +// Location: LCCOMB_X38_Y18_N12 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFAF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X46_Y10_N11 +// Location: FF_X35_Y17_N19 dffeas \z80_|interrupts_|iff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|iff1~1_combout ), @@ -19793,15 +19042,15 @@ defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; defparam \z80_|interrupts_|iff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N22 +// Location: LCCOMB_X37_Y33_N4 cycloneive_lcell_comb \ula_|video_|Equal2~1 ( // Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [3]))) +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [0]))) - .dataa(\ula_|video_|vga_vc [2]), - .datab(\ula_|video_|vga_vc [0]), + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|vga_vc [2]), .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [0]), .cin(gnd), .combout(\ula_|video_|Equal2~1_combout ), .cout()); @@ -19810,24 +19059,24 @@ defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N12 +// Location: LCCOMB_X37_Y33_N14 cycloneive_lcell_comb \ula_|video_|Equal2~2 ( // Equation(s): -// \ula_|video_|Equal2~2_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~1_combout & \ula_|video_|Equal2~0_combout )) +// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (\ula_|video_|Equal2~0_combout & !\ula_|video_|vga_vc [5])) .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|Equal2~1_combout ), - .datad(\ula_|video_|Equal2~0_combout ), + .datab(\ula_|video_|Equal2~1_combout ), + .datac(\ula_|video_|Equal2~0_combout ), + .datad(\ula_|video_|vga_vc [5]), .cin(gnd), .combout(\ula_|video_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h3000; +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h00C0; defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y20_N20 +// Location: LCCOMB_X35_Y31_N28 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( // Equation(s): // \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (\z80_|interrupts_|iff1~q & \ula_|video_|Equal2~2_combout ))) @@ -19844,7 +19093,7 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y20_N21 +// Location: FF_X35_Y31_N29 dffeas \z80_|interrupts_|int_armed ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), @@ -19863,32 +19112,15 @@ defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; defparam \z80_|interrupts_|int_armed .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N28 -cycloneive_lcell_comb \z80_|interrupts_|DFFE_inst44~feeder ( -// Equation(s): -// \z80_|interrupts_|DFFE_inst44~feeder_combout = \z80_|interrupts_|int_armed~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|interrupts_|int_armed~q ), - .cin(gnd), - .combout(\z80_|interrupts_|DFFE_inst44~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_inst44~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|DFFE_inst44~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X50_Y12_N29 +// Location: FF_X32_Y15_N11 dffeas \z80_|interrupts_|DFFE_inst44 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|DFFE_inst44~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|interrupts_|int_armed~q ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|interrupts_|test1~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -19899,127 +19131,163 @@ defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Location: LCCOMB_X32_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) +// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datab(gnd), .datac(\z80_|decode_state_|in_halt~q ), - .datad(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .combout(\z80_|execute_|pc_inc_hold~38_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Location: LCCOMB_X35_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~6_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~7_combout ) +// \z80_|execute_|ctl_inc_cy~91_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .combout(\z80_|execute_|ctl_inc_cy~91_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Location: LCCOMB_X35_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~45 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|pc_inc_hold~40_combout ))) +// \z80_|execute_|pc_inc_hold~45_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & +// (((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|pc_inc_hold~40_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .combout(\z80_|execute_|pc_inc_hold~45_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~45 .lut_mask = 16'hF888; +defparam \z80_|execute_|pc_inc_hold~45 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Location: LCCOMB_X35_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~44 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (((\z80_|execute_|ctl_alu_op_low~14_combout & -// \z80_|execute_|ctl_mRead~38_combout )))) +// \z80_|execute_|pc_inc_hold~44_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~49_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~44 .lut_mask = 16'h8CCC; +defparam \z80_|execute_|pc_inc_hold~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~46 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~46_combout = (\z80_|execute_|pc_inc_hold~45_combout ) # ((\z80_|execute_|pc_inc_hold~44_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~49_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~45_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|pc_inc_hold~44_combout ), + .datad(\z80_|execute_|pc_inc_hold~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~46 .lut_mask = 16'hFAFE; +defparam \z80_|execute_|pc_inc_hold~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & +// (\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), + .datab(\z80_|pla_decode_|Equal52~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), + .combout(\z80_|execute_|pc_inc_hold~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hF8A8; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Location: LCCOMB_X35_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~50 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = (((\z80_|execute_|ctl_inc_cy~49_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~11_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ) +// \z80_|execute_|pc_inc_hold~50_combout = (\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datad(\z80_|execute_|ctl_inc_cy~49_combout ), + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|pc_inc_hold~37_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .combout(\z80_|execute_|pc_inc_hold~50_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~50 .lut_mask = 16'hECCC; +defparam \z80_|execute_|pc_inc_hold~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Location: LCCOMB_X36_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_inc_cy~51_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout )) +// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_mRead~10_combout & (((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal6~1_combout & +// ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) - .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), - .datab(\z80_|execute_|ctl_inc_cy~50_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .combout(\z80_|execute_|pc_inc_hold~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Location: LCCOMB_X36_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = (\z80_|execute_|ctl_inc_cy~52_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # (!\z80_|execute_|fMRead~11_combout )))) +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~52_combout ), - .datac(\z80_|execute_|fMRead~11_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hEFCC; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N8 +// Location: LCCOMB_X34_Y17_N26 cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( // Equation(s): // \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~2_combout ))) @@ -20036,4853 +19304,1086 @@ defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|pc_inc_hold~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datad(\z80_|execute_|pc_inc_hold~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hF8FC; -defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~24_combout = (\z80_|execute_|ixy_d~4_combout & (((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) # (!\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & -// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ixy_d~4_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (((\z80_|execute_|ctl_mRead~17_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ixy_d~4_combout & -// (\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hECE0; -defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~25_combout = (\z80_|execute_|pc_inc_hold~22_combout ) # ((\z80_|execute_|pc_inc_hold~24_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # (\z80_|execute_|pc_inc_hold~23_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~22_combout ), - .datab(\z80_|execute_|pc_inc_hold~24_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datad(\z80_|execute_|pc_inc_hold~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~20_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal25~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFF37; -defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~10_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hA080; -defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~21_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~19_combout ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'h37FF; -defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~26_combout = (!\z80_|execute_|pc_inc_hold~25_combout & (\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|pc_inc_hold~21_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(\z80_|execute_|pc_inc_hold~20_combout ), - .datac(\z80_|execute_|pc_inc_hold~41_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'h0400; -defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & -// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|execute_|ctl_inc_cy~44_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~13_combout )) # (!\z80_|execute_|ctl_inc_cy~87_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ctl_inc_cy~45_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~43_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~85_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'hBBB3; -defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~43_combout ) # (!\z80_|execute_|ctl_inc_cy~47_combout ))) # (!\z80_|execute_|ctl_inc_cy~33_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~33_combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~47_combout ), - .datad(\z80_|execute_|ctl_inc_cy~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|execute_|pc_inc_hold~30_combout & (((\z80_|execute_|pc_inc_hold~26_combout & \z80_|execute_|ctl_inc_cy~48_combout )))) # (!\z80_|execute_|pc_inc_hold~30_combout & ((\z80_|execute_|ctl_inc_cy~54_combout ) # -// ((\z80_|execute_|ctl_inc_cy~48_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~30_combout ), - .datab(\z80_|execute_|ctl_inc_cy~54_combout ), - .datac(\z80_|execute_|pc_inc_hold~26_combout ), - .datad(\z80_|execute_|ctl_inc_cy~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hF544; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ixy_d~10_combout & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~42_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hA800; -defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|pc_inc_hold~19_combout & \z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout & -// (\z80_|execute_|pc_inc_hold~19_combout & (\z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|pc_inc_hold~19_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|execute_|pc_inc_hold~27_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|pc_inc_hold~27_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|pc_inc_hold~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .datab(\z80_|execute_|pc_inc_hold~26_combout ), - .datac(\z80_|execute_|pc_inc_hold~42_combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'h0004; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout & (((\z80_|execute_|ctl_inc_cy~39_combout & \z80_|execute_|pc_inc_hold~29_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'hB030; -defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|pc_inc_hold~42_combout & (\z80_|execute_|pc_inc_hold~26_combout & (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout & !\z80_|execute_|pc_inc_hold~28_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~42_combout ), - .datab(\z80_|execute_|pc_inc_hold~26_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|execute_|ctl_inc_cy~41_combout ) # ((\z80_|execute_|ctl_inc_cy~83_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # (!\z80_|execute_|pc_inc_hold~30_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~41_combout ), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|ctl_inc_cy~83_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hFABA; -defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (!\z80_|decode_state_|in_halt~q & \z80_|execute_|ctl_mRead~16_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~62_combout ) # ((!\z80_|execute_|pc_inc_hold~22_combout & !\z80_|execute_|ctl_reg_sys_hilo~24_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~22_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~62_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'hC0C4; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N20 +// Location: LCCOMB_X36_Y19_N26 cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~23_combout ) # ((\z80_|execute_|pc_inc_hold~22_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ixy_d~4_combout ))) +// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout )))) - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|pc_inc_hold~23_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|pc_inc_hold~22_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|pc_inc_hold~28_combout ), .cin(gnd), .combout(\z80_|execute_|pc_inc_hold~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hECEE; defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|pc_inc_hold~31_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~63_combout ), - .datad(\z80_|execute_|pc_inc_hold~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'hF0F8; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal33~1_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = ((!\z80_|execute_|pc_inc_hold~22_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout & \z80_|execute_|ctl_inc_cy~58_combout ))) # (!\z80_|execute_|pc_inc_hold~30_combout ) - - .dataa(\z80_|execute_|pc_inc_hold~22_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_inc_cy~58_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'h1F0F; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~12_combout ) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|execute_|pc_inc_hold~25_combout & (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_inc_cy~59_combout ))) # (!\z80_|execute_|pc_inc_hold~25_combout & -// (((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & \z80_|execute_|ctl_inc_cy~59_combout )) # (!\z80_|execute_|ctl_inc_cy~60_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_inc_cy~59_combout ), - .datad(\z80_|execute_|ctl_inc_cy~60_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'hC0D5; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N8 +// Location: LCCOMB_X36_Y19_N12 cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|pc_inc_hold~25_combout ) # ((\z80_|execute_|pc_inc_hold~41_combout ) # (!\z80_|execute_|pc_inc_hold~20_combout )) +// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|execute_|ctl_mRead~15_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(gnd), - .datac(\z80_|execute_|pc_inc_hold~41_combout ), - .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), .cin(gnd), .combout(\z80_|execute_|pc_inc_hold~32_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hFAFF; +defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hEEA0; defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N2 +// Location: LCCOMB_X36_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~31_combout ) # (\z80_|execute_|pc_inc_hold~32_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~33_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~31_combout ), + .datad(\z80_|execute_|pc_inc_hold~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~51 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~51_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~51 .lut_mask = 16'h57FF; +defparam \z80_|execute_|pc_inc_hold~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~52 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~52_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~52 .lut_mask = 16'hA800; +defparam \z80_|execute_|pc_inc_hold~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~35_combout = (!\z80_|execute_|pc_inc_hold~34_combout & (\z80_|execute_|pc_inc_hold~51_combout & (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~52_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~34_combout ), + .datab(\z80_|execute_|pc_inc_hold~51_combout ), + .datac(\z80_|execute_|pc_inc_hold~30_combout ), + .datad(\z80_|execute_|pc_inc_hold~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'h0040; +defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|pc_inc_hold~35_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hCF8F; +defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~10_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_inc_cy~44_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~50_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|ctl_inc_cy~44_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~43 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~43_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~43 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~91_combout & (!\z80_|execute_|pc_inc_hold~46_combout & (\z80_|execute_|ctl_inc_cy~45_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), + .datab(\z80_|execute_|pc_inc_hold~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~45_combout ), + .datad(\z80_|execute_|pc_inc_hold~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~72_combout & \z80_|execute_|ctl_inc_cy~71_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_inc_cy~72_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~71_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_mWrite~16_combout & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h8C00; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~53 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~53_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~53 .lut_mask = 16'hE000; +defparam \z80_|execute_|pc_inc_hold~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~39_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~53_combout & (\z80_|execute_|pc_inc_hold~35_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~50_combout ), + .datab(\z80_|execute_|pc_inc_hold~53_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'h0010; +defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~47 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~47_combout = (\z80_|execute_|pc_inc_hold~46_combout ) # ((\z80_|execute_|pc_inc_hold~43_combout ) # ((!\z80_|execute_|ctl_inc_cy~44_combout ) # (!\z80_|execute_|pc_inc_hold~39_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~46_combout ), + .datab(\z80_|execute_|pc_inc_hold~43_combout ), + .datac(\z80_|execute_|pc_inc_hold~39_combout ), + .datad(\z80_|execute_|ctl_inc_cy~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~47 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|pc_inc_hold~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~34_combout )) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~43_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~43_combout ), + .datab(\z80_|execute_|ctl_inc_cy~35_combout ), + .datac(\z80_|execute_|ctl_inc_cy~34_combout ), + .datad(\z80_|execute_|ctl_inc_cy~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = ((\z80_|execute_|ctl_inc_cy~74_combout ) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~39_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~39_combout ), + .datac(\z80_|execute_|ctl_inc_cy~77_combout ), + .datad(\z80_|execute_|ctl_inc_cy~74_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|pc_inc_hold~47_combout & \z80_|execute_|ctl_inc_cy~91_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~47_combout ), + .datab(\z80_|execute_|ctl_inc_cy~78_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~91_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h4C0C; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|pc_inc_hold~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal19~1_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|pla_decode_|Equal19~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hA800; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|ctl_inc_cy~81_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|pc_inc_hold~47_combout & (!\z80_|execute_|pc_inc_hold~38_combout & ((\z80_|execute_|ctl_inc_cy~82_combout ) # (!\z80_|execute_|ctl_inc_cy~38_combout )))) # (!\z80_|execute_|pc_inc_hold~47_combout +// & ((\z80_|execute_|ctl_inc_cy~82_combout ) # ((!\z80_|execute_|ctl_inc_cy~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~47_combout ), + .datab(\z80_|execute_|ctl_inc_cy~82_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h4C5F; +defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N26 cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout )) - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ctl_inc_cy~80_combout ), + .datad(\z80_|execute_|ctl_inc_cy~83_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_inc_cy~84_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hFFFC; defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Location: LCCOMB_X37_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~64_combout ) # ((\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|pc_inc_hold~32_combout & !\z80_|execute_|ctl_inc_cy~84_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), - .datab(\z80_|execute_|ctl_inc_cy~61_combout ), - .datac(\z80_|execute_|pc_inc_hold~32_combout ), - .datad(\z80_|execute_|ctl_inc_cy~84_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = ((!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h575F; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = (!\z80_|execute_|ctl_inc_cy~56_combout & (!\z80_|execute_|pc_inc_hold~42_combout & \z80_|execute_|pc_inc_hold~26_combout )) +// \z80_|execute_|pc_inc_hold~42_combout = ((\z80_|execute_|pc_inc_hold~34_combout ) # (\z80_|execute_|pc_inc_hold~52_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ) .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~56_combout ), - .datac(\z80_|execute_|pc_inc_hold~42_combout ), - .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .datab(\z80_|execute_|pc_inc_hold~30_combout ), + .datac(\z80_|execute_|pc_inc_hold~34_combout ), + .datad(\z80_|execute_|pc_inc_hold~52_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .combout(\z80_|execute_|pc_inc_hold~42_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'h0300; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( +// Location: LCCOMB_X37_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|pc_inc_hold~30_combout & ((\z80_|execute_|pc_inc_hold~25_combout ) # (!\z80_|execute_|pc_inc_hold~20_combout ))) +// \z80_|execute_|ctl_inc_cy~90_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(gnd), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), + .combout(\z80_|execute_|ctl_inc_cy~90_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hA0F0; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N2 +// Location: LCCOMB_X36_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~31_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|pc_inc_hold~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N18 cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = (\z80_|execute_|ctl_inc_cy~65_combout ) # ((\z80_|execute_|ctl_inc_cy~57_combout ) # ((!\z80_|execute_|pc_inc_hold~33_combout & !\z80_|execute_|ctl_inc_cy~38_combout ))) +// \z80_|execute_|ctl_inc_cy~66_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q ))) - .dataa(\z80_|execute_|ctl_inc_cy~65_combout ), - .datab(\z80_|execute_|ctl_inc_cy~57_combout ), - .datac(\z80_|execute_|pc_inc_hold~33_combout ), - .datad(\z80_|execute_|ctl_inc_cy~38_combout ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), .combout(\z80_|execute_|ctl_inc_cy~66_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hEEEF; +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h0004; defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N20 +// Location: LCCOMB_X36_Y19_N4 cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~40_combout ) # ((\z80_|execute_|ctl_inc_cy~42_combout ) # (\z80_|execute_|ctl_inc_cy~66_combout ))) +// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & !\z80_|execute_|pc_inc_hold~31_combout )))) - .dataa(\z80_|execute_|ctl_inc_cy~55_combout ), - .datab(\z80_|execute_|ctl_inc_cy~40_combout ), - .datac(\z80_|execute_|ctl_inc_cy~42_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datac(\z80_|execute_|pc_inc_hold~31_combout ), .datad(\z80_|execute_|ctl_inc_cy~66_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_inc_cy~67_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hAA02; defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Location: LCCOMB_X36_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = (((!\z80_|execute_|ctl_inc_cy~37_combout ) # (!\z80_|execute_|ctl_inc_cy~31_combout )) # (!\z80_|execute_|ctl_inc_cy~36_combout )) # (!\z80_|execute_|ctl_inc_cy~30_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~30_combout ), - .datab(\z80_|execute_|ctl_inc_cy~36_combout ), - .datac(\z80_|execute_|ctl_inc_cy~31_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~75_combout ) # ((!\z80_|execute_|ctl_inc_cy~35_combout ) # (!\z80_|execute_|ctl_inc_cy~78_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_inc_cy~78_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'hBBFF; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = ((\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_inc_cy~72_combout & \z80_|pla_decode_|Equal19~1_combout ))) # (!\z80_|execute_|ctl_inc_cy~34_combout ) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_inc_cy~34_combout ), - .datac(\z80_|execute_|ctl_inc_cy~72_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'hB333; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|ctl_mRead~15_combout ))) .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|pc_inc_hold~41_combout ), + .datac(\z80_|execute_|ctl_inc_cy~67_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Location: LCCOMB_X36_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & (!\z80_|execute_|pc_inc_hold~34_combout & \z80_|execute_|pc_inc_hold~29_combout ))) +// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~31_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~73_combout & ((!\z80_|execute_|pc_inc_hold~30_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_inc_cy~73_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'hFF4C; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~74_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout & ((\z80_|execute_|ctl_inc_cy~68_combout ) # (!\z80_|execute_|pc_inc_hold~30_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~68_combout ), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_inc_cy~74_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hFF8C; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = (!\z80_|execute_|ctl_inc_dec~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'h5F5F; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .lut_mask = 16'h2F00; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~53_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_flags_oe~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~53 .lut_mask = 16'h050D; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .lut_mask = 16'hECFC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal25~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~54 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~54_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~54 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~27_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ), - .datac(\z80_|execute_|ctl_mRead~27_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~20_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~20 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # (((\z80_|execute_|ctl_ir_we~15_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo~24_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout = (\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & ((\z80_|execute_|rsel0~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// (((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|rsel0~combout )) # (!\z80_|execute_|setM1~48_combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|execute_|rsel0~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .lut_mask = 16'hCD05; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~47 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) # (!\z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .datac(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = (\z80_|pla_decode_|Equal40~1_combout & (((\z80_|execute_|ixy_d~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal40~1_combout & (\z80_|pla_decode_|Equal39~0_combout & -// ((\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFAC0; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0A00; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hA8A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout )) # (!\z80_|execute_|ctl_alu_op_low~21_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ixy_d~4_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|execute_|ctl_mRead~38_combout )))) # (!\z80_|execute_|ixy_d~4_combout & (((\z80_|execute_|ctl_eval_cond~0_combout & -// \z80_|execute_|ctl_mRead~38_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFC88; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h55F7; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~23_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal44~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_state_alu~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel~5_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hFF0F; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~17_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~17_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~39_combout = (((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~18_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'h7F77; -defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op_low~39_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout & ((\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'hF0E0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal56~0_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~38_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~38_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h0777; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~10_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h0155; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hEEEC; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_flags_cf_cpl~2_combout & ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hEF00; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mWrite~2_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout & -// (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (!\z80_|execute_|ctl_flags_cf_cpl~3_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h0200; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_alu_op_low~30_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC800; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = ((\z80_|execute_|ctl_reg_gp_sel~5_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal72~2_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~11_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal72~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|pla_decode_|Equal61~2_combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal61~2_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~11_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal21~0_combout ) # ((\z80_|pla_decode_|Equal3~0_combout )))) # (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_eval_cond~0_combout & -// ((\z80_|pla_decode_|Equal21~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .lut_mask = 16'hFAC8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout -// ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .lut_mask = 16'hFFF8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (\z80_|execute_|ctl_alu_op_low~36_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~36_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'h4000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (!\z80_|pla_decode_|Equal72~2_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal72~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & \z80_|execute_|ctl_flags_nf_we~1_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~38_combout = (\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'h8880; -defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|execute_|ctl_alu_op_low~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~38_combout ) # (\z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_alu_op_low~32_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|pla_decode_|Equal64~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h00C4; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|pla_decode_|Equal20~0_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (\z80_|execute_|ctl_flags_use_cf2~9_combout ))) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|execute_|ctl_flags_bus~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hBAFA; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_mRead~38_combout & \z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|pc_inc_hold~31_combout ), .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Location: LCCOMB_X37_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = (((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (\z80_|execute_|ctl_flags_cf_we~5_combout )) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (((\z80_|ir_|opcode [3]) # (!\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'hF700; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|execute_|ctl_alu_core_R~2_combout ) # ((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|execute_|ctl_alu_op_low~25_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # (((\z80_|execute_|ctl_alu_op_low~33_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout )) # (!\z80_|execute_|ctl_alu_op_low~39_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~34_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hCC40; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hA0A8; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h54F0; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~18_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h5C4C; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~19_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h5F08; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_mWrite~2_combout ) # (\z80_|execute_|ctl_alu_shift_oe~20_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~20_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h5F40; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~21_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout -// & ((\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hEEC0; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_ir_we~7_combout )))) # (!\z80_|execute_|ctl_bus_db_oe~7_combout & ((\z80_|execute_|ixy_d~7_combout ) -// # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'hDC50; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_alu_shift_oe~24_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~44_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ) # (\z80_|execute_|ctl_alu_shift_oe~16_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0F0E; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~23_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF45; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hC4C0; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) +// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|pc_inc_hold~34_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_sw_4u~0_combout )))) .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|pc_inc_hold~34_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0C08; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Location: LCCOMB_X37_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( // Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~22_combout ) # (\z80_|execute_|ctl_mRead~28_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) +// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_inc_cy~64_combout ), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hFFC4; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_inc_cy~68_combout ) # ((\z80_|execute_|ctl_inc_cy~65_combout ) # ((!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|ctl_inc_cy~90_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~42_combout ), + .datab(\z80_|execute_|ctl_inc_cy~90_combout ), + .datac(\z80_|execute_|ctl_inc_cy~68_combout ), + .datad(\z80_|execute_|ctl_inc_cy~65_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~49_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_inc_cy~92_combout ) .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|execute_|ctl_mRead~28_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_inc_cy~92_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Location: LCCOMB_X35_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( // Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) +// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ixy_d~9_combout & +// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h5F40; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_flags_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~22_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~42_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hB0A0; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( -// Equation(s): -// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .dataa(\z80_|execute_|ixy_d~9_combout ), .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Location: LCCOMB_X36_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~2_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~10_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_ir_we~10_combout ))) +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_inc_cy~94_combout )) - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|execute_|ctl_inc_cy~94_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Location: LCCOMB_X35_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) +// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|pla_decode_|Equal11~0_combout ))) - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~51_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Location: LCCOMB_X36_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( // Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_mWrite~3_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) +// \z80_|execute_|ctl_inc_cy~36_combout = ((!\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .combout(\z80_|execute_|ctl_inc_cy~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_alu_res_oe~1_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( -// Equation(s): -// \z80_|alu_|db_high[3]~1_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # ((\z80_|alu_|db_high[3]~0_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~0_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFEFF; -defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~2 ( -// Equation(s): -// \z80_|alu_|db_low[3]~2_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [3]), - .datac(\z80_|alu_|op2_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~2 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db_low[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hC0C0; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N26 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~3 ( -// Equation(s): -// \z80_|alu_|db_low[3]~3_combout = (\z80_|alu_|db_low[3]~2_combout & (((!\z80_|bus_control_|db[5]~17_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|alu_|db_low[3]~2_combout ), - .datab(\z80_|bus_control_|db[5]~17_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~3 .lut_mask = 16'h2A0A; -defparam \z80_|alu_|db_low[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y16_N13 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( -// Equation(s): -// \z80_|alu_|db_low[3]~4_combout = (\z80_|alu_|db_low[3]~3_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|alu_|db_low[3]~3_combout ), - .datab(\z80_|alu_|result_lo [3]), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hAA88; -defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (((\z80_|alu_|db_low[3]~1_combout & \z80_|alu_|db_low[3]~4_combout )) # (!\z80_|alu_|db_high[3]~1_combout ))) - - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .lut_mask = 16'hB030; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|alu_|db_high[3]~19_combout ), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .lut_mask = 16'h00F8; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_low~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N29 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[3]~3_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|alu_|alu_op2[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFCD; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = ((!\z80_|execute_|ctl_alu_core_S~11_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h3FFF; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|pla_decode_|Equal62~2_combout & \z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFBBB; -defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ) # (\z80_|execute_|ctl_alu_core_S~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~25 ( -// Equation(s): -// \z80_|alu_|db_high[2]~25_combout = (\z80_|alu_|db_high[2]~24_combout ) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_high[3]~1_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|alu_|db_high[2]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~25 .lut_mask = 16'hFF55; -defparam \z80_|alu_|db_high[2]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [6] & ((\z80_|reg_file_|gdfx_temp1[6]~21_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[6]~21_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~0 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|db_hi_as[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~1_combout = (\z80_|reg_file_|db_hi_as[6]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[6]~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~1 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|db_hi_as[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N29 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [14]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [13]))))) - - .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~3_combout = ((\z80_|reg_file_|db_hi_as[6]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[6]~1_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~3 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_hi_as[6]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X36_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 ( +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( // Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) +// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~36_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_sw_2u~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~36_combout ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), + .combout(\z80_|execute_|ctl_inc_cy~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Location: LCCOMB_X35_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) +// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout ))) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_inc_cy~52_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~9 ( +// Location: LCCOMB_X39_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) +// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|ctl_mRead~17_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~9_combout ), + .combout(\z80_|execute_|ctl_inc_cy~41_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~9 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~9 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0045; +defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~10 ( +// Location: LCCOMB_X39_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) +// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout )) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~10 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~11_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~11 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~12_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[6]~22_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~12 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~14_combout = (\z80_|reg_file_|gdfx_temp1[6]~10_combout & (\z80_|reg_file_|gdfx_temp1[6]~11_combout & (\z80_|reg_file_|gdfx_temp1[6]~13_combout & \z80_|reg_file_|gdfx_temp1[6]~12_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~10_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~11_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~13_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~21_combout - - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), + .datad(\z80_|execute_|ctl_inc_cy~41_combout ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hEEFF; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~8 ( +// Location: LCCOMB_X35_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~8_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) +// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & +// ((\z80_|execute_|ctl_mRead~36_combout )))) - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~8_combout ), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~8 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[6]~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~15 ( +// Location: LCCOMB_X38_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~15_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout & (\z80_|reg_file_|gdfx_temp1[6]~9_combout & (\z80_|reg_file_|gdfx_temp1[6]~14_combout & \z80_|reg_file_|gdfx_temp1[6]~8_combout ))) +// \z80_|execute_|ctl_inc_cy~56_combout = (((!\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|fMRead~3_combout ) - .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~8_combout ), + .dataa(\z80_|execute_|fMRead~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~15_combout ), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~21 ( +// Location: LCCOMB_X39_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~21_combout = ((\z80_|reg_file_|gdfx_temp1[6]~15_combout & ((\z80_|reg_file_|db_hi_as[6]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) +// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - .dataa(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), + .combout(\z80_|execute_|ctl_inc_cy~89_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~21 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp1[6]~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hA020; +defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N24 -cycloneive_lcell_comb \z80_|interrupts_|im2~feeder ( +// Location: LCCOMB_X39_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( // Equation(s): -// \z80_|interrupts_|im2~feeder_combout = \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout +// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~56_combout ) # (\z80_|execute_|ctl_inc_cy~89_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ctl_inc_cy~55_combout ), + .datac(\z80_|execute_|ctl_inc_cy~56_combout ), + .datad(\z80_|execute_|ctl_inc_cy~89_combout ), .cin(gnd), - .combout(\z80_|interrupts_|im2~feeder_combout ), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|im2~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|im2~feeder .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y12_N25 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|im2~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Location: LCCOMB_X39_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( // Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) +// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~57_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~58_combout ) # (!\z80_|execute_|fMRead~5_combout )))) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_inc_cy~58_combout ), + .datac(\z80_|execute_|fMRead~5_combout ), + .datad(\z80_|execute_|ctl_inc_cy~57_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hFF8A; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Location: LCCOMB_X37_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( // Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|execute_|ctl_mRead~14_combout & (\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|pc_inc_hold~38_combout & (\z80_|execute_|pc_inc_hold~35_combout & (\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|pc_inc_hold~38_combout & (((\z80_|execute_|ctl_inc_cy~54_combout ) # +// (\z80_|execute_|ctl_inc_cy~59_combout )))) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|pc_inc_hold~35_combout ), + .datac(\z80_|execute_|ctl_inc_cy~54_combout ), + .datad(\z80_|execute_|ctl_inc_cy~59_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hD5D0; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N0 -cycloneive_lcell_comb \z80_|sw1_|db_down[6]~0 ( +// Location: LCCOMB_X35_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( // Equation(s): -// \z80_|sw1_|db_down[6]~0_combout = ((\z80_|bus_control_|db[6]~7_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) +// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|pc_inc_hold~50_combout ))) - .dataa(gnd), - .datab(\z80_|bus_control_|db[6]~7_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~50_combout ), .cin(gnd), - .combout(\z80_|sw1_|db_down[6]~0_combout ), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), .cout()); // synopsys translate_off -defparam \z80_|sw1_|db_down[6]~0 .lut_mask = 16'h0CFF; -defparam \z80_|sw1_|db_down[6]~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~10 ( +// Location: LCCOMB_X37_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( // Equation(s): -// \z80_|alu_|db_low[1]~10_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & !\z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~10 .lut_mask = 16'h3373; -defparam \z80_|alu_|db_low[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) +// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .combout(\z80_|execute_|ctl_inc_cy~88_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hAA08; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y17_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 ( +// Location: LCCOMB_X37_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( // Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout = (\z80_|alu_|db_low[1]~15_combout & \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) +// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_inc_cy~88_combout & ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~39_combout ), + .datab(\z80_|execute_|ctl_inc_cy~47_combout ), + .datac(\z80_|execute_|ctl_inc_cy~88_combout ), + .datad(\z80_|execute_|pc_inc_hold~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hECFC; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~40_combout = (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~34_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|pc_inc_hold~30_combout ), + .datac(\z80_|execute_|pc_inc_hold~34_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h3200; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|ctl_inc_cy~42_combout & ((\z80_|execute_|pc_inc_hold~40_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|pc_inc_hold~40_combout ), + .datac(\z80_|execute_|ctl_inc_cy~61_combout ), + .datad(\z80_|execute_|ctl_inc_cy~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hF0FD; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~48_combout ) # (\z80_|execute_|ctl_inc_cy~62_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), + .datab(\z80_|execute_|ctl_inc_cy~60_combout ), + .datac(\z80_|execute_|ctl_inc_cy~48_combout ), + .datad(\z80_|execute_|ctl_inc_cy~62_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~85_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~70_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), + .datab(\z80_|execute_|ctl_inc_cy~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~84_combout ), + .datad(\z80_|execute_|ctl_inc_cy~70_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (\z80_|execute_|ctl_inc_cy~85_combout ) .dataa(gnd), .datab(gnd), - .datac(\z80_|alu_|db_low[1]~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_cy~85_combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .lut_mask = 16'hF000; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( // Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .dataa(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFCF8; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hAF2F; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~12 ( +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( // Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~12_combout = (((!\z80_|execute_|nextM~11_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout )) # (!\z80_|execute_|ctl_reg_use_sp~0_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|ctl_mRead~38_combout -// & (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~13_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[1]~15_combout ) # ((\z80_|alu_|db_high[1]~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_high[1]~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(\z80_|alu_|db_high[1]~7_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|db_low[1]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) +// \z80_|address_latch_|abusz [0] = (\z80_|reg_file_|db_lo_as[0]~3_combout & !\z80_|resets_|clrpc~0_combout ) .dataa(gnd), - .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] + + .dataa(gnd), + .datab(gnd), .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|address_latch_|abusz [0]), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout ), + .combout(\z80_|address_latch_|Q[0]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1 .lut_mask = 16'h00CC; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # (\z80_|execute_|ctl_alu_op2_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N13 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[1]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[1]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00A0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N1 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~3 ( -// Equation(s): -// \z80_|alu_|db_high[1]~3_combout = (\z80_|alu_|op2_high [1] & (((\z80_|alu_|op1_high [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_high [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [1]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [1]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~3 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~2 ( -// Equation(s): -// \z80_|alu_|db_high[1]~2_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~2 .lut_mask = 16'h7333; -defparam \z80_|alu_|db_high[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N2 -cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( -// Equation(s): -// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_sw_2d~13_combout ) # ((\z80_|execute_|ctl_alu_oe~14_combout ) # (\z80_|execute_|ctl_reg_out_hi~7_combout )) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFEE; -defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( +// Location: FF_X31_Y16_N23 +dffeas \z80_|address_latch_|Q[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~70 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~72 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~71_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[5]~24_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~71 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~69 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~73_combout = (\z80_|reg_file_|gdfx_temp1[5]~70_combout & (\z80_|reg_file_|gdfx_temp1[5]~72_combout & (\z80_|reg_file_|gdfx_temp1[5]~71_combout & \z80_|reg_file_|gdfx_temp1[5]~69_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~70_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~72_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~71_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~69_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~67_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~67 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N27 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~16 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~68 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~74_combout = (\z80_|reg_file_|gdfx_temp1[5]~73_combout & (\z80_|reg_file_|gdfx_temp1[5]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout & \z80_|reg_file_|gdfx_temp1[5]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~75_combout = ((\z80_|reg_file_|gdfx_temp1[5]~74_combout & ((\z80_|reg_file_|db_hi_as[5]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~74_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~75 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp1[5]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N4 -cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( -// Equation(s): -// \z80_|alu_|db[5]~23_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[5]~29_combout & ((\z80_|reg_file_|gdfx_temp1[5]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// (((\z80_|reg_file_|gdfx_temp1[5]~75_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|alu_control_|db[5]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N6 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_high[1]~7_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db[5]~23_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_mWrite~2_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~24_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y11_N25 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [12]), + .d(\z80_|address_latch_|Q[0]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -24891,815 +20392,31 @@ dffeas \z80_|address_latch_|Q[12] ( .ena(\z80_|execute_|ctl_al_we~12_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), + .q(\z80_|address_latch_|Q [0]), .prn(vcc)); // synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [11] $ -// (\z80_|execute_|ctl_inc_dec~8_combout ))))) +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - .dataa(\z80_|address_latch_|Q [12]), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [4] & ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~22 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|db_hi_as[4]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~23_combout = (\z80_|reg_file_|db_hi_as[4]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~22_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~23 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[4]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~24_combout = ((\z80_|reg_file_|db_hi_as[4]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~24 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~17 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~77 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~76 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~79 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~78 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~80_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[4]~10_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[4]~10_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~80 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~81 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~82_combout = (\z80_|reg_file_|gdfx_temp1[4]~79_combout & (\z80_|reg_file_|gdfx_temp1[4]~78_combout & (\z80_|reg_file_|gdfx_temp1[4]~80_combout & \z80_|reg_file_|gdfx_temp1[4]~81_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~79_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~78_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~80_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~81_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~83_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout & (\z80_|reg_file_|gdfx_temp1[4]~77_combout & (\z80_|reg_file_|gdfx_temp1[4]~76_combout & \z80_|reg_file_|gdfx_temp1[4]~82_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~76_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~84_combout = ((\z80_|reg_file_|gdfx_temp1[4]~83_combout & ((\z80_|reg_file_|db_hi_as[4]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~83_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~84 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp1[4]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~2_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~19_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # (\z80_|execute_|ctl_sw_4u~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & \z80_|decode_state_|DFFE_inst4~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # (\z80_|execute_|ctl_inc_cy~80_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~70_combout ), - .datab(\z80_|execute_|ctl_inc_cy~67_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~81_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), - .datab(\z80_|address_latch_|Q [1]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h66CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N11 +// Location: FF_X31_Y17_N5 dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), @@ -25718,5802 +20435,7 @@ defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hFAD8; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N13 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_alu_op_low~32_combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~32_combout & (\z80_|alu_|op1_high [2])))) # -// (!\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|alu_|op1_low [2])))) - - .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hF0D8; -defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[1]~1_combout = (\z80_|execute_|ctl_alu_op_low~32_combout & (((\z80_|alu_|op1_low [1])))) # (!\z80_|execute_|ctl_alu_op_low~32_combout & ((\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|alu_|op1_high [1])) # -// (!\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|alu_|op1_low [1]))))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[1]~1 .lut_mask = 16'hE2F0; -defparam \z80_|alu_|alu_op1[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op2[1]~0_combout & \z80_|alu_|alu_op1[1]~1_combout )) - - .dataa(\z80_|alu_|alu_op2[1]~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~combout ), - .datac(gnd), - .datad(\z80_|alu_|alu_op1[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hEECC; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[1]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [1]))))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|alu_|alu_op2[1]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0027; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N8 -cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( -// Equation(s): -// \z80_|alu_|db[1]~15_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[1]~26_combout & ((\z80_|reg_file_|gdfx_temp1[1]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// (((\z80_|reg_file_|gdfx_temp1[1]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N10 -cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( -// Equation(s): -// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~15_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db[1]~15_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~48_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[0]~48_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~10 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~11_combout = (\z80_|reg_file_|db_hi_as[0]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~11 .lut_mask = 16'hB0B0; -defparam \z80_|reg_file_|db_hi_as[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0020; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[6]~15_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datad(\z80_|alu_control_|db[6]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|decode_state_|DFFE_inst4~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~75_combout & (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~78_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout & (\z80_|reg_file_|gdfx_temp0[6]~74_combout & \z80_|reg_file_|gdfx_temp0[6]~73_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (\z80_|reg_file_|db_lo_as[4]~15_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N11 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [4]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [4]) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h3C3C; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ -// (\z80_|execute_|ctl_inc_dec~8_combout ))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|Q [4]), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|Q [5]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'hD728; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X39_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~29_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[5]~29_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|alu_control_|db[5]~29_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~67_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~63_combout & (\z80_|reg_file_|gdfx_temp0[5]~64_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datac(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout = \z80_|reg_file_|db_lo_as[5]~18_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (\z80_|reg_file_|db_lo_as[5]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|address_latch_|Q[5]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[5]~feeder_combout = \z80_|address_latch_|abusz [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [5]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N9 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[5]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (\z80_|execute_|ctl_inc_dec~6_combout )) # (!\z80_|execute_|ctl_inc_dec~7_combout ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h5559; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N15 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~8_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & -// (\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_inc_dec~8_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2 .lut_mask = 16'h0BB0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[7]~18_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (\z80_|reg_file_|db_lo_as[7]~24_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[7]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[7]~feeder_combout = \z80_|address_latch_|abusz [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [7]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N5 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[7]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~12_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N31 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [7]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hD728; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~12_combout = ((\z80_|reg_file_|db_hi_as[0]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~11_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~12 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_hi_as[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~41 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~14 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~42 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~44_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[0]~18_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[0]~18_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~44 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[0]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~45 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[0]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~43_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~46_combout = (\z80_|reg_file_|gdfx_temp1[0]~42_combout & (\z80_|reg_file_|gdfx_temp1[0]~44_combout & (\z80_|reg_file_|gdfx_temp1[0]~45_combout & \z80_|reg_file_|gdfx_temp1[0]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~42_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~44_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~45_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~40 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[0]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~47_combout = (\z80_|reg_file_|gdfx_temp1[0]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout & (\z80_|reg_file_|gdfx_temp1[0]~46_combout & \z80_|reg_file_|gdfx_temp1[0]~40_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~41_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~46_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~48_combout = ((\z80_|reg_file_|gdfx_temp1[0]~47_combout & ((\z80_|reg_file_|db_hi_as[0]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~47_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~48 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp1[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N24 -cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( -// Equation(s): -// \z80_|alu_|db[0]~17_combout = (\z80_|alu_|db_low[0]~21_combout & (((\z80_|reg_file_|gdfx_temp1[0]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_|db_low[0]~21_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & -// ((\z80_|reg_file_|gdfx_temp1[0]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_|db_low[0]~21_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N22 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|alu_|db[0]~17_combout ), - .datac(\z80_|alu_control_|db[0]~12_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4FF; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N2 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [3] & ((\z80_|ir_|opcode [5] & ((\z80_|alu_|db[7]~20_combout ))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_|db[0]~18_combout )))) # (!\z80_|ir_|opcode [3] & -// (((\z80_|alu_|db[7]~20_combout & !\z80_|ir_|opcode [5])))) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hC0AC; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N4 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N20 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((!\z80_|ir_|opcode [4] & \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout )) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datac(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hF4F4; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~16 ( -// Equation(s): -// \z80_|alu_|db_low[0]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[1]~16_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~16 .lut_mask = 16'hF5A0; -defparam \z80_|alu_|db_low[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~17 ( -// Equation(s): -// \z80_|alu_|db_low[0]~17_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~16_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~18_combout )))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db_low[0]~16_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(\z80_|alu_|db[0]~18_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~17 .lut_mask = 16'hB8FF; -defparam \z80_|alu_|db_low[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( -// Equation(s): -// \z80_|alu_|db_low[0]~19_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [0] & ((\z80_|alu_|op1_low [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [0])) -// # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|alu_|op2_low [0]), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hF351; -defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # -// (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h57FF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~16_combout )))) # -// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~16_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & -// (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hEEC0; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # ((!\z80_|execute_|ctl_flags_alu~15_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & ((\z80_|execute_|ctl_flags_hf_we~2_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hB8AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y14_N23 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~14_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~11_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~11_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'h55F7; -defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & !\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal61~2_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFFA8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_control_|db[1]~26_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFFEC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|alu_|db_high[3]~19_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) - - .dataa(\z80_|alu_|db_high[3]~19_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFBF3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hB0F0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'h40C0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~16_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout )) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout & (\z80_|execute_|ctl_alu_core_hf~16_combout & \z80_|execute_|ctl_flags_nf_we~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal61~2_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~4_combout = ((\z80_|execute_|ctl_flags_nf_we~3_combout ) # ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_alu_core_hf~16_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hF000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N8 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (((!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0133; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout & (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'hB830; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X44_Y15_N29 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~9_combout = (\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_flags_hf_cpl~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (\z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_hf_cpl~10_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~8_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'h4404; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N0 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h0FB4; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_core_hf~16_combout & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~14_combout )) # (!\z80_|execute_|ctl_alu_core_hf~17_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (!\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|execute_|ctl_alu_core_hf~15_combout ) # ((!\z80_|execute_|ctl_alu_op_low~38_combout & \z80_|execute_|ctl_alu_core_hf~18_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'h3130; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hF400; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'hDCFC; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~20_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hFFF4; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout & (((!\z80_|execute_|ctl_alu_op_low~27_combout & \z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_op_low~34_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~23_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (\z80_|execute_|ctl_alu_core_hf~21_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h30BA; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_op_low~18_combout & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_alu_op_low~33_combout & ((\z80_|execute_|ctl_alu_core_hf~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~17_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_mWrite~2_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h8A88; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) # (!\z80_|execute_|ctl_mRead~8_combout & -// (\z80_|sequencer_|DFFE_M2_ff~q & ((!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (((\z80_|execute_|ctl_alu_op_low~17_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ixy_d~7_combout & -// (!\z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hF022; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (!\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout ))) # -// (!\z80_|pla_decode_|Equal56~0_combout & (\z80_|execute_|ctl_alu_core_hf~29_combout & \z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'h5440; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout & ((\z80_|execute_|ctl_alu_core_hf~31_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal10~0_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (!\z80_|execute_|ctl_alu_op_low~20_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~26_combout ) # (\z80_|execute_|ctl_alu_core_hf~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h0054; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout & !\z80_|execute_|ctl_alu_op_low~26_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ixy_d~5_combout ) # ((!\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ixy_d~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hF3F0; -defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~39_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~4_combout & \z80_|pla_decode_|Equal40~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hD0C0; -defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_alu_core_hf~24_combout ) # ((\z80_|execute_|ctl_alu_core_hf~33_combout ) # ((\z80_|execute_|ctl_alu_core_hf~40_combout & !\z80_|execute_|ctl_alu_op_low~30_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_core_hf~19_combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N30 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~35_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~35_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_flags_|flags_hf~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hCCAA; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~8 ( -// Equation(s): -// \z80_|alu_|db_high[0]~8_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~8 .lut_mask = 16'h3733; -defparam \z80_|alu_|db_high[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[0]~13_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00A0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N27 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~9 ( -// Equation(s): -// \z80_|alu_|db_high[0]~9_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [0] & ((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_high -// [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datab(\z80_|alu_|op2_high [0]), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op1_high [0]), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~9 .lut_mask = 16'hDD0D; -defparam \z80_|alu_|db_high[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~10 ( -// Equation(s): -// \z80_|alu_|db_high[0]~10_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~10 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_high[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~11 ( -// Equation(s): -// \z80_|alu_|db_high[0]~11_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~10_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~10_combout )) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~11 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_high[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~12 ( -// Equation(s): -// \z80_|alu_|db_high[0]~12_combout = (\z80_|alu_|db_high[0]~8_combout & (\z80_|alu_|db_high[0]~9_combout & ((\z80_|alu_|db_high[0]~11_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~8_combout ), - .datab(\z80_|alu_|db_high[0]~9_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[0]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~12 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~13 ( -// Equation(s): -// \z80_|alu_|db_high[0]~13_combout = ((\z80_|alu_|db_high[0]~12_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datab(\z80_|alu_|db_high[0]~12_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~13 .lut_mask = 16'hC8FF; -defparam \z80_|alu_|db_high[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[0]~13_combout ) # ((\z80_|alu_|db_low[0]~21_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((\z80_|alu_|db_low[0]~21_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_high[0]~13_combout ), - .datac(\z80_|alu_|db_low[0]~21_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N15 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_bus_inc_oe~44_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|pla_decode_|Equal61~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ) # (!\z80_|execute_|ctl_alu_op_low~39_combout -// ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # (((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # (((\z80_|execute_|ctl_alu_sel_op2_neg~12_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N20 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datab(\z80_|alu_|op2_low [0]), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~1 .lut_mask = 16'h1BE4; -defparam \z80_|alu_|alu_op2[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~0_combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op2[0]~1_combout -// )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & (\z80_|alu_|alu_op1[0]~0_combout & (\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op2[0]~1_combout ))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datab(\z80_|alu_|alu_op1[0]~0_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op2[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hEAA8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N17 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( -// Equation(s): -// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & !\z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h3337; -defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( -// Equation(s): -// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~19_combout & (\z80_|alu_|db_low[0]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|db_low[0]~19_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|alu_|db_low[0]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'hC800; -defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = ((\z80_|alu_|db_low[0]~17_combout & \z80_|alu_|db_low[0]~20_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(gnd), - .datab(\z80_|alu_|db_low[0]~17_combout ), - .datac(\z80_|alu_|db_low[0]~20_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hC0FF; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[0]~13_combout ) # ((\z80_|alu_|db_low[0]~21_combout & \z80_|execute_|ctl_alu_op1_sel_bus~14_combout )))) # -// (!\z80_|execute_|ctl_alu_op1_sel_low~combout & (\z80_|alu_|db_low[0]~21_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|alu_|db_low[0]~21_combout ), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N11 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|alu_|op1_high [0]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~0 .lut_mask = 16'hF3C0; -defparam \z80_|alu_|alu_op1[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_low[0]~21_combout ) # ((\z80_|alu_|alu_op1[0]~0_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|alu_|alu_op1[0]~0_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|alu_op1[0]~0_combout ), - .datac(\z80_|alu_|db_low[0]~21_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(gnd), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0C0C; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N29 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(gnd), - .datab(\z80_|alu_|op2_low [0]), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~0_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & !\z80_|execute_|ctl_alu_core_S~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hCCCF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # -// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h2223; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & \z80_|alu_|alu_op2[2]~2_combout )) - - .dataa(\z80_|alu_|alu_op1[2]~2_combout ), - .datab(gnd), - .datac(\z80_|alu_|alu_op2[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFA0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h33BF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op1[2]~2_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op2[2]~2_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op1[2]~2_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[2]~2_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[2]~2_combout ), - .datab(\z80_|alu_|alu_op2[2]~2_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hFE80; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y16_N11 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h3030; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N26 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~7 ( -// Equation(s): -// \z80_|alu_|db_low[2]~7_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|op2_low [2]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~7 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db_low[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~8 ( -// Equation(s): -// \z80_|alu_|db_low[2]~8_combout = (\z80_|alu_|db_low[2]~7_combout & (((!\z80_|bus_control_|db[5]~17_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~17_combout ), - .datab(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_low[2]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~8 .lut_mask = 16'h4F00; -defparam \z80_|alu_|db_low[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~59 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~62_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[2]~12_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[2]~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~62 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~63 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~61_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~61 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~60 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~64_combout = (\z80_|reg_file_|gdfx_temp1[2]~62_combout & (\z80_|reg_file_|gdfx_temp1[2]~63_combout & (\z80_|reg_file_|gdfx_temp1[2]~61_combout & \z80_|reg_file_|gdfx_temp1[2]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~62_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~63_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~61_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~15 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~58_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~58 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~65_combout = (\z80_|reg_file_|gdfx_temp1[2]~59_combout & (\z80_|reg_file_|gdfx_temp1[2]~64_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout & \z80_|reg_file_|gdfx_temp1[2]~58_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~59_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~64_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~58_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~66_combout = ((\z80_|reg_file_|gdfx_temp1[2]~65_combout & ((\z80_|reg_file_|db_hi_as[2]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~65_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~66 .lut_mask = 16'hDD5D; -defparam \z80_|reg_file_|gdfx_temp1[2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( -// Equation(s): -// \z80_|alu_|db[2]~11_combout = (\z80_|alu_control_|db[2]~22_combout & ((\z80_|reg_file_|gdfx_temp1[2]~66_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[2]~22_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[2]~66_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[2]~22_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~11 .lut_mask = 16'h8ACF; -defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N14 -cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( -// Equation(s): -// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~22_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[2]~11_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db_low[2]~22_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( -// Equation(s): -// \z80_|alu_|db_low[2]~5_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( -// Equation(s): -// \z80_|alu_|db_low[2]~6_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~5_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~12_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_|db_low[2]~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'hCAFF; -defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N2 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( -// Equation(s): -// \z80_|alu_|db_low[2]~9_combout = (\z80_|alu_|db_low[2]~8_combout & (\z80_|alu_|db_low[2]~6_combout & ((\z80_|alu_|result_lo [2]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|result_lo [2]), - .datab(\z80_|alu_|db_low[2]~8_combout ), - .datac(\z80_|alu_|db_low[2]~6_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hC080; -defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~22 ( -// Equation(s): -// \z80_|alu_|db_low[2]~22_combout = (\z80_|alu_|db_low[2]~9_combout ) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_low[2]~9_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~22 .lut_mask = 16'hF3F3; -defparam \z80_|alu_|db_low[2]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & ((\z80_|alu_|db_low[2]~22_combout ) # ((\z80_|alu_|db_high[2]~25_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[2]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(\z80_|alu_|db_high[2]~25_combout ), - .datac(\z80_|alu_|db_low[2]~22_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N19 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N24 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hFC00; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~19 ( -// Equation(s): -// \z80_|alu_control_|db[2]~19_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|alu_flags_|flags_hf2~q ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_66_oe~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~19 .lut_mask = 16'hFFEF; -defparam \z80_|alu_control_|db[2]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~8_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~23 ( -// Equation(s): -// \z80_|alu_control_|db[1]~23_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|alu_|db[1]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_oe~2_combout ) # -// ((!\z80_|alu_|db[1]~16_combout & \z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~23 .lut_mask = 16'h7350; -defparam \z80_|alu_control_|db[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( -// Equation(s): -// \z80_|alu_control_|db[1]~24_combout = (\z80_|alu_control_|db[2]~19_combout & (!\z80_|alu_control_|db[1]~23_combout & ((\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|db[2]~19_combout ), - .datac(\z80_|alu_control_|db[1]~23_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0C04; -defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|alu_control_|db[1]~24_combout & (((\z80_|bus_control_|db[1]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[1]~13_combout ), - .datab(\z80_|alu_control_|db[1]~24_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h08CC; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = (\z80_|alu_control_|db[1]~25_combout ) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_control_|db[1]~25_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'hF0FF; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[1]~26_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .datad(\z80_|alu_control_|db[1]~26_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~29_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~25_combout & \z80_|reg_file_|gdfx_temp0[1]~28_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N3 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N29 +// Location: FF_X31_Y13_N23 dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -31532,101 +20454,101 @@ defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N28 +// Location: LCCOMB_X31_Y13_N22 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[1]~32_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hA2F3; defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N12 +// Location: LCCOMB_X31_Y17_N26 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( // Equation(s): // \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hAF00; +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF300; defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N10 +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~85_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_cy~85_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h6A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N4 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .dataa(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hAF2F; defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N2 +// Location: LCCOMB_X30_Y17_N14 cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( // Equation(s): -// \z80_|address_latch_|abusz [1] = (\z80_|reg_file_|db_lo_as[1]~6_combout & !\z80_|resets_|clrpc~0_combout ) +// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - .dataa(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), .cin(gnd), .combout(\z80_|address_latch_|abusz [1]), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h00AA; +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h3300; defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[1]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[1]~feeder_combout = \z80_|address_latch_|abusz [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N23 +// Location: FF_X30_Y17_N19 dffeas \z80_|address_latch_|Q[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[1]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [1]), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|execute_|ctl_al_we~12_combout ), .devclrn(devclrn), .devpor(devpor), @@ -31637,30 +20559,13 @@ defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; defparam \z80_|address_latch_|Q[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hFF0F; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 +// Location: LCCOMB_X30_Y17_N6 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ))) +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), .datac(\z80_|address_latch_|Q [1]), .datad(\z80_|execute_|ctl_inc_dec~10_combout ), .cin(gnd), @@ -31671,493 +20576,16 @@ defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .lut_mask = defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[2]~22_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|alu_control_|db[2]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~35_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~37_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[2]~42_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 +// Location: LCCOMB_X29_Y17_N22 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & -// \z80_|execute_|ctl_inc_cy~81_combout )))) +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|execute_|ctl_inc_cy~85_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datab(\z80_|execute_|ctl_inc_cy~85_combout ), .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|execute_|ctl_inc_cy~81_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), .cout()); @@ -32166,44 +20594,61 @@ defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N4 +// Location: LCCOMB_X31_Y17_N16 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - .dataa(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'h8FAF; +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hF575; defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N16 +// Location: LCCOMB_X29_Y17_N12 cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( // Equation(s): -// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) +// \z80_|address_latch_|abusz [2] = (\z80_|reg_file_|db_lo_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - .dataa(gnd), + .dataa(\z80_|reg_file_|db_lo_as[2]~9_combout ), .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), .cin(gnd), .combout(\z80_|address_latch_|abusz [2]), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h00AA; defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N17 +// Location: LCCOMB_X29_Y17_N14 +cycloneive_lcell_comb \z80_|address_latch_|Q[2]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[2]~feeder_combout = \z80_|address_latch_|abusz [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [2]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N15 dffeas \z80_|address_latch_|Q[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [2]), + .d(\z80_|address_latch_|Q[2]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -32219,2641 +20664,112 @@ defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; defparam \z80_|address_latch_|Q[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y10_N28 +// Location: LCCOMB_X30_Y17_N2 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ))) +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|address_latch_|Q [2]), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h0F87; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h40BF; defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Location: LCCOMB_X35_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( // Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) +// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ctl_inc_cy~80_combout ), + .datad(\z80_|execute_|ctl_inc_cy~83_combout ), .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), + .combout(\z80_|execute_|ctl_inc_cy~86_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N13 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [3]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [4]) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(gnd), - .datac(\z80_|address_latch_|Q [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hAF00; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hDD00; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X39_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~59_combout & (\z80_|reg_file_|gdfx_temp0[4]~58_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .datab(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .datac(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h80A0; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & (\z80_|reg_file_|gdfx_temp0[4]~56_combout & \z80_|reg_file_|gdfx_temp0[4]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( -// Equation(s): -// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~10_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~10_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; -defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (!\z80_|alu_control_|db[4]~30_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_control_|db[4]~30_combout ), - .datab(\z80_|alu_flags_|flags_hf~combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h4500; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|alu_control_|db[4]~31_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hC4FF; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( -// Equation(s): -// \z80_|alu_|db[4]~8_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[4]~32_combout & ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .datac(\z80_|alu_control_|db[4]~32_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~8 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N16 -cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( -// Equation(s): -// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[4]~8_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~4 ( -// Equation(s): -// \z80_|alu_|db_high[1]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~22_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~10_combout )) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~4 .lut_mask = 16'hCACA; -defparam \z80_|alu_|db_high[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~5 ( -// Equation(s): -// \z80_|alu_|db_high[1]~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[1]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~5 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_high[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~6 ( -// Equation(s): -// \z80_|alu_|db_high[1]~6_combout = (\z80_|alu_|db_high[1]~3_combout & (\z80_|alu_|db_high[1]~2_combout & ((\z80_|alu_|db_high[1]~5_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~3_combout ), - .datab(\z80_|alu_|db_high[1]~2_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[1]~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~6 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~7 ( -// Equation(s): -// \z80_|alu_|db_high[1]~7_combout = ((\z80_|alu_|db_high[1]~6_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_high[3]~1_combout ), - .datab(\z80_|alu_|db_high[1]~6_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~7 .lut_mask = 16'hDDD5; -defparam \z80_|alu_|db_high[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), - .datac(\z80_|alu_|db_high[1]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'h00EC; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N9 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hC480; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~15_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) - - .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datab(\z80_|alu_|db_low[1]~15_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N11 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|alu_|op2_high [1]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~0 .lut_mask = 16'h3C5A; -defparam \z80_|alu_|alu_op2[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h7773; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & -// \z80_|alu_|alu_op1[1]~1_combout )))) # (!\z80_|alu_|alu_op2[1]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~1_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[1]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .datad(\z80_|alu_|alu_op1[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hF2B0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y16_N29 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~11 ( -// Equation(s): -// \z80_|alu_|db_low[1]~11_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [1] & ((\z80_|alu_|op2_low [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op2_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~11 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db_low[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( -// Equation(s): -// \z80_|alu_|db_low[1]~12_combout = (\z80_|alu_|db_low[1]~10_combout & (\z80_|alu_|db_low[1]~11_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~10_combout ), - .datab(\z80_|alu_|result_lo [1]), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_low[1]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( -// Equation(s): -// \z80_|alu_|db_low[1]~13_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_|db[0]~18_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hAACC; -defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( -// Equation(s): -// \z80_|alu_|db_low[1]~14_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~13_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~16_combout )) - - .dataa(\z80_|alu_|db[1]~16_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_low[1]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = ((\z80_|alu_|db_low[1]~12_combout & ((\z80_|alu_|db_low[1]~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_low[1]~12_combout ), - .datab(\z80_|alu_|db_low[1]~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'h8AFF; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (\z80_|alu_|db_high[3]~1_combout & (!\z80_|alu_|db_low[2]~9_combout & ((!\z80_|alu_|db_low[3]~4_combout ) # (!\z80_|alu_|db_low[3]~1_combout )))) - - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_low[2]~9_combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~15_combout & (\z80_|execute_|ctl_flags_alu~16_combout & (!\z80_|alu_|db_low[0]~21_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(\z80_|execute_|ctl_flags_alu~16_combout ), - .datac(\z80_|alu_|db_low[0]~21_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[0]~13_combout & !\z80_|alu_|db_high[1]~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|alu_|db_high[1]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h000F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & (!\z80_|alu_|db_high[2]~25_combout & !\z80_|alu_|db_high[3]~19_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .datac(\z80_|alu_|db_high[2]~25_combout ), - .datad(\z80_|alu_|db_high[3]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .lut_mask = 16'h0008; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal13~0_combout ) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hDFFF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[6]~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[6]~15_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hF800; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y15_N13 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N2 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_control_|out[6]~0_combout & \z80_|alu_|op1_high [0]))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|alu_|op1_high [0]), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFFEA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N14 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) - - .dataa(\z80_|alu_control_|out[6]~1_combout ), - .datab(\z80_|execute_|ctl_66_oe~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|alu_|op1_high [3]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~13 ( -// Equation(s): -// \z80_|alu_control_|db[6]~13_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|out[6]~2_combout ) # (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) # -// (!\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|alu_control_|out[6]~2_combout ) # (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~13 .lut_mask = 16'hDDD0; -defparam \z80_|alu_control_|db[6]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~14 ( -// Equation(s): -// \z80_|alu_control_|db[6]~14_combout = (\z80_|alu_control_|db[6]~13_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(\z80_|alu_control_|db[6]~13_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~14 .lut_mask = 16'h88AA; -defparam \z80_|alu_control_|db[6]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_reg_out_lo~2_combout ))) - - .dataa(\z80_|execute_|rsel3~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFFC8; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hF4F0; -defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~15 ( -// Equation(s): -// \z80_|alu_control_|db[6]~15_combout = ((\z80_|sw1_|db_down[6]~0_combout & (\z80_|alu_control_|db[6]~14_combout & \z80_|reg_file_|db_lo_ds[6]~0_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|sw1_|db_down[6]~0_combout ), - .datab(\z80_|alu_control_|db[6]~14_combout ), - .datac(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~15 .lut_mask = 16'h80FF; -defparam \z80_|alu_control_|db[6]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N20 -cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( -// Equation(s): -// \z80_|alu_|db[6]~21_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[6]~15_combout & ((\z80_|reg_file_|gdfx_temp1[6]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// (((\z80_|reg_file_|gdfx_temp1[6]~21_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .datad(\z80_|alu_control_|db[6]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N26 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_high[2]~25_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[6]~21_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~20 ( -// Equation(s): -// \z80_|alu_|db_high[2]~20_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~20_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|alu_|db[7]~20_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~20 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_high[2]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~21 ( -// Equation(s): -// \z80_|alu_|db_high[2]~21_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~20_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[2]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~21 .lut_mask = 16'hFD5D; -defparam \z80_|alu_|db_high[2]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[2]~9_combout ) # (!\z80_|alu_|db_high[3]~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(gnd), - .datac(\z80_|alu_|db_low[2]~9_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6 .lut_mask = 16'hA0AA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ) # ((\z80_|alu_|db_high[2]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|db_high[2]~25_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7 .lut_mask = 16'h5540; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N21 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~22 ( -// Equation(s): -// \z80_|alu_|db_high[2]~22_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [2] & ((\z80_|alu_|op1_high [2]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high -// [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~22 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db_high[2]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~23 ( -// Equation(s): -// \z80_|alu_|db_high[2]~23_combout = (\z80_|alu_|db_high[2]~22_combout & (((\z80_|bus_control_|db[5]~17_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~17_combout ), - .datab(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_high[2]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~23 .lut_mask = 16'h8F00; -defparam \z80_|alu_|db_high[2]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~24 ( -// Equation(s): -// \z80_|alu_|db_high[2]~24_combout = (\z80_|alu_|db_high[2]~21_combout & (\z80_|alu_|db_high[2]~23_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_high[2]~21_combout ), - .datab(\z80_|alu_|db_high[2]~23_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~24 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_high[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|db_high[2]~24_combout ) # (!\z80_|alu_|db_high[3]~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(\z80_|alu_|db_high[2]~24_combout ), - .datac(\z80_|alu_|db_high[3]~1_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h008A; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N7 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'hE400; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_low[2]~22_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) - - .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .datab(\z80_|alu_|db_low[2]~22_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N7 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [2]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [2])))) - - .dataa(\z80_|alu_|op2_low [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~2 .lut_mask = 16'h3C66; -defparam \z80_|alu_|alu_op2[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [2]))))) - - .dataa(\z80_|alu_|alu_op2[2]~2_combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [2]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1015; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hCCEF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hCFCE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~12_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout -// & ((\z80_|execute_|ctl_flags_alu~16_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~12_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_flags_alu~16_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hF444; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~0_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~0 .lut_mask = 16'h2202; -defparam \z80_|execute_|ctl_flags_cf2_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~1_combout = (((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_we~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_we~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~1 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_flags_cf2_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~1_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0D8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y14_N23 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|alu_|db[0]~18_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hE4E4; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # -// (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & -// ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h4472; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout $ ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout & \z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y14_N1 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hFE10; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = (\z80_|execute_|ctl_state_alu~11_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'h8500; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|pla_decode_|Equal10~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'hCECC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_alu_op_low~37_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~27_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'hFFD5; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) # ((\z80_|execute_|ctl_alu_op_low~32_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'hFFEA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~18_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'h7775; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|pla_decode_|Equal9~0_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & -// (((\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFCB8; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hFF20; -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~11_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~11 .lut_mask = 16'hF0F8; -defparam \z80_|execute_|ctl_flags_cf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~11_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_alu_op_low~33_combout & \z80_|execute_|ctl_alu_op_low~18_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~11_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout & \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N14 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~10_combout ))))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0A28; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( -// Equation(s): -// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~15_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|bus_control_|db[0]~15_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h5D00; -defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N28 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|db[0]~18_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hF0FF; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( -// Equation(s): -// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~8_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'hA200; -defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( -// Equation(s): -// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_control_|db[0]~9_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'h8CFF; -defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[0]~12_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .datad(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hC040; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~13_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .datab(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y11_N29 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [0]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~7_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 +// Location: LCCOMB_X29_Y17_N0 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # -// (\z80_|execute_|ctl_inc_cy~80_combout )))) +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~86_combout ) # +// (\z80_|execute_|ctl_inc_cy~70_combout )))) - .dataa(\z80_|execute_|ctl_inc_cy~70_combout ), - .datab(\z80_|execute_|ctl_inc_cy~67_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datab(\z80_|execute_|ctl_inc_cy~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~86_combout ), + .datad(\z80_|execute_|ctl_inc_cy~70_combout ), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hFE00; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hAAA8; defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y10_N16 +// Location: LCCOMB_X30_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|execute_|ctl_inc_cy~85_combout & ((\z80_|address_latch_|Q [1] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q [0])) # (!\z80_|address_latch_|Q +// [1] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [0])))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_cy~85_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'h2400; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N10 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout +// ))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), + .dataa(gnd), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), .datad(\z80_|address_latch_|Q [3]), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h7F80; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h3FC0; defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N3 +// Location: FF_X28_Y10_N15 dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -34872,7 +20788,7 @@ defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y11_N21 +// Location: FF_X28_Y10_N21 dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -34891,7 +20807,7 @@ defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y11_N2 +// Location: LCCOMB_X28_Y10_N14 cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( // Equation(s): // \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # @@ -34909,15 +20825,32 @@ defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y12_N19 +// Location: LCCOMB_X29_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N27 dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -34928,7 +20861,7 @@ defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X38_Y12_N3 +// Location: FF_X30_Y11_N11 dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -34947,123 +20880,33 @@ defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N2 +// Location: LCCOMB_X30_Y11_N10 cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) +// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), .cin(gnd), .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hB0BB; defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[3]~35_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|alu_control_|db[3]~35_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N13 +// Location: FF_X30_Y10_N5 dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), .devclrn(devclrn), .devpor(devpor), @@ -35074,7 +20917,7 @@ defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X39_Y12_N29 +// Location: FF_X30_Y10_N11 dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -35093,345 +20936,3536 @@ defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y12_N28 +// Location: LCCOMB_X30_Y10_N10 cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) +// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), .cin(gnd), .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~47_combout & \z80_|reg_file_|gdfx_temp0[3]~49_combout ))) +// \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N6 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~2 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~2_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~2 .lut_mask = 16'hF8FC; -defparam \z80_|sw1_|db_down[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~2_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[3]~33_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datad(\z80_|sw1_|db_down[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hA200; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[3]~34_combout ), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hD5DD; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N18 -cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( -// Equation(s): -// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|alu_|db[3]~13_combout ), - .datac(\z80_|alu_control_|db[3]~35_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hC4FF; -defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~0 ( -// Equation(s): -// \z80_|alu_|db_low[3]~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) - - .dataa(\z80_|alu_|db[2]~12_combout ), + .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~0 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~1 ( -// Equation(s): -// \z80_|alu_|db_low[3]~1_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~14_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[3]~14_combout ), - .datab(\z80_|alu_|db_low[3]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~1 .lut_mask = 16'hCAFF; -defparam \z80_|alu_|db_low[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~23 ( -// Equation(s): -// \z80_|alu_|db_low[3]~23_combout = ((\z80_|alu_|db_low[3]~1_combout & \z80_|alu_|db_low[3]~4_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), .datac(gnd), - .datad(\z80_|alu_|db_low[3]~4_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .cin(gnd), - .combout(\z80_|alu_|db_low[3]~23_combout ), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|db_low[3]~23 .lut_mask = 16'hBB33; -defparam \z80_|alu_|db_low[3]~23 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))))) +// Location: FF_X29_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(\z80_|alu_|op1_low [3]), - .datac(\z80_|alu_|op1_high [3]), +// Location: FF_X30_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h3F3B; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~29_combout ) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|setM1~29_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_al_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hB3F3; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|execute_|setM1~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h5DDD; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # (!\z80_|execute_|ctl_reg_gp_we~2_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB3FF; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (\z80_|execute_|ctl_reg_in_hi~11_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~4_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|alu_|db[3]~11_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[3]~11_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[3]~11_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h4444; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|execute_|ctl_reg_gp_we~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5450; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~3_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hFB33; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (\z80_|execute_|ctl_reg_sys_we~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF3; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0002; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0008; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & (\z80_|reg_file_|gdfx_temp1[3]~45_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~40_combout & (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout & \z80_|reg_file_|gdfx_temp1[3]~46_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~13_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~13_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[1]~13_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout & (\z80_|reg_file_|gdfx_temp1[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'h8AAA; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h96CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~19_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~19_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[0]~19_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~24_combout & (\z80_|reg_file_|gdfx_temp1[0]~26_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & \z80_|reg_file_|gdfx_temp1[0]~27_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~6_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N9 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [7] & (\z80_|address_latch_|Q [8] & !\z80_|execute_|ctl_inc_dec~11_combout +// )) # (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [8] & \z80_|execute_|ctl_inc_dec~11_combout )))) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1800; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0C0C; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N5 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[9]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [9]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|alu_|db[2]~15_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[2]~15_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[2]~15_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N15 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~35_combout & (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~33_combout & \z80_|reg_file_|gdfx_temp1[2]~36_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~32_combout & (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .datab(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'h8FAF; +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hCC44; +defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (\z80_|reg_file_|db_hi_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|Q[10]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[10]~feeder_combout = \z80_|address_latch_|abusz [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [10]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N27 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[10]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [10] & (\z80_|address_latch_|Q [9] & +// !\z80_|execute_|ctl_inc_dec~11_combout )) # (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [9] & \z80_|execute_|ctl_inc_dec~11_combout )))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [9]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h1800; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N15 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [11]) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(gnd), + .datac(\z80_|address_latch_|Q [11]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|alu_|db_low[3]~11_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'h888A; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~8_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N7 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~3 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~3_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])) + + .dataa(gnd), + .datab(\z80_|alu_|op1_high [3]), + .datac(\z80_|alu_|op1_low [3]), .datad(\z80_|execute_|ctl_alu_op_low~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .combout(\z80_|alu_|alu_op1[3]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'h88A0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_|alu_op1[3]~3 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|alu_op1[3]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( +// Location: LCCOMB_X38_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( // Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|alu_|db_low[3]~23_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high +// [2])))) - .dataa(\z80_|alu_|db_low[3]~23_combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|alu_op2[2]~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h00EC; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0305; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y17_N5 -dffeas \z80_|alu_|op2_low[3] ( +// Location: LCCOMB_X39_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = ((\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mWrite~2_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAAFB; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # +// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[1]~17_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_high[1]~20_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'h5050; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N1 +dffeas \z80_|alu_|op2_high[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -35440,51 +24474,1928 @@ dffeas \z80_|alu_|op2_low[3] ( .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), + .q(\z80_|alu_|op2_high [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4 ( +// Location: LCCOMB_X36_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( // Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[3]~1_combout & \z80_|alu_|db_low[3]~4_combout )) # (!\z80_|alu_|db_high[3]~1_combout ))) +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~20_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[1]~20_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4 .lut_mask = 16'hB030; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ) # ((\z80_|alu_|db_high[3]~19_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) +// Location: FF_X36_Y10_N23 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ), - .datab(\z80_|alu_|db_high[3]~19_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), +// Location: LCCOMB_X37_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'h8C80; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N21 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~20_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal68~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # ((\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|execute_|ctl_state_alu~8_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~9_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~12_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h7577; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal61~2_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hFC00; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~20_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~21_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout & (((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout +// ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .lut_mask = 16'hC4CC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~12_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_alu_core_hf~20_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & !\z80_|pla_decode_|Equal71~2_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|pla_decode_|Equal71~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|pla_decode_|Equal21~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal3~0_combout & +// ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'hFCA8; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal13~1_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & \z80_|pla_decode_|Equal63~0_combout +// ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hFFEC; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|execute_|ctl_alu_op_low~31_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal72~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (!\z80_|pla_decode_|Equal72~2_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datab(\z80_|pla_decode_|Equal72~2_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout )) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFAFF; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_flags_sz_we~5_combout & \z80_|execute_|ctl_alu_core_R~0_combout )))) # +// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~4_combout = (((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (\z80_|execute_|ctl_flags_sz_we~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'h5000; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( +// Equation(s): +// \z80_|execute_|setM1~16_combout = (\z80_|execute_|setM1~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~31_combout ))) + + .dataa(\z80_|execute_|setM1~15_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0200; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|setM1~16_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|execute_|setM1~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_alu_oe~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (\z80_|execute_|ctl_flags_xy_we~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal11~1_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal11~1_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBAA; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; +defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~8_combout = ((\z80_|execute_|ctl_flags_alu~7_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~8_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_flags_alu~6_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_alu~7_combout ), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0070; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_xy_we~16_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datac(\z80_|execute_|ctl_sw_2d~4_combout ), + .datad(\z80_|execute_|ctl_flags_alu~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_flags_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|execute_|ctl_flags_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = ((\z80_|execute_|ctl_flags_alu~8_combout ) # ((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_alu~8_combout ), + .datac(\z80_|execute_|ctl_flags_alu~14_combout ), + .datad(\z80_|execute_|ctl_flags_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), + .datac(\z80_|alu_control_|db[1]~26_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEEE; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_high[3]~8_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFFB3; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h3070; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'h0800; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'hD850; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y9_N27 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|sequencer_|DFFE_M2_ff~q & +// (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'h7707; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = ((\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'hB3BB; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~15_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal13~2_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) + + .dataa(\z80_|alu_|op2_high [1]), + .datab(\z80_|alu_|op2_low [1]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h5A3C; +defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [1]))))) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(\z80_|alu_|op1_low [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = (((\z80_|pla_decode_|Equal71~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datad(\z80_|pla_decode_|Equal71~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|db_high[0]~26_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|alu_|db_high[0]~26_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) + + .dataa(\z80_|alu_|db_high[0]~26_combout ), + .datab(\z80_|alu_|db_low[0]~23_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout ), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .lut_mask = 16'h00F0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y17_N31 +// Location: FF_X37_Y10_N7 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|alu_|op2_high [0]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h3C5A; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & ((\z80_|ir_|opcode [3]) # ((!\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal62~2_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'hB0F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & \z80_|execute_|ctl_alu_core_S~7_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~9_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # +// (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h37FF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_alu_core_hf~20_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_core_hf~18_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hA0E0; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout & (((\z80_|execute_|ctl_alu_core_hf~19_combout & !\z80_|execute_|ctl_alu_op_low~29_combout )) # (!\z80_|execute_|ctl_alu_op_low~28_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~22_combout & (\z80_|execute_|ctl_alu_core_hf~19_combout & (!\z80_|execute_|ctl_alu_op_low~29_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0CAE; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hFF30; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hDFCC; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~20_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h22F2; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datab(\z80_|execute_|ctl_state_alu~13_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & !\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~7_combout & +// ((!\z80_|execute_|ctl_mWrite~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hC0CA; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~43_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~6_combout & (\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # +// ((\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~43 .lut_mask = 16'hD5C0; +defparam \z80_|execute_|ctl_alu_core_hf~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (!\z80_|execute_|ctl_alu_core_hf~43_combout & ((\z80_|execute_|ctl_alu_core_hf~32_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~32_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'h00E8; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~42_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~42 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_core_hf~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~42_combout & ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # (\z80_|execute_|ctl_alu_core_hf~33_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~41_combout = (!\z80_|execute_|ctl_state_alu~4_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal10~0_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~41 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_core_hf~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & +// (\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal11~1_combout & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal11~1_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~41_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~41_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .datad(\z80_|execute_|ctl_mWrite~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h0054; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~44_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~44 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & ((\z80_|execute_|ctl_alu_core_hf~44_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~44_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'h0E0A; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # ((!\z80_|execute_|ctl_alu_op_low~30_combout & \z80_|execute_|ctl_alu_core_hf~35_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~24_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFCFE; +defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~39_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = (\z80_|execute_|ctl_alu_core_R~2_combout ) # (((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[3]~11_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .lut_mask = 16'hC0D0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[3]~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), + .datad(\z80_|alu_|db_high[3]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .lut_mask = 16'h5450; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N9 dffeas \z80_|alu_|op2_high[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -35500,649 +26411,2610 @@ defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; defparam \z80_|alu_|op2_high[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y16_N20 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~3 ( +// Location: LCCOMB_X37_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 ( // Equation(s): -// \z80_|alu_|alu_op2[3]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) - - .dataa(\z80_|alu_|op2_low [3]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|op2_high [3]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~3 .lut_mask = 16'h3C66; -defparam \z80_|alu_|alu_op2[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~3_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [3])))) +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|alu_|alu_op2[3]~3_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), .datac(\z80_|execute_|ctl_alu_op_low~combout ), .datad(\z80_|alu_|op1_low [3]), .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), + .datac(\z80_|alu_|db_low[3]~25_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N19 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) + + .dataa(\z80_|alu_|op2_high [3]), + .datab(\z80_|alu_|op2_low [3]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h5A3C; +defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[3]~3_combout & \z80_|alu_|alu_op2[3]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) + + .dataa(\z80_|alu_|alu_op1[3]~3_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|alu_|alu_op2[3]~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high +// [3])))) + + .dataa(\z80_|alu_|alu_op2[3]~2_combout ), + .datab(\z80_|alu_|op1_high [3]), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0131; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0511; defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N24 +// Location: LCCOMB_X39_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hAFAE; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # +// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[4]~32_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|pla_decode_|Equal10~0_combout & +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hFC88; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~14_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~14_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N7 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ctl_state_alu~14_combout )) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|alu_flags_|DFFE_inst_latch_nf~q ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N8 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( +// Equation(s): +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h559A; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N30 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~40_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~40_combout & (\z80_|alu_flags_|flags_cf~combout )) + + .dataa(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(gnd), + .datad(\z80_|alu_flags_|flags_hf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hEE44; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~1_combout )))) +// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~1_combout )))) + + .dataa(\z80_|alu_|alu_op2[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~25_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|alu_|db[3]~11_combout ), + .datac(\z80_|alu_|db[5]~25_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hE4E4; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0C0C; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|Q[12]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[12]~feeder_combout = \z80_|address_latch_|abusz [12] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [12]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[12]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[12]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N15 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[12]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ +// (\z80_|address_latch_|Q [11]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .datad(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~12_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~17_combout )) # (!\z80_|execute_|ctl_reg_in_hi~12_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|alu_|db[4]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y11_N29 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & (\z80_|reg_file_|gdfx_temp1[4]~61_combout & \z80_|reg_file_|gdfx_temp1[4]~60_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|db[4]~16 ( +// Equation(s): +// \z80_|alu_|db[4]~16_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[4]~32_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[4]~32_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~16 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|db[7]~26 ( +// Equation(s): +// \z80_|alu_|db[7]~26_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_alu_oe~13_combout ), + .datac(\z80_|execute_|ctl_alu_oe~9_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~26 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|db[7]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( +// Equation(s): +// \z80_|alu_|db[4]~17_combout = ((\z80_|alu_|db[4]~16_combout & ((\z80_|alu_|db_high[0]~26_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[4]~16_combout ), + .datab(\z80_|alu_|db[7]~26_combout ), + .datac(\z80_|alu_|db_high[0]~26_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h00C8; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~6_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[0]~23_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[4]~17_combout ))) + + .dataa(\z80_|alu_|db_high[0]~23_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[4]~17_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hAAF0; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'h5575; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~26_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[0]~26_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N21 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op1_high [0] & (((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [0] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [0]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [0]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~22_combout & ((\z80_|alu_|db_high[0]~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[0]~24_combout ), + .datab(\z80_|alu_|db_high[0]~21_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'h8C00; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~26 ( +// Equation(s): +// \z80_|alu_|db_high[0]~26_combout = ((\z80_|alu_|db_high[0]~25_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~26 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) # +// (!\z80_|alu_|db_low[0]~23_combout & (((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) + + .dataa(\z80_|alu_|db_low[0]~23_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datad(\z80_|alu_|db_high[0]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h00F0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFEFE; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N31 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|alu_|op1_high [0]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) # +// (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_low[0]~23_combout )))) + + .dataa(\z80_|alu_|alu_op1[0]~1_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h5050; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N15 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(gnd), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0AA; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~9_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & +// \z80_|execute_|ctl_alu_core_S~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_low [1]), + .datac(gnd), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hDD88; +defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[1]~0_combout & \z80_|alu_|alu_op2[1]~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datac(\z80_|alu_|alu_op1[1]~0_combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFBBB; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # +// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F01; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( +// Equation(s): +// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(gnd), + .datad(\z80_|alu_|op1_low [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hEE22; +defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op2[2]~0_combout & \z80_|alu_|alu_op1[2]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|alu_|alu_op1[2]~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hFF0B; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N14 cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( // Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|execute_|ctl_alu_core_R~5_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ))) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op1[3]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & +// \z80_|alu_|alu_op2[3]~2_combout )))) # (!\z80_|alu_|alu_op1[3]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .dataa(\z80_|alu_|alu_op1[3]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|alu_|alu_op2[3]~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), .cin(gnd), .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'h152F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFB20; defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 ( +// Location: LCCOMB_X28_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder ( // Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout -// )) +// \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout .dataa(gnd), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .lut_mask = 16'hCCFC; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~14 ( -// Equation(s): -// \z80_|alu_|db_high[3]~14_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~14 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_high[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~15 ( -// Equation(s): -// \z80_|alu_|db_high[3]~15_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~14_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~20_combout )))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db_high[3]~14_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~15 .lut_mask = 16'hACFF; -defparam \z80_|alu_|db_high[3]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~16 ( -// Equation(s): -// \z80_|alu_|db_high[3]~16_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_high [3] & ((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high -// [3]) # ((!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op2_high [3]), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~16 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db_high[3]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~17 ( -// Equation(s): -// \z80_|alu_|db_high[3]~17_combout = (\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[5]~17_combout )) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~17 .lut_mask = 16'hC000; -defparam \z80_|alu_|db_high[3]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~18 ( -// Equation(s): -// \z80_|alu_|db_high[3]~18_combout = (\z80_|alu_|db_high[3]~15_combout & (\z80_|alu_|db_high[3]~16_combout & ((\z80_|alu_|db_high[3]~17_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) - - .dataa(\z80_|alu_|db_high[3]~15_combout ), - .datab(\z80_|alu_|db_high[3]~16_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_high[3]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~18 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[3]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~19 ( -// Equation(s): -// \z80_|alu_|db_high[3]~19_combout = ((\z80_|alu_|db_high[3]~18_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_high[3]~18_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~19 .lut_mask = 16'hF3B3; -defparam \z80_|alu_|db_high[3]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N30 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~19_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_high[3]~19_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( -// Equation(s): -// \z80_|alu_control_|db[7]~16_combout = (\z80_|alu_flags_|DFFE_inst_latch_sf~q & (!\z80_|alu_|db[7]~20_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q & ((\z80_|execute_|ctl_flags_oe~2_combout ) # -// ((!\z80_|alu_|db[7]~20_combout & \z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h7350; -defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[7]~1_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[7]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[7]~1 .lut_mask = 16'hFF40; -defparam \z80_|reg_file_|db_lo_ds[7]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( -// Equation(s): -// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~1_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~9_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datab(\z80_|reg_file_|db_lo_ds[7]~1_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h4C0C; -defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = ((!\z80_|alu_control_|db[7]~16_combout & (\z80_|alu_control_|db[7]~17_combout & \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[7]~16_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_control_|db[7]~17_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h7333; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|execute_|ctl_flags_alu~16_combout & \z80_|alu_|db_high[3]~19_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (\z80_|execute_|ctl_flags_alu~16_combout & ((\z80_|alu_|db_high[3]~19_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|execute_|ctl_flags_alu~16_combout ), - .datac(\z80_|alu_control_|db[7]~18_combout ), - .datad(\z80_|alu_|db_high[3]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hECA0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y15_N5 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( +// Location: FF_X28_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N18 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal40~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) +// Location: FF_X28_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), +// Location: LCCOMB_X28_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N28 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ) # ((\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|ir_|opcode [4] & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// !\z80_|alu_control_|sel[1]~0_combout )))) +// Location: FF_X27_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|alu_control_|sel[1]~0_combout ), +// Location: FF_X27_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hAAD8; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ))) +// Location: FF_X27_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), +// Location: FF_X28_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N10 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q ))) +// Location: FF_X28_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|alu_|alu_parity_out~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), +// Location: LCCOMB_X28_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|alu_|db[7]~21_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[7]~21_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[7]~21_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~69_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & (\z80_|reg_file_|gdfx_temp1[7]~72_combout & \z80_|reg_file_|gdfx_temp1[7]~71_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout & \z80_|reg_file_|gdfx_temp1[7]~68_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~75_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & +// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [13]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|alu_|db[5]~25_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[5]~25_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[5]~25_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~52_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N9 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~50_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), .datad(gnd), .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), + .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h5656; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X41_Y13_N11 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( // Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~11_combout ))) +// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), + .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout ) +// \z80_|address_latch_|abusz [13] = (\z80_|reg_file_|db_hi_as[5]~15_combout & !\z80_|resets_|clrpc~0_combout ) - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal62~3_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .combout(\z80_|address_latch_|abusz [13]), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'hFFFD; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0C0C; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|Q[13]~feeder ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h7000; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|alu_control_|DFFE_latch_pf_tmp~q ) # (\z80_|execute_|ctl_alu_op_low~combout ))))) - - .dataa(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|alu_parity_out~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h1E00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~38_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = ((\z80_|execute_|ctl_flags_pf_we~5_combout ) # ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_flags_xy_we~11_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & \z80_|execute_|ctl_flags_alu~16_combout ) +// \z80_|address_latch_|Q[13]~feeder_combout = \z80_|address_latch_|abusz [13] .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [13]), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .combout(\z80_|address_latch_|Q[13]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'hF000; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|Q[13]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[13]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~19_combout )) +// Location: FF_X28_Y16_N23 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[13]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ) + + .dataa(gnd), .datab(gnd), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|address_latch_|Q [13]), + .datad(\z80_|execute_|ctl_inc_dec~11_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'h000A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~11 ( +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~11_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout )) # (!\z80_|pla_decode_|Equal69~0_combout ))) +// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~21_combout & !\z80_|resets_|clrpc~0_combout ) - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout ), + .combout(\z80_|address_latch_|abusz [15]), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~11 .lut_mask = 16'h8A0A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~11 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [9] & (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & !\z80_|address_latch_|Q [8]))) - - .dataa(\z80_|address_latch_|Q [9]), - .datab(\z80_|address_latch_|Q [10]), - .datac(\z80_|address_latch_|Q [11]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [1] & (!\z80_|address_latch_|Q [2] & !\z80_|address_latch_|Q [3]))) - - .dataa(\z80_|address_latch_|Q [0]), - .datab(\z80_|address_latch_|Q [1]), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [7] & !\z80_|address_latch_|Q [5]))) - - .dataa(\z80_|address_latch_|Q [6]), - .datab(\z80_|address_latch_|Q [4]), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|Q [5]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N15 +// Location: FF_X28_Y16_N27 dffeas \z80_|address_latch_|Q[15] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_latch_|abusz [15]), @@ -36161,15 +29033,4509 @@ defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; defparam \z80_|address_latch_|Q[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N0 +// Location: LCCOMB_X28_Y16_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|execute_|ctl_inc_dec~11_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|alu_|db[6]~23_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[6]~23_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[6]~23_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & (\z80_|reg_file_|gdfx_temp1[6]~78_combout & \z80_|reg_file_|gdfx_temp1[6]~81_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~76_combout & (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .datab(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|Q[14]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[14]~feeder_combout = \z80_|address_latch_|abusz [14] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [14]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N5 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[14]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [14]), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3363; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( +// Equation(s): +// \z80_|alu_|db[7]~20_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .datad(\z80_|alu_control_|db[7]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db[7]~21 ( +// Equation(s): +// \z80_|alu_|db[7]~21_combout = ((\z80_|alu_|db[7]~20_combout & ((\z80_|alu_|db_high[3]~8_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|alu_|db[7]~26_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~21 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[7]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N22 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~21_combout & ((\z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & +// (\z80_|alu_|db[7]~21_combout )))) + + .dataa(\z80_|alu_|db[7]~21_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_|db[0]~19_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB822; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|alu_control_|db[0]~12_combout & (\z80_|execute_|ctl_flags_bus~combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & +// ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[0]~12_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hD5C0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hE000; +defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y9_N3 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N0 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N4 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) + + .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCCEE; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~23_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(\z80_|alu_|db[6]~23_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~5_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~21_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(\z80_|alu_|db_high[3]~5_combout ), + .datac(\z80_|alu_|db[7]~21_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op2_high [3] & (((\z80_|alu_|op1_high [3])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_high [3] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [3]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_high [3]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~27 ( +// Equation(s): +// \z80_|alu_|db_high[3]~27_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~27 .lut_mask = 16'hD555; +defparam \z80_|alu_|db_high[3]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~27_combout & ((\z80_|alu_|db_high[3]~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[3]~6_combout ), + .datab(\z80_|alu_|db_high[3]~4_combout ), + .datac(\z80_|alu_|db_high[3]~27_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'h80C0; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~8 ( +// Equation(s): +// \z80_|alu_|db_high[3]~8_combout = ((\z80_|alu_|db_high[3]~7_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~8 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~8_combout )))) + + .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .lut_mask = 16'h00EA; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N15 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~9 ( +// Equation(s): +// \z80_|alu_|db_low[3]~9_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~9 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_low[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~10 ( +// Equation(s): +// \z80_|alu_|db_low[3]~10_combout = (\z80_|alu_|db_low[3]~9_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~15_combout ), + .datab(\z80_|alu_|db_low[3]~9_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~10 .lut_mask = 16'h4C0C; +defparam \z80_|alu_|db_low[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N15 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( +// Equation(s): +// \z80_|alu_|db_low[3]~7_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~17_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) + + .dataa(\z80_|alu_|db[4]~17_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( +// Equation(s): +// \z80_|alu_|db_low[3]~8_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~7_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~11_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|alu_|db[3]~11_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_low[3]~7_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~11 ( +// Equation(s): +// \z80_|alu_|db_low[3]~11_combout = (\z80_|alu_|db_low[3]~10_combout & (\z80_|alu_|db_low[3]~8_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[3]~10_combout ), + .datab(\z80_|alu_|result_lo [3]), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|db_low[3]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~11 .lut_mask = 16'hA800; +defparam \z80_|alu_|db_low[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( +// Equation(s): +// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_high[3]~2_combout ), + .datac(\z80_|alu_|db_low[3]~11_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hF1F1; +defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N12 +cycloneive_lcell_comb \z80_|alu_|db[3]~10 ( +// Equation(s): +// \z80_|alu_|db[3]~10_combout = (\z80_|execute_|ctl_alu_oe~14_combout & (\z80_|alu_|db_low[3]~25_combout & ((\z80_|reg_file_|gdfx_temp1[3]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~14_combout & +// (((\z80_|reg_file_|gdfx_temp1[3]~48_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datad(\z80_|alu_|db_low[3]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~10 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|db[3]~11 ( +// Equation(s): +// \z80_|alu_|db[3]~11_combout = ((\z80_|alu_|db[3]~10_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[3]~10_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[3]~35_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~11 .lut_mask = 16'hA2FF; +defparam \z80_|alu_|db[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~9_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~3_combout ), + .datac(\z80_|execute_|ctl_alu_oe~9_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0070; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~14_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|setM1~49_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_|db_low[3]~25_combout & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[3]~35_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_low[3]~25_combout & +// (\z80_|alu_control_|db[3]~35_combout & (\z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_|db_low[3]~25_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hEAC0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00CC; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|pla_decode_|Equal56~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # +// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N31 +dffeas \z80_|alu_flags_|flags_xf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_xf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( +// Equation(s): +// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|alu_flags_|flags_xf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF030; +defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N16 +cycloneive_lcell_comb \z80_|sw1_|db_down[3]~1 ( +// Equation(s): +// \z80_|sw1_|db_down[3]~1_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[3]~1 .lut_mask = 16'hFF8C; +defparam \z80_|sw1_|db_down[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( +// Equation(s): +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~1_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datab(\z80_|alu_control_|db[3]~33_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|sw1_|db_down[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8C00; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~11_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_|db[3]~11_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[3]~34_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N3 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N17 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [3]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h40BF; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout )))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h6AAA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N27 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N9 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|alu_control_|db[4]~32_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~59_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & \z80_|reg_file_|gdfx_temp0[4]~56_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp0[4]~62_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hCC0C; +defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N23 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [4]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|address_latch_|Q [4]), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0F4B; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout +// ))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h6A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N5 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|alu_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N3 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~68_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hF050; +defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N27 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5595; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|alu_control_|db[6]~22_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N5 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & \z80_|reg_file_|gdfx_temp0[6]~75_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N23 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout ))))) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h001E; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hF575; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|alu_control_|db[7]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[7]~0_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[7]~0 .lut_mask = 16'hF0F8; +defparam \z80_|reg_file_|db_lo_ds[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N11 +dffeas \z80_|interrupts_|im2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|interrupts_|im2~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( +// Equation(s): +// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|reg_file_|db_lo_ds[7]~0_combout ), + .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|bus_control_|db[7]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2A0A; +defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( +// Equation(s): +// \z80_|alu_control_|db[7]~16_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[7]~21_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (\z80_|execute_|ctl_sw_2u~7_combout & (!\z80_|alu_|db[7]~21_combout ))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_|db[7]~21_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h0CAE; +defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( +// Equation(s): +// \z80_|alu_control_|db[7]~18_combout = ((\z80_|alu_control_|db[7]~17_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & !\z80_|alu_control_|db[7]~16_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[7]~17_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|alu_control_|db[7]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h33B3; +defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[7]~18_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y9_N9 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal62~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h008C; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (\z80_|execute_|ctl_flags_pf_we~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_pf_sel[0]~3_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~11_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & (\z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[2]~29_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datad(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'h88F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal62~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3070; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h152A; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h3B00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N24 cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( // Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [15] & (!\z80_|address_latch_|Q [13] & !\z80_|address_latch_|Q [12]))) +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [13]))) .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|address_latch_|Q [15]), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|Q [12]), + .datab(\z80_|address_latch_|Q [12]), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|Q [13]), .cin(gnd), .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), .cout()); @@ -36178,15 +33544,66 @@ defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y12_N0 +// Location: LCCOMB_X30_Y17_N16 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [2]))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|address_latch_|Q [3]), + .datad(\z80_|address_latch_|Q [2]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0004; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & !\z80_|address_latch_|Q [4]))) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(\z80_|address_latch_|Q [6]), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|address_latch_|Q [4]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [8]))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [11]), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [8]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N18 cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( // Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~0_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~1_combout ))) - .dataa(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .dataa(\z80_|decode_state_|DFFE_instNonRep~0_combout ), .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), .datac(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~1_combout ), .cin(gnd), .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), .cout()); @@ -36195,7 +33612,7 @@ defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N28 +// Location: LCCOMB_X32_Y16_N16 cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( // Equation(s): // \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & @@ -36213,7 +33630,7 @@ defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X41_Y13_N29 +// Location: FF_X32_Y16_N17 dffeas \z80_|decode_state_|DFFE_instNonRep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), @@ -36232,133 +33649,220 @@ defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~12 ( +// Location: LCCOMB_X32_Y16_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout & (((!\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout & -// (((\z80_|decode_state_|DFFE_instNonRep~q )))) +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout ), - .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~12 .lut_mask = 16'h7F2A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'h02AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N8 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .dataa(\z80_|pla_decode_|Equal62~3_combout ), .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h152A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0040; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'h40CC; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~14 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~14_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~14 .lut_mask = 16'hFF01; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N0 +// Location: LCCOMB_X32_Y16_N10 cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[2]~22_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datab(\z80_|execute_|ctl_flags_bus~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|alu_control_|db[2]~22_combout ), + .dataa(\z80_|interrupts_|DFFE_instIFF2~q ), + .datab(\z80_|decode_state_|DFFE_instNonRep~q ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), .cin(gnd), .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hD850; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hA030; defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~13 ( +// Location: LCCOMB_X32_Y16_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~13_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # (\z80_|alu_flags_|DFFE_inst_latch_pf~14_combout -// )))) +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h808C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N23 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & +// \z80_|alu_|alu_op1[1]~0_combout )))) # (!\z80_|alu_|alu_op2[1]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|alu_op1[1]~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hFB20; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hA55A; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( +// Equation(s): +// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datad(\z80_|alu_|alu_parity_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out .lut_mask = 16'hA956; +defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal62~3_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFEF; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h20A0; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datac(\z80_|alu_|alu_parity_out~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~13_combout ), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~13 .lut_mask = 16'hFFC8; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~13 .sum_lutc_input = "datac"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X41_Y15_N27 +// Location: LCCOMB_X36_Y11_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hECCC; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N15 dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~13_combout ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -36374,34 +33878,190 @@ defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N26 +// Location: LCCOMB_X37_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[1]~20_combout & (!\z80_|alu_|db_high[3]~8_combout & (!\z80_|alu_|db_high[2]~14_combout & !\z80_|alu_|db_high[0]~26_combout ))) + + .dataa(\z80_|alu_|db_high[1]~20_combout ), + .datab(\z80_|alu_|db_high[3]~8_combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|alu_|db_high[0]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) + + .dataa(\z80_|alu_control_|db[6]~22_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hAA00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~11_combout & (\z80_|alu_|db_high[3]~3_combout & ((!\z80_|alu_|db_low[2]~3_combout ) # (!\z80_|alu_|db_low[2]~6_combout )))) + + .dataa(\z80_|alu_|db_low[2]~6_combout ), + .datab(\z80_|alu_|db_low[3]~11_combout ), + .datac(\z80_|alu_|db_low[2]~3_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h1300; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~17_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[0]~23_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) + + .dataa(\z80_|alu_|db_low[1]~17_combout ), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|alu_|db_low[0]~23_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hEC00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N27 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] +// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N18 cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( // Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ) # ((!\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|alu_control_|sel[1]~0_combout )))) +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|alu_control_|sel[1]~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), .cin(gnd), .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hB8CC; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N24 +// Location: LCCOMB_X37_Y11_N20 cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( // Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout $ (((!\z80_|ir_|opcode [3]))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & // (((\z80_|alu_control_|flags_cond_true~q )))) - .dataa(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .dataa(\z80_|ir_|opcode [3]), .datab(\z80_|execute_|ctl_eval_cond~0_combout ), .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), .cin(gnd), .combout(\z80_|alu_control_|flags_cond_true~0_combout ), .cout()); @@ -36410,7 +34070,7 @@ defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y16_N25 +// Location: FF_X37_Y11_N21 dffeas \z80_|alu_control_|flags_cond_true ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|alu_control_|flags_cond_true~0_combout ), @@ -36429,32 +34089,32 @@ defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Location: LCCOMB_X35_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( // Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ixy_d~5_combout ) +// \z80_|execute_|ctl_reg_sel_wz~13_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - .dataa(\z80_|execute_|ixy_d~5_combout ), + .dataa(\z80_|pla_decode_|Equal35~0_combout ), .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), .datad(\z80_|pla_decode_|Equal34~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y15_N16 +// Location: LCCOMB_X35_Y16_N18 cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( // Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~10_combout ) +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - .dataa(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~13_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), .cout()); @@ -36463,3091 +34123,2050 @@ defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'hF7FF; defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y15_N4 +// Location: LCCOMB_X34_Y14_N0 cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( // Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (((\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~16_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) - .dataa(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~11_combout ), .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hBFFF; defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~17_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Location: LCCOMB_X30_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Location: LCCOMB_X29_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Location: LCCOMB_X30_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~16_combout ) # ((\z80_|execute_|ctl_sw_4u~5_combout ) # (\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( +// Location: FF_X30_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( +// Location: FF_X31_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~32 ( +// Location: LCCOMB_X31_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~32_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~32 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~32 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( +// Location: FF_X31_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~13 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) +// Location: FF_X30_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), +// Location: FF_X30_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~13 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~13 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~33 ( +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~33_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~33 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~33 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( +// Location: FF_X30_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y15_N3 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~36 ( +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|alu_control_|db[1]~26_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~36_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~36 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~36 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( +// Location: FF_X28_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X35_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~34 ( +// Location: LCCOMB_X28_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~34 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~35_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[1]~16_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~35 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~37_combout = (\z80_|reg_file_|gdfx_temp1[1]~33_combout & (\z80_|reg_file_|gdfx_temp1[1]~36_combout & (\z80_|reg_file_|gdfx_temp1[1]~34_combout & \z80_|reg_file_|gdfx_temp1[1]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~33_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~36_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~34_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~39_combout +// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( +// Location: FF_X28_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~31 ( +// Location: LCCOMB_X28_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~31_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~31_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~31 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[1]~31 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~38 ( +// Location: LCCOMB_X31_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~38_combout = (\z80_|reg_file_|gdfx_temp1[1]~32_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~37_combout & \z80_|reg_file_|gdfx_temp1[1]~31_combout ))) +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~29_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - .dataa(\z80_|reg_file_|gdfx_temp1[1]~32_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~37_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~31_combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~38_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~38 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~39 ( +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~39_combout = ((\z80_|reg_file_|gdfx_temp1[1]~38_combout & ((\z80_|reg_file_|db_hi_as[1]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~39 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp1[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~7_combout = (\z80_|reg_file_|gdfx_temp1[1]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[1]~39_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~7 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~8_combout = (\z80_|reg_file_|db_hi_as[1]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[1]~7_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~8 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|execute_|ctl_inc_dec~8_combout & (!\z80_|address_latch_|Q [7] & !\z80_|address_latch_|Q -// [8])) # (!\z80_|execute_|ctl_inc_dec~8_combout & (\z80_|address_latch_|Q [7] & \z80_|address_latch_|Q [8])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) +// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout .dataa(gnd), .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~9_combout = ((\z80_|reg_file_|db_hi_as[1]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[1]~8_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~9 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~9_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y11_N27 -dffeas \z80_|address_latch_|Q[9] ( +// Location: FF_X29_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [9]), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q -// [9]))))) - - .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), - .datab(\z80_|address_latch_|Q [10]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( +// Location: FF_X29_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~18_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~16 ( +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( // Equation(s): -// \z80_|reg_file_|db_hi_as[2]~16_combout = (\z80_|reg_file_|gdfx_temp1[2]~66_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[2]~66_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - .dataa(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~16_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~16 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[2]~16 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( +// Location: FF_X30_Y13_N23 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~18_combout ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hF733; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hF0F8; +defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( +// Equation(s): +// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|bus_control_|db[1]~11_combout ), + .datab(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0C8C; +defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( +// Equation(s): +// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[1]~13_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[1]~13_combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_|db[1]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0ACE; +defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( +// Equation(s): +// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~23_combout & !\z80_|alu_control_|db[1]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[1]~25_combout ), + .datab(\z80_|alu_control_|db[2]~23_combout ), + .datac(\z80_|alu_control_|db[6]~11_combout ), + .datad(\z80_|alu_control_|db[1]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h0F8F; +defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|db[1]~12 ( +// Equation(s): +// \z80_|alu_|db[1]~12_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[1]~26_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[1]~26_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~12 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db[1]~13 ( +// Equation(s): +// \z80_|alu_|db[1]~13_combout = ((\z80_|alu_|db[1]~12_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[1]~12_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~13 .lut_mask = 16'hA2FF; +defparam \z80_|alu_|db[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( +// Equation(s): +// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~13_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|alu_|db[1]~13_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF5A0; +defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( +// Equation(s): +// \z80_|alu_|db_low[0]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~19_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[0]~21_combout ), + .datac(\z80_|alu_|db[0]~19_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( +// Equation(s): +// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h5557; +defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( +// Equation(s): +// \z80_|alu_|db_low[0]~19_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op1_low [0]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N25 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( +// Equation(s): +// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~18_combout & (\z80_|alu_|db_low[0]~19_combout & ((\z80_|alu_|result_lo [0]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[0]~18_combout ), + .datab(\z80_|alu_|db_low[0]~19_combout ), + .datac(\z80_|alu_|result_lo [0]), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( +// Equation(s): +// \z80_|alu_|db_low[0]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & ((\z80_|alu_|db_low[0]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~20_combout ) # +// (!\z80_|alu_|db_high[3]~2_combout )))) + + .dataa(\z80_|alu_|db_low[0]~22_combout ), + .datab(\z80_|alu_|db_high[3]~2_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[0]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hAF03; +defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( +// Equation(s): +// \z80_|alu_|db[0]~18_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_|db_low[0]~23_combout ) # ((!\z80_|execute_|ctl_alu_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_|db_low[0]~23_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db[0]~19 ( +// Equation(s): +// \z80_|alu_|db[0]~19_combout = ((\z80_|alu_|db[0]~18_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[0]~12_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~19 .lut_mask = 16'hA2FF; +defparam \z80_|alu_|db[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( +// Equation(s): +// \z80_|alu_|db_low[1]~15_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~19_combout )) + + .dataa(\z80_|alu_|db[0]~19_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( +// Equation(s): +// \z80_|alu_|db_low[1]~16_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[1]~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[1]~13_combout ))) + + .dataa(\z80_|alu_|db_low[1]~15_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[1]~13_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAAF0; +defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( +// Equation(s): +// \z80_|alu_|db_low[1]~12_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'h5755; +defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( +// Equation(s): +// \z80_|alu_|db_low[1]~13_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op1_low [1]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N21 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( +// Equation(s): +// \z80_|alu_|db_low[1]~14_combout = (\z80_|alu_|db_low[1]~12_combout & (\z80_|alu_|db_low[1]~13_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[1]~12_combout ), + .datab(\z80_|alu_|db_low[1]~13_combout ), + .datac(\z80_|alu_|result_lo [1]), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( +// Equation(s): +// \z80_|alu_|db_low[1]~17_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~16_combout & \z80_|alu_|db_low[1]~14_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~14_combout )) # +// (!\z80_|alu_|db_high[3]~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_high[3]~2_combout ), + .datac(\z80_|alu_|db_low[1]~16_combout ), + .datad(\z80_|alu_|db_low[1]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hF511; +defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_low[1]~17_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[1]~20_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00F0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N1 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .q(\z80_|alu_|op1_low [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~17 ( +// Location: LCCOMB_X36_Y10_N28 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( // Equation(s): -// \z80_|reg_file_|db_hi_as[2]~17_combout = (\z80_|reg_file_|db_hi_as[2]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) - .dataa(\z80_|reg_file_|db_hi_as[2]~16_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .dataa(gnd), + .datab(\z80_|alu_|op1_low [1]), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|alu_|op1_low [2]), .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~17_combout ), + .combout(\z80_|alu_control_|out[6]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~17 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[2]~17 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0C0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~18 ( +// Location: LCCOMB_X36_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( // Equation(s): -// \z80_|reg_file_|db_hi_as[2]~18_combout = ((\z80_|reg_file_|db_hi_as[2]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout ) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~17_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~18 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_hi_as[2]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~18_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), + .dataa(gnd), .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[2]~18_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N8 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|alu_control_|db[4]~32_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N9 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( +// Equation(s): +// \z80_|alu_control_|db[2]~23_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|alu_flags_|flags_hf2~q ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~combout ), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|alu_flags_|flags_hf2~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFEF; +defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|bus_control_|db[2]~13_combout ), + .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h2F00; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( +// Equation(s): +// \z80_|alu_control_|db[2]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[2]~15_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (!\z80_|alu_|db[2]~15_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|alu_|db[2]~15_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h3B0A; +defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( +// Equation(s): +// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~23_combout & (\z80_|alu_control_|db[2]~28_combout & !\z80_|alu_control_|db[2]~27_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[6]~11_combout ), + .datab(\z80_|alu_control_|db[2]~23_combout ), + .datac(\z80_|alu_control_|db[2]~28_combout ), + .datad(\z80_|alu_control_|db[2]~27_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h55D5; +defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db[2]~14 ( +// Equation(s): +// \z80_|alu_|db[2]~14_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~39_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[2]~29_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[2]~29_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~14 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[2]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( +// Equation(s): +// \z80_|alu_|db[2]~15_combout = ((\z80_|alu_|db[2]~14_combout & ((\z80_|alu_|db_low[2]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db_low[2]~24_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[2]~14_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~2 ( +// Equation(s): +// \z80_|alu_|db_low[2]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~13_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|alu_|db[3]~11_combout ), + .datac(\z80_|alu_|db[1]~13_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), + .combout(\z80_|alu_|db_low[2]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~2 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|db_low[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N31 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [10]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Location: LCCOMB_X35_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~3 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~8_combout & (!\z80_|address_latch_|Q [10] & -// !\z80_|address_latch_|Q [9])) # (!\z80_|execute_|ctl_inc_dec~8_combout & (\z80_|address_latch_|Q [10] & \z80_|address_latch_|Q [9])))) +// \z80_|alu_|db_low[2]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~15_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), - .datab(\z80_|address_latch_|Q [10]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .dataa(\z80_|alu_|db[2]~15_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_low[2]~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .combout(\z80_|alu_|db_low[2]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h4200; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~3 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_low[2]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Location: LCCOMB_X35_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [11] & (!\z80_|execute_|ctl_inc_dec~8_combout & -// \z80_|address_latch_|Q [12])) # (!\z80_|address_latch_|Q [11] & (\z80_|execute_|ctl_inc_dec~8_combout & !\z80_|address_latch_|Q [12])))) +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|Q [12]), + .dataa(\z80_|alu_|db_low[2]~6_combout ), + .datab(\z80_|alu_|db_high[3]~3_combout ), + .datac(\z80_|alu_|db_low[2]~3_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0820; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hB300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Location: LCCOMB_X36_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - .dataa(gnd), - .datab(\z80_|address_latch_|Q [13]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h33CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3222; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [5] & ((\z80_|reg_file_|gdfx_temp1[5]~75_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[5]~75_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~19 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[5]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~20_combout = (\z80_|reg_file_|db_hi_as[5]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datad(\z80_|reg_file_|db_hi_as[5]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~20 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_hi_as[5]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~21_combout = ((\z80_|reg_file_|db_hi_as[5]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~21 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[5]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~21_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N27 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [13]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [13]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|Q [13]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~7_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~4_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [7] & ((\z80_|reg_file_|gdfx_temp1[7]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[7]~30_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~4 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|db_hi_as[7]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~5_combout = (\z80_|reg_file_|db_hi_as[7]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[7]~4_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~5 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[7]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~6_combout = ((\z80_|reg_file_|db_hi_as[7]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .datab(\z80_|reg_file_|db_hi_as[7]~5_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~6 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_hi_as[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~6_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h0A0A; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|execute_|ctl_inc_dec~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|execute_|ctl_apin_mux~1_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'hF333; -defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|address_latch_|abusz [15]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0D0D; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ctl_mWrite~2_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~15_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & !\z80_|execute_|fIOWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|fIORead~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( -// Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|ctl_mRead~7_combout & \z80_|execute_|fIOWrite~3_combout ))) - - .dataa(\z80_|execute_|fIORead~2_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|fIOWrite~3_combout ), - .datad(\z80_|execute_|fIORead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N14 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fMRead~36_combout ) # (((\z80_|execute_|fIORead~3_combout ) # (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )) - - .dataa(\z80_|execute_|fMRead~36_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFBF; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout ) # -// ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h4F44; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( +// Location: FF_X36_Y10_N25 +dffeas \z80_|alu_|op1_low[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~17 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[15]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~15_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0030; -defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h0202; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg -// [6] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|WideOr17~0_combout & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|WideOr17~0_combout ), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0088; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~0_combout ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N13 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), + .q(\z80_|alu_|op1_low [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Location: LCCOMB_X37_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [2])) +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [2]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Location: LCCOMB_X37_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~41_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q ))) +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ) # ((\z80_|alu_|db_low[2]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|extended~q ), + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), + .datac(\z80_|alu_|db_low[2]~24_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|zx_keyboard_|keys[6][1]~42_combout & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & (!\ula_|zx_keyboard_|keys[6][1]~40_combout )) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & ((\ula_|zx_keyboard_|keys[6][1]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N31 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( +// Location: FF_X37_Y10_N13 +dffeas \z80_|alu_|op2_low[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~16 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[14]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \D[1]~27 ( -// Equation(s): -// \D[1]~27_combout = (\ula_|zx_keyboard_|keys[7][1]~q & (\z80_|address_pins_|abus[15]~17_combout & ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[7][1]~q & -// (((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~q ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\z80_|address_pins_|abus[14]~16_combout ), - .cin(gnd), - .combout(\D[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~27 .lut_mask = 16'hDD0D; -defparam \D[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~19_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~19 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|keys[7][1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hF000; -defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|keys[5][4]~24_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~26_combout = (\ula_|zx_keyboard_|keys[1][4]~25_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h0C00; -defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N11 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .q(\z80_|alu_|op2_low [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Location: LCCOMB_X38_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) +// \z80_|alu_|db_low[2]~5_combout = (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - .dataa(\z80_|address_latch_|abusz [10]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .dataa(\z80_|alu_|op2_low [2]), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .combout(\z80_|alu_|db_low[2]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'h8ACF; +defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), +// Location: FF_X39_Y10_N13 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [10]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~22 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[10]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00A0; -defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~28_combout = (\ula_|zx_keyboard_|keys[5][4]~24_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[7][1]~19_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N9 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .q(\z80_|alu_|result_lo [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Location: LCCOMB_X35_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) +// \z80_|alu_|db_low[2]~6_combout = (\z80_|alu_|db_low[2]~4_combout & (\z80_|alu_|db_low[2]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2])))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|address_latch_|abusz [11]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|alu_|db_low[2]~4_combout ), + .datab(\z80_|alu_|db_low[2]~5_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|result_lo [2]), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .combout(\z80_|alu_|db_low[2]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N23 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( +// Location: LCCOMB_X35_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) + + .dataa(\z80_|alu_|db_low[2]~6_combout ), + .datab(\z80_|alu_|db_low[2]~3_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h80F0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N27 +dffeas \z80_|alu_|op2_high[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [11]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~21 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[11]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N2 -cycloneive_lcell_comb \D[1]~25 ( -// Equation(s): -// \D[1]~25_combout = (\ula_|zx_keyboard_|keys[2][1]~q & (\z80_|address_pins_|abus[10]~22_combout & ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) # (!\ula_|zx_keyboard_|keys[2][1]~q & -// (((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[2][1]~q ), - .datab(\z80_|address_pins_|abus[10]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\z80_|address_pins_|abus[11]~21_combout ), - .cin(gnd), - .combout(\D[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~25 .lut_mask = 16'hDD0D; -defparam \D[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~31_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h5050; -defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~32_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h1100; -defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][2]~32_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N5 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .q(\z80_|alu_|op2_high [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Location: LCCOMB_X38_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [12]))) +// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [12]), + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|alu_|op2_low [2]), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .combout(\z80_|alu_|alu_op2[2]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h4B78; +defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y2_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~24 ( +// Location: LCCOMB_X39_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( // Equation(s): -// \z80_|address_pins_|abus[12]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [12]), + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~24_combout ), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[12]~24 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[12]~24 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0BFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Location: LCCOMB_X39_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [13])) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~2_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - .dataa(\z80_|address_latch_|abusz [13]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|alu_op1[2]~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N3 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~23 ( +// Location: LCCOMB_X34_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( // Equation(s): -// \z80_|address_pins_|abus[13]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_|db_high[2]~9_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - .dataa(gnd), + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'h55D5; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~21_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~25_combout )) + + .dataa(\z80_|ir_|opcode [3]), .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|alu_|db[5]~25_combout ), + .datad(\z80_|alu_|db[7]~21_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~23_combout ), + .combout(\z80_|alu_|db_high[2]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[13]~23 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[13]~23 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hFA50; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( +// Location: LCCOMB_X35_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0011; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|ps2_keyboard_|shiftreg [4])) +// \z80_|alu_|db_high[2]~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[2]~11_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[6]~23_combout ))) .dataa(gnd), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\z80_|alu_|db_high[2]~11_combout ), + .datac(\z80_|alu_|db[6]~23_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .combout(\z80_|alu_|db_high[2]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0030; -defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Location: LCCOMB_X38_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [6])) +// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_high [2]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .combout(\z80_|alu_|db_high[2]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'h8800; -defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Location: LCCOMB_X34_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) +// \z80_|alu_|db_high[2]~13_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~12_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(gnd), + .dataa(\z80_|alu_|db_high[2]~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[2]~12_combout ), + .datad(\z80_|alu_|db_high[2]~10_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .combout(\z80_|alu_|db_high[2]~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( +// Location: LCCOMB_X35_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~14 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~38_combout & ((\ula_|zx_keyboard_|keys[5][1]~37_combout & ((!\ula_|zx_keyboard_|keys[5][1]~35_combout ))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & -// (\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) +// \z80_|alu_|db_high[2]~14_combout = ((\z80_|alu_|db_high[2]~13_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - .dataa(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .datab(\z80_|alu_|db_high[3]~3_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|db_high[2]~13_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .combout(\z80_|alu_|db_high[2]~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~14 .lut_mask = 16'hFB33; +defparam \z80_|alu_|db_high[2]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y13_N29 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \D[1]~26 ( +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( // Equation(s): -// \D[1]~26_combout = (\ula_|zx_keyboard_|keys[4][1]~q & (\z80_|address_pins_|abus[12]~24_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\ula_|zx_keyboard_|keys[4][1]~q & -// (((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) +// \z80_|alu_|db[6]~22_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - .dataa(\ula_|zx_keyboard_|keys[4][1]~q ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[5][1]~q ), + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .datad(\z80_|alu_control_|db[6]~22_combout ), .cin(gnd), - .combout(\D[1]~26_combout ), + .combout(\z80_|alu_|db[6]~22_combout ), .cout()); // synopsys translate_off -defparam \D[1]~26 .lut_mask = 16'hD0DD; -defparam \D[1]~26 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db[6]~23 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [9])) +// \z80_|alu_|db[6]~23_combout = ((\z80_|alu_|db[6]~22_combout & ((\z80_|alu_|db_high[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - .dataa(\z80_|address_latch_|abusz [9]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|alu_|db_high[2]~14_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .combout(\z80_|alu_|db[6]~23_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db[6]~23 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[6]~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y3_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~19 ( +// Location: LCCOMB_X36_Y10_N10 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( // Equation(s): -// \z80_|address_pins_|abus[9]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|alu_|op1_high [1]), + .datad(\z80_|alu_control_|out[6]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N26 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) + + .dataa(\z80_|execute_|ctl_66_oe~combout ), + .datab(\z80_|alu_control_|out[6]~1_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEA; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~19 ( +// Equation(s): +// \z80_|alu_control_|db[6]~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & +// (!\z80_|execute_|ctl_flags_oe~2_combout & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|out[6]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~19 .lut_mask = 16'hAF8C; +defparam \z80_|alu_control_|db[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( +// Equation(s): +// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_control_|db[6]~19_combout & ((\z80_|alu_|db[6]~23_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [9]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|alu_|db[6]~23_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[6]~19_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~19_combout ), + .combout(\z80_|alu_control_|db[6]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[9]~19 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[9]~19 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'hCF00; +defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Location: LCCOMB_X34_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) +// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|db[6]~20_combout & (((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - .dataa(\z80_|address_latch_|abusz [8]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|bus_control_|db[6]~9_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|alu_control_|db[6]~20_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .combout(\z80_|alu_control_|db[6]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h30B0; +defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N27 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~20 ( +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( // Equation(s): -// \z80_|address_pins_|abus[8]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_control_|db[6]~22_combout = ((\z80_|alu_control_|db[6]~21_combout & ((\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [8]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|alu_control_|db[6]~11_combout ), + .datab(\z80_|alu_control_|db[6]~21_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~20_combout ), + .combout(\z80_|alu_control_|db[6]~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[8]~20 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[8]~20 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hD5DD; +defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Location: LCCOMB_X39_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) +// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - .dataa(gnd), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hF0F3; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0028; -defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2400; -defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & -// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N1 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~20_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~20 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|keys[1][1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~21 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~21_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~21 .lut_mask = 16'h3000; -defparam \ula_|zx_keyboard_|keys[6][4]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~21_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~23_combout = (\ula_|zx_keyboard_|keys[1][1]~20_combout & ((\ula_|zx_keyboard_|keys[1][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~22_combout & ((\ula_|zx_keyboard_|keys[1][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[1][1]~20_combout & (((\ula_|zx_keyboard_|keys[1][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[1][1]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~23 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[1][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y14_N7 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~23_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N0 -cycloneive_lcell_comb \D[1]~24 ( -// Equation(s): -// \D[1]~24_combout = (\z80_|address_pins_|abus[9]~19_combout & ((\z80_|address_pins_|abus[8]~20_combout ) # ((!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\z80_|address_pins_|abus[9]~19_combout & (!\ula_|zx_keyboard_|keys[1][1]~q & -// ((\z80_|address_pins_|abus[8]~20_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~19_combout ), - .datab(\z80_|address_pins_|abus[8]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[1][1]~q ), - .cin(gnd), - .combout(\D[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~24 .lut_mask = 16'h8ACF; -defparam \D[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N4 -cycloneive_lcell_comb \D[1]~28 ( -// Equation(s): -// \D[1]~28_combout = (\D[1]~27_combout & (\D[1]~25_combout & (\D[1]~26_combout & \D[1]~24_combout ))) - - .dataa(\D[1]~27_combout ), - .datab(\D[1]~25_combout ), - .datac(\D[1]~26_combout ), - .datad(\D[1]~24_combout ), - .cin(gnd), - .combout(\D[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~28 .lut_mask = 16'h8000; -defparam \D[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y14_N0 -cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( -// Equation(s): -// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; -defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y14_N1 -dffeas \z80_|clk_delay_|DFF_inst5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|DFF_inst5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y14_N26 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y14_N27 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; -// synopsys translate_on - -// Location: FF_X52_Y14_N5 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = ((!\z80_|execute_|ctl_mRead~38_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'h337F; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_iorw~12_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_iorw~12_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), + .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hC800; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Location: LCCOMB_X34_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( // Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~13_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~6_combout ) +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) - .dataa(\z80_|execute_|nextM~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[3]~21_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h00CC; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N25 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( +// Location: FF_X34_Y10_N9 +dffeas \z80_|interrupts_|im1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(\z80_|execute_|ctl_im_we~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .q(\z80_|interrupts_|im1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( +// Location: LCCOMB_X32_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( // Equation(s): -// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|interrupts_|im1~q ), + .datac(\z80_|interrupts_|im2~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hDC00; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h40EE; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( +// Equation(s): +// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hFF31; +defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), + .combout(\z80_|bus_control_|db[6]~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N13 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N8 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Location: LCCOMB_X37_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( // Equation(s): -// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q +// \z80_|execute_|ctl_mRead~37_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .combout(\z80_|execute_|ctl_mRead~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N9 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X50_Y16_N3 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N2 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Location: LCCOMB_X37_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( // Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) +// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~37_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .dataa(\z80_|execute_|ctl_mRead~37_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), + .combout(\z80_|execute_|ctl_mRead~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N4 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Location: LCCOMB_X37_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( // Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ctl_mRead~28_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) - .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), - .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), + .dataa(\z80_|execute_|ctl_mRead~28_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .combout(\z80_|execute_|ctl_mRead~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( -// Equation(s): -// \z80_|execute_|setM1~38_combout = (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|fMRead~4_combout & !\z80_|pla_decode_|Equal9~1_combout )) - - .dataa(\z80_|pla_decode_|Equal29~0_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0404; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~57 ( -// Equation(s): -// \z80_|execute_|setM1~57_combout = (!\z80_|execute_|ctl_mRead~16_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~57 .lut_mask = 16'h00EF; -defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~57_combout & (\z80_|execute_|setM1~37_combout & !\z80_|execute_|ctl_mRead~18_combout ))) - - .dataa(\z80_|execute_|setM1~38_combout ), - .datab(\z80_|execute_|setM1~57_combout ), - .datac(\z80_|execute_|setM1~37_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & ((!\z80_|execute_|setM1~39_combout ) # (!\z80_|execute_|ctl_mRead~21_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_mRead~21_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h1050; -defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~35_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~14_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hEEAA; -defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~40 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~40_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal38~2_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~40 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_mRead~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~39 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~39_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~38_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~39 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_mRead~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N0 +// Location: LCCOMB_X35_Y16_N28 cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( // Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~27_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )))) +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~29_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_mRead~27_combout ), + .dataa(\z80_|execute_|ctl_mRead~29_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'h0080; defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Location: LCCOMB_X38_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( // Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~40_combout & (\z80_|execute_|ctl_mRead~26_combout & (\z80_|execute_|ctl_mRead~39_combout & \z80_|execute_|ctl_mRead~30_combout ))) +// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|ctl_al_we~4_combout & \z80_|execute_|ctl_inc_cy~41_combout ))) - .dataa(\z80_|execute_|ctl_mRead~40_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_mRead~39_combout ), - .datad(\z80_|execute_|ctl_mRead~30_combout ), + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|execute_|ctl_inc_cy~41_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), + .combout(\z80_|execute_|setM1~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~37 .lut_mask = 16'h1000; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Location: LCCOMB_X40_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( // Equation(s): -// \z80_|execute_|nextM~4_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) +// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'h3233; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (!\z80_|execute_|ctl_mRead~16_combout & (\z80_|execute_|setM1~37_combout & (\z80_|execute_|setM1~55_combout & \z80_|execute_|setM1~36_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|setM1~37_combout ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|execute_|setM1~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'h4000; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|setM1~38_combout ))) + + .dataa(\z80_|execute_|setM1~38_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|nextM~3 ( +// Equation(s): +// \z80_|execute_|nextM~3_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) .dataa(gnd), .datab(\z80_|pla_decode_|Equal41~2_combout ), .datac(\z80_|execute_|ixy_d~10_combout ), .datad(\z80_|execute_|ixy_d~16_combout ), .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), + .combout(\z80_|execute_|nextM~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0003; +defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Location: LCCOMB_X40_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( // Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|nextM~4_combout ))) +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|nextM~4_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|ctl_mRead~32_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFC0; defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( +// Location: LCCOMB_X43_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( // Equation(s): -// \z80_|execute_|ctl_mRead~37_combout = (\z80_|execute_|ctl_mRead~36_combout ) # ((\z80_|execute_|ctl_mRead~35_combout ) # ((\z80_|execute_|ctl_mRead~33_combout ) # (!\z80_|execute_|ctl_mRead~31_combout ))) +// \z80_|execute_|ctl_mRead~35_combout = ((\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (\z80_|execute_|ctl_mRead~33_combout ))) # (!\z80_|execute_|ctl_mRead~30_combout ) - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ctl_mRead~35_combout ), + .dataa(\z80_|execute_|ctl_mRead~30_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), .datac(\z80_|execute_|ctl_mRead~31_combout ), .datad(\z80_|execute_|ctl_mRead~33_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~37_combout ), + .combout(\z80_|execute_|ctl_mRead~35_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X49_Y16_N15 +// Location: FF_X43_Y17_N23 dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~37_combout ), + .d(\z80_|execute_|ctl_mRead~35_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -39563,7 +36182,7 @@ defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N22 +// Location: LCCOMB_X46_Y15_N24 cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( // Equation(s): // \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q @@ -39580,7 +36199,7 @@ defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N23 +// Location: FF_X46_Y15_N25 dffeas \z80_|memory_ifc_|wait_mrd ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), @@ -39599,7 +36218,7 @@ defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; // synopsys translate_on -// Location: FF_X50_Y16_N15 +// Location: FF_X43_Y17_N3 dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -39618,28 +36237,151 @@ defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N26 +// Location: LCCOMB_X43_Y17_N8 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( // Equation(s): // \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) .dataa(\z80_|memory_ifc_|wait_mrd~q ), .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datad(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nRD_out~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0505; +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N7 -dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( +// Location: LCCOMB_X40_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout ) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|nextM~4_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ctl_iorw~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N7 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_iorw~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( +// Equation(s): +// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N27 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y17_N9 +dffeas \z80_|memory_ifc_|wait_iorq ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|execute_|setM1~52_combout ), + .asdata(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), @@ -39647,6 +36389,129 @@ dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y17_N13 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|wait_iorq~q ), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hA800; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|fIORead~1_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFF2; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Equation(s): +// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hA080; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|fIOWrite~1_combout ), + .datab(\z80_|execute_|fIORead~2_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|fIORead~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X41_Y17_N25 +dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|setM1~52_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), .prn(vcc)); // synopsys translate_off @@ -39654,7 +36519,7 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N30 +// Location: LCCOMB_X43_Y17_N14 cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( // Equation(s): // \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q @@ -39671,7 +36536,7 @@ defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N31 +// Location: FF_X43_Y17_N15 dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), @@ -39690,7 +36555,7 @@ defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; // synopsys translate_on -// Location: FF_X50_Y16_N17 +// Location: FF_X43_Y17_N21 dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -39709,139 +36574,817 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N16 +// Location: LCCOMB_X43_Y17_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( // Equation(s): -// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & (((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|interrupts_|DFFE_inst44~q ))) # (!\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & -// (\z80_|memory_ifc_|DFFE_m1_ff3~q & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|interrupts_|DFFE_inst44~q )))) +// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|DFFE_inst44~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|DFFE_inst44~q & +// ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - .dataa(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), + .dataa(\z80_|interrupts_|DFFE_inst44~q ), + .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nRD_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFA32; +defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFC54; defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N20 +// Location: LCCOMB_X43_Y17_N18 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( // Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) +// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) .dataa(\z80_|memory_ifc_|nRD_out~1_combout ), - .datab(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|memory_ifc_|iorq~0_combout ), .datac(\z80_|execute_|fIORead~3_combout ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nRD_out~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFDDD; +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFFD5; defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N4 -cycloneive_lcell_comb \Equal2~0 ( +// Location: LCCOMB_X31_Y12_N24 +cycloneive_lcell_comb \Equal2~1 ( // Equation(s): -// \Equal2~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) +// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) - .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), .datab(\z80_|memory_ifc_|nRD_out~2_combout ), .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .datad(gnd), .cin(gnd), - .combout(\Equal2~0_combout ), + .combout(\Equal2~1_combout ), .cout()); // synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h0080; -defparam \Equal2~0 .sum_lutc_input = "datac"; +defparam \Equal2~1 .lut_mask = 16'h4040; +defparam \Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y13_N21 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N12 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~0 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram1|altsyncram_component|auto_generated|address_reg_a [0] +// \z80_|pin_control_|bus_db_pin_oe~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~0 .lut_mask = 16'hFFAA; +defparam \z80_|pin_control_|bus_db_pin_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3F33; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) + + .dataa(\z80_|execute_|fMWrite~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'h5554; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( +// Equation(s): +// \z80_|execute_|fMWrite~2_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h555F; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fMWrite~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h00EF; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~1 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~1_combout = (\z80_|execute_|ctl_bus_inc_oe~24_combout & (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|fMWrite~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .datab(\z80_|execute_|fIOWrite~5_combout ), + .datac(\z80_|execute_|fMWrite~6_combout ), + .datad(\z80_|execute_|fMWrite~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~1 .lut_mask = 16'h0002; +defparam \z80_|pin_control_|bus_db_pin_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'h135F; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|pin_control_|bus_db_pin_oe~2_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'hA2AA; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_mRead~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'h0003; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~7_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|fMWrite~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hCD00; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h0777; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|fMRead~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout )) # +// (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|fMRead~1_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h3715; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~9 ( +// Equation(s): +// \z80_|execute_|fMWrite~9_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout )) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal46~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~9 .lut_mask = 16'hCEFF; +defparam \z80_|execute_|fMWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & +// (((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fMWrite~9_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hDDD0; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|execute_|fMWrite~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout )) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datab(\z80_|execute_|fMWrite~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0808; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_state_alu~6_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & (\z80_|execute_|ctl_reg_sel_wz~5_combout & (!\z80_|execute_|fMWrite~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~5_combout ), + .datac(\z80_|execute_|fMWrite~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h0800; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~7_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~5_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|fMWrite~10 ( +// Equation(s): +// \z80_|execute_|fMWrite~10_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & +// ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~10 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & (!\z80_|execute_|fMWrite~10_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .datac(\z80_|execute_|fMWrite~10_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h0800; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2A00; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~1_combout & (\z80_|pin_control_|bus_db_pin_oe~12_combout & \z80_|execute_|ctl_inc_cy~37_combout ))) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout ))) # +// (!\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|fIOWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'hF222; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y15_N0 +cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( +// Equation(s): +// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; +defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y13_N13 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( +// Location: FF_X43_Y15_N1 +dffeas \z80_|clk_delay_|DFF_inst5 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .q(\z80_|clk_delay_|DFF_inst5~q ), .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \ExtRamWE~0 ( +// Location: LCCOMB_X43_Y15_N22 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( // Equation(s): -// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|memory_ifc_|nIORQ_out~0_combout & !\z80_|memory_ifc_|nRD_out~2_combout ))) +// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|clk_delay_|DFF_inst5~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y15_N23 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y15_N13 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y15_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datad(\z80_|memory_ifc_|iorq~0_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nIORQ_out~0_combout ))) .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datad(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h4000; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), .cin(gnd), .combout(\ExtRamWE~0_combout ), .cout()); // synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h0008; +defparam \ExtRamWE~0 .lut_mask = 16'h0020; defparam \ExtRamWE~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N10 +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [13]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0B0B; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~2_combout = (((\z80_|execute_|fMRead~35_combout ) # (\z80_|execute_|fIORead~3_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .datac(\z80_|execute_|fMRead~35_combout ), + .datad(\z80_|execute_|fIORead~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFF7; +defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pin_control_|bus_ab_pin_we~2_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T3_ff~q & +// (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h3B0A; +defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [14]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N4 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [15]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[15]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hF3F3; +defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N8 cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), .cin(gnd), .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .cout()); @@ -39850,24 +37393,41 @@ defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_m defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N8 +// Location: LCCOMB_X32_Y14_N22 cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) .dataa(gnd), .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), .cin(gnd), .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h0C00; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00C0; defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N8 +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) @@ -39884,7 +37444,7 @@ defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hDD88; defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N9 +// Location: FF_X31_Y17_N29 dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), @@ -39903,41 +37463,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N4 +// Location: LCCOMB_X31_Y18_N20 cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( // Equation(s): // \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(gnd), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [1]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [1]), .cin(gnd), .combout(\z80_|address_pins_|abus[1]~25_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hFF55; defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N8 +// Location: LCCOMB_X31_Y17_N18 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [2]))) +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [2]), .datac(gnd), - .datad(\z80_|address_latch_|abusz [2]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N9 +// Location: FF_X31_Y17_N19 dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), @@ -39956,7 +37516,7 @@ defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N16 +// Location: LCCOMB_X31_Y18_N26 cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( // Equation(s): // \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) @@ -39973,24 +37533,24 @@ defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N30 +// Location: LCCOMB_X31_Y17_N0 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) - .dataa(\z80_|address_latch_|abusz [3]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [3]), .datac(gnd), .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N31 +// Location: FF_X31_Y17_N1 dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), @@ -40009,41 +37569,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y2_N22 +// Location: LCCOMB_X31_Y18_N12 cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( // Equation(s): // \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\z80_|address_pins_|DFFE_apin_latch [3]), .cin(gnd), .combout(\z80_|address_pins_|abus[3]~27_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N4 +// Location: LCCOMB_X31_Y17_N30 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) - .dataa(\z80_|address_latch_|abusz [4]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [4]), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N5 +// Location: FF_X31_Y17_N31 dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), @@ -40062,41 +37622,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y3_N22 +// Location: LCCOMB_X31_Y18_N2 cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( // Equation(s): // \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [4]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [4]), .cin(gnd), .combout(\z80_|address_pins_|abus[4]~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N12 +// Location: LCCOMB_X30_Y16_N12 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - .dataa(\z80_|address_latch_|abusz [5]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [5]), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y13_N13 +// Location: FF_X30_Y16_N13 dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), @@ -40115,41 +37675,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N10 +// Location: LCCOMB_X29_Y17_N20 cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( // Equation(s): // \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|address_pins_|DFFE_apin_latch [5]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(gnd), .cin(gnd), .combout(\z80_|address_pins_|abus[5]~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF3F3; defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N6 +// Location: LCCOMB_X30_Y16_N10 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [6]), + .dataa(\z80_|address_latch_|abusz [6]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hCCAA; defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N7 +// Location: FF_X30_Y16_N11 dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), @@ -40168,41 +37728,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N8 +// Location: LCCOMB_X31_Y18_N28 cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( // Equation(s): // \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [6]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [6]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|address_pins_|abus[6]~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N22 +// Location: LCCOMB_X30_Y16_N30 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - .dataa(\z80_|address_latch_|abusz [7]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [7]), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y13_N23 +// Location: FF_X30_Y16_N31 dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), @@ -40221,2261 +37781,289 @@ defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N24 +// Location: LCCOMB_X31_Y18_N22 cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( // Equation(s): // \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\z80_|address_pins_|DFFE_apin_latch [7]), .cin(gnd), .combout(\z80_|address_pins_|abus[7]~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y29_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X29_Y14_N27 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~16_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N23 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (!\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), + .dataa(\z80_|address_latch_|abusz [8]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0400; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N21 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [8]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [14] & !\z80_|address_pins_|DFFE_apin_latch [13])) +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: FF_X31_Y16_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N30 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (!\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h4000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [14] & !\z80_|address_pins_|DFFE_apin_latch [13])) +// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .combout(\z80_|address_pins_|abus[9]~17_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h00C0; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N16 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout & -// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEA4A; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & !\z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N20 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datab(\z80_|address_latch_|abusz [10]), .datac(gnd), - .datad(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), - .combout(\~GND~combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), .cout()); // synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y30_N2 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) - - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0028; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N21 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y30_N25 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N2 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h00FF; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N3 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N0 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [7] $ (\ula_|video_|vga_hc [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N1 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N30 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [7]))) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'hA555; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N31 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N8 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N10 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N12 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N14 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N15 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N16 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N17 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N18 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N19 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N20 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N28 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFC30; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y30_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( -// Equation(s): -// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) - - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[9]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0028; -defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N29 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N22 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [8]), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N26 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|Add4~2_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hF3C0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N27 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N2 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [0]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h1020; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|Add4~4_combout ), - .datab(\ula_|video_|vram_address[10]~2_combout ), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hB830; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y31_N29 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N4 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N5 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N6 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|Add4~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFCFC; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N7 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y20_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X30_Y13_N27 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y13_N9 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: M9K_X33_Y9_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (!\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & !\z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0040; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y29_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \Selector1~0 ( -// Equation(s): -// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~16_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\Selector1~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~0 .lut_mask = 16'hBA98; -defparam \Selector1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \Selector1~1 ( -// Equation(s): -// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\Selector1~0_combout ), - .cin(gnd), - .combout(\Selector1~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~1 .lut_mask = 16'hBBC0; -defparam \Selector1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \D[1]~22 ( -// Equation(s): -// \D[1]~22_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector1~1_combout ))))) - - .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .datad(\Selector1~1_combout ), - .cin(gnd), - .combout(\D[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~22 .lut_mask = 16'h5140; -defparam \D[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \D[1]~23 ( -// Equation(s): -// \D[1]~23_combout = ((\z80_|memory_ifc_|nWR_out~0_combout ) # ((\D[1]~22_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[1]~22_combout ), - .cin(gnd), - .combout(\D[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~23 .lut_mask = 16'hFFDF; -defparam \D[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \D[1]~29 ( -// Equation(s): -// \D[1]~29_combout = (\D[1]~23_combout ) # ((\Equal2~0_combout & ((\z80_|address_pins_|abus[0]~18_combout ) # (\D[1]~28_combout )))) - - .dataa(\z80_|address_pins_|abus[0]~18_combout ), - .datab(\D[1]~28_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[1]~23_combout ), - .cin(gnd), - .combout(\D[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~29 .lut_mask = 16'hFFE0; -defparam \D[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \D[1]~31 ( -// Equation(s): -// \D[1]~31_combout = ((\D[1]~29_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\D[0]~30_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\D[1]~29_combout ), - .cin(gnd), - .combout(\D[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'hF755; -defparam \D[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N6 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[1]~31_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[1]~13_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[1]~13_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[1]~13_combout ), - .datad(\D[1]~31_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N8 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T3_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hAE0C; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N22 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .datad(\z80_|execute_|fMRead~36_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFEFA; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N7 -dffeas \z80_|data_pins_|dout[1] ( +// Location: FF_X31_Y16_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .asdata(vcc), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [1]), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[1] .power_up = "low"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~12 ( +// Location: LCCOMB_X30_Y20_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( // Equation(s): -// \z80_|bus_control_|db[1]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~12 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h0203; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( -// Equation(s): -// \z80_|bus_control_|db[0]~6_combout = ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (\z80_|execute_|ctl_bus_db_oe~combout )) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFFF5; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~13 ( -// Equation(s): -// \z80_|bus_control_|db[1]~13_combout = ((\z80_|bus_control_|db[1]~12_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [1]), - .datab(\z80_|bus_control_|db[1]~12_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~13 .lut_mask = 16'h8FCF; -defparam \z80_|bus_control_|db[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~5_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hFB33; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N17 -dffeas \z80_|ir_|opcode[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[1]~13_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y15_N29 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N20 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) +// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), + .combout(\z80_|address_pins_|abus[10]~24_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFF0; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y15_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( // Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [0]))) +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [0]), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datab(\z80_|address_latch_|abusz [11]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal36~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal36~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal36~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hAE0C; -defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y15_N27 -dffeas \z80_|decode_state_|DFFE_instCB ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), +// Location: FF_X31_Y16_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instCB~q ), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), .prn(vcc)); // synopsys translate_off -defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y15_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Location: LCCOMB_X30_Y20_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( // Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0004; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|pla_decode_|Equal50~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q ))) # (!\z80_|pla_decode_|Equal50~0_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & -// !\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal33~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0357; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mRead~9_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_mRead~9_combout & -// (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~11_combout & (\z80_|execute_|ctl_mWrite~9_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mWrite~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~11_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~3_combout & (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_bus_db_oe~6_combout & \z80_|execute_|ctl_mWrite~12_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_mWrite~14_combout ) # (((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~14_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hDCFF; -defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X50_Y16_N29 -dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~15_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N18 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q - - .dataa(gnd), + .dataa(\z80_|address_pins_|DFFE_apin_latch [11]), .datab(gnd), .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .combout(\z80_|address_pins_|abus[11]~19_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N19 -dffeas \z80_|memory_ifc_|wait_mwr ( +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) + + .dataa(\z80_|address_latch_|abusz [12]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mwr~q ), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N0 -cycloneive_lcell_comb \z80_|memory_ifc_|mwr_wr~feeder ( +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( // Equation(s): -// \z80_|memory_ifc_|mwr_wr~feeder_combout = \z80_|memory_ifc_|wait_mwr~q +// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(gnd), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mwr~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [12]), .cin(gnd), - .combout(\z80_|memory_ifc_|mwr_wr~feeder_combout ), + .combout(\z80_|address_pins_|abus[12]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|mwr_wr~feeder .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N1 -dffeas \z80_|memory_ifc_|mwr_wr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|mwr_wr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|mwr_wr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N4 -cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~4_combout & \z80_|memory_ifc_|iorq~0_combout )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|mwr_wr~q ), - .datac(\z80_|execute_|fIOWrite~4_combout ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nWR_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hFCCC; -defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N30 -cycloneive_lcell_comb \D[0]~30 ( -// Equation(s): -// \D[0]~30_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cin(gnd), - .combout(\D[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~30 .lut_mask = 16'hFF40; -defparam \D[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 +// Location: M9K_X33_Y11_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -42483,7 +38071,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .ena1(vcc), @@ -42491,10 +38079,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -42532,26 +38120,1177 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), - .cout()); +// Location: FF_X32_Y14_N31 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[13]~20_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hE6C4; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y16_N0 +// Location: FF_X32_Y14_N1 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0200; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: FF_X29_Y14_N5 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0C00; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \D[6]~90 ( +// Equation(s): +// \D[6]~90_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\D[6]~90_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~90 .lut_mask = 16'hCCE2; +defparam \D[6]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N16 +cycloneive_lcell_comb \D[6]~91 ( +// Equation(s): +// \D[6]~91_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~90_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~90_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~90_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[6]~90_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\D[6]~91_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~91 .lut_mask = 16'hF838; +defparam \D[6]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0020; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y24_N16 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N20 +cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [4]), + .cin(gnd), + .combout(\ula_|video_|vram_address[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N4 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N21 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y33_N19 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N0 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N1 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N26 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N27 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N28 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'hA50F; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N29 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N2 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N4 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N6 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N8 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y33_N9 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N10 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y33_N11 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N12 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y33_N13 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N14 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N22 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) + + .dataa(gnd), + .datab(\ula_|video_|Add4~12_combout ), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hCCF0; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N14 +cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( +// Equation(s): +// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N23 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N16 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [8]), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) + + .dataa(\ula_|video_|Add4~14_combout ), + .datab(gnd), + .datac(\ula_|video_|Add4~2_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hAAF0; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N21 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N30 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & (\ula_|video_|vga_hc [1]))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|Add4~4_combout ), + .datab(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|vram_address[10]~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N31 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) + + .dataa(gnd), + .datab(\ula_|video_|Add4~12_combout ), + .datac(gnd), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFCC; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N17 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N26 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|Add4~14_combout ) # (\ula_|video_|vga_hc [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|Add4~14_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N27 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N23 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y14_N1 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -42561,16 +39300,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -42624,7 +39363,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y13_N0 +// Location: M9K_X33_Y33_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(vcc), .portare(vcc), @@ -42634,16 +39373,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -42682,7 +39421,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; // synopsys translate_on -// Location: M9K_X33_Y13_N0 +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \D[6]~87 ( +// Equation(s): +// \D[6]~87_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\D[6]~87_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~87 .lut_mask = 16'hE6A2; +defparam \D[6]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y1_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portawe(vcc), .portare(vcc), @@ -42692,16 +39449,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -42740,3739 +39497,175 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; // synopsys translate_on -// Location: M9K_X33_Y17_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \Selector6~0 ( -// Equation(s): -// \Selector6~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector6~0 .lut_mask = 16'hAEA4; -defparam \Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N0 -cycloneive_lcell_comb \D[6]~70 ( -// Equation(s): -// \D[6]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector6~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\Selector6~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector6~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datad(\Selector6~0_combout ), - .cin(gnd), - .combout(\D[6]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~70 .lut_mask = 16'hBBC0; -defparam \D[6]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \D[6]~71 ( -// Equation(s): -// \D[6]~71_combout = ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\D[6]~70_combout )))) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\z80_|memory_ifc_|nRD_out~2_combout ), - .datad(\D[6]~70_combout ), - .cin(gnd), - .combout(\D[6]~71_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~71 .lut_mask = 16'hBF8F; -defparam \D[6]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G19 -cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2]}), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk )); -// synopsys translate_off -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock"; -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~77_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[3]~21_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[3]~21_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\D[3]~77_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N11 -dffeas \z80_|data_pins_|dout[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~64 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~64_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~64 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[5][4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~101_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[5][4]~64_combout & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~101_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~101 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[3][3]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~102 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~102_combout = (\ula_|zx_keyboard_|keys[3][3]~101_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~101_combout & (\ula_|zx_keyboard_|keys[3][3]~q )) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~101_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~102_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~102 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[3][3]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N3 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~102_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'hCCCF; -defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~104 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~104_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~104 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[2][3]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~135 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~135_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[2][3]~104_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[2][3]~104_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~135_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~135 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[2][3]~135 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~105_combout = (\ula_|zx_keyboard_|keys[2][3]~135_combout & (!\ula_|zx_keyboard_|keys[2][3]~103_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~135_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~135_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~105 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N17 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~105_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \D[3]~55 ( -// Equation(s): -// \D[3]~55_combout = (\z80_|address_pins_|abus[11]~21_combout & (((\z80_|address_pins_|abus[10]~22_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~21_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~22_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~21_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~q ), - .datac(\z80_|address_pins_|abus[10]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[2][3]~q ), - .cin(gnd), - .combout(\D[3]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~55 .lut_mask = 16'hB0BB; -defparam \D[3]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~21_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~95_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][3]~94_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~95 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[1][3]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~96_combout = (\ula_|zx_keyboard_|keys[1][3]~95_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][3]~95_combout & ((\ula_|zx_keyboard_|keys[1][3]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|keys[1][3]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~96_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~96 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[1][3]~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N9 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~96_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~97 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~97_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~97 .lut_mask = 16'hAAEE; -defparam \ula_|zx_keyboard_|keys[2][4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~99_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [6])))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~99_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~99 .lut_mask = 16'h0220; -defparam \ula_|zx_keyboard_|keys[0][4]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~100 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~100_combout = (\ula_|zx_keyboard_|keys[0][3]~98_combout & ((\ula_|zx_keyboard_|keys[0][4]~99_combout & (!\ula_|zx_keyboard_|keys[2][4]~97_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~99_combout & -// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][3]~98_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~99_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~100 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N31 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~100_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \D[3]~54 ( -// Equation(s): -// \D[3]~54_combout = (\z80_|address_pins_|abus[8]~20_combout & (((\z80_|address_pins_|abus[9]~19_combout )) # (!\ula_|zx_keyboard_|keys[1][3]~q ))) # (!\z80_|address_pins_|abus[8]~20_combout & (!\ula_|zx_keyboard_|keys[0][3]~q & -// ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[1][3]~q ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\z80_|address_pins_|abus[9]~19_combout ), - .cin(gnd), - .combout(\D[3]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~54 .lut_mask = 16'hAF23; -defparam \D[3]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~79_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[3][0]~79_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~136 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~136_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), - .datab(\ula_|zx_keyboard_|Selector5~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~136_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~136 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~136 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~109 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~109_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~108_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~136_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[4][3]~136_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~108_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~109_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~109 .lut_mask = 16'hEA40; -defparam \ula_|zx_keyboard_|keys[4][3]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~137 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~137_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~137_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~137 .lut_mask = 16'hFF02; -defparam \ula_|zx_keyboard_|keys[4][3]~137 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~110 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~110_combout = (\ula_|zx_keyboard_|keys[4][3]~109_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|zx_keyboard_|keys[4][3]~137_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & -// ((\ula_|zx_keyboard_|keys[4][3]~q ))))) # (!\ula_|zx_keyboard_|keys[4][3]~109_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~109_combout ), - .datab(\ula_|zx_keyboard_|keys[4][3]~137_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~110_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~110 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][3]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N19 -dffeas \ula_|zx_keyboard_|keys[4][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][3]~110_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~106 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~106_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~106 .lut_mask = 16'h00C0; -defparam \ula_|zx_keyboard_|keys[5][3]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~107 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~107_combout = (\ula_|zx_keyboard_|keys[1][4]~25_combout & ((\ula_|zx_keyboard_|keys[5][3]~106_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][3]~106_combout & ((\ula_|zx_keyboard_|keys[5][3]~q -// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|keys[5][3]~106_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~107_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~107 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][3]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y14_N17 -dffeas \ula_|zx_keyboard_|keys[5][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~107_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N26 -cycloneive_lcell_comb \D[3]~56 ( -// Equation(s): -// \D[3]~56_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][3]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[5][3]~q ), - .cin(gnd), - .combout(\D[3]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~56 .lut_mask = 16'h8ACF; -defparam \D[3]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~115 ( +cycloneive_lcell_comb \D[6]~88 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~115_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) +// \D[6]~88_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~87_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~87_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~87_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~115_combout ), + .combout(\D[6]~88_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~115 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][3]~115 .sum_lutc_input = "datac"; +defparam \D[6]~88 .lut_mask = 16'h22D8; +defparam \D[6]~88 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~116 ( +cycloneive_lcell_comb \D[6]~89 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~116_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~115_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[7][2]~32_combout & ((\ula_|ps2_keyboard_|shiftreg [2])))) +// \D[6]~89_combout = (\D[6]~87_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~88_combout )))) # (!\D[6]~87_combout & +// (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \D[6]~88_combout )))) - .dataa(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datab(\ula_|zx_keyboard_|keys[6][3]~115_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\D[6]~87_combout ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\D[6]~88_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~116_combout ), + .combout(\D[6]~89_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~116 .lut_mask = 16'hCCA0; -defparam \ula_|zx_keyboard_|keys[6][3]~116 .sum_lutc_input = "datac"; +defparam \D[6]~89 .lut_mask = 16'hC3C8; +defparam \D[6]~89 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~139 ( +cycloneive_lcell_comb \D[6]~111 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~139_combout = (((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout )) # (!\ula_|zx_keyboard_|keys[6][3]~116_combout ) +// \D[6]~111_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[6]~91_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[6]~89_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[6]~91_combout )) - .dataa(\ula_|zx_keyboard_|keys[6][3]~116_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), + .dataa(\D[6]~91_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\D[6]~89_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~139_combout ), + .combout(\D[6]~111_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~139 .lut_mask = 16'hFF7F; -defparam \ula_|zx_keyboard_|keys[6][3]~139 .sum_lutc_input = "datac"; +defparam \D[6]~111 .lut_mask = 16'hAEA2; +defparam \D[6]~111 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(gnd), +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \D[6]~86 ( +// Equation(s): +// \D[6]~86_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(gnd), + .datac(\raw_loader_in~input_o ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector13~0_combout ), + .combout(\D[6]~86_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hF2F2; -defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; +defparam \D[6]~86 .lut_mask = 16'hFAFF; +defparam \D[6]~86 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~140 ( +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \D[6]~100 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~140_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~139_combout & (\ula_|zx_keyboard_|keys[6][3]~q )) # (!\ula_|zx_keyboard_|keys[6][3]~139_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout -// ))))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) +// \D[6]~100_combout = ((\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout ))) # (!\Equal2~1_combout ) - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[6][3]~139_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), + .dataa(\Equal2~1_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[6]~111_combout ), + .datad(\D[6]~86_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~140_combout ), + .combout(\D[6]~100_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~140 .lut_mask = 16'hD0F2; -defparam \ula_|zx_keyboard_|keys[6][3]~140 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N9 -dffeas \ula_|zx_keyboard_|keys[6][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~140_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFCF0; -defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h00CC; -defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~62_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hF080; -defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; +defparam \D[6]~100 .lut_mask = 16'hFD75; +defparam \D[6]~100 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( +cycloneive_lcell_comb \D[6]~101 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & ((\ula_|zx_keyboard_|keys[7][3]~q ))) +// \D[6]~101_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [6] & \D[6]~100_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[6]~100_combout )) # (!\Equal2~1_combout ))) - .dataa(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [6]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[6]~100_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .combout(\D[6]~101_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; +defparam \D[6]~101 .lut_mask = 16'hCF05; +defparam \D[6]~101 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N5 -dffeas \ula_|zx_keyboard_|keys[7][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N16 -cycloneive_lcell_comb \D[3]~57 ( -// Equation(s): -// \D[3]~57_combout = (\ula_|zx_keyboard_|keys[6][3]~q & (\z80_|address_pins_|abus[14]~16_combout & ((\z80_|address_pins_|abus[15]~17_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~q & -// (((\z80_|address_pins_|abus[15]~17_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[6][3]~q ), - .datab(\ula_|zx_keyboard_|keys[7][3]~q ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\D[3]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~57 .lut_mask = 16'hF531; -defparam \D[3]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N16 -cycloneive_lcell_comb \D[3]~58 ( -// Equation(s): -// \D[3]~58_combout = (\D[3]~55_combout & (\D[3]~54_combout & (\D[3]~56_combout & \D[3]~57_combout ))) - - .dataa(\D[3]~55_combout ), - .datab(\D[3]~54_combout ), - .datac(\D[3]~56_combout ), - .datad(\D[3]~57_combout ), - .cin(gnd), - .combout(\D[3]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~58 .lut_mask = 16'h8000; -defparam \D[3]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y31_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hBBC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; -// synopsys translate_on - -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; -// synopsys translate_on - -// Location: M9K_X33_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N18 -cycloneive_lcell_comb \Selector3~0 ( -// Equation(s): -// \Selector3~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector3~0 .lut_mask = 16'hCEC2; -defparam \Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N12 -cycloneive_lcell_comb \Selector3~1 ( -// Equation(s): -// \Selector3~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\Selector3~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector3~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\Selector3~0_combout ), - .cin(gnd), - .combout(\Selector3~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector3~1 .lut_mask = 16'hBBC0; -defparam \Selector3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N6 -cycloneive_lcell_comb \D[3]~52 ( -// Equation(s): -// \D[3]~52_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector3~1_combout ))))) - - .dataa(\z80_|address_pins_|abus[15]~17_combout ), - .datab(\Equal2~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), - .datad(\Selector3~1_combout ), - .cin(gnd), - .combout(\D[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~52 .lut_mask = 16'h3120; -defparam \D[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N20 -cycloneive_lcell_comb \D[3]~53 ( -// Equation(s): -// \D[3]~53_combout = (\z80_|memory_ifc_|nWR_out~0_combout ) # (((\D[3]~52_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|memory_ifc_|nRD_out~2_combout )) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~52_combout ), - .cin(gnd), - .combout(\D[3]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~53 .lut_mask = 16'hFFBF; -defparam \D[3]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N10 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\D[3]~53_combout ) # ((\Equal2~0_combout & ((\z80_|address_pins_|abus[0]~18_combout ) # (\D[3]~58_combout )))) - - .dataa(\z80_|address_pins_|abus[0]~18_combout ), - .datab(\D[3]~58_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[3]~53_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'hFFE0; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N24 -cycloneive_lcell_comb \D[3]~77 ( -// Equation(s): -// \D[3]~77_combout = ((\D[3]~76_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\z80_|data_pins_|dout [3]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[0]~30_combout ), - .datad(\D[3]~76_combout ), - .cin(gnd), - .combout(\D[3]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~77 .lut_mask = 16'hBF0F; -defparam \D[3]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N0 -cycloneive_lcell_comb \ula_|always0~0 ( -// Equation(s): -// \ula_|always0~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [0])) - - .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|always0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|always0~0 .lut_mask = 16'h0808; -defparam \ula_|always0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N2 -cycloneive_lcell_comb \ula_|always0~1 ( -// Equation(s): -// \ula_|always0~1_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|always0~0_combout ), - .cin(gnd), - .combout(\ula_|always0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|always0~1 .lut_mask = 16'h2000; -defparam \ula_|always0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y15_N25 -dffeas \ula_|pcm_outl[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[3]~77_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|pcm_outl [13]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y17_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|mclk_r~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y17_N5 -dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|mclk_r~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) - - .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add0~1_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; -defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) -// \ula_|i2s_intf_|Add0~3 = CARRY((!\ula_|i2s_intf_|lrdivider [1] & !\ula_|i2s_intf_|Add0~1_cout )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~1_cout ), - .combout(\ula_|i2s_intf_|Add0~2_combout ), - .cout(\ula_|i2s_intf_|Add0~3 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add0~2_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N29 -dffeas \ula_|i2s_intf_|lrdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) -// \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) - - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~3 ), - .combout(\ula_|i2s_intf_|Add0~4_combout ), - .cout(\ula_|i2s_intf_|Add0~5 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~4_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N5 -dffeas \ula_|i2s_intf_|lrdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) -// \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~5 ), - .combout(\ula_|i2s_intf_|Add0~6_combout ), - .cout(\ula_|i2s_intf_|Add0~7 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; -defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~6_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; -defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y15_N1 -dffeas \ula_|i2s_intf_|lrdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) -// \ula_|i2s_intf_|Add0~9 = CARRY((\ula_|i2s_intf_|lrdivider [4]) # (!\ula_|i2s_intf_|Add0~7 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~7 ), - .combout(\ula_|i2s_intf_|Add0~8_combout ), - .cout(\ula_|i2s_intf_|Add0~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; -defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N25 -dffeas \ula_|i2s_intf_|lrdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) -// \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) - - .dataa(\ula_|i2s_intf_|lrdivider [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~9 ), - .combout(\ula_|i2s_intf_|Add0~10_combout ), - .cout(\ula_|i2s_intf_|Add0~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; -defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[5]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y16_N17 -dffeas \ula_|i2s_intf_|lrdivider[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) -// \ula_|i2s_intf_|Add0~13 = CARRY((!\ula_|i2s_intf_|Add0~11 ) # (!\ula_|i2s_intf_|lrdivider [6])) - - .dataa(\ula_|i2s_intf_|lrdivider [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~11 ), - .combout(\ula_|i2s_intf_|Add0~12_combout ), - .cout(\ula_|i2s_intf_|Add0~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~12_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[6]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y16_N15 -dffeas \ula_|i2s_intf_|lrdivider[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) -// \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) - - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~13 ), - .combout(\ula_|i2s_intf_|Add0~14_combout ), - .cout(\ula_|i2s_intf_|Add0~15 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; -defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y16_N1 -dffeas \ula_|i2s_intf_|lrdivider[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) -// \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [8]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~15 ), - .combout(\ula_|i2s_intf_|Add0~16_combout ), - .cout(\ula_|i2s_intf_|Add0~17 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add0~16_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N25 -dffeas \ula_|i2s_intf_|lrdivider[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrdivider [9]), - .cin(\ula_|i2s_intf_|Add0~17 ), - .combout(\ula_|i2s_intf_|Add0~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; -defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~18_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; -defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N21 -dffeas \ula_|i2s_intf_|lrdivider[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|lrdivider [8]))) - - .dataa(\ula_|i2s_intf_|lrdivider [6]), - .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [7]), - .datad(\ula_|i2s_intf_|lrdivider [8]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0080; -defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( -// Equation(s): -// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|lrdivider [4]))) - - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(\ula_|i2s_intf_|lrdivider [3]), - .datac(\ula_|i2s_intf_|lrdivider [5]), - .datad(\ula_|i2s_intf_|lrdivider [4]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h0080; -defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( -// Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~0_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~1_combout ))) - - .dataa(\ula_|i2s_intf_|Equal0~0_combout ), - .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; -defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] -// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .cout(\ula_|i2s_intf_|bitcount[0]~6 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; -defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(\ula_|i2s_intf_|bitcount [2]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h33C3; -defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add2~7_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0033; -defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) -// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~7_cout ), - .combout(\ula_|i2s_intf_|Add2~8_combout ), - .cout(\ula_|i2s_intf_|Add2~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (\ula_|i2s_intf_|Add2~8_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|Add2~8_combout ), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h020A; -defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N25 -dffeas \ula_|i2s_intf_|bdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) -// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) - - .dataa(\ula_|i2s_intf_|bdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~9 ), - .combout(\ula_|i2s_intf_|Add2~10_combout ), - .cout(\ula_|i2s_intf_|Add2~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[8]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|Add2~10_combout ), - .datac(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h000B; -defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N13 -dffeas \ula_|i2s_intf_|bdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) -// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - - .dataa(\ula_|i2s_intf_|bdivider [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~11 ), - .combout(\ula_|i2s_intf_|Add2~12_combout ), - .cout(\ula_|i2s_intf_|Add2~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|Add2~12_combout ), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h020A; -defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N27 -dffeas \ula_|i2s_intf_|bdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~19_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(\ula_|i2s_intf_|Add2~13 ), - .combout(\ula_|i2s_intf_|Add2~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; -defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[8]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .datad(\ula_|i2s_intf_|Add2~14_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N11 -dffeas \ula_|i2s_intf_|bdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (\ula_|i2s_intf_|bdivider [4] & (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & \ula_|i2s_intf_|bdivider [2]))) - - .dataa(\ula_|i2s_intf_|bdivider [4]), - .datab(\ula_|i2s_intf_|bdivider [1]), - .datac(\ula_|i2s_intf_|bdivider [3]), - .datad(\ula_|i2s_intf_|bdivider [2]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0200; -defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[8]~1 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[8]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bitcount [4]), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(\ula_|i2s_intf_|LessThan0~0_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8]~1 .lut_mask = 16'hC400; -defparam \ula_|i2s_intf_|shiftreg[8]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[8]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .datac(\ula_|i2s_intf_|bdivider [0]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; -defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N29 -dffeas \ula_|i2s_intf_|bdivider[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; -defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) - - .dataa(\ula_|i2s_intf_|bclk_r~0_combout ), - .datab(\ula_|i2s_intf_|Equal1~1_combout ), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00B8; -defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bclk_r~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N15 -dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[8]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hAFAA; -defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N1 -dffeas \ula_|i2s_intf_|bitcount[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) -// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[0]~6 ), - .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .cout(\ula_|i2s_intf_|bitcount[1]~8 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N3 -dffeas \ula_|i2s_intf_|bitcount[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) -// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[1]~8 ), - .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .cout(\ula_|i2s_intf_|bitcount[2]~10 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N5 -dffeas \ula_|i2s_intf_|bitcount[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) -// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[2]~10 ), - .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .cout(\ula_|i2s_intf_|bitcount[3]~12 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N7 -dffeas \ula_|i2s_intf_|bitcount[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [4]), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2s_intf_|bitcount[3]~12 ), - .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; -defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N9 -dffeas \ula_|i2s_intf_|bitcount[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~19_combout = (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & (\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bitcount [4]), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|Equal1~1_combout ), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h3010; -defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X23_Y34_N22 -cycloneive_io_ibuf \AUD_ADCDAT~input ( - .i(AUD_ADCDAT), - .ibar(gnd), - .o(\AUD_ADCDAT~input_o )); -// synopsys translate_off -defparam \AUD_ADCDAT~input .bus_hold = "false"; -defparam \AUD_ADCDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) - - .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [0]), - .datad(\AUD_ADCDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; -defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N3 -dffeas \ula_|i2s_intf_|shiftreg[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[8]~2 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[8]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[8]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8]~2 .lut_mask = 16'hFAAA; -defparam \ula_|i2s_intf_|shiftreg[8]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N1 -dffeas \ula_|i2s_intf_|shiftreg[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N19 -dffeas \ula_|i2s_intf_|shiftreg[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N29 -dffeas \ula_|i2s_intf_|shiftreg[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N27 -dffeas \ula_|i2s_intf_|shiftreg[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~15_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(\ula_|i2s_intf_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0A0A; -defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N21 -dffeas \ula_|i2s_intf_|shiftreg[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~14_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N15 -dffeas \ula_|i2s_intf_|shiftreg[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~13_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [6]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N25 -dffeas \ula_|i2s_intf_|shiftreg[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~11_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [7]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N11 -dffeas \ula_|i2s_intf_|shiftreg[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~11_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [8]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N9 -dffeas \ula_|i2s_intf_|shiftreg[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~10_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [9]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N31 -dffeas \ula_|i2s_intf_|shiftreg[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~9_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(\ula_|i2s_intf_|shiftreg [10]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0A0A; -defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N13 -dffeas \ula_|i2s_intf_|shiftreg[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~8_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~7_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [11]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [11]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N23 -dffeas \ula_|i2s_intf_|shiftreg[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~7_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; -defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N21 -dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( -// Equation(s): -// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|PCM_INR [14])))) # -// (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (((\ula_|i2s_intf_|PCM_INR [14])))) - - .dataa(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|shiftreg [14]), - .cin(gnd), - .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hF870; -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N19 -dffeas \ula_|i2s_intf_|PCM_INR[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|PCM_INR [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \ula_|ula_data~0 ( -// Equation(s): -// \ula_|ula_data~0_combout = (\ula_|i2s_intf_|PCM_INL [14]) # (\ula_|i2s_intf_|PCM_INR [14]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|PCM_INR [14]), - .cin(gnd), - .combout(\ula_|ula_data~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ula_data~0 .lut_mask = 16'hFFF0; -defparam \ula_|ula_data~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N3 -dffeas \ula_|pcm_outl[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ula_data~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|pcm_outl [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) - - .dataa(\ula_|i2s_intf_|shiftreg [12]), - .datab(\ula_|pcm_outl [12]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hCACA; -defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N17 -dffeas \ula_|i2s_intf_|shiftreg[13] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [13]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) - - .dataa(\ula_|pcm_outl [13]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [13]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hB8B8; -defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N9 -dffeas \ula_|i2s_intf_|shiftreg[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( -// Equation(s): -// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) - - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N5 -dffeas \ula_|i2s_intf_|PCM_INL[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|PCM_INL [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \D[6]~72 ( -// Equation(s): -// \D[6]~72_combout = (!\z80_|address_pins_|abus[0]~18_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (!\ula_|i2s_intf_|PCM_INL [14] & !\ula_|i2s_intf_|PCM_INR [14]))) - - .dataa(\z80_|address_pins_|abus[0]~18_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|PCM_INR [14]), - .cin(gnd), - .combout(\D[6]~72_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~72 .lut_mask = 16'h0004; -defparam \D[6]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \D[6]~73 ( -// Equation(s): -// \D[6]~73_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Equal2~0_combout & ((\D[6]~72_combout ))) # (!\Equal2~0_combout & (!\D[6]~71_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\Equal2~0_combout ), - .datac(\D[6]~71_combout ), - .datad(\D[6]~72_combout ), - .cin(gnd), - .combout(\D[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~73 .lut_mask = 16'h8A02; -defparam \D[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \D[6]~74 ( -// Equation(s): -// \D[6]~74_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (((\z80_|data_pins_|dout [6])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) # (!\z80_|memory_ifc_|nWR_out~0_combout & (!\D[6]~73_combout & ((\z80_|data_pins_|dout [6]) # -// (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\D[6]~73_combout ), - .cin(gnd), - .combout(\D[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~74 .lut_mask = 16'hA2F3; -defparam \D[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 -cycloneive_lcell_comb \D[6]~81 ( -// Equation(s): -// \D[6]~81_combout = (\D[6]~74_combout ) # (!\D[0]~30_combout ) - - .dataa(\D[0]~30_combout ), - .datab(\D[6]~74_combout ), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\D[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~81 .lut_mask = 16'hDDDD; -defparam \D[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 +// Location: LCCOMB_X32_Y13_N12 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~81_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~7_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[6]~7_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~101_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & +// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[6]~7_combout ), - .datad(\D[6]~81_combout ), + .datab(\D[6]~101_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[6]~9_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N1 +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # +// ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|fIORead~3_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|fIORead~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hDC50; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|execute_|fMRead~35_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N13 dffeas \z80_|data_pins_|dout[6] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), @@ -46491,44 +39684,61 @@ defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~5 ( +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( // Equation(s): -// \z80_|bus_control_|db[6]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|db[6]~15_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~5 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[6]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~7 ( -// Equation(s): -// \z80_|bus_control_|db[6]~7_combout = ((\z80_|bus_control_|db[6]~5_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(\z80_|bus_control_|db[6]~8_combout ), .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[6]~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[6]~7_combout ), + .combout(\z80_|bus_control_|db[6]~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[6]~7 .lut_mask = 16'hDF0F; -defparam \z80_|bus_control_|db[6]~7 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'h8AFF; +defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N19 +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~9_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[6]~9_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N9 dffeas \z80_|ir_|opcode[6] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[6]~7_combout ), + .d(\z80_|ir_|opcode[6]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -46544,3371 +39754,239 @@ defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y15_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( +// Location: LCCOMB_X37_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( // Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), + .combout(\z80_|pla_decode_|Equal41~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h4400; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Location: LCCOMB_X38_Y16_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( // Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) +// \z80_|pla_decode_|Equal41~1_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [5]))) - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), + .combout(\z80_|pla_decode_|Equal41~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Location: LCCOMB_X38_Y16_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( // Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) +// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_sw_1d~8_combout ), + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal41~1_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .combout(\z80_|pla_decode_|Equal41~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X40_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( // Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_2d~9_combout & \z80_|execute_|ctl_sw_1d~4_combout ))) +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal41~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_1d~5_combout ), - .datac(\z80_|execute_|ctl_sw_2d~9_combout ), - .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFF08; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Location: LCCOMB_X34_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( // Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|execute_|ctl_66_oe~2_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) +// \z80_|alu_|db_high[1]~15_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'h7555; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_high [1]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~23_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~17_combout ))) + + .dataa(\z80_|alu_|db[6]~23_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[4]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[1]~17_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[5]~25_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[1]~17_combout ), + .datac(\z80_|alu_|db[5]~25_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = (\z80_|alu_|db_high[1]~15_combout & (\z80_|alu_|db_high[1]~16_combout & ((\z80_|alu_|db_high[1]~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[1]~15_combout ), + .datab(\z80_|alu_|db_high[1]~16_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[1]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~20 ( +// Equation(s): +// \z80_|alu_|db_high[1]~20_combout = ((\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~20 .lut_mask = 16'hA8FF; +defparam \z80_|alu_|db_high[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[5]~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db[5]~25 ( +// Equation(s): +// \z80_|alu_|db[5]~25_combout = ((\z80_|alu_|db[5]~24_combout & ((\z80_|alu_|db_high[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db_high[1]~20_combout ), + .datab(\z80_|alu_|db[7]~26_combout ), + .datac(\z80_|alu_|db[5]~24_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~25 .lut_mask = 16'hB3F3; +defparam \z80_|alu_|db[5]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N14 +cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Equation(s): +// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7733; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( -// Equation(s): -// \z80_|alu_control_|db[6]~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_flags_oe~2_combout ) # (\z80_|execute_|ctl_66_oe~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_66_oe~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFFC; -defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( -// Equation(s): -// \z80_|alu_control_|db[6]~11_combout = (\z80_|execute_|ctl_sw_1d~7_combout ) # ((\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_reg_out_lo~8_combout ) # (\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|alu_control_|db[6]~10_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFFFE; -defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~20 ( -// Equation(s): -// \z80_|alu_control_|db[2]~20_combout = (\z80_|alu_|db[2]~12_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & (\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_|db[2]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~20 .lut_mask = 16'h7530; -defparam \z80_|alu_control_|db[2]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hF4F0; -defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~21 ( -// Equation(s): -// \z80_|alu_control_|db[2]~21_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[2]~11_combout ), - .datab(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~21 .lut_mask = 16'h08CC; -defparam \z80_|alu_control_|db[2]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~22 ( -// Equation(s): -// \z80_|alu_control_|db[2]~22_combout = ((!\z80_|alu_control_|db[2]~20_combout & (\z80_|alu_control_|db[2]~21_combout & \z80_|alu_control_|db[2]~19_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[2]~20_combout ), - .datac(\z80_|alu_control_|db[2]~21_combout ), - .datad(\z80_|alu_control_|db[2]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~22 .lut_mask = 16'h7555; -defparam \z80_|alu_control_|db[2]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~10 ( -// Equation(s): -// \z80_|bus_control_|db[2]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|db[2]~22_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~10 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h0A0A; -defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~59 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~59_combout = (\ula_|zx_keyboard_|keys[5][2]~58_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][2]~58_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~59_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~59 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][2]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \ula_|zx_keyboard_|keys[5][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~59_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~133_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][2]~60_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~133 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[4][2]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~132_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~132 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][4]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~61 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~61_combout = (\ula_|zx_keyboard_|keys[4][2]~133_combout & ((\ula_|zx_keyboard_|keys[3][4]~132_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~132_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~133_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][2]~133_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~132_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~61 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N23 -dffeas \ula_|zx_keyboard_|keys[4][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~61_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N6 -cycloneive_lcell_comb \D[2]~34 ( -// Equation(s): -// \D[2]~34_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|keys[4][2]~q ), - .cin(gnd), - .combout(\D[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~34 .lut_mask = 16'h8CAF; -defparam \D[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h000C; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~51_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N21 -dffeas \ula_|zx_keyboard_|keys[3][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~55_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~55 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[1][4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~56_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|Equal0~2_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h3000; -defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~57_combout = (\ula_|zx_keyboard_|keys[1][4]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~56_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~56_combout & ((\ula_|zx_keyboard_|keys[2][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~55_combout & (((\ula_|zx_keyboard_|keys[2][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][4]~55_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~57_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~57 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[2][2]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \ula_|zx_keyboard_|keys[2][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~57_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \D[2]~33 ( -// Equation(s): -// \D[2]~33_combout = (\z80_|address_pins_|abus[10]~22_combout & (((\z80_|address_pins_|abus[11]~21_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) # (!\z80_|address_pins_|abus[10]~22_combout & (!\ula_|zx_keyboard_|keys[2][2]~q & -// ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\z80_|address_pins_|abus[10]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[3][2]~q ), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\z80_|address_pins_|abus[11]~21_combout ), - .cin(gnd), - .combout(\D[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~33 .lut_mask = 16'hAF23; -defparam \D[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~48 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~48_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[6][4]~21_combout & \ula_|zx_keyboard_|keys[6][4]~47_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~48 .lut_mask = 16'h4400; -defparam \ula_|zx_keyboard_|keys[1][2]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[1][2]~48_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][2]~48_combout & (\ula_|zx_keyboard_|keys[1][2]~q )) - - .dataa(\ula_|zx_keyboard_|keys[1][2]~48_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h0303; -defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & (\ula_|zx_keyboard_|keys[0][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N1 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N26 -cycloneive_lcell_comb \D[2]~32 ( -// Equation(s): -// \D[2]~32_combout = (\z80_|address_pins_|abus[8]~20_combout & (((\z80_|address_pins_|abus[9]~19_combout )) # (!\ula_|zx_keyboard_|keys[1][2]~q ))) # (!\z80_|address_pins_|abus[8]~20_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & -// ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[1][2]~q ), - .datac(\z80_|address_pins_|abus[9]~19_combout ), - .datad(\ula_|zx_keyboard_|keys[0][2]~q ), - .cin(gnd), - .combout(\D[2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~32 .lut_mask = 16'hA2F3; -defparam \D[2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~63_combout = (\ula_|zx_keyboard_|keys[7][2]~62_combout & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~63 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~65_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~63_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~64_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[7][2]~63_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'hF800; -defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (\ula_|zx_keyboard_|keys[7][2]~65_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~67_combout = (\ula_|zx_keyboard_|keys[7][2]~66_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~66_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][2]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~67 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][2]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N29 -dffeas \ula_|zx_keyboard_|keys[7][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~67_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~68 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~68_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~68_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~68 .lut_mask = 16'hF3F0; -defparam \ula_|zx_keyboard_|keys[5][0]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~70_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~69_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~71_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & ((\ula_|zx_keyboard_|keys[6][2]~70_combout & (!\ula_|zx_keyboard_|keys[5][0]~68_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~70_combout & -// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~41_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~68_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~71 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][2]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N29 -dffeas \ula_|zx_keyboard_|keys[6][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~71_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N30 -cycloneive_lcell_comb \D[2]~35 ( -// Equation(s): -// \D[2]~35_combout = (\ula_|zx_keyboard_|keys[7][2]~q & (\z80_|address_pins_|abus[15]~17_combout & ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~q & -// (((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~q ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(\z80_|address_pins_|abus[14]~16_combout ), - .cin(gnd), - .combout(\D[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~35 .lut_mask = 16'hDD0D; -defparam \D[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \D[2]~36 ( -// Equation(s): -// \D[2]~36_combout = (\D[2]~34_combout & (\D[2]~33_combout & (\D[2]~32_combout & \D[2]~35_combout ))) - - .dataa(\D[2]~34_combout ), - .datab(\D[2]~33_combout ), - .datac(\D[2]~32_combout ), - .datad(\D[2]~35_combout ), - .cin(gnd), - .combout(\D[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~36 .lut_mask = 16'h8000; -defparam \D[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \D[2]~83 ( -// Equation(s): -// \D[2]~83_combout = (\Equal2~0_combout & ((\D[2]~36_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) - - .dataa(\D[2]~36_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[2]~83_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~83 .lut_mask = 16'hFB00; -defparam \D[2]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hF4A4; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y23_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .lut_mask = 16'hEC64; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; -// synopsys translate_on - -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \Selector0~0 ( -// Equation(s): -// \Selector0~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .cin(gnd), - .combout(\Selector0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector0~0 .lut_mask = 16'hCEC2; -defparam \Selector0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \Selector0~1 ( -// Equation(s): -// \Selector0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\Selector0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector0~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datac(\Selector0~0_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\Selector0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector0~1 .lut_mask = 16'hDAD0; -defparam \Selector0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N30 -cycloneive_lcell_comb \D[2]~37 ( -// Equation(s): -// \D[2]~37_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector0~1_combout ))))) - - .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), - .datad(\Selector0~1_combout ), - .cin(gnd), - .combout(\D[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~37 .lut_mask = 16'h5140; -defparam \D[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \D[2]~38 ( -// Equation(s): -// \D[2]~38_combout = (((\D[2]~37_combout ) # (\z80_|memory_ifc_|nWR_out~0_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[2]~37_combout ), - .datad(\z80_|memory_ifc_|nWR_out~0_combout ), - .cin(gnd), - .combout(\D[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~38 .lut_mask = 16'hFFF7; -defparam \D[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \D[2]~39 ( -// Equation(s): -// \D[2]~39_combout = (\D[2]~83_combout & (((\z80_|data_pins_|dout [2])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) # (!\D[2]~83_combout & (\D[2]~38_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) - - .dataa(\D[2]~83_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\D[2]~38_combout ), - .cin(gnd), - .combout(\D[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~39 .lut_mask = 16'hF3A2; -defparam \D[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \D[2]~40 ( -// Equation(s): -// \D[2]~40_combout = (\D[2]~39_combout ) # (!\D[0]~30_combout ) - - .dataa(\D[2]~39_combout ), - .datab(gnd), - .datac(\D[0]~30_combout ), - .datad(gnd), - .cin(gnd), - .combout(\D[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~40 .lut_mask = 16'hAFAF; -defparam \D[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[2]~40_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[2]~11_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~11_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\D[2]~40_combout ), - .datad(\z80_|bus_control_|db[2]~11_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N31 -dffeas \z80_|data_pins_|dout[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~11 ( -// Equation(s): -// \z80_|bus_control_|db[2]~11_combout = ((\z80_|bus_control_|db[2]~10_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[2]~10_combout ), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~11 .lut_mask = 16'hB3BB; -defparam \z80_|bus_control_|db[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N31 -dffeas \z80_|ir_|opcode[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[2]~11_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00AA; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|pla_decode_|Equal3~2_combout & (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal3~2_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N3 -dffeas \z80_|decode_state_|DFFE_instIY1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_inst4~q )) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0404; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (!\z80_|execute_|ctl_bus_db_oe~2_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h33FF; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_bus_db_oe~4_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & ((\z80_|execute_|ctl_bus_db_oe~3_combout ) # ((\z80_|execute_|ctl_bus_db_oe~5_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), .datad(\z80_|execute_|ctl_sw_1d~6_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .combout(\z80_|sw1_|db_down[5]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hEFCC; +defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h2080; -defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~84 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~84_combout = (\ula_|zx_keyboard_|keys[5][0]~83_combout & (!\ula_|zx_keyboard_|keys[5][0]~68_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~83_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[5][0]~68_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~84 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[5][0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N3 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~84_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'hFF50; -defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'h0160; -defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~87_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~85_combout & (!\ula_|zx_keyboard_|keys[4][0]~86_combout )) # (!\ula_|zx_keyboard_|keys[4][0]~85_combout & -// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~87 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N21 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~87_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N14 -cycloneive_lcell_comb \D[0]~45 ( -// Equation(s): -// \D[0]~45_combout = (\ula_|zx_keyboard_|keys[5][0]~q & (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~q ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[4][0]~q ), - .cin(gnd), - .combout(\D[0]~45_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~45 .lut_mask = 16'hC4F5; -defparam \D[0]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~81_combout = (\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][0]~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|zx_keyboard_|released~q )))) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & (((\ula_|zx_keyboard_|keys[2][0]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~81 .lut_mask = 16'hF074; -defparam \ula_|zx_keyboard_|keys[2][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N21 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~81_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~80_combout = (\ula_|zx_keyboard_|keys[3][0]~79_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][0]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][0]~79_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~80 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N31 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N22 -cycloneive_lcell_comb \D[0]~44 ( -// Equation(s): -// \D[0]~44_combout = (\ula_|zx_keyboard_|keys[2][0]~q & (\z80_|address_pins_|abus[10]~22_combout & ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\ula_|zx_keyboard_|keys[2][0]~q & -// (((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[2][0]~q ), - .datab(\z80_|address_pins_|abus[10]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\z80_|address_pins_|abus[11]~21_combout ), - .cin(gnd), - .combout(\D[0]~44_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~44 .lut_mask = 16'hDD0D; -defparam \D[0]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~134 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~134_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[3][0]~79_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~134_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~134 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[7][0]~134 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h000F; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|WideOr16~3_combout & (\ula_|zx_keyboard_|keys[5][4]~64_combout & !\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|WideOr16~3_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & ((\ula_|zx_keyboard_|keys[7][0]~134_combout ) # (\ula_|zx_keyboard_|keys[7][0]~88_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[7][0]~134_combout ), - .datac(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'hA800; -defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~90 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~90_combout = (\ula_|zx_keyboard_|keys[7][0]~89_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~89_combout & ((\ula_|zx_keyboard_|keys[7][0]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~90_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~90 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[7][0]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N31 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~90_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0C0C; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|shifted~1_combout & \ula_|zx_keyboard_|keys[6][0]~91_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datac(\ula_|zx_keyboard_|shifted~1_combout ), - .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~93_combout = (\ula_|zx_keyboard_|keys[6][0]~92_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][0]~92_combout & (\ula_|zx_keyboard_|keys[6][0]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~93 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N15 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~93_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \D[0]~46 ( -// Equation(s): -// \D[0]~46_combout = (\ula_|zx_keyboard_|keys[7][0]~q & (\z80_|address_pins_|abus[15]~17_combout & ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][0]~q )))) # (!\ula_|zx_keyboard_|keys[7][0]~q & -// ((\z80_|address_pins_|abus[14]~16_combout ) # ((!\ula_|zx_keyboard_|keys[6][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~q ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\D[0]~46_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~46 .lut_mask = 16'hCF45; -defparam \D[0]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg -// [1] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8180; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~77_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~77 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~74_combout = (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~74 .lut_mask = 16'h8888; -defparam \ula_|zx_keyboard_|keys[4][3]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// ((\ula_|ps2_keyboard_|shiftreg [2]))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0510; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~75_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~21_combout )) # (!\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .datac(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~75 .lut_mask = 16'h0F77; -defparam \ula_|zx_keyboard_|keys~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~76_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~74_combout & !\ula_|zx_keyboard_|keys~75_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~74_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|keys~75_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~76 .lut_mask = 16'h30B0; -defparam \ula_|zx_keyboard_|keys[0][0]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~78 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~78_combout = (\ula_|zx_keyboard_|keys~77_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~77_combout & ((\ula_|zx_keyboard_|keys[0][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[0][0]~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys~77_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~76_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~78_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~78 .lut_mask = 16'hD1F0; -defparam \ula_|zx_keyboard_|keys[0][0]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N7 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~78_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~25_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~73 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~73_combout = (\ula_|zx_keyboard_|keys[1][0]~72_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~72_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~73_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~73 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[1][0]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y14_N11 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~73_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N24 -cycloneive_lcell_comb \D[0]~43 ( -// Equation(s): -// \D[0]~43_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~20_combout & ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & -// (((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), - .datab(\z80_|address_pins_|abus[8]~20_combout ), - .datac(\z80_|address_pins_|abus[9]~19_combout ), - .datad(\ula_|zx_keyboard_|keys[1][0]~q ), - .cin(gnd), - .combout(\D[0]~43_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~43 .lut_mask = 16'hD0DD; -defparam \D[0]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \D[0]~47 ( -// Equation(s): -// \D[0]~47_combout = (\D[0]~45_combout & (\D[0]~44_combout & (\D[0]~46_combout & \D[0]~43_combout ))) - - .dataa(\D[0]~45_combout ), - .datab(\D[0]~44_combout ), - .datac(\D[0]~46_combout ), - .datad(\D[0]~43_combout ), - .cin(gnd), - .combout(\D[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~47 .lut_mask = 16'h8000; -defparam \D[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .lut_mask = 16'hF588; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \Selector2~0 ( -// Equation(s): -// \Selector2~0_combout = (\z80_|address_pins_|abus[14]~16_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector2~0 .lut_mask = 16'hBA98; -defparam \Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \Selector2~1 ( -// Equation(s): -// \Selector2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector2~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\Selector2~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector2~0_combout )))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datad(\Selector2~0_combout ), - .cin(gnd), - .combout(\Selector2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector2~1 .lut_mask = 16'hF388; -defparam \Selector2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \D[0]~41 ( -// Equation(s): -// \D[0]~41_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector2~1_combout ))))) - - .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), - .datad(\Selector2~1_combout ), - .cin(gnd), - .combout(\D[0]~41_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~41 .lut_mask = 16'h5140; -defparam \D[0]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \D[0]~42 ( -// Equation(s): -// \D[0]~42_combout = ((\z80_|memory_ifc_|nWR_out~0_combout ) # ((\D[0]~41_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[0]~41_combout ), - .cin(gnd), - .combout(\D[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~42 .lut_mask = 16'hFFDF; -defparam \D[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N18 -cycloneive_lcell_comb \D[0]~48 ( -// Equation(s): -// \D[0]~48_combout = (\D[0]~42_combout ) # ((\Equal2~0_combout & ((\D[0]~47_combout ) # (\z80_|address_pins_|abus[0]~18_combout )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|address_pins_|abus[0]~18_combout ), - .datac(\D[0]~42_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~48 .lut_mask = 16'hFEF0; -defparam \D[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \D[0]~49 ( -// Equation(s): -// \D[0]~49_combout = ((\D[0]~48_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\D[0]~30_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\D[0]~48_combout ), - .cin(gnd), - .combout(\D[0]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~49 .lut_mask = 16'hF755; -defparam \D[0]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[0]~49_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[0]~15_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[0]~15_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[0]~49_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~15_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N15 -dffeas \z80_|data_pins_|dout[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~14 ( -// Equation(s): -// \z80_|bus_control_|db[0]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(gnd), - .datac(\z80_|data_pins_|dout [0]), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~14 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~15 ( -// Equation(s): -// \z80_|bus_control_|db[0]~15_combout = ((\z80_|bus_control_|db[0]~14_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~14_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~15 .lut_mask = 16'hCF4F; -defparam \z80_|bus_control_|db[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N1 -dffeas \z80_|ir_|opcode[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[0]~15_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hAB00; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mWrite~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # -// (!\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~4_combout & (\z80_|execute_|setM1~56_combout & \z80_|execute_|ctl_sw_2u~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~4_combout ), - .datac(\z80_|execute_|setM1~56_combout ), - .datad(\z80_|execute_|ctl_sw_2u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((\z80_|execute_|ctl_sw_2u~5_combout & !\z80_|execute_|ctl_reg_gp_sel~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h3B00; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N8 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[5]~1_combout = (\z80_|bus_control_|db[5]~17_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|bus_control_|db[5]~17_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|execute_|ctl_sw_1d~6_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[5]~1 .lut_mask = 16'hFBAA; -defparam \z80_|sw1_|db_down[5]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N0 +// Location: LCCOMB_X36_Y11_N22 cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( // Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[5]~29_combout ) # ((\z80_|alu_|db_high[1]~7_combout & \z80_|execute_|ctl_flags_alu~16_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (\z80_|alu_|db_high[1]~7_combout & ((\z80_|execute_|ctl_flags_alu~16_combout )))) +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|alu_control_|db[5]~15_combout +// & (\z80_|alu_|db_high[1]~20_combout & ((\z80_|execute_|ctl_flags_alu~15_combout )))) - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_|db_high[1]~7_combout ), - .datac(\z80_|alu_control_|db[5]~29_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .dataa(\z80_|alu_control_|db[5]~15_combout ), + .datab(\z80_|alu_|db_high[1]~20_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), .cin(gnd), .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), .cout()); @@ -49917,7 +39995,7 @@ defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y15_N1 +// Location: FF_X36_Y11_N23 dffeas \z80_|alu_flags_|flags_yf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), @@ -49936,133 +40014,76 @@ defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; defparam \z80_|alu_flags_|flags_yf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~27 ( +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( // Equation(s): -// \z80_|alu_control_|db[5]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) +// \z80_|alu_control_|db[5]~13_combout = (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|flags_yf~q & (!\z80_|execute_|ctl_flags_oe~2_combout & +// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .dataa(\z80_|alu_flags_|flags_yf~q ), .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|flags_yf~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|out[6]~2_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~27_combout ), + .combout(\z80_|alu_control_|db[5]~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~27 .lut_mask = 16'hFC54; -defparam \z80_|alu_control_|db[5]~27 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hAF8C; +defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~28 ( +// Location: LCCOMB_X34_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( // Equation(s): -// \z80_|alu_control_|db[5]~28_combout = (\z80_|sw1_|db_down[5]~1_combout & (\z80_|alu_control_|db[5]~27_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) +// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|sw1_|db_down[5]~1_combout ), + .dataa(\z80_|sw1_|db_down[5]~0_combout ), + .datab(\z80_|alu_control_|db[5]~13_combout ), .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datad(\z80_|alu_control_|db[5]~27_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~28_combout ), + .combout(\z80_|alu_control_|db[5]~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~28 .lut_mask = 16'hC400; -defparam \z80_|alu_control_|db[5]~28 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; +defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~29 ( +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( // Equation(s): -// \z80_|alu_control_|db[5]~29_combout = ((\z80_|alu_control_|db[5]~28_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) +// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~25_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(\z80_|alu_control_|db[5]~28_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_|db[5]~24_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .dataa(\z80_|alu_control_|db[6]~11_combout ), + .datab(\z80_|alu_|db[5]~25_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[5]~14_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~29_combout ), + .combout(\z80_|alu_control_|db[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~29 .lut_mask = 16'hB3BB; -defparam \z80_|alu_control_|db[5]~29 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hDF55; +defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N28 -cycloneive_lcell_comb \D[5]~68 ( +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \D[0]~107 ( // Equation(s): -// \D[5]~68_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) +// \D[0]~107_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout ))) - .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), .cin(gnd), - .combout(\D[5]~68_combout ), + .combout(\D[0]~107_combout ), .cout()); // synopsys translate_off -defparam \D[5]~68 .lut_mask = 16'h0040; -defparam \D[5]~68 .sum_lutc_input = "datac"; +defparam \D[0]~107 .lut_mask = 16'hFF40; +defparam \D[0]~107 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y11_N0 +// Location: M9K_X22_Y6_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -50070,7 +40091,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), .ena1(vcc), @@ -50078,10 +40099,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50119,7 +40140,7 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y30_N0 +// Location: M9K_X22_Y9_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -50127,7 +40148,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), .ena1(vcc), @@ -50135,10 +40156,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50176,7 +40197,7 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; // synopsys translate_on -// Location: M9K_X33_Y32_N0 +// Location: M9K_X22_Y7_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -50184,7 +40205,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .ena1(vcc), @@ -50192,10 +40213,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50233,103 +40254,102 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Location: LCCOMB_X29_Y10_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hFC22; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hAFC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(vcc), +// Location: M9K_X33_Y23_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y24_N0 +// Location: LCCOMB_X29_Y10_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -50339,16 +40359,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -50402,7 +40422,65 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y6_N0 +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -50412,16 +40490,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50460,7 +40538,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: M9K_X33_Y23_N0 +// Location: M9K_X33_Y29_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), .portare(vcc), @@ -50470,16 +40548,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -50532,104 +40610,104 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N6 +// Location: LCCOMB_X29_Y10_N0 cycloneive_lcell_comb \Mux2~0 ( // Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) +// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .cin(gnd), .combout(\Mux2~0_combout ), .cout()); // synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hCEC2; +defparam \Mux2~0 .lut_mask = 16'hBA98; defparam \Mux2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N12 +// Location: LCCOMB_X29_Y10_N2 cycloneive_lcell_comb \Mux2~1 ( // Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # (!\Mux2~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) +// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), .datad(\Mux2~0_combout ), .cin(gnd), .combout(\Mux2~1_combout ), .cout()); // synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hF588; +defparam \Mux2~1 .lut_mask = 16'hBBC0; defparam \Mux2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N2 -cycloneive_lcell_comb \D[5]~88 ( +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \D[5]~110 ( // Equation(s): -// \D[5]~88_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux2~1_combout ))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )))) +// \D[5]~110_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), .datad(\Mux2~1_combout ), .cin(gnd), - .combout(\D[5]~88_combout ), + .combout(\D[5]~110_combout ), .cout()); // synopsys translate_off -defparam \D[5]~88 .lut_mask = 16'hBA8A; -defparam \D[5]~88 .sum_lutc_input = "datac"; +defparam \D[5]~110 .lut_mask = 16'hAEA2; +defparam \D[5]~110 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N10 -cycloneive_lcell_comb \D[5]~69 ( +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \D[5]~85 ( // Equation(s): -// \D[5]~69_combout = (\D[5]~68_combout & (\D[5]~88_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~68_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) +// \D[5]~85_combout = (\D[5]~84_combout & (\D[5]~110_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout ))) - .dataa(\D[5]~68_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .dataa(\D[5]~84_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), .datac(\z80_|data_pins_|dout [5]), - .datad(\D[5]~88_combout ), + .datad(\D[5]~110_combout ), .cin(gnd), - .combout(\D[5]~69_combout ), + .combout(\D[5]~85_combout ), .cout()); // synopsys translate_off -defparam \D[5]~69 .lut_mask = 16'hF351; -defparam \D[5]~69 .sum_lutc_input = "datac"; +defparam \D[5]~85 .lut_mask = 16'hF351; +defparam \D[5]~85 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N14 -cycloneive_lcell_comb \D[5]~80 ( +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \D[5]~99 ( // Equation(s): -// \D[5]~80_combout = (\D[5]~69_combout ) # (!\D[0]~30_combout ) +// \D[5]~99_combout = (\D[5]~85_combout ) # (!\D[0]~107_combout ) - .dataa(gnd), + .dataa(\D[0]~107_combout ), .datab(gnd), - .datac(\D[0]~30_combout ), - .datad(\D[5]~69_combout ), + .datac(gnd), + .datad(\D[5]~85_combout ), .cin(gnd), - .combout(\D[5]~80_combout ), + .combout(\D[5]~99_combout ), .cout()); // synopsys translate_off -defparam \D[5]~80 .lut_mask = 16'hFF0F; -defparam \D[5]~80 .sum_lutc_input = "datac"; +defparam \D[5]~99 .lut_mask = 16'hFF55; +defparam \D[5]~99 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N22 +// Location: LCCOMB_X32_Y13_N14 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[5]~80_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~17_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[5]~17_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[5]~15_combout ) # ((\D[5]~99_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[5]~99_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[5]~17_combout ), - .datad(\D[5]~80_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[5]~99_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), .cout()); @@ -50638,7 +40716,7 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N23 +// Location: FF_X32_Y13_N15 dffeas \z80_|data_pins_|dout[5] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), @@ -50657,49 +40735,49 @@ defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~16 ( +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( // Equation(s): -// \z80_|bus_control_|db[5]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|bus_control_|db[0]~4_combout ), - .datab(\z80_|data_pins_|dout [5]), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [5]), + .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~16_combout ), + .combout(\z80_|bus_control_|db[5]~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~16 .lut_mask = 16'h88AA; -defparam \z80_|bus_control_|db[5]~16 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF300; +defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~17 ( +// Location: LCCOMB_X34_Y10_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( // Equation(s): -// \z80_|bus_control_|db[5]~17_combout = ((\z80_|bus_control_|db[5]~16_combout & ((\z80_|alu_control_|db[5]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|alu_control_|db[5]~29_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[5]~16_combout ), + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|alu_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[5]~14_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~17_combout ), + .combout(\z80_|bus_control_|db[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~17 .lut_mask = 16'hDF0F; -defparam \z80_|bus_control_|db[5]~17 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hF755; +defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N3 +// Location: FF_X34_Y10_N13 dffeas \z80_|ir_|opcode[5] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[5]~17_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|bus_control_|db[5]~15_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), @@ -50710,642 +40788,513 @@ defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( +// Location: LCCOMB_X37_Y15_N20 +cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( // Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [5])) +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|ir_|opcode [5] & +// ((\z80_|pla_decode_|Equal3~2_combout )))) - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3350; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N21 +dffeas \z80_|decode_state_|DFFE_inst4 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_inst4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N4 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Equation(s): +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), + .combout(\z80_|decode_state_|use_ixiy~combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h2020; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Location: LCCOMB_X34_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( // Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) +// \z80_|execute_|ctl_mRead~23_combout = (!\z80_|decode_state_|use_ixiy~combout & (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sel_wz~7_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~20_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( -// Equation(s): -// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|ctl_ir_we~12_combout ) # (((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|fMWrite~1_combout )) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|fMWrite~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hCFEF; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|fMRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .datab(\z80_|execute_|fMRead~15_combout ), - .datac(\z80_|execute_|fMRead~11_combout ), - .datad(\z80_|execute_|fMRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hAAEF; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( -// Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ctl_mRead~16_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|fMRead~27_combout ) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|fMRead~27_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'h0F8F; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( -// Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), .datad(\z80_|pla_decode_|Equal33~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), + .combout(\z80_|execute_|ctl_mRead~23_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hC800; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( -// Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|fMRead~30_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout ) # (\z80_|execute_|ctl_ir_we~9_combout )))) - - .dataa(\z80_|execute_|fMRead~30_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( -// Equation(s): -// \z80_|execute_|fMRead~29_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|execute_|nextM~6_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|nextM~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( -// Equation(s): -// \z80_|execute_|fMRead~32_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( -// Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~29_combout ) # ((\z80_|execute_|fMRead~32_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ))) - - .dataa(\z80_|execute_|fMRead~31_combout ), - .datab(\z80_|execute_|fMRead~29_combout ), - .datac(\z80_|execute_|fMRead~32_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( -// Equation(s): -// \z80_|execute_|fMRead~37_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~17_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h00A8; -defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N12 +// Location: LCCOMB_X39_Y18_N16 cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( // Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|ctl_mRead~17_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )))) # -// (!\z80_|execute_|ctl_alu_shift_oe~14_combout & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) +// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMWrite~3_combout )) - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|execute_|fMWrite~3_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~34_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFBFF; defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Location: LCCOMB_X41_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( // Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|fMRead~37_combout ) # (!\z80_|execute_|fMRead~34_combout ))) +// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) - .dataa(\z80_|execute_|fMRead~28_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~37_combout ), - .datad(\z80_|execute_|fMRead~34_combout ), + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), + .combout(\z80_|execute_|fMRead~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Location: LCCOMB_X37_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( // Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) +// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), + .combout(\z80_|execute_|fMRead~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC800; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Location: LCCOMB_X37_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( // Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~17_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_mRead~32_combout ))) +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) - .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|fMRead~29_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .datab(\z80_|execute_|fMRead~31_combout ), + .datac(\z80_|execute_|fMRead~30_combout ), + .datad(\z80_|execute_|fMRead~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~53_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datab(\z80_|execute_|ctl_inc_cy~77_combout ), + .datac(\z80_|execute_|ctl_inc_cy~53_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_mRead~23_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~23_combout ), .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), + .combout(\z80_|execute_|fMRead~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( -// Equation(s): -// \z80_|execute_|fMRead~20_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|fMRead~19_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|fMWrite~3_combout ), - .datad(\z80_|execute_|fMRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h0F0E; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N22 +// Location: LCCOMB_X39_Y18_N18 cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( // Equation(s): -// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~7_combout & !\z80_|pla_decode_|Equal6~1_combout ))) +// \z80_|execute_|fMRead~10_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0002; +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0100; defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Location: LCCOMB_X39_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( // Equation(s): -// \z80_|execute_|fMRead~17_combout = (((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~32_combout )) # (!\z80_|execute_|pc_inc_hold~18_combout )) # (!\z80_|execute_|nextM~4_combout ) +// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|pc_inc_hold~28_combout )) - .dataa(\z80_|execute_|nextM~4_combout ), - .datab(\z80_|execute_|pc_inc_hold~18_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|nextM~3_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), + .combout(\z80_|execute_|fMRead~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Location: LCCOMB_X39_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( // Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~17_combout )) # (!\z80_|execute_|fMRead~10_combout ))) - - .dataa(\z80_|execute_|fMRead~10_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( -// Equation(s): -// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~18_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|fMRead~21_combout ))) +// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|fMRead~10_combout ))) .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~21_combout ), - .datac(\z80_|execute_|fMRead~20_combout ), - .datad(\z80_|execute_|fMRead~18_combout ), + .datab(\z80_|execute_|fMRead~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|fMRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hAAA2; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fMRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_mRead~6_combout )))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|fMWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h00FE; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|fMRead~14_combout ), + .datab(\z80_|execute_|fMRead~11_combout ), + .datac(\z80_|execute_|fMRead~13_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Equation(s): +// \z80_|execute_|fMRead~20_combout = (((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~19_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datab(\z80_|execute_|fMRead~19_combout ), + .datac(\z80_|execute_|fMRead~15_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~48 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~48_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~48 .lut_mask = 16'hE0C0; +defparam \z80_|execute_|pc_inc_hold~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( +// Equation(s): +// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_mRead~18_combout & +// ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_mRead~18_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFAC8; defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y14_N8 +// Location: LCCOMB_X38_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|fMRead~2_combout ))) + + .dataa(\z80_|execute_|fMRead~2_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|fMRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N10 cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( // Equation(s): -// \z80_|execute_|fMRead~23_combout = (((\z80_|execute_|fMRead~22_combout ) # (!\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) +// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|pc_inc_hold~48_combout ) # ((\z80_|execute_|fMRead~22_combout ) # (\z80_|execute_|fMRead~21_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|pc_inc_hold~48_combout ), .datac(\z80_|execute_|fMRead~22_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), + .datad(\z80_|execute_|fMRead~21_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~23_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hFFFD; defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_mRead~38_combout ) # ((!\z80_|execute_|fMRead~5_combout ) # (!\z80_|execute_|fMRead~4_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|fMRead~4_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( -// Equation(s): -// \z80_|execute_|fMRead~25_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (((\z80_|execute_|ctl_mRead~20_combout ) # (\z80_|execute_|ctl_mRead~19_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (\z80_|execute_|ctl_ir_we~4_combout & -// ((\z80_|execute_|ctl_mRead~20_combout ) # (\z80_|execute_|ctl_mRead~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~39_combout = (\z80_|execute_|ixy_d~4_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'hF800; -defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N2 +// Location: LCCOMB_X36_Y12_N8 cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( // Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout ))) +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - .dataa(\z80_|execute_|fMRead~24_combout ), - .datab(\z80_|execute_|fMRead~25_combout ), - .datac(\z80_|execute_|pc_inc_hold~39_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hCCEC; defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( +// Location: LCCOMB_X38_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( // Equation(s): -// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~16_combout ) # ((\z80_|execute_|fMRead~35_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~26_combout ))) +// \z80_|execute_|fMRead~25_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|fMRead~24_combout ) - .dataa(\z80_|execute_|fMRead~16_combout ), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|execute_|fMRead~23_combout ), - .datad(\z80_|execute_|fMRead~26_combout ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|fMRead~24_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~36_combout ), + .combout(\z80_|execute_|fMRead~25_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'h2F0F; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y13_N28 +// Location: LCCOMB_X37_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~26_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|execute_|fMRead~3_combout ) + + .dataa(\z80_|execute_|fMRead~26_combout ), + .datab(\z80_|execute_|fMRead~3_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|fMRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~27_combout ))) + + .dataa(\z80_|execute_|fMRead~32_combout ), + .datab(\z80_|execute_|fMRead~20_combout ), + .datac(\z80_|execute_|fMRead~23_combout ), + .datad(\z80_|execute_|fMRead~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Equation(s): +// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|fMRead~0_combout ))) + + .dataa(\z80_|execute_|fMRead~34_combout ), + .datab(\z80_|execute_|fMRead~33_combout ), + .datac(\z80_|execute_|fMRead~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N30 cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( // Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~36_combout & \z80_|sequencer_|DFFE_T2_ff~q )) +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q )) - .dataa(\z80_|execute_|fMRead~36_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .dataa(gnd), + .datab(\z80_|execute_|fMRead~35_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), .cin(gnd), .combout(\z80_|pin_control_|bus_db_pin_re~combout ), .cout()); // synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hEECC; +defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y24_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), .ena1(vcc), @@ -51353,75 +41302,132 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), +// Location: LCCOMB_X32_Y14_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), .ena1(vcc), @@ -51429,68 +41435,125 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N2 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ) # -// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout )) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hBC8C; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC64; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), .portaaddrstall(gnd), @@ -51499,16 +41562,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51516,54 +41579,54 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -51572,56 +41635,56 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; // synopsys translate_on -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -51630,56 +41693,56 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; // synopsys translate_on -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), .portare(vcc), .portaaddrstall(gnd), @@ -51688,16 +41751,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51705,161 +41768,2152 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N0 -cycloneive_lcell_comb \Mux0~0 ( +// Location: LCCOMB_X32_Y18_N0 +cycloneive_lcell_comb \Selector1~0 ( // Equation(s): -// \Mux0~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~16_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~16_combout & -// ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) # (!\z80_|address_pins_|abus[14]~16_combout & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) +// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .cin(gnd), - .combout(\Mux0~0_combout ), + .combout(\Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hDC98; -defparam \Mux0~0 .sum_lutc_input = "datac"; +defparam \Selector1~0 .lut_mask = 16'hBA98; +defparam \Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N18 -cycloneive_lcell_comb \Mux0~1 ( +// Location: LCCOMB_X32_Y18_N2 +cycloneive_lcell_comb \Selector1~1 ( // Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) +// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\Selector1~0_combout ), .cin(gnd), - .combout(\Mux0~1_combout ), + .combout(\Selector1~1_combout ), .cout()); // synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hDDA0; -defparam \Mux0~1 .sum_lutc_input = "datac"; +defparam \Selector1~1 .lut_mask = 16'hBBC0; +defparam \Selector1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N24 -cycloneive_lcell_comb \D[7]~89 ( +// Location: LCCOMB_X32_Y18_N12 +cycloneive_lcell_comb \D[1]~103 ( // Equation(s): -// \D[7]~89_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )))) +// \D[1]~103_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector1~1_combout +// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), - .datad(\Mux0~1_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .datad(\Selector1~1_combout ), .cin(gnd), - .combout(\D[7]~89_combout ), + .combout(\D[1]~103_combout ), .cout()); // synopsys translate_off -defparam \D[7]~89 .lut_mask = 16'hF2D0; -defparam \D[7]~89 .sum_lutc_input = "datac"; +defparam \D[1]~103 .lut_mask = 16'hF2D0; +defparam \D[1]~103 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N8 -cycloneive_lcell_comb \D[7]~75 ( -// Equation(s): -// \D[7]~75_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~89_combout ) # (!\D[5]~68_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[7]~89_combout ) # (!\D[5]~68_combout )))) +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[5]~68_combout ), - .datad(\D[7]~89_combout ), +// Location: CLKCTRL_G5 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), .cin(gnd), - .combout(\D[7]~75_combout ), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), .cout()); // synopsys translate_off -defparam \D[7]~75 .lut_mask = 16'hBB0B; -defparam \D[7]~75 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N16 -cycloneive_lcell_comb \D[7]~82 ( -// Equation(s): -// \D[7]~82_combout = (\D[7]~75_combout ) # (!\D[0]~30_combout ) +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on - .dataa(\D[0]~30_combout ), +// Location: LCCOMB_X20_Y26_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), .datab(gnd), - .datac(\D[7]~75_combout ), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N1 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N7 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N21 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [5] & !\ula_|ps2_keyboard_|clk_filter [4]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [6]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [5]), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N29 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N23 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [3]))) + + .dataa(\ula_|ps2_keyboard_|Equal0~0_combout ), + .datab(\ula_|ps2_keyboard_|clk_filter [2]), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0002; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), .datad(gnd), .cin(gnd), - .combout(\D[7]~82_combout ), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), .cout()); // synopsys translate_off -defparam \D[7]~82 .lut_mask = 16'hF5F5; -defparam \D[7]~82 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Location: FF_X20_Y26_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[7]~82_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[7]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[7]~9_combout ))) +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[7]~9_combout ), - .datad(\D[7]~82_combout ), + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFC30; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N27 -dffeas \z80_|data_pins_|dout[7] ( +// Location: FF_X20_Y26_N27 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0C00; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N5 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N3 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N1 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & +// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N17 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & +// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [3]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N27 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\PS2_DAT~input_o ), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCCC0; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|always1~0_combout ), + .datab(\ula_|ps2_keyboard_|bit_count [0]), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00D0; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N9 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N15 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [8]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N11 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N11 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N25 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N29 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N1 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [1]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|Equal0~0_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF300; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) + + .dataa(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datab(\PS2_DAT~input_o ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N9 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y20_N1 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~15_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & !\ula_|ps2_keyboard_|shiftreg [7])) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0202; +defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[0][0]~15_combout )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q )) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( +// Equation(s): +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|released~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hC8F0; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N19 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y21_N3 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hFF88; +defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0003; +defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[5][1]~38_combout & (!\ula_|zx_keyboard_|keys[5][1]~35_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & +// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N19 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~31_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h00CC; +defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~23_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~23 .lut_mask = 16'h1010; +defparam \ula_|zx_keyboard_|keys[7][1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[7][2]~32_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q +// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), + .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N9 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \D[1]~30 ( +// Equation(s): +// \D[1]~30_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][1]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~30 .lut_mask = 16'hBB0B; +defparam \D[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hA0A0; +defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~24_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00C0; +defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N17 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & \ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h4040; +defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N17 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; +defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0060; +defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2040; +defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & +// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y21_N7 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|scan_code_ready~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~19 .lut_mask = 16'h0100; +defparam \ula_|zx_keyboard_|keys[7][4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~20 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~20 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[6][4]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~21 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~21_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[6][4]~20_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~21 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[1][1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|zx_keyboard_|keys[1][1]~21_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][1]~21_combout & (\ula_|zx_keyboard_|keys[1][1]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[1][1]~21_combout ), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N13 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~22_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N2 +cycloneive_lcell_comb \D[1]~28 ( +// Equation(s): +// \D[1]~28_combout = (\ula_|zx_keyboard_|keys[0][1]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) # (!\ula_|zx_keyboard_|keys[0][1]~q & +// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][1]~q ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\ula_|zx_keyboard_|keys[1][1]~q ), + .cin(gnd), + .combout(\D[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~28 .lut_mask = 16'hD0DD; +defparam \D[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N26 +cycloneive_lcell_comb \D[1]~29 ( +// Equation(s): +// \D[1]~29_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~28_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~q ), + .datab(\ula_|zx_keyboard_|key_row~0_combout ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\D[1]~28_combout ), + .cin(gnd), + .combout(\D[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~29 .lut_mask = 16'hC400; +defparam \D[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~41_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~42_combout )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; +defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & ((!\ula_|zx_keyboard_|keys[6][1]~40_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N25 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~45_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [7]))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [7]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0002; +defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; +defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0044; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0140; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hF022; +defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~5_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|WideOr16~5_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF808; +defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N31 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N20 +cycloneive_lcell_comb \D[1]~31 ( +// Equation(s): +// \D[1]~31_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~q ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\ula_|zx_keyboard_|keys[7][1]~q ), + .cin(gnd), + .combout(\D[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~31 .lut_mask = 16'hB0BB; +defparam \D[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N18 +cycloneive_lcell_comb \D[1]~32 ( +// Equation(s): +// \D[1]~32_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~30_combout & (\D[1]~29_combout & \D[1]~31_combout ))) + + .dataa(\D[1]~30_combout ), + .datab(\z80_|address_pins_|abus[0]~16_combout ), + .datac(\D[1]~29_combout ), + .datad(\D[1]~31_combout ), + .cin(gnd), + .combout(\D[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~32 .lut_mask = 16'hECCC; +defparam \D[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N4 +cycloneive_lcell_comb \D[1]~33 ( +// Equation(s): +// \D[1]~33_combout = ((\Equal2~0_combout & ((\D[1]~32_combout ))) # (!\Equal2~0_combout & (\D[1]~103_combout ))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[1]~103_combout ), + .datad(\D[1]~32_combout ), + .cin(gnd), + .combout(\D[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~33 .lut_mask = 16'hFB73; +defparam \D[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N8 +cycloneive_lcell_comb \D[1]~34 ( +// Equation(s): +// \D[1]~34_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout & \z80_|data_pins_|dout [1])))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[1]~33_combout ), + .datad(\z80_|data_pins_|dout [1]), + .cin(gnd), + .combout(\D[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~34 .lut_mask = 16'hF151; +defparam \D[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[1]~11_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\D[1]~34_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N19 +dffeas \z80_|data_pins_|dout[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -51868,51 +43922,68 @@ dffeas \z80_|data_pins_|dout[7] ( .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [7]), + .q(\z80_|data_pins_|dout [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[7] .power_up = "low"; +defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~8 ( +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( // Equation(s): -// \z80_|bus_control_|db[7]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - .dataa(\z80_|alu_control_|db[7]~18_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\z80_|alu_control_|db[1]~26_combout ), .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~8_combout ), + .combout(\z80_|bus_control_|db[1]~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~8 .lut_mask = 16'hAF00; -defparam \z80_|bus_control_|db[7]~8 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~9 ( +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( // Equation(s): -// \z80_|bus_control_|db[7]~9_combout = ((\z80_|bus_control_|db[7]~8_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|bus_control_|db[7]~8_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|bus_control_|db[1]~10_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~9_combout ), + .combout(\z80_|bus_control_|db[1]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~9 .lut_mask = 16'hB3F3; -defparam \z80_|bus_control_|db[7]~9 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD0FF; +defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N9 -dffeas \z80_|ir_|opcode[7] ( +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|ir_|opcode[1]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[1]~feeder_combout = \z80_|bus_control_|db[1]~11_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[1]~11_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N15 +dffeas \z80_|ir_|opcode[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[7]~9_combout ), + .d(\z80_|ir_|opcode[1]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -51921,666 +43992,2542 @@ dffeas \z80_|ir_|opcode[7] ( .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [7]), + .q(\z80_|ir_|opcode [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[7] .power_up = "low"; +defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y15_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( // Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), + .combout(\z80_|pla_decode_|Equal40~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Location: LCCOMB_X37_Y11_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( // Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0]))) +// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|ir_|opcode [0]), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .combout(\z80_|pla_decode_|Equal21~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y12_N19 -dffeas \z80_|interrupts_|im1 ( +// Location: LCCOMB_X39_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hC080; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~28_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|pla_decode_|Equal64~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h001F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h153F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0088; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h4000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_flags_cf_cpl~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h040C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout = (((!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .lut_mask = 16'h777F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h0F0C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC0E0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAA8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_nf_we~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & !\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ))) + + .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h0008; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h20A0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal10~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hCECC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~20_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFB3; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'h8500; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~21_combout )) + + .dataa(\z80_|alu_|db[7]~21_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[0]~19_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hF0AA; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout +// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h11D8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y9_N31 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0B00; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~14_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout )) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout )) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hF0E4; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout & \z80_|execute_|ctl_alu_op_low~28_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~12_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFF40; +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~19_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (\z80_|execute_|ctl_state_alu~7_combout )))) # (!\z80_|execute_|ctl_state_alu~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_state_alu~15_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h3F3B; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal68~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF32; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~12_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC0CC; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N4 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~9_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( +// Equation(s): +// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~17_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|bus_control_|db[0]~17_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h22A2; +defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N20 +cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( +// Equation(s): +// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~19_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_|db[0]~19_combout ), + .cin(gnd), + .combout(\z80_|sw2_|db_up[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hFF0F; +defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( +// Equation(s): +// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[0]~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|sw2_|db_up[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8A00; +defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( +// Equation(s): +// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[0]~9_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; +defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~67_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~67 .lut_mask = 16'hFF50; +defparam \ula_|zx_keyboard_|keys[5][0]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0420; +defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[5][0]~81_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h2800; +defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), + .datab(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h7474; +defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N11 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~83_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h0160; +defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'hBABA; +defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~84_combout & ((!\ula_|zx_keyboard_|keys[4][0]~85_combout ))) # (!\ula_|zx_keyboard_|keys[4][0]~84_combout & +// (\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N27 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~86_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \D[0]~49 ( +// Equation(s): +// \D[0]~49_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[5][0]~q ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[0]~49_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~49 .lut_mask = 16'hBB0B; +defparam \D[0]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|ps2_keyboard_|shiftreg [6])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & +// (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8810; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~76_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) + + .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~76 .lut_mask = 16'h3313; +defparam \ula_|zx_keyboard_|keys~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~73 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~73_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~73_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~73 .lut_mask = 16'hF000; +defparam \ula_|zx_keyboard_|keys[4][3]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// ((\ula_|ps2_keyboard_|shiftreg [2]))))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0310; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~74_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h353F; +defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~73_combout & !\ula_|zx_keyboard_|keys~74_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~73_combout ), + .datab(\ula_|zx_keyboard_|keys~74_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'h2F00; +defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~77_combout = (\ula_|zx_keyboard_|keys~76_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~75_combout & ((!\ula_|zx_keyboard_|released~q ))) # +// (!\ula_|zx_keyboard_|keys[0][0]~75_combout & (\ula_|zx_keyboard_|keys[0][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys~76_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~77 .lut_mask = 16'hB0F4; +defparam \ula_|zx_keyboard_|keys[0][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N15 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~71_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~71 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[1][0]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|zx_keyboard_|keys[1][0]~71_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][0]~71_combout & (\ula_|zx_keyboard_|keys[1][0]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[1][0]~71_combout ), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N17 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~72_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N30 +cycloneive_lcell_comb \D[0]~47 ( +// Equation(s): +// \D[0]~47_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & +// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\ula_|zx_keyboard_|keys[1][0]~q ), + .cin(gnd), + .combout(\D[0]~47_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~47 .lut_mask = 16'hD0DD; +defparam \D[0]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~80 .lut_mask = 16'hB1F0; +defparam \ula_|zx_keyboard_|keys[2][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N23 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~80_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~78 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|keys[3][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~79_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (\ula_|zx_keyboard_|keys[3][0]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][0]~78_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N5 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~79_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~1_combout = ((\z80_|address_pins_|DFFE_apin_latch [11]) # (!\ula_|zx_keyboard_|keys[3][0]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [11]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hFF3F; +defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N4 +cycloneive_lcell_comb \D[0]~48 ( +// Equation(s): +// \D[0]~48_combout = (\D[0]~47_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) + + .dataa(\D[0]~47_combout ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|key_row~1_combout ), + .cin(gnd), + .combout(\D[0]~48_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~48 .lut_mask = 16'h8A00; +defparam \D[0]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|shifted~1_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[6][0]~90_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|shifted~1_combout ), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|zx_keyboard_|keys[6][0]~91_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~91_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N21 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~92_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~63_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~63 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[5][4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0303; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[5][4]~63_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|WideOr16~3_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~132 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~132_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~132_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~132 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[7][0]~132 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & ((\ula_|zx_keyboard_|keys[7][0]~87_combout ) # (\ula_|zx_keyboard_|keys[7][0]~132_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~132_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h8880; +defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|zx_keyboard_|keys[7][0]~88_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~88_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) + + .dataa(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N7 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~89_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N28 +cycloneive_lcell_comb \D[0]~50 ( +// Equation(s): +// \D[0]~50_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~q ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~q ), + .cin(gnd), + .combout(\D[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~50 .lut_mask = 16'hB0BB; +defparam \D[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N10 +cycloneive_lcell_comb \D[0]~51 ( +// Equation(s): +// \D[0]~51_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~49_combout & (\D[0]~48_combout & \D[0]~50_combout ))) + + .dataa(\D[0]~49_combout ), + .datab(\z80_|address_pins_|abus[0]~16_combout ), + .datac(\D[0]~48_combout ), + .datad(\D[0]~50_combout ), + .cin(gnd), + .combout(\D[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~51 .lut_mask = 16'hECCC; +defparam \D[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N14 +cycloneive_lcell_comb \D[0]~55 ( +// Equation(s): +// \D[0]~55_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\D[0]~55_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~55 .lut_mask = 16'hE3E0; +defparam \D[0]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \D[0]~56 ( +// Equation(s): +// \D[0]~56_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~55_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\D[0]~55_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~55_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[0]~55_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\D[0]~56_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~56 .lut_mask = 16'hBCB0; +defparam \D[0]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \D[0]~52 ( +// Equation(s): +// \D[0]~52_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~23_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\D[0]~52_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~52 .lut_mask = 16'hF858; +defparam \D[0]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \D[0]~53 ( +// Equation(s): +// \D[0]~53_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ ((\D[0]~52_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & (((!\D[0]~52_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\z80_|address_pins_|abus[15]~22_combout ), + .datac(\D[0]~52_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\D[0]~53_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~53 .lut_mask = 16'h4B48; +defparam \D[0]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \D[0]~54 ( +// Equation(s): +// \D[0]~54_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~52_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~52_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~53_combout )) # (!\D[0]~52_combout & ((\D[0]~53_combout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[0]~52_combout ), + .datad(\D[0]~53_combout ), + .cin(gnd), + .combout(\D[0]~54_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~54 .lut_mask = 16'hC3E0; +defparam \D[0]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \D[0]~106 ( +// Equation(s): +// \D[0]~106_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~56_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~54_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[0]~56_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[0]~56_combout ), + .datad(\D[0]~54_combout ), + .cin(gnd), + .combout(\D[0]~106_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~106 .lut_mask = 16'hF4B0; +defparam \D[0]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \D[0]~57 ( +// Equation(s): +// \D[0]~57_combout = ((\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~1_combout ), + .datab(\D[0]~51_combout ), + .datac(\D[0]~106_combout ), + .datad(\Equal2~0_combout ), + .cin(gnd), + .combout(\D[0]~57_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~57 .lut_mask = 16'hDDF5; +defparam \D[0]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \D[0]~58 ( +// Equation(s): +// \D[0]~58_combout = (\D[0]~57_combout & (((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[0]~57_combout & (!\Equal2~1_combout & ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\D[0]~57_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\D[0]~58_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~58 .lut_mask = 16'hC0F5; +defparam \D[0]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~17_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\D[0]~58_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N1 +dffeas \z80_|data_pins_|dout[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Equation(s): +// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|data_pins_|dout [0]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hC0CC; +defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N28 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Equation(s): +// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~16_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF55; +defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y13_N27 +dffeas \z80_|ir_|opcode[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .asdata(\z80_|bus_control_|db[0]~17_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|im2~q ), - .datac(\z80_|interrupts_|im1~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hF400; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h5D50; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hCECF; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( -// Equation(s): -// \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|bus_control_|db[0]~4_combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'h88AA; -defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( -// Equation(s): -// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[3]~20_combout ), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hBB3B; -defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N23 -dffeas \z80_|ir_|opcode[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[3]~21_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [3]), + .q(\z80_|ir_|opcode [0]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[3] .power_up = "low"; +defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( +// Location: LCCOMB_X39_Y16_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( // Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .dataa(\z80_|ir_|opcode [0]), .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~1_combout ), + .combout(\z80_|pla_decode_|Equal63~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N20 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Location: LCCOMB_X40_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( // Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N20 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h070F; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( +// Equation(s): +// \z80_|alu_control_|db[6]~10_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) + + .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFF5; +defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( +// Equation(s): +// \z80_|alu_control_|db[6]~11_combout = (\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_sw_1d~7_combout ) # (\z80_|execute_|ctl_reg_out_lo~8_combout )) + + .dataa(\z80_|alu_control_|db[6]~10_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), + .combout(\z80_|alu_control_|db[6]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h1010; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFEFE; +defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N8 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( // Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|decode_state_|in_halt~q ))) +// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~17_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~17_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - .dataa(\z80_|pla_decode_|Equal77~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|decode_state_|in_halt~0_combout ), + .dataa(\z80_|alu_|db[4]~17_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), .cin(gnd), - .combout(\z80_|decode_state_|in_halt~1_combout ), + .combout(\z80_|alu_control_|db[4]~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hFF08; -defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; +defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y12_N9 -dffeas \z80_|decode_state_|in_halt ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|in_halt~1_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|in_halt~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; -defparam \z80_|decode_state_|in_halt .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal77~0_combout ))) +// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|alu_control_|db[4]~30_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .combout(\z80_|alu_control_|db[4]~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h00B0; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Location: LCCOMB_X32_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) +// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[4]~31_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .combout(\z80_|alu_control_|db[4]~32_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) +// \ula_|zx_keyboard_|keys[2][4]~119_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h0420; +defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Location: LCCOMB_X29_Y18_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = ((\z80_|execute_|ctl_bus_db_we~4_combout ) # ((!\z80_|execute_|ctl_apin_mux~0_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout ))) # (!\z80_|execute_|ctl_bus_db_we~5_combout ) +// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - .dataa(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datac(\z80_|execute_|ctl_sw_2u~3_combout ), - .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datab(\ula_|zx_keyboard_|keys[2][4]~119_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Location: LCCOMB_X29_Y18_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~95 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h2220; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_ir_we~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFE0; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~6_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_db_we~3_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~124_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~124 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[5][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~125 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~125_combout = (\ula_|zx_keyboard_|keys[5][4]~124_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & ((\ula_|zx_keyboard_|keys[5][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][4]~124_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) +// \ula_|zx_keyboard_|keys[2][4]~95_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[5][4]~124_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~125_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~125 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][4]~125 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N17 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~126_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [6])) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|shiftreg -// [6])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(gnd), + .datab(gnd), + .datac(\ula_|zx_keyboard_|shifted~q ), .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~126_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~95_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~126 .lut_mask = 16'h4422; -defparam \ula_|zx_keyboard_|keys[4][4]~126 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~95 .lut_mask = 16'hAFAA; +defparam \ula_|zx_keyboard_|keys[2][4]~95 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~127_combout = (\ula_|zx_keyboard_|keys[4][4]~126_combout & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[4][4]~126_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~127 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~128_combout = (\ula_|zx_keyboard_|keys[4][4]~127_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (\ula_|zx_keyboard_|keys[4][4]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][4]~127_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][4]~127_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~128 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][4]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N23 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~128_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \D[4]~64 ( -// Equation(s): -// \D[4]~64_combout = (\ula_|zx_keyboard_|keys[5][4]~q & (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][4]~q )))) # (!\ula_|zx_keyboard_|keys[5][4]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\D[4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~64 .lut_mask = 16'hCF45; -defparam \D[4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~119_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg -// [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~119 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[3][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~138 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~138_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|keys[3][4]~119_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~138_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~138 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[3][4]~138 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~120 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~120_combout = (\ula_|zx_keyboard_|keys[3][4]~132_combout & ((\ula_|zx_keyboard_|keys[3][4]~138_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][4]~138_combout & -// (\ula_|zx_keyboard_|keys[3][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][4]~132_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][4]~132_combout ), - .datab(\ula_|zx_keyboard_|keys[3][4]~138_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~120_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~120 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][4]~120 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N29 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~120_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 +// Location: LCCOMB_X29_Y18_N22 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~121 ( // Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|zx_keyboard_|keys[2][4]~120_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~120_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\ula_|zx_keyboard_|keys[2][4]~120_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[2][4]~121_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h50FA; defparam \ula_|zx_keyboard_|keys[2][4]~121 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y15_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|zx_keyboard_|keys[2][4]~121_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~122 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[2][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~123_combout = (\ula_|zx_keyboard_|keys[2][4]~122_combout & (!\ula_|zx_keyboard_|keys[2][4]~97_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~122_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[2][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~122_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~123 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N19 +// Location: FF_X29_Y18_N23 dffeas \ula_|zx_keyboard_|keys[2][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~123_combout ), + .d(\ula_|zx_keyboard_|keys[2][4]~121_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52596,46 +46543,80 @@ defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \D[4]~63 ( +// Location: LCCOMB_X29_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( // Equation(s): -// \D[4]~63_combout = (\z80_|address_pins_|abus[10]~22_combout & (((\z80_|address_pins_|abus[11]~21_combout )) # (!\ula_|zx_keyboard_|keys[3][4]~q ))) # (!\z80_|address_pins_|abus[10]~22_combout & (!\ula_|zx_keyboard_|keys[2][4]~q & -// ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][4]~q )))) +// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|extended~q ))) - .dataa(\z80_|address_pins_|abus[10]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[3][4]~q ), - .datac(\z80_|address_pins_|abus[11]~21_combout ), - .datad(\ula_|zx_keyboard_|keys[2][4]~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\D[4]~63_combout ), + .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), .cout()); // synopsys translate_off -defparam \D[4]~63 .lut_mask = 16'hA2F3; -defparam \D[4]~63 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~129 ( +// Location: LCCOMB_X29_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~136 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~129_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) +// \ula_|zx_keyboard_|keys[3][4]~136_combout = (\ula_|zx_keyboard_|keys[3][4]~117_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [4]))) - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .dataa(\ula_|zx_keyboard_|keys[3][4]~117_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~129_combout ), + .combout(\ula_|zx_keyboard_|keys[3][4]~136_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~129 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][4]~129 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][4]~136 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[3][4]~136 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y15_N25 -dffeas \ula_|zx_keyboard_|keys[7][4] ( +// Location: LCCOMB_X28_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~130_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~130 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[3][4]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|zx_keyboard_|keys[3][4]~136_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[3][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~136_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~136_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N9 +dffeas \ula_|zx_keyboard_|keys[3][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~129_combout ), + .d(\ula_|zx_keyboard_|keys[3][4]~118_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52644,52 +46625,124 @@ dffeas \ula_|zx_keyboard_|keys[7][4] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~130 ( +// Location: LCCOMB_X29_Y19_N18 +cycloneive_lcell_comb \D[4]~78 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~130_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) +// \D[4]~78_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~q ), + .cin(gnd), + .combout(\D[4]~78_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~78 .lut_mask = 16'h8ACF; +defparam \D[4]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~126_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~130_combout ), + .combout(\ula_|zx_keyboard_|keys[5][4]~128_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~130 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[6][4]~130 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][4]~128 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[5][4]~128 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~131 ( +// Location: LCCOMB_X28_Y19_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~129 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~131_combout = (\ula_|zx_keyboard_|keys[6][4]~130_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~130_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) +// \ula_|zx_keyboard_|keys[5][4]~129_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[5][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~128_combout & +// (\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[6][4]~130_combout ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~128_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~131_combout ), + .combout(\ula_|zx_keyboard_|keys[5][4]~129_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~131 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[6][4]~131 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][4]~129 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][4]~129 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y14_N31 +// Location: FF_X28_Y19_N9 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~129_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~127_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~20_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~20_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~127 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[6][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N5 dffeas \ula_|zx_keyboard_|keys[6][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~131_combout ), + .d(\ula_|zx_keyboard_|keys[6][4]~127_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52705,46 +46758,257 @@ defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \D[4]~65 ( +// Location: LCCOMB_X28_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( // Equation(s): -// \D[4]~65_combout = (\z80_|address_pins_|abus[15]~17_combout & (((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~17_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & -// ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) +// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - .dataa(\z80_|address_pins_|abus[15]~17_combout ), - .datab(\ula_|zx_keyboard_|keys[7][4]~q ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\ula_|zx_keyboard_|keys[6][4]~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), .cin(gnd), - .combout(\D[4]~65_combout ), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \D[4]~65 .lut_mask = 16'hB0BB; -defparam \D[4]~65 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~118 ( +// Location: LCCOMB_X28_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~118_combout = (\ula_|zx_keyboard_|keys[0][4]~99_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~99_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) +// \ula_|zx_keyboard_|keys[7][4]~51_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - .dataa(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~99_combout ), + .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) +// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~1_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N11 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N30 +cycloneive_lcell_comb \D[4]~79 ( +// Equation(s): +// \D[4]~79_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & +// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .cin(gnd), + .combout(\D[4]~79_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~79 .lut_mask = 16'h8ACF; +defparam \D[4]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & +// \ula_|zx_keyboard_|extended~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h4422; +defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][4]~122_combout ))) + + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N25 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\ula_|zx_keyboard_|keys[4][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [12]), + .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hF3FF; +defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N8 +cycloneive_lcell_comb \D[4]~80 ( +// Equation(s): +// \D[4]~80_combout = (\D[4]~79_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), + .datab(\D[4]~79_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|key_row~3_combout ), + .cin(gnd), + .combout(\D[4]~80_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~80 .lut_mask = 16'hC400; +defparam \D[4]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFAAA; +defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~97_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~97 .lut_mask = 16'h0060; +defparam \ula_|zx_keyboard_|keys[0][4]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~116_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & +// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~111_combout ), .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .datad(\ula_|zx_keyboard_|keys[0][4]~97_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~118_combout ), + .combout(\ula_|zx_keyboard_|keys[0][4]~116_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~118 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[0][4]~118 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[0][4]~116 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][4]~116 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N3 +// Location: FF_X29_Y18_N11 dffeas \ula_|zx_keyboard_|keys[0][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~118_combout ), + .d(\ula_|zx_keyboard_|keys[0][4]~116_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52760,28 +47024,28 @@ defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~117 ( +// Location: LCCOMB_X29_Y19_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~115 ( // Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~117_combout = (\ula_|zx_keyboard_|keys[1][4]~25_combout & ((\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # -// (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) +// \ula_|zx_keyboard_|keys[1][4]~115_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # +// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - .dataa(\ula_|zx_keyboard_|released~q ), + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~117_combout ), + .combout(\ula_|zx_keyboard_|keys[1][4]~115_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~117 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[1][4]~117 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[1][4]~115 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][4]~115 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y14_N3 +// Location: FF_X29_Y19_N7 dffeas \ula_|zx_keyboard_|keys[1][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~117_combout ), + .d(\ula_|zx_keyboard_|keys[1][4]~115_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52797,308 +47061,42 @@ defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N4 -cycloneive_lcell_comb \D[4]~62 ( +// Location: LCCOMB_X29_Y19_N28 +cycloneive_lcell_comb \D[4]~77 ( // Equation(s): -// \D[4]~62_combout = (\ula_|zx_keyboard_|keys[0][4]~q & (\z80_|address_pins_|abus[8]~20_combout & ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][4]~q )))) # (!\ula_|zx_keyboard_|keys[0][4]~q & -// (((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][4]~q )))) +// \D[4]~77_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - .dataa(\ula_|zx_keyboard_|keys[0][4]~q ), - .datab(\z80_|address_pins_|abus[8]~20_combout ), - .datac(\z80_|address_pins_|abus[9]~19_combout ), + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), .datad(\ula_|zx_keyboard_|keys[1][4]~q ), .cin(gnd), - .combout(\D[4]~62_combout ), + .combout(\D[4]~77_combout ), .cout()); // synopsys translate_off -defparam \D[4]~62 .lut_mask = 16'hD0DD; -defparam \D[4]~62 .sum_lutc_input = "datac"; +defparam \D[4]~77 .lut_mask = 16'h8ACF; +defparam \D[4]~77 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \D[4]~66 ( +// Location: LCCOMB_X29_Y19_N26 +cycloneive_lcell_comb \D[4]~81 ( // Equation(s): -// \D[4]~66_combout = (\D[4]~64_combout & (\D[4]~63_combout & (\D[4]~65_combout & \D[4]~62_combout ))) +// \D[4]~81_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~78_combout & (\D[4]~80_combout & \D[4]~77_combout ))) - .dataa(\D[4]~64_combout ), - .datab(\D[4]~63_combout ), - .datac(\D[4]~65_combout ), - .datad(\D[4]~62_combout ), + .dataa(\z80_|address_pins_|abus[0]~16_combout ), + .datab(\D[4]~78_combout ), + .datac(\D[4]~80_combout ), + .datad(\D[4]~77_combout ), .cin(gnd), - .combout(\D[4]~66_combout ), + .combout(\D[4]~81_combout ), .cout()); // synopsys translate_off -defparam \D[4]~66 .lut_mask = 16'h8000; -defparam \D[4]~66 .sum_lutc_input = "datac"; +defparam \D[4]~81 .lut_mask = 16'hEAAA; +defparam \D[4]~81 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y32_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y21_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X23_Y21_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y21_N2 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hF388; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y4_N0 +// Location: M9K_X22_Y1_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portawe(vcc), .portare(vcc), @@ -53108,16 +47106,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -53156,7 +47154,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: M9K_X33_Y28_N0 +// Location: M9K_X22_Y22_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -53166,16 +47164,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -53229,7 +47227,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y12_N0 +// Location: M9K_X33_Y3_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(vcc), .portare(vcc), @@ -53239,16 +47237,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -53287,7 +47285,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: M9K_X33_Y30_N0 +// Location: M9K_X22_Y25_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), .portare(vcc), @@ -53297,16 +47295,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -53359,120 +47357,370 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N12 +// Location: LCCOMB_X29_Y14_N2 cycloneive_lcell_comb \Selector4~0 ( // Equation(s): -// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) +// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), .cin(gnd), .combout(\Selector4~0_combout ), .cout()); // synopsys translate_off -defparam \Selector4~0 .lut_mask = 16'hAEA4; +defparam \Selector4~0 .lut_mask = 16'hBA98; defparam \Selector4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N2 +// Location: LCCOMB_X29_Y14_N26 cycloneive_lcell_comb \Selector4~1 ( // Equation(s): // \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & // (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), .datad(\Selector4~0_combout ), .cin(gnd), .combout(\Selector4~1_combout ), .cout()); // synopsys translate_off -defparam \Selector4~1 .lut_mask = 16'hF588; +defparam \Selector4~1 .lut_mask = 16'hF388; defparam \Selector4~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \D[4]~60 ( +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 ( // Equation(s): -// \D[4]~60_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector4~1_combout ))))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .lut_mask = 16'hE5E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .lut_mask = 16'hAFC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \D[4]~109 ( +// Equation(s): +// \D[4]~109_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Selector4~1_combout +// )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ))))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Selector4~1_combout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), + .cin(gnd), + .combout(\D[4]~109_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~109 .lut_mask = 16'hFB40; +defparam \D[4]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \D[4]~97 ( +// Equation(s): +// \D[4]~97_combout = ((\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout )))) # (!\Equal2~1_combout ) .dataa(\Equal2~0_combout ), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), - .datac(\z80_|address_pins_|abus[15]~17_combout ), - .datad(\Selector4~1_combout ), + .datab(\D[4]~81_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[4]~109_combout ), .cin(gnd), - .combout(\D[4]~60_combout ), + .combout(\D[4]~97_combout ), .cout()); // synopsys translate_off -defparam \D[4]~60 .lut_mask = 16'h4540; -defparam \D[4]~60 .sum_lutc_input = "datac"; +defparam \D[4]~97 .lut_mask = 16'hDF8F; +defparam \D[4]~97 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \D[4]~61 ( +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \D[4]~98 ( // Equation(s): -// \D[4]~61_combout = (((\z80_|memory_ifc_|nWR_out~0_combout ) # (\D[4]~60_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|memory_ifc_|nRD_out~2_combout ) +// \D[4]~98_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~97_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[4]~97_combout ) # (!\Equal2~1_combout )))) - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nWR_out~0_combout ), - .datad(\D[4]~60_combout ), + .dataa(\z80_|data_pins_|dout [4]), + .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[4]~97_combout ), .cin(gnd), - .combout(\D[4]~61_combout ), + .combout(\D[4]~98_combout ), .cout()); // synopsys translate_off -defparam \D[4]~61 .lut_mask = 16'hFFF7; -defparam \D[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \D[4]~78 ( -// Equation(s): -// \D[4]~78_combout = (\D[4]~61_combout ) # ((\Equal2~0_combout & ((\D[4]~66_combout ) # (\z80_|address_pins_|abus[0]~18_combout )))) - - .dataa(\D[4]~66_combout ), - .datab(\z80_|address_pins_|abus[0]~18_combout ), - .datac(\D[4]~61_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~78 .lut_mask = 16'hFEF0; -defparam \D[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \D[4]~79 ( -// Equation(s): -// \D[4]~79_combout = ((\D[4]~78_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\D[4]~78_combout ), - .datab(\z80_|data_pins_|dout [4]), - .datac(\D[0]~30_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cin(gnd), - .combout(\D[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~79 .lut_mask = 16'h8FAF; -defparam \D[4]~79 .sum_lutc_input = "datac"; +defparam \D[4]~98 .lut_mask = 16'hBB03; +defparam \D[4]~98 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X32_Y13_N24 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[4]~79_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[4]~19_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[4]~19_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[4]~19_combout ) # ((\D[4]~98_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[4]~98_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\D[4]~79_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[4]~98_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), .cout()); @@ -53500,41 +47748,41 @@ defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N20 +// Location: LCCOMB_X32_Y13_N20 cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( // Equation(s): // \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(gnd), - .datac(\z80_|data_pins_|dout [4]), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|data_pins_|dout [4]), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), .combout(\z80_|bus_control_|db[4]~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hF500; +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88CC; defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N4 +// Location: LCCOMB_X34_Y10_N18 cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( // Equation(s): // \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .dataa(\z80_|bus_control_|db[0]~6_combout ), .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[4]~19_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF0F; +defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF55; defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N5 +// Location: FF_X34_Y10_N19 dffeas \z80_|ir_|opcode[4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|bus_control_|db[4]~19_combout ), @@ -53553,32 +47801,2546 @@ defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X41_Y11_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Location: LCCOMB_X40_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( // Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) +// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), + .datab(gnd), .datac(\z80_|ir_|opcode [3]), - .datad(gnd), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), + .combout(\z80_|pla_decode_|Equal21~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h3030; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N12 +// Location: LCCOMB_X35_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( +// Equation(s): +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|fMRead~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|fMRead~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Equation(s): +// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F0F; +defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( +// Equation(s): +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|fIOWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( +// Equation(s): +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~5_combout ))) + + .dataa(\z80_|execute_|fIOWrite~1_combout ), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|fIOWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & +// (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~15_combout = ((\z80_|execute_|ctl_mWrite~14_combout ) # ((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout ))) # (!\z80_|execute_|ctl_mWrite~13_combout ) + + .dataa(\z80_|execute_|ixy_d~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~13_combout ), + .datac(\z80_|execute_|ctl_mWrite~14_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF7F3; +defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N29 +dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mWrite~15_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N4 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N5 +dffeas \z80_|memory_ifc_|wait_mwr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mwr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y17_N17 +dffeas \z80_|memory_ifc_|mwr_wr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|mwr_wr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N16 +cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(\z80_|memory_ifc_|iorq~0_combout ), + .datac(\z80_|memory_ifc_|mwr_wr~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|memory_ifc_|nWR_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; +defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \D[5]~84 ( +// Equation(s): +// \D[5]~84_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cin(gnd), + .combout(\D[5]~84_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~84 .lut_mask = 16'h0040; +defparam \D[5]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF858; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~0 .lut_mask = 16'hBA98; +defparam \Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \Mux0~1 ( +// Equation(s): +// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datad(\Mux0~0_combout ), + .cin(gnd), + .combout(\Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~1 .lut_mask = 16'hBBC0; +defparam \Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N22 +cycloneive_lcell_comb \D[7]~112 ( +// Equation(s): +// \D[7]~112_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux0~1_combout ))) +// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~112_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~112 .lut_mask = 16'hF4B0; +defparam \D[7]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N30 +cycloneive_lcell_comb \D[7]~94 ( +// Equation(s): +// \D[7]~94_combout = (\D[5]~84_combout & (\D[7]~112_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) + + .dataa(\D[5]~84_combout ), + .datab(\z80_|data_pins_|dout [7]), + .datac(\D[7]~112_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\D[7]~94_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~94 .lut_mask = 16'hC4F5; +defparam \D[7]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \D[7]~102 ( +// Equation(s): +// \D[7]~102_combout = (\D[7]~94_combout ) # (!\D[0]~107_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\D[7]~94_combout ), + .datad(\D[0]~107_combout ), + .cin(gnd), + .combout(\D[7]~102_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~102 .lut_mask = 16'hF0FF; +defparam \D[7]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\D[7]~102_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[7]~7_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[7]~102_combout & (\z80_|bus_control_|db[7]~7_combout +// & ((\z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[7]~102_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N27 +dffeas \z80_|data_pins_|dout[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Equation(s): +// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[7]~18_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N8 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Equation(s): +// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|data_pins_|dout [7]), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|bus_control_|db[7]~5_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hBF0F; +defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N21 +dffeas \z80_|ir_|opcode[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[7]~7_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_ir_we~4_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h3020; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC8C0; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~6_combout = (((\z80_|execute_|ctl_bus_db_we~4_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~2_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~3_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h000F; +defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & ((\ula_|zx_keyboard_|keys[0][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N17 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~48_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~48 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[3][3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), + .datab(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N23 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N22 +cycloneive_lcell_comb \D[2]~35 ( +// Equation(s): +// \D[2]~35_combout = (\z80_|address_pins_|abus[8]~18_combout & (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\z80_|address_pins_|abus[8]~18_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & +// ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) + + .dataa(\z80_|address_pins_|abus[8]~18_combout ), + .datab(\ula_|zx_keyboard_|keys[0][2]~q ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\z80_|address_pins_|abus[9]~17_combout ), + .cin(gnd), + .combout(\D[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~35 .lut_mask = 16'hBB0B; +defparam \D[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h3300; +defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|zx_keyboard_|keys[5][2]~57_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[5][2]~57_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N15 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h0420; +defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[4][2]~59_combout & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~131 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[4][2]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|zx_keyboard_|keys[4][2]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~131_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[4][2]~131_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N15 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \D[2]~37 ( +// Equation(s): +// \D[2]~37_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[5][2]~q ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~37 .lut_mask = 16'hBB0B; +defparam \D[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~55 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[2][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~56_combout = (\ula_|zx_keyboard_|keys[2][2]~55_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][2]~q ), + .datad(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N27 +dffeas \ula_|zx_keyboard_|keys[2][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N29 +dffeas \ula_|zx_keyboard_|keys[3][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N8 +cycloneive_lcell_comb \D[2]~36 ( +// Equation(s): +// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~24_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & +// (((\z80_|address_pins_|abus[11]~19_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), + .datab(\ula_|zx_keyboard_|keys[3][2]~q ), + .datac(\z80_|address_pins_|abus[10]~24_combout ), + .datad(\z80_|address_pins_|abus[11]~19_combout ), + .cin(gnd), + .combout(\D[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~36 .lut_mask = 16'hF531; +defparam \D[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h0180; +defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~68_combout )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~70_combout = (\ula_|zx_keyboard_|keys[6][2]~69_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~69_combout & ((\ula_|zx_keyboard_|keys[6][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), + .datab(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .datac(\ula_|zx_keyboard_|keys[6][2]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h7474; +defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N1 +dffeas \ula_|zx_keyboard_|keys[6][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[7][2]~61_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~62_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~63_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[7][2]~62_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'hC8C0; +defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~65_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & \ula_|zx_keyboard_|keys[7][2]~64_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector13~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF22; +defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[7][2]~65_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~65_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][2]~q ), + .datad(\ula_|zx_keyboard_|Selector13~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N13 +dffeas \ula_|zx_keyboard_|keys[7][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N0 +cycloneive_lcell_comb \D[2]~38 ( +// Equation(s): +// \D[2]~38_combout = (\z80_|address_pins_|abus[15]~22_combout & (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][2]~q & +// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\ula_|zx_keyboard_|keys[6][2]~q ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~q ), + .cin(gnd), + .combout(\D[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~38 .lut_mask = 16'hA2F3; +defparam \D[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N14 +cycloneive_lcell_comb \D[2]~39 ( +// Equation(s): +// \D[2]~39_combout = (\D[2]~35_combout & (\D[2]~37_combout & (\D[2]~36_combout & \D[2]~38_combout ))) + + .dataa(\D[2]~35_combout ), + .datab(\D[2]~37_combout ), + .datac(\D[2]~36_combout ), + .datad(\D[2]~38_combout ), + .cin(gnd), + .combout(\D[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~39 .lut_mask = 16'h8000; +defparam \D[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \D[2]~104 ( +// Equation(s): +// \D[2]~104_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\D[2]~39_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [0]), + .datad(\D[2]~39_combout ), + .cin(gnd), + .combout(\D[2]~104_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~104 .lut_mask = 16'hFFF3; +defparam \D[2]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \D[2]~43 ( +// Equation(s): +// \D[2]~43_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\D[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~43 .lut_mask = 16'hB9A8; +defparam \D[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \D[2]~44 ( +// Equation(s): +// \D[2]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~43_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout )) # (!\D[2]~43_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~43_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\D[2]~43_combout ), + .cin(gnd), + .combout(\D[2]~44_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~44 .lut_mask = 16'hBBC0; +defparam \D[2]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \D[2]~40 ( +// Equation(s): +// \D[2]~40_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\D[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~40 .lut_mask = 16'hEA62; +defparam \D[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \D[2]~41 ( +// Equation(s): +// \D[2]~41_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ (\D[2]~40_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & ((!\D[2]~40_combout )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\D[2]~40_combout ), + .cin(gnd), + .combout(\D[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~41 .lut_mask = 16'h0AE4; +defparam \D[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \D[2]~42 ( +// Equation(s): +// \D[2]~42_combout = (\D[2]~40_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~41_combout )))) # (!\D[2]~40_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~41_combout )))) + + .dataa(\D[2]~40_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\D[2]~41_combout ), + .cin(gnd), + .combout(\D[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~42 .lut_mask = 16'h99A8; +defparam \D[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \D[2]~105 ( +// Equation(s): +// \D[2]~105_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[2]~44_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~42_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[2]~44_combout )))) + + .dataa(\D[2]~44_combout ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\D[2]~42_combout ), + .cin(gnd), + .combout(\D[2]~105_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~105 .lut_mask = 16'hBA8A; +defparam \D[2]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N28 +cycloneive_lcell_comb \D[2]~45 ( +// Equation(s): +// \D[2]~45_combout = ((\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[2]~104_combout ), + .datad(\D[2]~105_combout ), + .cin(gnd), + .combout(\D[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~45 .lut_mask = 16'hF7B3; +defparam \D[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N30 +cycloneive_lcell_comb \D[2]~46 ( +// Equation(s): +// \D[2]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~45_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[2]~45_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[2]~45_combout ), + .cin(gnd), + .combout(\D[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~46 .lut_mask = 16'hAF03; +defparam \D[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N2 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[2]~46_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[2]~46_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\D[2]~46_combout ), + .datad(\z80_|bus_control_|db[2]~13_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N3 +dffeas \z80_|data_pins_|dout[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( +// Equation(s): +// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[2]~29_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( +// Equation(s): +// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|bus_control_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hBF33; +defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N13 +dffeas \z80_|ir_|opcode[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[2]~13_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N26 cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( // Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) +// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal43~0_combout ), .cout()); @@ -53587,14 +50349,14 @@ defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N14 +// Location: LCCOMB_X35_Y17_N24 cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( // Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal79~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & !\z80_|pla_decode_|Equal36~0_combout ))) +// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) .dataa(\z80_|pla_decode_|Equal43~0_combout ), - .datab(\z80_|pla_decode_|Equal79~0_combout ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datab(\z80_|pla_decode_|Equal3~2_combout ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), .datad(\z80_|pla_decode_|Equal36~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|test1~2_combout ), @@ -53604,24 +50366,24 @@ defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N22 +// Location: LCCOMB_X43_Y15_N26 cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( // Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & (((\z80_|interrupts_|test1~2_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) +// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|interrupts_|test1~2_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|interrupts_|test1~2_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|interrupts_|test1~2_combout ), .cin(gnd), .combout(\z80_|interrupts_|test1~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h00FD; +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h5545; defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y12_N27 +// Location: FF_X32_Y15_N13 dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), @@ -53640,7 +50402,7 @@ defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N16 +// Location: LCCOMB_X43_Y15_N2 cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( // Equation(s): // \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) @@ -53657,7 +50419,7 @@ defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y12_N17 +// Location: FF_X43_Y15_N3 dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), @@ -53676,7 +50438,7 @@ defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N2 +// Location: LCCOMB_X43_Y15_N20 cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( // Equation(s): // \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) @@ -53693,7 +50455,7 @@ defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0033; defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N1 +// Location: FF_X32_Y17_N13 dffeas \z80_|sequencer_|DFFE_T1_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|ena_M~combout ), @@ -53712,24 +50474,24 @@ defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N26 +// Location: LCCOMB_X32_Y17_N4 cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( // Equation(s): // \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), .datac(\z80_|execute_|setM1~52_combout ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0030; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N27 +// Location: FF_X32_Y17_N5 dffeas \z80_|sequencer_|DFFE_T2_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), @@ -53748,318 +50510,56 @@ defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N16 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|resets_|x3 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - .dataa(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datac(\z80_|resets_|x1~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .combout(\z80_|resets_|x3~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +defparam \z80_|resets_|x3 .lut_mask = 16'hF0FA; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N17 -dffeas \z80_|sequencer_|DFFE_T3_ff ( +// Location: FF_X35_Y13_N11 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .d(\z80_|resets_|x3~combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N14 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N15 -dffeas \z80_|sequencer_|DFFE_T4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), +// Location: CLKCTRL_G7 +cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), + .clkselect(2'b00), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), - .prn(vcc)); + .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X44_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( -// Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (\z80_|execute_|setM1~39_combout & !\z80_|execute_|ctl_mWrite~5_combout ) - - .dataa(\z80_|execute_|setM1~39_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h00AA; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~53 ( -// Equation(s): -// \z80_|execute_|setM1~53_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & \z80_|execute_|ctl_mRead~29_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~53_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h2AAA; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'hA800; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ctl_mRead~38_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|execute_|nextM~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|ctl_alu_op_low~37_combout ) # (\z80_|execute_|nextM~10_combout )) # (!\z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|nextM~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~37_combout ), - .datad(\z80_|execute_|nextM~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|fMRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'h8808; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (((\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|nextM~4_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|nextM~4_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~5_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~6_combout ) - - .dataa(\z80_|execute_|nextM~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|nextM~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( -// Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ixy_d~8_combout & (((!\z80_|alu_control_|flags_cond_true~q & \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|ixy_d~8_combout & -// (((!\z80_|alu_control_|flags_cond_true~q & \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout )))) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h2F22; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # ((\z80_|execute_|nextM~7_combout ) # (\z80_|execute_|nextM~8_combout ))) - - .dataa(\z80_|execute_|nextM~12_combout ), - .datab(\z80_|execute_|nextM~15_combout ), - .datac(\z80_|execute_|nextM~7_combout ), - .datad(\z80_|execute_|nextM~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~3_combout ) # ((\z80_|execute_|nextM~13_combout ) # ((!\z80_|execute_|ctl_mWrite~13_combout ) # (!\z80_|execute_|ctl_mRead~31_combout ))) - - .dataa(\z80_|execute_|nextM~3_combout ), - .datab(\z80_|execute_|nextM~13_combout ), - .datac(\z80_|execute_|ctl_mRead~31_combout ), - .datad(\z80_|execute_|ctl_mWrite~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N4 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; -defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N5 +// Location: FF_X32_Y17_N21 dffeas \z80_|sequencer_|DFFE_M1_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), @@ -54078,644 +50578,7 @@ defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N24 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N25 -dffeas \z80_|sequencer_|T6 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|T6~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|T6 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~9_combout )) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0011; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~43 ( -// Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0004; -defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~42_combout & (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|setM1~43_combout & !\z80_|pla_decode_|Equal21~1_combout ))) - - .dataa(\z80_|execute_|setM1~42_combout ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|setM1~43_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0020; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (\z80_|execute_|setM1~44_combout & (\z80_|execute_|setM1~41_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|execute_|setM1~44_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0888; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & -// (((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal21~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & !\z80_|pla_decode_|Equal1~6_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal77~1_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|pla_decode_|Equal1~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (!\z80_|pla_decode_|Equal2~2_combout & (\z80_|execute_|setM1~15_combout & (\z80_|execute_|setM1~14_combout & \z80_|interrupts_|test1~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|execute_|setM1~15_combout ), - .datac(\z80_|execute_|setM1~14_combout ), - .datad(\z80_|interrupts_|test1~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~49_combout & (\z80_|execute_|setM1~46_combout & \z80_|execute_|setM1~16_combout ))) - - .dataa(\z80_|execute_|setM1~45_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|execute_|setM1~46_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|setM1~41_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & -// (\z80_|execute_|setM1~40_combout ))) - - .dataa(\z80_|sequencer_|T6~q ), - .datab(\z80_|execute_|setM1~50_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'hC0EA; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hCDCC; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal6~1_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout ) # (\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|fMWrite~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|fMWrite~1_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~11_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|setM1~11_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|setM1~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & ((\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hDC50; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = ((\z80_|execute_|setM1~8_combout & \z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|execute_|setM1~8_combout ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF333; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( -// Equation(s): -// \z80_|execute_|setM1~13_combout = (\z80_|execute_|setM1~9_combout ) # (((\z80_|execute_|setM1~12_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) - - .dataa(\z80_|execute_|setM1~12_combout ), - .datab(\z80_|execute_|setM1~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'hECFF; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (\z80_|execute_|setM1~17_combout & (\z80_|execute_|ctl_alu_op_low~36_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|setM1~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~36_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0008; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~13_combout ) # (((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|setM1~16_combout )) # (!\z80_|execute_|setM1~18_combout )) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|setM1~16_combout ), - .datac(\z80_|execute_|setM1~13_combout ), - .datad(\z80_|execute_|setM1~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hF2FF; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = (\z80_|alu_control_|flags_cond_true~q & (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) # (!\z80_|alu_control_|flags_cond_true~q & -// ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((!\z80_|execute_|ctl_mRead~14_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'h7350; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|execute_|fMWrite~6_combout ))) - - .dataa(\z80_|execute_|fMWrite~1_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|fMWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0200; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'hFF02; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( -// Equation(s): -// \z80_|execute_|setM1~55_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~22_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~22_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'hC888; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~55_combout )) # (!\z80_|execute_|setM1~23_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~55_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|setM1~23_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~55_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h2F22; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hBAFF; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = ((\z80_|execute_|setM1~26_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datad(\z80_|execute_|setM1~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|setM1~27_combout ))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~24_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|setM1~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_mRead~38_combout & \z80_|execute_|setM1~11_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|setM1~11_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~20_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ctl_mRead~20_combout & -// (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|setM1~29_combout & \z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|setM1~30_combout )) # (!\z80_|execute_|setM1~56_combout ) - - .dataa(\z80_|execute_|setM1~29_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|setM1~56_combout ), - .datad(\z80_|execute_|setM1~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~33_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|setM1~33_combout ), - .datac(\z80_|execute_|setM1~32_combout ), - .datad(\z80_|execute_|setM1~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = ((\z80_|execute_|ctl_iorw~10_combout & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hD555; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~13_combout & (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~13_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20AA; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|execute_|setM1~20_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hECCC; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~34_combout ) # ((\z80_|execute_|setM1~54_combout ) # (\z80_|execute_|setM1~21_combout ))) - - .dataa(\z80_|execute_|setM1~28_combout ), - .datab(\z80_|execute_|setM1~34_combout ), - .datac(\z80_|execute_|setM1~54_combout ), - .datad(\z80_|execute_|setM1~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( -// Equation(s): -// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~19_combout & (!\z80_|execute_|setM1~35_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|setM1~51_combout ), - .datac(\z80_|execute_|setM1~19_combout ), - .datad(\z80_|execute_|setM1~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'h000B; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N18 +// Location: LCCOMB_X32_Y17_N10 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( // Equation(s): // \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) @@ -54732,7 +50595,7 @@ defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N19 +// Location: FF_X32_Y17_N11 dffeas \z80_|sequencer_|DFFE_M2_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), @@ -54751,195 +50614,2625 @@ defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( // Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .combout(\z80_|execute_|ctl_mWrite~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Location: LCCOMB_X41_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~39_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) +// \z80_|execute_|nextM~11_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ctl_mWrite~3_combout ) - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .combout(\z80_|execute_|nextM~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Location: LCCOMB_X40_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = (\z80_|execute_|pc_inc_hold~19_combout & ((\z80_|execute_|ctl_mRead~38_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|pc_inc_hold~19_combout & -// (((\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ixy_d~4_combout )))) +// \z80_|execute_|nextM~8_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout +// ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~19_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ixy_d~8_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .combout(\z80_|execute_|nextM~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~8 .lut_mask = 16'h44F4; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Location: LCCOMB_X39_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (((\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_bus_db_oe~7_combout )) # (!\z80_|execute_|pc_inc_hold~40_combout ))) +// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ixy_d~6_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~40_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .combout(\z80_|execute_|nextM~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~9 .lut_mask = 16'h8880; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( +// Location: LCCOMB_X40_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|execute_|pc_inc_hold~36_combout ) # ((\z80_|execute_|pc_inc_hold~35_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|pc_inc_hold~40_combout ))) +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|ixy_d~9_combout ))) - .dataa(\z80_|execute_|pc_inc_hold~36_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|pc_inc_hold~40_combout ), - .datad(\z80_|execute_|pc_inc_hold~35_combout ), + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datab(\z80_|execute_|nextM~9_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~37_combout ), + .combout(\z80_|execute_|nextM~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( +// Location: LCCOMB_X40_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~38_combout = ((\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|pc_inc_hold~34_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout ))) # (!\z80_|execute_|ctl_inc_cy~39_combout ) +// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|ctl_alu_op_low~32_combout ))) # (!\z80_|execute_|nextM~11_combout ) - .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), - .datab(\z80_|execute_|pc_inc_hold~37_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .dataa(\z80_|execute_|nextM~11_combout ), + .datab(\z80_|execute_|nextM~8_combout ), + .datac(\z80_|execute_|nextM~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~38_combout ), + .combout(\z80_|execute_|nextM~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Location: LCCOMB_X39_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (!\z80_|execute_|pc_inc_hold~38_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) +// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|fMRead~10_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .combout(\z80_|execute_|nextM~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~15 .lut_mask = 16'h80A0; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Location: LCCOMB_X40_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) +// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|nM1_int~2_combout ), + .dataa(\z80_|execute_|ixy_d~17_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'hDF5F; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ixy_d~8_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|execute_|nextM~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # (\z80_|execute_|nextM~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(\z80_|execute_|nextM~15_combout ), + .datad(\z80_|execute_|nextM~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (!\z80_|execute_|ctl_mWrite~5_combout & \z80_|execute_|setM1~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|setM1~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0F00; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~45_combout ) # (!\z80_|execute_|nextM~2_combout )) # (!\z80_|execute_|setM1~39_combout ))) + + .dataa(\z80_|execute_|setM1~39_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|setM1~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~13_combout ) # (((\z80_|execute_|nextM~5_combout ) # (!\z80_|execute_|ctl_mRead~30_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) + + .dataa(\z80_|execute_|nextM~13_combout ), + .datab(\z80_|execute_|ctl_mWrite~13_combout ), + .datac(\z80_|execute_|ctl_mRead~30_combout ), + .datad(\z80_|execute_|nextM~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N14 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|setM1~52_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N15 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N18 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N19 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N26 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|setM1~52_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N27 +dffeas \z80_|sequencer_|T6 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|T6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|T6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal21~2_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & +// (((!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal21~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'h153F; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal77~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~1_combout ), + .datab(\z80_|execute_|ctl_alu_oe~3_combout ), + .datac(\z80_|pla_decode_|Equal1~6_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~13_combout & (\z80_|interrupts_|test1~2_combout & \z80_|execute_|setM1~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~13_combout ), + .datac(\z80_|interrupts_|test1~2_combout ), + .datad(\z80_|execute_|setM1~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'hC000; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0005; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0100; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~43 ( +// Equation(s): +// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~41_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~42_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|setM1~41_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|setM1~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0400; +defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (\z80_|execute_|setM1~40_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|execute_|setM1~40_combout ), + .datad(\z80_|pla_decode_|Equal2~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h20A0; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~14_combout & (\z80_|execute_|setM1~44_combout & \z80_|execute_|setM1~49_combout ))) + + .dataa(\z80_|execute_|setM1~46_combout ), + .datab(\z80_|execute_|setM1~14_combout ), + .datac(\z80_|execute_|setM1~44_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~39_combout )) # (!\z80_|execute_|setM1~40_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & +// ((\z80_|execute_|setM1~39_combout )))) + + .dataa(\z80_|sequencer_|T6~q ), + .datab(\z80_|execute_|setM1~50_combout ), + .datac(\z80_|execute_|setM1~40_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'hCE0A; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~6 ( +// Equation(s): +// \z80_|execute_|setM1~6_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & (\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & +// \z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~6 .lut_mask = 16'hD5C0; +defparam \z80_|execute_|setM1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~7 ( +// Equation(s): +// \z80_|execute_|setM1~7_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|setM1~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~7 .lut_mask = 16'hF333; +defparam \z80_|execute_|setM1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~8 ( +// Equation(s): +// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|fMWrite~3_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~8 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~9 ( +// Equation(s): +// \z80_|execute_|setM1~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF1F0; +defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = ((\z80_|execute_|setM1~8_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~9_combout ))) # (!\z80_|execute_|nextM~2_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~16_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|setM1~8_combout ), + .datad(\z80_|execute_|setM1~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = (\z80_|execute_|setM1~7_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~10_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) + + .dataa(\z80_|execute_|setM1~7_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|setM1~10_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = ((\z80_|execute_|setM1~11_combout ) # ((!\z80_|execute_|setM1~14_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~16_combout ) + + .dataa(\z80_|execute_|setM1~16_combout ), + .datab(\z80_|execute_|setM1~14_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'hFF75; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~18_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & +// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~18_combout )))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hECA0; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|setM1~28_combout )) # (!\z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~54_combout ) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|execute_|setM1~29_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|setM1~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'hF777; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|setM1~9_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|setM1~9_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~32_combout ))) + + .dataa(\z80_|execute_|setM1~31_combout ), + .datab(\z80_|execute_|setM1~30_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|setM1~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'hAF0F; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_mRead~12_combout ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & ((!\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|alu_control_|flags_cond_true~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|setM1~25_combout ) # (\z80_|execute_|setM1~26_combout )))) + + .dataa(\z80_|execute_|setM1~25_combout ), + .datab(\z80_|execute_|setM1~26_combout ), + .datac(\z80_|execute_|setM1~24_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|execute_|fMWrite~9_combout & (!\z80_|execute_|ctl_mRead~8_combout & \z80_|execute_|fMWrite~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|fMWrite~9_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'h0400; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF1F0; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~53 ( +// Equation(s): +// \z80_|execute_|setM1~53_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~21_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|setM1~21_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~53 .lut_mask = 16'hC888; +defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~22_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # +// ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) + + .dataa(\z80_|execute_|setM1~22_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'h4F44; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|execute_|ctl_flags_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'h08CC; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~18_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) + + .dataa(\z80_|execute_|setM1~18_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'hEAAA; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = ((\z80_|execute_|setM1~19_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|ctl_mWrite~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~3_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datad(\z80_|execute_|setM1~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|setM1~23_combout ) # (\z80_|execute_|setM1~20_combout ))) + + .dataa(\z80_|execute_|setM1~33_combout ), + .datab(\z80_|execute_|setM1~27_combout ), + .datac(\z80_|execute_|setM1~23_combout ), + .datad(\z80_|execute_|setM1~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~17_combout & (!\z80_|execute_|setM1~34_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|setM1~34_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'h0301; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N24 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N25 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N24 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Equation(s): +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|decode_state_|in_halt~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0050; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( +// Equation(s): +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|decode_state_|in_halt~0_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|pla_decode_|Equal77~1_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|in_halt~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hCECC; +defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N25 +dffeas \z80_|decode_state_|in_halt ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|in_halt~1_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|in_halt~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; +defparam \z80_|decode_state_|in_halt .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_zero_oe~0_combout & (!\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0031; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), .datad(\z80_|pla_decode_|Equal41~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'h010F; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~68_combout & \z80_|execute_|ctl_inc_cy~69_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ))) +// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - .dataa(\z80_|execute_|ctl_inc_cy~68_combout ), - .datab(\z80_|execute_|ctl_inc_cy~69_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'h8F00; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # (\z80_|execute_|ctl_inc_cy~80_combout )))) +// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - .dataa(\z80_|execute_|ctl_inc_cy~70_combout ), - .datab(\z80_|execute_|ctl_inc_cy~67_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~80_combout ), + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0F1E; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N20 +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Equation(s): +// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; +defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|zx_keyboard_|keys[1][3]~93_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][3]~93_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N31 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~94_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|zx_keyboard_|keys[0][3]~96_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & +// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~97_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N1 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~98_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N4 +cycloneive_lcell_comb \D[3]~65 ( +// Equation(s): +// \D[3]~65_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][3]~q ), + .cin(gnd), + .combout(\D[3]~65_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~65 .lut_mask = 16'h8CAF; +defparam \D[3]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~99_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~99 .lut_mask = 16'h4040; +defparam \ula_|zx_keyboard_|keys[3][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~100 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~100_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[3][3]~99_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~99_combout & (\ula_|zx_keyboard_|keys[3][3]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), + .datab(\ula_|zx_keyboard_|keys[3][3]~99_combout ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~100_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~100 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][3]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N9 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~100_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'hCCDD; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~133 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~133_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][3]~102_combout & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~133_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~133 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[2][3]~133 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|keys[2][3]~133_combout & (!\ula_|zx_keyboard_|keys[2][3]~101_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~133_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][3]~133_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N3 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~103_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N28 +cycloneive_lcell_comb \D[3]~66 ( +// Equation(s): +// \D[3]~66_combout = (\z80_|address_pins_|abus[11]~19_combout & (((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[3][3]~q ), + .datac(\z80_|address_pins_|abus[10]~24_combout ), + .datad(\ula_|zx_keyboard_|keys[2][3]~q ), + .cin(gnd), + .combout(\D[3]~66_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~66 .lut_mask = 16'hB0BB; +defparam \D[3]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[5][3]~q +// )))) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N23 +dffeas \ula_|zx_keyboard_|keys[5][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|WideOr16~2_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~134 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~134_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), + .datab(\ula_|zx_keyboard_|Selector5~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~134 .lut_mask = 16'hCECC; +defparam \ula_|zx_keyboard_|keys[4][3]~134 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~106_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][3]~134_combout )))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~135 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~135_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~135 .lut_mask = 16'hCDCC; +defparam \ula_|zx_keyboard_|keys[4][3]~135 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|keys[4][3]~135_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & +// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N23 +dffeas \ula_|zx_keyboard_|keys[4][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][3]~108_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N20 +cycloneive_lcell_comb \D[3]~67 ( +// Equation(s): +// \D[3]~67_combout = (\ula_|zx_keyboard_|keys[5][3]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][3]~q & +// (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][3]~q ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[3]~67_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~67 .lut_mask = 16'hDD0D; +defparam \D[3]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~61_combout )))) + + .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hA888; +defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & ((!\ula_|zx_keyboard_|keys[0][4]~111_combout ))) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & (\ula_|zx_keyboard_|keys[7][3]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y20_N9 +dffeas \ula_|zx_keyboard_|keys[7][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~109_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~109 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[6][3]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~110_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~109_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~32_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~110 .lut_mask = 16'hF088; +defparam \ula_|zx_keyboard_|keys[6][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~137 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~137_combout = (\ula_|zx_keyboard_|extended~q ) # (((!\ula_|zx_keyboard_|keys[0][0]~15_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~110_combout )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~137 .lut_mask = 16'hBFFF; +defparam \ula_|zx_keyboard_|keys[6][3]~137 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~138 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~138_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~137_combout & ((\ula_|zx_keyboard_|keys[6][3]~q ))) # (!\ula_|zx_keyboard_|keys[6][3]~137_combout & +// (!\ula_|zx_keyboard_|Selector13~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~138 .lut_mask = 16'hF072; +defparam \ula_|zx_keyboard_|keys[6][3]~138 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N29 +dffeas \ula_|zx_keyboard_|keys[6][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # ((!\ula_|zx_keyboard_|keys[6][3]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[6][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \D[3]~68 ( +// Equation(s): +// \D[3]~68_combout = (\D[3]~67_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\D[3]~67_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|key_row~2_combout ), + .cin(gnd), + .combout(\D[3]~68_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~68 .lut_mask = 16'h8C00; +defparam \D[3]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \D[3]~69 ( +// Equation(s): +// \D[3]~69_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~65_combout & (\D[3]~66_combout & \D[3]~68_combout ))) + + .dataa(\D[3]~65_combout ), + .datab(\z80_|address_pins_|abus[0]~16_combout ), + .datac(\D[3]~66_combout ), + .datad(\D[3]~68_combout ), + .cin(gnd), + .combout(\D[3]~69_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~69 .lut_mask = 16'hECCC; +defparam \D[3]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \D[3]~73 ( +// Equation(s): +// \D[3]~73_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\D[3]~73_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~73 .lut_mask = 16'hCCE2; +defparam \D[3]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \D[3]~74 ( +// Equation(s): +// \D[3]~74_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[3]~73_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ))) # (!\D[3]~73_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~73_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datac(\D[3]~73_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .cin(gnd), + .combout(\D[3]~74_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~74 .lut_mask = 16'hF858; +defparam \D[3]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \D[3]~70 ( +// Equation(s): +// \D[3]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~23_combout )) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\D[3]~70_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~70 .lut_mask = 16'hEC64; +defparam \D[3]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \D[3]~71 ( +// Equation(s): +// \D[3]~71_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout $ (((\D[3]~70_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & !\D[3]~70_combout )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\D[3]~70_combout ), + .cin(gnd), + .combout(\D[3]~71_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~71 .lut_mask = 16'h22D8; +defparam \D[3]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \D[3]~72 ( +// Equation(s): +// \D[3]~72_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~70_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~70_combout & (!\D[3]~71_combout & +// \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )) # (!\D[3]~70_combout & (\D[3]~71_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\D[3]~70_combout ), + .datac(\D[3]~71_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\D[3]~72_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~72 .lut_mask = 16'h9C98; +defparam \D[3]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \D[3]~108 ( +// Equation(s): +// \D[3]~108_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[3]~74_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[3]~72_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[3]~74_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\D[3]~74_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\D[3]~72_combout ), + .cin(gnd), + .combout(\D[3]~108_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~108 .lut_mask = 16'hDC8C; +defparam \D[3]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \D[3]~95 ( +// Equation(s): +// \D[3]~95_combout = ((\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[3]~69_combout ), + .datab(\Equal2~1_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[3]~108_combout ), + .cin(gnd), + .combout(\D[3]~95_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~95 .lut_mask = 16'hBFB3; +defparam \D[3]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \D[3]~96 ( +// Equation(s): +// \D[3]~96_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [3] & \D[3]~95_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[3]~95_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [3]), + .datad(\D[3]~95_combout ), + .cin(gnd), + .combout(\D[3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~96 .lut_mask = 16'hF511; +defparam \D[3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\D[3]~96_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[3]~96_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[3]~96_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N7 +dffeas \z80_|data_pins_|dout[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( +// Equation(s): +// \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(\z80_|data_pins_|dout [3]), + .datac(gnd), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hDD00; +defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( +// Equation(s): +// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N1 +dffeas \z80_|ir_|opcode[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[3]~21_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_apin_mux~1_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ctl_apin_mux~1_combout ), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h8F8F; +defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N18 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .datab(\z80_|address_latch_|abusz [0]), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|abusz [0]), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N21 +// Location: FF_X31_Y16_N19 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -54958,160 +53251,228 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \D[0]~84 ( +// Location: LCCOMB_X29_Y14_N12 +cycloneive_lcell_comb \D[0]~59 ( // Equation(s): -// \D[0]~84_combout = (\Equal2~0_combout & ((\D[0]~47_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~84 .lut_mask = 16'hFB00; -defparam \D[0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \D[0]~50 ( -// Equation(s): -// \D[0]~50_combout = (\D[0]~84_combout & (((\z80_|data_pins_|dout [0])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) # (!\D[0]~84_combout & (\D[0]~42_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) - - .dataa(\D[0]~84_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\D[0]~42_combout ), - .cin(gnd), - .combout(\D[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~50 .lut_mask = 16'hF3A2; -defparam \D[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N30 -cycloneive_lcell_comb \D[1]~85 ( -// Equation(s): -// \D[1]~85_combout = (\Equal2~0_combout & ((\z80_|address_pins_|DFFE_apin_latch [0]) # ((\D[1]~28_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \D[0]~59_combout = (\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout ))) .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\D[1]~28_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\D[0]~51_combout ), + .datac(\D[0]~106_combout ), + .datad(gnd), .cin(gnd), - .combout(\D[1]~85_combout ), + .combout(\D[0]~59_combout ), .cout()); // synopsys translate_off -defparam \D[1]~85 .lut_mask = 16'hA8AA; -defparam \D[1]~85 .sum_lutc_input = "datac"; +defparam \D[0]~59 .lut_mask = 16'hD8D8; +defparam \D[0]~59 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \D[1]~51 ( +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \D[0]~60 ( // Equation(s): -// \D[1]~51_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~85_combout ) # (\D[1]~23_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[1]~85_combout ) # (\D[1]~23_combout )))) +// \D[0]~60_combout = (\Equal2~1_combout & (\D[0]~59_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [0]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\D[1]~85_combout ), - .datad(\D[1]~23_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[0]~59_combout ), .cin(gnd), - .combout(\D[1]~51_combout ), + .combout(\D[0]~60_combout ), .cout()); // synopsys translate_off -defparam \D[1]~51 .lut_mask = 16'hDDD0; -defparam \D[1]~51 .sum_lutc_input = "datac"; +defparam \D[0]~60 .lut_mask = 16'hCF45; +defparam \D[0]~60 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N22 -cycloneive_lcell_comb \D[3]~86 ( +// Location: LCCOMB_X32_Y18_N20 +cycloneive_lcell_comb \D[1]~61 ( // Equation(s): -// \D[3]~86_combout = (\Equal2~0_combout & ((\z80_|address_pins_|DFFE_apin_latch [0]) # ((\D[3]~58_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \D[1]~61_combout = (\Equal2~0_combout & (\D[1]~32_combout )) # (!\Equal2~0_combout & ((\D[1]~103_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(\Equal2~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~58_combout ), + .dataa(\Equal2~0_combout ), + .datab(gnd), + .datac(\D[1]~32_combout ), + .datad(\D[1]~103_combout ), .cin(gnd), - .combout(\D[3]~86_combout ), + .combout(\D[1]~61_combout ), .cout()); // synopsys translate_off -defparam \D[3]~86 .lut_mask = 16'hCC8C; -defparam \D[3]~86 .sum_lutc_input = "datac"; +defparam \D[1]~61 .lut_mask = 16'hF5A0; +defparam \D[1]~61 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N14 -cycloneive_lcell_comb \D[3]~59 ( +// Location: LCCOMB_X32_Y18_N22 +cycloneive_lcell_comb \D[1]~62 ( // Equation(s): -// \D[3]~59_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~86_combout ) # (\D[3]~53_combout )))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[3]~86_combout ) # (\D[3]~53_combout )))) +// \D[1]~62_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~61_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~61_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [1]), + .datad(\D[1]~61_combout ), + .cin(gnd), + .combout(\D[1]~62_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~62 .lut_mask = 16'hF531; +defparam \D[1]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \D[2]~63 ( +// Equation(s): +// \D[2]~63_combout = (\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout ))) + + .dataa(\Equal2~0_combout ), + .datab(gnd), + .datac(\D[2]~104_combout ), + .datad(\D[2]~105_combout ), + .cin(gnd), + .combout(\D[2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~63 .lut_mask = 16'hF5A0; +defparam \D[2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \D[2]~64 ( +// Equation(s): +// \D[2]~64_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~63_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[2]~63_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[2]~63_combout ), + .cin(gnd), + .combout(\D[2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~64 .lut_mask = 16'hAF23; +defparam \D[2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \D[3]~75 ( +// Equation(s): +// \D[3]~75_combout = (\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout ))) + + .dataa(\D[3]~69_combout ), + .datab(gnd), + .datac(\Equal2~0_combout ), + .datad(\D[3]~108_combout ), + .cin(gnd), + .combout(\D[3]~75_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~75 .lut_mask = 16'hAFA0; +defparam \D[3]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \D[3]~76 ( +// Equation(s): +// \D[3]~76_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~75_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[3]~75_combout ) # (!\Equal2~1_combout )))) .dataa(\z80_|data_pins_|dout [3]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[3]~86_combout ), - .datad(\D[3]~53_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[3]~75_combout ), .cin(gnd), - .combout(\D[3]~59_combout ), + .combout(\D[3]~76_combout ), .cout()); // synopsys translate_off -defparam \D[3]~59 .lut_mask = 16'hBBB0; -defparam \D[3]~59 .sum_lutc_input = "datac"; +defparam \D[3]~76 .lut_mask = 16'hAF23; +defparam \D[3]~76 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \D[4]~87 ( +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \D[4]~82 ( // Equation(s): -// \D[4]~87_combout = (\Equal2~0_combout & ((\D[4]~66_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \D[4]~82_combout = (\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout ))) - .dataa(\D[4]~66_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\Equal2~0_combout ), + .dataa(\Equal2~0_combout ), + .datab(\D[4]~81_combout ), + .datac(gnd), + .datad(\D[4]~109_combout ), .cin(gnd), - .combout(\D[4]~87_combout ), + .combout(\D[4]~82_combout ), .cout()); // synopsys translate_off -defparam \D[4]~87 .lut_mask = 16'hFB00; -defparam \D[4]~87 .sum_lutc_input = "datac"; +defparam \D[4]~82 .lut_mask = 16'hDD88; +defparam \D[4]~82 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N4 -cycloneive_lcell_comb \D[4]~67 ( +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \D[4]~83 ( // Equation(s): -// \D[4]~67_combout = (\z80_|data_pins_|dout [4] & (((\D[4]~87_combout ) # (\D[4]~61_combout )))) # (!\z80_|data_pins_|dout [4] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[4]~87_combout ) # (\D[4]~61_combout )))) +// \D[4]~83_combout = (\Equal2~1_combout & (\D[4]~82_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[4]~87_combout ), - .datad(\D[4]~61_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[4]~82_combout ), .cin(gnd), - .combout(\D[4]~67_combout ), + .combout(\D[4]~83_combout ), .cout()); // synopsys translate_off -defparam \D[4]~67 .lut_mask = 16'hBBB0; -defparam \D[4]~67 .sum_lutc_input = "datac"; +defparam \D[4]~83 .lut_mask = 16'hCF45; +defparam \D[4]~83 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N2 +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \D[6]~92 ( +// Equation(s): +// \D[6]~92_combout = (\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout )) + + .dataa(gnd), + .datab(\Equal2~0_combout ), + .datac(\D[6]~111_combout ), + .datad(\D[6]~86_combout ), + .cin(gnd), + .combout(\D[6]~92_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~92 .lut_mask = 16'hFC30; +defparam \D[6]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \D[6]~93 ( +// Equation(s): +// \D[6]~93_combout = (\Equal2~1_combout & (\D[6]~92_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [6]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [6]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[6]~92_combout ), + .cin(gnd), + .combout(\D[6]~93_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~93 .lut_mask = 16'hCF45; +defparam \D[6]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N0 cycloneive_lcell_comb \z80_|nM1_int~3 ( // Equation(s): // \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) - .dataa(\z80_|execute_|setM1~52_combout ), + .dataa(gnd), .datab(\z80_|sequencer_|DFFE_T1_ff~q ), .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), + .datad(\z80_|execute_|setM1~52_combout ), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hA8A8; +defparam \z80_|nM1_int~3 .lut_mask = 16'hFC00; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N3 +// Location: FF_X43_Y17_N1 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -55130,7 +53491,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y16_N24 +// Location: LCCOMB_X43_Y17_N30 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -55147,7 +53508,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y16_N25 +// Location: FF_X43_Y17_N31 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -55166,7 +53527,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X50_Y16_N11 +// Location: FF_X43_Y17_N25 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -55185,7 +53546,7 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N10 +// Location: LCCOMB_X43_Y17_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) @@ -55202,15 +53563,15 @@ defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N14 +// Location: LCCOMB_X43_Y17_N2 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nRD_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nMREQ_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nRD_out~0_combout ))) .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datad(\z80_|memory_ifc_|nMREQ_out~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), .cout()); @@ -55219,7 +53580,20 @@ defparam \z80_|memory_ifc_|nMREQ_out~1 .lut_mask = 16'h0001; defparam \z80_|memory_ifc_|nMREQ_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N10 +// Location: CLKCTRL_G19 +cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk )); +// synopsys translate_off +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock"; +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( // Equation(s): // \ula_|i2c_loader_|state.Idle~feeder_combout = VCC @@ -55236,7 +53610,7 @@ defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N12 +// Location: LCCOMB_X4_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -55253,7 +53627,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N13 +// Location: FF_X4_Y24_N1 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -55272,14 +53646,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X4_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) - .dataa(\ula_|i2c_loader_|divider [0]), - .datab(\ula_|i2c_loader_|divider [1]), + .dataa(\ula_|i2c_loader_|divider [1]), + .datab(\ula_|i2c_loader_|divider [0]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -55290,7 +53664,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N15 +// Location: FF_X4_Y24_N11 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -55309,25 +53683,25 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N16 +// Location: LCCOMB_X4_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) // \ula_|i2c_loader_|divider[2]~8 = CARRY((!\ula_|i2c_loader_|divider[1]~6 ) # (!\ula_|i2c_loader_|divider [2])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [2]), + .dataa(\ula_|i2c_loader_|divider [2]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[1]~6 ), .combout(\ula_|i2c_loader_|divider[2]~7_combout ), .cout(\ula_|i2c_loader_|divider[2]~8 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N17 +// Location: FF_X4_Y24_N13 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -55346,7 +53720,7 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N18 +// Location: LCCOMB_X4_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) @@ -55364,7 +53738,7 @@ defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hC30C; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N19 +// Location: FF_X4_Y24_N15 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -55383,7 +53757,7 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N20 +// Location: LCCOMB_X4_Y24_N16 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) @@ -55401,7 +53775,7 @@ defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N21 +// Location: FF_X4_Y24_N17 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -55420,24 +53794,24 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N22 +// Location: LCCOMB_X4_Y24_N18 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): -// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider [5] $ (!\ula_|i2c_loader_|divider[4]~12 ) +// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) - .dataa(\ula_|i2c_loader_|divider [5]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|i2c_loader_|divider [5]), .cin(\ula_|i2c_loader_|divider[4]~12 ), .combout(\ula_|i2c_loader_|divider[5]~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N23 +// Location: FF_X4_Y24_N19 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -55456,14 +53830,14 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N2 +// Location: LCCOMB_X4_Y24_N22 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0]) +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [1]) - .dataa(\ula_|i2c_loader_|divider [0]), - .datab(\ula_|i2c_loader_|divider [3]), - .datac(\ula_|i2c_loader_|divider [1]), + .dataa(\ula_|i2c_loader_|divider [1]), + .datab(\ula_|i2c_loader_|divider [0]), + .datac(\ula_|i2c_loader_|divider [3]), .datad(\ula_|i2c_loader_|divider [2]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), @@ -55473,24 +53847,24 @@ defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N28 +// Location: LCCOMB_X4_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [5])) # (!\ula_|i2c_loader_|divider [4]) +// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [4]), - .datac(\ula_|i2c_loader_|divider [5]), - .datad(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datab(\ula_|i2c_loader_|divider [5]), + .datac(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datad(\ula_|i2c_loader_|divider [4]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hFF3F; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hF3FF; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N11 +// Location: FF_X1_Y23_N1 dffeas \ula_|i2c_loader_|state.Idle ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), @@ -55509,7 +53883,7 @@ defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N2 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( // Equation(s): // \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) @@ -55526,7 +53900,7 @@ defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N3 +// Location: FF_X1_Y23_N5 dffeas \ula_|i2c_loader_|phase[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~0_combout ), @@ -55545,24 +53919,24 @@ defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N8 +// Location: LCCOMB_X1_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( // Equation(s): -// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [1] $ (\ula_|i2c_loader_|phase [0]))) +// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) - .dataa(\ula_|i2c_loader_|state.Idle~q ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|phase~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h0AA0; +defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N9 +// Location: FF_X1_Y23_N15 dffeas \ula_|i2c_loader_|phase[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~1_combout ), @@ -55581,558 +53955,24 @@ defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( -// Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux42~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [0] $ (!\ula_|i2c_loader_|nbit [1])) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|nbit [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hB7B7; -defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|nbyte [0])) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|nbyte [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h0202; -defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|phase [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y23_N1 -cycloneive_io_ibuf \I2C_SDAT~input ( - .i(I2C_SDAT), - .ibar(gnd), - .o(\I2C_SDAT~input_o )); -// synopsys translate_off -defparam \I2C_SDAT~input .bus_hold = "false"; -defparam \I2C_SDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|thisbyte[0]~7_combout & ((\ula_|i2c_loader_|nbyte[0]~1_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hCAC0; -defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h0C00; -defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y23_N5 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [1] & (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbyte [0])) - - .dataa(\ula_|i2c_loader_|nbyte [1]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(gnd), - .datad(\ula_|i2c_loader_|nbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0011; -defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; -defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|state.Done~0_combout ) # (\ula_|i2c_loader_|nbit[0]~2_combout )))) - - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|state.Done~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; -defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|Mux42~0_combout & \ula_|i2c_loader_|state.Idle~q ))) - - .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|Mux42~0_combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h1000; -defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N17 -dffeas \ula_|i2c_loader_|nbit[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [0] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) - - .dataa(\ula_|i2c_loader_|nbit [0]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~0_combout = (!\ula_|i2c_loader_|state.Pause~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Start~q ))) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'h0001; -defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Ack~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Done~0_combout ), - .datab(\ula_|i2c_loader_|state.Ack~0_combout ), - .datac(\ula_|i2c_loader_|Mux42~0_combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hB0FF; -defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~2_combout = (\ula_|i2c_loader_|state.Ack~1_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # -// (!\ula_|i2c_loader_|state.Ack~1_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|state.Ack~1_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~2 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Ack~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N31 -dffeas \ula_|i2c_loader_|state.Ack ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Ack~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Ack~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( -// Equation(s): -// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [1]) # (\ula_|i2c_loader_|nbyte [0]))) - - .dataa(\ula_|i2c_loader_|nbyte [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|nbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hF0A0; -defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( -// Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|state~24_combout & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1])) - - .dataa(\ula_|i2c_loader_|state~24_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; -defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( -// Equation(s): -// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|phase [1]) # (!\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|phase [0]) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|state.Done~1_combout ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h3FFF; -defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~27_combout ))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~26_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state~26_combout ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state~27_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Data~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hFC0C; -defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N21 -dffeas \ula_|i2c_loader_|state.Data ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Data~0_combout ), - .asdata(\ula_|i2c_loader_|Mux42~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Data~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Data .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N26 +// Location: LCCOMB_X3_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( // Equation(s): // \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|nbit [0]) # (!\ula_|i2c_loader_|state.Data~q ) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(gnd), .datac(\ula_|i2c_loader_|nbit [0]), .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|nbit~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h3F3F; +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h5F5F; defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N27 -dffeas \ula_|i2c_loader_|nbit[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|nbit [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|nbit [2]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF3B7; -defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N21 -dffeas \ula_|i2c_loader_|nbit[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|nbit [0]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0003; -defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|state.Pause~q & (((!\ula_|i2c_loader_|state.Done~1_combout & \ula_|i2c_loader_|state.Data~q )))) # (!\ula_|i2c_loader_|state.Pause~q & ((\ula_|i2c_loader_|scl_out~0_combout ) # -// ((!\ula_|i2c_loader_|state.Done~1_combout & \ula_|i2c_loader_|state.Data~q )))) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|scl_out~0_combout ), - .datac(\ula_|i2c_loader_|state.Done~1_combout ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h4F44; -defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Done~2_combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h8AFF; -defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|phase [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5CFC; -defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N10 +// Location: LCCOMB_X2_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) @@ -56150,332 +53990,119 @@ defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Location: LCCOMB_X1_Y24_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|phase [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Mux42~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) .dataa(\ula_|i2c_loader_|nbyte [0]), .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; -defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y23_N11 -dffeas \ula_|i2c_loader_|thisbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), - .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h5A5F; -defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N13 -dffeas \ula_|i2c_loader_|thisbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) -// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), - .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; -defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N15 -dffeas \ula_|i2c_loader_|thisbyte[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), - .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N17 -dffeas \ula_|i2c_loader_|thisbyte[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte[3]~15 $ (!\ula_|i2c_loader_|thisbyte [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), - .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hF00F; -defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N19 -dffeas \ula_|i2c_loader_|thisbyte[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Pause~0_combout ), - .datac(\ula_|i2c_loader_|Equal2~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h0CCC; -defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Pause~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~1_combout ))))) # -// (!\ula_|i2c_loader_|state.Pause~2_combout & (((\ula_|i2c_loader_|state.Pause~q )))) - - .dataa(\ula_|i2c_loader_|state.Pause~2_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Pause~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N7 -dffeas \ula_|i2c_loader_|state.Pause ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Pause~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Pause~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( -// Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # -// (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; -defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N17 -dffeas \ula_|i2c_loader_|state.Start ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state~25_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Start~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Start .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [1] $ (!\ula_|i2c_loader_|nbyte [0])))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hECCE; +defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hFF84; defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N31 +// Location: LCCOMB_X1_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N1 +cycloneive_io_ibuf \I2C_SDAT~input ( + .i(I2C_SDAT), + .ibar(gnd), + .o(\I2C_SDAT~input_o )); +// synopsys translate_off +defparam \I2C_SDAT~input .bus_hold = "false"; +defparam \I2C_SDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hEFE0; +defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; +defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~3_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbyte[0]~2_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h3000; +defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N29 dffeas \ula_|i2c_loader_|nbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbyte~4_combout ), @@ -56494,42 +54121,42 @@ defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 +// Location: LCCOMB_X2_Y24_N18 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [1] & (\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|nbyte [0])) +// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) - .dataa(\ula_|i2c_loader_|nbyte [1]), - .datab(gnd), + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|nbyte [0]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|state.Stop~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0050; +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h1010; defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N24 +// Location: LCCOMB_X1_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( // Equation(s): -// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Stop~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))))) # -// (!\ula_|i2c_loader_|Mux42~0_combout & (((\ula_|i2c_loader_|state.Stop~q )))) +// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))) # +// (!\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~q )))) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), .datac(\ula_|i2c_loader_|state.Stop~q ), .datad(\ula_|i2c_loader_|state.Stop~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Stop~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF4B0; defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N25 +// Location: FF_X1_Y24_N3 dffeas \ula_|i2c_loader_|state.Stop ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Stop~1_combout ), @@ -56548,16 +54175,763 @@ defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Location: LCCOMB_X1_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Ack~q ))) - .dataa(gnd), + .dataa(\ula_|i2c_loader_|state.Start~q ), .datab(\ula_|i2c_loader_|state.Stop~q ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; +defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|nbit [2]), + .datad(\ula_|i2c_loader_|nbit [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N1 +dffeas \ula_|i2c_loader_|nbit[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [0]))) + + .dataa(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|nbit [2]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Idle~0_combout ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|state.Done~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hAF2F; +defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), .datac(\ula_|i2c_loader_|state.Ack~q ), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N31 +dffeas \ula_|i2c_loader_|state.Ack ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Ack~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Ack~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hEFE0; +defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N15 +dffeas \ula_|i2c_loader_|thisbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), + .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N17 +dffeas \ula_|i2c_loader_|thisbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) +// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), + .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N19 +dffeas \ula_|i2c_loader_|thisbyte[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), + .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N21 +dffeas \ula_|i2c_loader_|thisbyte[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Stop~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5FCC; +defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), + .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N23 +dffeas \ula_|i2c_loader_|thisbyte[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|Equal2~0_combout ), + .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h30F0; +defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & +// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Done~1_combout )))) + + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Done~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0ACE; +defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Done~2_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hC4FF; +defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~2_combout & (\ula_|i2c_loader_|state.Pause~1_combout )) # +// (!\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) + + .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Pause~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hE2F0; +defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N23 +dffeas \ula_|i2c_loader_|state.Pause ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Pause~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Pause~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( +// Equation(s): +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; +defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N31 +dffeas \ula_|i2c_loader_|state.Start ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Start~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Start .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; +defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N11 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0005; +defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|phase [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; +defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) + + .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Done~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; +defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) + + .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0400; +defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N3 +dffeas \ula_|i2c_loader_|nbit[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF55F; +defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N13 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & !\ula_|i2c_loader_|nbit [0])) + + .dataa(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|nbit [2]), + .datac(gnd), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( +// Equation(s): +// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Done~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Done~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; +defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( +// Equation(s): +// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hE0E0; +defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( +// Equation(s): +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; +defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) + + .dataa(\ula_|i2c_loader_|state~27_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state~26_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Data~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hAFA0; +defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N29 +dffeas \ula_|i2c_loader_|state.Data ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Data~0_combout ), + .asdata(\ula_|i2c_loader_|Mux42~0_combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2c_loader_|state.Start~q ), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Data~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Data .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Stop~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|state.Stop~q ), + .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~0_combout ), .cout()); // synopsys translate_off @@ -56565,7 +54939,7 @@ defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N9 +// Location: FF_X1_Y23_N13 dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|scl_out~2_combout ), @@ -56584,38 +54958,38 @@ defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N28 +// Location: LCCOMB_X1_Y23_N16 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ ((!\ula_|i2c_loader_|state.Start~q )))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # -// ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q & \ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # +// ((\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|scl_out~_Duplicate_1_q )))) - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hD7C2; +defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hBA74; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N8 +// Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|scl_out~1_combout ))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|scl_out~1_combout )) +// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & ((\ula_|i2c_loader_|state.Start~q ))) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|state.Start~q )) .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|scl_out~1_combout ), + .datab(\ula_|i2c_loader_|scl_out~1_combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hF005; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hCC11; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56638,7 +55012,7 @@ defparam \ula_|i2c_loader_|scl_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out .power_up = "high"; // synopsys translate_on -// Location: FF_X1_Y23_N31 +// Location: FF_X1_Y23_N23 dffeas \ula_|i2c_loader_|sda_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|sda_out~4_combout ), @@ -56657,88 +55031,156 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N6 +// Location: LCCOMB_X3_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state.Start~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; +defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte [0] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [2]), .cin(gnd), .combout(\ula_|i2c_loader_|Mux35~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h20A0; +defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h2A00; defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X2_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h001A; +defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h00F0; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|shiftreg~14_combout ))) + + .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~14_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hAABA; +defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: LCCOMB_X3_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3])) +// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0030; +defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0300; defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 +// Location: LCCOMB_X1_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [0] & !\ula_|i2c_loader_|phase [1])) +// \ula_|i2c_loader_|shiftreg[0]~6_combout = (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Data~q )) - .dataa(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|phase [1]), .datab(gnd), .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h00A0; +defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h5000; defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N26 +// Location: LCCOMB_X1_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state~24_combout ) # (\ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) - .dataa(\ula_|i2c_loader_|state~24_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|Mux42~0_combout ), - .datad(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .datad(\ula_|i2c_loader_|state~24_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFFE0; +defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFCF8; defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N20 +// Location: LCCOMB_X1_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|shiftreg[0]~7_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q )) +// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|shiftreg[0]~7_combout )) - .dataa(\ula_|i2c_loader_|shiftreg[0]~7_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h2200; +defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h0C00; defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56761,54 +55203,37 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; -defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N24 +// Location: LCCOMB_X2_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [3]))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte [2]))) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2])))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [4]), + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [2]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hA010; +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hC010; defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N2 +// Location: LCCOMB_X3_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~21_combout ), + .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), + .datab(\ula_|i2c_loader_|shiftreg~4_combout ), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~22_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'hAA08; +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h88C8; defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56829,33 +55254,33 @@ defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N10 +// Location: LCCOMB_X2_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|phase [1]))))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q -// ) # (\ula_|i2c_loader_|state~24_combout )))) +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q +// & (!\ula_|i2c_loader_|state.Start~q ))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state~24_combout ), - .datad(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state~24_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hDC22; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hA6A4; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N24 +// Location: LCCOMB_X2_Y24_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|shiftreg[6]~10_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ))) +// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|shiftreg[6]~10_combout ))) - .dataa(\ula_|i2c_loader_|shiftreg[6]~10_combout ), + .dataa(\ula_|i2c_loader_|phase [0]), .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .cout()); @@ -56883,41 +55308,41 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N20 +// Location: LCCOMB_X2_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) +// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [1]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [3])))) - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(\ula_|i2c_loader_|thisbyte [4]), + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h4070; +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h10B0; defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N22 +// Location: LCCOMB_X3_Y23_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0])) # (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|shiftreg~18_combout )))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .dataa(\ula_|i2c_loader_|thisbyte [0]), .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~18_combout ), + .datac(\ula_|i2c_loader_|shiftreg~18_combout ), + .datad(\ula_|i2c_loader_|shiftreg~4_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h7F5D; +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h74FF; defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N16 +// Location: LCCOMB_X3_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) @@ -56934,7 +55359,7 @@ defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hAF00; defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N17 +// Location: FF_X3_Y23_N3 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~20_combout ), @@ -56953,58 +55378,41 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|thisbyte [2]), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0F00; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N0 +// Location: LCCOMB_X2_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(\ula_|i2c_loader_|thisbyte [4]), - .datac(\ula_|i2c_loader_|thisbyte [2]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h04F4; +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h10BA; defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N2 +// Location: LCCOMB_X3_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|shiftreg~14_combout & ((\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [3] & ((!\ula_|i2c_loader_|shiftreg~14_combout )))) - .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), - .datab(\ula_|i2c_loader_|shiftreg~16_combout ), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|shiftreg~16_combout ), + .datad(\ula_|i2c_loader_|shiftreg~14_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hC5C0; +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hA0E4; defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 +// Location: LCCOMB_X3_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg~17_combout )))) @@ -57021,7 +55429,7 @@ defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hC5C0; defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X3_Y23_N7 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~26_combout ), @@ -57040,58 +55448,24 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [4])) # (!\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4]))))) - - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h0310; -defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|shiftreg~14_combout & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), - .datab(\ula_|i2c_loader_|shiftreg~13_combout ), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hCCDC; -defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N4 +// Location: LCCOMB_X2_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|shiftreg~15_combout )))) +// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|shiftreg [3]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~15_combout ), + .dataa(\ula_|i2c_loader_|shiftreg~15_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|shiftreg [3]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hCFCA; +defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE32; defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N5 +// Location: FF_X2_Y23_N1 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~25_combout ), @@ -57110,7 +55484,7 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N8 +// Location: LCCOMB_X2_Y24_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) @@ -57127,7 +55501,7 @@ defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hEE22; defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N9 +// Location: FF_X2_Y24_N5 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~12_combout ), @@ -57146,24 +55520,24 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 +// Location: LCCOMB_X3_Y23_N18 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) - .dataa(\ula_|i2c_loader_|shiftreg [5]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg [5]), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|Mux35~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hAFA0; +defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hCFC0; defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N11 +// Location: FF_X3_Y23_N19 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~9_combout ), @@ -57182,7 +55556,7 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N28 +// Location: LCCOMB_X3_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( // Equation(s): // \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) @@ -57199,7 +55573,7 @@ defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N29 +// Location: FF_X3_Y23_N5 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), @@ -57218,21 +55592,21 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N26 +// Location: LCCOMB_X2_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|shiftreg [7]))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|state.Data~q & // (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|shiftreg [7]), - .datab(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|shiftreg [7]), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hB8F0; +defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hF870; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57241,67 +55615,67 @@ cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): // \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|sda_out~0_combout ), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|sda_out~0_combout ), .datad(\I2C_SDAT~input_o ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hA0A8; +defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hC0E0; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N4 +// Location: LCCOMB_X1_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h5054; +defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N10 +// Location: LCCOMB_X1_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|sda_out~1_combout )))) # (!\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|phase [0] -// & ((!\ula_|i2c_loader_|sda_out~1_combout ))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )))) +// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase +// [0] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|sda_out~1_combout )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'h8EBA; +defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2AE; defparam \ula_|i2c_loader_|sda_out~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N30 +// Location: LCCOMB_X1_Y23_N22 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~4 ( // Equation(s): // \ula_|i2c_loader_|sda_out~4_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|sda_out~2_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & ((\ula_|i2c_loader_|sda_out~3_combout )))) - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|scl_out~0_combout ), .datac(\ula_|i2c_loader_|sda_out~2_combout ), .datad(\ula_|i2c_loader_|sda_out~3_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1D0C; +defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1B0A; defparam \ula_|i2c_loader_|sda_out~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57324,6 +55698,42 @@ defparam \ula_|i2c_loader_|sda_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out .power_up = "high"; // synopsys translate_on +// Location: LCCOMB_X27_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|mclk_r~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N17 +dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|mclk_r~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + // Location: DDIOOUTCELL_X20_Y34_N25 dffeas \ula_|i2s_intf_|mclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -57343,6 +55753,612 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X29_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) + + .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add0~1_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) +// \ula_|i2s_intf_|Add0~3 = CARRY((!\ula_|i2s_intf_|lrdivider [1] & !\ula_|i2s_intf_|Add0~1_cout )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~1_cout ), + .combout(\ula_|i2s_intf_|Add0~2_combout ), + .cout(\ula_|i2s_intf_|Add0~3 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y23_N29 +dffeas \ula_|i2s_intf_|lrdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) +// \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) + + .dataa(\ula_|i2s_intf_|lrdivider [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~3 ), + .combout(\ula_|i2s_intf_|Add0~4_combout ), + .cout(\ula_|i2s_intf_|Add0~5 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~4_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y23_N7 +dffeas \ula_|i2s_intf_|lrdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) +// \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~5 ), + .combout(\ula_|i2s_intf_|Add0~6_combout ), + .cout(\ula_|i2s_intf_|Add0~7 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N7 +dffeas \ula_|i2s_intf_|lrdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) +// \ula_|i2s_intf_|Add0~9 = CARRY((\ula_|i2s_intf_|lrdivider [4]) # (!\ula_|i2s_intf_|Add0~7 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~7 ), + .combout(\ula_|i2s_intf_|Add0~8_combout ), + .cout(\ula_|i2s_intf_|Add0~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y23_N5 +dffeas \ula_|i2s_intf_|lrdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) +// \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~9 ), + .combout(\ula_|i2s_intf_|Add0~10_combout ), + .cout(\ula_|i2s_intf_|Add0~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~10_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[5]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y23_N3 +dffeas \ula_|i2s_intf_|lrdivider[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) + + .dataa(\ula_|i2s_intf_|lrdivider [2]), + .datab(\ula_|i2s_intf_|lrdivider [4]), + .datac(\ula_|i2s_intf_|lrdivider [3]), + .datad(\ula_|i2s_intf_|lrdivider [5]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) +// \ula_|i2s_intf_|Add0~13 = CARRY((!\ula_|i2s_intf_|Add0~11 ) # (!\ula_|i2s_intf_|lrdivider [6])) + + .dataa(\ula_|i2s_intf_|lrdivider [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~11 ), + .combout(\ula_|i2s_intf_|Add0~12_combout ), + .cout(\ula_|i2s_intf_|Add0~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~12_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N27 +dffeas \ula_|i2s_intf_|lrdivider[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) +// \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) + + .dataa(\ula_|i2s_intf_|lrdivider [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~13 ), + .combout(\ula_|i2s_intf_|Add0~14_combout ), + .cout(\ula_|i2s_intf_|Add0~15 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y23_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~14_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y23_N5 +dffeas \ula_|i2s_intf_|lrdivider[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) +// \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) + + .dataa(\ula_|i2s_intf_|lrdivider [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~15 ), + .combout(\ula_|i2s_intf_|Add0~16_combout ), + .cout(\ula_|i2s_intf_|Add0~17 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h5AAF; +defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Add0~16_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0C0C; +defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N17 +dffeas \ula_|i2s_intf_|lrdivider[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|lrdivider [9]), + .cin(\ula_|i2s_intf_|Add0~17 ), + .combout(\ula_|i2s_intf_|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; +defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~18_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N25 +dffeas \ula_|i2s_intf_|lrdivider[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal0~0_combout = (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [6] & \ula_|i2s_intf_|lrdivider [7]))) + + .dataa(\ula_|i2s_intf_|lrdivider [8]), + .datab(\ula_|i2s_intf_|lrdivider [9]), + .datac(\ula_|i2s_intf_|lrdivider [6]), + .datad(\ula_|i2s_intf_|lrdivider [7]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h4000; +defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( +// Equation(s): +// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) + + .dataa(\ula_|i2s_intf_|Equal0~1_combout ), + .datab(\ula_|i2s_intf_|lrdivider [1]), + .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( +// Equation(s): +// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N25 +dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; +defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X16_Y34_N18 dffeas \ula_|i2s_intf_|lrclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -57381,6 +56397,596 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X31_Y22_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] +// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .cout(\ula_|i2s_intf_|bitcount[0]~6 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; +defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N11 +dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bclk_r~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF0FC; +defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N1 +dffeas \ula_|i2s_intf_|bitcount[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) +// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[0]~6 ), + .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .cout(\ula_|i2s_intf_|bitcount[1]~8 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N3 +dffeas \ula_|i2s_intf_|bitcount[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) +// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[1]~8 ), + .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .cout(\ula_|i2s_intf_|bitcount[2]~10 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N5 +dffeas \ula_|i2s_intf_|bitcount[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) +// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) + + .dataa(\ula_|i2s_intf_|bitcount [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[2]~10 ), + .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .cout(\ula_|i2s_intf_|bitcount[3]~12 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; +defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N7 +dffeas \ula_|i2s_intf_|bitcount[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) + + .dataa(\ula_|i2s_intf_|bitcount [3]), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(\ula_|i2s_intf_|bitcount [2]), + .datad(\ula_|i2s_intf_|bitcount [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [4]), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2s_intf_|bitcount[3]~12 ), + .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; +defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N9 +dffeas \ula_|i2s_intf_|bitcount[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add2~7_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) +// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~7_cout ), + .combout(\ula_|i2s_intf_|Add2~8_combout ), + .cout(\ula_|i2s_intf_|Add2~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; +defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|Add2~8_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1300; +defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N13 +dffeas \ula_|i2s_intf_|bdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) +// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) + + .dataa(\ula_|i2s_intf_|bdivider [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~9 ), + .combout(\ula_|i2s_intf_|Add2~10_combout ), + .cout(\ula_|i2s_intf_|Add2~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Add2~10_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0203; +defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N17 +dffeas \ula_|i2s_intf_|bdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) +// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~11 ), + .combout(\ula_|i2s_intf_|Add2~12_combout ), + .cout(\ula_|i2s_intf_|Add2~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~19_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~12_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|Add2~12_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h1300; +defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N3 +dffeas \ula_|i2s_intf_|bdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(\ula_|i2s_intf_|Add2~13 ), + .combout(\ula_|i2s_intf_|Add2~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; +defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Add2~14_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; +defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N19 +dffeas \ula_|i2s_intf_|bdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & \ula_|i2s_intf_|bdivider [4]))) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(\ula_|i2s_intf_|bdivider [2]), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h1000; +defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~1 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[4]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8A00; +defparam \ula_|i2s_intf_|shiftreg[4]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N13 +dffeas \ula_|i2s_intf_|bdivider[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hF000; +defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h30CF; +defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|bclk_r~0_combout ), + .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00D8; +defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X14_Y34_N18 dffeas \ula_|i2s_intf_|bclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -57400,16 +57006,781 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y13_N29 -dffeas \ula_|pcm_outl[14] ( +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( +// Equation(s): +// \ula_|pcm_outl[13]~feeder_combout = \D[3]~96_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[3]~96_combout ), + .cin(gnd), + .combout(\ula_|pcm_outl[13]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; +defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N2 +cycloneive_lcell_comb \ula_|always0~2 ( +// Equation(s): +// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|always0~2 .lut_mask = 16'h2020; +defparam \ula_|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \ula_|always0~3 ( +// Equation(s): +// \ula_|always0~3_combout = (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|always0~2_combout ), + .cin(gnd), + .combout(\ula_|always0~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|always0~3 .lut_mask = 16'h4000; +defparam \ula_|always0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N25 +dffeas \ula_|pcm_outl[13] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[4]~79_combout ), + .d(\ula_|pcm_outl[13]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|always0~1_combout ), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|pcm_outl [13]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h008A; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y34_N22 +cycloneive_io_ibuf \AUD_ADCDAT~input ( + .i(AUD_ADCDAT), + .ibar(gnd), + .o(\AUD_ADCDAT~input_o )); +// synopsys translate_off +defparam \AUD_ADCDAT~input .bus_hold = "false"; +defparam \AUD_ADCDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # +// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) + + .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [0]), + .datad(\AUD_ADCDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N21 +dffeas \ula_|i2s_intf_|shiftreg[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~18_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~2 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFCF0; +defparam \ula_|i2s_intf_|shiftreg[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N27 +dffeas \ula_|i2s_intf_|shiftreg[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [1] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [1]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N25 +dffeas \ula_|i2s_intf_|shiftreg[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N19 +dffeas \ula_|i2s_intf_|shiftreg[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~15_combout = (\ula_|i2s_intf_|shiftreg [3] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [3]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N1 +dffeas \ula_|i2s_intf_|shiftreg[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~15_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [4]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N11 +dffeas \ula_|i2s_intf_|shiftreg[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~14_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~13_combout = (\ula_|i2s_intf_|shiftreg [5] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(\ula_|i2s_intf_|shiftreg [5]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N17 +dffeas \ula_|i2s_intf_|shiftreg[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~13_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [6]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N31 +dffeas \ula_|i2s_intf_|shiftreg[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [7]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N29 +dffeas \ula_|i2s_intf_|shiftreg[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~11_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~10_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [8]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N23 +dffeas \ula_|i2s_intf_|shiftreg[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~10_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [9]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N13 +dffeas \ula_|i2s_intf_|shiftreg[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~9_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(\ula_|i2s_intf_|shiftreg [10]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N3 +dffeas \ula_|i2s_intf_|shiftreg[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~8_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [11]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N9 +dffeas \ula_|i2s_intf_|shiftreg[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~7_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( +// Equation(s): +// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # +// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) + + .dataa(\ula_|i2s_intf_|shiftreg [14]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N31 +dffeas \ula_|i2s_intf_|PCM_INR[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|PCM_INR [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( +// Equation(s): +// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # +// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) + + .dataa(\ula_|i2s_intf_|shiftreg [14]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|PCM_INL [14]), + .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N29 +dffeas \ula_|i2s_intf_|PCM_INL[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|PCM_INL [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N6 +cycloneive_lcell_comb \ula_|pcm_outr~0 ( +// Equation(s): +// \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datad(\ula_|i2s_intf_|PCM_INL [14]), + .cin(gnd), + .combout(\ula_|pcm_outr~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; +defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N7 +dffeas \ula_|pcm_outl[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|pcm_outr~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|pcm_outl [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [12]), + .datad(\ula_|pcm_outl [12]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N15 +dffeas \ula_|i2s_intf_|shiftreg[13] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [13]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) + + .dataa(gnd), + .datab(\ula_|pcm_outl [13]), + .datac(\ula_|i2s_intf_|shiftreg [13]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCCF0; +defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N5 +dffeas \ula_|i2s_intf_|shiftreg[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N31 +dffeas \ula_|pcm_outl[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\D[4]~98_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|pcm_outl [14]), @@ -57419,24 +57790,24 @@ defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y13_N22 +// Location: LCCOMB_X28_Y22_N4 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|pcm_outl [14]), + .datab(gnd), + .datac(\ula_|pcm_outl [14]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hEE22; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF0AA; defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y13_N23 +// Location: FF_X28_Y22_N5 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~4_combout ), @@ -57445,7 +57816,7 @@ dffeas \ula_|i2s_intf_|shiftreg[15] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [15]), @@ -57455,24 +57826,24 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y13_N24 +// Location: LCCOMB_X28_Y22_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) +// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|shiftreg [15] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), .datac(\ula_|i2s_intf_|shiftreg [15]), - .datad(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h3030; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h00F0; defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y13_N25 +// Location: FF_X28_Y22_N1 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~3_combout ), @@ -57481,7 +57852,7 @@ dffeas \ula_|i2s_intf_|shiftreg[16] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [16]), @@ -57491,20 +57862,20 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y13_N30 +// Location: LCCOMB_X28_Y22_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [16]) +// \ula_|i2s_intf_|shiftreg~0_combout = (\ula_|i2s_intf_|shiftreg [16] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [16]), - .datad(gnd), + .datab(\ula_|i2s_intf_|shiftreg [16]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h3030; +defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h00CC; defparam \ula_|i2s_intf_|shiftreg~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57517,7 +57888,7 @@ dffeas \ula_|i2s_intf_|shiftreg[17] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [17]), @@ -57527,33 +57898,136 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \ula_|border[1]~feeder ( +// Location: LCCOMB_X38_Y33_N8 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( // Equation(s): -// \ula_|border[1]~feeder_combout = \D[1]~31_combout +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [6]))) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[1]~31_combout ), + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [6]), .cin(gnd), - .combout(\ula_|border[1]~feeder_combout ), + .combout(\ula_|video_|LessThan2~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N13 +// Location: LCCOMB_X38_Y33_N4 +cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( +// Equation(s): +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(\ula_|video_|vga_vc [3]), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0111; +defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N30 +cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( +// Equation(s): +// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|vga_vc [4]), + .datac(\ula_|video_|LessThan2~0_combout ), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7050; +defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N16 +cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( +// Equation(s): +// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|LessThan6~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|LessThan6~0_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h5D55; +defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N22 +cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( +// Equation(s): +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [5])) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [6]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0011; +defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N24 +cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( +// Equation(s): +// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((\ula_|video_|LessThan0~0_combout & !\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # +// ((!\ula_|video_|LessThan0~0_combout & \ula_|video_|vga_hc [7])))) + + .dataa(\ula_|video_|LessThan0~0_combout ), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [7]), + .datad(\ula_|video_|vga_hc [9]), + .cin(gnd), + .combout(\ula_|video_|disp_enable~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h3BDC; +defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N2 +cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( +// Equation(s): +// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) + + .dataa(\ula_|video_|LessThan2~1_combout ), + .datab(\ula_|video_|LessThan3~0_combout ), + .datac(gnd), + .datad(\ula_|video_|disp_enable~0_combout ), + .cin(gnd), + .combout(\ula_|video_|disp_enable~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; +defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N11 dffeas \ula_|border[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[1]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[1]~34_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), + .sload(vcc), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|border [1]), @@ -57563,7 +58037,76 @@ defparam \ula_|border[1] .is_wysiwyg = "true"; defparam \ula_|border[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y29_N4 +// Location: LCCOMB_X37_Y33_N8 +cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( +// Equation(s): +// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; +defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N28 +cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( +// Equation(s): +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [5]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; +defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y33_N10 +cycloneive_lcell_comb \ula_|video_|screen_en~0 ( +// Equation(s): +// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|LessThan4~0_combout ), + .datad(\ula_|video_|vga_hc [8]), + .cin(gnd), + .combout(\ula_|video_|screen_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1121; +defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y33_N22 +cycloneive_lcell_comb \ula_|video_|screen_en~1 ( +// Equation(s): +// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # +// (!\ula_|video_|LessThan6~1_combout ))))) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|LessThan6~1_combout ), + .datad(\ula_|video_|screen_en~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; +defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N28 cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -57580,14 +58123,14 @@ defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y30_N10 +// Location: LCCOMB_X34_Y31_N10 cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( // Equation(s): -// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) +// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), .datad(\ula_|video_|vga_hc [0]), .cin(gnd), .combout(\ula_|video_|Decoder0~1_combout ), @@ -57597,7 +58140,7 @@ defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y29_N5 +// Location: FF_X32_Y33_N29 dffeas \ula_|video_|attr_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), @@ -57616,32 +58159,15 @@ defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N4 -cycloneive_lcell_comb \ula_|video_|attr[1]~feeder ( -// Equation(s): -// \ula_|video_|attr[1]~feeder_combout = \ula_|video_|attr_prefetch [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|attr_prefetch [1]), - .cin(gnd), - .combout(\ula_|video_|attr[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y30_N0 +// Location: LCCOMB_X34_Y31_N12 cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( // Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & \ula_|video_|vga_hc [3]))) +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & \ula_|video_|vga_hc [0]))) - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [3]), + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), .cin(gnd), .combout(\ula_|video_|Decoder0~0_combout ), .cout()); @@ -57650,15 +58176,15 @@ defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y31_N5 +// Location: FF_X37_Y33_N27 dffeas \ula_|video_|attr[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr[1]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [1]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -57669,7 +58195,7 @@ defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N0 +// Location: LCCOMB_X32_Y33_N10 cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 @@ -57686,7 +58212,7 @@ defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y30_N1 +// Location: FF_X32_Y33_N11 dffeas \ula_|video_|attr_prefetch[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), @@ -57705,7 +58231,7 @@ defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N15 +// Location: FF_X37_Y33_N13 dffeas \ula_|video_|attr[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -57724,278 +58250,7 @@ defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; defparam \ula_|video_|attr[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N0 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y30_N0 -cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( -// Equation(s): -// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0020; -defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N1 -dffeas \ula_|video_|bits_prefetch[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N7 -dffeas \ula_|video_|bits[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N2 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N3 -dffeas \ula_|video_|bits_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N13 -dffeas \ula_|video_|bits[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y23_N16 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y23_N17 -dffeas \ula_|video_|bits_prefetch[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N25 -dffeas \ula_|video_|bits[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y25_N28 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y25_N29 -dffeas \ula_|video_|bits_prefetch[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N19 -dffeas \ula_|video_|bits[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y31_N18 -cycloneive_lcell_comb \ula_|video_|Mux0~0 ( -// Equation(s): -// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [5]), - .datac(\ula_|video_|bits [7]), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE50; -defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y31_N12 -cycloneive_lcell_comb \ula_|video_|Mux0~1 ( -// Equation(s): -// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [6]), - .datac(\ula_|video_|bits [4]), - .datad(\ula_|video_|Mux0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; -defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y25_N26 +// Location: LCCOMB_X32_Y33_N24 cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58012,7 +58267,7 @@ defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y25_N27 +// Location: FF_X32_Y33_N25 dffeas \ula_|video_|attr_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), @@ -58031,7 +58286,7 @@ defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N27 +// Location: FF_X36_Y33_N5 dffeas \ula_|video_|attr[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58050,24 +58305,24 @@ defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N28 +// Location: LCCOMB_X34_Y33_N22 cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( // Equation(s): -// \ula_|video_|frame[0]~12_combout = \ula_|video_|frame [0] $ (\ula_|video_|Equal3~1_combout ) +// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) - .dataa(gnd), + .dataa(\ula_|video_|Equal3~1_combout ), .datab(gnd), .datac(\ula_|video_|frame [0]), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|frame[0]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h0FF0; +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h5A5A; defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N29 +// Location: FF_X34_Y33_N23 dffeas \ula_|video_|frame[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[0]~12_combout ), @@ -58086,14 +58341,14 @@ defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; defparam \ula_|video_|frame[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N4 +// Location: LCCOMB_X35_Y33_N24 cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( // Equation(s): -// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [1] & (\ula_|video_|frame [0] $ (VCC))) # (!\ula_|video_|frame [1] & (\ula_|video_|frame [0] & VCC)) -// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [1] & \ula_|video_|frame [0])) +// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) +// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [0] & \ula_|video_|frame [1])) - .dataa(\ula_|video_|frame [1]), - .datab(\ula_|video_|frame [0]), + .dataa(\ula_|video_|frame [0]), + .datab(\ula_|video_|frame [1]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -58104,15 +58359,15 @@ defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y30_N13 +// Location: FF_X35_Y33_N25 dffeas \ula_|video_|frame[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[1]~4_combout ), + .d(\ula_|video_|frame[1]~4_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58123,33 +58378,33 @@ defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; defparam \ula_|video_|frame[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N6 +// Location: LCCOMB_X35_Y33_N26 cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( // Equation(s): // \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) // \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - .dataa(gnd), - .datab(\ula_|video_|frame [2]), + .dataa(\ula_|video_|frame [2]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[1]~5 ), .combout(\ula_|video_|frame[2]~6_combout ), .cout(\ula_|video_|frame[2]~7 )); // synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h5A5F; defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N21 +// Location: FF_X35_Y33_N27 dffeas \ula_|video_|frame[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[2]~6_combout ), + .d(\ula_|video_|frame[2]~6_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58160,25 +58415,25 @@ defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; defparam \ula_|video_|frame[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N8 +// Location: LCCOMB_X35_Y33_N28 cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( // Equation(s): // \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) // \ula_|video_|frame[3]~9 = CARRY((\ula_|video_|frame [3] & !\ula_|video_|frame[2]~7 )) - .dataa(\ula_|video_|frame [3]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|frame [3]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[2]~7 ), .combout(\ula_|video_|frame[3]~8_combout ), .cout(\ula_|video_|frame[3]~9 )); // synopsys translate_off -defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X36_Y31_N9 +// Location: FF_X35_Y33_N29 dffeas \ula_|video_|frame[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[3]~8_combout ), @@ -58197,32 +58452,32 @@ defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; defparam \ula_|video_|frame[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N10 +// Location: LCCOMB_X35_Y33_N30 cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( // Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame [4] $ (\ula_|video_|frame[3]~9 ) - .dataa(gnd), + .dataa(\ula_|video_|frame [4]), .datab(gnd), .datac(gnd), - .datad(\ula_|video_|frame [4]), + .datad(gnd), .cin(\ula_|video_|frame[3]~9 ), .combout(\ula_|video_|frame[4]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h5A5A; defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X36_Y31_N17 +// Location: FF_X35_Y33_N31 dffeas \ula_|video_|frame[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[4]~10_combout ), + .d(\ula_|video_|frame[4]~10_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58233,7 +58488,7 @@ defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; defparam \ula_|video_|frame[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N26 +// Location: LCCOMB_X36_Y33_N4 cycloneive_lcell_comb \ula_|video_|inverted ( // Equation(s): // \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) @@ -58250,7 +58505,312 @@ defparam \ula_|video_|inverted .lut_mask = 16'hF000; defparam \ula_|video_|inverted .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y21_N0 +// Location: LCCOMB_X32_Y33_N12 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( +// Equation(s): +// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0008; +defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N13 +dffeas \ula_|video_|bits_prefetch[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N6 +cycloneive_lcell_comb \ula_|video_|bits[6]~feeder ( +// Equation(s): +// \ula_|video_|bits[6]~feeder_combout = \ula_|video_|bits_prefetch [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [6]), + .cin(gnd), + .combout(\ula_|video_|bits[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N7 +dffeas \ula_|video_|bits[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N22 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N23 +dffeas \ula_|video_|bits_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y33_N23 +dffeas \ula_|video_|bits[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N18 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N19 +dffeas \ula_|video_|bits_prefetch[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N18 +cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( +// Equation(s): +// \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [5]), + .cin(gnd), + .combout(\ula_|video_|bits[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N19 +dffeas \ula_|video_|bits[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N0 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N1 +dffeas \ula_|video_|bits_prefetch[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y33_N1 +dffeas \ula_|video_|bits[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N0 +cycloneive_lcell_comb \ula_|video_|Mux0~0 ( +// Equation(s): +// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) + + .dataa(\ula_|video_|bits [5]), + .datab(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|bits [7]), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N22 +cycloneive_lcell_comb \ula_|video_|Mux0~1 ( +// Equation(s): +// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) + + .dataa(\ula_|video_|bits [6]), + .datab(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|bits [4]), + .datad(\ula_|video_|Mux0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N16 cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58267,7 +58827,7 @@ defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y21_N1 +// Location: FF_X32_Y33_N17 dffeas \ula_|video_|bits_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), @@ -58286,15 +58846,32 @@ defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N5 +// Location: LCCOMB_X36_Y33_N12 +cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( +// Equation(s): +// \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [2]), + .cin(gnd), + .combout(\ula_|video_|bits[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N13 dffeas \ula_|video_|bits[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [2]), + .d(\ula_|video_|bits[2]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58305,7 +58882,7 @@ defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y27_N4 +// Location: LCCOMB_X32_Y33_N14 cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -58322,7 +58899,7 @@ defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y27_N5 +// Location: FF_X32_Y33_N15 dffeas \ula_|video_|bits_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), @@ -58341,7 +58918,7 @@ defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N21 +// Location: FF_X36_Y33_N3 dffeas \ula_|video_|bits[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58360,7 +58937,7 @@ defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y29_N6 +// Location: LCCOMB_X32_Y33_N6 cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -58377,7 +58954,7 @@ defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y29_N7 +// Location: FF_X32_Y33_N7 dffeas \ula_|video_|bits_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), @@ -58396,7 +58973,7 @@ defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N24 +// Location: LCCOMB_X36_Y33_N26 cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( // Equation(s): // \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] @@ -58413,7 +58990,7 @@ defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y31_N25 +// Location: FF_X36_Y33_N27 dffeas \ula_|video_|bits[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[1]~feeder_combout ), @@ -58432,24 +59009,24 @@ defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N18 +// Location: LCCOMB_X32_Y33_N4 cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), - .datad(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), .cin(gnd), .combout(\ula_|video_|bits_prefetch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hF0F0; +defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y31_N19 +// Location: FF_X32_Y33_N5 dffeas \ula_|video_|bits_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), @@ -58468,7 +59045,7 @@ defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N3 +// Location: FF_X36_Y33_N25 dffeas \ula_|video_|bits[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58487,58 +59064,58 @@ defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N2 +// Location: LCCOMB_X36_Y33_N24 cycloneive_lcell_comb \ula_|video_|Mux0~2 ( // Equation(s): // \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [1]), + .dataa(\ula_|video_|bits [1]), + .datab(\ula_|video_|vga_hc [1]), .datac(\ula_|video_|bits [3]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE30; defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N20 +// Location: LCCOMB_X36_Y33_N2 cycloneive_lcell_comb \ula_|video_|Mux0~3 ( // Equation(s): // \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [2]), + .dataa(\ula_|video_|bits [2]), + .datab(\ula_|video_|vga_hc [1]), .datac(\ula_|video_|bits [0]), .datad(\ula_|video_|Mux0~2_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF388; defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N28 +// Location: LCCOMB_X36_Y33_N10 cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( // Equation(s): // \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - .dataa(\ula_|video_|Mux0~1_combout ), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|inverted~combout ), + .dataa(\ula_|video_|vga_hc [3]), + .datab(\ula_|video_|inverted~combout ), + .datac(\ula_|video_|Mux0~1_combout ), .datad(\ula_|video_|Mux0~3_combout ), .cin(gnd), .combout(\ula_|video_|cindex[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h1ED2; +defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h369C; defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N14 +// Location: LCCOMB_X37_Y33_N12 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): // \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) @@ -58555,213 +59132,24 @@ defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N4 -cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( -// Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|vga_vc [3]), - .cin(gnd), - .combout(\ula_|video_|LessThan6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0013; -defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N24 -cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( -// Equation(s): -// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan6~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; -defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N30 -cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( -// Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [6])) # (!\ula_|video_|vga_hc [7]) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|LessThan4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; -defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N22 -cycloneive_lcell_comb \ula_|video_|screen_en~0 ( -// Equation(s): -// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|vga_hc [9]), - .datad(\ula_|video_|LessThan4~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1203; -defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N26 -cycloneive_lcell_comb \ula_|video_|screen_en~1 ( -// Equation(s): -// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # -// (!\ula_|video_|LessThan6~1_combout ))))) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(\ula_|video_|LessThan6~1_combout ), - .datac(\ula_|video_|screen_en~0_combout ), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|screen_en~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~1 .lut_mask = 16'hD0B0; -defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N12 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( -// Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N26 -cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( -// Equation(s): -// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|LessThan6~0_combout ), - .datad(\ula_|video_|LessThan2~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7500; -defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N14 -cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( -// Equation(s): -// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|Equal2~0_combout & (\ula_|video_|LessThan6~0_combout & !\ula_|video_|vga_vc [5]))) # (!\ula_|video_|vga_vc [9]) - - .dataa(\ula_|video_|Equal2~0_combout ), - .datab(\ula_|video_|LessThan6~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|vga_vc [9]), - .cin(gnd), - .combout(\ula_|video_|LessThan3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h08FF; -defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N2 -cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( -// Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [6]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|vga_hc [5]), - .cin(gnd), - .combout(\ula_|video_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0003; -defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N28 -cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( -// Equation(s): -// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & -// !\ula_|video_|LessThan0~0_combout )))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [9]), - .datad(\ula_|video_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|disp_enable~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; -defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N16 -cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( -// Equation(s): -// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) - - .dataa(\ula_|video_|LessThan2~1_combout ), - .datab(\ula_|video_|LessThan3~0_combout ), - .datac(gnd), - .datad(\ula_|video_|disp_enable~0_combout ), - .cin(gnd), - .combout(\ula_|video_|disp_enable~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; -defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y31_N22 +// Location: LCCOMB_X37_Y33_N24 cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( // Equation(s): // \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - .dataa(\ula_|border [1]), - .datab(\ula_|video_|cindex[1]~1_combout ), + .dataa(\ula_|video_|disp_enable~1_combout ), + .datab(\ula_|border [1]), .datac(\ula_|video_|screen_en~1_combout ), - .datad(\ula_|video_|disp_enable~1_combout ), + .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hCA00; +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hA808; defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N14 +// Location: LCCOMB_X32_Y33_N26 cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 @@ -58778,7 +59166,7 @@ defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N15 +// Location: FF_X32_Y33_N27 dffeas \ula_|video_|attr_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), @@ -58797,7 +59185,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X35_Y31_N19 +// Location: FF_X38_Y33_N1 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58816,50 +59204,50 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N18 +// Location: LCCOMB_X38_Y33_N0 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): -// \ula_|video_|VGA_B[1]~0_combout = (\ula_|video_|LessThan3~0_combout & (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) +// \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) - .dataa(\ula_|video_|LessThan3~0_combout ), - .datab(\ula_|video_|LessThan2~1_combout ), + .dataa(\ula_|video_|LessThan2~1_combout ), + .datab(\ula_|video_|LessThan3~0_combout ), .datac(\ula_|video_|attr [6]), .datad(\ula_|video_|disp_enable~0_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h2000; +defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N16 +// Location: LCCOMB_X37_Y33_N2 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): -// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[1]~1_combout & \ula_|video_|VGA_B[1]~0_combout )) +// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[1]~1_combout )) .dataa(\ula_|video_|screen_en~1_combout ), - .datab(\ula_|video_|cindex[1]~1_combout ), - .datac(gnd), - .datad(\ula_|video_|VGA_B[1]~0_combout ), + .datab(gnd), + .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8800; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N3 +// Location: FF_X31_Y12_N17 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\D[2]~40_combout ), + .asdata(\D[2]~46_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\ula_|always0~1_combout ), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|border [2]), @@ -58869,7 +59257,7 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y21_N30 +// Location: LCCOMB_X32_Y33_N8 cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58886,7 +59274,7 @@ defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y21_N31 +// Location: FF_X32_Y33_N9 dffeas \ula_|video_|attr_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), @@ -58905,7 +59293,7 @@ defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N11 +// Location: FF_X36_Y33_N21 dffeas \ula_|video_|attr[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58924,7 +59312,7 @@ defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y23_N14 +// Location: LCCOMB_X32_Y33_N30 cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -58941,7 +59329,7 @@ defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y23_N15 +// Location: FF_X32_Y33_N31 dffeas \ula_|video_|attr_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), @@ -58960,7 +59348,7 @@ defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N1 +// Location: FF_X36_Y33_N15 dffeas \ula_|video_|attr[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58979,49 +59367,49 @@ defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N0 +// Location: LCCOMB_X36_Y33_N14 cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( // Equation(s): // \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) - .dataa(\ula_|video_|attr [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|attr [2]), .datac(\ula_|video_|attr [5]), .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N30 +// Location: LCCOMB_X38_Y33_N26 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) .dataa(\ula_|border [2]), - .datab(\ula_|video_|disp_enable~1_combout ), - .datac(\ula_|video_|screen_en~1_combout ), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hC808; +defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hE020; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N24 +// Location: LCCOMB_X36_Y33_N20 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|VGA_B[1]~0_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|screen_en~1_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), .datab(\ula_|video_|cindex[2]~2_combout ), .datac(gnd), - .datad(\ula_|video_|VGA_B[1]~0_combout ), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), .cout()); @@ -59030,33 +59418,16 @@ defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \ula_|border[0]~feeder ( -// Equation(s): -// \ula_|border[0]~feeder_combout = \D[0]~49_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[0]~49_combout ), - .cin(gnd), - .combout(\ula_|border[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N9 +// Location: FF_X32_Y22_N1 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[0]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[0]~58_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), + .sload(vcc), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|border [0]), @@ -59066,7 +59437,7 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y27_N6 +// Location: LCCOMB_X32_Y33_N20 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -59083,7 +59454,7 @@ defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y27_N7 +// Location: FF_X32_Y33_N21 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -59102,15 +59473,32 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y31_N7 +// Location: LCCOMB_X37_Y33_N28 +cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( +// Equation(s): +// \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|attr_prefetch [0]), + .cin(gnd), + .combout(\ula_|video_|attr[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y33_N29 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [0]), + .d(\ula_|video_|attr[0]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59121,15 +59509,32 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X34_Y31_N13 +// Location: LCCOMB_X32_Y33_N2 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N3 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59140,7 +59545,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y31_N9 +// Location: FF_X36_Y33_N29 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59159,49 +59564,49 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N8 +// Location: LCCOMB_X36_Y33_N28 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): // \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) - .dataa(\ula_|video_|attr [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|attr [0]), .datac(\ula_|video_|attr [3]), .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N2 +// Location: LCCOMB_X37_Y33_N30 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) - .dataa(\ula_|border [0]), - .datab(\ula_|video_|cindex[0]~3_combout ), - .datac(\ula_|video_|disp_enable~1_combout ), - .datad(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|video_|disp_enable~1_combout ), + .datab(\ula_|border [0]), + .datac(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hC0A0; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hA808; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y31_N0 +// Location: LCCOMB_X37_Y33_N0 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[0]~3_combout & \ula_|video_|VGA_B[1]~0_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[0]~3_combout )) .dataa(\ula_|video_|screen_en~1_combout ), .datab(gnd), - .datac(\ula_|video_|cindex[0]~3_combout ), - .datad(\ula_|video_|VGA_B[1]~0_combout ), + .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~2_combout ), .cout()); @@ -59210,24 +59615,24 @@ defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N4 +// Location: LCCOMB_X37_Y33_N26 cycloneive_lcell_comb \ula_|video_|Equal0~2 ( // Equation(s): -// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_hc [8] & \ula_|video_|vga_hc [6])) +// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [9] & !\ula_|video_|vga_hc [8])) - .dataa(\ula_|video_|vga_hc [9]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [6]), + .dataa(\ula_|video_|vga_hc [6]), + .datab(\ula_|video_|vga_hc [9]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [8]), .cin(gnd), .combout(\ula_|video_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0500; +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0022; defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y31_N9 +// Location: FF_X37_Y33_N7 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -59246,21 +59651,21 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N8 +// Location: LCCOMB_X37_Y33_N6 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): -// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|VGA_HS~_Duplicate_1_q & \ula_|video_|Equal1~0_combout )))) # (!\ula_|video_|Equal0~2_combout & (((\ula_|video_|VGA_HS~_Duplicate_1_q -// & \ula_|video_|Equal1~0_combout )))) +// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & +// (\ula_|video_|VGA_HS~_Duplicate_1_q ))) .dataa(\ula_|video_|Equal0~2_combout ), - .datab(\ula_|video_|Equal0~1_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|VGA_HS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal0~1_combout ), .cin(gnd), .combout(\ula_|video_|Selector0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector0~0 .lut_mask = 16'hF888; +defparam \ula_|video_|Selector0~0 .lut_mask = 16'hEAC0; defparam \ula_|video_|Selector0~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59283,7 +59688,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y31_N31 +// Location: FF_X34_Y33_N25 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -59302,21 +59707,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N30 +// Location: LCCOMB_X34_Y33_N24 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1]) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|Equal2~2_combout & (((\ula_|video_|VGA_VS~_Duplicate_1_q & -// !\ula_|video_|Equal3~1_combout )))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal3~1_combout & (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1])))) # (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|VGA_VS~_Duplicate_1_q ) # ((\ula_|video_|Equal2~2_combout & +// \ula_|video_|vga_vc [1])))) - .dataa(\ula_|video_|Equal2~2_combout ), - .datab(\ula_|video_|vga_vc [1]), + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Equal2~2_combout ), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'hDC50; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59339,7 +59744,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N30 +// Location: LCCOMB_X47_Y17_N4 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -59356,7 +59761,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N31 +// Location: FF_X47_Y17_N5 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -59375,7 +59780,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X52_Y13_N9 +// Location: FF_X47_Y17_N25 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -59394,7 +59799,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N8 +// Location: LCCOMB_X47_Y17_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -59411,41 +59816,41 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N22 +// Location: LCCOMB_X47_Y17_N26 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(gnd), .datab(gnd), - .datac(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nM1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF55; +defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y16_N4 +// Location: LCCOMB_X23_Y26_N0 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[3]~77_combout $ (\D[4]~79_combout $ (((\ula_|i2s_intf_|PCM_INL [14]) # (\ula_|i2s_intf_|PCM_INR [14])))) +// \ula_|beep~0_combout = \D[4]~98_combout $ (\raw_loader_in~input_o $ (\D[3]~96_combout )) - .dataa(\D[3]~77_combout ), - .datab(\ula_|i2s_intf_|PCM_INL [14]), - .datac(\D[4]~79_combout ), - .datad(\ula_|i2s_intf_|PCM_INR [14]), + .dataa(gnd), + .datab(\D[4]~98_combout ), + .datac(\raw_loader_in~input_o ), + .datad(\D[3]~96_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hA596; +defparam \ula_|beep~0 .lut_mask = 16'hC33C; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y16_N5 +// Location: FF_X23_Y26_N1 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), @@ -59454,7 +59859,7 @@ dffeas \ula_|beep ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|always0~1_combout ), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|beep~q ), diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo index c295d00..5f5d1b7 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/31/2022 14:04:23" +// DATE "04/01/2022 18:55:51" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -49,14 +49,15 @@ module spectrum ( VGA_VS, SW, GPIO_1, - buzzer_out); + buzzer_out, + raw_loader_in); output [7:0] LED; input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -inout I2C_SCLK; -inout I2C_SDAT; +output I2C_SCLK; +output I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -71,6 +72,7 @@ output VGA_VS; input [3:0] SW; output [33:0] GPIO_1; output buzzer_out; +input raw_loader_in; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -141,10 +143,11 @@ output buzzer_out; // I2C_SDAT => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[1] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: Default // SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// raw_loader_in => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: Default // KEY[0] => Location: PIN_J15, I/O Standard: 3.3-V LVTTL, Current Strength: Default // CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default -// KEY[1] => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_DAT => Location: PIN_B7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// KEY[1] => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_CLK => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default // AUD_ADCDAT => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -175,7 +178,692 @@ wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; +wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; wire \z80_|sequencer_|ena_M~combout ; +wire \KEY[1]~input_o ; +wire \z80_|interrupts_|nmi_armed~feeder_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; +wire \z80_|interrupts_|nmi_armed~q ; +wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~q ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~q ; +wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal1~7_combout ; +wire \z80_|pla_decode_|Equal2~0_combout ; +wire \z80_|pla_decode_|Equal36~0_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|pla_decode_|Equal2~1_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_sw_1d~8_combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~1_combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; +wire \z80_|execute_|ctl_state_iy_set~2_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|pla_decode_|Equal50~0_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|execute_|ixy_d~17_combout ; +wire \z80_|execute_|ixy_d~5_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~15_combout ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|execute_|ctl_ir_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~14_combout ; +wire \z80_|execute_|ctl_mWrite~2_combout ; +wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|ctl_reg_in_hi~5_combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|pla_decode_|Equal9~0_combout ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|pla_decode_|Equal9~1_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|pla_decode_|Equal1~4_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; +wire \z80_|pla_decode_|Equal24~1_combout ; +wire \z80_|pla_decode_|Equal34~0_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|sequencer_|M5~0_combout ; +wire \z80_|sequencer_|M5~q ; +wire \z80_|execute_|ctl_reg_in_hi~2_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; +wire \z80_|execute_|ctl_ir_we~7_combout ; +wire \z80_|pla_decode_|Equal52~1_combout ; +wire \z80_|execute_|ctl_state_alu~14_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|execute_|fMRead~17_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|fMRead~16_combout ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_flags_alu~6_combout ; +wire \z80_|execute_|ctl_ir_we~6_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_reg_in_hi~3_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; +wire \z80_|execute_|ctl_mRead~36_combout ; +wire \z80_|execute_|ctl_alu_op_low~9_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|execute_|ctl_alu_op_low~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|alu_|db_low[2]~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|pla_decode_|Equal1~5_combout ; +wire \z80_|execute_|ctl_alu_op_low~14_combout ; +wire \z80_|execute_|ctl_alu_op_low~12_combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~11_combout ; +wire \z80_|execute_|nextM~2_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_oe~3_combout ; +wire \z80_|execute_|ctl_alu_op_low~15_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~13_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|ctl_flags_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op_low~13_combout ; +wire \z80_|execute_|ctl_flags_bus~15_combout ; +wire \z80_|execute_|ctl_flags_bus~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|execute_|ctl_flags_bus~12_combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_bus_db_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|execute_|ctl_alu_op_low~10_combout ; +wire \z80_|execute_|fMWrite~11_combout ; +wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|execute_|ctl_alu_op_low~22_combout ; +wire \z80_|execute_|ctl_alu_op_low~16_combout ; +wire \z80_|execute_|ctl_alu_op_low~17_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_gp_sel~36_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_alu_op_low~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~19_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_alu_op_low~20_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~14_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|execute_|ctl_flags_alu~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|pla_decode_|Equal11~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; +wire \z80_|execute_|ctl_alu_oe~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_oe~15_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; +wire \z80_|alu_|db_low[2]~24_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_alu_oe~12_combout ; +wire \z80_|execute_|ctl_alu_oe~13_combout ; +wire \z80_|execute_|ctl_alu_oe~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; +wire \z80_|execute_|ctl_reg_out_hi~8_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|execute_|ctl_sw_2u~1_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_inc_cy~35_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_mWrite~6_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_sw_2u~0_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~7_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|execute_|ctl_inc_cy~34_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~92_combout ; +wire \z80_|pla_decode_|Equal19~1_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_inc_cy~38_combout ; +wire \z80_|execute_|ctl_inc_cy~93_combout ; +wire \z80_|execute_|ctl_inc_cy~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; +wire \z80_|execute_|ctl_reg_gp_we~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|fMRead~3_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; +wire \z80_|execute_|ctl_inc_cy~94_combout ; +wire \z80_|execute_|ctl_inc_cy~87_combout ; +wire \z80_|execute_|ctl_inc_cy~42_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|pla_decode_|Equal1~6_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~12_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~13_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|fMWrite~3_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~7_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_sw_1d~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|execute_|setM1~47_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_al_we~13_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_reg_in_hi~13_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_inc_cy~40_combout ; +wire \z80_|execute_|ctl_inc_dec~2_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_inc_cy~43_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_state_alu~13_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_state_alu~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|reg_control_|reg_sel_de2~5_combout ; +wire \z80_|reg_control_|reg_sel_de2~6_combout ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_al_we~14_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|ctl_flags_bus~13_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|pc_inc_hold~49_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|fMRead~5_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; +wire \z80_|execute_|pc_inc_hold~29_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|execute_|ctl_reg_in_hi~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; +wire \z80_|execute_|fMRead~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; +wire \z80_|execute_|fMRead~1_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|ctl_sw_4d~1_combout ; +wire \z80_|execute_|ctl_sw_4d~0_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|execute_|fMRead~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; wire \KEY[0]~input_o ; wire \reset~combout ; @@ -184,801 +872,92 @@ wire \z80_|fpga_reset~feeder_combout ; wire \z80_|fpga_reset~q ; wire \z80_|fpga_reset~clkctrl_outclk ; wire \z80_|resets_|x1~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \KEY[1]~input_o ; -wire \z80_|interrupts_|nmi_armed~feeder_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; -wire \z80_|interrupts_|nmi_armed~q ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|execute_|ctl_ir_we~4_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|pla_decode_|Equal9~0_combout ; -wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|sequencer_|M5~0_combout ; -wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; -wire \z80_|execute_|ctl_mWrite~3_combout ; -wire \z80_|execute_|ctl_mWrite~16_combout ; -wire \z80_|execute_|ixy_d~4_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|pla_decode_|Equal41~1_combout ; -wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ixy_d~8_combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|pla_decode_|Equal19~0_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|execute_|ctl_state_alu~2_combout ; -wire \z80_|execute_|ctl_inc_cy~36_combout ; -wire \z80_|execute_|ctl_inc_dec~0_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|fMWrite~0_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|pla_decode_|Equal19~1_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; -wire \z80_|execute_|ctl_state_alu~3_combout ; -wire \z80_|execute_|ctl_inc_cy~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|execute_|ctl_inc_cy~30_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|fMWrite~1_combout ; -wire \z80_|execute_|fMWrite~2_combout ; -wire \z80_|execute_|fMWrite~3_combout ; -wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|execute_|ctl_inc_cy~34_combout ; -wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|execute_|ctl_inc_cy~35_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|execute_|ctl_mRead~38_combout ; -wire \z80_|execute_|fIOWrite~1_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|execute_|fMRead~2_combout ; -wire \z80_|execute_|ctl_mWrite~2_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|execute_|ctl_inc_cy~32_combout ; -wire \z80_|execute_|ctl_inc_cy~33_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; -wire \z80_|address_pins_|abus[0]~18_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|WideOr16~5_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|WideOr16~7_combout ; -wire \ula_|zx_keyboard_|WideOr16~6_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|pc_inc_hold~19_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|ctl_inc_cy~37_combout ; -wire \z80_|execute_|ctl_inc_dec~1_combout ; -wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; wire \z80_|resets_|clrpc_int~0_combout ; wire \z80_|resets_|clrpc_int~q ; wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|execute_|ctl_inc_cy~47_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|execute_|ctl_inc_cy~38_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|fMRead~12_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~3_combout ; -wire \z80_|execute_|fMRead~13_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~25_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|nextM~11_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~8_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_reg_in_hi~13_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_we~9_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_we~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~8_combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_sel~5_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|pla_decode_|Equal11~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|ctl_iorw~12_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; -wire \z80_|execute_|ctl_bus_db_oe~2_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|pla_decode_|Equal76~0_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~7_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; -wire \z80_|execute_|setM1~56_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~40_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|pc_inc_hold~18_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ; -wire \z80_|execute_|pc_inc_hold~40_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~11_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|ctl_alu_op_low~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_flags_alu~6_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_flags_alu~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~19_combout ; -wire \z80_|execute_|ctl_flags_alu~7_combout ; -wire \z80_|execute_|ctl_flags_alu~9_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|reg_control_|reg_sel_de2~6_combout ; -wire \z80_|reg_control_|reg_sel_de2~5_combout ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~22_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; -wire \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~23_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~24_combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~26_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~25_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~39_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|fMRead~11_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~28_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~29_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~30_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_bus_db_oe~6_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|fMRead~9_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|alu_|db[7]~19_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~52_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~53_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~56_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_file_|db_hi_as[3]~13_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|db_hi_as[3]~14_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; wire \z80_|execute_|ctl_apin_mux~1_combout ; wire \z80_|execute_|ctl_al_we~6_combout ; wire \z80_|execute_|ctl_al_we~7_combout ; wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; wire \z80_|execute_|ctl_al_we~11_combout ; wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|execute_|ctl_inc_cy~78_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|reg_file_|db_hi_as[3]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~57_combout ; -wire \z80_|alu_|db[3]~13_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_sz_we~5_combout ; -wire \z80_|execute_|ctl_flags_sz_we~6_combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_flags_xy_we~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~14_combout ; -wire \z80_|execute_|ctl_flags_xy_we~15_combout ; -wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[3]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|Add0~15 ; wire \ula_|video_|Add0~16_combout ; wire \ula_|video_|vga_hc~2_combout ; wire \ula_|video_|Add0~17 ; wire \ula_|video_|Add0~18_combout ; wire \ula_|video_|vga_hc~1_combout ; -wire \ula_|video_|Equal0~0_combout ; -wire \ula_|video_|Equal0~1_combout ; -wire \ula_|video_|Equal1~0_combout ; +wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; wire \ula_|video_|Add0~1 ; wire \ula_|video_|Add0~2_combout ; +wire \ula_|video_|vga_hc[1]~feeder_combout ; wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; -wire \ula_|video_|vga_hc[2]~feeder_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; +wire \ula_|video_|vga_hc[3]~feeder_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; +wire \ula_|video_|Equal0~0_combout ; +wire \ula_|video_|Equal0~1_combout ; +wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add0~9 ; wire \ula_|video_|Add0~10_combout ; wire \ula_|video_|vga_hc~0_combout ; @@ -987,8 +966,6 @@ wire \ula_|video_|Add0~12_combout ; wire \ula_|video_|Add0~13 ; wire \ula_|video_|Add0~14_combout ; wire \ula_|video_|Add1~0_combout ; -wire \ula_|video_|vga_vc[0]~0_combout ; -wire \ula_|video_|Add1~1 ; wire \ula_|video_|Add1~3 ; wire \ula_|video_|Add1~4_combout ; wire \ula_|video_|vga_vc[2]~2_combout ; @@ -1010,22 +987,24 @@ wire \ula_|video_|vga_vc[7]~6_combout ; wire \ula_|video_|Add1~15 ; wire \ula_|video_|Add1~16_combout ; wire \ula_|video_|vga_vc[8]~7_combout ; -wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Add1~17 ; wire \ula_|video_|Add1~18_combout ; wire \ula_|video_|vga_vc[9]~9_combout ; +wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~0_combout ; wire \ula_|video_|Equal3~1_combout ; +wire \ula_|video_|vga_vc[0]~0_combout ; +wire \ula_|video_|Add1~1 ; wire \ula_|video_|Add1~2_combout ; wire \ula_|video_|vga_vc[1]~1_combout ; wire \SW[1]~input_o ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|iff1~0_combout ; wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; wire \z80_|interrupts_|DFFE_instIFF2~q ; +wire \z80_|interrupts_|iff1~0_combout ; wire \z80_|interrupts_|iff1~1_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; wire \z80_|interrupts_|iff1~q ; @@ -1033,875 +1012,787 @@ wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|interrupts_|int_armed~q ; -wire \z80_|interrupts_|DFFE_inst44~feeder_combout ; wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_cy~49_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~22_combout ; -wire \z80_|execute_|pc_inc_hold~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~23_combout ; -wire \z80_|execute_|pc_inc_hold~25_combout ; -wire \z80_|execute_|pc_inc_hold~20_combout ; -wire \z80_|execute_|pc_inc_hold~41_combout ; -wire \z80_|execute_|pc_inc_hold~21_combout ; -wire \z80_|execute_|pc_inc_hold~26_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|ctl_inc_cy~43_combout ; -wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~42_combout ; -wire \z80_|execute_|pc_inc_hold~27_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|ctl_inc_cy~40_combout ; -wire \z80_|execute_|ctl_inc_cy~41_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~42_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; -wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|pc_inc_hold~38_combout ; +wire \z80_|execute_|ctl_inc_cy~91_combout ; +wire \z80_|execute_|pc_inc_hold~45_combout ; +wire \z80_|execute_|pc_inc_hold~44_combout ; +wire \z80_|execute_|pc_inc_hold~46_combout ; +wire \z80_|execute_|pc_inc_hold~37_combout ; +wire \z80_|execute_|pc_inc_hold~50_combout ; wire \z80_|execute_|pc_inc_hold~33_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~31_combout ; +wire \z80_|execute_|pc_inc_hold~32_combout ; +wire \z80_|execute_|pc_inc_hold~34_combout ; +wire \z80_|execute_|pc_inc_hold~51_combout ; +wire \z80_|execute_|pc_inc_hold~30_combout ; +wire \z80_|execute_|pc_inc_hold~52_combout ; +wire \z80_|execute_|pc_inc_hold~35_combout ; +wire \z80_|execute_|pc_inc_hold~36_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|pc_inc_hold~43_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_inc_cy~46_combout ; +wire \z80_|execute_|pc_inc_hold~53_combout ; +wire \z80_|execute_|pc_inc_hold~39_combout ; +wire \z80_|execute_|pc_inc_hold~47_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|execute_|ctl_inc_cy~78_combout ; +wire \z80_|execute_|ctl_inc_cy~79_combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~82_combout ; +wire \z80_|execute_|ctl_inc_cy~83_combout ; +wire \z80_|execute_|ctl_inc_cy~84_combout ; +wire \z80_|execute_|pc_inc_hold~42_combout ; +wire \z80_|execute_|ctl_inc_cy~90_combout ; +wire \z80_|execute_|pc_inc_hold~41_combout ; wire \z80_|execute_|ctl_inc_cy~66_combout ; wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~31_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op_low~39_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|pla_decode_|Equal72~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~0_combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; -wire \z80_|execute_|ctl_flags_nf_we~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|execute_|ctl_alu_op_low~38_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_alu_core_R~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~35_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|alu_|db_high[3]~0_combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|alu_|db_high[3]~1_combout ; -wire \z80_|alu_|db_low[3]~2_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|alu_|db_low[3]~3_combout ; -wire \z80_|alu_|db_low[3]~4_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|db_high[2]~25_combout ; -wire \z80_|reg_file_|db_hi_as[6]~0_combout ; -wire \z80_|reg_file_|db_hi_as[6]~1_combout ; -wire \z80_|reg_file_|db_hi_as[6]~3_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~14_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~8_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~21_combout ; -wire \z80_|interrupts_|im2~feeder_combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|sw1_|db_down[6]~0_combout ; -wire \z80_|alu_|db_low[1]~10_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|alu_|db_high[1]~3_combout ; -wire \z80_|alu_|db_high[1]~2_combout ; -wire \z80_|alu_|db[7]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~74_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~75_combout ; -wire \z80_|alu_|db[5]~23_combout ; -wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~22_combout ; -wire \z80_|reg_file_|db_hi_as[4]~23_combout ; -wire \z80_|reg_file_|db_hi_as[4]~24_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~77_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~79_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~82_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~84_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_inc_cy~36_combout ; +wire \z80_|execute_|ctl_inc_cy~37_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~41_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~89_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|execute_|ctl_inc_cy~48_combout ; +wire \z80_|execute_|pc_inc_hold~40_combout ; +wire \z80_|execute_|ctl_inc_cy~61_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|ctl_inc_cy~85_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|address_latch_|Q[0]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_|alu_op1[2]~2_combout ; -wire \z80_|alu_|alu_op1[1]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|db[1]~15_combout ; -wire \z80_|alu_|db[1]~16_combout ; -wire \z80_|reg_file_|db_hi_as[0]~10_combout ; -wire \z80_|reg_file_|db_hi_as[0]~11_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; -wire \z80_|reg_file_|db_lo_as[6]~19_combout ; -wire \z80_|reg_file_|db_lo_as[6]~20_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; -wire \z80_|reg_file_|db_lo_as[5]~16_combout ; -wire \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|db_lo_as[5]~17_combout ; -wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|Q[5]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|db_lo_as[6]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|address_latch_|Q[7]~feeder_combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; +wire \z80_|address_latch_|Q[2]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; +wire \z80_|execute_|ctl_inc_cy~86_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; +wire \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|db_hi_as[1]~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|reg_file_|db_hi_as[0]~2_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~41_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~44_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~45_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~43_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~46_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~40_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~47_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~48_combout ; -wire \z80_|alu_|db[0]~17_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_low[0]~16_combout ; -wire \z80_|alu_|db_low[0]~17_combout ; -wire \z80_|alu_|db_low[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|reg_file_|db_hi_as[0]~4_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[1]~3_combout ; +wire \z80_|address_latch_|Q[9]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; +wire \z80_|reg_file_|db_hi_as[2]~7_combout ; +wire \z80_|reg_file_|db_hi_as[2]~8_combout ; +wire \z80_|reg_file_|db_hi_as[2]~9_combout ; +wire \z80_|address_latch_|Q[10]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|db_hi_as[3]~10_combout ; +wire \z80_|reg_file_|db_hi_as[3]~11_combout ; +wire \z80_|reg_file_|db_hi_as[3]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|alu_|alu_op1[3]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~20_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~21_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_flags_sz_we~4_combout ; +wire \z80_|pla_decode_|Equal71~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; +wire \z80_|pla_decode_|Equal72~2_combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|execute_|ctl_flags_nf_we~1_combout ; +wire \z80_|execute_|ctl_flags_nf_we~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; +wire \z80_|execute_|ctl_flags_sz_we~5_combout ; +wire \z80_|execute_|ctl_flags_sz_we~6_combout ; +wire \z80_|execute_|ctl_flags_nf_we~4_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|ctl_flags_xy_we~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~7_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; +wire \z80_|execute_|ctl_flags_alu~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~19_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|alu_|alu_op2[1]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~38_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~43_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|execute_|ctl_alu_core_hf~42_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~41_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~44_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~39_combout ; +wire \z80_|execute_|ctl_alu_core_hf~40_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ; +wire \z80_|alu_|alu_op2[3]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; wire \z80_|execute_|ctl_flags_hf_we~3_combout ; wire \z80_|execute_|ctl_flags_hf_we~4_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_alu_core_hf~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|execute_|ctl_alu_core_hf~16_combout ; -wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; -wire \z80_|execute_|ctl_flags_nf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~9_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|execute_|ctl_alu_core_hf~15_combout ; -wire \z80_|execute_|ctl_alu_core_hf~17_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|execute_|ctl_alu_core_hf~39_combout ; -wire \z80_|execute_|ctl_alu_core_hf~40_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; -wire \z80_|alu_|db_high[0]~8_combout ; -wire \z80_|alu_|db_high[0]~9_combout ; -wire \z80_|alu_|db_high[0]~10_combout ; -wire \z80_|alu_|db_high[0]~11_combout ; -wire \z80_|alu_|db_high[0]~12_combout ; -wire \z80_|alu_|db_high[0]~13_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|alu_|alu_op2[0]~1_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_low[0]~18_combout ; -wire \z80_|alu_|db_low[0]~20_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|address_latch_|Q[12]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[4]~16_combout ; +wire \z80_|reg_file_|db_hi_as[4]~17_combout ; +wire \z80_|reg_file_|db_hi_as[4]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; +wire \z80_|alu_|db[4]~16_combout ; +wire \z80_|alu_|db[7]~26_combout ; +wire \z80_|alu_|db[4]~17_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|db_high[0]~26_combout ; wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|alu_op1[0]~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|alu_|alu_op1[0]~1_combout ; wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|alu_op1[1]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|alu_|alu_op1[2]~2_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|alu_|db_low[2]~7_combout ; -wire \z80_|alu_|db_low[2]~8_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~63_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~61_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~64_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~58_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~65_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~66_combout ; -wire \z80_|alu_|db[2]~11_combout ; -wire \z80_|alu_|db[2]~12_combout ; -wire \z80_|alu_|db_low[2]~5_combout ; -wire \z80_|alu_|db_low[2]~6_combout ; -wire \z80_|alu_|db_low[2]~9_combout ; -wire \z80_|alu_|db_low[2]~22_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|alu_control_|db[2]~19_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; +wire \z80_|reg_file_|db_hi_as[7]~19_combout ; +wire \z80_|reg_file_|db_hi_as[7]~20_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; +wire \z80_|reg_file_|db_hi_as[5]~13_combout ; +wire \z80_|reg_file_|db_hi_as[5]~14_combout ; +wire \z80_|reg_file_|db_hi_as[5]~15_combout ; +wire \z80_|address_latch_|Q[13]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; +wire \z80_|reg_file_|db_hi_as[6]~22_combout ; +wire \z80_|reg_file_|db_hi_as[6]~23_combout ; +wire \z80_|reg_file_|db_hi_as[6]~24_combout ; +wire \z80_|address_latch_|Q[14]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|reg_file_|db_hi_as[7]~21_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; +wire \z80_|alu_|db[7]~20_combout ; +wire \z80_|alu_|db[7]~21_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~4_combout ; +wire \z80_|alu_|db_high[3]~27_combout ; +wire \z80_|alu_|db_high[3]~7_combout ; +wire \z80_|alu_|db_high[3]~8_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ; +wire \z80_|alu_|db_low[3]~9_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|alu_|db_low[3]~10_combout ; +wire \z80_|alu_|db_low[3]~7_combout ; +wire \z80_|alu_|db_low[3]~8_combout ; +wire \z80_|alu_|db_low[3]~11_combout ; +wire \z80_|alu_|db_low[3]~25_combout ; +wire \z80_|alu_|db[3]~10_combout ; +wire \z80_|alu_|db[3]~11_combout ; wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|alu_control_|db[1]~23_combout ; -wire \z80_|alu_control_|db[1]~24_combout ; -wire \z80_|alu_control_|db[1]~25_combout ; -wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|Q[1]~feeder_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; -wire \z80_|alu_control_|db[4]~30_combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \z80_|alu_|db[4]~8_combout ; -wire \z80_|alu_|db[4]~10_combout ; -wire \z80_|alu_|db_high[1]~4_combout ; -wire \z80_|alu_|db_high[1]~5_combout ; -wire \z80_|alu_|db_high[1]~6_combout ; -wire \z80_|alu_|db_high[1]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|alu_op2[1]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; -wire \z80_|alu_|db_low[1]~11_combout ; -wire \z80_|alu_|db_low[1]~12_combout ; -wire \z80_|alu_|db_low[1]~13_combout ; -wire \z80_|alu_|db_low[1]~14_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_control_|db[6]~13_combout ; -wire \z80_|alu_control_|db[6]~14_combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; +wire \z80_|execute_|ctl_flags_xy_we~13_combout ; +wire \z80_|execute_|ctl_flags_xy_we~14_combout ; +wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|alu_flags_|flags_xf~q ; +wire \z80_|alu_control_|db[3]~33_combout ; wire \z80_|execute_|ctl_reg_out_lo~3_combout ; wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; wire \z80_|execute_|ctl_reg_out_lo~4_combout ; wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; -wire \z80_|alu_control_|db[6]~15_combout ; -wire \z80_|alu_|db[6]~21_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db_high[2]~20_combout ; -wire \z80_|alu_|db_high[2]~21_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout ; -wire \z80_|alu_|db_high[2]~22_combout ; -wire \z80_|alu_|db_high[2]~23_combout ; -wire \z80_|alu_|db_high[2]~24_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|alu_op2[2]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~37_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~11_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|alu_control_|db[0]~8_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~9_combout ; -wire \z80_|alu_control_|db[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|sw1_|db_down[3]~1_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; -wire \z80_|sw1_|db_down[3]~2_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|alu_|db[3]~14_combout ; -wire \z80_|alu_|db_low[3]~0_combout ; -wire \z80_|alu_|db_low[3]~1_combout ; -wire \z80_|alu_|db_low[3]~23_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout ; -wire \z80_|alu_|alu_op2[3]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ; -wire \z80_|alu_|db_high[3]~14_combout ; -wire \z80_|alu_|db_high[3]~15_combout ; -wire \z80_|alu_|db_high[3]~16_combout ; -wire \z80_|alu_|db_high[3]~17_combout ; -wire \z80_|alu_|db_high[3]~18_combout ; -wire \z80_|alu_|db_high[3]~19_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_control_|db[7]~16_combout ; -wire \z80_|reg_file_|db_lo_ds[7]~1_combout ; +wire \z80_|reg_file_|db_lo_as[3]~10_combout ; +wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|reg_file_|db_lo_as[3]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; +wire \z80_|reg_file_|db_lo_as[4]~13_combout ; +wire \z80_|reg_file_|db_lo_as[4]~14_combout ; +wire \z80_|reg_file_|db_lo_as[4]~15_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; +wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; +wire \z80_|reg_file_|db_lo_as[5]~16_combout ; +wire \z80_|reg_file_|db_lo_as[5]~17_combout ; +wire \z80_|reg_file_|db_lo_as[5]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|db_lo_as[6]~19_combout ; +wire \z80_|reg_file_|db_lo_as[6]~20_combout ; +wire \z80_|reg_file_|db_lo_as[6]~21_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; +wire \z80_|reg_file_|db_lo_ds[7]~0_combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; wire \z80_|alu_control_|db[7]~17_combout ; +wire \z80_|alu_control_|db[7]~16_combout ; wire \z80_|alu_control_|db[7]~18_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; -wire \z80_|alu_|alu_parity_out~0_combout ; -wire \z80_|alu_|alu_parity_out~combout ; -wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; wire \z80_|execute_|ctl_flags_pf_we~5_combout ; wire \z80_|execute_|ctl_flags_pf_we~6_combout ; wire \z80_|execute_|ctl_flags_pf_we~7_combout ; wire \z80_|execute_|ctl_flags_pf_we~8_combout ; wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~11_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; wire \z80_|decode_state_|DFFE_instNonRep~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; +wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|alu_parity_out~0_combout ; +wire \z80_|alu_|alu_parity_out~combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~14_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~13_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; +wire \z80_|alu_control_|sel[1]~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; +wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; wire \z80_|alu_control_|flags_cond_true~0_combout ; wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~32_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~33_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~36_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~34_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~35_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~37_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~38_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~39_combout ; -wire \z80_|reg_file_|db_hi_as[1]~7_combout ; -wire \z80_|reg_file_|db_hi_as[1]~8_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~9_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[2]~16_combout ; -wire \z80_|reg_file_|db_hi_as[2]~17_combout ; -wire \z80_|reg_file_|db_hi_as[2]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[5]~19_combout ; -wire \z80_|reg_file_|db_hi_as[5]~20_combout ; -wire \z80_|reg_file_|db_hi_as[5]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~4_combout ; -wire \z80_|reg_file_|db_hi_as[7]~5_combout ; -wire \z80_|reg_file_|db_hi_as[7]~6_combout ; -wire \z80_|execute_|ctl_apin_mux~2_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; -wire \z80_|execute_|ctl_apin_mux2~0_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|fIORead~3_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; -wire \z80_|address_pins_|abus[15]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; -wire \z80_|address_pins_|abus[14]~16_combout ; -wire \D[1]~27_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~19_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; -wire \z80_|address_pins_|abus[10]~22_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; -wire \z80_|address_pins_|abus[11]~21_combout ; -wire \D[1]~25_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~24_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; -wire \z80_|address_pins_|abus[13]~23_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \D[1]~26_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~20_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \ula_|zx_keyboard_|keys[1][1]~20_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~21_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \D[1]~24_combout ; -wire \D[1]~28_combout ; -wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; -wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; -wire \z80_|memory_ifc_|wait_iorqinta~q ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|ctl_iorw~8_combout ; -wire \z80_|execute_|ctl_iorw~9_combout ; -wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; -wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; -wire \z80_|memory_ifc_|wait_iorq~q ; -wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; -wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|memory_ifc_|nIORQ_out~0_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|execute_|setM1~57_combout ; -wire \z80_|execute_|setM1~39_combout ; -wire \z80_|execute_|ctl_mRead~36_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|ctl_mRead~35_combout ; -wire \z80_|execute_|ctl_mRead~40_combout ; -wire \z80_|execute_|ctl_mRead~39_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|nextM~4_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; +wire \z80_|reg_file_|db_lo_ds[1]~1_combout ; +wire \z80_|alu_control_|db[1]~25_combout ; +wire \z80_|alu_control_|db[1]~24_combout ; +wire \z80_|alu_control_|db[1]~26_combout ; +wire \z80_|alu_|db[1]~12_combout ; +wire \z80_|alu_|db[1]~13_combout ; +wire \z80_|alu_|db_low[0]~21_combout ; +wire \z80_|alu_|db_low[0]~22_combout ; +wire \z80_|alu_|db_low[0]~18_combout ; +wire \z80_|alu_|db_low[0]~19_combout ; +wire \z80_|alu_|db_low[0]~20_combout ; +wire \z80_|alu_|db_low[0]~23_combout ; +wire \z80_|alu_|db[0]~18_combout ; +wire \z80_|alu_|db[0]~19_combout ; +wire \z80_|alu_|db_low[1]~15_combout ; +wire \z80_|alu_|db_low[1]~16_combout ; +wire \z80_|alu_|db_low[1]~12_combout ; +wire \z80_|alu_|db_low[1]~13_combout ; +wire \z80_|alu_|db_low[1]~14_combout ; +wire \z80_|alu_|db_low[1]~17_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|db[2]~23_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|alu_control_|db[2]~27_combout ; +wire \z80_|alu_control_|db[2]~29_combout ; +wire \z80_|alu_|db[2]~14_combout ; +wire \z80_|alu_|db[2]~15_combout ; +wire \z80_|alu_|db_low[2]~2_combout ; +wire \z80_|alu_|db_low[2]~3_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ; +wire \z80_|alu_|db_low[2]~5_combout ; +wire \z80_|alu_|db_low[2]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ; +wire \z80_|alu_|alu_op2[2]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|alu_|db_high[2]~14_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|alu_|db[6]~23_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_control_|db[6]~19_combout ; +wire \z80_|alu_control_|db[6]~20_combout ; +wire \z80_|alu_control_|db[6]~21_combout ; +wire \z80_|alu_control_|db[6]~22_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|interrupts_|im1~q ; +wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; +wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; +wire \z80_|bus_control_|db[0]~4_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; wire \z80_|execute_|ctl_mRead~37_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|setM1~55_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|nextM~3_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|execute_|ctl_mRead~35_combout ; wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; wire \z80_|memory_ifc_|wait_mrd~q ; wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|execute_|nextM~4_combout ; +wire \z80_|execute_|ctl_iorw~12_combout ; +wire \z80_|execute_|ctl_iorw~8_combout ; +wire \z80_|execute_|ctl_iorw~9_combout ; +wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; +wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; +wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; +wire \z80_|memory_ifc_|wait_iorq~q ; +wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; +wire \z80_|memory_ifc_|iorq~0_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|fIORead~3_combout ; wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; wire \z80_|memory_ifc_|nRD_out~0_combout ; wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \Equal2~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~0_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|execute_|fMWrite~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; +wire \z80_|execute_|fMWrite~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|execute_|fMWrite~8_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; +wire \z80_|execute_|fMWrite~10_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; +wire \z80_|clk_delay_|DFF_inst5~q ; +wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; +wire \z80_|memory_ifc_|wait_iorqinta~q ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; +wire \z80_|memory_ifc_|nIORQ_out~0_combout ; wire \Equal2~0_combout ; -wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; wire \ExtRamWE~0_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \z80_|execute_|ctl_apin_mux2~0_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; +wire \z80_|address_pins_|abus[13]~20_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; +wire \z80_|address_pins_|abus[14]~23_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; +wire \z80_|address_pins_|abus[15]~22_combout ; wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \z80_|address_pins_|abus[0]~16_combout ; wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|address_pins_|abus[1]~25_combout ; wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; @@ -1916,18 +1807,29 @@ wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; wire \z80_|address_pins_|abus[6]~30_combout ; wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; wire \z80_|address_pins_|abus[7]~31_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~18_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~17_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; +wire \z80_|address_pins_|abus[10]~24_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|address_pins_|abus[11]~19_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~21_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \D[6]~90_combout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \D[6]~91_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; wire \CLOCK_50~inputclkctrl_outclk ; wire \~GND~combout ; +wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; @@ -1940,9 +1842,9 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; wire \ula_|video_|vram_address[9]~1_combout ; wire \ula_|video_|Add4~13 ; @@ -1954,505 +1856,469 @@ wire \ula_|video_|vram_address[10]~2_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \Selector1~0_combout ; -wire \Selector1~1_combout ; -wire \D[1]~22_combout ; -wire \D[1]~23_combout ; -wire \D[1]~29_combout ; -wire \D[1]~31_combout ; -wire \z80_|pin_control_|bus_db_pin_re~2_combout ; -wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[1]~12_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|bus_control_|db[0]~6_combout ; -wire \z80_|bus_control_|db[1]~13_combout ; -wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; -wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~feeder_combout ; -wire \z80_|memory_ifc_|mwr_wr~q ; -wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \D[0]~30_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \D[6]~87_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \Selector6~0_combout ; -wire \D[6]~70_combout ; -wire \D[6]~71_combout ; -wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; -wire \ula_|zx_keyboard_|keys[5][4]~64_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~135_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \D[3]~55_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~95_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~96_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~97_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~99_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~q ; -wire \D[3]~54_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~136_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~109_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~137_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~110_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \ula_|zx_keyboard_|keys[5][3]~106_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \D[3]~56_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~115_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~116_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~139_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~140_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; -wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \D[3]~57_combout ; -wire \D[3]~58_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \Selector3~0_combout ; -wire \Selector3~1_combout ; -wire \D[3]~52_combout ; -wire \D[3]~53_combout ; -wire \D[3]~76_combout ; -wire \D[3]~77_combout ; -wire \ula_|always0~0_combout ; -wire \ula_|always0~1_combout ; -wire \ula_|i2s_intf_|mclk_r~0_combout ; -wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|Add0~1_cout ; -wire \ula_|i2s_intf_|Add0~2_combout ; -wire \ula_|i2s_intf_|lrdivider~2_combout ; -wire \ula_|i2s_intf_|Add0~3 ; -wire \ula_|i2s_intf_|Add0~4_combout ; -wire \ula_|i2s_intf_|lrdivider[2]~8_combout ; -wire \ula_|i2s_intf_|Add0~5 ; -wire \ula_|i2s_intf_|Add0~6_combout ; -wire \ula_|i2s_intf_|lrdivider[3]~7_combout ; -wire \ula_|i2s_intf_|Add0~7 ; -wire \ula_|i2s_intf_|Add0~8_combout ; -wire \ula_|i2s_intf_|lrdivider~1_combout ; -wire \ula_|i2s_intf_|Add0~9 ; -wire \ula_|i2s_intf_|Add0~10_combout ; -wire \ula_|i2s_intf_|lrdivider[5]~6_combout ; -wire \ula_|i2s_intf_|Add0~11 ; -wire \ula_|i2s_intf_|Add0~12_combout ; -wire \ula_|i2s_intf_|lrdivider[6]~5_combout ; -wire \ula_|i2s_intf_|Add0~13 ; -wire \ula_|i2s_intf_|Add0~14_combout ; -wire \ula_|i2s_intf_|lrdivider[7]~4_combout ; -wire \ula_|i2s_intf_|Add0~15 ; -wire \ula_|i2s_intf_|Add0~16_combout ; -wire \ula_|i2s_intf_|lrdivider~0_combout ; -wire \ula_|i2s_intf_|Add0~17 ; -wire \ula_|i2s_intf_|Add0~18_combout ; -wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; -wire \ula_|i2s_intf_|Equal0~0_combout ; -wire \ula_|i2s_intf_|Equal0~1_combout ; -wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|bitcount[0]~5_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; -wire \ula_|i2s_intf_|bclk_r~0_combout ; -wire \ula_|i2s_intf_|Add2~7_cout ; -wire \ula_|i2s_intf_|Add2~8_combout ; -wire \ula_|i2s_intf_|Add2~20_combout ; -wire \ula_|i2s_intf_|Add2~9 ; -wire \ula_|i2s_intf_|Add2~10_combout ; -wire \ula_|i2s_intf_|Add2~17_combout ; -wire \ula_|i2s_intf_|Add2~11 ; -wire \ula_|i2s_intf_|Add2~12_combout ; -wire \ula_|i2s_intf_|Add2~19_combout ; -wire \ula_|i2s_intf_|Add2~13 ; -wire \ula_|i2s_intf_|Add2~14_combout ; -wire \ula_|i2s_intf_|Add2~16_combout ; -wire \ula_|i2s_intf_|Equal1~0_combout ; -wire \ula_|i2s_intf_|shiftreg[8]~1_combout ; -wire \ula_|i2s_intf_|Add2~18_combout ; -wire \ula_|i2s_intf_|Equal1~1_combout ; -wire \ula_|i2s_intf_|bclk_r~1_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|bitcount[4]~15_combout ; -wire \ula_|i2s_intf_|bitcount[0]~6 ; -wire \ula_|i2s_intf_|bitcount[1]~7_combout ; -wire \ula_|i2s_intf_|bitcount[1]~8 ; -wire \ula_|i2s_intf_|bitcount[2]~9_combout ; -wire \ula_|i2s_intf_|bitcount[2]~10 ; -wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|bitcount[3]~12 ; -wire \ula_|i2s_intf_|bitcount[4]~13_combout ; -wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; -wire \AUD_ADCDAT~input_o ; -wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; -wire \ula_|i2s_intf_|shiftreg~18_combout ; -wire \ula_|i2s_intf_|shiftreg[8]~2_combout ; -wire \ula_|i2s_intf_|shiftreg~17_combout ; -wire \ula_|i2s_intf_|shiftreg~16_combout ; -wire \ula_|i2s_intf_|shiftreg~15_combout ; -wire \ula_|i2s_intf_|shiftreg~14_combout ; -wire \ula_|i2s_intf_|shiftreg~13_combout ; -wire \ula_|i2s_intf_|shiftreg~12_combout ; -wire \ula_|i2s_intf_|shiftreg~11_combout ; -wire \ula_|i2s_intf_|shiftreg~10_combout ; -wire \ula_|i2s_intf_|shiftreg~9_combout ; -wire \ula_|i2s_intf_|shiftreg~8_combout ; -wire \ula_|i2s_intf_|shiftreg~7_combout ; -wire \ula_|i2s_intf_|lrclk_r~0_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; -wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; -wire \ula_|ula_data~0_combout ; -wire \ula_|i2s_intf_|shiftreg~6_combout ; -wire \ula_|i2s_intf_|shiftreg~5_combout ; -wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; -wire \D[6]~72_combout ; -wire \D[6]~73_combout ; -wire \D[6]~74_combout ; -wire \D[6]~81_combout ; -wire \z80_|bus_control_|db[6]~5_combout ; -wire \z80_|bus_control_|db[6]~7_combout ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|alu_control_|db[6]~10_combout ; -wire \z80_|alu_control_|db[6]~11_combout ; -wire \z80_|alu_control_|db[2]~20_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; -wire \z80_|alu_control_|db[2]~21_combout ; -wire \z80_|alu_control_|db[2]~22_combout ; -wire \z80_|bus_control_|db[2]~10_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~59_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~133_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~132_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~34_combout ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~55_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \D[2]~33_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~48_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \D[2]~32_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~63_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~67_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \ula_|zx_keyboard_|keys[5][0]~68_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~71_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; -wire \D[2]~35_combout ; -wire \D[2]~36_combout ; -wire \D[2]~83_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \Selector0~0_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \Selector0~1_combout ; -wire \D[2]~37_combout ; -wire \D[2]~38_combout ; -wire \D[2]~39_combout ; -wire \D[2]~40_combout ; -wire \z80_|bus_control_|db[2]~11_combout ; -wire \z80_|pla_decode_|Equal3~1_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|execute_|ctl_bus_db_oe~4_combout ; -wire \z80_|execute_|ctl_bus_db_oe~5_combout ; -wire \z80_|execute_|ctl_bus_db_oe~combout ; -wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \D[0]~45_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \D[0]~44_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~134_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~93_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \D[0]~46_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~77_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~74_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~75_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~76_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~73_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \D[0]~43_combout ; -wire \D[0]~47_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \Selector2~0_combout ; -wire \Selector2~1_combout ; -wire \D[0]~41_combout ; -wire \D[0]~42_combout ; -wire \D[0]~48_combout ; -wire \D[0]~49_combout ; -wire \z80_|bus_control_|db[0]~14_combout ; -wire \z80_|bus_control_|db[0]~15_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|sw1_|db_down[5]~1_combout ; +wire \D[6]~88_combout ; +wire \D[6]~89_combout ; +wire \D[6]~111_combout ; +wire \raw_loader_in~input_o ; +wire \D[6]~86_combout ; +wire \D[6]~100_combout ; +wire \D[6]~101_combout ; +wire \z80_|pin_control_|bus_db_pin_re~2_combout ; +wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; +wire \z80_|bus_control_|db[6]~9_combout ; +wire \z80_|ir_|opcode[6]~feeder_combout ; +wire \z80_|execute_|ctl_ir_we~13_combout ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal41~1_combout ; +wire \z80_|pla_decode_|Equal41~2_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|db_high[1]~20_combout ; +wire \z80_|alu_|db[5]~24_combout ; +wire \z80_|alu_|db[5]~25_combout ; +wire \z80_|sw1_|db_down[5]~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; wire \z80_|alu_flags_|flags_yf~q ; -wire \z80_|alu_control_|db[5]~27_combout ; -wire \z80_|alu_control_|db[5]~28_combout ; -wire \z80_|alu_control_|db[5]~29_combout ; -wire \D[5]~68_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \z80_|alu_control_|db[5]~13_combout ; +wire \z80_|alu_control_|db[5]~14_combout ; +wire \z80_|alu_control_|db[5]~15_combout ; +wire \D[0]~107_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \Mux2~0_combout ; wire \Mux2~1_combout ; -wire \D[5]~88_combout ; -wire \D[5]~69_combout ; -wire \D[5]~80_combout ; -wire \z80_|bus_control_|db[5]~16_combout ; -wire \z80_|bus_control_|db[5]~17_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; -wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|fMRead~28_combout ; -wire \z80_|execute_|fMRead~30_combout ; +wire \D[5]~110_combout ; +wire \D[5]~85_combout ; +wire \D[5]~99_combout ; +wire \z80_|bus_control_|db[5]~14_combout ; +wire \z80_|bus_control_|db[5]~15_combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|fMRead~34_combout ; wire \z80_|execute_|fMRead~31_combout ; wire \z80_|execute_|fMRead~29_combout ; +wire \z80_|execute_|fMRead~30_combout ; +wire \z80_|execute_|fMRead~28_combout ; wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~37_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~35_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; +wire \z80_|execute_|fMRead~14_combout ; wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~11_combout ; +wire \z80_|execute_|fMRead~12_combout ; +wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|fMRead~15_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|pc_inc_hold~48_combout ; wire \z80_|execute_|fMRead~22_combout ; +wire \z80_|execute_|fMRead~21_combout ; wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|pc_inc_hold~39_combout ; wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|fMRead~36_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|fMRead~35_combout ; wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \Mux0~0_combout ; -wire \Mux0~1_combout ; -wire \D[7]~89_combout ; -wire \D[7]~75_combout ; -wire \D[7]~82_combout ; -wire \z80_|bus_control_|db[7]~8_combout ; -wire \z80_|bus_control_|db[7]~9_combout ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; -wire \z80_|interrupts_|im1~q ; -wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; -wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|pla_decode_|Equal21~0_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; -wire \z80_|execute_|ctl_bus_db_we~4_combout ; -wire \z80_|execute_|ctl_bus_db_we~6_combout ; -wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; -wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[4][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~128_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \D[4]~64_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~138_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \Selector1~0_combout ; +wire \Selector1~1_combout ; +wire \D[1]~103_combout ; +wire \PS2_DAT~input_o ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; +wire \ula_|zx_keyboard_|shifted~0_combout ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~23_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \D[1]~30_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \ula_|zx_keyboard_|key_row~0_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~19_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~21_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \D[1]~28_combout ; +wire \D[1]~29_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; +wire \ula_|zx_keyboard_|WideOr16~5_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|WideOr16~7_combout ; +wire \ula_|zx_keyboard_|WideOr16~6_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; +wire \D[1]~31_combout ; +wire \D[1]~32_combout ; +wire \D[1]~33_combout ; +wire \D[1]~34_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; +wire \z80_|bus_control_|db[1]~11_combout ; +wire \z80_|ir_|opcode[1]~feeder_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|execute_|ctl_flags_cf_set~0_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|alu_control_|db[0]~8_combout ; +wire \z80_|sw2_|db_up[0]~0_combout ; +wire \z80_|alu_control_|db[0]~9_combout ; +wire \z80_|alu_control_|db[0]~12_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~67_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \D[0]~49_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys~76_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~73_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~74_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; +wire \ula_|zx_keyboard_|keys[1][0]~71_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \D[0]~47_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \ula_|zx_keyboard_|keys[3][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \ula_|zx_keyboard_|key_row~1_combout ; +wire \D[0]~48_combout ; +wire \ula_|zx_keyboard_|shifted~1_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|keys[5][4]~63_combout ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~132_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \D[0]~50_combout ; +wire \D[0]~51_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~55_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \D[0]~56_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \D[0]~52_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~53_combout ; +wire \D[0]~54_combout ; +wire \D[0]~106_combout ; +wire \D[0]~57_combout ; +wire \D[0]~58_combout ; +wire \z80_|bus_control_|db[0]~16_combout ; +wire \z80_|bus_control_|db[0]~17_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|alu_control_|db[6]~10_combout ; +wire \z80_|alu_control_|db[6]~11_combout ; +wire \z80_|alu_control_|db[4]~30_combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \z80_|alu_control_|db[4]~32_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~95_combout ; wire \ula_|zx_keyboard_|keys[2][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~123_combout ; wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \D[4]~63_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~129_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \ula_|zx_keyboard_|keys[6][4]~130_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~131_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~136_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~130_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \D[4]~78_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~128_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~129_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \ula_|zx_keyboard_|keys[6][4]~127_combout ; wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \D[4]~65_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~118_combout ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \D[4]~79_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \ula_|zx_keyboard_|key_row~3_combout ; +wire \D[4]~80_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~97_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~116_combout ; wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~115_combout ; wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~62_combout ; -wire \D[4]~66_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \D[4]~77_combout ; +wire \D[4]~81_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; wire \Selector4~0_combout ; wire \Selector4~1_combout ; -wire \D[4]~60_combout ; -wire \D[4]~61_combout ; -wire \D[4]~78_combout ; -wire \D[4]~79_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ; +wire \D[4]~109_combout ; +wire \D[4]~97_combout ; +wire \D[4]~98_combout ; wire \z80_|bus_control_|db[4]~18_combout ; wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|pla_decode_|Equal21~0_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_mWrite~13_combout ; +wire \z80_|execute_|ctl_mWrite~14_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; +wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; +wire \z80_|memory_ifc_|wait_mwr~q ; +wire \z80_|memory_ifc_|mwr_wr~q ; +wire \z80_|memory_ifc_|nWR_out~0_combout ; +wire \D[5]~84_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Mux0~0_combout ; +wire \Mux0~1_combout ; +wire \D[7]~112_combout ; +wire \D[7]~94_combout ; +wire \D[7]~102_combout ; +wire \z80_|bus_control_|db[7]~5_combout ; +wire \z80_|bus_control_|db[7]~7_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|execute_|ctl_mWrite~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_bus_db_we~8_combout ; +wire \z80_|execute_|ctl_bus_db_we~2_combout ; +wire \z80_|execute_|ctl_bus_db_we~4_combout ; +wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_bus_db_we~7_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \ula_|zx_keyboard_|keys[3][3]~48_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \D[2]~35_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~131_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \D[2]~37_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \D[2]~36_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \D[2]~38_combout ; +wire \D[2]~39_combout ; +wire \D[2]~104_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \D[2]~43_combout ; +wire \D[2]~44_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \D[2]~40_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \D[2]~41_combout ; +wire \D[2]~42_combout ; +wire \D[2]~105_combout ; +wire \D[2]~45_combout ; +wire \D[2]~46_combout ; +wire \z80_|bus_control_|db[2]~12_combout ; +wire \z80_|bus_control_|db[2]~13_combout ; +wire \z80_|pla_decode_|Equal3~1_combout ; wire \z80_|pla_decode_|Equal43~0_combout ; wire \z80_|interrupts_|test1~2_combout ; wire \z80_|interrupts_|test1~3_combout ; @@ -2463,83 +2329,151 @@ wire \z80_|clk_delay_|hold_clk_iorq~combout ; wire \z80_|sequencer_|DFFE_T1_ff~q ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; -wire \z80_|sequencer_|DFFE_T3_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|setM1~53_combout ; -wire \z80_|execute_|nextM~3_combout ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; +wire \z80_|execute_|ctl_mWrite~3_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|execute_|nextM~8_combout ; wire \z80_|execute_|nextM~9_combout ; wire \z80_|execute_|nextM~10_combout ; wire \z80_|execute_|nextM~12_combout ; wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~5_combout ; +wire \z80_|execute_|nextM~6_combout ; wire \z80_|execute_|nextM~7_combout ; -wire \z80_|execute_|nextM~8_combout ; wire \z80_|execute_|nextM~13_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|nextM~5_combout ; wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; wire \z80_|sequencer_|T6~q ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~41_combout ; wire \z80_|execute_|setM1~42_combout ; wire \z80_|execute_|setM1~43_combout ; wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~16_combout ; wire \z80_|execute_|setM1~50_combout ; wire \z80_|execute_|setM1~51_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~6_combout ; +wire \z80_|execute_|setM1~7_combout ; wire \z80_|execute_|setM1~8_combout ; wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~53_combout ; +wire \z80_|execute_|setM1~23_combout ; wire \z80_|execute_|setM1~18_combout ; wire \z80_|execute_|setM1~19_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~54_combout ; wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~34_combout ; wire \z80_|execute_|setM1~52_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_inc_cy~39_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~37_combout ; -wire \z80_|execute_|pc_inc_hold~38_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; +wire \z80_|sequencer_|DFFE_T3_ff~q ; +wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|execute_|ctl_bus_db_oe~2_combout ; +wire \z80_|execute_|ctl_bus_db_oe~5_combout ; +wire \z80_|execute_|ctl_bus_db_oe~6_combout ; +wire \z80_|execute_|ctl_bus_db_oe~4_combout ; +wire \z80_|execute_|ctl_bus_db_oe~combout ; +wire \z80_|bus_control_|db[0]~6_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~q ; +wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~q ; +wire \D[3]~65_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~133_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \D[3]~66_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~134_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~135_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \D[3]~67_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~q ; +wire \ula_|zx_keyboard_|keys[6][3]~109_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~110_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~137_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~138_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \ula_|zx_keyboard_|key_row~2_combout ; +wire \D[3]~68_combout ; +wire \D[3]~69_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \D[3]~73_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \D[3]~74_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \D[3]~70_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~71_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~72_combout ; +wire \D[3]~108_combout ; +wire \D[3]~95_combout ; +wire \D[3]~96_combout ; +wire \z80_|bus_control_|db[3]~20_combout ; +wire \z80_|bus_control_|db[3]~21_combout ; +wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \z80_|execute_|ctl_apin_mux~2_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~84_combout ; -wire \D[0]~50_combout ; -wire \D[1]~85_combout ; -wire \D[1]~51_combout ; -wire \D[3]~86_combout ; -wire \D[3]~59_combout ; -wire \D[4]~87_combout ; -wire \D[4]~67_combout ; +wire \D[0]~59_combout ; +wire \D[0]~60_combout ; +wire \D[1]~61_combout ; +wire \D[1]~62_combout ; +wire \D[2]~63_combout ; +wire \D[2]~64_combout ; +wire \D[3]~75_combout ; +wire \D[3]~76_combout ; +wire \D[4]~82_combout ; +wire \D[4]~83_combout ; +wire \D[6]~92_combout ; +wire \D[6]~93_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2547,6 +2481,7 @@ wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ; wire \z80_|memory_ifc_|DFFE_mreq_ff2~q ; wire \z80_|memory_ifc_|nMREQ_out~0_combout ; wire \z80_|memory_ifc_|nMREQ_out~1_combout ; +wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|divider[0]~15_combout ; wire \ula_|i2c_loader_|divider[1]~5_combout ; @@ -2563,35 +2498,24 @@ wire \ula_|i2c_loader_|WideAnd0~combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; +wire \ula_|i2c_loader_|nbit~5_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|Mux42~0_combout ; -wire \ula_|i2c_loader_|nbit~6_combout ; -wire \ula_|i2c_loader_|nbyte~0_combout ; +wire \ula_|i2c_loader_|nbyte~4_combout ; wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; wire \I2C_SDAT~input_o ; wire \ula_|i2c_loader_|nbyte[0]~1_combout ; wire \ula_|i2c_loader_|nbyte[0]~2_combout ; wire \ula_|i2c_loader_|nbyte[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~4_combout ; +wire \ula_|i2c_loader_|state.Stop~0_combout ; +wire \ula_|i2c_loader_|state.Stop~1_combout ; +wire \ula_|i2c_loader_|state.Stop~q ; +wire \ula_|i2c_loader_|state.Idle~0_combout ; +wire \ula_|i2c_loader_|nbit~0_combout ; wire \ula_|i2c_loader_|state.Done~0_combout ; wire \ula_|i2c_loader_|state.Ack~0_combout ; wire \ula_|i2c_loader_|state.Ack~1_combout ; -wire \ula_|i2c_loader_|state.Ack~2_combout ; wire \ula_|i2c_loader_|state.Ack~q ; -wire \ula_|i2c_loader_|state~24_combout ; -wire \ula_|i2c_loader_|state~26_combout ; -wire \ula_|i2c_loader_|state~27_combout ; -wire \ula_|i2c_loader_|state.Data~0_combout ; -wire \ula_|i2c_loader_|state.Data~q ; -wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|nbit~0_combout ; -wire \ula_|i2c_loader_|state.Done~1_combout ; -wire \ula_|i2c_loader_|state.Done~2_combout ; -wire \ula_|i2c_loader_|state.Pause~2_combout ; -wire \ula_|i2c_loader_|state.Pause~0_combout ; -wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|nbyte[1]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; @@ -2601,29 +2525,43 @@ wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; wire \ula_|i2c_loader_|Equal2~0_combout ; +wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|state.Done~2_combout ; +wire \ula_|i2c_loader_|state.Pause~2_combout ; wire \ula_|i2c_loader_|state.Pause~3_combout ; wire \ula_|i2c_loader_|state.Pause~q ; wire \ula_|i2c_loader_|state~25_combout ; wire \ula_|i2c_loader_|state.Start~q ; -wire \ula_|i2c_loader_|nbyte~4_combout ; -wire \ula_|i2c_loader_|state.Stop~0_combout ; -wire \ula_|i2c_loader_|state.Stop~1_combout ; -wire \ula_|i2c_loader_|state.Stop~q ; +wire \ula_|i2c_loader_|nbyte~0_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit[0]~4_combout ; +wire \ula_|i2c_loader_|nbit~6_combout ; +wire \ula_|i2c_loader_|state.Done~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; +wire \ula_|i2c_loader_|state~24_combout ; +wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|state.Data~0_combout ; +wire \ula_|i2c_loader_|state.Data~q ; wire \ula_|i2c_loader_|scl_out~0_combout ; wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|scl_out~1_combout ; wire \ula_|i2c_loader_|scl_out~2_combout ; wire \ula_|i2c_loader_|scl_out~q ; wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; +wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|Mux35~0_combout ; +wire \ula_|i2c_loader_|shiftreg~13_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~15_combout ; wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|shiftreg~21_combout ; wire \ula_|i2c_loader_|shiftreg~22_combout ; wire \ula_|i2c_loader_|shiftreg~23_combout ; @@ -2632,12 +2570,9 @@ wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; wire \ula_|i2c_loader_|shiftreg~18_combout ; wire \ula_|i2c_loader_|shiftreg~19_combout ; wire \ula_|i2c_loader_|shiftreg~20_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; wire \ula_|i2c_loader_|shiftreg~16_combout ; wire \ula_|i2c_loader_|shiftreg~17_combout ; wire \ula_|i2c_loader_|shiftreg~26_combout ; -wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~15_combout ; wire \ula_|i2c_loader_|shiftreg~25_combout ; wire \ula_|i2c_loader_|shiftreg~12_combout ; wire \ula_|i2c_loader_|shiftreg~9_combout ; @@ -2648,31 +2583,120 @@ wire \ula_|i2c_loader_|sda_out~2_combout ; wire \ula_|i2c_loader_|sda_out~3_combout ; wire \ula_|i2c_loader_|sda_out~4_combout ; wire \ula_|i2c_loader_|sda_out~q ; +wire \ula_|i2s_intf_|mclk_r~0_combout ; +wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|mclk_r~q ; +wire \ula_|i2s_intf_|Add0~1_cout ; +wire \ula_|i2s_intf_|Add0~2_combout ; +wire \ula_|i2s_intf_|lrdivider~2_combout ; +wire \ula_|i2s_intf_|Add0~3 ; +wire \ula_|i2s_intf_|Add0~4_combout ; +wire \ula_|i2s_intf_|lrdivider[2]~8_combout ; +wire \ula_|i2s_intf_|Add0~5 ; +wire \ula_|i2s_intf_|Add0~6_combout ; +wire \ula_|i2s_intf_|lrdivider[3]~7_combout ; +wire \ula_|i2s_intf_|Add0~7 ; +wire \ula_|i2s_intf_|Add0~8_combout ; +wire \ula_|i2s_intf_|lrdivider~1_combout ; +wire \ula_|i2s_intf_|Add0~9 ; +wire \ula_|i2s_intf_|Add0~10_combout ; +wire \ula_|i2s_intf_|lrdivider[5]~6_combout ; +wire \ula_|i2s_intf_|Equal0~1_combout ; +wire \ula_|i2s_intf_|Add0~11 ; +wire \ula_|i2s_intf_|Add0~12_combout ; +wire \ula_|i2s_intf_|lrdivider[6]~5_combout ; +wire \ula_|i2s_intf_|Add0~13 ; +wire \ula_|i2s_intf_|Add0~14_combout ; +wire \ula_|i2s_intf_|lrdivider[7]~4_combout ; +wire \ula_|i2s_intf_|Add0~15 ; +wire \ula_|i2s_intf_|Add0~16_combout ; +wire \ula_|i2s_intf_|lrdivider~0_combout ; +wire \ula_|i2s_intf_|Add0~17 ; +wire \ula_|i2s_intf_|Add0~18_combout ; +wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; +wire \ula_|i2s_intf_|Equal0~0_combout ; +wire \ula_|i2s_intf_|Equal0~2_combout ; +wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; +wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; +wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|bitcount[0]~5_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|bitcount[4]~15_combout ; +wire \ula_|i2s_intf_|bitcount[0]~6 ; +wire \ula_|i2s_intf_|bitcount[1]~7_combout ; +wire \ula_|i2s_intf_|bitcount[1]~8 ; +wire \ula_|i2s_intf_|bitcount[2]~9_combout ; +wire \ula_|i2s_intf_|bitcount[2]~10 ; +wire \ula_|i2s_intf_|bitcount[3]~11_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|bitcount[3]~12 ; +wire \ula_|i2s_intf_|bitcount[4]~13_combout ; +wire \ula_|i2s_intf_|Add2~7_cout ; +wire \ula_|i2s_intf_|Add2~8_combout ; +wire \ula_|i2s_intf_|Add2~20_combout ; +wire \ula_|i2s_intf_|Add2~9 ; +wire \ula_|i2s_intf_|Add2~10_combout ; +wire \ula_|i2s_intf_|Add2~17_combout ; +wire \ula_|i2s_intf_|Add2~11 ; +wire \ula_|i2s_intf_|Add2~12_combout ; +wire \ula_|i2s_intf_|Add2~19_combout ; +wire \ula_|i2s_intf_|Add2~13 ; +wire \ula_|i2s_intf_|Add2~14_combout ; +wire \ula_|i2s_intf_|Add2~16_combout ; +wire \ula_|i2s_intf_|Equal1~0_combout ; +wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; +wire \ula_|i2s_intf_|Add2~18_combout ; +wire \ula_|i2s_intf_|Equal1~1_combout ; +wire \ula_|i2s_intf_|bclk_r~0_combout ; +wire \ula_|i2s_intf_|bclk_r~1_combout ; wire \ula_|i2s_intf_|bclk_r~q ; +wire \ula_|pcm_outl[13]~feeder_combout ; +wire \ula_|always0~2_combout ; +wire \ula_|always0~3_combout ; +wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; +wire \AUD_ADCDAT~input_o ; +wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; +wire \ula_|i2s_intf_|shiftreg~18_combout ; +wire \ula_|i2s_intf_|shiftreg[4]~2_combout ; +wire \ula_|i2s_intf_|shiftreg~17_combout ; +wire \ula_|i2s_intf_|shiftreg~16_combout ; +wire \ula_|i2s_intf_|shiftreg~15_combout ; +wire \ula_|i2s_intf_|shiftreg~14_combout ; +wire \ula_|i2s_intf_|shiftreg~13_combout ; +wire \ula_|i2s_intf_|shiftreg~12_combout ; +wire \ula_|i2s_intf_|shiftreg~11_combout ; +wire \ula_|i2s_intf_|shiftreg~10_combout ; +wire \ula_|i2s_intf_|shiftreg~9_combout ; +wire \ula_|i2s_intf_|shiftreg~8_combout ; +wire \ula_|i2s_intf_|shiftreg~7_combout ; +wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; +wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; +wire \ula_|pcm_outr~0_combout ; +wire \ula_|i2s_intf_|shiftreg~6_combout ; +wire \ula_|i2s_intf_|shiftreg~5_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|border[1]~feeder_combout ; +wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|video_|LessThan6~0_combout ; +wire \ula_|video_|LessThan2~1_combout ; +wire \ula_|video_|LessThan3~0_combout ; +wire \ula_|video_|LessThan0~0_combout ; +wire \ula_|video_|disp_enable~0_combout ; +wire \ula_|video_|disp_enable~1_combout ; +wire \ula_|video_|LessThan6~1_combout ; +wire \ula_|video_|LessThan4~0_combout ; +wire \ula_|video_|screen_en~0_combout ; +wire \ula_|video_|screen_en~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|Decoder0~1_combout ; -wire \ula_|video_|attr[1]~feeder_combout ; wire \ula_|video_|Decoder0~0_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[4]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[6]~feeder_combout ; -wire \ula_|video_|Decoder0~2_combout ; -wire \ula_|video_|bits_prefetch[4]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[5]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[7]~feeder_combout ; -wire \ula_|video_|Mux0~0_combout ; -wire \ula_|video_|Mux0~1_combout ; wire \ula_|video_|attr_prefetch[7]~feeder_combout ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; @@ -2683,8 +2707,20 @@ wire \ula_|video_|frame[3]~8_combout ; wire \ula_|video_|frame[3]~9 ; wire \ula_|video_|frame[4]~10_combout ; wire \ula_|video_|inverted~combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[6]~feeder_combout ; +wire \ula_|video_|Decoder0~2_combout ; +wire \ula_|video_|bits[6]~feeder_combout ; +wire \ula_|video_|bits_prefetch[4]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[5]~feeder_combout ; +wire \ula_|video_|bits[5]~feeder_combout ; +wire \ula_|video_|bits_prefetch[7]~feeder_combout ; +wire \ula_|video_|Mux0~0_combout ; +wire \ula_|video_|Mux0~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[2]~feeder_combout ; +wire \ula_|video_|bits[2]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[0]~feeder_combout ; wire \ula_|video_|bits_prefetch[1]~feeder_combout ; @@ -2695,17 +2731,6 @@ wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; wire \ula_|video_|cindex[1]~0_combout ; wire \ula_|video_|cindex[1]~1_combout ; -wire \ula_|video_|LessThan6~0_combout ; -wire \ula_|video_|LessThan6~1_combout ; -wire \ula_|video_|LessThan4~0_combout ; -wire \ula_|video_|screen_en~0_combout ; -wire \ula_|video_|screen_en~1_combout ; -wire \ula_|video_|LessThan2~0_combout ; -wire \ula_|video_|LessThan2~1_combout ; -wire \ula_|video_|LessThan3~0_combout ; -wire \ula_|video_|LessThan0~0_combout ; -wire \ula_|video_|disp_enable~0_combout ; -wire \ula_|video_|disp_enable~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; @@ -2715,8 +2740,9 @@ wire \ula_|video_|attr_prefetch[5]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; -wire \ula_|border[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[0]~feeder_combout ; +wire \ula_|video_|attr[0]~feeder_combout ; +wire \ula_|video_|attr_prefetch[3]~feeder_combout ; wire \ula_|video_|cindex[0]~3_combout ; wire \ula_|video_|VGA_B[0]~1_combout ; wire \ula_|video_|VGA_B[1]~2_combout ; @@ -2751,13 +2777,11 @@ wire [4:0] \ula_|video_|frame ; wire [7:0] \ula_|video_|bits_prefetch ; wire [7:0] \ula_|video_|attr_prefetch ; wire [7:0] \ula_|ps2_keyboard_|clk_filter ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; @@ -2768,9 +2792,10 @@ wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; wire [3:0] \z80_|alu_|op2_low ; wire [3:0] \z80_|alu_|op1_low ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; -wire [15:0] \z80_|address_latch_|abusz ; -wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [15:0] \z80_|address_latch_|Q ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; +wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [7:0] \z80_|data_pins_|dout ; wire [7:0] \z80_|ir_|opcode ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; @@ -2790,11 +2815,13 @@ wire [7:0] \ula_|video_|bits ; wire [7:0] \ula_|video_|attr ; wire [8:0] \ula_|ps2_keyboard_|shiftreg ; wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; @@ -2806,10 +2833,9 @@ wire [3:0] \z80_|alu_|result_lo ; wire [3:0] \z80_|alu_|op2_high ; wire [3:0] \z80_|alu_|op1_high ; wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; -wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; -wire [7:0] \z80_|data_pins_|dout ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; +wire [15:0] \z80_|address_latch_|abusz ; +wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; @@ -2821,33 +2847,33 @@ wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_b wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; @@ -2866,15 +2892,15 @@ wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_b wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; @@ -2909,60 +2935,60 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; @@ -2999,24 +3025,24 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; @@ -3245,8 +3271,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~50_combout ), - .oe(\D[0]~30_combout ), + .i(\D[0]~60_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3258,8 +3284,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~51_combout ), - .oe(\D[0]~30_combout ), + .i(\D[1]~62_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3271,8 +3297,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~39_combout ), - .oe(\D[0]~30_combout ), + .i(\D[2]~64_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3284,8 +3310,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~59_combout ), - .oe(\D[0]~30_combout ), + .i(\D[3]~76_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3297,8 +3323,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~67_combout ), - .oe(\D[0]~30_combout ), + .i(\D[4]~83_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3310,8 +3336,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~69_combout ), - .oe(\D[0]~30_combout ), + .i(\D[5]~85_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3323,8 +3349,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~74_combout ), - .oe(\D[0]~30_combout ), + .i(\D[6]~93_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3336,8 +3362,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~75_combout ), - .oe(\D[0]~30_combout ), + .i(\D[7]~94_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -3440,7 +3466,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(gnd), + .i(\raw_loader_in~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -4080,7 +4106,7 @@ defparam \ula_|clocks_|clk_cpu .is_wysiwyg = "true"; defparam \ula_|clocks_|clk_cpu .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G10 +// Location: CLKCTRL_G14 cycloneive_clkctrl \ula_|clocks_|clk_cpu~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\ula_|clocks_|clk_cpu~q }), @@ -4093,7 +4119,24 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N0 +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N12 cycloneive_lcell_comb \z80_|sequencer_|ena_M ( // Equation(s): // \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout ) @@ -4110,6 +4153,11802 @@ defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; // synopsys translate_on +// Location: IOIBUF_X0_Y16_N8 +cycloneive_io_ibuf \KEY[1]~input ( + .i(KEY[1]), + .ibar(gnd), + .o(\KEY[1]~input_o )); +// synopsys translate_off +defparam \KEY[1]~input .bus_hold = "false"; +defparam \KEY[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( +// Equation(s): +// \z80_|interrupts_|nmi_armed~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; +defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N2 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hAAFF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y15_N7 +dffeas \z80_|interrupts_|nmi_armed ( + .clk(!\KEY[1]~input_o ), + .d(\z80_|interrupts_|nmi_armed~feeder_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|nmi_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|nmi_armed .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N12 +cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( +// Equation(s): +// \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|interrupts_|nmi_armed~q ), + .cin(gnd), + .combout(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( +// Equation(s): +// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h1100; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N31 +dffeas \z80_|sequencer_|DFFE_M3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( +// Equation(s): +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hD0D0; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N2 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N3 +dffeas \z80_|sequencer_|DFFE_M4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h00CC; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( +// Equation(s): +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|decode_state_|table_xx~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal36~0_combout )))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|pla_decode_|Equal36~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal36~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hB3A0; +defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EA; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X41_Y17_N29 +dffeas \z80_|decode_state_|DFFE_instCB ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instCB~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X41_Y17_N17 +dffeas \z80_|decode_state_|DFFE_instED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) + + .dataa(\z80_|ir_|opcode [7]), + .datab(gnd), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout )) + + .dataa(gnd), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal49~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [3])) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~8_combout = (((!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h4FFF; +defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N12 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h0055; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hEF00; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( +// Equation(s): +// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal3~2_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( +// Equation(s): +// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( +// Equation(s): +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( +// Equation(s): +// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( +// Equation(s): +// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~8_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( +// Equation(s): +// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal44~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( +// Equation(s): +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( +// Equation(s): +// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|execute_|ixy_d~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(gnd), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal50~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( +// Equation(s): +// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|pla_decode_|Equal50~0_combout & ((!\z80_|pla_decode_|Equal33~2_combout )))) # (!\z80_|decode_state_|DFFE_inst4~q & (((!\z80_|pla_decode_|Equal50~0_combout & +// !\z80_|pla_decode_|Equal33~2_combout )) # (!\z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0537; +defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( +// Equation(s): +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & +// (!\z80_|execute_|ixy_d~13_combout & (\z80_|execute_|ixy_d~17_combout ))) + + .dataa(\z80_|execute_|ixy_d~12_combout ), + .datab(\z80_|execute_|ixy_d~13_combout ), + .datac(\z80_|execute_|ixy_d~17_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h30BA; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( +// Equation(s): +// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( +// Equation(s): +// \z80_|execute_|ixy_d~15_combout = ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|execute_|ixy_d~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & +// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N23 +dffeas \z80_|decode_state_|DFFE_instIY1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_iy_set~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instIY1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0500; +defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_mRead~26_combout & !\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ctl_mRead~27_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h5D00; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal12~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0500; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( +// Equation(s): +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|comb~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|comb~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~17_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~18_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal32~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|reg_control_|reg_sys_we_lo~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|pla_decode_|Equal24~1_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~3_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|reg_control_|reg_sys_we_lo~3_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h153F; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~20_combout ), + .datab(\z80_|execute_|ctl_mRead~21_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~18_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~18_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( +// Equation(s): +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|M5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N17 +dffeas \z80_|sequencer_|M5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|M5~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|M5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|M5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & +// (((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'h0777; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout +// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~29_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~7_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~14_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_state_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~14_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & +// (((!\z80_|execute_|ctl_state_alu~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'h115F; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F3F; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|pla_decode_|Equal29~0_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Equation(s): +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_state_alu~8_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~8_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'h7000; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & +// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mRead~18_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal41~0_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal46~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_flags_alu~17_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0505; +defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~6_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_alu~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~17_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_mWrite~8_combout ))) + + .dataa(\z80_|execute_|fMRead~17_combout ), + .datab(\z80_|execute_|ctl_sw_2d~4_combout ), + .datac(\z80_|execute_|fMRead~16_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_mRead~24_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~18_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~24_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|fMRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~36_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~9_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~3_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h007F; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ixy_d~6_combout & +// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~4_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal46~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & (((!\z80_|execute_|ctl_ir_we~12_combout ) # +// (!\z80_|execute_|ctl_mWrite~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0577; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datab(\z80_|execute_|ctl_sw_2d~7_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|fMRead~19_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|ctl_sw_2d~8_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), + .datab(\z80_|execute_|fMRead~19_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datad(\z80_|execute_|ctl_sw_2d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_sw_2d~9_combout ))) + + .dataa(\z80_|execute_|ctl_im_we~combout ), + .datab(\z80_|execute_|ctl_sw_1d~5_combout ), + .datac(\z80_|execute_|ctl_sw_1d~4_combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout ))) # (!\z80_|execute_|ctl_sw_1d~6_combout ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7333; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0111; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~4 ( +// Equation(s): +// \z80_|alu_|db_low[2]~4_combout = ((\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~4 .lut_mask = 16'h555D; +defparam \z80_|alu_|db_low[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_sw_4u~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # +// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~29_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) + + .dataa(\z80_|ir_|opcode [4]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00AA; +defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~2 ( +// Equation(s): +// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0011; +defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0103; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0D0; +defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~15_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0F3F; +defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_ir_we~7_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~15_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & !\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_mWrite~16_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~13 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_alu_bs_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_alu_bs_oe~13_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~13_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|pla_decode_|Equal68~2_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_flags_bus~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'hAFBF; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~10_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_flags_bus~8_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_flags_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~11_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~14_combout ), + .datab(\z80_|execute_|ctl_flags_bus~11_combout ), + .datac(\z80_|execute_|ctl_flags_bus~10_combout ), + .datad(\z80_|execute_|ctl_flags_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_state_alu~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) # +// (!\z80_|execute_|ctl_mWrite~3_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h3030; +defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|pla_decode_|Equal41~2_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1100; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[2]~14_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N17 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88C8; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~11 ( +// Equation(s): +// \z80_|execute_|fMWrite~11_combout = ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~11 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~21_combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_alu_op_low~9_combout ))) # (!\z80_|execute_|fMWrite~11_combout ) + + .dataa(\z80_|execute_|fMWrite~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~22_combout = ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h7737; +defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~16_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~36 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (\z80_|execute_|ctl_state_alu~8_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datab(\z80_|execute_|ctl_state_alu~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_mWrite~3_combout & +// (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~19_combout = ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'h77F7; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_mRead~36_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op_low~22_combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|execute_|ixy_d~5_combout & +// (\z80_|pla_decode_|Equal40~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hEAE0; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFF08; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = ((\z80_|execute_|ctl_alu_op_low~24_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~26_combout ) # (\z80_|execute_|ctl_mRead~27_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) + + .dataa(\z80_|execute_|ctl_mRead~26_combout ), + .datab(\z80_|execute_|ctl_mRead~27_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hEF0F; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = (\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (((\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = (\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hF200; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3F20; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~22_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0CEC; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h32F0; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h22EA; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~14_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~14 .lut_mask = 16'hC0C8; +defparam \z80_|execute_|ctl_alu_bs_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~14_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00EA; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & +// (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~4_combout +// & (\z80_|execute_|ctl_ir_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEAC8; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|execute_|ctl_alu_bs_oe~10_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (!\z80_|execute_|ctl_alu_bs_oe~11_combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h00CF; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~32_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_alu_shift_oe~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF51; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~7_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # +// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h3F20; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~12_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~26_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|pla_decode_|Equal48~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h1300; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0C00; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & +// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal11~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_alu~9_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~9_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~10_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_ir_we~14_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout ) # +// (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'h0377; +defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~25_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~13_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'h3331; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h5557; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h7000; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|ctl_state_alu~7_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~3_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & +// (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~3_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'h8C88; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~2_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(gnd), + .datac(\z80_|alu_|db_high[3]~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hFAFA; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~24 ( +// Equation(s): +// \z80_|alu_|db_low[2]~24_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~3_combout & (\z80_|alu_|db_low[2]~6_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~3_combout & +// \z80_|alu_|db_low[2]~6_combout )) # (!\z80_|alu_|db_high[3]~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[2]~3_combout ), + .datac(\z80_|alu_|db_low[2]~6_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~24 .lut_mask = 16'hC0D5; +defparam \z80_|alu_|db_low[2]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h0AAA; +defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|reg_control_|reg_sys_we_lo~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~43_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & \z80_|execute_|ctl_bus_inc_oe~25_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|execute_|ctl_alu_oe~8_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~8_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mWrite~16_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & +// (((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (((!\z80_|execute_|ctl_mRead~27_combout & !\z80_|execute_|ctl_mRead~26_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~27_combout ), + .datac(\z80_|execute_|ctl_mRead~26_combout ), + .datad(\z80_|execute_|ctl_alu_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|execute_|ctl_alu_oe~11_combout ) # (((!\z80_|execute_|ctl_alu_oe~7_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|execute_|ctl_alu_oe~5_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_alu_oe~12_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~12_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_oe~13_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hF5F5; +defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & +// (((!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mRead~26_combout ))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|nextM~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'h8C00; +defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( +// Equation(s): +// \z80_|execute_|setM1~54_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'hABFF; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~7_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_alu_oe~3_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout )) # +// (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_alu_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_sw_2u~4_combout )) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~1_combout ), + .datad(\z80_|execute_|ctl_sw_2u~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~36_combout & (\z80_|execute_|comb~0_combout $ ((!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_reg_gp_sel~36_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & +// (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~35_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_inc_cy~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(\z80_|execute_|ctl_sw_2u~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h7878; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & +// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (!\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h5AAA; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h0444; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~14_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~10_combout ), + .datab(\z80_|execute_|ctl_sw_2d~14_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEAA; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~11_combout ), + .datac(\z80_|execute_|ctl_sw_2d~12_combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_alu_oe~2_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|pla_decode_|Equal38~2_combout & ((!\z80_|pla_decode_|Equal37~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|pla_decode_|Equal38~2_combout +// & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~75_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal29~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~48_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|execute_|ctl_bus_inc_oe~48_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & +// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~92_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~38_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal3~1_combout )) # (!\z80_|pla_decode_|Equal19~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal19~1_combout ), + .datac(\z80_|execute_|ctl_sw_4u~0_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~93_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~93_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~93_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~24_combout = (\z80_|execute_|ctl_inc_cy~92_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~39_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~92_combout ), + .datac(\z80_|execute_|ctl_inc_cy~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~1_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (\z80_|execute_|ctl_bus_inc_oe~46_combout & (\z80_|execute_|ctl_inc_cy~53_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~53_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~44_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_sw_4u~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .datad(\z80_|execute_|ctl_sw_4u~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( +// Equation(s): +// \z80_|execute_|fMRead~3_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ctl_state_alu~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # +// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~15_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_state_alu~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_sw_4u~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~94_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~94_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~87_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~94_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ctl_inc_cy~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (\z80_|execute_|fMRead~3_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) + + .dataa(\z80_|execute_|fMRead~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout ))) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~5_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~6_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal1~5_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~6_combout & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal1~6_combout ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N23 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N27 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal2~1_combout ), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hC888; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~12_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal50~0_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( +// Equation(s): +// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFAF; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( +// Equation(s): +// \z80_|execute_|fMRead~2_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_flags_bus~5_combout )) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~14_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h1010; +defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|fMWrite~3_combout & (\z80_|execute_|fMRead~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|fMWrite~3_combout ), + .datac(\z80_|execute_|fMRead~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h00C0; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h50F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hC5CD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout & ((\z80_|execute_|ctl_ir_we~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hCAC0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [4]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~47_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~8_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~47_combout & \z80_|execute_|nextM~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~21_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~5_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_sw_1d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & +// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hAB00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~20_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|pla_decode_|Equal49~0_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .lut_mask = 16'h0101; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~22_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'h0032; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout & \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~36_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00CC; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h20AA; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0505; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|pla_decode_|Equal68~2_combout & (!\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_flags_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~48_combout )))) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|ctl_flags_oe~1_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0070; +defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~40_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (\z80_|execute_|ctl_inc_cy~43_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_inc_cy~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal29~0_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & +// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0357; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & +// !\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h111F; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|fMRead~7_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h10F0; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .datac(\z80_|execute_|fMRead~6_combout ), + .datad(\z80_|execute_|fMRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|execute_|ctl_state_alu~8_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~8_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'h3331; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) # +// (!\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|pla_decode_|Equal52~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (\z80_|execute_|ctl_state_alu~14_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|execute_|ctl_state_alu~14_combout & (\z80_|pla_decode_|Equal52~1_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'hF3A2; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~9_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hFD00; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~4_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h373F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~9_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00FD; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal64~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hEEFF; +defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .datac(\z80_|execute_|ctl_alu_oe~7_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_state_alu~14_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|pla_decode_|Equal52~1_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~15 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|ctl_state_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (\z80_|execute_|ctl_state_alu~15_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )) + + .dataa(\z80_|execute_|ctl_state_alu~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ) # (((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout & \z80_|ir_|opcode [5])) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & +// ((\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hFF70; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hF7F7; +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h22A2; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; +defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h0F0B; +defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N15 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) + + .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hAC00; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_state_alu~15_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_state_alu~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h1100; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout & ((!\z80_|execute_|ctl_iorw~10_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout +// )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|pla_decode_|Equal25~0_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout & !\z80_|execute_|ctl_sw_1d~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), + .datad(\z80_|execute_|ctl_sw_1d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_reg_gp_we~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~5_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .datab(\z80_|execute_|ctl_sw_4u~3_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~7_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; +defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_flags_oe~1_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h1033; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ctl_al_we~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFBF0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h40CC; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (((\z80_|execute_|ctl_ir_we~7_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_iorw~11_combout ) # ((\z80_|execute_|ctl_state_alu~14_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~14_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~25_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & +// (((\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )) # (!\z80_|execute_|setM1~48_combout ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hCD05; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~9_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout )) # +// (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h1357; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h1155; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~40_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h1101; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout +// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_gp_we~5_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_mRead~22_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00B0; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) + + .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N21 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (!\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_control_|bank_af~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h1000; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_control_|bank_af~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout ) # +// (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'h035F; +defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hF8F8; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_bus~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h0777; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~7_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~24_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), + .datab(\z80_|execute_|fMRead~24_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3777; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|fMRead~3_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7757; +defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ixy_d~16_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ixy_d~16_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h557F; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & +// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|execute_|ctl_mRead~17_combout )))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h0222; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sel_pc~10_combout & (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datab(\z80_|execute_|ctl_inc_cy~94_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ctl_inc_cy~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & +// !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|ir_|opcode [5]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h5455; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~49 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~49_combout = (!\z80_|pla_decode_|Equal35~0_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~49 .lut_mask = 16'h00FD; +defparam \z80_|execute_|pc_inc_hold~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) + + .dataa(\z80_|execute_|pc_inc_hold~49_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0A00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|pla_decode_|Equal33~2_combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0515; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'h0003; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( +// Equation(s): +// \z80_|execute_|setM1~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_mRead~9_combout & (\z80_|execute_|pc_inc_hold~28_combout & \z80_|execute_|setM1~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|setM1~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~36 .lut_mask = 16'h2000; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( +// Equation(s): +// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|setM1~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0100; +defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA222; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hC8C8; +defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(gnd), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEE00; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~49_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|pc_inc_hold~49_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hF0B0; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~3_combout = (((\z80_|execute_|ctl_reg_sys_we~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout )) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|execute_|ctl_reg_sys_we~3_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEFFF; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF5D; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~34_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~34_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'h8CCC; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal3~1_combout ) # (!\z80_|pla_decode_|Equal19~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal19~1_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h5777; +defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; +defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h80C0; +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|execute_|ctl_mRead~36_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_al_we~13_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (\z80_|execute_|setM1~52_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datac(\z80_|execute_|setM1~52_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ctl_mRead~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h2022; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~0 ( +// Equation(s): +// \z80_|execute_|fMRead~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~0 .lut_mask = 16'h5D5D; +defparam \z80_|execute_|fMRead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal52~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0030; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h050F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h0FAF; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_reg_sys_hilo~20_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # +// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datac(\z80_|execute_|ctl_inc_dec~4_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hD0DD; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_ir_we~14_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout +// )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00C4; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~49_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~49_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h08CC; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h4455; +defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~0_combout ) # ((!\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|pc_inc_hold~28_combout )))) + + .dataa(\z80_|execute_|fMRead~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00BA; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_al_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4404; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_state_alu~14_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~49_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h0222; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~45_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~1 ( +// Equation(s): +// \z80_|execute_|fMRead~1_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~1 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMRead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMRead~1_combout ))) + + .dataa(\z80_|execute_|fMRead~1_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~46_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~45_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~39_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout ) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_inc_cy~76_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # +// (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~2_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~53_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), + .datab(\z80_|execute_|ctl_inc_cy~77_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & +// (((!\z80_|execute_|ctl_alu_oe~2_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'hA0F3; +defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_sel_wz~10_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & +// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~6_combout ), + .datad(\z80_|execute_|fMRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_reg_sel_wz~11_combout & (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~4_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .datab(\z80_|execute_|ctl_sw_4d~3_combout ), + .datac(\z80_|execute_|ctl_sw_4d~4_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~19_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~19_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~45_combout & !\z80_|execute_|ctl_mWrite~6_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_al_we~13_combout ), + .datac(\z80_|execute_|setM1~45_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h00C0; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~1_combout = ((!\z80_|decode_state_|use_ixiy~combout & ((\z80_|pla_decode_|Equal50~0_combout ) # (\z80_|pla_decode_|Equal49~0_combout )))) # (!\z80_|execute_|setM1~46_combout ) + + .dataa(\z80_|pla_decode_|Equal50~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|setM1~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'h32FF; +defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_al_we~14_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = ((\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout & \z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~5_combout ), + .datab(\z80_|execute_|ctl_sw_4d~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_sw_4d~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( +// Equation(s): +// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; +defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|fMRead~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h5DFF; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & (((\z80_|decode_state_|table_xx~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h00DF; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5010; +defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|setM1~36_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .datad(\z80_|execute_|fMRead~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hF0F7; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((!\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h4FFF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (\z80_|execute_|ctl_reg_sel_pc~18_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0800; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|execute_|ctl_sw_4d~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hF030; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N26 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N27 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N9 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N29 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + // Location: IOIBUF_X53_Y14_N1 cycloneive_io_ibuf \KEY[0]~input ( .i(KEY[0]), @@ -4120,7 +15959,7 @@ defparam \KEY[0]~input .bus_hold = "false"; defparam \KEY[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N6 +// Location: LCCOMB_X52_Y14_N4 cycloneive_lcell_comb reset( // Equation(s): // \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) @@ -4137,7 +15976,7 @@ defparam reset.lut_mask = 16'h0FFF; defparam reset.sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N22 +// Location: LCCOMB_X35_Y13_N26 cycloneive_lcell_comb \z80_|resets_|x1~0 ( // Equation(s): // \z80_|resets_|x1~0_combout = !\reset~combout @@ -4203,7 +16042,7 @@ defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X52_Y17_N23 +// Location: FF_X35_Y13_N27 dffeas \z80_|resets_|x1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|x1~0_combout ), @@ -4222,4021 +16061,25 @@ defparam \z80_|resets_|x1 .is_wysiwyg = "true"; defparam \z80_|resets_|x1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N8 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|x3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hFF44; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y17_N9 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G7 -cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y16_N8 -cycloneive_io_ibuf \KEY[1]~input ( - .i(KEY[1]), - .ibar(gnd), - .o(\KEY[1]~input_o )); -// synopsys translate_off -defparam \KEY[1]~input .bus_hold = "false"; -defparam \KEY[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N12 -cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( -// Equation(s): -// \z80_|interrupts_|nmi_armed~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; -defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N14 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y15_N13 -dffeas \z80_|interrupts_|nmi_armed ( - .clk(!\KEY[1]~input_o ), - .d(\z80_|interrupts_|nmi_armed~feeder_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|nmi_armed~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|nmi_armed .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N26 -cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( -// Equation(s): -// \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|interrupts_|nmi_armed~q ), - .cin(gnd), - .combout(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N24 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h5500; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N20 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N21 -dffeas \z80_|sequencer_|DFFE_M3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N6 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N7 -dffeas \z80_|sequencer_|DFFE_M4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h0303; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0030; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N28 -cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( -// Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|M5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N29 -dffeas \z80_|sequencer_|M5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|M5~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|M5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|M5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~12_combout & -// ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|decode_state_|DFFE_instCB~q & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal46~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [6] & \z80_|ir_|opcode [7]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hC0C0; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0303; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (((!\z80_|execute_|ixy_d~7_combout )) # -// (!\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_alu_core_S~10_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~49_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout )) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|ir_|opcode [7] & (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [6] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ixy_d~4_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ctl_mWrite~16_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_bus_inc_oe~49_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N10 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N11 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|pla_decode_|Equal41~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal33~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC080; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~13_combout & (!\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ixy_d~12_combout ))) # (!\z80_|execute_|ixy_d~13_combout & ((\z80_|execute_|ixy_d~17_combout ) # ((!\z80_|execute_|ixy_d~4_combout -// & \z80_|execute_|ixy_d~12_combout )))) - - .dataa(\z80_|execute_|ixy_d~13_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ixy_d~12_combout ), - .datad(\z80_|execute_|ixy_d~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h7530; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (!\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'h0300; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hC8CC; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h0A00; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|execute_|ixy_d~11_combout & (\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|execute_|ixy_d~14_combout ), - .datab(\z80_|execute_|ixy_d~11_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'hD555; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N4 -cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|ir_|opcode [5] & -// \z80_|pla_decode_|Equal3~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h5530; -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N5 -dffeas \z80_|decode_state_|DFFE_inst4 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_inst4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N20 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( -// Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) - - .dataa(gnd), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFCC; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~9_combout & !\z80_|execute_|ctl_mWrite~4_combout )) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h0011; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hF000; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~36_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~0 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~0_combout = (\z80_|execute_|ctl_inc_cy~36_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_inc_cy~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~0 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_inc_dec~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ctl_inc_dec~0_combout & ((\z80_|execute_|fMWrite~5_combout ) # ((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|fMWrite~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~0_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hFE00; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~12_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout & -// (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~12_combout )) # (!\z80_|execute_|ctl_sw_4u~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|ctl_mRead~12_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hC000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'h007F; -defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( -// Equation(s): -// \z80_|execute_|fIOWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'h5755; -defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( -// Equation(s): -// \z80_|execute_|fMWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h1F1F; -defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal46~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hFF2F; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N8 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|fIOWrite~5_combout & (((\z80_|execute_|fMWrite~0_combout ) # (\z80_|execute_|fMWrite~6_combout )))) # (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|ctl_mWrite~6_combout & -// ((\z80_|execute_|fMWrite~0_combout ) # (\z80_|execute_|fMWrite~6_combout )))) - - .dataa(\z80_|execute_|fIOWrite~5_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|fMWrite~0_combout ), - .datad(\z80_|execute_|fMWrite~6_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'hBBB0; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = ((!\z80_|ir_|opcode [7]) # (!\z80_|execute_|ctl_ir_we~5_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|ir_|opcode [7]), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h3FFF; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal33~1_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N16 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|fMRead~3_combout & ((!\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~8_combout ) # -// (!\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h03AF; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~7_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~1_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal19~1_combout ) # (!\z80_|pla_decode_|Equal3~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h1F3F; -defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N18 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (!\z80_|execute_|fMWrite~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) - - .dataa(\z80_|execute_|fMWrite~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h4000; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (!\z80_|execute_|fMWrite~8_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & \z80_|pin_control_|bus_db_pin_oe~11_combout ))) - - .dataa(\z80_|execute_|fMWrite~8_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h4000; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N12 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h135F; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'hAA2A; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h2A00; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~3_combout = (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~31 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~31_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~31 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|execute_|ctl_inc_cy~31_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|execute_|ctl_inc_cy~31_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h8AAA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~30 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~30_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & -// (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_inc_cy~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_inc_cy~30_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( -// Equation(s): -// \z80_|execute_|fMWrite~1_combout = (!\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = (!\z80_|execute_|fMWrite~1_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|fMWrite~0_combout )))) - - .dataa(\z80_|execute_|fMWrite~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|fMWrite~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h5545; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h3F33; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h3332; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~34_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal19~1_combout )) # (!\z80_|pla_decode_|Equal3~1_combout ) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (((!\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_inc_cy~86_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_inc_cy~85_combout & (\z80_|execute_|ctl_inc_cy~34_combout & \z80_|execute_|ctl_inc_cy~35_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|execute_|ctl_inc_cy~34_combout ), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( -// Equation(s): -// \z80_|execute_|fIOWrite~3_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'hB0B0; -defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal21~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~38 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~38_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~38 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'h7575; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( -// Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|fIOWrite~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|execute_|fIOWrite~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h5F0F; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = (\z80_|execute_|ctl_iorw~10_combout & (((\z80_|execute_|ctl_mWrite~2_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|fMRead~2_combout ))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'hFD00; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( -// Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~0_combout ) # ((\z80_|execute_|fIOWrite~3_combout & \z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|fIOWrite~3_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|fIOWrite~2_combout ), - .datad(\z80_|execute_|fIOWrite~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (!\z80_|execute_|fMWrite~2_combout & (!\z80_|execute_|fMWrite~4_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & !\z80_|execute_|fIOWrite~4_combout ))) - - .dataa(\z80_|execute_|fMWrite~2_combout ), - .datab(\z80_|execute_|fMWrite~4_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h0010; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~32 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~32_combout = ((!\z80_|execute_|ixy_d~4_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~32 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_inc_cy~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~33 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~33_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~32_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_sw_2u~0_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~33 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_inc_cy~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~13_combout & (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~3_combout & \z80_|execute_|ctl_inc_cy~33_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datab(\z80_|execute_|ctl_apin_mux~0_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .datad(\z80_|execute_|ctl_inc_cy~33_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFFAA; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~15_combout = (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|execute_|fIOWrite~4_combout ) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout & \z80_|pin_control_|bus_db_pin_oe~2_combout )))) # (!\z80_|sequencer_|DFFE_T4_ff~q & -// (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|pin_control_|bus_db_pin_oe~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'hBA30; -defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G5 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [2] & !\ula_|ps2_keyboard_|bit_count [1])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0507; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: FF_X25_Y23_N21 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_CLK~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y23_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|clk_filter [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N25 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N7 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [5]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [6]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [4]), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [1] & (!\ula_|ps2_keyboard_|clk_filter [2] & (\ula_|ps2_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|clk_filter [3]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [1]), - .datab(\ula_|ps2_keyboard_|clk_filter [2]), - .datac(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0010; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h00FF; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFA50; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N27 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) - - .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0A00; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N29 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y15_N3 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [0]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1450; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N5 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & -// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N7 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N13 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [2]) # (\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hAAA0; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|always1~0_combout ), - .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h3010; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N27 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N21 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N19 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N15 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N23 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N31 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y15_N3 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~0_combout $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hA55A; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & \ula_|ps2_keyboard_|WideXor0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|clk_edge~q ), - .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N9 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|Equal0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF500; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N15 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~45_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0010; -defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hF830; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [1]) # (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; -defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h1004; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & ((!\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hC0E2; -defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|WideOr16~5_combout & (\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~5_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|WideOr16~7_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF088; -defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N7 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h00C0; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hAA88; -defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|pc_inc_hold~19_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|pc_inc_hold~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hEA00; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~9_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~9_combout )) # -// (!\z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h131F; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & (!\z80_|execute_|ctl_reg_sys_we~0_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~34_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4040; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~13_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~1 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~1_combout = (\z80_|execute_|ctl_inc_cy~37_combout & (((!\z80_|pla_decode_|Equal19~1_combout ) # (!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_inc_cy~37_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~1 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_inc_dec~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_dec~1_combout & (\z80_|execute_|ctl_inc_dec~0_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3F0F; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|fIOWrite~5_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|fIOWrite~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~38_combout ))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|execute_|ctl_mWrite~3_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h1F5F; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_inc_dec~4_combout ) # (((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_inc_dec~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .datad(\z80_|execute_|ctl_inc_dec~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'hCEFF; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (((\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )) # (!\z80_|execute_|ctl_inc_dec~7_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|execute_|ctl_inc_dec~2_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N28 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h00FF; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N29 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N22 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N23 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X51_Y12_N27 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N0 +// Location: LCCOMB_X29_Y17_N18 cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( // Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|resets_|clrpc_int~q & ((!\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|resets_|clrpc_int~q & -// (!\z80_|resets_|x1~q & \z80_|sequencer_|DFFE_T2_ff~q )))) +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # +// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|resets_|x1~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), .datac(\z80_|resets_|clrpc_int~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|resets_|x1~q ), .cin(gnd), .combout(\z80_|resets_|clrpc_int~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hA1F0; +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X51_Y12_N1 +// Location: FF_X29_Y17_N19 dffeas \z80_|resets_|clrpc_int ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|clrpc_int~0_combout ), @@ -8255,13 +16098,13 @@ defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; defparam \z80_|resets_|clrpc_int .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y12_N26 +// Location: LCCOMB_X29_Y17_N28 cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( // Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), .datac(\z80_|resets_|DFFE_intr_ff3~q ), .datad(\z80_|resets_|clrpc_int~q ), .cin(gnd), @@ -8272,9478 +16115,181 @@ defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .lut_mask = 16'h1300; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|pla_decode_|Equal38~2_combout & (!\z80_|execute_|ixy_d~4_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~4_combout & -// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_inc_cy~76_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ixy_d~4_combout ))) # (!\z80_|execute_|ctl_mRead~18_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & -// !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0357; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~50_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hF000; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|ir_|opcode [3]))) - - .dataa(\z80_|execute_|comb~1_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .datab(\z80_|pla_decode_|Equal4~0_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (\z80_|execute_|ctl_inc_cy~47_combout & (\z80_|execute_|ctl_bus_inc_oe~48_combout & \z80_|execute_|ctl_bus_inc_oe~26_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~77_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3])) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|pla_decode_|Equal56~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0101; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~4_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_sw_4u~2_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_sw_4u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (((\z80_|ir_|opcode [5]) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0F07; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~38_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'hAFBF; -defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout = (\z80_|execute_|ctl_inc_cy~82_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~87_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~82_combout ), - .datab(\z80_|execute_|ctl_inc_cy~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~87_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout = (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout -// )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'h040C; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0003; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hC0C0; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~34_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~34 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout & \z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal1~5_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal1~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'hFDDD; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (((\z80_|execute_|ctl_sw_4u~4_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~16_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .datac(\z80_|execute_|ctl_sw_4u~4_combout ), - .datad(\z80_|execute_|ctl_apin_mux~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~19_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( -// Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal29~0_combout & (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|pla_decode_|Equal29~0_combout & -// !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~3_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~13_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~3 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( -// Equation(s): -// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|execute_|ctl_mRead~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( -// Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|fMRead~13_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'h3070; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~25_combout = (\z80_|execute_|fMRead~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~3_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|fMRead~14_combout ))) - - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datad(\z80_|execute_|fMRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_mRead~13_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( -// Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h01FF; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~25_combout )) - - .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hBBFF; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N22 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h0303; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5515; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal12~0_combout ) - - .dataa(\z80_|pla_decode_|Equal12~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h2020; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~16_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0011; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_sw_1d~8_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|decode_state_|DFFE_instCB~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~3_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFBB; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|ir_|opcode [1])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|execute_|ctl_flags_oe~0_combout & \z80_|execute_|ctl_al_we~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_flags_oe~0_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hAFAF; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & !\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~8_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & (!\z80_|pla_decode_|Equal68~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|pla_decode_|Equal68~2_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal46~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|pla_decode_|Equal20~0_combout & !\z80_|execute_|ctl_ir_we~8_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h000F; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_hf_cpl~8_combout & (\z80_|execute_|setM1~47_combout & (\z80_|execute_|nextM~2_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datab(\z80_|execute_|setM1~47_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|setM1~48_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~1_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h004C; -defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_in_hi~8_combout & (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_mRead~19_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout -// & (((!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_mRead~19_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~18_combout & -// (((!\z80_|execute_|ctl_mRead~19_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~2_combout = (\z80_|execute_|ctl_mRead~27_combout & (\z80_|execute_|setM1~30_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|setM1~30_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~2 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & ((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|pla_decode_|Equal21~1_combout -// )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0007; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h035F; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h3233; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & \z80_|execute_|ctl_state_alu~9_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout -// & (\z80_|execute_|ctl_state_alu~5_combout & (\z80_|execute_|ctl_state_alu~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|pla_decode_|Equal52~1_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hF5C4; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal3~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout = ((!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .lut_mask = 16'h337F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h5551; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal64~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hFAFF; -defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal3~1_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_alu_oe~9_combout & (((!\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_mRead~28_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mRead~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & \z80_|execute_|ctl_alu_oe~10_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|execute_|ctl_alu_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_mRead~20_combout ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout & \z80_|execute_|ctl_reg_gp_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_we~5_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~2_combout & \z80_|execute_|ctl_reg_gp_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~8_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~9_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|execute_|setM1~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .lut_mask = 16'h8AFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_alu_op_low~19_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'h3233; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hCC04; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~51_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~51 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ctl_mRead~7_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~4_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .lut_mask = 16'h4C44; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h6A6A; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .lut_mask = 16'hFAFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h3FC0; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~10_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_sw_2u~0_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~50_combout = (\z80_|execute_|ctl_sw_2u~3_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|sequencer_|M5~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_sw_2u~3_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~50 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~5_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_gp_sel~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_2u~5_combout ) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ) # (((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .lut_mask = 16'hBFAF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout ) # -// (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h0757; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|pla_decode_|Equal4~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h030F; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|pla_decode_|Equal2~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|setM1~41_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h0023; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~25_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_state_alu~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h000C; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (!\z80_|execute_|ctl_mRead~15_combout & (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_ir_we~12_combout & \z80_|execute_|fMRead~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|fMWrite~1_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (((\z80_|ir_|opcode [7]) # (!\z80_|decode_state_|DFFE_instED~q )) # (!\z80_|ir_|opcode [6])) # (!\z80_|pla_decode_|Equal1~4_combout ) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_mRead~21_combout & (\z80_|execute_|ctl_iorw~12_combout & (!\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ctl_al_we~13_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~21_combout ), - .datab(\z80_|execute_|ctl_iorw~12_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h0800; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h3BBB; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal44~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~38_combout & !\z80_|execute_|ctl_iorw~11_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (\z80_|execute_|ctl_alu_shift_oe~26_combout & ((!\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal32~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|execute_|ixy_d~10_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_flags_bus~6_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_flags_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal76~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal76~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4])) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal76~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = ((!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|pla_decode_|Equal76~0_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|pla_decode_|Equal76~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|execute_|ctl_alu_op_low~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_flags_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~7_combout & (\z80_|execute_|ctl_flags_bus~8_combout & (\z80_|execute_|ctl_flags_bus~14_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), - .datab(\z80_|execute_|ctl_flags_bus~8_combout ), - .datac(\z80_|execute_|ctl_flags_bus~14_combout ), - .datad(\z80_|execute_|ctl_flags_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout & \z80_|execute_|ctl_flags_bus~10_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_flags_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h1115; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h0111; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~7_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~22_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|execute_|ctl_mRead~22_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~7 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & \z80_|execute_|ctl_reg_gp_sel[0]~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datab(\z80_|execute_|nextM~11_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal21~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # (\z80_|sequencer_|M5~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h0302; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~34_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~34 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((!\z80_|pla_decode_|Equal12~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hB0F5; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & (\z80_|execute_|ctl_ir_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~6_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hF808; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~2_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~34_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h80F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # (\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ))) # -// (!\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal2~1_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal4~0_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'hA8A0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'h0F0E; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # ((\z80_|execute_|ctl_mRead~38_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~56 ( -// Equation(s): -// \z80_|execute_|setM1~56_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~56 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout = (\z80_|execute_|setM1~56_combout & (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|setM1~56_combout ), - .datab(\z80_|execute_|ctl_sw_2u~1_combout ), - .datac(\z80_|execute_|ctl_sw_2u~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|ir_|opcode [2] & !\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~26_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~5_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~26 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~7_combout & (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout & \z80_|execute_|ctl_reg_gp_sel[0]~26_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~25_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_mRead~38_combout ) # ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'h3377; -defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_ir_we~12_combout & \z80_|execute_|fMRead~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|fMWrite~1_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # (!\z80_|execute_|ctl_mRead~29_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_mRead~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hB3F3; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~29 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~24_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~24 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_reg_sys_hilo~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ctl_reg_sys_hilo~24_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h22A2; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~31_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & -// ((\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~31 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~31_combout ) # ((\z80_|ir_|opcode [1] & !\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~31_combout ), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'hAAEE; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~28_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal1~5_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N18 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|pla_decode_|Equal1~6_combout & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|pla_decode_|Equal1~6_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hF078; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N19 -dffeas \z80_|reg_control_|bank_exx ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0200; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0200; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFFEE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N0 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((\z80_|pla_decode_|Equal32~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal21~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N1 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|reg_control_|bank_af~q & (!\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0200; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_control_|bank_af~q & (!\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h0800; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h4400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|pla_decode_|Equal19~0_combout )) # -// (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h07FF; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal29~0_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal38~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~11_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_sel_wz~6_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & \z80_|execute_|ctl_reg_in_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|execute_|ctl_mRead~11_combout & -// ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h45CF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # ((\z80_|execute_|ctl_mRead~19_combout ) # (\z80_|pla_decode_|Equal34~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_mRead~19_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~4_combout ) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal25~0_combout ), - .datac(\z80_|pla_decode_|Equal12~1_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h55F7; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ixy_d~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ixy_d~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|execute_|ixy_d~4_combout & -// (((!\z80_|execute_|ixy_d~16_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (!\z80_|execute_|ctl_reg_sel_pc~9_combout & (\z80_|execute_|ctl_reg_sel_pc~7_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h1050; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout = (\z80_|execute_|ctl_inc_cy~82_combout & (\z80_|execute_|ctl_inc_cy~38_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~87_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~82_combout ), - .datab(\z80_|execute_|ctl_inc_cy~38_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datad(\z80_|execute_|ctl_inc_cy~87_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_mWrite~16_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_sel_pc~11_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ixy_d~16_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ixy_d~16_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~40_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~40 .lut_mask = 16'h4050; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_ir_we~6_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~18_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'h001F; -defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (!\z80_|execute_|ctl_mRead~19_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h00AF; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (!\z80_|execute_|ctl_reg_sel_wz~7_combout & ((\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00FE; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & ((\z80_|execute_|fMRead~2_combout ) # ((!\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|pc_inc_hold~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|fMRead~2_combout ), - .datac(\z80_|execute_|pc_inc_hold~18_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h00DC; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal40~0_combout ) - - .dataa(\z80_|pla_decode_|Equal40~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h57FF; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout = (!\z80_|pla_decode_|Equal24~1_combout & (!\z80_|pla_decode_|Equal19~0_combout & (!\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~1_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .lut_mask = 16'h050F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~40_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h3323; -defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0101; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (\z80_|pla_decode_|Equal33~3_combout & (\z80_|execute_|ctl_inc_dec~3_combout & ((\z80_|execute_|ctl_reg_sys_hilo~24_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )))) # -// (!\z80_|pla_decode_|Equal33~3_combout & (((\z80_|execute_|ctl_reg_sys_hilo~24_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_inc_dec~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'hF531; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4500; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & (((\z80_|execute_|pc_inc_hold~40_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~40_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h3B00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h4500; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~16_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (!\z80_|execute_|ctl_reg_sys_hilo~20_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hA8AA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h8C0C; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (\z80_|execute_|setM1~52_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout & \z80_|execute_|ctl_reg_sel_pc~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~20_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~19_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h5444; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # (((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~10_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_ir_we~4_combout & (((\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~7_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((\z80_|execute_|ctl_reg_sel_wz~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hCF05; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & \z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~19_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'hFFDC; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal38~2_combout ) # (\z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N4 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .datac(\z80_|pla_decode_|Equal24~1_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N4 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|reg_control_|reg_sys_we_lo~1_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h0777; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # (\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~24_combout & !\z80_|execute_|ctl_mRead~23_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~24_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datad(\z80_|execute_|ctl_mRead~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h01FF; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~3_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h2A00; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~25_combout & (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal13~1_combout )) # (!\z80_|pla_decode_|Equal13~0_combout ) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'hEAEA; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~11_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_bus~4_combout ), - .datad(\z80_|execute_|ctl_flags_bus~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'hCC4C; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( -// Equation(s): -// \z80_|execute_|fMRead~27_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_alu_shift_oe~28_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_flags_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~12_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~27_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~12_combout ), - .datab(\z80_|execute_|fMRead~27_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~7_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .lut_mask = 16'hBABB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~36_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & \z80_|execute_|ctl_alu_op_low~36_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_state_alu~7_combout & !\z80_|execute_|ctl_alu_shift_oe~15_combout )) - - .dataa(\z80_|execute_|ctl_sw_2u~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'h0088; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (\z80_|execute_|ctl_alu_op_low~21_combout & (!\z80_|execute_|ctl_reg_gp_sel~5_combout & (\z80_|execute_|setM1~17_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datac(\z80_|execute_|setM1~17_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_mRead~38_combout & (!\z80_|execute_|ctl_mRead~13_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_mRead~38_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~27_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hC8CC; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~2_combout = (\z80_|execute_|ctl_flags_cf_we~7_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_flags_use_cf2~13_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_pf_sel[0]~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & (\z80_|execute_|ctl_alu_oe~6_combout & \z80_|execute_|ctl_flags_pf_we~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~6_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~11_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|ir_|opcode [5] & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mRead~38_combout )))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mWrite~7_combout & ((!\z80_|execute_|ctl_mWrite~2_combout )))) # (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_ir_we~11_combout )) -// # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datad(\z80_|pla_decode_|Equal20~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_xy_we~16_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~13_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ctl_reg_use_sp~1_combout & \z80_|execute_|ctl_flags_alu~14_combout ))) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1010; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T5_ff~q )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal10~0_combout & ((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (((!\z80_|execute_|ixy_d~5_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & \z80_|execute_|ctl_flags_alu~10_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~11_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datab(\z80_|execute_|ctl_flags_alu~11_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~6_combout = (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~8_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|execute_|ctl_flags_alu~6_combout & \z80_|execute_|ctl_flags_alu~17_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_alu~6_combout ), - .datad(\z80_|execute_|ctl_flags_alu~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal56~0_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal1~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal1~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hEFCC; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~19_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~19_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~9_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_flags_alu~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout ))) # (!\z80_|execute_|ctl_flags_alu~8_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .datac(\z80_|execute_|ctl_flags_alu~7_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (((\z80_|execute_|ctl_flags_alu~9_combout ) # (!\z80_|execute_|ctl_flags_alu~12_combout )) # (!\z80_|execute_|ctl_flags_alu~15_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_alu~15_combout ), - .datac(\z80_|execute_|ctl_flags_alu~12_combout ), - .datad(\z80_|execute_|ctl_flags_alu~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFFE0; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~6_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|execute_|ctl_reg_gp_sel~5_combout & (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|execute_|comb~0_combout -// $ (!\z80_|ir_|opcode [0])))) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'hD00D; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout & !\z80_|execute_|ctl_sw_2u~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ), - .datad(\z80_|execute_|ctl_sw_2u~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|execute_|nextM~2_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hC040; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = (((\z80_|execute_|ctl_reg_out_hi~8_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N20 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N21 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~28_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h3323; -defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & !\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; -defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h3120; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h3210; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N12 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N13 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de2~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hC840; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~22_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~22 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de2~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hC480; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_hl2~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~23_combout = (\z80_|reg_file_|gdfx_temp1[7]~22_combout & (\z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~23 .lut_mask = 16'hC400; -defparam \z80_|reg_file_|gdfx_temp1[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_af~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_control_|bank_exx~q & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|reg_control_|bank_exx~q & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~24 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h1115; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_mRead~7_combout -// & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h2020; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (\z80_|execute_|ctl_reg_in_hi~10_combout & (\z80_|execute_|ctl_reg_in_hi~7_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = ((\z80_|execute_|ctl_reg_in_hi~9_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~11_combout ) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~26_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[7]~20_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~26 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|decode_state_|DFFE_inst4~q & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~25_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~25 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (!\z80_|pla_decode_|Equal33~3_combout & (!\z80_|pla_decode_|Equal24~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal6~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|pla_decode_|Equal24~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|execute_|ctl_mWrite~16_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~32_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hBFAF; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~1_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hDDD5; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (!\z80_|execute_|ctl_mRead~16_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~0_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~39_combout = (\z80_|execute_|pc_inc_hold~18_combout & (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|pc_inc_hold~18_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~39 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_reg_sys_hilo~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (\z80_|execute_|setM1~36_combout & (\z80_|execute_|ctl_reg_sys_hilo~39_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ))) - - .dataa(\z80_|execute_|setM1~36_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~39_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h0800; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( -// Equation(s): -// \z80_|execute_|fMRead~11_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~37_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'h0004; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (((\z80_|execute_|ctl_bus_inc_oe~31_combout & \z80_|execute_|fMRead~11_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datac(\z80_|execute_|fMRead~11_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h80AA; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFDFF; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~17_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~27 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[7]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~28_combout = (\z80_|reg_file_|gdfx_temp1[7]~24_combout & (\z80_|reg_file_|gdfx_temp1[7]~26_combout & (\z80_|reg_file_|gdfx_temp1[7]~25_combout & \z80_|reg_file_|gdfx_temp1[7]~27_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~27_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_32 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~29_combout = (\z80_|reg_file_|gdfx_temp1[7]~23_combout & (\z80_|reg_file_|gdfx_temp1[7]~28_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~23_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datac(\z80_|reg_file_|gdfx_temp1[7]~28_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~29 .lut_mask = 16'h80A0; -defparam \z80_|reg_file_|gdfx_temp1[7]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~30_combout = ((\z80_|reg_file_|gdfx_temp1[7]~29_combout & ((\z80_|reg_file_|db_hi_as[7]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~29_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~30 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp1[7]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_shift_oe~15_combout ) # (\z80_|execute_|ctl_alu_op_low~20_combout )))) - - .dataa(\z80_|execute_|rsel3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~16_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h3133; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_iorw~10_combout & \z80_|execute_|rsel3~combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hB030; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_sw_2d~14_combout ), - .datad(\z80_|execute_|ctl_sw_2d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hFF2A; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = (\z80_|execute_|ctl_flags_alu~19_combout & (((!\z80_|execute_|ctl_mRead~28_combout & !\z80_|execute_|ctl_mRead~22_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_mRead~28_combout ), - .datac(\z80_|execute_|ctl_flags_alu~19_combout ), - .datad(\z80_|execute_|ctl_mRead~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~6_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~7_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h7030; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (\z80_|execute_|ixy_d~15_combout & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h070F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~13_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~7_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~7_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_sw_2d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & \z80_|execute_|ctl_sw_2d~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|ctl_sw_2d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~25_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~20_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~25_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h40C0; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_flags_alu~6_combout & \z80_|execute_|ctl_flags_alu~17_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_flags_alu~6_combout ), - .datad(\z80_|execute_|ctl_flags_alu~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|execute_|ctl_mRead~20_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (((!\z80_|execute_|ctl_mRead~20_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|ctl_sw_2d~4_combout ))) - - .dataa(\z80_|execute_|fMRead~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~9_combout ), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|ctl_sw_2d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( -// Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_mRead~26_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~2_combout & \z80_|execute_|fMRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & (\z80_|execute_|ctl_sw_2d~8_combout & \z80_|execute_|fMRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datac(\z80_|execute_|ctl_sw_2d~8_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~12_combout ) # ((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~12_combout ), - .datac(\z80_|execute_|ctl_sw_2d~11_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N0 -cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( -// Equation(s): -// \z80_|alu_|db[7]~19_combout = (\z80_|alu_control_|db[7]~18_combout & (((\z80_|reg_file_|gdfx_temp1[7]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_control_|db[7]~18_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[7]~30_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[7]~18_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_alu_oe~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hCF8F; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_alu_oe~12_combout ) # ((\z80_|execute_|ctl_alu_oe~11_combout ) # (!\z80_|execute_|ctl_alu_oe~10_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_oe~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h3F00; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_reg_in_hi~7_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_mWrite~8_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mRead~22_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_alu_oe~7_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|ctl_bus_db_we~5_combout & \z80_|execute_|ctl_alu_oe~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_alu_oe~8_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~13_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_alu_oe~8_combout ), - .datad(\z80_|execute_|ctl_flags_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout -// & (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_ir_we~7_combout & (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & \z80_|execute_|ctl_flags_sz_we~0_combout -// ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~1_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal1~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal1~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op_low~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_mRead~38_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # -// (!\z80_|execute_|ctl_mRead~38_combout & (((!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~31_combout & (\z80_|execute_|ctl_alu_shift_oe~30_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h0507; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|execute_|ctl_mWrite~2_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout -// & (((!\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~5_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout & \z80_|execute_|ctl_alu_op1_sel_bus~6_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~12_combout & (\z80_|execute_|ctl_flags_xy_we~12_combout & ((!\z80_|pla_decode_|Equal48~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) # (((!\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~4_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_66_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[3]~19_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~19_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00A0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFAA; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N13 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_hl2~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~49_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~49 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~50_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout & (\z80_|reg_file_|gdfx_temp1[3]~49_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datad(\z80_|reg_file_|gdfx_temp1[3]~49_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~50 .lut_mask = 16'hC400; -defparam \z80_|reg_file_|gdfx_temp1[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~52 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~51 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~54 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[3]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~53_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[3]~14_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[3]~14_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~53 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~55_combout = (\z80_|reg_file_|gdfx_temp1[3]~52_combout & (\z80_|reg_file_|gdfx_temp1[3]~51_combout & (\z80_|reg_file_|gdfx_temp1[3]~54_combout & \z80_|reg_file_|gdfx_temp1[3]~53_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~52_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~54_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~56_combout = (\z80_|reg_file_|gdfx_temp1[3]~50_combout & (\z80_|reg_file_|gdfx_temp1[3]~55_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datab(\z80_|reg_file_|gdfx_temp1[3]~50_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~55_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~56 .lut_mask = 16'h80C0; -defparam \z80_|reg_file_|gdfx_temp1[3]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_bus_inc_oe~32_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~11_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal21~1_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'h000F; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|setM1~37_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~15_combout )))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datac(\z80_|execute_|setM1~37_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'hFF15; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_al_we~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sel_wz~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~4_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0C00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h2FFF; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~18_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # (\z80_|execute_|ctl_reg_sel_pc~17_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (\z80_|reg_control_|reg_sel_pc~2_combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h2000; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0200; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|reg_control_|reg_sel_pc~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h0F0A; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = (\z80_|execute_|ctl_reg_sel_ir~0_combout ) # (((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hCFEF; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hF777; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEEFF; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|setM1~46_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|setM1~46_combout ), - .datac(\z80_|execute_|ctl_alu_oe~5_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_flags_bus~5_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h0DDD; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~3_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|fMRead~14_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|fMRead~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|fMRead~14_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|fMRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~4_combout & (\z80_|execute_|ctl_reg_sel_wz~13_combout & (\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datac(\z80_|execute_|ctl_sw_4d~3_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_4d~0_combout ), - .datac(\z80_|execute_|ctl_sw_4d~1_combout ), - .datad(\z80_|execute_|ctl_sw_4d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hF700; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [3] & ((\z80_|reg_file_|gdfx_temp1[3]~57_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[3]~57_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|reg_control_|reg_sel_pc~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~14_combout = (\z80_|reg_file_|db_hi_as[3]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~13_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~14 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~15_combout ) +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) .dataa(gnd), .datab(gnd), .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~15_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), + .combout(\z80_|address_latch_|abusz [7]), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_ir_we~4_combout & (((!\z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_state_alu~4_combout & -// ((!\z80_|execute_|ctl_al_we~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h32FA; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~9_combout ) # (((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) - - .dataa(\z80_|execute_|ctl_al_we~9_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N20 +// Location: LCCOMB_X37_Y17_N14 cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), .combout(\z80_|execute_|ctl_apin_mux~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h3322; +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N2 +// Location: LCCOMB_X37_Y17_N26 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( // Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((!\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )) # (!\z80_|execute_|ctl_al_we~5_combout ))) - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_al_we~5_combout ), - .datad(\z80_|execute_|ctl_apin_mux~1_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|execute_|ctl_al_we~14_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hAA2A; defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y18_N4 +// Location: LCCOMB_X40_Y17_N8 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( // Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = (((!\z80_|execute_|ctl_al_we~4_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) +// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & (\z80_|execute_|ctl_ir_we~4_combout & +// ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datab(\z80_|execute_|ctl_alu_oe~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_al_we~13_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h0EEE; defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y17_N18 +// Location: LCCOMB_X40_Y17_N30 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( // Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_al_we~7_combout ) # (!\z80_|execute_|ctl_iorw~12_combout )) # (!\z80_|execute_|ctl_mRead~21_combout ))) +// \z80_|execute_|ctl_al_we~8_combout = ((\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - .dataa(\z80_|execute_|ctl_mRead~21_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ctl_iorw~12_combout ), - .datad(\z80_|execute_|ctl_al_we~7_combout ), + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_al_we~7_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBF3; defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N16 +// Location: LCCOMB_X34_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = (((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout )) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), + .datab(\z80_|execute_|ctl_al_we~4_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_al_we~9_combout ) # (!\z80_|execute_|setM1~45_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|setM1~45_combout ), + .datad(\z80_|execute_|ctl_al_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEEAE; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N0 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( // Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~10_combout ) # ((\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) +// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - .dataa(\z80_|execute_|ctl_al_we~10_combout ), - .datab(\z80_|execute_|ctl_al_we~6_combout ), + .dataa(\z80_|execute_|ctl_al_we~6_combout ), + .datab(gnd), .datac(\z80_|execute_|ctl_sw_4d~5_combout ), - .datad(\z80_|execute_|ctl_al_we~8_combout ), + .datad(\z80_|execute_|ctl_al_we~10_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFAF; defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N18 +// Location: LCCOMB_X41_Y18_N4 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( // Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = ((\z80_|execute_|ctl_al_we~11_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|setM1~52_combout ) +// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|setM1~52_combout )) - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_al_we~11_combout ), .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hEFCF; defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N5 -dffeas \z80_|address_latch_|Q[11] ( +// Location: FF_X30_Y16_N5 +dffeas \z80_|address_latch_|Q[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), + .d(\z80_|address_latch_|abusz [7]), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -17752,724 +16298,119 @@ dffeas \z80_|address_latch_|Q[11] ( .ena(\z80_|execute_|ctl_al_we~12_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), + .q(\z80_|address_latch_|Q [7]), .prn(vcc)); // synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Location: LCCOMB_X35_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) +// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - .dataa(gnd), - .datab(\z80_|address_latch_|Q [11]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h33CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Location: LCCOMB_X36_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) +// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|execute_|ctl_inc_cy~77_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_inc_cy~47_combout & \z80_|execute_|ctl_inc_cy~78_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_inc_cy~78_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|fMRead~3_combout ))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (\z80_|execute_|ctl_bus_inc_oe~39_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~48_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # (\z80_|execute_|ctl_bus_inc_oe~37_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~45_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFD55; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~46_combout ) # (\z80_|execute_|ctl_bus_inc_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = (((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~15_combout = ((\z80_|reg_file_|db_hi_as[3]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[3]~14_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~15 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_hi_as[3]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~57_combout = ((\z80_|reg_file_|gdfx_temp1[3]~56_combout & ((\z80_|reg_file_|db_hi_as[3]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~56_combout ), - .datab(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~57 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|gdfx_temp1[3]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N28 -cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( -// Equation(s): -// \z80_|alu_|db[3]~13_combout = (\z80_|alu_|db_low[3]~23_combout & (((\z80_|reg_file_|gdfx_temp1[3]~57_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_|db_low[3]~23_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & -// ((\z80_|reg_file_|gdfx_temp1[3]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_|db_low[3]~23_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|setM1~48_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h040C; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_flags_alu~16_combout & ((\z80_|alu_|db_low[3]~23_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[3]~35_combout )))) # -// (!\z80_|execute_|ctl_flags_alu~16_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[3]~35_combout )))) - - .dataa(\z80_|execute_|ctl_flags_alu~16_combout ), - .datab(\z80_|alu_|db_low[3]~23_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .combout(\z80_|execute_|fIOWrite~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFFCF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3373; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Location: LCCOMB_X36_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( // Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & \z80_|execute_|ctl_flags_sz_we~5_combout )))) # -// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_alu_core_R~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout ))) +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_inc_dec~4_combout ))) - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|execute_|ctl_inc_dec~4_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Location: LCCOMB_X36_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( // Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) +// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~0_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_inc_dec~3_combout ), + .datad(\z80_|execute_|ctl_inc_dec~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hFF4F; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF3F3; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( // Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) +// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # (((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout )) # -// (!\z80_|execute_|ctl_flags_xy_we~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_flags_xy_we~13_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~7_combout ) # (!\z80_|execute_|ctl_flags_xy_we~16_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = ((\z80_|execute_|ctl_flags_xy_we~14_combout ) # ((!\z80_|execute_|ctl_flags_pf_we~4_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y15_N19 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N28 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( -// Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( -// Equation(s): -// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_flags_|flags_xf~q ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF300; -defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~30_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|M5~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_inc_cy~30_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal48~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .lut_mask = 16'hBAAA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~35_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout & \z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~35 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~42_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~42 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h55FF; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( +// Location: FF_X31_Y17_N17 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -18478,28 +16419,1319 @@ dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Location: LCCOMB_X26_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N1 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hCA00; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h1000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2A2; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[2]~29_combout & +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|alu_control_|db[2]~29_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datac(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8CAF; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0020; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[2]~42_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N31 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[0]~12_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .datad(\z80_|alu_control_|db[0]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~16_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & \z80_|reg_file_|gdfx_temp0[0]~13_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|reg_file_|gdfx_temp0[0]~22_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; // synopsys translate_on // Location: CLKCTRL_G18 @@ -18515,25 +17747,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N6 -cycloneive_lcell_comb \ula_|video_|Add0~0 ( -// Equation(s): -// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) -// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add0~0_combout ), - .cout(\ula_|video_|Add0~1 )); -// synopsys translate_off -defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; -defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N20 +// Location: LCCOMB_X39_Y33_N16 cycloneive_lcell_comb \ula_|video_|Add0~14 ( // Equation(s): // \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) @@ -18551,50 +17765,50 @@ defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N22 +// Location: LCCOMB_X39_Y33_N18 cycloneive_lcell_comb \ula_|video_|Add0~16 ( // Equation(s): // \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) // \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [8]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~15 ), .combout(\ula_|video_|Add0~16_combout ), .cout(\ula_|video_|Add0~17 )); // synopsys translate_off -defparam \ula_|video_|Add0~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N0 +// Location: LCCOMB_X39_Y33_N26 cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( // Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) - .dataa(\ula_|video_|Add0~16_combout ), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~16_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hAA00; +defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y31_N15 +// Location: FF_X39_Y33_N27 dffeas \ula_|video_|vga_hc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~2_combout ), + .d(\ula_|video_|vga_hc~2_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18605,32 +17819,32 @@ defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N24 +// Location: LCCOMB_X39_Y33_N20 cycloneive_lcell_comb \ula_|video_|Add0~18 ( // Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|vga_hc [9] $ (\ula_|video_|Add0~17 ) +// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) .dataa(gnd), - .datab(\ula_|video_|vga_hc [9]), + .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|vga_hc [9]), .cin(\ula_|video_|Add0~17 ), .combout(\ula_|video_|Add0~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h3C3C; +defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N4 +// Location: LCCOMB_X37_Y33_N20 cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( // Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) .dataa(gnd), - .datab(\ula_|video_|Add0~18_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~18_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~1_combout ), .cout()); @@ -18639,15 +17853,15 @@ defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y31_N29 +// Location: FF_X37_Y33_N21 dffeas \ula_|video_|vga_hc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~1_combout ), + .d(\ula_|video_|vga_hc~1_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18658,58 +17872,25 @@ defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N20 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Location: LCCOMB_X39_Y33_N2 +cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [0] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) +// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) +// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - .dataa(\ula_|video_|vga_hc [2]), + .dataa(gnd), .datab(\ula_|video_|vga_hc [0]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), + .datac(gnd), + .datad(vcc), .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); + .combout(\ula_|video_|Add0~0_combout ), + .cout(\ula_|video_|Add0~1 )); // synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N14 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & (\ula_|video_|vga_hc [5] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [4]), - .datac(\ula_|video_|vga_hc [5]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h1000; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N24 -cycloneive_lcell_comb \ula_|video_|Equal1~0 ( -// Equation(s): -// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|Equal0~1_combout ), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hFF7F; -defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N6 +// Location: LCCOMB_X34_Y31_N0 cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( // Equation(s): // \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) @@ -18726,15 +17907,15 @@ defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N11 +// Location: FF_X34_Y31_N1 dffeas \ula_|video_|vga_hc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~3_combout ), + .d(\ula_|video_|vga_hc~3_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18745,7 +17926,7 @@ defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N8 +// Location: LCCOMB_X39_Y33_N4 cycloneive_lcell_comb \ula_|video_|Add0~2 ( // Equation(s): // \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) @@ -18763,15 +17944,32 @@ defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y31_N17 +// Location: LCCOMB_X36_Y33_N16 +cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( +// Equation(s): +// \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Add0~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N17 dffeas \ula_|video_|vga_hc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~2_combout ), + .d(\ula_|video_|vga_hc[1]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18782,50 +17980,33 @@ defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N10 +// Location: LCCOMB_X39_Y33_N6 cycloneive_lcell_comb \ula_|video_|Add0~4 ( // Equation(s): // \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) // \ula_|video_|Add0~5 = CARRY((\ula_|video_|vga_hc [2] & !\ula_|video_|Add0~3 )) - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~3 ), .combout(\ula_|video_|Add0~4_combout ), .cout(\ula_|video_|Add0~5 )); // synopsys translate_off -defparam \ula_|video_|Add0~4 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N22 -cycloneive_lcell_comb \ula_|video_|vga_hc[2]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[2]~feeder_combout = \ula_|video_|Add0~4_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~4_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y31_N23 +// Location: FF_X39_Y33_N23 dffeas \ula_|video_|vga_hc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[2]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|Add0~4_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18836,7 +18017,7 @@ defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N12 +// Location: LCCOMB_X39_Y33_N8 cycloneive_lcell_comb \ula_|video_|Add0~6 ( // Equation(s): // \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) @@ -18854,10 +18035,27 @@ defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N13 +// Location: LCCOMB_X36_Y33_N8 +cycloneive_lcell_comb \ula_|video_|vga_hc[3]~feeder ( +// Equation(s): +// \ula_|video_|vga_hc[3]~feeder_combout = \ula_|video_|Add0~6_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Add0~6_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vga_hc[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N9 dffeas \ula_|video_|vga_hc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add0~6_combout ), + .d(\ula_|video_|vga_hc[3]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -18873,25 +18071,25 @@ defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N14 +// Location: LCCOMB_X39_Y33_N10 cycloneive_lcell_comb \ula_|video_|Add0~8 ( // Equation(s): // \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) // \ula_|video_|Add0~9 = CARRY((\ula_|video_|vga_hc [4] & !\ula_|video_|Add0~7 )) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [4]), + .dataa(\ula_|video_|vga_hc [4]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~7 ), .combout(\ula_|video_|Add0~8_combout ), .cout(\ula_|video_|Add0~9 )); // synopsys translate_off -defparam \ula_|video_|Add0~8 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N3 +// Location: FF_X39_Y33_N31 dffeas \ula_|video_|vga_hc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18910,7 +18108,58 @@ defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N16 +// Location: LCCOMB_X34_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N30 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( +// Equation(s): +// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) + + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|vga_hc [4]), + .datad(\ula_|video_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0200; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y33_N16 +cycloneive_lcell_comb \ula_|video_|Equal1~0 ( +// Equation(s): +// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; +defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N12 cycloneive_lcell_comb \ula_|video_|Add0~10 ( // Equation(s): // \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) @@ -18928,32 +18177,32 @@ defparam \ula_|video_|Add0~10 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N26 +// Location: LCCOMB_X39_Y33_N0 cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( // Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) - .dataa(\ula_|video_|Add0~10_combout ), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~10_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hAA00; +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y31_N1 +// Location: FF_X39_Y33_N1 dffeas \ula_|video_|vga_hc[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~0_combout ), + .d(\ula_|video_|vga_hc~0_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18964,7 +18213,7 @@ defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N18 +// Location: LCCOMB_X39_Y33_N14 cycloneive_lcell_comb \ula_|video_|Add0~12 ( // Equation(s): // \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) @@ -18982,7 +18231,7 @@ defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N5 +// Location: FF_X39_Y33_N29 dffeas \ula_|video_|vga_hc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -19001,7 +18250,7 @@ defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X31_Y31_N27 +// Location: FF_X39_Y33_N25 dffeas \ula_|video_|vga_hc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -19020,61 +18269,25 @@ defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N2 +// Location: LCCOMB_X35_Y33_N0 cycloneive_lcell_comb \ula_|video_|Add1~0 ( // Equation(s): // \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) // \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) - .dataa(\ula_|video_|vga_vc [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [0]), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\ula_|video_|Add1~0_combout ), .cout(\ula_|video_|Add1~1 )); // synopsys translate_off -defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; +defparam \ula_|video_|Add1~0 .lut_mask = 16'h33CC; defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N8 -cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( -// Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [0])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~0_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Add1~0_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y31_N9 -dffeas \ula_|video_|vga_vc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[0]~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N4 +// Location: LCCOMB_X35_Y33_N2 cycloneive_lcell_comb \ula_|video_|Add1~2 ( // Equation(s): // \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) @@ -19092,42 +18305,42 @@ defparam \ula_|video_|Add1~2 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N6 +// Location: LCCOMB_X35_Y33_N4 cycloneive_lcell_comb \ula_|video_|Add1~4 ( // Equation(s): // \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) // \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), + .dataa(\ula_|video_|vga_vc [2]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~3 ), .combout(\ula_|video_|Add1~4_combout ), .cout(\ula_|video_|Add1~5 )); // synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N24 +// Location: LCCOMB_X38_Y33_N12 cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( // Equation(s): // \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), .datab(\ula_|video_|Add1~4_combout ), .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N25 +// Location: FF_X38_Y33_N13 dffeas \ula_|video_|vga_vc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[2]~2_combout ), @@ -19146,7 +18359,7 @@ defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N8 +// Location: LCCOMB_X35_Y33_N6 cycloneive_lcell_comb \ula_|video_|Add1~6 ( // Equation(s): // \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) @@ -19164,7 +18377,7 @@ defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N2 +// Location: LCCOMB_X35_Y33_N20 cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( // Equation(s): // \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) @@ -19181,15 +18394,15 @@ defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h5140; defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N3 +// Location: FF_X38_Y33_N3 dffeas \ula_|video_|vga_vc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[3]~3_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|vga_vc[3]~3_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -19200,42 +18413,42 @@ defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N10 +// Location: LCCOMB_X35_Y33_N8 cycloneive_lcell_comb \ula_|video_|Add1~8 ( // Equation(s): // \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) // \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - .dataa(\ula_|video_|vga_vc [4]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~7 ), .combout(\ula_|video_|Add1~8_combout ), .cout(\ula_|video_|Add1~9 )); // synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N20 +// Location: LCCOMB_X38_Y33_N20 cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( // Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [4])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~8_combout ))))) +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~8_combout ), .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Add1~8_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[4]~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N21 +// Location: FF_X38_Y33_N21 dffeas \ula_|video_|vga_vc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[4]~5_combout ), @@ -19254,50 +18467,50 @@ defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N12 +// Location: LCCOMB_X35_Y33_N10 cycloneive_lcell_comb \ula_|video_|Add1~10 ( // Equation(s): // \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) // \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~9 ), .combout(\ula_|video_|Add1~10_combout ), .cout(\ula_|video_|Add1~11 )); // synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N0 +// Location: LCCOMB_X35_Y33_N22 cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( // Equation(s): // \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|vga_vc [5]), .datad(\ula_|video_|Add1~10_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[5]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5140; defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N1 +// Location: FF_X38_Y33_N17 dffeas \ula_|video_|vga_vc[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[5]~8_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|vga_vc[5]~8_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -19308,42 +18521,42 @@ defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N14 +// Location: LCCOMB_X35_Y33_N12 cycloneive_lcell_comb \ula_|video_|Add1~12 ( // Equation(s): // \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) // \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~11 ), .combout(\ula_|video_|Add1~12_combout ), .cout(\ula_|video_|Add1~13 )); // synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N6 +// Location: LCCOMB_X38_Y33_N6 cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( // Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [6])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~12_combout ))))) +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~12_combout ), .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Add1~12_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[6]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N7 +// Location: FF_X38_Y33_N7 dffeas \ula_|video_|vga_vc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[6]~4_combout ), @@ -19362,42 +18575,42 @@ defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N16 +// Location: LCCOMB_X35_Y33_N14 cycloneive_lcell_comb \ula_|video_|Add1~14 ( // Equation(s): // \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) // \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) - .dataa(\ula_|video_|vga_vc [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~13 ), .combout(\ula_|video_|Add1~14_combout ), .cout(\ula_|video_|Add1~15 )); // synopsys translate_off -defparam \ula_|video_|Add1~14 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N22 +// Location: LCCOMB_X38_Y33_N14 cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( // Equation(s): // \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), .datab(\ula_|video_|Add1~14_combout ), .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[7]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N23 +// Location: FF_X38_Y33_N15 dffeas \ula_|video_|vga_vc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[7]~6_combout ), @@ -19416,7 +18629,7 @@ defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N18 +// Location: LCCOMB_X35_Y33_N16 cycloneive_lcell_comb \ula_|video_|Add1~16 ( // Equation(s): // \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) @@ -19434,24 +18647,24 @@ defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N0 +// Location: LCCOMB_X38_Y33_N24 cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( // Equation(s): -// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [8])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~16_combout ))))) +// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~16_combout ), .datac(\ula_|video_|vga_vc [8]), - .datad(\ula_|video_|Add1~16_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[8]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N1 +// Location: FF_X38_Y33_N25 dffeas \ula_|video_|vga_vc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[8]~7_combout ), @@ -19470,24 +18683,7 @@ defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N10 -cycloneive_lcell_comb \ula_|video_|Equal2~0 ( -// Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N20 +// Location: LCCOMB_X35_Y33_N18 cycloneive_lcell_comb \ula_|video_|Add1~18 ( // Equation(s): // \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) @@ -19504,24 +18700,24 @@ defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N28 +// Location: LCCOMB_X38_Y33_N10 cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( // Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [9])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~18_combout ))))) +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~18_combout ), .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Add1~18_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[9]~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N29 +// Location: FF_X38_Y33_N11 dffeas \ula_|video_|vga_vc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[9]~9_combout ), @@ -19540,58 +18736,111 @@ defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N26 +// Location: LCCOMB_X38_Y33_N18 +cycloneive_lcell_comb \ula_|video_|Equal2~0 ( +// Equation(s): +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(\ula_|video_|vga_vc [4]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [8]), + .cin(gnd), + .combout(\ula_|video_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N30 cycloneive_lcell_comb \ula_|video_|Equal3~0 ( // Equation(s): -// \ula_|video_|Equal3~0_combout = (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [2] & \ula_|video_|vga_vc [3]))) +// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0]))) - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [0]), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|vga_vc [3]), + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|vga_vc [0]), .cin(gnd), .combout(\ula_|video_|Equal3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h4000; +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0800; defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N16 +// Location: LCCOMB_X37_Y33_N18 cycloneive_lcell_comb \ula_|video_|Equal3~1 ( // Equation(s): -// \ula_|video_|Equal3~1_combout = (\ula_|video_|Equal2~0_combout & (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & \ula_|video_|Equal3~0_combout ))) +// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal2~0_combout & \ula_|video_|Equal3~0_combout ))) - .dataa(\ula_|video_|Equal2~0_combout ), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [9]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|Equal2~0_combout ), .datad(\ula_|video_|Equal3~0_combout ), .cin(gnd), .combout(\ula_|video_|Equal3~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal3~1 .lut_mask = 16'h2000; +defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N30 +// Location: LCCOMB_X38_Y33_N28 +cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( +// Equation(s): +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~0_combout ), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y33_N29 +dffeas \ula_|video_|vga_vc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N22 cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( // Equation(s): // \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), .datab(\ula_|video_|Add1~2_combout ), .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N31 +// Location: FF_X38_Y33_N23 dffeas \ula_|video_|vga_vc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[1]~1_combout ), @@ -19620,14 +18869,14 @@ defparam \SW[1]~input .bus_hold = "false"; defparam \SW[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N16 +// Location: LCCOMB_X34_Y33_N30 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & (!\ula_|video_|vga_hc [8] & !\ula_|video_|vga_hc [9]))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & !\ula_|video_|vga_hc [9]))) - .dataa(\ula_|video_|vga_vc [1]), - .datab(\SW[1]~input_o ), - .datac(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [8]), + .datab(\ula_|video_|vga_vc [1]), + .datac(\SW[1]~input_o ), .datad(\ula_|video_|vga_hc [9]), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), @@ -19637,15 +18886,15 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N0 +// Location: LCCOMB_X35_Y17_N30 cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( // Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [5]), + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), .combout(\z80_|pla_decode_|Equal79~0_combout ), .cout()); @@ -19654,34 +18903,16 @@ defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N26 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( -// Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )) - - .dataa(\z80_|interrupts_|iff1~q ), - .datab(\z80_|pla_decode_|Equal79~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hE2AA; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N16 +// Location: LCCOMB_X35_Y17_N16 cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( // Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|DFFE_instIFF2~q +// ))))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal79~0_combout ), .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .cin(gnd), .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), .cout()); @@ -19690,24 +18921,24 @@ defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N24 +// Location: LCCOMB_X32_Y15_N28 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( // Equation(s): // \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h5F0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h7733; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: CLKCTRL_G8 +// Location: CLKCTRL_G16 cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), @@ -19720,7 +18951,7 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clo defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X46_Y10_N17 +// Location: FF_X35_Y17_N17 dffeas \z80_|interrupts_|DFFE_instIFF2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), @@ -19739,42 +18970,60 @@ defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N10 +// Location: LCCOMB_X35_Y17_N2 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|interrupts_|iff1~q ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hEC4C; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N18 cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( // Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )) +// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|iff1~0_combout ))))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|interrupts_|iff1~0_combout )))) - .dataa(\z80_|interrupts_|iff1~0_combout ), + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|interrupts_|iff1~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|iff1~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hCAAA; +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hDF80; defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N6 +// Location: LCCOMB_X38_Y18_N12 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFAF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X46_Y10_N11 +// Location: FF_X35_Y17_N19 dffeas \z80_|interrupts_|iff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|iff1~1_combout ), @@ -19793,15 +19042,15 @@ defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; defparam \z80_|interrupts_|iff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N22 +// Location: LCCOMB_X37_Y33_N4 cycloneive_lcell_comb \ula_|video_|Equal2~1 ( // Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [3]))) +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [0]))) - .dataa(\ula_|video_|vga_vc [2]), - .datab(\ula_|video_|vga_vc [0]), + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|vga_vc [2]), .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [0]), .cin(gnd), .combout(\ula_|video_|Equal2~1_combout ), .cout()); @@ -19810,24 +19059,24 @@ defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N12 +// Location: LCCOMB_X37_Y33_N14 cycloneive_lcell_comb \ula_|video_|Equal2~2 ( // Equation(s): -// \ula_|video_|Equal2~2_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~1_combout & \ula_|video_|Equal2~0_combout )) +// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (\ula_|video_|Equal2~0_combout & !\ula_|video_|vga_vc [5])) .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|Equal2~1_combout ), - .datad(\ula_|video_|Equal2~0_combout ), + .datab(\ula_|video_|Equal2~1_combout ), + .datac(\ula_|video_|Equal2~0_combout ), + .datad(\ula_|video_|vga_vc [5]), .cin(gnd), .combout(\ula_|video_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h3000; +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h00C0; defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y20_N20 +// Location: LCCOMB_X35_Y31_N28 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( // Equation(s): // \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (\z80_|interrupts_|iff1~q & \ula_|video_|Equal2~2_combout ))) @@ -19844,7 +19093,7 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y20_N21 +// Location: FF_X35_Y31_N29 dffeas \z80_|interrupts_|int_armed ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), @@ -19863,32 +19112,15 @@ defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; defparam \z80_|interrupts_|int_armed .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N28 -cycloneive_lcell_comb \z80_|interrupts_|DFFE_inst44~feeder ( -// Equation(s): -// \z80_|interrupts_|DFFE_inst44~feeder_combout = \z80_|interrupts_|int_armed~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|interrupts_|int_armed~q ), - .cin(gnd), - .combout(\z80_|interrupts_|DFFE_inst44~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_inst44~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|DFFE_inst44~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X50_Y12_N29 +// Location: FF_X32_Y15_N11 dffeas \z80_|interrupts_|DFFE_inst44 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|DFFE_inst44~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|interrupts_|int_armed~q ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|interrupts_|test1~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -19899,127 +19131,163 @@ defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Location: LCCOMB_X32_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) +// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datab(gnd), .datac(\z80_|decode_state_|in_halt~q ), - .datad(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .combout(\z80_|execute_|pc_inc_hold~38_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Location: LCCOMB_X35_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~6_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~7_combout ) +// \z80_|execute_|ctl_inc_cy~91_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .combout(\z80_|execute_|ctl_inc_cy~91_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Location: LCCOMB_X35_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~45 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|pc_inc_hold~40_combout ))) +// \z80_|execute_|pc_inc_hold~45_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & +// (((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|pc_inc_hold~40_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .combout(\z80_|execute_|pc_inc_hold~45_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~45 .lut_mask = 16'hF888; +defparam \z80_|execute_|pc_inc_hold~45 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Location: LCCOMB_X35_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~44 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (((\z80_|execute_|ctl_alu_op_low~14_combout & -// \z80_|execute_|ctl_mRead~38_combout )))) +// \z80_|execute_|pc_inc_hold~44_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~49_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~44 .lut_mask = 16'h8CCC; +defparam \z80_|execute_|pc_inc_hold~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~46 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~46_combout = (\z80_|execute_|pc_inc_hold~45_combout ) # ((\z80_|execute_|pc_inc_hold~44_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~49_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~45_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|pc_inc_hold~44_combout ), + .datad(\z80_|execute_|pc_inc_hold~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~46 .lut_mask = 16'hFAFE; +defparam \z80_|execute_|pc_inc_hold~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & +// (\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), + .datab(\z80_|pla_decode_|Equal52~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), + .combout(\z80_|execute_|pc_inc_hold~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hF8A8; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Location: LCCOMB_X35_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~50 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = (((\z80_|execute_|ctl_inc_cy~49_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~11_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ) +// \z80_|execute_|pc_inc_hold~50_combout = (\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datad(\z80_|execute_|ctl_inc_cy~49_combout ), + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|pc_inc_hold~37_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .combout(\z80_|execute_|pc_inc_hold~50_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~50 .lut_mask = 16'hECCC; +defparam \z80_|execute_|pc_inc_hold~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Location: LCCOMB_X36_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_inc_cy~51_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout )) +// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_mRead~10_combout & (((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal6~1_combout & +// ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) - .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), - .datab(\z80_|execute_|ctl_inc_cy~50_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .combout(\z80_|execute_|pc_inc_hold~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Location: LCCOMB_X36_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = (\z80_|execute_|ctl_inc_cy~52_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # (!\z80_|execute_|fMRead~11_combout )))) +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~52_combout ), - .datac(\z80_|execute_|fMRead~11_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hEFCC; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N8 +// Location: LCCOMB_X34_Y17_N26 cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( // Equation(s): // \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~2_combout ))) @@ -20036,4853 +19304,1086 @@ defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|pc_inc_hold~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datad(\z80_|execute_|pc_inc_hold~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hF8FC; -defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~24_combout = (\z80_|execute_|ixy_d~4_combout & (((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) # (!\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & -// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ixy_d~4_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (((\z80_|execute_|ctl_mRead~17_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ixy_d~4_combout & -// (\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hECE0; -defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~25_combout = (\z80_|execute_|pc_inc_hold~22_combout ) # ((\z80_|execute_|pc_inc_hold~24_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # (\z80_|execute_|pc_inc_hold~23_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~22_combout ), - .datab(\z80_|execute_|pc_inc_hold~24_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datad(\z80_|execute_|pc_inc_hold~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~20_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal25~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFF37; -defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~10_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hA080; -defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~21_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~19_combout ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'h37FF; -defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~26_combout = (!\z80_|execute_|pc_inc_hold~25_combout & (\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|pc_inc_hold~21_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(\z80_|execute_|pc_inc_hold~20_combout ), - .datac(\z80_|execute_|pc_inc_hold~41_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'h0400; -defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & -// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|execute_|ctl_inc_cy~44_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~13_combout )) # (!\z80_|execute_|ctl_inc_cy~87_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ctl_inc_cy~45_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~43_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~85_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'hBBB3; -defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~43_combout ) # (!\z80_|execute_|ctl_inc_cy~47_combout ))) # (!\z80_|execute_|ctl_inc_cy~33_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~33_combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~47_combout ), - .datad(\z80_|execute_|ctl_inc_cy~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|execute_|pc_inc_hold~30_combout & (((\z80_|execute_|pc_inc_hold~26_combout & \z80_|execute_|ctl_inc_cy~48_combout )))) # (!\z80_|execute_|pc_inc_hold~30_combout & ((\z80_|execute_|ctl_inc_cy~54_combout ) # -// ((\z80_|execute_|ctl_inc_cy~48_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~30_combout ), - .datab(\z80_|execute_|ctl_inc_cy~54_combout ), - .datac(\z80_|execute_|pc_inc_hold~26_combout ), - .datad(\z80_|execute_|ctl_inc_cy~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hF544; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ixy_d~10_combout & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~42_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hA800; -defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|pc_inc_hold~19_combout & \z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout & -// (\z80_|execute_|pc_inc_hold~19_combout & (\z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|pc_inc_hold~19_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|execute_|pc_inc_hold~27_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|pc_inc_hold~27_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|pc_inc_hold~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .datab(\z80_|execute_|pc_inc_hold~26_combout ), - .datac(\z80_|execute_|pc_inc_hold~42_combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'h0004; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout & (((\z80_|execute_|ctl_inc_cy~39_combout & \z80_|execute_|pc_inc_hold~29_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'hB030; -defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|pc_inc_hold~42_combout & (\z80_|execute_|pc_inc_hold~26_combout & (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout & !\z80_|execute_|pc_inc_hold~28_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~42_combout ), - .datab(\z80_|execute_|pc_inc_hold~26_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|execute_|ctl_inc_cy~41_combout ) # ((\z80_|execute_|ctl_inc_cy~83_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # (!\z80_|execute_|pc_inc_hold~30_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~41_combout ), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|ctl_inc_cy~83_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hFABA; -defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (!\z80_|decode_state_|in_halt~q & \z80_|execute_|ctl_mRead~16_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~62_combout ) # ((!\z80_|execute_|pc_inc_hold~22_combout & !\z80_|execute_|ctl_reg_sys_hilo~24_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~22_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~62_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'hC0C4; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N20 +// Location: LCCOMB_X36_Y19_N26 cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~23_combout ) # ((\z80_|execute_|pc_inc_hold~22_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ixy_d~4_combout ))) +// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout )))) - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|pc_inc_hold~23_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|pc_inc_hold~22_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|pc_inc_hold~28_combout ), .cin(gnd), .combout(\z80_|execute_|pc_inc_hold~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hECEE; defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|pc_inc_hold~31_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~63_combout ), - .datad(\z80_|execute_|pc_inc_hold~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'hF0F8; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal33~1_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = ((!\z80_|execute_|pc_inc_hold~22_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout & \z80_|execute_|ctl_inc_cy~58_combout ))) # (!\z80_|execute_|pc_inc_hold~30_combout ) - - .dataa(\z80_|execute_|pc_inc_hold~22_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_inc_cy~58_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'h1F0F; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~12_combout ) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|execute_|pc_inc_hold~25_combout & (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_inc_cy~59_combout ))) # (!\z80_|execute_|pc_inc_hold~25_combout & -// (((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & \z80_|execute_|ctl_inc_cy~59_combout )) # (!\z80_|execute_|ctl_inc_cy~60_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_inc_cy~59_combout ), - .datad(\z80_|execute_|ctl_inc_cy~60_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'hC0D5; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N8 +// Location: LCCOMB_X36_Y19_N12 cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|pc_inc_hold~25_combout ) # ((\z80_|execute_|pc_inc_hold~41_combout ) # (!\z80_|execute_|pc_inc_hold~20_combout )) +// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|execute_|ctl_mRead~15_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(gnd), - .datac(\z80_|execute_|pc_inc_hold~41_combout ), - .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), .cin(gnd), .combout(\z80_|execute_|pc_inc_hold~32_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hFAFF; +defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hEEA0; defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N2 +// Location: LCCOMB_X36_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~31_combout ) # (\z80_|execute_|pc_inc_hold~32_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~33_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~31_combout ), + .datad(\z80_|execute_|pc_inc_hold~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~51 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~51_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~51 .lut_mask = 16'h57FF; +defparam \z80_|execute_|pc_inc_hold~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~52 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~52_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~52 .lut_mask = 16'hA800; +defparam \z80_|execute_|pc_inc_hold~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~35_combout = (!\z80_|execute_|pc_inc_hold~34_combout & (\z80_|execute_|pc_inc_hold~51_combout & (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~52_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~34_combout ), + .datab(\z80_|execute_|pc_inc_hold~51_combout ), + .datac(\z80_|execute_|pc_inc_hold~30_combout ), + .datad(\z80_|execute_|pc_inc_hold~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'h0040; +defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|pc_inc_hold~35_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hCF8F; +defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~10_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_inc_cy~44_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~50_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|ctl_inc_cy~44_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~43 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~43_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~43 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~91_combout & (!\z80_|execute_|pc_inc_hold~46_combout & (\z80_|execute_|ctl_inc_cy~45_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), + .datab(\z80_|execute_|pc_inc_hold~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~45_combout ), + .datad(\z80_|execute_|pc_inc_hold~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~72_combout & \z80_|execute_|ctl_inc_cy~71_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_inc_cy~72_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~71_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_mWrite~16_combout & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h8C00; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~53 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~53_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~53 .lut_mask = 16'hE000; +defparam \z80_|execute_|pc_inc_hold~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~39_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~53_combout & (\z80_|execute_|pc_inc_hold~35_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~50_combout ), + .datab(\z80_|execute_|pc_inc_hold~53_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'h0010; +defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~47 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~47_combout = (\z80_|execute_|pc_inc_hold~46_combout ) # ((\z80_|execute_|pc_inc_hold~43_combout ) # ((!\z80_|execute_|ctl_inc_cy~44_combout ) # (!\z80_|execute_|pc_inc_hold~39_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~46_combout ), + .datab(\z80_|execute_|pc_inc_hold~43_combout ), + .datac(\z80_|execute_|pc_inc_hold~39_combout ), + .datad(\z80_|execute_|ctl_inc_cy~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~47 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|pc_inc_hold~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~34_combout )) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~43_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~43_combout ), + .datab(\z80_|execute_|ctl_inc_cy~35_combout ), + .datac(\z80_|execute_|ctl_inc_cy~34_combout ), + .datad(\z80_|execute_|ctl_inc_cy~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = ((\z80_|execute_|ctl_inc_cy~74_combout ) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~39_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~39_combout ), + .datac(\z80_|execute_|ctl_inc_cy~77_combout ), + .datad(\z80_|execute_|ctl_inc_cy~74_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|pc_inc_hold~47_combout & \z80_|execute_|ctl_inc_cy~91_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~47_combout ), + .datab(\z80_|execute_|ctl_inc_cy~78_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~91_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h4C0C; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|pc_inc_hold~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal19~1_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|pla_decode_|Equal19~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hA800; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|ctl_inc_cy~81_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|pc_inc_hold~47_combout & (!\z80_|execute_|pc_inc_hold~38_combout & ((\z80_|execute_|ctl_inc_cy~82_combout ) # (!\z80_|execute_|ctl_inc_cy~38_combout )))) # (!\z80_|execute_|pc_inc_hold~47_combout +// & ((\z80_|execute_|ctl_inc_cy~82_combout ) # ((!\z80_|execute_|ctl_inc_cy~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~47_combout ), + .datab(\z80_|execute_|ctl_inc_cy~82_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h4C5F; +defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N26 cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout )) - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ctl_inc_cy~80_combout ), + .datad(\z80_|execute_|ctl_inc_cy~83_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_inc_cy~84_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hFFFC; defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Location: LCCOMB_X37_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~64_combout ) # ((\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|pc_inc_hold~32_combout & !\z80_|execute_|ctl_inc_cy~84_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), - .datab(\z80_|execute_|ctl_inc_cy~61_combout ), - .datac(\z80_|execute_|pc_inc_hold~32_combout ), - .datad(\z80_|execute_|ctl_inc_cy~84_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = ((!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h575F; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = (!\z80_|execute_|ctl_inc_cy~56_combout & (!\z80_|execute_|pc_inc_hold~42_combout & \z80_|execute_|pc_inc_hold~26_combout )) +// \z80_|execute_|pc_inc_hold~42_combout = ((\z80_|execute_|pc_inc_hold~34_combout ) # (\z80_|execute_|pc_inc_hold~52_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ) .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~56_combout ), - .datac(\z80_|execute_|pc_inc_hold~42_combout ), - .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .datab(\z80_|execute_|pc_inc_hold~30_combout ), + .datac(\z80_|execute_|pc_inc_hold~34_combout ), + .datad(\z80_|execute_|pc_inc_hold~52_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .combout(\z80_|execute_|pc_inc_hold~42_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'h0300; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( +// Location: LCCOMB_X37_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|pc_inc_hold~30_combout & ((\z80_|execute_|pc_inc_hold~25_combout ) # (!\z80_|execute_|pc_inc_hold~20_combout ))) +// \z80_|execute_|ctl_inc_cy~90_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(gnd), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), + .combout(\z80_|execute_|ctl_inc_cy~90_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hA0F0; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N2 +// Location: LCCOMB_X36_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~31_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|pc_inc_hold~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N18 cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = (\z80_|execute_|ctl_inc_cy~65_combout ) # ((\z80_|execute_|ctl_inc_cy~57_combout ) # ((!\z80_|execute_|pc_inc_hold~33_combout & !\z80_|execute_|ctl_inc_cy~38_combout ))) +// \z80_|execute_|ctl_inc_cy~66_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q ))) - .dataa(\z80_|execute_|ctl_inc_cy~65_combout ), - .datab(\z80_|execute_|ctl_inc_cy~57_combout ), - .datac(\z80_|execute_|pc_inc_hold~33_combout ), - .datad(\z80_|execute_|ctl_inc_cy~38_combout ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), .combout(\z80_|execute_|ctl_inc_cy~66_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hEEEF; +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h0004; defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N20 +// Location: LCCOMB_X36_Y19_N4 cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~40_combout ) # ((\z80_|execute_|ctl_inc_cy~42_combout ) # (\z80_|execute_|ctl_inc_cy~66_combout ))) +// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & !\z80_|execute_|pc_inc_hold~31_combout )))) - .dataa(\z80_|execute_|ctl_inc_cy~55_combout ), - .datab(\z80_|execute_|ctl_inc_cy~40_combout ), - .datac(\z80_|execute_|ctl_inc_cy~42_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datac(\z80_|execute_|pc_inc_hold~31_combout ), .datad(\z80_|execute_|ctl_inc_cy~66_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_inc_cy~67_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hAA02; defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Location: LCCOMB_X36_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = (((!\z80_|execute_|ctl_inc_cy~37_combout ) # (!\z80_|execute_|ctl_inc_cy~31_combout )) # (!\z80_|execute_|ctl_inc_cy~36_combout )) # (!\z80_|execute_|ctl_inc_cy~30_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~30_combout ), - .datab(\z80_|execute_|ctl_inc_cy~36_combout ), - .datac(\z80_|execute_|ctl_inc_cy~31_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~75_combout ) # ((!\z80_|execute_|ctl_inc_cy~35_combout ) # (!\z80_|execute_|ctl_inc_cy~78_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_inc_cy~78_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'hBBFF; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = ((\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_inc_cy~72_combout & \z80_|pla_decode_|Equal19~1_combout ))) # (!\z80_|execute_|ctl_inc_cy~34_combout ) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_inc_cy~34_combout ), - .datac(\z80_|execute_|ctl_inc_cy~72_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'hB333; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|ctl_mRead~15_combout ))) .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|pc_inc_hold~41_combout ), + .datac(\z80_|execute_|ctl_inc_cy~67_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Location: LCCOMB_X36_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & (!\z80_|execute_|pc_inc_hold~34_combout & \z80_|execute_|pc_inc_hold~29_combout ))) +// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~31_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~73_combout & ((!\z80_|execute_|pc_inc_hold~30_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_inc_cy~73_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'hFF4C; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~74_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout & ((\z80_|execute_|ctl_inc_cy~68_combout ) # (!\z80_|execute_|pc_inc_hold~30_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~68_combout ), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_inc_cy~74_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hFF8C; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = (!\z80_|execute_|ctl_inc_dec~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'h5F5F; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .lut_mask = 16'h2F00; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~53_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_flags_oe~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~53 .lut_mask = 16'h050D; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .lut_mask = 16'hECFC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal25~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~54 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~54_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~54 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~27_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ), - .datac(\z80_|execute_|ctl_mRead~27_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~20_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~20 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # (((\z80_|execute_|ctl_ir_we~15_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo~24_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout = (\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & ((\z80_|execute_|rsel0~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// (((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|rsel0~combout )) # (!\z80_|execute_|setM1~48_combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|execute_|rsel0~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .lut_mask = 16'hCD05; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~47 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) # (!\z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .datac(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = (\z80_|pla_decode_|Equal40~1_combout & (((\z80_|execute_|ixy_d~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal40~1_combout & (\z80_|pla_decode_|Equal39~0_combout & -// ((\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFAC0; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0A00; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hA8A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout )) # (!\z80_|execute_|ctl_alu_op_low~21_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ixy_d~4_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|execute_|ctl_mRead~38_combout )))) # (!\z80_|execute_|ixy_d~4_combout & (((\z80_|execute_|ctl_eval_cond~0_combout & -// \z80_|execute_|ctl_mRead~38_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFC88; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h55F7; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~23_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal44~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_state_alu~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel~5_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hFF0F; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~17_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~17_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~39_combout = (((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~18_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'h7F77; -defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op_low~39_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout & ((\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'hF0E0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal56~0_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~38_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~38_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h0777; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~10_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h0155; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hEEEC; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_flags_cf_cpl~2_combout & ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hEF00; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mWrite~2_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout & -// (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (!\z80_|execute_|ctl_flags_cf_cpl~3_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h0200; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_alu_op_low~30_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC800; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = ((\z80_|execute_|ctl_reg_gp_sel~5_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal72~2_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~11_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal72~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|pla_decode_|Equal61~2_combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal61~2_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~11_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal21~0_combout ) # ((\z80_|pla_decode_|Equal3~0_combout )))) # (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_eval_cond~0_combout & -// ((\z80_|pla_decode_|Equal21~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .lut_mask = 16'hFAC8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout -// ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .lut_mask = 16'hFFF8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (\z80_|execute_|ctl_alu_op_low~36_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~36_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'h4000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (!\z80_|pla_decode_|Equal72~2_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal72~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & \z80_|execute_|ctl_flags_nf_we~1_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~38_combout = (\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'h8880; -defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|execute_|ctl_alu_op_low~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~38_combout ) # (\z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_alu_op_low~32_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|pla_decode_|Equal64~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h00C4; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|pla_decode_|Equal20~0_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (\z80_|execute_|ctl_flags_use_cf2~9_combout ))) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|execute_|ctl_flags_bus~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hBAFA; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_mRead~38_combout & \z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|pc_inc_hold~31_combout ), .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Location: LCCOMB_X37_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = (((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (\z80_|execute_|ctl_flags_cf_we~5_combout )) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (((\z80_|ir_|opcode [3]) # (!\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'hF700; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|execute_|ctl_alu_core_R~2_combout ) # ((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|execute_|ctl_alu_op_low~25_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # (((\z80_|execute_|ctl_alu_op_low~33_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout )) # (!\z80_|execute_|ctl_alu_op_low~39_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~34_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hCC40; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hA0A8; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h54F0; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~18_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h5C4C; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~19_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h5F08; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_mWrite~2_combout ) # (\z80_|execute_|ctl_alu_shift_oe~20_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~20_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h5F40; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~21_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout -// & ((\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hEEC0; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_ir_we~7_combout )))) # (!\z80_|execute_|ctl_bus_db_oe~7_combout & ((\z80_|execute_|ixy_d~7_combout ) -// # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'hDC50; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_alu_shift_oe~24_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~44_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ) # (\z80_|execute_|ctl_alu_shift_oe~16_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0F0E; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~23_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF45; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hC4C0; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) +// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|pc_inc_hold~34_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_sw_4u~0_combout )))) .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|pc_inc_hold~34_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0C08; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Location: LCCOMB_X37_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( // Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~22_combout ) # (\z80_|execute_|ctl_mRead~28_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) +// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_inc_cy~64_combout ), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hFFC4; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_inc_cy~68_combout ) # ((\z80_|execute_|ctl_inc_cy~65_combout ) # ((!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|ctl_inc_cy~90_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~42_combout ), + .datab(\z80_|execute_|ctl_inc_cy~90_combout ), + .datac(\z80_|execute_|ctl_inc_cy~68_combout ), + .datad(\z80_|execute_|ctl_inc_cy~65_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~49_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_inc_cy~92_combout ) .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|execute_|ctl_mRead~28_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_inc_cy~92_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Location: LCCOMB_X35_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( // Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) +// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ixy_d~9_combout & +// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h5F40; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_flags_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~22_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~42_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hB0A0; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( -// Equation(s): -// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .dataa(\z80_|execute_|ixy_d~9_combout ), .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Location: LCCOMB_X36_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~2_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~10_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_ir_we~10_combout ))) +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_inc_cy~94_combout )) - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|execute_|ctl_inc_cy~94_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Location: LCCOMB_X35_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) +// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|pla_decode_|Equal11~0_combout ))) - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~51_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Location: LCCOMB_X36_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( // Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_mWrite~3_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) +// \z80_|execute_|ctl_inc_cy~36_combout = ((!\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .combout(\z80_|execute_|ctl_inc_cy~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_alu_res_oe~1_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( -// Equation(s): -// \z80_|alu_|db_high[3]~1_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # ((\z80_|alu_|db_high[3]~0_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~0_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFEFF; -defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~2 ( -// Equation(s): -// \z80_|alu_|db_low[3]~2_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [3]), - .datac(\z80_|alu_|op2_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~2 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db_low[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hC0C0; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N26 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~3 ( -// Equation(s): -// \z80_|alu_|db_low[3]~3_combout = (\z80_|alu_|db_low[3]~2_combout & (((!\z80_|bus_control_|db[5]~17_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|alu_|db_low[3]~2_combout ), - .datab(\z80_|bus_control_|db[5]~17_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~3 .lut_mask = 16'h2A0A; -defparam \z80_|alu_|db_low[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y16_N13 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( -// Equation(s): -// \z80_|alu_|db_low[3]~4_combout = (\z80_|alu_|db_low[3]~3_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|alu_|db_low[3]~3_combout ), - .datab(\z80_|alu_|result_lo [3]), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hAA88; -defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (((\z80_|alu_|db_low[3]~1_combout & \z80_|alu_|db_low[3]~4_combout )) # (!\z80_|alu_|db_high[3]~1_combout ))) - - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .lut_mask = 16'hB030; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|alu_|db_high[3]~19_combout ), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .lut_mask = 16'h00F8; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_low~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N29 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[3]~3_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|alu_|alu_op2[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFCD; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = ((!\z80_|execute_|ctl_alu_core_S~11_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h3FFF; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|pla_decode_|Equal62~2_combout & \z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFBBB; -defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ) # (\z80_|execute_|ctl_alu_core_S~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~25 ( -// Equation(s): -// \z80_|alu_|db_high[2]~25_combout = (\z80_|alu_|db_high[2]~24_combout ) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_high[3]~1_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|alu_|db_high[2]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~25 .lut_mask = 16'hFF55; -defparam \z80_|alu_|db_high[2]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [6] & ((\z80_|reg_file_|gdfx_temp1[6]~21_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[6]~21_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~0 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|db_hi_as[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~1_combout = (\z80_|reg_file_|db_hi_as[6]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[6]~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~1 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|db_hi_as[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N29 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [14]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [13]))))) - - .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~3_combout = ((\z80_|reg_file_|db_hi_as[6]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[6]~1_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~3 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_hi_as[6]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X36_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 ( +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( // Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) +// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~36_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_sw_2u~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~36_combout ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), + .combout(\z80_|execute_|ctl_inc_cy~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Location: LCCOMB_X35_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) +// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout ))) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_inc_cy~52_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~9 ( +// Location: LCCOMB_X39_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) +// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|ctl_mRead~17_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~9_combout ), + .combout(\z80_|execute_|ctl_inc_cy~41_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~9 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~9 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0045; +defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~10 ( +// Location: LCCOMB_X39_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) +// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout )) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~10 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~11_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~11 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~12_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[6]~22_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~12 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~14_combout = (\z80_|reg_file_|gdfx_temp1[6]~10_combout & (\z80_|reg_file_|gdfx_temp1[6]~11_combout & (\z80_|reg_file_|gdfx_temp1[6]~13_combout & \z80_|reg_file_|gdfx_temp1[6]~12_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~10_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~11_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~13_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~21_combout - - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), + .datad(\z80_|execute_|ctl_inc_cy~41_combout ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hEEFF; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~8 ( +// Location: LCCOMB_X35_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~8_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) +// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & +// ((\z80_|execute_|ctl_mRead~36_combout )))) - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~8_combout ), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~8 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[6]~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~15 ( +// Location: LCCOMB_X38_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~15_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout & (\z80_|reg_file_|gdfx_temp1[6]~9_combout & (\z80_|reg_file_|gdfx_temp1[6]~14_combout & \z80_|reg_file_|gdfx_temp1[6]~8_combout ))) +// \z80_|execute_|ctl_inc_cy~56_combout = (((!\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|fMRead~3_combout ) - .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~8_combout ), + .dataa(\z80_|execute_|fMRead~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~15_combout ), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~21 ( +// Location: LCCOMB_X39_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~21_combout = ((\z80_|reg_file_|gdfx_temp1[6]~15_combout & ((\z80_|reg_file_|db_hi_as[6]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) +// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - .dataa(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), + .combout(\z80_|execute_|ctl_inc_cy~89_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~21 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp1[6]~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hA020; +defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N24 -cycloneive_lcell_comb \z80_|interrupts_|im2~feeder ( +// Location: LCCOMB_X39_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( // Equation(s): -// \z80_|interrupts_|im2~feeder_combout = \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout +// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~56_combout ) # (\z80_|execute_|ctl_inc_cy~89_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ctl_inc_cy~55_combout ), + .datac(\z80_|execute_|ctl_inc_cy~56_combout ), + .datad(\z80_|execute_|ctl_inc_cy~89_combout ), .cin(gnd), - .combout(\z80_|interrupts_|im2~feeder_combout ), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|im2~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|im2~feeder .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y12_N25 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|im2~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Location: LCCOMB_X39_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( // Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) +// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~57_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~58_combout ) # (!\z80_|execute_|fMRead~5_combout )))) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_inc_cy~58_combout ), + .datac(\z80_|execute_|fMRead~5_combout ), + .datad(\z80_|execute_|ctl_inc_cy~57_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hFF8A; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Location: LCCOMB_X37_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( // Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|execute_|ctl_mRead~14_combout & (\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|pc_inc_hold~38_combout & (\z80_|execute_|pc_inc_hold~35_combout & (\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|pc_inc_hold~38_combout & (((\z80_|execute_|ctl_inc_cy~54_combout ) # +// (\z80_|execute_|ctl_inc_cy~59_combout )))) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|pc_inc_hold~35_combout ), + .datac(\z80_|execute_|ctl_inc_cy~54_combout ), + .datad(\z80_|execute_|ctl_inc_cy~59_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hD5D0; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N0 -cycloneive_lcell_comb \z80_|sw1_|db_down[6]~0 ( +// Location: LCCOMB_X35_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( // Equation(s): -// \z80_|sw1_|db_down[6]~0_combout = ((\z80_|bus_control_|db[6]~7_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) +// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|pc_inc_hold~50_combout ))) - .dataa(gnd), - .datab(\z80_|bus_control_|db[6]~7_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~50_combout ), .cin(gnd), - .combout(\z80_|sw1_|db_down[6]~0_combout ), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), .cout()); // synopsys translate_off -defparam \z80_|sw1_|db_down[6]~0 .lut_mask = 16'h0CFF; -defparam \z80_|sw1_|db_down[6]~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~10 ( +// Location: LCCOMB_X37_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( // Equation(s): -// \z80_|alu_|db_low[1]~10_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & !\z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~10 .lut_mask = 16'h3373; -defparam \z80_|alu_|db_low[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) +// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .combout(\z80_|execute_|ctl_inc_cy~88_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hAA08; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y17_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 ( +// Location: LCCOMB_X37_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( // Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout = (\z80_|alu_|db_low[1]~15_combout & \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) +// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_inc_cy~88_combout & ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~39_combout ), + .datab(\z80_|execute_|ctl_inc_cy~47_combout ), + .datac(\z80_|execute_|ctl_inc_cy~88_combout ), + .datad(\z80_|execute_|pc_inc_hold~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hECFC; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~40_combout = (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~34_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|pc_inc_hold~30_combout ), + .datac(\z80_|execute_|pc_inc_hold~34_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h3200; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|ctl_inc_cy~42_combout & ((\z80_|execute_|pc_inc_hold~40_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|pc_inc_hold~40_combout ), + .datac(\z80_|execute_|ctl_inc_cy~61_combout ), + .datad(\z80_|execute_|ctl_inc_cy~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hF0FD; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~48_combout ) # (\z80_|execute_|ctl_inc_cy~62_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), + .datab(\z80_|execute_|ctl_inc_cy~60_combout ), + .datac(\z80_|execute_|ctl_inc_cy~48_combout ), + .datad(\z80_|execute_|ctl_inc_cy~62_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~85_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~70_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), + .datab(\z80_|execute_|ctl_inc_cy~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~84_combout ), + .datad(\z80_|execute_|ctl_inc_cy~70_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (\z80_|execute_|ctl_inc_cy~85_combout ) .dataa(gnd), .datab(gnd), - .datac(\z80_|alu_|db_low[1]~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_cy~85_combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .lut_mask = 16'hF000; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( // Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .dataa(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFCF8; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hAF2F; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~12 ( +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( // Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~12_combout = (((!\z80_|execute_|nextM~11_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout )) # (!\z80_|execute_|ctl_reg_use_sp~0_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|ctl_mRead~38_combout -// & (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~13_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[1]~15_combout ) # ((\z80_|alu_|db_high[1]~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_high[1]~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(\z80_|alu_|db_high[1]~7_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|db_low[1]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) +// \z80_|address_latch_|abusz [0] = (\z80_|reg_file_|db_lo_as[0]~3_combout & !\z80_|resets_|clrpc~0_combout ) .dataa(gnd), - .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] + + .dataa(gnd), + .datab(gnd), .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|address_latch_|abusz [0]), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout ), + .combout(\z80_|address_latch_|Q[0]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1 .lut_mask = 16'h00CC; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # (\z80_|execute_|ctl_alu_op2_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N13 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[1]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[1]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00A0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N1 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~3 ( -// Equation(s): -// \z80_|alu_|db_high[1]~3_combout = (\z80_|alu_|op2_high [1] & (((\z80_|alu_|op1_high [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_high [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [1]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [1]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~3 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~2 ( -// Equation(s): -// \z80_|alu_|db_high[1]~2_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~2 .lut_mask = 16'h7333; -defparam \z80_|alu_|db_high[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N2 -cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( -// Equation(s): -// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_sw_2d~13_combout ) # ((\z80_|execute_|ctl_alu_oe~14_combout ) # (\z80_|execute_|ctl_reg_out_hi~7_combout )) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFEE; -defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( +// Location: FF_X31_Y16_N23 +dffeas \z80_|address_latch_|Q[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~70 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~72 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~71_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[5]~24_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~71 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~69 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~73_combout = (\z80_|reg_file_|gdfx_temp1[5]~70_combout & (\z80_|reg_file_|gdfx_temp1[5]~72_combout & (\z80_|reg_file_|gdfx_temp1[5]~71_combout & \z80_|reg_file_|gdfx_temp1[5]~69_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~70_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~72_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~71_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~69_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~67_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~67 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N27 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~16 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~68 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~74_combout = (\z80_|reg_file_|gdfx_temp1[5]~73_combout & (\z80_|reg_file_|gdfx_temp1[5]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout & \z80_|reg_file_|gdfx_temp1[5]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~75_combout = ((\z80_|reg_file_|gdfx_temp1[5]~74_combout & ((\z80_|reg_file_|db_hi_as[5]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~74_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~75 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp1[5]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N4 -cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( -// Equation(s): -// \z80_|alu_|db[5]~23_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[5]~29_combout & ((\z80_|reg_file_|gdfx_temp1[5]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// (((\z80_|reg_file_|gdfx_temp1[5]~75_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|alu_control_|db[5]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N6 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_high[1]~7_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db[5]~23_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_mWrite~2_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~24_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y11_N25 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [12]), + .d(\z80_|address_latch_|Q[0]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -24891,815 +20392,31 @@ dffeas \z80_|address_latch_|Q[12] ( .ena(\z80_|execute_|ctl_al_we~12_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), + .q(\z80_|address_latch_|Q [0]), .prn(vcc)); // synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [11] $ -// (\z80_|execute_|ctl_inc_dec~8_combout ))))) +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - .dataa(\z80_|address_latch_|Q [12]), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [4] & ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~22 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|db_hi_as[4]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~23_combout = (\z80_|reg_file_|db_hi_as[4]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~22_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~23 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[4]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~24_combout = ((\z80_|reg_file_|db_hi_as[4]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~24 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~17 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~77 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~76 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~79 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~78 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~80_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[4]~10_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[4]~10_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~80 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~81 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~82_combout = (\z80_|reg_file_|gdfx_temp1[4]~79_combout & (\z80_|reg_file_|gdfx_temp1[4]~78_combout & (\z80_|reg_file_|gdfx_temp1[4]~80_combout & \z80_|reg_file_|gdfx_temp1[4]~81_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~79_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~78_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~80_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~81_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~83_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout & (\z80_|reg_file_|gdfx_temp1[4]~77_combout & (\z80_|reg_file_|gdfx_temp1[4]~76_combout & \z80_|reg_file_|gdfx_temp1[4]~82_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~76_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~84_combout = ((\z80_|reg_file_|gdfx_temp1[4]~83_combout & ((\z80_|reg_file_|db_hi_as[4]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~83_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~84 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp1[4]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~2_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~19_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # (\z80_|execute_|ctl_sw_4u~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & \z80_|decode_state_|DFFE_inst4~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # (\z80_|execute_|ctl_inc_cy~80_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~70_combout ), - .datab(\z80_|execute_|ctl_inc_cy~67_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~81_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), - .datab(\z80_|address_latch_|Q [1]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h66CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N11 +// Location: FF_X31_Y17_N5 dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), @@ -25718,5802 +20435,7 @@ defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hFAD8; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N13 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_alu_op_low~32_combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~32_combout & (\z80_|alu_|op1_high [2])))) # -// (!\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|alu_|op1_low [2])))) - - .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hF0D8; -defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[1]~1_combout = (\z80_|execute_|ctl_alu_op_low~32_combout & (((\z80_|alu_|op1_low [1])))) # (!\z80_|execute_|ctl_alu_op_low~32_combout & ((\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|alu_|op1_high [1])) # -// (!\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|alu_|op1_low [1]))))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[1]~1 .lut_mask = 16'hE2F0; -defparam \z80_|alu_|alu_op1[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op2[1]~0_combout & \z80_|alu_|alu_op1[1]~1_combout )) - - .dataa(\z80_|alu_|alu_op2[1]~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~combout ), - .datac(gnd), - .datad(\z80_|alu_|alu_op1[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hEECC; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[1]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [1]))))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|alu_|alu_op2[1]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0027; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N8 -cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( -// Equation(s): -// \z80_|alu_|db[1]~15_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[1]~26_combout & ((\z80_|reg_file_|gdfx_temp1[1]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// (((\z80_|reg_file_|gdfx_temp1[1]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N10 -cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( -// Equation(s): -// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~15_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db[1]~15_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~48_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[0]~48_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~10 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~11_combout = (\z80_|reg_file_|db_hi_as[0]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~11 .lut_mask = 16'hB0B0; -defparam \z80_|reg_file_|db_hi_as[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0020; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[6]~15_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datad(\z80_|alu_control_|db[6]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|decode_state_|DFFE_inst4~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~75_combout & (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~78_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout & (\z80_|reg_file_|gdfx_temp0[6]~74_combout & \z80_|reg_file_|gdfx_temp0[6]~73_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (\z80_|reg_file_|db_lo_as[4]~15_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N11 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [4]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [4]) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h3C3C; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ -// (\z80_|execute_|ctl_inc_dec~8_combout ))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|Q [4]), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|Q [5]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'hD728; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X39_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~29_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[5]~29_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|alu_control_|db[5]~29_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~67_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~63_combout & (\z80_|reg_file_|gdfx_temp0[5]~64_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datac(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout = \z80_|reg_file_|db_lo_as[5]~18_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (\z80_|reg_file_|db_lo_as[5]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|address_latch_|Q[5]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[5]~feeder_combout = \z80_|address_latch_|abusz [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [5]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N9 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[5]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (\z80_|execute_|ctl_inc_dec~6_combout )) # (!\z80_|execute_|ctl_inc_dec~7_combout ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h5559; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N15 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~8_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & -// (\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_inc_dec~8_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2 .lut_mask = 16'h0BB0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[7]~18_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (\z80_|reg_file_|db_lo_as[7]~24_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[7]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[7]~feeder_combout = \z80_|address_latch_|abusz [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [7]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N5 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[7]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~12_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N31 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [7]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hD728; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~12_combout = ((\z80_|reg_file_|db_hi_as[0]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~11_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~12 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_hi_as[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~41 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~14 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~42 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~44_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[0]~18_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[0]~18_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~44 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[0]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~45 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[0]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~43_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~46_combout = (\z80_|reg_file_|gdfx_temp1[0]~42_combout & (\z80_|reg_file_|gdfx_temp1[0]~44_combout & (\z80_|reg_file_|gdfx_temp1[0]~45_combout & \z80_|reg_file_|gdfx_temp1[0]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~42_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~44_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~45_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~40 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[0]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~47_combout = (\z80_|reg_file_|gdfx_temp1[0]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout & (\z80_|reg_file_|gdfx_temp1[0]~46_combout & \z80_|reg_file_|gdfx_temp1[0]~40_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~41_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~46_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~48_combout = ((\z80_|reg_file_|gdfx_temp1[0]~47_combout & ((\z80_|reg_file_|db_hi_as[0]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~47_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~48 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp1[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N24 -cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( -// Equation(s): -// \z80_|alu_|db[0]~17_combout = (\z80_|alu_|db_low[0]~21_combout & (((\z80_|reg_file_|gdfx_temp1[0]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_|db_low[0]~21_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & -// ((\z80_|reg_file_|gdfx_temp1[0]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_|db_low[0]~21_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N22 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|alu_|db[0]~17_combout ), - .datac(\z80_|alu_control_|db[0]~12_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4FF; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N2 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [3] & ((\z80_|ir_|opcode [5] & ((\z80_|alu_|db[7]~20_combout ))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_|db[0]~18_combout )))) # (!\z80_|ir_|opcode [3] & -// (((\z80_|alu_|db[7]~20_combout & !\z80_|ir_|opcode [5])))) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hC0AC; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N4 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N20 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((!\z80_|ir_|opcode [4] & \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout )) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datac(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hF4F4; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~16 ( -// Equation(s): -// \z80_|alu_|db_low[0]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[1]~16_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~16 .lut_mask = 16'hF5A0; -defparam \z80_|alu_|db_low[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~17 ( -// Equation(s): -// \z80_|alu_|db_low[0]~17_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~16_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~18_combout )))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db_low[0]~16_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(\z80_|alu_|db[0]~18_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~17 .lut_mask = 16'hB8FF; -defparam \z80_|alu_|db_low[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( -// Equation(s): -// \z80_|alu_|db_low[0]~19_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [0] & ((\z80_|alu_|op1_low [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [0])) -// # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|alu_|op2_low [0]), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hF351; -defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # -// (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h57FF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~16_combout )))) # -// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~16_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & -// (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hEEC0; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # ((!\z80_|execute_|ctl_flags_alu~15_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & ((\z80_|execute_|ctl_flags_hf_we~2_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hB8AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y14_N23 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~14_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~11_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~11_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'h55F7; -defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & !\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal61~2_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFFA8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_control_|db[1]~26_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFFEC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|alu_|db_high[3]~19_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) - - .dataa(\z80_|alu_|db_high[3]~19_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFBF3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hB0F0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'h40C0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~16_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout )) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout & (\z80_|execute_|ctl_alu_core_hf~16_combout & \z80_|execute_|ctl_flags_nf_we~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal61~2_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~4_combout = ((\z80_|execute_|ctl_flags_nf_we~3_combout ) # ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_alu_core_hf~16_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hF000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N8 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (((!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0133; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout & (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'hB830; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X44_Y15_N29 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~9_combout = (\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_flags_hf_cpl~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (\z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_hf_cpl~10_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~8_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'h4404; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N0 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h0FB4; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_core_hf~16_combout & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~14_combout )) # (!\z80_|execute_|ctl_alu_core_hf~17_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (!\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|execute_|ctl_alu_core_hf~15_combout ) # ((!\z80_|execute_|ctl_alu_op_low~38_combout & \z80_|execute_|ctl_alu_core_hf~18_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'h3130; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hF400; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'hDCFC; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~20_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hFFF4; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout & (((!\z80_|execute_|ctl_alu_op_low~27_combout & \z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_op_low~34_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~23_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (\z80_|execute_|ctl_alu_core_hf~21_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h30BA; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_op_low~18_combout & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_alu_op_low~33_combout & ((\z80_|execute_|ctl_alu_core_hf~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~17_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_mWrite~2_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h8A88; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) # (!\z80_|execute_|ctl_mRead~8_combout & -// (\z80_|sequencer_|DFFE_M2_ff~q & ((!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (((\z80_|execute_|ctl_alu_op_low~17_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ixy_d~7_combout & -// (!\z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hF022; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (!\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout ))) # -// (!\z80_|pla_decode_|Equal56~0_combout & (\z80_|execute_|ctl_alu_core_hf~29_combout & \z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'h5440; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout & ((\z80_|execute_|ctl_alu_core_hf~31_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal10~0_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (!\z80_|execute_|ctl_alu_op_low~20_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~26_combout ) # (\z80_|execute_|ctl_alu_core_hf~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h0054; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout & !\z80_|execute_|ctl_alu_op_low~26_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ixy_d~5_combout ) # ((!\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ixy_d~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hF3F0; -defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~39_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~4_combout & \z80_|pla_decode_|Equal40~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hD0C0; -defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_alu_core_hf~24_combout ) # ((\z80_|execute_|ctl_alu_core_hf~33_combout ) # ((\z80_|execute_|ctl_alu_core_hf~40_combout & !\z80_|execute_|ctl_alu_op_low~30_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_core_hf~19_combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N30 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~35_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~35_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_flags_|flags_hf~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hCCAA; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~8 ( -// Equation(s): -// \z80_|alu_|db_high[0]~8_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~8 .lut_mask = 16'h3733; -defparam \z80_|alu_|db_high[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[0]~13_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00A0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N27 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~9 ( -// Equation(s): -// \z80_|alu_|db_high[0]~9_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [0] & ((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_high -// [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datab(\z80_|alu_|op2_high [0]), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op1_high [0]), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~9 .lut_mask = 16'hDD0D; -defparam \z80_|alu_|db_high[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~10 ( -// Equation(s): -// \z80_|alu_|db_high[0]~10_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~10 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_high[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~11 ( -// Equation(s): -// \z80_|alu_|db_high[0]~11_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~10_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~10_combout )) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~11 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_high[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~12 ( -// Equation(s): -// \z80_|alu_|db_high[0]~12_combout = (\z80_|alu_|db_high[0]~8_combout & (\z80_|alu_|db_high[0]~9_combout & ((\z80_|alu_|db_high[0]~11_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~8_combout ), - .datab(\z80_|alu_|db_high[0]~9_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[0]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~12 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~13 ( -// Equation(s): -// \z80_|alu_|db_high[0]~13_combout = ((\z80_|alu_|db_high[0]~12_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datab(\z80_|alu_|db_high[0]~12_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~13 .lut_mask = 16'hC8FF; -defparam \z80_|alu_|db_high[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[0]~13_combout ) # ((\z80_|alu_|db_low[0]~21_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((\z80_|alu_|db_low[0]~21_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_high[0]~13_combout ), - .datac(\z80_|alu_|db_low[0]~21_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N15 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_bus_inc_oe~44_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|pla_decode_|Equal61~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ) # (!\z80_|execute_|ctl_alu_op_low~39_combout -// ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # (((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # (((\z80_|execute_|ctl_alu_sel_op2_neg~12_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N20 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datab(\z80_|alu_|op2_low [0]), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~1 .lut_mask = 16'h1BE4; -defparam \z80_|alu_|alu_op2[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~0_combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op2[0]~1_combout -// )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & (\z80_|alu_|alu_op1[0]~0_combout & (\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op2[0]~1_combout ))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datab(\z80_|alu_|alu_op1[0]~0_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op2[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hEAA8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N17 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( -// Equation(s): -// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & !\z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h3337; -defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( -// Equation(s): -// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~19_combout & (\z80_|alu_|db_low[0]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|db_low[0]~19_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|alu_|db_low[0]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'hC800; -defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = ((\z80_|alu_|db_low[0]~17_combout & \z80_|alu_|db_low[0]~20_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(gnd), - .datab(\z80_|alu_|db_low[0]~17_combout ), - .datac(\z80_|alu_|db_low[0]~20_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hC0FF; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[0]~13_combout ) # ((\z80_|alu_|db_low[0]~21_combout & \z80_|execute_|ctl_alu_op1_sel_bus~14_combout )))) # -// (!\z80_|execute_|ctl_alu_op1_sel_low~combout & (\z80_|alu_|db_low[0]~21_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|alu_|db_low[0]~21_combout ), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N11 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|alu_|op1_high [0]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~0 .lut_mask = 16'hF3C0; -defparam \z80_|alu_|alu_op1[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_low[0]~21_combout ) # ((\z80_|alu_|alu_op1[0]~0_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|alu_|alu_op1[0]~0_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|alu_op1[0]~0_combout ), - .datac(\z80_|alu_|db_low[0]~21_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(gnd), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0C0C; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N29 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(gnd), - .datab(\z80_|alu_|op2_low [0]), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~0_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & !\z80_|execute_|ctl_alu_core_S~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hCCCF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # -// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h2223; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & \z80_|alu_|alu_op2[2]~2_combout )) - - .dataa(\z80_|alu_|alu_op1[2]~2_combout ), - .datab(gnd), - .datac(\z80_|alu_|alu_op2[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFA0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h33BF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op1[2]~2_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op2[2]~2_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op1[2]~2_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[2]~2_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[2]~2_combout ), - .datab(\z80_|alu_|alu_op2[2]~2_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hFE80; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y16_N11 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h3030; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N26 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~7 ( -// Equation(s): -// \z80_|alu_|db_low[2]~7_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|op2_low [2]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~7 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db_low[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~8 ( -// Equation(s): -// \z80_|alu_|db_low[2]~8_combout = (\z80_|alu_|db_low[2]~7_combout & (((!\z80_|bus_control_|db[5]~17_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~17_combout ), - .datab(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_low[2]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~8 .lut_mask = 16'h4F00; -defparam \z80_|alu_|db_low[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~59 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~62_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[2]~12_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[2]~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~62 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~63 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~61_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~61 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~60 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~64_combout = (\z80_|reg_file_|gdfx_temp1[2]~62_combout & (\z80_|reg_file_|gdfx_temp1[2]~63_combout & (\z80_|reg_file_|gdfx_temp1[2]~61_combout & \z80_|reg_file_|gdfx_temp1[2]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~62_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~63_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~61_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~15 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~58_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~58 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~65_combout = (\z80_|reg_file_|gdfx_temp1[2]~59_combout & (\z80_|reg_file_|gdfx_temp1[2]~64_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout & \z80_|reg_file_|gdfx_temp1[2]~58_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~59_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~64_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~58_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~66_combout = ((\z80_|reg_file_|gdfx_temp1[2]~65_combout & ((\z80_|reg_file_|db_hi_as[2]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~65_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~66 .lut_mask = 16'hDD5D; -defparam \z80_|reg_file_|gdfx_temp1[2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( -// Equation(s): -// \z80_|alu_|db[2]~11_combout = (\z80_|alu_control_|db[2]~22_combout & ((\z80_|reg_file_|gdfx_temp1[2]~66_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[2]~22_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[2]~66_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[2]~22_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~11 .lut_mask = 16'h8ACF; -defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N14 -cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( -// Equation(s): -// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~22_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[2]~11_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db_low[2]~22_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( -// Equation(s): -// \z80_|alu_|db_low[2]~5_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( -// Equation(s): -// \z80_|alu_|db_low[2]~6_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~5_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~12_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_|db_low[2]~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'hCAFF; -defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N2 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( -// Equation(s): -// \z80_|alu_|db_low[2]~9_combout = (\z80_|alu_|db_low[2]~8_combout & (\z80_|alu_|db_low[2]~6_combout & ((\z80_|alu_|result_lo [2]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|result_lo [2]), - .datab(\z80_|alu_|db_low[2]~8_combout ), - .datac(\z80_|alu_|db_low[2]~6_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hC080; -defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~22 ( -// Equation(s): -// \z80_|alu_|db_low[2]~22_combout = (\z80_|alu_|db_low[2]~9_combout ) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_low[2]~9_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~22 .lut_mask = 16'hF3F3; -defparam \z80_|alu_|db_low[2]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & ((\z80_|alu_|db_low[2]~22_combout ) # ((\z80_|alu_|db_high[2]~25_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[2]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(\z80_|alu_|db_high[2]~25_combout ), - .datac(\z80_|alu_|db_low[2]~22_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N19 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N24 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hFC00; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~19 ( -// Equation(s): -// \z80_|alu_control_|db[2]~19_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|alu_flags_|flags_hf2~q ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_66_oe~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~19 .lut_mask = 16'hFFEF; -defparam \z80_|alu_control_|db[2]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~8_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~23 ( -// Equation(s): -// \z80_|alu_control_|db[1]~23_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|alu_|db[1]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_oe~2_combout ) # -// ((!\z80_|alu_|db[1]~16_combout & \z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~23 .lut_mask = 16'h7350; -defparam \z80_|alu_control_|db[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( -// Equation(s): -// \z80_|alu_control_|db[1]~24_combout = (\z80_|alu_control_|db[2]~19_combout & (!\z80_|alu_control_|db[1]~23_combout & ((\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|db[2]~19_combout ), - .datac(\z80_|alu_control_|db[1]~23_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0C04; -defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|alu_control_|db[1]~24_combout & (((\z80_|bus_control_|db[1]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[1]~13_combout ), - .datab(\z80_|alu_control_|db[1]~24_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h08CC; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = (\z80_|alu_control_|db[1]~25_combout ) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_control_|db[1]~25_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'hF0FF; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[1]~26_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .datad(\z80_|alu_control_|db[1]~26_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~29_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~25_combout & \z80_|reg_file_|gdfx_temp0[1]~28_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N3 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N29 +// Location: FF_X31_Y13_N23 dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -31532,101 +20454,101 @@ defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N28 +// Location: LCCOMB_X31_Y13_N22 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[1]~32_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hA2F3; defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N12 +// Location: LCCOMB_X31_Y17_N26 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( // Equation(s): // \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hAF00; +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF300; defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N10 +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~85_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_cy~85_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h6A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N4 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .dataa(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hAF2F; defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N2 +// Location: LCCOMB_X30_Y17_N14 cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( // Equation(s): -// \z80_|address_latch_|abusz [1] = (\z80_|reg_file_|db_lo_as[1]~6_combout & !\z80_|resets_|clrpc~0_combout ) +// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - .dataa(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), .cin(gnd), .combout(\z80_|address_latch_|abusz [1]), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h00AA; +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h3300; defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[1]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[1]~feeder_combout = \z80_|address_latch_|abusz [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N23 +// Location: FF_X30_Y17_N19 dffeas \z80_|address_latch_|Q[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[1]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [1]), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|execute_|ctl_al_we~12_combout ), .devclrn(devclrn), .devpor(devpor), @@ -31637,30 +20559,13 @@ defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; defparam \z80_|address_latch_|Q[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hFF0F; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 +// Location: LCCOMB_X30_Y17_N6 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ))) +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), .datac(\z80_|address_latch_|Q [1]), .datad(\z80_|execute_|ctl_inc_dec~10_combout ), .cin(gnd), @@ -31671,493 +20576,16 @@ defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .lut_mask = defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[2]~22_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|alu_control_|db[2]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~35_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~37_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[2]~42_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 +// Location: LCCOMB_X29_Y17_N22 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & -// \z80_|execute_|ctl_inc_cy~81_combout )))) +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|execute_|ctl_inc_cy~85_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datab(\z80_|execute_|ctl_inc_cy~85_combout ), .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|execute_|ctl_inc_cy~81_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), .cout()); @@ -32166,44 +20594,61 @@ defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N4 +// Location: LCCOMB_X31_Y17_N16 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - .dataa(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'h8FAF; +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hF575; defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N16 +// Location: LCCOMB_X29_Y17_N12 cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( // Equation(s): -// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) +// \z80_|address_latch_|abusz [2] = (\z80_|reg_file_|db_lo_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - .dataa(gnd), + .dataa(\z80_|reg_file_|db_lo_as[2]~9_combout ), .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), .cin(gnd), .combout(\z80_|address_latch_|abusz [2]), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h00AA; defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N17 +// Location: LCCOMB_X29_Y17_N14 +cycloneive_lcell_comb \z80_|address_latch_|Q[2]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[2]~feeder_combout = \z80_|address_latch_|abusz [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [2]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N15 dffeas \z80_|address_latch_|Q[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [2]), + .d(\z80_|address_latch_|Q[2]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -32219,2641 +20664,112 @@ defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; defparam \z80_|address_latch_|Q[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y10_N28 +// Location: LCCOMB_X30_Y17_N2 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ))) +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|address_latch_|Q [2]), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h0F87; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h40BF; defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Location: LCCOMB_X35_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( // Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) +// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ctl_inc_cy~80_combout ), + .datad(\z80_|execute_|ctl_inc_cy~83_combout ), .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), + .combout(\z80_|execute_|ctl_inc_cy~86_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N13 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [3]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [4]) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(gnd), - .datac(\z80_|address_latch_|Q [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hAF00; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hDD00; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X39_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~59_combout & (\z80_|reg_file_|gdfx_temp0[4]~58_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .datab(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .datac(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h80A0; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & (\z80_|reg_file_|gdfx_temp0[4]~56_combout & \z80_|reg_file_|gdfx_temp0[4]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( -// Equation(s): -// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~10_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~10_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; -defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (!\z80_|alu_control_|db[4]~30_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_control_|db[4]~30_combout ), - .datab(\z80_|alu_flags_|flags_hf~combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h4500; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|alu_control_|db[4]~31_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hC4FF; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( -// Equation(s): -// \z80_|alu_|db[4]~8_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[4]~32_combout & ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .datac(\z80_|alu_control_|db[4]~32_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~8 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N16 -cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( -// Equation(s): -// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[4]~8_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~4 ( -// Equation(s): -// \z80_|alu_|db_high[1]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~22_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~10_combout )) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~4 .lut_mask = 16'hCACA; -defparam \z80_|alu_|db_high[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~5 ( -// Equation(s): -// \z80_|alu_|db_high[1]~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[1]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~5 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_high[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~6 ( -// Equation(s): -// \z80_|alu_|db_high[1]~6_combout = (\z80_|alu_|db_high[1]~3_combout & (\z80_|alu_|db_high[1]~2_combout & ((\z80_|alu_|db_high[1]~5_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~3_combout ), - .datab(\z80_|alu_|db_high[1]~2_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[1]~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~6 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~7 ( -// Equation(s): -// \z80_|alu_|db_high[1]~7_combout = ((\z80_|alu_|db_high[1]~6_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_high[3]~1_combout ), - .datab(\z80_|alu_|db_high[1]~6_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~7 .lut_mask = 16'hDDD5; -defparam \z80_|alu_|db_high[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), - .datac(\z80_|alu_|db_high[1]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'h00EC; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N9 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hC480; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~15_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) - - .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datab(\z80_|alu_|db_low[1]~15_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N11 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|alu_|op2_high [1]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~0 .lut_mask = 16'h3C5A; -defparam \z80_|alu_|alu_op2[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h7773; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & -// \z80_|alu_|alu_op1[1]~1_combout )))) # (!\z80_|alu_|alu_op2[1]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~1_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[1]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .datad(\z80_|alu_|alu_op1[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hF2B0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y16_N29 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~11 ( -// Equation(s): -// \z80_|alu_|db_low[1]~11_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [1] & ((\z80_|alu_|op2_low [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op2_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~11 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db_low[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( -// Equation(s): -// \z80_|alu_|db_low[1]~12_combout = (\z80_|alu_|db_low[1]~10_combout & (\z80_|alu_|db_low[1]~11_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~10_combout ), - .datab(\z80_|alu_|result_lo [1]), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_low[1]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( -// Equation(s): -// \z80_|alu_|db_low[1]~13_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_|db[0]~18_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hAACC; -defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( -// Equation(s): -// \z80_|alu_|db_low[1]~14_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~13_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~16_combout )) - - .dataa(\z80_|alu_|db[1]~16_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_low[1]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = ((\z80_|alu_|db_low[1]~12_combout & ((\z80_|alu_|db_low[1]~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_low[1]~12_combout ), - .datab(\z80_|alu_|db_low[1]~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'h8AFF; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (\z80_|alu_|db_high[3]~1_combout & (!\z80_|alu_|db_low[2]~9_combout & ((!\z80_|alu_|db_low[3]~4_combout ) # (!\z80_|alu_|db_low[3]~1_combout )))) - - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_low[2]~9_combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~15_combout & (\z80_|execute_|ctl_flags_alu~16_combout & (!\z80_|alu_|db_low[0]~21_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(\z80_|execute_|ctl_flags_alu~16_combout ), - .datac(\z80_|alu_|db_low[0]~21_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[0]~13_combout & !\z80_|alu_|db_high[1]~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|alu_|db_high[1]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h000F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & (!\z80_|alu_|db_high[2]~25_combout & !\z80_|alu_|db_high[3]~19_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .datac(\z80_|alu_|db_high[2]~25_combout ), - .datad(\z80_|alu_|db_high[3]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .lut_mask = 16'h0008; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal13~0_combout ) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hDFFF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[6]~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[6]~15_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hF800; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y15_N13 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N2 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_control_|out[6]~0_combout & \z80_|alu_|op1_high [0]))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|alu_|op1_high [0]), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFFEA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N14 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) - - .dataa(\z80_|alu_control_|out[6]~1_combout ), - .datab(\z80_|execute_|ctl_66_oe~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|alu_|op1_high [3]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~13 ( -// Equation(s): -// \z80_|alu_control_|db[6]~13_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|out[6]~2_combout ) # (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) # -// (!\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|alu_control_|out[6]~2_combout ) # (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~13 .lut_mask = 16'hDDD0; -defparam \z80_|alu_control_|db[6]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~14 ( -// Equation(s): -// \z80_|alu_control_|db[6]~14_combout = (\z80_|alu_control_|db[6]~13_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(\z80_|alu_control_|db[6]~13_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~14 .lut_mask = 16'h88AA; -defparam \z80_|alu_control_|db[6]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_reg_out_lo~2_combout ))) - - .dataa(\z80_|execute_|rsel3~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFFC8; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hF4F0; -defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~15 ( -// Equation(s): -// \z80_|alu_control_|db[6]~15_combout = ((\z80_|sw1_|db_down[6]~0_combout & (\z80_|alu_control_|db[6]~14_combout & \z80_|reg_file_|db_lo_ds[6]~0_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|sw1_|db_down[6]~0_combout ), - .datab(\z80_|alu_control_|db[6]~14_combout ), - .datac(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~15 .lut_mask = 16'h80FF; -defparam \z80_|alu_control_|db[6]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N20 -cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( -// Equation(s): -// \z80_|alu_|db[6]~21_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[6]~15_combout & ((\z80_|reg_file_|gdfx_temp1[6]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// (((\z80_|reg_file_|gdfx_temp1[6]~21_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .datad(\z80_|alu_control_|db[6]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N26 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_high[2]~25_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[6]~21_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~20 ( -// Equation(s): -// \z80_|alu_|db_high[2]~20_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~20_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|alu_|db[7]~20_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~20 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_high[2]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~21 ( -// Equation(s): -// \z80_|alu_|db_high[2]~21_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~20_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[2]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~21 .lut_mask = 16'hFD5D; -defparam \z80_|alu_|db_high[2]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[2]~9_combout ) # (!\z80_|alu_|db_high[3]~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(gnd), - .datac(\z80_|alu_|db_low[2]~9_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6 .lut_mask = 16'hA0AA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ) # ((\z80_|alu_|db_high[2]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|db_high[2]~25_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7 .lut_mask = 16'h5540; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N21 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~22 ( -// Equation(s): -// \z80_|alu_|db_high[2]~22_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [2] & ((\z80_|alu_|op1_high [2]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high -// [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~22 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db_high[2]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~23 ( -// Equation(s): -// \z80_|alu_|db_high[2]~23_combout = (\z80_|alu_|db_high[2]~22_combout & (((\z80_|bus_control_|db[5]~17_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~17_combout ), - .datab(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_high[2]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~23 .lut_mask = 16'h8F00; -defparam \z80_|alu_|db_high[2]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~24 ( -// Equation(s): -// \z80_|alu_|db_high[2]~24_combout = (\z80_|alu_|db_high[2]~21_combout & (\z80_|alu_|db_high[2]~23_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_high[2]~21_combout ), - .datab(\z80_|alu_|db_high[2]~23_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~24 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_high[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|db_high[2]~24_combout ) # (!\z80_|alu_|db_high[3]~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(\z80_|alu_|db_high[2]~24_combout ), - .datac(\z80_|alu_|db_high[3]~1_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h008A; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N7 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'hE400; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_low[2]~22_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) - - .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .datab(\z80_|alu_|db_low[2]~22_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N7 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [2]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [2])))) - - .dataa(\z80_|alu_|op2_low [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~2 .lut_mask = 16'h3C66; -defparam \z80_|alu_|alu_op2[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [2]))))) - - .dataa(\z80_|alu_|alu_op2[2]~2_combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [2]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1015; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hCCEF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hCFCE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~12_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout -// & ((\z80_|execute_|ctl_flags_alu~16_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~12_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_flags_alu~16_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hF444; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~0_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~0 .lut_mask = 16'h2202; -defparam \z80_|execute_|ctl_flags_cf2_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~1_combout = (((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_we~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_we~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~1 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_flags_cf2_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~1_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0D8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y14_N23 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|alu_|db[0]~18_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hE4E4; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # -// (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & -// ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h4472; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout $ ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout & \z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y14_N1 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hFE10; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = (\z80_|execute_|ctl_state_alu~11_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'h8500; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|pla_decode_|Equal10~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'hCECC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_alu_op_low~37_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~27_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'hFFD5; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) # ((\z80_|execute_|ctl_alu_op_low~32_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'hFFEA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~18_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'h7775; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|pla_decode_|Equal9~0_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & -// (((\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFCB8; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hFF20; -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~11_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~11 .lut_mask = 16'hF0F8; -defparam \z80_|execute_|ctl_flags_cf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~11_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_alu_op_low~33_combout & \z80_|execute_|ctl_alu_op_low~18_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~11_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout & \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N14 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~10_combout ))))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0A28; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( -// Equation(s): -// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~15_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|bus_control_|db[0]~15_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h5D00; -defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N28 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|db[0]~18_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hF0FF; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( -// Equation(s): -// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~8_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'hA200; -defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( -// Equation(s): -// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_control_|db[0]~9_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'h8CFF; -defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[0]~12_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .datad(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hC040; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~13_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .datab(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y11_N29 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [0]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~7_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 +// Location: LCCOMB_X29_Y17_N0 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # -// (\z80_|execute_|ctl_inc_cy~80_combout )))) +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~86_combout ) # +// (\z80_|execute_|ctl_inc_cy~70_combout )))) - .dataa(\z80_|execute_|ctl_inc_cy~70_combout ), - .datab(\z80_|execute_|ctl_inc_cy~67_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datab(\z80_|execute_|ctl_inc_cy~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~86_combout ), + .datad(\z80_|execute_|ctl_inc_cy~70_combout ), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hFE00; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hAAA8; defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y10_N16 +// Location: LCCOMB_X30_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|execute_|ctl_inc_cy~85_combout & ((\z80_|address_latch_|Q [1] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q [0])) # (!\z80_|address_latch_|Q +// [1] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [0])))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_cy~85_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'h2400; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N10 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout +// ))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), + .dataa(gnd), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), .datad(\z80_|address_latch_|Q [3]), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h7F80; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h3FC0; defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N3 +// Location: FF_X28_Y10_N15 dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -34872,7 +20788,7 @@ defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y11_N21 +// Location: FF_X28_Y10_N21 dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -34891,7 +20807,7 @@ defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y11_N2 +// Location: LCCOMB_X28_Y10_N14 cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( // Equation(s): // \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # @@ -34909,15 +20825,32 @@ defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y12_N19 +// Location: LCCOMB_X29_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N27 dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -34928,7 +20861,7 @@ defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X38_Y12_N3 +// Location: FF_X30_Y11_N11 dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -34947,123 +20880,33 @@ defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N2 +// Location: LCCOMB_X30_Y11_N10 cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) +// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), .cin(gnd), .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hB0BB; defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[3]~35_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|alu_control_|db[3]~35_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N13 +// Location: FF_X30_Y10_N5 dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), .devclrn(devclrn), .devpor(devpor), @@ -35074,7 +20917,7 @@ defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X39_Y12_N29 +// Location: FF_X30_Y10_N11 dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -35093,345 +20936,3536 @@ defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y12_N28 +// Location: LCCOMB_X30_Y10_N10 cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) +// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), .cin(gnd), .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~47_combout & \z80_|reg_file_|gdfx_temp0[3]~49_combout ))) +// \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N6 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~2 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~2_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~2 .lut_mask = 16'hF8FC; -defparam \z80_|sw1_|db_down[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~2_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[3]~33_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datad(\z80_|sw1_|db_down[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hA200; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[3]~34_combout ), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hD5DD; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N18 -cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( -// Equation(s): -// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|alu_|db[3]~13_combout ), - .datac(\z80_|alu_control_|db[3]~35_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hC4FF; -defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~0 ( -// Equation(s): -// \z80_|alu_|db_low[3]~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) - - .dataa(\z80_|alu_|db[2]~12_combout ), + .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~0 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~1 ( -// Equation(s): -// \z80_|alu_|db_low[3]~1_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~14_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[3]~14_combout ), - .datab(\z80_|alu_|db_low[3]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~1 .lut_mask = 16'hCAFF; -defparam \z80_|alu_|db_low[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~23 ( -// Equation(s): -// \z80_|alu_|db_low[3]~23_combout = ((\z80_|alu_|db_low[3]~1_combout & \z80_|alu_|db_low[3]~4_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), .datac(gnd), - .datad(\z80_|alu_|db_low[3]~4_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .cin(gnd), - .combout(\z80_|alu_|db_low[3]~23_combout ), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|db_low[3]~23 .lut_mask = 16'hBB33; -defparam \z80_|alu_|db_low[3]~23 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))))) +// Location: FF_X29_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(\z80_|alu_|op1_low [3]), - .datac(\z80_|alu_|op1_high [3]), +// Location: FF_X30_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h3F3B; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~29_combout ) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|setM1~29_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_al_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hB3F3; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|execute_|setM1~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h5DDD; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # (!\z80_|execute_|ctl_reg_gp_we~2_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB3FF; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (\z80_|execute_|ctl_reg_in_hi~11_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~4_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|alu_|db[3]~11_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[3]~11_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[3]~11_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h4444; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|execute_|ctl_reg_gp_we~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5450; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~3_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hFB33; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (\z80_|execute_|ctl_reg_sys_we~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF3; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0002; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0008; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & (\z80_|reg_file_|gdfx_temp1[3]~45_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~40_combout & (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout & \z80_|reg_file_|gdfx_temp1[3]~46_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~13_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~13_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[1]~13_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout & (\z80_|reg_file_|gdfx_temp1[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'h8AAA; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h96CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~19_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~19_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[0]~19_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~24_combout & (\z80_|reg_file_|gdfx_temp1[0]~26_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & \z80_|reg_file_|gdfx_temp1[0]~27_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~6_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N9 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [7] & (\z80_|address_latch_|Q [8] & !\z80_|execute_|ctl_inc_dec~11_combout +// )) # (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [8] & \z80_|execute_|ctl_inc_dec~11_combout )))) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1800; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0C0C; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N5 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[9]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [9]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|alu_|db[2]~15_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[2]~15_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[2]~15_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N15 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~35_combout & (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~33_combout & \z80_|reg_file_|gdfx_temp1[2]~36_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~32_combout & (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .datab(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'h8FAF; +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hCC44; +defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (\z80_|reg_file_|db_hi_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|Q[10]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[10]~feeder_combout = \z80_|address_latch_|abusz [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [10]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N27 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[10]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [10] & (\z80_|address_latch_|Q [9] & +// !\z80_|execute_|ctl_inc_dec~11_combout )) # (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [9] & \z80_|execute_|ctl_inc_dec~11_combout )))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [9]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h1800; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N15 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [11]) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(gnd), + .datac(\z80_|address_latch_|Q [11]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|alu_|db_low[3]~11_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'h888A; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~8_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N7 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~3 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~3_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])) + + .dataa(gnd), + .datab(\z80_|alu_|op1_high [3]), + .datac(\z80_|alu_|op1_low [3]), .datad(\z80_|execute_|ctl_alu_op_low~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .combout(\z80_|alu_|alu_op1[3]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'h88A0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_|alu_op1[3]~3 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|alu_op1[3]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( +// Location: LCCOMB_X38_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( // Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|alu_|db_low[3]~23_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high +// [2])))) - .dataa(\z80_|alu_|db_low[3]~23_combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|alu_op2[2]~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h00EC; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0305; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y17_N5 -dffeas \z80_|alu_|op2_low[3] ( +// Location: LCCOMB_X39_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = ((\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mWrite~2_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAAFB; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # +// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[1]~17_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_high[1]~20_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'h5050; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N1 +dffeas \z80_|alu_|op2_high[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -35440,51 +24474,1928 @@ dffeas \z80_|alu_|op2_low[3] ( .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), + .q(\z80_|alu_|op2_high [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4 ( +// Location: LCCOMB_X36_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( // Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[3]~1_combout & \z80_|alu_|db_low[3]~4_combout )) # (!\z80_|alu_|db_high[3]~1_combout ))) +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~20_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[1]~20_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4 .lut_mask = 16'hB030; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ) # ((\z80_|alu_|db_high[3]~19_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) +// Location: FF_X36_Y10_N23 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ), - .datab(\z80_|alu_|db_high[3]~19_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), +// Location: LCCOMB_X37_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'h8C80; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N21 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~20_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal68~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # ((\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|execute_|ctl_state_alu~8_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~9_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~12_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h7577; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal61~2_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hFC00; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~20_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~21_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout & (((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout +// ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .lut_mask = 16'hC4CC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~12_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_alu_core_hf~20_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & !\z80_|pla_decode_|Equal71~2_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|pla_decode_|Equal71~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|pla_decode_|Equal21~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal3~0_combout & +// ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'hFCA8; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal13~1_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & \z80_|pla_decode_|Equal63~0_combout +// ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hFFEC; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|execute_|ctl_alu_op_low~31_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal72~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (!\z80_|pla_decode_|Equal72~2_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datab(\z80_|pla_decode_|Equal72~2_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout )) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFAFF; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_flags_sz_we~5_combout & \z80_|execute_|ctl_alu_core_R~0_combout )))) # +// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~4_combout = (((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (\z80_|execute_|ctl_flags_sz_we~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'h5000; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( +// Equation(s): +// \z80_|execute_|setM1~16_combout = (\z80_|execute_|setM1~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~31_combout ))) + + .dataa(\z80_|execute_|setM1~15_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0200; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|setM1~16_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|execute_|setM1~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_alu_oe~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (\z80_|execute_|ctl_flags_xy_we~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal11~1_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal11~1_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBAA; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; +defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~8_combout = ((\z80_|execute_|ctl_flags_alu~7_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~8_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_flags_alu~6_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_alu~7_combout ), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0070; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_xy_we~16_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datac(\z80_|execute_|ctl_sw_2d~4_combout ), + .datad(\z80_|execute_|ctl_flags_alu~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_flags_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|execute_|ctl_flags_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = ((\z80_|execute_|ctl_flags_alu~8_combout ) # ((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_alu~8_combout ), + .datac(\z80_|execute_|ctl_flags_alu~14_combout ), + .datad(\z80_|execute_|ctl_flags_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), + .datac(\z80_|alu_control_|db[1]~26_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEEE; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_high[3]~8_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFFB3; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h3070; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'h0800; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'hD850; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y9_N27 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|sequencer_|DFFE_M2_ff~q & +// (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'h7707; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = ((\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'hB3BB; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~15_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal13~2_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) + + .dataa(\z80_|alu_|op2_high [1]), + .datab(\z80_|alu_|op2_low [1]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h5A3C; +defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [1]))))) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(\z80_|alu_|op1_low [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = (((\z80_|pla_decode_|Equal71~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datad(\z80_|pla_decode_|Equal71~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|db_high[0]~26_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|alu_|db_high[0]~26_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) + + .dataa(\z80_|alu_|db_high[0]~26_combout ), + .datab(\z80_|alu_|db_low[0]~23_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout ), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .lut_mask = 16'h00F0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y17_N31 +// Location: FF_X37_Y10_N7 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|alu_|op2_high [0]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h3C5A; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & ((\z80_|ir_|opcode [3]) # ((!\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal62~2_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'hB0F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & \z80_|execute_|ctl_alu_core_S~7_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~9_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # +// (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h37FF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_alu_core_hf~20_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_core_hf~18_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hA0E0; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout & (((\z80_|execute_|ctl_alu_core_hf~19_combout & !\z80_|execute_|ctl_alu_op_low~29_combout )) # (!\z80_|execute_|ctl_alu_op_low~28_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~22_combout & (\z80_|execute_|ctl_alu_core_hf~19_combout & (!\z80_|execute_|ctl_alu_op_low~29_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0CAE; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hFF30; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hDFCC; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~20_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h22F2; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datab(\z80_|execute_|ctl_state_alu~13_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & !\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~7_combout & +// ((!\z80_|execute_|ctl_mWrite~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hC0CA; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~43_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~6_combout & (\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # +// ((\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~43 .lut_mask = 16'hD5C0; +defparam \z80_|execute_|ctl_alu_core_hf~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (!\z80_|execute_|ctl_alu_core_hf~43_combout & ((\z80_|execute_|ctl_alu_core_hf~32_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~32_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'h00E8; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~42_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~42 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_core_hf~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~42_combout & ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # (\z80_|execute_|ctl_alu_core_hf~33_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~41_combout = (!\z80_|execute_|ctl_state_alu~4_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal10~0_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~41 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_core_hf~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & +// (\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal11~1_combout & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal11~1_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~41_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~41_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .datad(\z80_|execute_|ctl_mWrite~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h0054; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~44_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~44 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & ((\z80_|execute_|ctl_alu_core_hf~44_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~44_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'h0E0A; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # ((!\z80_|execute_|ctl_alu_op_low~30_combout & \z80_|execute_|ctl_alu_core_hf~35_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~24_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFCFE; +defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~39_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = (\z80_|execute_|ctl_alu_core_R~2_combout ) # (((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[3]~11_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .lut_mask = 16'hC0D0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[3]~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), + .datad(\z80_|alu_|db_high[3]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .lut_mask = 16'h5450; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N9 dffeas \z80_|alu_|op2_high[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -35500,649 +26411,2610 @@ defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; defparam \z80_|alu_|op2_high[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y16_N20 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~3 ( +// Location: LCCOMB_X37_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 ( // Equation(s): -// \z80_|alu_|alu_op2[3]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) - - .dataa(\z80_|alu_|op2_low [3]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|op2_high [3]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~3 .lut_mask = 16'h3C66; -defparam \z80_|alu_|alu_op2[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~3_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [3])))) +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|alu_|alu_op2[3]~3_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), .datac(\z80_|execute_|ctl_alu_op_low~combout ), .datad(\z80_|alu_|op1_low [3]), .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), + .datac(\z80_|alu_|db_low[3]~25_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N19 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) + + .dataa(\z80_|alu_|op2_high [3]), + .datab(\z80_|alu_|op2_low [3]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h5A3C; +defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[3]~3_combout & \z80_|alu_|alu_op2[3]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) + + .dataa(\z80_|alu_|alu_op1[3]~3_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|alu_|alu_op2[3]~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high +// [3])))) + + .dataa(\z80_|alu_|alu_op2[3]~2_combout ), + .datab(\z80_|alu_|op1_high [3]), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0131; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0511; defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N24 +// Location: LCCOMB_X39_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hAFAE; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # +// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[4]~32_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|pla_decode_|Equal10~0_combout & +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hFC88; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~14_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~14_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N7 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ctl_state_alu~14_combout )) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|alu_flags_|DFFE_inst_latch_nf~q ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N8 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( +// Equation(s): +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h559A; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N30 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~40_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~40_combout & (\z80_|alu_flags_|flags_cf~combout )) + + .dataa(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(gnd), + .datad(\z80_|alu_flags_|flags_hf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hEE44; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~1_combout )))) +// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~1_combout )))) + + .dataa(\z80_|alu_|alu_op2[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~25_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|alu_|db[3]~11_combout ), + .datac(\z80_|alu_|db[5]~25_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hE4E4; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0C0C; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|Q[12]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[12]~feeder_combout = \z80_|address_latch_|abusz [12] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [12]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[12]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[12]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N15 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[12]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ +// (\z80_|address_latch_|Q [11]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .datad(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~12_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~17_combout )) # (!\z80_|execute_|ctl_reg_in_hi~12_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|alu_|db[4]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y11_N29 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & (\z80_|reg_file_|gdfx_temp1[4]~61_combout & \z80_|reg_file_|gdfx_temp1[4]~60_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|db[4]~16 ( +// Equation(s): +// \z80_|alu_|db[4]~16_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[4]~32_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[4]~32_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~16 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|db[7]~26 ( +// Equation(s): +// \z80_|alu_|db[7]~26_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_alu_oe~13_combout ), + .datac(\z80_|execute_|ctl_alu_oe~9_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~26 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|db[7]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( +// Equation(s): +// \z80_|alu_|db[4]~17_combout = ((\z80_|alu_|db[4]~16_combout & ((\z80_|alu_|db_high[0]~26_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[4]~16_combout ), + .datab(\z80_|alu_|db[7]~26_combout ), + .datac(\z80_|alu_|db_high[0]~26_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h00C8; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~6_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[0]~23_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[4]~17_combout ))) + + .dataa(\z80_|alu_|db_high[0]~23_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[4]~17_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hAAF0; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'h5575; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~26_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[0]~26_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N21 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op1_high [0] & (((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [0] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [0]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [0]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~22_combout & ((\z80_|alu_|db_high[0]~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[0]~24_combout ), + .datab(\z80_|alu_|db_high[0]~21_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'h8C00; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~26 ( +// Equation(s): +// \z80_|alu_|db_high[0]~26_combout = ((\z80_|alu_|db_high[0]~25_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~26 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) # +// (!\z80_|alu_|db_low[0]~23_combout & (((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) + + .dataa(\z80_|alu_|db_low[0]~23_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datad(\z80_|alu_|db_high[0]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h00F0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFEFE; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N31 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|alu_|op1_high [0]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) # +// (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_low[0]~23_combout )))) + + .dataa(\z80_|alu_|alu_op1[0]~1_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h5050; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N15 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(gnd), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0AA; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~9_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & +// \z80_|execute_|ctl_alu_core_S~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_low [1]), + .datac(gnd), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hDD88; +defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[1]~0_combout & \z80_|alu_|alu_op2[1]~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datac(\z80_|alu_|alu_op1[1]~0_combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFBBB; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # +// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F01; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( +// Equation(s): +// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(gnd), + .datad(\z80_|alu_|op1_low [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hEE22; +defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op2[2]~0_combout & \z80_|alu_|alu_op1[2]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|alu_|alu_op1[2]~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hFF0B; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N14 cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( // Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|execute_|ctl_alu_core_R~5_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ))) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op1[3]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & +// \z80_|alu_|alu_op2[3]~2_combout )))) # (!\z80_|alu_|alu_op1[3]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .dataa(\z80_|alu_|alu_op1[3]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|alu_|alu_op2[3]~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), .cin(gnd), .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'h152F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFB20; defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 ( +// Location: LCCOMB_X28_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder ( // Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout -// )) +// \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout .dataa(gnd), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .lut_mask = 16'hCCFC; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~14 ( -// Equation(s): -// \z80_|alu_|db_high[3]~14_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~14 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_high[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~15 ( -// Equation(s): -// \z80_|alu_|db_high[3]~15_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~14_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~20_combout )))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db_high[3]~14_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~15 .lut_mask = 16'hACFF; -defparam \z80_|alu_|db_high[3]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~16 ( -// Equation(s): -// \z80_|alu_|db_high[3]~16_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_high [3] & ((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high -// [3]) # ((!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op2_high [3]), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~16 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db_high[3]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~17 ( -// Equation(s): -// \z80_|alu_|db_high[3]~17_combout = (\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[5]~17_combout )) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~17 .lut_mask = 16'hC000; -defparam \z80_|alu_|db_high[3]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~18 ( -// Equation(s): -// \z80_|alu_|db_high[3]~18_combout = (\z80_|alu_|db_high[3]~15_combout & (\z80_|alu_|db_high[3]~16_combout & ((\z80_|alu_|db_high[3]~17_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) - - .dataa(\z80_|alu_|db_high[3]~15_combout ), - .datab(\z80_|alu_|db_high[3]~16_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_high[3]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~18 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[3]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~19 ( -// Equation(s): -// \z80_|alu_|db_high[3]~19_combout = ((\z80_|alu_|db_high[3]~18_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_high[3]~18_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~19 .lut_mask = 16'hF3B3; -defparam \z80_|alu_|db_high[3]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N30 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~19_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_high[3]~19_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( -// Equation(s): -// \z80_|alu_control_|db[7]~16_combout = (\z80_|alu_flags_|DFFE_inst_latch_sf~q & (!\z80_|alu_|db[7]~20_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q & ((\z80_|execute_|ctl_flags_oe~2_combout ) # -// ((!\z80_|alu_|db[7]~20_combout & \z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h7350; -defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[7]~1_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[7]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[7]~1 .lut_mask = 16'hFF40; -defparam \z80_|reg_file_|db_lo_ds[7]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( -// Equation(s): -// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~1_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~9_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datab(\z80_|reg_file_|db_lo_ds[7]~1_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h4C0C; -defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = ((!\z80_|alu_control_|db[7]~16_combout & (\z80_|alu_control_|db[7]~17_combout & \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[7]~16_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_control_|db[7]~17_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h7333; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|execute_|ctl_flags_alu~16_combout & \z80_|alu_|db_high[3]~19_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (\z80_|execute_|ctl_flags_alu~16_combout & ((\z80_|alu_|db_high[3]~19_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|execute_|ctl_flags_alu~16_combout ), - .datac(\z80_|alu_control_|db[7]~18_combout ), - .datad(\z80_|alu_|db_high[3]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hECA0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y15_N5 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( +// Location: FF_X28_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N18 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal40~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) +// Location: FF_X28_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), +// Location: LCCOMB_X28_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N28 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ) # ((\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|ir_|opcode [4] & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// !\z80_|alu_control_|sel[1]~0_combout )))) +// Location: FF_X27_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|alu_control_|sel[1]~0_combout ), +// Location: FF_X27_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hAAD8; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ))) +// Location: FF_X27_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), +// Location: FF_X28_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N10 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q ))) +// Location: FF_X28_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|alu_|alu_parity_out~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), +// Location: LCCOMB_X28_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|alu_|db[7]~21_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[7]~21_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[7]~21_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~69_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & (\z80_|reg_file_|gdfx_temp1[7]~72_combout & \z80_|reg_file_|gdfx_temp1[7]~71_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout & \z80_|reg_file_|gdfx_temp1[7]~68_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~75_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & +// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [13]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|alu_|db[5]~25_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[5]~25_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[5]~25_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~52_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N9 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~50_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), .datad(gnd), .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), + .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h5656; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X41_Y13_N11 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( // Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~11_combout ))) +// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), + .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout ) +// \z80_|address_latch_|abusz [13] = (\z80_|reg_file_|db_hi_as[5]~15_combout & !\z80_|resets_|clrpc~0_combout ) - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal62~3_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .combout(\z80_|address_latch_|abusz [13]), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'hFFFD; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0C0C; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|Q[13]~feeder ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h7000; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|alu_control_|DFFE_latch_pf_tmp~q ) # (\z80_|execute_|ctl_alu_op_low~combout ))))) - - .dataa(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|alu_parity_out~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h1E00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~38_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = ((\z80_|execute_|ctl_flags_pf_we~5_combout ) # ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_flags_xy_we~11_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & \z80_|execute_|ctl_flags_alu~16_combout ) +// \z80_|address_latch_|Q[13]~feeder_combout = \z80_|address_latch_|abusz [13] .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [13]), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .combout(\z80_|address_latch_|Q[13]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'hF000; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|Q[13]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[13]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~19_combout )) +// Location: FF_X28_Y16_N23 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[13]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ) + + .dataa(gnd), .datab(gnd), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|address_latch_|Q [13]), + .datad(\z80_|execute_|ctl_inc_dec~11_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'h000A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~11 ( +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~11_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout )) # (!\z80_|pla_decode_|Equal69~0_combout ))) +// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~21_combout & !\z80_|resets_|clrpc~0_combout ) - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout ), + .combout(\z80_|address_latch_|abusz [15]), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~11 .lut_mask = 16'h8A0A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~11 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [9] & (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & !\z80_|address_latch_|Q [8]))) - - .dataa(\z80_|address_latch_|Q [9]), - .datab(\z80_|address_latch_|Q [10]), - .datac(\z80_|address_latch_|Q [11]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [1] & (!\z80_|address_latch_|Q [2] & !\z80_|address_latch_|Q [3]))) - - .dataa(\z80_|address_latch_|Q [0]), - .datab(\z80_|address_latch_|Q [1]), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [7] & !\z80_|address_latch_|Q [5]))) - - .dataa(\z80_|address_latch_|Q [6]), - .datab(\z80_|address_latch_|Q [4]), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|Q [5]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N15 +// Location: FF_X28_Y16_N27 dffeas \z80_|address_latch_|Q[15] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_latch_|abusz [15]), @@ -36161,15 +29033,4509 @@ defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; defparam \z80_|address_latch_|Q[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N0 +// Location: LCCOMB_X28_Y16_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|execute_|ctl_inc_dec~11_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|alu_|db[6]~23_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[6]~23_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[6]~23_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & (\z80_|reg_file_|gdfx_temp1[6]~78_combout & \z80_|reg_file_|gdfx_temp1[6]~81_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~76_combout & (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .datab(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|Q[14]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[14]~feeder_combout = \z80_|address_latch_|abusz [14] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [14]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N5 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[14]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [14]), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3363; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( +// Equation(s): +// \z80_|alu_|db[7]~20_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .datad(\z80_|alu_control_|db[7]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db[7]~21 ( +// Equation(s): +// \z80_|alu_|db[7]~21_combout = ((\z80_|alu_|db[7]~20_combout & ((\z80_|alu_|db_high[3]~8_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|alu_|db[7]~26_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~21 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[7]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N22 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~21_combout & ((\z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & +// (\z80_|alu_|db[7]~21_combout )))) + + .dataa(\z80_|alu_|db[7]~21_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_|db[0]~19_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB822; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|alu_control_|db[0]~12_combout & (\z80_|execute_|ctl_flags_bus~combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & +// ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[0]~12_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hD5C0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hE000; +defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y9_N3 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N0 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N4 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) + + .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCCEE; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~23_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(\z80_|alu_|db[6]~23_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~5_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~21_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(\z80_|alu_|db_high[3]~5_combout ), + .datac(\z80_|alu_|db[7]~21_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op2_high [3] & (((\z80_|alu_|op1_high [3])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_high [3] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [3]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_high [3]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~27 ( +// Equation(s): +// \z80_|alu_|db_high[3]~27_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~27 .lut_mask = 16'hD555; +defparam \z80_|alu_|db_high[3]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~27_combout & ((\z80_|alu_|db_high[3]~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[3]~6_combout ), + .datab(\z80_|alu_|db_high[3]~4_combout ), + .datac(\z80_|alu_|db_high[3]~27_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'h80C0; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~8 ( +// Equation(s): +// \z80_|alu_|db_high[3]~8_combout = ((\z80_|alu_|db_high[3]~7_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~8 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~8_combout )))) + + .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .lut_mask = 16'h00EA; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N15 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~9 ( +// Equation(s): +// \z80_|alu_|db_low[3]~9_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~9 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_low[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~10 ( +// Equation(s): +// \z80_|alu_|db_low[3]~10_combout = (\z80_|alu_|db_low[3]~9_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~15_combout ), + .datab(\z80_|alu_|db_low[3]~9_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~10 .lut_mask = 16'h4C0C; +defparam \z80_|alu_|db_low[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N15 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( +// Equation(s): +// \z80_|alu_|db_low[3]~7_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~17_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) + + .dataa(\z80_|alu_|db[4]~17_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( +// Equation(s): +// \z80_|alu_|db_low[3]~8_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~7_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~11_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|alu_|db[3]~11_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_low[3]~7_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~11 ( +// Equation(s): +// \z80_|alu_|db_low[3]~11_combout = (\z80_|alu_|db_low[3]~10_combout & (\z80_|alu_|db_low[3]~8_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[3]~10_combout ), + .datab(\z80_|alu_|result_lo [3]), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|db_low[3]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~11 .lut_mask = 16'hA800; +defparam \z80_|alu_|db_low[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( +// Equation(s): +// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_high[3]~2_combout ), + .datac(\z80_|alu_|db_low[3]~11_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hF1F1; +defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N12 +cycloneive_lcell_comb \z80_|alu_|db[3]~10 ( +// Equation(s): +// \z80_|alu_|db[3]~10_combout = (\z80_|execute_|ctl_alu_oe~14_combout & (\z80_|alu_|db_low[3]~25_combout & ((\z80_|reg_file_|gdfx_temp1[3]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~14_combout & +// (((\z80_|reg_file_|gdfx_temp1[3]~48_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datad(\z80_|alu_|db_low[3]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~10 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|db[3]~11 ( +// Equation(s): +// \z80_|alu_|db[3]~11_combout = ((\z80_|alu_|db[3]~10_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[3]~10_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[3]~35_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~11 .lut_mask = 16'hA2FF; +defparam \z80_|alu_|db[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~9_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~3_combout ), + .datac(\z80_|execute_|ctl_alu_oe~9_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0070; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~14_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|setM1~49_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_|db_low[3]~25_combout & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[3]~35_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_low[3]~25_combout & +// (\z80_|alu_control_|db[3]~35_combout & (\z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_|db_low[3]~25_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hEAC0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00CC; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|pla_decode_|Equal56~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # +// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N31 +dffeas \z80_|alu_flags_|flags_xf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_xf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( +// Equation(s): +// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|alu_flags_|flags_xf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF030; +defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N16 +cycloneive_lcell_comb \z80_|sw1_|db_down[3]~1 ( +// Equation(s): +// \z80_|sw1_|db_down[3]~1_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[3]~1 .lut_mask = 16'hFF8C; +defparam \z80_|sw1_|db_down[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( +// Equation(s): +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~1_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datab(\z80_|alu_control_|db[3]~33_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|sw1_|db_down[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8C00; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~11_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_|db[3]~11_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[3]~34_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N3 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N17 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [3]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h40BF; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout )))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h6AAA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N27 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N9 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|alu_control_|db[4]~32_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~59_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & \z80_|reg_file_|gdfx_temp0[4]~56_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp0[4]~62_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hCC0C; +defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N23 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [4]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|address_latch_|Q [4]), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0F4B; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout +// ))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h6A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N5 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|alu_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N3 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~68_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hF050; +defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N27 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5595; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|alu_control_|db[6]~22_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N5 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & \z80_|reg_file_|gdfx_temp0[6]~75_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N23 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout ))))) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h001E; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hF575; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|alu_control_|db[7]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[7]~0_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[7]~0 .lut_mask = 16'hF0F8; +defparam \z80_|reg_file_|db_lo_ds[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N11 +dffeas \z80_|interrupts_|im2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|interrupts_|im2~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( +// Equation(s): +// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|reg_file_|db_lo_ds[7]~0_combout ), + .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|bus_control_|db[7]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2A0A; +defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( +// Equation(s): +// \z80_|alu_control_|db[7]~16_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[7]~21_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (\z80_|execute_|ctl_sw_2u~7_combout & (!\z80_|alu_|db[7]~21_combout ))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_|db[7]~21_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h0CAE; +defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( +// Equation(s): +// \z80_|alu_control_|db[7]~18_combout = ((\z80_|alu_control_|db[7]~17_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & !\z80_|alu_control_|db[7]~16_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[7]~17_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|alu_control_|db[7]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h33B3; +defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[7]~18_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y9_N9 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal62~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h008C; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (\z80_|execute_|ctl_flags_pf_we~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_pf_sel[0]~3_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~11_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & (\z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[2]~29_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datad(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'h88F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal62~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3070; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h152A; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h3B00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N24 cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( // Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [15] & (!\z80_|address_latch_|Q [13] & !\z80_|address_latch_|Q [12]))) +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [13]))) .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|address_latch_|Q [15]), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|Q [12]), + .datab(\z80_|address_latch_|Q [12]), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|Q [13]), .cin(gnd), .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), .cout()); @@ -36178,15 +33544,66 @@ defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y12_N0 +// Location: LCCOMB_X30_Y17_N16 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [2]))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|address_latch_|Q [3]), + .datad(\z80_|address_latch_|Q [2]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0004; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & !\z80_|address_latch_|Q [4]))) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(\z80_|address_latch_|Q [6]), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|address_latch_|Q [4]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [8]))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [11]), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [8]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N18 cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( // Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~0_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~1_combout ))) - .dataa(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .dataa(\z80_|decode_state_|DFFE_instNonRep~0_combout ), .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), .datac(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~1_combout ), .cin(gnd), .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), .cout()); @@ -36195,7 +33612,7 @@ defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N28 +// Location: LCCOMB_X32_Y16_N16 cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( // Equation(s): // \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & @@ -36213,7 +33630,7 @@ defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X41_Y13_N29 +// Location: FF_X32_Y16_N17 dffeas \z80_|decode_state_|DFFE_instNonRep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), @@ -36232,133 +33649,220 @@ defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~12 ( +// Location: LCCOMB_X32_Y16_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout & (((!\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout & -// (((\z80_|decode_state_|DFFE_instNonRep~q )))) +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout ), - .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~12 .lut_mask = 16'h7F2A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'h02AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N8 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .dataa(\z80_|pla_decode_|Equal62~3_combout ), .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h152A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0040; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'h40CC; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~14 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~14_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~14 .lut_mask = 16'hFF01; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N0 +// Location: LCCOMB_X32_Y16_N10 cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[2]~22_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datab(\z80_|execute_|ctl_flags_bus~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|alu_control_|db[2]~22_combout ), + .dataa(\z80_|interrupts_|DFFE_instIFF2~q ), + .datab(\z80_|decode_state_|DFFE_instNonRep~q ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), .cin(gnd), .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hD850; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hA030; defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~13 ( +// Location: LCCOMB_X32_Y16_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~13_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # (\z80_|alu_flags_|DFFE_inst_latch_pf~14_combout -// )))) +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h808C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N23 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & +// \z80_|alu_|alu_op1[1]~0_combout )))) # (!\z80_|alu_|alu_op2[1]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|alu_op1[1]~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hFB20; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hA55A; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( +// Equation(s): +// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datad(\z80_|alu_|alu_parity_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out .lut_mask = 16'hA956; +defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal62~3_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFEF; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h20A0; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datac(\z80_|alu_|alu_parity_out~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~13_combout ), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~13 .lut_mask = 16'hFFC8; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~13 .sum_lutc_input = "datac"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X41_Y15_N27 +// Location: LCCOMB_X36_Y11_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hECCC; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N15 dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~13_combout ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -36374,34 +33878,190 @@ defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N26 +// Location: LCCOMB_X37_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[1]~20_combout & (!\z80_|alu_|db_high[3]~8_combout & (!\z80_|alu_|db_high[2]~14_combout & !\z80_|alu_|db_high[0]~26_combout ))) + + .dataa(\z80_|alu_|db_high[1]~20_combout ), + .datab(\z80_|alu_|db_high[3]~8_combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|alu_|db_high[0]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) + + .dataa(\z80_|alu_control_|db[6]~22_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hAA00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~11_combout & (\z80_|alu_|db_high[3]~3_combout & ((!\z80_|alu_|db_low[2]~3_combout ) # (!\z80_|alu_|db_low[2]~6_combout )))) + + .dataa(\z80_|alu_|db_low[2]~6_combout ), + .datab(\z80_|alu_|db_low[3]~11_combout ), + .datac(\z80_|alu_|db_low[2]~3_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h1300; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~17_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[0]~23_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) + + .dataa(\z80_|alu_|db_low[1]~17_combout ), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|alu_|db_low[0]~23_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hEC00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N27 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] +// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N18 cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( // Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ) # ((!\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|alu_control_|sel[1]~0_combout )))) +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|alu_control_|sel[1]~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), .cin(gnd), .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hB8CC; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N24 +// Location: LCCOMB_X37_Y11_N20 cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( // Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout $ (((!\z80_|ir_|opcode [3]))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & // (((\z80_|alu_control_|flags_cond_true~q )))) - .dataa(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .dataa(\z80_|ir_|opcode [3]), .datab(\z80_|execute_|ctl_eval_cond~0_combout ), .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), .cin(gnd), .combout(\z80_|alu_control_|flags_cond_true~0_combout ), .cout()); @@ -36410,7 +34070,7 @@ defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y16_N25 +// Location: FF_X37_Y11_N21 dffeas \z80_|alu_control_|flags_cond_true ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|alu_control_|flags_cond_true~0_combout ), @@ -36429,32 +34089,32 @@ defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Location: LCCOMB_X35_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( // Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ixy_d~5_combout ) +// \z80_|execute_|ctl_reg_sel_wz~13_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - .dataa(\z80_|execute_|ixy_d~5_combout ), + .dataa(\z80_|pla_decode_|Equal35~0_combout ), .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), .datad(\z80_|pla_decode_|Equal34~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y15_N16 +// Location: LCCOMB_X35_Y16_N18 cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( // Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~10_combout ) +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - .dataa(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~13_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), .cout()); @@ -36463,3091 +34123,2050 @@ defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'hF7FF; defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y15_N4 +// Location: LCCOMB_X34_Y14_N0 cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( // Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (((\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~16_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) - .dataa(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~11_combout ), .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hBFFF; defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~17_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Location: LCCOMB_X30_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Location: LCCOMB_X29_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Location: LCCOMB_X30_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~16_combout ) # ((\z80_|execute_|ctl_sw_4u~5_combout ) # (\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( +// Location: FF_X30_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( +// Location: FF_X31_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~32 ( +// Location: LCCOMB_X31_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~32_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~32 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~32 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( +// Location: FF_X31_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~13 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) +// Location: FF_X30_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), +// Location: FF_X30_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~13 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~13 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~33 ( +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~33_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~33 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~33 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( +// Location: FF_X30_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y15_N3 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~36 ( +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|alu_control_|db[1]~26_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~36_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~36 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~36 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( +// Location: FF_X28_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X35_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~34 ( +// Location: LCCOMB_X28_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~34 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~35_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[1]~16_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~35 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~37_combout = (\z80_|reg_file_|gdfx_temp1[1]~33_combout & (\z80_|reg_file_|gdfx_temp1[1]~36_combout & (\z80_|reg_file_|gdfx_temp1[1]~34_combout & \z80_|reg_file_|gdfx_temp1[1]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~33_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~36_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~34_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~39_combout +// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( +// Location: FF_X28_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~31 ( +// Location: LCCOMB_X28_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~31_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~31_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~31 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[1]~31 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~38 ( +// Location: LCCOMB_X31_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~38_combout = (\z80_|reg_file_|gdfx_temp1[1]~32_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~37_combout & \z80_|reg_file_|gdfx_temp1[1]~31_combout ))) +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~29_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - .dataa(\z80_|reg_file_|gdfx_temp1[1]~32_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~37_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~31_combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~38_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~38 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~39 ( +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~39_combout = ((\z80_|reg_file_|gdfx_temp1[1]~38_combout & ((\z80_|reg_file_|db_hi_as[1]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~39 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp1[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~7_combout = (\z80_|reg_file_|gdfx_temp1[1]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[1]~39_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~7 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~8_combout = (\z80_|reg_file_|db_hi_as[1]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[1]~7_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~8 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|execute_|ctl_inc_dec~8_combout & (!\z80_|address_latch_|Q [7] & !\z80_|address_latch_|Q -// [8])) # (!\z80_|execute_|ctl_inc_dec~8_combout & (\z80_|address_latch_|Q [7] & \z80_|address_latch_|Q [8])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) +// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout .dataa(gnd), .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~9_combout = ((\z80_|reg_file_|db_hi_as[1]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[1]~8_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~9 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~9_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y11_N27 -dffeas \z80_|address_latch_|Q[9] ( +// Location: FF_X29_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [9]), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q -// [9]))))) - - .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), - .datab(\z80_|address_latch_|Q [10]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( +// Location: FF_X29_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~18_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~16 ( +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( // Equation(s): -// \z80_|reg_file_|db_hi_as[2]~16_combout = (\z80_|reg_file_|gdfx_temp1[2]~66_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[2]~66_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - .dataa(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~16_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~16 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[2]~16 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( +// Location: FF_X30_Y13_N23 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~18_combout ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hF733; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hF0F8; +defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( +// Equation(s): +// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|bus_control_|db[1]~11_combout ), + .datab(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0C8C; +defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( +// Equation(s): +// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[1]~13_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[1]~13_combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_|db[1]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0ACE; +defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( +// Equation(s): +// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~23_combout & !\z80_|alu_control_|db[1]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[1]~25_combout ), + .datab(\z80_|alu_control_|db[2]~23_combout ), + .datac(\z80_|alu_control_|db[6]~11_combout ), + .datad(\z80_|alu_control_|db[1]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h0F8F; +defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|db[1]~12 ( +// Equation(s): +// \z80_|alu_|db[1]~12_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[1]~26_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[1]~26_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~12 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db[1]~13 ( +// Equation(s): +// \z80_|alu_|db[1]~13_combout = ((\z80_|alu_|db[1]~12_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[1]~12_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~13 .lut_mask = 16'hA2FF; +defparam \z80_|alu_|db[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( +// Equation(s): +// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~13_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|alu_|db[1]~13_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF5A0; +defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( +// Equation(s): +// \z80_|alu_|db_low[0]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~19_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[0]~21_combout ), + .datac(\z80_|alu_|db[0]~19_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( +// Equation(s): +// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h5557; +defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( +// Equation(s): +// \z80_|alu_|db_low[0]~19_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op1_low [0]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N25 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( +// Equation(s): +// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~18_combout & (\z80_|alu_|db_low[0]~19_combout & ((\z80_|alu_|result_lo [0]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[0]~18_combout ), + .datab(\z80_|alu_|db_low[0]~19_combout ), + .datac(\z80_|alu_|result_lo [0]), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( +// Equation(s): +// \z80_|alu_|db_low[0]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & ((\z80_|alu_|db_low[0]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~20_combout ) # +// (!\z80_|alu_|db_high[3]~2_combout )))) + + .dataa(\z80_|alu_|db_low[0]~22_combout ), + .datab(\z80_|alu_|db_high[3]~2_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[0]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hAF03; +defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( +// Equation(s): +// \z80_|alu_|db[0]~18_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_|db_low[0]~23_combout ) # ((!\z80_|execute_|ctl_alu_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_|db_low[0]~23_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db[0]~19 ( +// Equation(s): +// \z80_|alu_|db[0]~19_combout = ((\z80_|alu_|db[0]~18_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[0]~12_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~19 .lut_mask = 16'hA2FF; +defparam \z80_|alu_|db[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( +// Equation(s): +// \z80_|alu_|db_low[1]~15_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~19_combout )) + + .dataa(\z80_|alu_|db[0]~19_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( +// Equation(s): +// \z80_|alu_|db_low[1]~16_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[1]~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[1]~13_combout ))) + + .dataa(\z80_|alu_|db_low[1]~15_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[1]~13_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAAF0; +defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( +// Equation(s): +// \z80_|alu_|db_low[1]~12_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'h5755; +defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( +// Equation(s): +// \z80_|alu_|db_low[1]~13_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op1_low [1]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N21 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( +// Equation(s): +// \z80_|alu_|db_low[1]~14_combout = (\z80_|alu_|db_low[1]~12_combout & (\z80_|alu_|db_low[1]~13_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[1]~12_combout ), + .datab(\z80_|alu_|db_low[1]~13_combout ), + .datac(\z80_|alu_|result_lo [1]), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( +// Equation(s): +// \z80_|alu_|db_low[1]~17_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~16_combout & \z80_|alu_|db_low[1]~14_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~14_combout )) # +// (!\z80_|alu_|db_high[3]~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_high[3]~2_combout ), + .datac(\z80_|alu_|db_low[1]~16_combout ), + .datad(\z80_|alu_|db_low[1]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hF511; +defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_low[1]~17_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[1]~20_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00F0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N1 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .q(\z80_|alu_|op1_low [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~17 ( +// Location: LCCOMB_X36_Y10_N28 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( // Equation(s): -// \z80_|reg_file_|db_hi_as[2]~17_combout = (\z80_|reg_file_|db_hi_as[2]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) - .dataa(\z80_|reg_file_|db_hi_as[2]~16_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .dataa(gnd), + .datab(\z80_|alu_|op1_low [1]), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|alu_|op1_low [2]), .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~17_combout ), + .combout(\z80_|alu_control_|out[6]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~17 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[2]~17 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0C0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~18 ( +// Location: LCCOMB_X36_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( // Equation(s): -// \z80_|reg_file_|db_hi_as[2]~18_combout = ((\z80_|reg_file_|db_hi_as[2]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout ) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~17_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~18 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_hi_as[2]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~18_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), + .dataa(gnd), .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[2]~18_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N8 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|alu_control_|db[4]~32_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N9 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( +// Equation(s): +// \z80_|alu_control_|db[2]~23_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|alu_flags_|flags_hf2~q ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~combout ), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|alu_flags_|flags_hf2~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFEF; +defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|bus_control_|db[2]~13_combout ), + .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h2F00; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( +// Equation(s): +// \z80_|alu_control_|db[2]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[2]~15_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (!\z80_|alu_|db[2]~15_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|alu_|db[2]~15_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h3B0A; +defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( +// Equation(s): +// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~23_combout & (\z80_|alu_control_|db[2]~28_combout & !\z80_|alu_control_|db[2]~27_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[6]~11_combout ), + .datab(\z80_|alu_control_|db[2]~23_combout ), + .datac(\z80_|alu_control_|db[2]~28_combout ), + .datad(\z80_|alu_control_|db[2]~27_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h55D5; +defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db[2]~14 ( +// Equation(s): +// \z80_|alu_|db[2]~14_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~39_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[2]~29_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[2]~29_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~14 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[2]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( +// Equation(s): +// \z80_|alu_|db[2]~15_combout = ((\z80_|alu_|db[2]~14_combout & ((\z80_|alu_|db_low[2]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db_low[2]~24_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[2]~14_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~2 ( +// Equation(s): +// \z80_|alu_|db_low[2]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~13_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|alu_|db[3]~11_combout ), + .datac(\z80_|alu_|db[1]~13_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), + .combout(\z80_|alu_|db_low[2]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~2 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|db_low[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N31 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [10]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Location: LCCOMB_X35_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~3 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~8_combout & (!\z80_|address_latch_|Q [10] & -// !\z80_|address_latch_|Q [9])) # (!\z80_|execute_|ctl_inc_dec~8_combout & (\z80_|address_latch_|Q [10] & \z80_|address_latch_|Q [9])))) +// \z80_|alu_|db_low[2]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~15_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), - .datab(\z80_|address_latch_|Q [10]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .dataa(\z80_|alu_|db[2]~15_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_low[2]~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .combout(\z80_|alu_|db_low[2]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h4200; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~3 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_low[2]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Location: LCCOMB_X35_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [11] & (!\z80_|execute_|ctl_inc_dec~8_combout & -// \z80_|address_latch_|Q [12])) # (!\z80_|address_latch_|Q [11] & (\z80_|execute_|ctl_inc_dec~8_combout & !\z80_|address_latch_|Q [12])))) +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|Q [12]), + .dataa(\z80_|alu_|db_low[2]~6_combout ), + .datab(\z80_|alu_|db_high[3]~3_combout ), + .datac(\z80_|alu_|db_low[2]~3_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0820; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hB300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Location: LCCOMB_X36_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - .dataa(gnd), - .datab(\z80_|address_latch_|Q [13]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h33CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3222; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [5] & ((\z80_|reg_file_|gdfx_temp1[5]~75_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[5]~75_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~19 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[5]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~20_combout = (\z80_|reg_file_|db_hi_as[5]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datad(\z80_|reg_file_|db_hi_as[5]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~20 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_hi_as[5]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~21_combout = ((\z80_|reg_file_|db_hi_as[5]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~21 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[5]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~21_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N27 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [13]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [13]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|Q [13]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~7_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~4_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [7] & ((\z80_|reg_file_|gdfx_temp1[7]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[7]~30_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~4 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|db_hi_as[7]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~5_combout = (\z80_|reg_file_|db_hi_as[7]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[7]~4_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~5 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[7]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~6_combout = ((\z80_|reg_file_|db_hi_as[7]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .datab(\z80_|reg_file_|db_hi_as[7]~5_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~6 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_hi_as[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~6_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h0A0A; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|execute_|ctl_inc_dec~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|execute_|ctl_apin_mux~1_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'hF333; -defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|address_latch_|abusz [15]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0D0D; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ctl_mWrite~2_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~15_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & !\z80_|execute_|fIOWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|fIORead~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( -// Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|ctl_mRead~7_combout & \z80_|execute_|fIOWrite~3_combout ))) - - .dataa(\z80_|execute_|fIORead~2_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|fIOWrite~3_combout ), - .datad(\z80_|execute_|fIORead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N14 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fMRead~36_combout ) # (((\z80_|execute_|fIORead~3_combout ) # (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )) - - .dataa(\z80_|execute_|fMRead~36_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFBF; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout ) # -// ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h4F44; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( +// Location: FF_X36_Y10_N25 +dffeas \z80_|alu_|op1_low[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~17 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[15]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~15_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0030; -defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h0202; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg -// [6] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|WideOr17~0_combout & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|WideOr17~0_combout ), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0088; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~0_combout ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N13 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), + .q(\z80_|alu_|op1_low [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Location: LCCOMB_X37_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [2])) +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [2]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Location: LCCOMB_X37_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~41_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q ))) +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ) # ((\z80_|alu_|db_low[2]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|extended~q ), + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), + .datac(\z80_|alu_|db_low[2]~24_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|zx_keyboard_|keys[6][1]~42_combout & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & (!\ula_|zx_keyboard_|keys[6][1]~40_combout )) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & ((\ula_|zx_keyboard_|keys[6][1]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N31 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( +// Location: FF_X37_Y10_N13 +dffeas \z80_|alu_|op2_low[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~16 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[14]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \D[1]~27 ( -// Equation(s): -// \D[1]~27_combout = (\ula_|zx_keyboard_|keys[7][1]~q & (\z80_|address_pins_|abus[15]~17_combout & ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[7][1]~q & -// (((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~q ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\z80_|address_pins_|abus[14]~16_combout ), - .cin(gnd), - .combout(\D[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~27 .lut_mask = 16'hDD0D; -defparam \D[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~19_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~19 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|keys[7][1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hF000; -defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|keys[5][4]~24_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~26_combout = (\ula_|zx_keyboard_|keys[1][4]~25_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h0C00; -defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N11 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .q(\z80_|alu_|op2_low [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Location: LCCOMB_X38_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) +// \z80_|alu_|db_low[2]~5_combout = (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - .dataa(\z80_|address_latch_|abusz [10]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .dataa(\z80_|alu_|op2_low [2]), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .combout(\z80_|alu_|db_low[2]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'h8ACF; +defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), +// Location: FF_X39_Y10_N13 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [10]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~22 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[10]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00A0; -defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~28_combout = (\ula_|zx_keyboard_|keys[5][4]~24_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[7][1]~19_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N9 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .q(\z80_|alu_|result_lo [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Location: LCCOMB_X35_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) +// \z80_|alu_|db_low[2]~6_combout = (\z80_|alu_|db_low[2]~4_combout & (\z80_|alu_|db_low[2]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2])))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|address_latch_|abusz [11]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|alu_|db_low[2]~4_combout ), + .datab(\z80_|alu_|db_low[2]~5_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|result_lo [2]), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .combout(\z80_|alu_|db_low[2]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N23 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( +// Location: LCCOMB_X35_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) + + .dataa(\z80_|alu_|db_low[2]~6_combout ), + .datab(\z80_|alu_|db_low[2]~3_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h80F0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N27 +dffeas \z80_|alu_|op2_high[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [11]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~21 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[11]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N2 -cycloneive_lcell_comb \D[1]~25 ( -// Equation(s): -// \D[1]~25_combout = (\ula_|zx_keyboard_|keys[2][1]~q & (\z80_|address_pins_|abus[10]~22_combout & ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) # (!\ula_|zx_keyboard_|keys[2][1]~q & -// (((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[2][1]~q ), - .datab(\z80_|address_pins_|abus[10]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\z80_|address_pins_|abus[11]~21_combout ), - .cin(gnd), - .combout(\D[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~25 .lut_mask = 16'hDD0D; -defparam \D[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~31_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h5050; -defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~32_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h1100; -defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][2]~32_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N5 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .q(\z80_|alu_|op2_high [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Location: LCCOMB_X38_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [12]))) +// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [12]), + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|alu_|op2_low [2]), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .combout(\z80_|alu_|alu_op2[2]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h4B78; +defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y2_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~24 ( +// Location: LCCOMB_X39_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( // Equation(s): -// \z80_|address_pins_|abus[12]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [12]), + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~24_combout ), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[12]~24 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[12]~24 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0BFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Location: LCCOMB_X39_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [13])) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~2_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - .dataa(\z80_|address_latch_|abusz [13]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|alu_op1[2]~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N3 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~23 ( +// Location: LCCOMB_X34_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( // Equation(s): -// \z80_|address_pins_|abus[13]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_|db_high[2]~9_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - .dataa(gnd), + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'h55D5; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~21_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~25_combout )) + + .dataa(\z80_|ir_|opcode [3]), .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|alu_|db[5]~25_combout ), + .datad(\z80_|alu_|db[7]~21_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~23_combout ), + .combout(\z80_|alu_|db_high[2]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[13]~23 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[13]~23 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hFA50; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( +// Location: LCCOMB_X35_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0011; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|ps2_keyboard_|shiftreg [4])) +// \z80_|alu_|db_high[2]~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[2]~11_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[6]~23_combout ))) .dataa(gnd), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\z80_|alu_|db_high[2]~11_combout ), + .datac(\z80_|alu_|db[6]~23_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .combout(\z80_|alu_|db_high[2]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0030; -defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Location: LCCOMB_X38_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [6])) +// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_high [2]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .combout(\z80_|alu_|db_high[2]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'h8800; -defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Location: LCCOMB_X34_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) +// \z80_|alu_|db_high[2]~13_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~12_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(gnd), + .dataa(\z80_|alu_|db_high[2]~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[2]~12_combout ), + .datad(\z80_|alu_|db_high[2]~10_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .combout(\z80_|alu_|db_high[2]~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( +// Location: LCCOMB_X35_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~14 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~38_combout & ((\ula_|zx_keyboard_|keys[5][1]~37_combout & ((!\ula_|zx_keyboard_|keys[5][1]~35_combout ))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & -// (\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) +// \z80_|alu_|db_high[2]~14_combout = ((\z80_|alu_|db_high[2]~13_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - .dataa(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .datab(\z80_|alu_|db_high[3]~3_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|db_high[2]~13_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .combout(\z80_|alu_|db_high[2]~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~14 .lut_mask = 16'hFB33; +defparam \z80_|alu_|db_high[2]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y13_N29 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \D[1]~26 ( +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( // Equation(s): -// \D[1]~26_combout = (\ula_|zx_keyboard_|keys[4][1]~q & (\z80_|address_pins_|abus[12]~24_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\ula_|zx_keyboard_|keys[4][1]~q & -// (((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) +// \z80_|alu_|db[6]~22_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - .dataa(\ula_|zx_keyboard_|keys[4][1]~q ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[5][1]~q ), + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .datad(\z80_|alu_control_|db[6]~22_combout ), .cin(gnd), - .combout(\D[1]~26_combout ), + .combout(\z80_|alu_|db[6]~22_combout ), .cout()); // synopsys translate_off -defparam \D[1]~26 .lut_mask = 16'hD0DD; -defparam \D[1]~26 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db[6]~23 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [9])) +// \z80_|alu_|db[6]~23_combout = ((\z80_|alu_|db[6]~22_combout & ((\z80_|alu_|db_high[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - .dataa(\z80_|address_latch_|abusz [9]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|alu_|db_high[2]~14_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .combout(\z80_|alu_|db[6]~23_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db[6]~23 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[6]~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y3_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~19 ( +// Location: LCCOMB_X36_Y10_N10 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( // Equation(s): -// \z80_|address_pins_|abus[9]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|alu_|op1_high [1]), + .datad(\z80_|alu_control_|out[6]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N26 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) + + .dataa(\z80_|execute_|ctl_66_oe~combout ), + .datab(\z80_|alu_control_|out[6]~1_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEA; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~19 ( +// Equation(s): +// \z80_|alu_control_|db[6]~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & +// (!\z80_|execute_|ctl_flags_oe~2_combout & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|out[6]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~19 .lut_mask = 16'hAF8C; +defparam \z80_|alu_control_|db[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( +// Equation(s): +// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_control_|db[6]~19_combout & ((\z80_|alu_|db[6]~23_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [9]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|alu_|db[6]~23_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[6]~19_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~19_combout ), + .combout(\z80_|alu_control_|db[6]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[9]~19 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[9]~19 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'hCF00; +defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Location: LCCOMB_X34_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) +// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|db[6]~20_combout & (((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - .dataa(\z80_|address_latch_|abusz [8]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|bus_control_|db[6]~9_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|alu_control_|db[6]~20_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .combout(\z80_|alu_control_|db[6]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h30B0; +defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N27 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~20 ( +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( // Equation(s): -// \z80_|address_pins_|abus[8]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_control_|db[6]~22_combout = ((\z80_|alu_control_|db[6]~21_combout & ((\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [8]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|alu_control_|db[6]~11_combout ), + .datab(\z80_|alu_control_|db[6]~21_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~20_combout ), + .combout(\z80_|alu_control_|db[6]~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[8]~20 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[8]~20 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hD5DD; +defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Location: LCCOMB_X39_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) +// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - .dataa(gnd), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hF0F3; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0028; -defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2400; -defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & -// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N1 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~20_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~20 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|keys[1][1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~21 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~21_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~21 .lut_mask = 16'h3000; -defparam \ula_|zx_keyboard_|keys[6][4]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~21_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~23_combout = (\ula_|zx_keyboard_|keys[1][1]~20_combout & ((\ula_|zx_keyboard_|keys[1][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~22_combout & ((\ula_|zx_keyboard_|keys[1][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[1][1]~20_combout & (((\ula_|zx_keyboard_|keys[1][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[1][1]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~23 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[1][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y14_N7 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~23_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N0 -cycloneive_lcell_comb \D[1]~24 ( -// Equation(s): -// \D[1]~24_combout = (\z80_|address_pins_|abus[9]~19_combout & ((\z80_|address_pins_|abus[8]~20_combout ) # ((!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\z80_|address_pins_|abus[9]~19_combout & (!\ula_|zx_keyboard_|keys[1][1]~q & -// ((\z80_|address_pins_|abus[8]~20_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~19_combout ), - .datab(\z80_|address_pins_|abus[8]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[1][1]~q ), - .cin(gnd), - .combout(\D[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~24 .lut_mask = 16'h8ACF; -defparam \D[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N4 -cycloneive_lcell_comb \D[1]~28 ( -// Equation(s): -// \D[1]~28_combout = (\D[1]~27_combout & (\D[1]~25_combout & (\D[1]~26_combout & \D[1]~24_combout ))) - - .dataa(\D[1]~27_combout ), - .datab(\D[1]~25_combout ), - .datac(\D[1]~26_combout ), - .datad(\D[1]~24_combout ), - .cin(gnd), - .combout(\D[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~28 .lut_mask = 16'h8000; -defparam \D[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y14_N0 -cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( -// Equation(s): -// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; -defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y14_N1 -dffeas \z80_|clk_delay_|DFF_inst5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|DFF_inst5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y14_N26 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y14_N27 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; -// synopsys translate_on - -// Location: FF_X52_Y14_N5 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = ((!\z80_|execute_|ctl_mRead~38_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'h337F; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_iorw~12_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_iorw~12_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), + .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hC800; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Location: LCCOMB_X34_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( // Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~13_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~6_combout ) +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) - .dataa(\z80_|execute_|nextM~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[3]~21_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h00CC; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N25 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( +// Location: FF_X34_Y10_N9 +dffeas \z80_|interrupts_|im1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(\z80_|execute_|ctl_im_we~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .q(\z80_|interrupts_|im1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( +// Location: LCCOMB_X32_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( // Equation(s): -// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|interrupts_|im1~q ), + .datac(\z80_|interrupts_|im2~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hDC00; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h40EE; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( +// Equation(s): +// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hFF31; +defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), + .combout(\z80_|bus_control_|db[6]~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N13 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N8 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Location: LCCOMB_X37_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( // Equation(s): -// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q +// \z80_|execute_|ctl_mRead~37_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .combout(\z80_|execute_|ctl_mRead~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N9 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X50_Y16_N3 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N2 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Location: LCCOMB_X37_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( // Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) +// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~37_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .dataa(\z80_|execute_|ctl_mRead~37_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), + .combout(\z80_|execute_|ctl_mRead~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N4 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Location: LCCOMB_X37_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( // Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ctl_mRead~28_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) - .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), - .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), + .dataa(\z80_|execute_|ctl_mRead~28_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .combout(\z80_|execute_|ctl_mRead~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( -// Equation(s): -// \z80_|execute_|setM1~38_combout = (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|fMRead~4_combout & !\z80_|pla_decode_|Equal9~1_combout )) - - .dataa(\z80_|pla_decode_|Equal29~0_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0404; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~57 ( -// Equation(s): -// \z80_|execute_|setM1~57_combout = (!\z80_|execute_|ctl_mRead~16_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~57 .lut_mask = 16'h00EF; -defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~57_combout & (\z80_|execute_|setM1~37_combout & !\z80_|execute_|ctl_mRead~18_combout ))) - - .dataa(\z80_|execute_|setM1~38_combout ), - .datab(\z80_|execute_|setM1~57_combout ), - .datac(\z80_|execute_|setM1~37_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & ((!\z80_|execute_|setM1~39_combout ) # (!\z80_|execute_|ctl_mRead~21_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_mRead~21_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h1050; -defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~35_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~14_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hEEAA; -defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~40 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~40_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal38~2_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~40 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_mRead~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~39 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~39_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~38_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~39 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_mRead~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N0 +// Location: LCCOMB_X35_Y16_N28 cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( // Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~27_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )))) +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~29_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_mRead~27_combout ), + .dataa(\z80_|execute_|ctl_mRead~29_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'h0080; defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Location: LCCOMB_X38_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( // Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~40_combout & (\z80_|execute_|ctl_mRead~26_combout & (\z80_|execute_|ctl_mRead~39_combout & \z80_|execute_|ctl_mRead~30_combout ))) +// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|ctl_al_we~4_combout & \z80_|execute_|ctl_inc_cy~41_combout ))) - .dataa(\z80_|execute_|ctl_mRead~40_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_mRead~39_combout ), - .datad(\z80_|execute_|ctl_mRead~30_combout ), + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|execute_|ctl_inc_cy~41_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), + .combout(\z80_|execute_|setM1~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~37 .lut_mask = 16'h1000; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Location: LCCOMB_X40_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( // Equation(s): -// \z80_|execute_|nextM~4_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) +// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'h3233; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (!\z80_|execute_|ctl_mRead~16_combout & (\z80_|execute_|setM1~37_combout & (\z80_|execute_|setM1~55_combout & \z80_|execute_|setM1~36_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|setM1~37_combout ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|execute_|setM1~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'h4000; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|setM1~38_combout ))) + + .dataa(\z80_|execute_|setM1~38_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|nextM~3 ( +// Equation(s): +// \z80_|execute_|nextM~3_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) .dataa(gnd), .datab(\z80_|pla_decode_|Equal41~2_combout ), .datac(\z80_|execute_|ixy_d~10_combout ), .datad(\z80_|execute_|ixy_d~16_combout ), .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), + .combout(\z80_|execute_|nextM~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0003; +defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Location: LCCOMB_X40_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( // Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|nextM~4_combout ))) +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|nextM~4_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|ctl_mRead~32_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFC0; defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( +// Location: LCCOMB_X43_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( // Equation(s): -// \z80_|execute_|ctl_mRead~37_combout = (\z80_|execute_|ctl_mRead~36_combout ) # ((\z80_|execute_|ctl_mRead~35_combout ) # ((\z80_|execute_|ctl_mRead~33_combout ) # (!\z80_|execute_|ctl_mRead~31_combout ))) +// \z80_|execute_|ctl_mRead~35_combout = ((\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (\z80_|execute_|ctl_mRead~33_combout ))) # (!\z80_|execute_|ctl_mRead~30_combout ) - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ctl_mRead~35_combout ), + .dataa(\z80_|execute_|ctl_mRead~30_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), .datac(\z80_|execute_|ctl_mRead~31_combout ), .datad(\z80_|execute_|ctl_mRead~33_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~37_combout ), + .combout(\z80_|execute_|ctl_mRead~35_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X49_Y16_N15 +// Location: FF_X43_Y17_N23 dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~37_combout ), + .d(\z80_|execute_|ctl_mRead~35_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -39563,7 +36182,7 @@ defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N22 +// Location: LCCOMB_X46_Y15_N24 cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( // Equation(s): // \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q @@ -39580,7 +36199,7 @@ defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N23 +// Location: FF_X46_Y15_N25 dffeas \z80_|memory_ifc_|wait_mrd ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), @@ -39599,7 +36218,7 @@ defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; // synopsys translate_on -// Location: FF_X50_Y16_N15 +// Location: FF_X43_Y17_N3 dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -39618,28 +36237,151 @@ defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N26 +// Location: LCCOMB_X43_Y17_N8 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( // Equation(s): // \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) .dataa(\z80_|memory_ifc_|wait_mrd~q ), .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datad(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nRD_out~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0505; +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N7 -dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( +// Location: LCCOMB_X40_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout ) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|nextM~4_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ctl_iorw~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N7 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_iorw~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( +// Equation(s): +// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N27 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y17_N9 +dffeas \z80_|memory_ifc_|wait_iorq ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|execute_|setM1~52_combout ), + .asdata(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), @@ -39647,6 +36389,129 @@ dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y17_N13 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|wait_iorq~q ), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hA800; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|fIORead~1_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFF2; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Equation(s): +// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hA080; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|fIOWrite~1_combout ), + .datab(\z80_|execute_|fIORead~2_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|fIORead~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X41_Y17_N25 +dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|setM1~52_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), .prn(vcc)); // synopsys translate_off @@ -39654,7 +36519,7 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N30 +// Location: LCCOMB_X43_Y17_N14 cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( // Equation(s): // \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q @@ -39671,7 +36536,7 @@ defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N31 +// Location: FF_X43_Y17_N15 dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), @@ -39690,7 +36555,7 @@ defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; // synopsys translate_on -// Location: FF_X50_Y16_N17 +// Location: FF_X43_Y17_N21 dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -39709,139 +36574,817 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N16 +// Location: LCCOMB_X43_Y17_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( // Equation(s): -// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & (((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|interrupts_|DFFE_inst44~q ))) # (!\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & -// (\z80_|memory_ifc_|DFFE_m1_ff3~q & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|interrupts_|DFFE_inst44~q )))) +// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|DFFE_inst44~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|DFFE_inst44~q & +// ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - .dataa(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), + .dataa(\z80_|interrupts_|DFFE_inst44~q ), + .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nRD_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFA32; +defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFC54; defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N20 +// Location: LCCOMB_X43_Y17_N18 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( // Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) +// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) .dataa(\z80_|memory_ifc_|nRD_out~1_combout ), - .datab(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|memory_ifc_|iorq~0_combout ), .datac(\z80_|execute_|fIORead~3_combout ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nRD_out~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFDDD; +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFFD5; defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N4 -cycloneive_lcell_comb \Equal2~0 ( +// Location: LCCOMB_X31_Y12_N24 +cycloneive_lcell_comb \Equal2~1 ( // Equation(s): -// \Equal2~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) +// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) - .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), .datab(\z80_|memory_ifc_|nRD_out~2_combout ), .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .datad(gnd), .cin(gnd), - .combout(\Equal2~0_combout ), + .combout(\Equal2~1_combout ), .cout()); // synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h0080; -defparam \Equal2~0 .sum_lutc_input = "datac"; +defparam \Equal2~1 .lut_mask = 16'h4040; +defparam \Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y13_N21 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N12 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~0 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram1|altsyncram_component|auto_generated|address_reg_a [0] +// \z80_|pin_control_|bus_db_pin_oe~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~0 .lut_mask = 16'hFFAA; +defparam \z80_|pin_control_|bus_db_pin_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3F33; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) + + .dataa(\z80_|execute_|fMWrite~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'h5554; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( +// Equation(s): +// \z80_|execute_|fMWrite~2_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h555F; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fMWrite~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h00EF; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~1 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~1_combout = (\z80_|execute_|ctl_bus_inc_oe~24_combout & (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|fMWrite~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .datab(\z80_|execute_|fIOWrite~5_combout ), + .datac(\z80_|execute_|fMWrite~6_combout ), + .datad(\z80_|execute_|fMWrite~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~1 .lut_mask = 16'h0002; +defparam \z80_|pin_control_|bus_db_pin_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'h135F; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|pin_control_|bus_db_pin_oe~2_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'hA2AA; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_mRead~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'h0003; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~7_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|fMWrite~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hCD00; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h0777; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|fMRead~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout )) # +// (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|fMRead~1_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h3715; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~9 ( +// Equation(s): +// \z80_|execute_|fMWrite~9_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout )) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal46~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~9 .lut_mask = 16'hCEFF; +defparam \z80_|execute_|fMWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & +// (((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fMWrite~9_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hDDD0; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|execute_|fMWrite~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout )) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datab(\z80_|execute_|fMWrite~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0808; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_state_alu~6_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & (\z80_|execute_|ctl_reg_sel_wz~5_combout & (!\z80_|execute_|fMWrite~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~5_combout ), + .datac(\z80_|execute_|fMWrite~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h0800; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~7_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~5_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|fMWrite~10 ( +// Equation(s): +// \z80_|execute_|fMWrite~10_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & +// ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~10 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & (!\z80_|execute_|fMWrite~10_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .datac(\z80_|execute_|fMWrite~10_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h0800; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2A00; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~1_combout & (\z80_|pin_control_|bus_db_pin_oe~12_combout & \z80_|execute_|ctl_inc_cy~37_combout ))) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout ))) # +// (!\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|fIOWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'hF222; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y15_N0 +cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( +// Equation(s): +// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; +defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y13_N13 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( +// Location: FF_X43_Y15_N1 +dffeas \z80_|clk_delay_|DFF_inst5 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .q(\z80_|clk_delay_|DFF_inst5~q ), .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \ExtRamWE~0 ( +// Location: LCCOMB_X43_Y15_N22 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( // Equation(s): -// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|memory_ifc_|nIORQ_out~0_combout & !\z80_|memory_ifc_|nRD_out~2_combout ))) +// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|clk_delay_|DFF_inst5~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y15_N23 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y15_N13 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y15_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datad(\z80_|memory_ifc_|iorq~0_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nIORQ_out~0_combout ))) .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datad(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h4000; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), .cin(gnd), .combout(\ExtRamWE~0_combout ), .cout()); // synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h0008; +defparam \ExtRamWE~0 .lut_mask = 16'h0020; defparam \ExtRamWE~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N10 +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [13]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0B0B; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~2_combout = (((\z80_|execute_|fMRead~35_combout ) # (\z80_|execute_|fIORead~3_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .datac(\z80_|execute_|fMRead~35_combout ), + .datad(\z80_|execute_|fIORead~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFF7; +defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pin_control_|bus_ab_pin_we~2_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T3_ff~q & +// (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h3B0A; +defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [14]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N4 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [15]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[15]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hF3F3; +defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N8 cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), .cin(gnd), .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .cout()); @@ -39850,24 +37393,41 @@ defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_m defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N8 +// Location: LCCOMB_X32_Y14_N22 cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) .dataa(gnd), .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), .cin(gnd), .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h0C00; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00C0; defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N8 +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) @@ -39884,7 +37444,7 @@ defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hDD88; defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N9 +// Location: FF_X31_Y17_N29 dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), @@ -39903,41 +37463,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N4 +// Location: LCCOMB_X31_Y18_N20 cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( // Equation(s): // \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(gnd), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [1]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [1]), .cin(gnd), .combout(\z80_|address_pins_|abus[1]~25_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hFF55; defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N8 +// Location: LCCOMB_X31_Y17_N18 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [2]))) +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [2]), .datac(gnd), - .datad(\z80_|address_latch_|abusz [2]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N9 +// Location: FF_X31_Y17_N19 dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), @@ -39956,7 +37516,7 @@ defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N16 +// Location: LCCOMB_X31_Y18_N26 cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( // Equation(s): // \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) @@ -39973,24 +37533,24 @@ defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N30 +// Location: LCCOMB_X31_Y17_N0 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) - .dataa(\z80_|address_latch_|abusz [3]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [3]), .datac(gnd), .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N31 +// Location: FF_X31_Y17_N1 dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), @@ -40009,41 +37569,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y2_N22 +// Location: LCCOMB_X31_Y18_N12 cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( // Equation(s): // \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\z80_|address_pins_|DFFE_apin_latch [3]), .cin(gnd), .combout(\z80_|address_pins_|abus[3]~27_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N4 +// Location: LCCOMB_X31_Y17_N30 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) - .dataa(\z80_|address_latch_|abusz [4]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [4]), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N5 +// Location: FF_X31_Y17_N31 dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), @@ -40062,41 +37622,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y3_N22 +// Location: LCCOMB_X31_Y18_N2 cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( // Equation(s): // \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [4]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [4]), .cin(gnd), .combout(\z80_|address_pins_|abus[4]~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N12 +// Location: LCCOMB_X30_Y16_N12 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - .dataa(\z80_|address_latch_|abusz [5]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [5]), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y13_N13 +// Location: FF_X30_Y16_N13 dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), @@ -40115,41 +37675,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N10 +// Location: LCCOMB_X29_Y17_N20 cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( // Equation(s): // \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|address_pins_|DFFE_apin_latch [5]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(gnd), .cin(gnd), .combout(\z80_|address_pins_|abus[5]~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF3F3; defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N6 +// Location: LCCOMB_X30_Y16_N10 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [6]), + .dataa(\z80_|address_latch_|abusz [6]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hCCAA; defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N7 +// Location: FF_X30_Y16_N11 dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), @@ -40168,41 +37728,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N8 +// Location: LCCOMB_X31_Y18_N28 cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( // Equation(s): // \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [6]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [6]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|address_pins_|abus[6]~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N22 +// Location: LCCOMB_X30_Y16_N30 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - .dataa(\z80_|address_latch_|abusz [7]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [7]), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y13_N23 +// Location: FF_X30_Y16_N31 dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), @@ -40221,2261 +37781,289 @@ defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N24 +// Location: LCCOMB_X31_Y18_N22 cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( // Equation(s): // \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\z80_|address_pins_|DFFE_apin_latch [7]), .cin(gnd), .combout(\z80_|address_pins_|abus[7]~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y29_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X29_Y14_N27 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~16_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N23 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (!\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), + .dataa(\z80_|address_latch_|abusz [8]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0400; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N21 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [8]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [14] & !\z80_|address_pins_|DFFE_apin_latch [13])) +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: FF_X31_Y16_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N30 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (!\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h4000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [14] & !\z80_|address_pins_|DFFE_apin_latch [13])) +// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .combout(\z80_|address_pins_|abus[9]~17_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h00C0; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N16 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout & -// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEA4A; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & !\z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N20 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datab(\z80_|address_latch_|abusz [10]), .datac(gnd), - .datad(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), - .combout(\~GND~combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), .cout()); // synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y30_N2 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) - - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0028; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N21 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y30_N25 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N2 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h00FF; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N3 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N0 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [7] $ (\ula_|video_|vga_hc [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N1 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N30 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [7]))) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'hA555; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N31 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N8 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N10 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N12 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N14 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N15 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N16 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N17 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N18 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N19 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N20 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N28 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFC30; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y30_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( -// Equation(s): -// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) - - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[9]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0028; -defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N29 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N22 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [8]), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N26 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|Add4~2_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hF3C0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N27 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N2 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [0]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h1020; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|Add4~4_combout ), - .datab(\ula_|video_|vram_address[10]~2_combout ), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hB830; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y31_N29 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N4 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N5 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N6 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|Add4~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFCFC; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N7 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y20_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X30_Y13_N27 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y13_N9 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: M9K_X33_Y9_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (!\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & !\z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0040; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y29_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \Selector1~0 ( -// Equation(s): -// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~16_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\Selector1~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~0 .lut_mask = 16'hBA98; -defparam \Selector1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \Selector1~1 ( -// Equation(s): -// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\Selector1~0_combout ), - .cin(gnd), - .combout(\Selector1~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~1 .lut_mask = 16'hBBC0; -defparam \Selector1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \D[1]~22 ( -// Equation(s): -// \D[1]~22_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector1~1_combout ))))) - - .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .datad(\Selector1~1_combout ), - .cin(gnd), - .combout(\D[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~22 .lut_mask = 16'h5140; -defparam \D[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \D[1]~23 ( -// Equation(s): -// \D[1]~23_combout = ((\z80_|memory_ifc_|nWR_out~0_combout ) # ((\D[1]~22_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[1]~22_combout ), - .cin(gnd), - .combout(\D[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~23 .lut_mask = 16'hFFDF; -defparam \D[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \D[1]~29 ( -// Equation(s): -// \D[1]~29_combout = (\D[1]~23_combout ) # ((\Equal2~0_combout & ((\z80_|address_pins_|abus[0]~18_combout ) # (\D[1]~28_combout )))) - - .dataa(\z80_|address_pins_|abus[0]~18_combout ), - .datab(\D[1]~28_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[1]~23_combout ), - .cin(gnd), - .combout(\D[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~29 .lut_mask = 16'hFFE0; -defparam \D[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \D[1]~31 ( -// Equation(s): -// \D[1]~31_combout = ((\D[1]~29_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\D[0]~30_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\D[1]~29_combout ), - .cin(gnd), - .combout(\D[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'hF755; -defparam \D[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N6 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[1]~31_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[1]~13_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[1]~13_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[1]~13_combout ), - .datad(\D[1]~31_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N8 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T3_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hAE0C; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N22 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .datad(\z80_|execute_|fMRead~36_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFEFA; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N7 -dffeas \z80_|data_pins_|dout[1] ( +// Location: FF_X31_Y16_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .asdata(vcc), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [1]), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[1] .power_up = "low"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~12 ( +// Location: LCCOMB_X30_Y20_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( // Equation(s): -// \z80_|bus_control_|db[1]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~12 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h0203; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( -// Equation(s): -// \z80_|bus_control_|db[0]~6_combout = ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (\z80_|execute_|ctl_bus_db_oe~combout )) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFFF5; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~13 ( -// Equation(s): -// \z80_|bus_control_|db[1]~13_combout = ((\z80_|bus_control_|db[1]~12_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [1]), - .datab(\z80_|bus_control_|db[1]~12_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~13 .lut_mask = 16'h8FCF; -defparam \z80_|bus_control_|db[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~5_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hFB33; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N17 -dffeas \z80_|ir_|opcode[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[1]~13_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y15_N29 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N20 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) +// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), + .combout(\z80_|address_pins_|abus[10]~24_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFF0; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y15_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( // Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [0]))) +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [0]), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datab(\z80_|address_latch_|abusz [11]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal36~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal36~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal36~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hAE0C; -defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y15_N27 -dffeas \z80_|decode_state_|DFFE_instCB ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), +// Location: FF_X31_Y16_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instCB~q ), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), .prn(vcc)); // synopsys translate_off -defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y15_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Location: LCCOMB_X30_Y20_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( // Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0004; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|pla_decode_|Equal50~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q ))) # (!\z80_|pla_decode_|Equal50~0_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & -// !\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal33~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0357; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mRead~9_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_mRead~9_combout & -// (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~11_combout & (\z80_|execute_|ctl_mWrite~9_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mWrite~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~11_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~3_combout & (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_bus_db_oe~6_combout & \z80_|execute_|ctl_mWrite~12_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_mWrite~14_combout ) # (((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~14_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hDCFF; -defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X50_Y16_N29 -dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~15_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N18 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q - - .dataa(gnd), + .dataa(\z80_|address_pins_|DFFE_apin_latch [11]), .datab(gnd), .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .combout(\z80_|address_pins_|abus[11]~19_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N19 -dffeas \z80_|memory_ifc_|wait_mwr ( +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) + + .dataa(\z80_|address_latch_|abusz [12]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mwr~q ), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N0 -cycloneive_lcell_comb \z80_|memory_ifc_|mwr_wr~feeder ( +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( // Equation(s): -// \z80_|memory_ifc_|mwr_wr~feeder_combout = \z80_|memory_ifc_|wait_mwr~q +// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(gnd), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mwr~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [12]), .cin(gnd), - .combout(\z80_|memory_ifc_|mwr_wr~feeder_combout ), + .combout(\z80_|address_pins_|abus[12]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|mwr_wr~feeder .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N1 -dffeas \z80_|memory_ifc_|mwr_wr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|mwr_wr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|mwr_wr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N4 -cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~4_combout & \z80_|memory_ifc_|iorq~0_combout )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|mwr_wr~q ), - .datac(\z80_|execute_|fIOWrite~4_combout ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nWR_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hFCCC; -defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N30 -cycloneive_lcell_comb \D[0]~30 ( -// Equation(s): -// \D[0]~30_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cin(gnd), - .combout(\D[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~30 .lut_mask = 16'hFF40; -defparam \D[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 +// Location: M9K_X33_Y11_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -42483,7 +38071,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .ena1(vcc), @@ -42491,10 +38079,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -42532,26 +38120,1177 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), - .cout()); +// Location: FF_X32_Y14_N31 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[13]~20_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hE6C4; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y16_N0 +// Location: FF_X32_Y14_N1 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0200; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: FF_X29_Y14_N5 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0C00; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \D[6]~90 ( +// Equation(s): +// \D[6]~90_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\D[6]~90_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~90 .lut_mask = 16'hCCE2; +defparam \D[6]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N16 +cycloneive_lcell_comb \D[6]~91 ( +// Equation(s): +// \D[6]~91_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~90_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~90_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~90_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[6]~90_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\D[6]~91_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~91 .lut_mask = 16'hF838; +defparam \D[6]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0020; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y24_N16 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N20 +cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [4]), + .cin(gnd), + .combout(\ula_|video_|vram_address[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N4 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N21 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y33_N19 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N0 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N1 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N26 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N27 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N28 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'hA50F; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N29 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N2 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N4 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N6 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N8 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y33_N9 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N10 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y33_N11 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N12 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y33_N13 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N14 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N22 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) + + .dataa(gnd), + .datab(\ula_|video_|Add4~12_combout ), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hCCF0; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N14 +cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( +// Equation(s): +// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N23 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N16 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [8]), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) + + .dataa(\ula_|video_|Add4~14_combout ), + .datab(gnd), + .datac(\ula_|video_|Add4~2_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hAAF0; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N21 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N30 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & (\ula_|video_|vga_hc [1]))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|Add4~4_combout ), + .datab(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|vram_address[10]~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N31 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) + + .dataa(gnd), + .datab(\ula_|video_|Add4~12_combout ), + .datac(gnd), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFCC; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N17 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N26 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|Add4~14_combout ) # (\ula_|video_|vga_hc [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|Add4~14_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N27 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N23 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y14_N1 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -42561,16 +39300,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -42624,7 +39363,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y13_N0 +// Location: M9K_X33_Y33_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(vcc), .portare(vcc), @@ -42634,16 +39373,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -42682,7 +39421,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; // synopsys translate_on -// Location: M9K_X33_Y13_N0 +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \D[6]~87 ( +// Equation(s): +// \D[6]~87_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\D[6]~87_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~87 .lut_mask = 16'hE6A2; +defparam \D[6]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y1_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portawe(vcc), .portare(vcc), @@ -42692,16 +39449,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -42740,3739 +39497,175 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; // synopsys translate_on -// Location: M9K_X33_Y17_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \Selector6~0 ( -// Equation(s): -// \Selector6~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector6~0 .lut_mask = 16'hAEA4; -defparam \Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N0 -cycloneive_lcell_comb \D[6]~70 ( -// Equation(s): -// \D[6]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector6~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\Selector6~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector6~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datad(\Selector6~0_combout ), - .cin(gnd), - .combout(\D[6]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~70 .lut_mask = 16'hBBC0; -defparam \D[6]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \D[6]~71 ( -// Equation(s): -// \D[6]~71_combout = ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\D[6]~70_combout )))) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\z80_|memory_ifc_|nRD_out~2_combout ), - .datad(\D[6]~70_combout ), - .cin(gnd), - .combout(\D[6]~71_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~71 .lut_mask = 16'hBF8F; -defparam \D[6]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G19 -cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2]}), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk )); -// synopsys translate_off -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock"; -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~77_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[3]~21_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[3]~21_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\D[3]~77_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N11 -dffeas \z80_|data_pins_|dout[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~64 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~64_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~64 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[5][4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~101_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[5][4]~64_combout & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~101_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~101 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[3][3]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~102 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~102_combout = (\ula_|zx_keyboard_|keys[3][3]~101_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~101_combout & (\ula_|zx_keyboard_|keys[3][3]~q )) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~101_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~102_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~102 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[3][3]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N3 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~102_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'hCCCF; -defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~104 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~104_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~104 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[2][3]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~135 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~135_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[2][3]~104_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[2][3]~104_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~135_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~135 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[2][3]~135 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~105_combout = (\ula_|zx_keyboard_|keys[2][3]~135_combout & (!\ula_|zx_keyboard_|keys[2][3]~103_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~135_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~135_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~105 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N17 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~105_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \D[3]~55 ( -// Equation(s): -// \D[3]~55_combout = (\z80_|address_pins_|abus[11]~21_combout & (((\z80_|address_pins_|abus[10]~22_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~21_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~22_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~21_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~q ), - .datac(\z80_|address_pins_|abus[10]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[2][3]~q ), - .cin(gnd), - .combout(\D[3]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~55 .lut_mask = 16'hB0BB; -defparam \D[3]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~21_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~95_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][3]~94_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~95 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[1][3]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~96_combout = (\ula_|zx_keyboard_|keys[1][3]~95_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][3]~95_combout & ((\ula_|zx_keyboard_|keys[1][3]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|keys[1][3]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~96_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~96 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[1][3]~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N9 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~96_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~97 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~97_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~97 .lut_mask = 16'hAAEE; -defparam \ula_|zx_keyboard_|keys[2][4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~99_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [6])))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~99_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~99 .lut_mask = 16'h0220; -defparam \ula_|zx_keyboard_|keys[0][4]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~100 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~100_combout = (\ula_|zx_keyboard_|keys[0][3]~98_combout & ((\ula_|zx_keyboard_|keys[0][4]~99_combout & (!\ula_|zx_keyboard_|keys[2][4]~97_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~99_combout & -// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][3]~98_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~99_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~100 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N31 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~100_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \D[3]~54 ( -// Equation(s): -// \D[3]~54_combout = (\z80_|address_pins_|abus[8]~20_combout & (((\z80_|address_pins_|abus[9]~19_combout )) # (!\ula_|zx_keyboard_|keys[1][3]~q ))) # (!\z80_|address_pins_|abus[8]~20_combout & (!\ula_|zx_keyboard_|keys[0][3]~q & -// ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[1][3]~q ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\z80_|address_pins_|abus[9]~19_combout ), - .cin(gnd), - .combout(\D[3]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~54 .lut_mask = 16'hAF23; -defparam \D[3]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~79_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[3][0]~79_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~136 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~136_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), - .datab(\ula_|zx_keyboard_|Selector5~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~136_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~136 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~136 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~109 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~109_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~108_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~136_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[4][3]~136_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~108_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~109_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~109 .lut_mask = 16'hEA40; -defparam \ula_|zx_keyboard_|keys[4][3]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~137 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~137_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~137_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~137 .lut_mask = 16'hFF02; -defparam \ula_|zx_keyboard_|keys[4][3]~137 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~110 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~110_combout = (\ula_|zx_keyboard_|keys[4][3]~109_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|zx_keyboard_|keys[4][3]~137_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & -// ((\ula_|zx_keyboard_|keys[4][3]~q ))))) # (!\ula_|zx_keyboard_|keys[4][3]~109_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~109_combout ), - .datab(\ula_|zx_keyboard_|keys[4][3]~137_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~110_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~110 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][3]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N19 -dffeas \ula_|zx_keyboard_|keys[4][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][3]~110_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~106 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~106_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~106 .lut_mask = 16'h00C0; -defparam \ula_|zx_keyboard_|keys[5][3]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~107 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~107_combout = (\ula_|zx_keyboard_|keys[1][4]~25_combout & ((\ula_|zx_keyboard_|keys[5][3]~106_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][3]~106_combout & ((\ula_|zx_keyboard_|keys[5][3]~q -// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|keys[5][3]~106_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~107_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~107 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][3]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y14_N17 -dffeas \ula_|zx_keyboard_|keys[5][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~107_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N26 -cycloneive_lcell_comb \D[3]~56 ( -// Equation(s): -// \D[3]~56_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][3]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[5][3]~q ), - .cin(gnd), - .combout(\D[3]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~56 .lut_mask = 16'h8ACF; -defparam \D[3]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~115 ( +cycloneive_lcell_comb \D[6]~88 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~115_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) +// \D[6]~88_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~87_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~87_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~87_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~115_combout ), + .combout(\D[6]~88_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~115 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][3]~115 .sum_lutc_input = "datac"; +defparam \D[6]~88 .lut_mask = 16'h22D8; +defparam \D[6]~88 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~116 ( +cycloneive_lcell_comb \D[6]~89 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~116_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~115_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[7][2]~32_combout & ((\ula_|ps2_keyboard_|shiftreg [2])))) +// \D[6]~89_combout = (\D[6]~87_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~88_combout )))) # (!\D[6]~87_combout & +// (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \D[6]~88_combout )))) - .dataa(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datab(\ula_|zx_keyboard_|keys[6][3]~115_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\D[6]~87_combout ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\D[6]~88_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~116_combout ), + .combout(\D[6]~89_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~116 .lut_mask = 16'hCCA0; -defparam \ula_|zx_keyboard_|keys[6][3]~116 .sum_lutc_input = "datac"; +defparam \D[6]~89 .lut_mask = 16'hC3C8; +defparam \D[6]~89 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~139 ( +cycloneive_lcell_comb \D[6]~111 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~139_combout = (((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout )) # (!\ula_|zx_keyboard_|keys[6][3]~116_combout ) +// \D[6]~111_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[6]~91_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[6]~89_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[6]~91_combout )) - .dataa(\ula_|zx_keyboard_|keys[6][3]~116_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), + .dataa(\D[6]~91_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\D[6]~89_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~139_combout ), + .combout(\D[6]~111_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~139 .lut_mask = 16'hFF7F; -defparam \ula_|zx_keyboard_|keys[6][3]~139 .sum_lutc_input = "datac"; +defparam \D[6]~111 .lut_mask = 16'hAEA2; +defparam \D[6]~111 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(gnd), +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \D[6]~86 ( +// Equation(s): +// \D[6]~86_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(gnd), + .datac(\raw_loader_in~input_o ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector13~0_combout ), + .combout(\D[6]~86_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hF2F2; -defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; +defparam \D[6]~86 .lut_mask = 16'hFAFF; +defparam \D[6]~86 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~140 ( +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \D[6]~100 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~140_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~139_combout & (\ula_|zx_keyboard_|keys[6][3]~q )) # (!\ula_|zx_keyboard_|keys[6][3]~139_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout -// ))))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) +// \D[6]~100_combout = ((\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout ))) # (!\Equal2~1_combout ) - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[6][3]~139_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), + .dataa(\Equal2~1_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[6]~111_combout ), + .datad(\D[6]~86_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~140_combout ), + .combout(\D[6]~100_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~140 .lut_mask = 16'hD0F2; -defparam \ula_|zx_keyboard_|keys[6][3]~140 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N9 -dffeas \ula_|zx_keyboard_|keys[6][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~140_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFCF0; -defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h00CC; -defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~62_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hF080; -defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; +defparam \D[6]~100 .lut_mask = 16'hFD75; +defparam \D[6]~100 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( +cycloneive_lcell_comb \D[6]~101 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & ((\ula_|zx_keyboard_|keys[7][3]~q ))) +// \D[6]~101_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [6] & \D[6]~100_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[6]~100_combout )) # (!\Equal2~1_combout ))) - .dataa(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [6]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[6]~100_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .combout(\D[6]~101_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; +defparam \D[6]~101 .lut_mask = 16'hCF05; +defparam \D[6]~101 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N5 -dffeas \ula_|zx_keyboard_|keys[7][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N16 -cycloneive_lcell_comb \D[3]~57 ( -// Equation(s): -// \D[3]~57_combout = (\ula_|zx_keyboard_|keys[6][3]~q & (\z80_|address_pins_|abus[14]~16_combout & ((\z80_|address_pins_|abus[15]~17_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~q & -// (((\z80_|address_pins_|abus[15]~17_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[6][3]~q ), - .datab(\ula_|zx_keyboard_|keys[7][3]~q ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\D[3]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~57 .lut_mask = 16'hF531; -defparam \D[3]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N16 -cycloneive_lcell_comb \D[3]~58 ( -// Equation(s): -// \D[3]~58_combout = (\D[3]~55_combout & (\D[3]~54_combout & (\D[3]~56_combout & \D[3]~57_combout ))) - - .dataa(\D[3]~55_combout ), - .datab(\D[3]~54_combout ), - .datac(\D[3]~56_combout ), - .datad(\D[3]~57_combout ), - .cin(gnd), - .combout(\D[3]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~58 .lut_mask = 16'h8000; -defparam \D[3]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y31_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hBBC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; -// synopsys translate_on - -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; -// synopsys translate_on - -// Location: M9K_X33_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N18 -cycloneive_lcell_comb \Selector3~0 ( -// Equation(s): -// \Selector3~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector3~0 .lut_mask = 16'hCEC2; -defparam \Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N12 -cycloneive_lcell_comb \Selector3~1 ( -// Equation(s): -// \Selector3~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\Selector3~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector3~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\Selector3~0_combout ), - .cin(gnd), - .combout(\Selector3~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector3~1 .lut_mask = 16'hBBC0; -defparam \Selector3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N6 -cycloneive_lcell_comb \D[3]~52 ( -// Equation(s): -// \D[3]~52_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector3~1_combout ))))) - - .dataa(\z80_|address_pins_|abus[15]~17_combout ), - .datab(\Equal2~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), - .datad(\Selector3~1_combout ), - .cin(gnd), - .combout(\D[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~52 .lut_mask = 16'h3120; -defparam \D[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N20 -cycloneive_lcell_comb \D[3]~53 ( -// Equation(s): -// \D[3]~53_combout = (\z80_|memory_ifc_|nWR_out~0_combout ) # (((\D[3]~52_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|memory_ifc_|nRD_out~2_combout )) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~52_combout ), - .cin(gnd), - .combout(\D[3]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~53 .lut_mask = 16'hFFBF; -defparam \D[3]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N10 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\D[3]~53_combout ) # ((\Equal2~0_combout & ((\z80_|address_pins_|abus[0]~18_combout ) # (\D[3]~58_combout )))) - - .dataa(\z80_|address_pins_|abus[0]~18_combout ), - .datab(\D[3]~58_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[3]~53_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'hFFE0; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N24 -cycloneive_lcell_comb \D[3]~77 ( -// Equation(s): -// \D[3]~77_combout = ((\D[3]~76_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\z80_|data_pins_|dout [3]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[0]~30_combout ), - .datad(\D[3]~76_combout ), - .cin(gnd), - .combout(\D[3]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~77 .lut_mask = 16'hBF0F; -defparam \D[3]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N0 -cycloneive_lcell_comb \ula_|always0~0 ( -// Equation(s): -// \ula_|always0~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [0])) - - .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|always0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|always0~0 .lut_mask = 16'h0808; -defparam \ula_|always0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N2 -cycloneive_lcell_comb \ula_|always0~1 ( -// Equation(s): -// \ula_|always0~1_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|always0~0_combout ), - .cin(gnd), - .combout(\ula_|always0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|always0~1 .lut_mask = 16'h2000; -defparam \ula_|always0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y15_N25 -dffeas \ula_|pcm_outl[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[3]~77_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|pcm_outl [13]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y17_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|mclk_r~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y17_N5 -dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|mclk_r~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) - - .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add0~1_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; -defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) -// \ula_|i2s_intf_|Add0~3 = CARRY((!\ula_|i2s_intf_|lrdivider [1] & !\ula_|i2s_intf_|Add0~1_cout )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~1_cout ), - .combout(\ula_|i2s_intf_|Add0~2_combout ), - .cout(\ula_|i2s_intf_|Add0~3 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add0~2_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N29 -dffeas \ula_|i2s_intf_|lrdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) -// \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) - - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~3 ), - .combout(\ula_|i2s_intf_|Add0~4_combout ), - .cout(\ula_|i2s_intf_|Add0~5 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~4_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N5 -dffeas \ula_|i2s_intf_|lrdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) -// \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~5 ), - .combout(\ula_|i2s_intf_|Add0~6_combout ), - .cout(\ula_|i2s_intf_|Add0~7 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; -defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~6_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; -defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y15_N1 -dffeas \ula_|i2s_intf_|lrdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) -// \ula_|i2s_intf_|Add0~9 = CARRY((\ula_|i2s_intf_|lrdivider [4]) # (!\ula_|i2s_intf_|Add0~7 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~7 ), - .combout(\ula_|i2s_intf_|Add0~8_combout ), - .cout(\ula_|i2s_intf_|Add0~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; -defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N25 -dffeas \ula_|i2s_intf_|lrdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) -// \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) - - .dataa(\ula_|i2s_intf_|lrdivider [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~9 ), - .combout(\ula_|i2s_intf_|Add0~10_combout ), - .cout(\ula_|i2s_intf_|Add0~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; -defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[5]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y16_N17 -dffeas \ula_|i2s_intf_|lrdivider[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) -// \ula_|i2s_intf_|Add0~13 = CARRY((!\ula_|i2s_intf_|Add0~11 ) # (!\ula_|i2s_intf_|lrdivider [6])) - - .dataa(\ula_|i2s_intf_|lrdivider [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~11 ), - .combout(\ula_|i2s_intf_|Add0~12_combout ), - .cout(\ula_|i2s_intf_|Add0~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~12_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[6]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y16_N15 -dffeas \ula_|i2s_intf_|lrdivider[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) -// \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) - - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~13 ), - .combout(\ula_|i2s_intf_|Add0~14_combout ), - .cout(\ula_|i2s_intf_|Add0~15 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; -defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y16_N1 -dffeas \ula_|i2s_intf_|lrdivider[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) -// \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [8]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~15 ), - .combout(\ula_|i2s_intf_|Add0~16_combout ), - .cout(\ula_|i2s_intf_|Add0~17 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add0~16_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N25 -dffeas \ula_|i2s_intf_|lrdivider[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrdivider [9]), - .cin(\ula_|i2s_intf_|Add0~17 ), - .combout(\ula_|i2s_intf_|Add0~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; -defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~18_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; -defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N21 -dffeas \ula_|i2s_intf_|lrdivider[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|lrdivider [8]))) - - .dataa(\ula_|i2s_intf_|lrdivider [6]), - .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [7]), - .datad(\ula_|i2s_intf_|lrdivider [8]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0080; -defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( -// Equation(s): -// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|lrdivider [4]))) - - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(\ula_|i2s_intf_|lrdivider [3]), - .datac(\ula_|i2s_intf_|lrdivider [5]), - .datad(\ula_|i2s_intf_|lrdivider [4]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h0080; -defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( -// Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~0_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~1_combout ))) - - .dataa(\ula_|i2s_intf_|Equal0~0_combout ), - .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; -defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] -// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .cout(\ula_|i2s_intf_|bitcount[0]~6 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; -defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(\ula_|i2s_intf_|bitcount [2]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h33C3; -defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add2~7_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0033; -defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) -// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~7_cout ), - .combout(\ula_|i2s_intf_|Add2~8_combout ), - .cout(\ula_|i2s_intf_|Add2~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (\ula_|i2s_intf_|Add2~8_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|Add2~8_combout ), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h020A; -defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N25 -dffeas \ula_|i2s_intf_|bdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) -// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) - - .dataa(\ula_|i2s_intf_|bdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~9 ), - .combout(\ula_|i2s_intf_|Add2~10_combout ), - .cout(\ula_|i2s_intf_|Add2~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[8]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|Add2~10_combout ), - .datac(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h000B; -defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N13 -dffeas \ula_|i2s_intf_|bdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) -// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - - .dataa(\ula_|i2s_intf_|bdivider [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~11 ), - .combout(\ula_|i2s_intf_|Add2~12_combout ), - .cout(\ula_|i2s_intf_|Add2~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|Add2~12_combout ), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h020A; -defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N27 -dffeas \ula_|i2s_intf_|bdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~19_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(\ula_|i2s_intf_|Add2~13 ), - .combout(\ula_|i2s_intf_|Add2~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; -defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[8]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .datad(\ula_|i2s_intf_|Add2~14_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N11 -dffeas \ula_|i2s_intf_|bdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (\ula_|i2s_intf_|bdivider [4] & (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & \ula_|i2s_intf_|bdivider [2]))) - - .dataa(\ula_|i2s_intf_|bdivider [4]), - .datab(\ula_|i2s_intf_|bdivider [1]), - .datac(\ula_|i2s_intf_|bdivider [3]), - .datad(\ula_|i2s_intf_|bdivider [2]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0200; -defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[8]~1 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[8]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bitcount [4]), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(\ula_|i2s_intf_|LessThan0~0_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8]~1 .lut_mask = 16'hC400; -defparam \ula_|i2s_intf_|shiftreg[8]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[8]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .datac(\ula_|i2s_intf_|bdivider [0]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; -defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N29 -dffeas \ula_|i2s_intf_|bdivider[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; -defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) - - .dataa(\ula_|i2s_intf_|bclk_r~0_combout ), - .datab(\ula_|i2s_intf_|Equal1~1_combout ), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00B8; -defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bclk_r~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N15 -dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[8]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hAFAA; -defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N1 -dffeas \ula_|i2s_intf_|bitcount[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) -// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[0]~6 ), - .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .cout(\ula_|i2s_intf_|bitcount[1]~8 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N3 -dffeas \ula_|i2s_intf_|bitcount[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) -// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[1]~8 ), - .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .cout(\ula_|i2s_intf_|bitcount[2]~10 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N5 -dffeas \ula_|i2s_intf_|bitcount[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) -// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[2]~10 ), - .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .cout(\ula_|i2s_intf_|bitcount[3]~12 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N7 -dffeas \ula_|i2s_intf_|bitcount[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [4]), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2s_intf_|bitcount[3]~12 ), - .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; -defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N9 -dffeas \ula_|i2s_intf_|bitcount[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~19_combout = (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & (\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bitcount [4]), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|Equal1~1_combout ), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h3010; -defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X23_Y34_N22 -cycloneive_io_ibuf \AUD_ADCDAT~input ( - .i(AUD_ADCDAT), - .ibar(gnd), - .o(\AUD_ADCDAT~input_o )); -// synopsys translate_off -defparam \AUD_ADCDAT~input .bus_hold = "false"; -defparam \AUD_ADCDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) - - .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [0]), - .datad(\AUD_ADCDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; -defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N3 -dffeas \ula_|i2s_intf_|shiftreg[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[8]~2 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[8]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[8]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8]~2 .lut_mask = 16'hFAAA; -defparam \ula_|i2s_intf_|shiftreg[8]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N1 -dffeas \ula_|i2s_intf_|shiftreg[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N19 -dffeas \ula_|i2s_intf_|shiftreg[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N29 -dffeas \ula_|i2s_intf_|shiftreg[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N27 -dffeas \ula_|i2s_intf_|shiftreg[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~15_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(\ula_|i2s_intf_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0A0A; -defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N21 -dffeas \ula_|i2s_intf_|shiftreg[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~14_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N15 -dffeas \ula_|i2s_intf_|shiftreg[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~13_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [6]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N25 -dffeas \ula_|i2s_intf_|shiftreg[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~11_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [7]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N11 -dffeas \ula_|i2s_intf_|shiftreg[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~11_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [8]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N9 -dffeas \ula_|i2s_intf_|shiftreg[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~10_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [9]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N31 -dffeas \ula_|i2s_intf_|shiftreg[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~9_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(\ula_|i2s_intf_|shiftreg [10]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0A0A; -defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N13 -dffeas \ula_|i2s_intf_|shiftreg[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~8_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~7_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [11]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [11]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N23 -dffeas \ula_|i2s_intf_|shiftreg[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~7_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; -defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N21 -dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( -// Equation(s): -// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|PCM_INR [14])))) # -// (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (((\ula_|i2s_intf_|PCM_INR [14])))) - - .dataa(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|shiftreg [14]), - .cin(gnd), - .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hF870; -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N19 -dffeas \ula_|i2s_intf_|PCM_INR[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|PCM_INR [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \ula_|ula_data~0 ( -// Equation(s): -// \ula_|ula_data~0_combout = (\ula_|i2s_intf_|PCM_INL [14]) # (\ula_|i2s_intf_|PCM_INR [14]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|PCM_INR [14]), - .cin(gnd), - .combout(\ula_|ula_data~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ula_data~0 .lut_mask = 16'hFFF0; -defparam \ula_|ula_data~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N3 -dffeas \ula_|pcm_outl[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ula_data~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|pcm_outl [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) - - .dataa(\ula_|i2s_intf_|shiftreg [12]), - .datab(\ula_|pcm_outl [12]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hCACA; -defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N17 -dffeas \ula_|i2s_intf_|shiftreg[13] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [13]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) - - .dataa(\ula_|pcm_outl [13]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [13]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hB8B8; -defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N9 -dffeas \ula_|i2s_intf_|shiftreg[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( -// Equation(s): -// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) - - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N5 -dffeas \ula_|i2s_intf_|PCM_INL[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|PCM_INL [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \D[6]~72 ( -// Equation(s): -// \D[6]~72_combout = (!\z80_|address_pins_|abus[0]~18_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (!\ula_|i2s_intf_|PCM_INL [14] & !\ula_|i2s_intf_|PCM_INR [14]))) - - .dataa(\z80_|address_pins_|abus[0]~18_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|PCM_INR [14]), - .cin(gnd), - .combout(\D[6]~72_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~72 .lut_mask = 16'h0004; -defparam \D[6]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \D[6]~73 ( -// Equation(s): -// \D[6]~73_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Equal2~0_combout & ((\D[6]~72_combout ))) # (!\Equal2~0_combout & (!\D[6]~71_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\Equal2~0_combout ), - .datac(\D[6]~71_combout ), - .datad(\D[6]~72_combout ), - .cin(gnd), - .combout(\D[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~73 .lut_mask = 16'h8A02; -defparam \D[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \D[6]~74 ( -// Equation(s): -// \D[6]~74_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (((\z80_|data_pins_|dout [6])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) # (!\z80_|memory_ifc_|nWR_out~0_combout & (!\D[6]~73_combout & ((\z80_|data_pins_|dout [6]) # -// (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\D[6]~73_combout ), - .cin(gnd), - .combout(\D[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~74 .lut_mask = 16'hA2F3; -defparam \D[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 -cycloneive_lcell_comb \D[6]~81 ( -// Equation(s): -// \D[6]~81_combout = (\D[6]~74_combout ) # (!\D[0]~30_combout ) - - .dataa(\D[0]~30_combout ), - .datab(\D[6]~74_combout ), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\D[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~81 .lut_mask = 16'hDDDD; -defparam \D[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 +// Location: LCCOMB_X32_Y13_N12 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~81_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~7_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[6]~7_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~101_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & +// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[6]~7_combout ), - .datad(\D[6]~81_combout ), + .datab(\D[6]~101_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[6]~9_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N1 +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # +// ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|fIORead~3_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|fIORead~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hDC50; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|execute_|fMRead~35_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N13 dffeas \z80_|data_pins_|dout[6] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), @@ -46491,44 +39684,61 @@ defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~5 ( +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( // Equation(s): -// \z80_|bus_control_|db[6]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|db[6]~15_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~5 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[6]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~7 ( -// Equation(s): -// \z80_|bus_control_|db[6]~7_combout = ((\z80_|bus_control_|db[6]~5_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(\z80_|bus_control_|db[6]~8_combout ), .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[6]~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[6]~7_combout ), + .combout(\z80_|bus_control_|db[6]~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[6]~7 .lut_mask = 16'hDF0F; -defparam \z80_|bus_control_|db[6]~7 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'h8AFF; +defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N19 +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~9_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[6]~9_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N9 dffeas \z80_|ir_|opcode[6] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[6]~7_combout ), + .d(\z80_|ir_|opcode[6]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -46544,3371 +39754,239 @@ defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y15_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( +// Location: LCCOMB_X37_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( // Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), + .combout(\z80_|pla_decode_|Equal41~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h4400; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Location: LCCOMB_X38_Y16_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( // Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) +// \z80_|pla_decode_|Equal41~1_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [5]))) - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), + .combout(\z80_|pla_decode_|Equal41~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Location: LCCOMB_X38_Y16_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( // Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) +// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_sw_1d~8_combout ), + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal41~1_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .combout(\z80_|pla_decode_|Equal41~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X40_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( // Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_2d~9_combout & \z80_|execute_|ctl_sw_1d~4_combout ))) +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal41~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_1d~5_combout ), - .datac(\z80_|execute_|ctl_sw_2d~9_combout ), - .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFF08; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Location: LCCOMB_X34_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( // Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|execute_|ctl_66_oe~2_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) +// \z80_|alu_|db_high[1]~15_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'h7555; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_high [1]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~23_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~17_combout ))) + + .dataa(\z80_|alu_|db[6]~23_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[4]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[1]~17_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[5]~25_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[1]~17_combout ), + .datac(\z80_|alu_|db[5]~25_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = (\z80_|alu_|db_high[1]~15_combout & (\z80_|alu_|db_high[1]~16_combout & ((\z80_|alu_|db_high[1]~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[1]~15_combout ), + .datab(\z80_|alu_|db_high[1]~16_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[1]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~20 ( +// Equation(s): +// \z80_|alu_|db_high[1]~20_combout = ((\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~20 .lut_mask = 16'hA8FF; +defparam \z80_|alu_|db_high[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[5]~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db[5]~25 ( +// Equation(s): +// \z80_|alu_|db[5]~25_combout = ((\z80_|alu_|db[5]~24_combout & ((\z80_|alu_|db_high[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db_high[1]~20_combout ), + .datab(\z80_|alu_|db[7]~26_combout ), + .datac(\z80_|alu_|db[5]~24_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~25 .lut_mask = 16'hB3F3; +defparam \z80_|alu_|db[5]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N14 +cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Equation(s): +// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7733; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( -// Equation(s): -// \z80_|alu_control_|db[6]~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_flags_oe~2_combout ) # (\z80_|execute_|ctl_66_oe~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_66_oe~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFFC; -defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( -// Equation(s): -// \z80_|alu_control_|db[6]~11_combout = (\z80_|execute_|ctl_sw_1d~7_combout ) # ((\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_reg_out_lo~8_combout ) # (\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|alu_control_|db[6]~10_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFFFE; -defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~20 ( -// Equation(s): -// \z80_|alu_control_|db[2]~20_combout = (\z80_|alu_|db[2]~12_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & (\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_|db[2]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~20 .lut_mask = 16'h7530; -defparam \z80_|alu_control_|db[2]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hF4F0; -defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~21 ( -// Equation(s): -// \z80_|alu_control_|db[2]~21_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[2]~11_combout ), - .datab(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~21 .lut_mask = 16'h08CC; -defparam \z80_|alu_control_|db[2]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~22 ( -// Equation(s): -// \z80_|alu_control_|db[2]~22_combout = ((!\z80_|alu_control_|db[2]~20_combout & (\z80_|alu_control_|db[2]~21_combout & \z80_|alu_control_|db[2]~19_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[2]~20_combout ), - .datac(\z80_|alu_control_|db[2]~21_combout ), - .datad(\z80_|alu_control_|db[2]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~22 .lut_mask = 16'h7555; -defparam \z80_|alu_control_|db[2]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~10 ( -// Equation(s): -// \z80_|bus_control_|db[2]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|db[2]~22_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~10 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h0A0A; -defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~59 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~59_combout = (\ula_|zx_keyboard_|keys[5][2]~58_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][2]~58_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~59_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~59 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][2]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \ula_|zx_keyboard_|keys[5][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~59_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~133_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][2]~60_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~133 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[4][2]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~132_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~132 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][4]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~61 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~61_combout = (\ula_|zx_keyboard_|keys[4][2]~133_combout & ((\ula_|zx_keyboard_|keys[3][4]~132_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~132_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~133_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][2]~133_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~132_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~61 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N23 -dffeas \ula_|zx_keyboard_|keys[4][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~61_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N6 -cycloneive_lcell_comb \D[2]~34 ( -// Equation(s): -// \D[2]~34_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|keys[4][2]~q ), - .cin(gnd), - .combout(\D[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~34 .lut_mask = 16'h8CAF; -defparam \D[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h000C; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~51_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N21 -dffeas \ula_|zx_keyboard_|keys[3][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~55_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~55 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[1][4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~56_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|Equal0~2_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h3000; -defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~57_combout = (\ula_|zx_keyboard_|keys[1][4]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~56_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~56_combout & ((\ula_|zx_keyboard_|keys[2][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~55_combout & (((\ula_|zx_keyboard_|keys[2][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][4]~55_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~57_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~57 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[2][2]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \ula_|zx_keyboard_|keys[2][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~57_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \D[2]~33 ( -// Equation(s): -// \D[2]~33_combout = (\z80_|address_pins_|abus[10]~22_combout & (((\z80_|address_pins_|abus[11]~21_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) # (!\z80_|address_pins_|abus[10]~22_combout & (!\ula_|zx_keyboard_|keys[2][2]~q & -// ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\z80_|address_pins_|abus[10]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[3][2]~q ), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\z80_|address_pins_|abus[11]~21_combout ), - .cin(gnd), - .combout(\D[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~33 .lut_mask = 16'hAF23; -defparam \D[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~48 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~48_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[6][4]~21_combout & \ula_|zx_keyboard_|keys[6][4]~47_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~48 .lut_mask = 16'h4400; -defparam \ula_|zx_keyboard_|keys[1][2]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[1][2]~48_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][2]~48_combout & (\ula_|zx_keyboard_|keys[1][2]~q )) - - .dataa(\ula_|zx_keyboard_|keys[1][2]~48_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h0303; -defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & (\ula_|zx_keyboard_|keys[0][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N1 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N26 -cycloneive_lcell_comb \D[2]~32 ( -// Equation(s): -// \D[2]~32_combout = (\z80_|address_pins_|abus[8]~20_combout & (((\z80_|address_pins_|abus[9]~19_combout )) # (!\ula_|zx_keyboard_|keys[1][2]~q ))) # (!\z80_|address_pins_|abus[8]~20_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & -// ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[1][2]~q ), - .datac(\z80_|address_pins_|abus[9]~19_combout ), - .datad(\ula_|zx_keyboard_|keys[0][2]~q ), - .cin(gnd), - .combout(\D[2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~32 .lut_mask = 16'hA2F3; -defparam \D[2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~63_combout = (\ula_|zx_keyboard_|keys[7][2]~62_combout & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~63 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~65_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~63_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~64_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[7][2]~63_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'hF800; -defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (\ula_|zx_keyboard_|keys[7][2]~65_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~67_combout = (\ula_|zx_keyboard_|keys[7][2]~66_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~66_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][2]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~67 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][2]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N29 -dffeas \ula_|zx_keyboard_|keys[7][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~67_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~68 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~68_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~68_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~68 .lut_mask = 16'hF3F0; -defparam \ula_|zx_keyboard_|keys[5][0]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~70_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~69_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~71_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & ((\ula_|zx_keyboard_|keys[6][2]~70_combout & (!\ula_|zx_keyboard_|keys[5][0]~68_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~70_combout & -// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~41_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~68_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~71 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][2]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N29 -dffeas \ula_|zx_keyboard_|keys[6][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~71_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N30 -cycloneive_lcell_comb \D[2]~35 ( -// Equation(s): -// \D[2]~35_combout = (\ula_|zx_keyboard_|keys[7][2]~q & (\z80_|address_pins_|abus[15]~17_combout & ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~q & -// (((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~q ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(\z80_|address_pins_|abus[14]~16_combout ), - .cin(gnd), - .combout(\D[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~35 .lut_mask = 16'hDD0D; -defparam \D[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \D[2]~36 ( -// Equation(s): -// \D[2]~36_combout = (\D[2]~34_combout & (\D[2]~33_combout & (\D[2]~32_combout & \D[2]~35_combout ))) - - .dataa(\D[2]~34_combout ), - .datab(\D[2]~33_combout ), - .datac(\D[2]~32_combout ), - .datad(\D[2]~35_combout ), - .cin(gnd), - .combout(\D[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~36 .lut_mask = 16'h8000; -defparam \D[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \D[2]~83 ( -// Equation(s): -// \D[2]~83_combout = (\Equal2~0_combout & ((\D[2]~36_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) - - .dataa(\D[2]~36_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[2]~83_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~83 .lut_mask = 16'hFB00; -defparam \D[2]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hF4A4; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y23_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .lut_mask = 16'hEC64; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; -// synopsys translate_on - -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \Selector0~0 ( -// Equation(s): -// \Selector0~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .cin(gnd), - .combout(\Selector0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector0~0 .lut_mask = 16'hCEC2; -defparam \Selector0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \Selector0~1 ( -// Equation(s): -// \Selector0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\Selector0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector0~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datac(\Selector0~0_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\Selector0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector0~1 .lut_mask = 16'hDAD0; -defparam \Selector0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N30 -cycloneive_lcell_comb \D[2]~37 ( -// Equation(s): -// \D[2]~37_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector0~1_combout ))))) - - .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), - .datad(\Selector0~1_combout ), - .cin(gnd), - .combout(\D[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~37 .lut_mask = 16'h5140; -defparam \D[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \D[2]~38 ( -// Equation(s): -// \D[2]~38_combout = (((\D[2]~37_combout ) # (\z80_|memory_ifc_|nWR_out~0_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[2]~37_combout ), - .datad(\z80_|memory_ifc_|nWR_out~0_combout ), - .cin(gnd), - .combout(\D[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~38 .lut_mask = 16'hFFF7; -defparam \D[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \D[2]~39 ( -// Equation(s): -// \D[2]~39_combout = (\D[2]~83_combout & (((\z80_|data_pins_|dout [2])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) # (!\D[2]~83_combout & (\D[2]~38_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) - - .dataa(\D[2]~83_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\D[2]~38_combout ), - .cin(gnd), - .combout(\D[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~39 .lut_mask = 16'hF3A2; -defparam \D[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \D[2]~40 ( -// Equation(s): -// \D[2]~40_combout = (\D[2]~39_combout ) # (!\D[0]~30_combout ) - - .dataa(\D[2]~39_combout ), - .datab(gnd), - .datac(\D[0]~30_combout ), - .datad(gnd), - .cin(gnd), - .combout(\D[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~40 .lut_mask = 16'hAFAF; -defparam \D[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[2]~40_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[2]~11_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~11_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\D[2]~40_combout ), - .datad(\z80_|bus_control_|db[2]~11_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N31 -dffeas \z80_|data_pins_|dout[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~11 ( -// Equation(s): -// \z80_|bus_control_|db[2]~11_combout = ((\z80_|bus_control_|db[2]~10_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[2]~10_combout ), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~11 .lut_mask = 16'hB3BB; -defparam \z80_|bus_control_|db[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N31 -dffeas \z80_|ir_|opcode[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[2]~11_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00AA; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|pla_decode_|Equal3~2_combout & (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal3~2_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N3 -dffeas \z80_|decode_state_|DFFE_instIY1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_inst4~q )) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0404; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (!\z80_|execute_|ctl_bus_db_oe~2_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h33FF; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_bus_db_oe~4_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & ((\z80_|execute_|ctl_bus_db_oe~3_combout ) # ((\z80_|execute_|ctl_bus_db_oe~5_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), .datad(\z80_|execute_|ctl_sw_1d~6_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .combout(\z80_|sw1_|db_down[5]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hEFCC; +defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h2080; -defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~84 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~84_combout = (\ula_|zx_keyboard_|keys[5][0]~83_combout & (!\ula_|zx_keyboard_|keys[5][0]~68_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~83_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[5][0]~68_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~84 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[5][0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N3 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~84_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'hFF50; -defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'h0160; -defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~87_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~85_combout & (!\ula_|zx_keyboard_|keys[4][0]~86_combout )) # (!\ula_|zx_keyboard_|keys[4][0]~85_combout & -// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~87 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N21 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~87_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N14 -cycloneive_lcell_comb \D[0]~45 ( -// Equation(s): -// \D[0]~45_combout = (\ula_|zx_keyboard_|keys[5][0]~q & (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~q ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[4][0]~q ), - .cin(gnd), - .combout(\D[0]~45_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~45 .lut_mask = 16'hC4F5; -defparam \D[0]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~81_combout = (\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][0]~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|zx_keyboard_|released~q )))) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & (((\ula_|zx_keyboard_|keys[2][0]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~81 .lut_mask = 16'hF074; -defparam \ula_|zx_keyboard_|keys[2][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N21 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~81_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~80_combout = (\ula_|zx_keyboard_|keys[3][0]~79_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][0]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][0]~79_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~80 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N31 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N22 -cycloneive_lcell_comb \D[0]~44 ( -// Equation(s): -// \D[0]~44_combout = (\ula_|zx_keyboard_|keys[2][0]~q & (\z80_|address_pins_|abus[10]~22_combout & ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\ula_|zx_keyboard_|keys[2][0]~q & -// (((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[2][0]~q ), - .datab(\z80_|address_pins_|abus[10]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\z80_|address_pins_|abus[11]~21_combout ), - .cin(gnd), - .combout(\D[0]~44_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~44 .lut_mask = 16'hDD0D; -defparam \D[0]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~134 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~134_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[3][0]~79_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~134_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~134 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[7][0]~134 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h000F; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|WideOr16~3_combout & (\ula_|zx_keyboard_|keys[5][4]~64_combout & !\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|WideOr16~3_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & ((\ula_|zx_keyboard_|keys[7][0]~134_combout ) # (\ula_|zx_keyboard_|keys[7][0]~88_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[7][0]~134_combout ), - .datac(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'hA800; -defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~90 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~90_combout = (\ula_|zx_keyboard_|keys[7][0]~89_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~89_combout & ((\ula_|zx_keyboard_|keys[7][0]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~90_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~90 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[7][0]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N31 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~90_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0C0C; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|shifted~1_combout & \ula_|zx_keyboard_|keys[6][0]~91_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datac(\ula_|zx_keyboard_|shifted~1_combout ), - .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~93_combout = (\ula_|zx_keyboard_|keys[6][0]~92_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][0]~92_combout & (\ula_|zx_keyboard_|keys[6][0]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~93 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N15 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~93_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \D[0]~46 ( -// Equation(s): -// \D[0]~46_combout = (\ula_|zx_keyboard_|keys[7][0]~q & (\z80_|address_pins_|abus[15]~17_combout & ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][0]~q )))) # (!\ula_|zx_keyboard_|keys[7][0]~q & -// ((\z80_|address_pins_|abus[14]~16_combout ) # ((!\ula_|zx_keyboard_|keys[6][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~q ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\D[0]~46_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~46 .lut_mask = 16'hCF45; -defparam \D[0]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg -// [1] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8180; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~77_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~77 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~74_combout = (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~74 .lut_mask = 16'h8888; -defparam \ula_|zx_keyboard_|keys[4][3]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// ((\ula_|ps2_keyboard_|shiftreg [2]))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0510; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~75_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~21_combout )) # (!\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .datac(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~75 .lut_mask = 16'h0F77; -defparam \ula_|zx_keyboard_|keys~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~76_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~74_combout & !\ula_|zx_keyboard_|keys~75_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~74_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|keys~75_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~76 .lut_mask = 16'h30B0; -defparam \ula_|zx_keyboard_|keys[0][0]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~78 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~78_combout = (\ula_|zx_keyboard_|keys~77_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~77_combout & ((\ula_|zx_keyboard_|keys[0][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[0][0]~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys~77_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~76_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~78_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~78 .lut_mask = 16'hD1F0; -defparam \ula_|zx_keyboard_|keys[0][0]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N7 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~78_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~25_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~73 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~73_combout = (\ula_|zx_keyboard_|keys[1][0]~72_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~72_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~73_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~73 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[1][0]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y14_N11 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~73_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N24 -cycloneive_lcell_comb \D[0]~43 ( -// Equation(s): -// \D[0]~43_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~20_combout & ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & -// (((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), - .datab(\z80_|address_pins_|abus[8]~20_combout ), - .datac(\z80_|address_pins_|abus[9]~19_combout ), - .datad(\ula_|zx_keyboard_|keys[1][0]~q ), - .cin(gnd), - .combout(\D[0]~43_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~43 .lut_mask = 16'hD0DD; -defparam \D[0]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \D[0]~47 ( -// Equation(s): -// \D[0]~47_combout = (\D[0]~45_combout & (\D[0]~44_combout & (\D[0]~46_combout & \D[0]~43_combout ))) - - .dataa(\D[0]~45_combout ), - .datab(\D[0]~44_combout ), - .datac(\D[0]~46_combout ), - .datad(\D[0]~43_combout ), - .cin(gnd), - .combout(\D[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~47 .lut_mask = 16'h8000; -defparam \D[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .lut_mask = 16'hF588; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \Selector2~0 ( -// Equation(s): -// \Selector2~0_combout = (\z80_|address_pins_|abus[14]~16_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector2~0 .lut_mask = 16'hBA98; -defparam \Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \Selector2~1 ( -// Equation(s): -// \Selector2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector2~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\Selector2~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector2~0_combout )))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datad(\Selector2~0_combout ), - .cin(gnd), - .combout(\Selector2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector2~1 .lut_mask = 16'hF388; -defparam \Selector2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \D[0]~41 ( -// Equation(s): -// \D[0]~41_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector2~1_combout ))))) - - .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), - .datad(\Selector2~1_combout ), - .cin(gnd), - .combout(\D[0]~41_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~41 .lut_mask = 16'h5140; -defparam \D[0]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \D[0]~42 ( -// Equation(s): -// \D[0]~42_combout = ((\z80_|memory_ifc_|nWR_out~0_combout ) # ((\D[0]~41_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[0]~41_combout ), - .cin(gnd), - .combout(\D[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~42 .lut_mask = 16'hFFDF; -defparam \D[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N18 -cycloneive_lcell_comb \D[0]~48 ( -// Equation(s): -// \D[0]~48_combout = (\D[0]~42_combout ) # ((\Equal2~0_combout & ((\D[0]~47_combout ) # (\z80_|address_pins_|abus[0]~18_combout )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|address_pins_|abus[0]~18_combout ), - .datac(\D[0]~42_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~48 .lut_mask = 16'hFEF0; -defparam \D[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \D[0]~49 ( -// Equation(s): -// \D[0]~49_combout = ((\D[0]~48_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\D[0]~30_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\D[0]~48_combout ), - .cin(gnd), - .combout(\D[0]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~49 .lut_mask = 16'hF755; -defparam \D[0]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[0]~49_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[0]~15_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[0]~15_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[0]~49_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~15_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N15 -dffeas \z80_|data_pins_|dout[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~14 ( -// Equation(s): -// \z80_|bus_control_|db[0]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(gnd), - .datac(\z80_|data_pins_|dout [0]), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~14 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~15 ( -// Equation(s): -// \z80_|bus_control_|db[0]~15_combout = ((\z80_|bus_control_|db[0]~14_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~14_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~15 .lut_mask = 16'hCF4F; -defparam \z80_|bus_control_|db[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N1 -dffeas \z80_|ir_|opcode[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[0]~15_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hAB00; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mWrite~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # -// (!\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~4_combout & (\z80_|execute_|setM1~56_combout & \z80_|execute_|ctl_sw_2u~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~4_combout ), - .datac(\z80_|execute_|setM1~56_combout ), - .datad(\z80_|execute_|ctl_sw_2u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((\z80_|execute_|ctl_sw_2u~5_combout & !\z80_|execute_|ctl_reg_gp_sel~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h3B00; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N8 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[5]~1_combout = (\z80_|bus_control_|db[5]~17_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|bus_control_|db[5]~17_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|execute_|ctl_sw_1d~6_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[5]~1 .lut_mask = 16'hFBAA; -defparam \z80_|sw1_|db_down[5]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N0 +// Location: LCCOMB_X36_Y11_N22 cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( // Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[5]~29_combout ) # ((\z80_|alu_|db_high[1]~7_combout & \z80_|execute_|ctl_flags_alu~16_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (\z80_|alu_|db_high[1]~7_combout & ((\z80_|execute_|ctl_flags_alu~16_combout )))) +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|alu_control_|db[5]~15_combout +// & (\z80_|alu_|db_high[1]~20_combout & ((\z80_|execute_|ctl_flags_alu~15_combout )))) - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_|db_high[1]~7_combout ), - .datac(\z80_|alu_control_|db[5]~29_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .dataa(\z80_|alu_control_|db[5]~15_combout ), + .datab(\z80_|alu_|db_high[1]~20_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), .cin(gnd), .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), .cout()); @@ -49917,7 +39995,7 @@ defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y15_N1 +// Location: FF_X36_Y11_N23 dffeas \z80_|alu_flags_|flags_yf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), @@ -49936,133 +40014,76 @@ defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; defparam \z80_|alu_flags_|flags_yf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~27 ( +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( // Equation(s): -// \z80_|alu_control_|db[5]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) +// \z80_|alu_control_|db[5]~13_combout = (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|flags_yf~q & (!\z80_|execute_|ctl_flags_oe~2_combout & +// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .dataa(\z80_|alu_flags_|flags_yf~q ), .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|flags_yf~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|out[6]~2_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~27_combout ), + .combout(\z80_|alu_control_|db[5]~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~27 .lut_mask = 16'hFC54; -defparam \z80_|alu_control_|db[5]~27 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hAF8C; +defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~28 ( +// Location: LCCOMB_X34_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( // Equation(s): -// \z80_|alu_control_|db[5]~28_combout = (\z80_|sw1_|db_down[5]~1_combout & (\z80_|alu_control_|db[5]~27_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) +// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|sw1_|db_down[5]~1_combout ), + .dataa(\z80_|sw1_|db_down[5]~0_combout ), + .datab(\z80_|alu_control_|db[5]~13_combout ), .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datad(\z80_|alu_control_|db[5]~27_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~28_combout ), + .combout(\z80_|alu_control_|db[5]~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~28 .lut_mask = 16'hC400; -defparam \z80_|alu_control_|db[5]~28 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; +defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~29 ( +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( // Equation(s): -// \z80_|alu_control_|db[5]~29_combout = ((\z80_|alu_control_|db[5]~28_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) +// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~25_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(\z80_|alu_control_|db[5]~28_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_|db[5]~24_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .dataa(\z80_|alu_control_|db[6]~11_combout ), + .datab(\z80_|alu_|db[5]~25_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[5]~14_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~29_combout ), + .combout(\z80_|alu_control_|db[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~29 .lut_mask = 16'hB3BB; -defparam \z80_|alu_control_|db[5]~29 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hDF55; +defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N28 -cycloneive_lcell_comb \D[5]~68 ( +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \D[0]~107 ( // Equation(s): -// \D[5]~68_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) +// \D[0]~107_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout ))) - .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), .cin(gnd), - .combout(\D[5]~68_combout ), + .combout(\D[0]~107_combout ), .cout()); // synopsys translate_off -defparam \D[5]~68 .lut_mask = 16'h0040; -defparam \D[5]~68 .sum_lutc_input = "datac"; +defparam \D[0]~107 .lut_mask = 16'hFF40; +defparam \D[0]~107 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y11_N0 +// Location: M9K_X22_Y6_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -50070,7 +40091,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), .ena1(vcc), @@ -50078,10 +40099,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50119,7 +40140,7 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y30_N0 +// Location: M9K_X22_Y9_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -50127,7 +40148,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), .ena1(vcc), @@ -50135,10 +40156,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50176,7 +40197,7 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; // synopsys translate_on -// Location: M9K_X33_Y32_N0 +// Location: M9K_X22_Y7_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -50184,7 +40205,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .ena1(vcc), @@ -50192,10 +40213,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50233,103 +40254,102 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Location: LCCOMB_X29_Y10_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hFC22; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hAFC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(vcc), +// Location: M9K_X33_Y23_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y24_N0 +// Location: LCCOMB_X29_Y10_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -50339,16 +40359,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -50402,7 +40422,65 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y6_N0 +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -50412,16 +40490,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50460,7 +40538,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: M9K_X33_Y23_N0 +// Location: M9K_X33_Y29_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), .portare(vcc), @@ -50470,16 +40548,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -50532,104 +40610,104 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N6 +// Location: LCCOMB_X29_Y10_N0 cycloneive_lcell_comb \Mux2~0 ( // Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) +// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .cin(gnd), .combout(\Mux2~0_combout ), .cout()); // synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hCEC2; +defparam \Mux2~0 .lut_mask = 16'hBA98; defparam \Mux2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N12 +// Location: LCCOMB_X29_Y10_N2 cycloneive_lcell_comb \Mux2~1 ( // Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # (!\Mux2~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) +// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), .datad(\Mux2~0_combout ), .cin(gnd), .combout(\Mux2~1_combout ), .cout()); // synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hF588; +defparam \Mux2~1 .lut_mask = 16'hBBC0; defparam \Mux2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N2 -cycloneive_lcell_comb \D[5]~88 ( +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \D[5]~110 ( // Equation(s): -// \D[5]~88_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux2~1_combout ))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )))) +// \D[5]~110_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), .datad(\Mux2~1_combout ), .cin(gnd), - .combout(\D[5]~88_combout ), + .combout(\D[5]~110_combout ), .cout()); // synopsys translate_off -defparam \D[5]~88 .lut_mask = 16'hBA8A; -defparam \D[5]~88 .sum_lutc_input = "datac"; +defparam \D[5]~110 .lut_mask = 16'hAEA2; +defparam \D[5]~110 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N10 -cycloneive_lcell_comb \D[5]~69 ( +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \D[5]~85 ( // Equation(s): -// \D[5]~69_combout = (\D[5]~68_combout & (\D[5]~88_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~68_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) +// \D[5]~85_combout = (\D[5]~84_combout & (\D[5]~110_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout ))) - .dataa(\D[5]~68_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .dataa(\D[5]~84_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), .datac(\z80_|data_pins_|dout [5]), - .datad(\D[5]~88_combout ), + .datad(\D[5]~110_combout ), .cin(gnd), - .combout(\D[5]~69_combout ), + .combout(\D[5]~85_combout ), .cout()); // synopsys translate_off -defparam \D[5]~69 .lut_mask = 16'hF351; -defparam \D[5]~69 .sum_lutc_input = "datac"; +defparam \D[5]~85 .lut_mask = 16'hF351; +defparam \D[5]~85 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N14 -cycloneive_lcell_comb \D[5]~80 ( +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \D[5]~99 ( // Equation(s): -// \D[5]~80_combout = (\D[5]~69_combout ) # (!\D[0]~30_combout ) +// \D[5]~99_combout = (\D[5]~85_combout ) # (!\D[0]~107_combout ) - .dataa(gnd), + .dataa(\D[0]~107_combout ), .datab(gnd), - .datac(\D[0]~30_combout ), - .datad(\D[5]~69_combout ), + .datac(gnd), + .datad(\D[5]~85_combout ), .cin(gnd), - .combout(\D[5]~80_combout ), + .combout(\D[5]~99_combout ), .cout()); // synopsys translate_off -defparam \D[5]~80 .lut_mask = 16'hFF0F; -defparam \D[5]~80 .sum_lutc_input = "datac"; +defparam \D[5]~99 .lut_mask = 16'hFF55; +defparam \D[5]~99 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N22 +// Location: LCCOMB_X32_Y13_N14 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[5]~80_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~17_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[5]~17_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[5]~15_combout ) # ((\D[5]~99_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[5]~99_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[5]~17_combout ), - .datad(\D[5]~80_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[5]~99_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), .cout()); @@ -50638,7 +40716,7 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N23 +// Location: FF_X32_Y13_N15 dffeas \z80_|data_pins_|dout[5] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), @@ -50657,49 +40735,49 @@ defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~16 ( +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( // Equation(s): -// \z80_|bus_control_|db[5]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|bus_control_|db[0]~4_combout ), - .datab(\z80_|data_pins_|dout [5]), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [5]), + .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~16_combout ), + .combout(\z80_|bus_control_|db[5]~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~16 .lut_mask = 16'h88AA; -defparam \z80_|bus_control_|db[5]~16 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF300; +defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~17 ( +// Location: LCCOMB_X34_Y10_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( // Equation(s): -// \z80_|bus_control_|db[5]~17_combout = ((\z80_|bus_control_|db[5]~16_combout & ((\z80_|alu_control_|db[5]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|alu_control_|db[5]~29_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[5]~16_combout ), + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|alu_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[5]~14_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~17_combout ), + .combout(\z80_|bus_control_|db[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~17 .lut_mask = 16'hDF0F; -defparam \z80_|bus_control_|db[5]~17 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hF755; +defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N3 +// Location: FF_X34_Y10_N13 dffeas \z80_|ir_|opcode[5] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[5]~17_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|bus_control_|db[5]~15_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), @@ -50710,642 +40788,513 @@ defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( +// Location: LCCOMB_X37_Y15_N20 +cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( // Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [5])) +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|ir_|opcode [5] & +// ((\z80_|pla_decode_|Equal3~2_combout )))) - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3350; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N21 +dffeas \z80_|decode_state_|DFFE_inst4 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_inst4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N4 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Equation(s): +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), + .combout(\z80_|decode_state_|use_ixiy~combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h2020; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Location: LCCOMB_X34_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( // Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) +// \z80_|execute_|ctl_mRead~23_combout = (!\z80_|decode_state_|use_ixiy~combout & (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sel_wz~7_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~20_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( -// Equation(s): -// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|ctl_ir_we~12_combout ) # (((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|fMWrite~1_combout )) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|fMWrite~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hCFEF; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|fMRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .datab(\z80_|execute_|fMRead~15_combout ), - .datac(\z80_|execute_|fMRead~11_combout ), - .datad(\z80_|execute_|fMRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hAAEF; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( -// Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ctl_mRead~16_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|fMRead~27_combout ) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|fMRead~27_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'h0F8F; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( -// Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), .datad(\z80_|pla_decode_|Equal33~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), + .combout(\z80_|execute_|ctl_mRead~23_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hC800; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( -// Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|fMRead~30_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout ) # (\z80_|execute_|ctl_ir_we~9_combout )))) - - .dataa(\z80_|execute_|fMRead~30_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( -// Equation(s): -// \z80_|execute_|fMRead~29_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|execute_|nextM~6_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|nextM~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( -// Equation(s): -// \z80_|execute_|fMRead~32_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( -// Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~29_combout ) # ((\z80_|execute_|fMRead~32_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ))) - - .dataa(\z80_|execute_|fMRead~31_combout ), - .datab(\z80_|execute_|fMRead~29_combout ), - .datac(\z80_|execute_|fMRead~32_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( -// Equation(s): -// \z80_|execute_|fMRead~37_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~17_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h00A8; -defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N12 +// Location: LCCOMB_X39_Y18_N16 cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( // Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|ctl_mRead~17_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )))) # -// (!\z80_|execute_|ctl_alu_shift_oe~14_combout & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) +// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMWrite~3_combout )) - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|execute_|fMWrite~3_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~34_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFBFF; defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Location: LCCOMB_X41_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( // Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|fMRead~37_combout ) # (!\z80_|execute_|fMRead~34_combout ))) +// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) - .dataa(\z80_|execute_|fMRead~28_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~37_combout ), - .datad(\z80_|execute_|fMRead~34_combout ), + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), + .combout(\z80_|execute_|fMRead~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Location: LCCOMB_X37_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( // Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) +// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), + .combout(\z80_|execute_|fMRead~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC800; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Location: LCCOMB_X37_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( // Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~17_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_mRead~32_combout ))) +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) - .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|fMRead~29_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .datab(\z80_|execute_|fMRead~31_combout ), + .datac(\z80_|execute_|fMRead~30_combout ), + .datad(\z80_|execute_|fMRead~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~53_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datab(\z80_|execute_|ctl_inc_cy~77_combout ), + .datac(\z80_|execute_|ctl_inc_cy~53_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_mRead~23_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~23_combout ), .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), + .combout(\z80_|execute_|fMRead~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( -// Equation(s): -// \z80_|execute_|fMRead~20_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|fMRead~19_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|fMWrite~3_combout ), - .datad(\z80_|execute_|fMRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h0F0E; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N22 +// Location: LCCOMB_X39_Y18_N18 cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( // Equation(s): -// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~7_combout & !\z80_|pla_decode_|Equal6~1_combout ))) +// \z80_|execute_|fMRead~10_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0002; +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0100; defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Location: LCCOMB_X39_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( // Equation(s): -// \z80_|execute_|fMRead~17_combout = (((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~32_combout )) # (!\z80_|execute_|pc_inc_hold~18_combout )) # (!\z80_|execute_|nextM~4_combout ) +// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|pc_inc_hold~28_combout )) - .dataa(\z80_|execute_|nextM~4_combout ), - .datab(\z80_|execute_|pc_inc_hold~18_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|nextM~3_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), + .combout(\z80_|execute_|fMRead~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Location: LCCOMB_X39_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( // Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~17_combout )) # (!\z80_|execute_|fMRead~10_combout ))) - - .dataa(\z80_|execute_|fMRead~10_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( -// Equation(s): -// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~18_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|fMRead~21_combout ))) +// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|fMRead~10_combout ))) .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~21_combout ), - .datac(\z80_|execute_|fMRead~20_combout ), - .datad(\z80_|execute_|fMRead~18_combout ), + .datab(\z80_|execute_|fMRead~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|fMRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hAAA2; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fMRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_mRead~6_combout )))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|fMWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h00FE; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|fMRead~14_combout ), + .datab(\z80_|execute_|fMRead~11_combout ), + .datac(\z80_|execute_|fMRead~13_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Equation(s): +// \z80_|execute_|fMRead~20_combout = (((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~19_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datab(\z80_|execute_|fMRead~19_combout ), + .datac(\z80_|execute_|fMRead~15_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~48 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~48_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~48 .lut_mask = 16'hE0C0; +defparam \z80_|execute_|pc_inc_hold~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( +// Equation(s): +// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_mRead~18_combout & +// ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_mRead~18_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFAC8; defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y14_N8 +// Location: LCCOMB_X38_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|fMRead~2_combout ))) + + .dataa(\z80_|execute_|fMRead~2_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|fMRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N10 cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( // Equation(s): -// \z80_|execute_|fMRead~23_combout = (((\z80_|execute_|fMRead~22_combout ) # (!\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) +// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|pc_inc_hold~48_combout ) # ((\z80_|execute_|fMRead~22_combout ) # (\z80_|execute_|fMRead~21_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|pc_inc_hold~48_combout ), .datac(\z80_|execute_|fMRead~22_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), + .datad(\z80_|execute_|fMRead~21_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~23_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hFFFD; defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_mRead~38_combout ) # ((!\z80_|execute_|fMRead~5_combout ) # (!\z80_|execute_|fMRead~4_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|fMRead~4_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( -// Equation(s): -// \z80_|execute_|fMRead~25_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (((\z80_|execute_|ctl_mRead~20_combout ) # (\z80_|execute_|ctl_mRead~19_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (\z80_|execute_|ctl_ir_we~4_combout & -// ((\z80_|execute_|ctl_mRead~20_combout ) # (\z80_|execute_|ctl_mRead~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~39_combout = (\z80_|execute_|ixy_d~4_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'hF800; -defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N2 +// Location: LCCOMB_X36_Y12_N8 cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( // Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout ))) +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - .dataa(\z80_|execute_|fMRead~24_combout ), - .datab(\z80_|execute_|fMRead~25_combout ), - .datac(\z80_|execute_|pc_inc_hold~39_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hCCEC; defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( +// Location: LCCOMB_X38_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( // Equation(s): -// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~16_combout ) # ((\z80_|execute_|fMRead~35_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~26_combout ))) +// \z80_|execute_|fMRead~25_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|fMRead~24_combout ) - .dataa(\z80_|execute_|fMRead~16_combout ), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|execute_|fMRead~23_combout ), - .datad(\z80_|execute_|fMRead~26_combout ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|fMRead~24_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~36_combout ), + .combout(\z80_|execute_|fMRead~25_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'h2F0F; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y13_N28 +// Location: LCCOMB_X37_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~26_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|execute_|fMRead~3_combout ) + + .dataa(\z80_|execute_|fMRead~26_combout ), + .datab(\z80_|execute_|fMRead~3_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|fMRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~27_combout ))) + + .dataa(\z80_|execute_|fMRead~32_combout ), + .datab(\z80_|execute_|fMRead~20_combout ), + .datac(\z80_|execute_|fMRead~23_combout ), + .datad(\z80_|execute_|fMRead~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Equation(s): +// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|fMRead~0_combout ))) + + .dataa(\z80_|execute_|fMRead~34_combout ), + .datab(\z80_|execute_|fMRead~33_combout ), + .datac(\z80_|execute_|fMRead~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N30 cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( // Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~36_combout & \z80_|sequencer_|DFFE_T2_ff~q )) +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q )) - .dataa(\z80_|execute_|fMRead~36_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .dataa(gnd), + .datab(\z80_|execute_|fMRead~35_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), .cin(gnd), .combout(\z80_|pin_control_|bus_db_pin_re~combout ), .cout()); // synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hEECC; +defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y24_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), .ena1(vcc), @@ -51353,75 +41302,132 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), +// Location: LCCOMB_X32_Y14_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), .ena1(vcc), @@ -51429,68 +41435,125 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N2 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ) # -// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout )) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hBC8C; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC64; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), .portaaddrstall(gnd), @@ -51499,16 +41562,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51516,54 +41579,54 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -51572,56 +41635,56 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; // synopsys translate_on -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -51630,56 +41693,56 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; // synopsys translate_on -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), .portare(vcc), .portaaddrstall(gnd), @@ -51688,16 +41751,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51705,161 +41768,2152 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N0 -cycloneive_lcell_comb \Mux0~0 ( +// Location: LCCOMB_X32_Y18_N0 +cycloneive_lcell_comb \Selector1~0 ( // Equation(s): -// \Mux0~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~16_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~16_combout & -// ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) # (!\z80_|address_pins_|abus[14]~16_combout & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) +// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .cin(gnd), - .combout(\Mux0~0_combout ), + .combout(\Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hDC98; -defparam \Mux0~0 .sum_lutc_input = "datac"; +defparam \Selector1~0 .lut_mask = 16'hBA98; +defparam \Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N18 -cycloneive_lcell_comb \Mux0~1 ( +// Location: LCCOMB_X32_Y18_N2 +cycloneive_lcell_comb \Selector1~1 ( // Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) +// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\Selector1~0_combout ), .cin(gnd), - .combout(\Mux0~1_combout ), + .combout(\Selector1~1_combout ), .cout()); // synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hDDA0; -defparam \Mux0~1 .sum_lutc_input = "datac"; +defparam \Selector1~1 .lut_mask = 16'hBBC0; +defparam \Selector1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N24 -cycloneive_lcell_comb \D[7]~89 ( +// Location: LCCOMB_X32_Y18_N12 +cycloneive_lcell_comb \D[1]~103 ( // Equation(s): -// \D[7]~89_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )))) +// \D[1]~103_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector1~1_combout +// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), - .datad(\Mux0~1_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .datad(\Selector1~1_combout ), .cin(gnd), - .combout(\D[7]~89_combout ), + .combout(\D[1]~103_combout ), .cout()); // synopsys translate_off -defparam \D[7]~89 .lut_mask = 16'hF2D0; -defparam \D[7]~89 .sum_lutc_input = "datac"; +defparam \D[1]~103 .lut_mask = 16'hF2D0; +defparam \D[1]~103 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N8 -cycloneive_lcell_comb \D[7]~75 ( -// Equation(s): -// \D[7]~75_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~89_combout ) # (!\D[5]~68_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[7]~89_combout ) # (!\D[5]~68_combout )))) +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[5]~68_combout ), - .datad(\D[7]~89_combout ), +// Location: CLKCTRL_G5 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), .cin(gnd), - .combout(\D[7]~75_combout ), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), .cout()); // synopsys translate_off -defparam \D[7]~75 .lut_mask = 16'hBB0B; -defparam \D[7]~75 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N16 -cycloneive_lcell_comb \D[7]~82 ( -// Equation(s): -// \D[7]~82_combout = (\D[7]~75_combout ) # (!\D[0]~30_combout ) +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on - .dataa(\D[0]~30_combout ), +// Location: LCCOMB_X20_Y26_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), .datab(gnd), - .datac(\D[7]~75_combout ), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N1 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N7 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N21 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [5] & !\ula_|ps2_keyboard_|clk_filter [4]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [6]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [5]), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N29 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N23 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [3]))) + + .dataa(\ula_|ps2_keyboard_|Equal0~0_combout ), + .datab(\ula_|ps2_keyboard_|clk_filter [2]), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0002; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), .datad(gnd), .cin(gnd), - .combout(\D[7]~82_combout ), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), .cout()); // synopsys translate_off -defparam \D[7]~82 .lut_mask = 16'hF5F5; -defparam \D[7]~82 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Location: FF_X20_Y26_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[7]~82_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[7]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[7]~9_combout ))) +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[7]~9_combout ), - .datad(\D[7]~82_combout ), + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFC30; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N27 -dffeas \z80_|data_pins_|dout[7] ( +// Location: FF_X20_Y26_N27 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0C00; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N5 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N3 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N1 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & +// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N17 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & +// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [3]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N27 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\PS2_DAT~input_o ), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCCC0; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|always1~0_combout ), + .datab(\ula_|ps2_keyboard_|bit_count [0]), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00D0; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N9 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N15 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [8]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N11 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N11 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N25 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N29 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N1 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [1]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|Equal0~0_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF300; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) + + .dataa(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datab(\PS2_DAT~input_o ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N9 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y20_N1 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~15_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & !\ula_|ps2_keyboard_|shiftreg [7])) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0202; +defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[0][0]~15_combout )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q )) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( +// Equation(s): +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|released~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hC8F0; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N19 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y21_N3 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hFF88; +defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0003; +defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[5][1]~38_combout & (!\ula_|zx_keyboard_|keys[5][1]~35_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & +// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N19 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~31_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h00CC; +defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~23_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~23 .lut_mask = 16'h1010; +defparam \ula_|zx_keyboard_|keys[7][1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[7][2]~32_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q +// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), + .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N9 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \D[1]~30 ( +// Equation(s): +// \D[1]~30_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][1]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~30 .lut_mask = 16'hBB0B; +defparam \D[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hA0A0; +defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~24_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00C0; +defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N17 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & \ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h4040; +defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N17 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; +defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0060; +defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2040; +defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & +// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y21_N7 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|scan_code_ready~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~19 .lut_mask = 16'h0100; +defparam \ula_|zx_keyboard_|keys[7][4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~20 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~20 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[6][4]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~21 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~21_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[6][4]~20_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~21 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[1][1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|zx_keyboard_|keys[1][1]~21_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][1]~21_combout & (\ula_|zx_keyboard_|keys[1][1]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[1][1]~21_combout ), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N13 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~22_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N2 +cycloneive_lcell_comb \D[1]~28 ( +// Equation(s): +// \D[1]~28_combout = (\ula_|zx_keyboard_|keys[0][1]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) # (!\ula_|zx_keyboard_|keys[0][1]~q & +// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][1]~q ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\ula_|zx_keyboard_|keys[1][1]~q ), + .cin(gnd), + .combout(\D[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~28 .lut_mask = 16'hD0DD; +defparam \D[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N26 +cycloneive_lcell_comb \D[1]~29 ( +// Equation(s): +// \D[1]~29_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~28_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~q ), + .datab(\ula_|zx_keyboard_|key_row~0_combout ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\D[1]~28_combout ), + .cin(gnd), + .combout(\D[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~29 .lut_mask = 16'hC400; +defparam \D[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~41_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~42_combout )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; +defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & ((!\ula_|zx_keyboard_|keys[6][1]~40_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N25 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~45_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [7]))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [7]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0002; +defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; +defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0044; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0140; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hF022; +defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~5_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|WideOr16~5_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF808; +defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N31 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N20 +cycloneive_lcell_comb \D[1]~31 ( +// Equation(s): +// \D[1]~31_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~q ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\ula_|zx_keyboard_|keys[7][1]~q ), + .cin(gnd), + .combout(\D[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~31 .lut_mask = 16'hB0BB; +defparam \D[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N18 +cycloneive_lcell_comb \D[1]~32 ( +// Equation(s): +// \D[1]~32_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~30_combout & (\D[1]~29_combout & \D[1]~31_combout ))) + + .dataa(\D[1]~30_combout ), + .datab(\z80_|address_pins_|abus[0]~16_combout ), + .datac(\D[1]~29_combout ), + .datad(\D[1]~31_combout ), + .cin(gnd), + .combout(\D[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~32 .lut_mask = 16'hECCC; +defparam \D[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N4 +cycloneive_lcell_comb \D[1]~33 ( +// Equation(s): +// \D[1]~33_combout = ((\Equal2~0_combout & ((\D[1]~32_combout ))) # (!\Equal2~0_combout & (\D[1]~103_combout ))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[1]~103_combout ), + .datad(\D[1]~32_combout ), + .cin(gnd), + .combout(\D[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~33 .lut_mask = 16'hFB73; +defparam \D[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N8 +cycloneive_lcell_comb \D[1]~34 ( +// Equation(s): +// \D[1]~34_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout & \z80_|data_pins_|dout [1])))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[1]~33_combout ), + .datad(\z80_|data_pins_|dout [1]), + .cin(gnd), + .combout(\D[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~34 .lut_mask = 16'hF151; +defparam \D[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[1]~11_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\D[1]~34_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N19 +dffeas \z80_|data_pins_|dout[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -51868,51 +43922,68 @@ dffeas \z80_|data_pins_|dout[7] ( .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [7]), + .q(\z80_|data_pins_|dout [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[7] .power_up = "low"; +defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~8 ( +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( // Equation(s): -// \z80_|bus_control_|db[7]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - .dataa(\z80_|alu_control_|db[7]~18_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\z80_|alu_control_|db[1]~26_combout ), .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~8_combout ), + .combout(\z80_|bus_control_|db[1]~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~8 .lut_mask = 16'hAF00; -defparam \z80_|bus_control_|db[7]~8 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~9 ( +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( // Equation(s): -// \z80_|bus_control_|db[7]~9_combout = ((\z80_|bus_control_|db[7]~8_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|bus_control_|db[7]~8_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|bus_control_|db[1]~10_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~9_combout ), + .combout(\z80_|bus_control_|db[1]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~9 .lut_mask = 16'hB3F3; -defparam \z80_|bus_control_|db[7]~9 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD0FF; +defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N9 -dffeas \z80_|ir_|opcode[7] ( +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|ir_|opcode[1]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[1]~feeder_combout = \z80_|bus_control_|db[1]~11_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[1]~11_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N15 +dffeas \z80_|ir_|opcode[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[7]~9_combout ), + .d(\z80_|ir_|opcode[1]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -51921,666 +43992,2542 @@ dffeas \z80_|ir_|opcode[7] ( .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [7]), + .q(\z80_|ir_|opcode [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[7] .power_up = "low"; +defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y15_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( // Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), + .combout(\z80_|pla_decode_|Equal40~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Location: LCCOMB_X37_Y11_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( // Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0]))) +// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|ir_|opcode [0]), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .combout(\z80_|pla_decode_|Equal21~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y12_N19 -dffeas \z80_|interrupts_|im1 ( +// Location: LCCOMB_X39_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hC080; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~28_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|pla_decode_|Equal64~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h001F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h153F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0088; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h4000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_flags_cf_cpl~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h040C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout = (((!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .lut_mask = 16'h777F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h0F0C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC0E0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAA8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_nf_we~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & !\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ))) + + .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h0008; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h20A0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal10~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hCECC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~20_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFB3; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'h8500; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~21_combout )) + + .dataa(\z80_|alu_|db[7]~21_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[0]~19_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hF0AA; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout +// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h11D8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y9_N31 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0B00; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~14_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout )) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout )) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hF0E4; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout & \z80_|execute_|ctl_alu_op_low~28_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~12_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFF40; +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~19_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (\z80_|execute_|ctl_state_alu~7_combout )))) # (!\z80_|execute_|ctl_state_alu~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_state_alu~15_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h3F3B; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal68~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF32; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~12_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC0CC; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N4 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~9_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( +// Equation(s): +// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~17_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|bus_control_|db[0]~17_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h22A2; +defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N20 +cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( +// Equation(s): +// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~19_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_|db[0]~19_combout ), + .cin(gnd), + .combout(\z80_|sw2_|db_up[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hFF0F; +defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( +// Equation(s): +// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[0]~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|sw2_|db_up[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8A00; +defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( +// Equation(s): +// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[0]~9_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; +defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~67_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~67 .lut_mask = 16'hFF50; +defparam \ula_|zx_keyboard_|keys[5][0]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0420; +defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[5][0]~81_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h2800; +defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), + .datab(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h7474; +defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N11 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~83_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h0160; +defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'hBABA; +defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~84_combout & ((!\ula_|zx_keyboard_|keys[4][0]~85_combout ))) # (!\ula_|zx_keyboard_|keys[4][0]~84_combout & +// (\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N27 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~86_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \D[0]~49 ( +// Equation(s): +// \D[0]~49_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[5][0]~q ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[0]~49_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~49 .lut_mask = 16'hBB0B; +defparam \D[0]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|ps2_keyboard_|shiftreg [6])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & +// (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8810; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~76_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) + + .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~76 .lut_mask = 16'h3313; +defparam \ula_|zx_keyboard_|keys~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~73 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~73_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~73_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~73 .lut_mask = 16'hF000; +defparam \ula_|zx_keyboard_|keys[4][3]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// ((\ula_|ps2_keyboard_|shiftreg [2]))))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0310; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~74_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h353F; +defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~73_combout & !\ula_|zx_keyboard_|keys~74_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~73_combout ), + .datab(\ula_|zx_keyboard_|keys~74_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'h2F00; +defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~77_combout = (\ula_|zx_keyboard_|keys~76_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~75_combout & ((!\ula_|zx_keyboard_|released~q ))) # +// (!\ula_|zx_keyboard_|keys[0][0]~75_combout & (\ula_|zx_keyboard_|keys[0][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys~76_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~77 .lut_mask = 16'hB0F4; +defparam \ula_|zx_keyboard_|keys[0][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N15 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~71_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~71 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[1][0]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|zx_keyboard_|keys[1][0]~71_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][0]~71_combout & (\ula_|zx_keyboard_|keys[1][0]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[1][0]~71_combout ), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N17 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~72_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N30 +cycloneive_lcell_comb \D[0]~47 ( +// Equation(s): +// \D[0]~47_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & +// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\ula_|zx_keyboard_|keys[1][0]~q ), + .cin(gnd), + .combout(\D[0]~47_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~47 .lut_mask = 16'hD0DD; +defparam \D[0]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~80 .lut_mask = 16'hB1F0; +defparam \ula_|zx_keyboard_|keys[2][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N23 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~80_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~78 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|keys[3][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~79_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (\ula_|zx_keyboard_|keys[3][0]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][0]~78_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N5 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~79_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~1_combout = ((\z80_|address_pins_|DFFE_apin_latch [11]) # (!\ula_|zx_keyboard_|keys[3][0]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [11]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hFF3F; +defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N4 +cycloneive_lcell_comb \D[0]~48 ( +// Equation(s): +// \D[0]~48_combout = (\D[0]~47_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) + + .dataa(\D[0]~47_combout ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|key_row~1_combout ), + .cin(gnd), + .combout(\D[0]~48_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~48 .lut_mask = 16'h8A00; +defparam \D[0]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|shifted~1_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[6][0]~90_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|shifted~1_combout ), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|zx_keyboard_|keys[6][0]~91_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~91_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N21 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~92_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~63_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~63 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[5][4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0303; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[5][4]~63_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|WideOr16~3_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~132 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~132_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~132_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~132 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[7][0]~132 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & ((\ula_|zx_keyboard_|keys[7][0]~87_combout ) # (\ula_|zx_keyboard_|keys[7][0]~132_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~132_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h8880; +defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|zx_keyboard_|keys[7][0]~88_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~88_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) + + .dataa(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N7 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~89_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N28 +cycloneive_lcell_comb \D[0]~50 ( +// Equation(s): +// \D[0]~50_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~q ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~q ), + .cin(gnd), + .combout(\D[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~50 .lut_mask = 16'hB0BB; +defparam \D[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N10 +cycloneive_lcell_comb \D[0]~51 ( +// Equation(s): +// \D[0]~51_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~49_combout & (\D[0]~48_combout & \D[0]~50_combout ))) + + .dataa(\D[0]~49_combout ), + .datab(\z80_|address_pins_|abus[0]~16_combout ), + .datac(\D[0]~48_combout ), + .datad(\D[0]~50_combout ), + .cin(gnd), + .combout(\D[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~51 .lut_mask = 16'hECCC; +defparam \D[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N14 +cycloneive_lcell_comb \D[0]~55 ( +// Equation(s): +// \D[0]~55_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\D[0]~55_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~55 .lut_mask = 16'hE3E0; +defparam \D[0]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \D[0]~56 ( +// Equation(s): +// \D[0]~56_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~55_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\D[0]~55_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~55_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[0]~55_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\D[0]~56_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~56 .lut_mask = 16'hBCB0; +defparam \D[0]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \D[0]~52 ( +// Equation(s): +// \D[0]~52_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~23_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\D[0]~52_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~52 .lut_mask = 16'hF858; +defparam \D[0]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \D[0]~53 ( +// Equation(s): +// \D[0]~53_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ ((\D[0]~52_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & (((!\D[0]~52_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\z80_|address_pins_|abus[15]~22_combout ), + .datac(\D[0]~52_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\D[0]~53_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~53 .lut_mask = 16'h4B48; +defparam \D[0]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \D[0]~54 ( +// Equation(s): +// \D[0]~54_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~52_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~52_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~53_combout )) # (!\D[0]~52_combout & ((\D[0]~53_combout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[0]~52_combout ), + .datad(\D[0]~53_combout ), + .cin(gnd), + .combout(\D[0]~54_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~54 .lut_mask = 16'hC3E0; +defparam \D[0]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \D[0]~106 ( +// Equation(s): +// \D[0]~106_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~56_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~54_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[0]~56_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[0]~56_combout ), + .datad(\D[0]~54_combout ), + .cin(gnd), + .combout(\D[0]~106_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~106 .lut_mask = 16'hF4B0; +defparam \D[0]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \D[0]~57 ( +// Equation(s): +// \D[0]~57_combout = ((\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~1_combout ), + .datab(\D[0]~51_combout ), + .datac(\D[0]~106_combout ), + .datad(\Equal2~0_combout ), + .cin(gnd), + .combout(\D[0]~57_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~57 .lut_mask = 16'hDDF5; +defparam \D[0]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \D[0]~58 ( +// Equation(s): +// \D[0]~58_combout = (\D[0]~57_combout & (((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[0]~57_combout & (!\Equal2~1_combout & ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\D[0]~57_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\D[0]~58_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~58 .lut_mask = 16'hC0F5; +defparam \D[0]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~17_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\D[0]~58_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N1 +dffeas \z80_|data_pins_|dout[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Equation(s): +// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|data_pins_|dout [0]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hC0CC; +defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N28 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Equation(s): +// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~16_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF55; +defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y13_N27 +dffeas \z80_|ir_|opcode[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .asdata(\z80_|bus_control_|db[0]~17_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|im2~q ), - .datac(\z80_|interrupts_|im1~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hF400; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h5D50; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hCECF; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( -// Equation(s): -// \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|bus_control_|db[0]~4_combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'h88AA; -defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( -// Equation(s): -// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[3]~20_combout ), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hBB3B; -defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N23 -dffeas \z80_|ir_|opcode[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[3]~21_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [3]), + .q(\z80_|ir_|opcode [0]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[3] .power_up = "low"; +defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( +// Location: LCCOMB_X39_Y16_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( // Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .dataa(\z80_|ir_|opcode [0]), .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~1_combout ), + .combout(\z80_|pla_decode_|Equal63~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N20 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Location: LCCOMB_X40_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( // Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N20 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h070F; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( +// Equation(s): +// \z80_|alu_control_|db[6]~10_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) + + .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFF5; +defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( +// Equation(s): +// \z80_|alu_control_|db[6]~11_combout = (\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_sw_1d~7_combout ) # (\z80_|execute_|ctl_reg_out_lo~8_combout )) + + .dataa(\z80_|alu_control_|db[6]~10_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), + .combout(\z80_|alu_control_|db[6]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h1010; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFEFE; +defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N8 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( // Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|decode_state_|in_halt~q ))) +// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~17_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~17_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - .dataa(\z80_|pla_decode_|Equal77~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|decode_state_|in_halt~0_combout ), + .dataa(\z80_|alu_|db[4]~17_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), .cin(gnd), - .combout(\z80_|decode_state_|in_halt~1_combout ), + .combout(\z80_|alu_control_|db[4]~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hFF08; -defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; +defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y12_N9 -dffeas \z80_|decode_state_|in_halt ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|in_halt~1_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|in_halt~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; -defparam \z80_|decode_state_|in_halt .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal77~0_combout ))) +// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|alu_control_|db[4]~30_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .combout(\z80_|alu_control_|db[4]~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h00B0; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Location: LCCOMB_X32_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) +// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[4]~31_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .combout(\z80_|alu_control_|db[4]~32_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) +// \ula_|zx_keyboard_|keys[2][4]~119_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h0420; +defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Location: LCCOMB_X29_Y18_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = ((\z80_|execute_|ctl_bus_db_we~4_combout ) # ((!\z80_|execute_|ctl_apin_mux~0_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout ))) # (!\z80_|execute_|ctl_bus_db_we~5_combout ) +// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - .dataa(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datac(\z80_|execute_|ctl_sw_2u~3_combout ), - .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datab(\ula_|zx_keyboard_|keys[2][4]~119_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Location: LCCOMB_X29_Y18_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~95 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h2220; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_ir_we~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFE0; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~6_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_db_we~3_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~124_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~124 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[5][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~125 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~125_combout = (\ula_|zx_keyboard_|keys[5][4]~124_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & ((\ula_|zx_keyboard_|keys[5][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][4]~124_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) +// \ula_|zx_keyboard_|keys[2][4]~95_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[5][4]~124_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~125_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~125 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][4]~125 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N17 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~126_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [6])) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|shiftreg -// [6])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(gnd), + .datab(gnd), + .datac(\ula_|zx_keyboard_|shifted~q ), .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~126_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~95_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~126 .lut_mask = 16'h4422; -defparam \ula_|zx_keyboard_|keys[4][4]~126 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~95 .lut_mask = 16'hAFAA; +defparam \ula_|zx_keyboard_|keys[2][4]~95 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~127_combout = (\ula_|zx_keyboard_|keys[4][4]~126_combout & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[4][4]~126_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~127 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~128_combout = (\ula_|zx_keyboard_|keys[4][4]~127_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (\ula_|zx_keyboard_|keys[4][4]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][4]~127_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][4]~127_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~128 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][4]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N23 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~128_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \D[4]~64 ( -// Equation(s): -// \D[4]~64_combout = (\ula_|zx_keyboard_|keys[5][4]~q & (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][4]~q )))) # (!\ula_|zx_keyboard_|keys[5][4]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\D[4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~64 .lut_mask = 16'hCF45; -defparam \D[4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~119_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg -// [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~119 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[3][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~138 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~138_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|keys[3][4]~119_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~138_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~138 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[3][4]~138 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~120 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~120_combout = (\ula_|zx_keyboard_|keys[3][4]~132_combout & ((\ula_|zx_keyboard_|keys[3][4]~138_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][4]~138_combout & -// (\ula_|zx_keyboard_|keys[3][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][4]~132_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][4]~132_combout ), - .datab(\ula_|zx_keyboard_|keys[3][4]~138_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~120_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~120 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][4]~120 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N29 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~120_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 +// Location: LCCOMB_X29_Y18_N22 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~121 ( // Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|zx_keyboard_|keys[2][4]~120_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~120_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\ula_|zx_keyboard_|keys[2][4]~120_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[2][4]~121_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h50FA; defparam \ula_|zx_keyboard_|keys[2][4]~121 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y15_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|zx_keyboard_|keys[2][4]~121_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~122 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[2][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~123_combout = (\ula_|zx_keyboard_|keys[2][4]~122_combout & (!\ula_|zx_keyboard_|keys[2][4]~97_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~122_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[2][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~122_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~123 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N19 +// Location: FF_X29_Y18_N23 dffeas \ula_|zx_keyboard_|keys[2][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~123_combout ), + .d(\ula_|zx_keyboard_|keys[2][4]~121_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52596,46 +46543,80 @@ defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \D[4]~63 ( +// Location: LCCOMB_X29_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( // Equation(s): -// \D[4]~63_combout = (\z80_|address_pins_|abus[10]~22_combout & (((\z80_|address_pins_|abus[11]~21_combout )) # (!\ula_|zx_keyboard_|keys[3][4]~q ))) # (!\z80_|address_pins_|abus[10]~22_combout & (!\ula_|zx_keyboard_|keys[2][4]~q & -// ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][4]~q )))) +// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|extended~q ))) - .dataa(\z80_|address_pins_|abus[10]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[3][4]~q ), - .datac(\z80_|address_pins_|abus[11]~21_combout ), - .datad(\ula_|zx_keyboard_|keys[2][4]~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\D[4]~63_combout ), + .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), .cout()); // synopsys translate_off -defparam \D[4]~63 .lut_mask = 16'hA2F3; -defparam \D[4]~63 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~129 ( +// Location: LCCOMB_X29_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~136 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~129_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) +// \ula_|zx_keyboard_|keys[3][4]~136_combout = (\ula_|zx_keyboard_|keys[3][4]~117_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [4]))) - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .dataa(\ula_|zx_keyboard_|keys[3][4]~117_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~129_combout ), + .combout(\ula_|zx_keyboard_|keys[3][4]~136_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~129 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][4]~129 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][4]~136 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[3][4]~136 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y15_N25 -dffeas \ula_|zx_keyboard_|keys[7][4] ( +// Location: LCCOMB_X28_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~130_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~130 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[3][4]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|zx_keyboard_|keys[3][4]~136_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[3][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~136_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~136_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N9 +dffeas \ula_|zx_keyboard_|keys[3][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~129_combout ), + .d(\ula_|zx_keyboard_|keys[3][4]~118_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52644,52 +46625,124 @@ dffeas \ula_|zx_keyboard_|keys[7][4] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~130 ( +// Location: LCCOMB_X29_Y19_N18 +cycloneive_lcell_comb \D[4]~78 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~130_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) +// \D[4]~78_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~q ), + .cin(gnd), + .combout(\D[4]~78_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~78 .lut_mask = 16'h8ACF; +defparam \D[4]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~126_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~130_combout ), + .combout(\ula_|zx_keyboard_|keys[5][4]~128_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~130 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[6][4]~130 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][4]~128 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[5][4]~128 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~131 ( +// Location: LCCOMB_X28_Y19_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~129 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~131_combout = (\ula_|zx_keyboard_|keys[6][4]~130_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~130_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) +// \ula_|zx_keyboard_|keys[5][4]~129_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[5][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~128_combout & +// (\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[6][4]~130_combout ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~128_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~131_combout ), + .combout(\ula_|zx_keyboard_|keys[5][4]~129_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~131 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[6][4]~131 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][4]~129 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][4]~129 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y14_N31 +// Location: FF_X28_Y19_N9 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~129_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~127_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~20_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~20_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~127 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[6][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N5 dffeas \ula_|zx_keyboard_|keys[6][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~131_combout ), + .d(\ula_|zx_keyboard_|keys[6][4]~127_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52705,46 +46758,257 @@ defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \D[4]~65 ( +// Location: LCCOMB_X28_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( // Equation(s): -// \D[4]~65_combout = (\z80_|address_pins_|abus[15]~17_combout & (((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~17_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & -// ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) +// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - .dataa(\z80_|address_pins_|abus[15]~17_combout ), - .datab(\ula_|zx_keyboard_|keys[7][4]~q ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\ula_|zx_keyboard_|keys[6][4]~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), .cin(gnd), - .combout(\D[4]~65_combout ), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \D[4]~65 .lut_mask = 16'hB0BB; -defparam \D[4]~65 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~118 ( +// Location: LCCOMB_X28_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~118_combout = (\ula_|zx_keyboard_|keys[0][4]~99_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~99_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) +// \ula_|zx_keyboard_|keys[7][4]~51_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - .dataa(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~99_combout ), + .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) +// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~1_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N11 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N30 +cycloneive_lcell_comb \D[4]~79 ( +// Equation(s): +// \D[4]~79_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & +// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .cin(gnd), + .combout(\D[4]~79_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~79 .lut_mask = 16'h8ACF; +defparam \D[4]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & +// \ula_|zx_keyboard_|extended~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h4422; +defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][4]~122_combout ))) + + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N25 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\ula_|zx_keyboard_|keys[4][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [12]), + .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hF3FF; +defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N8 +cycloneive_lcell_comb \D[4]~80 ( +// Equation(s): +// \D[4]~80_combout = (\D[4]~79_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), + .datab(\D[4]~79_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|key_row~3_combout ), + .cin(gnd), + .combout(\D[4]~80_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~80 .lut_mask = 16'hC400; +defparam \D[4]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFAAA; +defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~97_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~97 .lut_mask = 16'h0060; +defparam \ula_|zx_keyboard_|keys[0][4]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~116_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & +// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~111_combout ), .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .datad(\ula_|zx_keyboard_|keys[0][4]~97_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~118_combout ), + .combout(\ula_|zx_keyboard_|keys[0][4]~116_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~118 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[0][4]~118 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[0][4]~116 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][4]~116 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N3 +// Location: FF_X29_Y18_N11 dffeas \ula_|zx_keyboard_|keys[0][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~118_combout ), + .d(\ula_|zx_keyboard_|keys[0][4]~116_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52760,28 +47024,28 @@ defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~117 ( +// Location: LCCOMB_X29_Y19_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~115 ( // Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~117_combout = (\ula_|zx_keyboard_|keys[1][4]~25_combout & ((\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # -// (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) +// \ula_|zx_keyboard_|keys[1][4]~115_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # +// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - .dataa(\ula_|zx_keyboard_|released~q ), + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~117_combout ), + .combout(\ula_|zx_keyboard_|keys[1][4]~115_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~117 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[1][4]~117 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[1][4]~115 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][4]~115 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y14_N3 +// Location: FF_X29_Y19_N7 dffeas \ula_|zx_keyboard_|keys[1][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~117_combout ), + .d(\ula_|zx_keyboard_|keys[1][4]~115_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52797,308 +47061,42 @@ defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N4 -cycloneive_lcell_comb \D[4]~62 ( +// Location: LCCOMB_X29_Y19_N28 +cycloneive_lcell_comb \D[4]~77 ( // Equation(s): -// \D[4]~62_combout = (\ula_|zx_keyboard_|keys[0][4]~q & (\z80_|address_pins_|abus[8]~20_combout & ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][4]~q )))) # (!\ula_|zx_keyboard_|keys[0][4]~q & -// (((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][4]~q )))) +// \D[4]~77_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - .dataa(\ula_|zx_keyboard_|keys[0][4]~q ), - .datab(\z80_|address_pins_|abus[8]~20_combout ), - .datac(\z80_|address_pins_|abus[9]~19_combout ), + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), .datad(\ula_|zx_keyboard_|keys[1][4]~q ), .cin(gnd), - .combout(\D[4]~62_combout ), + .combout(\D[4]~77_combout ), .cout()); // synopsys translate_off -defparam \D[4]~62 .lut_mask = 16'hD0DD; -defparam \D[4]~62 .sum_lutc_input = "datac"; +defparam \D[4]~77 .lut_mask = 16'h8ACF; +defparam \D[4]~77 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \D[4]~66 ( +// Location: LCCOMB_X29_Y19_N26 +cycloneive_lcell_comb \D[4]~81 ( // Equation(s): -// \D[4]~66_combout = (\D[4]~64_combout & (\D[4]~63_combout & (\D[4]~65_combout & \D[4]~62_combout ))) +// \D[4]~81_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~78_combout & (\D[4]~80_combout & \D[4]~77_combout ))) - .dataa(\D[4]~64_combout ), - .datab(\D[4]~63_combout ), - .datac(\D[4]~65_combout ), - .datad(\D[4]~62_combout ), + .dataa(\z80_|address_pins_|abus[0]~16_combout ), + .datab(\D[4]~78_combout ), + .datac(\D[4]~80_combout ), + .datad(\D[4]~77_combout ), .cin(gnd), - .combout(\D[4]~66_combout ), + .combout(\D[4]~81_combout ), .cout()); // synopsys translate_off -defparam \D[4]~66 .lut_mask = 16'h8000; -defparam \D[4]~66 .sum_lutc_input = "datac"; +defparam \D[4]~81 .lut_mask = 16'hEAAA; +defparam \D[4]~81 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y32_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y21_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X23_Y21_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y21_N2 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hF388; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y4_N0 +// Location: M9K_X22_Y1_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portawe(vcc), .portare(vcc), @@ -53108,16 +47106,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -53156,7 +47154,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: M9K_X33_Y28_N0 +// Location: M9K_X22_Y22_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -53166,16 +47164,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -53229,7 +47227,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y12_N0 +// Location: M9K_X33_Y3_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(vcc), .portare(vcc), @@ -53239,16 +47237,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -53287,7 +47285,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: M9K_X33_Y30_N0 +// Location: M9K_X22_Y25_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), .portare(vcc), @@ -53297,16 +47295,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -53359,120 +47357,370 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N12 +// Location: LCCOMB_X29_Y14_N2 cycloneive_lcell_comb \Selector4~0 ( // Equation(s): -// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) +// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), .cin(gnd), .combout(\Selector4~0_combout ), .cout()); // synopsys translate_off -defparam \Selector4~0 .lut_mask = 16'hAEA4; +defparam \Selector4~0 .lut_mask = 16'hBA98; defparam \Selector4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N2 +// Location: LCCOMB_X29_Y14_N26 cycloneive_lcell_comb \Selector4~1 ( // Equation(s): // \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & // (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), .datad(\Selector4~0_combout ), .cin(gnd), .combout(\Selector4~1_combout ), .cout()); // synopsys translate_off -defparam \Selector4~1 .lut_mask = 16'hF588; +defparam \Selector4~1 .lut_mask = 16'hF388; defparam \Selector4~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \D[4]~60 ( +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 ( // Equation(s): -// \D[4]~60_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector4~1_combout ))))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .lut_mask = 16'hE5E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .lut_mask = 16'hAFC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \D[4]~109 ( +// Equation(s): +// \D[4]~109_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Selector4~1_combout +// )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ))))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Selector4~1_combout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), + .cin(gnd), + .combout(\D[4]~109_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~109 .lut_mask = 16'hFB40; +defparam \D[4]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \D[4]~97 ( +// Equation(s): +// \D[4]~97_combout = ((\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout )))) # (!\Equal2~1_combout ) .dataa(\Equal2~0_combout ), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), - .datac(\z80_|address_pins_|abus[15]~17_combout ), - .datad(\Selector4~1_combout ), + .datab(\D[4]~81_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[4]~109_combout ), .cin(gnd), - .combout(\D[4]~60_combout ), + .combout(\D[4]~97_combout ), .cout()); // synopsys translate_off -defparam \D[4]~60 .lut_mask = 16'h4540; -defparam \D[4]~60 .sum_lutc_input = "datac"; +defparam \D[4]~97 .lut_mask = 16'hDF8F; +defparam \D[4]~97 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \D[4]~61 ( +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \D[4]~98 ( // Equation(s): -// \D[4]~61_combout = (((\z80_|memory_ifc_|nWR_out~0_combout ) # (\D[4]~60_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|memory_ifc_|nRD_out~2_combout ) +// \D[4]~98_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~97_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[4]~97_combout ) # (!\Equal2~1_combout )))) - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nWR_out~0_combout ), - .datad(\D[4]~60_combout ), + .dataa(\z80_|data_pins_|dout [4]), + .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[4]~97_combout ), .cin(gnd), - .combout(\D[4]~61_combout ), + .combout(\D[4]~98_combout ), .cout()); // synopsys translate_off -defparam \D[4]~61 .lut_mask = 16'hFFF7; -defparam \D[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \D[4]~78 ( -// Equation(s): -// \D[4]~78_combout = (\D[4]~61_combout ) # ((\Equal2~0_combout & ((\D[4]~66_combout ) # (\z80_|address_pins_|abus[0]~18_combout )))) - - .dataa(\D[4]~66_combout ), - .datab(\z80_|address_pins_|abus[0]~18_combout ), - .datac(\D[4]~61_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~78 .lut_mask = 16'hFEF0; -defparam \D[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \D[4]~79 ( -// Equation(s): -// \D[4]~79_combout = ((\D[4]~78_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\D[4]~78_combout ), - .datab(\z80_|data_pins_|dout [4]), - .datac(\D[0]~30_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cin(gnd), - .combout(\D[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~79 .lut_mask = 16'h8FAF; -defparam \D[4]~79 .sum_lutc_input = "datac"; +defparam \D[4]~98 .lut_mask = 16'hBB03; +defparam \D[4]~98 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X32_Y13_N24 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[4]~79_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[4]~19_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[4]~19_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[4]~19_combout ) # ((\D[4]~98_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[4]~98_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\D[4]~79_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[4]~98_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), .cout()); @@ -53500,41 +47748,41 @@ defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N20 +// Location: LCCOMB_X32_Y13_N20 cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( // Equation(s): // \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(gnd), - .datac(\z80_|data_pins_|dout [4]), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|data_pins_|dout [4]), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), .combout(\z80_|bus_control_|db[4]~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hF500; +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88CC; defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N4 +// Location: LCCOMB_X34_Y10_N18 cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( // Equation(s): // \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .dataa(\z80_|bus_control_|db[0]~6_combout ), .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[4]~19_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF0F; +defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF55; defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N5 +// Location: FF_X34_Y10_N19 dffeas \z80_|ir_|opcode[4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|bus_control_|db[4]~19_combout ), @@ -53553,32 +47801,2546 @@ defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X41_Y11_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Location: LCCOMB_X40_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( // Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) +// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), + .datab(gnd), .datac(\z80_|ir_|opcode [3]), - .datad(gnd), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), + .combout(\z80_|pla_decode_|Equal21~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h3030; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N12 +// Location: LCCOMB_X35_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( +// Equation(s): +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|fMRead~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|fMRead~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Equation(s): +// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F0F; +defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( +// Equation(s): +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|fIOWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( +// Equation(s): +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~5_combout ))) + + .dataa(\z80_|execute_|fIOWrite~1_combout ), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|fIOWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & +// (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~15_combout = ((\z80_|execute_|ctl_mWrite~14_combout ) # ((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout ))) # (!\z80_|execute_|ctl_mWrite~13_combout ) + + .dataa(\z80_|execute_|ixy_d~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~13_combout ), + .datac(\z80_|execute_|ctl_mWrite~14_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF7F3; +defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N29 +dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mWrite~15_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N4 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N5 +dffeas \z80_|memory_ifc_|wait_mwr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mwr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y17_N17 +dffeas \z80_|memory_ifc_|mwr_wr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|mwr_wr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N16 +cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(\z80_|memory_ifc_|iorq~0_combout ), + .datac(\z80_|memory_ifc_|mwr_wr~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|memory_ifc_|nWR_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; +defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \D[5]~84 ( +// Equation(s): +// \D[5]~84_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cin(gnd), + .combout(\D[5]~84_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~84 .lut_mask = 16'h0040; +defparam \D[5]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF858; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~0 .lut_mask = 16'hBA98; +defparam \Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \Mux0~1 ( +// Equation(s): +// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datad(\Mux0~0_combout ), + .cin(gnd), + .combout(\Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~1 .lut_mask = 16'hBBC0; +defparam \Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N22 +cycloneive_lcell_comb \D[7]~112 ( +// Equation(s): +// \D[7]~112_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux0~1_combout ))) +// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~112_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~112 .lut_mask = 16'hF4B0; +defparam \D[7]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N30 +cycloneive_lcell_comb \D[7]~94 ( +// Equation(s): +// \D[7]~94_combout = (\D[5]~84_combout & (\D[7]~112_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) + + .dataa(\D[5]~84_combout ), + .datab(\z80_|data_pins_|dout [7]), + .datac(\D[7]~112_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\D[7]~94_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~94 .lut_mask = 16'hC4F5; +defparam \D[7]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \D[7]~102 ( +// Equation(s): +// \D[7]~102_combout = (\D[7]~94_combout ) # (!\D[0]~107_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\D[7]~94_combout ), + .datad(\D[0]~107_combout ), + .cin(gnd), + .combout(\D[7]~102_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~102 .lut_mask = 16'hF0FF; +defparam \D[7]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\D[7]~102_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[7]~7_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[7]~102_combout & (\z80_|bus_control_|db[7]~7_combout +// & ((\z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[7]~102_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N27 +dffeas \z80_|data_pins_|dout[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Equation(s): +// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[7]~18_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N8 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Equation(s): +// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|data_pins_|dout [7]), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|bus_control_|db[7]~5_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hBF0F; +defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N21 +dffeas \z80_|ir_|opcode[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[7]~7_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_ir_we~4_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h3020; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC8C0; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~6_combout = (((\z80_|execute_|ctl_bus_db_we~4_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~2_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~3_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h000F; +defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & ((\ula_|zx_keyboard_|keys[0][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N17 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~48_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~48 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[3][3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), + .datab(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N23 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N22 +cycloneive_lcell_comb \D[2]~35 ( +// Equation(s): +// \D[2]~35_combout = (\z80_|address_pins_|abus[8]~18_combout & (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\z80_|address_pins_|abus[8]~18_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & +// ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) + + .dataa(\z80_|address_pins_|abus[8]~18_combout ), + .datab(\ula_|zx_keyboard_|keys[0][2]~q ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\z80_|address_pins_|abus[9]~17_combout ), + .cin(gnd), + .combout(\D[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~35 .lut_mask = 16'hBB0B; +defparam \D[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h3300; +defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|zx_keyboard_|keys[5][2]~57_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[5][2]~57_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N15 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h0420; +defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[4][2]~59_combout & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~131 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[4][2]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|zx_keyboard_|keys[4][2]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~131_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[4][2]~131_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N15 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \D[2]~37 ( +// Equation(s): +// \D[2]~37_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[5][2]~q ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~37 .lut_mask = 16'hBB0B; +defparam \D[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~55 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[2][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~56_combout = (\ula_|zx_keyboard_|keys[2][2]~55_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][2]~q ), + .datad(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N27 +dffeas \ula_|zx_keyboard_|keys[2][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N29 +dffeas \ula_|zx_keyboard_|keys[3][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N8 +cycloneive_lcell_comb \D[2]~36 ( +// Equation(s): +// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~24_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & +// (((\z80_|address_pins_|abus[11]~19_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), + .datab(\ula_|zx_keyboard_|keys[3][2]~q ), + .datac(\z80_|address_pins_|abus[10]~24_combout ), + .datad(\z80_|address_pins_|abus[11]~19_combout ), + .cin(gnd), + .combout(\D[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~36 .lut_mask = 16'hF531; +defparam \D[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h0180; +defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~68_combout )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~70_combout = (\ula_|zx_keyboard_|keys[6][2]~69_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~69_combout & ((\ula_|zx_keyboard_|keys[6][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), + .datab(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .datac(\ula_|zx_keyboard_|keys[6][2]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h7474; +defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N1 +dffeas \ula_|zx_keyboard_|keys[6][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[7][2]~61_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~62_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~63_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[7][2]~62_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'hC8C0; +defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~65_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & \ula_|zx_keyboard_|keys[7][2]~64_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector13~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF22; +defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[7][2]~65_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~65_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][2]~q ), + .datad(\ula_|zx_keyboard_|Selector13~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N13 +dffeas \ula_|zx_keyboard_|keys[7][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N0 +cycloneive_lcell_comb \D[2]~38 ( +// Equation(s): +// \D[2]~38_combout = (\z80_|address_pins_|abus[15]~22_combout & (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][2]~q & +// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\ula_|zx_keyboard_|keys[6][2]~q ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~q ), + .cin(gnd), + .combout(\D[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~38 .lut_mask = 16'hA2F3; +defparam \D[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N14 +cycloneive_lcell_comb \D[2]~39 ( +// Equation(s): +// \D[2]~39_combout = (\D[2]~35_combout & (\D[2]~37_combout & (\D[2]~36_combout & \D[2]~38_combout ))) + + .dataa(\D[2]~35_combout ), + .datab(\D[2]~37_combout ), + .datac(\D[2]~36_combout ), + .datad(\D[2]~38_combout ), + .cin(gnd), + .combout(\D[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~39 .lut_mask = 16'h8000; +defparam \D[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \D[2]~104 ( +// Equation(s): +// \D[2]~104_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\D[2]~39_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [0]), + .datad(\D[2]~39_combout ), + .cin(gnd), + .combout(\D[2]~104_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~104 .lut_mask = 16'hFFF3; +defparam \D[2]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \D[2]~43 ( +// Equation(s): +// \D[2]~43_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\D[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~43 .lut_mask = 16'hB9A8; +defparam \D[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \D[2]~44 ( +// Equation(s): +// \D[2]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~43_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout )) # (!\D[2]~43_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~43_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\D[2]~43_combout ), + .cin(gnd), + .combout(\D[2]~44_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~44 .lut_mask = 16'hBBC0; +defparam \D[2]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \D[2]~40 ( +// Equation(s): +// \D[2]~40_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\D[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~40 .lut_mask = 16'hEA62; +defparam \D[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \D[2]~41 ( +// Equation(s): +// \D[2]~41_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ (\D[2]~40_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & ((!\D[2]~40_combout )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\D[2]~40_combout ), + .cin(gnd), + .combout(\D[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~41 .lut_mask = 16'h0AE4; +defparam \D[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \D[2]~42 ( +// Equation(s): +// \D[2]~42_combout = (\D[2]~40_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~41_combout )))) # (!\D[2]~40_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~41_combout )))) + + .dataa(\D[2]~40_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\D[2]~41_combout ), + .cin(gnd), + .combout(\D[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~42 .lut_mask = 16'h99A8; +defparam \D[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \D[2]~105 ( +// Equation(s): +// \D[2]~105_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[2]~44_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~42_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[2]~44_combout )))) + + .dataa(\D[2]~44_combout ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\D[2]~42_combout ), + .cin(gnd), + .combout(\D[2]~105_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~105 .lut_mask = 16'hBA8A; +defparam \D[2]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N28 +cycloneive_lcell_comb \D[2]~45 ( +// Equation(s): +// \D[2]~45_combout = ((\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[2]~104_combout ), + .datad(\D[2]~105_combout ), + .cin(gnd), + .combout(\D[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~45 .lut_mask = 16'hF7B3; +defparam \D[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N30 +cycloneive_lcell_comb \D[2]~46 ( +// Equation(s): +// \D[2]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~45_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[2]~45_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[2]~45_combout ), + .cin(gnd), + .combout(\D[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~46 .lut_mask = 16'hAF03; +defparam \D[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N2 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[2]~46_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[2]~46_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\D[2]~46_combout ), + .datad(\z80_|bus_control_|db[2]~13_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N3 +dffeas \z80_|data_pins_|dout[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( +// Equation(s): +// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[2]~29_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( +// Equation(s): +// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|bus_control_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hBF33; +defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N13 +dffeas \z80_|ir_|opcode[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[2]~13_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N26 cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( // Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) +// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal43~0_combout ), .cout()); @@ -53587,14 +50349,14 @@ defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N14 +// Location: LCCOMB_X35_Y17_N24 cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( // Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal79~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & !\z80_|pla_decode_|Equal36~0_combout ))) +// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) .dataa(\z80_|pla_decode_|Equal43~0_combout ), - .datab(\z80_|pla_decode_|Equal79~0_combout ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datab(\z80_|pla_decode_|Equal3~2_combout ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), .datad(\z80_|pla_decode_|Equal36~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|test1~2_combout ), @@ -53604,24 +50366,24 @@ defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N22 +// Location: LCCOMB_X43_Y15_N26 cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( // Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & (((\z80_|interrupts_|test1~2_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) +// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|interrupts_|test1~2_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|interrupts_|test1~2_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|interrupts_|test1~2_combout ), .cin(gnd), .combout(\z80_|interrupts_|test1~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h00FD; +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h5545; defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y12_N27 +// Location: FF_X32_Y15_N13 dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), @@ -53640,7 +50402,7 @@ defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N16 +// Location: LCCOMB_X43_Y15_N2 cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( // Equation(s): // \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) @@ -53657,7 +50419,7 @@ defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y12_N17 +// Location: FF_X43_Y15_N3 dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), @@ -53676,7 +50438,7 @@ defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N2 +// Location: LCCOMB_X43_Y15_N20 cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( // Equation(s): // \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) @@ -53693,7 +50455,7 @@ defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0033; defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N1 +// Location: FF_X32_Y17_N13 dffeas \z80_|sequencer_|DFFE_T1_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|ena_M~combout ), @@ -53712,24 +50474,24 @@ defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N26 +// Location: LCCOMB_X32_Y17_N4 cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( // Equation(s): // \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), .datac(\z80_|execute_|setM1~52_combout ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0030; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N27 +// Location: FF_X32_Y17_N5 dffeas \z80_|sequencer_|DFFE_T2_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), @@ -53748,318 +50510,56 @@ defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N16 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|resets_|x3 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - .dataa(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datac(\z80_|resets_|x1~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .combout(\z80_|resets_|x3~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +defparam \z80_|resets_|x3 .lut_mask = 16'hF0FA; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N17 -dffeas \z80_|sequencer_|DFFE_T3_ff ( +// Location: FF_X35_Y13_N11 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .d(\z80_|resets_|x3~combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N14 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N15 -dffeas \z80_|sequencer_|DFFE_T4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), +// Location: CLKCTRL_G7 +cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), + .clkselect(2'b00), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), - .prn(vcc)); + .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X44_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( -// Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (\z80_|execute_|setM1~39_combout & !\z80_|execute_|ctl_mWrite~5_combout ) - - .dataa(\z80_|execute_|setM1~39_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h00AA; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~53 ( -// Equation(s): -// \z80_|execute_|setM1~53_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & \z80_|execute_|ctl_mRead~29_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~53_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h2AAA; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'hA800; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ctl_mRead~38_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|execute_|nextM~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|ctl_alu_op_low~37_combout ) # (\z80_|execute_|nextM~10_combout )) # (!\z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|nextM~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~37_combout ), - .datad(\z80_|execute_|nextM~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|fMRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'h8808; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (((\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|nextM~4_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|nextM~4_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~5_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~6_combout ) - - .dataa(\z80_|execute_|nextM~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|nextM~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( -// Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ixy_d~8_combout & (((!\z80_|alu_control_|flags_cond_true~q & \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|ixy_d~8_combout & -// (((!\z80_|alu_control_|flags_cond_true~q & \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout )))) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h2F22; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # ((\z80_|execute_|nextM~7_combout ) # (\z80_|execute_|nextM~8_combout ))) - - .dataa(\z80_|execute_|nextM~12_combout ), - .datab(\z80_|execute_|nextM~15_combout ), - .datac(\z80_|execute_|nextM~7_combout ), - .datad(\z80_|execute_|nextM~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~3_combout ) # ((\z80_|execute_|nextM~13_combout ) # ((!\z80_|execute_|ctl_mWrite~13_combout ) # (!\z80_|execute_|ctl_mRead~31_combout ))) - - .dataa(\z80_|execute_|nextM~3_combout ), - .datab(\z80_|execute_|nextM~13_combout ), - .datac(\z80_|execute_|ctl_mRead~31_combout ), - .datad(\z80_|execute_|ctl_mWrite~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N4 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; -defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N5 +// Location: FF_X32_Y17_N21 dffeas \z80_|sequencer_|DFFE_M1_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), @@ -54078,644 +50578,7 @@ defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N24 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N25 -dffeas \z80_|sequencer_|T6 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|T6~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|T6 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~9_combout )) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0011; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~43 ( -// Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0004; -defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~42_combout & (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|setM1~43_combout & !\z80_|pla_decode_|Equal21~1_combout ))) - - .dataa(\z80_|execute_|setM1~42_combout ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|setM1~43_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0020; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (\z80_|execute_|setM1~44_combout & (\z80_|execute_|setM1~41_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|execute_|setM1~44_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0888; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & -// (((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal21~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & !\z80_|pla_decode_|Equal1~6_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal77~1_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|pla_decode_|Equal1~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (!\z80_|pla_decode_|Equal2~2_combout & (\z80_|execute_|setM1~15_combout & (\z80_|execute_|setM1~14_combout & \z80_|interrupts_|test1~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|execute_|setM1~15_combout ), - .datac(\z80_|execute_|setM1~14_combout ), - .datad(\z80_|interrupts_|test1~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~49_combout & (\z80_|execute_|setM1~46_combout & \z80_|execute_|setM1~16_combout ))) - - .dataa(\z80_|execute_|setM1~45_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|execute_|setM1~46_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|setM1~41_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & -// (\z80_|execute_|setM1~40_combout ))) - - .dataa(\z80_|sequencer_|T6~q ), - .datab(\z80_|execute_|setM1~50_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'hC0EA; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hCDCC; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal6~1_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout ) # (\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|fMWrite~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|fMWrite~1_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~11_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|setM1~11_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|setM1~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & ((\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hDC50; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = ((\z80_|execute_|setM1~8_combout & \z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|execute_|setM1~8_combout ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF333; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( -// Equation(s): -// \z80_|execute_|setM1~13_combout = (\z80_|execute_|setM1~9_combout ) # (((\z80_|execute_|setM1~12_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) - - .dataa(\z80_|execute_|setM1~12_combout ), - .datab(\z80_|execute_|setM1~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'hECFF; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (\z80_|execute_|setM1~17_combout & (\z80_|execute_|ctl_alu_op_low~36_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|setM1~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~36_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0008; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~13_combout ) # (((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|setM1~16_combout )) # (!\z80_|execute_|setM1~18_combout )) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|setM1~16_combout ), - .datac(\z80_|execute_|setM1~13_combout ), - .datad(\z80_|execute_|setM1~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hF2FF; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = (\z80_|alu_control_|flags_cond_true~q & (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) # (!\z80_|alu_control_|flags_cond_true~q & -// ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((!\z80_|execute_|ctl_mRead~14_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'h7350; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|execute_|fMWrite~6_combout ))) - - .dataa(\z80_|execute_|fMWrite~1_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|fMWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0200; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'hFF02; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( -// Equation(s): -// \z80_|execute_|setM1~55_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~22_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~22_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'hC888; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~55_combout )) # (!\z80_|execute_|setM1~23_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~55_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|setM1~23_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~55_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h2F22; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hBAFF; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = ((\z80_|execute_|setM1~26_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datad(\z80_|execute_|setM1~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|setM1~27_combout ))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~24_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|setM1~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_mRead~38_combout & \z80_|execute_|setM1~11_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|setM1~11_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~20_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ctl_mRead~20_combout & -// (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|setM1~29_combout & \z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|setM1~30_combout )) # (!\z80_|execute_|setM1~56_combout ) - - .dataa(\z80_|execute_|setM1~29_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|setM1~56_combout ), - .datad(\z80_|execute_|setM1~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~33_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|setM1~33_combout ), - .datac(\z80_|execute_|setM1~32_combout ), - .datad(\z80_|execute_|setM1~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = ((\z80_|execute_|ctl_iorw~10_combout & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hD555; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~13_combout & (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~13_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20AA; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|execute_|setM1~20_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hECCC; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~34_combout ) # ((\z80_|execute_|setM1~54_combout ) # (\z80_|execute_|setM1~21_combout ))) - - .dataa(\z80_|execute_|setM1~28_combout ), - .datab(\z80_|execute_|setM1~34_combout ), - .datac(\z80_|execute_|setM1~54_combout ), - .datad(\z80_|execute_|setM1~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( -// Equation(s): -// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~19_combout & (!\z80_|execute_|setM1~35_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|setM1~51_combout ), - .datac(\z80_|execute_|setM1~19_combout ), - .datad(\z80_|execute_|setM1~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'h000B; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N18 +// Location: LCCOMB_X32_Y17_N10 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( // Equation(s): // \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) @@ -54732,7 +50595,7 @@ defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N19 +// Location: FF_X32_Y17_N11 dffeas \z80_|sequencer_|DFFE_M2_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), @@ -54751,195 +50614,2625 @@ defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( // Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .combout(\z80_|execute_|ctl_mWrite~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Location: LCCOMB_X41_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~39_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) +// \z80_|execute_|nextM~11_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ctl_mWrite~3_combout ) - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .combout(\z80_|execute_|nextM~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Location: LCCOMB_X40_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = (\z80_|execute_|pc_inc_hold~19_combout & ((\z80_|execute_|ctl_mRead~38_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|pc_inc_hold~19_combout & -// (((\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ixy_d~4_combout )))) +// \z80_|execute_|nextM~8_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout +// ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~19_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ixy_d~8_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .combout(\z80_|execute_|nextM~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~8 .lut_mask = 16'h44F4; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Location: LCCOMB_X39_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (((\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_bus_db_oe~7_combout )) # (!\z80_|execute_|pc_inc_hold~40_combout ))) +// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ixy_d~6_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~40_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .combout(\z80_|execute_|nextM~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~9 .lut_mask = 16'h8880; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( +// Location: LCCOMB_X40_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|execute_|pc_inc_hold~36_combout ) # ((\z80_|execute_|pc_inc_hold~35_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|pc_inc_hold~40_combout ))) +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|ixy_d~9_combout ))) - .dataa(\z80_|execute_|pc_inc_hold~36_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|pc_inc_hold~40_combout ), - .datad(\z80_|execute_|pc_inc_hold~35_combout ), + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datab(\z80_|execute_|nextM~9_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~37_combout ), + .combout(\z80_|execute_|nextM~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( +// Location: LCCOMB_X40_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~38_combout = ((\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|pc_inc_hold~34_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout ))) # (!\z80_|execute_|ctl_inc_cy~39_combout ) +// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|ctl_alu_op_low~32_combout ))) # (!\z80_|execute_|nextM~11_combout ) - .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), - .datab(\z80_|execute_|pc_inc_hold~37_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .dataa(\z80_|execute_|nextM~11_combout ), + .datab(\z80_|execute_|nextM~8_combout ), + .datac(\z80_|execute_|nextM~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~38_combout ), + .combout(\z80_|execute_|nextM~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Location: LCCOMB_X39_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (!\z80_|execute_|pc_inc_hold~38_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) +// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|fMRead~10_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .combout(\z80_|execute_|nextM~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~15 .lut_mask = 16'h80A0; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Location: LCCOMB_X40_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) +// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|nM1_int~2_combout ), + .dataa(\z80_|execute_|ixy_d~17_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'hDF5F; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ixy_d~8_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|execute_|nextM~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # (\z80_|execute_|nextM~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(\z80_|execute_|nextM~15_combout ), + .datad(\z80_|execute_|nextM~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (!\z80_|execute_|ctl_mWrite~5_combout & \z80_|execute_|setM1~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|setM1~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0F00; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~45_combout ) # (!\z80_|execute_|nextM~2_combout )) # (!\z80_|execute_|setM1~39_combout ))) + + .dataa(\z80_|execute_|setM1~39_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|setM1~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~13_combout ) # (((\z80_|execute_|nextM~5_combout ) # (!\z80_|execute_|ctl_mRead~30_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) + + .dataa(\z80_|execute_|nextM~13_combout ), + .datab(\z80_|execute_|ctl_mWrite~13_combout ), + .datac(\z80_|execute_|ctl_mRead~30_combout ), + .datad(\z80_|execute_|nextM~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N14 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|setM1~52_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N15 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N18 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N19 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N26 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|setM1~52_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N27 +dffeas \z80_|sequencer_|T6 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|T6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|T6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal21~2_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & +// (((!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal21~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'h153F; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal77~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~1_combout ), + .datab(\z80_|execute_|ctl_alu_oe~3_combout ), + .datac(\z80_|pla_decode_|Equal1~6_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~13_combout & (\z80_|interrupts_|test1~2_combout & \z80_|execute_|setM1~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~13_combout ), + .datac(\z80_|interrupts_|test1~2_combout ), + .datad(\z80_|execute_|setM1~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'hC000; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0005; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0100; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~43 ( +// Equation(s): +// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~41_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~42_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|setM1~41_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|setM1~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0400; +defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (\z80_|execute_|setM1~40_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|execute_|setM1~40_combout ), + .datad(\z80_|pla_decode_|Equal2~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h20A0; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~14_combout & (\z80_|execute_|setM1~44_combout & \z80_|execute_|setM1~49_combout ))) + + .dataa(\z80_|execute_|setM1~46_combout ), + .datab(\z80_|execute_|setM1~14_combout ), + .datac(\z80_|execute_|setM1~44_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~39_combout )) # (!\z80_|execute_|setM1~40_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & +// ((\z80_|execute_|setM1~39_combout )))) + + .dataa(\z80_|sequencer_|T6~q ), + .datab(\z80_|execute_|setM1~50_combout ), + .datac(\z80_|execute_|setM1~40_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'hCE0A; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~6 ( +// Equation(s): +// \z80_|execute_|setM1~6_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & (\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & +// \z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~6 .lut_mask = 16'hD5C0; +defparam \z80_|execute_|setM1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~7 ( +// Equation(s): +// \z80_|execute_|setM1~7_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|setM1~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~7 .lut_mask = 16'hF333; +defparam \z80_|execute_|setM1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~8 ( +// Equation(s): +// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|fMWrite~3_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~8 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~9 ( +// Equation(s): +// \z80_|execute_|setM1~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF1F0; +defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = ((\z80_|execute_|setM1~8_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~9_combout ))) # (!\z80_|execute_|nextM~2_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~16_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|setM1~8_combout ), + .datad(\z80_|execute_|setM1~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = (\z80_|execute_|setM1~7_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~10_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) + + .dataa(\z80_|execute_|setM1~7_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|setM1~10_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = ((\z80_|execute_|setM1~11_combout ) # ((!\z80_|execute_|setM1~14_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~16_combout ) + + .dataa(\z80_|execute_|setM1~16_combout ), + .datab(\z80_|execute_|setM1~14_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'hFF75; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~18_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & +// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~18_combout )))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hECA0; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|setM1~28_combout )) # (!\z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~54_combout ) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|execute_|setM1~29_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|setM1~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'hF777; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|setM1~9_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|setM1~9_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~32_combout ))) + + .dataa(\z80_|execute_|setM1~31_combout ), + .datab(\z80_|execute_|setM1~30_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|setM1~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'hAF0F; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_mRead~12_combout ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & ((!\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|alu_control_|flags_cond_true~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|setM1~25_combout ) # (\z80_|execute_|setM1~26_combout )))) + + .dataa(\z80_|execute_|setM1~25_combout ), + .datab(\z80_|execute_|setM1~26_combout ), + .datac(\z80_|execute_|setM1~24_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|execute_|fMWrite~9_combout & (!\z80_|execute_|ctl_mRead~8_combout & \z80_|execute_|fMWrite~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|fMWrite~9_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'h0400; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF1F0; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~53 ( +// Equation(s): +// \z80_|execute_|setM1~53_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~21_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|setM1~21_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~53 .lut_mask = 16'hC888; +defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~22_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # +// ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) + + .dataa(\z80_|execute_|setM1~22_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'h4F44; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|execute_|ctl_flags_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'h08CC; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~18_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) + + .dataa(\z80_|execute_|setM1~18_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'hEAAA; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = ((\z80_|execute_|setM1~19_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|ctl_mWrite~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~3_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datad(\z80_|execute_|setM1~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|setM1~23_combout ) # (\z80_|execute_|setM1~20_combout ))) + + .dataa(\z80_|execute_|setM1~33_combout ), + .datab(\z80_|execute_|setM1~27_combout ), + .datac(\z80_|execute_|setM1~23_combout ), + .datad(\z80_|execute_|setM1~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~17_combout & (!\z80_|execute_|setM1~34_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|setM1~34_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'h0301; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N24 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N25 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N24 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Equation(s): +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|decode_state_|in_halt~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0050; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( +// Equation(s): +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|decode_state_|in_halt~0_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|pla_decode_|Equal77~1_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|in_halt~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hCECC; +defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N25 +dffeas \z80_|decode_state_|in_halt ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|in_halt~1_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|in_halt~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; +defparam \z80_|decode_state_|in_halt .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_zero_oe~0_combout & (!\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0031; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), .datad(\z80_|pla_decode_|Equal41~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'h010F; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~68_combout & \z80_|execute_|ctl_inc_cy~69_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ))) +// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - .dataa(\z80_|execute_|ctl_inc_cy~68_combout ), - .datab(\z80_|execute_|ctl_inc_cy~69_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'h8F00; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # (\z80_|execute_|ctl_inc_cy~80_combout )))) +// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - .dataa(\z80_|execute_|ctl_inc_cy~70_combout ), - .datab(\z80_|execute_|ctl_inc_cy~67_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~80_combout ), + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0F1E; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N20 +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Equation(s): +// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; +defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|zx_keyboard_|keys[1][3]~93_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][3]~93_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N31 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~94_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|zx_keyboard_|keys[0][3]~96_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & +// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~97_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N1 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~98_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N4 +cycloneive_lcell_comb \D[3]~65 ( +// Equation(s): +// \D[3]~65_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][3]~q ), + .cin(gnd), + .combout(\D[3]~65_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~65 .lut_mask = 16'h8CAF; +defparam \D[3]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~99_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~99 .lut_mask = 16'h4040; +defparam \ula_|zx_keyboard_|keys[3][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~100 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~100_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[3][3]~99_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~99_combout & (\ula_|zx_keyboard_|keys[3][3]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), + .datab(\ula_|zx_keyboard_|keys[3][3]~99_combout ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~100_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~100 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][3]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N9 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~100_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'hCCDD; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~133 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~133_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][3]~102_combout & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~133_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~133 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[2][3]~133 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|keys[2][3]~133_combout & (!\ula_|zx_keyboard_|keys[2][3]~101_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~133_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][3]~133_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N3 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~103_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N28 +cycloneive_lcell_comb \D[3]~66 ( +// Equation(s): +// \D[3]~66_combout = (\z80_|address_pins_|abus[11]~19_combout & (((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[3][3]~q ), + .datac(\z80_|address_pins_|abus[10]~24_combout ), + .datad(\ula_|zx_keyboard_|keys[2][3]~q ), + .cin(gnd), + .combout(\D[3]~66_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~66 .lut_mask = 16'hB0BB; +defparam \D[3]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[5][3]~q +// )))) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N23 +dffeas \ula_|zx_keyboard_|keys[5][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|WideOr16~2_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~134 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~134_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), + .datab(\ula_|zx_keyboard_|Selector5~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~134 .lut_mask = 16'hCECC; +defparam \ula_|zx_keyboard_|keys[4][3]~134 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~106_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][3]~134_combout )))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~135 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~135_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~135 .lut_mask = 16'hCDCC; +defparam \ula_|zx_keyboard_|keys[4][3]~135 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|keys[4][3]~135_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & +// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N23 +dffeas \ula_|zx_keyboard_|keys[4][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][3]~108_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N20 +cycloneive_lcell_comb \D[3]~67 ( +// Equation(s): +// \D[3]~67_combout = (\ula_|zx_keyboard_|keys[5][3]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][3]~q & +// (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][3]~q ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[3]~67_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~67 .lut_mask = 16'hDD0D; +defparam \D[3]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~61_combout )))) + + .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hA888; +defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & ((!\ula_|zx_keyboard_|keys[0][4]~111_combout ))) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & (\ula_|zx_keyboard_|keys[7][3]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y20_N9 +dffeas \ula_|zx_keyboard_|keys[7][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~109_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~109 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[6][3]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~110_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~109_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~32_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~110 .lut_mask = 16'hF088; +defparam \ula_|zx_keyboard_|keys[6][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~137 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~137_combout = (\ula_|zx_keyboard_|extended~q ) # (((!\ula_|zx_keyboard_|keys[0][0]~15_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~110_combout )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~137 .lut_mask = 16'hBFFF; +defparam \ula_|zx_keyboard_|keys[6][3]~137 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~138 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~138_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~137_combout & ((\ula_|zx_keyboard_|keys[6][3]~q ))) # (!\ula_|zx_keyboard_|keys[6][3]~137_combout & +// (!\ula_|zx_keyboard_|Selector13~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~138 .lut_mask = 16'hF072; +defparam \ula_|zx_keyboard_|keys[6][3]~138 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N29 +dffeas \ula_|zx_keyboard_|keys[6][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # ((!\ula_|zx_keyboard_|keys[6][3]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[6][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \D[3]~68 ( +// Equation(s): +// \D[3]~68_combout = (\D[3]~67_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\D[3]~67_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|key_row~2_combout ), + .cin(gnd), + .combout(\D[3]~68_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~68 .lut_mask = 16'h8C00; +defparam \D[3]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \D[3]~69 ( +// Equation(s): +// \D[3]~69_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~65_combout & (\D[3]~66_combout & \D[3]~68_combout ))) + + .dataa(\D[3]~65_combout ), + .datab(\z80_|address_pins_|abus[0]~16_combout ), + .datac(\D[3]~66_combout ), + .datad(\D[3]~68_combout ), + .cin(gnd), + .combout(\D[3]~69_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~69 .lut_mask = 16'hECCC; +defparam \D[3]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \D[3]~73 ( +// Equation(s): +// \D[3]~73_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\D[3]~73_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~73 .lut_mask = 16'hCCE2; +defparam \D[3]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \D[3]~74 ( +// Equation(s): +// \D[3]~74_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[3]~73_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ))) # (!\D[3]~73_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~73_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datac(\D[3]~73_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .cin(gnd), + .combout(\D[3]~74_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~74 .lut_mask = 16'hF858; +defparam \D[3]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \D[3]~70 ( +// Equation(s): +// \D[3]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~23_combout )) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\D[3]~70_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~70 .lut_mask = 16'hEC64; +defparam \D[3]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \D[3]~71 ( +// Equation(s): +// \D[3]~71_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout $ (((\D[3]~70_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & !\D[3]~70_combout )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\D[3]~70_combout ), + .cin(gnd), + .combout(\D[3]~71_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~71 .lut_mask = 16'h22D8; +defparam \D[3]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \D[3]~72 ( +// Equation(s): +// \D[3]~72_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~70_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~70_combout & (!\D[3]~71_combout & +// \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )) # (!\D[3]~70_combout & (\D[3]~71_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\D[3]~70_combout ), + .datac(\D[3]~71_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\D[3]~72_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~72 .lut_mask = 16'h9C98; +defparam \D[3]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \D[3]~108 ( +// Equation(s): +// \D[3]~108_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[3]~74_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[3]~72_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[3]~74_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\D[3]~74_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\D[3]~72_combout ), + .cin(gnd), + .combout(\D[3]~108_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~108 .lut_mask = 16'hDC8C; +defparam \D[3]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \D[3]~95 ( +// Equation(s): +// \D[3]~95_combout = ((\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[3]~69_combout ), + .datab(\Equal2~1_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[3]~108_combout ), + .cin(gnd), + .combout(\D[3]~95_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~95 .lut_mask = 16'hBFB3; +defparam \D[3]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \D[3]~96 ( +// Equation(s): +// \D[3]~96_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [3] & \D[3]~95_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[3]~95_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [3]), + .datad(\D[3]~95_combout ), + .cin(gnd), + .combout(\D[3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~96 .lut_mask = 16'hF511; +defparam \D[3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\D[3]~96_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[3]~96_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[3]~96_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N7 +dffeas \z80_|data_pins_|dout[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( +// Equation(s): +// \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(\z80_|data_pins_|dout [3]), + .datac(gnd), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hDD00; +defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( +// Equation(s): +// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N1 +dffeas \z80_|ir_|opcode[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[3]~21_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_apin_mux~1_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ctl_apin_mux~1_combout ), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h8F8F; +defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N18 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .datab(\z80_|address_latch_|abusz [0]), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|abusz [0]), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N21 +// Location: FF_X31_Y16_N19 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -54958,160 +53251,228 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \D[0]~84 ( +// Location: LCCOMB_X29_Y14_N12 +cycloneive_lcell_comb \D[0]~59 ( // Equation(s): -// \D[0]~84_combout = (\Equal2~0_combout & ((\D[0]~47_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~84 .lut_mask = 16'hFB00; -defparam \D[0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \D[0]~50 ( -// Equation(s): -// \D[0]~50_combout = (\D[0]~84_combout & (((\z80_|data_pins_|dout [0])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) # (!\D[0]~84_combout & (\D[0]~42_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) - - .dataa(\D[0]~84_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\D[0]~42_combout ), - .cin(gnd), - .combout(\D[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~50 .lut_mask = 16'hF3A2; -defparam \D[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N30 -cycloneive_lcell_comb \D[1]~85 ( -// Equation(s): -// \D[1]~85_combout = (\Equal2~0_combout & ((\z80_|address_pins_|DFFE_apin_latch [0]) # ((\D[1]~28_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \D[0]~59_combout = (\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout ))) .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\D[1]~28_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\D[0]~51_combout ), + .datac(\D[0]~106_combout ), + .datad(gnd), .cin(gnd), - .combout(\D[1]~85_combout ), + .combout(\D[0]~59_combout ), .cout()); // synopsys translate_off -defparam \D[1]~85 .lut_mask = 16'hA8AA; -defparam \D[1]~85 .sum_lutc_input = "datac"; +defparam \D[0]~59 .lut_mask = 16'hD8D8; +defparam \D[0]~59 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \D[1]~51 ( +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \D[0]~60 ( // Equation(s): -// \D[1]~51_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~85_combout ) # (\D[1]~23_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[1]~85_combout ) # (\D[1]~23_combout )))) +// \D[0]~60_combout = (\Equal2~1_combout & (\D[0]~59_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [0]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\D[1]~85_combout ), - .datad(\D[1]~23_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[0]~59_combout ), .cin(gnd), - .combout(\D[1]~51_combout ), + .combout(\D[0]~60_combout ), .cout()); // synopsys translate_off -defparam \D[1]~51 .lut_mask = 16'hDDD0; -defparam \D[1]~51 .sum_lutc_input = "datac"; +defparam \D[0]~60 .lut_mask = 16'hCF45; +defparam \D[0]~60 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N22 -cycloneive_lcell_comb \D[3]~86 ( +// Location: LCCOMB_X32_Y18_N20 +cycloneive_lcell_comb \D[1]~61 ( // Equation(s): -// \D[3]~86_combout = (\Equal2~0_combout & ((\z80_|address_pins_|DFFE_apin_latch [0]) # ((\D[3]~58_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \D[1]~61_combout = (\Equal2~0_combout & (\D[1]~32_combout )) # (!\Equal2~0_combout & ((\D[1]~103_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(\Equal2~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~58_combout ), + .dataa(\Equal2~0_combout ), + .datab(gnd), + .datac(\D[1]~32_combout ), + .datad(\D[1]~103_combout ), .cin(gnd), - .combout(\D[3]~86_combout ), + .combout(\D[1]~61_combout ), .cout()); // synopsys translate_off -defparam \D[3]~86 .lut_mask = 16'hCC8C; -defparam \D[3]~86 .sum_lutc_input = "datac"; +defparam \D[1]~61 .lut_mask = 16'hF5A0; +defparam \D[1]~61 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N14 -cycloneive_lcell_comb \D[3]~59 ( +// Location: LCCOMB_X32_Y18_N22 +cycloneive_lcell_comb \D[1]~62 ( // Equation(s): -// \D[3]~59_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~86_combout ) # (\D[3]~53_combout )))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[3]~86_combout ) # (\D[3]~53_combout )))) +// \D[1]~62_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~61_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~61_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [1]), + .datad(\D[1]~61_combout ), + .cin(gnd), + .combout(\D[1]~62_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~62 .lut_mask = 16'hF531; +defparam \D[1]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \D[2]~63 ( +// Equation(s): +// \D[2]~63_combout = (\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout ))) + + .dataa(\Equal2~0_combout ), + .datab(gnd), + .datac(\D[2]~104_combout ), + .datad(\D[2]~105_combout ), + .cin(gnd), + .combout(\D[2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~63 .lut_mask = 16'hF5A0; +defparam \D[2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \D[2]~64 ( +// Equation(s): +// \D[2]~64_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~63_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[2]~63_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[2]~63_combout ), + .cin(gnd), + .combout(\D[2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~64 .lut_mask = 16'hAF23; +defparam \D[2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \D[3]~75 ( +// Equation(s): +// \D[3]~75_combout = (\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout ))) + + .dataa(\D[3]~69_combout ), + .datab(gnd), + .datac(\Equal2~0_combout ), + .datad(\D[3]~108_combout ), + .cin(gnd), + .combout(\D[3]~75_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~75 .lut_mask = 16'hAFA0; +defparam \D[3]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \D[3]~76 ( +// Equation(s): +// \D[3]~76_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~75_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[3]~75_combout ) # (!\Equal2~1_combout )))) .dataa(\z80_|data_pins_|dout [3]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[3]~86_combout ), - .datad(\D[3]~53_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[3]~75_combout ), .cin(gnd), - .combout(\D[3]~59_combout ), + .combout(\D[3]~76_combout ), .cout()); // synopsys translate_off -defparam \D[3]~59 .lut_mask = 16'hBBB0; -defparam \D[3]~59 .sum_lutc_input = "datac"; +defparam \D[3]~76 .lut_mask = 16'hAF23; +defparam \D[3]~76 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \D[4]~87 ( +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \D[4]~82 ( // Equation(s): -// \D[4]~87_combout = (\Equal2~0_combout & ((\D[4]~66_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \D[4]~82_combout = (\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout ))) - .dataa(\D[4]~66_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\Equal2~0_combout ), + .dataa(\Equal2~0_combout ), + .datab(\D[4]~81_combout ), + .datac(gnd), + .datad(\D[4]~109_combout ), .cin(gnd), - .combout(\D[4]~87_combout ), + .combout(\D[4]~82_combout ), .cout()); // synopsys translate_off -defparam \D[4]~87 .lut_mask = 16'hFB00; -defparam \D[4]~87 .sum_lutc_input = "datac"; +defparam \D[4]~82 .lut_mask = 16'hDD88; +defparam \D[4]~82 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N4 -cycloneive_lcell_comb \D[4]~67 ( +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \D[4]~83 ( // Equation(s): -// \D[4]~67_combout = (\z80_|data_pins_|dout [4] & (((\D[4]~87_combout ) # (\D[4]~61_combout )))) # (!\z80_|data_pins_|dout [4] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[4]~87_combout ) # (\D[4]~61_combout )))) +// \D[4]~83_combout = (\Equal2~1_combout & (\D[4]~82_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[4]~87_combout ), - .datad(\D[4]~61_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[4]~82_combout ), .cin(gnd), - .combout(\D[4]~67_combout ), + .combout(\D[4]~83_combout ), .cout()); // synopsys translate_off -defparam \D[4]~67 .lut_mask = 16'hBBB0; -defparam \D[4]~67 .sum_lutc_input = "datac"; +defparam \D[4]~83 .lut_mask = 16'hCF45; +defparam \D[4]~83 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N2 +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \D[6]~92 ( +// Equation(s): +// \D[6]~92_combout = (\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout )) + + .dataa(gnd), + .datab(\Equal2~0_combout ), + .datac(\D[6]~111_combout ), + .datad(\D[6]~86_combout ), + .cin(gnd), + .combout(\D[6]~92_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~92 .lut_mask = 16'hFC30; +defparam \D[6]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \D[6]~93 ( +// Equation(s): +// \D[6]~93_combout = (\Equal2~1_combout & (\D[6]~92_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [6]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [6]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[6]~92_combout ), + .cin(gnd), + .combout(\D[6]~93_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~93 .lut_mask = 16'hCF45; +defparam \D[6]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N0 cycloneive_lcell_comb \z80_|nM1_int~3 ( // Equation(s): // \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) - .dataa(\z80_|execute_|setM1~52_combout ), + .dataa(gnd), .datab(\z80_|sequencer_|DFFE_T1_ff~q ), .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), + .datad(\z80_|execute_|setM1~52_combout ), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hA8A8; +defparam \z80_|nM1_int~3 .lut_mask = 16'hFC00; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N3 +// Location: FF_X43_Y17_N1 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -55130,7 +53491,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y16_N24 +// Location: LCCOMB_X43_Y17_N30 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -55147,7 +53508,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y16_N25 +// Location: FF_X43_Y17_N31 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -55166,7 +53527,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X50_Y16_N11 +// Location: FF_X43_Y17_N25 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -55185,7 +53546,7 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N10 +// Location: LCCOMB_X43_Y17_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) @@ -55202,15 +53563,15 @@ defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N14 +// Location: LCCOMB_X43_Y17_N2 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nRD_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nMREQ_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nRD_out~0_combout ))) .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datad(\z80_|memory_ifc_|nMREQ_out~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), .cout()); @@ -55219,7 +53580,20 @@ defparam \z80_|memory_ifc_|nMREQ_out~1 .lut_mask = 16'h0001; defparam \z80_|memory_ifc_|nMREQ_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N10 +// Location: CLKCTRL_G19 +cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk )); +// synopsys translate_off +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock"; +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( // Equation(s): // \ula_|i2c_loader_|state.Idle~feeder_combout = VCC @@ -55236,7 +53610,7 @@ defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N12 +// Location: LCCOMB_X4_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -55253,7 +53627,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N13 +// Location: FF_X4_Y24_N1 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -55272,14 +53646,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X4_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) - .dataa(\ula_|i2c_loader_|divider [0]), - .datab(\ula_|i2c_loader_|divider [1]), + .dataa(\ula_|i2c_loader_|divider [1]), + .datab(\ula_|i2c_loader_|divider [0]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -55290,7 +53664,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N15 +// Location: FF_X4_Y24_N11 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -55309,25 +53683,25 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N16 +// Location: LCCOMB_X4_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) // \ula_|i2c_loader_|divider[2]~8 = CARRY((!\ula_|i2c_loader_|divider[1]~6 ) # (!\ula_|i2c_loader_|divider [2])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [2]), + .dataa(\ula_|i2c_loader_|divider [2]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[1]~6 ), .combout(\ula_|i2c_loader_|divider[2]~7_combout ), .cout(\ula_|i2c_loader_|divider[2]~8 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N17 +// Location: FF_X4_Y24_N13 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -55346,7 +53720,7 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N18 +// Location: LCCOMB_X4_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) @@ -55364,7 +53738,7 @@ defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hC30C; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N19 +// Location: FF_X4_Y24_N15 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -55383,7 +53757,7 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N20 +// Location: LCCOMB_X4_Y24_N16 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) @@ -55401,7 +53775,7 @@ defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N21 +// Location: FF_X4_Y24_N17 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -55420,24 +53794,24 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N22 +// Location: LCCOMB_X4_Y24_N18 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): -// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider [5] $ (!\ula_|i2c_loader_|divider[4]~12 ) +// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) - .dataa(\ula_|i2c_loader_|divider [5]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|i2c_loader_|divider [5]), .cin(\ula_|i2c_loader_|divider[4]~12 ), .combout(\ula_|i2c_loader_|divider[5]~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N23 +// Location: FF_X4_Y24_N19 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -55456,14 +53830,14 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N2 +// Location: LCCOMB_X4_Y24_N22 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0]) +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [1]) - .dataa(\ula_|i2c_loader_|divider [0]), - .datab(\ula_|i2c_loader_|divider [3]), - .datac(\ula_|i2c_loader_|divider [1]), + .dataa(\ula_|i2c_loader_|divider [1]), + .datab(\ula_|i2c_loader_|divider [0]), + .datac(\ula_|i2c_loader_|divider [3]), .datad(\ula_|i2c_loader_|divider [2]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), @@ -55473,24 +53847,24 @@ defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N28 +// Location: LCCOMB_X4_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [5])) # (!\ula_|i2c_loader_|divider [4]) +// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [4]), - .datac(\ula_|i2c_loader_|divider [5]), - .datad(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datab(\ula_|i2c_loader_|divider [5]), + .datac(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datad(\ula_|i2c_loader_|divider [4]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hFF3F; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hF3FF; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N11 +// Location: FF_X1_Y23_N1 dffeas \ula_|i2c_loader_|state.Idle ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), @@ -55509,7 +53883,7 @@ defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N2 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( // Equation(s): // \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) @@ -55526,7 +53900,7 @@ defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N3 +// Location: FF_X1_Y23_N5 dffeas \ula_|i2c_loader_|phase[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~0_combout ), @@ -55545,24 +53919,24 @@ defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N8 +// Location: LCCOMB_X1_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( // Equation(s): -// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [1] $ (\ula_|i2c_loader_|phase [0]))) +// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) - .dataa(\ula_|i2c_loader_|state.Idle~q ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|phase~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h0AA0; +defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N9 +// Location: FF_X1_Y23_N15 dffeas \ula_|i2c_loader_|phase[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~1_combout ), @@ -55581,558 +53955,24 @@ defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( -// Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux42~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [0] $ (!\ula_|i2c_loader_|nbit [1])) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|nbit [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hB7B7; -defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|nbyte [0])) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|nbyte [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h0202; -defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|phase [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y23_N1 -cycloneive_io_ibuf \I2C_SDAT~input ( - .i(I2C_SDAT), - .ibar(gnd), - .o(\I2C_SDAT~input_o )); -// synopsys translate_off -defparam \I2C_SDAT~input .bus_hold = "false"; -defparam \I2C_SDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|thisbyte[0]~7_combout & ((\ula_|i2c_loader_|nbyte[0]~1_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hCAC0; -defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h0C00; -defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y23_N5 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [1] & (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbyte [0])) - - .dataa(\ula_|i2c_loader_|nbyte [1]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(gnd), - .datad(\ula_|i2c_loader_|nbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0011; -defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; -defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|state.Done~0_combout ) # (\ula_|i2c_loader_|nbit[0]~2_combout )))) - - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|state.Done~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; -defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|Mux42~0_combout & \ula_|i2c_loader_|state.Idle~q ))) - - .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|Mux42~0_combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h1000; -defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N17 -dffeas \ula_|i2c_loader_|nbit[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [0] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) - - .dataa(\ula_|i2c_loader_|nbit [0]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~0_combout = (!\ula_|i2c_loader_|state.Pause~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Start~q ))) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'h0001; -defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Ack~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Done~0_combout ), - .datab(\ula_|i2c_loader_|state.Ack~0_combout ), - .datac(\ula_|i2c_loader_|Mux42~0_combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hB0FF; -defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~2_combout = (\ula_|i2c_loader_|state.Ack~1_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # -// (!\ula_|i2c_loader_|state.Ack~1_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|state.Ack~1_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~2 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Ack~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N31 -dffeas \ula_|i2c_loader_|state.Ack ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Ack~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Ack~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( -// Equation(s): -// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [1]) # (\ula_|i2c_loader_|nbyte [0]))) - - .dataa(\ula_|i2c_loader_|nbyte [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|nbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hF0A0; -defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( -// Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|state~24_combout & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1])) - - .dataa(\ula_|i2c_loader_|state~24_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; -defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( -// Equation(s): -// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|phase [1]) # (!\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|phase [0]) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|state.Done~1_combout ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h3FFF; -defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~27_combout ))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~26_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state~26_combout ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state~27_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Data~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hFC0C; -defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N21 -dffeas \ula_|i2c_loader_|state.Data ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Data~0_combout ), - .asdata(\ula_|i2c_loader_|Mux42~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Data~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Data .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N26 +// Location: LCCOMB_X3_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( // Equation(s): // \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|nbit [0]) # (!\ula_|i2c_loader_|state.Data~q ) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(gnd), .datac(\ula_|i2c_loader_|nbit [0]), .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|nbit~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h3F3F; +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h5F5F; defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N27 -dffeas \ula_|i2c_loader_|nbit[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|nbit [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|nbit [2]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF3B7; -defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N21 -dffeas \ula_|i2c_loader_|nbit[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|nbit [0]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0003; -defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|state.Pause~q & (((!\ula_|i2c_loader_|state.Done~1_combout & \ula_|i2c_loader_|state.Data~q )))) # (!\ula_|i2c_loader_|state.Pause~q & ((\ula_|i2c_loader_|scl_out~0_combout ) # -// ((!\ula_|i2c_loader_|state.Done~1_combout & \ula_|i2c_loader_|state.Data~q )))) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|scl_out~0_combout ), - .datac(\ula_|i2c_loader_|state.Done~1_combout ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h4F44; -defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Done~2_combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h8AFF; -defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|phase [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5CFC; -defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N10 +// Location: LCCOMB_X2_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) @@ -56150,332 +53990,119 @@ defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Location: LCCOMB_X1_Y24_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|phase [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Mux42~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) .dataa(\ula_|i2c_loader_|nbyte [0]), .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; -defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y23_N11 -dffeas \ula_|i2c_loader_|thisbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), - .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h5A5F; -defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N13 -dffeas \ula_|i2c_loader_|thisbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) -// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), - .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; -defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N15 -dffeas \ula_|i2c_loader_|thisbyte[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), - .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N17 -dffeas \ula_|i2c_loader_|thisbyte[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte[3]~15 $ (!\ula_|i2c_loader_|thisbyte [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), - .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hF00F; -defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N19 -dffeas \ula_|i2c_loader_|thisbyte[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Pause~0_combout ), - .datac(\ula_|i2c_loader_|Equal2~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h0CCC; -defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Pause~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~1_combout ))))) # -// (!\ula_|i2c_loader_|state.Pause~2_combout & (((\ula_|i2c_loader_|state.Pause~q )))) - - .dataa(\ula_|i2c_loader_|state.Pause~2_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Pause~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N7 -dffeas \ula_|i2c_loader_|state.Pause ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Pause~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Pause~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( -// Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # -// (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; -defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N17 -dffeas \ula_|i2c_loader_|state.Start ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state~25_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Start~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Start .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [1] $ (!\ula_|i2c_loader_|nbyte [0])))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hECCE; +defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hFF84; defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N31 +// Location: LCCOMB_X1_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N1 +cycloneive_io_ibuf \I2C_SDAT~input ( + .i(I2C_SDAT), + .ibar(gnd), + .o(\I2C_SDAT~input_o )); +// synopsys translate_off +defparam \I2C_SDAT~input .bus_hold = "false"; +defparam \I2C_SDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hEFE0; +defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; +defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~3_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbyte[0]~2_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h3000; +defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N29 dffeas \ula_|i2c_loader_|nbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbyte~4_combout ), @@ -56494,42 +54121,42 @@ defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 +// Location: LCCOMB_X2_Y24_N18 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [1] & (\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|nbyte [0])) +// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) - .dataa(\ula_|i2c_loader_|nbyte [1]), - .datab(gnd), + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|nbyte [0]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|state.Stop~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0050; +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h1010; defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N24 +// Location: LCCOMB_X1_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( // Equation(s): -// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Stop~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))))) # -// (!\ula_|i2c_loader_|Mux42~0_combout & (((\ula_|i2c_loader_|state.Stop~q )))) +// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))) # +// (!\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~q )))) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), .datac(\ula_|i2c_loader_|state.Stop~q ), .datad(\ula_|i2c_loader_|state.Stop~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Stop~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF4B0; defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N25 +// Location: FF_X1_Y24_N3 dffeas \ula_|i2c_loader_|state.Stop ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Stop~1_combout ), @@ -56548,16 +54175,763 @@ defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Location: LCCOMB_X1_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Ack~q ))) - .dataa(gnd), + .dataa(\ula_|i2c_loader_|state.Start~q ), .datab(\ula_|i2c_loader_|state.Stop~q ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; +defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|nbit [2]), + .datad(\ula_|i2c_loader_|nbit [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N1 +dffeas \ula_|i2c_loader_|nbit[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [0]))) + + .dataa(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|nbit [2]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Idle~0_combout ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|state.Done~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hAF2F; +defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), .datac(\ula_|i2c_loader_|state.Ack~q ), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N31 +dffeas \ula_|i2c_loader_|state.Ack ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Ack~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Ack~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hEFE0; +defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N15 +dffeas \ula_|i2c_loader_|thisbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), + .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N17 +dffeas \ula_|i2c_loader_|thisbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) +// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), + .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N19 +dffeas \ula_|i2c_loader_|thisbyte[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), + .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N21 +dffeas \ula_|i2c_loader_|thisbyte[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Stop~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5FCC; +defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), + .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N23 +dffeas \ula_|i2c_loader_|thisbyte[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|Equal2~0_combout ), + .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h30F0; +defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & +// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Done~1_combout )))) + + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Done~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0ACE; +defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Done~2_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hC4FF; +defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~2_combout & (\ula_|i2c_loader_|state.Pause~1_combout )) # +// (!\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) + + .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Pause~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hE2F0; +defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N23 +dffeas \ula_|i2c_loader_|state.Pause ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Pause~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Pause~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( +// Equation(s): +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; +defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N31 +dffeas \ula_|i2c_loader_|state.Start ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Start~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Start .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; +defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N11 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0005; +defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|phase [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; +defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) + + .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Done~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; +defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) + + .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0400; +defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N3 +dffeas \ula_|i2c_loader_|nbit[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF55F; +defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N13 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & !\ula_|i2c_loader_|nbit [0])) + + .dataa(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|nbit [2]), + .datac(gnd), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( +// Equation(s): +// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Done~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Done~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; +defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( +// Equation(s): +// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hE0E0; +defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( +// Equation(s): +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; +defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) + + .dataa(\ula_|i2c_loader_|state~27_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state~26_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Data~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hAFA0; +defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N29 +dffeas \ula_|i2c_loader_|state.Data ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Data~0_combout ), + .asdata(\ula_|i2c_loader_|Mux42~0_combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2c_loader_|state.Start~q ), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Data~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Data .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Stop~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|state.Stop~q ), + .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~0_combout ), .cout()); // synopsys translate_off @@ -56565,7 +54939,7 @@ defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N9 +// Location: FF_X1_Y23_N13 dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|scl_out~2_combout ), @@ -56584,38 +54958,38 @@ defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N28 +// Location: LCCOMB_X1_Y23_N16 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ ((!\ula_|i2c_loader_|state.Start~q )))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # -// ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q & \ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # +// ((\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|scl_out~_Duplicate_1_q )))) - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hD7C2; +defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hBA74; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N8 +// Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|scl_out~1_combout ))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|scl_out~1_combout )) +// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & ((\ula_|i2c_loader_|state.Start~q ))) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|state.Start~q )) .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|scl_out~1_combout ), + .datab(\ula_|i2c_loader_|scl_out~1_combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hF005; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hCC11; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56638,7 +55012,7 @@ defparam \ula_|i2c_loader_|scl_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out .power_up = "high"; // synopsys translate_on -// Location: FF_X1_Y23_N31 +// Location: FF_X1_Y23_N23 dffeas \ula_|i2c_loader_|sda_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|sda_out~4_combout ), @@ -56657,88 +55031,156 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N6 +// Location: LCCOMB_X3_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state.Start~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; +defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte [0] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [2]), .cin(gnd), .combout(\ula_|i2c_loader_|Mux35~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h20A0; +defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h2A00; defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X2_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h001A; +defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h00F0; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|shiftreg~14_combout ))) + + .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~14_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hAABA; +defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: LCCOMB_X3_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3])) +// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0030; +defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0300; defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 +// Location: LCCOMB_X1_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [0] & !\ula_|i2c_loader_|phase [1])) +// \ula_|i2c_loader_|shiftreg[0]~6_combout = (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Data~q )) - .dataa(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|phase [1]), .datab(gnd), .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h00A0; +defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h5000; defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N26 +// Location: LCCOMB_X1_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state~24_combout ) # (\ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) - .dataa(\ula_|i2c_loader_|state~24_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|Mux42~0_combout ), - .datad(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .datad(\ula_|i2c_loader_|state~24_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFFE0; +defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFCF8; defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N20 +// Location: LCCOMB_X1_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|shiftreg[0]~7_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q )) +// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|shiftreg[0]~7_combout )) - .dataa(\ula_|i2c_loader_|shiftreg[0]~7_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h2200; +defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h0C00; defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56761,54 +55203,37 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; -defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N24 +// Location: LCCOMB_X2_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [3]))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte [2]))) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2])))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [4]), + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [2]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hA010; +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hC010; defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N2 +// Location: LCCOMB_X3_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~21_combout ), + .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), + .datab(\ula_|i2c_loader_|shiftreg~4_combout ), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~22_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'hAA08; +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h88C8; defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56829,33 +55254,33 @@ defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N10 +// Location: LCCOMB_X2_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|phase [1]))))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q -// ) # (\ula_|i2c_loader_|state~24_combout )))) +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q +// & (!\ula_|i2c_loader_|state.Start~q ))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state~24_combout ), - .datad(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state~24_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hDC22; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hA6A4; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N24 +// Location: LCCOMB_X2_Y24_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|shiftreg[6]~10_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ))) +// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|shiftreg[6]~10_combout ))) - .dataa(\ula_|i2c_loader_|shiftreg[6]~10_combout ), + .dataa(\ula_|i2c_loader_|phase [0]), .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .cout()); @@ -56883,41 +55308,41 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N20 +// Location: LCCOMB_X2_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) +// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [1]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [3])))) - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(\ula_|i2c_loader_|thisbyte [4]), + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h4070; +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h10B0; defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N22 +// Location: LCCOMB_X3_Y23_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0])) # (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|shiftreg~18_combout )))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .dataa(\ula_|i2c_loader_|thisbyte [0]), .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~18_combout ), + .datac(\ula_|i2c_loader_|shiftreg~18_combout ), + .datad(\ula_|i2c_loader_|shiftreg~4_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h7F5D; +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h74FF; defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N16 +// Location: LCCOMB_X3_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) @@ -56934,7 +55359,7 @@ defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hAF00; defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N17 +// Location: FF_X3_Y23_N3 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~20_combout ), @@ -56953,58 +55378,41 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|thisbyte [2]), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0F00; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N0 +// Location: LCCOMB_X2_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(\ula_|i2c_loader_|thisbyte [4]), - .datac(\ula_|i2c_loader_|thisbyte [2]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h04F4; +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h10BA; defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N2 +// Location: LCCOMB_X3_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|shiftreg~14_combout & ((\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [3] & ((!\ula_|i2c_loader_|shiftreg~14_combout )))) - .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), - .datab(\ula_|i2c_loader_|shiftreg~16_combout ), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|shiftreg~16_combout ), + .datad(\ula_|i2c_loader_|shiftreg~14_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hC5C0; +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hA0E4; defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 +// Location: LCCOMB_X3_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg~17_combout )))) @@ -57021,7 +55429,7 @@ defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hC5C0; defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X3_Y23_N7 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~26_combout ), @@ -57040,58 +55448,24 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [4])) # (!\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4]))))) - - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h0310; -defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|shiftreg~14_combout & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), - .datab(\ula_|i2c_loader_|shiftreg~13_combout ), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hCCDC; -defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N4 +// Location: LCCOMB_X2_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|shiftreg~15_combout )))) +// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|shiftreg [3]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~15_combout ), + .dataa(\ula_|i2c_loader_|shiftreg~15_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|shiftreg [3]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hCFCA; +defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE32; defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N5 +// Location: FF_X2_Y23_N1 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~25_combout ), @@ -57110,7 +55484,7 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N8 +// Location: LCCOMB_X2_Y24_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) @@ -57127,7 +55501,7 @@ defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hEE22; defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N9 +// Location: FF_X2_Y24_N5 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~12_combout ), @@ -57146,24 +55520,24 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 +// Location: LCCOMB_X3_Y23_N18 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) - .dataa(\ula_|i2c_loader_|shiftreg [5]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg [5]), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|Mux35~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hAFA0; +defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hCFC0; defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N11 +// Location: FF_X3_Y23_N19 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~9_combout ), @@ -57182,7 +55556,7 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N28 +// Location: LCCOMB_X3_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( // Equation(s): // \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) @@ -57199,7 +55573,7 @@ defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N29 +// Location: FF_X3_Y23_N5 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), @@ -57218,21 +55592,21 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N26 +// Location: LCCOMB_X2_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|shiftreg [7]))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|state.Data~q & // (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|shiftreg [7]), - .datab(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|shiftreg [7]), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hB8F0; +defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hF870; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57241,67 +55615,67 @@ cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): // \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|sda_out~0_combout ), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|sda_out~0_combout ), .datad(\I2C_SDAT~input_o ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hA0A8; +defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hC0E0; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N4 +// Location: LCCOMB_X1_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h5054; +defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N10 +// Location: LCCOMB_X1_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|sda_out~1_combout )))) # (!\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|phase [0] -// & ((!\ula_|i2c_loader_|sda_out~1_combout ))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )))) +// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase +// [0] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|sda_out~1_combout )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'h8EBA; +defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2AE; defparam \ula_|i2c_loader_|sda_out~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N30 +// Location: LCCOMB_X1_Y23_N22 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~4 ( // Equation(s): // \ula_|i2c_loader_|sda_out~4_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|sda_out~2_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & ((\ula_|i2c_loader_|sda_out~3_combout )))) - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|scl_out~0_combout ), .datac(\ula_|i2c_loader_|sda_out~2_combout ), .datad(\ula_|i2c_loader_|sda_out~3_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1D0C; +defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1B0A; defparam \ula_|i2c_loader_|sda_out~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57324,6 +55698,42 @@ defparam \ula_|i2c_loader_|sda_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out .power_up = "high"; // synopsys translate_on +// Location: LCCOMB_X27_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|mclk_r~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N17 +dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|mclk_r~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + // Location: DDIOOUTCELL_X20_Y34_N25 dffeas \ula_|i2s_intf_|mclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -57343,6 +55753,612 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X29_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) + + .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add0~1_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) +// \ula_|i2s_intf_|Add0~3 = CARRY((!\ula_|i2s_intf_|lrdivider [1] & !\ula_|i2s_intf_|Add0~1_cout )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~1_cout ), + .combout(\ula_|i2s_intf_|Add0~2_combout ), + .cout(\ula_|i2s_intf_|Add0~3 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y23_N29 +dffeas \ula_|i2s_intf_|lrdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) +// \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) + + .dataa(\ula_|i2s_intf_|lrdivider [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~3 ), + .combout(\ula_|i2s_intf_|Add0~4_combout ), + .cout(\ula_|i2s_intf_|Add0~5 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~4_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y23_N7 +dffeas \ula_|i2s_intf_|lrdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) +// \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~5 ), + .combout(\ula_|i2s_intf_|Add0~6_combout ), + .cout(\ula_|i2s_intf_|Add0~7 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N7 +dffeas \ula_|i2s_intf_|lrdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) +// \ula_|i2s_intf_|Add0~9 = CARRY((\ula_|i2s_intf_|lrdivider [4]) # (!\ula_|i2s_intf_|Add0~7 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~7 ), + .combout(\ula_|i2s_intf_|Add0~8_combout ), + .cout(\ula_|i2s_intf_|Add0~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y23_N5 +dffeas \ula_|i2s_intf_|lrdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) +// \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~9 ), + .combout(\ula_|i2s_intf_|Add0~10_combout ), + .cout(\ula_|i2s_intf_|Add0~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~10_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[5]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y23_N3 +dffeas \ula_|i2s_intf_|lrdivider[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) + + .dataa(\ula_|i2s_intf_|lrdivider [2]), + .datab(\ula_|i2s_intf_|lrdivider [4]), + .datac(\ula_|i2s_intf_|lrdivider [3]), + .datad(\ula_|i2s_intf_|lrdivider [5]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) +// \ula_|i2s_intf_|Add0~13 = CARRY((!\ula_|i2s_intf_|Add0~11 ) # (!\ula_|i2s_intf_|lrdivider [6])) + + .dataa(\ula_|i2s_intf_|lrdivider [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~11 ), + .combout(\ula_|i2s_intf_|Add0~12_combout ), + .cout(\ula_|i2s_intf_|Add0~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~12_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N27 +dffeas \ula_|i2s_intf_|lrdivider[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) +// \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) + + .dataa(\ula_|i2s_intf_|lrdivider [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~13 ), + .combout(\ula_|i2s_intf_|Add0~14_combout ), + .cout(\ula_|i2s_intf_|Add0~15 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y23_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~14_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y23_N5 +dffeas \ula_|i2s_intf_|lrdivider[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) +// \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) + + .dataa(\ula_|i2s_intf_|lrdivider [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~15 ), + .combout(\ula_|i2s_intf_|Add0~16_combout ), + .cout(\ula_|i2s_intf_|Add0~17 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h5AAF; +defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Add0~16_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0C0C; +defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N17 +dffeas \ula_|i2s_intf_|lrdivider[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|lrdivider [9]), + .cin(\ula_|i2s_intf_|Add0~17 ), + .combout(\ula_|i2s_intf_|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; +defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~18_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N25 +dffeas \ula_|i2s_intf_|lrdivider[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal0~0_combout = (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [6] & \ula_|i2s_intf_|lrdivider [7]))) + + .dataa(\ula_|i2s_intf_|lrdivider [8]), + .datab(\ula_|i2s_intf_|lrdivider [9]), + .datac(\ula_|i2s_intf_|lrdivider [6]), + .datad(\ula_|i2s_intf_|lrdivider [7]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h4000; +defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( +// Equation(s): +// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) + + .dataa(\ula_|i2s_intf_|Equal0~1_combout ), + .datab(\ula_|i2s_intf_|lrdivider [1]), + .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( +// Equation(s): +// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N25 +dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; +defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X16_Y34_N18 dffeas \ula_|i2s_intf_|lrclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -57381,6 +56397,596 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X31_Y22_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] +// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .cout(\ula_|i2s_intf_|bitcount[0]~6 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; +defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N11 +dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bclk_r~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF0FC; +defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N1 +dffeas \ula_|i2s_intf_|bitcount[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) +// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[0]~6 ), + .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .cout(\ula_|i2s_intf_|bitcount[1]~8 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N3 +dffeas \ula_|i2s_intf_|bitcount[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) +// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[1]~8 ), + .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .cout(\ula_|i2s_intf_|bitcount[2]~10 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N5 +dffeas \ula_|i2s_intf_|bitcount[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) +// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) + + .dataa(\ula_|i2s_intf_|bitcount [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[2]~10 ), + .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .cout(\ula_|i2s_intf_|bitcount[3]~12 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; +defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N7 +dffeas \ula_|i2s_intf_|bitcount[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) + + .dataa(\ula_|i2s_intf_|bitcount [3]), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(\ula_|i2s_intf_|bitcount [2]), + .datad(\ula_|i2s_intf_|bitcount [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [4]), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2s_intf_|bitcount[3]~12 ), + .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; +defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N9 +dffeas \ula_|i2s_intf_|bitcount[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add2~7_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) +// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~7_cout ), + .combout(\ula_|i2s_intf_|Add2~8_combout ), + .cout(\ula_|i2s_intf_|Add2~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; +defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|Add2~8_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1300; +defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N13 +dffeas \ula_|i2s_intf_|bdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) +// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) + + .dataa(\ula_|i2s_intf_|bdivider [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~9 ), + .combout(\ula_|i2s_intf_|Add2~10_combout ), + .cout(\ula_|i2s_intf_|Add2~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Add2~10_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0203; +defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N17 +dffeas \ula_|i2s_intf_|bdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) +// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~11 ), + .combout(\ula_|i2s_intf_|Add2~12_combout ), + .cout(\ula_|i2s_intf_|Add2~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~19_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~12_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|Add2~12_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h1300; +defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N3 +dffeas \ula_|i2s_intf_|bdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(\ula_|i2s_intf_|Add2~13 ), + .combout(\ula_|i2s_intf_|Add2~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; +defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Add2~14_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; +defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N19 +dffeas \ula_|i2s_intf_|bdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & \ula_|i2s_intf_|bdivider [4]))) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(\ula_|i2s_intf_|bdivider [2]), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h1000; +defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~1 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[4]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8A00; +defparam \ula_|i2s_intf_|shiftreg[4]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N13 +dffeas \ula_|i2s_intf_|bdivider[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hF000; +defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h30CF; +defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|bclk_r~0_combout ), + .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00D8; +defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X14_Y34_N18 dffeas \ula_|i2s_intf_|bclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -57400,16 +57006,781 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y13_N29 -dffeas \ula_|pcm_outl[14] ( +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( +// Equation(s): +// \ula_|pcm_outl[13]~feeder_combout = \D[3]~96_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[3]~96_combout ), + .cin(gnd), + .combout(\ula_|pcm_outl[13]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; +defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N2 +cycloneive_lcell_comb \ula_|always0~2 ( +// Equation(s): +// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|always0~2 .lut_mask = 16'h2020; +defparam \ula_|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \ula_|always0~3 ( +// Equation(s): +// \ula_|always0~3_combout = (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|always0~2_combout ), + .cin(gnd), + .combout(\ula_|always0~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|always0~3 .lut_mask = 16'h4000; +defparam \ula_|always0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N25 +dffeas \ula_|pcm_outl[13] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[4]~79_combout ), + .d(\ula_|pcm_outl[13]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|always0~1_combout ), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|pcm_outl [13]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h008A; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y34_N22 +cycloneive_io_ibuf \AUD_ADCDAT~input ( + .i(AUD_ADCDAT), + .ibar(gnd), + .o(\AUD_ADCDAT~input_o )); +// synopsys translate_off +defparam \AUD_ADCDAT~input .bus_hold = "false"; +defparam \AUD_ADCDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # +// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) + + .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [0]), + .datad(\AUD_ADCDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N21 +dffeas \ula_|i2s_intf_|shiftreg[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~18_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~2 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFCF0; +defparam \ula_|i2s_intf_|shiftreg[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N27 +dffeas \ula_|i2s_intf_|shiftreg[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [1] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [1]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N25 +dffeas \ula_|i2s_intf_|shiftreg[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N19 +dffeas \ula_|i2s_intf_|shiftreg[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~15_combout = (\ula_|i2s_intf_|shiftreg [3] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [3]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N1 +dffeas \ula_|i2s_intf_|shiftreg[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~15_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [4]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N11 +dffeas \ula_|i2s_intf_|shiftreg[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~14_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~13_combout = (\ula_|i2s_intf_|shiftreg [5] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(\ula_|i2s_intf_|shiftreg [5]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N17 +dffeas \ula_|i2s_intf_|shiftreg[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~13_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [6]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N31 +dffeas \ula_|i2s_intf_|shiftreg[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [7]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N29 +dffeas \ula_|i2s_intf_|shiftreg[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~11_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~10_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [8]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N23 +dffeas \ula_|i2s_intf_|shiftreg[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~10_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [9]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N13 +dffeas \ula_|i2s_intf_|shiftreg[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~9_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(\ula_|i2s_intf_|shiftreg [10]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N3 +dffeas \ula_|i2s_intf_|shiftreg[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~8_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [11]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N9 +dffeas \ula_|i2s_intf_|shiftreg[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~7_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( +// Equation(s): +// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # +// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) + + .dataa(\ula_|i2s_intf_|shiftreg [14]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N31 +dffeas \ula_|i2s_intf_|PCM_INR[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|PCM_INR [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( +// Equation(s): +// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # +// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) + + .dataa(\ula_|i2s_intf_|shiftreg [14]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|PCM_INL [14]), + .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N29 +dffeas \ula_|i2s_intf_|PCM_INL[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|PCM_INL [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N6 +cycloneive_lcell_comb \ula_|pcm_outr~0 ( +// Equation(s): +// \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datad(\ula_|i2s_intf_|PCM_INL [14]), + .cin(gnd), + .combout(\ula_|pcm_outr~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; +defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N7 +dffeas \ula_|pcm_outl[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|pcm_outr~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|pcm_outl [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [12]), + .datad(\ula_|pcm_outl [12]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N15 +dffeas \ula_|i2s_intf_|shiftreg[13] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [13]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) + + .dataa(gnd), + .datab(\ula_|pcm_outl [13]), + .datac(\ula_|i2s_intf_|shiftreg [13]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCCF0; +defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N5 +dffeas \ula_|i2s_intf_|shiftreg[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N31 +dffeas \ula_|pcm_outl[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\D[4]~98_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|pcm_outl [14]), @@ -57419,24 +57790,24 @@ defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y13_N22 +// Location: LCCOMB_X28_Y22_N4 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|pcm_outl [14]), + .datab(gnd), + .datac(\ula_|pcm_outl [14]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hEE22; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF0AA; defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y13_N23 +// Location: FF_X28_Y22_N5 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~4_combout ), @@ -57445,7 +57816,7 @@ dffeas \ula_|i2s_intf_|shiftreg[15] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [15]), @@ -57455,24 +57826,24 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y13_N24 +// Location: LCCOMB_X28_Y22_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) +// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|shiftreg [15] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), .datac(\ula_|i2s_intf_|shiftreg [15]), - .datad(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h3030; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h00F0; defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y13_N25 +// Location: FF_X28_Y22_N1 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~3_combout ), @@ -57481,7 +57852,7 @@ dffeas \ula_|i2s_intf_|shiftreg[16] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [16]), @@ -57491,20 +57862,20 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y13_N30 +// Location: LCCOMB_X28_Y22_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [16]) +// \ula_|i2s_intf_|shiftreg~0_combout = (\ula_|i2s_intf_|shiftreg [16] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [16]), - .datad(gnd), + .datab(\ula_|i2s_intf_|shiftreg [16]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h3030; +defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h00CC; defparam \ula_|i2s_intf_|shiftreg~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57517,7 +57888,7 @@ dffeas \ula_|i2s_intf_|shiftreg[17] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [17]), @@ -57527,33 +57898,136 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \ula_|border[1]~feeder ( +// Location: LCCOMB_X38_Y33_N8 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( // Equation(s): -// \ula_|border[1]~feeder_combout = \D[1]~31_combout +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [6]))) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[1]~31_combout ), + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [6]), .cin(gnd), - .combout(\ula_|border[1]~feeder_combout ), + .combout(\ula_|video_|LessThan2~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N13 +// Location: LCCOMB_X38_Y33_N4 +cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( +// Equation(s): +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(\ula_|video_|vga_vc [3]), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0111; +defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N30 +cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( +// Equation(s): +// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|vga_vc [4]), + .datac(\ula_|video_|LessThan2~0_combout ), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7050; +defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N16 +cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( +// Equation(s): +// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|LessThan6~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|LessThan6~0_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h5D55; +defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N22 +cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( +// Equation(s): +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [5])) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [6]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0011; +defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N24 +cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( +// Equation(s): +// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((\ula_|video_|LessThan0~0_combout & !\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # +// ((!\ula_|video_|LessThan0~0_combout & \ula_|video_|vga_hc [7])))) + + .dataa(\ula_|video_|LessThan0~0_combout ), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [7]), + .datad(\ula_|video_|vga_hc [9]), + .cin(gnd), + .combout(\ula_|video_|disp_enable~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h3BDC; +defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N2 +cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( +// Equation(s): +// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) + + .dataa(\ula_|video_|LessThan2~1_combout ), + .datab(\ula_|video_|LessThan3~0_combout ), + .datac(gnd), + .datad(\ula_|video_|disp_enable~0_combout ), + .cin(gnd), + .combout(\ula_|video_|disp_enable~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; +defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N11 dffeas \ula_|border[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[1]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[1]~34_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), + .sload(vcc), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|border [1]), @@ -57563,7 +58037,76 @@ defparam \ula_|border[1] .is_wysiwyg = "true"; defparam \ula_|border[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y29_N4 +// Location: LCCOMB_X37_Y33_N8 +cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( +// Equation(s): +// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; +defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N28 +cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( +// Equation(s): +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [5]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; +defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y33_N10 +cycloneive_lcell_comb \ula_|video_|screen_en~0 ( +// Equation(s): +// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|LessThan4~0_combout ), + .datad(\ula_|video_|vga_hc [8]), + .cin(gnd), + .combout(\ula_|video_|screen_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1121; +defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y33_N22 +cycloneive_lcell_comb \ula_|video_|screen_en~1 ( +// Equation(s): +// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # +// (!\ula_|video_|LessThan6~1_combout ))))) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|LessThan6~1_combout ), + .datad(\ula_|video_|screen_en~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; +defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N28 cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -57580,14 +58123,14 @@ defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y30_N10 +// Location: LCCOMB_X34_Y31_N10 cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( // Equation(s): -// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) +// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), .datad(\ula_|video_|vga_hc [0]), .cin(gnd), .combout(\ula_|video_|Decoder0~1_combout ), @@ -57597,7 +58140,7 @@ defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y29_N5 +// Location: FF_X32_Y33_N29 dffeas \ula_|video_|attr_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), @@ -57616,32 +58159,15 @@ defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N4 -cycloneive_lcell_comb \ula_|video_|attr[1]~feeder ( -// Equation(s): -// \ula_|video_|attr[1]~feeder_combout = \ula_|video_|attr_prefetch [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|attr_prefetch [1]), - .cin(gnd), - .combout(\ula_|video_|attr[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y30_N0 +// Location: LCCOMB_X34_Y31_N12 cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( // Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & \ula_|video_|vga_hc [3]))) +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & \ula_|video_|vga_hc [0]))) - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [3]), + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), .cin(gnd), .combout(\ula_|video_|Decoder0~0_combout ), .cout()); @@ -57650,15 +58176,15 @@ defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y31_N5 +// Location: FF_X37_Y33_N27 dffeas \ula_|video_|attr[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr[1]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [1]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -57669,7 +58195,7 @@ defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N0 +// Location: LCCOMB_X32_Y33_N10 cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 @@ -57686,7 +58212,7 @@ defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y30_N1 +// Location: FF_X32_Y33_N11 dffeas \ula_|video_|attr_prefetch[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), @@ -57705,7 +58231,7 @@ defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N15 +// Location: FF_X37_Y33_N13 dffeas \ula_|video_|attr[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -57724,278 +58250,7 @@ defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; defparam \ula_|video_|attr[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N0 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y30_N0 -cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( -// Equation(s): -// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0020; -defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N1 -dffeas \ula_|video_|bits_prefetch[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N7 -dffeas \ula_|video_|bits[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N2 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N3 -dffeas \ula_|video_|bits_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N13 -dffeas \ula_|video_|bits[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y23_N16 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y23_N17 -dffeas \ula_|video_|bits_prefetch[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N25 -dffeas \ula_|video_|bits[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y25_N28 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y25_N29 -dffeas \ula_|video_|bits_prefetch[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N19 -dffeas \ula_|video_|bits[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y31_N18 -cycloneive_lcell_comb \ula_|video_|Mux0~0 ( -// Equation(s): -// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [5]), - .datac(\ula_|video_|bits [7]), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE50; -defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y31_N12 -cycloneive_lcell_comb \ula_|video_|Mux0~1 ( -// Equation(s): -// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [6]), - .datac(\ula_|video_|bits [4]), - .datad(\ula_|video_|Mux0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; -defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y25_N26 +// Location: LCCOMB_X32_Y33_N24 cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58012,7 +58267,7 @@ defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y25_N27 +// Location: FF_X32_Y33_N25 dffeas \ula_|video_|attr_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), @@ -58031,7 +58286,7 @@ defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N27 +// Location: FF_X36_Y33_N5 dffeas \ula_|video_|attr[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58050,24 +58305,24 @@ defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N28 +// Location: LCCOMB_X34_Y33_N22 cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( // Equation(s): -// \ula_|video_|frame[0]~12_combout = \ula_|video_|frame [0] $ (\ula_|video_|Equal3~1_combout ) +// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) - .dataa(gnd), + .dataa(\ula_|video_|Equal3~1_combout ), .datab(gnd), .datac(\ula_|video_|frame [0]), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|frame[0]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h0FF0; +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h5A5A; defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N29 +// Location: FF_X34_Y33_N23 dffeas \ula_|video_|frame[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[0]~12_combout ), @@ -58086,14 +58341,14 @@ defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; defparam \ula_|video_|frame[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N4 +// Location: LCCOMB_X35_Y33_N24 cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( // Equation(s): -// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [1] & (\ula_|video_|frame [0] $ (VCC))) # (!\ula_|video_|frame [1] & (\ula_|video_|frame [0] & VCC)) -// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [1] & \ula_|video_|frame [0])) +// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) +// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [0] & \ula_|video_|frame [1])) - .dataa(\ula_|video_|frame [1]), - .datab(\ula_|video_|frame [0]), + .dataa(\ula_|video_|frame [0]), + .datab(\ula_|video_|frame [1]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -58104,15 +58359,15 @@ defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y30_N13 +// Location: FF_X35_Y33_N25 dffeas \ula_|video_|frame[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[1]~4_combout ), + .d(\ula_|video_|frame[1]~4_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58123,33 +58378,33 @@ defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; defparam \ula_|video_|frame[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N6 +// Location: LCCOMB_X35_Y33_N26 cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( // Equation(s): // \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) // \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - .dataa(gnd), - .datab(\ula_|video_|frame [2]), + .dataa(\ula_|video_|frame [2]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[1]~5 ), .combout(\ula_|video_|frame[2]~6_combout ), .cout(\ula_|video_|frame[2]~7 )); // synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h5A5F; defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N21 +// Location: FF_X35_Y33_N27 dffeas \ula_|video_|frame[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[2]~6_combout ), + .d(\ula_|video_|frame[2]~6_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58160,25 +58415,25 @@ defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; defparam \ula_|video_|frame[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N8 +// Location: LCCOMB_X35_Y33_N28 cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( // Equation(s): // \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) // \ula_|video_|frame[3]~9 = CARRY((\ula_|video_|frame [3] & !\ula_|video_|frame[2]~7 )) - .dataa(\ula_|video_|frame [3]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|frame [3]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[2]~7 ), .combout(\ula_|video_|frame[3]~8_combout ), .cout(\ula_|video_|frame[3]~9 )); // synopsys translate_off -defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X36_Y31_N9 +// Location: FF_X35_Y33_N29 dffeas \ula_|video_|frame[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[3]~8_combout ), @@ -58197,32 +58452,32 @@ defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; defparam \ula_|video_|frame[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N10 +// Location: LCCOMB_X35_Y33_N30 cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( // Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame [4] $ (\ula_|video_|frame[3]~9 ) - .dataa(gnd), + .dataa(\ula_|video_|frame [4]), .datab(gnd), .datac(gnd), - .datad(\ula_|video_|frame [4]), + .datad(gnd), .cin(\ula_|video_|frame[3]~9 ), .combout(\ula_|video_|frame[4]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h5A5A; defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X36_Y31_N17 +// Location: FF_X35_Y33_N31 dffeas \ula_|video_|frame[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[4]~10_combout ), + .d(\ula_|video_|frame[4]~10_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58233,7 +58488,7 @@ defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; defparam \ula_|video_|frame[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N26 +// Location: LCCOMB_X36_Y33_N4 cycloneive_lcell_comb \ula_|video_|inverted ( // Equation(s): // \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) @@ -58250,7 +58505,312 @@ defparam \ula_|video_|inverted .lut_mask = 16'hF000; defparam \ula_|video_|inverted .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y21_N0 +// Location: LCCOMB_X32_Y33_N12 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( +// Equation(s): +// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0008; +defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N13 +dffeas \ula_|video_|bits_prefetch[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N6 +cycloneive_lcell_comb \ula_|video_|bits[6]~feeder ( +// Equation(s): +// \ula_|video_|bits[6]~feeder_combout = \ula_|video_|bits_prefetch [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [6]), + .cin(gnd), + .combout(\ula_|video_|bits[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N7 +dffeas \ula_|video_|bits[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N22 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N23 +dffeas \ula_|video_|bits_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y33_N23 +dffeas \ula_|video_|bits[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N18 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N19 +dffeas \ula_|video_|bits_prefetch[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N18 +cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( +// Equation(s): +// \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [5]), + .cin(gnd), + .combout(\ula_|video_|bits[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N19 +dffeas \ula_|video_|bits[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N0 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N1 +dffeas \ula_|video_|bits_prefetch[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y33_N1 +dffeas \ula_|video_|bits[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N0 +cycloneive_lcell_comb \ula_|video_|Mux0~0 ( +// Equation(s): +// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) + + .dataa(\ula_|video_|bits [5]), + .datab(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|bits [7]), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N22 +cycloneive_lcell_comb \ula_|video_|Mux0~1 ( +// Equation(s): +// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) + + .dataa(\ula_|video_|bits [6]), + .datab(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|bits [4]), + .datad(\ula_|video_|Mux0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N16 cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58267,7 +58827,7 @@ defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y21_N1 +// Location: FF_X32_Y33_N17 dffeas \ula_|video_|bits_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), @@ -58286,15 +58846,32 @@ defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N5 +// Location: LCCOMB_X36_Y33_N12 +cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( +// Equation(s): +// \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [2]), + .cin(gnd), + .combout(\ula_|video_|bits[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N13 dffeas \ula_|video_|bits[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [2]), + .d(\ula_|video_|bits[2]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58305,7 +58882,7 @@ defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y27_N4 +// Location: LCCOMB_X32_Y33_N14 cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -58322,7 +58899,7 @@ defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y27_N5 +// Location: FF_X32_Y33_N15 dffeas \ula_|video_|bits_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), @@ -58341,7 +58918,7 @@ defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N21 +// Location: FF_X36_Y33_N3 dffeas \ula_|video_|bits[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58360,7 +58937,7 @@ defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y29_N6 +// Location: LCCOMB_X32_Y33_N6 cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -58377,7 +58954,7 @@ defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y29_N7 +// Location: FF_X32_Y33_N7 dffeas \ula_|video_|bits_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), @@ -58396,7 +58973,7 @@ defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N24 +// Location: LCCOMB_X36_Y33_N26 cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( // Equation(s): // \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] @@ -58413,7 +58990,7 @@ defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y31_N25 +// Location: FF_X36_Y33_N27 dffeas \ula_|video_|bits[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[1]~feeder_combout ), @@ -58432,24 +59009,24 @@ defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N18 +// Location: LCCOMB_X32_Y33_N4 cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), - .datad(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), .cin(gnd), .combout(\ula_|video_|bits_prefetch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hF0F0; +defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y31_N19 +// Location: FF_X32_Y33_N5 dffeas \ula_|video_|bits_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), @@ -58468,7 +59045,7 @@ defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N3 +// Location: FF_X36_Y33_N25 dffeas \ula_|video_|bits[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58487,58 +59064,58 @@ defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N2 +// Location: LCCOMB_X36_Y33_N24 cycloneive_lcell_comb \ula_|video_|Mux0~2 ( // Equation(s): // \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [1]), + .dataa(\ula_|video_|bits [1]), + .datab(\ula_|video_|vga_hc [1]), .datac(\ula_|video_|bits [3]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE30; defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N20 +// Location: LCCOMB_X36_Y33_N2 cycloneive_lcell_comb \ula_|video_|Mux0~3 ( // Equation(s): // \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [2]), + .dataa(\ula_|video_|bits [2]), + .datab(\ula_|video_|vga_hc [1]), .datac(\ula_|video_|bits [0]), .datad(\ula_|video_|Mux0~2_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF388; defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N28 +// Location: LCCOMB_X36_Y33_N10 cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( // Equation(s): // \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - .dataa(\ula_|video_|Mux0~1_combout ), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|inverted~combout ), + .dataa(\ula_|video_|vga_hc [3]), + .datab(\ula_|video_|inverted~combout ), + .datac(\ula_|video_|Mux0~1_combout ), .datad(\ula_|video_|Mux0~3_combout ), .cin(gnd), .combout(\ula_|video_|cindex[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h1ED2; +defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h369C; defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N14 +// Location: LCCOMB_X37_Y33_N12 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): // \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) @@ -58555,213 +59132,24 @@ defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N4 -cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( -// Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|vga_vc [3]), - .cin(gnd), - .combout(\ula_|video_|LessThan6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0013; -defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N24 -cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( -// Equation(s): -// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan6~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; -defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N30 -cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( -// Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [6])) # (!\ula_|video_|vga_hc [7]) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|LessThan4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; -defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N22 -cycloneive_lcell_comb \ula_|video_|screen_en~0 ( -// Equation(s): -// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|vga_hc [9]), - .datad(\ula_|video_|LessThan4~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1203; -defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N26 -cycloneive_lcell_comb \ula_|video_|screen_en~1 ( -// Equation(s): -// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # -// (!\ula_|video_|LessThan6~1_combout ))))) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(\ula_|video_|LessThan6~1_combout ), - .datac(\ula_|video_|screen_en~0_combout ), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|screen_en~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~1 .lut_mask = 16'hD0B0; -defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N12 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( -// Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N26 -cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( -// Equation(s): -// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|LessThan6~0_combout ), - .datad(\ula_|video_|LessThan2~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7500; -defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N14 -cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( -// Equation(s): -// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|Equal2~0_combout & (\ula_|video_|LessThan6~0_combout & !\ula_|video_|vga_vc [5]))) # (!\ula_|video_|vga_vc [9]) - - .dataa(\ula_|video_|Equal2~0_combout ), - .datab(\ula_|video_|LessThan6~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|vga_vc [9]), - .cin(gnd), - .combout(\ula_|video_|LessThan3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h08FF; -defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N2 -cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( -// Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [6]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|vga_hc [5]), - .cin(gnd), - .combout(\ula_|video_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0003; -defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N28 -cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( -// Equation(s): -// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & -// !\ula_|video_|LessThan0~0_combout )))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [9]), - .datad(\ula_|video_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|disp_enable~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; -defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N16 -cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( -// Equation(s): -// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) - - .dataa(\ula_|video_|LessThan2~1_combout ), - .datab(\ula_|video_|LessThan3~0_combout ), - .datac(gnd), - .datad(\ula_|video_|disp_enable~0_combout ), - .cin(gnd), - .combout(\ula_|video_|disp_enable~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; -defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y31_N22 +// Location: LCCOMB_X37_Y33_N24 cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( // Equation(s): // \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - .dataa(\ula_|border [1]), - .datab(\ula_|video_|cindex[1]~1_combout ), + .dataa(\ula_|video_|disp_enable~1_combout ), + .datab(\ula_|border [1]), .datac(\ula_|video_|screen_en~1_combout ), - .datad(\ula_|video_|disp_enable~1_combout ), + .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hCA00; +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hA808; defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N14 +// Location: LCCOMB_X32_Y33_N26 cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 @@ -58778,7 +59166,7 @@ defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N15 +// Location: FF_X32_Y33_N27 dffeas \ula_|video_|attr_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), @@ -58797,7 +59185,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X35_Y31_N19 +// Location: FF_X38_Y33_N1 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58816,50 +59204,50 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N18 +// Location: LCCOMB_X38_Y33_N0 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): -// \ula_|video_|VGA_B[1]~0_combout = (\ula_|video_|LessThan3~0_combout & (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) +// \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) - .dataa(\ula_|video_|LessThan3~0_combout ), - .datab(\ula_|video_|LessThan2~1_combout ), + .dataa(\ula_|video_|LessThan2~1_combout ), + .datab(\ula_|video_|LessThan3~0_combout ), .datac(\ula_|video_|attr [6]), .datad(\ula_|video_|disp_enable~0_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h2000; +defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N16 +// Location: LCCOMB_X37_Y33_N2 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): -// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[1]~1_combout & \ula_|video_|VGA_B[1]~0_combout )) +// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[1]~1_combout )) .dataa(\ula_|video_|screen_en~1_combout ), - .datab(\ula_|video_|cindex[1]~1_combout ), - .datac(gnd), - .datad(\ula_|video_|VGA_B[1]~0_combout ), + .datab(gnd), + .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8800; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N3 +// Location: FF_X31_Y12_N17 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\D[2]~40_combout ), + .asdata(\D[2]~46_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\ula_|always0~1_combout ), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|border [2]), @@ -58869,7 +59257,7 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y21_N30 +// Location: LCCOMB_X32_Y33_N8 cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58886,7 +59274,7 @@ defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y21_N31 +// Location: FF_X32_Y33_N9 dffeas \ula_|video_|attr_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), @@ -58905,7 +59293,7 @@ defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N11 +// Location: FF_X36_Y33_N21 dffeas \ula_|video_|attr[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58924,7 +59312,7 @@ defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y23_N14 +// Location: LCCOMB_X32_Y33_N30 cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -58941,7 +59329,7 @@ defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y23_N15 +// Location: FF_X32_Y33_N31 dffeas \ula_|video_|attr_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), @@ -58960,7 +59348,7 @@ defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N1 +// Location: FF_X36_Y33_N15 dffeas \ula_|video_|attr[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58979,49 +59367,49 @@ defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N0 +// Location: LCCOMB_X36_Y33_N14 cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( // Equation(s): // \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) - .dataa(\ula_|video_|attr [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|attr [2]), .datac(\ula_|video_|attr [5]), .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N30 +// Location: LCCOMB_X38_Y33_N26 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) .dataa(\ula_|border [2]), - .datab(\ula_|video_|disp_enable~1_combout ), - .datac(\ula_|video_|screen_en~1_combout ), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hC808; +defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hE020; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N24 +// Location: LCCOMB_X36_Y33_N20 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|VGA_B[1]~0_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|screen_en~1_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), .datab(\ula_|video_|cindex[2]~2_combout ), .datac(gnd), - .datad(\ula_|video_|VGA_B[1]~0_combout ), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), .cout()); @@ -59030,33 +59418,16 @@ defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \ula_|border[0]~feeder ( -// Equation(s): -// \ula_|border[0]~feeder_combout = \D[0]~49_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[0]~49_combout ), - .cin(gnd), - .combout(\ula_|border[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N9 +// Location: FF_X32_Y22_N1 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[0]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[0]~58_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), + .sload(vcc), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|border [0]), @@ -59066,7 +59437,7 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y27_N6 +// Location: LCCOMB_X32_Y33_N20 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -59083,7 +59454,7 @@ defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y27_N7 +// Location: FF_X32_Y33_N21 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -59102,15 +59473,32 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y31_N7 +// Location: LCCOMB_X37_Y33_N28 +cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( +// Equation(s): +// \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|attr_prefetch [0]), + .cin(gnd), + .combout(\ula_|video_|attr[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y33_N29 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [0]), + .d(\ula_|video_|attr[0]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59121,15 +59509,32 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X34_Y31_N13 +// Location: LCCOMB_X32_Y33_N2 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N3 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59140,7 +59545,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y31_N9 +// Location: FF_X36_Y33_N29 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59159,49 +59564,49 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N8 +// Location: LCCOMB_X36_Y33_N28 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): // \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) - .dataa(\ula_|video_|attr [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|attr [0]), .datac(\ula_|video_|attr [3]), .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N2 +// Location: LCCOMB_X37_Y33_N30 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) - .dataa(\ula_|border [0]), - .datab(\ula_|video_|cindex[0]~3_combout ), - .datac(\ula_|video_|disp_enable~1_combout ), - .datad(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|video_|disp_enable~1_combout ), + .datab(\ula_|border [0]), + .datac(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hC0A0; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hA808; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y31_N0 +// Location: LCCOMB_X37_Y33_N0 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[0]~3_combout & \ula_|video_|VGA_B[1]~0_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[0]~3_combout )) .dataa(\ula_|video_|screen_en~1_combout ), .datab(gnd), - .datac(\ula_|video_|cindex[0]~3_combout ), - .datad(\ula_|video_|VGA_B[1]~0_combout ), + .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~2_combout ), .cout()); @@ -59210,24 +59615,24 @@ defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N4 +// Location: LCCOMB_X37_Y33_N26 cycloneive_lcell_comb \ula_|video_|Equal0~2 ( // Equation(s): -// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_hc [8] & \ula_|video_|vga_hc [6])) +// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [9] & !\ula_|video_|vga_hc [8])) - .dataa(\ula_|video_|vga_hc [9]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [6]), + .dataa(\ula_|video_|vga_hc [6]), + .datab(\ula_|video_|vga_hc [9]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [8]), .cin(gnd), .combout(\ula_|video_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0500; +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0022; defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y31_N9 +// Location: FF_X37_Y33_N7 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -59246,21 +59651,21 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N8 +// Location: LCCOMB_X37_Y33_N6 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): -// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|VGA_HS~_Duplicate_1_q & \ula_|video_|Equal1~0_combout )))) # (!\ula_|video_|Equal0~2_combout & (((\ula_|video_|VGA_HS~_Duplicate_1_q -// & \ula_|video_|Equal1~0_combout )))) +// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & +// (\ula_|video_|VGA_HS~_Duplicate_1_q ))) .dataa(\ula_|video_|Equal0~2_combout ), - .datab(\ula_|video_|Equal0~1_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|VGA_HS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal0~1_combout ), .cin(gnd), .combout(\ula_|video_|Selector0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector0~0 .lut_mask = 16'hF888; +defparam \ula_|video_|Selector0~0 .lut_mask = 16'hEAC0; defparam \ula_|video_|Selector0~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59283,7 +59688,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y31_N31 +// Location: FF_X34_Y33_N25 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -59302,21 +59707,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N30 +// Location: LCCOMB_X34_Y33_N24 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1]) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|Equal2~2_combout & (((\ula_|video_|VGA_VS~_Duplicate_1_q & -// !\ula_|video_|Equal3~1_combout )))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal3~1_combout & (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1])))) # (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|VGA_VS~_Duplicate_1_q ) # ((\ula_|video_|Equal2~2_combout & +// \ula_|video_|vga_vc [1])))) - .dataa(\ula_|video_|Equal2~2_combout ), - .datab(\ula_|video_|vga_vc [1]), + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Equal2~2_combout ), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'hDC50; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59339,7 +59744,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N30 +// Location: LCCOMB_X47_Y17_N4 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -59356,7 +59761,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N31 +// Location: FF_X47_Y17_N5 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -59375,7 +59780,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X52_Y13_N9 +// Location: FF_X47_Y17_N25 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -59394,7 +59799,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N8 +// Location: LCCOMB_X47_Y17_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -59411,41 +59816,41 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N22 +// Location: LCCOMB_X47_Y17_N26 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(gnd), .datab(gnd), - .datac(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nM1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF55; +defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y16_N4 +// Location: LCCOMB_X23_Y26_N0 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[3]~77_combout $ (\D[4]~79_combout $ (((\ula_|i2s_intf_|PCM_INL [14]) # (\ula_|i2s_intf_|PCM_INR [14])))) +// \ula_|beep~0_combout = \D[4]~98_combout $ (\raw_loader_in~input_o $ (\D[3]~96_combout )) - .dataa(\D[3]~77_combout ), - .datab(\ula_|i2s_intf_|PCM_INL [14]), - .datac(\D[4]~79_combout ), - .datad(\ula_|i2s_intf_|PCM_INR [14]), + .dataa(gnd), + .datab(\D[4]~98_combout ), + .datac(\raw_loader_in~input_o ), + .datad(\D[3]~96_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hA596; +defparam \ula_|beep~0 .lut_mask = 16'hC33C; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y16_N5 +// Location: FF_X23_Y26_N1 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), @@ -59454,7 +59859,7 @@ dffeas \ula_|beep ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|always0~1_combout ), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|beep~q ), diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo index 22052c4..33e447c 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/31/2022 14:04:24") + (DATE "04/01/2022 18:55:52") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1712:1712:1712) (1713:1713:1713)) - (PORT oe (592:592:592) (623:623:623)) + (PORT i (1954:1954:1954) (1953:1953:1953)) + (PORT oe (1513:1513:1513) (1540:1540:1540)) (IOPATH i o (2194:2194:2194) (2119:2119:2119)) (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1420:1420:1420) (1454:1454:1454)) - (PORT oe (2026:2026:2026) (2039:2039:2039)) + (PORT i (1975:1975:1975) (1942:1942:1942)) + (PORT oe (1769:1769:1769) (1737:1737:1737)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1196:1196:1196) (1185:1185:1185)) - (PORT oe (2026:2026:2026) (2039:2039:2039)) + (PORT i (1830:1830:1830) (1856:1856:1856)) + (PORT oe (1769:1769:1769) (1737:1737:1737)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1502:1502:1502) (1519:1519:1519)) - (PORT oe (2197:2197:2197) (2257:2257:2257)) + (PORT i (2041:2041:2041) (2075:2075:2075)) + (PORT oe (1983:1983:1983) (2026:2026:2026)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1231:1231:1231) (1234:1234:1234)) - (PORT oe (2197:2197:2197) (2257:2257:2257)) + (PORT i (2091:2091:2091) (2141:2141:2141)) + (PORT oe (1983:1983:1983) (2026:2026:2026)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1059:1059:1059) (1081:1081:1081)) - (PORT oe (2172:2172:2172) (2219:2219:2219)) + (PORT i (1824:1824:1824) (1811:1811:1811)) + (PORT oe (1772:1772:1772) (1805:1805:1805)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1239:1239:1239) (1254:1254:1254)) - (PORT oe (2172:2172:2172) (2219:2219:2219)) + (PORT i (1513:1513:1513) (1526:1526:1526)) + (PORT oe (1772:1772:1772) (1805:1805:1805)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (846:846:846) (882:882:882)) - (PORT oe (2172:2172:2172) (2219:2219:2219)) + (PORT i (1827:1827:1827) (1912:1912:1912)) + (PORT oe (1772:1772:1772) (1805:1805:1805)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (892:892:892) (913:913:913)) - (PORT oe (2174:2174:2174) (2224:2224:2224)) + (PORT i (909:909:909) (940:940:940)) + (PORT oe (1999:1999:1999) (2033:2033:2033)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1016:1016:1016) (1031:1031:1031)) - (PORT oe (2174:2174:2174) (2224:2224:2224)) + (PORT i (1589:1589:1589) (1611:1611:1611)) + (PORT oe (1999:1999:1999) (2033:2033:2033)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1042:1042:1042) (1068:1068:1068)) - (PORT oe (2371:2371:2371) (2444:2444:2444)) + (PORT i (1797:1797:1797) (1798:1798:1798)) + (PORT oe (2219:2219:2219) (2301:2301:2301)) (IOPATH i o (4033:4033:4033) (3610:3610:3610)) (IOPATH oe o (4029:4029:4029) (3565:3565:3565)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1030:1030:1030) (1043:1043:1043)) - (PORT oe (2174:2174:2174) (2224:2224:2224)) + (PORT i (1305:1305:1305) (1313:1313:1313)) + (PORT oe (1999:1999:1999) (2033:2033:2033)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (1458:1458:1458) (1449:1449:1449)) - (PORT oe (2020:2020:2020) (2038:2038:2038)) + (PORT i (2024:2024:2024) (1964:1964:1964)) + (PORT oe (1581:1581:1581) (1553:1553:1553)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (1010:1010:1010) (1043:1043:1043)) - (PORT oe (2371:2371:2371) (2445:2445:2445)) + (PORT i (2054:2054:2054) (2078:2078:2078)) + (PORT oe (2220:2220:2220) (2301:2301:2301)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1324:1324:1324) (1338:1338:1338)) - (PORT oe (2177:2177:2177) (2230:2230:2230)) + (PORT i (1495:1495:1495) (1526:1526:1526)) + (PORT oe (1979:1979:1979) (2021:2021:2021)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1023:1023:1023) (1031:1031:1031)) - (PORT oe (2196:2196:2196) (2251:2251:2251)) + (PORT i (1599:1599:1599) (1663:1663:1663)) + (PORT oe (1787:1787:1787) (1749:1749:1749)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (1014:1014:1014) (1014:1014:1014)) - (PORT oe (2591:2591:2591) (2591:2591:2591)) + (PORT i (1110:1110:1110) (1123:1123:1123)) + (PORT oe (2254:2254:2254) (2230:2230:2230)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (1052:1052:1052) (1028:1028:1028)) - (PORT oe (2535:2535:2535) (2513:2513:2513)) + (PORT i (1121:1121:1121) (1144:1144:1144)) + (PORT oe (2255:2255:2255) (2231:2231:2231)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (1103:1103:1103) (1108:1108:1108)) - (PORT oe (2277:2277:2277) (2254:2254:2254)) + (PORT i (1039:1039:1039) (1034:1034:1034)) + (PORT oe (1972:1972:1972) (1940:1940:1940)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (1070:1070:1070) (1073:1073:1073)) - (PORT oe (2591:2591:2591) (2591:2591:2591)) + (PORT i (1077:1077:1077) (1107:1107:1107)) + (PORT oe (2254:2254:2254) (2230:2230:2230)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (1359:1359:1359) (1342:1342:1342)) - (PORT oe (2266:2266:2266) (2243:2243:2243)) + (PORT i (1347:1347:1347) (1360:1360:1360)) + (PORT oe (1937:1937:1937) (1909:1909:1909)) (IOPATH i o (2194:2194:2194) (2119:2119:2119)) (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (883:883:883) (903:903:903)) - (PORT oe (2276:2276:2276) (2253:2253:2253)) + (PORT i (1247:1247:1247) (1225:1225:1225)) + (PORT oe (1971:1971:1971) (1939:1939:1939)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (1236:1236:1236) (1235:1235:1235)) - (PORT oe (2214:2214:2214) (2187:2187:2187)) + (PORT i (1127:1127:1127) (1128:1128:1128)) + (PORT oe (1883:1883:1883) (1842:1842:1842)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (821:821:821) (808:808:808)) - (PORT oe (2556:2556:2556) (2542:2542:2542)) + (PORT i (1045:1045:1045) (1025:1025:1025)) + (PORT oe (2220:2220:2220) (2182:2182:2182)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (1193:1193:1193) (1207:1207:1207)) - (PORT oe (1114:1114:1114) (1158:1158:1158)) + (PORT i (1255:1255:1255) (1313:1313:1313)) + (PORT oe (1518:1518:1518) (1539:1539:1539)) (IOPATH i o (2119:2119:2119) (2194:2194:2194)) (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1320:1320:1320) (1375:1375:1375)) - (PORT oe (2196:2196:2196) (2251:2251:2251)) + (PORT i (1602:1602:1602) (1577:1577:1577)) + (PORT oe (1787:1787:1787) (1749:1749:1749)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -353,8 +353,8 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (557:557:557) (566:566:566)) - (PORT oe (846:846:846) (903:903:903)) + (PORT i (1357:1357:1357) (1419:1419:1419)) + (PORT oe (1250:1250:1250) (1266:1266:1266)) (IOPATH i o (2180:2180:2180) (2277:2277:2277)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (715:715:715) (671:671:671)) - (PORT oe (623:623:623) (670:670:670)) + (PORT i (967:967:967) (940:940:940)) + (PORT oe (1226:1226:1226) (1242:1242:1242)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -377,7 +377,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1441:1441:1441) (1396:1396:1396)) + (PORT i (1447:1447:1447) (1410:1410:1410)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -392,6 +392,16 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1202:1202:1202) (1194:1194:1194)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_obuf") (INSTANCE AUD_XCK\~output) @@ -442,7 +452,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1103:1103:1103) (1138:1138:1138)) + (PORT i (1082:1082:1082) (1068:1068:1068)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -452,7 +462,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1146:1146:1146) (1140:1140:1140)) + (PORT i (995:995:995) (1003:1003:1003)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -462,7 +472,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (486:486:486) (483:483:483)) + (PORT i (719:719:719) (672:672:672)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -472,7 +482,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1077:1077:1077) (1116:1116:1116)) + (PORT i (917:917:917) (865:865:865)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -482,7 +492,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (795:795:795) (779:779:779)) + (PORT i (908:908:908) (871:871:871)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -492,7 +502,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (758:758:758) (719:719:719)) + (PORT i (670:670:670) (626:626:626)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -502,7 +512,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (993:993:993) (969:969:969)) + (PORT i (784:784:784) (728:728:728)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -512,7 +522,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (993:993:993) (969:969:969)) + (PORT i (784:784:784) (728:728:728)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -522,7 +532,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (686:686:686) (662:662:662)) + (PORT i (664:664:664) (633:633:633)) (IOPATH i o (4033:4033:4033) (3610:3610:3610)) ) ) @@ -532,7 +542,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (473:473:473) (459:459:459)) + (PORT i (645:645:645) (617:617:617)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -542,7 +552,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (964:964:964) (910:910:910)) + (PORT i (883:883:883) (830:830:830)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -552,7 +562,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1321:1321:1321) (1252:1252:1252)) + (PORT i (1278:1278:1278) (1196:1196:1196)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -580,7 +590,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (1126:1126:1126) (1086:1086:1086)) + (PORT i (1842:1842:1842) (1809:1809:1809)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) ) ) @@ -590,7 +600,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (558:558:558) (553:553:553)) + (PORT i (1161:1161:1161) (1186:1186:1186)) (IOPATH i o (3539:3539:3539) (3961:3961:3961)) ) ) @@ -600,7 +610,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (287:287:287) (283:283:283)) + (PORT i (862:862:862) (826:826:826)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) ) ) @@ -610,7 +620,7 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (1662:1662:1662) (1720:1720:1720)) + (PORT i (1253:1253:1253) (1261:1261:1261)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -724,7 +734,20 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (691:691:691) (698:698:698)) + (PORT inclk[0] (655:655:655) (669:669:669)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1052:1052:1052)) + (PORT datad (1052:1052:1052) (1044:1044:1044)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -733,122 +756,13 @@ (INSTANCE z80_\|sequencer_\|ena_M) (DELAY (ABSOLUTE - (PORT datac (828:828:828) (848:848:848)) - (PORT datad (797:797:797) (806:806:806)) + (PORT datac (1029:1029:1029) (1028:1028:1028)) + (PORT datad (1049:1049:1049) (1040:1040:1040)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE KEY\[0\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (461:461:461) (708:708:708)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE reset) - (DELAY - (ABSOLUTE - (PORT datac (1753:1753:1753) (1657:1657:1657)) - (PORT datad (757:757:757) (748:748:748)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x1\~0) - (DELAY - (ABSOLUTE - (PORT datad (181:181:181) (202:202:202)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|fpga_reset) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|fpga_reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (667:667:667) (673:673:673)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|x1) - (DELAY - (ABSOLUTE - (PORT clk (1371:1371:1371) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1360:1360:1360)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) - (DELAY - (ABSOLUTE - (PORT dataa (1060:1060:1060) (1088:1088:1088)) - (PORT datab (979:979:979) (1026:1026:1026)) - (PORT datad (339:339:339) (384:384:384)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1360:1360:1360)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (540:540:540) (584:584:584)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE KEY\[1\]\~input) @@ -863,9 +777,9 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) (DELAY (ABSOLUTE - (PORT datac (3460:3460:3460) (3524:3524:3524)) - (PORT datad (1044:1044:1044) (1070:1070:1070)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (321:321:321) (448:448:448)) + (PORT datad (1849:1849:1849) (1871:1871:1871)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -875,9 +789,9 @@ (INSTANCE z80_\|interrupts_\|nmi_armed) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1704:1704:1704)) + (PORT clk (1351:1351:1351) (1338:1338:1338)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (695:695:695) (696:696:696)) + (PORT clrn (1229:1229:1229) (1175:1175:1175)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -891,31 +805,33 @@ (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) (DELAY (ABSOLUTE - (PORT datad (984:984:984) (1001:1001:1001)) + (PORT datad (736:736:736) (745:745:745)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) (DELAY (ABSOLUTE - (PORT datac (1194:1194:1194) (1198:1198:1198)) - (PORT datad (1121:1121:1121) (1161:1161:1161)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datac (219:219:219) (288:288:288)) + (PORT datad (226:226:226) (290:290:290)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (INSTANCE z80_\|execute_\|ixy_d\~4) (DELAY (ABSOLUTE - (PORT dataa (1203:1203:1203) (1275:1275:1275)) - (PORT datad (1280:1280:1280) (1292:1292:1292)) - (IOPATH dataa combout (287:287:287) (289:289:289)) + (PORT dataa (2229:2229:2229) (2292:2292:2292)) + (PORT datab (2226:2226:2226) (2286:2286:2286)) + (PORT datad (1468:1468:1468) (1557:1557:1557)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -925,9 +841,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (851:851:851) (873:873:873)) - (PORT datab (248:248:248) (322:322:322)) - (PORT datad (808:808:808) (818:818:818)) + (PORT dataa (1045:1045:1045) (1047:1047:1047)) + (PORT datab (378:378:378) (425:425:425)) + (PORT datad (1056:1056:1056) (1045:1045:1045)) (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -940,9 +856,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) + (PORT clk (1362:1362:1362) (1383:1383:1383)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) + (PORT clrn (1408:1408:1408) (1379:1379:1379)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -951,14 +867,28 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1262:1262:1262) (1213:1213:1213)) + (PORT datab (1423:1423:1423) (1478:1478:1478)) + (PORT datac (1249:1249:1249) (1279:1279:1279)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (857:857:857) (888:888:888)) - (PORT datab (242:242:242) (312:312:312)) - (PORT datad (797:797:797) (809:809:809)) + (PORT dataa (1060:1060:1060) (1066:1066:1066)) + (PORT datab (379:379:379) (433:433:433)) + (PORT datad (1043:1043:1043) (1031:1031:1031)) (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -971,9 +901,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) + (PORT clk (1362:1362:1362) (1383:1383:1383)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) + (PORT clrn (1408:1408:1408) (1379:1379:1379)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -984,13 +914,53 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) + (INSTANCE z80_\|pla_decode_\|Equal32\~0) (DELAY (ABSOLUTE - (PORT dataa (1295:1295:1295) (1313:1313:1313)) - (PORT datac (798:798:798) (834:834:834)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (360:360:360) (412:412:412)) + (PORT datad (612:612:612) (661:661:661)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) + (DELAY + (ABSOLUTE + (PORT datab (2400:2400:2400) (2429:2429:2429)) + (PORT datad (1482:1482:1482) (1552:1552:1552)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1268:1268:1268) (1344:1344:1344)) + (PORT datad (1113:1113:1113) (1173:1173:1173)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1551:1551:1551) (1547:1547:1547)) + (PORT datab (863:863:863) (876:876:876)) + (PORT datac (1969:1969:1969) (2066:2066:2066)) + (PORT datad (1075:1075:1075) (1083:1083:1083)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -999,8 +969,8 @@ (INSTANCE z80_\|pla_decode_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT datac (1285:1285:1285) (1318:1318:1318)) - (PORT datad (1268:1268:1268) (1285:1285:1285)) + (PORT datac (1336:1336:1336) (1371:1371:1371)) + (PORT datad (2093:2093:2093) (2156:2156:2156)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -1008,25 +978,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (INSTANCE z80_\|pla_decode_\|Equal36\~0) (DELAY (ABSOLUTE - (PORT datab (898:898:898) (942:942:942)) - (PORT datac (884:884:884) (927:927:927)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (1155:1155:1155) (1200:1200:1200)) + (PORT datab (1518:1518:1518) (1601:1601:1601)) + (PORT datac (834:834:834) (865:865:865)) + (PORT datad (878:878:878) (895:895:895)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) (DELAY (ABSOLUTE - (PORT dataa (1117:1117:1117) (1138:1138:1138)) - (PORT datab (1257:1257:1257) (1212:1212:1212)) - (PORT datac (1877:1877:1877) (1894:1894:1894)) - (PORT datad (837:837:837) (848:848:848)) + (PORT dataa (1601:1601:1601) (1614:1614:1614)) + (PORT datab (1315:1315:1315) (1312:1312:1312)) + (PORT datac (783:783:783) (794:794:794)) + (PORT datad (731:731:731) (698:698:698)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1169:1169:1169)) + (PORT datab (2443:2443:2443) (2464:2464:2464)) + (PORT datac (781:781:781) (791:791:791)) + (PORT datad (898:898:898) (951:951:951)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1371:1371:1371)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (725:725:725)) + (PORT datab (1149:1149:1149) (1197:1197:1197)) + (PORT datac (897:897:897) (935:935:935)) + (PORT datad (1227:1227:1227) (1306:1306:1306)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2170:2170:2170) (2236:2236:2236)) + (PORT datab (1514:1514:1514) (1603:1603:1603)) + (PORT datac (834:834:834) (863:863:863)) + (PORT datad (622:622:622) (647:647:647)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -1034,15 +1074,121 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (DELAY + (ABSOLUTE + (PORT dataa (1618:1618:1618) (1654:1654:1654)) + (PORT datab (780:780:780) (764:764:764)) + (PORT datac (1286:1286:1286) (1282:1282:1282)) + (PORT datad (1889:1889:1889) (1943:1943:1943)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instED) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1371:1371:1371)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (728:728:728)) + (PORT datac (890:890:890) (927:927:927)) + (PORT datad (1223:1223:1223) (1301:1301:1301)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2001:2001:2001) (2098:2098:2098)) + (PORT datac (1337:1337:1337) (1368:1368:1368)) + (PORT datad (2095:2095:2095) (2153:2153:2153)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (569:569:569)) + (PORT datab (972:972:972) (1033:1033:1033)) + (PORT datac (1235:1235:1235) (1324:1324:1324)) + (PORT datad (850:850:850) (879:879:879)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT datab (917:917:917) (979:979:979)) + (PORT datac (601:601:601) (640:640:640)) + (PORT datad (1151:1151:1151) (1208:1208:1208)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1348:1348:1348)) + (PORT datab (1375:1375:1375) (1421:1421:1421)) + (PORT datac (1321:1321:1321) (1379:1379:1379)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pla_decode_\|Equal6\~0) (DELAY (ABSOLUTE - (PORT dataa (1286:1286:1286) (1296:1296:1296)) - (PORT datab (1208:1208:1208) (1216:1216:1216)) - (PORT datac (253:253:253) (339:339:339)) - (PORT datad (263:263:263) (339:339:339)) + (PORT dataa (662:662:662) (725:725:725)) + (PORT datab (1149:1149:1149) (1197:1197:1197)) + (PORT datac (897:897:897) (936:936:936)) + (PORT datad (1227:1227:1227) (1307:1307:1307)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -1052,13 +1198,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (INSTANCE z80_\|execute_\|ctl_mRead\~14) (DELAY (ABSOLUTE - (PORT datab (1285:1285:1285) (1337:1337:1337)) - (PORT datac (1570:1570:1570) (1624:1624:1624)) - (PORT datad (1561:1561:1561) (1604:1604:1604)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (1126:1126:1126) (1167:1167:1167)) + (PORT datab (1177:1177:1177) (1243:1243:1243)) + (PORT datad (653:653:653) (694:694:694)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2447:2447:2447) (2537:2537:2537)) + (PORT datab (821:821:821) (835:835:835)) + (PORT datac (1028:1028:1028) (1065:1065:1065)) + (PORT datad (1063:1063:1063) (1082:1082:1082)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -1066,15 +1228,1137 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) (DELAY (ABSOLUTE - (PORT dataa (1265:1265:1265) (1283:1283:1283)) - (PORT datab (824:824:824) (821:821:821)) - (PORT datac (999:999:999) (989:989:989)) - (PORT datad (1059:1059:1059) (1073:1073:1073)) + (PORT dataa (863:863:863) (923:923:923)) + (PORT datab (1440:1440:1440) (1502:1502:1502)) + (PORT datac (1299:1299:1299) (1315:1315:1315)) + (PORT datad (182:182:182) (214:214:214)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1119:1119:1119)) + (PORT datad (1947:1947:1947) (2004:2004:2004)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (1052:1052:1052)) + (PORT datab (1029:1029:1029) (1024:1024:1024)) + (PORT datac (310:310:310) (319:319:319)) + (PORT datad (638:638:638) (672:672:672)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datac (1314:1314:1314) (1383:1383:1383)) + (PORT datad (1350:1350:1350) (1411:1411:1411)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1191:1191:1191)) + (PORT datab (1516:1516:1516) (1601:1601:1601)) + (PORT datac (1576:1576:1576) (1593:1593:1593)) + (PORT datad (879:879:879) (897:897:897)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT datac (1830:1830:1830) (1949:1949:1949)) + (PORT datad (1139:1139:1139) (1170:1170:1170)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1785:1785:1785) (1823:1823:1823)) + (PORT datac (2376:2376:2376) (2399:2399:2399)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (835:835:835)) + (PORT datab (947:947:947) (992:992:992)) + (PORT datac (779:779:779) (830:830:830)) + (PORT datad (859:859:859) (876:876:876)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~1) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (842:842:842)) + (PORT datab (821:821:821) (826:826:826)) + (PORT datac (838:838:838) (890:890:890)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (841:841:841)) + (PORT datab (824:824:824) (822:822:822)) + (PORT datac (839:839:839) (888:888:888)) + (PORT datad (1082:1082:1082) (1087:1087:1087)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (807:807:807)) + (PORT datac (904:904:904) (936:936:936)) + (PORT datad (1074:1074:1074) (1054:1054:1054)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2000:2000:2000) (2094:2094:2094)) + (PORT datac (1337:1337:1337) (1365:1365:1365)) + (PORT datad (2091:2091:2091) (2150:2150:2150)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (861:861:861)) + (PORT datab (1587:1587:1587) (1615:1615:1615)) + (PORT datac (1051:1051:1051) (1035:1035:1035)) + (PORT datad (602:602:602) (618:618:618)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (871:871:871)) + (PORT datab (2149:2149:2149) (2219:2219:2219)) + (PORT datac (1578:1578:1578) (1596:1596:1596)) + (PORT datad (618:618:618) (643:643:643)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1186:1186:1186)) + (PORT datab (1912:1912:1912) (2034:2034:2034)) + (PORT datac (798:798:798) (784:784:784)) + (PORT datad (1339:1339:1339) (1371:1371:1371)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT datab (1310:1310:1310) (1338:1338:1338)) + (PORT datac (1438:1438:1438) (1451:1451:1451)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~6) + (DELAY + (ABSOLUTE + (PORT datac (1484:1484:1484) (1509:1509:1509)) + (PORT datad (1740:1740:1740) (1785:1785:1785)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~9) + (DELAY + (ABSOLUTE + (PORT datac (951:951:951) (1008:1008:1008)) + (PORT datad (910:910:910) (938:938:938)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (955:955:955)) + (PORT datab (917:917:917) (933:933:933)) + (PORT datac (837:837:837) (836:836:836)) + (PORT datad (1899:1899:1899) (1915:1915:1915)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (411:411:411)) + (PORT datab (1065:1065:1065) (1080:1080:1080)) + (PORT datac (573:573:573) (605:605:605)) + (PORT datad (1017:1017:1017) (1034:1034:1034)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal44\~0) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (727:727:727)) + (PORT datab (1154:1154:1154) (1202:1202:1202)) + (PORT datac (891:891:891) (928:928:928)) + (PORT datad (1223:1223:1223) (1302:1302:1302)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~16) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (972:972:972)) + (PORT datab (1230:1230:1230) (1207:1207:1207)) + (PORT datac (856:856:856) (914:914:914)) + (PORT datad (1025:1025:1025) (1004:1004:1004)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT datab (773:773:773) (797:797:797)) + (PORT datac (572:572:572) (595:595:595)) + (PORT datad (192:192:192) (222:222:222)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal50\~0) + (DELAY + (ABSOLUTE + (PORT datab (918:918:918) (983:983:983)) + (PORT datac (602:602:602) (637:637:637)) + (PORT datad (1080:1080:1080) (1127:1127:1127)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1166:1166:1166)) + (PORT datab (1178:1178:1178) (1243:1243:1243)) + (PORT datad (653:653:653) (694:694:694)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~17) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (961:961:961)) + (PORT datab (1021:1021:1021) (990:990:990)) + (PORT datac (854:854:854) (908:908:908)) + (PORT datad (1001:1001:1001) (970:970:970)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datac (1464:1464:1464) (1537:1537:1537)) + (PORT datad (909:909:909) (938:938:938)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (600:600:600)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (1021:1021:1021) (995:995:995)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1484:1484:1484)) + (PORT datab (1312:1312:1312) (1341:1341:1341)) + (PORT datac (350:350:350) (354:354:354)) + (PORT datad (1660:1660:1660) (1718:1718:1718)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1006:1006:1006) (1006:1006:1006)) + (PORT datab (212:212:212) (254:254:254)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1234:1234:1234)) + (PORT datab (1381:1381:1381) (1410:1410:1410)) + (PORT datac (1348:1348:1348) (1401:1401:1401)) + (PORT datad (1893:1893:1893) (2005:2005:2005)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1407:1407:1407) (1373:1373:1373)) + (PORT ena (745:745:745) (752:752:752)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (851:851:851)) + (PORT datac (591:591:591) (628:628:628)) + (PORT datad (1268:1268:1268) (1330:1330:1330)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (1209:1209:1209)) + (PORT datab (418:418:418) (465:465:465)) + (PORT datac (1561:1561:1561) (1571:1571:1571)) + (PORT datad (244:244:244) (293:293:293)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (710:710:710)) + (PORT datab (925:925:925) (963:963:963)) + (PORT datac (632:632:632) (694:694:694)) + (PORT datad (1226:1226:1226) (1304:1304:1304)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1491:1491:1491) (1603:1603:1603)) + (PORT datab (1405:1405:1405) (1444:1444:1444)) + (PORT datac (1574:1574:1574) (1628:1628:1628)) + (PORT datad (1380:1380:1380) (1457:1457:1457)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1253:1253:1253)) + (PORT datab (1150:1150:1150) (1183:1183:1183)) + (PORT datac (957:957:957) (983:983:983)) + (PORT datad (1554:1554:1554) (1554:1554:1554)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT datac (625:625:625) (655:655:655)) + (PORT datad (1595:1595:1595) (1666:1666:1666)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (593:593:593)) + (PORT datac (1016:1016:1016) (1041:1041:1041)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (227:227:227)) + (PORT datab (218:218:218) (262:262:262)) + (PORT datac (616:616:616) (628:628:628)) + (PORT datad (1898:1898:1898) (1914:1914:1914)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (960:960:960)) + (PORT datab (1142:1142:1142) (1138:1138:1138)) + (PORT datac (627:627:627) (661:661:661)) + (PORT datad (164:164:164) (186:186:186)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (921:921:921)) + (PORT datab (1436:1436:1436) (1502:1502:1502)) + (PORT datac (1297:1297:1297) (1313:1313:1313)) + (PORT datad (184:184:184) (214:214:214)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (DELAY + (ABSOLUTE + (PORT dataa (261:261:261) (346:346:346)) + (PORT datac (833:833:833) (861:861:861)) + (PORT datad (852:852:852) (878:878:878)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1621:1621:1621) (1670:1670:1670)) + (PORT datac (1054:1054:1054) (1097:1097:1097)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (597:597:597)) + (PORT datab (1083:1083:1083) (1081:1081:1081)) + (PORT datac (858:858:858) (922:922:922)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (638:638:638)) + (PORT datab (601:601:601) (604:604:604)) + (PORT datac (859:859:859) (924:924:924)) + (PORT datad (829:829:829) (826:826:826)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (868:868:868)) + (PORT datab (1107:1107:1107) (1080:1080:1080)) + (PORT datac (1672:1672:1672) (1725:1725:1725)) + (PORT datad (807:807:807) (820:820:820)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1556:1556:1556) (1580:1580:1580)) + (PORT datac (1522:1522:1522) (1548:1548:1548)) + (PORT datad (1081:1081:1081) (1109:1109:1109)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datac (767:767:767) (786:786:786)) + (PORT datad (825:825:825) (873:873:873)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1584:1584:1584)) + (PORT datab (1552:1552:1552) (1580:1580:1580)) + (PORT datac (1363:1363:1363) (1419:1419:1419)) + (PORT datad (1142:1142:1142) (1162:1162:1162)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1387:1387:1387)) + (PORT datab (1132:1132:1132) (1189:1189:1189)) + (PORT datac (1315:1315:1315) (1370:1370:1370)) + (PORT datad (770:770:770) (747:747:747)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (808:808:808)) + (PORT datab (1149:1149:1149) (1166:1166:1166)) + (PORT datac (1267:1267:1267) (1245:1245:1245)) + (PORT datad (1175:1175:1175) (1183:1183:1183)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (590:590:590)) + (PORT datab (881:881:881) (942:942:942)) + (PORT datad (1060:1060:1060) (1048:1048:1048)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1442:1442:1442) (1476:1476:1476)) + (PORT datab (917:917:917) (932:932:932)) + (PORT datac (1484:1484:1484) (1570:1570:1570)) + (PORT datad (1129:1129:1129) (1157:1157:1157)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1344:1344:1344) (1415:1415:1415)) + (PORT datab (1421:1421:1421) (1497:1497:1497)) + (PORT datac (1271:1271:1271) (1288:1288:1288)) + (PORT datad (1447:1447:1447) (1437:1437:1437)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (819:819:819)) + (PORT datab (1683:1683:1683) (1701:1701:1701)) + (PORT datac (805:805:805) (790:790:790)) + (PORT datad (1375:1375:1375) (1390:1390:1390)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1167:1167:1167)) + (PORT datac (876:876:876) (907:907:907)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (865:865:865)) + (PORT datab (863:863:863) (893:893:893)) + (PORT datac (1483:1483:1483) (1575:1575:1575)) + (PORT datad (1128:1128:1128) (1157:1157:1157)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT datac (1578:1578:1578) (1613:1613:1613)) + (PORT datad (1886:1886:1886) (1938:1938:1938)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (237:237:237)) + (PORT datab (1078:1078:1078) (1072:1072:1072)) + (PORT datac (1486:1486:1486) (1452:1452:1452)) + (PORT datad (1339:1339:1339) (1387:1387:1387)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1474:1474:1474)) + (PORT datab (913:913:913) (929:929:929)) + (PORT datac (1483:1483:1483) (1581:1581:1581)) + (PORT datad (1134:1134:1134) (1164:1164:1164)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2001:2001:2001) (2097:2097:2097)) + (PORT datab (865:865:865) (881:881:881)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (385:385:385) (421:421:421)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (453:453:453)) + (PORT datab (863:863:863) (875:875:875)) + (PORT datac (1973:1973:1973) (2062:2062:2062)) + (PORT datad (1053:1053:1053) (1052:1052:1052)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (452:452:452)) + (PORT datab (863:863:863) (876:876:876)) + (PORT datac (1969:1969:1969) (2064:2064:2064)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal38\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1493:1493:1493) (1602:1602:1602)) + (PORT datab (1418:1418:1418) (1497:1497:1497)) + (PORT datac (1573:1573:1573) (1625:1625:1625)) + (PORT datad (1334:1334:1334) (1354:1354:1354)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1033:1033:1033) (1015:1015:1015)) + (PORT datab (1013:1013:1013) (1053:1053:1053)) + (PORT datac (546:546:546) (546:546:546)) + (PORT datad (822:822:822) (842:842:842)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (821:821:821)) + (PORT datab (1265:1265:1265) (1297:1297:1297)) + (PORT datac (543:543:543) (561:561:561)) + (PORT datad (547:547:547) (536:536:536)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datab (1792:1792:1792) (1827:1827:1827)) + (PORT datac (1077:1077:1077) (1135:1135:1135)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (461:461:461)) + (PORT datab (865:865:865) (881:881:881)) + (PORT datac (1972:1972:1972) (2061:2061:2061)) + (PORT datad (340:340:340) (342:342:342)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1227:1227:1227)) + (PORT datab (1119:1119:1119) (1117:1117:1117)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1173:1173:1173) (1221:1221:1221)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (636:636:636)) + (PORT datab (594:594:594) (585:585:585)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (1082:1082:1082) (1083:1083:1083)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (869:869:869)) + (PORT datab (208:208:208) (254:254:254)) + (PORT datac (576:576:576) (584:584:584)) + (PORT datad (603:603:603) (621:621:621)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (1339:1339:1339) (1327:1327:1327)) + (PORT datab (1126:1126:1126) (1187:1187:1187)) + (PORT datac (631:631:631) (657:657:657)) + (PORT datad (1056:1056:1056) (1051:1051:1051)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (680:680:680)) + (PORT datab (1062:1062:1062) (1049:1049:1049)) + (PORT datac (1678:1678:1678) (1728:1728:1728)) + (PORT datad (540:540:540) (545:545:545)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1345:1345:1345) (1407:1407:1407)) + (PORT datab (1044:1044:1044) (1070:1070:1070)) + (PORT datac (1099:1099:1099) (1163:1163:1163)) + (PORT datad (600:600:600) (626:626:626)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1351:1351:1351) (1413:1413:1413)) + (PORT datab (628:628:628) (661:661:661)) + (PORT datac (1097:1097:1097) (1155:1155:1155)) + (PORT datad (1294:1294:1294) (1285:1285:1285)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -1085,9 +2369,9 @@ (INSTANCE z80_\|sequencer_\|M5\~0) (DELAY (ABSOLUTE - (PORT dataa (844:844:844) (869:869:869)) - (PORT datab (377:377:377) (423:423:423)) - (PORT datad (809:809:809) (818:818:818)) + (PORT dataa (1055:1055:1055) (1060:1060:1060)) + (PORT datab (243:243:243) (313:313:313)) + (PORT datad (1055:1055:1055) (1041:1041:1041)) (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -1100,9 +2384,9 @@ (INSTANCE z80_\|sequencer_\|M5) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) + (PORT clk (1362:1362:1362) (1383:1383:1383)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) + (PORT clrn (1408:1408:1408) (1379:1379:1379)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -1116,37 +2400,57 @@ (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) (DELAY (ABSOLUTE - (PORT dataa (1326:1326:1326) (1337:1337:1337)) - (PORT datac (1227:1227:1227) (1219:1219:1219)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT datab (1460:1460:1460) (1548:1548:1548)) + (PORT datac (2403:2403:2403) (2409:2409:2409)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) + (INSTANCE z80_\|execute_\|setM1\~29) (DELAY (ABSOLUTE - (PORT datac (1078:1078:1078) (1106:1106:1106)) - (PORT datad (1662:1662:1662) (1652:1652:1652)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (599:599:599) (596:596:596)) + (PORT datab (866:866:866) (895:895:895)) + (PORT datac (934:934:934) (949:949:949)) + (PORT datad (608:608:608) (635:635:635)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) + (INSTANCE z80_\|execute_\|ctl_mRead\~25) (DELAY (ABSOLUTE - (PORT dataa (823:823:823) (816:816:816)) - (PORT datab (1522:1522:1522) (1513:1513:1513)) - (PORT datac (936:936:936) (946:946:946)) - (PORT datad (825:825:825) (833:833:833)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1795:1795:1795) (1857:1857:1857)) + (PORT datab (633:633:633) (669:669:669)) + (PORT datac (612:612:612) (643:643:643)) + (PORT datad (551:551:551) (551:551:551)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1769:1769:1769) (1771:1771:1771)) + (PORT datab (824:824:824) (869:869:869)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -1156,10 +2460,154 @@ (INSTANCE z80_\|execute_\|ctl_ir_we\~7) (DELAY (ABSOLUTE - (PORT dataa (1239:1239:1239) (1240:1240:1240)) - (PORT datab (563:563:563) (587:587:587)) - (PORT datac (1354:1354:1354) (1340:1340:1340)) - (PORT datad (872:872:872) (883:883:883)) + (PORT dataa (1164:1164:1164) (1212:1212:1212)) + (PORT datab (419:419:419) (463:463:463)) + (PORT datac (1560:1560:1560) (1572:1572:1572)) + (PORT datad (242:242:242) (294:294:294)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1269:1269:1269) (1344:1344:1344)) + (PORT datab (863:863:863) (909:909:909)) + (PORT datac (889:889:889) (907:907:907)) + (PORT datad (1117:1117:1117) (1173:1173:1173)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (968:968:968)) + (PORT datab (1229:1229:1229) (1209:1209:1209)) + (PORT datac (851:851:851) (913:913:913)) + (PORT datad (1024:1024:1024) (1000:1000:1000)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (598:598:598)) + (PORT datab (1162:1162:1162) (1169:1169:1169)) + (PORT datac (524:524:524) (520:520:520)) + (PORT datad (1507:1507:1507) (1516:1516:1516)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (713:713:713)) + (PORT datab (199:199:199) (233:233:233)) + (PORT datac (231:231:231) (314:314:314)) + (PORT datad (826:826:826) (839:839:839)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (845:845:845)) + (PORT datab (1015:1015:1015) (1057:1057:1057)) + (PORT datac (1018:1018:1018) (1024:1024:1024)) + (PORT datad (622:622:622) (638:638:638)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (438:438:438)) + (PORT datab (1792:1792:1792) (1867:1867:1867)) + (PORT datac (958:958:958) (971:971:971)) + (PORT datad (1445:1445:1445) (1464:1464:1464)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (886:886:886)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (822:822:822) (840:840:840)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (602:602:602)) + (PORT datab (1112:1112:1112) (1118:1118:1118)) + (PORT datac (185:185:185) (225:225:225)) + (PORT datad (578:578:578) (592:592:592)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (408:408:408)) + (PORT datab (1081:1081:1081) (1087:1087:1087)) + (PORT datac (571:571:571) (603:603:603)) + (PORT datad (1022:1022:1022) (1035:1035:1035)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -1167,17 +2615,129 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1492:1492:1492) (1602:1602:1602)) + (PORT datab (1404:1404:1404) (1447:1447:1447)) + (PORT datac (1574:1574:1574) (1625:1625:1625)) + (PORT datad (1378:1378:1378) (1458:1458:1458)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1491:1491:1491) (1604:1604:1604)) + (PORT datab (1406:1406:1406) (1443:1443:1443)) + (PORT datac (1575:1575:1575) (1624:1624:1624)) + (PORT datad (1381:1381:1381) (1455:1455:1455)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1563:1563:1563) (1599:1599:1599)) + (PORT datab (1362:1362:1362) (1404:1404:1404)) + (PORT datac (2378:2378:2378) (2398:2398:2398)) + (PORT datad (1743:1743:1743) (1779:1779:1779)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (602:602:602)) + (PORT datab (1161:1161:1161) (1170:1170:1170)) + (PORT datac (1041:1041:1041) (1032:1032:1032)) + (PORT datad (523:523:523) (506:506:506)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1212:1212:1212)) + (PORT datab (419:419:419) (462:462:462)) + (PORT datac (1561:1561:1561) (1572:1572:1572)) + (PORT datad (241:241:241) (293:293:293)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1044:1044:1044)) + (PORT datab (1056:1056:1056) (1076:1076:1076)) + (PORT datac (507:507:507) (487:487:487)) + (PORT datad (565:565:565) (562:562:562)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (325:325:325)) + (PORT datab (421:421:421) (461:461:461)) + (PORT datac (173:173:173) (203:203:203)) + (PORT datad (1271:1271:1271) (1327:1327:1327)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pla_decode_\|Equal46\~0) (DELAY (ABSOLUTE - (PORT dataa (1314:1314:1314) (1336:1336:1336)) - (PORT datab (1990:1990:1990) (1994:1994:1994)) - (PORT datac (255:255:255) (341:341:341)) - (PORT datad (1273:1273:1273) (1281:1281:1281)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (259:259:259) (342:342:342)) + (PORT datab (875:875:875) (908:908:908)) + (PORT datac (836:836:836) (860:860:860)) + (PORT datad (1108:1108:1108) (1167:1167:1167)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -1188,56 +2748,28 @@ (INSTANCE z80_\|execute_\|ctl_ir_we\~10) (DELAY (ABSOLUTE - (PORT dataa (1380:1380:1380) (1370:1370:1370)) - (PORT datab (1195:1195:1195) (1195:1195:1195)) - (PORT datac (542:542:542) (564:564:564)) - (PORT datad (560:560:560) (565:565:565)) + (PORT dataa (1156:1156:1156) (1205:1205:1205)) + (PORT datab (794:794:794) (808:808:808)) + (PORT datac (1564:1564:1564) (1573:1573:1573)) + (PORT datad (242:242:242) (287:287:287)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1957:1957:1957) (1991:1991:1991)) + (PORT datab (1894:1894:1894) (1936:1936:1936)) + (PORT datac (896:896:896) (945:945:945)) + (PORT datad (1119:1119:1119) (1134:1134:1134)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1379:1379:1379) (1383:1383:1383)) - (PORT datab (1106:1106:1106) (1130:1130:1130)) - (PORT datac (1493:1493:1493) (1505:1505:1505)) - (PORT datad (1545:1545:1545) (1537:1537:1537)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) - (DELAY - (ABSOLUTE - (PORT datab (1265:1265:1265) (1271:1271:1271)) - (PORT datac (1249:1249:1249) (1259:1259:1259)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (574:574:574) (593:593:593)) - (PORT datab (556:556:556) (578:578:578)) - (PORT datac (638:638:638) (689:689:689)) - (PORT datad (874:874:874) (889:889:889)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -1245,44 +2777,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) (DELAY (ABSOLUTE - (PORT dataa (1281:1281:1281) (1273:1273:1273)) - (PORT datab (1102:1102:1102) (1126:1126:1126)) - (PORT datac (1489:1489:1489) (1501:1501:1501)) - (PORT datad (1213:1213:1213) (1213:1213:1213)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1279:1279:1279) (1291:1291:1291)) + (PORT datab (978:978:978) (1022:1022:1022)) + (PORT datac (711:711:711) (680:680:680)) + (PORT datad (1137:1137:1137) (1143:1143:1143)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1238:1238:1238) (1242:1242:1242)) - (PORT datab (569:569:569) (594:594:594)) - (PORT datac (1353:1353:1353) (1342:1342:1342)) - (PORT datad (870:870:870) (887:887:887)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_ir_we\~6) (DELAY (ABSOLUTE - (PORT datab (1269:1269:1269) (1278:1278:1278)) - (PORT datac (1254:1254:1254) (1266:1266:1266)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (907:907:907) (947:947:947)) + (PORT datac (1064:1064:1064) (1085:1085:1085)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) ) ) @@ -1292,284 +2808,12 @@ (INSTANCE z80_\|execute_\|ctl_ir_we\~8) (DELAY (ABSOLUTE - (PORT dataa (611:611:611) (626:626:626)) - (PORT datab (575:575:575) (599:599:599)) - (PORT datac (633:633:633) (685:685:685)) - (PORT datad (870:870:870) (881:881:881)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT datac (1049:1049:1049) (1083:1083:1083)) - (PORT datad (1094:1094:1094) (1142:1142:1142)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1038:1038:1038) (1054:1054:1054)) - (PORT datab (596:596:596) (595:595:595)) - (PORT datac (1442:1442:1442) (1398:1398:1398)) - (PORT datad (1056:1056:1056) (1062:1062:1062)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1021:1021:1021) (1019:1019:1019)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2855:2855:2855) (2838:2838:2838)) - (PORT datab (2009:2009:2009) (2022:2022:2022)) - (PORT datac (891:891:891) (920:920:920)) - (PORT datad (965:965:965) (940:940:940)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1142:1142:1142)) - (PORT datab (1084:1084:1084) (1096:1096:1096)) - (PORT datac (1081:1081:1081) (1133:1133:1133)) - (PORT datad (184:184:184) (208:208:208)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1282:1282:1282) (1294:1294:1294)) - (PORT datab (292:292:292) (377:377:377)) - (PORT datac (1176:1176:1176) (1185:1185:1185)) - (PORT datad (1221:1221:1221) (1244:1244:1244)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1726:1726:1726) (1790:1790:1790)) - (PORT datab (1591:1591:1591) (1643:1643:1643)) - (PORT datac (1569:1569:1569) (1618:1618:1618)) - (PORT datad (1260:1260:1260) (1301:1301:1301)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) - (DELAY - (ABSOLUTE - (PORT datac (1060:1060:1060) (1102:1102:1102)) - (PORT datad (1272:1272:1272) (1276:1276:1276)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1235:1235:1235)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (605:605:605) (630:630:630)) - (PORT datad (1717:1717:1717) (1718:1718:1718)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (585:585:585)) - (PORT datab (609:609:609) (619:619:619)) - (PORT datac (155:155:155) (186:186:186)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datab (1247:1247:1247) (1273:1273:1273)) - (PORT datad (1265:1265:1265) (1272:1272:1272)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (884:884:884)) - (PORT datac (216:216:216) (283:283:283)) - (PORT datad (800:800:800) (811:811:811)) + (PORT dataa (269:269:269) (332:332:332)) + (PORT datab (420:420:420) (460:460:460)) + (PORT datac (1115:1115:1115) (1139:1139:1139)) + (PORT datad (1266:1266:1266) (1324:1324:1324)) (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (PORT ena (1120:1120:1120) (1095:1095:1095)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1959:1959:1959) (1963:1963:1963)) - (PORT datab (1256:1256:1256) (1279:1279:1279)) - (PORT datac (1277:1277:1277) (1303:1303:1303)) - (PORT datad (1269:1269:1269) (1284:1284:1284)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1379:1379:1379)) - (PORT datab (230:230:230) (285:285:285)) - (PORT datac (323:323:323) (328:328:328)) - (PORT datad (1015:1015:1015) (1009:1009:1009)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1486:1486:1486) (1464:1464:1464)) - (PORT datab (211:211:211) (250:250:250)) - (PORT datac (637:637:637) (699:699:699)) - (PORT datad (546:546:546) (552:552:552)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1283:1283:1283) (1298:1298:1298)) - (PORT datab (1203:1203:1203) (1218:1218:1218)) - (PORT datac (258:258:258) (346:346:346)) - (PORT datad (268:268:268) (346:346:346)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (634:634:634)) - (PORT datab (761:761:761) (758:758:758)) - (PORT datac (811:811:811) (816:816:816)) - (PORT datad (371:371:371) (406:406:406)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -1577,513 +2821,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) (DELAY (ABSOLUTE - (PORT datab (600:600:600) (624:624:624)) - (PORT datac (750:750:750) (740:740:740)) - (PORT datad (552:552:552) (542:542:542)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datac (1278:1278:1278) (1285:1285:1285)) - (PORT datad (1491:1491:1491) (1479:1479:1479)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) - (DELAY - (ABSOLUTE - (PORT datac (881:881:881) (930:930:930)) - (PORT datad (852:852:852) (882:882:882)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (791:791:791)) - (PORT datab (1195:1195:1195) (1191:1191:1191)) - (PORT datac (787:787:787) (784:784:784)) - (PORT datad (632:632:632) (659:659:659)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datab (1003:1003:1003) (997:997:997)) - (PORT datac (492:492:492) (482:482:482)) - (PORT datad (184:184:184) (212:212:212)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT datab (1438:1438:1438) (1434:1434:1434)) - (PORT datac (889:889:889) (957:957:957)) - (PORT datad (1664:1664:1664) (1655:1655:1655)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (612:612:612)) - (PORT datab (623:623:623) (645:645:645)) - (PORT datac (553:553:553) (574:574:574)) - (PORT datad (630:630:630) (658:658:658)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1263:1263:1263) (1228:1228:1228)) - (PORT datac (817:817:817) (847:847:847)) - (PORT datad (735:735:735) (721:721:721)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (179:179:179) (211:211:211)) - (PORT datac (867:867:867) (885:885:885)) - (PORT datad (204:204:204) (232:232:232)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datac (1056:1056:1056) (1065:1065:1065)) - (PORT datad (963:963:963) (935:935:935)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (967:967:967) (956:956:956)) - (PORT datab (1657:1657:1657) (1684:1684:1684)) - (PORT datac (491:491:491) (481:481:481)) - (PORT datad (943:943:943) (905:905:905)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (878:878:878)) - (PORT datab (980:980:980) (1029:1029:1029)) - (PORT datac (1018:1018:1018) (1018:1018:1018)) - (PORT datad (1034:1034:1034) (1049:1049:1049)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1374:1374:1374)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1367:1367:1367)) - (PORT ena (1421:1421:1421) (1410:1410:1410)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) - (DELAY - (ABSOLUTE - (PORT datab (861:861:861) (893:893:893)) - (PORT datad (1423:1423:1423) (1409:1409:1409)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1485:1485:1485) (1463:1463:1463)) - (PORT datab (673:673:673) (734:734:734)) - (PORT datac (1221:1221:1221) (1206:1206:1206)) - (PORT datad (541:541:541) (550:550:550)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (2229:2229:2229) (2236:2236:2236)) - (PORT datab (2642:2642:2642) (2620:2620:2620)) - (PORT datac (1035:1035:1035) (1055:1055:1055)) - (PORT datad (995:995:995) (963:963:963)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1730:1730:1730) (1699:1699:1699)) - (PORT datab (788:788:788) (781:781:781)) - (PORT datad (1212:1212:1212) (1179:1179:1179)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT datab (1435:1435:1435) (1444:1444:1444)) - (PORT datac (1112:1112:1112) (1166:1166:1166)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1034:1034:1034)) - (PORT datab (865:865:865) (882:882:882)) - (PORT datac (1877:1877:1877) (1888:1888:1888)) - (PORT datad (1060:1060:1060) (1071:1071:1071)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datac (1682:1682:1682) (1673:1673:1673)) - (PORT datad (1526:1526:1526) (1538:1538:1538)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1985:1985:1985) (1998:1998:1998)) - (PORT datab (230:230:230) (285:285:285)) - (PORT datac (344:344:344) (380:380:380)) - (PORT datad (965:965:965) (933:933:933)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (408:408:408)) - (PORT datab (232:232:232) (287:287:287)) - (PORT datac (1957:1957:1957) (1962:1962:1962)) - (PORT datad (1420:1420:1420) (1373:1373:1373)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1184:1184:1184)) - (PORT datac (1404:1404:1404) (1411:1411:1411)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1047:1047:1047) (1027:1027:1027)) - (PORT datab (636:636:636) (659:659:659)) - (PORT datac (1096:1096:1096) (1119:1119:1119)) - (PORT datad (1310:1310:1310) (1312:1312:1312)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1152:1152:1152)) - (PORT datab (596:596:596) (613:613:613)) - (PORT datac (821:821:821) (839:839:839)) - (PORT datad (164:164:164) (189:189:189)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (712:712:712)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (569:569:569) (564:564:564)) - (PORT datad (164:164:164) (186:186:186)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (799:799:799)) - (PORT datab (1067:1067:1067) (1034:1034:1034)) - (PORT datac (980:980:980) (979:979:979)) - (PORT datad (1314:1314:1314) (1318:1318:1318)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1328:1328:1328)) - (PORT datad (875:875:875) (915:915:915)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT datac (1026:1026:1026) (1036:1036:1036)) - (PORT datad (874:874:874) (913:913:913)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1143:1143:1143) (1167:1167:1167)) - (PORT datab (1506:1506:1506) (1496:1496:1496)) - (PORT datac (504:504:504) (489:489:489)) - (PORT datad (1536:1536:1536) (1558:1558:1558)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1844:1844:1844) (1861:1861:1861)) - (PORT datab (1133:1133:1133) (1113:1113:1113)) - (PORT datac (771:771:771) (758:758:758)) - (PORT datad (774:774:774) (761:761:761)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT datab (1287:1287:1287) (1336:1336:1336)) - (PORT datac (1570:1570:1570) (1621:1621:1621)) - (PORT datad (1563:1563:1563) (1600:1600:1600)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1211:1211:1211) (1183:1183:1183)) - (PORT datab (1302:1302:1302) (1309:1309:1309)) - (PORT datac (2301:2301:2301) (2295:2295:2295)) - (PORT datad (2188:2188:2188) (2184:2184:2184)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1487:1487:1487) (1471:1471:1471)) - (PORT datab (679:679:679) (743:743:743)) - (PORT datac (762:762:762) (731:731:731)) - (PORT datad (1244:1244:1244) (1237:1237:1237)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1453:1453:1453) (1426:1426:1426)) - (PORT datab (870:870:870) (893:893:893)) - (PORT datac (1219:1219:1219) (1203:1203:1203)) - (PORT datad (762:762:762) (755:755:755)) + (PORT dataa (1041:1041:1041) (1136:1136:1136)) + (PORT datab (2035:2035:2035) (2054:2054:2054)) + (PORT datac (1230:1230:1230) (1285:1285:1285)) + (PORT datad (884:884:884) (922:922:922)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -2093,15 +2837,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) (DELAY (ABSOLUTE - (PORT dataa (847:847:847) (868:868:868)) - (PORT datab (1118:1118:1118) (1119:1119:1119)) - (PORT datac (1429:1429:1429) (1398:1398:1398)) - (PORT datad (821:821:821) (853:853:853)) + (PORT dataa (1669:1669:1669) (1692:1692:1692)) + (PORT datab (1199:1199:1199) (1213:1213:1213)) + (PORT datac (1267:1267:1267) (1246:1246:1246)) + (PORT datad (814:814:814) (797:797:797)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -2109,15 +2853,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) (DELAY (ABSOLUTE - (PORT dataa (1898:1898:1898) (1882:1882:1882)) - (PORT datab (825:825:825) (837:837:837)) - (PORT datac (1190:1190:1190) (1207:1207:1207)) - (PORT datad (1045:1045:1045) (1065:1065:1065)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT dataa (564:564:564) (562:562:562)) + (PORT datac (510:510:510) (508:508:508)) + (PORT datad (1141:1141:1141) (1159:1159:1159)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (218:218:218)) + (PORT datab (200:200:200) (232:232:232)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (793:793:793) (783:783:783)) + (PORT datad (788:788:788) (795:795:795)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) + (DELAY + (ABSOLUTE + (PORT datac (1912:1912:1912) (1952:1952:1952)) + (PORT datad (880:880:880) (918:918:918)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -2125,28 +2911,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~0) + (INSTANCE z80_\|execute_\|ctl_mRead\~36) (DELAY (ABSOLUTE - (PORT dataa (1453:1453:1453) (1424:1424:1424)) - (PORT datab (1119:1119:1119) (1123:1123:1123)) - (PORT datac (794:794:794) (814:814:814)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) + (PORT dataa (1483:1483:1483) (1600:1600:1600)) + (PORT datab (1404:1404:1404) (1443:1443:1443)) + (PORT datac (1566:1566:1566) (1623:1623:1623)) + (PORT datad (1374:1374:1374) (1455:1455:1455)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) (DELAY (ABSOLUTE - (PORT dataa (1383:1383:1383) (1375:1375:1375)) - (PORT datab (1198:1198:1198) (1199:1199:1199)) - (PORT datac (525:525:525) (547:547:547)) - (PORT datad (556:556:556) (559:559:559)) - (IOPATH dataa combout (307:307:307) (280:280:280)) + (PORT dataa (625:625:625) (655:655:655)) + (PORT datab (1379:1379:1379) (1404:1404:1404)) + (PORT datac (1050:1050:1050) (1096:1096:1096)) + (PORT datad (1279:1279:1279) (1264:1264:1264)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1976:1976:1976) (2058:2058:2058)) + (PORT datab (622:622:622) (670:670:670)) + (PORT datac (1582:1582:1582) (1588:1588:1588)) + (PORT datad (185:185:185) (212:212:212)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -2155,29 +2959,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) + (INSTANCE z80_\|execute_\|ctl_mRead\~11) (DELAY (ABSOLUTE - (PORT dataa (358:358:358) (369:369:369)) - (PORT datab (1243:1243:1243) (1231:1231:1231)) - (PORT datac (163:163:163) (196:196:196)) - (PORT datad (305:305:305) (308:308:308)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1183:1183:1183) (1233:1233:1233)) + (PORT datad (1885:1885:1885) (1995:1995:1995)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) (DELAY (ABSOLUTE - (PORT datab (913:913:913) (918:918:918)) - (PORT datac (528:528:528) (549:549:549)) - (PORT datad (1173:1173:1173) (1163:1163:1163)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (859:859:859) (885:885:885)) + (PORT datab (419:419:419) (435:435:435)) + (PORT datac (369:369:369) (398:398:398)) + (PORT datad (1436:1436:1436) (1448:1448:1448)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -2185,13 +2987,105 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) (DELAY (ABSOLUTE - (PORT dataa (1486:1486:1486) (1471:1471:1471)) - (PORT datab (214:214:214) (255:255:255)) - (PORT datac (647:647:647) (711:711:711)) - (PORT datad (541:541:541) (545:545:545)) + (PORT dataa (584:584:584) (593:593:593)) + (PORT datab (1062:1062:1062) (1073:1073:1073)) + (PORT datac (1335:1335:1335) (1345:1345:1345)) + (PORT datad (312:312:312) (324:324:324)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) + (DELAY + (ABSOLUTE + (PORT datac (1401:1401:1401) (1456:1456:1456)) + (PORT datad (1072:1072:1072) (1084:1084:1084)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1212:1212:1212)) + (PORT datab (794:794:794) (806:806:806)) + (PORT datac (1559:1559:1559) (1567:1567:1567)) + (PORT datad (244:244:244) (294:294:294)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1211:1211:1211)) + (PORT datab (419:419:419) (460:460:460)) + (PORT datac (1559:1559:1559) (1568:1568:1568)) + (PORT datad (248:248:248) (293:293:293)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1310:1310:1310)) + (PORT datab (1018:1018:1018) (1005:1005:1005)) + (PORT datac (995:995:995) (972:972:972)) + (PORT datad (868:868:868) (909:909:909)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (658:658:658)) + (PORT datab (1076:1076:1076) (1125:1125:1125)) + (PORT datac (1339:1339:1339) (1351:1351:1351)) + (PORT datad (1353:1353:1353) (1375:1375:1375)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (375:375:375)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (571:571:571) (590:590:590)) + (PORT datad (170:170:170) (198:198:198)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -2201,14 +3095,284 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) (DELAY (ABSOLUTE - (PORT dataa (367:367:367) (374:374:374)) - (PORT datab (1066:1066:1066) (1072:1072:1072)) - (PORT datac (562:562:562) (578:578:578)) - (PORT datad (781:781:781) (784:784:784)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT dataa (529:529:529) (528:528:528)) + (PORT datab (799:799:799) (782:782:782)) + (PORT datac (788:788:788) (812:812:812)) + (PORT datad (747:747:747) (739:739:739)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1062:1062:1062)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (169:169:169) (209:209:209)) + (PORT datad (164:164:164) (186:186:186)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (440:440:440)) + (PORT datab (1127:1127:1127) (1143:1143:1143)) + (PORT datac (630:630:630) (641:641:641)) + (PORT datad (1195:1195:1195) (1262:1262:1262)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) + (DELAY + (ABSOLUTE + (PORT datab (2689:2689:2689) (2747:2747:2747)) + (PORT datac (1865:1865:1865) (1891:1891:1891)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1749:1749:1749) (1741:1741:1741)) + (PORT datab (1929:1929:1929) (1999:1999:1999)) + (PORT datac (1035:1035:1035) (1006:1006:1006)) + (PORT datad (188:188:188) (215:215:215)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (1142:1142:1142) (1188:1188:1188)) + (PORT datad (578:578:578) (592:592:592)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1097:1097:1097) (1115:1115:1115)) + (PORT datab (845:845:845) (865:865:865)) + (PORT datac (1866:1866:1866) (1858:1858:1858)) + (PORT datad (1360:1360:1360) (1373:1373:1373)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) + (DELAY + (ABSOLUTE + (PORT dataa (975:975:975) (1040:1040:1040)) + (PORT datab (2198:2198:2198) (2252:2252:2252)) + (PORT datad (1951:1951:1951) (2009:2009:2009)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1369:1369:1369) (1399:1399:1399)) + (PORT datab (934:934:934) (962:962:962)) + (PORT datac (824:824:824) (840:840:840)) + (PORT datad (1077:1077:1077) (1057:1057:1057)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1337:1337:1337) (1317:1317:1317)) + (PORT datab (1045:1045:1045) (1069:1069:1069)) + (PORT datac (313:313:313) (327:327:327)) + (PORT datad (1050:1050:1050) (1046:1046:1046)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (371:371:371)) + (PORT datab (1005:1005:1005) (1005:1005:1005)) + (PORT datac (1453:1453:1453) (1473:1473:1473)) + (PORT datad (754:754:754) (748:748:748)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (1057:1057:1057) (1058:1058:1058)) + (PORT datab (1080:1080:1080) (1081:1081:1081)) + (PORT datac (784:784:784) (792:792:792)) + (PORT datad (748:748:748) (744:744:744)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1095:1095:1095) (1095:1095:1095)) + (PORT datab (247:247:247) (316:316:316)) + (PORT datac (224:224:224) (279:279:279)) + (PORT datad (230:230:230) (267:267:267)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) + (DELAY + (ABSOLUTE + (PORT datac (876:876:876) (907:907:907)) + (PORT datad (1861:1861:1861) (1900:1900:1900)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (807:807:807)) + (PORT datab (935:935:935) (964:964:964)) + (PORT datac (1128:1128:1128) (1143:1143:1143)) + (PORT datad (1076:1076:1076) (1053:1053:1053)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (232:232:232)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1095:1095:1095) (1114:1114:1114)) + (PORT datab (936:936:936) (965:965:965)) + (PORT datac (1864:1864:1864) (1858:1858:1858)) + (PORT datad (1360:1360:1360) (1376:1376:1376)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1242:1242:1242)) + (PORT datab (1088:1088:1088) (1118:1118:1118)) + (PORT datac (782:782:782) (781:781:781)) + (PORT datad (1227:1227:1227) (1301:1301:1301)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (896:896:896)) + (PORT datab (883:883:883) (907:907:907)) + (PORT datac (1114:1114:1114) (1158:1158:1158)) + (PORT datad (607:607:607) (628:628:628)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -2217,12 +3381,669 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (155:155:155) (184:184:184)) + (PORT dataa (1254:1254:1254) (1342:1342:1342)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (356:356:356) (362:362:362)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal69\~0) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (857:857:857)) + (PORT datab (1584:1584:1584) (1611:1611:1611)) + (PORT datac (1047:1047:1047) (1030:1030:1030)) + (PORT datad (605:605:605) (621:621:621)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1153:1153:1153)) + (PORT datad (1097:1097:1097) (1114:1114:1114)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (946:946:946)) + (PORT datab (1862:1862:1862) (1865:1865:1865)) + (PORT datac (1051:1051:1051) (1035:1035:1035)) + (PORT datad (602:602:602) (618:618:618)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1626:1626:1626) (1696:1696:1696)) + (PORT datab (862:862:862) (871:871:871)) + (PORT datad (197:197:197) (219:219:219)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (640:640:640)) + (PORT datab (1083:1083:1083) (1081:1081:1081)) + (PORT datac (857:857:857) (921:921:921)) + (PORT datad (843:843:843) (863:863:863)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1361:1361:1361) (1388:1388:1388)) + (PORT datab (1126:1126:1126) (1184:1184:1184)) + (PORT datac (1320:1320:1320) (1376:1376:1376)) + (PORT datad (766:766:766) (743:743:743)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~2) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (765:765:765)) + (PORT datab (785:785:785) (803:803:803)) + (PORT datad (612:612:612) (635:635:635)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1851:1851:1851) (1879:1879:1879)) + (PORT datab (1944:1944:1944) (1958:1958:1958)) + (PORT datac (513:513:513) (506:506:506)) + (PORT datad (1594:1594:1594) (1608:1608:1608)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (798:798:798)) + (PORT datab (877:877:877) (901:901:901)) + (PORT datac (160:160:160) (193:193:193)) + (PORT datad (1351:1351:1351) (1370:1370:1370)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT datac (1076:1076:1076) (1085:1085:1085)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1170:1170:1170)) + (PORT datab (912:912:912) (976:976:976)) + (PORT datac (603:603:603) (636:636:636)) + (PORT datad (1148:1148:1148) (1203:1203:1203)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) + (DELAY + (ABSOLUTE + (PORT datab (996:996:996) (1071:1071:1071)) + (PORT datac (1357:1357:1357) (1402:1402:1402)) + (PORT datad (2154:2154:2154) (2212:2212:2212)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (656:656:656)) + (PORT datab (1652:1652:1652) (1651:1651:1651)) + (PORT datac (898:898:898) (950:950:950)) + (PORT datad (1119:1119:1119) (1138:1138:1138)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (980:980:980)) + (PORT datab (1157:1157:1157) (1169:1169:1169)) + (PORT datac (1014:1014:1014) (1031:1031:1031)) + (PORT datad (168:168:168) (192:192:192)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (880:880:880)) + (PORT datab (1011:1011:1011) (1050:1050:1050)) + (PORT datac (912:912:912) (952:952:952)) + (PORT datad (1082:1082:1082) (1086:1086:1086)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (980:980:980)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (1152:1152:1152) (1191:1191:1191)) + (PORT datad (973:973:973) (1014:1014:1014)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT datab (1410:1410:1410) (1479:1479:1479)) + (PORT datac (1389:1389:1389) (1444:1444:1444)) + (PORT datad (1204:1204:1204) (1168:1168:1168)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (740:740:740)) + (PORT datab (799:799:799) (766:766:766)) + (PORT datac (1149:1149:1149) (1124:1124:1124)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1298:1298:1298) (1298:1298:1298)) + (PORT datab (1920:1920:1920) (1910:1910:1910)) + (PORT datac (776:776:776) (769:769:769)) + (PORT datad (734:734:734) (710:710:710)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal48\~0) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (857:857:857)) + (PORT datab (1584:1584:1584) (1610:1610:1610)) + (PORT datac (1047:1047:1047) (1029:1029:1029)) + (PORT datad (606:606:606) (621:621:621)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (892:892:892)) + (PORT datab (833:833:833) (876:876:876)) + (PORT datac (874:874:874) (902:902:902)) + (PORT datad (1198:1198:1198) (1213:1213:1213)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1212:1212:1212)) + (PORT datab (910:910:910) (938:938:938)) + (PORT datac (187:187:187) (223:223:223)) + (PORT datad (1100:1100:1100) (1133:1133:1133)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1710:1710:1710) (1758:1758:1758)) + (PORT datab (1197:1197:1197) (1242:1242:1242)) + (PORT datac (1863:1863:1863) (1898:1898:1898)) + (PORT datad (776:776:776) (751:751:751)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1130:1130:1130)) + (PORT datab (935:935:935) (959:959:959)) + (PORT datac (573:573:573) (592:592:592)) + (PORT datad (1081:1081:1081) (1058:1058:1058)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (829:829:829)) + (PORT datab (980:980:980) (1012:1012:1012)) + (PORT datac (534:534:534) (541:541:541)) + (PORT datad (1010:1010:1010) (990:990:990)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1486:1486:1486) (1597:1597:1597)) + (PORT datab (1406:1406:1406) (1486:1486:1486)) + (PORT datac (1570:1570:1570) (1623:1623:1623)) + (PORT datad (1338:1338:1338) (1358:1358:1358)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1559:1559:1559) (1557:1557:1557)) + (PORT datab (1417:1417:1417) (1466:1466:1466)) + (PORT datac (875:875:875) (902:902:902)) + (PORT datad (1069:1069:1069) (1109:1109:1109)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (564:564:564)) + (PORT datab (861:861:861) (862:862:862)) + (PORT datac (878:878:878) (906:906:906)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1553:1553:1553)) + (PORT datab (986:986:986) (1053:1053:1053)) + (PORT datac (1675:1675:1675) (1745:1745:1745)) + (PORT datad (871:871:871) (912:912:912)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1145:1145:1145) (1159:1159:1159)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (889:889:889) (916:916:916)) + (PORT datad (840:840:840) (871:871:871)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1268:1268:1268)) + (PORT datab (907:907:907) (938:938:938)) + (PORT datac (544:544:544) (545:545:545)) + (PORT datad (586:586:586) (604:604:604)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1846:1846:1846) (1909:1909:1909)) + (PORT datab (1409:1409:1409) (1459:1459:1459)) + (PORT datac (201:201:201) (245:245:245)) + (PORT datad (1019:1019:1019) (1030:1030:1030)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1485:1485:1485) (1596:1596:1596)) + (PORT datab (1407:1407:1407) (1486:1486:1486)) + (PORT datac (1569:1569:1569) (1622:1622:1622)) + (PORT datad (1338:1338:1338) (1358:1358:1358)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (890:890:890)) + (PORT datab (1324:1324:1324) (1342:1342:1342)) + (PORT datac (1230:1230:1230) (1288:1288:1288)) + (PORT datad (1439:1439:1439) (1489:1489:1489)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (643:643:643)) + (PORT datab (1512:1512:1512) (1464:1464:1464)) + (PORT datac (1211:1211:1211) (1179:1179:1179)) + (PORT datad (1329:1329:1329) (1380:1380:1380)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1527:1527:1527)) + (PORT datab (1258:1258:1258) (1314:1314:1314)) + (PORT datac (1072:1072:1072) (1074:1074:1074)) + (PORT datad (764:764:764) (745:745:745)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (652:652:652)) + (PORT datab (917:917:917) (953:953:953)) + (PORT datac (993:993:993) (1090:1090:1090)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) + (DELAY + (ABSOLUTE + (PORT dataa (2092:2092:2092) (2170:2170:2170)) + (PORT datab (780:780:780) (796:796:796)) + (PORT datac (1947:1947:1947) (1965:1965:1965)) + (PORT datad (609:609:609) (634:634:634)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (891:891:891)) + (PORT datab (910:910:910) (942:942:942)) + (PORT datac (1321:1321:1321) (1340:1340:1340)) + (PORT datad (1414:1414:1414) (1436:1436:1436)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (611:611:611)) + (PORT datab (412:412:412) (427:427:427)) + (PORT datac (181:181:181) (215:215:215)) + (PORT datad (1303:1303:1303) (1297:1297:1297)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (580:580:580)) + (PORT datab (907:907:907) (935:935:935)) + (PORT datac (817:817:817) (816:816:816)) + (PORT datad (754:754:754) (757:757:757)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (352:352:352)) + (PORT datab (307:307:307) (325:325:325)) + (PORT datac (154:154:154) (184:184:184)) (PORT datad (159:159:159) (179:179:179)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) @@ -2231,15 +4052,6031 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (206:206:206) (245:245:245)) + (PORT datac (181:181:181) (216:216:216)) + (PORT datad (184:184:184) (209:209:209)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (584:584:584)) + (PORT datab (1311:1311:1311) (1349:1349:1349)) + (PORT datac (579:579:579) (584:584:584)) + (PORT datad (1507:1507:1507) (1522:1522:1522)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (631:631:631)) + (PORT datab (917:917:917) (951:951:951)) + (PORT datac (993:993:993) (1088:1088:1088)) + (PORT datad (2123:2123:2123) (2118:2118:2118)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (890:890:890)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (320:320:320) (331:331:331)) + (PORT datad (2124:2124:2124) (2121:2121:2121)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~4) + (DELAY + (ABSOLUTE + (PORT datab (976:976:976) (1054:1054:1054)) + (PORT datac (1345:1345:1345) (1372:1372:1372)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1309:1309:1309)) + (PORT datab (882:882:882) (907:907:907)) + (PORT datac (958:958:958) (1025:1025:1025)) + (PORT datad (1298:1298:1298) (1305:1305:1305)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (934:934:934)) + (PORT datab (1321:1321:1321) (1331:1331:1331)) + (PORT datac (889:889:889) (919:919:919)) + (PORT datad (178:178:178) (201:201:201)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1038:1038:1038) (1018:1018:1018)) + (PORT datab (1093:1093:1093) (1100:1100:1100)) + (PORT datac (609:609:609) (638:638:638)) + (PORT datad (810:810:810) (832:832:832)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (555:555:555)) + (PORT datac (539:539:539) (529:529:529)) + (PORT datad (491:491:491) (485:485:485)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (275:275:275)) + (PORT datab (1147:1147:1147) (1139:1139:1139)) + (PORT datac (1072:1072:1072) (1085:1085:1085)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (838:838:838)) + (PORT datab (791:791:791) (782:782:782)) + (PORT datac (320:320:320) (326:326:326)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1843:1843:1843) (1913:1913:1913)) + (PORT datab (830:830:830) (855:855:855)) + (PORT datac (198:198:198) (243:243:243)) + (PORT datad (1301:1301:1301) (1303:1303:1303)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT dataa (1673:1673:1673) (1743:1743:1743)) + (PORT datab (1490:1490:1490) (1552:1552:1552)) + (PORT datad (1304:1304:1304) (1336:1336:1336)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1897:1897:1897) (1897:1897:1897)) + (PORT datab (869:869:869) (915:915:915)) + (PORT datac (1005:1005:1005) (1022:1022:1022)) + (PORT datad (848:848:848) (890:890:890)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1248:1248:1248) (1215:1215:1215)) + (PORT datab (1074:1074:1074) (1125:1125:1125)) + (PORT datac (1366:1366:1366) (1365:1365:1365)) + (PORT datad (1353:1353:1353) (1375:1375:1375)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (1068:1068:1068) (1064:1064:1064)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (780:780:780) (768:768:768)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT datab (888:888:888) (913:913:913)) + (PORT datac (547:547:547) (540:540:540)) + (PORT datad (628:628:628) (648:648:648)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT datac (858:858:858) (882:882:882)) + (PORT datad (633:633:633) (656:656:656)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (959:959:959)) + (PORT datab (655:655:655) (689:689:689)) + (PORT datac (837:837:837) (839:839:839)) + (PORT datad (1600:1600:1600) (1674:1674:1674)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1376:1376:1376) (1454:1454:1454)) + (PORT datab (1348:1348:1348) (1415:1415:1415)) + (PORT datac (1702:1702:1702) (1704:1704:1704)) + (PORT datad (376:376:376) (398:398:398)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1166:1166:1166)) + (PORT datac (873:873:873) (903:903:903)) + (PORT datad (1115:1115:1115) (1158:1158:1158)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1128:1128:1128) (1145:1145:1145)) + (PORT datab (1319:1319:1319) (1327:1327:1327)) + (PORT datac (1020:1020:1020) (994:994:994)) + (PORT datad (1237:1237:1237) (1210:1210:1210)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) + (DELAY + (ABSOLUTE + (PORT datab (864:864:864) (860:860:860)) + (PORT datac (496:496:496) (486:486:486)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (958:958:958)) + (PORT datab (655:655:655) (689:689:689)) + (PORT datac (835:835:835) (838:838:838)) + (PORT datad (1599:1599:1599) (1672:1672:1672)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1256:1256:1256) (1253:1253:1253)) + (PORT datab (843:843:843) (852:852:852)) + (PORT datad (569:569:569) (580:580:580)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (816:816:816)) + (PORT datab (1350:1350:1350) (1391:1391:1391)) + (PORT datac (1212:1212:1212) (1289:1289:1289)) + (PORT datad (2057:2057:2057) (2079:2079:2079)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~36) + (DELAY + (ABSOLUTE + (PORT dataa (2171:2171:2171) (2222:2222:2222)) + (PORT datab (828:828:828) (853:853:853)) + (PORT datac (345:345:345) (360:360:360)) + (PORT datad (1356:1356:1356) (1393:1393:1393)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (234:234:234)) + (PORT datab (215:215:215) (256:256:256)) + (PORT datac (780:780:780) (771:771:771)) + (PORT datad (525:525:525) (507:507:507)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (DELAY + (ABSOLUTE + (PORT datac (2248:2248:2248) (2394:2394:2394)) + (PORT datad (1842:1842:1842) (1860:1860:1860)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1349:1349:1349) (1371:1371:1371)) + (PORT datab (775:775:775) (797:797:797)) + (PORT datac (849:849:849) (884:884:884)) + (PORT datad (606:606:606) (629:629:629)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1321:1321:1321) (1320:1320:1320)) + (PORT datab (1246:1246:1246) (1217:1217:1217)) + (PORT datac (792:792:792) (789:789:789)) + (PORT datad (754:754:754) (719:719:719)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1015:1015:1015) (999:999:999)) + (PORT datab (2388:2388:2388) (2382:2382:2382)) + (PORT datac (1421:1421:1421) (1511:1511:1511)) + (PORT datad (1582:1582:1582) (1635:1635:1635)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) + (DELAY + (ABSOLUTE + (PORT datac (187:187:187) (225:225:225)) + (PORT datad (190:190:190) (216:216:216)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1147:1147:1147)) + (PORT datab (1182:1182:1182) (1237:1237:1237)) + (PORT datac (1617:1617:1617) (1628:1628:1628)) + (PORT datad (783:783:783) (768:768:768)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (378:378:378)) + (PORT datab (376:376:376) (377:377:377)) + (PORT datac (346:346:346) (350:350:350)) + (PORT datad (183:183:183) (220:220:220)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1369:1369:1369) (1400:1400:1400)) + (PORT datab (1173:1173:1173) (1231:1231:1231)) + (PORT datac (824:824:824) (841:841:841)) + (PORT datad (1076:1076:1076) (1060:1060:1060)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (676:676:676)) + (PORT datab (2586:2586:2586) (2576:2576:2576)) + (PORT datac (1203:1203:1203) (1279:1279:1279)) + (PORT datad (528:528:528) (521:521:521)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (813:813:813)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (175:175:175) (215:215:215)) + (PORT datad (167:167:167) (193:193:193)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (619:619:619)) + (PORT datab (199:199:199) (233:233:233)) + (PORT datac (539:539:539) (532:532:532)) + (PORT datad (1313:1313:1313) (1331:1331:1331)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1275:1275:1275) (1269:1269:1269)) + (PORT datab (1702:1702:1702) (1643:1643:1643)) + (PORT datac (1043:1043:1043) (1045:1045:1045)) + (PORT datad (1615:1615:1615) (1615:1615:1615)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1738:1738:1738) (1736:1736:1736)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (1052:1052:1052) (1081:1081:1081)) + (PORT datad (560:560:560) (567:567:567)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (586:586:586)) + (PORT datab (958:958:958) (1002:1002:1002)) + (PORT datac (817:817:817) (816:816:816)) + (PORT datad (1479:1479:1479) (1546:1546:1546)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (336:336:336) (355:355:355)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (966:966:966) (920:920:920)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1322:1322:1322) (1335:1335:1335)) + (PORT datab (1318:1318:1318) (1333:1333:1333)) + (PORT datac (568:568:568) (566:566:566)) + (PORT datad (838:838:838) (870:870:870)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1510:1510:1510) (1554:1554:1554)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (1675:1675:1675) (1745:1745:1745)) + (PORT datad (845:845:845) (877:877:877)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1322:1322:1322) (1335:1335:1335)) + (PORT datab (1317:1317:1317) (1334:1334:1334)) + (PORT datac (961:961:961) (1026:1026:1026)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1666:1666:1666) (1679:1679:1679)) + (PORT datab (310:310:310) (325:325:325)) + (PORT datac (958:958:958) (1026:1026:1026)) + (PORT datad (1099:1099:1099) (1115:1115:1115)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1309:1309:1309)) + (PORT datab (1319:1319:1319) (1327:1327:1327)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (867:867:867) (906:906:906)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (908:908:908) (942:942:942)) + (PORT datac (997:997:997) (973:973:973)) + (PORT datad (1098:1098:1098) (1114:1114:1114)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (294:294:294)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1816:1816:1816) (1865:1865:1865)) + (PORT datab (1699:1699:1699) (1638:1638:1638)) + (PORT datac (1040:1040:1040) (1043:1043:1043)) + (PORT datad (1843:1843:1843) (1917:1917:1917)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (361:361:361)) + (PORT datab (1699:1699:1699) (1639:1639:1639)) + (PORT datac (1465:1465:1465) (1441:1441:1441)) + (PORT datad (169:169:169) (199:199:199)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (612:612:612)) + (PORT datab (919:919:919) (961:961:961)) + (PORT datac (1200:1200:1200) (1207:1207:1207)) + (PORT datad (743:743:743) (733:733:733)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (599:599:599)) + (PORT datac (980:980:980) (963:963:963)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (934:934:934)) + (PORT datab (1320:1320:1320) (1328:1328:1328)) + (PORT datac (892:892:892) (915:915:915)) + (PORT datad (1102:1102:1102) (1119:1119:1119)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (366:366:366)) + (PORT datab (194:194:194) (232:232:232)) + (PORT datac (331:331:331) (342:342:342)) + (PORT datad (324:324:324) (326:326:326)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT datab (598:598:598) (600:600:600)) + (PORT datac (802:802:802) (819:819:819)) + (PORT datad (166:166:166) (189:189:189)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (547:547:547)) + (PORT datab (825:825:825) (812:812:812)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (760:760:760)) + (PORT datab (634:634:634) (663:663:663)) + (PORT datac (850:850:850) (886:886:886)) + (PORT datad (751:751:751) (757:757:757)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datab (805:805:805) (798:798:798)) + (PORT datad (757:757:757) (738:738:738)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT datab (195:195:195) (234:234:234)) + (PORT datac (332:332:332) (342:342:342)) + (PORT datad (324:324:324) (326:326:326)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1555:1555:1555)) + (PORT datab (1686:1686:1686) (1724:1724:1724)) + (PORT datac (1674:1674:1674) (1748:1748:1748)) + (PORT datad (873:873:873) (896:896:896)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1322:1322:1322) (1336:1336:1336)) + (PORT datab (1319:1319:1319) (1328:1328:1328)) + (PORT datac (892:892:892) (920:920:920)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1667:1667:1667) (1681:1681:1681)) + (PORT datab (918:918:918) (948:948:948)) + (PORT datac (297:297:297) (304:304:304)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (616:616:616)) + (PORT datab (559:559:559) (561:561:561)) + (PORT datac (762:762:762) (744:744:744)) + (PORT datad (314:314:314) (313:313:313)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (218:218:218)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1188:1188:1188) (1198:1198:1198)) + (PORT datab (909:909:909) (990:990:990)) + (PORT datac (993:993:993) (1063:1063:1063)) + (PORT datad (891:891:891) (962:962:962)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1358:1358:1358) (1324:1324:1324)) + (PORT datab (1281:1281:1281) (1252:1252:1252)) + (PORT datac (1502:1502:1502) (1479:1479:1479)) + (PORT datad (1157:1157:1157) (1199:1199:1199)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1120:1120:1120) (1110:1110:1110)) + (PORT datab (966:966:966) (1033:1033:1033)) + (PORT datad (1249:1249:1249) (1347:1347:1347)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (656:656:656)) + (PORT datab (922:922:922) (918:918:918)) + (PORT datac (517:517:517) (502:502:502)) + (PORT datad (202:202:202) (225:225:225)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (715:715:715)) + (PORT datab (871:871:871) (917:917:917)) + (PORT datac (1005:1005:1005) (1023:1023:1023)) + (PORT datad (843:843:843) (885:885:885)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1172:1172:1172)) + (PORT datab (203:203:203) (245:245:245)) + (PORT datac (2166:2166:2166) (2200:2200:2200)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT datab (1924:1924:1924) (1977:1977:1977)) + (PORT datac (1577:1577:1577) (1617:1617:1617)) + (PORT datad (1064:1064:1064) (1115:1115:1115)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1336:1336:1336) (1342:1342:1342)) + (PORT datab (1328:1328:1328) (1302:1302:1302)) + (PORT datac (772:772:772) (771:771:771)) + (PORT datad (364:364:364) (378:378:378)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (804:804:804)) + (PORT datab (1094:1094:1094) (1088:1088:1088)) + (PORT datac (908:908:908) (931:931:931)) + (PORT datad (900:900:900) (934:934:934)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1847:1847:1847) (1918:1918:1918)) + (PORT datab (415:415:415) (432:432:432)) + (PORT datac (920:920:920) (954:954:954)) + (PORT datad (834:834:834) (846:846:846)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~1) + (DELAY + (ABSOLUTE + (PORT datac (1462:1462:1462) (1567:1567:1567)) + (PORT datad (1383:1383:1383) (1455:1455:1455)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (927:927:927)) + (PORT datab (1103:1103:1103) (1088:1088:1088)) + (PORT datac (1796:1796:1796) (1829:1829:1829)) + (PORT datad (596:596:596) (615:615:615)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (573:573:573) (590:590:590)) + (PORT datac (1558:1558:1558) (1610:1610:1610)) + (PORT datad (578:578:578) (592:592:592)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1386:1386:1386) (1425:1425:1425)) + (PORT datab (329:329:329) (353:353:353)) + (PORT datac (1936:1936:1936) (1950:1950:1950)) + (PORT datad (552:552:552) (533:533:533)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (715:715:715)) + (PORT datab (870:870:870) (912:912:912)) + (PORT datac (1004:1004:1004) (1021:1021:1021)) + (PORT datad (845:845:845) (889:889:889)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1390:1390:1390)) + (PORT datab (1129:1129:1129) (1189:1189:1189)) + (PORT datac (1349:1349:1349) (1357:1357:1357)) + (PORT datad (1052:1052:1052) (1047:1047:1047)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1699:1699:1699) (1727:1727:1727)) + (PORT datab (1918:1918:1918) (1966:1966:1966)) + (PORT datac (1236:1236:1236) (1200:1200:1200)) + (PORT datad (1859:1859:1859) (1904:1904:1904)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1032:1032:1032) (1089:1089:1089)) + (PORT datab (602:602:602) (604:604:604)) + (PORT datac (1124:1124:1124) (1159:1159:1159)) + (PORT datad (553:553:553) (559:559:559)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1048:1048:1048) (1038:1038:1038)) + (PORT datab (786:786:786) (772:772:772)) + (PORT datad (534:534:534) (525:525:525)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) + (DELAY + (ABSOLUTE + (PORT datac (1624:1624:1624) (1672:1672:1672)) + (PORT datad (1455:1455:1455) (1524:1524:1524)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (967:967:967)) + (PORT datab (959:959:959) (994:994:994)) + (PORT datac (978:978:978) (1009:1009:1009)) + (PORT datad (585:585:585) (593:593:593)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1467:1467:1467) (1544:1544:1544)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (978:978:978) (1009:1009:1009)) + (PORT datad (1658:1658:1658) (1738:1738:1738)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1132:1132:1132)) + (PORT datab (639:639:639) (634:634:634)) + (PORT datac (1175:1175:1175) (1251:1251:1251)) + (PORT datad (1462:1462:1462) (1539:1539:1539)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (239:239:239)) + (PORT datab (194:194:194) (234:234:234)) + (PORT datac (1174:1174:1174) (1251:1251:1251)) + (PORT datad (1465:1465:1465) (1543:1543:1543)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1133:1133:1133)) + (PORT datab (1529:1529:1529) (1476:1476:1476)) + (PORT datac (729:729:729) (713:713:713)) + (PORT datad (541:541:541) (543:543:543)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (597:597:597)) + (PORT datab (610:610:610) (626:626:626)) + (PORT datac (627:627:627) (658:658:658)) + (PORT datad (740:740:740) (792:792:792)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (963:963:963)) + (PORT datab (1558:1558:1558) (1560:1560:1560)) + (PORT datac (1455:1455:1455) (1513:1513:1513)) + (PORT datad (889:889:889) (912:912:912)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1204:1204:1204)) + (PORT datab (854:854:854) (864:864:864)) + (PORT datac (905:905:905) (931:931:931)) + (PORT datad (1082:1082:1082) (1058:1058:1058)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (351:351:351)) + (PORT datab (1367:1367:1367) (1350:1350:1350)) + (PORT datac (995:995:995) (995:995:995)) + (PORT datad (1254:1254:1254) (1233:1233:1233)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (353:353:353)) + (PORT datab (216:216:216) (250:250:250)) + (PORT datac (969:969:969) (989:989:989)) + (PORT datad (1280:1280:1280) (1284:1284:1284)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (806:806:806)) + (PORT datab (342:342:342) (353:353:353)) + (PORT datac (605:605:605) (626:626:626)) + (PORT datad (771:771:771) (793:793:793)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (727:727:727)) + (PORT datab (863:863:863) (905:905:905)) + (PORT datac (889:889:889) (926:926:926)) + (PORT datad (176:176:176) (197:197:197)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1343:1343:1343) (1389:1389:1389)) + (PORT datab (571:571:571) (573:573:573)) + (PORT datac (1107:1107:1107) (1146:1146:1146)) + (PORT datad (778:778:778) (761:761:761)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (249:249:249)) + (PORT datab (190:190:190) (226:226:226)) + (PORT datac (548:548:548) (534:534:534)) + (PORT datad (797:797:797) (784:784:784)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1118:1118:1118)) + (PORT datab (888:888:888) (925:925:925)) + (PORT datac (963:963:963) (1020:1020:1020)) + (PORT datad (1328:1328:1328) (1332:1332:1332)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1052:1052:1052)) + (PORT datab (893:893:893) (931:931:931)) + (PORT datac (292:292:292) (301:301:301)) + (PORT datad (588:588:588) (597:597:597)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (981:981:981)) + (PORT datab (1278:1278:1278) (1267:1267:1267)) + (PORT datac (1084:1084:1084) (1086:1086:1086)) + (PORT datad (1118:1118:1118) (1133:1133:1133)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datab (1155:1155:1155) (1173:1173:1173)) + (PORT datac (894:894:894) (943:943:943)) + (PORT datad (585:585:585) (594:594:594)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (809:809:809)) + (PORT datab (1331:1331:1331) (1306:1306:1306)) + (PORT datac (1553:1553:1553) (1554:1554:1554)) + (PORT datad (1898:1898:1898) (1969:1969:1969)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (574:574:574)) + (PORT datab (189:189:189) (226:226:226)) + (PORT datac (1291:1291:1291) (1332:1332:1332)) + (PORT datad (1314:1314:1314) (1311:1311:1311)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1677:1677:1677) (1730:1730:1730)) + (PORT datab (780:780:780) (772:772:772)) + (PORT datac (774:774:774) (776:776:776)) + (PORT datad (1897:1897:1897) (1970:1970:1970)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (775:775:775) (754:754:754)) + (PORT datab (731:731:731) (724:724:724)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (339:339:339)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (506:506:506) (496:496:496)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (899:899:899)) + (PORT datab (807:807:807) (798:798:798)) + (PORT datac (1556:1556:1556) (1622:1622:1622)) + (PORT datad (1087:1087:1087) (1096:1096:1096)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1205:1205:1205)) + (PORT datab (1072:1072:1072) (1087:1087:1087)) + (PORT datac (1037:1037:1037) (1010:1010:1010)) + (PORT datad (620:620:620) (635:635:635)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1124:1124:1124)) + (PORT datac (549:549:549) (548:548:548)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (1119:1119:1119)) + (PORT datab (603:603:603) (603:603:603)) + (PORT datac (174:174:174) (223:223:223)) + (PORT datad (571:571:571) (570:570:570)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (248:248:248)) + (PORT datac (1939:1939:1939) (1948:1948:1948)) + (PORT datad (1345:1345:1345) (1382:1382:1382)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (411:411:411)) + (PORT datab (1066:1066:1066) (1075:1075:1075)) + (PORT datac (1350:1350:1350) (1358:1358:1358)) + (PORT datad (1016:1016:1016) (1032:1032:1032)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1047:1047:1047)) + (PORT datab (960:960:960) (1002:1002:1002)) + (PORT datac (1084:1084:1084) (1085:1085:1085)) + (PORT datad (1118:1118:1118) (1133:1133:1133)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (817:817:817)) + (PORT datab (606:606:606) (624:624:624)) + (PORT datac (1030:1030:1030) (994:994:994)) + (PORT datad (723:723:723) (705:705:705)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1040:1040:1040) (1029:1029:1029)) + (PORT datab (1420:1420:1420) (1483:1483:1483)) + (PORT datac (568:568:568) (595:595:595)) + (PORT datad (165:165:165) (190:190:190)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (703:703:703)) + (PORT datab (781:781:781) (795:795:795)) + (PORT datac (733:733:733) (731:731:731)) + (PORT datad (610:610:610) (634:634:634)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (981:981:981)) + (PORT datab (892:892:892) (930:930:930)) + (PORT datac (173:173:173) (203:203:203)) + (PORT datad (1328:1328:1328) (1329:1329:1329)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1192:1192:1192) (1254:1254:1254)) + (PORT datab (891:891:891) (929:929:929)) + (PORT datac (965:965:965) (1018:1018:1018)) + (PORT datad (1442:1442:1442) (1506:1506:1506)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1191:1191:1191) (1254:1254:1254)) + (PORT datab (1156:1156:1156) (1167:1167:1167)) + (PORT datac (894:894:894) (945:945:945)) + (PORT datad (1443:1443:1443) (1507:1507:1507)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datac (161:161:161) (196:196:196)) + (PORT datad (165:165:165) (191:191:191)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (517:517:517)) + (PORT datab (217:217:217) (259:259:259)) + (PORT datac (503:503:503) (491:491:491)) + (PORT datad (1341:1341:1341) (1348:1348:1348)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (1285:1285:1285) (1264:1264:1264)) + (PORT datac (533:533:533) (527:527:527)) + (PORT datad (559:559:559) (564:564:564)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (656:656:656)) + (PORT datab (1042:1042:1042) (1050:1050:1050)) + (PORT datac (894:894:894) (891:891:891)) + (PORT datad (1079:1079:1079) (1090:1090:1090)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (896:896:896)) + (PORT datab (883:883:883) (906:906:906)) + (PORT datac (1114:1114:1114) (1159:1159:1159)) + (PORT datad (355:355:355) (359:359:359)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1638:1638:1638) (1596:1596:1596)) + (PORT datab (1504:1504:1504) (1511:1511:1511)) + (PORT datac (1208:1208:1208) (1288:1288:1288)) + (PORT datad (1428:1428:1428) (1521:1521:1521)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1032:1032:1032) (1036:1036:1036)) + (PORT datab (970:970:970) (989:989:989)) + (PORT datac (876:876:876) (885:885:885)) + (PORT datad (764:764:764) (753:753:753)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (917:917:917)) + (PORT datab (644:644:644) (656:656:656)) + (PORT datac (191:191:191) (236:236:236)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (790:790:790)) + (PORT datab (602:602:602) (612:612:612)) + (PORT datac (814:814:814) (813:813:813)) + (PORT datad (759:759:759) (751:751:751)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (329:329:329) (355:355:355)) + (PORT datac (899:899:899) (931:931:931)) + (PORT datad (552:552:552) (532:532:532)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (239:239:239)) + (PORT datac (1584:1584:1584) (1557:1557:1557)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (268:268:268)) + (PORT datab (1098:1098:1098) (1106:1106:1106)) + (PORT datac (1117:1117:1117) (1107:1107:1107)) + (PORT datad (521:521:521) (507:507:507)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1031:1031:1031) (1039:1039:1039)) + (PORT datab (220:220:220) (265:265:265)) + (PORT datac (835:835:835) (838:838:838)) + (PORT datad (1812:1812:1812) (1811:1811:1811)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (768:768:768) (752:752:752)) + (PORT datab (804:804:804) (790:790:790)) + (PORT datac (554:554:554) (548:548:548)) + (PORT datad (758:758:758) (736:736:736)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1996:1996:1996) (2051:2051:2051)) + (PORT datab (1617:1617:1617) (1676:1676:1676)) + (PORT datac (813:813:813) (805:805:805)) + (PORT datad (2159:2159:2159) (2213:2213:2213)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (933:933:933)) + (PORT datab (1942:1942:1942) (1959:1959:1959)) + (PORT datac (513:513:513) (510:510:510)) + (PORT datad (1825:1825:1825) (1841:1841:1841)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1648:1648:1648) (1706:1706:1706)) + (PORT datab (988:988:988) (1054:1054:1054)) + (PORT datac (889:889:889) (915:915:915)) + (PORT datad (1891:1891:1891) (1927:1927:1927)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1041:1041:1041) (1131:1131:1131)) + (PORT datab (1090:1090:1090) (1095:1095:1095)) + (PORT datac (564:564:564) (560:560:560)) + (PORT datad (2123:2123:2123) (2121:2121:2121)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (928:928:928)) + (PORT datab (1059:1059:1059) (1039:1039:1039)) + (PORT datac (321:321:321) (343:343:343)) + (PORT datad (576:576:576) (601:601:601)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (815:815:815)) + (PORT datac (775:775:775) (771:771:771)) + (PORT datad (485:485:485) (478:478:478)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (260:260:260)) + (PORT datab (223:223:223) (267:267:267)) + (PORT datac (1819:1819:1819) (1877:1877:1877)) + (PORT datad (184:184:184) (214:214:214)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1338:1338:1338)) + (PORT datab (1252:1252:1252) (1227:1227:1227)) + (PORT datac (806:806:806) (800:800:800)) + (PORT datad (1348:1348:1348) (1350:1350:1350)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (1092:1092:1092)) + (PORT datab (627:627:627) (671:671:671)) + (PORT datac (883:883:883) (964:964:964)) + (PORT datad (568:568:568) (558:558:558)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (597:597:597)) + (PORT datab (890:890:890) (953:953:953)) + (PORT datac (1596:1596:1596) (1638:1638:1638)) + (PORT datad (1056:1056:1056) (1043:1043:1043)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1834:1834:1834) (1832:1832:1832)) + (PORT datab (811:811:811) (805:805:805)) + (PORT datac (1249:1249:1249) (1292:1292:1292)) + (PORT datad (1251:1251:1251) (1268:1268:1268)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (584:584:584)) + (PORT datab (977:977:977) (1008:1008:1008)) + (PORT datac (186:186:186) (223:223:223)) + (PORT datad (810:810:810) (824:824:824)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (571:571:571)) + (PORT datab (184:184:184) (221:221:221)) + (PORT datac (804:804:804) (814:814:814)) + (PORT datad (797:797:797) (788:788:788)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1600:1600:1600) (1606:1606:1606)) + (PORT datab (979:979:979) (1057:1057:1057)) + (PORT datac (1109:1109:1109) (1153:1153:1153)) + (PORT datad (803:803:803) (799:799:799)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (657:657:657)) + (PORT datab (1074:1074:1074) (1122:1122:1122)) + (PORT datac (1365:1365:1365) (1362:1362:1362)) + (PORT datad (1355:1355:1355) (1371:1371:1371)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (797:797:797)) + (PORT datab (1287:1287:1287) (1268:1268:1268)) + (PORT datac (730:730:730) (706:706:706)) + (PORT datad (1594:1594:1594) (1604:1604:1604)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (1293:1293:1293) (1323:1323:1323)) + (PORT datab (2166:2166:2166) (2220:2220:2220)) + (PORT datac (1040:1040:1040) (1047:1047:1047)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (905:905:905)) + (PORT datab (946:946:946) (963:963:963)) + (PORT datac (163:163:163) (199:199:199)) + (PORT datad (592:592:592) (606:606:606)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (567:567:567)) + (PORT datab (622:622:622) (640:640:640)) + (PORT datac (474:474:474) (464:464:464)) + (PORT datad (780:780:780) (784:784:784)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (820:820:820) (834:834:834)) + (PORT datac (817:817:817) (831:831:831)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT dataa (2000:2000:2000) (2094:2094:2094)) + (PORT datac (1337:1337:1337) (1366:1366:1366)) + (PORT datad (2090:2090:2090) (2151:2151:2151)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (DELAY + (ABSOLUTE + (PORT datab (855:855:855) (898:898:898)) + (PORT datac (1428:1428:1428) (1488:1488:1488)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (663:663:663)) + (PORT datab (804:804:804) (798:798:798)) + (PORT datac (1185:1185:1185) (1244:1244:1244)) + (PORT datad (830:830:830) (837:837:837)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1371:1371:1371) (1382:1382:1382)) + (PORT datab (186:186:186) (221:221:221)) + (PORT datac (915:915:915) (939:939:939)) + (PORT datad (943:943:943) (974:974:974)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (257:257:257)) + (PORT datab (348:348:348) (358:358:358)) + (PORT datac (557:557:557) (574:574:574)) + (PORT datad (182:182:182) (214:214:214)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1490:1490:1490) (1599:1599:1599)) + (PORT datab (1414:1414:1414) (1492:1492:1492)) + (PORT datac (1571:1571:1571) (1623:1623:1623)) + (PORT datad (1336:1336:1336) (1357:1357:1357)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1639:1639:1639) (1647:1647:1647)) + (PORT datab (618:618:618) (642:642:642)) + (PORT datac (515:515:515) (508:508:508)) + (PORT datad (1048:1048:1048) (1051:1051:1051)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (671:671:671)) + (PORT datab (921:921:921) (982:982:982)) + (PORT datac (174:174:174) (205:205:205)) + (PORT datad (1151:1151:1151) (1208:1208:1208)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (562:562:562)) + (PORT datab (813:813:813) (811:811:811)) + (PORT datac (314:314:314) (324:324:324)) + (PORT datad (635:635:635) (668:668:668)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (630:630:630)) + (PORT datab (875:875:875) (898:898:898)) + (PORT datac (542:542:542) (538:538:538)) + (PORT datad (593:593:593) (607:607:607)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1038:1038:1038)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (537:537:537) (532:532:532)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (453:453:453)) + (PORT datab (1209:1209:1209) (1252:1252:1252)) + (PORT datac (633:633:633) (694:694:694)) + (PORT datad (1201:1201:1201) (1265:1265:1265)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1460:1460:1460) (1479:1479:1479)) + (PORT datab (843:843:843) (847:847:847)) + (PORT datac (1162:1162:1162) (1169:1169:1169)) + (PORT datad (1542:1542:1542) (1536:1536:1536)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (355:355:355)) + (PORT datab (201:201:201) (236:236:236)) + (PORT datac (595:595:595) (637:637:637)) + (PORT datad (1543:1543:1543) (1538:1538:1538)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1240:1240:1240)) + (PORT datab (1096:1096:1096) (1120:1120:1120)) + (PORT datac (1060:1060:1060) (1088:1088:1088)) + (PORT datad (1228:1228:1228) (1299:1299:1299)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (838:838:838)) + (PORT datab (357:357:357) (362:362:362)) + (PORT datac (595:595:595) (625:625:625)) + (PORT datad (1112:1112:1112) (1131:1131:1131)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (1036:1036:1036) (1010:1010:1010)) + (PORT datab (840:840:840) (845:845:845)) + (PORT datac (938:938:938) (942:942:942)) + (PORT datad (844:844:844) (850:850:850)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (226:226:226)) + (PORT datab (882:882:882) (943:943:943)) + (PORT datac (788:788:788) (775:775:775)) + (PORT datad (845:845:845) (863:863:863)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (960:960:960)) + (PORT datab (1111:1111:1111) (1133:1133:1133)) + (PORT datac (1453:1453:1453) (1510:1510:1510)) + (PORT datad (1061:1061:1061) (1067:1067:1067)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (599:599:599)) + (PORT datab (1910:1910:1910) (2031:2031:2031)) + (PORT datac (794:794:794) (793:793:793)) + (PORT datad (1137:1137:1137) (1187:1187:1187)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (853:853:853)) + (PORT datab (838:838:838) (837:837:837)) + (PORT datac (1039:1039:1039) (1029:1029:1029)) + (PORT datad (845:845:845) (851:851:851)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (1006:1006:1006)) + (PORT datab (1459:1459:1459) (1555:1555:1555)) + (PORT datac (578:578:578) (579:579:579)) + (PORT datad (1554:1554:1554) (1605:1605:1605)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pla_decode_\|Equal19\~1) (DELAY (ABSOLUTE - (PORT dataa (1043:1043:1043) (1041:1041:1041)) - (PORT datab (2444:2444:2444) (2433:2433:2433)) - (PORT datac (778:778:778) (763:763:763)) - (PORT datad (1490:1490:1490) (1519:1519:1519)) + (PORT dataa (2170:2170:2170) (2236:2236:2236)) + (PORT datab (1515:1515:1515) (1602:1602:1602)) + (PORT datac (833:833:833) (863:863:863)) + (PORT datad (622:622:622) (647:647:647)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (994:994:994)) + (PORT datad (1419:1419:1419) (1497:1497:1497)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1241:1241:1241)) + (PORT datab (604:604:604) (626:626:626)) + (PORT datac (1256:1256:1256) (1261:1261:1261)) + (PORT datad (824:824:824) (814:814:814)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) + (DELAY + (ABSOLUTE + (PORT dataa (1046:1046:1046) (1058:1058:1058)) + (PORT datab (1581:1581:1581) (1635:1635:1635)) + (PORT datac (1431:1431:1431) (1520:1520:1520)) + (PORT datad (922:922:922) (971:971:971)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1258:1258:1258) (1338:1338:1338)) + (PORT datab (769:769:769) (764:764:764)) + (PORT datac (1036:1036:1036) (1044:1044:1044)) + (PORT datad (587:587:587) (616:616:616)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) + (DELAY + (ABSOLUTE + (PORT datab (1090:1090:1090) (1101:1101:1101)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (792:792:792) (802:802:802)) + (PORT datac (176:176:176) (220:220:220)) + (PORT datad (620:620:620) (653:653:653)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (937:937:937)) + (PORT datab (857:857:857) (883:883:883)) + (PORT datac (1297:1297:1297) (1301:1301:1301)) + (PORT datad (505:505:505) (493:493:493)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (573:573:573)) + (PORT datab (813:813:813) (797:797:797)) + (PORT datac (1265:1265:1265) (1299:1299:1299)) + (PORT datad (1371:1371:1371) (1415:1415:1415)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (902:902:902)) + (PORT datab (838:838:838) (839:839:839)) + (PORT datac (844:844:844) (867:867:867)) + (PORT datad (1421:1421:1421) (1476:1476:1476)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1086:1086:1086)) + (PORT datab (598:598:598) (626:626:626)) + (PORT datac (842:842:842) (851:851:851)) + (PORT datad (313:313:313) (321:321:321)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (DELAY + (ABSOLUTE + (PORT datab (1398:1398:1398) (1449:1449:1449)) + (PORT datac (1595:1595:1595) (1640:1640:1640)) + (PORT datad (992:992:992) (983:983:983)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (651:651:651)) + (PORT datab (1077:1077:1077) (1092:1092:1092)) + (PORT datac (791:791:791) (802:802:802)) + (PORT datad (1085:1085:1085) (1121:1121:1121)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (893:893:893)) + (PORT datab (871:871:871) (898:898:898)) + (PORT datac (588:588:588) (608:608:608)) + (PORT datad (1068:1068:1068) (1085:1085:1085)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT datab (795:795:795) (812:812:812)) + (PORT datac (162:162:162) (193:193:193)) + (PORT datad (785:785:785) (796:796:796)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (955:955:955)) + (PORT datab (1347:1347:1347) (1362:1362:1362)) + (PORT datac (1202:1202:1202) (1202:1202:1202)) + (PORT datad (796:796:796) (783:783:783)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1584:1584:1584)) + (PORT datab (1555:1555:1555) (1584:1584:1584)) + (PORT datac (1364:1364:1364) (1421:1421:1421)) + (PORT datad (800:800:800) (784:784:784)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (1339:1339:1339) (1364:1364:1364)) + (PORT datab (1555:1555:1555) (1579:1579:1579)) + (PORT datac (1526:1526:1526) (1546:1546:1546)) + (PORT datad (1081:1081:1081) (1109:1109:1109)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (823:823:823)) + (PORT datab (566:566:566) (558:558:558)) + (PORT datac (1372:1372:1372) (1392:1392:1392)) + (PORT datad (529:529:529) (531:531:531)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (889:889:889)) + (PORT datab (852:852:852) (861:861:861)) + (PORT datac (819:819:819) (835:835:835)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) + (DELAY + (ABSOLUTE + (PORT dataa (1666:1666:1666) (1693:1693:1693)) + (PORT datab (1579:1579:1579) (1635:1635:1635)) + (PORT datac (1433:1433:1433) (1520:1520:1520)) + (PORT datad (924:924:924) (971:971:971)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1490:1490:1490) (1562:1562:1562)) + (PORT datac (2316:2316:2316) (2354:2354:2354)) + (PORT datad (1370:1370:1370) (1419:1419:1419)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1093:1093:1093) (1079:1079:1079)) + (PORT datab (1076:1076:1076) (1084:1084:1084)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (801:801:801) (790:790:790)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (633:633:633) (649:649:649)) + (PORT datac (350:350:350) (372:372:372)) + (PORT datad (185:185:185) (210:210:210)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (441:441:441)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (755:755:755) (733:733:733)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (366:366:366)) + (PORT datab (840:840:840) (809:809:809)) + (PORT datac (583:583:583) (587:587:587)) + (PORT datad (1100:1100:1100) (1110:1110:1110)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1201:1201:1201)) + (PORT datab (1520:1520:1520) (1606:1606:1606)) + (PORT datac (837:837:837) (864:864:864)) + (PORT datad (875:875:875) (891:891:891)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1344:1344:1344) (1403:1403:1403)) + (PORT datab (1544:1544:1544) (1566:1566:1566)) + (PORT datac (780:780:780) (766:766:766)) + (PORT datad (599:599:599) (622:622:622)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1397:1397:1397)) + (PORT datab (841:841:841) (835:835:835)) + (PORT datad (2159:2159:2159) (2215:2215:2215)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1082:1082:1082) (1075:1075:1075)) + (PORT datab (1111:1111:1111) (1127:1127:1127)) + (PORT datad (1118:1118:1118) (1164:1164:1164)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1414:1414:1414) (1380:1380:1380)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (872:872:872)) + (PORT datab (1882:1882:1882) (1862:1862:1862)) + (PORT datac (749:749:749) (731:731:731)) + (PORT datad (308:308:308) (321:321:321)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (889:889:889)) + (PORT datab (1596:1596:1596) (1576:1576:1576)) + (PORT datac (1137:1137:1137) (1193:1193:1193)) + (PORT datad (1069:1069:1069) (1084:1084:1084)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (721:721:721) (704:704:704)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1138:1138:1138) (1195:1195:1195)) + (PORT datad (1423:1423:1423) (1478:1478:1478)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1167:1167:1167)) + (PORT datab (1180:1180:1180) (1243:1243:1243)) + (PORT datac (1064:1064:1064) (1081:1081:1081)) + (PORT datad (653:653:653) (698:698:698)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (587:587:587)) + (PORT datab (558:558:558) (547:547:547)) + (PORT datac (842:842:842) (851:851:851)) + (PORT datad (1614:1614:1614) (1636:1636:1636)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (882:882:882)) + (PORT datab (334:334:334) (351:351:351)) + (PORT datac (1095:1095:1095) (1094:1094:1094)) + (PORT datad (1866:1866:1866) (1908:1908:1908)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (333:333:333)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (814:814:814) (838:838:838)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (966:966:966)) + (PORT datab (841:841:841) (903:903:903)) + (PORT datac (994:994:994) (962:962:962)) + (PORT datad (981:981:981) (973:973:973)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1243:1243:1243) (1274:1274:1274)) + (PORT datab (836:836:836) (860:860:860)) + (PORT datac (614:614:614) (619:619:619)) + (PORT datad (1077:1077:1077) (1096:1096:1096)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1883:1883:1883) (1905:1905:1905)) + (PORT datac (1526:1526:1526) (1519:1519:1519)) + (PORT datad (1594:1594:1594) (1640:1640:1640)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (952:952:952)) + (PORT datab (1230:1230:1230) (1233:1233:1233)) + (PORT datac (1216:1216:1216) (1250:1250:1250)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT datab (614:614:614) (609:609:609)) + (PORT datac (605:605:605) (605:605:605)) + (PORT datad (830:830:830) (864:864:864)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (614:614:614)) + (PORT datab (656:656:656) (655:655:655)) + (PORT datac (625:625:625) (659:659:659)) + (PORT datad (773:773:773) (751:751:751)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (788:788:788)) + (PORT datac (1768:1768:1768) (1803:1803:1803)) + (PORT datad (182:182:182) (216:216:216)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (599:599:599)) + (PORT datab (802:802:802) (832:832:832)) + (PORT datac (1015:1015:1015) (1007:1007:1007)) + (PORT datad (767:767:767) (769:769:769)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1061:1061:1061)) + (PORT datab (925:925:925) (982:982:982)) + (PORT datac (1298:1298:1298) (1315:1315:1315)) + (PORT datad (185:185:185) (216:216:216)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1063:1063:1063)) + (PORT datab (1826:1826:1826) (1865:1865:1865)) + (PORT datac (1066:1066:1066) (1087:1087:1087)) + (PORT datad (862:862:862) (902:902:902)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (2410:2410:2410) (2500:2500:2500)) + (PORT datad (176:176:176) (198:198:198)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (922:922:922)) + (PORT datac (1027:1027:1027) (1063:1063:1063)) + (PORT datad (1062:1062:1062) (1079:1079:1079)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (923:923:923)) + (PORT datab (784:784:784) (755:755:755)) + (PORT datac (1854:1854:1854) (1845:1845:1845)) + (PORT datad (1290:1290:1290) (1271:1271:1271)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1463:1463:1463) (1537:1537:1537)) + (PORT datab (846:846:846) (865:865:865)) + (PORT datac (857:857:857) (889:889:889)) + (PORT datad (1410:1410:1410) (1477:1477:1477)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (602:602:602)) + (PORT datab (806:806:806) (796:796:796)) + (PORT datac (556:556:556) (588:588:588)) + (PORT datad (756:756:756) (737:737:737)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1120:1120:1120)) + (PORT datac (1287:1287:1287) (1310:1310:1310)) + (PORT datad (1946:1946:1946) (2000:2000:2000)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (866:866:866)) + (PORT datab (1437:1437:1437) (1489:1489:1489)) + (PORT datac (189:189:189) (227:227:227)) + (PORT datad (571:571:571) (571:571:571)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1273:1273:1273) (1297:1297:1297)) + (PORT datab (570:570:570) (567:567:567)) + (PORT datac (730:730:730) (709:709:709)) + (PORT datad (553:553:553) (545:545:545)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1541:1541:1541) (1540:1540:1540)) + (PORT datab (1032:1032:1032) (1027:1027:1027)) + (PORT datac (973:973:973) (1020:1020:1020)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1222:1222:1222) (1283:1283:1283)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (553:553:553) (560:560:560)) + (PORT datad (1361:1361:1361) (1405:1405:1405)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (529:529:529)) + (PORT datab (572:572:572) (598:598:598)) + (PORT datac (568:568:568) (565:565:565)) + (PORT datad (543:543:543) (521:521:521)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (2077:2077:2077) (2125:2125:2125)) + (PORT datab (237:237:237) (304:304:304)) + (PORT datac (1069:1069:1069) (1106:1106:1106)) + (PORT datad (214:214:214) (271:271:271)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (161:161:161) (196:196:196)) + (PORT datad (809:809:809) (823:823:823)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (189:189:189) (226:226:226)) + (PORT datad (614:614:614) (630:630:630)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (239:239:239)) + (PORT datab (959:959:959) (957:957:957)) + (PORT datac (310:310:310) (319:319:319)) + (PORT datad (637:637:637) (668:668:668)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1041:1041:1041) (1135:1135:1135)) + (PORT datac (825:825:825) (856:856:856)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) + (DELAY + (ABSOLUTE + (PORT datac (611:611:611) (666:666:666)) + (PORT datad (830:830:830) (826:826:826)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1328:1328:1328) (1337:1337:1337)) + (PORT datab (575:575:575) (576:576:576)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1052:1052:1052) (1050:1050:1050)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~47) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (570:570:570)) + (PORT datab (602:602:602) (594:594:594)) + (PORT datac (827:827:827) (826:826:826)) + (PORT datad (819:819:819) (832:832:832)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (341:341:341)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (566:566:566) (585:585:585)) + (PORT datad (985:985:985) (968:968:968)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1884:1884:1884) (1906:1906:1906)) + (PORT datac (1526:1526:1526) (1518:1518:1518)) + (PORT datad (1595:1595:1595) (1640:1640:1640)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1225:1225:1225) (1290:1290:1290)) + (PORT datab (1026:1026:1026) (1009:1009:1009)) + (PORT datac (849:849:849) (867:867:867)) + (PORT datad (521:521:521) (513:513:513)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (250:250:250)) + (PORT datab (207:207:207) (246:246:246)) + (PORT datac (1092:1092:1092) (1118:1118:1118)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) + (DELAY + (ABSOLUTE + (PORT dataa (757:757:757) (754:754:754)) + (PORT datab (1168:1168:1168) (1189:1189:1189)) + (PORT datac (1657:1657:1657) (1708:1708:1708)) + (PORT datad (1950:1950:1950) (2008:2008:2008)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (585:585:585) (583:583:583)) + (PORT datac (554:554:554) (549:549:549)) + (PORT datad (782:782:782) (777:777:777)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1258:1258:1258) (1344:1344:1344)) + (PORT datab (688:688:688) (729:729:729)) + (PORT datac (809:809:809) (805:805:805)) + (PORT datad (829:829:829) (860:860:860)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (809:809:809)) + (PORT datab (623:623:623) (666:666:666)) + (PORT datac (899:899:899) (929:929:929)) + (PORT datad (1646:1646:1646) (1664:1664:1664)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1254:1254:1254)) + (PORT datab (820:820:820) (825:825:825)) + (PORT datac (579:579:579) (580:580:580)) + (PORT datad (1600:1600:1600) (1599:1599:1599)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1258:1258:1258) (1346:1346:1346)) + (PORT datab (597:597:597) (633:633:633)) + (PORT datac (810:810:810) (806:806:806)) + (PORT datad (355:355:355) (359:359:359)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (851:851:851)) + (PORT datab (627:627:627) (668:668:668)) + (PORT datac (894:894:894) (935:935:935)) + (PORT datad (579:579:579) (570:570:570)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1347:1347:1347) (1368:1368:1368)) + (PORT datab (867:867:867) (863:863:863)) + (PORT datac (173:173:173) (204:204:204)) + (PORT datad (1302:1302:1302) (1304:1304:1304)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1469:1469:1469) (1500:1500:1500)) + (PORT datab (1474:1474:1474) (1453:1453:1453)) + (PORT datac (920:920:920) (954:954:954)) + (PORT datad (1434:1434:1434) (1445:1445:1445)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1366:1366:1366)) + (PORT datab (824:824:824) (865:865:865)) + (PORT datac (758:758:758) (792:792:792)) + (PORT datad (550:550:550) (549:549:549)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1349:1349:1349) (1363:1363:1363)) + (PORT datab (825:825:825) (869:869:869)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (842:842:842) (874:874:874)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (549:549:549)) + (PORT datab (794:794:794) (812:812:812)) + (PORT datac (731:731:731) (762:762:762)) + (PORT datad (725:725:725) (755:755:755)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (604:604:604)) + (PORT datab (214:214:214) (255:255:255)) + (PORT datac (1213:1213:1213) (1288:1288:1288)) + (PORT datad (2060:2060:2060) (2081:2081:2081)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1666:1666:1666) (1749:1749:1749)) + (PORT datab (1520:1520:1520) (1585:1585:1585)) + (PORT datac (1196:1196:1196) (1253:1253:1253)) + (PORT datad (2365:2365:2365) (2392:2392:2392)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1182:1182:1182)) + (PORT datab (803:803:803) (793:793:793)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (546:546:546) (541:541:541)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1342:1342:1342) (1384:1384:1384)) + (PORT datab (236:236:236) (278:278:278)) + (PORT datac (1106:1106:1106) (1143:1143:1143)) + (PORT datad (776:776:776) (760:760:760)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~2) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (815:815:815)) + (PORT datab (827:827:827) (812:812:812)) + (PORT datac (798:798:798) (782:782:782)) + (PORT datad (830:830:830) (868:868:868)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (821:821:821)) + (PORT datab (865:865:865) (910:910:910)) + (PORT datac (173:173:173) (217:217:217)) + (PORT datad (1070:1070:1070) (1075:1075:1075)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1350:1350:1350) (1336:1336:1336)) + (PORT datab (1385:1385:1385) (1402:1402:1402)) + (PORT datac (1018:1018:1018) (1017:1017:1017)) + (PORT datad (369:369:369) (395:395:395)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (812:812:812)) + (PORT datab (829:829:829) (812:812:812)) + (PORT datac (800:800:800) (784:784:784)) + (PORT datad (831:831:831) (871:871:871)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (727:727:727)) + (PORT datab (721:721:721) (791:791:791)) + (PORT datad (1092:1092:1092) (1075:1075:1075)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (538:538:538)) + (PORT datab (1080:1080:1080) (1067:1067:1067)) + (PORT datac (796:796:796) (816:816:816)) + (PORT datad (838:838:838) (844:844:844)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1342:1342:1342) (1386:1386:1386)) + (PORT datab (799:799:799) (795:795:795)) + (PORT datac (1177:1177:1177) (1213:1213:1213)) + (PORT datad (1481:1481:1481) (1552:1552:1552)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1376:1376:1376) (1455:1455:1455)) + (PORT datab (1328:1328:1328) (1314:1314:1314)) + (PORT datac (1318:1318:1318) (1387:1387:1387)) + (PORT datad (376:376:376) (397:397:397)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (940:940:940)) + (PORT datac (742:742:742) (722:722:722)) + (PORT datad (941:941:941) (930:930:930)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (368:368:368) (398:398:398)) + (PORT datac (907:907:907) (902:902:902)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (330:330:330)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (547:547:547) (551:551:551)) + (PORT datad (1399:1399:1399) (1467:1467:1467)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1148:1148:1148)) + (PORT datab (1126:1126:1126) (1152:1152:1152)) + (PORT datac (820:820:820) (852:852:852)) + (PORT datad (1400:1400:1400) (1447:1447:1447)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (784:784:784)) + (PORT datab (208:208:208) (247:247:247)) + (PORT datac (1074:1074:1074) (1134:1134:1134)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1578:1578:1578)) + (PORT datab (1555:1555:1555) (1584:1584:1584)) + (PORT datac (1366:1366:1366) (1422:1422:1422)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (923:923:923)) + (PORT datab (187:187:187) (221:221:221)) + (PORT datac (1105:1105:1105) (1128:1128:1128)) + (PORT datad (820:820:820) (821:821:821)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (1117:1117:1117) (1098:1098:1098)) + (PORT datac (1157:1157:1157) (1166:1166:1166)) + (PORT datad (735:735:735) (714:714:714)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (864:864:864)) + (PORT datab (873:873:873) (894:894:894)) + (PORT datac (1056:1056:1056) (1047:1047:1047)) + (PORT datad (356:356:356) (376:376:376)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1190:1190:1190) (1198:1198:1198)) + (PORT datab (1113:1113:1113) (1096:1096:1096)) + (PORT datac (1053:1053:1053) (1046:1046:1046)) + (PORT datad (735:735:735) (713:713:713)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (307:307:307)) + (PORT datab (200:200:200) (245:245:245)) + (PORT datac (316:316:316) (331:331:331)) + (PORT datad (1131:1131:1131) (1174:1174:1174)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1078:1078:1078)) + (PORT datab (1108:1108:1108) (1126:1126:1126)) + (PORT datad (1131:1131:1131) (1181:1181:1181)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1414:1414:1414) (1380:1380:1380)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (357:357:357)) + (PORT datab (199:199:199) (242:242:242)) + (PORT datac (200:200:200) (270:270:270)) + (PORT datad (1114:1114:1114) (1162:1162:1162)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (519:519:519)) + (PORT datab (960:960:960) (961:961:961)) + (PORT datac (314:314:314) (324:324:324)) + (PORT datad (635:635:635) (668:668:668)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (629:629:629)) + (PORT datab (1595:1595:1595) (1613:1613:1613)) + (PORT datad (813:813:813) (804:804:804)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (2436:2436:2436) (2440:2440:2440)) + (PORT datab (1579:1579:1579) (1634:1634:1634)) + (PORT datac (945:945:945) (943:943:943)) + (PORT datad (1419:1419:1419) (1423:1423:1423)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (251:251:251)) + (PORT datab (819:819:819) (824:824:824)) + (PORT datac (1371:1371:1371) (1418:1418:1418)) + (PORT datad (1122:1122:1122) (1134:1134:1134)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (921:921:921)) + (PORT datab (185:185:185) (222:222:222)) + (PORT datac (878:878:878) (906:906:906)) + (PORT datad (190:190:190) (217:217:217)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla30npla13M5T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (908:908:908)) + (PORT datab (210:210:210) (251:251:251)) + (PORT datac (1296:1296:1296) (1317:1317:1317)) + (PORT datad (1395:1395:1395) (1410:1410:1410)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1073:1073:1073)) + (PORT datab (1434:1434:1434) (1430:1430:1430)) + (PORT datac (553:553:553) (573:573:573)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (347:347:347)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (163:163:163) (187:187:187)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (847:847:847)) + (PORT datab (615:615:615) (615:615:615)) + (PORT datac (1030:1030:1030) (994:994:994)) + (PORT datad (723:723:723) (705:705:705)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1491:1491:1491) (1597:1597:1597)) + (PORT datab (1403:1403:1403) (1444:1444:1444)) + (PORT datac (1573:1573:1573) (1621:1621:1621)) + (PORT datad (986:986:986) (963:963:963)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1855:1855:1855) (1982:1982:1982)) + (PORT datab (1351:1351:1351) (1392:1392:1392)) + (PORT datac (1387:1387:1387) (1427:1427:1427)) + (PORT datad (1772:1772:1772) (1781:1781:1781)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (863:863:863)) + (PORT datab (808:808:808) (808:808:808)) + (PORT datac (747:747:747) (789:789:789)) + (PORT datad (1402:1402:1402) (1458:1458:1458)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (590:590:590)) + (PORT datab (616:616:616) (645:645:645)) + (PORT datac (850:850:850) (872:872:872)) + (PORT datad (164:164:164) (190:190:190)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (669:669:669)) + (PORT datab (1098:1098:1098) (1128:1128:1128)) + (PORT datac (615:615:615) (620:620:620)) + (PORT datad (1199:1199:1199) (1235:1235:1235)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1268:1268:1268) (1283:1283:1283)) + (PORT datab (599:599:599) (612:612:612)) + (PORT datac (1228:1228:1228) (1222:1222:1222)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1093:1093:1093)) + (PORT datab (1683:1683:1683) (1698:1698:1698)) + (PORT datad (892:892:892) (959:959:959)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (839:839:839)) + (PORT datab (631:631:631) (663:663:663)) + (PORT datac (182:182:182) (216:216:216)) + (PORT datad (2040:2040:2040) (2019:2019:2019)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1188:1188:1188)) + (PORT datab (1375:1375:1375) (1404:1404:1404)) + (PORT datac (1140:1140:1140) (1139:1139:1139)) + (PORT datad (1133:1133:1133) (1131:1131:1131)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1770:1770:1770) (1773:1773:1773)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (797:797:797) (838:838:838)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (568:568:568)) + (PORT datab (199:199:199) (233:233:233)) + (PORT datac (824:824:824) (827:827:827)) + (PORT datad (752:752:752) (779:779:779)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (800:800:800)) + (PORT datab (186:186:186) (222:222:222)) + (PORT datac (521:521:521) (520:520:520)) + (PORT datad (572:572:572) (593:593:593)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (787:787:787)) + (PORT datac (188:188:188) (230:230:230)) + (PORT datad (184:184:184) (217:217:217)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1214:1214:1214) (1240:1240:1240)) + (PORT datab (574:574:574) (563:563:563)) + (PORT datac (779:779:779) (772:772:772)) + (PORT datad (568:568:568) (574:574:574)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1325:1325:1325)) + (PORT datab (851:851:851) (858:858:858)) + (PORT datac (1050:1050:1050) (1064:1064:1064)) + (PORT datad (1086:1086:1086) (1124:1124:1124)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1615:1615:1615) (1648:1648:1648)) + (PORT datab (777:777:777) (759:759:759)) + (PORT datac (1852:1852:1852) (1834:1834:1834)) + (PORT datad (1888:1888:1888) (1939:1939:1939)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~40) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (870:870:870)) + (PORT datab (1014:1014:1014) (1032:1032:1032)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (501:501:501)) + (PORT datab (615:615:615) (629:629:629)) + (PORT datac (1842:1842:1842) (1822:1822:1822)) + (PORT datad (511:511:511) (487:487:487)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (791:791:791) (833:833:833)) + (PORT datac (162:162:162) (194:194:194)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (790:790:790) (781:781:781)) + (PORT datac (530:530:530) (525:525:525)) + (PORT datad (166:166:166) (189:189:189)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1110:1110:1110)) + (PORT datab (984:984:984) (938:938:938)) + (PORT datac (1084:1084:1084) (1078:1078:1078)) + (PORT datad (1262:1262:1262) (1238:1238:1238)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (301:301:301)) + (PORT datab (199:199:199) (242:242:242)) + (PORT datac (314:314:314) (326:326:326)) + (PORT datad (1115:1115:1115) (1162:1162:1162)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT datab (1303:1303:1303) (1278:1278:1278)) + (PORT datac (1080:1080:1080) (1073:1073:1073)) + (PORT datad (551:551:551) (560:560:560)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) + (DELAY + (ABSOLUTE + (PORT datac (836:836:836) (844:844:844)) + (PORT datad (1247:1247:1247) (1232:1232:1232)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1085:1085:1085) (1104:1104:1104)) + (PORT datab (202:202:202) (244:244:244)) + (PORT datac (1054:1054:1054) (1051:1051:1051)) + (PORT datad (624:624:624) (643:643:643)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (685:685:685)) + (PORT datab (1364:1364:1364) (1393:1393:1393)) + (PORT datac (1057:1057:1057) (1051:1051:1051)) + (PORT datad (179:179:179) (212:212:212)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (678:678:678)) + (PORT datab (1366:1366:1366) (1398:1398:1398)) + (PORT datac (1051:1051:1051) (1047:1047:1047)) + (PORT datad (176:176:176) (209:209:209)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1241:1241:1241) (1264:1264:1264)) + (PORT datab (802:802:802) (818:818:818)) + (PORT datac (1675:1675:1675) (1702:1702:1702)) + (PORT datad (1446:1446:1446) (1466:1466:1466)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datad (798:798:798) (802:802:802)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (968:968:968)) + (PORT datab (603:603:603) (608:608:608)) + (PORT datac (851:851:851) (875:875:875)) + (PORT datad (1334:1334:1334) (1387:1387:1387)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1057:1057:1057)) + (PORT datab (651:651:651) (704:704:704)) + (PORT datac (1319:1319:1319) (1387:1387:1387)) + (PORT datad (1351:1351:1351) (1415:1415:1415)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (558:558:558)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datac (576:576:576) (588:588:588)) + (PORT datad (1016:1016:1016) (977:977:977)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (370:370:370)) + (PORT datab (1097:1097:1097) (1091:1091:1091)) + (PORT datac (330:330:330) (337:337:337)) + (PORT datad (1019:1019:1019) (993:993:993)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1192:1192:1192)) + (PORT datab (1464:1464:1464) (1534:1534:1534)) + (PORT datac (2034:2034:2034) (2016:2016:2016)) + (PORT datad (985:985:985) (1044:1044:1044)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (909:909:909)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1151:1151:1151) (1162:1162:1162)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (587:587:587)) + (PORT datac (614:614:614) (623:623:623)) + (PORT datad (519:519:519) (489:489:489)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1076:1076:1076)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1048:1048:1048) (1041:1041:1041)) + (PORT datad (615:615:615) (635:635:635)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~2) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (840:840:840)) + (PORT datab (823:823:823) (821:821:821)) + (PORT datac (839:839:839) (888:888:888)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (674:674:674)) + (PORT datab (1094:1094:1094) (1073:1073:1073)) + (PORT datad (877:877:877) (872:872:872)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1368:1368:1368)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1063:1063:1063) (1081:1081:1081)) + (PORT datab (225:225:225) (296:296:296)) + (PORT datac (1056:1056:1056) (1051:1051:1051)) + (PORT datad (624:624:624) (643:643:643)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (644:644:644)) + (PORT datab (1269:1269:1269) (1248:1248:1248)) + (PORT datad (843:843:843) (858:858:858)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1063:1063:1063) (1075:1075:1075)) + (PORT datab (226:226:226) (299:299:299)) + (PORT datac (1050:1050:1050) (1045:1045:1045)) + (PORT datad (614:614:614) (638:638:638)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (1612:1612:1612) (1604:1604:1604)) + (PORT datab (1085:1085:1085) (1084:1084:1084)) + (PORT datad (744:744:744) (705:705:705)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (681:681:681)) + (PORT datab (857:857:857) (878:878:878)) + (PORT datac (1675:1675:1675) (1732:1732:1732)) + (PORT datad (1057:1057:1057) (1054:1054:1054)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1364:1364:1364) (1424:1424:1424)) + (PORT datac (942:942:942) (961:961:961)) + (PORT datad (304:304:304) (309:309:309)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1321:1321:1321) (1321:1321:1321)) + (PORT datab (1079:1079:1079) (1103:1103:1103)) + (PORT datac (1868:1868:1868) (1905:1905:1905)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1079:1079:1079) (1075:1075:1075)) + (PORT datab (1895:1895:1895) (1904:1904:1904)) + (PORT datac (878:878:878) (907:907:907)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (764:764:764) (823:823:823)) + (PORT datab (1401:1401:1401) (1421:1421:1421)) + (PORT datac (1205:1205:1205) (1204:1204:1204)) + (PORT datad (802:802:802) (787:787:787)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) + (DELAY + (ABSOLUTE + (PORT datab (207:207:207) (246:246:246)) + (PORT datac (182:182:182) (217:217:217)) + (PORT datad (184:184:184) (209:209:209)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (1424:1424:1424) (1497:1497:1497)) + (PORT datac (186:186:186) (222:222:222)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (551:551:551)) + (PORT datab (811:811:811) (812:812:812)) + (PORT datac (1275:1275:1275) (1293:1293:1293)) + (PORT datad (1806:1806:1806) (1800:1800:1800)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (240:240:240)) + (PORT datab (1860:1860:1860) (1858:1858:1858)) + (PORT datac (752:752:752) (731:731:731)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (662:662:662)) + (PORT datab (1339:1339:1339) (1359:1359:1359)) + (PORT datac (330:330:330) (348:348:348)) + (PORT datad (1037:1037:1037) (1058:1058:1058)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (251:251:251)) + (PORT datab (527:527:527) (514:514:514)) + (PORT datac (745:745:745) (740:740:740)) + (PORT datad (550:550:550) (564:564:564)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1118:1118:1118)) + (PORT datab (554:554:554) (551:551:551)) + (PORT datac (594:594:594) (624:624:624)) + (PORT datad (792:792:792) (796:796:796)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (659:659:659)) + (PORT datab (1109:1109:1109) (1110:1110:1110)) + (PORT datac (1070:1070:1070) (1080:1080:1080)) + (PORT datad (549:549:549) (536:536:536)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (830:830:830)) + (PORT datab (1103:1103:1103) (1126:1126:1126)) + (PORT datac (830:830:830) (843:843:843)) + (PORT datad (586:586:586) (608:608:608)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (543:543:543)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (862:862:862)) + (PORT datab (1104:1104:1104) (1125:1125:1125)) + (PORT datac (332:332:332) (352:352:352)) + (PORT datad (1035:1035:1035) (1058:1058:1058)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1119:1119:1119)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1071:1071:1071) (1083:1083:1083)) + (PORT datad (789:789:789) (795:795:795)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (228:228:228)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (593:593:593) (623:623:623)) + (PORT datad (785:785:785) (799:799:799)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (565:565:565)) + (PORT datab (634:634:634) (646:646:646)) + (PORT datac (350:350:350) (370:370:370)) + (PORT datad (184:184:184) (208:208:208)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (565:565:565) (563:563:563)) + (PORT datac (499:499:499) (482:482:482)) + (PORT datad (781:781:781) (787:787:787)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (880:880:880)) + (PORT datab (1437:1437:1437) (1501:1501:1501)) + (PORT datac (1296:1296:1296) (1312:1312:1312)) + (PORT datad (182:182:182) (213:213:213)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (594:594:594)) + (PORT datab (884:884:884) (945:945:945)) + (PORT datac (1595:1595:1595) (1641:1641:1641)) + (PORT datad (1057:1057:1057) (1049:1049:1049)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1055:1055:1055)) + (PORT datab (1346:1346:1346) (1415:1415:1415)) + (PORT datac (1487:1487:1487) (1528:1528:1528)) + (PORT datad (1084:1084:1084) (1099:1099:1099)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1272:1272:1272)) + (PORT datab (1148:1148:1148) (1164:1164:1164)) + (PORT datac (1167:1167:1167) (1153:1153:1153)) + (PORT datad (1172:1172:1172) (1180:1180:1180)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1049:1049:1049) (1030:1030:1030)) + (PORT datac (570:570:570) (565:565:565)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (256:256:256)) + (PORT datab (199:199:199) (231:231:231)) + (PORT datac (1059:1059:1059) (1076:1076:1076)) + (PORT datad (177:177:177) (197:197:197)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~35) + (DELAY + (ABSOLUTE + (PORT datab (1858:1858:1858) (1864:1864:1864)) + (PORT datac (1247:1247:1247) (1235:1235:1235)) + (PORT datad (790:790:790) (789:789:789)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (240:240:240)) + (PORT datab (840:840:840) (833:833:833)) + (PORT datac (578:578:578) (576:576:576)) + (PORT datad (849:849:849) (870:870:870)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1397:1397:1397) (1416:1416:1416)) + (PORT datab (1081:1081:1081) (1069:1069:1069)) + (PORT datac (1016:1016:1016) (1034:1034:1034)) + (PORT datad (505:505:505) (499:499:499)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (580:580:580)) + (PORT datab (213:213:213) (251:251:251)) + (PORT datac (1050:1050:1050) (1062:1062:1062)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1572:1572:1572)) + (PORT datab (938:938:938) (988:988:988)) + (PORT datac (951:951:951) (1012:1012:1012)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1081:1081:1081) (1102:1102:1102)) + (PORT datab (1421:1421:1421) (1474:1474:1474)) + (PORT datad (184:184:184) (207:207:207)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (825:825:825)) + (PORT datab (529:529:529) (526:526:526)) + (PORT datac (561:561:561) (561:561:561)) + (PORT datad (557:557:557) (551:551:551)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1167:1167:1167)) + (PORT datab (1177:1177:1177) (1248:1248:1248)) + (PORT datac (1063:1063:1063) (1080:1080:1080)) + (PORT datad (650:650:650) (693:693:693)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (658:658:658)) + (PORT datab (1248:1248:1248) (1207:1207:1207)) + (PORT datac (1129:1129:1129) (1140:1140:1140)) + (PORT datad (1536:1536:1536) (1551:1551:1551)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (979:979:979)) + (PORT datab (833:833:833) (842:842:842)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (202:202:202) (225:225:225)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (1023:1023:1023)) + (PORT datac (2019:2019:2019) (2030:2030:2030)) + (PORT datad (599:599:599) (636:636:636)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (697:697:697)) + (PORT datab (1056:1056:1056) (1042:1042:1042)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (1057:1057:1057) (1062:1062:1062)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (993:993:993)) + (PORT datab (618:618:618) (616:616:616)) + (PORT datac (929:929:929) (990:990:990)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (863:863:863) (870:870:870)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (327:327:327)) + (PORT datac (217:217:217) (285:285:285)) + (PORT datad (223:223:223) (285:285:285)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (887:887:887)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (1024:1024:1024) (1002:1002:1002)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (1095:1095:1095)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (592:592:592) (638:638:638)) + (PORT datad (891:891:891) (959:959:959)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (2372:2372:2372) (2400:2400:2400)) + (PORT datab (1481:1481:1481) (1548:1548:1548)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (199:199:199) (236:236:236)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (987:987:987) (1008:1008:1008)) + (PORT datab (186:186:186) (221:221:221)) + (PORT datac (822:822:822) (802:802:802)) + (PORT datad (770:770:770) (760:760:760)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (852:852:852) (879:879:879)) + (PORT datad (579:579:579) (590:590:590)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (607:607:607)) + (PORT datab (843:843:843) (873:873:873)) + (PORT datac (998:998:998) (992:992:992)) + (PORT datad (183:183:183) (207:207:207)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -2252,12 +10089,12 @@ (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) (DELAY (ABSOLUTE - (PORT dataa (1096:1096:1096) (1126:1126:1126)) - (PORT datab (632:632:632) (658:658:658)) - (PORT datac (887:887:887) (843:843:843)) - (PORT datad (577:577:577) (578:578:578)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (827:827:827) (855:855:855)) + (PORT datab (836:836:836) (832:832:832)) + (PORT datac (577:577:577) (600:600:600)) + (PORT datad (826:826:826) (816:816:816)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -2268,10 +10105,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) (DELAY (ABSOLUTE - (PORT dataa (2179:2179:2179) (2182:2182:2182)) - (PORT datab (828:828:828) (829:829:829)) - (PORT datac (522:522:522) (517:517:517)) - (PORT datad (1000:1000:1000) (964:964:964)) + (PORT dataa (1848:1848:1848) (1914:1914:1914)) + (PORT datab (833:833:833) (859:859:859)) + (PORT datac (197:197:197) (239:239:239)) + (PORT datad (1066:1066:1066) (1061:1061:1061)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -2284,10 +10121,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) (DELAY (ABSOLUTE - (PORT dataa (1560:1560:1560) (1596:1596:1596)) - (PORT datab (1505:1505:1505) (1493:1493:1493)) - (PORT datac (1501:1501:1501) (1477:1477:1477)) - (PORT datad (1090:1090:1090) (1054:1054:1054)) + (PORT dataa (853:853:853) (886:886:886)) + (PORT datab (847:847:847) (864:864:864)) + (PORT datac (815:815:815) (817:817:817)) + (PORT datad (555:555:555) (563:563:563)) (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -2300,8 +10137,24 @@ (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) (DELAY (ABSOLUTE - (PORT datac (748:748:748) (751:751:751)) - (PORT datad (159:159:159) (181:181:181)) + (PORT dataa (833:833:833) (845:845:845)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (988:988:988)) + (PORT datab (828:828:828) (845:845:845)) + (PORT datac (561:561:561) (591:591:591)) + (PORT datad (799:799:799) (810:810:810)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -2309,46 +10162,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) (DELAY (ABSOLUTE - (PORT dataa (309:309:309) (329:329:329)) - (PORT datab (189:189:189) (227:227:227)) - (PORT datac (732:732:732) (720:720:720)) - (PORT datad (178:178:178) (201:201:201)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (2231:2231:2231) (2295:2295:2295)) + (PORT datab (1676:1676:1676) (1732:1732:1732)) + (PORT datac (994:994:994) (967:967:967)) + (PORT datad (1468:1468:1468) (1554:1554:1554)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) (DELAY (ABSOLUTE - (PORT dataa (791:791:791) (800:800:800)) - (PORT datab (820:820:820) (809:809:809)) - (PORT datac (806:806:806) (819:819:819)) - (PORT datad (569:569:569) (585:585:585)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1726:1726:1726) (1791:1791:1791)) - (PORT datab (1584:1584:1584) (1633:1633:1633)) - (PORT datac (1574:1574:1574) (1630:1630:1630)) - (PORT datad (1247:1247:1247) (1289:1289:1289)) - (IOPATH dataa combout (318:318:318) (307:307:307)) + (PORT dataa (769:769:769) (746:746:746)) + (PORT datab (846:846:846) (845:845:845)) + (PORT datac (771:771:771) (772:772:772)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -2357,75 +10194,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) (DELAY (ABSOLUTE - (PORT dataa (1142:1142:1142) (1173:1173:1173)) - (PORT datab (804:804:804) (802:802:802)) - (PORT datac (1447:1447:1447) (1417:1417:1417)) - (PORT datad (1266:1266:1266) (1260:1260:1260)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (926:926:926) (982:982:982)) - (PORT datac (786:786:786) (780:780:780)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (806:806:806) (805:805:805)) - (PORT datac (1481:1481:1481) (1473:1473:1473)) - (PORT datad (161:161:161) (182:182:182)) + (PORT dataa (2232:2232:2232) (2296:2296:2296)) + (PORT datab (2223:2223:2223) (2283:2283:2283)) + (PORT datac (1302:1302:1302) (1339:1339:1339)) + (PORT datad (1465:1465:1465) (1553:1553:1553)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~3) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) (DELAY (ABSOLUTE - (PORT datab (958:958:958) (1006:1006:1006)) - (PORT datad (859:859:859) (914:914:914)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (207:207:207) (245:245:245)) + (PORT datac (183:183:183) (220:220:220)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~31) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) (DELAY (ABSOLUTE - (PORT dataa (946:946:946) (991:991:991)) - (PORT datab (632:632:632) (654:654:654)) - (PORT datac (998:998:998) (970:970:970)) - (PORT datad (936:936:936) (918:918:918)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT dataa (1150:1150:1150) (1196:1196:1196)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (769:769:769) (746:746:746)) + (PORT datad (807:807:807) (817:817:817)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (796:796:796)) + (PORT datab (216:216:216) (254:254:254)) + (PORT datac (572:572:572) (594:594:594)) + (PORT datad (1245:1245:1245) (1260:1260:1260)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -2436,690 +10261,40 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) (DELAY (ABSOLUTE - (PORT dataa (191:191:191) (231:231:231)) - (PORT datab (880:880:880) (906:906:906)) - (PORT datac (1260:1260:1260) (1294:1294:1294)) - (PORT datad (575:575:575) (582:582:582)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1049:1049:1049) (1061:1061:1061)) - (PORT datab (631:631:631) (653:653:653)) - (PORT datac (572:572:572) (568:568:568)) - (PORT datad (1002:1002:1002) (989:989:989)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (810:810:810)) - (PORT datab (1325:1325:1325) (1345:1345:1345)) - (PORT datac (786:786:786) (802:802:802)) - (PORT datad (760:760:760) (760:760:760)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1477:1477:1477) (1460:1460:1460)) - (PORT datab (1856:1856:1856) (1813:1813:1813)) - (PORT datac (796:796:796) (800:800:800)) - (PORT datad (1066:1066:1066) (1086:1086:1086)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1078:1078:1078) (1090:1090:1090)) - (PORT datab (798:798:798) (785:785:785)) - (PORT datac (160:160:160) (192:192:192)) - (PORT datad (703:703:703) (681:681:681)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT datab (871:871:871) (892:892:892)) - (PORT datac (1089:1089:1089) (1096:1096:1096)) - (PORT datad (819:819:819) (853:853:853)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (550:550:550)) - (PORT datab (607:607:607) (613:613:613)) - (PORT datac (958:958:958) (969:969:969)) - (PORT datad (536:536:536) (551:551:551)) + (PORT dataa (1130:1130:1130) (1195:1195:1195)) + (PORT datab (1281:1281:1281) (1366:1366:1366)) + (PORT datac (800:800:800) (838:838:838)) + (PORT datad (779:779:779) (766:766:766)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) + (INSTANCE z80_\|execute_\|fMRead\~0) (DELAY (ABSOLUTE - (PORT dataa (585:585:585) (608:608:608)) - (PORT datab (911:911:911) (947:947:947)) - (PORT datac (1026:1026:1026) (1036:1036:1036)) - (PORT datad (1263:1263:1263) (1286:1286:1286)) + (PORT dataa (1902:1902:1902) (1924:1924:1924)) + (PORT datab (2319:2319:2319) (2469:2469:2469)) + (PORT datac (2661:2661:2661) (2717:2717:2717)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1130:1130:1130)) - (PORT datab (633:633:633) (649:649:649)) - (PORT datac (794:794:794) (788:788:788)) - (PORT datad (578:578:578) (576:576:576)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1323:1323:1323)) - (PORT datab (1494:1494:1494) (1496:1496:1496)) - (PORT datac (1023:1023:1023) (1032:1032:1032)) - (PORT datad (878:878:878) (917:917:917)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (991:991:991)) - (PORT datab (1024:1024:1024) (1035:1035:1035)) - (PORT datac (1326:1326:1326) (1343:1343:1343)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) - (DELAY - (ABSOLUTE - (PORT datab (185:185:185) (221:221:221)) - (PORT datac (582:582:582) (592:592:592)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (886:886:886)) - (PORT datab (611:611:611) (637:637:637)) - (PORT datac (847:847:847) (880:880:880)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1138:1138:1138)) - (PORT datab (1256:1256:1256) (1244:1244:1244)) - (PORT datac (1874:1874:1874) (1890:1890:1890)) - (PORT datad (836:836:836) (848:848:848)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1726:1726:1726) (1791:1791:1791)) - (PORT datab (1591:1591:1591) (1638:1638:1638)) - (PORT datac (1568:1568:1568) (1611:1611:1611)) - (PORT datad (1262:1262:1262) (1301:1301:1301)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1097:1097:1097) (1142:1142:1142)) - (PORT datab (1101:1101:1101) (1121:1121:1121)) - (PORT datac (1069:1069:1069) (1112:1112:1112)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1265:1265:1265) (1263:1263:1263)) - (PORT datab (213:213:213) (253:253:253)) - (PORT datac (1587:1587:1587) (1574:1574:1574)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1351:1351:1351)) - (PORT datac (1389:1389:1389) (1404:1404:1404)) - (PORT datad (1257:1257:1257) (1271:1271:1271)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~2) - (DELAY - (ABSOLUTE - (PORT datac (1280:1280:1280) (1290:1290:1290)) - (PORT datad (1250:1250:1250) (1226:1226:1226)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1548:1548:1548) (1551:1551:1551)) - (PORT datab (1547:1547:1547) (1572:1572:1572)) - (PORT datac (1002:1002:1002) (987:987:987)) - (PORT datad (1709:1709:1709) (1706:1706:1706)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1477:1477:1477) (1452:1452:1452)) - (PORT datab (203:203:203) (237:237:237)) - (PORT datac (1581:1581:1581) (1621:1621:1621)) - (PORT datad (1040:1040:1040) (1037:1037:1037)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (701:701:701)) - (PORT datab (1788:1788:1788) (1788:1788:1788)) - (PORT datac (726:726:726) (711:711:711)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1146:1146:1146) (1185:1185:1185)) - (PORT datab (704:704:704) (664:664:664)) - (PORT datac (708:708:708) (670:670:670)) - (PORT datad (757:757:757) (726:726:726)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (978:978:978) (950:950:950)) - (PORT datab (530:530:530) (527:527:527)) - (PORT datac (633:633:633) (661:661:661)) - (PORT datad (781:781:781) (784:784:784)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~32) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) (DELAY (ABSOLUTE - (PORT dataa (1192:1192:1192) (1173:1173:1173)) - (PORT datab (1638:1638:1638) (1662:1662:1662)) - (PORT datac (1507:1507:1507) (1531:1531:1531)) - (PORT datad (781:781:781) (788:788:788)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~33) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (940:940:940)) - (PORT datab (199:199:199) (233:233:233)) - (PORT datac (1162:1162:1162) (1141:1141:1141)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1010:1010:1010) (984:984:984)) - (PORT datab (813:813:813) (800:800:800)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (514:514:514) (502:502:502)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1086:1086:1086)) - (PORT datad (979:979:979) (987:987:987)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1013:1013:1013) (1015:1015:1015)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (761:761:761) (729:729:729)) - (IOPATH dataa combout (272:272:272) (269:269:269)) + (PORT datab (786:786:786) (805:805:805)) + (PORT datac (919:919:919) (926:926:926)) + (PORT datad (1273:1273:1273) (1259:1259:1259)) (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (1150:1150:1150) (1159:1159:1159)) - (PORT datad (3024:3024:3024) (3116:3116:3116)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_DAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (459:459:459) (708:708:708)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (522:522:522) (514:514:514)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (343:343:343)) - (PORT datab (247:247:247) (330:330:330)) - (PORT datad (226:226:226) (293:293:293)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_CLK\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (459:459:459) (708:708:708)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1360:1360:1360)) - (PORT asdata (3274:3274:3274) (3523:3523:3523)) - (PORT clrn (1393:1393:1393) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (205:205:205) (267:267:267)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (219:219:219) (277:277:277)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (208:208:208) (268:268:268)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1360:1360:1360)) - (PORT asdata (514:514:514) (579:579:579)) - (PORT clrn (1393:1393:1393) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (208:208:208) (268:268:268)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (205:205:205) (267:267:267)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (427:427:427)) - (PORT datab (229:229:229) (299:299:299)) - (PORT datac (203:203:203) (272:272:272)) - (PORT datad (204:204:204) (264:264:264)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (306:306:306)) - (PORT datab (231:231:231) (303:303:303)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (205:205:205) (266:266:266)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -3127,917 +10302,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) (DELAY (ABSOLUTE - (PORT datad (206:206:206) (270:270:270)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (236:236:236)) - (PORT datad (207:207:207) (268:268:268)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (237:237:237)) - (PORT datac (195:195:195) (262:262:262)) - (PORT datad (208:208:208) (268:268:268)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1372:1372:1372)) - (PORT ena (1459:1459:1459) (1496:1496:1496)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (PORT datab (242:242:242) (317:317:317)) - (PORT datad (224:224:224) (293:293:293)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1372:1372:1372)) - (PORT ena (1459:1459:1459) (1496:1496:1496)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (344:344:344)) - (PORT datab (246:246:246) (330:330:330)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1372:1372:1372)) - (PORT ena (1459:1459:1459) (1496:1496:1496)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (335:335:335)) - (PORT datab (248:248:248) (334:334:334)) - (PORT datad (218:218:218) (285:285:285)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1372:1372:1372)) - (PORT ena (1459:1459:1459) (1496:1496:1496)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (PORT datab (246:246:246) (332:332:332)) - (PORT datac (3115:3115:3115) (3365:3365:3365)) - (PORT datad (226:226:226) (294:294:294)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (PORT datac (220:220:220) (304:304:304)) - (PORT datad (227:227:227) (296:296:296)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (223:223:223)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datac (868:868:868) (922:922:922)) - (PORT datad (220:220:220) (286:286:286)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1379:1379:1379)) - (PORT asdata (3469:3469:3469) (3713:3713:3713)) - (PORT clrn (1398:1398:1398) (1380:1380:1380)) - (PORT ena (1157:1157:1157) (1155:1155:1155)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1379:1379:1379)) - (PORT asdata (506:506:506) (569:569:569)) - (PORT clrn (1398:1398:1398) (1380:1380:1380)) - (PORT ena (1157:1157:1157) (1155:1155:1155)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1379:1379:1379)) - (PORT asdata (530:530:530) (609:609:609)) - (PORT clrn (1398:1398:1398) (1380:1380:1380)) - (PORT ena (1157:1157:1157) (1155:1155:1155)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) - (PORT asdata (1169:1169:1169) (1194:1194:1194)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1553:1553:1553) (1573:1573:1573)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1379:1379:1379)) - (PORT asdata (877:877:877) (907:907:907)) - (PORT clrn (1398:1398:1398) (1380:1380:1380)) - (PORT ena (1157:1157:1157) (1155:1155:1155)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) - (PORT asdata (1405:1405:1405) (1417:1417:1417)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1553:1553:1553) (1573:1573:1573)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) - (PORT asdata (865:865:865) (890:890:890)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1553:1553:1553) (1573:1573:1573)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1379:1379:1379)) - (PORT asdata (1372:1372:1372) (1381:1381:1381)) - (PORT clrn (1398:1398:1398) (1380:1380:1380)) - (PORT ena (1157:1157:1157) (1155:1155:1155)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) - (PORT asdata (1322:1322:1322) (1339:1339:1339)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1151:1151:1151) (1158:1158:1158)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1134:1134:1134) (1149:1149:1149)) - (PORT datab (415:415:415) (475:475:475)) - (PORT datac (592:592:592) (635:635:635)) - (PORT datad (1086:1086:1086) (1101:1101:1101)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (631:631:631)) - (PORT datab (248:248:248) (333:333:333)) - (PORT datad (583:583:583) (612:612:612)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (365:365:365)) - (PORT datac (505:505:505) (491:491:491)) - (PORT datad (223:223:223) (283:283:283)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) - (DELAY - (ABSOLUTE - (PORT dataa (900:900:900) (958:958:958)) - (PORT datab (191:191:191) (228:228:228)) - (PORT datac (3115:3115:3115) (3363:3363:3363)) - (PORT datad (495:495:495) (482:482:482)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1372:1372:1372)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1130:1130:1130)) - (PORT datab (604:604:604) (632:632:632)) - (PORT datac (219:219:219) (302:302:302)) - (PORT datad (850:850:850) (864:864:864)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (324:324:324)) - (PORT datab (183:183:183) (215:215:215)) - (PORT datac (1063:1063:1063) (1077:1077:1077)) - (PORT datad (581:581:581) (609:609:609)) + (PORT dataa (197:197:197) (241:241:241)) + (PORT datac (609:609:609) (621:621:621)) + (PORT datad (955:955:955) (992:992:992)) (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (933:933:933)) - (PORT datad (591:591:591) (592:592:592)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|extended) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1592:1592:1592) (1631:1631:1631)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (638:638:638)) - (PORT datab (247:247:247) (332:332:332)) - (PORT datac (615:615:615) (674:674:674)) - (PORT datad (652:652:652) (692:692:692)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (935:935:935)) - (PORT datab (1039:1039:1039) (1091:1091:1091)) - (PORT datad (591:591:591) (592:592:592)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1135:1135:1135) (1152:1152:1152)) - (PORT datab (408:408:408) (470:470:470)) - (PORT datac (597:597:597) (642:642:642)) - (PORT datad (1082:1082:1082) (1099:1099:1099)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1150:1150:1150)) - (PORT datac (593:593:593) (637:637:637)) - (PORT datad (385:385:385) (443:443:443)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1133:1133:1133) (1152:1152:1152)) - (PORT datab (415:415:415) (475:475:475)) - (PORT datac (593:593:593) (636:636:636)) - (PORT datad (1086:1086:1086) (1101:1101:1101)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (242:242:242)) - (PORT datab (433:433:433) (481:481:481)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (1082:1082:1082) (1100:1100:1100)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (433:433:433) (482:482:482)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (616:616:616) (656:656:656)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datab (902:902:902) (932:932:932)) - (PORT datad (302:302:302) (300:300:300)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1324:1324:1324)) - (PORT datab (1106:1106:1106) (1100:1100:1100)) - (PORT datac (742:742:742) (735:735:735)) - (PORT datad (878:878:878) (914:914:914)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1727:1727:1727) (1797:1797:1797)) - (PORT datab (1586:1586:1586) (1637:1637:1637)) - (PORT datac (1574:1574:1574) (1630:1630:1630)) - (PORT datad (1248:1248:1248) (1284:1284:1284)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT datab (1284:1284:1284) (1331:1331:1331)) - (PORT datac (1573:1573:1573) (1627:1627:1627)) - (PORT datad (1557:1557:1557) (1605:1605:1605)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1161:1161:1161)) - (PORT datab (1099:1099:1099) (1117:1117:1117)) - (PORT datad (1276:1276:1276) (1279:1279:1279)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (814:814:814)) - (PORT datab (856:856:856) (866:866:866)) - (PORT datac (740:740:740) (734:734:734)) - (PORT datad (727:727:727) (713:713:713)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (815:815:815)) - (PORT datab (1064:1064:1064) (1066:1066:1066)) - (PORT datac (747:747:747) (736:736:736)) - (PORT datad (190:190:190) (220:220:220)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (188:188:188) (221:221:221)) - (PORT datac (173:173:173) (204:204:204)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1167:1167:1167)) - (PORT datab (1083:1083:1083) (1096:1096:1096)) - (PORT datac (511:511:511) (516:516:516)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (784:784:784)) - (PORT datab (801:801:801) (788:788:788)) - (PORT datac (505:505:505) (502:502:502)) - (PORT datad (795:795:795) (785:785:785)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (952:952:952)) - (PORT datad (1087:1087:1087) (1133:1133:1133)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1048:1048:1048) (1028:1028:1028)) - (PORT datab (631:631:631) (653:653:653)) - (PORT datac (1044:1044:1044) (1040:1040:1040)) - (PORT datad (967:967:967) (950:950:950)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1098:1098:1098) (1127:1127:1127)) - (PORT datab (187:187:187) (221:221:221)) - (PORT datac (1043:1043:1043) (1040:1040:1040)) - (PORT datad (576:576:576) (573:573:573)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (850:850:850) (867:867:867)) - (PORT datac (1041:1041:1041) (1044:1044:1044)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT datab (1082:1082:1082) (1093:1093:1093)) - (PORT datac (1219:1219:1219) (1240:1240:1240)) - (PORT datad (1071:1071:1071) (1100:1100:1100)) - (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -4048,12 +10319,10 @@ (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (603:603:603)) - (PORT datab (776:776:776) (786:786:786)) - (PORT datac (1136:1136:1136) (1086:1086:1086)) - (PORT datad (779:779:779) (783:783:783)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (1226:1226:1226) (1317:1317:1317)) + (PORT datac (1093:1093:1093) (1091:1091:1091)) + (PORT datad (1863:1863:1863) (1900:1900:1900)) + (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -4061,14 +10330,232 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) (DELAY (ABSOLUTE - (PORT dataa (1586:1586:1586) (1610:1610:1610)) - (PORT datab (870:870:870) (924:924:924)) - (PORT datac (1089:1089:1089) (1111:1111:1111)) - (PORT datad (1585:1585:1585) (1569:1569:1569)) - (IOPATH dataa combout (299:299:299) (304:304:304)) + (PORT dataa (1036:1036:1036) (1029:1029:1029)) + (PORT datab (204:204:204) (240:240:240)) + (PORT datac (557:557:557) (554:554:554)) + (PORT datad (1064:1064:1064) (1079:1079:1079)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1023:1023:1023) (1113:1113:1113)) + (PORT datac (1050:1050:1050) (1044:1044:1044)) + (PORT datad (880:880:880) (917:917:917)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT datab (1942:1942:1942) (1961:1961:1961)) + (PORT datac (856:856:856) (896:896:896)) + (PORT datad (1825:1825:1825) (1843:1843:1843)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1094:1094:1094) (1117:1117:1117)) + (PORT datab (565:565:565) (549:549:549)) + (PORT datac (806:806:806) (820:820:820)) + (PORT datad (1059:1059:1059) (1068:1068:1068)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1048:1048:1048) (1033:1033:1033)) + (PORT datab (553:553:553) (543:543:543)) + (PORT datac (1042:1042:1042) (1045:1045:1045)) + (PORT datad (810:810:810) (811:811:811)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1663:1663:1663) (1690:1690:1690)) + (PORT datab (1460:1460:1460) (1462:1462:1462)) + (PORT datad (920:920:920) (921:921:921)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (853:853:853)) + (PORT datab (1074:1074:1074) (1100:1100:1100)) + (PORT datac (1370:1370:1370) (1409:1409:1409)) + (PORT datad (1025:1025:1025) (1017:1017:1017)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (656:656:656)) + (PORT datab (843:843:843) (834:834:834)) + (PORT datac (575:575:575) (572:572:572)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (182:182:182) (213:213:213)) + (PORT datac (1401:1401:1401) (1413:1413:1413)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (855:855:855)) + (PORT datab (829:829:829) (870:870:870)) + (PORT datac (169:169:169) (207:207:207)) + (PORT datad (816:816:816) (798:798:798)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (1591:1591:1591) (1613:1613:1613)) + (PORT datad (303:303:303) (314:314:314)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1097:1097:1097)) + (PORT datab (780:780:780) (766:766:766)) + (PORT datac (784:784:784) (778:778:778)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1431:1431:1431) (1492:1492:1492)) + (PORT datab (1625:1625:1625) (1632:1632:1632)) + (PORT datac (2403:2403:2403) (2409:2409:2409)) + (PORT datad (1067:1067:1067) (1081:1081:1081)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (2438:2438:2438) (2445:2445:2445)) + (PORT datab (1459:1459:1459) (1552:1552:1552)) + (PORT datac (581:581:581) (581:581:581)) + (PORT datad (185:185:185) (212:212:212)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (563:563:563)) + (PORT datab (604:604:604) (616:616:616)) + (PORT datac (583:583:583) (607:607:607)) + (PORT datad (790:790:790) (806:806:806)) + (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -4077,15 +10564,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) (DELAY (ABSOLUTE - (PORT dataa (2151:2151:2151) (2072:2072:2072)) - (PORT datab (850:850:850) (845:845:845)) - (PORT datac (854:854:854) (901:901:901)) - (PORT datad (876:876:876) (914:914:914)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT datab (659:659:659) (665:665:665)) + (PORT datac (981:981:981) (963:963:963)) + (PORT datad (842:842:842) (856:856:856)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (357:357:357)) + (PORT datab (1036:1036:1036) (1034:1034:1034)) + (PORT datac (965:965:965) (955:955:955)) + (PORT datad (773:773:773) (761:761:761)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1599:1599:1599) (1605:1605:1605)) + (PORT datab (824:824:824) (816:816:816)) + (PORT datac (1393:1393:1393) (1460:1460:1460)) + (PORT datad (1048:1048:1048) (1075:1075:1075)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1064:1064:1064) (1034:1034:1034)) + (PORT datab (1534:1534:1534) (1529:1529:1529)) + (PORT datac (1059:1059:1059) (1072:1072:1072)) + (PORT datad (194:194:194) (224:224:224)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -4096,12 +10629,26 @@ (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) (DELAY (ABSOLUTE - (PORT dataa (188:188:188) (226:226:226)) - (PORT datab (803:803:803) (800:800:800)) - (PORT datac (892:892:892) (955:955:955)) - (PORT datad (885:885:885) (940:940:940)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (PORT dataa (621:621:621) (626:626:626)) + (PORT datab (1072:1072:1072) (1065:1065:1065)) + (PORT datac (1092:1092:1092) (1109:1109:1109)) + (PORT datad (891:891:891) (936:936:936)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~1) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (330:330:330)) + (PORT datac (1563:1563:1563) (1574:1574:1574)) + (PORT datad (394:394:394) (428:428:428)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -4109,43 +10656,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) (DELAY (ABSOLUTE - (PORT dataa (196:196:196) (240:240:240)) - (PORT datab (1167:1167:1167) (1162:1162:1162)) - (PORT datac (1715:1715:1715) (1686:1686:1686)) - (PORT datad (827:827:827) (819:819:819)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1200:1200:1200)) - (PORT datac (1226:1226:1226) (1251:1251:1251)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT dataa (611:611:611) (623:623:623)) + (PORT datab (1068:1068:1068) (1096:1096:1096)) + (PORT datac (1370:1370:1370) (1407:1407:1407)) + (PORT datad (1176:1176:1176) (1194:1194:1194)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) (DELAY (ABSOLUTE - (PORT dataa (893:893:893) (940:940:940)) - (PORT datab (1028:1028:1028) (997:997:997)) - (PORT datac (1281:1281:1281) (1266:1266:1266)) - (PORT datad (845:845:845) (862:862:862)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (PORT dataa (1333:1333:1333) (1335:1335:1335)) + (PORT datab (846:846:846) (864:864:864)) + (PORT datac (830:830:830) (829:829:829)) + (PORT datad (893:893:893) (897:897:897)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -4153,14 +10688,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) (DELAY (ABSOLUTE - (PORT dataa (2166:2166:2166) (2175:2175:2175)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (608:608:608) (619:619:619)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (272:272:272) (269:269:269)) + (PORT dataa (814:814:814) (806:806:806)) + (PORT datac (924:924:924) (944:944:944)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1014:1014:1014)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1006:1006:1006) (987:987:987)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -4169,27 +10718,582 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) (DELAY (ABSOLUTE - (PORT dataa (1202:1202:1202) (1177:1177:1177)) - (PORT datab (1043:1043:1043) (1024:1024:1024)) - (PORT datac (1144:1144:1144) (1105:1105:1105)) - (PORT datad (1000:1000:1000) (977:977:977)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT dataa (322:322:322) (331:331:331)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (320:320:320) (344:344:344)) + (PORT datad (793:793:793) (779:779:779)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1282:1282:1282)) + (PORT datab (770:770:770) (753:753:753)) + (PORT datac (1562:1562:1562) (1571:1571:1571)) + (PORT datad (851:851:851) (864:864:864)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1026:1026:1026)) + (PORT datab (620:620:620) (624:624:624)) + (PORT datac (805:805:805) (782:782:782)) + (PORT datad (811:811:811) (819:819:819)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (249:249:249)) + (PORT datab (594:594:594) (608:608:608)) + (PORT datac (1273:1273:1273) (1300:1300:1300)) + (PORT datad (1052:1052:1052) (1059:1059:1059)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1503:1503:1503) (1574:1574:1574)) + (PORT datab (939:939:939) (984:984:984)) + (PORT datac (1792:1792:1792) (1771:1771:1771)) + (PORT datad (1535:1535:1535) (1547:1547:1547)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (237:237:237)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (598:598:598) (624:624:624)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (598:598:598) (591:591:591)) + (PORT datac (181:181:181) (215:215:215)) + (PORT datad (1100:1100:1100) (1080:1080:1080)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (949:949:949) (970:970:970)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (552:552:552) (562:562:562)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (859:859:859)) + (PORT datab (1049:1049:1049) (1051:1051:1051)) + (PORT datac (814:814:814) (819:819:819)) + (PORT datad (1055:1055:1055) (1070:1070:1070)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) + (DELAY + (ABSOLUTE + (PORT datab (199:199:199) (231:231:231)) + (PORT datac (547:547:547) (579:579:579)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (238:238:238)) + (PORT datac (514:514:514) (511:511:511)) + (PORT datad (750:750:750) (794:794:794)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1239:1239:1239)) + (PORT datab (610:610:610) (611:611:611)) + (PORT datac (176:176:176) (208:208:208)) + (PORT datad (1090:1090:1090) (1098:1098:1098)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (521:521:521)) + (PORT datac (731:731:731) (762:762:762)) + (PORT datad (724:724:724) (755:755:755)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (850:850:850)) + (PORT datab (615:615:615) (631:631:631)) + (PORT datac (349:349:349) (360:360:360)) + (PORT datad (549:549:549) (569:569:569)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (619:619:619)) + (PORT datab (810:810:810) (784:784:784)) + (PORT datac (794:794:794) (808:808:808)) + (PORT datad (591:591:591) (614:614:614)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~46) + (DELAY + (ABSOLUTE + (PORT datab (767:767:767) (753:753:753)) + (PORT datac (180:180:180) (215:215:215)) + (PORT datad (1316:1316:1316) (1348:1348:1348)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (542:542:542)) + (PORT datab (860:860:860) (874:874:874)) + (PORT datac (541:541:541) (537:537:537)) + (PORT datad (552:552:552) (548:548:548)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (904:904:904)) + (PORT datab (1439:1439:1439) (1492:1492:1492)) + (PORT datac (778:778:778) (780:780:780)) + (PORT datad (347:347:347) (357:357:357)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (225:225:225)) + (PORT datab (317:317:317) (334:334:334)) + (PORT datac (189:189:189) (227:227:227)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (859:859:859)) + (PORT datac (801:801:801) (843:843:843)) + (PORT datad (777:777:777) (765:765:765)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (609:609:609)) + (PORT datab (1386:1386:1386) (1385:1385:1385)) + (PORT datac (759:759:759) (755:755:755)) + (PORT datad (767:767:767) (781:781:781)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (456:456:456)) + (PORT datab (863:863:863) (880:880:880)) + (PORT datac (347:347:347) (362:362:362)) + (PORT datad (1765:1765:1765) (1823:1823:1823)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) + (DELAY + (ABSOLUTE + (PORT dataa (2276:2276:2276) (2425:2425:2425)) + (PORT datab (513:513:513) (511:511:511)) + (PORT datac (825:825:825) (840:840:840)) + (PORT datad (1041:1041:1041) (1050:1050:1050)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (620:620:620)) + (PORT datab (539:539:539) (531:531:531)) + (PORT datac (725:725:725) (754:754:754)) + (PORT datad (184:184:184) (208:208:208)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (551:551:551)) + (PORT datab (811:811:811) (812:812:812)) + (PORT datac (1834:1834:1834) (1833:1833:1833)) + (PORT datad (558:558:558) (552:552:552)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1067:1067:1067) (1036:1036:1036)) + (PORT datab (1449:1449:1449) (1509:1509:1509)) + (PORT datac (592:592:592) (615:615:615)) + (PORT datad (560:560:560) (573:573:573)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (822:822:822)) + (PORT datab (522:522:522) (518:518:518)) + (PORT datac (567:567:567) (580:580:580)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (608:608:608)) + (PORT datab (843:843:843) (873:873:873)) + (PORT datac (499:499:499) (485:485:485)) + (PORT datad (808:808:808) (804:804:804)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (249:249:249)) + (PORT datab (604:604:604) (610:610:610)) + (PORT datac (777:777:777) (770:770:770)) + (PORT datad (321:321:321) (324:324:324)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT datab (1339:1339:1339) (1361:1361:1361)) + (PORT datac (845:845:845) (849:849:849)) + (PORT datad (758:758:758) (746:746:746)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (249:249:249)) + (PORT datab (1244:1244:1244) (1192:1192:1192)) + (PORT datac (1279:1279:1279) (1261:1261:1261)) + (PORT datad (291:291:291) (298:298:298)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT datab (868:868:868) (895:895:895)) + (PORT datac (1335:1335:1335) (1361:1361:1361)) + (PORT datad (622:622:622) (633:633:633)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT asdata (890:890:890) (916:916:916)) + (PORT ena (1105:1105:1105) (1078:1078:1078)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1743:1743:1743) (1706:1706:1706)) + (PORT datab (649:649:649) (667:667:667)) + (PORT datad (1111:1111:1111) (1126:1126:1126)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT datab (661:661:661) (663:663:663)) + (PORT datac (983:983:983) (964:964:964)) + (PORT datad (844:844:844) (855:855:855)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1175:1175:1175) (1170:1170:1170)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (677:677:677) (704:704:704)) + (PORT datac (571:571:571) (586:586:586)) + (PORT datad (198:198:198) (256:256:256)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT datad (1070:1070:1070) (1111:1111:1111)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (1855:1855:1855) (1856:1856:1856)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -4198,7 +11302,7 @@ (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) (DELAY (ABSOLUTE - (PORT clk (1360:1360:1360) (1368:1368:1368)) + (PORT clk (1370:1370:1370) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -4207,37 +11311,13 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (204:204:204) (265:265:265)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) (DELAY (ABSOLUTE - (PORT clk (1360:1360:1360) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1368:1368:1368)) - (PORT asdata (512:512:512) (578:578:578)) + (PORT clk (1370:1370:1370) (1377:1377:1377)) + (PORT asdata (513:513:513) (580:580:580)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -4245,16 +11325,100 @@ (HOLD asdata (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1370:1370:1370) (1377:1377:1377)) + (PORT asdata (513:513:513) (581:581:581)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE KEY\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (461:461:461) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE reset) + (DELAY + (ABSOLUTE + (PORT datac (1395:1395:1395) (1420:1420:1420)) + (PORT datad (490:490:490) (462:462:462)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x1\~0) + (DELAY + (ABSOLUTE + (PORT datad (1368:1368:1368) (1388:1388:1388)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|fpga_reset) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|fpga_reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (666:666:666) (673:673:673)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|x1) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1667:1667:1667) (1646:1646:1646)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|resets_\|clrpc_int\~0) (DELAY (ABSOLUTE - (PORT dataa (873:873:873) (892:892:892)) - (PORT datab (871:871:871) (928:928:928)) - (PORT datad (846:846:846) (852:852:852)) - (IOPATH dataa combout (273:273:273) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (604:604:604) (644:644:644)) + (PORT datab (568:568:568) (588:588:588)) + (PORT datad (1091:1091:1091) (1101:1101:1101)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (312:312:312)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -4265,9 +11429,9 @@ (INSTANCE z80_\|resets_\|clrpc_int) (DELAY (ABSOLUTE - (PORT clk (1360:1360:1360) (1368:1368:1368)) + (PORT clk (1370:1370:1370) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1367:1367:1367)) + (PORT clrn (1409:1409:1409) (1380:1380:1380)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -4282,8367 +11446,10 @@ (DELAY (ABSOLUTE (PORT dataa (228:228:228) (302:302:302)) - (PORT datab (226:226:226) (296:296:296)) - (PORT datad (200:200:200) (257:257:257)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) - (DELAY - (ABSOLUTE - (PORT datab (541:541:541) (547:547:547)) - (PORT datac (1056:1056:1056) (1069:1069:1069)) - (PORT datad (1231:1231:1231) (1213:1213:1213)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1583:1583:1583) (1607:1607:1607)) - (PORT datab (751:751:751) (745:745:745)) - (PORT datac (1201:1201:1201) (1176:1176:1176)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal38\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2016:2016:2016) (2014:2014:2014)) - (PORT datab (1741:1741:1741) (1752:1752:1752)) - (PORT datac (1354:1354:1354) (1290:1290:1290)) - (PORT datad (1516:1516:1516) (1529:1529:1529)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) - (DELAY - (ABSOLUTE - (PORT datac (1667:1667:1667) (1643:1643:1643)) - (PORT datad (1487:1487:1487) (1462:1462:1462)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (414:414:414)) - (PORT datab (230:230:230) (281:281:281)) - (PORT datac (1960:1960:1960) (1968:1968:1968)) - (PORT datad (1272:1272:1272) (1263:1263:1263)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (839:839:839)) - (PORT datab (653:653:653) (672:672:672)) - (PORT datac (945:945:945) (913:913:913)) - (PORT datad (1526:1526:1526) (1534:1534:1534)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1034:1034:1034)) - (PORT datab (861:861:861) (877:877:877)) - (PORT datac (568:568:568) (575:575:575)) - (PORT datad (1489:1489:1489) (1517:1517:1517)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1569:1569:1569) (1573:1573:1573)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (769:769:769) (774:774:774)) - (PORT datad (618:618:618) (638:638:638)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1784:1784:1784) (1800:1800:1800)) - (PORT datab (533:533:533) (520:520:520)) - (PORT datac (1099:1099:1099) (1114:1114:1114)) - (PORT datad (2135:2135:2135) (2121:2121:2121)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (783:783:783)) - (PORT datab (1539:1539:1539) (1563:1563:1563)) - (PORT datac (1164:1164:1164) (1139:1139:1139)) - (PORT datad (796:796:796) (783:783:783)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1394:1394:1394) (1402:1402:1402)) - (PORT datab (1175:1175:1175) (1169:1169:1169)) - (PORT datac (1978:1978:1978) (1983:1983:1983)) - (PORT datad (852:852:852) (882:882:882)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT datac (2297:2297:2297) (2290:2290:2290)) - (PORT datad (2186:2186:2186) (2179:2179:2179)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (750:750:750) (731:731:731)) - (PORT datab (1128:1128:1128) (1143:1143:1143)) - (PORT datac (492:492:492) (483:483:483)) - (PORT datad (2137:2137:2137) (2123:2123:2123)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (193:193:193) (229:229:229)) - (PORT datac (880:880:880) (928:928:928)) - (PORT datad (1220:1220:1220) (1215:1215:1215)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (581:581:581)) - (PORT datab (588:588:588) (599:599:599)) - (PORT datac (757:757:757) (747:747:747)) - (PORT datad (968:968:968) (912:912:912)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (870:870:870)) - (PORT datac (1006:1006:1006) (1000:1000:1000)) - (PORT datad (1708:1708:1708) (1696:1696:1696)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1106:1106:1106)) - (PORT datab (977:977:977) (974:974:974)) - (PORT datac (1177:1177:1177) (1168:1168:1168)) - (PORT datad (2719:2719:2719) (2705:2705:2705)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (796:796:796)) - (PORT datab (2274:2274:2274) (2271:2271:2271)) - (PORT datac (808:808:808) (806:806:806)) - (PORT datad (2715:2715:2715) (2699:2699:2699)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (844:844:844)) - (PORT datab (1054:1054:1054) (1076:1076:1076)) - (PORT datac (1524:1524:1524) (1529:1529:1529)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (871:871:871) (859:859:859)) - (PORT datab (872:872:872) (927:927:927)) - (PORT datac (1202:1202:1202) (1176:1176:1176)) - (PORT datad (1087:1087:1087) (1106:1106:1106)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (237:237:237)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (973:973:973) (963:963:963)) - (PORT datab (1287:1287:1287) (1338:1338:1338)) - (PORT datac (1569:1569:1569) (1621:1621:1621)) - (PORT datad (1563:1563:1563) (1606:1606:1606)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1237:1237:1237) (1243:1243:1243)) - (PORT datab (570:570:570) (595:595:595)) - (PORT datac (1353:1353:1353) (1340:1340:1340)) - (PORT datad (869:869:869) (885:885:885)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT dataa (1070:1070:1070) (1087:1087:1087)) - (PORT datac (534:534:534) (545:545:545)) - (PORT datad (1253:1253:1253) (1236:1236:1236)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (352:352:352)) - (PORT datab (819:819:819) (813:813:813)) - (PORT datac (1043:1043:1043) (1049:1049:1049)) - (PORT datad (1462:1462:1462) (1468:1468:1468)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (991:991:991)) - (PORT datac (948:948:948) (934:934:934)) - (PORT datad (888:888:888) (943:943:943)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2740:2740:2740) (2741:2741:2741)) - (PORT datab (2274:2274:2274) (2276:2276:2276)) - (PORT datac (767:767:767) (769:769:769)) - (PORT datad (1064:1064:1064) (1071:1071:1071)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (929:929:929)) - (PORT datab (1218:1218:1218) (1216:1216:1216)) - (PORT datac (767:767:767) (767:767:767)) - (PORT datad (1502:1502:1502) (1535:1535:1535)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (789:789:789)) - (PORT datab (817:817:817) (829:829:829)) - (PORT datac (777:777:777) (783:783:783)) - (PORT datad (573:573:573) (581:581:581)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1104:1104:1104)) - (PORT datab (981:981:981) (981:981:981)) - (PORT datac (1172:1172:1172) (1163:1163:1163)) - (PORT datad (2714:2714:2714) (2698:2698:2698)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (774:774:774)) - (PORT datab (976:976:976) (1022:1022:1022)) - (PORT datac (603:603:603) (667:667:667)) - (PORT datad (921:921:921) (918:918:918)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (618:618:618)) - (PORT datab (802:802:802) (782:782:782)) - (PORT datad (767:767:767) (767:767:767)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (966:966:966)) - (PORT datab (602:602:602) (589:589:589)) - (PORT datac (948:948:948) (910:910:910)) - (PORT datad (815:815:815) (823:823:823)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2168:2168:2168) (2171:2171:2171)) - (PORT datab (878:878:878) (895:895:895)) - (PORT datac (1398:1398:1398) (1360:1360:1360)) - (PORT datad (743:743:743) (731:731:731)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1147:1147:1147) (1173:1173:1173)) - (PORT datab (189:189:189) (227:227:227)) - (PORT datac (164:164:164) (198:198:198)) - (PORT datad (788:788:788) (773:773:773)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (829:829:829)) - (PORT datab (787:787:787) (776:776:776)) - (PORT datac (490:490:490) (478:478:478)) - (PORT datad (745:745:745) (733:733:733)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT datab (1288:1288:1288) (1339:1339:1339)) - (PORT datac (1569:1569:1569) (1616:1616:1616)) - (PORT datad (1562:1562:1562) (1607:1607:1607)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (633:633:633)) - (PORT datab (796:796:796) (824:824:824)) - (PORT datac (827:827:827) (871:871:871)) - (PORT datad (1707:1707:1707) (1663:1663:1663)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datab (904:904:904) (950:950:950)) - (PORT datac (880:880:880) (923:923:923)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (903:903:903)) - (PORT datab (799:799:799) (821:821:821)) - (PORT datac (1065:1065:1065) (1053:1053:1053)) - (PORT datad (1705:1705:1705) (1660:1660:1660)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1732:1732:1732) (1703:1703:1703)) - (PORT datab (796:796:796) (822:822:822)) - (PORT datac (827:827:827) (871:871:871)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1290:1290:1290)) - (PORT datab (818:818:818) (795:795:795)) - (PORT datac (889:889:889) (912:912:912)) - (PORT datad (1117:1117:1117) (1133:1133:1133)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1291:1291:1291)) - (PORT datab (1144:1144:1144) (1169:1169:1169)) - (PORT datac (896:896:896) (917:917:917)) - (PORT datad (1054:1054:1054) (1040:1040:1040)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (198:198:198) (231:231:231)) - (PORT datac (182:182:182) (217:217:217)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT datac (2302:2302:2302) (2297:2297:2297)) - (PORT datad (2190:2190:2190) (2185:2185:2185)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (250:250:250)) - (PORT datab (1302:1302:1302) (1307:1307:1307)) - (PORT datac (1185:1185:1185) (1153:1153:1153)) - (PORT datad (193:193:193) (221:221:221)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (827:827:827)) - (PORT datab (993:993:993) (978:978:978)) - (PORT datac (689:689:689) (661:661:661)) - (PORT datad (1001:1001:1001) (965:965:965)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (620:620:620)) - (PORT datab (187:187:187) (224:224:224)) - (PORT datac (495:495:495) (484:484:484)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2854:2854:2854) (2837:2837:2837)) - (PORT datab (2008:2008:2008) (2019:2019:2019)) - (PORT datac (779:779:779) (788:788:788)) - (PORT datad (959:959:959) (926:926:926)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (822:822:822)) - (PORT datab (1488:1488:1488) (1497:1497:1497)) - (PORT datac (764:764:764) (780:780:780)) - (PORT datad (825:825:825) (850:850:850)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (218:218:218)) - (PORT datab (1194:1194:1194) (1155:1155:1155)) - (PORT datac (936:936:936) (942:942:942)) - (PORT datad (629:629:629) (671:671:671)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1161:1161:1161) (1199:1199:1199)) - (PORT datab (838:838:838) (834:834:834)) - (PORT datac (804:804:804) (824:824:824)) - (PORT datad (1558:1558:1558) (1565:1565:1565)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1207:1207:1207) (1172:1172:1172)) - (PORT datab (1636:1636:1636) (1659:1659:1659)) - (PORT datac (943:943:943) (934:934:934)) - (PORT datad (754:754:754) (755:755:755)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1161:1161:1161) (1198:1198:1198)) - (PORT datab (1177:1177:1177) (1144:1144:1144)) - (PORT datac (767:767:767) (756:756:756)) - (PORT datad (1558:1558:1558) (1565:1565:1565)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1203:1203:1203)) - (PORT datab (199:199:199) (233:233:233)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1556:1556:1556) (1568:1568:1568)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (227:227:227)) - (PORT datab (800:800:800) (787:787:787)) - (PORT datac (991:991:991) (966:966:966)) - (PORT datad (163:163:163) (188:188:188)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (778:778:778) (786:786:786)) - (PORT datab (543:543:543) (533:533:533)) - (PORT datac (694:694:694) (673:673:673)) - (PORT datad (1217:1217:1217) (1203:1203:1203)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (848:848:848)) - (PORT datab (1555:1555:1555) (1555:1555:1555)) - (PORT datac (1125:1125:1125) (1165:1165:1165)) - (PORT datad (1033:1033:1033) (1045:1045:1045)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (841:841:841)) - (PORT datab (1054:1054:1054) (1077:1077:1077)) - (PORT datac (1523:1523:1523) (1530:1530:1530)) - (PORT datad (809:809:809) (825:825:825)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (609:609:609) (616:616:616)) - (PORT datac (594:594:594) (619:619:619)) - (PORT datad (981:981:981) (964:964:964)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (778:778:778)) - (PORT datab (577:577:577) (562:562:562)) - (PORT datad (163:163:163) (188:188:188)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT datab (1167:1167:1167) (1238:1238:1238)) - (PORT datac (1083:1083:1083) (1135:1135:1135)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1283:1283:1283) (1266:1266:1266)) - (PORT datab (339:339:339) (363:363:363)) - (PORT datac (1138:1138:1138) (1096:1096:1096)) - (PORT datad (735:735:735) (734:734:734)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1076:1076:1076)) - (PORT datab (1044:1044:1044) (1041:1041:1041)) - (PORT datac (1020:1020:1020) (1029:1029:1029)) - (PORT datad (959:959:959) (926:926:926)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (2005:2005:2005) (2019:2019:2019)) - (PORT datac (780:780:780) (791:791:791)) - (PORT datad (962:962:962) (936:936:936)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (785:785:785) (781:781:781)) - (PORT datab (653:653:653) (702:702:702)) - (PORT datac (593:593:593) (606:606:606)) - (PORT datad (955:955:955) (922:922:922)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (956:956:956) (947:947:947)) - (PORT datab (1998:1998:1998) (1984:1984:1984)) - (PORT datac (2059:2059:2059) (2056:2056:2056)) - (PORT datad (1345:1345:1345) (1403:1403:1403)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal69\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1210:1210:1210) (1185:1185:1185)) - (PORT datab (1302:1302:1302) (1314:1314:1314)) - (PORT datac (2301:2301:2301) (2296:2296:2296)) - (PORT datad (2187:2187:2187) (2185:2185:2185)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1266:1266:1266) (1229:1229:1229)) - (PORT datab (1065:1065:1065) (1100:1100:1100)) - (PORT datac (799:799:799) (789:789:789)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (622:622:622)) - (PORT datab (233:233:233) (277:277:277)) - (PORT datad (186:186:186) (214:214:214)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1751:1751:1751) (1754:1754:1754)) - (PORT datab (201:201:201) (242:242:242)) - (PORT datac (515:515:515) (514:514:514)) - (PORT datad (171:171:171) (199:199:199)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (285:285:285) (373:373:373)) - (PORT datab (219:219:219) (252:252:252)) - (PORT datac (487:487:487) (471:471:471)) - (PORT datad (268:268:268) (341:341:341)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (636:636:636)) - (PORT datab (762:762:762) (760:760:760)) - (PORT datac (808:808:808) (818:818:818)) - (PORT datad (373:373:373) (408:408:408)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1102:1102:1102)) - (PORT datab (1010:1010:1010) (996:996:996)) - (PORT datac (1144:1144:1144) (1226:1226:1226)) - (PORT datad (1276:1276:1276) (1274:1274:1274)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1267:1267:1267) (1284:1284:1284)) - (PORT datab (555:555:555) (551:551:551)) - (PORT datac (1002:1002:1002) (988:988:988)) - (PORT datad (2616:2616:2616) (2586:2586:2586)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1333:1333:1333)) - (PORT datab (2193:2193:2193) (2190:2190:2190)) - (PORT datac (1320:1320:1320) (1365:1365:1365)) - (PORT datad (2197:2197:2197) (2184:2184:2184)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1539:1539:1539) (1563:1563:1563)) - (PORT datab (1704:1704:1704) (1775:1775:1775)) - (PORT datad (1971:1971:1971) (1970:1970:1970)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1548:1548:1548) (1553:1553:1553)) - (PORT datab (1545:1545:1545) (1572:1572:1572)) - (PORT datac (1000:1000:1000) (984:984:984)) - (PORT datad (1707:1707:1707) (1704:1704:1704)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (256:256:256)) - (PORT datab (1122:1122:1122) (1126:1126:1126)) - (PORT datac (799:799:799) (801:801:801)) - (PORT datad (1063:1063:1063) (1082:1082:1082)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT datab (1584:1584:1584) (1641:1641:1641)) - (PORT datac (1573:1573:1573) (1629:1629:1629)) - (PORT datad (1680:1680:1680) (1754:1754:1754)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1199:1199:1199) (1169:1169:1169)) - (PORT datab (798:798:798) (802:802:802)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (562:562:562) (566:566:566)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1034:1034:1034) (1049:1049:1049)) - (PORT datab (1095:1095:1095) (1093:1093:1093)) - (PORT datac (1655:1655:1655) (1656:1656:1656)) - (PORT datad (960:960:960) (928:928:928)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1779:1779:1779) (1786:1786:1786)) - (PORT datab (1033:1033:1033) (1026:1026:1026)) - (PORT datac (1045:1045:1045) (1076:1076:1076)) - (PORT datad (1676:1676:1676) (1669:1669:1669)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT dataa (2465:2465:2465) (2474:2474:2474)) - (PORT datac (489:489:489) (485:485:485)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (407:407:407)) - (PORT datab (1269:1269:1269) (1272:1272:1272)) - (PORT datac (1253:1253:1253) (1266:1266:1266)) - (PORT datad (352:352:352) (352:352:352)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (561:561:561)) - (PORT datab (864:864:864) (870:870:870)) - (PORT datac (156:156:156) (185:185:185)) - (PORT datad (1055:1055:1055) (1058:1058:1058)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1379:1379:1379) (1370:1370:1370)) - (PORT datab (1195:1195:1195) (1194:1194:1194)) - (PORT datac (541:541:541) (563:563:563)) - (PORT datad (560:560:560) (562:562:562)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1537:1537:1537) (1542:1542:1542)) - (PORT datab (1263:1263:1263) (1252:1252:1252)) - (PORT datac (488:488:488) (482:482:482)) - (PORT datad (585:585:585) (600:600:600)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1266:1266:1266) (1281:1281:1281)) - (PORT datab (552:552:552) (547:547:547)) - (PORT datac (999:999:999) (988:988:988)) - (PORT datad (2620:2620:2620) (2591:2591:2591)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT datac (523:523:523) (520:520:520)) - (PORT datad (993:993:993) (968:968:968)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (857:857:857) (897:897:897)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (550:550:550)) - (PORT datab (968:968:968) (1012:1012:1012)) - (PORT datac (1163:1163:1163) (1133:1133:1133)) - (PORT datad (1036:1036:1036) (1052:1052:1052)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (805:805:805)) - (PORT datab (603:603:603) (597:597:597)) - (PORT datac (1034:1034:1034) (1034:1034:1034)) - (PORT datad (1213:1213:1213) (1187:1187:1187)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1657:1657:1657)) - (PORT datab (652:652:652) (700:700:700)) - (PORT datac (326:326:326) (340:340:340)) - (PORT datad (1157:1157:1157) (1115:1115:1115)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (371:371:371)) - (PORT datab (1002:1002:1002) (1005:1005:1005)) - (PORT datac (935:935:935) (943:943:943)) - (PORT datad (1158:1158:1158) (1116:1116:1116)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1055:1055:1055)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (780:780:780) (784:784:784)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (1757:1757:1757) (1811:1811:1811)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (1235:1235:1235) (1258:1258:1258)) - (PORT datad (814:814:814) (791:791:791)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (1827:1827:1827) (1858:1858:1858)) - (PORT datab (848:848:848) (845:845:845)) - (PORT datac (856:856:856) (904:904:904)) - (PORT datad (876:876:876) (916:916:916)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1073:1073:1073) (1063:1063:1063)) - (PORT datab (999:999:999) (1017:1017:1017)) - (PORT datac (1050:1050:1050) (1036:1036:1036)) - (PORT datad (940:940:940) (911:911:911)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1096:1096:1096)) - (PORT datab (1113:1113:1113) (1127:1127:1127)) - (PORT datac (1282:1282:1282) (1295:1295:1295)) - (PORT datad (983:983:983) (963:963:963)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (263:263:263)) - (PORT datab (1327:1327:1327) (1321:1321:1321)) - (PORT datac (1140:1140:1140) (1225:1225:1225)) - (PORT datad (1056:1056:1056) (1055:1055:1055)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1310:1310:1310)) - (PORT datab (1170:1170:1170) (1252:1252:1252)) - (PORT datac (1298:1298:1298) (1294:1294:1294)) - (PORT datad (1090:1090:1090) (1131:1131:1131)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1093:1093:1093)) - (PORT datab (825:825:825) (829:829:829)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1113:1113:1113) (1132:1132:1132)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1011:1011:1011) (1004:1004:1004)) - (PORT datab (1009:1009:1009) (1000:1000:1000)) - (PORT datac (762:762:762) (765:765:765)) - (PORT datad (1062:1062:1062) (1054:1054:1054)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1910:1910:1910) (1899:1899:1899)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datac (169:169:169) (205:205:205)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (622:622:622)) - (PORT datab (1062:1062:1062) (1082:1082:1082)) - (PORT datac (1270:1270:1270) (1255:1255:1255)) - (PORT datad (2183:2183:2183) (2185:2185:2185)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1117:1117:1117) (1142:1142:1142)) - (PORT datab (1784:1784:1784) (1760:1760:1760)) - (PORT datac (1873:1873:1873) (1890:1890:1890)) - (PORT datad (835:835:835) (846:846:846)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1354:1354:1354) (1396:1396:1396)) - (PORT datab (1392:1392:1392) (1418:1418:1418)) - (PORT datac (1059:1059:1059) (1069:1069:1069)) - (PORT datad (1485:1485:1485) (1464:1464:1464)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1913:1913:1913) (1903:1903:1903)) - (PORT datab (187:187:187) (224:224:224)) - (PORT datac (167:167:167) (201:201:201)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1186:1186:1186) (1251:1251:1251)) - (PORT datac (1296:1296:1296) (1312:1312:1312)) - (PORT datad (787:787:787) (758:758:758)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1396:1396:1396)) - (PORT datab (1242:1242:1242) (1220:1220:1220)) - (PORT datac (1233:1233:1233) (1218:1218:1218)) - (PORT datad (1971:1971:1971) (1988:1988:1988)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1399:1399:1399)) - (PORT datab (1391:1391:1391) (1419:1419:1419)) - (PORT datac (1963:1963:1963) (1984:1984:1984)) - (PORT datad (2199:2199:2199) (2186:2186:2186)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (905:905:905)) - (PORT datab (225:225:225) (272:272:272)) - (PORT datac (1327:1327:1327) (1357:1357:1357)) - (PORT datad (501:501:501) (497:497:497)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT datac (1189:1189:1189) (1189:1189:1189)) - (PORT datad (729:729:729) (753:753:753)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT datac (1188:1188:1188) (1189:1189:1189)) - (PORT datad (729:729:729) (753:753:753)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (872:872:872)) - (PORT datab (790:790:790) (787:787:787)) - (PORT datac (784:784:784) (777:777:777)) - (PORT datad (758:758:758) (751:751:751)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (622:622:622)) - (PORT datab (800:800:800) (809:809:809)) - (PORT datac (486:486:486) (482:482:482)) - (PORT datad (545:545:545) (538:538:538)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (958:958:958)) - (PORT datab (903:903:903) (948:948:948)) - (PORT datac (2073:2073:2073) (2047:2047:2047)) - (PORT datad (1238:1238:1238) (1233:1233:1233)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1273:1273:1273)) - (PORT datab (1130:1130:1130) (1176:1176:1176)) - (PORT datad (804:804:804) (796:796:796)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1325:1325:1325) (1336:1336:1336)) - (PORT datab (1253:1253:1253) (1245:1245:1245)) - (PORT datac (751:751:751) (735:735:735)) - (PORT datad (734:734:734) (717:717:717)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (745:745:745) (733:733:733)) - (PORT datac (161:161:161) (193:193:193)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (796:796:796)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (994:994:994) (964:964:964)) - (PORT datad (163:163:163) (186:186:186)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1000:1000:1000) (962:962:962)) - (PORT datab (565:565:565) (546:546:546)) - (PORT datac (336:336:336) (345:345:345)) - (PORT datad (322:322:322) (328:328:328)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1752:1752:1752) (1805:1805:1805)) - (PORT datab (1292:1292:1292) (1317:1317:1317)) - (PORT datac (1285:1285:1285) (1318:1318:1318)) - (PORT datad (814:814:814) (818:818:818)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1075:1075:1075) (1096:1096:1096)) - (PORT datab (607:607:607) (638:638:638)) - (PORT datac (782:782:782) (779:779:779)) - (PORT datad (586:586:586) (597:597:597)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1516:1516:1516) (1488:1488:1488)) - (PORT datab (677:677:677) (743:743:743)) - (PORT datac (187:187:187) (227:227:227)) - (PORT datad (1440:1440:1440) (1428:1428:1428)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1172:1172:1172)) - (PORT datab (591:591:591) (583:583:583)) - (PORT datac (1261:1261:1261) (1282:1282:1282)) - (PORT datad (765:765:765) (745:745:745)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1000:1000:1000) (1010:1010:1010)) - (PORT datab (2667:2667:2667) (2640:2640:2640)) - (PORT datac (816:816:816) (835:835:835)) - (PORT datad (950:950:950) (919:919:919)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (520:520:520) (513:513:513)) - (PORT datab (369:369:369) (370:370:370)) - (PORT datac (605:605:605) (603:603:603)) - (PORT datad (1051:1051:1051) (1056:1056:1056)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (904:904:904)) - (PORT datab (1076:1076:1076) (1100:1100:1100)) - (PORT datac (747:747:747) (755:755:755)) - (PORT datad (171:171:171) (199:199:199)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1343:1343:1343) (1386:1386:1386)) - (PORT datab (606:606:606) (641:641:641)) - (PORT datac (1037:1037:1037) (1060:1060:1060)) - (PORT datad (930:930:930) (897:897:897)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1749:1749:1749) (1750:1750:1750)) - (PORT datab (218:218:218) (251:251:251)) - (PORT datac (516:516:516) (512:512:512)) - (PORT datad (176:176:176) (207:207:207)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (943:943:943) (916:916:916)) - (PORT datab (835:835:835) (840:840:840)) - (PORT datac (1269:1269:1269) (1266:1266:1266)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (960:960:960)) - (PORT datab (898:898:898) (942:942:942)) - (PORT datac (2076:2076:2076) (2048:2048:2048)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (1168:1168:1168) (1132:1132:1132)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT datab (1564:1564:1564) (1575:1575:1575)) - (PORT datac (1681:1681:1681) (1673:1673:1673)) - (PORT datad (2601:2601:2601) (2586:2586:2586)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (772:772:772)) - (PORT datab (769:769:769) (759:759:759)) - (PORT datac (1167:1167:1167) (1137:1137:1137)) - (PORT datad (591:591:591) (613:613:613)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (995:995:995) (969:969:969)) - (PORT datab (502:502:502) (494:494:494)) - (PORT datac (1291:1291:1291) (1322:1322:1322)) - (PORT datad (1196:1196:1196) (1132:1132:1132)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1110:1110:1110) (1136:1136:1136)) - (PORT datab (799:799:799) (817:817:817)) - (PORT datac (160:160:160) (192:192:192)) - (PORT datad (1180:1180:1180) (1137:1137:1137)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~5) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (414:414:414)) - (PORT datab (227:227:227) (280:280:280)) - (PORT datac (530:530:530) (519:519:519)) - (PORT datad (1005:1005:1005) (970:970:970)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (239:239:239)) - (PORT datab (206:206:206) (241:241:241)) - (PORT datac (785:785:785) (786:786:786)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (815:815:815)) - (PORT datab (194:194:194) (233:233:233)) - (PORT datac (576:576:576) (574:574:574)) - (PORT datad (163:163:163) (188:188:188)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (843:843:843)) - (PORT datab (784:784:784) (786:786:786)) - (PORT datac (1520:1520:1520) (1522:1522:1522)) - (PORT datad (1196:1196:1196) (1184:1184:1184)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT datab (615:615:615) (632:632:632)) - (PORT datac (166:166:166) (203:203:203)) - (PORT datad (540:540:540) (537:537:537)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1266:1266:1266) (1282:1282:1282)) - (PORT datab (2645:2645:2645) (2625:2625:2625)) - (PORT datac (792:792:792) (771:771:771)) - (PORT datad (999:999:999) (967:967:967)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1075:1075:1075) (1060:1060:1060)) - (PORT datab (559:559:559) (550:550:550)) - (PORT datac (1290:1290:1290) (1309:1309:1309)) - (PORT datad (1657:1657:1657) (1638:1638:1638)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~1) - (DELAY - (ABSOLUTE - (PORT datac (1684:1684:1684) (1695:1695:1695)) - (PORT datad (1659:1659:1659) (1638:1638:1638)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (963:963:963)) - (PORT datab (2010:2010:2010) (2073:2073:2073)) - (PORT datac (1293:1293:1293) (1310:1310:1310)) - (PORT datad (171:171:171) (195:195:195)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (754:754:754) (740:740:740)) - (PORT datab (187:187:187) (222:222:222)) - (PORT datac (531:531:531) (520:520:520)) - (PORT datad (163:163:163) (189:189:189)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (237:237:237)) - (PORT datab (307:307:307) (326:326:326)) - (PORT datac (886:886:886) (894:894:894)) - (PORT datad (295:295:295) (300:300:300)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (512:512:512)) - (PORT datab (895:895:895) (916:916:916)) - (PORT datac (1417:1417:1417) (1406:1406:1406)) - (PORT datad (837:837:837) (864:864:864)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (926:926:926)) - (PORT datab (2274:2274:2274) (2271:2271:2271)) - (PORT datac (768:768:768) (764:764:764)) - (PORT datad (1180:1180:1180) (1180:1180:1180)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT datab (797:797:797) (802:802:802)) - (PORT datac (1170:1170:1170) (1136:1136:1136)) - (PORT datad (1644:1644:1644) (1579:1579:1579)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1597:1597:1597) (1563:1563:1563)) - (PORT datab (207:207:207) (243:243:243)) - (PORT datac (1093:1093:1093) (1100:1100:1100)) - (PORT datad (305:305:305) (309:309:309)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1317:1317:1317) (1305:1305:1305)) - (PORT datab (1266:1266:1266) (1274:1274:1274)) - (PORT datac (1250:1250:1250) (1262:1262:1262)) - (PORT datad (358:358:358) (393:393:393)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~46) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (355:355:355)) - (PORT datab (785:785:785) (780:780:780)) - (PORT datac (740:740:740) (744:744:744)) - (PORT datad (567:567:567) (571:571:571)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1161:1161:1161) (1202:1202:1202)) - (PORT datab (198:198:198) (231:231:231)) - (PORT datac (1397:1397:1397) (1367:1367:1367)) - (PORT datad (569:569:569) (588:588:588)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1179:1179:1179)) - (PORT datab (1302:1302:1302) (1312:1312:1312)) - (PORT datac (2302:2302:2302) (2297:2297:2297)) - (PORT datad (2190:2190:2190) (2185:2185:2185)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1071:1071:1071)) - (PORT datab (949:949:949) (911:911:911)) - (PORT datac (1048:1048:1048) (1068:1068:1068)) - (PORT datad (967:967:967) (925:925:925)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (964:964:964) (944:944:944)) - (PORT datac (773:773:773) (763:763:763)) - (PORT datad (997:997:997) (964:964:964)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1540:1540:1540) (1557:1557:1557)) - (PORT datab (205:205:205) (240:240:240)) - (PORT datac (776:776:776) (766:766:766)) - (PORT datad (981:981:981) (945:945:945)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1101:1101:1101)) - (PORT datab (1013:1013:1013) (989:989:989)) - (PORT datac (1143:1143:1143) (1226:1226:1226)) - (PORT datad (1044:1044:1044) (1046:1046:1046)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1027:1027:1027)) - (PORT datab (826:826:826) (801:801:801)) - (PORT datac (944:944:944) (913:913:913)) - (PORT datad (1441:1441:1441) (1431:1431:1431)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (409:409:409)) - (PORT datab (229:229:229) (282:282:282)) - (PORT datac (1956:1956:1956) (1963:1963:1963)) - (PORT datad (1055:1055:1055) (1051:1051:1051)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (831:831:831)) - (PORT datab (872:872:872) (874:874:874)) - (PORT datac (764:764:764) (746:746:746)) - (PORT datad (1214:1214:1214) (1195:1195:1195)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1163:1163:1163)) - (PORT datab (776:776:776) (771:771:771)) - (PORT datac (600:600:600) (610:610:610)) - (PORT datad (191:191:191) (222:222:222)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1237:1237:1237) (1230:1230:1230)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (598:598:598) (617:617:617)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (963:963:963)) - (PORT datab (1443:1443:1443) (1422:1422:1422)) - (PORT datac (488:488:488) (485:485:485)) - (PORT datad (1008:1008:1008) (980:980:980)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1072:1072:1072) (1073:1073:1073)) - (PORT datab (782:782:782) (767:767:767)) - (PORT datac (812:812:812) (806:806:806)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal76\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2003:2003:2003) (2021:2021:2021)) - (PORT datac (1309:1309:1309) (1350:1350:1350)) - (PORT datad (2201:2201:2201) (2187:2187:2187)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (535:535:535) (528:528:528)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (903:903:903) (936:936:936)) - (PORT datad (1220:1220:1220) (1217:1217:1217)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1147:1147:1147) (1207:1207:1207)) - (PORT datab (554:554:554) (548:548:548)) - (PORT datac (836:836:836) (844:844:844)) - (PORT datad (1030:1030:1030) (1024:1024:1024)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1008:1008:1008) (976:976:976)) - (PORT datab (1054:1054:1054) (1057:1057:1057)) - (PORT datac (1266:1266:1266) (1291:1291:1291)) - (PORT datad (995:995:995) (972:972:972)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1072:1072:1072) (1073:1073:1073)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (519:519:519) (521:521:521)) - (PORT datad (520:520:520) (507:507:507)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (993:993:993) (999:999:999)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (791:791:791)) - (PORT datab (324:324:324) (337:337:337)) - (PORT datac (766:766:766) (763:763:763)) - (PORT datad (565:565:565) (560:560:560)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) - (DELAY - (ABSOLUTE - (PORT dataa (1355:1355:1355) (1397:1397:1397)) - (PORT datab (929:929:929) (964:964:964)) - (PORT datac (1962:1962:1962) (1984:1984:1984)) - (PORT datad (2199:2199:2199) (2186:2186:2186)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (559:559:559)) - (PORT datab (940:940:940) (976:976:976)) - (PORT datac (755:755:755) (753:753:753)) - (PORT datad (1686:1686:1686) (1636:1636:1636)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (980:980:980) (958:958:958)) - (PORT datac (1004:1004:1004) (1008:1008:1008)) - (PORT datad (983:983:983) (962:962:962)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (853:853:853)) - (PORT datab (341:341:341) (351:351:351)) - (PORT datac (821:821:821) (831:831:831)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT dataa (1053:1053:1053) (1066:1066:1066)) - (PORT datad (728:728:728) (722:722:722)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1272:1272:1272) (1290:1290:1290)) - (PORT datab (214:214:214) (258:258:258)) - (PORT datac (2174:2174:2174) (2160:2160:2160)) - (PORT datad (1713:1713:1713) (1771:1771:1771)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (786:786:786)) - (PORT datab (809:809:809) (831:831:831)) - (PORT datac (796:796:796) (812:812:812)) - (PORT datad (1078:1078:1078) (1072:1072:1072)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (905:905:905)) - (PORT datab (1506:1506:1506) (1476:1476:1476)) - (PORT datac (1503:1503:1503) (1503:1503:1503)) - (PORT datad (771:771:771) (755:755:755)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (547:547:547)) - (PORT datab (1219:1219:1219) (1206:1206:1206)) - (PORT datac (784:784:784) (783:783:783)) - (PORT datad (1010:1010:1010) (1009:1009:1009)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1225:1225:1225) (1201:1201:1201)) - (PORT datab (223:223:223) (262:262:262)) - (PORT datac (1147:1147:1147) (1206:1206:1206)) - (PORT datad (1427:1427:1427) (1404:1404:1404)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (490:490:490)) - (PORT datab (791:791:791) (802:802:802)) - (PORT datac (964:964:964) (922:922:922)) - (PORT datad (164:164:164) (187:187:187)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) - (DELAY - (ABSOLUTE - (PORT datac (1543:1543:1543) (1577:1577:1577)) - (PORT datad (1516:1516:1516) (1490:1490:1490)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1093:1093:1093)) - (PORT datab (295:295:295) (383:383:383)) - (PORT datac (259:259:259) (347:347:347)) - (PORT datad (838:838:838) (875:875:875)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1313:1313:1313) (1334:1334:1334)) - (PORT datab (179:179:179) (211:211:211)) - (PORT datac (1211:1211:1211) (1229:1229:1229)) - (PORT datad (1273:1273:1273) (1286:1286:1286)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1918:1918:1918) (1922:1922:1922)) - (PORT datab (790:790:790) (794:794:794)) - (PORT datac (1403:1403:1403) (1395:1395:1395)) - (PORT datad (808:808:808) (835:835:835)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1918:1918:1918) (1924:1924:1924)) - (PORT datab (1266:1266:1266) (1277:1277:1277)) - (PORT datac (1253:1253:1253) (1265:1265:1265)) - (PORT datad (807:807:807) (834:834:834)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (207:207:207) (243:243:243)) - (PORT datac (1959:1959:1959) (1964:1964:1964)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (869:869:869)) - (PORT datab (1147:1147:1147) (1177:1177:1177)) - (PORT datac (1070:1070:1070) (1091:1091:1091)) - (PORT datad (1233:1233:1233) (1237:1237:1237)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (596:596:596)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (741:741:741) (748:748:748)) - (PORT datad (496:496:496) (486:486:486)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (673:673:673)) - (PORT datab (779:779:779) (769:769:769)) - (PORT datac (2310:2310:2310) (2294:2294:2294)) - (PORT datad (164:164:164) (188:188:188)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (585:585:585)) - (PORT datab (624:624:624) (617:617:617)) - (PORT datac (1714:1714:1714) (1687:1687:1687)) - (PORT datad (752:752:752) (745:745:745)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla21M3T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (922:922:922)) - (PORT datab (1249:1249:1249) (1269:1269:1269)) - (PORT datac (1053:1053:1053) (1067:1067:1067)) - (PORT datad (1071:1071:1071) (1104:1104:1104)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (241:241:241)) - (PORT datab (751:751:751) (741:741:741)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1094:1094:1094) (1079:1079:1079)) - (PORT datab (1129:1129:1129) (1139:1139:1139)) - (PORT datac (167:167:167) (204:204:204)) - (PORT datad (1421:1421:1421) (1379:1379:1379)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1313:1313:1313) (1339:1339:1339)) - (PORT datab (854:854:854) (831:831:831)) - (PORT datac (503:503:503) (501:501:501)) - (PORT datad (778:778:778) (776:776:776)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (601:601:601)) - (PORT datab (857:857:857) (831:831:831)) - (PORT datac (758:758:758) (751:751:751)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~56) - (DELAY - (ABSOLUTE - (PORT dataa (1282:1282:1282) (1265:1265:1265)) - (PORT datab (1120:1120:1120) (1126:1126:1126)) - (PORT datac (1056:1056:1056) (1057:1057:1057)) - (PORT datad (736:736:736) (731:731:731)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1019:1019:1019) (1003:1003:1003)) - (PORT datab (845:845:845) (866:866:866)) - (PORT datac (1509:1509:1509) (1510:1510:1510)) - (PORT datad (1055:1055:1055) (1058:1058:1058)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (353:353:353)) - (PORT datab (553:553:553) (542:542:542)) - (PORT datac (545:545:545) (566:566:566)) - (PORT datad (183:183:183) (208:208:208)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1077:1077:1077) (1084:1084:1084)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1285:1285:1285) (1319:1319:1319)) - (PORT datad (840:840:840) (865:865:865)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT datab (804:804:804) (790:790:790)) - (PORT datac (1001:1001:1001) (983:983:983)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (992:992:992) (995:995:995)) - (PORT datab (1237:1237:1237) (1222:1222:1222)) - (PORT datac (774:774:774) (772:772:772)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (603:603:603) (597:597:597)) - (PORT datac (1033:1033:1033) (1033:1033:1033)) - (PORT datad (554:554:554) (551:551:551)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (794:794:794) (775:775:775)) - (PORT datac (161:161:161) (193:193:193)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1818:1818:1818) (1774:1774:1774)) - (PORT datab (896:896:896) (912:912:912)) - (PORT datac (513:513:513) (512:512:512)) - (PORT datad (202:202:202) (233:233:233)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1052:1052:1052) (1068:1068:1068)) - (PORT datab (767:767:767) (760:760:760)) - (PORT datad (973:973:973) (981:981:981)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT datab (207:207:207) (246:246:246)) - (PORT datac (1094:1094:1094) (1101:1101:1101)) - (PORT datad (305:305:305) (312:312:312)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (777:777:777) (780:780:780)) - (PORT datab (788:788:788) (796:796:796)) - (PORT datac (343:343:343) (369:369:369)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (593:593:593) (615:615:615)) - (PORT datac (598:598:598) (624:624:624)) - (PORT datad (760:760:760) (759:759:759)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~24) - (DELAY - (ABSOLUTE - (PORT datab (851:851:851) (866:866:866)) - (PORT datac (2310:2310:2310) (2294:2294:2294)) - (PORT datad (1218:1218:1218) (1206:1206:1206)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (2175:2175:2175) (2182:2182:2182)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (1097:1097:1097) (1115:1115:1115)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (574:574:574) (582:582:582)) - (PORT datab (874:874:874) (926:926:926)) - (PORT datac (592:592:592) (586:586:586)) - (PORT datad (825:825:825) (814:814:814)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1020:1020:1020) (1016:1016:1016)) - (PORT datab (1289:1289:1289) (1318:1318:1318)) - (PORT datad (840:840:840) (865:865:865)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (230:230:230)) - (PORT datac (594:594:594) (622:622:622)) - (PORT datad (573:573:573) (581:581:581)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (930:930:930)) - (PORT datab (865:865:865) (840:840:840)) - (PORT datac (1081:1081:1081) (1100:1100:1100)) - (PORT datad (733:733:733) (719:719:719)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1128:1128:1128)) - (PORT datab (798:798:798) (776:776:776)) - (PORT datac (802:802:802) (812:812:812)) - (PORT datad (1164:1164:1164) (1149:1149:1149)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1236:1236:1236) (1238:1238:1238)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datad (1123:1123:1123) (1163:1163:1163)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1389:1389:1389) (1361:1361:1361)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1462:1462:1462) (1540:1540:1540)) - (PORT datab (1193:1193:1193) (1221:1221:1221)) - (PORT datac (943:943:943) (927:927:927)) - (PORT datad (833:833:833) (810:810:810)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1633:1633:1633) (1686:1686:1686)) - (PORT datab (772:772:772) (761:761:761)) - (PORT datac (1676:1676:1676) (1650:1650:1650)) - (PORT datad (1150:1150:1150) (1186:1186:1186)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1109:1109:1109)) - (PORT datac (1505:1505:1505) (1517:1517:1517)) - (PORT datad (183:183:183) (207:207:207)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1459:1459:1459) (1534:1534:1534)) - (PORT datab (1190:1190:1190) (1218:1218:1218)) - (PORT datac (940:940:940) (924:924:924)) - (PORT datad (830:830:830) (808:808:808)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (373:373:373)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1734:1734:1734) (1700:1700:1700)) - (PORT datab (794:794:794) (819:819:819)) - (PORT datac (829:829:829) (874:874:874)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (793:793:793)) - (PORT datab (216:216:216) (259:259:259)) - (PORT datad (769:769:769) (761:761:761)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1389:1389:1389) (1361:1361:1361)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1529:1529:1529) (1568:1568:1568)) - (PORT datab (228:228:228) (301:301:301)) - (PORT datac (946:946:946) (945:945:945)) - (PORT datad (1396:1396:1396) (1354:1354:1354)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1529:1529:1529) (1570:1570:1570)) - (PORT datab (227:227:227) (300:300:300)) - (PORT datac (944:944:944) (942:942:942)) - (PORT datad (1395:1395:1395) (1353:1353:1353)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (1572:1572:1572) (1611:1611:1611)) - (PORT datab (1016:1016:1016) (996:996:996)) - (PORT datad (1514:1514:1514) (1488:1488:1488)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (853:853:853)) - (PORT datab (1035:1035:1035) (1048:1048:1048)) - (PORT datac (786:786:786) (802:802:802)) - (PORT datad (1138:1138:1138) (1110:1110:1110)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1521:1521:1521) (1537:1537:1537)) - (PORT datab (537:537:537) (528:528:528)) - (PORT datac (1244:1244:1244) (1251:1251:1251)) - (PORT datad (886:886:886) (924:924:924)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1115:1115:1115) (1137:1137:1137)) - (PORT datab (2446:2446:2446) (2431:2431:2431)) - (PORT datac (779:779:779) (760:760:760)) - (PORT datad (1493:1493:1493) (1519:1519:1519)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (942:942:942)) - (PORT datab (1017:1017:1017) (1010:1010:1010)) - (PORT datac (945:945:945) (911:911:911)) - (PORT datad (1042:1042:1042) (1050:1050:1050)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1452:1452:1452) (1413:1413:1413)) - (PORT datab (798:798:798) (803:803:803)) - (PORT datac (1180:1180:1180) (1129:1129:1129)) - (PORT datad (1042:1042:1042) (1051:1051:1051)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (839:839:839)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1041:1041:1041) (1052:1052:1052)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1073:1073:1073) (1062:1062:1062)) - (PORT datab (669:669:669) (697:697:697)) - (PORT datac (801:801:801) (799:799:799)) - (PORT datad (608:608:608) (624:624:624)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (603:603:603)) - (PORT datab (604:604:604) (601:601:601)) - (PORT datac (1009:1009:1009) (1000:1000:1000)) - (PORT datad (778:778:778) (759:759:759)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1266:1266:1266)) - (PORT datab (1326:1326:1326) (1337:1337:1337)) - (PORT datac (596:596:596) (612:612:612)) - (PORT datad (741:741:741) (722:722:722)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (248:248:248)) - (PORT datab (836:836:836) (815:815:815)) - (PORT datac (1388:1388:1388) (1353:1353:1353)) - (PORT datad (324:324:324) (328:328:328)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1037:1037:1037) (1007:1007:1007)) - (PORT datab (1227:1227:1227) (1222:1222:1222)) - (PORT datac (1417:1417:1417) (1409:1409:1409)) - (PORT datad (618:618:618) (640:640:640)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1776:1776:1776) (1762:1762:1762)) - (PORT datab (543:543:543) (537:537:537)) - (PORT datac (310:310:310) (327:327:327)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (1512:1512:1512) (1518:1518:1518)) - (PORT datad (735:735:735) (737:737:737)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1411:1411:1411) (1451:1451:1451)) - (PORT datab (1024:1024:1024) (1035:1035:1035)) - (PORT datac (981:981:981) (979:979:979)) - (PORT datad (793:793:793) (771:771:771)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1039:1039:1039) (1043:1043:1043)) - (PORT datab (817:817:817) (794:794:794)) - (PORT datac (742:742:742) (736:736:736)) - (PORT datad (783:783:783) (768:768:768)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1559:1559:1559) (1596:1596:1596)) - (PORT datab (815:815:815) (809:809:809)) - (PORT datac (999:999:999) (1008:1008:1008)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (775:775:775) (776:776:776)) - (PORT datab (838:838:838) (855:855:855)) - (PORT datac (681:681:681) (658:658:658)) - (PORT datad (1652:1652:1652) (1629:1629:1629)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1043:1043:1043)) - (PORT datab (839:839:839) (859:859:859)) - (PORT datac (1486:1486:1486) (1476:1476:1476)) - (PORT datad (581:581:581) (602:602:602)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (332:332:332)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (587:587:587)) - (PORT datab (397:397:397) (410:410:410)) - (PORT datac (762:762:762) (742:742:742)) - (PORT datad (1325:1325:1325) (1324:1324:1324)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (614:614:614)) - (PORT datab (801:801:801) (779:779:779)) - (PORT datac (177:177:177) (208:208:208)) - (PORT datad (772:772:772) (771:771:771)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1236:1236:1236)) - (PORT datab (849:849:849) (865:865:865)) - (PORT datac (820:820:820) (831:831:831)) - (PORT datad (803:803:803) (805:805:805)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (190:190:190) (226:226:226)) - (PORT datac (743:743:743) (729:729:729)) - (PORT datad (747:747:747) (735:735:735)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (824:824:824)) - (PORT datab (1364:1364:1364) (1385:1385:1385)) - (PORT datac (993:993:993) (1013:1013:1013)) - (PORT datad (1064:1064:1064) (1075:1075:1075)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1280:1280:1280) (1305:1305:1305)) - (PORT datab (1091:1091:1091) (1087:1087:1087)) - (PORT datac (1390:1390:1390) (1406:1406:1406)) - (PORT datad (170:170:170) (199:199:199)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (414:414:414)) - (PORT datab (1060:1060:1060) (1067:1067:1067)) - (PORT datac (531:531:531) (521:521:521)) - (PORT datad (186:186:186) (213:213:213)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~18) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (516:516:516)) - (PORT datab (896:896:896) (915:915:915)) - (PORT datac (742:742:742) (715:715:715)) - (PORT datad (570:570:570) (576:576:576)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (787:787:787)) - (PORT datac (777:777:777) (780:780:780)) - (PORT datad (915:915:915) (904:904:904)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1008:1008:1008) (964:964:964)) - (PORT datab (1095:1095:1095) (1098:1098:1098)) - (PORT datac (1563:1563:1563) (1577:1577:1577)) - (PORT datad (762:762:762) (761:761:761)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (964:964:964) (937:937:937)) - (PORT datab (205:205:205) (240:240:240)) - (PORT datac (1068:1068:1068) (1048:1048:1048)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1078:1078:1078) (1073:1073:1073)) - (PORT datab (1781:1781:1781) (1739:1739:1739)) - (PORT datac (1198:1198:1198) (1214:1214:1214)) - (PORT datad (540:540:540) (541:541:541)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (826:826:826)) - (PORT datab (1283:1283:1283) (1284:1284:1284)) - (PORT datac (1747:1747:1747) (1712:1712:1712)) - (PORT datad (754:754:754) (740:740:740)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1119:1119:1119) (1143:1143:1143)) - (PORT datab (1255:1255:1255) (1208:1208:1208)) - (PORT datac (1873:1873:1873) (1884:1884:1884)) - (PORT datad (835:835:835) (842:842:842)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1559:1559:1559) (1593:1593:1593)) - (PORT datab (1505:1505:1505) (1493:1493:1493)) - (PORT datac (587:587:587) (581:581:581)) - (PORT datad (784:784:784) (769:769:769)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (823:823:823)) - (PORT datab (828:828:828) (815:815:815)) - (PORT datac (764:764:764) (746:746:746)) - (PORT datad (511:511:511) (491:491:491)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (225:225:225)) - (PORT datac (181:181:181) (217:217:217)) - (PORT datad (580:580:580) (595:595:595)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1550:1550:1550) (1579:1579:1579)) - (PORT datab (875:875:875) (882:882:882)) - (PORT datac (517:517:517) (507:507:507)) - (PORT datad (2237:2237:2237) (2236:2236:2236)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1470:1470:1470) (1431:1431:1431)) - (PORT datab (988:988:988) (957:957:957)) - (PORT datac (565:565:565) (570:570:570)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1486:1486:1486) (1465:1465:1465)) - (PORT datab (671:671:671) (736:736:736)) - (PORT datac (1225:1225:1225) (1206:1206:1206)) - (PORT datad (541:541:541) (546:546:546)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (341:341:341)) - (PORT datab (1539:1539:1539) (1562:1562:1562)) - (PORT datac (558:558:558) (571:571:571)) - (PORT datad (1312:1312:1312) (1308:1308:1308)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (187:187:187) (225:225:225)) - (PORT datac (1168:1168:1168) (1161:1161:1161)) - (PORT datad (557:557:557) (559:559:559)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (843:843:843) (879:879:879)) - (PORT datab (1275:1275:1275) (1305:1305:1305)) - (PORT datac (1255:1255:1255) (1256:1256:1256)) - (PORT datad (812:812:812) (831:831:831)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (1264:1264:1264) (1271:1271:1271)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (868:868:868) (894:894:894)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1146:1146:1146) (1188:1188:1188)) - (PORT datab (1540:1540:1540) (1546:1546:1546)) - (PORT datac (1973:1973:1973) (1982:1982:1982)) - (PORT datad (586:586:586) (592:592:592)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (936:936:936) (909:909:909)) - (PORT datac (957:957:957) (931:931:931)) - (PORT datad (179:179:179) (202:202:202)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1198:1198:1198)) - (PORT datab (1435:1435:1435) (1441:1441:1441)) - (PORT datac (1973:1973:1973) (1983:1983:1983)) - (PORT datad (1503:1503:1503) (1512:1512:1512)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (789:789:789)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (578:578:578) (578:578:578)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (899:899:899)) - (PORT datab (888:888:888) (929:929:929)) - (PORT datac (1224:1224:1224) (1213:1213:1213)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (343:343:343)) - (PORT datab (523:523:523) (514:514:514)) - (PORT datac (579:579:579) (598:598:598)) - (PORT datad (575:575:575) (597:597:597)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (977:977:977) (969:969:969)) - (PORT datab (1002:1002:1002) (1004:1004:1004)) - (PORT datac (587:587:587) (595:595:595)) - (PORT datad (1157:1157:1157) (1116:1116:1116)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1062:1062:1062)) - (PORT datab (993:993:993) (976:976:976)) - (PORT datac (984:984:984) (950:950:950)) - (PORT datad (799:799:799) (806:806:806)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (2178:2178:2178) (2181:2181:2181)) - (PORT datab (826:826:826) (831:831:831)) - (PORT datac (1032:1032:1032) (1051:1051:1051)) - (PORT datad (1000:1000:1000) (966:966:966)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1013:1013:1013) (981:981:981)) - (PORT datab (1305:1305:1305) (1288:1288:1288)) - (PORT datac (1259:1259:1259) (1285:1285:1285)) - (PORT datad (782:782:782) (798:798:798)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1205:1205:1205) (1190:1190:1190)) - (PORT datab (1035:1035:1035) (1049:1049:1049)) - (PORT datac (907:907:907) (890:890:890)) - (PORT datad (512:512:512) (506:506:506)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (805:805:805)) - (PORT datab (796:796:796) (808:808:808)) - (PORT datac (462:462:462) (450:450:450)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (233:233:233)) - (PORT datab (188:188:188) (224:224:224)) - (PORT datac (611:611:611) (608:608:608)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1052:1052:1052)) - (PORT datab (187:187:187) (222:222:222)) - (PORT datac (1169:1169:1169) (1162:1162:1162)) - (PORT datad (996:996:996) (1000:1000:1000)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT datac (301:301:301) (312:312:312)) - (PORT datad (561:561:561) (567:567:567)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (979:979:979) (955:955:955)) - (PORT datab (868:868:868) (862:862:862)) - (PORT datac (592:592:592) (602:602:602)) - (PORT datad (1159:1159:1159) (1121:1121:1121)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (768:768:768)) - (PORT datab (762:762:762) (771:771:771)) - (PORT datac (1226:1226:1226) (1209:1209:1209)) - (PORT datad (840:840:840) (851:851:851)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (548:548:548)) - (PORT datab (179:179:179) (211:211:211)) - (PORT datac (331:331:331) (335:335:335)) - (PORT datad (336:336:336) (333:333:333)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1634:1634:1634) (1654:1654:1654)) - (PORT datab (597:597:597) (596:596:596)) - (PORT datac (1000:1000:1000) (965:965:965)) - (PORT datad (632:632:632) (667:667:667)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (866:866:866)) - (PORT datab (1521:1521:1521) (1513:1513:1513)) - (PORT datac (587:587:587) (594:594:594)) - (PORT datad (1247:1247:1247) (1238:1238:1238)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1660:1660:1660)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (176:176:176) (207:207:207)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1098:1098:1098)) - (PORT datab (1299:1299:1299) (1289:1289:1289)) - (PORT datac (1230:1230:1230) (1213:1213:1213)) - (PORT datad (1495:1495:1495) (1501:1501:1501)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1294:1294:1294)) - (PORT datab (1145:1145:1145) (1172:1172:1172)) - (PORT datac (896:896:896) (923:923:923)) - (PORT datad (185:185:185) (212:212:212)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (591:591:591)) - (PORT datab (794:794:794) (792:792:792)) - (PORT datac (1969:1969:1969) (1962:1962:1962)) - (PORT datad (809:809:809) (808:808:808)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (952:952:952)) - (PORT datab (193:193:193) (231:231:231)) - (PORT datac (1217:1217:1217) (1227:1227:1227)) - (PORT datad (1006:1006:1006) (1008:1008:1008)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1213:1213:1213) (1184:1184:1184)) - (PORT datab (1300:1300:1300) (1308:1308:1308)) - (PORT datac (2297:2297:2297) (2289:2289:2289)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (904:904:904)) - (PORT datab (1202:1202:1202) (1144:1144:1144)) - (PORT datac (979:979:979) (954:954:954)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1536:1536:1536) (1495:1495:1495)) - (PORT datab (1859:1859:1859) (1789:1789:1789)) - (PORT datac (757:757:757) (738:738:738)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (557:557:557)) - (PORT datab (1452:1452:1452) (1419:1419:1419)) - (PORT datac (614:614:614) (658:658:658)) - (PORT datad (1070:1070:1070) (1074:1074:1074)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (811:811:811) (791:791:791)) - (PORT datab (603:603:603) (595:595:595)) - (PORT datac (767:767:767) (764:764:764)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (222:222:222)) - (PORT datab (1341:1341:1341) (1345:1345:1345)) - (PORT datac (799:799:799) (795:795:795)) - (PORT datad (757:757:757) (732:732:732)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1288:1288:1288)) - (PORT datac (892:892:892) (920:920:920)) - (PORT datad (1118:1118:1118) (1137:1137:1137)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1320:1320:1320)) - (PORT datab (742:742:742) (722:722:722)) - (PORT datac (764:764:764) (762:762:762)) - (PORT datad (974:974:974) (991:991:991)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1108:1108:1108) (1100:1100:1100)) - (PORT datab (1009:1009:1009) (995:995:995)) - (PORT datac (763:763:763) (763:763:763)) - (PORT datad (785:785:785) (794:794:794)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1269:1269:1269) (1250:1250:1250)) - (PORT datab (2006:2006:2006) (2021:2021:2021)) - (PORT datac (1217:1217:1217) (1196:1196:1196)) - (PORT datad (1484:1484:1484) (1446:1446:1446)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT dataa (2743:2743:2743) (2743:2743:2743)) - (PORT datab (1281:1281:1281) (1259:1259:1259)) - (PORT datac (810:810:810) (808:808:808)) - (PORT datad (952:952:952) (943:943:943)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) - (DELAY - (ABSOLUTE - (PORT dataa (776:776:776) (778:778:778)) - (PORT datab (798:798:798) (819:819:819)) - (PORT datac (802:802:802) (839:839:839)) - (PORT datad (1185:1185:1185) (1169:1169:1169)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT datac (601:601:601) (631:631:631)) - (PORT datad (171:171:171) (201:201:201)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (584:584:584)) - (PORT datab (619:619:619) (621:621:621)) - (PORT datad (533:533:533) (529:529:529)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) - (DELAY - (ABSOLUTE - (PORT dataa (1999:1999:1999) (2010:2010:2010)) - (PORT datab (1335:1335:1335) (1320:1320:1320)) - (PORT datac (1323:1323:1323) (1368:1368:1368)) - (PORT datad (2192:2192:2192) (2178:2178:2178)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (239:239:239)) - (PORT datab (830:830:830) (828:828:828)) - (PORT datac (164:164:164) (200:200:200)) - (PORT datad (1246:1246:1246) (1229:1229:1229)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (893:893:893)) - (PORT datab (1219:1219:1219) (1202:1202:1202)) - (PORT datac (1466:1466:1466) (1447:1447:1447)) - (PORT datad (1262:1262:1262) (1237:1237:1237)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1468:1468:1468) (1432:1432:1432)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (1338:1338:1338) (1384:1384:1384)) - (PORT datad (1056:1056:1056) (1081:1081:1081)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1170:1170:1170)) - (PORT datab (803:803:803) (767:767:767)) - (PORT datac (1260:1260:1260) (1280:1280:1280)) - (PORT datad (1186:1186:1186) (1167:1167:1167)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1283:1283:1283) (1305:1305:1305)) - (PORT datab (788:788:788) (802:802:802)) - (PORT datac (1215:1215:1215) (1193:1193:1193)) - (PORT datad (1406:1406:1406) (1478:1478:1478)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (843:843:843) (852:852:852)) - (PORT datab (1058:1058:1058) (1085:1085:1085)) - (PORT datac (1045:1045:1045) (1087:1087:1087)) - (PORT datad (1235:1235:1235) (1219:1219:1219)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (230:230:230)) - (PORT datab (228:228:228) (278:278:278)) - (PORT datad (1036:1036:1036) (1034:1034:1034)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (965:965:965)) - (PORT datab (199:199:199) (231:231:231)) - (PORT datac (160:160:160) (192:192:192)) - (PORT datad (599:599:599) (627:627:627)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (592:592:592)) - (PORT datab (836:836:836) (822:822:822)) - (PORT datac (509:509:509) (495:495:495)) - (PORT datad (791:791:791) (776:776:776)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1134:1134:1134) (1165:1165:1165)) - (PORT datab (835:835:835) (830:830:830)) - (PORT datad (307:307:307) (307:307:307)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) - (DELAY - (ABSOLUTE - (PORT datac (593:593:593) (622:622:622)) - (PORT datad (977:977:977) (963:963:963)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1019:1019:1019)) - (PORT datab (808:808:808) (830:830:830)) - (PORT datac (800:800:800) (818:818:818)) - (PORT datad (1078:1078:1078) (1072:1072:1072)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (1261:1261:1261) (1244:1244:1244)) - (PORT datab (805:805:805) (810:810:810)) - (PORT datac (1150:1150:1150) (1145:1145:1145)) - (PORT datad (1100:1100:1100) (1111:1111:1111)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (241:241:241)) - (PORT datab (1103:1103:1103) (1108:1108:1108)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (1504:1504:1504) (1499:1499:1499)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (574:574:574)) - (PORT datab (1090:1090:1090) (1098:1098:1098)) - (PORT datac (1079:1079:1079) (1093:1093:1093)) - (PORT datad (964:964:964) (948:948:948)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1291:1291:1291) (1298:1298:1298)) - (PORT datab (783:783:783) (796:796:796)) - (PORT datac (1174:1174:1174) (1130:1130:1130)) - (PORT datad (1102:1102:1102) (1112:1112:1112)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (847:847:847)) - (PORT datab (1236:1236:1236) (1221:1221:1221)) - (PORT datac (1085:1085:1085) (1111:1111:1111)) - (PORT datad (1218:1218:1218) (1218:1218:1218)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1350:1350:1350) (1387:1387:1387)) - (PORT datab (788:788:788) (803:803:803)) - (PORT datac (1282:1282:1282) (1296:1296:1296)) - (PORT datad (987:987:987) (976:976:976)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2000:2000:2000) (2014:2014:2014)) - (PORT datab (1335:1335:1335) (1326:1326:1326)) - (PORT datac (1321:1321:1321) (1365:1365:1365)) - (PORT datad (2196:2196:2196) (2181:2181:2181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1541:1541:1541) (1569:1569:1569)) - (PORT datab (1674:1674:1674) (1651:1651:1651)) - (PORT datac (808:808:808) (815:815:815)) - (PORT datad (1039:1039:1039) (1025:1025:1025)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (567:567:567) (569:569:569)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (826:826:826)) - (PORT datab (1034:1034:1034) (1056:1056:1056)) - (PORT datac (585:585:585) (585:585:585)) - (PORT datad (557:557:557) (555:555:555)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1347:1347:1347) (1386:1386:1386)) - (PORT datab (1394:1394:1394) (1424:1424:1424)) - (PORT datac (1966:1966:1966) (1985:1985:1985)) - (PORT datad (2202:2202:2202) (2187:2187:2187)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1272:1272:1272)) - (PORT datab (1127:1127:1127) (1171:1171:1171)) - (PORT datac (1386:1386:1386) (1427:1427:1427)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (609:609:609)) - (PORT datab (825:825:825) (820:820:820)) - (PORT datac (1196:1196:1196) (1196:1196:1196)) - (PORT datad (1003:1003:1003) (1008:1008:1008)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (964:964:964)) - (PORT datab (1238:1238:1238) (1220:1220:1220)) - (PORT datac (540:540:540) (541:541:541)) - (PORT datad (504:504:504) (504:504:504)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1717:1717:1717) (1691:1691:1691)) - (PORT datab (2010:2010:2010) (2073:2073:2073)) - (PORT datac (1519:1519:1519) (1515:1515:1515)) - (PORT datad (804:804:804) (799:799:799)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (188:188:188) (222:222:222)) - (PORT datac (799:799:799) (794:794:794)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (538:538:538) (530:530:530)) - (PORT datab (746:746:746) (738:738:738)) - (PORT datac (1219:1219:1219) (1228:1228:1228)) - (PORT datad (1004:1004:1004) (1009:1009:1009)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1378:1378:1378) (1384:1384:1384)) - (PORT datab (1050:1050:1050) (1089:1089:1089)) - (PORT datac (1065:1065:1065) (1119:1119:1119)) - (PORT datad (1544:1544:1544) (1532:1532:1532)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1068:1068:1068)) - (PORT datab (996:996:996) (966:966:966)) - (PORT datac (1059:1059:1059) (1107:1107:1107)) - (PORT datad (999:999:999) (968:968:968)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1468:1468:1468) (1428:1428:1428)) - (PORT datab (1254:1254:1254) (1291:1291:1291)) - (PORT datac (568:568:568) (567:567:567)) - (PORT datad (1252:1252:1252) (1233:1233:1233)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (851:851:851)) - (PORT datac (804:804:804) (800:800:800)) - (PORT datad (598:598:598) (604:604:604)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) - (DELAY - (ABSOLUTE - (PORT datab (1423:1423:1423) (1434:1434:1434)) - (PORT datac (1295:1295:1295) (1321:1321:1321)) - (PORT datad (1258:1258:1258) (1253:1253:1253)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1326:1326:1326) (1341:1341:1341)) - (PORT datab (2004:2004:2004) (2065:2065:2065)) - (PORT datac (1523:1523:1523) (1519:1519:1519)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1187:1187:1187)) - (PORT datab (1303:1303:1303) (1308:1308:1308)) - (PORT datac (1283:1283:1283) (1307:1307:1307)) - (PORT datad (194:194:194) (221:221:221)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1280:1280:1280) (1306:1306:1306)) - (PORT datab (527:527:527) (516:516:516)) - (PORT datac (1103:1103:1103) (1149:1149:1149)) - (PORT datad (173:173:173) (205:205:205)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1069:1069:1069) (1086:1086:1086)) - (PORT datab (1082:1082:1082) (1080:1080:1080)) - (PORT datac (566:566:566) (570:570:570)) - (PORT datad (1285:1285:1285) (1278:1278:1278)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1163:1163:1163)) - (PORT datab (612:612:612) (623:623:623)) - (PORT datac (1034:1034:1034) (1056:1056:1056)) - (PORT datad (1019:1019:1019) (1019:1019:1019)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (496:496:496) (496:496:496)) - (PORT datab (804:804:804) (801:801:801)) - (PORT datac (529:529:529) (553:553:553)) - (PORT datad (810:810:810) (807:807:807)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (535:535:535) (540:540:540)) - (PORT datab (575:575:575) (572:572:572)) - (PORT datac (517:517:517) (503:503:503)) - (PORT datad (517:517:517) (501:501:501)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (557:557:557)) - (PORT datab (624:624:624) (634:634:634)) - (PORT datac (816:816:816) (835:835:835)) - (PORT datad (176:176:176) (198:198:198)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (543:543:543)) - (PORT datab (583:583:583) (575:575:575)) - (PORT datac (311:311:311) (313:313:313)) - (PORT datad (1170:1170:1170) (1150:1150:1150)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (240:240:240)) - (PORT datab (814:814:814) (810:810:810)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (2596:2596:2596) (2582:2582:2582)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (529:529:529) (513:513:513)) - (PORT datab (520:520:520) (508:508:508)) - (PORT datac (576:576:576) (576:576:576)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1115:1115:1115)) - (PORT datab (1029:1029:1029) (1029:1029:1029)) - (PORT datac (995:995:995) (998:998:998)) - (PORT datad (969:969:969) (952:952:952)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (779:779:779) (780:780:780)) - (PORT datab (1376:1376:1376) (1308:1308:1308)) - (PORT datac (153:153:153) (183:183:183)) - (PORT datad (1241:1241:1241) (1217:1217:1217)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1046:1046:1046) (1041:1041:1041)) - (PORT datab (862:862:862) (878:878:878)) - (PORT datac (1873:1873:1873) (1884:1884:1884)) - (PORT datad (1094:1094:1094) (1104:1104:1104)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (728:728:728) (703:703:703)) - (PORT datab (214:214:214) (256:256:256)) - (PORT datad (246:246:246) (322:322:322)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1389:1389:1389) (1361:1361:1361)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (229:229:229)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (598:598:598) (624:624:624)) - (PORT datad (570:570:570) (580:580:580)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1393:1393:1393)) - (PORT datab (2034:2034:2034) (2033:2033:2033)) - (PORT datac (1504:1504:1504) (1541:1541:1541)) - (PORT datad (1618:1618:1618) (1647:1647:1647)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (415:415:415)) - (PORT datab (270:270:270) (354:354:354)) - (PORT datac (774:774:774) (778:778:778)) - (PORT datad (178:178:178) (207:207:207)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (1630:1630:1630) (1683:1683:1683)) - (PORT datac (980:980:980) (982:982:982)) - (PORT datad (1496:1496:1496) (1479:1479:1479)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (412:412:412)) - (PORT datab (268:268:268) (350:350:350)) - (PORT datac (776:776:776) (780:780:780)) - (PORT datad (178:178:178) (206:206:206)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT dataa (1261:1261:1261) (1236:1236:1236)) - (PORT datac (1256:1256:1256) (1251:1251:1251)) - (PORT datad (1456:1456:1456) (1431:1431:1431)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT asdata (1375:1375:1375) (1363:1363:1363)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (1016:1016:1016) (983:983:983)) - (PORT datac (1598:1598:1598) (1655:1655:1655)) - (PORT datad (1496:1496:1496) (1483:1483:1483)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (705:705:705)) - (PORT datab (215:215:215) (259:259:259)) - (PORT datad (247:247:247) (322:322:322)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1389:1389:1389) (1361:1361:1361)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (302:302:302)) - (PORT datab (269:269:269) (353:353:353)) - (PORT datac (774:774:774) (776:776:776)) - (PORT datad (176:176:176) (204:204:204)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (1245:1245:1245) (1229:1229:1229)) - (PORT datac (1236:1236:1236) (1245:1245:1245)) - (PORT datad (1739:1739:1739) (1701:1701:1701)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT asdata (1378:1378:1378) (1367:1367:1367)) - (PORT ena (930:930:930) (921:921:921)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (1250:1250:1250) (1235:1235:1235)) - (PORT datac (1255:1255:1255) (1250:1250:1250)) - (PORT datad (1456:1456:1456) (1430:1430:1430)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (296:296:296)) - (PORT datab (641:641:641) (672:672:672)) - (PORT datad (209:209:209) (239:239:239)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) - (DELAY - (ABSOLUTE - (PORT datab (1627:1627:1627) (1680:1680:1680)) - (PORT datac (981:981:981) (983:983:983)) - (PORT datad (1497:1497:1497) (1483:1483:1483)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1122:1122:1122) (1106:1106:1106)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (303:303:303)) - (PORT datab (270:270:270) (353:353:353)) - (PORT datac (774:774:774) (777:777:777)) - (PORT datad (177:177:177) (205:205:205)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT dataa (1015:1015:1015) (1006:1006:1006)) - (PORT datab (1542:1542:1542) (1553:1553:1553)) - (PORT datad (1517:1517:1517) (1487:1487:1487)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1118:1118:1118) (1102:1102:1102)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[7\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1011:1011:1011)) - (PORT datab (1545:1545:1545) (1558:1558:1558)) - (PORT datad (1515:1515:1515) (1486:1486:1486)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (427:427:427)) - (PORT datab (584:584:584) (619:619:619)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT datab (1270:1270:1270) (1283:1283:1283)) - (PORT datac (1090:1090:1090) (1105:1105:1105)) - (PORT datad (1736:1736:1736) (1704:1704:1704)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1148:1148:1148) (1135:1135:1135)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) - (DELAY - (ABSOLUTE - (PORT datac (1506:1506:1506) (1521:1521:1521)) - (PORT datad (1045:1045:1045) (1067:1067:1067)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (957:957:957)) - (PORT datab (1189:1189:1189) (1218:1218:1218)) - (PORT datac (1422:1422:1422) (1500:1500:1500)) - (PORT datad (180:180:180) (210:210:210)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (871:871:871) (864:864:864)) - (PORT ena (882:882:882) (874:874:874)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (957:957:957)) - (PORT datab (1190:1190:1190) (1218:1218:1218)) - (PORT datac (1422:1422:1422) (1500:1500:1500)) - (PORT datad (179:179:179) (210:210:210)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (869:869:869) (865:865:865)) - (PORT ena (1397:1397:1397) (1371:1371:1371)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (436:436:436)) - (PORT datab (383:383:383) (412:412:412)) - (PORT datad (575:575:575) (604:604:604)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1192:1192:1192)) - (PORT datab (1033:1033:1033) (1047:1047:1047)) - (PORT datac (784:784:784) (797:797:797)) - (PORT datad (516:516:516) (507:507:507)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (642:642:642) (638:638:638)) - (PORT datac (795:795:795) (818:818:818)) - (PORT datad (1010:1010:1010) (1015:1015:1015)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (672:672:672)) - (PORT datab (567:567:567) (565:565:565)) - (PORT datac (971:971:971) (938:938:938)) - (PORT datad (571:571:571) (579:579:579)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1276:1276:1276) (1254:1254:1254)) - (PORT datab (1167:1167:1167) (1242:1242:1242)) - (PORT datac (958:958:958) (954:954:954)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (773:773:773)) - (PORT datab (563:563:563) (550:550:550)) - (PORT datac (337:337:337) (344:344:344)) - (PORT datad (528:528:528) (509:509:509)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (175:175:175) (205:205:205)) - (PORT datad (325:325:325) (328:328:328)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (351:351:351) (350:350:350)) - (PORT datac (181:181:181) (217:217:217)) - (PORT datad (965:965:965) (932:932:932)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (1572:1572:1572) (1614:1614:1614)) - (PORT datab (1017:1017:1017) (998:998:998)) - (PORT datad (1515:1515:1515) (1493:1493:1493)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (868:868:868) (865:865:865)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1220:1220:1220) (1187:1187:1187)) - (PORT datab (946:946:946) (969:969:969)) - (PORT datad (365:365:365) (370:370:370)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) - (DELAY - (ABSOLUTE - (PORT dataa (1093:1093:1093) (1111:1111:1111)) - (PORT datac (1502:1502:1502) (1516:1516:1516)) - (PORT datad (184:184:184) (208:208:208)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1368:1368:1368) (1360:1360:1360)) - (PORT ena (1108:1108:1108) (1069:1069:1069)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1132:1132:1132)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (1678:1678:1678) (1650:1650:1650)) - (PORT datad (739:739:739) (723:723:723)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1370:1370:1370) (1363:1363:1363)) - (PORT ena (1138:1138:1138) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1108:1108:1108) (1130:1130:1130)) - (PORT datab (770:770:770) (755:755:755)) - (PORT datac (1679:1679:1679) (1650:1650:1650)) - (PORT datad (828:828:828) (806:806:806)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (431:431:431)) - (PORT datab (605:605:605) (610:610:610)) - (PORT datad (580:580:580) (572:572:572)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1120:1120:1120)) - (PORT datab (607:607:607) (627:627:627)) - (PORT datac (498:498:498) (487:487:487)) - (PORT datad (1044:1044:1044) (1041:1041:1041)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (766:766:766) (787:787:787)) - (PORT datab (213:213:213) (248:248:248)) - (PORT datac (1040:1040:1040) (1042:1042:1042)) - (PORT datad (164:164:164) (188:188:188)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (814:814:814) (816:816:816)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (574:574:574) (567:567:567)) - (PORT datad (1320:1320:1320) (1318:1318:1318)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (873:873:873)) - (PORT datac (1869:1869:1869) (1884:1884:1884)) - (PORT datad (1896:1896:1896) (1822:1822:1822)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (816:816:816)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1004:1004:1004) (997:997:997)) - (PORT datad (1028:1028:1028) (1029:1029:1029)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (366:366:366)) - (PORT datab (1068:1068:1068) (1087:1087:1087)) - (PORT datac (797:797:797) (786:786:786)) - (PORT datad (546:546:546) (567:567:567)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (357:357:357)) - (PORT datab (649:649:649) (662:662:662)) - (PORT datac (1465:1465:1465) (1459:1459:1459)) - (PORT datad (1465:1465:1465) (1471:1471:1471)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~39) - (DELAY - (ABSOLUTE - (PORT dataa (963:963:963) (956:956:956)) - (PORT datab (363:363:363) (369:369:369)) - (PORT datac (1067:1067:1067) (1047:1047:1047)) - (PORT datad (844:844:844) (861:861:861)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (777:777:777) (776:776:776)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1253:1253:1253) (1254:1254:1254)) - (PORT datad (583:583:583) (598:598:598)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1017:1017:1017)) - (PORT datab (842:842:842) (847:847:847)) - (PORT datac (1215:1215:1215) (1158:1158:1158)) - (PORT datad (1142:1142:1142) (1109:1109:1109)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (790:790:790)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (596:596:596) (619:619:619)) - (PORT datad (793:793:793) (776:776:776)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (381:381:381)) - (PORT datab (756:756:756) (749:749:749)) - (PORT datac (327:327:327) (331:331:331)) - (PORT datad (760:760:760) (756:756:756)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (976:976:976)) - (PORT datab (910:910:910) (893:893:893)) - (PORT datad (955:955:955) (922:922:922)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (874:874:874) (876:876:876)) - (PORT ena (1327:1327:1327) (1302:1302:1302)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (947:947:947) (926:926:926)) - (PORT datab (1190:1190:1190) (1221:1221:1221)) - (PORT datac (940:940:940) (925:925:925)) - (PORT datad (178:178:178) (208:208:208)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (874:874:874) (878:878:878)) - (PORT ena (1311:1311:1311) (1323:1323:1323)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (453:453:453)) - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (612:612:612) (627:627:627)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (578:578:578)) - (PORT datab (353:353:353) (351:351:351)) - (PORT datac (312:312:312) (319:319:319)) - (PORT datad (573:573:573) (564:564:564)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_32) - (DELAY - (ABSOLUTE - (PORT dataa (1083:1083:1083) (1074:1074:1074)) - (PORT datac (1546:1546:1546) (1581:1581:1581)) - (PORT datad (1519:1519:1519) (1494:1494:1494)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (569:569:569)) - (PORT datab (220:220:220) (288:288:288)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (168:168:168) (192:192:192)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (579:579:579) (576:576:576)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (306:306:306) (323:323:323)) - (PORT datad (1196:1196:1196) (1257:1257:1257)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (799:799:799)) - (PORT datab (570:570:570) (565:565:565)) - (PORT datac (923:923:923) (914:914:914)) - (PORT datad (1248:1248:1248) (1231:1231:1231)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1262:1262:1262) (1223:1223:1223)) - (PORT datab (233:233:233) (275:275:275)) - (PORT datac (819:819:819) (848:848:848)) - (PORT datad (733:733:733) (718:718:718)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (654:654:654)) - (PORT datab (835:835:835) (842:842:842)) - (PORT datac (535:535:535) (545:545:545)) - (PORT datad (1169:1169:1169) (1131:1131:1131)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1749:1749:1749) (1749:1749:1749)) - (PORT datab (199:199:199) (240:240:240)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (804:804:804)) - (PORT datab (782:782:782) (783:783:783)) - (PORT datac (512:512:512) (505:505:505)) - (PORT datad (766:766:766) (753:753:753)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1218:1218:1218) (1222:1222:1222)) - (PORT datab (672:672:672) (697:697:697)) - (PORT datac (1191:1191:1191) (1165:1165:1165)) - (PORT datad (769:769:769) (767:767:767)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT datab (1165:1165:1165) (1126:1126:1126)) - (PORT datad (780:780:780) (801:801:801)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1097:1097:1097) (1141:1141:1141)) - (PORT datab (1614:1614:1614) (1605:1605:1605)) - (PORT datac (777:777:777) (753:753:753)) - (PORT datad (1273:1273:1273) (1280:1280:1280)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1161:1161:1161)) - (PORT datab (850:850:850) (838:838:838)) - (PORT datac (1180:1180:1180) (1171:1171:1171)) - (PORT datad (1042:1042:1042) (1051:1051:1051)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1314:1314:1314) (1344:1344:1344)) - (PORT datab (630:630:630) (647:647:647)) - (PORT datac (1047:1047:1047) (1046:1046:1046)) - (PORT datad (294:294:294) (291:291:291)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (944:944:944)) - (PORT datab (596:596:596) (615:615:615)) - (PORT datac (785:785:785) (786:786:786)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (983:983:983) (975:975:975)) - (PORT datab (657:657:657) (707:707:707)) - (PORT datac (176:176:176) (208:208:208)) - (PORT datad (179:179:179) (202:202:202)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1278:1278:1278)) - (PORT datab (610:610:610) (621:621:621)) - (PORT datac (573:573:573) (572:572:572)) - (PORT datad (1256:1256:1256) (1225:1225:1225)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (848:848:848)) - (PORT datab (351:351:351) (364:364:364)) - (PORT datac (804:804:804) (803:803:803)) - (PORT datad (599:599:599) (604:604:604)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1275:1275:1275)) - (PORT datab (1018:1018:1018) (996:996:996)) - (PORT datac (1176:1176:1176) (1153:1153:1153)) - (PORT datad (1192:1192:1192) (1171:1171:1171)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (187:187:187) (222:222:222)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (554:554:554) (562:562:562)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (368:368:368)) - (PORT datab (773:773:773) (771:771:771)) - (PORT datac (1447:1447:1447) (1400:1400:1400)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (603:603:603)) - (PORT datab (190:190:190) (225:225:225)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (567:567:567) (564:564:564)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (964:964:964)) - (PORT datab (181:181:181) (215:215:215)) - (PORT datac (756:756:756) (744:744:744)) - (PORT datad (1504:1504:1504) (1411:1411:1411)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1214:1214:1214) (1235:1235:1235)) - (PORT datab (1106:1106:1106) (1075:1075:1075)) - (PORT datac (787:787:787) (764:764:764)) - (PORT datad (1011:1011:1011) (990:990:990)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1072:1072:1072) (1068:1068:1068)) - (PORT datab (1012:1012:1012) (1022:1022:1022)) - (PORT datac (511:511:511) (497:497:497)) - (PORT datad (1453:1453:1453) (1424:1424:1424)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (852:852:852)) - (PORT datab (808:808:808) (811:811:811)) - (PORT datac (782:782:782) (774:774:774)) - (PORT datad (1100:1100:1100) (1120:1120:1120)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1257:1257:1257) (1229:1229:1229)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (542:542:542) (555:555:555)) - (PORT datad (567:567:567) (577:577:577)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) - (DELAY - (ABSOLUTE - (PORT datab (1041:1041:1041) (1045:1045:1045)) - (PORT datac (1217:1217:1217) (1230:1230:1230)) - (PORT datad (171:171:171) (201:201:201)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1219:1219:1219)) - (PORT datab (514:514:514) (509:509:509)) - (PORT datac (753:753:753) (745:745:745)) - (PORT datad (778:778:778) (755:755:755)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (845:845:845)) - (PORT datab (648:648:648) (661:661:661)) - (PORT datac (978:978:978) (962:962:962)) - (PORT datad (747:747:747) (723:723:723)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (649:649:649)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datac (1984:1984:1984) (1985:1985:1985)) - (PORT datad (164:164:164) (188:188:188)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (526:526:526) (519:519:519)) - (PORT datac (163:163:163) (199:199:199)) - (PORT datad (578:578:578) (598:598:598)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (365:365:365)) - (PORT datab (205:205:205) (242:242:242)) - (PORT datac (826:826:826) (815:815:815)) - (PORT datad (723:723:723) (704:704:704)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1237:1237:1237) (1253:1253:1253)) - (PORT datab (567:567:567) (559:559:559)) - (PORT datac (1481:1481:1481) (1442:1442:1442)) - (PORT datad (1232:1232:1232) (1237:1237:1237)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1239:1239:1239) (1252:1252:1252)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (1132:1132:1132) (1156:1156:1156)) - (PORT datad (1232:1232:1232) (1237:1237:1237)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1380:1380:1380) (1388:1388:1388)) - (PORT datab (566:566:566) (559:559:559)) - (PORT datac (1481:1481:1481) (1443:1443:1443)) - (PORT datad (1543:1543:1543) (1535:1535:1535)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1382:1382:1382) (1385:1385:1385)) - (PORT datab (186:186:186) (222:222:222)) - (PORT datac (1132:1132:1132) (1157:1157:1157)) - (PORT datad (1543:1543:1543) (1532:1532:1532)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT datab (1669:1669:1669) (1646:1646:1646)) - (PORT datac (1511:1511:1511) (1533:1533:1533)) - (PORT datad (1267:1267:1267) (1265:1265:1265)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1047:1047:1047)) - (PORT datab (634:634:634) (659:659:659)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (761:761:761) (765:765:765)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (619:619:619)) - (PORT datab (1034:1034:1034) (1056:1056:1056)) - (PORT datac (1169:1169:1169) (1148:1148:1148)) - (PORT datad (796:796:796) (802:802:802)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla83M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (925:925:925)) - (PORT datab (1299:1299:1299) (1312:1312:1312)) - (PORT datac (1181:1181:1181) (1153:1153:1153)) - (PORT datad (191:191:191) (220:220:220)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1760:1760:1760) (1773:1773:1773)) - (PORT datab (1389:1389:1389) (1421:1421:1421)) - (PORT datac (1265:1265:1265) (1269:1269:1269)) - (PORT datad (532:532:532) (528:528:528)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (833:833:833)) - (PORT datab (1298:1298:1298) (1286:1286:1286)) - (PORT datac (1284:1284:1284) (1297:1297:1297)) - (PORT datad (1094:1094:1094) (1119:1119:1119)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (776:776:776)) - (PORT datab (612:612:612) (624:624:624)) - (PORT datac (539:539:539) (555:555:555)) - (PORT datad (952:952:952) (939:939:939)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (829:829:829)) - (PORT datab (789:789:789) (781:781:781)) - (PORT datac (689:689:689) (662:662:662)) - (PORT datad (1001:1001:1001) (966:966:966)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (891:891:891)) - (PORT datab (1224:1224:1224) (1207:1207:1207)) - (PORT datac (1626:1626:1626) (1580:1580:1580)) - (PORT datad (1266:1266:1266) (1241:1241:1241)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (1492:1492:1492) (1471:1471:1471)) - (PORT datac (688:688:688) (659:659:659)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (871:871:871)) - (PORT datab (1075:1075:1075) (1070:1070:1070)) - (PORT datac (758:758:758) (753:753:753)) - (PORT datad (1519:1519:1519) (1520:1520:1520)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1473:1473:1473) (1434:1434:1434)) - (PORT datab (992:992:992) (985:985:985)) - (PORT datac (567:567:567) (568:568:568)) - (PORT datad (1486:1486:1486) (1468:1468:1468)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (238:238:238)) - (PORT datab (179:179:179) (212:212:212)) - (PORT datac (766:766:766) (747:747:747)) - (PORT datad (1487:1487:1487) (1470:1470:1470)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (801:801:801) (819:819:819)) - (PORT datac (762:762:762) (745:745:745)) - (PORT datad (960:960:960) (954:954:954)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (831:831:831)) - (PORT datab (1014:1014:1014) (982:982:982)) - (PORT datac (765:765:765) (737:737:737)) - (PORT datad (595:595:595) (615:615:615)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (187:187:187) (225:225:225)) - (PORT datac (176:176:176) (207:207:207)) - (PORT datad (164:164:164) (190:190:190)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2000:2000:2000) (2012:2012:2012)) - (PORT datab (1336:1336:1336) (1322:1322:1322)) - (PORT datac (1324:1324:1324) (1370:1370:1370)) - (PORT datad (2194:2194:2194) (2178:2178:2178)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (814:814:814) (820:820:820)) - (PORT datab (604:604:604) (626:626:626)) - (PORT datac (1517:1517:1517) (1474:1474:1474)) - (PORT datad (964:964:964) (940:940:940)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (1050:1050:1050) (1061:1061:1061)) - (PORT datac (1012:1012:1012) (1002:1002:1002)) - (PORT datad (826:826:826) (837:837:837)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1048:1048:1048) (1061:1061:1061)) - (PORT datad (827:827:827) (837:837:837)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1148:1148:1148) (1135:1135:1135)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1365:1365:1365) (1362:1362:1362)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1016:1016:1016) (1008:1008:1008)) - (PORT datab (1543:1543:1543) (1555:1555:1555)) - (PORT datad (1515:1515:1515) (1490:1490:1490)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1365:1365:1365) (1360:1360:1360)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT asdata (901:901:901) (928:928:928)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT asdata (901:901:901) (929:929:929)) - (PORT ena (930:930:930) (921:921:921)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (411:411:411)) - (PORT datab (642:642:642) (676:676:676)) - (PORT datad (210:210:210) (243:243:243)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (433:433:433)) - (PORT datab (316:316:316) (328:328:328)) - (PORT datad (561:561:561) (581:581:581)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1349:1349:1349) (1331:1331:1331)) - (PORT ena (1108:1108:1108) (1069:1069:1069)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1352:1352:1352) (1334:1334:1334)) - (PORT ena (1138:1138:1138) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (623:623:623)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (585:585:585) (571:571:571)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1074:1074:1074) (1073:1073:1073)) - (PORT ena (882:882:882) (874:874:874)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1073:1073:1073) (1072:1072:1072)) - (PORT ena (897:897:897) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (429:429:429)) - (PORT datab (384:384:384) (413:413:413)) + (PORT datab (230:230:230) (302:302:302)) (PORT datad (198:198:198) (254:254:254)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (857:857:857) (866:866:866)) - (PORT ena (1311:1311:1311) (1323:1323:1323)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (857:857:857) (865:865:865)) - (PORT ena (1327:1327:1327) (1302:1302:1302)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (449:449:449)) - (PORT datab (641:641:641) (658:658:658)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1343:1343:1343) (1341:1341:1341)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1220:1220:1220) (1191:1191:1191)) - (PORT datab (854:854:854) (845:845:845)) - (PORT datad (362:362:362) (369:369:369)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (319:319:319) (330:330:330)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (565:565:565) (559:559:559)) - (PORT datad (548:548:548) (544:544:544)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (296:296:296)) - (PORT datab (594:594:594) (586:586:586)) - (PORT datac (798:798:798) (775:775:775)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (823:823:823)) - (PORT datab (588:588:588) (595:595:595)) - (PORT datac (1732:1732:1732) (1745:1745:1745)) - (PORT datad (519:519:519) (507:507:507)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT datac (1214:1214:1214) (1158:1158:1158)) - (PORT datad (1006:1006:1006) (975:975:975)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (813:813:813) (815:815:815)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (812:812:812) (817:817:817)) - (PORT datad (301:301:301) (308:308:308)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) - (DELAY - (ABSOLUTE - (PORT datab (197:197:197) (234:234:234)) - (PORT datac (1066:1066:1066) (1064:1064:1064)) - (PORT datad (763:763:763) (762:762:762)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (695:695:695)) - (PORT datab (788:788:788) (790:790:790)) - (PORT datac (760:760:760) (741:741:741)) - (PORT datad (571:571:571) (565:565:565)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (778:778:778) (785:785:785)) - (PORT datab (727:727:727) (698:698:698)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (816:816:816)) - (PORT datab (911:911:911) (950:950:950)) - (PORT datac (1228:1228:1228) (1236:1236:1236)) - (PORT datad (517:517:517) (510:510:510)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (823:823:823)) - (PORT datab (186:186:186) (222:222:222)) - (PORT datac (596:596:596) (613:613:613)) - (PORT datad (1000:1000:1000) (985:985:985)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (221:221:221)) - (PORT datab (806:806:806) (794:794:794)) - (PORT datac (1998:1998:1998) (1901:1901:1901)) - (PORT datad (1013:1013:1013) (986:986:986)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) - (DELAY - (ABSOLUTE - (PORT datab (1129:1129:1129) (1152:1152:1152)) - (PORT datac (947:947:947) (918:918:918)) - (PORT datad (1560:1560:1560) (1533:1533:1533)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1138:1138:1138)) - (PORT datac (1281:1281:1281) (1304:1304:1304)) - (PORT datad (1811:1811:1811) (1833:1833:1833)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (248:248:248)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (801:801:801) (802:802:802)) - (PORT datad (176:176:176) (197:197:197)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) - (DELAY - (ABSOLUTE - (PORT datab (982:982:982) (962:962:962)) - (PORT datac (946:946:946) (921:921:921)) - (PORT datad (1091:1091:1091) (1120:1120:1120)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (743:743:743)) - (PORT datab (505:505:505) (499:499:499)) - (PORT datac (600:600:600) (624:624:624)) - (PORT datad (1769:1769:1769) (1793:1793:1793)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (221:221:221)) - (PORT datab (755:755:755) (748:748:748)) - (PORT datad (759:759:759) (756:756:756)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1211:1211:1211)) - (PORT datab (669:669:669) (730:730:730)) - (PORT datac (1225:1225:1225) (1209:1209:1209)) - (PORT datad (770:770:770) (763:763:763)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1161:1161:1161) (1198:1198:1198)) - (PORT datab (593:593:593) (622:622:622)) - (PORT datac (599:599:599) (620:620:620)) - (PORT datad (793:793:793) (810:810:810)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1581:1581:1581) (1601:1601:1601)) - (PORT datab (602:602:602) (619:619:619)) - (PORT datac (522:522:522) (513:513:513)) - (PORT datad (976:976:976) (961:961:961)) (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1526:1526:1526) (1523:1523:1523)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (805:805:805) (826:826:826)) - (PORT datad (938:938:938) (926:926:926)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT datab (801:801:801) (790:790:790)) - (PORT datac (328:328:328) (334:334:334)) - (PORT datad (295:295:295) (300:300:300)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (743:743:743) (749:749:749)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (584:584:584) (580:580:580)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1083:1083:1083) (1075:1075:1075)) - (PORT datab (1139:1139:1139) (1161:1161:1161)) - (PORT datac (1134:1134:1134) (1129:1129:1129)) - (PORT datad (1171:1171:1171) (1123:1123:1123)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT datab (980:980:980) (962:962:962)) - (PORT datac (947:947:947) (921:921:921)) - (PORT datad (1091:1091:1091) (1122:1122:1122)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (816:816:816) (794:794:794)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (302:302:302)) - (PORT datab (862:862:862) (907:907:907)) - (PORT datad (575:575:575) (579:579:579)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -12650,87 +11457,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (INSTANCE z80_\|address_latch_\|abusz\[7\]) (DELAY (ABSOLUTE - (PORT datab (1129:1129:1129) (1157:1157:1157)) - (PORT datac (947:947:947) (922:922:922)) - (PORT datad (1559:1559:1559) (1533:1533:1533)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (903:903:903) (898:898:898)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (417:417:417) (433:433:433)) - (PORT datac (295:295:295) (298:298:298)) - (PORT datad (196:196:196) (253:253:253)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[11\]) - (DELAY - (ABSOLUTE - (PORT datac (1403:1403:1403) (1447:1447:1447)) - (PORT datad (579:579:579) (590:590:590)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (846:846:846)) - (PORT datab (829:829:829) (814:814:814)) - (PORT datac (176:176:176) (208:208:208)) - (PORT datad (581:581:581) (582:582:582)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (829:829:829) (802:802:802)) - (PORT datac (1518:1518:1518) (1496:1496:1496)) - (PORT datad (1459:1459:1459) (1453:1453:1453)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT datac (609:609:609) (625:625:625)) + (PORT datad (564:564:564) (566:566:566)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -12741,11 +11472,11 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) (DELAY (ABSOLUTE - (PORT dataa (1146:1146:1146) (1190:1190:1190)) - (PORT datab (1543:1543:1543) (1551:1551:1551)) - (PORT datad (837:837:837) (881:881:881)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (2273:2273:2273) (2429:2429:2429)) + (PORT datac (825:825:825) (843:843:843)) + (PORT datad (1842:1842:1842) (1863:1863:1863)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -12755,12 +11486,12 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~6) (DELAY (ABSOLUTE - (PORT dataa (611:611:611) (652:652:652)) - (PORT datab (601:601:601) (597:597:597)) - (PORT datac (587:587:587) (585:585:585)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (PORT dataa (341:341:341) (351:351:351)) + (PORT datab (517:517:517) (516:516:516)) + (PORT datac (782:782:782) (783:783:783)) + (PORT datad (1040:1040:1040) (1050:1050:1050)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -12771,12 +11502,12 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~7) (DELAY (ABSOLUTE - (PORT dataa (565:565:565) (544:544:544)) - (PORT datab (839:839:839) (854:854:854)) - (PORT datac (162:162:162) (198:198:198)) - (PORT datad (169:169:169) (197:197:197)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (1033:1033:1033) (1044:1044:1044)) + (PORT datab (1069:1069:1069) (1075:1075:1075)) + (PORT datac (742:742:742) (726:726:726)) + (PORT datad (591:591:591) (584:584:584)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -12787,12 +11518,60 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~8) (DELAY (ABSOLUTE - (PORT dataa (336:336:336) (359:359:359)) - (PORT datab (371:371:371) (397:397:397)) - (PORT datac (759:759:759) (756:756:756)) - (PORT datad (704:704:704) (680:680:680)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (912:912:912) (948:948:948)) + (PORT datab (1520:1520:1520) (1487:1487:1487)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (1059:1059:1059) (1072:1072:1072)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1168:1168:1168)) + (PORT datab (921:921:921) (984:984:984)) + (PORT datac (599:599:599) (642:642:642)) + (PORT datad (1151:1151:1151) (1210:1210:1210)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (727:727:727) (703:703:703)) + (PORT datab (610:610:610) (603:603:603)) + (PORT datac (777:777:777) (798:798:798)) + (PORT datad (957:957:957) (972:972:972)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (659:659:659) (658:658:658)) + (PORT datac (181:181:181) (214:214:214)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -12803,12 +11582,10 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~11) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (613:613:613) (616:616:616)) - (PORT datad (317:317:317) (319:319:319)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (185:185:185) (222:222:222)) + (PORT datac (164:164:164) (200:200:200)) + (PORT datad (506:506:506) (506:506:506)) + (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -12819,12 +11596,12 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~12) (DELAY (ABSOLUTE - (PORT dataa (883:883:883) (902:902:902)) - (PORT datab (889:889:889) (931:931:931)) - (PORT datac (1225:1225:1225) (1212:1212:1212)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (1152:1152:1152) (1192:1192:1192)) + (PORT datab (776:776:776) (746:746:746)) + (PORT datac (772:772:772) (748:748:748)) + (PORT datad (809:809:809) (817:817:817)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -12832,13 +11609,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[11\]) + (INSTANCE z80_\|address_latch_\|Q\[7\]) (DELAY (ABSOLUTE - (PORT clk (1343:1343:1343) (1365:1365:1365)) + (PORT clk (1345:1345:1345) (1363:1363:1363)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1358:1358:1358)) - (PORT ena (2292:2292:2292) (2253:2253:2253)) + (PORT clrn (1400:1400:1400) (1370:1370:1370)) + (PORT ena (1981:1981:1981) (2010:2010:2010)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -12850,25 +11627,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) (DELAY (ABSOLUTE - (PORT datab (426:426:426) (487:487:487)) - (PORT datad (512:512:512) (498:498:498)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (378:378:378) (387:387:387)) + (PORT datab (1678:1678:1678) (1697:1697:1697)) + (PORT datac (181:181:181) (214:214:214)) + (PORT datad (594:594:594) (626:626:626)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (INSTANCE z80_\|execute_\|fIOWrite\~0) (DELAY (ABSOLUTE - (PORT dataa (1019:1019:1019) (992:992:992)) - (PORT datab (219:219:219) (254:254:254)) - (PORT datac (491:491:491) (479:479:479)) - (PORT datad (191:191:191) (219:219:219)) + (PORT dataa (1125:1125:1125) (1167:1167:1167)) + (PORT datab (1853:1853:1853) (1913:1913:1913)) + (PORT datac (1198:1198:1198) (1284:1284:1284)) + (PORT datad (1866:1866:1866) (1903:1903:1903)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (367:367:367)) + (PORT datab (192:192:192) (233:233:233)) + (PORT datac (1025:1025:1025) (1018:1018:1018)) + (PORT datad (1111:1111:1111) (1100:1100:1100)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -12878,325 +11675,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) (DELAY (ABSOLUTE - (PORT dataa (195:195:195) (240:240:240)) - (PORT datab (591:591:591) (601:601:601)) - (PORT datac (720:720:720) (717:717:717)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (375:375:375)) - (PORT datab (800:800:800) (778:778:778)) - (PORT datac (562:562:562) (578:578:578)) - (PORT datad (780:780:780) (784:784:784)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (783:783:783)) - (PORT datab (1508:1508:1508) (1485:1485:1485)) - (PORT datac (741:741:741) (724:724:724)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (646:646:646)) - (PORT datab (1081:1081:1081) (1096:1096:1096)) - (PORT datac (1221:1221:1221) (1243:1243:1243)) - (PORT datad (1087:1087:1087) (1105:1105:1105)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (598:598:598)) - (PORT datab (1062:1062:1062) (1084:1084:1084)) - (PORT datac (511:511:511) (505:505:505)) - (PORT datad (507:507:507) (501:501:501)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1232:1232:1232)) - (PORT datac (1810:1810:1810) (1830:1830:1830)) - (PORT datad (571:571:571) (556:556:556)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (630:630:630)) - (PORT datab (839:839:839) (881:881:881)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (833:833:833) (854:854:854)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1005:1005:1005)) - (PORT datab (821:821:821) (820:820:820)) - (PORT datac (1810:1810:1810) (1833:1833:1833)) - (PORT datad (1030:1030:1030) (1039:1039:1039)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (494:494:494) (487:487:487)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (771:771:771)) - (PORT datab (797:797:797) (791:791:791)) - (PORT datac (723:723:723) (716:716:716)) - (PORT datad (1185:1185:1185) (1166:1166:1166)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (308:308:308)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datac (1276:1276:1276) (1354:1354:1354)) - (PORT datad (808:808:808) (867:867:867)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (854:854:854) (870:870:870)) - (PORT datac (1531:1531:1531) (1611:1611:1611)) - (PORT datad (338:338:338) (353:353:353)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (218:218:218)) - (PORT datab (555:555:555) (573:573:573)) - (PORT datac (308:308:308) (320:320:320)) - (PORT datad (1195:1195:1195) (1255:1255:1255)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (814:814:814) (816:816:816)) - (PORT datab (1096:1096:1096) (1064:1064:1064)) - (PORT datac (779:779:779) (763:763:763)) - (PORT datad (787:787:787) (770:770:770)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1031:1031:1031) (1020:1020:1020)) - (PORT datab (597:597:597) (597:597:597)) - (PORT datac (1025:1025:1025) (982:982:982)) - (PORT datad (994:994:994) (971:971:971)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1248:1248:1248)) - (PORT datab (750:750:750) (750:750:750)) - (PORT datac (1264:1264:1264) (1275:1275:1275)) - (PORT datad (585:585:585) (585:585:585)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (286:286:286)) - (PORT datab (1016:1016:1016) (1009:1009:1009)) - (PORT datac (356:356:356) (384:384:384)) - (PORT datad (568:568:568) (567:567:567)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT datab (1093:1093:1093) (1133:1133:1133)) - (PORT datac (1108:1108:1108) (1153:1153:1153)) - (PORT datad (1066:1066:1066) (1095:1095:1095)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (238:238:238)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (859:859:859) (890:890:890)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datab (633:633:633) (642:642:642)) - (PORT datac (746:746:746) (738:738:738)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (774:774:774)) - (PORT datab (222:222:222) (259:259:259)) - (PORT datac (756:756:756) (744:744:744)) - (PORT datad (758:758:758) (736:736:736)) + (PORT dataa (201:201:201) (239:239:239)) + (PORT datab (1573:1573:1573) (1616:1616:1616)) + (PORT datac (518:518:518) (494:494:494)) + (PORT datad (158:158:158) (179:179:179)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13204,60 +11691,36 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) (DELAY (ABSOLUTE - (PORT dataa (817:817:817) (834:834:834)) - (PORT datab (802:802:802) (798:798:798)) - (PORT datac (488:488:488) (472:472:472)) - (PORT datad (764:764:764) (764:764:764)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (919:919:919) (924:924:924)) + (PORT datac (1042:1042:1042) (1028:1028:1028)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (208:208:208) (246:246:246)) - (PORT datac (497:497:497) (477:477:477)) - (PORT datad (308:308:308) (310:310:310)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (548:548:548)) - (PORT datab (512:512:512) (500:500:500)) - (PORT datac (616:616:616) (645:645:645)) - (PORT datad (535:535:535) (532:532:532)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (927:927:927) (951:951:951)) + (PORT datad (1038:1038:1038) (1031:1031:1031)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1370:1370:1370)) + (PORT clk (1363:1363:1363) (1384:1384:1384)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) + (PORT ena (1175:1175:1175) (1170:1170:1170)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -13268,15 +11731,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) (DELAY (ABSOLUTE - (PORT dataa (1038:1038:1038) (1075:1075:1075)) - (PORT datab (850:850:850) (880:880:880)) - (PORT datac (1571:1571:1571) (1521:1521:1521)) - (PORT datad (1148:1148:1148) (1092:1092:1092)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datab (1448:1448:1448) (1428:1428:1428)) + (PORT datac (1112:1112:1112) (1131:1131:1131)) + (PORT datad (1000:1000:1000) (984:984:984)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13284,61 +11745,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) (DELAY (ABSOLUTE - (PORT datab (1527:1527:1527) (1515:1515:1515)) - (PORT datac (570:570:570) (595:595:595)) - (PORT datad (318:318:318) (321:321:321)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1166:1166:1166)) - (PORT datab (1082:1082:1082) (1093:1093:1093)) - (PORT datac (743:743:743) (729:729:729)) - (PORT datad (509:509:509) (505:505:505)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (825:825:825)) - (PORT datab (1168:1168:1168) (1239:1239:1239)) - (PORT datac (958:958:958) (954:954:954)) - (PORT datad (1230:1230:1230) (1213:1213:1213)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (227:227:227)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1027:1027:1027) (1020:1020:1020)) - (PORT datad (2829:2829:2829) (2804:2804:2804)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT datab (1445:1445:1445) (1427:1427:1427)) + (PORT datac (1120:1120:1120) (1140:1140:1140)) + (PORT datad (914:914:914) (922:922:922)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13346,88 +11759,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~42) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) (DELAY (ABSOLUTE - (PORT dataa (832:832:832) (852:852:852)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (1225:1225:1225) (1233:1233:1233)) - (PORT datad (1238:1238:1238) (1217:1217:1217)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (958:958:958) (938:938:938)) - (PORT datab (531:531:531) (528:528:528)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT dataa (1083:1083:1083) (1078:1078:1078)) - (PORT datac (1129:1129:1129) (1122:1122:1122)) - (PORT datad (1302:1302:1302) (1271:1271:1271)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT datab (1162:1162:1162) (1154:1154:1154)) - (PORT datac (1188:1188:1188) (1159:1159:1159)) - (PORT datad (1303:1303:1303) (1273:1273:1273)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1173:1173:1173) (1142:1142:1142)) - (PORT datab (1328:1328:1328) (1404:1404:1404)) - (PORT datac (407:407:407) (437:437:437)) - (PORT datad (368:368:368) (384:384:384)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT datab (1161:1161:1161) (1153:1153:1153)) - (PORT datac (1188:1188:1188) (1158:1158:1158)) - (PORT datad (1302:1302:1302) (1272:1272:1272)) + (PORT datab (1444:1444:1444) (1428:1428:1428)) + (PORT datac (1121:1121:1121) (1141:1141:1141)) + (PORT datad (1001:1001:1001) (984:984:984)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13436,11 +11773,705 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1371:1371:1371)) - (PORT asdata (660:660:660) (675:675:675)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1304:1304:1304) (1285:1285:1285)) + (PORT ena (1588:1588:1588) (1555:1555:1555)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT datab (1449:1449:1449) (1432:1432:1432)) + (PORT datac (1106:1106:1106) (1125:1125:1125)) + (PORT datad (919:919:919) (927:927:927)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1304:1304:1304) (1285:1285:1285)) + (PORT ena (1297:1297:1297) (1275:1275:1275)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (840:840:840)) + (PORT datab (886:886:886) (937:937:937)) + (PORT datad (196:196:196) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT datab (1300:1300:1300) (1274:1274:1274)) + (PORT datac (1084:1084:1084) (1079:1079:1079)) + (PORT datad (546:546:546) (554:554:554)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (668:668:668) (669:669:669)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (359:359:359)) + (PORT datab (200:200:200) (245:245:245)) + (PORT datac (200:200:200) (269:269:269)) + (PORT datad (1129:1129:1129) (1170:1170:1170)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT datab (1107:1107:1107) (1100:1100:1100)) + (PORT datac (587:587:587) (609:609:609)) + (PORT datad (1264:1264:1264) (1244:1244:1244)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT datab (1109:1109:1109) (1104:1104:1104)) + (PORT datac (588:588:588) (608:608:608)) + (PORT datad (1264:1264:1264) (1238:1238:1238)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (667:667:667) (668:668:668)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (231:231:231) (284:284:284)) + (PORT datad (211:211:211) (246:246:246)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT datac (836:836:836) (843:843:843)) + (PORT datad (1245:1245:1245) (1229:1229:1229)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (680:680:680)) + (PORT datab (1084:1084:1084) (1078:1078:1078)) + (PORT datac (174:174:174) (214:214:214)) + (PORT datad (1330:1330:1330) (1362:1362:1362)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1094:1094:1094) (1096:1096:1096)) + (PORT ena (1155:1155:1155) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (681:681:681)) + (PORT datab (1081:1081:1081) (1078:1078:1078)) + (PORT datac (175:175:175) (213:213:213)) + (PORT datad (1333:1333:1333) (1363:1363:1363)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1095:1095:1095) (1094:1094:1094)) + (PORT ena (1109:1109:1109) (1074:1074:1074)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (444:444:444)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datad (587:587:587) (590:590:590)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (593:593:593)) + (PORT datab (869:869:869) (890:890:890)) + (PORT datad (623:623:623) (628:628:628)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1550:1550:1550) (1525:1525:1525)) + (PORT ena (1380:1380:1380) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (603:603:603)) + (PORT datab (1301:1301:1301) (1284:1284:1284)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1076:1076:1076)) + (PORT datab (1080:1080:1080) (1077:1077:1077)) + (PORT datac (174:174:174) (213:213:213)) + (PORT datad (614:614:614) (636:636:636)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1121:1121:1121) (1124:1124:1124)) + (PORT ena (1123:1123:1123) (1106:1106:1106)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (845:845:845)) + (PORT datab (385:385:385) (422:422:422)) + (PORT datac (853:853:853) (854:854:854)) + (PORT datad (566:566:566) (575:575:575)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (861:861:861)) + (PORT datab (871:871:871) (892:892:892)) + (PORT datac (1053:1053:1053) (1048:1048:1048)) + (PORT datad (356:356:356) (371:371:371)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT datab (863:863:863) (889:889:889)) + (PORT datac (1245:1245:1245) (1225:1225:1225)) + (PORT datad (819:819:819) (837:837:837)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1088:1088:1088) (1108:1108:1108)) + (PORT datab (1086:1086:1086) (1078:1078:1078)) + (PORT datac (174:174:174) (214:214:214)) + (PORT datad (624:624:624) (642:642:642)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1551:1551:1551) (1526:1526:1526)) + (PORT ena (1132:1132:1132) (1112:1112:1112)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT dataa (1680:1680:1680) (1620:1620:1620)) + (PORT datab (844:844:844) (872:872:872)) + (PORT datad (840:840:840) (857:857:857)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1122:1122:1122) (1126:1126:1126)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (415:415:415)) + (PORT datab (583:583:583) (608:608:608)) + (PORT datad (337:337:337) (366:366:366)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (1612:1612:1612) (1601:1601:1601)) + (PORT datab (1087:1087:1087) (1086:1086:1086)) + (PORT datad (743:743:743) (706:706:706)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT asdata (1298:1298:1298) (1281:1281:1281)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (784:784:784) (790:790:790)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT datab (977:977:977) (950:950:950)) + (PORT datac (843:843:843) (859:859:859)) + (PORT datad (821:821:821) (834:834:834)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1154:1154:1154) (1142:1142:1142)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (423:423:423)) + (PORT datab (543:543:543) (552:552:552)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (497:497:497) (482:482:482)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (617:617:617)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datad (727:727:727) (719:719:719)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (356:356:356)) + (PORT datab (579:579:579) (582:582:582)) + (PORT datac (1289:1289:1289) (1259:1259:1259)) + (PORT datad (578:578:578) (598:598:598)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT asdata (1299:1299:1299) (1282:1282:1282)) + (PORT ena (1105:1105:1105) (1078:1078:1078)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (238:238:238)) + (PORT datab (1144:1144:1144) (1154:1154:1154)) + (PORT datad (603:603:603) (628:628:628)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (632:632:632) (639:639:639)) + (PORT datac (1056:1056:1056) (1072:1072:1072)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1175:1175:1175) (1170:1170:1170)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1344:1344:1344) (1323:1323:1323)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1344:1344:1344) (1323:1323:1323)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (232:232:232) (284:284:284)) + (PORT datad (211:211:211) (246:246:246)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1095:1095:1095) (1097:1097:1097)) (PORT ena (739:739:739) (742:742:742)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13452,41 +12483,131 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1345:1345:1345) (1330:1330:1330)) - (PORT datab (217:217:217) (261:261:261)) - (PORT datad (1171:1171:1171) (1123:1123:1123)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1103:1103:1103) (1101:1101:1101)) + (PORT datab (1444:1444:1444) (1427:1427:1427)) + (PORT datad (1001:1001:1001) (984:984:984)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT dataa (1083:1083:1083) (1080:1080:1080)) - (PORT datac (1132:1132:1132) (1126:1126:1126)) - (PORT datad (1302:1302:1302) (1275:1275:1275)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1365:1365:1365) (1374:1374:1374)) + (PORT ena (1297:1297:1297) (1275:1275:1275)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (610:610:610)) + (PORT datab (1005:1005:1005) (1016:1016:1016)) + (PORT datad (860:860:860) (895:895:895)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1126:1126:1126) (1114:1114:1114)) + (PORT ena (1123:1123:1123) (1106:1106:1106)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1126:1126:1126) (1114:1114:1114)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (636:636:636)) + (PORT datab (220:220:220) (289:289:289)) + (PORT datad (344:344:344) (355:355:355)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1347:1347:1347) (1368:1368:1368)) + (PORT ena (1381:1381:1381) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (320:320:320) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (935:935:935) (942:942:942)) + (PORT ena (1155:1155:1155) (1140:1140:1140)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -13496,14 +12617,217 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT datab (342:342:342) (368:368:368)) - (PORT datac (404:404:404) (432:432:432)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1345:1345:1345) (1365:1365:1365)) + (PORT ena (1295:1295:1295) (1246:1246:1246)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (439:439:439)) + (PORT datab (607:607:607) (599:599:599)) + (PORT datad (765:765:765) (749:749:749)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1123:1123:1123) (1128:1128:1128)) + (PORT datab (855:855:855) (860:860:860)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (869:869:869) (860:860:860)) + (PORT ena (1109:1109:1109) (1074:1074:1074)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (435:435:435)) + (PORT datab (1063:1063:1063) (1045:1045:1045)) + (PORT datad (504:504:504) (492:492:492)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT asdata (1580:1580:1580) (1593:1593:1593)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT asdata (1580:1580:1580) (1596:1596:1596)) + (PORT ena (1154:1154:1154) (1142:1142:1142)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (426:426:426)) + (PORT datab (538:538:538) (545:545:545)) + (PORT datad (197:197:197) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (578:578:578)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (322:322:322) (325:325:325)) + (PORT datad (550:550:550) (542:542:542)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1119:1119:1119) (1114:1114:1114)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1018:1018:1018) (1023:1023:1023)) + (PORT datad (763:763:763) (762:762:762)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT asdata (1466:1466:1466) (1434:1434:1434)) + (PORT ena (1105:1105:1105) (1078:1078:1078)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1062:1062:1062)) + (PORT datab (642:642:642) (660:660:660)) + (PORT datad (1099:1099:1099) (1118:1118:1118)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (222:222:222) (290:290:290)) + (PORT datac (648:648:648) (673:673:673)) + (PORT datad (775:775:775) (771:771:771)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (877:877:877)) + (PORT datab (849:849:849) (884:884:884)) + (PORT datac (1400:1400:1400) (1394:1394:1394)) + (PORT datad (613:613:613) (652:652:652)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13518,24 +12842,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~0) - (DELAY - (ABSOLUTE - (PORT datab (620:620:620) (662:662:662)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~14) (DELAY (ABSOLUTE - (PORT datab (385:385:385) (432:432:432)) + (PORT datab (1297:1297:1297) (1300:1300:1300)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13549,9 +12861,9 @@ (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT datab (1161:1161:1161) (1171:1171:1171)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (241:241:241) (314:314:314)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -13563,9 +12875,9 @@ (INSTANCE ula_\|video_\|vga_hc\~2) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (223:223:223)) - (PORT datad (359:359:359) (363:363:363)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT datac (777:777:777) (776:776:776)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -13575,13 +12887,13 @@ (INSTANCE ula_\|video_\|vga_hc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (1270:1270:1270) (1242:1242:1242)) + (PORT clk (1354:1354:1354) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) ) ) (CELL @@ -13589,8 +12901,8 @@ (INSTANCE ula_\|video_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datab (1404:1404:1404) (1411:1411:1411)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT datad (609:609:609) (646:646:646)) + (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) ) @@ -13600,8 +12912,8 @@ (INSTANCE ula_\|video_\|vga_hc\~1) (DELAY (ABSOLUTE - (PORT datab (183:183:183) (216:216:216)) - (PORT datad (358:358:358) (361:361:361)) + (PORT datab (208:208:208) (246:246:246)) + (PORT datad (529:529:529) (517:517:517)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13612,59 +12924,23 @@ (INSTANCE ula_\|video_\|vga_hc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (604:604:604) (617:617:617)) + (PORT clk (1357:1357:1357) (1372:1372:1372)) + (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~0) + (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT dataa (923:923:923) (951:951:951)) - (PORT datab (660:660:660) (696:696:696)) - (PORT datac (1112:1112:1112) (1152:1152:1152)) - (PORT datad (637:637:637) (669:669:669)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1326:1326:1326) (1336:1336:1336)) - (PORT datab (593:593:593) (622:622:622)) - (PORT datac (1077:1077:1077) (1094:1094:1094)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1428:1428:1428) (1447:1447:1447)) - (PORT datab (1119:1119:1119) (1148:1148:1148)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (1081:1081:1081) (1096:1096:1096)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (997:997:997) (981:981:981)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -13674,8 +12950,8 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (292:292:292) (295:295:295)) - (PORT datad (186:186:186) (210:210:210)) + (PORT datac (772:772:772) (785:785:785)) + (PORT datad (844:844:844) (838:838:838)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13687,72 +12963,6 @@ (DELAY (ABSOLUTE (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT asdata (841:841:841) (825:825:825)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~2) - (DELAY - (ABSOLUTE - (PORT datab (664:664:664) (686:686:686)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) - (PORT asdata (870:870:870) (858:858:858)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (942:942:942)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (803:803:803) (777:777:777)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13763,10 +12973,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~6) + (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (1106:1106:1106) (1104:1104:1104)) + (PORT datab (629:629:629) (645:645:645)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13775,12 +12985,88 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (552:552:552) (552:552:552)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (431:431:431)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1369:1369:1369)) + (PORT asdata (607:607:607) (607:607:607)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (640:640:640) (667:667:667)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (523:523:523) (522:522:522)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13794,9 +13080,9 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (377:377:377) (425:425:425)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (1015:1015:1015) (1000:1000:1000)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -13808,8 +13094,8 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (840:840:840) (823:823:823)) + (PORT clk (1354:1354:1354) (1369:1369:1369)) + (PORT asdata (607:607:607) (607:607:607)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -13817,12 +13103,59 @@ (HOLD asdata (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1151:1151:1151) (1185:1185:1185)) + (PORT datab (892:892:892) (947:947:947)) + (PORT datac (891:891:891) (943:943:943)) + (PORT datad (258:258:258) (326:326:326)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (653:653:653)) + (PORT datab (1298:1298:1298) (1302:1302:1302)) + (PORT datad (874:874:874) (842:842:842)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (463:463:463)) + (PORT datab (641:641:641) (668:668:668)) + (PORT datac (600:600:600) (630:630:630)) + (PORT datad (528:528:528) (511:511:511)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (1298:1298:1298) (1297:1297:1297)) + (PORT dataa (633:633:633) (650:650:650)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13836,9 +13169,9 @@ (INSTANCE ula_\|video_\|vga_hc\~0) (DELAY (ABSOLUTE - (PORT dataa (320:320:320) (328:328:328)) - (PORT datad (354:354:354) (357:357:357)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT datac (780:780:780) (780:780:780)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -13848,13 +13181,13 @@ (INSTANCE ula_\|video_\|vga_hc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (846:846:846) (828:828:828)) + (PORT clk (1354:1354:1354) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) ) ) (CELL @@ -13862,7 +13195,7 @@ (INSTANCE ula_\|video_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (397:397:397) (450:450:450)) + (PORT dataa (590:590:590) (608:608:608)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13876,8 +13209,8 @@ (INSTANCE ula_\|video_\|vga_hc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (610:610:610) (615:615:615)) + (PORT clk (1354:1354:1354) (1369:1369:1369)) + (PORT asdata (467:467:467) (493:493:493)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -13890,8 +13223,8 @@ (INSTANCE ula_\|video_\|vga_hc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (782:782:782) (762:762:762)) + (PORT clk (1354:1354:1354) (1369:1369:1369)) + (PORT asdata (806:806:806) (780:780:780)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -13904,48 +13237,19 @@ (INSTANCE ula_\|video_\|Add1\~0) (DELAY (ABSOLUTE - (PORT dataa (1155:1155:1155) (1183:1183:1183)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (669:669:669) (695:695:695)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (723:723:723)) - (PORT datab (659:659:659) (682:682:682)) - (PORT datad (304:304:304) (308:308:308)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~2) (DELAY (ABSOLUTE - (PORT dataa (439:439:439) (482:482:482)) + (PORT dataa (654:654:654) (681:681:681)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13959,9 +13263,9 @@ (INSTANCE ula_\|video_\|Add1\~4) (DELAY (ABSOLUTE - (PORT datab (419:419:419) (455:455:455)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (637:637:637) (664:664:664)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -13973,9 +13277,9 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (693:693:693) (722:722:722)) - (PORT datab (321:321:321) (325:325:325)) - (PORT datad (623:623:623) (639:639:639)) + (PORT dataa (452:452:452) (501:501:501)) + (PORT datab (556:556:556) (546:546:546)) + (PORT datad (829:829:829) (818:818:818)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -13988,7 +13292,7 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -14002,7 +13306,7 @@ (INSTANCE ula_\|video_\|Add1\~6) (DELAY (ABSOLUTE - (PORT dataa (632:632:632) (656:656:656)) + (PORT dataa (660:660:660) (695:695:695)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -14016,12 +13320,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (695:695:695) (726:726:726)) - (PORT datab (661:661:661) (685:685:685)) - (PORT datad (286:286:286) (288:288:288)) + (PORT dataa (574:574:574) (576:576:576)) + (PORT datab (598:598:598) (610:610:610)) + (PORT datac (626:626:626) (665:665:665)) + (PORT datad (161:161:161) (182:182:182)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -14031,13 +13336,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) - (PORT d (67:67:67) (78:78:78)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT asdata (1257:1257:1257) (1200:1200:1200)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL @@ -14045,9 +13350,9 @@ (INSTANCE ula_\|video_\|Add1\~8) (DELAY (ABSOLUTE - (PORT dataa (404:404:404) (455:455:455)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (630:630:630) (668:668:668)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -14059,11 +13364,11 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) (DELAY (ABSOLUTE - (PORT dataa (694:694:694) (723:723:723)) - (PORT datab (655:655:655) (675:675:675)) - (PORT datad (305:305:305) (311:311:311)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (454:454:454) (503:503:503)) + (PORT datab (581:581:581) (564:564:564)) + (PORT datad (827:827:827) (817:817:817)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14074,7 +13379,7 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -14088,9 +13393,9 @@ (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT datab (263:263:263) (337:337:337)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (641:641:641) (684:684:684)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -14102,12 +13407,13 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) (DELAY (ABSOLUTE - (PORT dataa (623:623:623) (626:626:626)) - (PORT datab (1302:1302:1302) (1247:1247:1247)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (574:574:574) (573:573:573)) + (PORT datab (598:598:598) (607:607:607)) + (PORT datac (654:654:654) (677:677:677)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -14117,13 +13423,13 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT asdata (812:812:812) (796:796:796)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL @@ -14131,9 +13437,9 @@ (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT dataa (410:410:410) (460:460:460)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (665:665:665) (689:689:689)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -14145,11 +13451,11 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (694:694:694) (723:723:723)) - (PORT datab (660:660:660) (683:683:683)) - (PORT datad (290:290:290) (293:293:293)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (453:453:453) (501:501:501)) + (PORT datab (546:546:546) (539:539:539)) + (PORT datad (831:831:831) (812:812:812)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14160,7 +13466,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -14174,9 +13480,9 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT dataa (655:655:655) (681:681:681)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (641:641:641) (663:663:663)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -14188,9 +13494,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (692:692:692) (722:722:722)) - (PORT datab (552:552:552) (534:534:534)) - (PORT datad (622:622:622) (641:641:641)) + (PORT dataa (452:452:452) (500:500:500)) + (PORT datab (1086:1086:1086) (1066:1066:1066)) + (PORT datad (830:830:830) (816:816:816)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -14203,7 +13509,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -14217,7 +13523,7 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (441:441:441) (474:474:474)) + (PORT datab (685:685:685) (711:711:711)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -14231,11 +13537,11 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (696:696:696) (727:727:727)) - (PORT datab (662:662:662) (686:686:686)) - (PORT datad (290:290:290) (295:295:295)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (454:454:454) (497:497:497)) + (PORT datab (929:929:929) (887:887:887)) + (PORT datad (822:822:822) (812:812:812)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14246,7 +13552,47 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datad (607:607:607) (634:634:634)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (496:496:496)) + (PORT datab (942:942:942) (906:906:906)) + (PORT datad (827:827:827) (818:818:818)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -14260,10 +13606,10 @@ (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (265:265:265) (344:344:344)) - (PORT datab (263:263:263) (337:337:337)) - (PORT datac (238:238:238) (309:309:309)) - (PORT datad (240:240:240) (300:300:300)) + (PORT dataa (247:247:247) (322:322:322)) + (PORT datab (244:244:244) (318:318:318)) + (PORT datac (237:237:237) (307:307:307)) + (PORT datad (221:221:221) (283:283:283)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -14273,25 +13619,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~18) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT datad (370:370:370) (409:409:409)) + (PORT dataa (1082:1082:1082) (1131:1131:1131)) + (PORT datab (788:788:788) (823:823:823)) + (PORT datac (589:589:589) (595:595:595)) + (PORT datad (623:623:623) (667:667:667)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) + (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (694:694:694) (723:723:723)) - (PORT datab (652:652:652) (672:672:672)) - (PORT datad (306:306:306) (314:314:314)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (597:597:597) (627:627:627)) + (PORT datab (621:621:621) (651:651:651)) + (PORT datac (530:530:530) (525:525:525)) + (PORT datad (286:286:286) (291:291:291)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (500:500:500)) + (PORT datab (518:518:518) (503:503:503)) + (PORT datad (823:823:823) (811:811:811)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14299,10 +13666,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[9\]) + (INSTANCE ula_\|video_\|vga_vc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -14311,46 +13678,14 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1328:1328:1328) (1359:1359:1359)) - (PORT datab (1198:1198:1198) (1221:1221:1221)) - (PORT datac (1138:1138:1138) (1184:1184:1184)) - (PORT datad (1053:1053:1053) (1063:1063:1063)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (644:644:644)) - (PORT datab (696:696:696) (723:723:723)) - (PORT datac (663:663:663) (697:697:697)) - (PORT datad (300:300:300) (301:301:301)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (695:695:695) (723:723:723)) - (PORT datab (312:312:312) (328:328:328)) - (PORT datad (624:624:624) (636:636:636)) + (PORT dataa (454:454:454) (499:499:499)) + (PORT datab (526:526:526) (522:522:522)) + (PORT datad (821:821:821) (812:812:812)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -14363,7 +13698,7 @@ (INSTANCE ula_\|video_\|vga_vc\[1\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -14386,10 +13721,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (1412:1412:1412) (1452:1452:1452)) - (PORT datab (1169:1169:1169) (1128:1128:1128)) - (PORT datac (1112:1112:1112) (1159:1159:1159)) - (PORT datad (1341:1341:1341) (1366:1366:1366)) + (PORT dataa (1332:1332:1332) (1337:1337:1337)) + (PORT datab (659:659:659) (713:713:713)) + (PORT datac (1648:1648:1648) (1616:1616:1616)) + (PORT datad (627:627:627) (644:644:644)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -14402,10 +13737,10 @@ (INSTANCE z80_\|pla_decode_\|Equal79\~0) (DELAY (ABSOLUTE - (PORT dataa (1117:1117:1117) (1138:1138:1138)) - (PORT datab (866:866:866) (883:883:883)) - (PORT datac (1490:1490:1490) (1515:1515:1515)) - (PORT datad (1493:1493:1493) (1523:1523:1523)) + (PORT dataa (1161:1161:1161) (1205:1205:1205)) + (PORT datab (912:912:912) (925:925:925)) + (PORT datac (1486:1486:1486) (1580:1580:1580)) + (PORT datad (1098:1098:1098) (1166:1166:1166)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -14413,30 +13748,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (317:317:317)) - (PORT datab (769:769:769) (765:765:765)) - (PORT datac (2629:2629:2629) (2600:2600:2600)) - (PORT datad (933:933:933) (898:898:898)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) (DELAY (ABSOLUTE - (PORT dataa (2635:2635:2635) (2609:2609:2609)) - (PORT datab (957:957:957) (934:934:934)) - (PORT datad (745:745:745) (733:733:733)) + (PORT dataa (1390:1390:1390) (1431:1431:1431)) + (PORT datab (333:333:333) (349:349:349)) + (PORT datad (607:607:607) (643:643:643)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -14449,11 +13768,11 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) (DELAY (ABSOLUTE - (PORT dataa (306:306:306) (410:410:410)) - (PORT datac (1074:1074:1074) (1123:1123:1123)) - (PORT datad (250:250:250) (325:325:325)) + (PORT dataa (327:327:327) (454:454:454)) + (PORT datab (1869:1869:1869) (1898:1898:1898)) + (PORT datad (251:251:251) (319:319:319)) (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -14463,7 +13782,7 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (1165:1165:1165) (1141:1141:1141)) + (PORT inclk[0] (1460:1460:1460) (1433:1433:1433)) ) ) ) @@ -14472,9 +13791,9 @@ (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1369:1369:1369)) + (PORT clk (1358:1358:1358) (1380:1380:1380)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1373:1373:1373) (1353:1353:1353)) + (PORT clrn (1376:1376:1376) (1354:1354:1354)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -14483,18 +13802,34 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (684:684:684)) + (PORT datab (242:242:242) (312:312:312)) + (PORT datac (184:184:184) (218:218:218)) + (PORT datad (1342:1342:1342) (1384:1384:1384)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|interrupts_\|iff1\~1) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (242:242:242) (313:313:313)) - (PORT datac (1469:1469:1469) (1445:1445:1445)) - (PORT datad (861:861:861) (874:874:874)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1188:1188:1188) (1199:1199:1199)) + (PORT datab (242:242:242) (312:312:312)) + (PORT datac (825:825:825) (840:840:840)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -14504,11 +13839,11 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT dataa (313:313:313) (422:422:422)) - (PORT datac (1074:1074:1074) (1124:1124:1124)) - (PORT datad (256:256:256) (328:328:328)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (1328:1328:1328) (1332:1332:1332)) + (PORT datac (1398:1398:1398) (1422:1422:1422)) + (PORT datad (1171:1171:1171) (1211:1211:1211)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -14518,9 +13853,9 @@ (INSTANCE z80_\|interrupts_\|iff1) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1369:1369:1369)) + (PORT clk (1358:1358:1358) (1380:1380:1380)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1312:1312:1312) (1282:1282:1282)) + (PORT clrn (1290:1290:1290) (1255:1255:1255)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -14534,10 +13869,10 @@ (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (1165:1165:1165) (1214:1214:1214)) - (PORT datab (1197:1197:1197) (1218:1218:1218)) - (PORT datac (660:660:660) (696:696:696)) - (PORT datad (1053:1053:1053) (1063:1063:1063)) + (PORT dataa (1477:1477:1477) (1499:1499:1499)) + (PORT datab (784:784:784) (804:804:804)) + (PORT datac (591:591:591) (619:619:619)) + (PORT datad (398:398:398) (440:440:440)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -14550,11 +13885,11 @@ (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT datab (695:695:695) (721:721:721)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (608:608:608) (601:601:601)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (531:531:531) (526:526:526)) + (PORT datad (405:405:405) (457:457:457)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -14564,10 +13899,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT dataa (1409:1409:1409) (1444:1444:1444)) - (PORT datab (825:825:825) (822:822:822)) - (PORT datac (1747:1747:1747) (1766:1766:1766)) - (PORT datad (1319:1319:1319) (1310:1310:1310)) + (PORT dataa (1091:1091:1091) (1093:1093:1093)) + (PORT datab (582:582:582) (590:590:590)) + (PORT datac (1420:1420:1420) (1485:1485:1485)) + (PORT datad (780:780:780) (777:777:777)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -14580,9 +13915,9 @@ (INSTANCE z80_\|interrupts_\|int_armed) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1379:1379:1379) (1357:1357:1357)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -14591,59 +13926,33 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_inst44\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1308:1308:1308) (1341:1341:1341)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|interrupts_\|DFFE_inst44) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1374:1374:1374)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1366:1366:1366)) - (PORT ena (875:875:875) (869:869:869)) + (PORT clk (1354:1354:1354) (1375:1375:1375)) + (PORT asdata (1978:1978:1978) (2024:2024:2024)) + (PORT clrn (1413:1413:1413) (1379:1379:1379)) + (PORT ena (1556:1556:1556) (1512:1512:1512)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (INSTANCE z80_\|execute_\|pc_inc_hold\~38) (DELAY (ABSOLUTE - (PORT dataa (304:304:304) (406:406:406)) - (PORT datab (275:275:275) (362:362:362)) - (PORT datac (225:225:225) (298:298:298)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (783:783:783)) - (PORT datab (884:884:884) (891:891:891)) - (PORT datac (859:859:859) (889:889:889)) - (PORT datad (488:488:488) (479:479:479)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (324:324:324) (445:445:445)) + (PORT datac (1096:1096:1096) (1138:1138:1138)) + (PORT datad (245:245:245) (311:311:311)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14651,15 +13960,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) (DELAY (ABSOLUTE - (PORT dataa (1066:1066:1066) (1075:1075:1075)) - (PORT datab (396:396:396) (408:408:408)) - (PORT datac (1173:1173:1173) (1154:1154:1154)) - (PORT datad (1131:1131:1131) (1085:1085:1085)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (1544:1544:1544) (1565:1565:1565)) + (PORT datab (1160:1160:1160) (1190:1190:1190)) + (PORT datac (895:895:895) (947:947:947)) + (PORT datad (810:810:810) (791:791:791)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14667,79 +13976,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (INSTANCE z80_\|execute_\|pc_inc_hold\~45) (DELAY (ABSOLUTE - (PORT dataa (1585:1585:1585) (1609:1609:1609)) - (PORT datab (1230:1230:1230) (1204:1204:1204)) - (PORT datac (1090:1090:1090) (1113:1113:1113)) - (PORT datad (1584:1584:1584) (1569:1569:1569)) - (IOPATH dataa combout (307:307:307) (323:323:323)) + (PORT dataa (1008:1008:1008) (1008:1008:1008)) + (PORT datab (651:651:651) (683:683:683)) + (PORT datac (1101:1101:1101) (1142:1142:1142)) + (PORT datad (580:580:580) (593:593:593)) + (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (790:790:790) (777:777:777)) - (PORT datab (604:604:604) (596:596:596)) - (PORT datac (741:741:741) (730:730:730)) - (PORT datad (575:575:575) (588:588:588)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (218:218:218)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datac (763:763:763) (739:739:739)) - (PORT datad (1324:1324:1324) (1321:1321:1321)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (607:607:607) (623:623:623)) - (PORT datac (599:599:599) (622:622:622)) - (PORT datad (795:795:795) (780:780:780)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (654:654:654)) - (PORT datab (624:624:624) (646:646:646)) - (PORT datac (741:741:741) (713:713:713)) - (PORT datad (572:572:572) (577:577:577)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14747,15 +13992,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (INSTANCE z80_\|execute_\|pc_inc_hold\~44) (DELAY (ABSOLUTE - (PORT dataa (839:839:839) (838:838:838)) - (PORT datab (1352:1352:1352) (1364:1364:1364)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (177:177:177) (199:199:199)) + (PORT dataa (1011:1011:1011) (1009:1009:1009)) + (PORT datab (847:847:847) (880:880:880)) + (PORT datac (793:793:793) (800:800:800)) + (PORT datad (1020:1020:1020) (981:981:981)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~46) + (DELAY + (ABSOLUTE + (PORT dataa (310:310:310) (332:332:332)) + (PORT datab (654:654:654) (687:687:687)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (1024:1024:1024) (986:986:986)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14763,13 +14024,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (INSTANCE z80_\|execute_\|pc_inc_hold\~37) (DELAY (ABSOLUTE - (PORT dataa (1071:1071:1071) (1090:1090:1090)) - (PORT datab (808:808:808) (784:784:784)) - (PORT datac (1053:1053:1053) (1062:1062:1062)) - (PORT datad (1452:1452:1452) (1438:1438:1438)) + (PORT dataa (1077:1077:1077) (1102:1102:1102)) + (PORT datab (822:822:822) (841:841:841)) + (PORT datac (987:987:987) (979:979:979)) + (PORT datad (184:184:184) (209:209:209)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~50) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (772:772:772)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1461:1461:1461) (1534:1534:1534)) + (PORT datad (2107:2107:2107) (2149:2149:2149)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (249:249:249)) + (PORT datab (1071:1071:1071) (1094:1094:1094)) + (PORT datac (1006:1006:1006) (997:997:997)) + (PORT datad (551:551:551) (559:559:559)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -14782,10 +14075,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) (DELAY (ABSOLUTE - (PORT dataa (847:847:847) (864:864:864)) - (PORT datab (1193:1193:1193) (1166:1166:1166)) - (PORT datac (1065:1065:1065) (1074:1074:1074)) - (PORT datad (1607:1607:1607) (1551:1551:1551)) + (PORT dataa (1554:1554:1554) (1584:1584:1584)) + (PORT datab (576:576:576) (597:597:597)) + (PORT datac (1526:1526:1526) (1554:1554:1554)) + (PORT datad (1081:1081:1081) (1112:1112:1112)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -14795,29 +14088,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) (DELAY (ABSOLUTE - (PORT dataa (1032:1032:1032) (1037:1037:1037)) - (PORT datab (658:658:658) (710:710:710)) - (PORT datac (518:518:518) (514:514:514)) - (PORT datad (1004:1004:1004) (987:987:987)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (672:672:672) (721:721:721)) + (PORT datab (626:626:626) (663:663:663)) + (PORT datac (1059:1059:1059) (1071:1071:1071)) + (PORT datad (193:193:193) (224:224:224)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (INSTANCE z80_\|execute_\|pc_inc_hold\~31) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (361:361:361)) - (PORT datab (824:824:824) (835:835:835)) - (PORT datac (161:161:161) (197:197:197)) - (PORT datad (164:164:164) (188:188:188)) + (PORT dataa (1035:1035:1035) (1028:1028:1028)) + (PORT datab (794:794:794) (779:779:779)) + (PORT datac (1125:1125:1125) (1118:1118:1118)) + (PORT datad (765:765:765) (755:755:755)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1034:1034:1034) (1031:1031:1031)) + (PORT datab (575:575:575) (597:597:597)) + (PORT datac (186:186:186) (226:226:226)) + (PORT datad (1521:1521:1521) (1537:1537:1537)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~34) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (174:174:174) (216:216:216)) + (PORT datad (165:165:165) (189:189:189)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -14827,15 +14152,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (INSTANCE z80_\|execute_\|pc_inc_hold\~51) (DELAY (ABSOLUTE - (PORT dataa (1033:1033:1033) (1038:1038:1038)) - (PORT datab (835:835:835) (812:812:812)) - (PORT datac (630:630:630) (680:680:680)) - (PORT datad (753:753:753) (730:730:730)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1062:1062:1062) (1079:1079:1079)) + (PORT datab (1294:1294:1294) (1329:1329:1329)) + (PORT datac (2314:2314:2314) (2350:2350:2350)) + (PORT datad (1371:1371:1371) (1420:1420:1420)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14843,47 +14168,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~41) + (INSTANCE z80_\|execute_\|pc_inc_hold\~30) (DELAY (ABSOLUTE - (PORT dataa (924:924:924) (989:989:989)) - (PORT datab (923:923:923) (976:976:976)) - (PORT datac (1102:1102:1102) (1135:1135:1135)) - (PORT datad (883:883:883) (939:939:939)) + (PORT dataa (631:631:631) (660:660:660)) + (PORT datab (1059:1059:1059) (1088:1088:1088)) + (PORT datac (334:334:334) (351:351:351)) + (PORT datad (791:791:791) (793:793:793)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1451:1451:1451)) + (PORT datab (1290:1290:1290) (1325:1325:1325)) + (PORT datac (2318:2318:2318) (2353:2353:2353)) + (PORT datad (980:980:980) (990:990:990)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (361:361:361)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (574:574:574) (576:576:576)) + (PORT datad (164:164:164) (187:187:187)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1029:1029:1029) (1017:1017:1017)) + (PORT datab (595:595:595) (607:607:607)) + (PORT datac (578:578:578) (566:566:566)) + (PORT datad (1278:1278:1278) (1289:1289:1289)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~21) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (733:733:733)) - (PORT datab (956:956:956) (954:954:954)) - (PORT datac (647:647:647) (706:706:706)) - (PORT datad (934:934:934) (985:985:985)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~26) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (252:252:252)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datac (574:574:574) (595:595:595)) - (PORT datad (564:564:564) (571:571:571)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14894,390 +14235,10 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) (DELAY (ABSOLUTE - (PORT dataa (894:894:894) (941:941:941)) - (PORT datab (805:805:805) (799:799:799)) - (PORT datac (944:944:944) (935:935:935)) - (PORT datad (798:798:798) (789:789:789)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (362:362:362)) - (PORT datab (804:804:804) (821:821:821)) - (PORT datac (967:967:967) (955:955:955)) - (PORT datad (754:754:754) (757:757:757)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (1536:1536:1536) (1559:1559:1559)) - (PORT datac (865:865:865) (908:908:908)) - (PORT datad (779:779:779) (756:756:756)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (605:605:605)) - (PORT datab (186:186:186) (224:224:224)) - (PORT datac (746:746:746) (733:733:733)) - (PORT datad (1316:1316:1316) (1317:1317:1317)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (174:174:174) (205:205:205)) - (PORT datad (736:736:736) (711:711:711)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (1055:1055:1055) (1043:1043:1043)) - (PORT datab (1022:1022:1022) (1024:1024:1024)) - (PORT datac (522:522:522) (507:507:507)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (898:898:898)) - (PORT datac (684:684:684) (662:662:662)) - (PORT datad (848:848:848) (888:888:888)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1160:1160:1160)) - (PORT datab (1314:1314:1314) (1317:1317:1317)) - (PORT datac (1071:1071:1071) (1090:1090:1090)) - (PORT datad (1047:1047:1047) (1068:1068:1068)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~27) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (631:631:631)) - (PORT datab (1187:1187:1187) (1175:1175:1175)) - (PORT datac (721:721:721) (702:702:702)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (644:644:644)) - (PORT datab (872:872:872) (921:921:921)) - (PORT datac (594:594:594) (613:613:613)) - (PORT datad (833:833:833) (855:855:855)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (218:218:218)) - (PORT datab (629:629:629) (623:623:623)) - (PORT datac (944:944:944) (927:927:927)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1031:1031:1031) (1026:1026:1026)) - (PORT datab (777:777:777) (776:776:776)) - (PORT datac (554:554:554) (551:551:551)) - (PORT datad (777:777:777) (778:778:778)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (962:962:962)) - (PORT datab (629:629:629) (623:623:623)) - (PORT datac (162:162:162) (195:195:195)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (987:987:987)) - (PORT datab (923:923:923) (976:976:976)) - (PORT datac (950:950:950) (938:938:938)) - (PORT datad (167:167:167) (193:193:193)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) - (DELAY - (ABSOLUTE - (PORT dataa (764:764:764) (764:764:764)) - (PORT datab (778:778:778) (781:781:781)) - (PORT datac (998:998:998) (995:995:995)) - (PORT datad (776:776:776) (777:777:777)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) - (DELAY - (ABSOLUTE - (PORT dataa (311:311:311) (418:418:418)) - (PORT datab (280:280:280) (367:367:367)) - (PORT datac (223:223:223) (294:294:294)) - (PORT datad (792:792:792) (789:789:789)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (363:363:363)) - (PORT datab (659:659:659) (711:711:711)) - (PORT datac (459:459:459) (446:446:446)) - (PORT datad (1504:1504:1504) (1499:1499:1499)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1029:1029:1029) (1025:1025:1025)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (1005:1005:1005) (1008:1008:1008)) - (PORT datad (319:319:319) (325:325:325)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (543:543:543)) - (PORT datab (1087:1087:1087) (1117:1117:1117)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1091:1091:1091) (1104:1104:1104)) - (PORT datab (658:658:658) (710:710:710)) - (PORT datac (809:809:809) (829:829:829)) - (PORT datad (1607:1607:1607) (1551:1551:1551)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (361:361:361)) - (PORT datab (188:188:188) (222:222:222)) - (PORT datac (1185:1185:1185) (1157:1157:1157)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1249:1249:1249) (1266:1266:1266)) - (PORT datab (635:635:635) (696:696:696)) - (PORT datac (665:665:665) (736:736:736)) - (PORT datad (930:930:930) (980:980:980)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (251:251:251)) - (PORT datab (500:500:500) (504:504:504)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (595:595:595) (613:613:613)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (254:254:254)) - (PORT datac (577:577:577) (597:597:597)) - (PORT datad (169:169:169) (197:197:197)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (777:777:777)) - (PORT datab (977:977:977) (1025:1025:1025)) - (PORT datac (604:604:604) (667:667:667)) - (PORT datad (1192:1192:1192) (1169:1169:1169)) + (PORT dataa (1920:1920:1920) (1948:1948:1948)) + (PORT datab (847:847:847) (880:880:880)) + (PORT datac (1304:1304:1304) (1325:1325:1325)) + (PORT datad (594:594:594) (621:621:621)) (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -15287,183 +14248,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (553:553:553) (570:570:570)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (1585:1585:1585) (1609:1609:1609)) - (PORT datab (1250:1250:1250) (1271:1271:1271)) - (PORT datac (1089:1089:1089) (1114:1114:1114)) - (PORT datad (1028:1028:1028) (1031:1031:1031)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT datab (779:779:779) (768:768:768)) - (PORT datac (922:922:922) (899:899:899)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (254:254:254)) - (PORT datac (1182:1182:1182) (1152:1152:1152)) - (PORT datad (168:168:168) (196:196:196)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (550:550:550) (555:555:555)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (615:615:615)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (748:748:748) (743:743:743)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (500:500:500) (497:497:497)) - (PORT datab (187:187:187) (221:221:221)) - (PORT datac (163:163:163) (198:198:198)) - (PORT datad (164:164:164) (190:190:190)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (340:340:340)) - (PORT datab (748:748:748) (744:744:744)) - (PORT datad (779:779:779) (765:765:765)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (1050:1050:1050) (1062:1062:1062)) - (PORT datab (1073:1073:1073) (1072:1072:1072)) - (PORT datac (1091:1091:1091) (1113:1113:1113)) - (PORT datad (935:935:935) (918:918:918)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1127:1127:1127)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (579:579:579) (574:574:574)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1273:1273:1273) (1289:1289:1289)) - (PORT datab (214:214:214) (257:257:257)) - (PORT datac (2174:2174:2174) (2160:2160:2160)) - (PORT datad (1712:1712:1712) (1770:1770:1770)) + (PORT dataa (1231:1231:1231) (1280:1280:1280)) + (PORT datab (1626:1626:1626) (1684:1684:1684)) + (PORT datad (587:587:587) (607:607:607)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) (DELAY (ABSOLUTE - (PORT dataa (643:643:643) (690:690:690)) - (PORT datab (1066:1066:1066) (1103:1103:1103)) - (PORT datac (1815:1815:1815) (1848:1848:1848)) - (PORT datad (678:678:678) (654:654:654)) + (PORT dataa (196:196:196) (240:240:240)) + (PORT datab (195:195:195) (236:236:236)) + (PORT datac (621:621:621) (640:640:640)) + (PORT datad (531:531:531) (525:525:525)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1317:1317:1317) (1312:1312:1312)) + (PORT datab (618:618:618) (637:637:637)) + (PORT datac (1836:1836:1836) (1869:1869:1869)) + (PORT datad (1153:1153:1153) (1156:1156:1156)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -15476,27 +14297,137 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) (DELAY (ABSOLUTE - (PORT dataa (1030:1030:1030) (1025:1025:1025)) - (PORT datab (817:817:817) (844:844:844)) - (PORT datac (1205:1205:1205) (1195:1195:1195)) - (PORT datad (777:777:777) (774:774:774)) - (IOPATH dataa combout (265:265:265) (269:269:269)) + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (578:578:578) (601:601:601)) + (PORT datad (173:173:173) (201:201:201)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (378:378:378)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (582:582:582) (587:587:587)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (637:637:637)) + (PORT datab (651:651:651) (684:684:684)) + (PORT datac (584:584:584) (587:587:587)) + (PORT datad (1073:1073:1073) (1095:1095:1095)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1574:1574:1574)) + (PORT datab (981:981:981) (1037:1037:1037)) + (PORT datac (567:567:567) (581:581:581)) + (PORT datad (902:902:902) (949:949:949)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~39) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (238:238:238)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (579:579:579) (567:567:567)) + (PORT datad (526:526:526) (520:520:520)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~47) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (377:377:377)) + (PORT datab (194:194:194) (231:231:231)) + (PORT datac (581:581:581) (601:601:601)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) (DELAY (ABSOLUTE - (PORT dataa (191:191:191) (232:232:232)) - (PORT datab (788:788:788) (747:747:747)) - (PORT datac (753:753:753) (756:756:756)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (199:199:199) (233:233:233)) + (PORT datac (817:817:817) (795:795:795)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (DELAY + (ABSOLUTE + (PORT datab (189:189:189) (224:224:224)) + (PORT datac (582:582:582) (603:603:603)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (319:319:319) (333:333:333)) + (PORT datac (584:584:584) (590:590:590)) + (PORT datad (167:167:167) (194:194:194)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -15508,130 +14439,10 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) (DELAY (ABSOLUTE - (PORT dataa (190:190:190) (230:230:230)) - (PORT datab (582:582:582) (570:570:570)) - (PORT datac (752:752:752) (753:753:753)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1199:1199:1199) (1174:1174:1174)) - (PORT datac (1151:1151:1151) (1114:1114:1114)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (935:935:935) (942:942:942)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1753:1753:1753) (1751:1751:1751)) - (PORT datab (193:193:193) (229:229:229)) - (PORT datac (747:747:747) (753:753:753)) - (PORT datad (1170:1170:1170) (1131:1131:1131)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) - (DELAY - (ABSOLUTE - (PORT datab (766:766:766) (756:756:756)) - (PORT datad (972:972:972) (978:978:978)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (661:661:661)) - (PORT datab (1804:1804:1804) (1829:1829:1829)) - (PORT datac (738:738:738) (719:719:719)) - (PORT datad (1302:1302:1302) (1280:1280:1280)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1505:1505:1505) (1502:1502:1502)) - (PORT datab (960:960:960) (1003:1003:1003)) - (PORT datac (324:324:324) (338:338:338)) - (PORT datad (861:861:861) (913:913:913)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1256:1256:1256) (1274:1274:1274)) - (PORT datab (505:505:505) (499:499:499)) - (PORT datac (1070:1070:1070) (1090:1090:1090)) - (PORT datad (723:723:723) (713:713:713)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1143:1143:1143)) - (PORT datab (512:512:512) (515:515:515)) - (PORT datac (1203:1203:1203) (1181:1181:1181)) - (PORT datad (514:514:514) (502:502:502)) + (PORT dataa (618:618:618) (636:636:636)) + (PORT datab (848:848:848) (883:883:883)) + (PORT datac (1100:1100:1100) (1143:1143:1143)) + (PORT datad (171:171:171) (199:199:199)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -15641,79 +14452,155 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~54) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) (DELAY (ABSOLUTE - (PORT dataa (1090:1090:1090) (1074:1074:1074)) - (PORT datab (2004:2004:2004) (2008:2008:2008)) - (PORT datac (772:772:772) (785:785:785)) - (PORT datad (851:851:851) (880:880:880)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1224:1224:1224) (1197:1197:1197)) - (PORT datab (569:569:569) (588:588:588)) - (PORT datac (597:597:597) (606:606:606)) - (PORT datad (1037:1037:1037) (1045:1045:1045)) + (PORT dataa (815:815:815) (833:833:833)) + (PORT datab (632:632:632) (662:662:662)) + (PORT datac (893:893:893) (935:935:935)) + (PORT datad (575:575:575) (598:598:598)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~20) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (237:237:237)) - (PORT datab (1107:1107:1107) (1088:1088:1088)) - (PORT datac (770:770:770) (766:766:766)) - (PORT datad (183:183:183) (207:207:207)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1477:1477:1477) (1458:1458:1458)) - (PORT datab (815:815:815) (829:829:829)) - (PORT datac (793:793:793) (778:778:778)) - (PORT datad (1820:1820:1820) (1779:1779:1779)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1666:1666:1666) (1614:1614:1614)) - (PORT datab (206:206:206) (243:243:243)) - (PORT datac (340:340:340) (368:368:368)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (307:307:307) (280:280:280)) + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (624:624:624) (666:666:666)) + (PORT datac (899:899:899) (931:931:931)) + (PORT datad (1543:1543:1543) (1538:1538:1538)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (312:312:312) (331:331:331)) + (PORT datac (583:583:583) (588:588:588)) + (PORT datad (334:334:334) (333:333:333)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) + (DELAY + (ABSOLUTE + (PORT datab (186:186:186) (221:221:221)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~42) + (DELAY + (ABSOLUTE + (PORT datab (603:603:603) (606:606:606)) + (PORT datac (315:315:315) (333:333:333)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (985:985:985)) + (PORT datab (1013:1013:1013) (1022:1022:1022)) + (PORT datac (1086:1086:1086) (1108:1108:1108)) + (PORT datad (1371:1371:1371) (1420:1420:1420)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~41) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (580:580:580) (599:599:599)) + (PORT datac (186:186:186) (223:223:223)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (453:453:453)) + (PORT datab (841:841:841) (855:855:855)) + (PORT datac (1095:1095:1095) (1138:1138:1138)) + (PORT datad (249:249:249) (317:317:317)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (1034:1034:1034) (1029:1029:1029)) + (PORT datab (205:205:205) (243:243:243)) + (PORT datac (175:175:175) (220:220:220)) + (PORT datad (804:804:804) (807:807:807)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (1338:1338:1338) (1364:1364:1364)) + (PORT datab (179:179:179) (212:212:212)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (1522:1522:1522) (1538:1538:1538)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -15721,15 +14608,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~45) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) (DELAY (ABSOLUTE - (PORT dataa (491:491:491) (498:498:498)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (488:488:488) (475:475:475)) - (PORT datad (820:820:820) (836:836:836)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (1034:1034:1034) (1029:1029:1029)) + (PORT datab (212:212:212) (249:249:249)) + (PORT datac (175:175:175) (219:219:219)) + (PORT datad (550:550:550) (559:559:559)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -15737,14 +14624,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~46) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) (DELAY (ABSOLUTE - (PORT dataa (753:753:753) (766:766:766)) - (PORT datab (598:598:598) (608:608:608)) - (PORT datac (1009:1009:1009) (1007:1007:1007)) - (PORT datad (294:294:294) (293:293:293)) + (PORT dataa (812:812:812) (790:790:790)) + (PORT datab (1045:1045:1045) (1051:1051:1051)) + (PORT datac (319:319:319) (335:335:335)) + (PORT datad (796:796:796) (792:792:792)) (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1069:1069:1069)) + (PORT datab (349:349:349) (358:358:358)) + (PORT datac (290:290:290) (293:293:293)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (308:308:308) (313:313:313)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -15753,120 +14672,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~39) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) (DELAY (ABSOLUTE - (PORT dataa (767:767:767) (761:761:761)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (503:503:503) (490:490:490)) - (PORT datad (168:168:168) (197:197:197)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (507:507:507) (500:500:500)) - (PORT datad (562:562:562) (563:563:563)) + (PORT dataa (616:616:616) (636:636:636)) + (PORT datab (384:384:384) (391:391:391)) + (PORT datac (1039:1039:1039) (1029:1029:1029)) + (PORT datad (795:795:795) (794:794:794)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (1572:1572:1572) (1613:1613:1613)) - (PORT datac (1495:1495:1495) (1488:1488:1488)) - (PORT datad (1400:1400:1400) (1343:1343:1343)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (917:917:917) (932:932:932)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|db\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1574:1574:1574) (1606:1606:1606)) - (PORT datab (1791:1791:1791) (1764:1764:1764)) - (PORT datad (1402:1402:1402) (1343:1343:1343)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (1633:1633:1633) (1688:1688:1688)) - (PORT datac (983:983:983) (980:980:980)) - (PORT datad (1255:1255:1255) (1231:1231:1231)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (914:914:914) (912:912:912)) - (PORT ena (1109:1109:1109) (1075:1075:1075)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT datab (1634:1634:1634) (1690:1690:1690)) - (PORT datac (972:972:972) (947:947:947)) - (PORT datad (1253:1253:1253) (1233:1233:1233)) - (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -15874,43 +14688,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) (DELAY (ABSOLUTE - (PORT datab (1639:1639:1639) (1694:1694:1694)) - (PORT datac (973:973:973) (948:948:948)) - (PORT datad (1249:1249:1249) (1226:1226:1226)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (916:916:916) (910:910:910)) - (PORT ena (1094:1094:1094) (1065:1065:1065)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT datab (1619:1619:1619) (1669:1669:1669)) - (PORT datac (985:985:985) (983:983:983)) - (PORT datad (1256:1256:1256) (1234:1234:1234)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (615:615:615) (641:641:641)) + (PORT datab (870:870:870) (898:898:898)) + (PORT datac (1048:1048:1048) (1038:1038:1038)) + (PORT datad (1587:1587:1587) (1611:1611:1611)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -15918,300 +14704,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (294:294:294)) - (PORT datab (632:632:632) (643:643:643)) - (PORT datad (605:605:605) (615:615:615)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT datab (1019:1019:1019) (983:983:983)) - (PORT datac (1587:1587:1587) (1641:1641:1641)) - (PORT datad (1256:1256:1256) (1228:1228:1228)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1374:1374:1374)) - (PORT asdata (910:910:910) (931:931:931)) - (PORT ena (739:739:739) (742:742:742)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT datab (1016:1016:1016) (984:984:984)) - (PORT datac (1594:1594:1594) (1648:1648:1648)) - (PORT datad (1254:1254:1254) (1232:1232:1232)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) (DELAY (ABSOLUTE (PORT dataa (349:349:349) (355:355:355)) - (PORT datab (601:601:601) (592:592:592)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT datac (1769:1769:1769) (1771:1771:1771)) - (PORT datad (963:963:963) (928:928:928)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1309:1309:1309) (1374:1374:1374)) - (PORT datab (595:595:595) (641:641:641)) - (PORT datac (505:505:505) (509:509:509)) - (PORT datad (1190:1190:1190) (1177:1177:1177)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (954:954:954)) - (PORT datab (816:816:816) (792:792:792)) - (PORT datac (843:843:843) (857:857:857)) - (PORT datad (1054:1054:1054) (1041:1041:1041)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1296:1296:1296)) - (PORT datac (1119:1119:1119) (1188:1188:1188)) - (PORT datad (1245:1245:1245) (1224:1224:1224)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1291:1291:1291)) - (PORT datab (1303:1303:1303) (1307:1307:1307)) - (PORT datac (1224:1224:1224) (1218:1218:1218)) - (PORT datad (1223:1223:1223) (1241:1241:1241)) + (PORT datab (1054:1054:1054) (1048:1048:1048)) + (PORT datac (972:972:972) (945:945:945)) + (PORT datad (1110:1110:1110) (1100:1100:1100)) (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (616:616:616)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (807:807:807) (817:817:817)) - (PORT datad (784:784:784) (800:800:800)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (805:805:805)) - (PORT datab (1540:1540:1540) (1529:1529:1529)) - (PORT datac (800:800:800) (818:818:818)) - (PORT datad (1078:1078:1078) (1072:1072:1072)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1217:1217:1217) (1218:1218:1218)) - (PORT datab (1196:1196:1196) (1191:1191:1191)) - (PORT datac (3041:3041:3041) (2998:2998:2998)) - (PORT datad (633:633:633) (658:658:658)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) - (DELAY - (ABSOLUTE - (PORT dataa (984:984:984) (989:989:989)) - (PORT datab (852:852:852) (885:885:885)) - (PORT datad (960:960:960) (937:937:937)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1343:1343:1343) (1394:1394:1394)) - (PORT datab (1009:1009:1009) (983:983:983)) - (PORT datac (1298:1298:1298) (1291:1291:1291)) - (PORT datad (1019:1019:1019) (1014:1014:1014)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (260:260:260)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (838:838:838) (846:846:846)) - (PORT datad (988:988:988) (973:973:973)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT datac (821:821:821) (863:863:863)) - (PORT datad (746:746:746) (738:738:738)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1194:1194:1194)) - (PORT datab (1557:1557:1557) (1554:1554:1554)) - (PORT datac (803:803:803) (805:805:805)) - (PORT datad (809:809:809) (823:823:823)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1073:1073:1073)) - (PORT datab (1347:1347:1347) (1388:1388:1388)) - (PORT datac (1309:1309:1309) (1337:1337:1337)) - (PORT datad (1089:1089:1089) (1134:1134:1134)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (229:229:229)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (305:305:305) (314:314:314)) - (PORT datad (862:862:862) (880:880:880)) - (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -16220,477 +14720,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) (DELAY (ABSOLUTE - (PORT dataa (338:338:338) (359:359:359)) - (PORT datab (503:503:503) (508:508:508)) - (PORT datac (509:509:509) (508:508:508)) - (PORT datad (602:602:602) (631:631:631)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (237:237:237)) - (PORT datab (198:198:198) (242:242:242)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (591:591:591) (610:610:610)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1199:1199:1199)) - (PORT datab (1554:1554:1554) (1560:1560:1560)) - (PORT datac (516:516:516) (516:516:516)) - (PORT datad (1054:1054:1054) (1077:1077:1077)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2084:2084:2084) (2089:2089:2089)) - (PORT datab (2007:2007:2007) (2070:2070:2070)) - (PORT datac (1291:1291:1291) (1308:1308:1308)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (962:962:962)) - (PORT datab (1275:1275:1275) (1328:1328:1328)) - (PORT datac (1574:1574:1574) (1630:1630:1630)) - (PORT datad (1557:1557:1557) (1600:1600:1600)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (841:841:841)) - (PORT datab (569:569:569) (572:572:572)) - (PORT datac (736:736:736) (712:712:712)) - (PORT datad (1384:1384:1384) (1433:1433:1433)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1048:1048:1048)) - (PORT datab (570:570:570) (599:599:599)) - (PORT datac (787:787:787) (778:778:778)) - (PORT datad (544:544:544) (566:566:566)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (858:858:858)) - (PORT datab (847:847:847) (842:842:842)) - (PORT datac (1186:1186:1186) (1175:1175:1175)) - (PORT datad (1176:1176:1176) (1142:1142:1142)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (359:359:359)) - (PORT datab (636:636:636) (666:666:666)) - (PORT datac (510:510:510) (512:512:512)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1239:1239:1239) (1252:1252:1252)) - (PORT datab (816:816:816) (826:826:826)) - (PORT datac (1053:1053:1053) (1069:1069:1069)) - (PORT datad (1232:1232:1232) (1237:1237:1237)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1234:1234:1234) (1246:1246:1246)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (706:706:706) (684:684:684)) - (PORT datad (1230:1230:1230) (1229:1229:1229)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1359:1359:1359) (1401:1401:1401)) - (PORT datab (1391:1391:1391) (1422:1422:1422)) - (PORT datac (1060:1060:1060) (1071:1071:1071)) - (PORT datad (1296:1296:1296) (1284:1284:1284)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (342:342:342)) - (PORT datab (1165:1165:1165) (1205:1205:1205)) - (PORT datac (1081:1081:1081) (1133:1133:1133)) - (PORT datad (956:956:956) (920:920:920)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (841:841:841)) - (PORT datab (581:581:581) (592:592:592)) - (PORT datac (321:321:321) (335:335:335)) - (PORT datad (165:165:165) (190:190:190)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datac (934:934:934) (902:902:902)) - (PORT datad (569:569:569) (587:587:587)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (871:871:871) (887:887:887)) - (PORT datab (207:207:207) (243:243:243)) - (PORT datac (897:897:897) (918:918:918)) - (PORT datad (590:590:590) (609:609:609)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (260:260:260)) - (PORT datab (869:869:869) (874:874:874)) - (PORT datac (168:168:168) (203:203:203)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal72\~2) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (960:960:960)) - (PORT datab (902:902:902) (948:948:948)) - (PORT datac (2074:2074:2074) (2051:2051:2051)) - (PORT datad (554:554:554) (551:551:551)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1035:1035:1035) (1013:1013:1013)) - (PORT datab (2035:2035:2035) (2060:2060:2060)) - (PORT datac (538:538:538) (544:544:544)) - (PORT datad (545:545:545) (544:544:544)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (962:962:962)) - (PORT datab (901:901:901) (947:947:947)) - (PORT datac (2072:2072:2072) (2050:2050:2050)) - (PORT datad (555:555:555) (549:549:549)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1146:1146:1146) (1155:1155:1155)) - (PORT datab (1074:1074:1074) (1051:1051:1051)) - (PORT datac (798:798:798) (815:815:815)) - (PORT datad (992:992:992) (970:970:970)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1035:1035:1035) (1024:1024:1024)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (162:162:162) (195:195:195)) - (PORT datad (928:928:928) (903:903:903)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (590:590:590)) - (PORT datab (194:194:194) (231:231:231)) - (PORT datac (163:163:163) (196:196:196)) - (PORT datad (1352:1352:1352) (1291:1291:1291)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (746:746:746) (749:749:749)) - (PORT datab (604:604:604) (621:621:621)) - (PORT datac (799:799:799) (806:806:806)) - (PORT datad (591:591:591) (607:607:607)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (599:599:599) (602:602:602)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (581:581:581) (583:583:583)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1293:1293:1293)) - (PORT datab (1247:1247:1247) (1278:1278:1278)) - (PORT datac (1468:1468:1468) (1445:1445:1445)) - (PORT datad (1244:1244:1244) (1225:1225:1225)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (643:643:643)) - (PORT datab (200:200:200) (246:246:246)) - (PORT datac (300:300:300) (314:314:314)) - (PORT datad (173:173:173) (202:202:202)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (353:353:353)) - (PORT datab (804:804:804) (773:773:773)) - (PORT datac (528:528:528) (520:520:520)) - (PORT datad (180:180:180) (202:202:202)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1273:1273:1273)) - (PORT datab (1079:1079:1079) (1100:1100:1100)) - (PORT datac (1054:1054:1054) (1089:1089:1089)) - (PORT datad (1089:1089:1089) (1137:1137:1137)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (223:223:223) (261:261:261)) - (PORT datac (1382:1382:1382) (1423:1423:1423)) - (PORT datad (505:505:505) (493:493:493)) + (PORT dataa (603:603:603) (639:639:639)) + (PORT datab (843:843:843) (842:842:842)) + (PORT datac (842:842:842) (866:866:866)) + (PORT datad (294:294:294) (292:292:292)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -16700,29 +14736,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) (DELAY (ABSOLUTE - (PORT dataa (1472:1472:1472) (1432:1432:1432)) - (PORT datab (597:597:597) (595:595:595)) - (PORT datac (766:766:766) (748:748:748)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (758:758:758) (740:740:740)) - (PORT datab (792:792:792) (768:768:768)) - (PORT datac (1020:1020:1020) (999:999:999)) - (PORT datad (482:482:482) (461:461:461)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (842:842:842) (884:884:884)) + (PORT datab (831:831:831) (839:839:839)) + (PORT datac (1318:1318:1318) (1302:1302:1302)) + (PORT datad (794:794:794) (793:793:793)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -16730,79 +14752,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (238:238:238)) - (PORT datab (199:199:199) (233:233:233)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (811:811:811) (813:813:813)) - (PORT datab (194:194:194) (231:231:231)) - (PORT datac (773:773:773) (770:770:770)) - (PORT datad (795:795:795) (794:794:794)) + (PORT dataa (1346:1346:1346) (1338:1338:1338)) + (PORT datab (841:841:841) (888:888:888)) + (PORT datac (300:300:300) (317:317:317)) + (PORT datad (160:160:160) (181:181:181)) (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1015:1015:1015) (984:984:984)) - (PORT datab (1043:1043:1043) (1035:1035:1035)) - (PORT datac (757:757:757) (727:727:727)) - (PORT datad (797:797:797) (774:774:774)) - (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (819:819:819)) - (PORT datab (1050:1050:1050) (1028:1028:1028)) - (PORT datac (1572:1572:1572) (1523:1523:1523)) - (PORT datad (1215:1215:1215) (1191:1191:1191)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (379:379:379)) - (PORT datab (212:212:212) (253:253:253)) - (PORT datac (1012:1012:1012) (995:995:995)) - (PORT datad (1467:1467:1467) (1465:1465:1465)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -16810,93 +14768,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) (DELAY (ABSOLUTE - (PORT dataa (545:545:545) (540:540:540)) - (PORT datab (226:226:226) (274:274:274)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (166:166:166) (192:192:192)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (549:549:549)) - (PORT datab (202:202:202) (236:236:236)) + (PORT dataa (205:205:205) (251:251:251)) + (PORT datab (183:183:183) (217:217:217)) (PORT datac (154:154:154) (184:184:184)) - (PORT datad (768:768:768) (745:745:745)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (802:802:802) (817:817:817)) - (PORT datab (2008:2008:2008) (2069:2069:2069)) - (PORT datac (1520:1520:1520) (1518:1518:1518)) - (PORT datad (803:803:803) (798:798:798)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (621:621:621)) - (PORT datab (2206:2206:2206) (2218:2218:2218)) - (PORT datac (1037:1037:1037) (1059:1059:1059)) - (PORT datad (592:592:592) (608:608:608)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (347:347:347)) - (PORT datab (350:350:350) (366:366:366)) - (PORT datac (558:558:558) (567:567:567)) - (PORT datad (752:752:752) (739:739:739)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (801:801:801)) - (PORT datab (552:552:552) (534:534:534)) - (PORT datac (815:815:815) (824:824:824)) - (PORT datad (774:774:774) (752:752:752)) + (PORT datad (548:548:548) (534:534:534)) (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -16906,93 +14784,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) (DELAY (ABSOLUTE - (PORT dataa (769:769:769) (774:774:774)) - (PORT datab (902:902:902) (915:915:915)) - (PORT datac (818:818:818) (860:860:860)) - (PORT datad (166:166:166) (192:192:192)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (355:355:355)) - (PORT datab (808:808:808) (820:820:820)) - (PORT datac (512:512:512) (512:512:512)) - (PORT datad (570:570:570) (577:577:577)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (240:240:240)) - (PORT datab (199:199:199) (241:241:241)) - (PORT datac (736:736:736) (726:726:726)) - (PORT datad (561:561:561) (560:560:560)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (632:632:632)) - (PORT datab (638:638:638) (654:654:654)) - (PORT datac (180:180:180) (212:212:212)) - (PORT datad (176:176:176) (197:197:197)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) - (DELAY - (ABSOLUTE - (PORT dataa (1927:1927:1927) (1952:1952:1952)) - (PORT datab (337:337:337) (347:347:347)) - (PORT datac (1377:1377:1377) (1419:1419:1419)) - (PORT datad (601:601:601) (621:621:621)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT dataa (1097:1097:1097) (1113:1113:1113)) + (PORT datab (1059:1059:1059) (1091:1091:1091)) + (PORT datac (334:334:334) (354:354:354)) + (PORT datad (1059:1059:1059) (1083:1083:1083)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) (DELAY (ABSOLUTE - (PORT dataa (1542:1542:1542) (1560:1560:1560)) - (PORT datab (1091:1091:1091) (1138:1138:1138)) - (PORT datac (773:773:773) (765:765:765)) - (PORT datad (1100:1100:1100) (1144:1144:1144)) + (PORT dataa (1029:1029:1029) (1030:1030:1030)) + (PORT datab (1064:1064:1064) (1084:1084:1084)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (905:905:905)) + (PORT datab (843:843:843) (841:841:841)) + (PORT datac (591:591:591) (607:607:607)) + (PORT datad (1424:1424:1424) (1478:1478:1478)) (IOPATH dataa combout (307:307:307) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -17002,672 +14830,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) (DELAY (ABSOLUTE - (PORT dataa (612:612:612) (602:602:602)) - (PORT datab (1182:1182:1182) (1211:1211:1211)) - (PORT datac (1635:1635:1635) (1623:1623:1623)) - (PORT datad (1001:1001:1001) (1011:1011:1011)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1668:1668:1668) (1654:1654:1654)) - (PORT datab (1340:1340:1340) (1403:1403:1403)) - (PORT datac (1243:1243:1243) (1247:1247:1247)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1046:1046:1046) (1052:1052:1052)) - (PORT datab (1182:1182:1182) (1209:1209:1209)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1180:1180:1180) (1168:1168:1168)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (574:574:574)) - (PORT datab (876:876:876) (894:894:894)) - (PORT datac (483:483:483) (488:488:488)) - (PORT datad (1486:1486:1486) (1469:1469:1469)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (562:562:562) (574:574:574)) - (PORT datab (1090:1090:1090) (1099:1099:1099)) - (PORT datac (1169:1169:1169) (1162:1162:1162)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (577:577:577)) - (PORT datab (987:987:987) (981:981:981)) - (PORT datac (535:535:535) (544:544:544)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1541:1541:1541) (1562:1562:1562)) - (PORT datab (194:194:194) (233:233:233)) - (PORT datac (472:472:472) (457:457:457)) - (PORT datad (1078:1078:1078) (1093:1093:1093)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (974:974:974)) - (PORT datab (1014:1014:1014) (974:974:974)) - (PORT datac (773:773:773) (762:762:762)) - (PORT datad (813:813:813) (833:833:833)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (350:350:350)) - (PORT datab (195:195:195) (234:234:234)) - (PORT datac (166:166:166) (206:206:206)) - (PORT datad (166:166:166) (191:191:191)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1028:1028:1028)) - (PORT datab (1140:1140:1140) (1163:1163:1163)) - (PORT datac (787:787:787) (768:768:768)) - (PORT datad (983:983:983) (941:941:941)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datac (917:917:917) (891:891:891)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT datab (195:195:195) (235:235:235)) - (PORT datac (181:181:181) (216:216:216)) - (PORT datad (170:170:170) (201:201:201)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (871:871:871)) - (PORT datab (186:186:186) (220:220:220)) - (PORT datac (1047:1047:1047) (1045:1045:1045)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (819:819:819)) - (PORT datab (763:763:763) (744:744:744)) - (PORT datac (760:760:760) (763:763:763)) - (PORT datad (161:161:161) (187:187:187)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (834:834:834)) - (PORT datab (568:568:568) (586:586:586)) - (PORT datac (567:567:567) (558:558:558)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (1205:1205:1205) (1277:1277:1277)) - (PORT datab (852:852:852) (863:863:863)) - (PORT datac (1005:1005:1005) (1007:1007:1007)) - (PORT datad (1280:1280:1280) (1290:1290:1290)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (826:826:826)) - (PORT datab (823:823:823) (838:838:838)) - (PORT datac (1165:1165:1165) (1142:1142:1142)) - (PORT datad (1008:1008:1008) (1005:1005:1005)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1002:1002:1002)) - (PORT datab (187:187:187) (224:224:224)) - (PORT datac (798:798:798) (799:799:799)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (789:789:789) (806:806:806)) - (PORT datab (791:791:791) (787:787:787)) - (PORT datac (1007:1007:1007) (966:966:966)) - (PORT datad (303:303:303) (306:306:306)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (232:232:232)) - (PORT datab (632:632:632) (645:645:645)) - (PORT datac (746:746:746) (741:741:741)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (612:612:612)) - (PORT datab (244:244:244) (317:317:317)) - (PORT datac (223:223:223) (298:298:298)) - (PORT datad (221:221:221) (283:283:283)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (833:833:833) (865:865:865)) - (PORT datab (1123:1123:1123) (1151:1151:1151)) - (PORT datac (968:968:968) (945:945:945)) - (PORT datad (920:920:920) (887:887:887)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (1065:1065:1065) (1081:1081:1081)) - (PORT datac (971:971:971) (944:944:944)) - (PORT datad (164:164:164) (187:187:187)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (512:512:512)) - (PORT datab (602:602:602) (594:594:594)) - (PORT datac (844:844:844) (849:849:849)) - (PORT datad (717:717:717) (699:699:699)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (755:755:755)) - (PORT datab (779:779:779) (755:755:755)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1047:1047:1047) (1053:1053:1053)) - (PORT datab (1732:1732:1732) (1728:1728:1728)) - (PORT datac (1148:1148:1148) (1117:1117:1117)) - (PORT datad (1526:1526:1526) (1498:1498:1498)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (242:242:242)) - (PORT datab (1429:1429:1429) (1392:1392:1392)) - (PORT datac (526:526:526) (516:516:516)) - (PORT datad (1208:1208:1208) (1172:1172:1172)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (800:800:800)) - (PORT datab (563:563:563) (550:550:550)) - (PORT datac (520:520:520) (512:512:512)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (922:922:922) (895:895:895)) - (PORT datad (799:799:799) (797:797:797)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (668:668:668)) - (PORT datab (1008:1008:1008) (984:984:984)) - (PORT datac (1051:1051:1051) (1066:1066:1066)) - (PORT datad (778:778:778) (774:774:774)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1379:1379:1379) (1385:1385:1385)) - (PORT datab (1569:1569:1569) (1566:1566:1566)) - (PORT datac (1051:1051:1051) (1066:1066:1066)) - (PORT datad (780:780:780) (793:793:793)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1382:1382:1382) (1391:1391:1391)) - (PORT datab (189:189:189) (225:225:225)) - (PORT datac (707:707:707) (682:682:682)) - (PORT datad (1543:1543:1543) (1532:1532:1532)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (870:870:870)) - (PORT datab (1339:1339:1339) (1402:1402:1402)) - (PORT datac (1628:1628:1628) (1679:1679:1679)) - (PORT datad (1032:1032:1032) (1056:1056:1056)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (239:239:239)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (173:173:173) (205:205:205)) - (PORT datad (296:296:296) (294:294:294)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (815:815:815)) - (PORT datab (1010:1010:1010) (1020:1020:1020)) - (PORT datac (1031:1031:1031) (1031:1031:1031)) - (PORT datad (1456:1456:1456) (1428:1428:1428)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (778:778:778) (776:776:776)) + (PORT dataa (418:418:418) (445:445:445)) (PORT datab (200:200:200) (234:234:234)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1192:1192:1192)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (1175:1175:1175) (1161:1161:1161)) - (PORT datad (779:779:779) (753:753:753)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (846:846:846)) - (PORT datab (666:666:666) (723:723:723)) - (PORT datac (610:610:610) (657:657:657)) - (PORT datad (986:986:986) (961:961:961)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT datab (1203:1203:1203) (1172:1172:1172)) - (PORT datac (593:593:593) (609:609:609)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (577:577:577)) - (PORT datab (1232:1232:1232) (1228:1228:1228)) - (PORT datac (957:957:957) (957:957:957)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT datac (753:753:753) (732:732:732)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1874:1874:1874) (1835:1835:1835)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~4) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (645:645:645) (683:683:683)) - (PORT datad (794:794:794) (800:800:800)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (631:631:631)) - (PORT datab (837:837:837) (845:845:845)) - (PORT datac (1012:1012:1012) (994:994:994)) - (PORT datad (829:829:829) (830:830:830)) - (IOPATH dataa combout (265:265:265) (269:269:269)) + (PORT dataa (1230:1230:1230) (1279:1279:1279)) + (PORT datab (1072:1072:1072) (1037:1037:1037)) + (PORT datac (1318:1318:1318) (1311:1311:1311)) + (PORT datad (785:785:785) (799:799:799)) + (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -17676,119 +14862,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~1) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) (DELAY (ABSOLUTE - (PORT dataa (787:787:787) (783:783:783)) - (PORT datab (1040:1040:1040) (1030:1030:1030)) - (PORT datac (532:532:532) (521:521:521)) - (PORT datad (831:831:831) (840:840:840)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (1054:1054:1054) (1060:1060:1060)) - (PORT datac (750:750:750) (746:746:746)) - (PORT datad (761:761:761) (742:742:742)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (750:750:750)) - (PORT datab (187:187:187) (225:225:225)) - (PORT datac (1260:1260:1260) (1237:1237:1237)) - (PORT datad (641:641:641) (691:691:691)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1540:1540:1540) (1561:1561:1561)) - (PORT datab (1075:1075:1075) (1094:1094:1094)) - (PORT datac (919:919:919) (884:884:884)) - (PORT datad (1100:1100:1100) (1144:1144:1144)) + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (775:775:775) (761:761:761)) + (PORT datac (295:295:295) (301:301:301)) + (PORT datad (157:157:157) (178:178:178)) (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) - (DELAY - (ABSOLUTE - (PORT datab (587:587:587) (594:594:594)) - (PORT datac (570:570:570) (587:587:587)) - (PORT datad (809:809:809) (807:807:807)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (1204:1204:1204) (1138:1138:1138)) - (PORT datac (572:572:572) (596:596:596)) - (PORT datad (791:791:791) (804:804:804)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT datac (303:303:303) (312:312:312)) - (PORT datad (534:534:534) (531:531:531)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -17796,71 +14878,62 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~25) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) (DELAY (ABSOLUTE - (PORT dataa (534:534:534) (540:540:540)) - (PORT datad (291:291:291) (303:303:303)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (836:836:836) (835:835:835)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (549:549:549) (539:539:539)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (814:814:814) (801:801:801)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~0) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) (DELAY (ABSOLUTE - (PORT dataa (240:240:240) (307:307:307)) - (PORT datab (592:592:592) (595:595:595)) - (PORT datad (810:810:810) (861:861:861)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (1064:1064:1064) (1070:1070:1070)) + (PORT datab (199:199:199) (231:231:231)) + (PORT datac (517:517:517) (505:505:505)) + (PORT datad (522:522:522) (514:514:514)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (903:903:903) (898:898:898)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (PORT dataa (1017:1017:1017) (1017:1017:1017)) + (PORT datab (191:191:191) (231:231:231)) + (PORT datac (989:989:989) (981:981:981)) + (PORT datad (171:171:171) (202:202:202)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~1) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) (DELAY (ABSOLUTE - (PORT datab (351:351:351) (360:360:360)) - (PORT datac (195:195:195) (261:261:261)) - (PORT datad (383:383:383) (404:404:404)) + (PORT dataa (1491:1491:1491) (1562:1562:1562)) + (PORT datab (813:813:813) (800:800:800)) + (PORT datac (2318:2318:2318) (2351:2351:2351)) + (PORT datad (1368:1368:1368) (1417:1417:1417)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -17869,25 +14942,155 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) (DELAY (ABSOLUTE - (PORT datac (1379:1379:1379) (1408:1408:1408)) - (PORT datad (581:581:581) (589:589:589)) + (PORT dataa (557:557:557) (543:543:543)) + (PORT datab (546:546:546) (527:527:527)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1045:1045:1045) (1037:1037:1037)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~40) + (DELAY + (ABSOLUTE + (PORT datab (603:603:603) (606:606:606)) + (PORT datac (317:317:317) (331:331:331)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (251:251:251)) + (PORT datab (193:193:193) (234:234:234)) + (PORT datac (986:986:986) (981:981:981)) + (PORT datad (1053:1053:1053) (1063:1063:1063)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (1067:1067:1067) (1075:1075:1075)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (511:511:511) (508:508:508)) + (PORT datad (370:370:370) (382:382:382)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (153:153:153) (183:183:183)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1031:1031:1031)) + (PORT datab (1034:1034:1034) (999:999:999)) + (PORT datac (993:993:993) (991:991:991)) + (PORT datad (1086:1086:1086) (1100:1100:1100)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (646:646:646) (694:694:694)) + (PORT datad (338:338:338) (349:349:349)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (882:882:882) (898:898:898)) + (PORT datac (626:626:626) (663:663:663)) + (PORT datad (314:314:314) (326:326:326)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[0\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1365:1365:1365)) + (PORT datac (934:934:934) (903:903:903)) + (PORT datad (852:852:852) (845:845:845)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (164:164:164) (187:187:187)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1358:1358:1358)) - (PORT ena (2262:2262:2262) (2221:2221:2221)) + (PORT clrn (1400:1400:1400) (1370:1370:1370)) + (PORT ena (1924:1924:1924) (1928:1928:1928)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -17899,14 +15102,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) (DELAY (ABSOLUTE - (PORT dataa (595:595:595) (632:632:632)) - (PORT datab (607:607:607) (600:600:600)) - (PORT datac (1032:1032:1032) (1033:1033:1033)) - (PORT datad (170:170:170) (197:197:197)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (1071:1071:1071) (1059:1059:1059)) + (PORT datab (920:920:920) (926:926:926)) + (PORT datac (642:642:642) (688:688:688)) + (PORT datad (183:183:183) (207:207:207)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1175:1175:1175) (1170:1170:1170)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT asdata (899:899:899) (920:920:920)) + (PORT ena (1105:1105:1105) (1078:1078:1078)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (354:354:354)) + (PORT datab (642:642:642) (662:662:662)) + (PORT datad (1099:1099:1099) (1119:1119:1119)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (679:679:679) (706:706:706)) + (PORT datac (197:197:197) (264:264:264)) + (PORT datad (568:568:568) (585:585:585)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -17915,28 +15179,270 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~3) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) (DELAY (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (603:603:603) (606:606:606)) - (PORT datac (1526:1526:1526) (1603:1603:1603)) - (PORT datad (343:343:343) (355:355:355)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (783:783:783) (805:805:805)) + (PORT datab (376:376:376) (384:384:384)) + (PORT datac (175:175:175) (207:207:207)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (883:883:883) (896:896:896)) + (PORT datac (627:627:627) (664:664:664)) + (PORT datad (315:315:315) (324:324:324)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) (DELAY (ABSOLUTE - (PORT clk (1360:1360:1360) (1381:1381:1381)) - (PORT asdata (1162:1162:1162) (1181:1181:1181)) - (PORT ena (763:763:763) (771:771:771)) + (PORT datab (370:370:370) (379:379:379)) + (PORT datad (322:322:322) (329:329:329)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT asdata (485:485:485) (512:512:512)) + (PORT clrn (1409:1409:1409) (1380:1380:1380)) + (PORT ena (1969:1969:1969) (1997:1997:1997)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (948:948:948)) + (PORT datab (1064:1064:1064) (1061:1061:1061)) + (PORT datac (753:753:753) (774:774:774)) + (PORT datad (331:331:331) (342:342:342)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (392:392:392)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (214:214:214) (279:279:279)) + (PORT datad (307:307:307) (308:308:308)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (692:692:692)) + (PORT datab (885:885:885) (898:898:898)) + (PORT datac (579:579:579) (599:599:599)) + (PORT datad (491:491:491) (483:483:483)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (518:518:518)) + (PORT datad (192:192:192) (224:224:224)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (178:178:178) (199:199:199)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1409:1409:1409) (1380:1380:1380)) + (PORT ena (1976:1976:1976) (1995:1995:1995)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (379:379:379)) + (PORT datab (1064:1064:1064) (1065:1065:1065)) + (PORT datac (891:891:891) (917:917:917)) + (PORT datad (368:368:368) (400:400:400)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (236:236:236)) + (PORT datab (186:186:186) (223:223:223)) + (PORT datac (160:160:160) (192:192:192)) + (PORT datad (164:164:164) (187:187:187)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (389:389:389)) + (PORT datab (1032:1032:1032) (997:997:997)) + (PORT datac (998:998:998) (976:976:976)) + (PORT datad (1091:1091:1091) (1105:1105:1105)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1068:1068:1068) (1057:1057:1057)) + (PORT datab (915:915:915) (924:924:924)) + (PORT datac (886:886:886) (910:910:910)) + (PORT datad (1039:1039:1039) (1026:1026:1026)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (807:807:807)) + (PORT datab (1284:1284:1284) (1227:1227:1227)) + (PORT datac (641:641:641) (688:688:688)) + (PORT datad (342:342:342) (353:353:353)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT datab (186:186:186) (223:223:223)) + (PORT datac (307:307:307) (317:317:317)) + (PORT datad (222:222:222) (282:282:282)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT asdata (1283:1283:1283) (1264:1264:1264)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT asdata (1285:1285:1285) (1265:1265:1265)) + (PORT ena (1154:1154:1154) (1142:1142:1142)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -17947,27 +15453,53 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~12) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) (DELAY (ABSOLUTE - (PORT dataa (1117:1117:1117) (1141:1141:1141)) - (PORT datab (1267:1267:1267) (1279:1279:1279)) - (PORT datad (1738:1738:1738) (1706:1706:1706)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (389:389:389) (434:434:434)) + (PORT datab (546:546:546) (555:555:555)) + (PORT datad (200:200:200) (257:257:257)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1160:1160:1160) (1163:1163:1163)) - (PORT ena (860:860:860) (843:843:843)) + (PORT datad (755:755:755) (755:755:755)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1295:1295:1295) (1246:1246:1246)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1067:1067:1067) (1060:1060:1060)) + (PORT ena (1155:1155:1155) (1140:1140:1140)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -17977,12 +15509,27 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1161:1161:1161) (1165:1165:1165)) + (PORT dataa (578:578:578) (596:596:596)) + (PORT datab (774:774:774) (774:774:774)) + (PORT datad (589:589:589) (599:599:599)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1104:1104:1104) (1099:1099:1099)) (PORT ena (744:744:744) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -17993,136 +15540,54 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT datab (1635:1635:1635) (1690:1690:1690)) - (PORT datac (972:972:972) (948:948:948)) - (PORT datad (1497:1497:1497) (1480:1480:1480)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1103:1103:1103) (1102:1102:1102)) + (PORT ena (1123:1123:1123) (1106:1106:1106)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~9) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) (DELAY (ABSOLUTE - (PORT dataa (392:392:392) (433:433:433)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (365:365:365) (386:386:386)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (603:603:603) (646:646:646)) + (PORT datab (223:223:223) (293:293:293)) + (PORT datad (347:347:347) (360:360:360)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1208:1208:1208) (1219:1219:1219)) - (PORT ena (882:882:882) (874:874:874)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1207:1207:1207) (1219:1219:1219)) - (PORT ena (897:897:897) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~10) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (394:394:394) (437:437:437)) - (PORT datab (384:384:384) (413:413:413)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT datad (753:753:753) (752:752:752)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1391:1391:1391) (1382:1382:1382)) - (PORT ena (1108:1108:1108) (1069:1069:1069)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1394:1394:1394) (1386:1386:1386)) - (PORT ena (1138:1138:1138) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (410:410:410)) - (PORT datab (604:604:604) (609:609:609)) - (PORT datad (582:582:582) (577:577:577)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT clk (1342:1342:1342) (1359:1359:1359)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1311:1311:1311) (1323:1323:1323)) + (PORT ena (1381:1381:1381) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -18133,12 +15598,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (1104:1104:1104) (1103:1103:1103)) - (PORT ena (1327:1327:1327) (1302:1302:1302)) + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1070:1070:1070) (1064:1064:1064)) + (PORT ena (1109:1109:1109) (1074:1074:1074)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -18149,60 +15614,94 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~13) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) (DELAY (ABSOLUTE - (PORT dataa (423:423:423) (460:460:460)) - (PORT datab (221:221:221) (289:289:289)) - (PORT datad (611:611:611) (619:619:619)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (924:924:924) (938:938:938)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1218:1218:1218) (1181:1181:1181)) - (PORT datab (1263:1263:1263) (1251:1251:1251)) - (PORT datad (363:363:363) (364:364:364)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (869:869:869) (865:865:865)) + (PORT datab (565:565:565) (561:561:561)) + (PORT datac (513:513:513) (507:507:507)) + (PORT datad (1405:1405:1405) (1456:1456:1456)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~14) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (309:309:309) (327:327:327)) - (PORT datac (589:589:589) (587:587:587)) - (PORT datad (550:550:550) (547:547:547)) + (PORT dataa (889:889:889) (908:908:908)) + (PORT datab (536:536:536) (546:546:546)) + (PORT datac (918:918:918) (935:935:935)) + (PORT datad (794:794:794) (808:808:808)) (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (238:238:238)) + (PORT datab (619:619:619) (648:648:648)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (156:156:156) (177:177:177)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (496:496:496)) + (PORT datab (572:572:572) (561:561:561)) + (PORT datac (790:790:790) (807:807:807)) + (PORT datad (567:567:567) (574:574:574)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (606:606:606)) + (PORT datab (600:600:600) (612:612:612)) + (PORT datac (1070:1070:1070) (1099:1099:1099)) + (PORT datad (550:550:550) (550:550:550)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (181:181:181) (215:215:215)) + (PORT datac (566:566:566) (567:567:567)) + (PORT datad (167:167:167) (190:190:190)) + (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -18211,38 +15710,54 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) (DELAY (ABSOLUTE - (PORT datad (1095:1095:1095) (1092:1092:1092)) + (PORT datab (1320:1320:1320) (1344:1344:1344)) + (PORT datac (1116:1116:1116) (1136:1136:1136)) + (PORT datad (788:788:788) (810:810:810)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT datab (1320:1320:1320) (1346:1346:1346)) + (PORT datac (1120:1120:1120) (1139:1139:1139)) + (PORT datad (785:785:785) (795:795:795)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT datab (1321:1321:1321) (1338:1338:1338)) + (PORT datac (1109:1109:1109) (1129:1129:1129)) + (PORT datad (785:785:785) (793:793:793)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1381:1381:1381)) - (PORT asdata (1163:1163:1163) (1179:1179:1179)) - (PORT ena (739:739:739) (742:742:742)) + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (933:933:933) (955:955:955)) + (PORT ena (906:906:906) (905:905:905)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -18253,12 +15768,422 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~8) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) (DELAY (ABSOLUTE - (PORT dataa (392:392:392) (431:431:431)) - (PORT datab (378:378:378) (391:391:391)) - (PORT datad (606:606:606) (638:638:638)) + (PORT datab (1321:1321:1321) (1339:1339:1339)) + (PORT datac (1111:1111:1111) (1130:1130:1130)) + (PORT datad (790:790:790) (811:811:811)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (936:936:936) (957:957:957)) + (PORT ena (893:893:893) (877:877:877)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (472:472:472)) + (PORT datab (450:450:450) (480:480:480)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT datab (1320:1320:1320) (1340:1340:1340)) + (PORT datac (1115:1115:1115) (1134:1134:1134)) + (PORT datad (999:999:999) (984:984:984)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT datab (1320:1320:1320) (1346:1346:1346)) + (PORT datac (1120:1120:1120) (1139:1139:1139)) + (PORT datad (916:916:916) (925:925:925)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1093:1093:1093) (1077:1077:1077)) + (PORT ena (1281:1281:1281) (1292:1292:1292)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) + (DELAY + (ABSOLUTE + (PORT datab (1321:1321:1321) (1342:1342:1342)) + (PORT datac (1119:1119:1119) (1139:1139:1139)) + (PORT datad (1001:1001:1001) (985:985:985)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1095:1095:1095) (1080:1080:1080)) + (PORT ena (1271:1271:1271) (1296:1296:1296)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT datab (1323:1323:1323) (1343:1343:1343)) + (PORT datac (1122:1122:1122) (1141:1141:1141)) + (PORT datad (914:914:914) (922:922:922)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (892:892:892)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datad (799:799:799) (856:856:856)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT datab (1114:1114:1114) (1152:1152:1152)) + (PORT datac (829:829:829) (849:849:849)) + (PORT datad (833:833:833) (842:842:842)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1119:1119:1119) (1113:1113:1113)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (898:898:898)) + (PORT datab (1114:1114:1114) (1148:1148:1148)) + (PORT datad (821:821:821) (832:832:832)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1080:1080:1080) (1087:1087:1087)) + (PORT datab (186:186:186) (222:222:222)) + (PORT datac (1680:1680:1680) (1729:1729:1729)) + (PORT datad (181:181:181) (218:218:218)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (809:809:809)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datac (561:561:561) (588:588:588)) + (PORT datad (806:806:806) (810:810:810)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1373:1373:1373)) + (PORT datac (773:773:773) (748:748:748)) + (PORT datad (1042:1042:1042) (1034:1034:1034)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (906:906:906) (925:925:925)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT dataa (1361:1361:1361) (1373:1373:1373)) + (PORT datac (774:774:774) (748:748:748)) + (PORT datad (1045:1045:1045) (1035:1035:1035)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1007:1007:1007) (991:991:991)) + (PORT datab (1073:1073:1073) (1081:1081:1081)) + (PORT datad (219:219:219) (252:252:252)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (614:614:614) (637:637:637)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (DELAY + (ABSOLUTE + (PORT datab (1043:1043:1043) (1038:1038:1038)) + (PORT datac (1294:1294:1294) (1292:1292:1292)) + (PORT datad (762:762:762) (769:769:769)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (888:888:888)) + (PORT datab (1113:1113:1113) (1147:1147:1147)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (406:406:406)) + (PORT datab (876:876:876) (897:897:897)) + (PORT datac (1060:1060:1060) (1056:1056:1056)) + (PORT datad (615:615:615) (618:618:618)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) + (DELAY + (ABSOLUTE + (PORT datac (1323:1323:1323) (1335:1335:1335)) + (PORT datad (1042:1042:1042) (1031:1031:1031)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1108:1108:1108)) + (PORT datab (755:755:755) (739:739:739)) + (PORT datac (1047:1047:1047) (1044:1044:1044)) + (PORT datad (615:615:615) (635:635:635)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1390:1390:1390) (1376:1376:1376)) + (PORT ena (1039:1039:1039) (993:993:993)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (DELAY + (ABSOLUTE + (PORT datab (1043:1043:1043) (1039:1039:1039)) + (PORT datac (1294:1294:1294) (1292:1292:1292)) + (PORT datad (762:762:762) (766:766:766)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (405:405:405)) + (PORT datab (813:813:813) (838:838:838)) + (PORT datad (339:339:339) (352:352:352)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -18268,13 +16193,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~15) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (605:605:605) (619:619:619)) - (PORT datac (538:538:538) (542:542:542)) - (PORT datad (161:161:161) (183:183:183)) + (PORT dataa (381:381:381) (416:416:416)) + (PORT datab (1312:1312:1312) (1291:1291:1291)) + (PORT datac (1056:1056:1056) (1048:1048:1048)) + (PORT datad (612:612:612) (615:615:615)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -18284,15 +16209,111 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~21) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) (DELAY (ABSOLUTE - (PORT dataa (555:555:555) (552:552:552)) - (PORT datab (1827:1827:1827) (1904:1904:1904)) - (PORT datac (566:566:566) (579:579:579)) - (PORT datad (533:533:533) (522:522:522)) + (PORT dataa (1067:1067:1067) (1076:1076:1076)) + (PORT datab (757:757:757) (741:741:741)) + (PORT datac (1055:1055:1055) (1050:1050:1050)) + (PORT datad (622:622:622) (644:644:644)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1347:1347:1347) (1329:1329:1329)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1646:1646:1646) (1716:1716:1716)) + (PORT datab (893:893:893) (908:908:908)) + (PORT datac (1355:1355:1355) (1341:1341:1341)) + (PORT datad (1815:1815:1815) (1812:1812:1812)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (588:588:588)) + (PORT datab (1157:1157:1157) (1140:1140:1140)) + (PORT datac (1681:1681:1681) (1734:1734:1734)) + (PORT datad (1026:1026:1026) (1018:1018:1018)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (625:625:625)) + (PORT datab (846:846:846) (872:872:872)) + (PORT datac (804:804:804) (801:801:801)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (232:232:232)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1071:1071:1071) (1070:1070:1070)) + (PORT datad (183:183:183) (218:218:218)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (686:686:686)) + (PORT datab (188:188:188) (221:221:221)) + (PORT datac (322:322:322) (336:336:336)) + (PORT datad (1066:1066:1066) (1059:1059:1059)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18300,23 +16321,1271 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|im2\~feeder) + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) (DELAY (ABSOLUTE - (PORT datad (165:165:165) (188:188:188)) + (PORT datab (856:856:856) (854:854:854)) + (PORT datac (552:552:552) (546:546:546)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (813:813:813)) + (PORT datac (1053:1053:1053) (1034:1034:1034)) + (PORT datad (775:775:775) (763:763:763)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1367:1367:1367)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1392:1392:1392) (1376:1376:1376)) + (PORT ena (1164:1164:1164) (1167:1167:1167)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (811:811:811)) + (PORT datac (1047:1047:1047) (1033:1033:1033)) + (PORT datad (777:777:777) (763:763:763)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1011:1011:1011)) + (PORT datab (1187:1187:1187) (1245:1245:1245)) + (PORT datad (776:776:776) (789:789:789)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (614:614:614)) + (PORT datab (1170:1170:1170) (1220:1220:1220)) + (PORT datac (1060:1060:1060) (1052:1052:1052)) + (PORT datad (350:350:350) (371:371:371)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (912:912:912) (931:931:931)) + (PORT ena (1093:1093:1093) (1070:1070:1070)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (411:411:411)) + (PORT datab (1170:1170:1170) (1212:1212:1212)) + (PORT datac (1055:1055:1055) (1054:1054:1054)) + (PORT datad (612:612:612) (618:618:618)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (616:616:616)) + (PORT datab (1166:1166:1166) (1211:1211:1211)) + (PORT datac (1057:1057:1057) (1053:1053:1053)) + (PORT datad (356:356:356) (372:372:372)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (912:912:912) (931:931:931)) + (PORT ena (1173:1173:1173) (1169:1169:1169)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (409:409:409)) + (PORT datab (1169:1169:1169) (1219:1219:1219)) + (PORT datac (1060:1060:1060) (1052:1052:1052)) + (PORT datad (615:615:615) (614:614:614)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (429:429:429)) + (PORT datab (1479:1479:1479) (1478:1478:1478)) + (PORT datad (1098:1098:1098) (1089:1089:1089)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (566:566:566)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (730:730:730) (696:696:696)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (583:583:583)) + (PORT datab (312:312:312) (332:332:332)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (578:578:578) (588:588:588)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (882:882:882)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (572:572:572) (586:586:586)) + (PORT datad (728:728:728) (697:697:697)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (987:987:987) (1001:1001:1001)) + (PORT datab (778:778:778) (771:771:771)) + (PORT datac (192:192:192) (237:237:237)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (606:606:606)) + (PORT datab (777:777:777) (776:776:776)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (811:811:811) (817:817:817)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (239:239:239)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (176:176:176) (208:208:208)) + (PORT datad (178:178:178) (201:201:201)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1448:1448:1448) (1385:1385:1385)) + (PORT datab (782:782:782) (820:820:820)) + (PORT datac (1049:1049:1049) (1030:1030:1030)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT dataa (1211:1211:1211) (1259:1259:1259)) + (PORT datac (1051:1051:1051) (1039:1039:1039)) + (PORT datad (774:774:774) (762:762:762)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1360:1360:1360)) - (PORT ena (1792:1792:1792) (1756:1756:1756)) + (PORT ena (1196:1196:1196) (1178:1178:1178)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1080:1080:1080) (1105:1105:1105)) + (PORT ena (906:906:906) (905:905:905)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1079:1079:1079) (1103:1103:1103)) + (PORT ena (893:893:893) (877:877:877)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (478:478:478)) + (PORT datab (451:451:451) (487:487:487)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1792:1792:1792) (1799:1799:1799)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (892:892:892)) + (PORT datab (1114:1114:1114) (1155:1155:1155)) + (PORT datad (821:821:821) (832:832:832)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT asdata (493:493:493) (524:524:524)) + (PORT ena (1347:1347:1347) (1329:1329:1329)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1574:1574:1574) (1581:1581:1581)) + (PORT ena (1164:1164:1164) (1167:1167:1167)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1013:1013:1013)) + (PORT datab (603:603:603) (645:645:645)) + (PORT datad (779:779:779) (797:797:797)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (2031:2031:2031) (2021:2021:2021)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (787:787:787) (778:778:778)) + (PORT datab (1073:1073:1073) (1082:1082:1082)) + (PORT datad (219:219:219) (253:253:253)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1819:1819:1819) (1793:1793:1793)) + (PORT ena (1093:1093:1093) (1070:1070:1070)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1820:1820:1820) (1797:1797:1797)) + (PORT ena (1173:1173:1173) (1169:1169:1169)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (414:414:414)) + (PORT datab (1473:1473:1473) (1469:1469:1469)) + (PORT datad (1097:1097:1097) (1083:1083:1083)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1573:1573:1573) (1580:1580:1580)) + (PORT ena (1039:1039:1039) (993:993:993)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1482:1482:1482) (1473:1473:1473)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (391:391:391)) + (PORT datab (812:812:812) (837:837:837)) + (PORT datad (800:800:800) (823:823:823)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (591:591:591) (579:579:579)) + (PORT datac (311:311:311) (318:318:318)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (2181:2181:2181) (2175:2175:2175)) + (PORT ena (1271:1271:1271) (1296:1296:1296)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (2180:2180:2180) (2174:2174:2174)) + (PORT ena (1281:1281:1281) (1292:1292:1292)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (889:889:889)) + (PORT datab (826:826:826) (890:890:890)) + (PORT datad (198:198:198) (254:254:254)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (602:602:602)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (559:559:559) (557:557:557)) + (PORT datad (296:296:296) (289:289:289)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (814:814:814) (859:859:859)) + (PORT datab (507:507:507) (508:508:508)) + (PORT datac (969:969:969) (991:991:991)) + (PORT datad (1211:1211:1211) (1199:1199:1199)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (807:807:807)) + (PORT datac (1048:1048:1048) (1033:1033:1033)) + (PORT datad (786:786:786) (789:789:789)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (805:805:805)) + (PORT datac (1051:1051:1051) (1036:1036:1036)) + (PORT datad (787:787:787) (792:792:792)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT asdata (1278:1278:1278) (1296:1296:1296)) + (PORT ena (857:857:857) (835:835:835)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1093:1093:1093) (1067:1067:1067)) + (PORT datab (777:777:777) (766:766:766)) + (PORT datac (1052:1052:1052) (1034:1034:1034)) + (PORT datad (787:787:787) (789:789:789)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (248:248:248)) + (PORT datab (376:376:376) (397:397:397)) + (PORT datad (358:358:358) (374:374:374)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT dataa (1211:1211:1211) (1258:1258:1258)) + (PORT datac (1051:1051:1051) (1036:1036:1036)) + (PORT datad (774:774:774) (762:762:762)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datac (702:702:702) (733:733:733)) + (PORT datad (596:596:596) (596:596:596)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (265:265:265)) + (PORT datab (212:212:212) (250:250:250)) + (PORT datac (1025:1025:1025) (991:991:991)) + (PORT datad (194:194:194) (224:224:224)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (452:452:452)) + (PORT datab (251:251:251) (325:325:325)) + (PORT datac (1235:1235:1235) (1184:1184:1184)) + (PORT datad (169:169:169) (195:195:195)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (765:765:765) (779:779:779)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (877:877:877) (870:870:870)) + (PORT ena (1271:1271:1271) (1296:1296:1296)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (876:876:876) (869:869:869)) + (PORT ena (1281:1281:1281) (1292:1292:1292)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (882:882:882)) + (PORT datab (829:829:829) (893:893:893)) + (PORT datad (195:195:195) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1273:1273:1273) (1283:1283:1283)) + (PORT ena (906:906:906) (905:905:905)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1270:1270:1270) (1280:1280:1280)) + (PORT ena (893:893:893) (877:877:877)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (471:471:471)) + (PORT datab (454:454:454) (482:482:482)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1169:1169:1169) (1176:1176:1176)) + (PORT ena (1173:1173:1173) (1169:1169:1169)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1169:1169:1169) (1174:1174:1174)) + (PORT ena (1093:1093:1093) (1070:1070:1070)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (403:403:403)) + (PORT datab (1479:1479:1479) (1472:1472:1472)) + (PORT datad (1098:1098:1098) (1082:1082:1082)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1130:1130:1130) (1150:1150:1150)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (950:950:950)) + (PORT datab (1074:1074:1074) (1080:1080:1080)) + (PORT datad (217:217:217) (250:250:250)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (747:747:747) (778:778:778)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1118:1118:1118) (1094:1094:1094)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1154:1154:1154) (1178:1178:1178)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (217:217:217) (259:259:259)) + (PORT datad (812:812:812) (819:819:819)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (631:631:631) (635:635:635)) + (PORT ena (1298:1298:1298) (1265:1265:1265)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1357:1357:1357) (1333:1333:1333)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (954:954:954)) + (PORT datab (1176:1176:1176) (1200:1200:1200)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (766:766:766)) + (PORT datab (952:952:952) (970:970:970)) + (PORT datac (745:745:745) (771:771:771)) + (PORT datad (159:159:159) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (887:887:887) (875:875:875)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (887:887:887)) + (PORT datab (1114:1114:1114) (1151:1151:1151)) + (PORT datad (833:833:833) (842:842:842)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (381:381:381)) + (PORT datab (768:768:768) (789:789:789)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (522:522:522) (514:514:514)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (781:781:781) (779:779:779)) + (PORT datab (813:813:813) (808:808:808)) + (PORT datac (750:750:750) (780:780:780)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT asdata (815:815:815) (794:794:794)) + (PORT ena (862:862:862) (838:838:838)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (259:259:259)) + (PORT datab (839:839:839) (848:848:848)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (261:261:261)) + (PORT datac (194:194:194) (260:260:260)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1062:1062:1062) (1027:1027:1027)) + (PORT datab (767:767:767) (747:747:747)) + (PORT datac (179:179:179) (212:212:212)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (656:656:656)) + (PORT datac (742:742:742) (728:728:728)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1370:1370:1370)) + (PORT ena (1981:1981:1981) (2010:2010:2010)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -18328,27 +17597,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) (DELAY (ABSOLUTE - (PORT dataa (310:310:310) (417:417:417)) - (PORT datac (932:932:932) (911:911:911)) - (PORT datad (254:254:254) (330:330:330)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (308:308:308) (411:411:411)) - (PORT datab (325:325:325) (340:340:340)) - (PORT datac (971:971:971) (944:944:944)) - (PORT datad (1004:1004:1004) (993:993:993)) + (PORT dataa (396:396:396) (458:458:458)) + (PORT datab (252:252:252) (329:329:329)) + (PORT datac (1232:1232:1232) (1182:1182:1182)) + (PORT datad (173:173:173) (200:200:200)) (IOPATH dataa combout (267:267:267) (269:269:269)) (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -18358,29 +17613,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[6\]\~0) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) (DELAY (ABSOLUTE - (PORT datab (526:526:526) (522:522:522)) - (PORT datac (1177:1177:1177) (1142:1142:1142)) - (PORT datad (605:605:605) (617:617:617)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (645:645:645)) - (PORT datab (986:986:986) (984:984:984)) - (PORT datac (1179:1179:1179) (1141:1141:1141)) - (PORT datad (1200:1200:1200) (1198:1198:1198)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datac (220:220:220) (301:301:301)) + (PORT datad (302:302:302) (312:312:312)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18388,15 +17625,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) (DELAY (ABSOLUTE - (PORT dataa (1219:1219:1219) (1220:1220:1220)) - (PORT datab (1198:1198:1198) (1193:1193:1193)) - (PORT datac (3042:3042:3042) (2997:2997:2997)) - (PORT datad (635:635:635) (660:660:660)) + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (659:659:659) (668:668:668)) + (PORT datac (759:759:759) (753:753:753)) + (PORT datad (542:542:542) (535:535:535)) (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18404,11 +17641,404 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~4) + (INSTANCE z80_\|address_latch_\|abusz\[9\]) (DELAY (ABSOLUTE - (PORT datac (789:789:789) (787:787:787)) - (PORT datad (1027:1027:1027) (1025:1025:1025)) + (PORT datab (337:337:337) (345:345:345)) + (PORT datac (817:817:817) (816:816:816)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (512:512:512) (503:503:503)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1370:1370:1370)) + (PORT ena (1924:1924:1924) (1928:1928:1928)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (325:325:325)) + (PORT datab (250:250:250) (331:331:331)) + (PORT datac (1244:1244:1244) (1192:1192:1192)) + (PORT datad (303:303:303) (309:309:309)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1010:1010:1010) (1030:1030:1030)) + (PORT ena (1271:1271:1271) (1296:1296:1296)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1011:1011:1011) (1031:1031:1031)) + (PORT ena (1281:1281:1281) (1292:1292:1292)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (884:884:884)) + (PORT datab (828:828:828) (886:886:886)) + (PORT datad (197:197:197) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1776:1776:1776) (1820:1820:1820)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (757:757:757) (743:743:743)) + (PORT datab (1075:1075:1075) (1081:1081:1081)) + (PORT datad (220:220:220) (254:254:254)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1312:1312:1312) (1376:1376:1376)) + (PORT ena (1039:1039:1039) (993:993:993)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (714:714:714) (768:768:768)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (390:390:390)) + (PORT datab (812:812:812) (837:837:837)) + (PORT datad (325:325:325) (363:363:363)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (927:927:927) (951:951:951)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1093:1093:1093) (1070:1070:1070)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1824:1824:1824) (1865:1865:1865)) + (PORT ena (1173:1173:1173) (1169:1169:1169)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (565:565:565)) + (PORT datab (1478:1478:1478) (1476:1476:1476)) + (PORT datad (1096:1096:1096) (1087:1087:1087)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1347:1347:1347) (1329:1329:1329)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1312:1312:1312) (1374:1374:1374)) + (PORT ena (1164:1164:1164) (1167:1167:1167)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1020:1020:1020) (1009:1009:1009)) + (PORT datab (628:628:628) (666:666:666)) + (PORT datad (783:783:783) (799:799:799)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (582:582:582)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (552:552:552) (555:555:555)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1994:1994:1994) (2056:2056:2056)) + (PORT ena (893:893:893) (877:877:877)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1995:1995:1995) (2060:2060:2060)) + (PORT ena (906:906:906) (905:905:905)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (478:478:478)) + (PORT datab (222:222:222) (291:291:291)) + (PORT datad (413:413:413) (447:447:447)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (2016:2016:2016) (2070:2070:2070)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (891:891:891)) + (PORT datab (1113:1113:1113) (1148:1148:1148)) + (PORT datad (831:831:831) (837:837:837)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (753:753:753)) + (PORT datab (524:524:524) (527:527:527)) + (PORT datac (521:521:521) (502:502:502)) + (PORT datad (787:787:787) (800:800:800)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18416,93 +18046,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) (DELAY (ABSOLUTE - (PORT dataa (1282:1282:1282) (1311:1311:1311)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (578:578:578) (598:598:598)) - (PORT datad (1068:1068:1068) (1098:1098:1098)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (940:940:940)) - (PORT datab (623:623:623) (650:650:650)) - (PORT datac (811:811:811) (820:820:820)) - (PORT datad (978:978:978) (965:965:965)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (769:769:769) (825:825:825)) + (PORT datab (372:372:372) (373:373:373)) + (PORT datac (786:786:786) (830:830:830)) + (PORT datad (1209:1209:1209) (1198:1198:1198)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT dataa (862:862:862) (896:896:896)) - (PORT datab (1464:1464:1464) (1450:1450:1450)) - (PORT datac (1733:1733:1733) (1748:1748:1748)) - (PORT datad (1004:1004:1004) (966:966:966)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT asdata (492:492:492) (521:521:521)) + (PORT ena (862:862:862) (838:838:838)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) (DELAY (ABSOLUTE - (PORT dataa (526:526:526) (507:507:507)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (558:558:558) (556:556:556)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1047:1047:1047) (1067:1067:1067)) - (PORT datab (628:628:628) (641:641:641)) - (PORT datac (1022:1022:1022) (1016:1016:1016)) - (PORT datad (801:801:801) (804:804:804)) + (PORT dataa (1743:1743:1743) (1803:1803:1803)) + (PORT datab (213:213:213) (254:254:254)) + (PORT datad (193:193:193) (223:223:223)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (765:765:765) (779:779:779)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (260:260:260)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datad (334:334:334) (367:367:367)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) (DELAY (ABSOLUTE - (PORT dataa (1047:1047:1047) (1043:1043:1043)) - (PORT datab (201:201:201) (246:246:246)) - (PORT datac (182:182:182) (217:217:217)) - (PORT datad (789:789:789) (791:791:791)) + (PORT dataa (1066:1066:1066) (1029:1029:1029)) + (PORT datab (517:517:517) (500:500:500)) + (PORT datac (181:181:181) (216:216:216)) + (PORT datad (158:158:158) (178:178:178)) (IOPATH dataa combout (267:267:267) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -18512,24 +18139,419 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~1) + (INSTANCE z80_\|address_latch_\|abusz\[10\]) (DELAY (ABSOLUTE - (PORT datab (181:181:181) (213:213:213)) - (PORT datad (1064:1064:1064) (1068:1068:1068)) + (PORT datac (180:180:180) (213:213:213)) + (PORT datad (805:805:805) (809:809:809)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (495:495:495) (485:485:485)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1370:1370:1370)) + (PORT ena (1924:1924:1924) (1928:1928:1928)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (330:330:330)) + (PORT datab (246:246:246) (327:327:327)) + (PORT datac (1247:1247:1247) (1195:1195:1195)) + (PORT datad (302:302:302) (311:311:311)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[11\]) + (DELAY + (ABSOLUTE + (PORT datab (554:554:554) (576:576:576)) + (PORT datad (852:852:852) (845:845:845)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1370:1370:1370)) + (PORT ena (1924:1924:1924) (1928:1928:1928)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (239:239:239)) + (PORT datac (530:530:530) (559:559:559)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1196:1196:1196) (1178:1178:1178)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT asdata (671:671:671) (690:690:690)) + (PORT ena (857:857:857) (835:835:835)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (237:237:237)) + (PORT datab (373:373:373) (393:393:393)) + (PORT datad (364:364:364) (377:377:377)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (299:299:299)) + (PORT datac (750:750:750) (785:785:785)) + (PORT datad (594:594:594) (591:591:591)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (520:520:520)) + (PORT datab (792:792:792) (788:788:788)) + (PORT datac (630:630:630) (643:643:643)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (572:572:572)) + (PORT datab (758:758:758) (804:804:804)) + (PORT datac (360:360:360) (384:384:384)) + (PORT datad (1211:1211:1211) (1194:1194:1194)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (834:834:834)) + (PORT datab (200:200:200) (244:244:244)) + (PORT datac (1069:1069:1069) (1087:1087:1087)) + (PORT datad (571:571:571) (569:569:569)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (963:963:963)) + (PORT datab (1937:1937:1937) (1953:1953:1953)) + (PORT datac (626:626:626) (660:660:660)) + (PORT datad (1598:1598:1598) (1668:1668:1668)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT datab (889:889:889) (910:910:910)) + (PORT datac (1062:1062:1062) (1036:1036:1036)) + (PORT datad (632:632:632) (648:648:648)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (601:601:601) (629:629:629)) + (PORT datac (593:593:593) (618:618:618)) + (PORT datad (590:590:590) (591:591:591)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (626:626:626)) + (PORT datab (598:598:598) (633:633:633)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (543:543:543) (529:529:529)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1051:1051:1051) (1043:1043:1043)) + (PORT datab (1175:1175:1175) (1231:1231:1231)) + (PORT datac (561:561:561) (568:568:568)) + (PORT datad (1041:1041:1041) (1014:1014:1014)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1856:1856:1856) (1979:1979:1979)) + (PORT datab (1176:1176:1176) (1205:1205:1205)) + (PORT datac (914:914:914) (922:922:922)) + (PORT datad (1343:1343:1343) (1387:1387:1387)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (951:951:951)) + (PORT datab (1484:1484:1484) (1550:1550:1550)) + (PORT datac (1048:1048:1048) (1029:1029:1029)) + (PORT datad (606:606:606) (624:624:624)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2373:2373:2373) (2398:2398:2398)) + (PORT datab (1443:1443:1443) (1492:1492:1492)) + (PORT datac (800:800:800) (809:809:809)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (364:364:364)) + (PORT datab (744:744:744) (771:771:771)) + (PORT datac (778:778:778) (763:763:763)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (594:594:594)) + (PORT datab (1079:1079:1079) (1111:1111:1111)) + (PORT datac (520:520:520) (505:505:505)) + (PORT datad (553:553:553) (546:546:546)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (548:548:548)) + (PORT datab (1031:1031:1031) (1053:1053:1053)) + (PORT datac (521:521:521) (520:520:520)) + (PORT datad (843:843:843) (869:869:869)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (306:306:306)) + (PORT datac (154:154:154) (184:184:184)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) (DELAY (ABSOLUTE - (PORT dataa (1045:1045:1045) (1063:1063:1063)) - (PORT datac (1027:1027:1027) (1024:1024:1024)) - (PORT datad (1068:1068:1068) (1070:1070:1070)) + (PORT dataa (241:241:241) (312:312:312)) + (PORT datac (1002:1002:1002) (1029:1029:1029)) + (PORT datad (840:840:840) (869:869:869)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -18541,9 +18563,9 @@ (INSTANCE z80_\|alu_\|op2_high\[1\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1370:1370:1370)) + (PORT clk (1350:1350:1350) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (765:765:765) (779:779:779)) + (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -18557,10 +18579,10 @@ (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) (DELAY (ABSOLUTE - (PORT dataa (1054:1054:1054) (1059:1059:1059)) - (PORT datac (585:585:585) (589:589:589)) - (PORT datad (823:823:823) (831:831:831)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT datab (893:893:893) (911:911:911)) + (PORT datac (339:339:339) (364:364:364)) + (PORT datad (624:624:624) (645:645:645)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18571,7 +18593,7 @@ (INSTANCE z80_\|alu_\|op1_high\[1\]) (DELAY (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT clk (1350:1350:1350) (1357:1357:1357)) (PORT d (67:67:67) (78:78:78)) (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) @@ -18584,105 +18606,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~3) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (820:820:820) (854:854:854)) - (PORT datab (951:951:951) (923:923:923)) - (PORT datac (839:839:839) (860:860:860)) - (PORT datad (800:800:800) (796:796:796)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (626:626:626) (654:654:654)) + (PORT datab (1034:1034:1034) (1063:1063:1063)) + (PORT datac (551:551:551) (544:544:544)) + (PORT datad (353:353:353) (393:393:393)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~2) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (629:629:629) (647:647:647)) - (PORT datab (987:987:987) (987:987:987)) - (PORT datac (1179:1179:1179) (1148:1148:1148)) - (PORT datad (1198:1198:1198) (1200:1200:1200)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1028:1028:1028)) - (PORT datab (815:815:815) (810:810:810)) - (PORT datad (1067:1067:1067) (1040:1040:1040)) - (IOPATH dataa combout (318:318:318) (307:307:307)) + (PORT dataa (241:241:241) (312:312:312)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (520:520:520) (517:517:517)) + (PORT datad (838:838:838) (866:866:866)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (INSTANCE z80_\|alu_\|op2_low\[1\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1648:1648:1648) (1640:1640:1640)) - (PORT ena (1108:1108:1108) (1069:1069:1069)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1649:1649:1649) (1642:1642:1642)) - (PORT ena (1138:1138:1138) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (618:618:618)) - (PORT datab (222:222:222) (292:292:292)) - (PORT datad (586:586:586) (579:579:579)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT clk (1350:1350:1350) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1311:1311:1311) (1323:1323:1323)) + (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -18691,265 +18652,157 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (1814:1814:1814) (1827:1827:1827)) - (PORT ena (1327:1327:1327) (1302:1302:1302)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~72) + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) (DELAY (ABSOLUTE - (PORT dataa (421:421:421) (458:458:458)) - (PORT datab (222:222:222) (291:291:291)) - (PORT datad (610:610:610) (621:621:621)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (649:649:649) (653:653:653)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (1220:1220:1220) (1191:1191:1191)) - (PORT datab (783:783:783) (776:776:776)) - (PORT datad (365:365:365) (367:367:367)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1640:1640:1640) (1616:1616:1616)) - (PORT ena (882:882:882) (874:874:874)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (1635:1635:1635) (1626:1626:1626)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (425:425:425)) - (PORT datab (387:387:387) (417:417:417)) - (PORT datad (339:339:339) (373:373:373)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (1348:1348:1348) (1339:1339:1339)) + (PORT datab (1386:1386:1386) (1404:1404:1404)) + (PORT datac (1701:1701:1701) (1703:1703:1703)) + (PORT datad (373:373:373) (394:394:394)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~73) + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~20) (DELAY (ABSOLUTE - (PORT dataa (560:560:560) (546:546:546)) - (PORT datab (602:602:602) (590:590:590)) - (PORT datac (555:555:555) (549:549:549)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT asdata (1475:1475:1475) (1497:1497:1497)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT asdata (1478:1478:1478) (1500:1500:1500)) - (PORT ena (930:930:930) (921:921:921)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (296:296:296)) - (PORT datab (640:640:640) (672:672:672)) - (PORT datad (209:209:209) (239:239:239)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1381:1381:1381)) - (PORT asdata (1316:1316:1316) (1321:1321:1321)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1135:1135:1135)) - (PORT datab (1270:1270:1270) (1284:1284:1284)) - (PORT datad (1734:1734:1734) (1699:1699:1699)) + (PORT dataa (1326:1326:1326) (1339:1339:1339)) + (PORT datab (1518:1518:1518) (1587:1587:1587)) + (PORT datac (986:986:986) (975:975:975)) + (PORT datad (1189:1189:1189) (1255:1255:1255)) (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1131:1131:1131) (1118:1118:1118)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1134:1134:1134) (1122:1122:1122)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (431:431:431)) - (PORT datab (402:402:402) (418:418:418)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~74) + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) (DELAY (ABSOLUTE - (PORT dataa (560:560:560) (576:576:576)) - (PORT datab (307:307:307) (325:325:325)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (544:544:544) (563:563:563)) + (PORT dataa (821:821:821) (807:807:807)) + (PORT datab (875:875:875) (878:878:878)) + (PORT datac (797:797:797) (781:781:781)) + (PORT datad (603:603:603) (611:611:611)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (443:443:443) (460:460:460)) + (PORT datab (1102:1102:1102) (1116:1116:1116)) + (PORT datac (843:843:843) (891:891:891)) + (PORT datad (1284:1284:1284) (1328:1328:1328)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1605:1605:1605) (1652:1652:1652)) + (PORT datab (1274:1274:1274) (1292:1292:1292)) + (PORT datac (1463:1463:1463) (1566:1566:1566)) + (PORT datad (1384:1384:1384) (1457:1457:1457)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT datab (1689:1689:1689) (1725:1725:1725)) + (PORT datac (1573:1573:1573) (1613:1613:1613)) + (PORT datad (847:847:847) (878:878:878)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1726:1726:1726) (1696:1696:1696)) + (PORT datab (181:181:181) (215:215:215)) + (PORT datac (809:809:809) (787:787:787)) + (PORT datad (750:750:750) (734:734:734)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1234:1234:1234) (1289:1289:1289)) + (PORT datab (1624:1624:1624) (1652:1652:1652)) + (PORT datac (1346:1346:1346) (1370:1370:1370)) + (PORT datad (177:177:177) (200:200:200)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1414:1414:1414) (1447:1447:1447)) + (PORT datab (843:843:843) (875:875:875)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (185:185:185) (209:209:209)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (236:236:236)) + (PORT datab (189:189:189) (224:224:224)) + (PORT datac (161:161:161) (195:195:195)) + (PORT datad (167:167:167) (192:192:192)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -18959,14 +18812,62 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~75) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~22) (DELAY (ABSOLUTE - (PORT dataa (589:589:589) (581:581:581)) - (PORT datab (1830:1830:1830) (1906:1906:1906)) - (PORT datac (545:545:545) (555:555:555)) - (PORT datad (532:532:532) (518:518:518)) - (IOPATH dataa combout (265:265:265) (269:269:269)) + (PORT dataa (1638:1638:1638) (1596:1596:1596)) + (PORT datab (779:779:779) (785:785:785)) + (PORT datac (1208:1208:1208) (1288:1288:1288)) + (PORT datad (2364:2364:2364) (2375:2375:2375)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (551:551:551)) + (PORT datab (225:225:225) (259:259:259)) + (PORT datac (199:199:199) (233:233:233)) + (PORT datad (831:831:831) (867:867:867)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (953:953:953)) + (PORT datab (1500:1500:1500) (1507:1507:1507)) + (PORT datac (1094:1094:1094) (1102:1102:1102)) + (PORT datad (1617:1617:1617) (1563:1563:1563)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (821:821:821)) + (PORT datab (866:866:866) (911:911:911)) + (PORT datac (197:197:197) (231:231:231)) + (PORT datad (830:830:830) (866:866:866)) + (IOPATH dataa combout (267:267:267) (269:269:269)) (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -18975,14 +18876,562 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~23) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) (DELAY (ABSOLUTE - (PORT dataa (1041:1041:1041) (1034:1034:1034)) - (PORT datab (1110:1110:1110) (1079:1079:1079)) - (PORT datac (883:883:883) (905:905:905)) - (PORT datad (1561:1561:1561) (1579:1579:1579)) - (IOPATH dataa combout (309:309:309) (326:326:326)) + (PORT dataa (192:192:192) (234:234:234)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (181:181:181) (216:216:216)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1123:1123:1123) (1133:1133:1133)) + (PORT datab (207:207:207) (242:242:242)) + (PORT datac (1906:1906:1906) (1932:1932:1932)) + (PORT datad (1305:1305:1305) (1352:1352:1352)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (640:640:640)) + (PORT datab (1366:1366:1366) (1379:1379:1379)) + (PORT datac (1366:1366:1366) (1362:1362:1362)) + (PORT datad (588:588:588) (584:584:584)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (779:779:779) (767:767:767)) + (PORT datab (1367:1367:1367) (1380:1380:1380)) + (PORT datac (1486:1486:1486) (1439:1439:1439)) + (PORT datad (1331:1331:1331) (1383:1383:1383)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (194:194:194) (232:232:232)) + (PORT datac (778:778:778) (779:779:779)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (984:984:984) (969:969:969)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal72\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1320:1320:1320)) + (PORT datab (2167:2167:2167) (2220:2220:2220)) + (PORT datac (1039:1039:1039) (1045:1045:1045)) + (PORT datad (787:787:787) (766:766:766)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1843:1843:1843) (1911:1911:1911)) + (PORT datab (1033:1033:1033) (1056:1056:1056)) + (PORT datac (1247:1247:1247) (1267:1267:1267)) + (PORT datad (795:795:795) (774:774:774)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (929:929:929)) + (PORT datab (886:886:886) (934:934:934)) + (PORT datac (1635:1635:1635) (1643:1643:1643)) + (PORT datad (1348:1348:1348) (1364:1364:1364)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (963:963:963)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (566:566:566) (569:569:569)) + (PORT datad (553:553:553) (547:547:547)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1393:1393:1393) (1432:1432:1432)) + (PORT datab (1814:1814:1814) (1843:1843:1843)) + (PORT datac (1150:1150:1150) (1194:1194:1194)) + (PORT datad (852:852:852) (886:886:886)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT datab (806:806:806) (799:799:799)) + (PORT datac (757:757:757) (768:768:768)) + (PORT datad (753:753:753) (745:745:745)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2375:2375:2375) (2401:2401:2401)) + (PORT datac (1415:1415:1415) (1465:1465:1465)) + (PORT datad (1429:1429:1429) (1504:1504:1504)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (276:276:276)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (1075:1075:1075) (1083:1083:1083)) + (PORT datad (175:175:175) (203:203:203)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (771:771:771)) + (PORT datab (570:570:570) (593:593:593)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (735:735:735) (796:796:796)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (856:856:856)) + (PORT datac (771:771:771) (772:772:772)) + (PORT datad (594:594:594) (607:607:607)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (863:863:863)) + (PORT datab (339:339:339) (350:350:350)) + (PORT datac (545:545:545) (554:554:554)) + (PORT datad (318:318:318) (317:317:317)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) + (DELAY + (ABSOLUTE + (PORT datac (819:819:819) (825:825:825)) + (PORT datad (768:768:768) (767:767:767)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (595:595:595)) + (PORT datab (1019:1019:1019) (1019:1019:1019)) + (PORT datac (712:712:712) (684:684:684)) + (PORT datad (566:566:566) (579:579:579)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (842:842:842) (826:826:826)) + (PORT datab (190:190:190) (225:225:225)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1849:1849:1849) (1839:1839:1839)) + (PORT datab (207:207:207) (243:243:243)) + (PORT datac (1567:1567:1567) (1621:1621:1621)) + (PORT datad (1378:1378:1378) (1406:1406:1406)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1063:1063:1063)) + (PORT datab (1465:1465:1465) (1537:1537:1537)) + (PORT datac (2344:2344:2344) (2367:2367:2367)) + (PORT datad (173:173:173) (200:200:200)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (957:957:957)) + (PORT datab (1202:1202:1202) (1227:1227:1227)) + (PORT datac (828:828:828) (821:821:821)) + (PORT datad (165:165:165) (190:190:190)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (596:596:596)) + (PORT datab (2125:2125:2125) (2116:2116:2116)) + (PORT datac (1899:1899:1899) (1945:1945:1945)) + (PORT datad (1071:1071:1071) (1063:1063:1063)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (567:567:567)) + (PORT datab (564:564:564) (566:566:566)) + (PORT datac (508:508:508) (506:506:506)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (953:953:953) (964:964:964)) + (PORT datab (1889:1889:1889) (1959:1959:1959)) + (PORT datac (761:761:761) (747:747:747)) + (PORT datad (2321:2321:2321) (2343:2343:2343)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1430:1430:1430) (1444:1444:1444)) + (PORT datab (865:865:865) (915:915:915)) + (PORT datac (559:559:559) (587:587:587)) + (PORT datad (534:534:534) (521:521:521)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (772:772:772) (828:828:828)) + (PORT datab (201:201:201) (233:233:233)) + (PORT datac (617:617:617) (630:630:630)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (610:610:610)) + (PORT datab (1080:1080:1080) (1089:1089:1089)) + (PORT datac (594:594:594) (617:617:617)) + (PORT datad (287:287:287) (294:294:294)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (608:608:608)) + (PORT datab (742:742:742) (790:790:790)) + (PORT datac (1019:1019:1019) (1018:1018:1018)) + (PORT datad (548:548:548) (553:553:553)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (600:600:600)) + (PORT datab (600:600:600) (610:610:610)) + (PORT datac (859:859:859) (925:925:925)) + (PORT datad (772:772:772) (765:765:765)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1393:1393:1393) (1433:1433:1433)) + (PORT datab (979:979:979) (967:967:967)) + (PORT datac (1150:1150:1150) (1195:1195:1195)) + (PORT datad (850:850:850) (884:884:884)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1339:1339:1339) (1319:1319:1319)) + (PORT datab (1049:1049:1049) (1071:1071:1071)) + (PORT datac (1100:1100:1100) (1162:1162:1162)) + (PORT datad (1057:1057:1057) (1051:1051:1051)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (591:591:591)) + (PORT datab (949:949:949) (972:972:972)) + (PORT datac (738:738:738) (720:720:720)) + (PORT datad (572:572:572) (566:566:566)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (249:249:249)) + (PORT datab (958:958:958) (972:972:972)) + (PORT datac (793:793:793) (769:769:769)) + (PORT datad (551:551:551) (557:557:557)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (556:556:556)) + (PORT datab (201:201:201) (245:245:245)) + (PORT datac (765:765:765) (777:777:777)) + (PORT datad (1268:1268:1268) (1337:1337:1337)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -18991,15 +19440,172 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) (DELAY (ABSOLUTE - (PORT dataa (629:629:629) (654:654:654)) - (PORT datab (222:222:222) (276:276:276)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (785:785:785) (770:770:770)) + (PORT dataa (718:718:718) (754:754:754)) + (PORT datab (780:780:780) (772:772:772)) + (PORT datac (697:697:697) (758:758:758)) + (PORT datad (703:703:703) (726:726:726)) (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1133:1133:1133)) + (PORT datab (640:640:640) (667:667:667)) + (PORT datac (841:841:841) (887:887:887)) + (PORT datad (988:988:988) (976:976:976)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (599:599:599)) + (PORT datab (601:601:601) (604:604:604)) + (PORT datac (858:858:858) (924:924:924)) + (PORT datad (362:362:362) (363:363:363)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (921:921:921)) + (PORT datab (1659:1659:1659) (1669:1669:1669)) + (PORT datac (1148:1148:1148) (1193:1193:1193)) + (PORT datad (984:984:984) (962:962:962)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1863:1863:1863) (1886:1886:1886)) + (PORT datab (2223:2223:2223) (2282:2282:2282)) + (PORT datac (1279:1279:1279) (1294:1294:1294)) + (PORT datad (1468:1468:1468) (1553:1553:1553)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1425:1425:1425)) + (PORT datab (359:359:359) (365:365:365)) + (PORT datac (1149:1149:1149) (1187:1187:1187)) + (PORT datad (807:807:807) (816:816:816)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1150:1150:1150)) + (PORT datab (318:318:318) (332:332:332)) + (PORT datac (988:988:988) (973:973:973)) + (PORT datad (314:314:314) (316:316:316)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (347:347:347)) + (PORT datab (596:596:596) (587:587:587)) + (PORT datac (153:153:153) (183:183:183)) + (PORT datad (566:566:566) (571:571:571)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (781:781:781)) + (PORT datab (1040:1040:1040) (1059:1059:1059)) + (PORT datac (784:784:784) (802:802:802)) + (PORT datad (334:334:334) (376:376:376)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19007,14 +19613,646 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) (DELAY (ABSOLUTE - (PORT dataa (792:792:792) (781:781:781)) - (PORT datab (1364:1364:1364) (1409:1409:1409)) - (PORT datac (1441:1441:1441) (1400:1400:1400)) - (PORT datad (1045:1045:1045) (1047:1047:1047)) + (PORT dataa (2372:2372:2372) (2401:2401:2401)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (1289:1289:1289) (1277:1277:1277)) + (PORT datad (1742:1742:1742) (1773:1773:1773)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (472:472:472)) + (PORT datab (418:418:418) (467:467:467)) + (PORT datac (802:802:802) (802:802:802)) + (PORT datad (611:611:611) (624:624:624)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (513:513:513)) + (PORT datab (582:582:582) (628:628:628)) + (PORT datac (577:577:577) (576:576:576)) + (PORT datad (583:583:583) (615:615:615)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (760:760:760) (755:755:755)) + (PORT datab (579:579:579) (568:568:568)) + (PORT datac (176:176:176) (207:207:207)) + (PORT datad (167:167:167) (192:192:192)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (758:758:758) (732:732:732)) + (PORT datab (573:573:573) (570:570:570)) + (PORT datac (1004:1004:1004) (1027:1027:1027)) + (PORT datad (831:831:831) (865:865:865)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (213:213:213) (265:265:265)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (468:468:468)) + (PORT datab (625:625:625) (653:653:653)) + (PORT datac (802:802:802) (803:803:803)) + (PORT datad (611:611:611) (629:629:629)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (822:822:822)) + (PORT datab (200:200:200) (241:241:241)) + (PORT datac (767:767:767) (779:779:779)) + (PORT datad (829:829:829) (876:876:876)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (754:754:754)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1684:1684:1684) (1638:1638:1638)) + (PORT datad (741:741:741) (728:728:728)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (624:624:624)) + (PORT datab (1646:1646:1646) (1589:1589:1589)) + (PORT datac (161:161:161) (194:194:194)) + (PORT datad (763:763:763) (749:749:749)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (DELAY + (ABSOLUTE + (PORT dataa (2200:2200:2200) (2255:2255:2255)) + (PORT datab (1385:1385:1385) (1430:1430:1430)) + (PORT datac (812:812:812) (800:800:800)) + (PORT datad (936:936:936) (996:996:996)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (525:525:525)) + (PORT datab (910:910:910) (930:930:930)) + (PORT datac (615:615:615) (641:641:641)) + (PORT datad (759:759:759) (743:743:743)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (922:922:922)) + (PORT datab (407:407:407) (416:416:416)) + (PORT datac (878:878:878) (907:907:907)) + (PORT datad (1087:1087:1087) (1100:1100:1100)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (255:255:255)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (176:176:176) (208:208:208)) + (PORT datad (190:190:190) (214:214:214)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT datab (205:205:205) (251:251:251)) + (PORT datac (172:172:172) (211:211:211)) + (PORT datad (351:351:351) (351:351:351)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (590:590:590) (599:599:599)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (DELAY + (ABSOLUTE + (PORT datab (1176:1176:1176) (1233:1233:1233)) + (PORT datac (824:824:824) (837:837:837)) + (PORT datad (1082:1082:1082) (1061:1061:1061)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1191:1191:1191) (1202:1202:1202)) + (PORT datab (936:936:936) (969:969:969)) + (PORT datac (1342:1342:1342) (1366:1366:1366)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1896:1896:1896) (1896:1896:1896)) + (PORT datab (866:866:866) (914:914:914)) + (PORT datac (1118:1118:1118) (1108:1108:1108)) + (PORT datad (1005:1005:1005) (1001:1001:1001)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (850:850:850)) + (PORT datab (981:981:981) (964:964:964)) + (PORT datac (819:819:819) (829:829:829)) + (PORT datad (524:524:524) (522:522:522)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1375:1375:1375) (1411:1411:1411)) + (PORT datab (408:408:408) (415:415:415)) + (PORT datac (859:859:859) (884:884:884)) + (PORT datad (1089:1089:1089) (1098:1098:1098)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1379:1379:1379) (1416:1416:1416)) + (PORT datab (214:214:214) (251:251:251)) + (PORT datac (1854:1854:1854) (1845:1845:1845)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (571:571:571) (585:585:585)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (234:234:234)) + (PORT datab (198:198:198) (231:231:231)) + (PORT datac (745:745:745) (775:775:775)) + (PORT datad (525:525:525) (507:507:507)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1348:1348:1348) (1376:1376:1376)) + (PORT datab (1303:1303:1303) (1272:1272:1272)) + (PORT datac (1453:1453:1453) (1474:1474:1474)) + (PORT datad (983:983:983) (973:973:973)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (700:700:700)) + (PORT datab (637:637:637) (664:664:664)) + (PORT datac (1479:1479:1479) (1443:1443:1443)) + (PORT datad (1325:1325:1325) (1335:1335:1335)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1242:1242:1242) (1288:1288:1288)) + (PORT datab (1003:1003:1003) (1001:1001:1001)) + (PORT datac (1453:1453:1453) (1470:1470:1470)) + (PORT datad (1656:1656:1656) (1697:1697:1697)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (776:776:776) (796:796:796)) + (PORT datac (1482:1482:1482) (1447:1447:1447)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~42) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (781:781:781)) + (PORT datab (1008:1008:1008) (1007:1007:1007)) + (PORT datac (1948:1948:1948) (1963:1963:1963)) + (PORT datad (1650:1650:1650) (1690:1690:1690)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (947:947:947) (926:926:926)) + (PORT datad (158:158:158) (178:178:178)) (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~41) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (642:642:642)) + (PORT datab (1892:1892:1892) (1909:1909:1909)) + (PORT datac (1365:1365:1365) (1394:1394:1394)) + (PORT datad (1233:1233:1233) (1319:1319:1319)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1393:1393:1393) (1426:1426:1426)) + (PORT datab (1812:1812:1812) (1838:1838:1838)) + (PORT datac (1150:1150:1150) (1187:1187:1187)) + (PORT datad (805:805:805) (815:815:815)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1607:1607:1607) (1662:1662:1662)) + (PORT datab (951:951:951) (989:989:989)) + (PORT datac (178:178:178) (214:214:214)) + (PORT datad (1379:1379:1379) (1408:1408:1408)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1071:1071:1071) (1049:1049:1049)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1252:1252:1252) (1248:1248:1248)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~44) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (761:761:761)) + (PORT datab (1679:1679:1679) (1738:1738:1738)) + (PORT datac (1205:1205:1205) (1254:1254:1254)) + (PORT datad (1656:1656:1656) (1697:1697:1697)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (638:638:638) (671:671:671)) + (PORT datac (801:801:801) (797:797:797)) + (PORT datad (628:628:628) (658:658:658)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (493:493:493)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (594:594:594) (607:607:607)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (556:556:556)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (561:561:561) (564:564:564)) + (PORT datad (320:320:320) (324:324:324)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (848:848:848) (862:862:862)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (297:297:297) (298:298:298)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1565:1565:1565)) + (PORT datab (1312:1312:1312) (1351:1351:1351)) + (PORT datac (580:580:580) (585:585:585)) + (PORT datad (792:792:792) (769:769:769)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -19023,14 +20261,158 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) (DELAY (ABSOLUTE - (PORT dataa (1119:1119:1119) (1132:1132:1132)) - (PORT datab (988:988:988) (968:968:968)) - (PORT datac (634:634:634) (685:685:685)) - (PORT datad (869:869:869) (881:881:881)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (1337:1337:1337) (1346:1346:1346)) + (PORT datab (783:783:783) (774:774:774)) + (PORT datac (772:772:772) (771:771:771)) + (PORT datad (1291:1291:1291) (1267:1267:1267)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (779:779:779) (768:768:768)) + (PORT datab (1647:1647:1647) (1590:1590:1590)) + (PORT datac (567:567:567) (568:568:568)) + (PORT datad (762:762:762) (748:748:748)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1125:1125:1125)) + (PORT datab (199:199:199) (241:241:241)) + (PORT datac (845:845:845) (862:862:862)) + (PORT datad (571:571:571) (566:566:566)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (306:306:306)) + (PORT datab (883:883:883) (904:904:904)) + (PORT datac (493:493:493) (487:487:487)) + (PORT datad (1039:1039:1039) (999:999:999)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (599:599:599)) + (PORT datab (1031:1031:1031) (1053:1053:1053)) + (PORT datac (547:547:547) (538:538:538)) + (PORT datad (364:364:364) (394:394:394)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (311:311:311)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (517:517:517) (522:522:522)) + (PORT datad (839:839:839) (865:865:865)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (459:459:459)) + (PORT datab (386:386:386) (447:447:447)) + (PORT datac (803:803:803) (806:806:806)) + (PORT datad (608:608:608) (621:621:621)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datab (584:584:584) (588:588:588)) + (PORT datac (325:325:325) (340:340:340)) + (PORT datad (769:769:769) (749:749:749)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -19039,28 +20421,237 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (487:487:487) (494:494:494)) - (PORT datab (568:568:568) (592:592:592)) - (PORT datac (586:586:586) (598:598:598)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (360:360:360) (376:376:376)) + (PORT datab (601:601:601) (629:629:629)) + (PORT datac (594:594:594) (618:618:618)) + (PORT datad (590:590:590) (589:589:589)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (393:393:393)) + (PORT datab (214:214:214) (257:257:257)) + (PORT datac (164:164:164) (197:197:197)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (659:659:659)) + (PORT datab (1092:1092:1092) (1142:1142:1142)) + (PORT datac (795:795:795) (806:806:806)) + (PORT datad (620:620:620) (631:631:631)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1229:1229:1229)) + (PORT datab (1813:1813:1813) (1842:1842:1842)) + (PORT datac (1365:1365:1365) (1399:1399:1399)) + (PORT datad (1379:1379:1379) (1403:1403:1403)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1051:1051:1051) (1044:1044:1044)) + (PORT datab (560:560:560) (584:584:584)) + (PORT datac (766:766:766) (737:737:737)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (232:232:232)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datad (743:743:743) (721:721:721)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1078:1078:1078) (1068:1068:1068)) + (PORT datac (525:525:525) (522:522:522)) + (PORT datad (1507:1507:1507) (1518:1518:1518)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (829:829:829)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1689:1689:1689) (1734:1734:1734)) + (PORT datad (520:520:520) (523:523:523)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (370:370:370)) + (PORT datab (1925:1925:1925) (1970:1970:1970)) + (PORT datac (1213:1213:1213) (1286:1286:1286)) + (PORT datad (835:835:835) (875:875:875)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (406:406:406)) + (PORT datab (566:566:566) (560:560:560)) + (PORT datac (1084:1084:1084) (1116:1116:1116)) + (PORT datad (762:762:762) (766:766:766)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (529:529:529)) + (PORT datab (569:569:569) (564:564:564)) + (PORT datad (528:528:528) (509:509:509)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (609:609:609)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (742:742:742) (717:717:717)) + (PORT datad (185:185:185) (209:209:209)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1567:1567:1567) (1575:1575:1575)) + (PORT datab (848:848:848) (842:842:842)) + (PORT datac (817:817:817) (812:812:812)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_latch_\|abusz\[12\]) (DELAY (ABSOLUTE - (PORT datac (1397:1397:1397) (1445:1445:1445)) - (PORT datad (581:581:581) (590:590:590)) + (PORT datab (369:369:369) (402:402:402)) + (PORT datac (821:821:821) (818:818:818)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[12\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (293:293:293) (300:300:300)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -19070,10 +20661,10 @@ (INSTANCE z80_\|address_latch_\|Q\[12\]) (DELAY (ABSOLUTE - (PORT clk (1343:1343:1343) (1365:1365:1365)) + (PORT clk (1345:1345:1345) (1363:1363:1363)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1358:1358:1358)) - (PORT ena (2292:2292:2292) (2253:2253:2253)) + (PORT clrn (1400:1400:1400) (1371:1371:1371)) + (PORT ena (1896:1896:1896) (1904:1904:1904)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -19088,24 +20679,101 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) (DELAY (ABSOLUTE - (PORT dataa (419:419:419) (472:472:472)) - (PORT datab (425:425:425) (490:490:490)) - (PORT datac (908:908:908) (927:927:927)) - (PORT datad (513:513:513) (501:501:501)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (577:577:577) (566:566:566)) + (PORT datab (839:839:839) (828:828:828)) + (PORT datac (214:214:214) (291:291:291)) + (PORT datad (540:540:540) (567:567:567)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1196:1196:1196) (1178:1178:1178)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (1330:1330:1330) (1307:1307:1307)) + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT asdata (1164:1164:1164) (1172:1172:1172)) + (PORT ena (857:857:857) (835:835:835)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (408:408:408)) + (PORT datab (379:379:379) (396:396:396)) + (PORT datad (177:177:177) (197:197:197)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (638:638:638)) + (PORT datac (196:196:196) (263:263:263)) + (PORT datad (716:716:716) (727:727:727)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (369:369:369)) + (PORT datab (786:786:786) (780:780:780)) + (PORT datac (630:630:630) (636:636:636)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1869:1869:1869) (1838:1838:1838)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -19117,310 +20785,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~22) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) (DELAY (ABSOLUTE - (PORT dataa (237:237:237) (300:300:300)) - (PORT datab (199:199:199) (231:231:231)) - (PORT datad (823:823:823) (873:873:873)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (903:903:903) (898:898:898)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (418:418:418) (438:438:438)) - (PORT datac (283:283:283) (296:296:296)) - (PORT datad (198:198:198) (255:255:255)) + (PORT dataa (379:379:379) (391:391:391)) + (PORT datab (1072:1072:1072) (1080:1080:1080)) + (PORT datad (694:694:694) (665:665:665)) + (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (639:639:639)) - (PORT datab (366:366:366) (392:392:392)) - (PORT datac (1530:1530:1530) (1609:1609:1609)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1381:1381:1381)) - (PORT asdata (1139:1139:1139) (1147:1147:1147)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1139:1139:1139)) - (PORT datab (1267:1267:1267) (1279:1279:1279)) - (PORT datad (1738:1738:1738) (1705:1705:1705)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1131:1131:1131) (1117:1117:1117)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1131:1131:1131) (1117:1117:1117)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (398:398:398) (432:432:432)) - (PORT datab (400:400:400) (415:415:415)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT asdata (1181:1181:1181) (1201:1201:1201)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT asdata (1180:1180:1180) (1201:1201:1201)) - (PORT ena (930:930:930) (921:921:921)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (876:876:876)) - (PORT datab (218:218:218) (286:286:286)) - (PORT datad (212:212:212) (244:244:244)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1175:1175:1175) (1177:1177:1177)) - (PORT ena (1108:1108:1108) (1069:1069:1069)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1174:1174:1174) (1174:1174:1174)) - (PORT ena (1138:1138:1138) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (618:618:618)) - (PORT datab (220:220:220) (288:288:288)) - (PORT datad (585:585:585) (573:573:573)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1126:1126:1126) (1122:1122:1122)) - (PORT ena (882:882:882) (874:874:874)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1126:1126:1126) (1122:1122:1122)) - (PORT ena (897:897:897) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (434:434:434)) - (PORT datab (383:383:383) (412:412:412)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (865:865:865) (848:848:848)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (1217:1217:1217) (1183:1183:1183)) - (PORT datab (781:781:781) (773:773:773)) - (PORT datad (363:363:363) (364:364:364)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19431,9 +20803,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) + (PORT clk (1355:1355:1355) (1376:1376:1376)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1280:1280:1280) (1295:1295:1295)) + (PORT ena (1347:1347:1347) (1329:1329:1329)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -19447,9 +20819,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (847:847:847) (838:838:838)) - (PORT ena (1327:1327:1327) (1302:1302:1302)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1869:1869:1869) (1835:1835:1835)) + (PORT ena (1140:1140:1140) (1144:1144:1144)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -19460,14 +20832,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~81) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) (DELAY (ABSOLUTE - (PORT dataa (423:423:423) (460:460:460)) - (PORT datab (425:425:425) (467:467:467)) - (PORT datad (612:612:612) (620:620:620)) + (PORT dataa (643:643:643) (688:688:688)) + (PORT datab (813:813:813) (820:820:820)) + (PORT datad (802:802:802) (793:793:793)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1261:1261:1261) (1287:1287:1287)) + (PORT ena (1118:1118:1118) (1094:1094:1094)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1260:1260:1260) (1289:1289:1289)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (857:857:857)) + (PORT datab (218:218:218) (260:260:260)) + (PORT datad (197:197:197) (253:253:253)) (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19475,147 +20894,211 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~82) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (769:769:769) (768:768:768)) - (PORT datab (564:564:564) (587:587:587)) - (PORT datac (553:553:553) (558:558:558)) - (PORT datad (549:549:549) (555:555:555)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datad (1284:1284:1284) (1247:1247:1247)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~83) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT dataa (576:576:576) (598:598:598)) - (PORT datab (523:523:523) (520:520:520)) - (PORT datac (809:809:809) (810:810:810)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1093:1093:1093) (1070:1070:1070)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1583:1583:1583) (1534:1534:1534)) + (PORT ena (1173:1173:1173) (1169:1169:1169)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~84) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) (DELAY (ABSOLUTE - (PORT dataa (1854:1854:1854) (1925:1925:1925)) - (PORT datab (542:542:542) (539:539:539)) - (PORT datac (1019:1019:1019) (1002:1002:1002)) - (PORT datad (745:745:745) (774:774:774)) - (IOPATH dataa combout (287:287:287) (280:280:280)) + (PORT dataa (363:363:363) (411:411:411)) + (PORT datab (1472:1472:1472) (1470:1470:1470)) + (PORT datad (1096:1096:1096) (1083:1083:1083)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (749:749:749) (726:726:726)) + (PORT datad (565:565:565) (572:572:572)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT dataa (1575:1575:1575) (1606:1606:1606)) - (PORT datac (1494:1494:1494) (1486:1486:1486)) - (PORT datad (1399:1399:1399) (1337:1337:1337)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1722:1722:1722) (1763:1763:1763)) + (PORT ena (1271:1271:1271) (1296:1296:1296)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1722:1722:1722) (1763:1763:1763)) + (PORT ena (1281:1281:1281) (1292:1292:1292)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (894:894:894)) + (PORT datab (827:827:827) (886:886:886)) + (PORT datad (196:196:196) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1788:1788:1788) (1721:1721:1721)) + (PORT ena (906:906:906) (905:905:905)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1785:1785:1785) (1721:1721:1721)) + (PORT ena (893:893:893) (877:877:877)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (473:473:473)) + (PORT datab (449:449:449) (482:482:482)) + (PORT datad (198:198:198) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1719:1719:1719) (1758:1758:1758)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (888:888:888)) + (PORT datab (1114:1114:1114) (1157:1157:1157)) + (PORT datad (832:832:832) (841:841:841)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) (DELAY (ABSOLUTE - (PORT dataa (1008:1008:1008) (1010:1010:1010)) - (PORT datab (996:996:996) (969:969:969)) - (PORT datac (1590:1590:1590) (1646:1646:1646)) - (PORT datad (1255:1255:1255) (1227:1227:1227)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT datab (1634:1634:1634) (1689:1689:1689)) - (PORT datac (812:812:812) (807:807:807)) - (PORT datad (1245:1245:1245) (1226:1226:1226)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (961:961:961)) - (PORT datac (1112:1112:1112) (1106:1106:1106)) - (PORT datad (1261:1261:1261) (1260:1260:1260)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT datab (1799:1799:1799) (1802:1802:1802)) - (PORT datac (707:707:707) (686:686:686)) - (PORT datad (964:964:964) (928:928:928)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (1076:1076:1076) (1066:1066:1066)) - (PORT datac (1544:1544:1544) (1572:1572:1572)) - (PORT datad (1402:1402:1402) (1342:1342:1342)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (987:987:987) (965:965:965)) - (PORT datab (569:569:569) (557:557:557)) - (PORT datac (960:960:960) (948:948:948)) - (PORT datad (1326:1326:1326) (1344:1344:1344)) + (PORT dataa (610:610:610) (616:616:616)) + (PORT datab (308:308:308) (325:325:325)) + (PORT datac (541:541:541) (534:534:534)) + (PORT datad (159:159:159) (180:180:180)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -19625,15 +21108,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) (DELAY (ABSOLUTE - (PORT dataa (626:626:626) (612:612:612)) - (PORT datab (325:325:325) (345:345:345)) - (PORT datac (798:798:798) (804:804:804)) - (PORT datad (530:530:530) (531:531:531)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (816:816:816) (863:863:863)) + (PORT datab (772:772:772) (825:825:825)) + (PORT datac (786:786:786) (755:755:755)) + (PORT datad (1208:1208:1208) (1196:1196:1196)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1212:1212:1212)) + (PORT datab (897:897:897) (908:908:908)) + (PORT datac (817:817:817) (809:809:809)) + (PORT datad (1327:1327:1327) (1311:1311:1311)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1168:1168:1168) (1194:1194:1194)) + (PORT datab (1141:1141:1141) (1122:1122:1122)) + (PORT datac (845:845:845) (859:859:859)) + (PORT datad (861:861:861) (871:871:871)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (226:226:226)) + (PORT datab (227:227:227) (274:274:274)) + (PORT datac (995:995:995) (950:950:950)) + (PORT datad (877:877:877) (892:892:892)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1217:1217:1217)) + (PORT datab (863:863:863) (907:907:907)) + (PORT datac (348:348:348) (357:357:357)) + (PORT datad (1116:1116:1116) (1172:1172:1172)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1023:1023:1023) (1113:1113:1113)) + (PORT datab (1690:1690:1690) (1727:1727:1727)) + (PORT datac (819:819:819) (847:847:847)) + (PORT datad (1442:1442:1442) (1492:1492:1492)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19641,13 +21204,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) (DELAY (ABSOLUTE - (PORT dataa (1546:1546:1546) (1575:1575:1575)) - (PORT datab (540:540:540) (533:533:533)) - (PORT datac (1592:1592:1592) (1597:1597:1597)) - (PORT datad (2236:2236:2236) (2237:2237:2237)) + (PORT dataa (856:856:856) (881:881:881)) + (PORT datab (588:588:588) (597:597:597)) + (PORT datac (1286:1286:1286) (1346:1346:1346)) + (PORT datad (544:544:544) (546:546:546)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -19657,79 +21220,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (702:702:702) (669:669:669)) - (PORT datac (530:530:530) (521:521:521)) - (PORT datad (964:964:964) (936:936:936)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1307:1307:1307) (1369:1369:1369)) - (PORT datab (592:592:592) (639:639:639)) - (PORT datac (505:505:505) (505:505:505)) - (PORT datad (1187:1187:1187) (1172:1172:1172)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (776:776:776) (776:776:776)) - (PORT datab (360:360:360) (364:364:364)) - (PORT datac (314:314:314) (322:322:322)) - (PORT datad (1690:1690:1690) (1729:1729:1729)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1198:1198:1198)) - (PORT datab (1512:1512:1512) (1489:1489:1489)) - (PORT datac (527:527:527) (507:507:507)) - (PORT datad (2165:2165:2165) (2147:2147:2147)) + (PORT dataa (186:186:186) (224:224:224)) + (PORT datac (860:860:860) (864:864:864)) + (PORT datad (220:220:220) (254:254:254)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (598:598:598)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (340:340:340) (344:344:344)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19737,15 +21234,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) (DELAY (ABSOLUTE - (PORT dataa (666:666:666) (687:687:687)) - (PORT datab (633:633:633) (666:666:666)) - (PORT datac (542:542:542) (548:548:548)) - (PORT datad (547:547:547) (534:534:534)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (1095:1095:1095) (1096:1096:1096)) + (PORT datab (251:251:251) (320:320:320)) + (PORT datac (223:223:223) (275:275:275)) + (PORT datad (225:225:225) (262:262:262)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19753,40 +21250,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) (DELAY (ABSOLUTE - (PORT dataa (737:737:737) (727:727:727)) - (PORT datab (765:765:765) (741:741:741)) - (PORT datac (681:681:681) (653:653:653)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (228:228:228)) - (PORT datab (838:838:838) (890:890:890)) - (PORT datad (174:174:174) (202:202:202)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datab (334:334:334) (356:356:356)) + (PORT datac (857:857:857) (887:887:887)) + (PORT datad (625:625:625) (655:655:655)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (INSTANCE z80_\|alu_\|op1_high\[0\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) + (PORT clk (1350:1350:1350) (1357:1357:1357)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (935:935:935) (942:942:942)) + (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -19797,11 +21280,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) (DELAY (ABSOLUTE - (PORT datac (1603:1603:1603) (1660:1660:1660)) - (PORT datad (1248:1248:1248) (1226:1226:1226)) + (PORT dataa (593:593:593) (623:623:623)) + (PORT datab (1072:1072:1072) (1085:1085:1085)) + (PORT datac (595:595:595) (626:626:626)) + (PORT datad (619:619:619) (635:635:635)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19809,119 +21296,208 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (INSTANCE z80_\|alu_\|db_high\[0\]\~25) (DELAY (ABSOLUTE - (PORT dataa (810:810:810) (813:813:813)) - (PORT datab (987:987:987) (975:975:975)) - (PORT datac (951:951:951) (930:930:930)) - (PORT datad (1327:1327:1327) (1344:1344:1344)) + (PORT dataa (559:559:559) (560:560:560)) + (PORT datab (306:306:306) (321:321:321)) + (PORT datac (1071:1071:1071) (1088:1088:1088)) + (PORT datad (504:504:504) (485:485:485)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (606:606:606)) + (PORT datab (919:919:919) (929:929:929)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (199:199:199) (238:238:238)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT asdata (502:502:502) (528:528:528)) + (PORT dataa (556:556:556) (543:543:543)) + (PORT datab (889:889:889) (910:910:910)) + (PORT datac (799:799:799) (810:810:810)) + (PORT datad (312:312:312) (322:322:322)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (619:619:619) (648:648:648)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (DELAY + (ABSOLUTE + (PORT dataa (842:842:842) (853:853:853)) + (PORT datab (670:670:670) (693:693:693)) + (PORT datac (859:859:859) (885:885:885)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) (DELAY (ABSOLUTE - (PORT datac (725:725:725) (704:704:704)) - (PORT datad (208:208:208) (242:242:242)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (601:601:601) (607:607:607)) + (PORT datab (590:590:590) (623:623:623)) + (PORT datac (566:566:566) (594:594:594)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (583:583:583)) + (PORT datab (874:874:874) (897:897:897)) + (PORT datac (1004:1004:1004) (1034:1034:1034)) + (PORT datad (536:536:536) (536:536:536)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (815:815:815) (819:819:819)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datad (561:561:561) (567:567:567)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (240:240:240) (311:311:311)) + (PORT datac (156:156:156) (186:186:186)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) + (INSTANCE z80_\|alu_\|op2_low\[0\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1369:1369:1369)) + (PORT clk (1350:1350:1350) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (792:792:792) (798:798:798)) - (PORT datab (673:673:673) (726:726:726)) - (PORT datac (619:619:619) (665:665:665)) - (PORT datad (963:963:963) (931:931:931)) + (PORT dataa (397:397:397) (467:467:467)) + (PORT datac (596:596:596) (629:629:629)) + (PORT datad (609:609:609) (628:628:628)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (534:534:534)) + (PORT datab (765:765:765) (758:758:758)) + (PORT datac (740:740:740) (715:715:715)) + (PORT datad (184:184:184) (209:209:209)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (629:629:629)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (182:182:182) (217:217:217)) + (PORT datad (758:758:758) (742:742:742)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (606:606:606)) + (PORT datab (582:582:582) (628:628:628)) + (PORT datad (583:583:583) (615:615:615)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1047:1047:1047)) - (PORT datab (1025:1025:1025) (989:989:989)) - (PORT datac (638:638:638) (681:681:681)) - (PORT datad (766:766:766) (761:761:761)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (551:551:551)) - (PORT datab (569:569:569) (560:560:560)) - (PORT datad (527:527:527) (518:518:518)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -19931,28 +21507,12 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (1292:1292:1292) (1274:1274:1274)) - (PORT datab (665:665:665) (705:705:705)) - (PORT datac (1015:1015:1015) (1016:1016:1016)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1040:1040:1040) (1034:1034:1034)) - (PORT datab (1096:1096:1096) (1136:1136:1136)) - (PORT datac (950:950:950) (957:957:957)) - (PORT datad (1069:1069:1069) (1041:1041:1041)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (621:621:621) (621:621:621)) + (PORT datab (801:801:801) (784:784:784)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (480:480:480) (472:472:472)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19960,28 +21520,128 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~16) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) (DELAY (ABSOLUTE - (PORT dataa (716:716:716) (702:702:702)) - (PORT datab (224:224:224) (280:280:280)) - (PORT datac (158:158:158) (190:190:190)) - (PORT datad (784:784:784) (775:775:775)) - (IOPATH dataa combout (265:265:265) (269:269:269)) + (PORT dataa (187:187:187) (226:226:226)) + (PORT datab (192:192:192) (232:232:232)) + (PORT datac (181:181:181) (215:215:215)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (633:633:633)) + (PORT datab (616:616:616) (621:621:621)) + (PORT datad (567:567:567) (579:579:579)) + (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (365:365:365)) + (PORT datab (585:585:585) (589:589:589)) + (PORT datac (163:163:163) (195:195:195)) + (PORT datad (768:768:768) (749:749:749)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (368:368:368)) + (PORT datab (368:368:368) (374:374:374)) + (PORT datac (161:161:161) (194:194:194)) + (PORT datad (340:340:340) (345:345:345)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT datac (1618:1618:1618) (1563:1563:1563)) + (PORT datad (762:762:762) (748:748:748)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (363:363:363)) + (PORT datab (210:210:210) (251:251:251)) + (PORT datac (160:160:160) (193:193:193)) + (PORT datad (164:164:164) (187:187:187)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (212:212:212) (254:254:254)) + (PORT datac (325:325:325) (338:338:338)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1369:1369:1369)) + (PORT datad (987:987:987) (994:994:994)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (903:903:903) (898:898:898)) + (PORT ena (1093:1093:1093) (1070:1070:1070)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -19992,12 +21652,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (861:861:861) (847:847:847)) - (PORT ena (716:716:716) (714:714:714)) + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1322:1322:1322) (1333:1333:1333)) + (PORT ena (1173:1173:1173) (1169:1169:1169)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -20008,209 +21668,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~10) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) (DELAY (ABSOLUTE - (PORT dataa (234:234:234) (301:301:301)) - (PORT datab (864:864:864) (911:911:911)) - (PORT datad (530:530:530) (525:525:525)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (294:294:294)) - (PORT datab (415:415:415) (437:437:437)) - (PORT datac (310:310:310) (316:316:316)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT datab (1800:1800:1800) (1803:1803:1803)) - (PORT datac (708:708:708) (686:686:686)) - (PORT datad (964:964:964) (928:928:928)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (1146:1146:1146) (1136:1136:1136)) - (PORT ena (1157:1157:1157) (1125:1125:1125)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (795:795:795) (803:803:803)) - (PORT datab (1542:1542:1542) (1554:1554:1554)) - (PORT datad (1177:1177:1177) (1141:1141:1141)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (1148:1148:1148) (1138:1138:1138)) - (PORT ena (1312:1312:1312) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (612:612:612)) - (PORT datab (805:805:805) (824:824:824)) - (PORT datad (198:198:198) (254:254:254)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1464:1464:1464) (1537:1537:1537)) - (PORT datab (1193:1193:1193) (1220:1220:1220)) - (PORT datac (1073:1073:1073) (1061:1061:1061)) - (PORT datad (739:739:739) (723:723:723)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT asdata (877:877:877) (877:877:877)) - (PORT ena (1332:1332:1332) (1366:1366:1366)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1460:1460:1460) (1541:1541:1541)) - (PORT datab (1191:1191:1191) (1220:1220:1220)) - (PORT datac (1074:1074:1074) (1063:1063:1063)) - (PORT datad (738:738:738) (726:726:726)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT asdata (874:874:874) (874:874:874)) - (PORT ena (1099:1099:1099) (1089:1089:1089)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (324:324:324)) - (PORT datab (222:222:222) (291:291:291)) - (PORT datad (543:543:543) (547:547:547)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (965:965:965)) - (PORT datac (1116:1116:1116) (1109:1109:1109)) - (PORT datad (1261:1261:1261) (1259:1259:1259)) + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (1475:1475:1475) (1473:1473:1473)) + (PORT datad (1095:1095:1095) (1089:1089:1089)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT asdata (839:839:839) (829:829:829)) - (PORT ena (739:739:739) (742:742:742)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1514:1514:1514) (1542:1542:1542)) + (PORT ena (1118:1118:1118) (1094:1094:1094)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -20219,26 +21697,13 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT datab (341:341:341) (366:366:366)) - (PORT datad (197:197:197) (224:224:224)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT asdata (631:631:631) (630:630:630)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1512:1512:1512) (1538:1538:1538)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -20250,13 +21715,91 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) (DELAY (ABSOLUTE - (PORT dataa (552:552:552) (552:552:552)) - (PORT datab (233:233:233) (277:277:277)) - (PORT datad (1033:1033:1033) (1029:1029:1029)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT dataa (836:836:836) (854:854:854)) + (PORT datab (219:219:219) (261:261:261)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1347:1347:1347) (1329:1329:1329)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1287:1287:1287) (1329:1329:1329)) + (PORT ena (1140:1140:1140) (1144:1144:1144)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (702:702:702)) + (PORT datab (813:813:813) (820:820:820)) + (PORT datad (802:802:802) (793:793:793)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1287:1287:1287) (1330:1330:1330)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (1299:1299:1299) (1263:1263:1263)) + (PORT datab (1074:1074:1074) (1082:1082:1082)) + (PORT datad (218:218:218) (251:251:251)) + (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -20265,15 +21808,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) (DELAY (ABSOLUTE - (PORT dataa (1180:1180:1180) (1197:1197:1197)) - (PORT datab (1514:1514:1514) (1488:1488:1488)) - (PORT datac (546:546:546) (569:569:569)) - (PORT datad (2167:2167:2167) (2151:2151:2151)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (764:764:764) (758:758:758)) + (PORT datab (991:991:991) (1012:1012:1012)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20281,11 +21824,2190 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT asdata (856:856:856) (841:841:841)) + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1326:1326:1326) (1339:1339:1339)) + (PORT ena (906:906:906) (905:905:905)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1324:1324:1324) (1338:1338:1338)) + (PORT ena (893:893:893) (877:877:877)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (429:429:429) (477:477:477)) + (PORT datab (450:450:450) (481:481:481)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1262:1262:1262) (1284:1284:1284)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (895:895:895)) + (PORT datab (1115:1115:1115) (1156:1156:1156)) + (PORT datad (827:827:827) (840:840:840)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1086:1086:1086) (1125:1125:1125)) + (PORT ena (1271:1271:1271) (1296:1296:1296)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1086:1086:1086) (1124:1124:1124)) + (PORT ena (1281:1281:1281) (1292:1292:1292)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (885:885:885)) + (PORT datab (825:825:825) (893:893:893)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (363:363:363)) + (PORT datab (586:586:586) (607:607:607)) + (PORT datac (586:586:586) (597:597:597)) + (PORT datad (726:726:726) (777:777:777)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT asdata (1039:1039:1039) (1059:1059:1059)) + (PORT ena (857:857:857) (835:835:835)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (374:374:374) (393:393:393)) + (PORT datad (364:364:364) (377:377:377)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1196:1196:1196) (1178:1178:1178)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (777:777:777)) + (PORT datac (193:193:193) (259:259:259)) + (PORT datad (600:600:600) (600:600:600)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (563:563:563)) + (PORT datab (843:843:843) (835:835:835)) + (PORT datac (213:213:213) (287:287:287)) + (PORT datad (539:539:539) (564:564:564)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT datac (232:232:232) (309:309:309)) + (PORT datad (169:169:169) (199:199:199)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1287:1287:1287) (1338:1338:1338)) + (PORT ena (1164:1164:1164) (1167:1167:1167)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1347:1347:1347) (1329:1329:1329)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1013:1013:1013)) + (PORT datab (817:817:817) (832:832:832)) + (PORT datad (611:611:611) (654:654:654)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1879:1879:1879) (1893:1893:1893)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1533:1533:1533) (1489:1489:1489)) + (PORT datab (1071:1071:1071) (1076:1076:1076)) + (PORT datad (210:210:210) (243:243:243)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1017:1017:1017) (1055:1055:1055)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1093:1093:1093) (1070:1070:1070)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1300:1300:1300) (1335:1335:1335)) + (PORT ena (1173:1173:1173) (1169:1169:1169)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (408:408:408)) + (PORT datab (1474:1474:1474) (1477:1477:1477)) + (PORT datad (1095:1095:1095) (1089:1089:1089)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1647:1647:1647) (1670:1670:1670)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1288:1288:1288) (1337:1337:1337)) + (PORT ena (1039:1039:1039) (993:993:993)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (427:427:427)) + (PORT datab (808:808:808) (830:830:830)) + (PORT datad (339:339:339) (347:347:347)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (310:310:310) (329:329:329)) + (PORT datac (736:736:736) (718:718:718)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1322:1322:1322) (1359:1359:1359)) + (PORT ena (893:893:893) (877:877:877)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1323:1323:1323) (1361:1361:1361)) + (PORT ena (906:906:906) (905:905:905)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (473:473:473)) + (PORT datab (219:219:219) (287:287:287)) + (PORT datad (416:416:416) (454:454:454)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1580:1580:1580) (1596:1596:1596)) + (PORT ena (1281:1281:1281) (1292:1292:1292)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1581:1581:1581) (1599:1599:1599)) + (PORT ena (1271:1271:1271) (1296:1296:1296)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (892:892:892)) + (PORT datab (222:222:222) (291:291:291)) + (PORT datad (800:800:800) (850:850:850)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1621:1621:1621) (1650:1650:1650)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (890:890:890)) + (PORT datab (1113:1113:1113) (1157:1157:1157)) + (PORT datad (830:830:830) (842:842:842)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (615:615:615)) + (PORT datab (761:761:761) (785:785:785)) + (PORT datac (572:572:572) (565:565:565)) + (PORT datad (773:773:773) (752:752:752)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (861:861:861)) + (PORT datab (180:180:180) (211:211:211)) + (PORT datac (744:744:744) (776:776:776)) + (PORT datad (1208:1208:1208) (1193:1193:1193)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT asdata (1055:1055:1055) (1083:1083:1083)) + (PORT ena (857:857:857) (835:835:835)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (408:408:408)) + (PORT datab (198:198:198) (232:232:232)) + (PORT datad (354:354:354) (365:365:365)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1196:1196:1196) (1178:1178:1178)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (637:637:637)) + (PORT datab (348:348:348) (378:378:378)) + (PORT datac (195:195:195) (262:262:262)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (514:514:514)) + (PORT datab (791:791:791) (787:787:787)) + (PORT datac (633:633:633) (637:637:637)) + (PORT datad (159:159:159) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT datab (351:351:351) (381:381:381)) + (PORT datac (821:821:821) (822:822:822)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (312:312:312) (317:317:317)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1371:1371:1371)) + (PORT ena (1896:1896:1896) (1904:1904:1904)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (DELAY + (ABSOLUTE + (PORT datac (232:232:232) (309:309:309)) + (PORT datad (805:805:805) (797:797:797)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (DELAY + (ABSOLUTE + (PORT datac (333:333:333) (341:341:341)) + (PORT datad (803:803:803) (800:800:800)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1371:1371:1371)) + (PORT ena (1896:1896:1896) (1904:1904:1904)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (341:341:341)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (221:221:221) (291:291:291)) + (PORT datad (802:802:802) (798:798:798)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1196:1196:1196) (1178:1178:1178)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (2087:2087:2087) (2176:2176:2176)) + (PORT ena (906:906:906) (905:905:905)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (2087:2087:2087) (2177:2177:2177)) + (PORT ena (893:893:893) (877:877:877)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (472:472:472)) + (PORT datab (451:451:451) (487:487:487)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1723:1723:1723) (1782:1782:1782)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (739:739:739)) + (PORT datab (1074:1074:1074) (1081:1081:1081)) + (PORT datad (219:219:219) (254:254:254)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1085:1085:1085) (1135:1135:1135)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1949:1949:1949) (1996:1996:1996)) + (PORT ena (1039:1039:1039) (993:993:993)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (408:408:408)) + (PORT datab (809:809:809) (832:832:832)) + (PORT datad (339:339:339) (348:348:348)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1324:1324:1324) (1348:1348:1348)) + (PORT ena (1173:1173:1173) (1169:1169:1169)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1324:1324:1324) (1348:1348:1348)) + (PORT ena (1093:1093:1093) (1070:1070:1070)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1200:1200:1200)) + (PORT datab (1135:1135:1135) (1117:1117:1117)) + (PORT datad (195:195:195) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1347:1347:1347) (1329:1329:1329)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1951:1951:1951) (1996:1996:1996)) + (PORT ena (1164:1164:1164) (1167:1167:1167)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1008:1008:1008)) + (PORT datab (631:631:631) (669:669:669)) + (PORT datad (783:783:783) (794:794:794)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (554:554:554)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (548:548:548) (544:544:544)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1096:1096:1096) (1141:1141:1141)) + (PORT ena (1271:1271:1271) (1296:1296:1296)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1097:1097:1097) (1141:1141:1141)) + (PORT ena (1281:1281:1281) (1292:1292:1292)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (890:890:890)) + (PORT datab (826:826:826) (887:887:887)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1992:1992:1992) (1966:1966:1966)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (899:899:899)) + (PORT datab (1113:1113:1113) (1158:1158:1158)) + (PORT datad (825:825:825) (837:837:837)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (582:582:582)) + (PORT datab (585:585:585) (603:603:603)) + (PORT datac (460:460:460) (454:454:454)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (814:814:814) (859:859:859)) + (PORT datab (618:618:618) (614:614:614)) + (PORT datac (722:722:722) (755:755:755)) + (PORT datad (1211:1211:1211) (1194:1194:1194)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT asdata (1035:1035:1035) (1063:1063:1063)) + (PORT ena (857:857:857) (835:835:835)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (415:415:415)) + (PORT datab (199:199:199) (233:233:233)) + (PORT datad (351:351:351) (363:363:363)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (297:297:297)) + (PORT datab (620:620:620) (618:618:618)) + (PORT datad (600:600:600) (599:599:599)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (354:354:354)) + (PORT datab (659:659:659) (664:664:664)) + (PORT datac (758:758:758) (750:750:750)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (851:851:851)) + (PORT datac (334:334:334) (355:355:355)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (302:302:302) (296:296:296)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1371:1371:1371)) + (PORT ena (1896:1896:1896) (1904:1904:1904)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1060:1060:1060)) + (PORT datab (374:374:374) (427:427:427)) + (PORT datac (1030:1030:1030) (991:991:991)) + (PORT datad (586:586:586) (589:589:589)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (194:194:194) (233:233:233)) + (PORT datac (209:209:209) (281:281:281)) + (PORT datad (316:316:316) (319:319:319)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (370:370:370)) + (PORT datab (660:660:660) (671:671:671)) + (PORT datac (762:762:762) (758:758:758)) + (PORT datad (514:514:514) (503:503:503)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (813:813:813) (866:866:866)) + (PORT datab (615:615:615) (626:626:626)) + (PORT datac (726:726:726) (751:751:751)) + (PORT datad (1207:1207:1207) (1198:1198:1198)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1203:1203:1203)) + (PORT datab (905:905:905) (909:909:909)) + (PORT datac (1722:1722:1722) (1740:1740:1740)) + (PORT datad (765:765:765) (752:752:752)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (224:224:224)) + (PORT datab (231:231:231) (282:282:282)) + (PORT datac (1100:1100:1100) (1078:1078:1078)) + (PORT datad (870:870:870) (885:885:885)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (862:862:862)) + (PORT datab (1122:1122:1122) (1147:1147:1147)) + (PORT datac (839:839:839) (832:832:832)) + (PORT datad (1284:1284:1284) (1294:1294:1294)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (838:838:838)) + (PORT datab (614:614:614) (613:613:613)) + (PORT datac (614:614:614) (619:619:619)) + (PORT datad (621:621:621) (632:632:632)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1407:1407:1407) (1450:1450:1450)) + (PORT datab (1289:1289:1289) (1361:1361:1361)) + (PORT datac (1297:1297:1297) (1317:1317:1317)) + (PORT datad (780:780:780) (770:770:770)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (564:564:564)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (176:176:176) (207:207:207)) + (PORT datad (1005:1005:1005) (1002:1002:1002)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1081:1081:1081) (1074:1074:1074)) + (PORT datab (912:912:912) (944:944:944)) + (PORT datac (190:190:190) (227:227:227)) + (PORT datad (1859:1859:1859) (1867:1867:1867)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (236:236:236)) + (PORT datab (589:589:589) (575:575:575)) + (PORT datac (561:561:561) (550:550:550)) + (PORT datad (568:568:568) (566:566:566)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (642:642:642) (672:672:672)) + (PORT datac (1228:1228:1228) (1212:1212:1212)) + (PORT datad (1061:1061:1061) (1068:1068:1068)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1568:1568:1568) (1604:1604:1604)) + (PORT datab (1366:1366:1366) (1410:1410:1410)) + (PORT datac (2377:2377:2377) (2403:2403:2403)) + (PORT datad (1740:1740:1740) (1778:1778:1778)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1788:1788:1788) (1824:1824:1824)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (842:842:842) (859:859:859)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (608:608:608)) + (PORT datab (590:590:590) (598:598:598)) + (PORT datad (809:809:809) (830:830:830)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (1332:1332:1332) (1350:1350:1350)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1103:1103:1103) (1149:1149:1149)) + (PORT datab (231:231:231) (304:304:304)) + (PORT datac (1255:1255:1255) (1261:1261:1261)) + (PORT datad (1099:1099:1099) (1117:1117:1117)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (179:179:179) (212:212:212)) + (PORT datad (1079:1079:1079) (1113:1113:1113)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (822:822:822) (821:821:821)) + (PORT datad (1281:1281:1281) (1295:1295:1295)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (397:397:397)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (823:823:823) (829:829:829)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (459:459:459)) + (PORT datab (1065:1065:1065) (1077:1077:1077)) + (PORT datac (550:550:550) (577:577:577)) + (PORT datad (618:618:618) (634:634:634)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1093:1093:1093) (1092:1092:1092)) + (PORT datab (243:243:243) (309:309:309)) + (PORT datac (219:219:219) (274:274:274)) + (PORT datad (234:234:234) (271:271:271)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (333:333:333)) + (PORT datab (749:749:749) (742:742:742)) + (PORT datac (463:463:463) (447:447:447)) + (PORT datad (1014:1014:1014) (1005:1005:1005)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (567:567:567)) + (PORT datab (920:920:920) (930:930:930)) + (PORT datac (542:542:542) (538:538:538)) + (PORT datad (200:200:200) (239:239:239)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (361:361:361)) + (PORT datab (826:826:826) (839:839:839)) + (PORT datac (1063:1063:1063) (1038:1038:1038)) + (PORT datad (630:630:630) (650:650:650)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (676:676:676)) + (PORT datab (1072:1072:1072) (1089:1089:1089)) + (PORT datac (571:571:571) (605:605:605)) + (PORT datad (621:621:621) (641:641:641)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (DELAY + (ABSOLUTE + (PORT datab (249:249:249) (315:315:315)) + (PORT datad (229:229:229) (266:266:266)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (308:308:308)) + (PORT datab (583:583:583) (570:570:570)) + (PORT datac (1062:1062:1062) (1058:1058:1058)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1177:1177:1177) (1162:1162:1162)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (892:892:892)) + (PORT datac (1533:1533:1533) (1538:1538:1538)) + (PORT datad (1304:1304:1304) (1277:1277:1277)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1045:1045:1045) (1033:1033:1033)) + (PORT datab (1038:1038:1038) (1036:1036:1036)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (220:220:220) (254:254:254)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (476:476:476)) + (PORT datab (820:820:820) (835:835:835)) + (PORT datac (884:884:884) (892:892:892)) + (PORT datad (554:554:554) (543:543:543)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1121:1121:1121)) + (PORT datab (575:575:575) (574:574:574)) + (PORT datac (171:171:171) (213:213:213)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (626:626:626)) + (PORT datab (858:858:858) (851:851:851)) + (PORT datac (795:795:795) (793:793:793)) + (PORT datad (1069:1069:1069) (1065:1065:1065)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (599:599:599)) + (PORT datab (897:897:897) (906:906:906)) + (PORT datac (1066:1066:1066) (1069:1069:1069)) + (PORT datad (202:202:202) (243:243:243)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (252:252:252)) + (PORT datab (1335:1335:1335) (1345:1345:1345)) + (PORT datac (1038:1038:1038) (1033:1033:1033)) + (PORT datad (163:163:163) (186:186:186)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1129:1129:1129)) + (PORT datab (871:871:871) (866:866:866)) + (PORT datac (499:499:499) (489:489:489)) + (PORT datad (778:778:778) (762:762:762)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1340:1340:1340) (1384:1384:1384)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (209:209:209) (250:250:250)) + (PORT datad (1300:1300:1300) (1310:1310:1310)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (593:593:593)) + (PORT datab (568:568:568) (581:581:581)) + (PORT datac (609:609:609) (615:615:615)) + (PORT datad (626:626:626) (639:639:639)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datab (567:567:567) (590:590:590)) + (PORT datad (734:734:734) (793:793:793)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (597:597:597)) + (PORT datab (2129:2129:2129) (2118:2118:2118)) + (PORT datac (1897:1897:1897) (1944:1944:1944)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (378:378:378)) + (PORT datab (1506:1506:1506) (1510:1510:1510)) + (PORT datac (771:771:771) (762:762:762)) + (PORT datad (163:163:163) (189:189:189)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (788:788:788)) + (PORT datab (327:327:327) (353:353:353)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (166:166:166) (191:191:191)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (884:884:884)) + (PORT datab (639:639:639) (644:644:644)) + (PORT datac (528:528:528) (512:512:512)) + (PORT datad (567:567:567) (575:575:575)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (881:881:881) (876:876:876)) + (PORT datac (584:584:584) (610:610:610)) + (PORT datad (607:607:607) (634:634:634)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (334:334:334)) + (PORT datab (190:190:190) (226:226:226)) + (PORT datac (160:160:160) (192:192:192)) + (PORT datad (592:592:592) (607:607:607)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (804:804:804)) + (PORT datab (920:920:920) (947:947:947)) + (PORT datac (1321:1321:1321) (1376:1376:1376)) + (PORT datad (1057:1057:1057) (1052:1052:1052)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (617:617:617)) + (PORT datab (855:855:855) (865:865:865)) + (PORT datac (1341:1341:1341) (1367:1367:1367)) + (PORT datad (1066:1066:1066) (1053:1053:1053)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (578:578:578)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (820:820:820) (831:831:831)) + (PORT datad (176:176:176) (198:198:198)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT datab (1528:1528:1528) (1520:1520:1520)) + (PORT datac (1336:1336:1336) (1338:1338:1338)) + (PORT datad (1075:1075:1075) (1068:1068:1068)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (458:458:458)) + (PORT datab (1131:1131:1131) (1152:1152:1152)) + (PORT datac (1069:1069:1069) (1065:1065:1065)) + (PORT datad (845:845:845) (849:849:849)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (812:812:812)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (806:806:806) (817:817:817)) + (PORT datad (580:580:580) (589:589:589)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (575:575:575)) + (PORT datab (221:221:221) (266:266:266)) + (PORT datac (1066:1066:1066) (1070:1070:1070)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (450:450:450)) + (PORT datab (1071:1071:1071) (1055:1055:1055)) + (PORT datad (1350:1350:1350) (1340:1340:1340)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (434:434:434)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (1501:1501:1501) (1461:1461:1461)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) + (DELAY + (ABSOLUTE + (PORT datab (331:331:331) (345:345:345)) + (PORT datac (731:731:731) (710:710:710)) + (PORT datad (301:301:301) (301:301:301)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (887:887:887) (908:908:908)) + (PORT ena (1297:1297:1297) (1275:1275:1275)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (887:887:887) (908:908:908)) + (PORT ena (1588:1588:1588) (1555:1555:1555)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (300:300:300)) + (PORT datab (891:891:891) (937:937:937)) + (PORT datad (786:786:786) (805:805:805)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (797:797:797) (781:781:781)) (PORT ena (735:735:735) (733:733:733)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -20295,28 +24017,14 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT datab (1637:1637:1637) (1692:1692:1692)) - (PORT datac (813:813:813) (808:808:808)) - (PORT datad (1248:1248:1248) (1226:1226:1226)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT asdata (858:858:858) (844:844:844)) - (PORT ena (1355:1355:1355) (1327:1327:1327)) + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (797:797:797) (781:781:781)) + (PORT ena (763:763:763) (771:771:771)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -20327,122 +24035,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (320:320:320)) - (PORT datab (637:637:637) (677:677:677)) - (PORT datad (200:200:200) (257:257:257)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (747:747:747) (775:775:775)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (327:327:327) (332:332:332)) - (PORT datad (532:532:532) (518:518:518)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (1146:1146:1146) (1147:1147:1147)) - (PORT ena (1109:1109:1109) (1075:1075:1075)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (1142:1142:1142) (1143:1143:1143)) - (PORT ena (1094:1094:1094) (1065:1065:1065)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (411:411:411)) - (PORT datab (643:643:643) (649:649:649)) - (PORT datad (607:607:607) (606:606:606)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1152:1152:1152) (1157:1157:1157)) - (PORT ena (1104:1104:1104) (1097:1097:1097)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1150:1150:1150) (1153:1153:1153)) - (PORT ena (1197:1197:1197) (1191:1191:1191)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (294:294:294)) - (PORT datab (632:632:632) (667:667:667)) - (PORT datad (620:620:620) (646:646:646)) + (PORT dataa (223:223:223) (296:296:296)) + (PORT datab (231:231:231) (282:282:282)) + (PORT datad (207:207:207) (242:242:242)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -20452,29 +24050,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (521:521:521) (514:514:514)) - (PORT datad (772:772:772) (744:744:744)) + (PORT dataa (791:791:791) (771:771:771)) + (PORT datab (185:185:185) (219:219:219)) + (PORT datac (560:560:560) (567:567:567)) + (PORT datad (575:575:575) (587:587:587)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) (DELAY (ABSOLUTE - (PORT dataa (1417:1417:1417) (1460:1460:1460)) - (PORT datab (340:340:340) (347:347:347)) - (PORT datac (746:746:746) (735:735:735)) - (PORT datad (554:554:554) (551:551:551)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (798:798:798) (794:794:794)) + (PORT datab (564:564:564) (570:570:570)) + (PORT datac (311:311:311) (318:318:318)) + (PORT datad (1035:1035:1035) (1014:1014:1014)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20482,12 +24082,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1371:1371:1371)) - (PORT asdata (831:831:831) (826:826:826)) - (PORT ena (739:739:739) (742:742:742)) + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT asdata (886:886:886) (890:890:890)) + (PORT ena (1105:1105:1105) (1078:1078:1078)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -20498,12 +24098,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) (DELAY (ABSOLUTE - (PORT dataa (802:802:802) (792:792:792)) - (PORT datab (219:219:219) (265:265:265)) - (PORT datad (1171:1171:1171) (1123:1123:1123)) + (PORT dataa (1236:1236:1236) (1213:1213:1213)) + (PORT datab (647:647:647) (665:665:665)) + (PORT datad (1107:1107:1107) (1126:1126:1126)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -20513,12 +24113,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) + (PORT clk (1363:1363:1363) (1384:1384:1384)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (935:935:935) (942:942:942)) + (PORT ena (1175:1175:1175) (1170:1170:1170)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -20529,14 +24129,527 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (590:590:590)) + (PORT datac (647:647:647) (678:678:678)) + (PORT datad (201:201:201) (259:259:259)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (361:361:361)) + (PORT datab (884:884:884) (895:895:895)) + (PORT datac (628:628:628) (660:660:660)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT datab (217:217:217) (259:259:259)) + (PORT datac (511:511:511) (501:501:501)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT asdata (794:794:794) (788:788:788)) + (PORT clrn (1409:1409:1409) (1380:1380:1380)) + (PORT ena (1969:1969:1969) (1997:1997:1997)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (384:384:384)) + (PORT datab (1063:1063:1063) (1066:1066:1066)) + (PORT datac (889:889:889) (916:916:916)) + (PORT datad (222:222:222) (282:282:282)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (346:346:346)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (318:318:318) (325:325:325)) + (PORT datad (304:304:304) (306:306:306)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (315:315:315)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (308:308:308) (318:318:318)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1136:1136:1136) (1120:1120:1120)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1133:1133:1133) (1116:1116:1116)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (295:295:295)) + (PORT datab (229:229:229) (280:280:280)) + (PORT datad (207:207:207) (240:240:240)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (591:591:591)) + (PORT datab (1063:1063:1063) (1050:1050:1050)) + (PORT datad (582:582:582) (589:589:589)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT asdata (1104:1104:1104) (1087:1087:1087)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT asdata (1108:1108:1108) (1092:1092:1092)) + (PORT ena (1154:1154:1154) (1142:1142:1142)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (421:421:421)) + (PORT datab (544:544:544) (554:554:554)) + (PORT datad (199:199:199) (257:257:257)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1381:1381:1381) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (873:873:873) (865:865:865)) + (PORT ena (1109:1109:1109) (1074:1074:1074)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (874:874:874) (867:867:867)) + (PORT ena (1155:1155:1155) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (444:444:444)) + (PORT datab (612:612:612) (626:626:626)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (595:595:595)) + (PORT datab (856:856:856) (860:860:860)) + (PORT datac (193:193:193) (258:258:258)) + (PORT datad (312:312:312) (313:313:313)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (917:917:917) (924:924:924)) + (PORT ena (1588:1588:1588) (1555:1555:1555)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (918:918:918) (926:926:926)) + (PORT ena (1297:1297:1297) (1275:1275:1275)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (813:813:813) (846:846:846)) + (PORT datab (881:881:881) (934:934:934)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (903:903:903) (902:902:902)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (901:901:901) (899:899:899)) + (PORT ena (1123:1123:1123) (1106:1106:1106)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (640:640:640)) + (PORT datab (372:372:372) (391:391:391)) + (PORT datad (196:196:196) (253:253:253)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (804:804:804) (785:785:785)) + (PORT ena (1295:1295:1295) (1246:1246:1246)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (490:490:490)) + (PORT datad (763:763:763) (747:747:747)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (332:332:332)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (945:945:945) (917:917:917)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) (DELAY (ABSOLUTE (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (220:220:220) (255:255:255)) - (PORT datad (384:384:384) (429:429:429)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datab (800:800:800) (794:794:794)) + (PORT datac (1018:1018:1018) (1017:1017:1017)) + (PORT datad (1076:1076:1076) (1075:1075:1075)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT asdata (1258:1258:1258) (1240:1240:1240)) + (PORT ena (1105:1105:1105) (1078:1078:1078)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (805:805:805)) + (PORT datab (1148:1148:1148) (1158:1158:1158)) + (PORT datad (609:609:609) (629:629:629)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1175:1175:1175) (1170:1170:1170)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (579:579:579) (601:601:601)) + (PORT datac (647:647:647) (676:676:676)) + (PORT datad (197:197:197) (255:255:255)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (361:361:361)) + (PORT datab (883:883:883) (898:898:898)) + (PORT datac (627:627:627) (663:663:663)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -20546,9 +24659,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[4\]) (DELAY (ABSOLUTE - (PORT datac (814:814:814) (813:813:813)) - (PORT datad (1189:1189:1189) (1237:1237:1237)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datab (215:215:215) (256:256:256)) + (PORT datad (489:489:489) (481:481:481)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -20558,10 +24671,10 @@ (INSTANCE z80_\|address_latch_\|Q\[4\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1366:1366:1366)) - (PORT asdata (486:486:486) (513:513:513)) - (PORT clrn (1388:1388:1388) (1359:1359:1359)) - (PORT ena (2037:2037:2037) (2003:2003:2003)) + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT asdata (784:784:784) (765:765:765)) + (PORT clrn (1409:1409:1409) (1380:1380:1380)) + (PORT ena (1969:1969:1969) (1997:1997:1997)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -20576,10 +24689,13 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) (DELAY (ABSOLUTE - (PORT datab (1001:1001:1001) (1026:1026:1026)) - (PORT datac (781:781:781) (888:888:888)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1068:1068:1068) (1057:1057:1057)) + (PORT datab (917:917:917) (925:925:925)) + (PORT datad (183:183:183) (207:207:207)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -20588,71 +24704,12 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) (DELAY (ABSOLUTE - (PORT dataa (833:833:833) (853:853:853)) - (PORT datab (810:810:810) (922:922:922)) - (PORT datac (971:971:971) (998:998:998)) - (PORT datad (617:617:617) (666:666:666)) - (IOPATH dataa combout (307:307:307) (323:323:323)) + (PORT dataa (646:646:646) (680:680:680)) + (PORT datab (1067:1067:1067) (1069:1069:1069)) + (PORT datac (576:576:576) (586:586:586)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (851:851:851) (854:854:854)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1104:1104:1104) (1097:1097:1097)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1130:1130:1130) (1112:1112:1112)) - (PORT ena (1197:1197:1197) (1191:1191:1191)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (296:296:296)) - (PORT datab (636:636:636) (674:674:674)) - (PORT datad (619:619:619) (651:651:651)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -20661,9 +24718,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (1694:1694:1694) (1698:1698:1698)) - (PORT ena (1109:1109:1109) (1075:1075:1075)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (816:816:816) (799:799:799)) + (PORT ena (1297:1297:1297) (1275:1275:1275)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -20677,9 +24734,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (1691:1691:1691) (1694:1694:1694)) - (PORT ena (1094:1094:1094) (1065:1065:1065)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (815:815:815) (801:801:801)) + (PORT ena (1588:1588:1588) (1555:1555:1555)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -20693,9 +24750,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (408:408:408)) - (PORT datab (649:649:649) (657:657:657)) - (PORT datad (611:611:611) (615:615:615)) + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (882:882:882) (936:936:936)) + (PORT datad (785:785:785) (805:805:805)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -20705,12 +24762,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (919:919:919) (935:935:935)) - (PORT ena (1157:1157:1157) (1125:1125:1125)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (634:634:634) (638:638:638)) + (PORT ena (1353:1353:1353) (1319:1319:1319)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -20721,12 +24778,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (919:919:919) (934:934:934)) - (PORT ena (1312:1312:1312) (1275:1275:1275)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (634:634:634) (635:635:635)) + (PORT ena (1145:1145:1145) (1131:1131:1131)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -20737,71 +24794,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) (DELAY (ABSOLUTE - (PORT dataa (599:599:599) (609:609:609)) - (PORT datab (803:803:803) (825:825:825)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1102:1102:1102) (1104:1104:1104)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT asdata (867:867:867) (873:873:873)) - (PORT ena (1330:1330:1330) (1356:1356:1356)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (606:606:606)) - (PORT datab (599:599:599) (614:614:614)) - (PORT datad (542:542:542) (536:536:536)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (1020:1020:1020) (1039:1039:1039)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datad (604:604:604) (622:622:622)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20809,12 +24809,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1371:1371:1371)) - (PORT asdata (492:492:492) (524:524:524)) - (PORT ena (1352:1352:1352) (1323:1323:1323)) + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1330:1330:1330) (1311:1311:1311)) + (PORT ena (1381:1381:1381) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -20823,45 +24823,14 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT asdata (850:850:850) (835:835:835)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (887:887:887)) - (PORT datab (829:829:829) (840:840:840)) - (PORT datad (209:209:209) (248:248:248)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT asdata (662:662:662) (672:672:672)) - (PORT ena (1099:1099:1099) (1089:1089:1089)) + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1341:1341:1341) (1321:1321:1321)) + (PORT ena (1109:1109:1109) (1074:1074:1074)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -20875,11 +24844,24 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) (DELAY (ABSOLUTE - (PORT dataa (255:255:255) (324:324:324)) - (PORT datab (867:867:867) (881:881:881)) - (PORT datad (760:760:760) (732:732:732)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (401:401:401) (436:436:436)) + (PORT datab (1062:1062:1062) (1044:1044:1044)) + (PORT datad (581:581:581) (571:571:571)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT datab (854:854:854) (856:856:856)) + (PORT datad (315:315:315) (318:318:318)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20887,12 +24869,28 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT asdata (866:866:866) (871:871:871)) - (PORT ena (739:739:739) (742:742:742)) + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT asdata (1121:1121:1121) (1091:1091:1091)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT asdata (1120:1120:1120) (1090:1090:1090)) + (PORT ena (1154:1154:1154) (1142:1142:1142)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -20903,12 +24901,128 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) (DELAY (ABSOLUTE - (PORT datab (343:343:343) (368:368:368)) - (PORT datad (197:197:197) (224:224:224)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (383:383:383) (422:422:422)) + (PORT datab (545:545:545) (555:555:555)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1343:1343:1343) (1328:1328:1328)) + (PORT ena (1123:1123:1123) (1106:1106:1106)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (560:560:560) (554:554:554)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (633:633:633)) + (PORT datab (366:366:366) (384:384:384)) + (PORT datad (196:196:196) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (790:790:790) (780:780:780)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1295:1295:1295) (1246:1246:1246)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1342:1342:1342) (1323:1323:1323)) + (PORT ena (1155:1155:1155) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (564:564:564)) + (PORT datab (769:769:769) (765:765:765)) + (PORT datad (591:591:591) (597:597:597)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20919,10 +25033,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) (DELAY (ABSOLUTE - (PORT dataa (750:750:750) (781:781:781)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (322:322:322) (327:327:327)) - (PORT datad (159:159:159) (181:181:181)) + (PORT dataa (593:593:593) (597:597:597)) + (PORT datab (1039:1039:1039) (1014:1014:1014)) + (PORT datac (313:313:313) (320:320:320)) + (PORT datad (542:542:542) (549:549:549)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -20935,11 +25049,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) (DELAY (ABSOLUTE - (PORT dataa (790:790:790) (790:790:790)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datad (765:765:765) (753:753:753)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (348:348:348) (354:354:354)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -20949,13 +25063,13 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) (DELAY (ABSOLUTE - (PORT dataa (1236:1236:1236) (1218:1218:1218)) - (PORT datab (547:547:547) (532:532:532)) - (PORT datac (327:327:327) (336:336:336)) - (PORT datad (1191:1191:1191) (1263:1263:1263)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (597:597:597) (621:621:621)) + (PORT datab (861:861:861) (871:871:871)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1497:1497:1497) (1445:1445:1445)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -20965,9 +25079,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1371:1371:1371)) - (PORT asdata (636:636:636) (642:642:642)) - (PORT ena (739:739:739) (742:742:742)) + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT asdata (1126:1126:1126) (1121:1121:1121)) + (PORT ena (1105:1105:1105) (1078:1078:1078)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -20981,34 +25095,24 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datab (216:216:216) (260:260:260)) - (PORT datad (1172:1172:1172) (1123:1123:1123)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1092:1092:1092) (1090:1090:1090)) + (PORT datab (1149:1149:1149) (1158:1158:1158)) + (PORT datad (610:610:610) (629:629:629)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (177:177:177) (198:198:198)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1371:1371:1371)) + (PORT clk (1354:1354:1354) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) + (PORT ena (735:735:735) (733:733:733)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -21022,11 +25126,11 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) (DELAY (ABSOLUTE - (PORT dataa (358:358:358) (360:360:360)) - (PORT datac (364:364:364) (370:370:370)) - (PORT datad (200:200:200) (258:258:258)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (208:208:208) (249:249:249)) + (PORT datac (562:562:562) (576:576:576)) + (PORT datad (199:199:199) (257:257:257)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -21036,12 +25140,12 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) (DELAY (ABSOLUTE - (PORT dataa (1181:1181:1181) (1218:1218:1218)) - (PORT datab (561:561:561) (564:564:564)) - (PORT datac (526:526:526) (516:516:516)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (609:609:609) (601:601:601)) + (PORT datab (1245:1245:1245) (1193:1193:1193)) + (PORT datac (174:174:174) (204:204:204)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -21052,19 +25156,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[5\]) (DELAY (ABSOLUTE - (PORT datac (582:582:582) (592:592:592)) - (PORT datad (1190:1190:1190) (1242:1242:1242)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (177:177:177) (198:198:198)) + (PORT datac (606:606:606) (623:623:623)) + (PORT datad (770:770:770) (749:749:749)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -21074,10 +25168,10 @@ (INSTANCE z80_\|address_latch_\|Q\[5\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1366:1366:1366)) + (PORT clk (1345:1345:1345) (1363:1363:1363)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1359:1359:1359)) - (PORT ena (2037:2037:2037) (2003:2003:2003)) + (PORT clrn (1400:1400:1400) (1370:1370:1370)) + (PORT ena (1981:1981:1981) (2010:2010:2010)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -21089,15 +25183,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) (DELAY (ABSOLUTE - (PORT dataa (567:567:567) (602:602:602)) - (PORT datab (1041:1041:1041) (1028:1028:1028)) - (PORT datac (169:169:169) (209:209:209)) - (PORT datad (996:996:996) (976:976:976)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (843:843:843) (881:881:881)) + (PORT datab (1064:1064:1064) (1061:1061:1061)) + (PORT datac (886:886:886) (910:910:910)) + (PORT datad (335:335:335) (347:347:347)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -21108,10 +25202,10 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) (DELAY (ABSOLUTE - (PORT dataa (834:834:834) (854:854:854)) - (PORT datab (189:189:189) (226:226:226)) - (PORT datac (562:562:562) (594:594:594)) - (PORT datad (799:799:799) (816:816:816)) + (PORT dataa (604:604:604) (619:619:619)) + (PORT datab (1066:1066:1066) (1068:1068:1068)) + (PORT datac (751:751:751) (759:759:759)) + (PORT datad (564:564:564) (573:573:573)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -21119,16 +25213,449 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1175:1175:1175) (1170:1170:1170)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1549:1549:1549) (1512:1512:1512)) + (PORT ena (1588:1588:1588) (1555:1555:1555)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1237:1237:1237) (1208:1208:1208)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1297:1297:1297) (1275:1275:1275)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (843:843:843)) + (PORT datab (882:882:882) (933:933:933)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1744:1744:1744) (1690:1690:1690)) + (PORT ena (1353:1353:1353) (1319:1319:1319)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1742:1742:1742) (1687:1687:1687)) + (PORT ena (1145:1145:1145) (1131:1131:1131)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (1017:1017:1017) (1038:1038:1038)) + (PORT datab (220:220:220) (289:289:289)) + (PORT datad (601:601:601) (620:620:620)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1991:1991:1991) (1931:1931:1931)) + (PORT ena (1132:1132:1132) (1112:1112:1112)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (971:971:971) (951:951:951)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (420:420:420)) + (PORT datab (585:585:585) (612:612:612)) + (PORT datad (346:346:346) (387:387:387)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1342:1342:1342) (1311:1311:1311)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (679:679:679)) + (PORT datab (881:881:881) (880:880:880)) + (PORT datac (813:813:813) (804:804:804)) + (PORT datad (564:564:564) (571:571:571)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1992:1992:1992) (1930:1930:1930)) + (PORT ena (1380:1380:1380) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1208:1208:1208) (1166:1166:1166)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1155:1155:1155) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1485:1485:1485) (1445:1445:1445)) + (PORT ena (1109:1109:1109) (1074:1074:1074)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (444:444:444)) + (PORT datab (220:220:220) (289:289:289)) + (PORT datad (586:586:586) (594:594:594)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT datab (1303:1303:1303) (1285:1285:1285)) + (PORT datad (522:522:522) (515:515:515)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT asdata (1242:1242:1242) (1213:1213:1213)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT asdata (1317:1317:1317) (1303:1303:1303)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (426:426:426)) + (PORT datab (537:537:537) (544:544:544)) + (PORT datad (773:773:773) (790:790:790)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (357:357:357)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (736:736:736) (706:706:706)) + (PORT datad (717:717:717) (689:689:689)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (577:577:577)) + (PORT datab (620:620:620) (634:634:634)) + (PORT datac (1289:1289:1289) (1259:1259:1259)) + (PORT datad (554:554:554) (550:550:550)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT asdata (900:900:900) (912:912:912)) + (PORT ena (1105:1105:1105) (1078:1078:1078)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1220:1220:1220)) + (PORT datab (1145:1145:1145) (1153:1153:1153)) + (PORT datad (604:604:604) (628:628:628)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (634:634:634) (641:641:641)) + (PORT datac (611:611:611) (663:663:663)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) (DELAY (ABSOLUTE - (PORT dataa (570:570:570) (569:569:569)) - (PORT datab (1235:1235:1235) (1188:1188:1188)) - (PORT datac (540:540:540) (530:530:530)) - (PORT datad (1303:1303:1303) (1369:1369:1369)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT dataa (654:654:654) (695:695:695)) + (PORT datab (598:598:598) (620:620:620)) + (PORT datac (853:853:853) (867:867:867)) + (PORT datad (555:555:555) (576:576:576)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -21140,9 +25667,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[6\]) (DELAY (ABSOLUTE - (PORT datac (805:805:805) (800:800:800)) - (PORT datad (1126:1126:1126) (1186:1186:1186)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datac (606:606:606) (624:624:624)) + (PORT datad (759:759:759) (749:749:749)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -21152,10 +25679,10 @@ (INSTANCE z80_\|address_latch_\|Q\[6\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) + (PORT clk (1345:1345:1345) (1363:1363:1363)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1374:1374:1374)) - (PORT ena (2403:2403:2403) (2395:2395:2395)) + (PORT clrn (1400:1400:1400) (1370:1370:1370)) + (PORT ena (1981:1981:1981) (2010:2010:2010)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -21167,15 +25694,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~2) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) (DELAY (ABSOLUTE - (PORT dataa (1351:1351:1351) (1385:1385:1385)) - (PORT datab (1272:1272:1272) (1274:1274:1274)) - (PORT datac (582:582:582) (608:608:608)) - (PORT datad (556:556:556) (564:564:564)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) + (PORT dataa (587:587:587) (600:600:600)) + (PORT datab (583:583:583) (601:601:601)) + (PORT datac (749:749:749) (757:757:757)) + (PORT datad (1076:1076:1076) (1064:1064:1064)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (312:312:312)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -21186,10 +25713,10 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) (DELAY (ABSOLUTE - (PORT dataa (595:595:595) (595:595:595)) - (PORT datab (188:188:188) (226:226:226)) - (PORT datac (805:805:805) (822:822:822)) - (PORT datad (799:799:799) (816:816:816)) + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (1063:1063:1063) (1063:1063:1063)) + (PORT datac (578:578:578) (590:590:590)) + (PORT datad (565:565:565) (573:573:573)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -21202,35 +25729,25 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) (DELAY (ABSOLUTE - (PORT datac (834:834:834) (863:863:863)) - (PORT datad (567:567:567) (557:557:557)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (397:397:397) (459:459:459)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1132:1132:1132) (1127:1127:1127)) - (PORT ena (1197:1197:1197) (1191:1191:1191)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]\~feeder) + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) (DELAY (ABSOLUTE - (PORT datad (811:811:811) (808:808:808)) + (PORT dataa (649:649:649) (686:686:686)) + (PORT datab (886:886:886) (899:899:899)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (573:573:573) (580:580:580)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -21240,40 +25757,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1104:1104:1104) (1097:1097:1097)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (664:664:664) (690:690:690)) - (PORT datab (636:636:636) (673:673:673)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (1397:1397:1397) (1407:1407:1407)) - (PORT ena (1109:1109:1109) (1075:1075:1075)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1115:1115:1115) (1112:1112:1112)) + (PORT ena (1353:1353:1353) (1319:1319:1319)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -21282,14 +25768,61 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1114:1114:1114) (1114:1114:1114)) + (PORT ena (1145:1145:1145) (1131:1131:1131)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1038:1038:1038)) + (PORT datab (221:221:221) (291:291:291)) + (PORT datad (602:602:602) (623:623:623)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (1397:1397:1397) (1405:1405:1405)) - (PORT ena (1094:1094:1094) (1065:1065:1065)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1299:1299:1299) (1274:1274:1274)) + (PORT ena (1588:1588:1588) (1555:1555:1555)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1299:1299:1299) (1276:1276:1276)) + (PORT ena (1297:1297:1297) (1275:1275:1275)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -21303,11 +25836,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) (DELAY (ABSOLUTE - (PORT dataa (359:359:359) (405:405:405)) - (PORT datab (649:649:649) (655:655:655)) - (PORT datad (607:607:607) (612:612:612)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (814:814:814) (848:848:848)) + (PORT datab (881:881:881) (927:927:927)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -21318,9 +25851,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT asdata (1392:1392:1392) (1382:1382:1382)) - (PORT ena (735:735:735) (733:733:733)) + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1782:1782:1782) (1748:1748:1748)) + (PORT ena (1132:1132:1132) (1112:1112:1112)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -21329,71 +25862,24 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1496:1496:1496) (1460:1460:1460)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT asdata (1392:1392:1392) (1382:1382:1382)) - (PORT ena (1355:1355:1355) (1327:1327:1327)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (317:317:317)) - (PORT datab (637:637:637) (681:681:681)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1370:1370:1370)) - (PORT asdata (632:632:632) (653:653:653)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (573:573:573) (580:580:580)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) + (PORT clk (1349:1349:1349) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1312:1312:1312) (1275:1275:1275)) + (PORT ena (744:744:744) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -21404,12 +25890,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) (DELAY (ABSOLUTE - (PORT dataa (835:835:835) (839:839:839)) - (PORT datab (324:324:324) (345:345:345)) - (PORT datad (573:573:573) (596:596:596)) + (PORT dataa (396:396:396) (419:419:419)) + (PORT datab (585:585:585) (612:612:612)) + (PORT datad (342:342:342) (382:382:382)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -21419,17 +25905,33 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1332:1332:1332) (1366:1366:1366)) + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1781:1781:1781) (1748:1748:1748)) + (PORT ena (1380:1380:1380) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1795:1795:1795) (1766:1766:1766)) + (PORT ena (1155:1155:1155) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -21438,9 +25940,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT asdata (627:627:627) (639:639:639)) - (PORT ena (1099:1099:1099) (1089:1089:1089)) + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1795:1795:1795) (1766:1766:1766)) + (PORT ena (1109:1109:1109) (1074:1074:1074)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -21454,9 +25956,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) (DELAY (ABSOLUTE - (PORT dataa (250:250:250) (316:316:316)) - (PORT datab (222:222:222) (292:292:292)) - (PORT datad (547:547:547) (548:548:548)) + (PORT dataa (401:401:401) (436:436:436)) + (PORT datab (220:220:220) (287:287:287)) + (PORT datad (587:587:587) (591:591:591)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -21465,13 +25967,42 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1370:1370:1370)) - (PORT asdata (634:634:634) (651:651:651)) - (PORT ena (1341:1341:1341) (1293:1293:1293)) + (PORT datab (1303:1303:1303) (1287:1287:1287)) + (PORT datad (543:543:543) (535:535:535)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT asdata (1602:1602:1602) (1574:1574:1574)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT asdata (1600:1600:1600) (1576:1576:1576)) + (PORT ena (1154:1154:1154) (1142:1142:1142)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -21482,12 +26013,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) (DELAY (ABSOLUTE - (PORT dataa (321:321:321) (337:337:337)) - (PORT datad (582:582:582) (570:570:570)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (381:381:381) (422:422:422)) + (PORT datab (544:544:544) (553:553:553)) + (PORT datad (197:197:197) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -21498,14 +26031,14 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT asdata (1619:1619:1619) (1614:1614:1614)) - (PORT ena (716:716:716) (714:714:714)) + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1342:1342:1342) (1311:1311:1311)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -21514,12 +26047,13 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) (DELAY (ABSOLUTE - (PORT dataa (554:554:554) (553:553:553)) - (PORT datab (232:232:232) (278:278:278)) - (PORT datad (568:568:568) (564:564:564)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (594:594:594) (648:648:648)) + (PORT datab (881:881:881) (883:883:883)) + (PORT datac (778:778:778) (757:757:757)) + (PORT datad (562:562:562) (569:569:569)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -21529,10 +26063,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) (DELAY (ABSOLUTE - (PORT dataa (321:321:321) (329:329:329)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (517:517:517) (501:501:501)) + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (462:462:462) (448:448:448)) + (PORT datad (159:159:159) (181:181:181)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -21545,11 +26079,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) (DELAY (ABSOLUTE - (PORT datab (564:564:564) (558:558:558)) - (PORT datac (547:547:547) (539:539:539)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (340:340:340) (346:346:346)) + (PORT datad (532:532:532) (520:520:520)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -21559,73 +26093,12 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) (DELAY (ABSOLUTE - (PORT dataa (1189:1189:1189) (1249:1249:1249)) - (PORT datab (1490:1490:1490) (1456:1456:1456)) - (PORT datac (560:560:560) (559:559:559)) - (PORT datad (303:303:303) (310:310:310)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1371:1371:1371)) - (PORT asdata (607:607:607) (609:609:609)) - (PORT ena (739:739:739) (742:742:742)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (616:616:616)) - (PORT datab (220:220:220) (266:266:266)) - (PORT datad (1174:1174:1174) (1126:1126:1126)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (342:342:342)) - (PORT datac (364:364:364) (369:369:369)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (616:616:616) (641:641:641)) + (PORT datab (615:615:615) (627:627:627)) + (PORT datac (1288:1288:1288) (1258:1258:1258)) + (PORT datad (553:553:553) (552:552:552)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -21633,51 +26106,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1182:1182:1182) (1215:1215:1215)) - (PORT datab (186:186:186) (222:222:222)) - (PORT datac (526:526:526) (515:515:515)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT datac (567:567:567) (582:582:582)) - (PORT datad (1193:1193:1193) (1243:1243:1243)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (176:176:176) (197:197:197)) + (PORT dataa (1379:1379:1379) (1380:1380:1380)) + (PORT datab (1534:1534:1534) (1526:1526:1526)) + (PORT datac (807:807:807) (810:810:810)) + (PORT datad (1078:1078:1078) (1071:1071:1071)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) + (INSTANCE z80_\|interrupts_\|im2) (DELAY (ABSOLUTE (PORT clk (1345:1345:1345) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1359:1359:1359)) - (PORT ena (2037:2037:2037) (2003:2003:2003)) + (PORT clrn (1390:1390:1390) (1361:1361:1361)) + (PORT ena (1156:1156:1156) (1147:1147:1147)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -21689,671 +26140,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (INSTANCE z80_\|execute_\|ctl_mRead\~12) (DELAY (ABSOLUTE - (PORT datac (869:869:869) (878:878:878)) - (PORT datad (1124:1124:1124) (1184:1184:1184)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1374:1374:1374)) - (PORT ena (2403:2403:2403) (2395:2395:2395)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (253:253:253)) - (PORT datab (1002:1002:1002) (1027:1027:1027)) - (PORT datac (599:599:599) (654:654:654)) - (PORT datad (358:358:358) (398:398:398)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (840:840:840) (825:825:825)) - (PORT datac (1527:1527:1527) (1606:1606:1606)) - (PORT datad (343:343:343) (360:360:360)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1560:1560:1560) (1549:1549:1549)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1560:1560:1560) (1551:1551:1551)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (427:427:427)) - (PORT datab (399:399:399) (417:417:417)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (849:849:849) (838:838:838)) - (PORT ena (1148:1148:1148) (1135:1135:1135)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1077:1077:1077) (1068:1068:1068)) - (PORT datab (1735:1735:1735) (1740:1740:1740)) - (PORT datad (1513:1513:1513) (1488:1488:1488)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (899:899:899) (900:900:900)) - (PORT ena (897:897:897) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (898:898:898) (904:904:904)) - (PORT ena (882:882:882) (874:874:874)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (427:427:427)) - (PORT datab (385:385:385) (414:414:414)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1412:1412:1412) (1393:1393:1393)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1220:1220:1220) (1189:1189:1189)) - (PORT datab (1110:1110:1110) (1138:1138:1138)) - (PORT datad (365:365:365) (365:365:365)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1327:1327:1327) (1302:1302:1302)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (1065:1065:1065) (1037:1037:1037)) - (PORT ena (1311:1311:1311) (1323:1323:1323)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (453:453:453)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (611:611:611) (627:627:627)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1129:1129:1129) (1117:1117:1117)) - (PORT ena (1138:1138:1138) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1129:1129:1129) (1114:1114:1114)) - (PORT ena (1108:1108:1108) (1069:1069:1069)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (605:605:605) (610:610:610)) - (PORT datad (580:580:580) (572:572:572)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (588:588:588)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (295:295:295) (306:306:306)) - (PORT datad (525:525:525) (518:518:518)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT asdata (1336:1336:1336) (1318:1318:1318)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT asdata (1336:1336:1336) (1316:1316:1316)) - (PORT ena (930:930:930) (921:921:921)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (873:873:873)) - (PORT datab (220:220:220) (288:288:288)) - (PORT datad (209:209:209) (239:239:239)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (595:595:595)) - (PORT datab (345:345:345) (354:354:354)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (741:741:741) (742:742:742)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (553:553:553)) - (PORT datab (1829:1829:1829) (1902:1902:1902)) - (PORT datac (498:498:498) (491:491:491)) - (PORT datad (532:532:532) (518:518:518)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (821:821:821)) - (PORT datab (811:811:811) (806:806:806)) - (PORT datac (1144:1144:1144) (1146:1146:1146)) - (PORT datad (1058:1058:1058) (1032:1032:1032)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1037:1037:1037) (1027:1027:1027)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (553:553:553) (535:535:535)) - (PORT datad (203:203:203) (243:243:243)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1058:1058:1058)) - (PORT datab (795:795:795) (832:832:832)) - (PORT datac (1080:1080:1080) (1140:1140:1140)) - (PORT datad (971:971:971) (990:990:990)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (744:744:744)) - (PORT datab (844:844:844) (869:869:869)) - (PORT datac (1079:1079:1079) (1140:1140:1140)) - (PORT datad (971:971:971) (989:989:989)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (748:748:748)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (157:157:157) (187:187:187)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1177:1177:1177)) - (PORT datac (805:805:805) (795:795:795)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (1416:1416:1416) (1458:1458:1458)) - (PORT datac (1031:1031:1031) (1029:1029:1029)) - (PORT datad (1209:1209:1209) (1167:1167:1167)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (981:981:981)) - (PORT datab (847:847:847) (839:839:839)) - (PORT datac (844:844:844) (894:894:894)) - (PORT datad (210:210:210) (277:277:277)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (806:806:806)) - (PORT datab (571:571:571) (562:562:562)) - (PORT datac (761:761:761) (754:754:754)) - (PORT datad (771:771:771) (752:752:752)) + (PORT dataa (325:325:325) (451:451:451)) + (PORT datac (1130:1130:1130) (1175:1175:1175)) + (PORT datad (250:250:250) (317:317:317)) (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (411:411:411)) - (PORT datab (1007:1007:1007) (978:978:978)) - (PORT datac (722:722:722) (702:702:702)) - (PORT datad (214:214:214) (248:248:248)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1427:1427:1427) (1470:1470:1470)) - (PORT datab (942:942:942) (976:976:976)) - (PORT datac (759:759:759) (754:754:754)) - (PORT datad (1689:1689:1689) (1636:1636:1636)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (761:761:761) (751:751:751)) - (PORT datab (743:743:743) (751:751:751)) - (PORT datac (774:774:774) (760:760:760)) - (PORT datad (539:539:539) (535:535:535)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (358:358:358)) - (PORT datab (588:588:588) (583:583:583)) - (PORT datad (509:509:509) (493:493:493)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (594:594:594)) - (PORT datab (1265:1265:1265) (1253:1253:1253)) - (PORT datac (1006:1006:1006) (1014:1014:1014)) - (PORT datad (1011:1011:1011) (982:982:982)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (229:229:229)) - (PORT datab (212:212:212) (253:253:253)) - (PORT datac (831:831:831) (851:851:851)) - (PORT datad (202:202:202) (242:242:242)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1543:1543:1543) (1526:1526:1526)) - (PORT datab (1031:1031:1031) (1014:1014:1014)) - (PORT datac (1032:1032:1032) (1052:1052:1052)) - (PORT datad (2623:2623:2623) (2595:2595:2595)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22361,419 +26154,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) (DELAY (ABSOLUTE - (PORT dataa (1509:1509:1509) (1483:1483:1483)) - (PORT datab (943:943:943) (977:977:977)) - (PORT datac (721:721:721) (696:696:696)) - (PORT datad (1646:1646:1646) (1632:1632:1632)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1430:1430:1430) (1476:1476:1476)) - (PORT datab (569:569:569) (573:573:573)) - (PORT datac (756:756:756) (750:750:750)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (635:635:635)) - (PORT datab (756:756:756) (747:747:747)) - (PORT datac (356:356:356) (378:378:378)) - (PORT datad (783:783:783) (782:782:782)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (765:765:765) (771:771:771)) - (PORT datab (824:824:824) (829:829:829)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (211:211:211) (245:245:245)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1067:1067:1067)) - (PORT datab (1112:1112:1112) (1121:1121:1121)) - (PORT datac (769:769:769) (771:771:771)) - (PORT datad (996:996:996) (997:997:997)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1538:1538:1538) (1567:1567:1567)) - (PORT datab (1673:1673:1673) (1649:1649:1649)) - (PORT datac (746:746:746) (728:728:728)) - (PORT datad (1266:1266:1266) (1263:1263:1263)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (624:624:624)) - (PORT datab (619:619:619) (617:617:617)) - (PORT datac (1134:1134:1134) (1073:1073:1073)) - (PORT datad (790:790:790) (805:805:805)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (2073:2073:2073) (2051:2051:2051)) - (PORT datad (553:553:553) (551:551:551)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (649:649:649)) - (PORT datab (208:208:208) (242:242:242)) - (PORT datac (761:761:761) (758:758:758)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1431:1431:1431) (1471:1471:1471)) - (PORT datab (574:574:574) (567:567:567)) - (PORT datac (755:755:755) (750:750:750)) - (PORT datad (1685:1685:1685) (1634:1634:1634)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datab (600:600:600) (615:615:615)) - (PORT datac (747:747:747) (738:738:738)) - (PORT datad (594:594:594) (605:605:605)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) - (DELAY - (ABSOLUTE - (PORT datac (760:760:760) (760:760:760)) - (PORT datad (184:184:184) (212:212:212)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (843:843:843) (850:850:850)) - (PORT datab (814:814:814) (820:820:820)) - (PORT datac (1526:1526:1526) (1528:1528:1528)) - (PORT datad (1049:1049:1049) (1064:1064:1064)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (829:829:829) (834:834:834)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (753:753:753) (754:754:754)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (501:501:501) (510:510:510)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1374:1374:1374)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1095:1095:1095)) - (PORT datab (789:789:789) (801:801:801)) - (PORT datad (984:984:984) (959:959:959)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (319:319:319) (330:330:330)) - (PORT datab (808:808:808) (782:782:782)) - (PORT datac (1385:1385:1385) (1427:1427:1427)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (860:860:860)) - (PORT datab (835:835:835) (865:865:865)) - (PORT datac (944:944:944) (914:914:914)) - (PORT datad (945:945:945) (906:906:906)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (813:813:813)) - (PORT datab (1280:1280:1280) (1266:1266:1266)) - (PORT datac (195:195:195) (262:262:262)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1072:1072:1072) (1060:1060:1060)) - (PORT datab (782:782:782) (788:788:788)) - (PORT datac (917:917:917) (917:917:917)) - (PORT datad (978:978:978) (986:986:986)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) - (DELAY - (ABSOLUTE - (PORT dataa (954:954:954) (934:934:934)) - (PORT datab (767:767:767) (756:756:756)) - (PORT datac (991:991:991) (999:999:999)) - (PORT datad (973:973:973) (981:981:981)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (837:837:837)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (1004:1004:1004) (985:985:985)) - (PORT datad (1318:1318:1318) (1329:1329:1329)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (628:628:628)) - (PORT datab (638:638:638) (651:651:651)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (156:156:156) (177:177:177)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1313:1313:1313) (1337:1337:1337)) - (PORT datab (1546:1546:1546) (1536:1536:1536)) - (PORT datac (1495:1495:1495) (1496:1496:1496)) - (PORT datad (556:556:556) (561:561:561)) + (PORT dataa (326:326:326) (453:453:453)) + (PORT datab (663:663:663) (674:674:674)) + (PORT datac (173:173:173) (204:204:204)) + (PORT datad (1201:1201:1201) (1270:1270:1270)) (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (INSTANCE z80_\|alu_control_\|db\[7\]\~17) (DELAY (ABSOLUTE - (PORT dataa (803:803:803) (812:812:812)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (553:553:553) (562:562:562)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1362:1362:1362) (1406:1406:1406)) - (PORT datab (1335:1335:1335) (1327:1327:1327)) - (PORT datac (1062:1062:1062) (1072:1072:1072)) - (PORT datad (322:322:322) (322:322:322)) - (IOPATH dataa combout (287:287:287) (289:289:289)) + (PORT dataa (813:813:813) (813:813:813)) + (PORT datab (862:862:862) (865:865:865)) + (PORT datac (573:573:573) (605:605:605)) + (PORT datad (589:589:589) (590:590:590)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -22782,143 +26186,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (INSTANCE z80_\|alu_control_\|db\[7\]\~16) (DELAY (ABSOLUTE - (PORT dataa (1136:1136:1136) (1169:1169:1169)) - (PORT datab (743:743:743) (723:723:723)) - (PORT datac (1466:1466:1466) (1441:1441:1441)) - (PORT datad (1649:1649:1649) (1636:1636:1636)) + (PORT dataa (778:778:778) (765:765:765)) + (PORT datab (785:785:785) (798:798:798)) + (PORT datac (832:832:832) (840:840:840)) + (PORT datad (587:587:587) (633:633:633)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (224:224:224)) + (PORT datab (219:219:219) (262:262:262)) + (PORT datac (584:584:584) (609:609:609)) + (PORT datad (574:574:574) (563:563:563)) (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (494:494:494) (484:484:484)) - (PORT datad (570:570:570) (571:571:571)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) - (DELAY - (ABSOLUTE - (PORT dataa (802:802:802) (799:799:799)) - (PORT datab (637:637:637) (663:663:663)) - (PORT datac (551:551:551) (584:584:584)) - (PORT datad (176:176:176) (197:197:197)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1073:1073:1073)) - (PORT datab (1347:1347:1347) (1388:1388:1388)) - (PORT datac (1813:1813:1813) (1841:1841:1841)) - (PORT datad (1090:1090:1090) (1133:1133:1133)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (849:849:849)) - (PORT datab (204:204:204) (241:241:241)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (877:877:877) (914:914:914)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1451:1451:1451)) - (PORT datab (799:799:799) (819:819:819)) - (PORT datac (1267:1267:1267) (1272:1272:1272)) - (PORT datad (533:533:533) (529:529:529)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) - (DELAY - (ABSOLUTE - (PORT dataa (843:843:843) (852:852:852)) - (PORT datab (758:758:758) (769:769:769)) - (PORT datac (1050:1050:1050) (1068:1068:1068)) - (PORT datad (1064:1064:1064) (1081:1081:1081)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) - (DELAY - (ABSOLUTE - (PORT dataa (843:843:843) (853:853:853)) - (PORT datab (1058:1058:1058) (1086:1086:1086)) - (PORT datac (1050:1050:1050) (1068:1068:1068)) - (PORT datad (1089:1089:1089) (1139:1139:1139)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) - (DELAY - (ABSOLUTE - (PORT dataa (900:900:900) (950:950:950)) - (PORT datab (848:848:848) (858:858:858)) - (PORT datac (814:814:814) (816:816:816)) - (PORT datad (2194:2194:2194) (2179:2179:2179)) - (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (662:662:662)) + (PORT datab (825:825:825) (837:837:837)) + (PORT datac (791:791:791) (766:766:766)) + (PORT datad (184:184:184) (210:210:210)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22926,230 +26234,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (793:793:793) (767:767:767)) - (PORT datac (774:774:774) (801:801:801)) - (PORT datad (1498:1498:1498) (1483:1483:1483)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (608:608:608)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (505:505:505) (495:495:495)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (917:917:917) (964:964:964)) - (PORT datab (1239:1239:1239) (1220:1220:1220)) - (PORT datac (1086:1086:1086) (1109:1109:1109)) - (PORT datad (1217:1217:1217) (1215:1215:1215)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (967:967:967)) - (PORT datab (1241:1241:1241) (1221:1221:1221)) - (PORT datac (796:796:796) (814:814:814)) - (PORT datad (2039:2039:2039) (2048:2048:2048)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (550:550:550)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (177:177:177) (197:197:197)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (870:870:870) (891:891:891)) - (PORT datac (163:163:163) (198:198:198)) - (PORT datad (567:567:567) (570:570:570)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) - (DELAY - (ABSOLUTE - (PORT datab (1038:1038:1038) (1027:1027:1027)) - (PORT datac (1119:1119:1119) (1067:1067:1067)) - (PORT datad (742:742:742) (742:742:742)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1011:1011:1011) (992:992:992)) - (PORT datab (805:805:805) (823:823:823)) - (PORT datac (487:487:487) (471:471:471)) - (PORT datad (997:997:997) (982:982:982)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (628:628:628) (649:649:649)) - (PORT datac (736:736:736) (729:729:729)) + (PORT dataa (1159:1159:1159) (1215:1215:1215)) + (PORT datab (793:793:793) (816:816:816)) + (PORT datac (563:563:563) (574:574:574)) (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (592:592:592)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datac (1886:1886:1886) (1816:1816:1816)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (816:816:816)) - (PORT datab (190:190:190) (227:227:227)) - (PORT datad (511:511:511) (495:495:495)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (1448:1448:1448) (1410:1410:1410)) - (PORT datab (1308:1308:1308) (1314:1314:1314)) - (PORT datac (563:563:563) (561:561:561)) - (PORT datad (1491:1491:1491) (1480:1480:1480)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (644:644:644)) - (PORT datab (985:985:985) (985:985:985)) - (PORT datac (1175:1175:1175) (1141:1141:1141)) - (PORT datad (1194:1194:1194) (1193:1193:1193)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (1053:1053:1053) (1059:1059:1059)) - (PORT datac (600:600:600) (624:624:624)) - (PORT datad (831:831:831) (840:840:840)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) (DELAY (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT clk (1331:1331:1331) (1350:1350:1350)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) + (PORT ena (765:765:765) (779:779:779)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -23160,149 +26266,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~9) + (INSTANCE z80_\|pla_decode_\|Equal62\~3) (DELAY (ABSOLUTE - (PORT dataa (995:995:995) (973:973:973)) - (PORT datab (231:231:231) (303:303:303)) - (PORT datac (813:813:813) (803:803:803)) - (PORT datad (635:635:635) (683:683:683)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1174:1174:1174)) - (PORT datab (654:654:654) (678:678:678)) - (PORT datac (626:626:626) (652:652:652)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (871:871:871)) - (PORT datac (1391:1391:1391) (1436:1436:1436)) - (PORT datad (161:161:161) (181:181:181)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (571:571:571) (595:595:595)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1356:1356:1356) (1296:1296:1296)) - (PORT datad (576:576:576) (588:588:588)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (246:246:246)) - (PORT datab (322:322:322) (330:330:330)) - (PORT datac (762:762:762) (748:748:748)) - (PORT datad (767:767:767) (761:761:761)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1310:1310:1310) (1299:1299:1299)) - (PORT datab (198:198:198) (231:231:231)) - (PORT datac (586:586:586) (604:604:604)) - (PORT datad (985:985:985) (949:949:949)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (801:801:801)) - (PORT datac (156:156:156) (186:186:186)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1140:1140:1140) (1128:1128:1128)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1273:1273:1273)) - (PORT datab (626:626:626) (677:677:677)) - (PORT datac (947:947:947) (936:936:936)) - (PORT datad (498:498:498) (483:483:483)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (239:239:239)) - (PORT datab (187:187:187) (225:225:225)) - (PORT datac (161:161:161) (196:196:196)) - (PORT datad (164:164:164) (190:190:190)) + (PORT dataa (1352:1352:1352) (1422:1422:1422)) + (PORT datab (1360:1360:1360) (1401:1401:1401)) + (PORT datac (1021:1021:1021) (1041:1041:1041)) + (PORT datad (597:597:597) (607:607:607)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -23312,15 +26282,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) (DELAY (ABSOLUTE - (PORT dataa (744:744:744) (725:725:725)) - (PORT datab (1990:1990:1990) (1992:1992:1992)) - (PORT datac (1467:1467:1467) (1446:1446:1446)) - (PORT datad (1646:1646:1646) (1632:1632:1632)) + (PORT dataa (1042:1042:1042) (1037:1037:1037)) + (PORT datab (694:694:694) (696:696:696)) + (PORT datac (1298:1298:1298) (1313:1313:1313)) + (PORT datad (1097:1097:1097) (1118:1118:1118)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (899:899:899)) + (PORT datab (1077:1077:1077) (1086:1086:1086)) + (PORT datac (682:682:682) (744:744:744)) + (PORT datad (1745:1745:1745) (1842:1842:1842)) (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (717:717:717)) + (PORT datab (1288:1288:1288) (1362:1362:1362)) + (PORT datac (1032:1032:1032) (1024:1024:1024)) + (PORT datad (179:179:179) (212:212:212)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -23328,15 +26330,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) (DELAY (ABSOLUTE - (PORT dataa (1427:1427:1427) (1471:1471:1471)) - (PORT datab (327:327:327) (344:344:344)) - (PORT datac (538:538:538) (540:540:540)) - (PORT datad (989:989:989) (969:969:969)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (604:604:604) (593:593:593)) + (PORT datab (762:762:762) (741:741:741)) + (PORT datac (1037:1037:1037) (1041:1041:1041)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (617:617:617)) + (PORT datab (956:956:956) (977:977:977)) + (PORT datac (527:527:527) (511:511:511)) + (PORT datad (836:836:836) (845:845:845)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (659:659:659)) + (PORT datab (571:571:571) (563:563:563)) + (PORT datac (215:215:215) (282:282:282)) + (PORT datad (166:166:166) (193:193:193)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1037:1037:1037)) + (PORT datab (690:690:690) (692:692:692)) + (PORT datac (837:837:837) (854:854:854)) + (PORT datad (1098:1098:1098) (1095:1095:1095)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -23344,15 +26394,173 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) (DELAY (ABSOLUTE - (PORT dataa (1131:1131:1131) (1163:1163:1163)) - (PORT datab (1008:1008:1008) (975:975:975)) - (PORT datac (759:759:759) (753:753:753)) - (PORT datad (1379:1379:1379) (1425:1425:1425)) - (IOPATH dataa combout (307:307:307) (280:280:280)) + (PORT dataa (1337:1337:1337) (1338:1338:1338)) + (PORT datab (620:620:620) (638:638:638)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (1307:1307:1307) (1301:1301:1301)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1325:1325:1325) (1320:1320:1320)) + (PORT datab (691:691:691) (692:692:692)) + (PORT datac (1053:1053:1053) (1064:1064:1064)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (441:441:441)) + (PORT datab (241:241:241) (316:316:316)) + (PORT datac (206:206:206) (278:278:278)) + (PORT datad (566:566:566) (580:580:580)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (808:808:808)) + (PORT datab (673:673:673) (721:721:721)) + (PORT datad (370:370:370) (403:403:403)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (458:458:458)) + (PORT datab (357:357:357) (410:410:410)) + (PORT datac (611:611:611) (650:650:650)) + (PORT datad (624:624:624) (668:668:668)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (329:329:329)) + (PORT datab (559:559:559) (586:586:586)) + (PORT datac (217:217:217) (297:297:297)) + (PORT datad (344:344:344) (382:382:382)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (536:536:536)) + (PORT datab (840:840:840) (821:821:821)) + (PORT datac (523:523:523) (518:518:518)) + (PORT datad (287:287:287) (291:291:291)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1326:1326:1326) (1322:1322:1322)) + (PORT datab (1427:1427:1427) (1456:1456:1456)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1041:1041:1041) (1036:1036:1036)) + (PORT datab (619:619:619) (638:638:638)) + (PORT datac (838:838:838) (856:856:856)) + (PORT datad (1096:1096:1096) (1095:1095:1095)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (928:928:928)) + (PORT datab (247:247:247) (318:318:318)) + (PORT datac (1050:1050:1050) (1062:1062:1062)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -23360,14 +26568,309 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) (DELAY (ABSOLUTE (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (500:500:500) (496:496:496)) - (IOPATH dataa combout (272:272:272) (269:269:269)) + (PORT datab (691:691:691) (692:692:692)) + (PORT datac (1297:1297:1297) (1289:1289:1289)) + (PORT datad (221:221:221) (282:282:282)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1177:1177:1177) (1162:1162:1162)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (238:238:238)) + (PORT datab (193:193:193) (234:234:234)) + (PORT datac (163:163:163) (198:198:198)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (509:509:509)) + (PORT datab (192:192:192) (232:232:232)) + (PORT datac (160:160:160) (193:193:193)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (754:754:754) (727:727:727)) + (PORT datac (305:305:305) (316:316:316)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (338:338:338)) + (PORT datab (616:616:616) (622:622:622)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1041:1041:1041) (1041:1041:1041)) + (PORT datab (1081:1081:1081) (1091:1091:1091)) + (PORT datac (1297:1297:1297) (1292:1292:1292)) + (PORT datad (1098:1098:1098) (1098:1098:1098)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (888:888:888)) + (PORT datab (694:694:694) (697:697:697)) + (PORT datac (592:592:592) (608:608:608)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (181:181:181) (215:215:215)) + (PORT datac (1280:1280:1280) (1286:1286:1286)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (229:229:229)) + (PORT datab (317:317:317) (327:327:327)) + (PORT datac (1118:1118:1118) (1119:1119:1119)) + (PORT datad (622:622:622) (636:636:636)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (847:847:847)) + (PORT datab (1855:1855:1855) (1877:1877:1877)) + (PORT datac (839:839:839) (893:893:893)) + (PORT datad (786:786:786) (790:790:790)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (402:402:402)) + (PORT datab (1089:1089:1089) (1066:1066:1066)) + (PORT datac (547:547:547) (540:540:540)) + (PORT datad (310:310:310) (323:323:323)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (765:765:765) (773:773:773)) + (PORT datad (312:312:312) (317:317:317)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (253:253:253)) + (PORT datab (200:200:200) (243:243:243)) + (PORT datac (573:573:573) (573:573:573)) + (PORT datad (195:195:195) (234:234:234)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (539:539:539)) + (PORT datab (631:631:631) (626:626:626)) + (PORT datac (528:528:528) (512:512:512)) + (PORT datad (295:295:295) (288:288:288)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (593:593:593)) + (PORT datab (599:599:599) (604:604:604)) + (PORT datac (217:217:217) (285:285:285)) + (PORT datad (360:360:360) (362:362:362)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (614:614:614)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (571:571:571) (575:575:575)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1141:1141:1141) (1119:1119:1119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1518:1518:1518)) + (PORT datab (202:202:202) (237:237:237)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (812:812:812) (852:852:852)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -23376,31 +26879,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) (DELAY (ABSOLUTE - (PORT dataa (512:512:512) (501:501:501)) - (PORT datab (811:811:811) (824:824:824)) - (PORT datac (808:808:808) (810:810:810)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1261:1261:1261) (1248:1248:1248)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (180:180:180) (214:214:214)) - (PORT datad (572:572:572) (559:559:559)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (614:614:614) (674:674:674)) + (PORT datab (615:615:615) (632:632:632)) + (PORT datac (163:163:163) (198:198:198)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -23408,15 +26895,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1006:1006:1006) (1010:1010:1010)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1678:1678:1678) (1708:1708:1708)) + (PORT datab (1857:1857:1857) (1879:1879:1879)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|flags_cond_true) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (590:590:590)) + (PORT datab (1645:1645:1645) (1688:1688:1688)) + (PORT datac (1674:1674:1674) (1728:1728:1728)) + (PORT datad (517:517:517) (529:529:529)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (232:232:232)) + (PORT datab (207:207:207) (252:252:252)) + (PORT datac (530:530:530) (526:526:526)) + (PORT datad (164:164:164) (191:191:191)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -23424,14 +26956,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[0\]\~1) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) (DELAY (ABSOLUTE - (PORT dataa (566:566:566) (570:570:570)) - (PORT datab (233:233:233) (308:308:308)) - (PORT datac (207:207:207) (280:280:280)) - (PORT datad (1030:1030:1030) (1019:1019:1019)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (827:827:827) (822:822:822)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (577:577:577) (585:585:585)) + (PORT datad (1103:1103:1103) (1114:1114:1114)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (593:593:593)) + (PORT datab (868:868:868) (890:890:890)) + (PORT datad (622:622:622) (629:629:629)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (634:634:634)) + (PORT datab (490:490:490) (477:477:477)) + (PORT datac (692:692:692) (663:663:663)) + (PORT datad (1026:1026:1026) (1006:1006:1006)) + (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -23440,264 +27002,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (788:788:788) (793:793:793)) - (PORT datab (196:196:196) (236:236:236)) - (PORT datac (325:325:325) (332:332:332)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1369:1369:1369)) - (PORT asdata (492:492:492) (524:524:524)) - (PORT ena (1595:1595:1595) (1554:1554:1554)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (646:646:646)) - (PORT datab (987:987:987) (987:987:987)) - (PORT datac (1177:1177:1177) (1148:1148:1148)) - (PORT datad (1197:1197:1197) (1201:1201:1201)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (785:785:785)) - (PORT datab (185:185:185) (219:219:219)) - (PORT datad (771:771:771) (761:761:761)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (820:820:820) (836:836:836)) - (PORT datac (537:537:537) (528:528:528)) - (PORT datad (974:974:974) (954:954:954)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (788:788:788) (778:778:778)) - (PORT datab (802:802:802) (808:808:808)) - (PORT datac (603:603:603) (627:627:627)) - (PORT datad (1027:1027:1027) (1018:1018:1018)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (825:825:825) (836:836:836)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1036:1036:1036) (1018:1018:1018)) - (PORT datac (841:841:841) (888:888:888)) - (PORT datad (635:635:635) (686:686:686)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1307:1307:1307) (1294:1294:1294)) - (PORT datab (193:193:193) (232:232:232)) - (PORT datac (583:583:583) (601:601:601)) - (PORT datad (988:988:988) (952:952:952)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (763:763:763) (767:767:767)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1140:1140:1140) (1128:1128:1128)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datab (234:234:234) (308:308:308)) - (PORT datac (206:206:206) (280:280:280)) - (PORT datad (541:541:541) (532:532:532)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (1067:1067:1067) (1050:1050:1050)) - (PORT datac (326:326:326) (330:330:330)) - (PORT datad (172:172:172) (203:203:203)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (200:200:200) (245:245:245)) - (PORT datac (761:761:761) (755:755:755)) - (PORT datad (534:534:534) (530:530:530)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (231:231:231)) - (PORT datab (197:197:197) (241:241:241)) - (PORT datac (288:288:288) (302:302:302)) - (PORT datad (169:169:169) (197:197:197)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (807:807:807)) - (PORT datad (771:771:771) (751:751:751)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (518:518:518) (512:512:512)) - (PORT datac (321:321:321) (328:328:328)) - (PORT datad (536:536:536) (528:528:528)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT dataa (512:512:512) (511:511:511)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (538:538:538) (550:550:550)) + (PORT datad (582:582:582) (583:583:583)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -23705,103 +27018,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) (DELAY (ABSOLUTE - (PORT dataa (355:355:355) (364:364:364)) - (PORT datab (206:206:206) (242:242:242)) - (PORT datac (167:167:167) (203:203:203)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (517:517:517) (514:514:514)) - (PORT datab (348:348:348) (357:357:357)) - (PORT datac (168:168:168) (205:205:205)) - (PORT datad (287:287:287) (292:292:292)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (181:181:181) (218:218:218)) + (PORT datab (236:236:236) (281:281:281)) + (PORT datac (558:558:558) (555:555:555)) + (PORT datad (208:208:208) (250:250:250)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) (DELAY (ABSOLUTE (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1874:1874:1874) (1835:1835:1835)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT datab (1202:1202:1202) (1171:1171:1171)) - (PORT datac (597:597:597) (612:612:612)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (858:858:858)) - (PORT datab (651:651:651) (698:698:698)) - (PORT datac (615:615:615) (660:660:660)) - (PORT datad (993:993:993) (972:972:972)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1093:1093:1093)) - (PORT datab (1019:1019:1019) (1019:1019:1019)) - (PORT datac (1178:1178:1178) (1166:1166:1166)) - (PORT datad (323:323:323) (323:323:323)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1108:1108:1108) (1080:1080:1080)) + (PORT asdata (1730:1730:1730) (1680:1680:1680)) (PORT ena (744:744:744) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -23813,12 +27050,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1108:1108:1108) (1083:1083:1083)) - (PORT ena (860:860:860) (843:843:843)) + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1694:1694:1694) (1639:1639:1639)) + (PORT ena (1132:1132:1132) (1112:1112:1112)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -23829,43 +27066,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~59) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) (DELAY (ABSOLUTE - (PORT dataa (394:394:394) (424:424:424)) - (PORT datab (404:404:404) (418:418:418)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (875:875:875) (870:870:870)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1188:1188:1188)) - (PORT datab (808:808:808) (800:800:800)) - (PORT datad (361:361:361) (367:367:367)) + (PORT dataa (395:395:395) (415:415:415)) + (PORT datab (350:350:350) (401:401:401)) + (PORT datad (558:558:558) (575:575:575)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -23875,116 +27081,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1311:1311:1311) (1323:1323:1323)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (836:836:836) (825:825:825)) - (PORT ena (1327:1327:1327) (1302:1302:1302)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (458:458:458)) - (PORT datab (219:219:219) (286:286:286)) - (PORT datad (611:611:611) (618:618:618)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (832:832:832) (827:827:827)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1108:1108:1108) (1069:1069:1069)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1148:1148:1148) (1141:1141:1141)) - (PORT ena (1138:1138:1138) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (410:410:410)) - (PORT datab (601:601:601) (605:605:605)) - (PORT datad (585:585:585) (577:577:577)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1338:1338:1338) (1306:1306:1306)) - (PORT ena (882:882:882) (874:874:874)) + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1694:1694:1694) (1639:1639:1639)) + (PORT ena (1380:1380:1380) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -23995,12 +27097,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1335:1335:1335) (1303:1303:1303)) - (PORT ena (897:897:897) (877:877:877)) + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1963:1963:1963) (1914:1914:1914)) + (PORT ena (1109:1109:1109) (1074:1074:1074)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -24009,44 +27111,13 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (425:425:425)) - (PORT datab (386:386:386) (416:416:416)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (356:356:356) (356:356:356)) - (PORT datac (530:530:530) (518:518:518)) - (PORT datad (554:554:554) (551:551:551)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1360:1360:1360) (1381:1381:1381)) - (PORT asdata (1566:1566:1566) (1528:1528:1528)) + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (1965:1965:1965) (1916:1916:1916)) (PORT ena (763:763:763) (771:771:771)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -24058,14 +27129,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~15) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) (DELAY (ABSOLUTE - (PORT dataa (1115:1115:1115) (1136:1136:1136)) - (PORT datab (1270:1270:1270) (1283:1283:1283)) - (PORT datad (1734:1734:1734) (1700:1700:1700)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (402:402:402) (440:440:440)) + (PORT datab (612:612:612) (630:630:630)) + (PORT datad (588:588:588) (609:609:609)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -24073,38 +27144,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) (DELAY (ABSOLUTE - (PORT datad (862:862:862) (857:857:857)) + (PORT datab (1303:1303:1303) (1283:1283:1283)) + (PORT datad (541:541:541) (532:532:532)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT asdata (1161:1161:1161) (1151:1151:1151)) - (PORT ena (930:930:930) (921:921:921)) + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (1730:1730:1730) (1679:1679:1679)) + (PORT ena (1123:1123:1123) (1106:1106:1106)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -24115,14 +27173,72 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~58) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) (DELAY (ABSOLUTE - (PORT dataa (359:359:359) (409:409:409)) - (PORT datab (644:644:644) (675:675:675)) - (PORT datad (212:212:212) (243:243:243)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (602:602:602) (628:628:628)) + (PORT datab (882:882:882) (879:879:879)) + (PORT datac (831:831:831) (826:826:826)) + (PORT datad (564:564:564) (571:571:571)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT asdata (1498:1498:1498) (1466:1466:1466)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (764:764:764) (753:753:753)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1154:1154:1154) (1142:1142:1142)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (429:429:429)) + (PORT datab (537:537:537) (543:543:543)) + (PORT datad (544:544:544) (560:560:560)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -24130,13 +27246,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~65) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) (DELAY (ABSOLUTE - (PORT dataa (617:617:617) (633:633:633)) - (PORT datab (593:593:593) (594:594:594)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (305:305:305) (312:312:312)) + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (508:508:508) (497:497:497)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -24146,47 +27262,475 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~66) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (555:555:555) (555:555:555)) - (PORT datab (564:564:564) (585:585:585)) - (PORT datac (1808:1808:1808) (1854:1854:1854)) - (PORT datad (527:527:527) (528:528:528)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datad (1422:1422:1422) (1371:1371:1371)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~11) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT dataa (964:964:964) (930:930:930)) - (PORT datab (1235:1235:1235) (1176:1176:1176)) - (PORT datac (1010:1010:1010) (967:967:967)) - (PORT datad (952:952:952) (908:908:908)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1297:1297:1297) (1275:1275:1275)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1714:1714:1714) (1658:1658:1658)) + (PORT ena (1588:1588:1588) (1555:1555:1555)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~12) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) (DELAY (ABSOLUTE - (PORT dataa (321:321:321) (338:338:338)) - (PORT datab (226:226:226) (280:280:280)) - (PORT datac (1032:1032:1032) (1017:1017:1017)) - (PORT datad (784:784:784) (775:775:775)) + (PORT dataa (221:221:221) (293:293:293)) + (PORT datab (881:881:881) (929:929:929)) + (PORT datad (789:789:789) (804:804:804)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (654:654:654) (660:660:660)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (654:654:654) (660:660:660)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (293:293:293)) + (PORT datab (233:233:233) (286:286:286)) + (PORT datad (213:213:213) (247:247:247)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (643:643:643)) + (PORT datab (590:590:590) (599:599:599)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1254:1254:1254) (1219:1219:1219)) + (PORT datab (577:577:577) (581:581:581)) + (PORT datac (590:590:590) (615:615:615)) + (PORT datad (288:288:288) (293:293:293)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1376:1376:1376) (1382:1382:1382)) + (PORT datab (1533:1533:1533) (1529:1529:1529)) + (PORT datac (1413:1413:1413) (1363:1363:1363)) + (PORT datad (1079:1079:1079) (1074:1074:1074)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (909:909:909)) + (PORT datab (819:819:819) (814:814:814)) + (PORT datac (849:849:849) (861:861:861)) + (PORT datad (819:819:819) (821:821:821)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (640:640:640)) + (PORT datab (1060:1060:1060) (1067:1067:1067)) + (PORT datac (821:821:821) (860:860:860)) + (PORT datad (1088:1088:1088) (1085:1085:1085)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (223:223:223)) + (PORT datab (870:870:870) (873:873:873)) + (PORT datac (599:599:599) (602:602:602)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1209:1209:1209)) + (PORT datab (871:871:871) (867:867:867)) + (PORT datac (1329:1329:1329) (1335:1335:1335)) + (PORT datad (855:855:855) (872:872:872)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (224:224:224)) + (PORT datab (913:913:913) (921:921:921)) + (PORT datac (838:838:838) (837:837:837)) + (PORT datad (199:199:199) (240:240:240)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1565:1565:1565) (1571:1571:1571)) + (PORT datac (827:827:827) (824:824:824)) + (PORT datad (341:341:341) (342:342:342)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (856:856:856) (855:855:855)) + (PORT datad (216:216:216) (246:246:246)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1095:1095:1095) (1096:1096:1096)) + (PORT datab (247:247:247) (312:312:312)) + (PORT datac (223:223:223) (279:279:279)) + (PORT datad (233:233:233) (269:269:269)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (471:471:471)) + (PORT datab (1068:1068:1068) (1086:1086:1086)) + (PORT datac (1069:1069:1069) (1080:1080:1080)) + (PORT datad (615:615:615) (638:638:638)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1361:1361:1361)) + (PORT asdata (616:616:616) (621:621:621)) + (PORT ena (1177:1177:1177) (1162:1162:1162)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (594:594:594)) + (PORT datab (343:343:343) (350:350:350)) + (PORT datad (1055:1055:1055) (1049:1049:1049)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (539:539:539)) + (PORT datab (201:201:201) (234:234:234)) + (PORT datac (1038:1038:1038) (1019:1019:1019)) + (PORT datad (312:312:312) (313:313:313)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1170:1170:1170) (1202:1202:1202)) + (PORT datab (855:855:855) (828:828:828)) + (PORT datac (1037:1037:1037) (1036:1036:1036)) + (PORT datad (873:873:873) (892:892:892)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (896:896:896) (905:905:905)) + (PORT datac (754:754:754) (730:730:730)) + (PORT datad (204:204:204) (245:245:245)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (897:897:897)) + (PORT datac (1538:1538:1538) (1534:1534:1534)) + (PORT datad (1302:1302:1302) (1274:1274:1274)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datac (831:831:831) (829:829:829)) + (PORT datad (219:219:219) (253:253:253)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1095:1095:1095) (1095:1095:1095)) + (PORT datab (248:248:248) (314:314:314)) + (PORT datac (225:225:225) (275:275:275)) + (PORT datad (226:226:226) (263:263:263)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (652:652:652)) + (PORT datab (1068:1068:1068) (1086:1086:1086)) + (PORT datac (566:566:566) (605:605:605)) + (PORT datad (615:615:615) (637:637:637)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1361:1361:1361)) + (PORT asdata (1037:1037:1037) (1004:1004:1004)) + (PORT ena (1177:1177:1177) (1162:1162:1162)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (520:520:520)) + (PORT datab (308:308:308) (328:328:328)) + (PORT datad (1055:1055:1055) (1049:1049:1049)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (640:640:640)) + (PORT datab (335:335:335) (351:351:351)) + (PORT datac (741:741:741) (727:727:727)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -24194,29 +27738,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~5) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (1116:1116:1116) (1176:1176:1176)) - (PORT datab (829:829:829) (817:817:817)) - (PORT datac (624:624:624) (650:650:650)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (765:765:765) (814:814:814)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1384:1384:1384) (1427:1427:1427)) - (PORT datad (1209:1209:1209) (1170:1170:1170)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (551:551:551) (536:536:536)) + (PORT datab (893:893:893) (917:917:917)) + (PORT datac (339:339:339) (363:363:363)) + (PORT datad (797:797:797) (815:815:815)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -24224,55 +27754,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~9) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) (DELAY (ABSOLUTE - (PORT dataa (585:585:585) (607:607:607)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (499:499:499) (485:485:485)) - (PORT datad (778:778:778) (752:752:752)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (835:835:835) (852:852:852)) - (PORT datac (553:553:553) (562:562:562)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1053:1053:1053) (1059:1059:1059)) - (PORT datab (586:586:586) (612:612:612)) - (PORT datac (747:747:747) (711:711:711)) - (PORT datad (765:765:765) (740:740:740)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (830:830:830) (841:841:841)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (633:633:633) (656:656:656)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -24280,10 +27766,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) + (INSTANCE z80_\|alu_\|op1_low\[1\]) (DELAY (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT clk (1350:1350:1350) (1357:1357:1357)) (PORT d (67:67:67) (78:78:78)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) @@ -24299,40 +27785,65 @@ (INSTANCE z80_\|alu_control_\|out\[6\]\~0) (DELAY (ABSOLUTE - (PORT datab (237:237:237) (305:305:305)) - (PORT datac (219:219:219) (287:287:287)) + (PORT datab (240:240:240) (310:310:310)) + (PORT datac (213:213:213) (279:279:279)) (PORT datad (214:214:214) (271:271:271)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) (DELAY (ABSOLUTE - (PORT dataa (1116:1116:1116) (1170:1170:1170)) - (PORT datab (1056:1056:1056) (1052:1052:1052)) - (PORT datac (977:977:977) (946:946:946)) - (PORT datad (1026:1026:1026) (1043:1043:1043)) - (IOPATH dataa combout (287:287:287) (289:289:289)) + (PORT datac (792:792:792) (801:801:801)) + (PORT datad (625:625:625) (638:638:638)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (643:643:643)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datad (569:569:569) (563:563:563)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~19) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) (DELAY (ABSOLUTE - (PORT dataa (220:220:220) (292:292:292)) - (PORT datab (596:596:596) (628:628:628)) - (PORT datac (1220:1220:1220) (1201:1201:1201)) - (PORT datad (527:527:527) (526:526:526)) + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1097:1097:1097)) + (PORT datab (632:632:632) (626:626:626)) + (PORT datac (1043:1043:1043) (1070:1070:1070)) + (PORT datad (608:608:608) (650:650:650)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -24342,13 +27853,139 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (1569:1569:1569) (1547:1547:1547)) - (PORT datab (815:815:815) (818:818:818)) - (PORT datac (1004:1004:1004) (1002:1002:1002)) - (PORT datad (960:960:960) (930:930:930)) + (PORT dataa (1107:1107:1107) (1114:1114:1114)) + (PORT datab (1529:1529:1529) (1523:1523:1523)) + (PORT datac (1336:1336:1336) (1338:1338:1338)) + (PORT datad (781:781:781) (791:791:791)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (610:610:610)) + (PORT datab (862:862:862) (866:866:866)) + (PORT datac (572:572:572) (606:606:606)) + (PORT datad (779:779:779) (767:767:767)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (759:759:759)) + (PORT datab (838:838:838) (834:834:834)) + (PORT datac (386:386:386) (421:421:421)) + (PORT datad (771:771:771) (777:777:777)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (636:636:636)) + (PORT datab (870:870:870) (873:873:873)) + (PORT datac (540:540:540) (538:538:538)) + (PORT datad (297:297:297) (297:297:297)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1213:1213:1213)) + (PORT datab (895:895:895) (908:908:908)) + (PORT datac (855:855:855) (841:841:841)) + (PORT datad (1429:1429:1429) (1463:1463:1463)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (578:578:578)) + (PORT datab (914:914:914) (921:921:921)) + (PORT datac (159:159:159) (191:191:191)) + (PORT datad (198:198:198) (239:239:239)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1562:1562:1562) (1566:1566:1566)) + (PORT datab (845:845:845) (834:834:834)) + (PORT datac (833:833:833) (828:828:828)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1329:1329:1329) (1313:1313:1313)) + (PORT datab (1038:1038:1038) (1037:1037:1037)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (214:214:214) (247:247:247)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (254:254:254)) + (PORT datab (223:223:223) (273:273:273)) + (PORT datac (574:574:574) (576:576:576)) + (PORT datad (785:785:785) (799:799:799)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -24358,1663 +27995,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~23) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) (DELAY (ABSOLUTE - (PORT dataa (862:862:862) (888:888:888)) - (PORT datab (765:765:765) (736:736:736)) - (PORT datac (1471:1471:1471) (1460:1460:1460)) - (PORT datad (589:589:589) (607:607:607)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (785:785:785) (776:776:776)) - (PORT datab (190:190:190) (226:226:226)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1050:1050:1050) (1033:1033:1033)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (511:511:511) (502:502:502)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (1171:1171:1171) (1134:1134:1134)) - (PORT datad (603:603:603) (613:613:613)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (190:190:190) (219:219:219)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (557:557:557)) - (PORT datab (235:235:235) (283:283:283)) - (PORT datad (1046:1046:1046) (1030:1030:1030)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (577:577:577) (579:579:579)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1332:1332:1332) (1366:1366:1366)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT asdata (866:866:866) (849:849:849)) - (PORT ena (1099:1099:1099) (1089:1089:1089)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (250:250:250) (316:316:316)) - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (546:546:546) (544:544:544)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1370:1370:1370)) - (PORT asdata (906:906:906) (887:887:887)) - (PORT ena (1341:1341:1341) (1293:1293:1293)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (339:339:339)) - (PORT datad (581:581:581) (573:573:573)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (1279:1279:1279) (1282:1282:1282)) - (PORT ena (1312:1312:1312) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (1277:1277:1277) (1283:1283:1283)) - (PORT ena (1157:1157:1157) (1125:1125:1125)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (611:611:611)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (780:780:780) (796:796:796)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT asdata (912:912:912) (907:907:907)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT asdata (912:912:912) (906:906:906)) - (PORT ena (1355:1355:1355) (1327:1327:1327)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (255:255:255) (313:313:313)) - (PORT datab (637:637:637) (676:676:676)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (570:570:570)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (577:577:577) (575:575:575)) - (PORT datad (285:285:285) (290:290:290)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (1364:1364:1364) (1342:1342:1342)) - (PORT ena (1109:1109:1109) (1075:1075:1075)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (1360:1360:1360) (1337:1337:1337)) - (PORT ena (1094:1094:1094) (1065:1065:1065)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (434:434:434)) - (PORT datab (644:644:644) (648:648:648)) - (PORT datad (607:607:607) (606:606:606)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1150:1150:1150) (1146:1146:1146)) - (PORT ena (1197:1197:1197) (1191:1191:1191)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1155:1155:1155) (1150:1150:1150)) - (PORT ena (1104:1104:1104) (1097:1097:1097)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (687:687:687)) - (PORT datab (636:636:636) (675:675:675)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (789:789:789) (775:775:775)) - (PORT datab (587:587:587) (606:606:606)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (789:789:789) (773:773:773)) - (PORT datab (798:798:798) (804:804:804)) - (PORT datac (1395:1395:1395) (1432:1432:1432)) - (PORT datad (777:777:777) (775:775:775)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT asdata (649:649:649) (667:667:667)) - (PORT ena (896:896:896) (889:889:889)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1143:1143:1143)) - (PORT datab (1128:1128:1128) (1109:1109:1109)) - (PORT datad (370:370:370) (388:388:388)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datac (406:406:406) (435:435:435)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (806:806:806)) - (PORT datab (1330:1330:1330) (1410:1410:1410)) - (PORT datac (537:537:537) (534:534:534)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (747:747:747) (803:803:803)) - (PORT datad (1129:1129:1129) (1190:1190:1190)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (166:166:166) (189:189:189)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1374:1374:1374)) - (PORT ena (2403:2403:2403) (2395:2395:2395)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datac (952:952:952) (934:934:934)) - (PORT datad (758:758:758) (750:750:750)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1173:1173:1173)) - (PORT datab (1178:1178:1178) (1141:1141:1141)) - (PORT datac (1260:1260:1260) (1286:1286:1286)) - (PORT datad (1195:1195:1195) (1177:1177:1177)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (511:511:511) (516:516:516)) + (PORT datab (662:662:662) (684:684:684)) + (PORT datac (547:547:547) (541:541:541)) + (PORT datad (799:799:799) (812:812:812)) + (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (935:935:935) (942:942:942)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (1404:1404:1404) (1401:1401:1401)) - (PORT ena (1109:1109:1109) (1075:1075:1075)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (1404:1404:1404) (1400:1400:1400)) - (PORT ena (1094:1094:1094) (1065:1065:1065)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (405:405:405)) - (PORT datab (649:649:649) (650:650:650)) - (PORT datad (610:610:610) (609:609:609)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1124:1124:1124) (1112:1112:1112)) - (PORT ena (1104:1104:1104) (1097:1097:1097)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1127:1127:1127) (1115:1115:1115)) - (PORT ena (1197:1197:1197) (1191:1191:1191)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (296:296:296)) - (PORT datab (632:632:632) (666:666:666)) - (PORT datad (620:620:620) (645:645:645)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (1510:1510:1510) (1514:1514:1514)) - (PORT ena (1157:1157:1157) (1125:1125:1125)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (1508:1508:1508) (1513:1513:1513)) - (PORT ena (1312:1312:1312) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (611:611:611)) - (PORT datab (803:803:803) (823:823:823)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT asdata (485:485:485) (512:512:512)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (550:550:550) (556:556:556)) - (PORT datab (597:597:597) (588:588:588)) - (PORT datad (208:208:208) (246:246:246)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT asdata (854:854:854) (844:844:844)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT asdata (854:854:854) (845:845:845)) - (PORT ena (1355:1355:1355) (1327:1327:1327)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (317:317:317)) - (PORT datab (637:637:637) (677:677:677)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT asdata (865:865:865) (860:860:860)) - (PORT ena (1332:1332:1332) (1366:1366:1366)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT asdata (867:867:867) (862:862:862)) - (PORT ena (1099:1099:1099) (1089:1089:1089)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (321:321:321)) - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (543:543:543) (544:544:544)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT asdata (1485:1485:1485) (1483:1483:1483)) - (PORT ena (739:739:739) (742:742:742)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (368:368:368)) - (PORT datad (198:198:198) (229:229:229)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (766:766:766)) - (PORT datab (351:351:351) (353:353:353)) - (PORT datac (499:499:499) (483:483:483)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (774:774:774)) - (PORT datac (755:755:755) (751:751:751)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1422:1422:1422) (1463:1463:1463)) - (PORT datab (755:755:755) (744:744:744)) - (PORT datac (752:752:752) (738:738:738)) - (PORT datad (297:297:297) (290:290:290)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (INSTANCE z80_\|alu_\|op1_low\[2\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT asdata (486:486:486) (513:513:513)) - (PORT ena (896:896:896) (889:889:889)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1173:1173:1173) (1143:1143:1143)) - (PORT datab (1305:1305:1305) (1300:1300:1300)) - (PORT datad (368:368:368) (388:388:388)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (384:384:384) (444:444:444)) - (PORT datac (404:404:404) (433:433:433)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (241:241:241)) - (PORT datab (195:195:195) (233:233:233)) - (PORT datac (576:576:576) (617:617:617)) - (PORT datad (166:166:166) (193:193:193)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (216:216:216)) - (PORT datab (596:596:596) (598:598:598)) - (PORT datac (541:541:541) (530:530:530)) - (PORT datad (1304:1304:1304) (1369:1369:1369)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT datac (1380:1380:1380) (1411:1411:1411)) - (PORT datad (585:585:585) (592:592:592)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1365:1365:1365)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1358:1358:1358)) - (PORT ena (2262:2262:2262) (2221:2221:2221)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1173:1173:1173)) - (PORT datab (1178:1178:1178) (1141:1141:1141)) - (PORT datac (577:577:577) (617:617:617)) - (PORT datad (1195:1195:1195) (1177:1177:1177)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT datac (1378:1378:1378) (1411:1411:1411)) - (PORT datad (555:555:555) (560:560:560)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1365:1365:1365)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1358:1358:1358)) - (PORT ena (2262:2262:2262) (2221:2221:2221)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1240:1240:1240) (1218:1218:1218)) - (PORT datab (1176:1176:1176) (1140:1140:1140)) - (PORT datac (1163:1163:1163) (1141:1141:1141)) - (PORT datad (635:635:635) (670:670:670)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (242:242:242)) - (PORT datab (188:188:188) (226:226:226)) - (PORT datac (163:163:163) (199:199:199)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (833:833:833) (853:853:853)) - (PORT datac (781:781:781) (893:893:893)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (935:935:935) (942:942:942)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT asdata (485:485:485) (512:512:512)) - (PORT ena (896:896:896) (889:889:889)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1173:1173:1173) (1145:1145:1145)) - (PORT datab (972:972:972) (981:981:981)) - (PORT datad (367:367:367) (386:386:386)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (442:442:442)) - (PORT datac (405:405:405) (434:434:434)) - (PORT datad (159:159:159) (178:178:178)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (762:762:762)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (537:537:537) (533:533:533)) - (PORT datad (1304:1304:1304) (1373:1373:1373)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (634:634:634) (641:641:641)) - (PORT ena (1104:1104:1104) (1097:1097:1097)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (634:634:634) (639:639:639)) - (PORT ena (1197:1197:1197) (1191:1191:1191)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (404:404:404)) - (PORT datab (637:637:637) (675:675:675)) - (PORT datad (619:619:619) (652:652:652)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1257:1257:1257)) - (PORT datab (847:847:847) (866:866:866)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (1093:1093:1093) (1072:1072:1072)) - (PORT ena (1109:1109:1109) (1075:1075:1075)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (1093:1093:1093) (1074:1074:1074)) - (PORT ena (1094:1094:1094) (1065:1065:1065)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (411:411:411)) - (PORT datab (644:644:644) (656:656:656)) - (PORT datad (606:606:606) (614:614:614)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT asdata (1736:1736:1736) (1744:1744:1744)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT asdata (1107:1107:1107) (1100:1100:1100)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT asdata (1739:1739:1739) (1747:1747:1747)) - (PORT ena (1355:1355:1355) (1327:1327:1327)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (606:606:606)) - (PORT datab (637:637:637) (676:676:676)) - (PORT datad (588:588:588) (592:592:592)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (259:259:259) (319:319:319)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT asdata (1298:1298:1298) (1281:1281:1281)) - (PORT ena (1332:1332:1332) (1366:1366:1366)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT asdata (1302:1302:1302) (1281:1281:1281)) - (PORT ena (1099:1099:1099) (1089:1089:1089)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (321:321:321)) - (PORT datab (220:220:220) (288:288:288)) - (PORT datad (542:542:542) (543:543:543)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1113:1113:1113) (1063:1063:1063)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (864:864:864) (852:852:852)) - (PORT ena (1157:1157:1157) (1125:1125:1125)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (866:866:866) (854:854:854)) - (PORT ena (1312:1312:1312) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (612:612:612)) - (PORT datab (804:804:804) (824:824:824)) - (PORT datad (200:200:200) (257:257:257)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (560:560:560)) - (PORT datab (221:221:221) (291:291:291)) - (PORT datac (325:325:325) (327:327:327)) - (PORT datad (766:766:766) (746:746:746)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (329:329:329)) - (PORT datab (601:601:601) (606:606:606)) - (PORT datac (551:551:551) (544:544:544)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (370:370:370)) - (PORT datab (857:857:857) (861:861:861)) - (PORT datac (1147:1147:1147) (1190:1190:1190)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (539:539:539)) - (PORT datab (834:834:834) (842:842:842)) - (PORT datac (802:802:802) (816:816:816)) - (PORT datad (578:578:578) (574:574:574)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (186:186:186) (223:223:223)) - (PORT datac (1493:1493:1493) (1483:1483:1483)) - (PORT datad (315:315:315) (318:318:318)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (661:661:661)) - (PORT datab (581:581:581) (577:577:577)) - (PORT datac (295:295:295) (315:315:315)) - (PORT datad (192:192:192) (222:222:222)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1039:1039:1039) (1038:1038:1038)) - (PORT datab (635:635:635) (625:625:625)) - (PORT datac (832:832:832) (804:804:804)) - (PORT datad (1066:1066:1066) (1043:1043:1043)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (224:224:224)) - (PORT datab (228:228:228) (283:283:283)) - (PORT datac (1215:1215:1215) (1237:1237:1237)) - (PORT datad (784:784:784) (774:774:774)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (870:870:870)) - (PORT datab (648:648:648) (673:673:673)) - (PORT datac (1075:1075:1075) (1130:1130:1130)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (332:332:332) (344:344:344)) - (PORT datac (1290:1290:1290) (1306:1306:1306)) - (PORT datad (530:530:530) (535:535:535)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (572:572:572) (585:585:585)) - (PORT datac (1195:1195:1195) (1160:1160:1160)) - (PORT datad (558:558:558) (558:558:558)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (514:514:514) (511:511:511)) - (PORT datad (780:780:780) (756:756:756)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (788:788:788) (779:779:779)) - (PORT datab (182:182:182) (213:213:213)) - (PORT datac (584:584:584) (589:589:589)) - (PORT datad (825:825:825) (834:834:834)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT clk (1350:1350:1350) (1357:1357:1357)) (PORT d (67:67:67) (78:78:78)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) @@ -26027,279 +28027,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1215:1215:1215) (1183:1183:1183)) - (PORT datab (1186:1186:1186) (1172:1172:1172)) - (PORT datac (222:222:222) (293:293:293)) - (PORT datad (226:226:226) (286:286:286)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (360:360:360)) - (PORT datab (823:823:823) (837:837:837)) - (PORT datac (1024:1024:1024) (1020:1020:1020)) - (PORT datad (1064:1064:1064) (1070:1070:1070)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (765:765:765) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (715:715:715)) - (PORT datab (651:651:651) (694:694:694)) - (PORT datac (755:755:755) (771:771:771)) - (PORT datad (803:803:803) (789:789:789)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (228:228:228)) - (PORT datab (205:205:205) (242:242:242)) - (PORT datac (292:292:292) (307:307:307)) - (PORT datad (171:171:171) (198:198:198)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (551:551:551)) - (PORT datab (195:195:195) (230:230:230)) - (PORT datac (153:153:153) (183:183:183)) - (PORT datad (527:527:527) (518:518:518)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1874:1874:1874) (1835:1835:1835)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (858:858:858)) - (PORT datab (674:674:674) (717:717:717)) - (PORT datac (634:634:634) (686:686:686)) - (PORT datad (994:994:994) (972:972:972)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (611:611:611)) - (PORT datab (617:617:617) (653:653:653)) - (PORT datac (508:508:508) (507:507:507)) - (PORT datad (550:550:550) (547:547:547)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (588:588:588)) - (PORT datab (513:513:513) (519:519:519)) - (PORT datad (1929:1929:1929) (1937:1937:1937)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (545:545:545)) - (PORT datac (1263:1263:1263) (1283:1283:1283)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (551:551:551) (536:536:536)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (939:939:939) (901:901:901)) - (PORT datad (783:783:783) (780:780:780)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (635:635:635)) - (PORT datab (834:834:834) (847:847:847)) - (PORT datac (552:552:552) (560:560:560)) - (PORT datad (832:832:832) (832:832:832)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (789:789:789) (792:792:792)) - (PORT datab (616:616:616) (626:626:626)) - (PORT datac (614:614:614) (644:644:644)) - (PORT datad (556:556:556) (565:565:565)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) - (DELAY - (ABSOLUTE - (PORT datac (619:619:619) (641:641:641)) - (PORT datad (197:197:197) (219:219:219)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (502:502:502) (493:493:493)) - (PORT datad (300:300:300) (313:313:313)) + (PORT dataa (605:605:605) (637:637:637)) + (PORT datab (1034:1034:1034) (1055:1055:1055)) + (PORT datac (551:551:551) (541:541:541)) + (PORT datad (370:370:370) (411:411:411)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1505:1505:1505) (1478:1478:1478)) - (PORT datab (850:850:850) (893:893:893)) - (PORT datac (1100:1100:1100) (1136:1136:1136)) - (PORT datad (721:721:721) (691:691:691)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (418:418:418)) - (PORT datab (616:616:616) (636:636:636)) - (PORT datac (564:564:564) (559:559:559)) - (PORT datad (763:763:763) (769:769:769)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26307,372 +28043,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (537:537:537) (539:539:539)) - (PORT datab (986:986:986) (962:962:962)) - (PORT datac (987:987:987) (946:946:946)) - (PORT datad (512:512:512) (505:505:505)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~1) (DELAY (ABSOLUTE (PORT dataa (238:238:238) (310:310:310)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (214:214:214) (281:281:281)) - (PORT datad (219:219:219) (279:279:279)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (638:638:638)) - (PORT datab (811:811:811) (798:798:798)) - (PORT datac (219:219:219) (288:288:288)) - (PORT datad (627:627:627) (689:689:689)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1239:1239:1239)) - (PORT datab (647:647:647) (696:696:696)) - (PORT datac (586:586:586) (592:592:592)) - (PORT datad (564:564:564) (573:573:573)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (797:797:797) (811:811:811)) - (PORT datad (576:576:576) (591:591:591)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1208:1208:1208) (1199:1199:1199)) - (PORT datab (781:781:781) (781:781:781)) - (PORT datac (296:296:296) (303:303:303)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (953:953:953) (924:924:924)) - (PORT datab (791:791:791) (808:808:808)) - (PORT datac (1377:1377:1377) (1416:1416:1416)) - (PORT datad (1901:1901:1901) (1912:1912:1912)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (368:368:368)) - (PORT datab (640:640:640) (656:656:656)) - (PORT datac (173:173:173) (203:203:203)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (313:313:313) (333:333:333)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (935:935:935) (917:917:917)) - (PORT datad (167:167:167) (194:194:194)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (963:963:963)) - (PORT datab (1010:1010:1010) (987:987:987)) - (PORT datac (571:571:571) (568:568:568)) - (PORT datad (197:197:197) (228:228:228)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (579:579:579)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (159:159:159) (190:190:190)) - (PORT datad (594:594:594) (601:601:601)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1040:1040:1040) (1039:1039:1039)) - (PORT datab (1105:1105:1105) (1077:1077:1077)) - (PORT datac (743:743:743) (780:780:780)) - (PORT datad (774:774:774) (774:774:774)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (827:827:827)) - (PORT datab (813:813:813) (805:805:805)) - (PORT datac (330:330:330) (343:343:343)) - (PORT datad (205:205:205) (249:249:249)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1169:1169:1169)) - (PORT datab (652:652:652) (676:676:676)) - (PORT datac (776:776:776) (818:818:818)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (525:525:525) (514:514:514)) + (PORT datad (842:842:842) (871:871:871)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1197:1197:1197)) - (PORT datab (875:875:875) (865:865:865)) - (PORT datac (1316:1316:1316) (1343:1343:1343)) - (PORT datad (309:309:309) (318:318:318)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1062:1062:1062)) - (PORT datac (552:552:552) (560:560:560)) - (PORT datad (809:809:809) (812:812:812)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1108:1108:1108)) - (PORT datab (633:633:633) (643:643:643)) - (PORT datac (1027:1027:1027) (1024:1024:1024)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) + (INSTANCE z80_\|alu_\|op2_low\[2\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (765:765:765) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1035:1035:1035) (1005:1005:1005)) - (PORT datab (673:673:673) (726:726:726)) - (PORT datac (593:593:593) (631:631:631)) - (PORT datad (802:802:802) (804:804:804)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1110:1110:1110) (1096:1096:1096)) - (PORT datab (1011:1011:1011) (1012:1012:1012)) - (PORT datac (1178:1178:1178) (1163:1163:1163)) - (PORT datad (313:313:313) (313:313:313)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (471:471:471) (454:454:454)) - (PORT datad (784:784:784) (759:759:759)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1059:1059:1059)) - (PORT datab (618:618:618) (630:630:630)) - (PORT datac (596:596:596) (608:608:608)) - (PORT datad (824:824:824) (833:833:833)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT clk (1350:1350:1350) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) @@ -26685,910 +28075,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) + (INSTANCE z80_\|alu_\|db_low\[2\]\~5) (DELAY (ABSOLUTE - (PORT dataa (1293:1293:1293) (1276:1276:1276)) - (PORT datab (677:677:677) (733:733:733)) - (PORT datac (617:617:617) (663:663:663)) - (PORT datad (953:953:953) (942:942:942)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (579:579:579)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (1023:1023:1023) (1018:1018:1018)) - (PORT datad (1064:1064:1064) (1065:1065:1065)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (765:765:765) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (687:687:687)) - (PORT datab (781:781:781) (794:794:794)) - (PORT datac (590:590:590) (627:627:627)) - (PORT datad (802:802:802) (785:785:785)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (237:237:237)) - (PORT datab (642:642:642) (687:687:687)) - (PORT datac (1265:1265:1265) (1243:1243:1243)) - (PORT datad (650:650:650) (698:698:698)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (359:359:359)) - (PORT datab (199:199:199) (242:242:242)) - (PORT datac (167:167:167) (202:202:202)) - (PORT datad (164:164:164) (187:187:187)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (362:362:362)) - (PORT datab (198:198:198) (243:243:243)) - (PORT datac (310:310:310) (317:317:317)) - (PORT datad (189:189:189) (216:216:216)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (735:735:735)) - (PORT datab (351:351:351) (367:367:367)) - (PORT datac (356:356:356) (384:384:384)) - (PORT datad (773:773:773) (737:737:737)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (959:959:959) (945:945:945)) - (PORT datab (855:855:855) (885:885:885)) - (PORT datac (1026:1026:1026) (1013:1013:1013)) - (PORT datad (1219:1219:1219) (1192:1192:1192)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (986:986:986)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (1226:1226:1226) (1218:1218:1218)) - (PORT datad (998:998:998) (979:979:979)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (573:573:573) (580:580:580)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1159:1159:1159)) - (PORT datab (800:800:800) (839:839:839)) - (PORT datac (1027:1027:1027) (1024:1024:1024)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1310:1310:1310) (1333:1333:1333)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (742:742:742) (716:716:716)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1310:1310:1310) (1336:1336:1336)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (565:565:565) (576:576:576)) - (PORT datad (827:827:827) (854:854:854)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (856:856:856) (890:890:890)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (824:824:824)) - (PORT datab (1052:1052:1052) (1041:1041:1041)) - (PORT datac (218:218:218) (288:288:288)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (957:957:957)) - (PORT datab (905:905:905) (951:951:951)) - (PORT datac (2074:2074:2074) (2047:2047:2047)) - (PORT datad (551:551:551) (546:546:546)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1134:1134:1134)) - (PORT datab (1166:1166:1166) (1206:1206:1206)) - (PORT datac (1415:1415:1415) (1411:1411:1411)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1363:1363:1363) (1408:1408:1408)) - (PORT datab (551:551:551) (546:546:546)) - (PORT datac (1311:1311:1311) (1301:1301:1301)) - (PORT datad (177:177:177) (198:198:198)) + (PORT dataa (428:428:428) (482:482:482)) + (PORT datab (595:595:595) (630:630:630)) + (PORT datac (1025:1025:1025) (1003:1003:1003)) + (PORT datad (618:618:618) (634:634:634)) (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (337:337:337)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (343:343:343) (344:344:344)) - (PORT datad (289:289:289) (295:295:295)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (612:612:612)) - (PORT datab (228:228:228) (278:278:278)) - (PORT datac (729:729:729) (711:711:711)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (602:602:602)) - (PORT datab (804:804:804) (773:773:773)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (1016:1016:1016) (1009:1009:1009)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (652:652:652)) - (PORT datab (1112:1112:1112) (1106:1106:1106)) - (PORT datac (1256:1256:1256) (1254:1254:1254)) - (PORT datad (1574:1574:1574) (1577:1577:1577)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1351:1351:1351) (1392:1392:1392)) - (PORT datab (1338:1338:1338) (1320:1320:1320)) - (PORT datac (1068:1068:1068) (1076:1076:1076)) - (PORT datad (1356:1356:1356) (1384:1384:1384)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1268:1268:1268) (1251:1251:1251)) - (PORT datab (2007:2007:2007) (2022:2022:2022)) - (PORT datac (1216:1216:1216) (1196:1196:1196)) - (PORT datad (1295:1295:1295) (1286:1286:1286)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (239:239:239) (309:309:309)) - (PORT datac (913:913:913) (884:884:884)) - (PORT datad (544:544:544) (553:553:553)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (814:814:814) (840:840:840)) - (PORT datab (1113:1113:1113) (1106:1106:1106)) - (PORT datac (570:570:570) (591:591:591)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1073:1073:1073)) - (PORT datab (1347:1347:1347) (1389:1389:1389)) - (PORT datac (731:731:731) (709:709:709)) - (PORT datad (1089:1089:1089) (1135:1135:1135)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (2241:2241:2241) (2225:2225:2225)) - (PORT datab (207:207:207) (245:245:245)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1031:1031:1031) (1044:1044:1044)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (827:827:827)) - (PORT datab (609:609:609) (634:634:634)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (751:751:751) (739:739:739)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (501:501:501)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (745:745:745) (720:720:720)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (661:661:661)) - (PORT datab (1296:1296:1296) (1228:1228:1228)) - (PORT datac (1174:1174:1174) (1138:1138:1138)) - (PORT datad (547:547:547) (536:536:536)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (512:512:512) (500:500:500)) - (PORT datad (582:582:582) (577:577:577)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (585:585:585)) - (PORT datab (835:835:835) (843:843:843)) - (PORT datac (805:805:805) (814:814:814)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (813:813:813)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1494:1494:1494) (1486:1486:1486)) - (PORT datad (576:576:576) (571:571:571)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT asdata (859:859:859) (845:845:845)) - (PORT ena (1099:1099:1099) (1089:1089:1089)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (323:323:323)) - (PORT datab (965:965:965) (960:960:960)) - (PORT datad (759:759:759) (731:731:731)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (912:912:912) (907:907:907)) - (PORT ena (1312:1312:1312) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (912:912:912) (907:907:907)) - (PORT ena (1157:1157:1157) (1125:1125:1125)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (605:605:605)) - (PORT datab (220:220:220) (288:288:288)) - (PORT datad (784:784:784) (792:792:792)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT asdata (892:892:892) (886:886:886)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT asdata (859:859:859) (849:849:849)) - (PORT ena (1355:1355:1355) (1327:1327:1327)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (621:621:621)) - (PORT datab (636:636:636) (683:683:683)) - (PORT datad (587:587:587) (594:594:594)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (512:512:512) (507:507:507)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1332:1332:1332) (1366:1366:1366)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1372:1372:1372)) - (PORT asdata (858:858:858) (846:846:846)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (311:311:311)) - (PORT datab (624:624:624) (648:648:648)) - (PORT datad (536:536:536) (529:529:529)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1293:1293:1293)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (614:614:614)) - (PORT datab (347:347:347) (355:355:355)) - (PORT datac (281:281:281) (294:294:294)) - (PORT datad (196:196:196) (253:253:253)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (778:778:778) (784:784:784)) - (PORT datab (317:317:317) (328:328:328)) - (PORT datac (555:555:555) (548:548:548)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (966:966:966) (958:958:958)) - (PORT datac (531:531:531) (511:511:511)) - (PORT datad (1688:1688:1688) (1727:1727:1727)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT asdata (484:484:484) (510:510:510)) - (PORT ena (896:896:896) (889:889:889)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1141:1141:1141)) - (PORT datab (831:831:831) (830:830:830)) - (PORT datad (369:369:369) (385:385:385)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (385:385:385) (448:448:448)) - (PORT datac (403:403:403) (432:432:432)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (608:608:608)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datac (540:540:540) (530:530:530)) - (PORT datad (1304:1304:1304) (1370:1370:1370)) - (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (1436:1436:1436) (1477:1477:1477)) - (PORT datac (586:586:586) (588:588:588)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) + (INSTANCE z80_\|alu_\|result_lo\[2\]) (DELAY (ABSOLUTE - (PORT clk (1343:1343:1343) (1365:1365:1365)) + (PORT clk (1339:1339:1339) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1358:1358:1358)) - (PORT ena (2292:2292:2292) (2253:2253:2253)) + (PORT ena (1177:1177:1177) (1162:1162:1162)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK @@ -27598,45 +28107,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) + (INSTANCE z80_\|alu_\|db_low\[2\]\~6) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (244:244:244)) - (PORT datab (1043:1043:1043) (1026:1026:1026)) - (PORT datac (640:640:640) (675:675:675)) - (PORT datad (1001:1001:1001) (981:981:981)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (726:726:726)) - (PORT datab (766:766:766) (741:741:741)) - (PORT datac (681:681:681) (652:652:652)) - (PORT datad (173:173:173) (202:202:202)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (229:229:229)) - (PORT datab (188:188:188) (225:225:225)) - (PORT datac (170:170:170) (211:211:211)) - (PORT datad (637:637:637) (673:673:673)) + (PORT dataa (321:321:321) (330:330:330)) + (PORT datab (554:554:554) (558:558:558)) + (PORT datac (889:889:889) (901:901:901)) + (PORT datad (549:549:549) (571:571:571)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -27646,382 +28123,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) (DELAY (ABSOLUTE - (PORT dataa (567:567:567) (564:564:564)) - (PORT datab (1330:1330:1330) (1410:1410:1410)) - (PORT datac (555:555:555) (549:549:549)) - (PORT datad (570:570:570) (582:582:582)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (1361:1361:1361) (1350:1350:1350)) - (PORT ena (1157:1157:1157) (1125:1125:1125)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (1364:1364:1364) (1354:1354:1354)) - (PORT ena (1312:1312:1312) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (604:604:604)) - (PORT datab (810:810:810) (832:832:832)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT asdata (1563:1563:1563) (1532:1532:1532)) - (PORT ena (1149:1149:1149) (1128:1128:1128)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT asdata (1383:1383:1383) (1369:1369:1369)) - (PORT ena (1330:1330:1330) (1356:1356:1356)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (603:603:603)) - (PORT datab (392:392:392) (426:426:426)) - (PORT datad (545:545:545) (537:537:537)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1370:1370:1370)) - (PORT asdata (1397:1397:1397) (1376:1376:1376)) - (PORT ena (1099:1099:1099) (1089:1089:1089)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (322:322:322)) - (PORT datab (792:792:792) (813:813:813)) - (PORT datad (757:757:757) (730:730:730)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT asdata (1383:1383:1383) (1368:1368:1368)) - (PORT ena (739:739:739) (742:742:742)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (389:389:389)) - (PORT datad (196:196:196) (223:223:223)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (178:178:178) (200:200:200)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1352:1352:1352) (1323:1323:1323)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT asdata (1564:1564:1564) (1532:1532:1532)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1054:1054:1054)) - (PORT datab (831:831:831) (842:842:842)) - (PORT datad (208:208:208) (242:242:242)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (728:728:728) (775:775:775)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (296:296:296) (295:295:295)) + (PORT dataa (202:202:202) (250:250:250)) + (PORT datab (606:606:606) (599:599:599)) + (PORT datac (847:847:847) (864:864:864)) + (PORT datad (199:199:199) (239:239:239)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (882:882:882) (871:871:871)) - (PORT ena (1109:1109:1109) (1075:1075:1075)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1373:1373:1373)) - (PORT asdata (882:882:882) (871:871:871)) - (PORT ena (1094:1094:1094) (1065:1065:1065)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (647:647:647)) - (PORT datab (645:645:645) (653:653:653)) - (PORT datad (607:607:607) (612:612:612)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1156:1156:1156) (1167:1167:1167)) - (PORT ena (1104:1104:1104) (1097:1097:1097)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1154:1154:1154) (1165:1165:1165)) - (PORT ena (1197:1197:1197) (1191:1191:1191)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (296:296:296)) - (PORT datab (633:633:633) (670:670:670)) - (PORT datad (620:620:620) (644:644:644)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (781:781:781)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datad (570:570:570) (582:582:582)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (402:402:402)) - (PORT datab (518:518:518) (511:511:511)) - (PORT datac (1210:1210:1210) (1190:1190:1190)) - (PORT datad (1190:1190:1190) (1263:1263:1263)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1027:1027:1027)) - (PORT datab (215:215:215) (255:255:255)) - (PORT datac (1179:1179:1179) (1143:1143:1143)) - (PORT datad (581:581:581) (581:581:581)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -28029,780 +28139,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~4) (DELAY (ABSOLUTE - (PORT dataa (187:187:187) (224:224:224)) - (PORT datab (842:842:842) (850:850:850)) - (PORT datac (1534:1534:1534) (1493:1493:1493)) - (PORT datad (592:592:592) (601:601:601)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (609:609:609)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (547:547:547) (543:543:543)) - (PORT datad (582:582:582) (577:577:577)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1032:1032:1032)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (516:516:516) (510:510:510)) - (PORT datad (203:203:203) (248:248:248)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (762:762:762) (808:808:808)) - (PORT datac (1080:1080:1080) (1140:1140:1140)) - (PORT datad (798:798:798) (820:820:820)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1009:1009:1009)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (1386:1386:1386) (1425:1425:1425)) - (PORT datad (1209:1209:1209) (1167:1167:1167)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (630:630:630)) - (PORT datab (837:837:837) (846:846:846)) - (PORT datad (831:831:831) (831:831:831)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1065:1065:1065)) - (PORT datab (390:390:390) (440:440:440)) - (PORT datac (384:384:384) (418:418:418)) - (PORT datad (1035:1035:1035) (1023:1023:1023)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (317:317:317) (341:341:341)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (1023:1023:1023) (1017:1017:1017)) - (PORT datad (1064:1064:1064) (1065:1065:1065)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (765:765:765) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (630:630:630)) - (PORT datab (835:835:835) (847:847:847)) - (PORT datac (1017:1017:1017) (1030:1030:1030)) - (PORT datad (832:832:832) (828:828:828)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (598:598:598) (610:610:610)) - (PORT datac (1028:1028:1028) (1025:1025:1025)) - (PORT datad (1068:1068:1068) (1071:1071:1071)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (765:765:765) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (694:694:694)) - (PORT datab (783:783:783) (799:799:799)) - (PORT datac (604:604:604) (659:659:659)) - (PORT datad (802:802:802) (789:789:789)) + (PORT dataa (239:239:239) (308:308:308)) + (PORT datab (559:559:559) (546:546:546)) + (PORT datac (535:535:535) (527:527:527)) + (PORT datad (833:833:833) (861:861:861)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (751:751:751)) - (PORT datab (188:188:188) (226:226:226)) - (PORT datac (1263:1263:1263) (1241:1241:1241)) - (PORT datad (640:640:640) (693:693:693)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (363:363:363)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datac (313:313:313) (314:314:314)) - (PORT datad (193:193:193) (220:220:220)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~1) - (DELAY - (ABSOLUTE - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (302:302:302) (312:312:312)) - (PORT datad (191:191:191) (217:217:217)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (648:648:648) (674:674:674)) - (PORT datac (1076:1076:1076) (1138:1138:1138)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (797:797:797) (836:836:836)) - (PORT datac (1384:1384:1384) (1427:1427:1427)) - (PORT datad (1208:1208:1208) (1170:1170:1170)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (848:848:848)) - (PORT datab (631:631:631) (684:684:684)) - (PORT datac (647:647:647) (721:721:721)) - (PORT datad (987:987:987) (964:964:964)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (1206:1206:1206) (1170:1170:1170)) - (PORT datac (593:593:593) (605:605:605)) - (PORT datad (1194:1194:1194) (1193:1193:1193)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (561:561:561)) - (PORT datab (351:351:351) (355:355:355)) - (PORT datac (1177:1177:1177) (1165:1165:1165)) - (PORT datad (544:544:544) (546:546:546)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (531:531:531) (517:517:517)) - (PORT datab (1076:1076:1076) (1064:1064:1064)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (784:784:784) (760:760:760)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (596:596:596)) - (PORT datab (813:813:813) (806:806:806)) - (PORT datac (607:607:607) (624:624:624)) - (PORT datad (205:205:205) (249:249:249)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (677:677:677)) - (PORT datab (572:572:572) (570:570:570)) - (PORT datac (1477:1477:1477) (1467:1467:1467)) - (PORT datad (595:595:595) (614:614:614)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (955:955:955)) - (PORT datab (1003:1003:1003) (980:980:980)) - (PORT datac (335:335:335) (344:344:344)) - (PORT datad (797:797:797) (794:794:794)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1161:1161:1161)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (547:547:547) (554:554:554)) - (PORT datad (764:764:764) (759:759:759)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (608:608:608)) - (PORT datab (631:631:631) (638:638:638)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (566:566:566) (576:576:576)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (415:415:415)) - (PORT datab (351:351:351) (364:364:364)) - (PORT datac (574:574:574) (591:591:591)) - (PORT datad (742:742:742) (732:732:732)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1735:1735:1735) (1706:1706:1706)) - (PORT datab (798:798:798) (824:824:824)) - (PORT datac (831:831:831) (876:876:876)) - (PORT datad (1279:1279:1279) (1276:1276:1276)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2460:2460:2460) (2447:2447:2447)) - (PORT datab (1221:1221:1221) (1199:1199:1199)) - (PORT datac (832:832:832) (861:861:861)) - (PORT datad (166:166:166) (188:188:188)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (550:550:550) (544:544:544)) - (PORT datab (623:623:623) (635:635:635)) - (PORT datac (471:471:471) (453:453:453)) - (PORT datad (485:485:485) (475:475:475)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) - (DELAY - (ABSOLUTE - (PORT dataa (776:776:776) (782:782:782)) - (PORT datab (561:561:561) (562:562:562)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1115:1115:1115) (1102:1102:1102)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (959:959:959)) - (PORT datab (905:905:905) (951:951:951)) - (PORT datac (2074:2074:2074) (2048:2048:2048)) - (PORT datad (553:553:553) (547:547:547)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1044:1044:1044) (1036:1036:1036)) - (PORT datab (803:803:803) (786:786:786)) - (PORT datac (787:787:787) (784:784:784)) - (PORT datad (768:768:768) (752:752:752)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1835:1835:1835) (1800:1800:1800)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (796:796:796) (832:832:832)) - (PORT datad (315:315:315) (331:331:331)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (296:296:296)) - (PORT datab (559:559:559) (558:558:558)) - (PORT datac (749:749:749) (749:749:749)) - (PORT datad (159:159:159) (178:178:178)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (521:521:521) (517:517:517)) - (PORT datab (1042:1042:1042) (1074:1074:1074)) - (PORT datac (782:782:782) (774:774:774)) - (PORT datad (1101:1101:1101) (1118:1118:1118)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (814:814:814) (816:816:816)) - (PORT datab (1326:1326:1326) (1340:1340:1340)) - (PORT datac (1150:1150:1150) (1221:1221:1221)) - (PORT datad (1017:1017:1017) (1038:1038:1038)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (783:783:783)) - (PORT datab (2021:2021:2021) (1958:1958:1958)) - (PORT datac (786:786:786) (780:780:780)) - (PORT datad (1075:1075:1075) (1077:1077:1077)) - (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (233:233:233)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (591:591:591) (601:601:601)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (575:575:575)) - (PORT datab (833:833:833) (820:820:820)) - (PORT datac (618:618:618) (648:648:648)) - (PORT datad (810:810:810) (802:802:802)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) - (DELAY - (ABSOLUTE - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (214:214:214) (248:248:248)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (866:866:866)) - (PORT datac (775:775:775) (756:756:756)) - (PORT datad (772:772:772) (753:753:753)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1042:1042:1042) (1033:1033:1033)) - (PORT datab (184:184:184) (217:217:217)) - (PORT datac (787:787:787) (781:781:781)) - (PORT datad (311:311:311) (329:329:329)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (676:676:676)) - (PORT datab (406:406:406) (478:478:478)) - (PORT datac (397:397:397) (460:460:460)) - (PORT datad (1045:1045:1045) (1057:1057:1057)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (712:712:712)) - (PORT datab (844:844:844) (896:896:896)) - (PORT datac (574:574:574) (615:615:615)) - (PORT datad (638:638:638) (674:674:674)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (410:410:410)) - (PORT datab (811:811:811) (917:917:917)) - (PORT datac (595:595:595) (649:649:649)) - (PORT datad (617:617:617) (664:664:664)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) + (INSTANCE z80_\|alu_\|op2_high\[2\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1365:1365:1365)) + (PORT clk (1350:1350:1350) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1358:1358:1358)) - (PORT ena (2262:2262:2262) (2221:2221:2221)) + (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK @@ -28812,158 +28171,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (602:602:602) (638:638:638)) - (PORT datab (235:235:235) (308:308:308)) - (PORT datac (1029:1029:1029) (1030:1030:1030)) - (PORT datad (376:376:376) (415:415:415)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (584:584:584)) - (PORT datab (591:591:591) (587:587:587)) - (PORT datac (1305:1305:1305) (1367:1367:1367)) - (PORT datad (294:294:294) (301:301:301)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1043:1043:1043) (1032:1032:1032)) - (PORT datab (854:854:854) (841:841:841)) - (PORT datad (500:500:500) (487:487:487)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1362:1362:1362)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (849:849:849) (880:880:880)) - (PORT datac (786:786:786) (781:781:781)) - (PORT datad (204:204:204) (265:265:265)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (864:864:864)) - (PORT datab (806:806:806) (788:788:788)) - (PORT datac (774:774:774) (759:759:759)) - (PORT datad (1789:1789:1789) (1759:1759:1759)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (654:654:654)) - (PORT datab (341:341:341) (363:363:363)) - (PORT datac (156:156:156) (185:185:185)) - (PORT datad (568:568:568) (579:579:579)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (813:813:813) (813:813:813)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (1008:1008:1008) (999:999:999)) - (PORT datad (1788:1788:1788) (1756:1756:1756)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1257:1257:1257)) - (PORT datab (1325:1325:1325) (1339:1339:1339)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (358:358:358)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (217:217:217) (285:285:285)) - (PORT datad (755:755:755) (762:762:762)) + (PORT dataa (426:426:426) (475:475:475)) + (PORT datab (647:647:647) (660:660:660)) + (PORT datac (802:802:802) (805:805:805)) + (PORT datad (380:380:380) (436:436:436)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -28971,136 +28187,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~13) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (569:569:569) (595:595:595)) - (PORT datab (343:343:343) (350:350:350)) - (PORT datac (562:562:562) (577:577:577)) - (PORT datad (161:161:161) (182:182:182)) + (PORT dataa (359:359:359) (369:369:369)) + (PORT datab (369:369:369) (374:374:374)) + (PORT datac (161:161:161) (194:194:194)) + (PORT datad (325:325:325) (327:327:327)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (364:364:364)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (330:330:330) (335:335:335)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (833:833:833)) - (PORT datab (179:179:179) (212:212:212)) - (PORT datac (798:798:798) (817:817:817)) - (PORT datad (166:166:166) (188:188:188)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) (DELAY (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (1317:1317:1317) (1308:1308:1308)) - (PORT datad (1905:1905:1905) (1913:1913:1913)) + (PORT dataa (1092:1092:1092) (1091:1091:1091)) + (PORT datab (243:243:243) (308:308:308)) + (PORT datac (218:218:218) (274:274:274)) + (PORT datad (234:234:234) (271:271:271)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|flags_cond_true) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1373:1373:1373)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT dataa (986:986:986) (988:988:988)) - (PORT datab (813:813:813) (841:841:841)) - (PORT datac (760:760:760) (740:740:740)) - (PORT datad (1444:1444:1444) (1434:1434:1434)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (642:642:642) (638:638:638)) - (PORT datac (945:945:945) (930:930:930)) - (PORT datad (555:555:555) (554:554:554)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (236:236:236)) - (PORT datab (186:186:186) (223:223:223)) - (PORT datac (503:503:503) (500:500:500)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) - (DELAY - (ABSOLUTE - (PORT dataa (999:999:999) (972:972:972)) - (PORT datac (882:882:882) (863:863:863)) - (PORT datad (953:953:953) (919:919:919)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -29108,973 +28235,74 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1081:1081:1081) (1069:1069:1069)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datac (174:174:174) (204:204:204)) - (PORT datad (545:545:545) (541:541:541)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (236:236:236)) - (PORT datab (179:179:179) (211:211:211)) - (PORT datac (783:783:783) (762:762:762)) - (PORT datad (176:176:176) (197:197:197)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (347:347:347)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (174:174:174) (205:205:205)) - (PORT datad (594:594:594) (612:612:612)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (582:582:582)) - (PORT datab (555:555:555) (541:541:541)) - (PORT datac (1435:1435:1435) (1493:1493:1493)) - (PORT datad (1171:1171:1171) (1146:1146:1146)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1618:1618:1618) (1639:1639:1639)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1372:1372:1372)) - (PORT asdata (1614:1614:1614) (1635:1635:1635)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (397:397:397) (431:431:431)) - (PORT datab (401:401:401) (414:414:414)) - (PORT datad (337:337:337) (371:371:371)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1381:1381:1381)) - (PORT asdata (1339:1339:1339) (1331:1331:1331)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1140:1140:1140)) - (PORT datab (1266:1266:1266) (1283:1283:1283)) - (PORT datad (1736:1736:1736) (1703:1703:1703)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1639:1639:1639) (1650:1650:1650)) - (PORT ena (882:882:882) (874:874:874)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1635:1635:1635) (1649:1649:1649)) - (PORT ena (1397:1397:1397) (1371:1371:1371)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (434:434:434)) - (PORT datab (383:383:383) (415:415:415)) - (PORT datad (332:332:332) (372:372:372)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (860:860:860) (857:857:857)) - (PORT ena (1311:1311:1311) (1323:1323:1323)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (862:862:862) (860:860:860)) - (PORT ena (1327:1327:1327) (1302:1302:1302)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (448:448:448)) - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (614:614:614) (627:627:627)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1609:1609:1609) (1609:1609:1609)) - (PORT ena (1108:1108:1108) (1069:1069:1069)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1374:1374:1374)) - (PORT asdata (1610:1610:1610) (1607:1607:1607)) - (PORT ena (1138:1138:1138) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (620:620:620)) - (PORT datab (220:220:220) (287:287:287)) - (PORT datad (581:581:581) (573:573:573)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1373:1373:1373)) - (PORT asdata (1637:1637:1637) (1652:1652:1652)) - (PORT ena (860:860:860) (843:843:843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1190:1190:1190)) - (PORT datab (1023:1023:1023) (996:996:996)) - (PORT datad (365:365:365) (369:369:369)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (602:602:602)) - (PORT datab (631:631:631) (643:643:643)) - (PORT datac (557:557:557) (558:558:558)) - (PORT datad (549:549:549) (552:552:552)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (822:822:822) (837:837:837)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1381:1381:1381)) - (PORT asdata (1336:1336:1336) (1328:1328:1328)) - (PORT ena (739:739:739) (742:742:742)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (404:404:404)) - (PORT datab (377:377:377) (391:391:391)) - (PORT datad (605:605:605) (638:638:638)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (630:630:630)) - (PORT datab (182:182:182) (213:213:213)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1851:1851:1851) (1922:1922:1922)) - (PORT datab (545:545:545) (543:543:543)) - (PORT datac (523:523:523) (515:515:515)) - (PORT datad (792:792:792) (788:788:788)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (832:832:832) (818:818:818)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (858:858:858) (905:905:905)) - (PORT datad (215:215:215) (270:270:270)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (903:903:903) (898:898:898)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (323:323:323) (332:332:332)) - (PORT datab (416:416:416) (434:434:434)) - (PORT datad (200:200:200) (258:258:258)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (251:251:251)) - (PORT datab (1001:1001:1001) (1026:1026:1026)) - (PORT datac (596:596:596) (651:651:651)) - (PORT datad (360:360:360) (400:400:400)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (597:597:597) (649:649:649)) - (PORT datad (957:957:957) (960:960:960)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (370:370:370) (397:397:397)) - (PORT datac (1523:1523:1523) (1603:1603:1603)) - (PORT datad (575:575:575) (582:582:582)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) - (DELAY - (ABSOLUTE - (PORT datac (1397:1397:1397) (1441:1441:1441)) - (PORT datad (900:900:900) (925:925:925)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1365:1365:1365)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1358:1358:1358)) - (PORT ena (2292:2292:2292) (2253:2253:2253)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (948:948:948) (961:961:961)) - (PORT datab (406:406:406) (477:477:477)) - (PORT datac (595:595:595) (644:644:644)) - (PORT datad (956:956:956) (959:959:959)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (615:615:615) (625:625:625)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (549:549:549)) - (PORT datab (857:857:857) (908:908:908)) - (PORT datad (212:212:212) (264:264:264)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (903:903:903) (898:898:898)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (357:357:357)) - (PORT datab (422:422:422) (444:444:444)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (973:973:973)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (1530:1530:1530) (1609:1609:1609)) - (PORT datad (339:339:339) (359:359:359)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) - (DELAY - (ABSOLUTE - (PORT dataa (1437:1437:1437) (1477:1477:1477)) - (PORT datac (546:546:546) (558:558:558)) + (PORT dataa (1567:1567:1567) (1566:1566:1566)) + (PORT datac (816:816:816) (808:808:808)) + (PORT datad (814:814:814) (823:823:823)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1365:1365:1365)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1358:1358:1358)) - (PORT ena (2292:2292:2292) (2253:2253:2253)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (947:947:947) (960:960:960)) - (PORT datab (403:403:403) (475:475:475)) - (PORT datac (594:594:594) (647:647:647)) - (PORT datad (956:956:956) (961:961:961)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) (DELAY (ABSOLUTE - (PORT dataa (318:318:318) (338:338:338)) - (PORT datab (374:374:374) (425:425:425)) - (PORT datac (578:578:578) (573:573:573)) - (PORT datad (371:371:371) (410:410:410)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT datab (377:377:377) (423:423:423)) - (PORT datad (170:170:170) (198:198:198)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (903:903:903) (898:898:898)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (656:656:656) (654:654:654)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (307:307:307)) - (PORT datab (849:849:849) (897:897:897)) - (PORT datad (529:529:529) (521:521:521)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (418:418:418) (443:443:443)) - (PORT datac (195:195:195) (262:262:262)) - (PORT datad (286:286:286) (292:292:292)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (614:614:614)) - (PORT datab (369:369:369) (390:390:390)) - (PORT datac (1526:1526:1526) (1603:1603:1603)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) - (DELAY - (ABSOLUTE - (PORT datac (1379:1379:1379) (1407:1407:1407)) - (PORT datad (569:569:569) (570:570:570)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1365:1365:1365)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1358:1358:1358)) - (PORT ena (2262:2262:2262) (2221:2221:2221)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) - (DELAY - (ABSOLUTE - (PORT datac (574:574:574) (571:571:571)) - (PORT datad (352:352:352) (389:389:389)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (243:243:243)) - (PORT datab (1043:1043:1043) (1031:1031:1031)) - (PORT datac (597:597:597) (630:630:630)) - (PORT datad (997:997:997) (981:981:981)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (685:685:685)) - (PORT datab (195:195:195) (232:232:232)) - (PORT datac (207:207:207) (281:281:281)) - (PORT datad (747:747:747) (727:727:727)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT asdata (877:877:877) (861:861:861)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (306:306:306)) - (PORT datab (568:568:568) (584:584:584)) - (PORT datad (820:820:820) (871:871:871)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (903:903:903) (898:898:898)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (421:421:421) (436:436:436)) - (PORT datac (295:295:295) (303:303:303)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (614:614:614)) (PORT datab (181:181:181) (213:213:213)) - (PORT datac (1530:1530:1530) (1611:1611:1611)) - (PORT datad (338:338:338) (354:354:354)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datac (848:848:848) (853:853:853)) + (PORT datad (216:216:216) (249:249:249)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) (DELAY (ABSOLUTE - (PORT dataa (624:624:624) (630:630:630)) - (PORT datac (1378:1378:1378) (1411:1411:1411)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (591:591:591) (624:624:624)) + (PORT datab (1065:1065:1065) (1080:1080:1080)) + (PORT datac (386:386:386) (440:440:440)) + (PORT datad (617:617:617) (636:636:636)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) (DELAY (ABSOLUTE - (PORT datab (981:981:981) (963:963:963)) - (PORT datac (313:313:313) (321:321:321)) - (PORT datad (1232:1232:1232) (1233:1233:1233)) + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (1030:1030:1030) (1049:1049:1049)) + (PORT datac (560:560:560) (551:551:551)) + (PORT datad (584:584:584) (585:585:585)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1201:1201:1201)) + (PORT datab (217:217:217) (269:269:269)) + (PORT datac (885:885:885) (895:895:895)) + (PORT datad (305:305:305) (313:313:313)) + (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -30083,29 +28311,674 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) + (INSTANCE z80_\|alu_\|db\[6\]\~22) (DELAY (ABSOLUTE - (PORT dataa (745:745:745) (721:721:721)) - (PORT datab (1442:1442:1442) (1494:1494:1494)) - (PORT datad (178:178:178) (201:201:201)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1174:1174:1174) (1204:1204:1204)) + (PORT datab (895:895:895) (906:906:906)) + (PORT datac (1476:1476:1476) (1517:1517:1517)) + (PORT datad (802:802:802) (796:796:796)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) + (INSTANCE z80_\|alu_\|db\[6\]\~23) (DELAY (ABSOLUTE - (PORT dataa (1302:1302:1302) (1322:1322:1322)) - (PORT datab (801:801:801) (818:818:818)) - (PORT datac (1082:1082:1082) (1140:1140:1140)) + (PORT dataa (601:601:601) (599:599:599)) + (PORT datab (911:911:911) (924:924:924)) + (PORT datac (295:295:295) (308:308:308)) + (PORT datad (204:204:204) (246:246:246)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (410:410:410)) + (PORT datab (239:239:239) (308:308:308)) + (PORT datac (213:213:213) (280:280:280)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1094:1094:1094)) + (PORT datab (609:609:609) (601:601:601)) + (PORT datac (589:589:589) (613:613:613)) + (PORT datad (211:211:211) (277:277:277)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1068:1068:1068)) + (PORT datab (822:822:822) (846:846:846)) + (PORT datac (599:599:599) (610:610:610)) + (PORT datad (817:817:817) (808:808:808)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (856:856:856) (838:838:838)) + (PORT datac (1032:1032:1032) (1039:1039:1039)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (902:902:902)) + (PORT datab (874:874:874) (880:880:880)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (817:817:817) (818:818:818)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (638:638:638)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1481:1481:1481) (1435:1435:1435)) + (PORT datad (802:802:802) (786:786:786)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (584:584:584)) + (PORT datab (1154:1154:1154) (1156:1156:1156)) + (PORT datac (1065:1065:1065) (1071:1071:1071)) + (PORT datad (315:315:315) (325:325:325)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) + (DELAY + (ABSOLUTE + (PORT datab (249:249:249) (313:313:313)) + (PORT datad (228:228:228) (264:264:264)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1390:1390:1390) (1361:1361:1361)) + (PORT ena (1156:1156:1156) (1147:1147:1147)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1144:1144:1144)) + (PORT datab (1113:1113:1113) (1145:1145:1145)) + (PORT datac (1126:1126:1126) (1169:1169:1169)) + (PORT datad (248:248:248) (311:311:311)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (443:443:443)) + (PORT datab (179:179:179) (212:212:212)) + (PORT datac (1067:1067:1067) (1059:1059:1059)) + (PORT datad (1086:1086:1086) (1100:1100:1100)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (940:940:940)) + (PORT datab (1082:1082:1082) (1085:1085:1085)) + (PORT datac (627:627:627) (642:642:642)) + (PORT datad (580:580:580) (596:596:596)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (806:806:806) (794:794:794)) + (PORT datac (873:873:873) (899:899:899)) + (PORT datad (195:195:195) (224:224:224)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1236:1236:1236)) + (PORT datab (1913:1913:1913) (2038:2038:2038)) + (PORT datac (758:758:758) (794:794:794)) + (PORT datad (845:845:845) (866:866:866)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (1172:1172:1172) (1168:1168:1168)) + (PORT datac (1298:1298:1298) (1286:1286:1286)) + (PORT datad (841:841:841) (874:874:874)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (218:218:218)) + (PORT datab (220:220:220) (254:254:254)) + (PORT datac (1794:1794:1794) (1850:1850:1850)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (824:824:824)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (578:578:578) (585:585:585)) + (PORT datad (883:883:883) (899:899:899)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~37) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (985:985:985)) + (PORT datab (983:983:983) (994:994:994)) + (PORT datac (972:972:972) (942:942:942)) + (PORT datad (583:583:583) (575:575:575)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (946:946:946)) + (PORT datab (1050:1050:1050) (1021:1021:1021)) + (PORT datac (862:862:862) (936:936:936)) + (PORT datad (981:981:981) (970:970:970)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~38) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (822:822:822)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (502:502:502) (489:489:489)) + (PORT datad (502:502:502) (495:495:495)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (627:627:627)) + (PORT datab (825:825:825) (839:839:839)) + (PORT datac (1827:1827:1827) (1808:1808:1808)) + (PORT datad (771:771:771) (749:749:749)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~3) + (DELAY + (ABSOLUTE + (PORT datab (770:770:770) (793:793:793)) + (PORT datac (574:574:574) (598:598:598)) + (PORT datad (187:187:187) (216:216:216)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (253:253:253)) + (PORT datab (214:214:214) (257:257:257)) + (PORT datac (328:328:328) (343:343:343)) + (PORT datad (982:982:982) (974:974:974)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (711:711:711)) + (PORT datab (1492:1492:1492) (1462:1462:1462)) + (PORT datac (571:571:571) (584:584:584)) + (PORT datad (509:509:509) (507:507:507)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT datab (517:517:517) (515:515:515)) + (PORT datac (1224:1224:1224) (1208:1208:1208)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (964:964:964)) + (PORT datab (543:543:543) (527:527:527)) + (PORT datac (728:728:728) (703:703:703)) + (PORT datad (717:717:717) (688:688:688)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1378:1378:1378)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1189:1189:1189) (1191:1191:1191)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (758:758:758) (781:781:781)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1409:1409:1409) (1375:1375:1375)) + (PORT ena (1071:1071:1071) (1043:1043:1043)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT asdata (1135:1135:1135) (1150:1150:1150)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1217:1217:1217) (1223:1223:1223)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (871:871:871)) + (PORT datad (196:196:196) (253:253:253)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~4) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (254:254:254)) + (PORT datab (653:653:653) (703:703:703)) + (PORT datac (796:796:796) (805:805:805)) + (PORT datad (998:998:998) (1024:1024:1024)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1744:1744:1744) (1744:1744:1744)) + (PORT datab (1365:1365:1365) (1377:1377:1377)) + (PORT datac (1368:1368:1368) (1420:1420:1420)) + (PORT datad (1779:1779:1779) (1810:1810:1810)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (1058:1058:1058)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (180:180:180) (214:214:214)) + (PORT datad (631:631:631) (673:673:673)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~9) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (798:798:798)) + (PORT datab (1077:1077:1077) (1094:1094:1094)) + (PORT datac (766:766:766) (763:763:763)) + (PORT datad (743:743:743) (727:727:727)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1378:1378:1378)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1189:1189:1189) (1191:1191:1191)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (201:201:201) (258:258:258)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1378:1378:1378)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1189:1189:1189) (1191:1191:1191)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT asdata (525:525:525) (588:588:588)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1217:1217:1217) (1223:1223:1223)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) + (DELAY + (ABSOLUTE + (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT asdata (511:511:511) (578:578:578)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1217:1217:1217) (1223:1223:1223)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|iorq\~0) + (DELAY + (ABSOLUTE + (PORT datab (226:226:226) (298:298:298)) + (PORT datad (568:568:568) (588:588:588)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -30114,13 +28987,13 @@ (INSTANCE z80_\|execute_\|fIORead\~1) (DELAY (ABSOLUTE - (PORT dataa (1689:1689:1689) (1683:1683:1683)) - (PORT datab (1066:1066:1066) (1104:1104:1104)) - (PORT datac (1819:1819:1819) (1853:1853:1853)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (202:202:202) (239:239:239)) + (PORT datab (877:877:877) (922:922:922)) + (PORT datac (350:350:350) (355:355:355)) + (PORT datad (198:198:198) (220:220:220)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -30130,13 +29003,13 @@ (INSTANCE z80_\|execute_\|fIORead\~2) (DELAY (ABSOLUTE - (PORT dataa (368:368:368) (373:373:373)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (815:815:815) (826:826:826)) - (PORT datad (835:835:835) (849:849:849)) + (PORT dataa (823:823:823) (813:813:813)) + (PORT datab (193:193:193) (235:235:235)) + (PORT datac (1101:1101:1101) (1087:1087:1087)) + (PORT datad (1018:1018:1018) (1021:1021:1021)) (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -30146,10 +29019,10 @@ (INSTANCE z80_\|execute_\|fIORead\~0) (DELAY (ABSOLUTE - (PORT dataa (548:548:548) (556:556:556)) - (PORT datab (1066:1066:1066) (1105:1105:1105)) - (PORT datac (1817:1817:1817) (1849:1849:1849)) - (PORT datad (517:517:517) (513:513:513)) + (PORT dataa (1748:1748:1748) (1738:1738:1738)) + (PORT datab (1405:1405:1405) (1431:1431:1431)) + (PORT datac (2026:2026:2026) (2020:2020:2020)) + (PORT datad (190:190:190) (219:219:219)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -30162,195 +29035,107 @@ (INSTANCE z80_\|execute_\|fIORead\~3) (DELAY (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (890:890:890) (917:917:917)) - (PORT datac (1138:1138:1138) (1095:1095:1095)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (201:201:201) (237:237:237)) + (PORT datab (312:312:312) (331:331:331)) + (PORT datac (535:535:535) (526:526:526)) + (PORT datad (330:330:330) (340:340:340)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) (DELAY (ABSOLUTE - (PORT dataa (993:993:993) (958:958:958)) - (PORT datab (188:188:188) (224:224:224)) - (PORT datac (1091:1091:1091) (1146:1146:1146)) - (PORT datad (975:975:975) (956:956:956)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT clk (1362:1362:1362) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1371:1371:1371)) + (PORT ena (1671:1671:1671) (1677:1677:1677)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) + (DELAY + (ABSOLUTE + (PORT datad (545:545:545) (566:566:566)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT dataa (1295:1295:1295) (1318:1318:1318)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (1091:1091:1091) (1147:1147:1147)) - (PORT datad (1026:1026:1026) (1049:1049:1049)) + (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1217:1217:1217) (1223:1223:1223)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1378:1378:1378)) + (PORT asdata (512:512:512) (579:579:579)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1189:1189:1189) (1191:1191:1191)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1338:1338:1338) (1362:1362:1362)) + (PORT datab (227:227:227) (299:299:299)) + (PORT datad (1375:1375:1375) (1395:1395:1395)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (518:518:518) (589:589:589)) - (PORT sload (1762:1762:1762) (1778:1778:1778)) - (PORT ena (1755:1755:1755) (1705:1705:1705)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (1118:1118:1118) (1133:1133:1133)) - (PORT datad (2487:2487:2487) (2574:2574:2574)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT datab (245:245:245) (330:330:330)) - (PORT datac (614:614:614) (672:672:672)) - (PORT datad (302:302:302) (313:313:313)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (621:621:621)) - (PORT datab (284:284:284) (369:369:369)) - (PORT datac (866:866:866) (889:889:889)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (670:670:670)) - (PORT datab (434:434:434) (485:485:485)) - (PORT datac (1012:1012:1012) (1033:1033:1033)) - (PORT datad (1089:1089:1089) (1107:1107:1107)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) - (DELAY - (ABSOLUTE - (PORT dataa (664:664:664) (695:695:695)) - (PORT datab (184:184:184) (218:218:218)) - (PORT datad (1082:1082:1082) (1100:1100:1100)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (732:732:732)) - (PORT datab (562:562:562) (556:556:556)) - (PORT datad (769:769:769) (753:753:753)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) + (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) (DELAY (ABSOLUTE - (PORT dataa (677:677:677) (734:734:734)) - (PORT datab (391:391:391) (452:452:452)) - (PORT datac (871:871:871) (890:890:890)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (622:622:622)) - (PORT datab (891:891:891) (908:908:908)) - (PORT datac (826:826:826) (855:855:855)) - (PORT datad (373:373:373) (396:396:396)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (312:312:312) (336:336:336)) + (PORT datab (331:331:331) (350:350:350)) + (PORT datac (957:957:957) (925:925:925)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -30358,176 +29143,39 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (INSTANCE Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (864:864:864) (895:895:895)) - (PORT datab (907:907:907) (924:924:924)) - (PORT datac (871:871:871) (890:890:890)) - (PORT datad (680:680:680) (736:736:736)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (736:736:736)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (805:805:805) (832:832:832)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (224:224:224)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (523:523:523) (516:516:516)) - (PORT datab (1443:1443:1443) (1489:1489:1489)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (872:872:872) (905:905:905)) - (PORT sload (1762:1762:1762) (1778:1778:1778)) - (PORT ena (1755:1755:1755) (1705:1705:1705)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[14\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (2804:2804:2804) (2914:2914:2914)) - (PORT datac (1378:1378:1378) (1396:1396:1396)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (656:656:656)) - (PORT datab (795:795:795) (793:793:793)) - (PORT datac (570:570:570) (592:592:592)) - (PORT datad (844:844:844) (856:856:856)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (727:727:727)) - (PORT datab (246:246:246) (330:330:330)) - (PORT datac (614:614:614) (671:671:671)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT datac (1063:1063:1063) (1094:1094:1094)) - (PORT datad (407:407:407) (454:454:454)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (650:650:650)) - (PORT datab (533:533:533) (528:528:528)) - (PORT datac (177:177:177) (208:208:208)) - (PORT datad (857:857:857) (872:872:872)) + (PORT dataa (1619:1619:1619) (1653:1653:1653)) + (PORT datab (1479:1479:1479) (1531:1531:1531)) + (PORT datac (1107:1107:1107) (1125:1125:1125)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2204:2204:2204) (2261:2261:2261)) + (PORT datad (935:935:935) (996:996:996)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) + (INSTANCE z80_\|execute_\|fMWrite\~5) (DELAY (ABSOLUTE - (PORT datab (831:831:831) (822:822:822)) - (PORT datac (591:591:591) (629:629:629)) - (PORT datad (1052:1052:1052) (1051:1051:1051)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT datab (1235:1235:1235) (1290:1290:1290)) + (PORT datac (2660:2660:2660) (2719:2719:2719)) + (PORT datad (2283:2283:2283) (2440:2440:2440)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -30535,90 +29183,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) + (INSTANCE z80_\|execute_\|fMWrite\~6) (DELAY (ABSOLUTE - (PORT dataa (617:617:617) (676:676:676)) - (PORT datab (361:361:361) (364:364:364)) - (PORT datad (418:418:418) (476:476:476)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (1467:1467:1467) (1501:1501:1501)) - (PORT datad (325:325:325) (345:345:345)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1635:1635:1635) (1693:1693:1693)) - (PORT sload (1544:1544:1544) (1580:1580:1580)) - (PORT ena (1951:1951:1951) (1924:1924:1924)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (3060:3060:3060) (3154:3154:3154)) - (PORT datad (810:810:810) (831:831:831)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (514:514:514)) - (PORT datac (606:606:606) (631:631:631)) - (PORT datad (813:813:813) (828:828:828)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT dataa (354:354:354) (361:361:361)) + (PORT datab (801:801:801) (795:795:795)) + (PORT datac (880:880:880) (918:918:918)) + (PORT datad (988:988:988) (949:949:949)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -30626,14 +29199,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (INSTANCE z80_\|execute_\|fMWrite\~2) (DELAY (ABSOLUTE - (PORT dataa (566:566:566) (550:550:550)) - (PORT datab (1014:1014:1014) (1033:1033:1033)) - (PORT datac (374:374:374) (428:428:428)) - (PORT datad (575:575:575) (575:575:575)) - (IOPATH dataa combout (272:272:272) (269:269:269)) + (PORT dataa (859:859:859) (914:914:914)) + (PORT datac (1100:1100:1100) (1137:1137:1137)) + (PORT datad (1867:1867:1867) (1908:1908:1908)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1350:1350:1350) (1340:1340:1340)) + (PORT datab (842:842:842) (882:882:882)) + (PORT datac (334:334:334) (340:340:340)) + (PORT datad (176:176:176) (197:197:197)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (658:658:658)) + (PORT datab (776:776:776) (772:772:772)) + (PORT datac (808:808:808) (793:793:793)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1151:1151:1151) (1196:1196:1196)) + (PORT datab (804:804:804) (788:788:788)) + (PORT datac (1202:1202:1202) (1187:1187:1187)) + (PORT datad (579:579:579) (611:611:611)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -30642,92 +29261,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (672:672:672)) - (PORT datab (203:203:203) (236:236:236)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (181:181:181) (218:218:218)) + (PORT datab (1011:1011:1011) (984:984:984)) + (PORT datac (342:342:342) (353:353:353)) + (PORT datad (1653:1653:1653) (1697:1697:1697)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (INSTANCE z80_\|execute_\|fMWrite\~7) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (239:239:239)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datad (1425:1425:1425) (1461:1461:1461)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (711:711:711) (768:768:768)) - (PORT sload (1544:1544:1544) (1580:1580:1580)) - (PORT ena (1951:1951:1951) (1924:1924:1924)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[11\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (3061:3061:3061) (3158:3158:3158)) - (PORT datad (1354:1354:1354) (1401:1401:1401)) + (PORT datab (851:851:851) (867:867:867)) + (PORT datac (798:798:798) (800:800:800)) + (PORT datad (722:722:722) (701:701:701)) (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (293:293:293)) - (PORT datab (844:844:844) (856:856:856)) - (PORT datac (193:193:193) (259:259:259)) - (PORT datad (752:752:752) (743:743:743)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -30735,41 +29291,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) (DELAY (ABSOLUTE - (PORT dataa (626:626:626) (671:671:671)) - (PORT datac (879:879:879) (908:908:908)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (698:698:698)) - (PORT datab (886:886:886) (917:917:917)) - (PORT datad (390:390:390) (447:447:447)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (874:874:874)) - (PORT datab (562:562:562) (549:549:549)) - (PORT datac (864:864:864) (869:869:869)) - (PORT datad (499:499:499) (491:491:491)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (1398:1398:1398) (1438:1438:1438)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (1584:1584:1584) (1587:1587:1587)) + (PORT datad (811:811:811) (816:816:816)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -30777,331 +29307,93 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) (DELAY (ABSOLUTE - (PORT dataa (204:204:204) (243:243:243)) - (PORT datab (189:189:189) (227:227:227)) - (PORT datad (653:653:653) (701:701:701)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (385:385:385)) - (PORT datab (1464:1464:1464) (1499:1499:1499)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (704:704:704) (749:749:749)) - (PORT sload (1544:1544:1544) (1580:1580:1580)) - (PORT ena (1951:1951:1951) (1924:1924:1924)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (2264:2264:2264) (2330:2330:2330)) - (PORT datad (2316:2316:2316) (2324:2324:2324)) + (PORT dataa (1336:1336:1336) (1339:1339:1339)) + (PORT datab (1075:1075:1075) (1065:1065:1065)) + (PORT datac (828:828:828) (827:827:827)) + (PORT datad (722:722:722) (703:703:703)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1395:1395:1395) (1436:1436:1436)) + (PORT datab (1065:1065:1065) (1092:1092:1092)) + (PORT datac (1018:1018:1018) (1007:1007:1007)) + (PORT datad (562:562:562) (576:576:576)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1202:1202:1202)) + (PORT datab (797:797:797) (811:811:811)) + (PORT datac (1565:1565:1565) (1576:1576:1576)) + (PORT datad (238:238:238) (287:287:287)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1062:1062:1062) (1058:1058:1058)) + (PORT datab (192:192:192) (233:233:233)) + (PORT datac (174:174:174) (205:205:205)) + (PORT datad (576:576:576) (591:591:591)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) (DELAY (ABSOLUTE (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (1446:1446:1446) (1494:1494:1494)) - (PORT datad (300:300:300) (300:300:300)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1340:1340:1340) (1335:1335:1335)) - (PORT sload (1762:1762:1762) (1778:1778:1778)) - (PORT ena (1755:1755:1755) (1705:1705:1705)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~23) - (DELAY - (ABSOLUTE - (PORT datac (2775:2775:2775) (2893:2893:2893)) - (PORT datad (1365:1365:1365) (1387:1387:1387)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (936:936:936)) - (PORT datab (1016:1016:1016) (1040:1040:1040)) - (PORT datad (810:810:810) (828:828:828)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT datab (283:283:283) (365:365:365)) - (PORT datac (580:580:580) (594:594:594)) - (PORT datad (866:866:866) (888:888:888)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (951:951:951) (935:935:935)) - (PORT datab (1109:1109:1109) (1103:1103:1103)) - (PORT datad (847:847:847) (890:890:890)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (734:734:734)) - (PORT datab (391:391:391) (453:453:453)) - (PORT datac (836:836:836) (863:863:863)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (188:188:188) (224:224:224)) - (PORT datad (289:289:289) (292:292:292)) + (PORT datab (202:202:202) (237:237:237)) + (PORT datac (977:977:977) (948:948:948)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (774:774:774) (799:799:799)) - (PORT datab (1332:1332:1332) (1329:1329:1329)) - (PORT datac (788:788:788) (802:802:802)) - (PORT datad (199:199:199) (257:257:257)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (INSTANCE z80_\|execute_\|fMWrite\~8) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datad (1426:1426:1426) (1466:1466:1466)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (906:906:906) (955:955:955)) - (PORT sload (1544:1544:1544) (1580:1580:1580)) - (PORT ena (1951:1951:1951) (1924:1924:1924)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~19) - (DELAY - (ABSOLUTE - (PORT datac (1541:1541:1541) (1554:1554:1554)) - (PORT datad (2220:2220:2220) (2275:2275:2275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (180:180:180) (216:216:216)) - (PORT datab (742:742:742) (737:737:737)) - (PORT datad (1584:1584:1584) (1614:1614:1614)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2466:2466:2466) (2469:2469:2469)) - (PORT sload (1634:1634:1634) (1655:1655:1655)) - (PORT ena (1565:1565:1565) (1535:1535:1535)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~20) - (DELAY - (ABSOLUTE - (PORT datac (792:792:792) (809:809:809)) - (PORT datad (2766:2766:2766) (2873:2873:2873)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (390:390:390) (456:456:456)) - (PORT datac (638:638:638) (696:696:696)) - (PORT datad (682:682:682) (740:740:740)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1014:1014:1014) (988:988:988)) + (PORT datab (798:798:798) (790:790:790)) + (PORT datac (562:562:562) (584:584:584)) + (PORT datad (1108:1108:1108) (1102:1102:1102)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -31109,167 +29401,111 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) (DELAY (ABSOLUTE - (PORT dataa (445:445:445) (513:513:513)) - (PORT datab (633:633:633) (655:655:655)) - (PORT datac (861:861:861) (887:887:887)) - (PORT datad (811:811:811) (824:824:824)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (933:933:933)) - (PORT datab (855:855:855) (886:886:886)) - (PORT datac (571:571:571) (602:602:602)) - (PORT datad (515:515:515) (498:498:498)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (365:365:365)) - (PORT datab (184:184:184) (216:216:216)) - (PORT datad (554:554:554) (544:544:544)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (619:619:619)) - (PORT datac (376:376:376) (431:431:431)) - (PORT datad (989:989:989) (995:995:995)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (641:641:641) (686:686:686)) - (PORT datac (869:869:869) (902:902:902)) - (PORT datad (1032:1032:1032) (1042:1042:1042)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (443:443:443) (514:514:514)) - (PORT datac (860:860:860) (887:887:887)) - (PORT datad (538:538:538) (526:526:526)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (683:683:683)) - (PORT datab (348:348:348) (354:354:354)) - (PORT datad (297:297:297) (290:290:290)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1892:1892:1892) (1870:1870:1870)) - (PORT datab (556:556:556) (548:548:548)) - (PORT datac (517:517:517) (537:537:537)) - (PORT datad (337:337:337) (368:368:368)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (551:551:551) (565:565:565)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (774:774:774) (751:751:751)) - (PORT datad (157:157:157) (178:178:178)) + (PORT dataa (833:833:833) (846:846:846)) + (PORT datab (189:189:189) (222:222:222)) + (PORT datac (543:543:543) (535:535:535)) + (PORT datad (180:180:180) (202:202:202)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (310:310:310) (316:316:316)) + (PORT datad (755:755:755) (755:755:755)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (811:811:811)) + (PORT datab (959:959:959) (991:991:991)) + (PORT datac (1017:1017:1017) (1007:1007:1007)) + (PORT datad (1035:1035:1035) (1028:1028:1028)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (223:223:223)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (538:538:538)) + (PORT datab (1030:1030:1030) (1034:1034:1034)) + (PORT datac (1583:1583:1583) (1587:1587:1587)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (650:650:650)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (574:574:574) (566:566:566)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (861:861:861) (857:857:857)) + (PORT datac (971:971:971) (1049:1049:1049)) + (PORT datad (1053:1053:1053) (1051:1051:1051)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -31280,7 +29516,7 @@ (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) (DELAY (ABSOLUTE - (PORT datad (788:788:788) (796:796:796)) + (PORT datad (203:203:203) (264:264:264)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -31290,9 +29526,9 @@ (INSTANCE z80_\|clk_delay_\|DFF_inst5) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1349:1349:1349) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1412:1412:1412) (1378:1378:1378)) + (PORT clrn (1408:1408:1408) (1374:1374:1374)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -31316,9 +29552,9 @@ (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1370:1370:1370)) + (PORT clk (1356:1356:1356) (1363:1363:1363)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1412:1412:1412) (1378:1378:1378)) + (PORT clrn (1408:1408:1408) (1374:1374:1374)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -31332,9 +29568,9 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (513:513:513) (580:580:580)) - (PORT clrn (1412:1412:1412) (1378:1378:1378)) + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT asdata (514:514:514) (581:581:581)) + (PORT clrn (1408:1408:1408) (1374:1374:1374)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -31343,624 +29579,244 @@ (HOLD asdata (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (651:651:651)) - (PORT datab (939:939:939) (923:923:923)) - (PORT datac (947:947:947) (921:921:921)) - (PORT datad (779:779:779) (784:784:784)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~8) - (DELAY - (ABSOLUTE - (PORT dataa (550:550:550) (561:561:561)) - (PORT datab (1064:1064:1064) (1038:1038:1038)) - (PORT datac (860:860:860) (891:891:891)) - (PORT datad (765:765:765) (744:744:744)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~9) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (503:503:503)) - (PORT datab (353:353:353) (362:362:362)) - (PORT datac (736:736:736) (745:745:745)) - (PORT datad (577:577:577) (590:590:590)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (1344:1344:1344) (1326:1326:1326)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (200:200:200) (258:258:258)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (1344:1344:1344) (1326:1326:1326)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (205:205:205) (264:264:264)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (1318:1318:1318) (1291:1291:1291)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1368:1368:1368)) - (PORT asdata (511:511:511) (577:577:577)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (1318:1318:1318) (1291:1291:1291)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|iorq\~0) - (DELAY - (ABSOLUTE - (PORT datab (226:226:226) (296:296:296)) - (PORT datad (204:204:204) (262:262:262)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (228:228:228) (303:303:303)) - (PORT datad (738:738:738) (709:709:709)) + (PORT dataa (229:229:229) (305:305:305)) + (PORT datad (572:572:572) (576:576:576)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (631:631:631)) - (PORT datab (785:785:785) (786:786:786)) - (PORT datac (580:580:580) (589:589:589)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1444:1444:1444) (1442:1442:1442)) - (PORT datab (865:865:865) (897:897:897)) - (PORT datac (865:865:865) (883:883:883)) - (PORT datad (792:792:792) (793:793:793)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (521:521:521) (503:503:503)) - (PORT datac (812:812:812) (817:817:817)) - (PORT datad (521:521:521) (512:512:512)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1136:1136:1136) (1180:1180:1180)) - (PORT datab (567:567:567) (580:580:580)) - (PORT datac (836:836:836) (865:865:865)) - (PORT datad (743:743:743) (714:714:714)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1066:1066:1066) (1074:1074:1074)) - (PORT datab (398:398:398) (407:407:407)) - (PORT datac (1572:1572:1572) (1598:1598:1598)) - (PORT datad (1134:1134:1134) (1084:1084:1084)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (596:596:596)) - (PORT datab (585:585:585) (608:608:608)) - (PORT datad (1752:1752:1752) (1644:1644:1644)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1090:1090:1090)) - (PORT datab (1329:1329:1329) (1319:1319:1319)) - (PORT datac (998:998:998) (991:991:991)) - (PORT datad (1320:1320:1320) (1359:1359:1359)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1640:1640:1640) (1593:1593:1593)) - (PORT datab (821:821:821) (822:822:822)) - (PORT datac (858:858:858) (917:917:917)) - (PORT datad (1089:1089:1089) (1132:1132:1132)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1136:1136:1136) (1175:1175:1175)) - (PORT datab (796:796:796) (776:776:776)) - (PORT datac (860:860:860) (921:921:921)) - (PORT datad (572:572:572) (593:593:593)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (977:977:977) (969:969:969)) - (PORT datab (799:799:799) (792:792:792)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~4) - (DELAY - (ABSOLUTE - (PORT datab (601:601:601) (625:625:625)) - (PORT datac (747:747:747) (736:736:736)) - (PORT datad (548:548:548) (538:538:538)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1216:1216:1216)) - (PORT datab (898:898:898) (915:915:915)) - (PORT datac (181:181:181) (216:216:216)) - (PORT datad (203:203:203) (234:234:234)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (593:593:593) (612:612:612)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (PORT ena (1314:1314:1314) (1290:1290:1290)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (339:339:339) (367:367:367)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (1318:1318:1318) (1291:1291:1291)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1368:1368:1368)) - (PORT asdata (520:520:520) (592:592:592)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (1318:1318:1318) (1291:1291:1291)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (234:234:234) (312:312:312)) - (PORT datac (195:195:195) (261:261:261)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1368:1368:1368)) - (PORT asdata (1683:1683:1683) (1637:1637:1637)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (1318:1318:1318) (1291:1291:1291)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) - (DELAY - (ABSOLUTE - (PORT datad (201:201:201) (259:259:259)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (1318:1318:1318) (1291:1291:1291)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1376:1376:1376)) - (PORT asdata (513:513:513) (580:580:580)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (1344:1344:1344) (1326:1326:1326)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (303:303:303)) - (PORT datab (861:861:861) (882:882:882)) - (PORT datad (641:641:641) (681:681:681)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (188:188:188) (225:225:225)) - (PORT datac (545:545:545) (550:550:550)) - (PORT datad (186:186:186) (210:210:210)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (1941:1941:1941) (1887:1887:1887)) - (PORT datab (1418:1418:1418) (1422:1422:1422)) - (PORT datac (2786:2786:2786) (2899:2899:2899)) - (PORT datad (2227:2227:2227) (2300:2300:2300)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1620:1620:1620) (1655:1655:1655)) + (PORT datab (1476:1476:1476) (1535:1535:1535)) + (PORT datac (1106:1106:1106) (1124:1124:1124)) + (PORT datad (1131:1131:1131) (1160:1160:1160)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1357:1357:1357)) - (PORT asdata (1542:1542:1542) (1542:1542:1542)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (200:200:200) (258:258:258)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ExtRamWE\~0) (DELAY (ABSOLUTE - (PORT dataa (2378:2378:2378) (2409:2409:2409)) - (PORT datab (2805:2805:2805) (2916:2916:2916)) - (PORT datac (1650:1650:1650) (1603:1603:1603)) - (PORT datad (1629:1629:1629) (1637:1637:1637)) + (PORT dataa (1619:1619:1619) (1653:1653:1653)) + (PORT datab (1479:1479:1479) (1531:1531:1531)) + (PORT datac (1107:1107:1107) (1125:1125:1125)) + (PORT datad (1130:1130:1130) (1159:1159:1159)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1673:1673:1673) (1606:1606:1606)) + (PORT datab (793:793:793) (773:773:773)) + (PORT datad (312:312:312) (319:319:319)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (920:920:920)) + (PORT datab (921:921:921) (968:968:968)) + (PORT datac (1740:1740:1740) (1842:1842:1842)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1646:1646:1646)) + (PORT datab (908:908:908) (918:918:918)) + (PORT datac (878:878:878) (894:894:894)) + (PORT datad (1117:1117:1117) (1116:1116:1116)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (919:919:919)) + (PORT datab (922:922:922) (968:968:968)) + (PORT datac (1740:1740:1740) (1842:1842:1842)) + (PORT datad (573:573:573) (588:588:588)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (544:544:544) (617:617:617)) + (PORT sload (1041:1041:1041) (1053:1053:1053)) + (PORT ena (1068:1068:1068) (1021:1021:1021)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1116:1116:1116)) + (PORT datad (1866:1866:1866) (1899:1899:1899)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1672:1672:1672) (1604:1604:1604)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datad (304:304:304) (299:299:299)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (532:532:532) (598:598:598)) + (PORT sload (1041:1041:1041) (1053:1053:1053)) + (PORT ena (1068:1068:1068) (1021:1021:1021)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (1891:1891:1891) (1933:1933:1933)) + (PORT datad (1054:1054:1054) (1082:1082:1082)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1672:1672:1672) (1607:1607:1607)) + (PORT datab (319:319:319) (332:332:332)) + (PORT datad (517:517:517) (497:497:497)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (520:520:520) (588:588:588)) + (PORT sload (1041:1041:1041) (1053:1053:1053)) + (PORT ena (1068:1068:1068) (1021:1021:1021)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (1530:1530:1530) (1544:1544:1544)) + (PORT datac (1457:1457:1457) (1454:1454:1454)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (302:302:302)) - (PORT datab (211:211:211) (265:265:265)) - (PORT datac (204:204:204) (252:252:252)) - (PORT datad (1079:1079:1079) (1095:1095:1095)) + (PORT dataa (630:630:630) (659:659:659)) + (PORT datab (230:230:230) (284:284:284)) + (PORT datac (331:331:331) (358:358:358)) + (PORT datad (1200:1200:1200) (1152:1152:1152)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -31973,11 +29829,23 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (2804:2804:2804) (2917:2917:2917)) - (PORT datac (1378:1378:1378) (1398:1398:1398)) - (PORT datad (1369:1369:1369) (1389:1389:1389)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (1881:1881:1881) (1928:1928:1928)) + (PORT datac (1050:1050:1050) (1076:1076:1076)) + (PORT datad (1051:1051:1051) (1083:1083:1083)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (880:880:880)) + (PORT datad (1844:1844:1844) (1865:1865:1865)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -31987,9 +29855,9 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1630:1630:1630) (1654:1654:1654)) - (PORT datab (864:864:864) (879:879:879)) - (PORT datad (164:164:164) (187:187:187)) + (PORT dataa (799:799:799) (793:793:793)) + (PORT datab (348:348:348) (356:356:356)) + (PORT datad (316:316:316) (308:308:308)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -32001,11 +29869,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1366:1366:1366)) + (PORT clk (1370:1370:1370) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1146:1146:1146) (1164:1164:1164)) - (PORT sload (1634:1634:1634) (1655:1655:1655)) - (PORT ena (1565:1565:1565) (1535:1535:1535)) + (PORT asdata (1041:1041:1041) (1043:1043:1043)) + (PORT sload (1115:1115:1115) (1155:1155:1155)) + (PORT ena (1333:1333:1333) (1296:1296:1296)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -32021,9 +29889,9 @@ (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) (DELAY (ABSOLUTE - (PORT datac (991:991:991) (1050:1050:1050)) - (PORT datad (3020:3020:3020) (3091:3091:3091)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1659:1659:1659) (1683:1683:1683)) + (PORT datad (623:623:623) (656:656:656)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -32033,11 +29901,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (557:557:557) (555:555:555)) - (PORT datab (1446:1446:1446) (1490:1490:1490)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (802:802:802) (794:794:794)) + (PORT datab (560:560:560) (552:552:552)) + (PORT datad (491:491:491) (483:483:483)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -32047,11 +29915,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1358:1358:1358)) + (PORT clk (1370:1370:1370) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1131:1131:1131) (1146:1146:1146)) - (PORT sload (1762:1762:1762) (1778:1778:1778)) - (PORT ena (1755:1755:1755) (1705:1705:1705)) + (PORT asdata (915:915:915) (930:930:930)) + (PORT sload (1115:1115:1115) (1155:1155:1155)) + (PORT ena (1333:1333:1333) (1296:1296:1296)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -32067,8 +29935,8 @@ (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) (DELAY (ABSOLUTE - (PORT datac (2754:2754:2754) (2821:2821:2821)) - (PORT datad (1033:1033:1033) (1052:1052:1052)) + (PORT datac (1617:1617:1617) (1642:1642:1642)) + (PORT datad (587:587:587) (619:619:619)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -32079,11 +29947,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (1440:1440:1440) (1487:1487:1487)) - (PORT datad (751:751:751) (729:729:729)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (805:805:805) (801:801:801)) + (PORT datab (498:498:498) (489:489:489)) + (PORT datad (310:310:310) (319:319:319)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -32093,11 +29961,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1358:1358:1358)) + (PORT clk (1370:1370:1370) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (652:652:652) (696:696:696)) - (PORT sload (1762:1762:1762) (1778:1778:1778)) - (PORT ena (1755:1755:1755) (1705:1705:1705)) + (PORT asdata (688:688:688) (723:723:723)) + (PORT sload (1115:1115:1115) (1155:1155:1155)) + (PORT ena (1333:1333:1333) (1296:1296:1296)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -32113,9 +29981,9 @@ (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) (DELAY (ABSOLUTE - (PORT datab (2261:2261:2261) (2327:2327:2327)) - (PORT datad (1323:1323:1323) (1347:1347:1347)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datac (1622:1622:1622) (1649:1649:1649)) + (PORT datad (336:336:336) (379:379:379)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -32125,11 +29993,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) (DELAY (ABSOLUTE - (PORT dataa (590:590:590) (603:603:603)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datad (1584:1584:1584) (1610:1610:1610)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (799:799:799) (793:793:793)) + (PORT datab (499:499:499) (494:494:494)) + (PORT datad (310:310:310) (321:321:321)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -32139,11 +30007,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1366:1366:1366)) + (PORT clk (1370:1370:1370) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1093:1093:1093) (1195:1195:1195)) - (PORT sload (1634:1634:1634) (1655:1655:1655)) - (PORT ena (1565:1565:1565) (1535:1535:1535)) + (PORT asdata (896:896:896) (916:916:916)) + (PORT sload (1115:1115:1115) (1155:1155:1155)) + (PORT ena (1333:1333:1333) (1296:1296:1296)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -32159,9 +30027,9 @@ (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) (DELAY (ABSOLUTE - (PORT datac (1407:1407:1407) (1449:1449:1449)) - (PORT datad (2217:2217:2217) (2272:2272:2272)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datac (1624:1624:1624) (1654:1654:1654)) + (PORT datad (595:595:595) (629:629:629)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -32171,11 +30039,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) (DELAY (ABSOLUTE - (PORT dataa (829:829:829) (825:825:825)) - (PORT datab (561:561:561) (564:564:564)) - (PORT datad (1335:1335:1335) (1357:1357:1357)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1261:1261:1261) (1230:1230:1230)) + (PORT datab (320:320:320) (332:332:332)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -32185,11 +30053,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1366:1366:1366)) + (PORT clk (1349:1349:1349) (1359:1359:1359)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (934:934:934) (973:973:973)) - (PORT sload (1483:1483:1483) (1482:1482:1482)) - (PORT ena (1820:1820:1820) (1773:1773:1773)) + (PORT asdata (922:922:922) (957:957:957)) + (PORT sload (1062:1062:1062) (1091:1091:1091)) + (PORT ena (1086:1086:1086) (1050:1050:1050)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -32205,10 +30073,10 @@ (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) (DELAY (ABSOLUTE - (PORT dataa (240:240:240) (314:314:314)) - (PORT datad (3021:3021:3021) (3094:3094:3094)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (1883:1883:1883) (1881:1881:1881)) + (PORT datac (621:621:621) (665:665:665)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -32217,11 +30085,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) (DELAY (ABSOLUTE - (PORT dataa (1630:1630:1630) (1653:1653:1653)) - (PORT datab (180:180:180) (211:211:211)) - (PORT datad (550:550:550) (552:552:552)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datad (1236:1236:1236) (1194:1194:1194)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -32231,11 +30099,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1366:1366:1366)) + (PORT clk (1349:1349:1349) (1359:1359:1359)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (875:875:875) (898:898:898)) - (PORT sload (1634:1634:1634) (1655:1655:1655)) - (PORT ena (1565:1565:1565) (1535:1535:1535)) + (PORT asdata (1061:1061:1061) (1067:1067:1067)) + (PORT sload (1062:1062:1062) (1091:1091:1091)) + (PORT ena (1086:1086:1086) (1050:1050:1050)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -32251,10 +30119,10 @@ (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) (DELAY (ABSOLUTE - (PORT datac (1180:1180:1180) (1212:1212:1212)) - (PORT datad (3018:3018:3018) (3121:3121:3121)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (641:641:641) (694:694:694)) + (PORT datac (1617:1617:1617) (1643:1643:1643)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -32263,11 +30131,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) (DELAY (ABSOLUTE - (PORT dataa (583:583:583) (598:598:598)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datad (1337:1337:1337) (1356:1356:1356)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1264:1264:1264) (1232:1232:1232)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -32277,11 +30145,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1366:1366:1366)) + (PORT clk (1349:1349:1349) (1359:1359:1359)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1148:1148:1148) (1172:1172:1172)) - (PORT sload (1483:1483:1483) (1482:1482:1482)) - (PORT ena (1820:1820:1820) (1773:1773:1773)) + (PORT asdata (1519:1519:1519) (1486:1486:1486)) + (PORT sload (1062:1062:1062) (1091:1091:1091)) + (PORT ena (1086:1086:1086) (1050:1050:1050)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -32297,20 +30165,250 @@ (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) (DELAY (ABSOLUTE - (PORT datab (3061:3061:3061) (3153:3153:3153)) - (PORT datad (1132:1132:1132) (1159:1159:1159)) + (PORT datac (1615:1615:1615) (1647:1647:1647)) + (PORT datad (854:854:854) (894:894:894)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (339:339:339)) + (PORT datab (1265:1265:1265) (1219:1219:1219)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) (DELAY (ABSOLUTE - (PORT d[0] (2159:2159:2159) (2163:2163:2163)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT clk (1349:1349:1349) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (536:536:536) (608:608:608)) + (PORT sload (1062:1062:1062) (1091:1091:1091)) + (PORT ena (1086:1086:1086) (1050:1050:1050)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (871:871:871) (913:913:913)) + (PORT datad (1856:1856:1856) (1888:1888:1888)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1294:1294:1294) (1266:1266:1266)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datad (511:511:511) (504:504:504)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (529:529:529) (605:605:605)) + (PORT sload (1033:1033:1033) (1049:1049:1049)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) + (DELAY + (ABSOLUTE + (PORT datac (1624:1624:1624) (1649:1649:1649)) + (PORT datad (626:626:626) (674:674:674)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (238:238:238)) + (PORT datab (532:532:532) (519:519:519)) + (PORT datad (1271:1271:1271) (1229:1229:1229)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (525:525:525) (601:601:601)) + (PORT sload (1033:1033:1033) (1049:1049:1049)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) + (DELAY + (ABSOLUTE + (PORT datac (844:844:844) (879:879:879)) + (PORT datad (1349:1349:1349) (1383:1383:1383)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (237:237:237)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datad (1268:1268:1268) (1227:1227:1227)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (842:842:842) (864:864:864)) + (PORT sload (1033:1033:1033) (1049:1049:1049)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (913:913:913)) + (PORT datad (1349:1349:1349) (1385:1385:1385)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (337:337:337)) + (PORT datab (756:756:756) (741:741:741)) + (PORT datad (1458:1458:1458) (1392:1392:1392)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (524:524:524) (596:596:596)) + (PORT sload (1041:1041:1041) (1053:1053:1053)) + (PORT ena (1068:1068:1068) (1021:1021:1021)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1657:1657:1657) (1678:1678:1678)) + (PORT datad (796:796:796) (826:826:826)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (942:942:942) (945:945:945)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) ) ) (TIMINGCHECK @@ -32319,23 +30417,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2551:2551:2551) (2642:2642:2642)) - (PORT d[1] (1537:1537:1537) (1624:1624:1624)) - (PORT d[2] (2641:2641:2641) (2742:2742:2742)) - (PORT d[3] (2194:2194:2194) (2323:2323:2323)) - (PORT d[4] (2102:2102:2102) (2156:2156:2156)) - (PORT d[5] (2563:2563:2563) (2664:2664:2664)) - (PORT d[6] (1627:1627:1627) (1660:1660:1660)) - (PORT d[7] (3770:3770:3770) (3843:3843:3843)) - (PORT d[8] (2263:2263:2263) (2314:2314:2314)) - (PORT d[9] (2622:2622:2622) (2652:2652:2652)) - (PORT d[10] (1762:1762:1762) (1809:1809:1809)) - (PORT d[11] (1768:1768:1768) (1821:1821:1821)) - (PORT d[12] (3133:3133:3133) (3159:3159:3159)) - (PORT clk (1639:1639:1639) (1668:1668:1668)) + (PORT d[0] (930:930:930) (940:940:940)) + (PORT d[1] (1926:1926:1926) (2072:2072:2072)) + (PORT d[2] (1357:1357:1357) (1362:1362:1362)) + (PORT d[3] (2658:2658:2658) (2763:2763:2763)) + (PORT d[4] (2440:2440:2440) (2546:2546:2546)) + (PORT d[5] (2926:2926:2926) (3031:3031:3031)) + (PORT d[6] (1266:1266:1266) (1301:1301:1301)) + (PORT d[7] (2683:2683:2683) (2727:2727:2727)) + (PORT d[8] (924:924:924) (930:930:930)) + (PORT d[9] (1474:1474:1474) (1500:1500:1500)) + (PORT d[10] (1486:1486:1486) (1519:1519:1519)) + (PORT d[11] (2077:2077:2077) (2152:2152:2152)) + (PORT d[12] (1485:1485:1485) (1526:1526:1526)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) ) ) (TIMINGCHECK @@ -32344,11 +30442,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2533:2533:2533) (2502:2502:2502)) - (PORT clk (1639:1639:1639) (1668:1668:1668)) + (PORT d[0] (876:876:876) (848:848:848)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) ) ) (TIMINGCHECK @@ -32357,60 +30455,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (PORT d[0] (2636:2636:2636) (2620:2620:2620)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (1323:1323:1323) (1298:1298:1298)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT clk (1644:1644:1644) (1671:1671:1671)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT clk (1644:1644:1644) (1671:1671:1671)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT clk (1644:1644:1644) (1671:1671:1671)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT clk (1644:1644:1644) (1671:1671:1671)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1606:1606:1606) (1634:1634:1634)) + (PORT clk (1607:1607:1607) (1634:1634:1634)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -32421,49 +30519,49 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (877:877:877) (881:881:881)) + (PORT clk (878:878:878) (881:881:881)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (878:878:878) (882:882:882)) + (PORT clk (879:879:879) (882:882:882)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (878:878:878) (882:882:882)) + (PORT clk (879:879:879) (882:882:882)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (878:878:878) (882:882:882)) + (PORT clk (879:879:879) (882:882:882)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) - (PORT asdata (1086:1086:1086) (1085:1085:1085)) + (PORT clk (1680:1680:1680) (1699:1699:1699)) + (PORT asdata (1873:1873:1873) (1892:1892:1892)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -32473,11 +30571,11 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) - (PORT asdata (505:505:505) (567:567:567)) + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT asdata (1325:1325:1325) (1320:1320:1320)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -32490,12 +30588,12 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (237:237:237) (299:299:299)) - (PORT datab (214:214:214) (268:268:268)) - (PORT datac (207:207:207) (252:252:252)) - (PORT datad (1076:1076:1076) (1092:1092:1092)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT dataa (630:630:630) (658:658:658)) + (PORT datab (231:231:231) (286:286:286)) + (PORT datac (332:332:332) (357:357:357)) + (PORT datad (1201:1201:1201) (1156:1156:1156)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -32506,9 +30604,9 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (2804:2804:2804) (2918:2918:2918)) - (PORT datac (1379:1379:1379) (1399:1399:1399)) - (PORT datad (1368:1368:1368) (1391:1391:1391)) + (PORT datab (1888:1888:1888) (1933:1933:1933)) + (PORT datac (1051:1051:1051) (1079:1079:1079)) + (PORT datad (1052:1052:1052) (1086:1086:1086)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -32517,11 +30615,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1356:1356:1356) (1335:1335:1335)) - (PORT clk (1627:1627:1627) (1656:1656:1656)) + (PORT d[0] (923:923:923) (927:927:927)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) ) ) (TIMINGCHECK @@ -32530,23 +30628,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2057:2057:2057) (2126:2126:2126)) - (PORT d[1] (2222:2222:2222) (2344:2344:2344)) - (PORT d[2] (1925:1925:1925) (2021:2021:2021)) - (PORT d[3] (3618:3618:3618) (3825:3825:3825)) - (PORT d[4] (1763:1763:1763) (1805:1805:1805)) - (PORT d[5] (3939:3939:3939) (4098:4098:4098)) - (PORT d[6] (2139:2139:2139) (2166:2166:2166)) - (PORT d[7] (2308:2308:2308) (2314:2314:2314)) - (PORT d[8] (3124:3124:3124) (3229:3229:3229)) - (PORT d[9] (2324:2324:2324) (2341:2341:2341)) - (PORT d[10] (1484:1484:1484) (1523:1523:1523)) - (PORT d[11] (2538:2538:2538) (2595:2595:2595)) - (PORT d[12] (1767:1767:1767) (1740:1740:1740)) - (PORT clk (1624:1624:1624) (1654:1654:1654)) + (PORT d[0] (930:930:930) (941:941:941)) + (PORT d[1] (1940:1940:1940) (2085:2085:2085)) + (PORT d[2] (3079:3079:3079) (3130:3130:3130)) + (PORT d[3] (2650:2650:2650) (2742:2742:2742)) + (PORT d[4] (2385:2385:2385) (2480:2480:2480)) + (PORT d[5] (2942:2942:2942) (3050:3050:3050)) + (PORT d[6] (1495:1495:1495) (1516:1516:1516)) + (PORT d[7] (2675:2675:2675) (2709:2709:2709)) + (PORT d[8] (950:950:950) (959:959:959)) + (PORT d[9] (2990:2990:2990) (3064:3064:3064)) + (PORT d[10] (1520:1520:1520) (1559:1559:1559)) + (PORT d[11] (1785:1785:1785) (1857:1857:1857)) + (PORT d[12] (1722:1722:1722) (1759:1759:1759)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) ) ) (TIMINGCHECK @@ -32555,11 +30653,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1939:1939:1939) (1936:1936:1936)) - (PORT clk (1624:1624:1624) (1654:1654:1654)) + (PORT d[0] (869:869:869) (834:834:834)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) ) ) (TIMINGCHECK @@ -32568,60 +30666,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1627:1627:1627) (1656:1656:1656)) - (PORT d[0] (2585:2585:2585) (2605:2605:2605)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (1538:1538:1538) (1499:1499:1499)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1628:1628:1628) (1657:1657:1657)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1628:1628:1628) (1657:1657:1657)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1628:1628:1628) (1657:1657:1657)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1628:1628:1628) (1657:1657:1657)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1591:1591:1591) (1620:1620:1620)) + (PORT clk (1604:1604:1604) (1632:1632:1632)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -32632,69 +30730,81 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (862:862:862) (867:867:867)) + (PORT clk (875:875:875) (879:879:879)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (863:863:863) (868:868:868)) + (PORT clk (876:876:876) (880:880:880)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (863:863:863) (868:868:868)) + (PORT clk (876:876:876) (880:880:880)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (863:863:863) (868:868:868)) + (PORT clk (876:876:876) (880:880:880)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) (DELAY (ABSOLUTE - (PORT dataa (304:304:304) (412:412:412)) - (PORT datab (1189:1189:1189) (1190:1190:1190)) - (PORT datac (1069:1069:1069) (1104:1104:1104)) - (PORT datad (825:825:825) (808:808:808)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT asdata (1357:1357:1357) (1368:1368:1368)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT asdata (641:641:641) (686:686:686)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (237:237:237) (296:296:296)) - (PORT datab (214:214:214) (268:268:268)) - (PORT datac (208:208:208) (249:249:249)) - (PORT datad (1074:1074:1074) (1090:1090:1090)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (631:631:631) (658:658:658)) + (PORT datab (234:234:234) (289:289:289)) + (PORT datac (334:334:334) (358:358:358)) + (PORT datad (1201:1201:1201) (1153:1153:1153)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -32705,22 +30815,22 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (2805:2805:2805) (2923:2923:2923)) - (PORT datac (1381:1381:1381) (1401:1401:1401)) - (PORT datad (1365:1365:1365) (1388:1388:1388)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datab (1882:1882:1882) (1925:1925:1925)) + (PORT datac (1050:1050:1050) (1074:1074:1074)) + (PORT datad (1050:1050:1050) (1082:1082:1082)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1584:1584:1584) (1560:1560:1560)) - (PORT clk (1634:1634:1634) (1661:1661:1661)) + (PORT d[0] (1107:1107:1107) (1120:1120:1120)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) ) ) (TIMINGCHECK @@ -32729,23 +30839,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1810:1810:1810) (1888:1888:1888)) - (PORT d[1] (2263:2263:2263) (2381:2381:2381)) - (PORT d[2] (1909:1909:1909) (2025:2025:2025)) - (PORT d[3] (3610:3610:3610) (3814:3814:3814)) - (PORT d[4] (1790:1790:1790) (1835:1835:1835)) - (PORT d[5] (4234:4234:4234) (4406:4406:4406)) - (PORT d[6] (1872:1872:1872) (1890:1890:1890)) - (PORT d[7] (2059:2059:2059) (2058:2058:2058)) - (PORT d[8] (3145:3145:3145) (3250:3250:3250)) - (PORT d[9] (2356:2356:2356) (2379:2379:2379)) - (PORT d[10] (2143:2143:2143) (2244:2244:2244)) - (PORT d[11] (2277:2277:2277) (2349:2349:2349)) - (PORT d[12] (1497:1497:1497) (1469:1469:1469)) - (PORT clk (1631:1631:1631) (1659:1659:1659)) + (PORT d[0] (3685:3685:3685) (3782:3782:3782)) + (PORT d[1] (1575:1575:1575) (1658:1658:1658)) + (PORT d[2] (3077:3077:3077) (3135:3135:3135)) + (PORT d[3] (1984:1984:1984) (2041:2041:2041)) + (PORT d[4] (1991:1991:1991) (2039:2039:2039)) + (PORT d[5] (1534:1534:1534) (1598:1598:1598)) + (PORT d[6] (1634:1634:1634) (1654:1654:1654)) + (PORT d[7] (2839:2839:2839) (2868:2868:2868)) + (PORT d[8] (3080:3080:3080) (3193:3193:3193)) + (PORT d[9] (1627:1627:1627) (1656:1656:1656)) + (PORT d[10] (2978:2978:2978) (3070:3070:3070)) + (PORT d[11] (1943:1943:1943) (1980:1980:1980)) + (PORT d[12] (1645:1645:1645) (1683:1683:1683)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) ) ) (TIMINGCHECK @@ -32754,11 +30864,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2140:2140:2140) (2075:2075:2075)) - (PORT clk (1631:1631:1631) (1659:1659:1659)) + (PORT d[0] (2067:2067:2067) (2031:2031:2031)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) ) ) (TIMINGCHECK @@ -32767,60 +30877,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1634:1634:1634) (1661:1661:1661)) - (PORT d[0] (2375:2375:2375) (2355:2355:2355)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + (PORT d[0] (2694:2694:2694) (2699:2699:2699)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT clk (1633:1633:1633) (1661:1661:1661)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT clk (1633:1633:1633) (1661:1661:1661)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT clk (1633:1633:1633) (1661:1661:1661)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT clk (1633:1633:1633) (1661:1661:1661)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1598:1598:1598) (1625:1625:1625)) + (PORT clk (1596:1596:1596) (1624:1624:1624)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -32831,51 +30941,67 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (869:869:869) (872:872:872)) + (PORT clk (867:867:867) (871:871:871)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (870:870:870) (873:873:873)) + (PORT clk (868:868:868) (872:872:872)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (870:870:870) (873:873:873)) + (PORT clk (868:868:868) (872:872:872)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (870:870:870) (873:873:873)) + (PORT clk (868:868:868) (872:872:872)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (548:548:548)) + (PORT datab (896:896:896) (943:943:943)) + (PORT datac (772:772:772) (757:757:757)) + (PORT datad (1051:1051:1051) (1082:1082:1082)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (240:240:240) (302:302:302)) - (PORT datab (209:209:209) (262:262:262)) - (PORT datac (203:203:203) (247:247:247)) - (PORT datad (1080:1080:1080) (1091:1091:1091)) + (PORT dataa (630:630:630) (663:663:663)) + (PORT datab (233:233:233) (288:288:288)) + (PORT datac (334:334:334) (361:361:361)) + (PORT datad (1200:1200:1200) (1155:1155:1155)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -32888,9 +31014,9 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (2804:2804:2804) (2917:2917:2917)) - (PORT datac (1380:1380:1380) (1399:1399:1399)) - (PORT datad (1366:1366:1366) (1388:1388:1388)) + (PORT datab (1891:1891:1891) (1933:1933:1933)) + (PORT datac (1053:1053:1053) (1077:1077:1077)) + (PORT datad (1055:1055:1055) (1083:1083:1083)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -32899,11 +31025,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1611:1611:1611) (1592:1592:1592)) - (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (1113:1113:1113) (1106:1106:1106)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) ) ) (TIMINGCHECK @@ -32912,23 +31038,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1796:1796:1796) (1862:1862:1862)) - (PORT d[1] (2499:2499:2499) (2625:2625:2625)) - (PORT d[2] (1961:1961:1961) (2073:2073:2073)) - (PORT d[3] (1397:1397:1397) (1421:1421:1421)) - (PORT d[4] (2050:2050:2050) (2104:2104:2104)) - (PORT d[5] (4236:4236:4236) (4407:4407:4407)) - (PORT d[6] (2129:2129:2129) (2150:2150:2150)) - (PORT d[7] (2032:2032:2032) (2028:2028:2028)) - (PORT d[8] (2858:2858:2858) (2958:2958:2958)) - (PORT d[9] (2657:2657:2657) (2693:2693:2693)) - (PORT d[10] (2097:2097:2097) (2188:2188:2188)) - (PORT d[11] (2258:2258:2258) (2321:2321:2321)) - (PORT d[12] (1483:1483:1483) (1444:1444:1444)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) + (PORT d[0] (3904:3904:3904) (3985:3985:3985)) + (PORT d[1] (2171:2171:2171) (2294:2294:2294)) + (PORT d[2] (2971:2971:2971) (2995:2995:2995)) + (PORT d[3] (2388:2388:2388) (2476:2476:2476)) + (PORT d[4] (2373:2373:2373) (2471:2471:2471)) + (PORT d[5] (2627:2627:2627) (2712:2712:2712)) + (PORT d[6] (1769:1769:1769) (1832:1832:1832)) + (PORT d[7] (2401:2401:2401) (2428:2428:2428)) + (PORT d[8] (3102:3102:3102) (3241:3241:3241)) + (PORT d[9] (2698:2698:2698) (2767:2767:2767)) + (PORT d[10] (4706:4706:4706) (4798:4798:4798)) + (PORT d[11] (1774:1774:1774) (1826:1826:1826)) + (PORT d[12] (1997:1997:1997) (2046:2046:2046)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) ) ) (TIMINGCHECK @@ -32937,11 +31063,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1583:1583:1583) (1531:1531:1531)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) + (PORT d[0] (1851:1851:1851) (1777:1777:1777)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) ) ) (TIMINGCHECK @@ -32950,60 +31076,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (PORT d[0] (2934:2934:2934) (2884:2884:2884)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (2025:2025:2025) (1959:1959:1959)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) + (PORT clk (1604:1604:1604) (1632:1632:1632)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -33014,53 +31140,53 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) + (PORT clk (875:875:875) (879:879:879)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) + (PORT clk (876:876:876) (880:880:880)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) + (PORT clk (876:876:876) (880:880:880)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) + (PORT clk (876:876:876) (880:880:880)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (INSTANCE D\[6\]\~91) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (1167:1167:1167) (1174:1174:1174)) - (PORT datac (1068:1068:1068) (1103:1103:1103)) - (PORT datad (1143:1143:1143) (1161:1161:1161)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (782:782:782) (763:763:763)) + (PORT datab (1311:1311:1311) (1347:1347:1347)) + (PORT datac (296:296:296) (303:303:303)) + (PORT datad (1025:1025:1025) (1001:1001:1001)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -33068,15 +31194,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (302:302:302)) - (PORT datab (211:211:211) (265:265:265)) - (PORT datac (204:204:204) (252:252:252)) - (PORT datad (1079:1079:1079) (1093:1093:1093)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (631:631:631) (658:658:658)) + (PORT datab (228:228:228) (282:282:282)) + (PORT datac (330:330:330) (356:356:356)) + (PORT datad (1201:1201:1201) (1152:1152:1152)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -33091,17 +31217,27 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (977:977:977) (979:979:979)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|vram_address\~0) (DELAY (ABSOLUTE - (PORT dataa (1101:1101:1101) (1118:1118:1118)) - (PORT datab (1379:1379:1379) (1366:1366:1366)) - (PORT datac (1098:1098:1098) (1111:1111:1111)) - (PORT datad (810:810:810) (830:830:830)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (1154:1154:1154) (1185:1185:1185)) + (PORT datab (896:896:896) (950:950:950)) + (PORT datac (885:885:885) (936:936:936)) + (PORT datad (252:252:252) (321:321:321)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -33112,14 +31248,14 @@ (INSTANCE ula_\|video_\|vram_address\[0\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) - (PORT asdata (1154:1154:1154) (1174:1174:1174)) - (PORT ena (857:857:857) (835:835:835)) + (PORT clk (1360:1360:1360) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1111:1111:1111) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -33128,9 +31264,9 @@ (INSTANCE ula_\|video_\|vram_address\[1\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) - (PORT asdata (1161:1161:1161) (1174:1174:1174)) - (PORT ena (857:857:857) (835:835:835)) + (PORT clk (1360:1360:1360) (1375:1375:1375)) + (PORT asdata (1110:1110:1110) (1132:1132:1132)) + (PORT ena (1111:1111:1111) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -33144,8 +31280,8 @@ (INSTANCE ula_\|video_\|vram_address\[2\]\~4) (DELAY (ABSOLUTE - (PORT datad (880:880:880) (918:918:918)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (833:833:833) (864:864:864)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -33154,9 +31290,9 @@ (INSTANCE ula_\|video_\|vram_address\[2\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1360:1360:1360) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (857:857:857) (835:835:835)) + (PORT ena (1111:1111:1111) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -33170,8 +31306,8 @@ (INSTANCE ula_\|video_\|Add3\~0) (DELAY (ABSOLUTE - (PORT datac (908:908:908) (938:938:938)) - (PORT datad (880:880:880) (918:918:918)) + (PORT datac (829:829:829) (860:860:860)) + (PORT datad (1338:1338:1338) (1335:1335:1335)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -33182,9 +31318,9 @@ (INSTANCE ula_\|video_\|vram_address\[3\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1360:1360:1360) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (857:857:857) (835:835:835)) + (PORT ena (1111:1111:1111) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -33198,10 +31334,10 @@ (INSTANCE ula_\|video_\|Add3\~1) (DELAY (ABSOLUTE - (PORT dataa (890:890:890) (920:920:920)) - (PORT datac (904:904:904) (933:933:933)) - (PORT datad (876:876:876) (913:913:913)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (866:866:866) (895:895:895)) + (PORT datac (1295:1295:1295) (1303:1303:1303)) + (PORT datad (1339:1339:1339) (1335:1335:1335)) + (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -33212,9 +31348,9 @@ (INSTANCE ula_\|video_\|vram_address\[4\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1360:1360:1360) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (857:857:857) (835:835:835)) + (PORT ena (1111:1111:1111) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -33228,8 +31364,8 @@ (INSTANCE ula_\|video_\|Add4\~0) (DELAY (ABSOLUTE - (PORT dataa (910:910:910) (929:929:929)) - (PORT datab (635:635:635) (674:674:674)) + (PORT dataa (650:650:650) (694:694:694)) + (PORT datab (663:663:663) (715:715:715)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datab combout (306:306:306) (324:324:324)) @@ -33243,7 +31379,7 @@ (INSTANCE ula_\|video_\|Add4\~2) (DELAY (ABSOLUTE - (PORT datab (680:680:680) (710:710:710)) + (PORT datab (607:607:607) (640:640:640)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -33257,7 +31393,7 @@ (INSTANCE ula_\|video_\|Add4\~4) (DELAY (ABSOLUTE - (PORT datab (1081:1081:1081) (1115:1115:1115)) + (PORT datab (659:659:659) (688:688:688)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -33271,9 +31407,9 @@ (INSTANCE ula_\|video_\|Add4\~6) (DELAY (ABSOLUTE - (PORT dataa (879:879:879) (892:892:892)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (634:634:634) (682:682:682)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -33285,9 +31421,9 @@ (INSTANCE ula_\|video_\|vram_address\[5\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1360:1360:1360) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (857:857:857) (835:835:835)) + (PORT ena (1111:1111:1111) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -33301,9 +31437,9 @@ (INSTANCE ula_\|video_\|Add4\~8) (DELAY (ABSOLUTE - (PORT datab (668:668:668) (709:709:709)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (654:654:654) (702:702:702)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -33315,9 +31451,9 @@ (INSTANCE ula_\|video_\|vram_address\[6\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1360:1360:1360) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (857:857:857) (835:835:835)) + (PORT ena (1111:1111:1111) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -33331,7 +31467,7 @@ (INSTANCE ula_\|video_\|Add4\~10) (DELAY (ABSOLUTE - (PORT dataa (849:849:849) (867:867:867)) + (PORT dataa (907:907:907) (921:921:921)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -33345,9 +31481,9 @@ (INSTANCE ula_\|video_\|vram_address\[7\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1360:1360:1360) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (857:857:857) (835:835:835)) + (PORT ena (1111:1111:1111) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -33361,9 +31497,9 @@ (INSTANCE ula_\|video_\|Add4\~12) (DELAY (ABSOLUTE - (PORT dataa (657:657:657) (700:700:700)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (645:645:645) (681:681:681)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -33375,11 +31511,11 @@ (INSTANCE ula_\|video_\|Selector6\~0) (DELAY (ABSOLUTE - (PORT datab (1164:1164:1164) (1182:1182:1182)) - (PORT datac (158:158:158) (190:190:190)) - (PORT datad (166:166:166) (188:188:188)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (559:559:559) (581:581:581)) + (PORT datac (526:526:526) (531:531:531)) + (PORT datad (889:889:889) (923:923:923)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -33389,12 +31525,12 @@ (INSTANCE ula_\|video_\|vram_address\[9\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1095:1095:1095) (1111:1111:1111)) - (PORT datab (1378:1378:1378) (1367:1367:1367)) - (PORT datac (1102:1102:1102) (1116:1116:1116)) - (PORT datad (802:802:802) (821:821:821)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (1154:1154:1154) (1188:1188:1188)) + (PORT datab (895:895:895) (951:951:951)) + (PORT datac (889:889:889) (941:941:941)) + (PORT datad (257:257:257) (326:326:326)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -33405,9 +31541,9 @@ (INSTANCE ula_\|video_\|vram_address\[8\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (884:884:884) (868:868:868)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -33421,7 +31557,7 @@ (INSTANCE ula_\|video_\|Add4\~14) (DELAY (ABSOLUTE - (PORT datad (826:826:826) (839:839:839)) + (PORT datad (652:652:652) (694:694:694)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -33432,11 +31568,11 @@ (INSTANCE ula_\|video_\|Selector5\~0) (DELAY (ABSOLUTE - (PORT datab (1164:1164:1164) (1182:1182:1182)) - (PORT datac (162:162:162) (194:194:194)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (604:604:604) (612:612:612)) + (PORT datac (736:736:736) (733:733:733)) + (PORT datad (889:889:889) (927:927:927)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -33446,9 +31582,9 @@ (INSTANCE ula_\|video_\|vram_address\[9\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (884:884:884) (868:868:868)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -33462,13 +31598,13 @@ (INSTANCE ula_\|video_\|vram_address\[10\]\~2) (DELAY (ABSOLUTE - (PORT dataa (924:924:924) (950:950:950)) - (PORT datab (661:661:661) (695:695:695)) - (PORT datac (1114:1114:1114) (1153:1153:1153)) - (PORT datad (638:638:638) (666:666:666)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1152:1152:1152) (1182:1182:1182)) + (PORT datab (891:891:891) (944:944:944)) + (PORT datac (893:893:893) (945:945:945)) + (PORT datad (261:261:261) (330:330:330)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -33478,11 +31614,11 @@ (INSTANCE ula_\|video_\|vram_address\[10\]\~3) (DELAY (ABSOLUTE - (PORT dataa (844:844:844) (821:821:821)) - (PORT datab (185:185:185) (219:219:219)) - (PORT datad (640:640:640) (670:670:670)) + (PORT dataa (574:574:574) (583:583:583)) + (PORT datab (925:925:925) (976:976:976)) + (PORT datad (158:158:158) (179:179:179)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -33493,7 +31629,7 @@ (INSTANCE ula_\|video_\|vram_address\[10\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -33507,9 +31643,9 @@ (INSTANCE ula_\|video_\|Selector3\~0) (DELAY (ABSOLUTE - (PORT datac (1134:1134:1134) (1149:1149:1149)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datab (562:562:562) (582:582:582)) + (PORT datad (890:890:890) (925:925:925)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -33519,9 +31655,9 @@ (INSTANCE ula_\|video_\|vram_address\[11\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (884:884:884) (868:868:868)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -33535,10 +31671,10 @@ (INSTANCE ula_\|video_\|Selector2\~0) (DELAY (ABSOLUTE - (PORT datab (1162:1162:1162) (1177:1177:1177)) - (PORT datac (163:163:163) (196:196:196)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datac (566:566:566) (578:578:578)) + (PORT datad (889:889:889) (923:923:923)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -33547,9 +31683,9 @@ (INSTANCE ula_\|video_\|vram_address\[12\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (884:884:884) (868:868:868)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -33558,13 +31694,3730 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1438:1438:1438) (1457:1457:1457)) + (PORT clk (1649:1649:1649) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2413:2413:2413) (2427:2427:2427)) + (PORT d[1] (2186:2186:2186) (2314:2314:2314)) + (PORT d[2] (2143:2143:2143) (2219:2219:2219)) + (PORT d[3] (1833:1833:1833) (1876:1876:1876)) + (PORT d[4] (2724:2724:2724) (2866:2866:2866)) + (PORT d[5] (1945:1945:1945) (2062:2062:2062)) + (PORT d[6] (1446:1446:1446) (1485:1485:1485)) + (PORT d[7] (1502:1502:1502) (1535:1535:1535)) + (PORT d[8] (2576:2576:2576) (2689:2689:2689)) + (PORT d[9] (1919:1919:1919) (1944:1944:1944)) + (PORT d[10] (1964:1964:1964) (1995:1995:1995)) + (PORT d[11] (2954:2954:2954) (3003:3003:3003)) + (PORT d[12] (2038:2038:2038) (2059:2059:2059)) + (PORT clk (1646:1646:1646) (1675:1675:1675)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2558:2558:2558) (2482:2482:2482)) + (PORT clk (1646:1646:1646) (1675:1675:1675)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1677:1677:1677)) + (PORT d[0] (2573:2573:2573) (2575:2575:2575)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1607:1607:1607)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1996:1996:1996) (1985:1985:1985)) + (PORT clk (1616:1616:1616) (1614:1614:1614)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4310:4310:4310) (4203:4203:4203)) + (PORT d[1] (4109:4109:4109) (3957:3957:3957)) + (PORT d[2] (4248:4248:4248) (4146:4146:4146)) + (PORT d[3] (4389:4389:4389) (4241:4241:4241)) + (PORT d[4] (3981:3981:3981) (3826:3826:3826)) + (PORT d[5] (4115:4115:4115) (3954:3954:3954)) + (PORT d[6] (4311:4311:4311) (4251:4251:4251)) + (PORT d[7] (4106:4106:4106) (3931:3931:3931)) + (PORT d[8] (4394:4394:4394) (4226:4226:4226)) + (PORT d[9] (4253:4253:4253) (4312:4312:4312)) + (PORT d[10] (4136:4136:4136) (4024:4024:4024)) + (PORT d[11] (4334:4334:4334) (4189:4189:4189)) + (PORT d[12] (4138:4138:4138) (4057:4057:4057)) + (PORT clk (1613:1613:1613) (1611:1611:1611)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1616:1616:1616) (1614:1614:1614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1615:1615:1615)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1615:1615:1615)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1615:1615:1615)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1615:1615:1615)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1608:1608:1608)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1113:1113:1113) (1158:1158:1158)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1706:1706:1706) (1725:1725:1725)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT asdata (1584:1584:1584) (1576:1576:1576)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (658:658:658)) + (PORT datab (231:231:231) (285:285:285)) + (PORT datac (331:331:331) (357:357:357)) + (PORT datad (1200:1200:1200) (1156:1156:1156)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1404:1404:1404) (1421:1421:1421)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2693:2693:2693) (2714:2714:2714)) + (PORT d[1] (2208:2208:2208) (2339:2339:2339)) + (PORT d[2] (1126:1126:1126) (1144:1144:1144)) + (PORT d[3] (1855:1855:1855) (1908:1908:1908)) + (PORT d[4] (2708:2708:2708) (2836:2836:2836)) + (PORT d[5] (2235:2235:2235) (2355:2355:2355)) + (PORT d[6] (1416:1416:1416) (1429:1429:1429)) + (PORT d[7] (1186:1186:1186) (1211:1211:1211)) + (PORT d[8] (1580:1580:1580) (1586:1586:1586)) + (PORT d[9] (1446:1446:1446) (1451:1451:1451)) + (PORT d[10] (2003:2003:2003) (2052:2052:2052)) + (PORT d[11] (2973:2973:2973) (3030:3030:3030)) + (PORT d[12] (1779:1779:1779) (1812:1812:1812)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2500:2500:2500) (2409:2409:2409)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (2817:2817:2817) (2815:2815:2815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2015:2015:2015) (2003:2003:2003)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4298:4298:4298) (4182:4182:4182)) + (PORT d[1] (3895:3895:3895) (3763:3763:3763)) + (PORT d[2] (3977:3977:3977) (3887:3887:3887)) + (PORT d[3] (4174:4174:4174) (4075:4075:4075)) + (PORT d[4] (4037:4037:4037) (3903:3903:3903)) + (PORT d[5] (4054:4054:4054) (3954:3954:3954)) + (PORT d[6] (4151:4151:4151) (4124:4124:4124)) + (PORT d[7] (3882:3882:3882) (3713:3713:3713)) + (PORT d[8] (4101:4101:4101) (3936:3936:3936)) + (PORT d[9] (4231:4231:4231) (4282:4282:4282)) + (PORT d[10] (4119:4119:4119) (4022:4022:4022)) + (PORT d[11] (4215:4215:4215) (4129:4129:4129)) + (PORT d[12] (4134:4134:4134) (4050:4050:4050)) + (PORT clk (1607:1607:1607) (1604:1604:1604)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1607:1607:1607)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2355:2355:2355) (2346:2346:2346)) + (PORT d[1] (2066:2066:2066) (2149:2149:2149)) + (PORT d[2] (2142:2142:2142) (2225:2225:2225)) + (PORT d[3] (2023:2023:2023) (2092:2092:2092)) + (PORT d[4] (2698:2698:2698) (2836:2836:2836)) + (PORT d[5] (2125:2125:2125) (2238:2238:2238)) + (PORT d[6] (1723:1723:1723) (1771:1771:1771)) + (PORT d[7] (2056:2056:2056) (2040:2040:2040)) + (PORT d[8] (2548:2548:2548) (2649:2649:2649)) + (PORT d[9] (1614:1614:1614) (1648:1648:1648)) + (PORT d[10] (1630:1630:1630) (1624:1624:1624)) + (PORT d[11] (2891:2891:2891) (2914:2914:2914)) + (PORT d[12] (1192:1192:1192) (1217:1217:1217)) + (PORT clk (1654:1654:1654) (1681:1681:1681)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (PORT d[0] (2020:2020:2020) (2024:2024:2024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1682:1682:1682)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1647:1647:1647)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (892:892:892) (894:894:894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (895:895:895)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (895:895:895)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (895:895:895)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1240:1240:1240)) + (PORT datab (248:248:248) (325:325:325)) + (PORT datac (1284:1284:1284) (1276:1276:1276)) + (PORT datad (1538:1538:1538) (1507:1507:1507)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3394:3394:3394) (3476:3476:3476)) + (PORT d[1] (2412:2412:2412) (2539:2539:2539)) + (PORT d[2] (2265:2265:2265) (2288:2288:2288)) + (PORT d[3] (1992:1992:1992) (2060:2060:2060)) + (PORT d[4] (2069:2069:2069) (2140:2140:2140)) + (PORT d[5] (1928:1928:1928) (2016:2016:2016)) + (PORT d[6] (1784:1784:1784) (1847:1847:1847)) + (PORT d[7] (1844:1844:1844) (1862:1862:1862)) + (PORT d[8] (2787:2787:2787) (2891:2891:2891)) + (PORT d[9] (2420:2420:2420) (2486:2486:2486)) + (PORT d[10] (4385:4385:4385) (4449:4449:4449)) + (PORT d[11] (1943:1943:1943) (1988:1988:1988)) + (PORT d[12] (2255:2255:2255) (2302:2302:2302)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1672:1672:1672)) + (PORT d[0] (2836:2836:2836) (2867:2867:2867)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (1191:1191:1191) (1152:1152:1152)) + (PORT datab (1080:1080:1080) (1050:1050:1050)) + (PORT datac (1488:1488:1488) (1466:1466:1466)) + (PORT datad (163:163:163) (188:188:188)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (1324:1324:1324) (1337:1337:1337)) + (PORT datab (190:190:190) (225:225:225)) + (PORT datac (580:580:580) (608:608:608)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (604:604:604)) + (PORT datab (1866:1866:1866) (1894:1894:1894)) + (PORT datac (848:848:848) (891:891:891)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE raw_loader_in\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (876:876:876)) + (PORT datac (1426:1426:1426) (1503:1503:1503)) + (PORT datad (1841:1841:1841) (1862:1862:1862)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (895:895:895)) + (PORT datab (1277:1277:1277) (1232:1232:1232)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~101) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (888:888:888)) + (PORT datab (824:824:824) (860:860:860)) + (PORT datac (1535:1535:1535) (1519:1519:1519)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (297:297:297)) + (PORT datab (1288:1288:1288) (1272:1272:1272)) + (PORT datac (874:874:874) (915:915:915)) + (PORT datad (772:772:772) (740:740:740)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1556:1556:1556) (1645:1645:1645)) + (PORT datab (703:703:703) (765:765:765)) + (PORT datac (881:881:881) (918:918:918)) + (PORT datad (1120:1120:1120) (1121:1121:1121)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (944:944:944)) + (PORT datab (906:906:906) (920:920:920)) + (PORT datac (883:883:883) (919:919:919)) + (PORT datad (166:166:166) (189:189:189)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (1089:1089:1089) (1102:1102:1102)) + (PORT datac (202:202:202) (249:249:249)) + (PORT datad (190:190:190) (219:219:219)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (178:178:178) (198:198:198)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1078:1078:1078)) + (PORT datab (838:838:838) (869:869:869)) + (PORT datac (607:607:607) (638:638:638)) + (PORT datad (352:352:352) (353:353:353)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1395:1395:1395) (1367:1367:1367)) + (PORT ena (1130:1130:1130) (1103:1103:1103)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (DELAY + (ABSOLUTE + (PORT datac (1564:1564:1564) (1572:1572:1572)) + (PORT datad (1132:1132:1132) (1167:1167:1167)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1375:1375:1375) (1400:1400:1400)) + (PORT datab (2129:2129:2129) (2186:2186:2186)) + (PORT datac (1970:1970:1970) (2062:2062:2062)) + (PORT datad (1338:1338:1338) (1386:1386:1386)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (454:454:454)) + (PORT datab (1517:1517:1517) (1484:1484:1484)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (1017:1017:1017) (1026:1026:1026)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (1815:1815:1815) (1864:1864:1864)) + (PORT datab (1040:1040:1040) (1024:1024:1024)) + (PORT datac (1910:1910:1910) (1950:1950:1950)) + (PORT datad (164:164:164) (186:186:186)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (1097:1097:1097)) + (PORT datab (252:252:252) (318:318:318)) + (PORT datac (228:228:228) (287:287:287)) + (PORT datad (224:224:224) (260:260:260)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1046:1046:1046) (1077:1077:1077)) + (PORT datab (1066:1066:1066) (1087:1087:1087)) + (PORT datac (384:384:384) (438:438:438)) + (PORT datad (619:619:619) (637:637:637)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (890:890:890)) + (PORT datac (1540:1540:1540) (1543:1543:1543)) + (PORT datad (836:836:836) (826:826:826)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (184:184:184) (217:217:217)) + (PORT datac (820:820:820) (816:816:816)) + (PORT datad (223:223:223) (257:257:257)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (350:350:350)) + (PORT datab (585:585:585) (576:576:576)) + (PORT datac (1068:1068:1068) (1089:1089:1089)) + (PORT datad (565:565:565) (556:556:556)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (919:919:919) (929:929:929)) + (PORT datac (549:549:549) (545:545:545)) + (PORT datad (200:200:200) (239:239:239)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1208:1208:1208)) + (PORT datab (868:868:868) (867:867:867)) + (PORT datac (1676:1676:1676) (1689:1689:1689)) + (PORT datad (864:864:864) (874:874:874)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (606:606:606)) + (PORT datab (230:230:230) (282:282:282)) + (PORT datac (159:159:159) (190:190:190)) + (PORT datad (871:871:871) (883:883:883)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (459:459:459)) + (PORT datab (1249:1249:1249) (1259:1259:1259)) + (PORT datac (1070:1070:1070) (1065:1065:1065)) + (PORT datad (1106:1106:1106) (1118:1118:1118)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (511:511:511)) + (PORT datab (584:584:584) (585:585:585)) + (PORT datac (608:608:608) (617:617:617)) + (PORT datad (625:625:625) (634:634:634)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (618:618:618)) + (PORT datab (827:827:827) (852:852:852)) + (PORT datac (605:605:605) (615:615:615)) + (PORT datad (821:821:821) (812:812:812)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (902:902:902)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (874:874:874) (874:874:874)) + (PORT datad (805:805:805) (791:791:791)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (641:641:641)) + (PORT datab (1109:1109:1109) (1091:1091:1091)) + (PORT datac (1028:1028:1028) (1036:1036:1036)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (1618:1618:1618) (1660:1660:1660)) + (PORT datab (1133:1133:1133) (1150:1150:1150)) + (PORT datac (1446:1446:1446) (1508:1508:1508)) + (PORT datad (1045:1045:1045) (1034:1034:1034)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1107:1107:1107) (1081:1081:1081)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3423:3423:3423) (3511:3511:3511)) + (PORT d[1] (1610:1610:1610) (1712:1712:1712)) + (PORT d[2] (2815:2815:2815) (2865:2865:2865)) + (PORT d[3] (1754:1754:1754) (1799:1799:1799)) + (PORT d[4] (2040:2040:2040) (2098:2098:2098)) + (PORT d[5] (2484:2484:2484) (2590:2590:2590)) + (PORT d[6] (1915:1915:1915) (1948:1948:1948)) + (PORT d[7] (2568:2568:2568) (2586:2586:2586)) + (PORT d[8] (2819:2819:2819) (2925:2925:2925)) + (PORT d[9] (2617:2617:2617) (2662:2662:2662)) + (PORT d[10] (3254:3254:3254) (3360:3360:3360)) + (PORT d[11] (1682:1682:1682) (1715:1715:1715)) + (PORT d[12] (1930:1930:1930) (1983:1983:1983)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1794:1794:1794) (1753:1753:1753)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1660:1660:1660)) + (PORT d[0] (2430:2430:2430) (2431:2431:2431)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1596:1596:1596) (1624:1624:1624)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (871:871:871)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1096:1096:1096) (1074:1074:1074)) + (PORT clk (1630:1630:1630) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3694:3694:3694) (3794:3794:3794)) + (PORT d[1] (1581:1581:1581) (1666:1666:1666)) + (PORT d[2] (3056:3056:3056) (3113:3113:3113)) + (PORT d[3] (1749:1749:1749) (1779:1779:1779)) + (PORT d[4] (1736:1736:1736) (1765:1765:1765)) + (PORT d[5] (1519:1519:1519) (1586:1586:1586)) + (PORT d[6] (1635:1635:1635) (1666:1666:1666)) + (PORT d[7] (2830:2830:2830) (2851:2851:2851)) + (PORT d[8] (3086:3086:3086) (3198:3198:3198)) + (PORT d[9] (2654:2654:2654) (2713:2713:2713)) + (PORT d[10] (3197:3197:3197) (3270:3270:3270)) + (PORT d[11] (1430:1430:1430) (1454:1454:1454)) + (PORT d[12] (1604:1604:1604) (1641:1641:1641)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1789:1789:1789) (1719:1719:1719)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1630:1630:1630) (1658:1658:1658)) + (PORT d[0] (2199:2199:2199) (2121:2121:2121)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1594:1594:1594) (1622:1622:1622)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (865:865:865) (869:869:869)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1132:1132:1132) (1118:1118:1118)) + (PORT clk (1630:1630:1630) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3424:3424:3424) (3512:3512:3512)) + (PORT d[1] (1571:1571:1571) (1675:1675:1675)) + (PORT d[2] (2754:2754:2754) (2823:2823:2823)) + (PORT d[3] (1969:1969:1969) (1988:1988:1988)) + (PORT d[4] (2069:2069:2069) (2124:2124:2124)) + (PORT d[5] (2492:2492:2492) (2612:2612:2612)) + (PORT d[6] (1673:1673:1673) (1720:1720:1720)) + (PORT d[7] (2571:2571:2571) (2592:2592:2592)) + (PORT d[8] (3107:3107:3107) (3211:3211:3211)) + (PORT d[9] (2672:2672:2672) (2732:2732:2732)) + (PORT d[10] (3224:3224:3224) (3324:3324:3324)) + (PORT d[11] (1692:1692:1692) (1728:1728:1728)) + (PORT d[12] (1875:1875:1875) (1914:1914:1914)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1755:1755:1755) (1697:1697:1697)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1630:1630:1630) (1658:1658:1658)) + (PORT d[0] (2267:2267:2267) (2233:2233:2233)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1594:1594:1594) (1622:1622:1622)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (865:865:865) (869:869:869)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1338:1338:1338) (1342:1342:1342)) + (PORT datab (1310:1310:1310) (1345:1345:1345)) + (PORT datac (1055:1055:1055) (1028:1028:1028)) + (PORT datad (1035:1035:1035) (1017:1017:1017)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1177:1177:1177) (1189:1189:1189)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2678:2678:2678) (2705:2705:2705)) + (PORT d[1] (2465:2465:2465) (2605:2605:2605)) + (PORT d[2] (1123:1123:1123) (1138:1138:1138)) + (PORT d[3] (1565:1565:1565) (1603:1603:1603)) + (PORT d[4] (2689:2689:2689) (2795:2795:2795)) + (PORT d[5] (2214:2214:2214) (2342:2342:2342)) + (PORT d[6] (1167:1167:1167) (1193:1193:1193)) + (PORT d[7] (1224:1224:1224) (1251:1251:1251)) + (PORT d[8] (1619:1619:1619) (1631:1631:1631)) + (PORT d[9] (1169:1169:1169) (1184:1184:1184)) + (PORT d[10] (2227:2227:2227) (2272:2272:2272)) + (PORT d[11] (2936:2936:2936) (3022:3022:3022)) + (PORT d[12] (2039:2039:2039) (2078:2078:2078)) + (PORT clk (1636:1636:1636) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1377:1377:1377) (1357:1357:1357)) + (PORT clk (1636:1636:1636) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT d[0] (1925:1925:1925) (1914:1914:1914)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1631:1631:1631)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1045:1045:1045) (1054:1054:1054)) + (PORT datab (1569:1569:1569) (1585:1585:1585)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (1315:1315:1315) (1322:1322:1322)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1492:1492:1492) (1530:1530:1530)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2957:2957:2957) (2968:2968:2968)) + (PORT d[1] (1859:1859:1859) (1960:1960:1960)) + (PORT d[2] (2024:2024:2024) (2042:2042:2042)) + (PORT d[3] (1726:1726:1726) (1784:1784:1784)) + (PORT d[4] (2308:2308:2308) (2357:2357:2357)) + (PORT d[5] (2072:2072:2072) (2153:2153:2153)) + (PORT d[6] (1595:1595:1595) (1605:1605:1605)) + (PORT d[7] (1567:1567:1567) (1598:1598:1598)) + (PORT d[8] (2423:2423:2423) (2497:2497:2497)) + (PORT d[9] (1817:1817:1817) (1859:1859:1859)) + (PORT d[10] (1866:1866:1866) (1904:1904:1904)) + (PORT d[11] (2253:2253:2253) (2298:2298:2298)) + (PORT d[12] (2364:2364:2364) (2372:2372:2372)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2369:2369:2369) (2331:2331:2331)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (3638:3638:3638) (3625:3625:3625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1597:1597:1597) (1595:1595:1595)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1613:1613:1613) (1560:1560:1560)) + (PORT clk (1605:1605:1605) (1602:1602:1602)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4091:4091:4091) (4004:4004:4004)) + (PORT d[1] (3942:3942:3942) (3858:3858:3858)) + (PORT d[2] (4035:4035:4035) (3940:3940:3940)) + (PORT d[3] (4359:4359:4359) (4253:4253:4253)) + (PORT d[4] (4055:4055:4055) (3927:3927:3927)) + (PORT d[5] (4299:4299:4299) (4223:4223:4223)) + (PORT d[6] (4408:4408:4408) (4355:4355:4355)) + (PORT d[7] (4042:4042:4042) (3983:3983:3983)) + (PORT d[8] (4110:4110:4110) (3989:3989:3989)) + (PORT d[9] (4148:4148:4148) (4218:4218:4218)) + (PORT d[10] (4304:4304:4304) (4166:4166:4166)) + (PORT d[11] (4107:4107:4107) (3994:3994:3994)) + (PORT d[12] (4188:4188:4188) (4201:4201:4201)) + (PORT clk (1602:1602:1602) (1599:1599:1599)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1602:1602:1602)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1603:1603:1603)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2654:2654:2654) (2677:2677:2677)) + (PORT d[1] (1605:1605:1605) (1701:1701:1701)) + (PORT d[2] (1805:1805:1805) (1844:1844:1844)) + (PORT d[3] (1758:1758:1758) (1811:1811:1811)) + (PORT d[4] (2545:2545:2545) (2597:2597:2597)) + (PORT d[5] (2062:2062:2062) (2158:2158:2158)) + (PORT d[6] (1833:1833:1833) (1844:1844:1844)) + (PORT d[7] (1979:1979:1979) (2050:2050:2050)) + (PORT d[8] (2211:2211:2211) (2278:2278:2278)) + (PORT d[9] (1831:1831:1831) (1863:1863:1863)) + (PORT d[10] (1561:1561:1561) (1568:1568:1568)) + (PORT d[11] (1894:1894:1894) (1910:1910:1910)) + (PORT d[12] (2323:2323:2323) (2341:2341:2341)) + (PORT clk (1642:1642:1642) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1671:1671:1671)) + (PORT d[0] (2518:2518:2518) (2506:2506:2506)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1637:1637:1637)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3650:3650:3650) (3721:3721:3721)) + (PORT d[1] (2659:2659:2659) (2780:2780:2780)) + (PORT d[2] (2501:2501:2501) (2532:2532:2532)) + (PORT d[3] (2111:2111:2111) (2186:2186:2186)) + (PORT d[4] (2332:2332:2332) (2410:2410:2410)) + (PORT d[5] (2343:2343:2343) (2420:2420:2420)) + (PORT d[6] (1758:1758:1758) (1814:1814:1814)) + (PORT d[7] (2110:2110:2110) (2124:2124:2124)) + (PORT d[8] (2878:2878:2878) (3013:3013:3013)) + (PORT d[9] (2488:2488:2488) (2560:2560:2560)) + (PORT d[10] (4188:4188:4188) (4256:4256:4256)) + (PORT d[11] (1794:1794:1794) (1865:1865:1865)) + (PORT d[12] (2232:2232:2232) (2284:2284:2284)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (3251:3251:3251) (3306:3306:3306)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1637:1637:1637)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1388:1388:1388) (1400:1400:1400)) + (PORT clk (1653:1653:1653) (1680:1680:1680)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2615:2615:2615) (2615:2615:2615)) + (PORT d[1] (1928:1928:1928) (2048:2048:2048)) + (PORT d[2] (2048:2048:2048) (2108:2108:2108)) + (PORT d[3] (2094:2094:2094) (2149:2149:2149)) + (PORT d[4] (2727:2727:2727) (2871:2871:2871)) + (PORT d[5] (2213:2213:2213) (2304:2304:2304)) + (PORT d[6] (1452:1452:1452) (1493:1493:1493)) + (PORT d[7] (1446:1446:1446) (1477:1477:1477)) + (PORT d[8] (2564:2564:2564) (2665:2665:2665)) + (PORT d[9] (1933:1933:1933) (1963:1963:1963)) + (PORT d[10] (1735:1735:1735) (1770:1770:1770)) + (PORT d[11] (2684:2684:2684) (2729:2729:2729)) + (PORT d[12] (1488:1488:1488) (1509:1509:1509)) + (PORT clk (1650:1650:1650) (1678:1678:1678)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2318:2318:2318) (2256:2256:2256)) + (PORT clk (1650:1650:1650) (1678:1678:1678)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (PORT d[0] (2607:2607:2607) (2597:2597:2597)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1610:1610:1610)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2309:2309:2309) (2319:2319:2319)) + (PORT clk (1620:1620:1620) (1617:1617:1617)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4211:4211:4211) (4070:4070:4070)) + (PORT d[1] (3836:3836:3836) (3699:3699:3699)) + (PORT d[2] (4108:4108:4108) (3975:3975:3975)) + (PORT d[3] (4152:4152:4152) (4053:4053:4053)) + (PORT d[4] (4243:4243:4243) (4094:4094:4094)) + (PORT d[5] (4089:4089:4089) (4013:4013:4013)) + (PORT d[6] (4274:4274:4274) (4211:4211:4211)) + (PORT d[7] (3881:3881:3881) (3728:3728:3728)) + (PORT d[8] (4330:4330:4330) (4206:4206:4206)) + (PORT d[9] (4176:4176:4176) (4207:4207:4207)) + (PORT d[10] (4313:4313:4313) (4213:4213:4213)) + (PORT d[11] (4097:4097:4097) (3970:3970:3970)) + (PORT d[12] (4147:4147:4147) (4084:4084:4084)) + (PORT clk (1617:1617:1617) (1614:1614:1614)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1618:1618:1618)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1618:1618:1618)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1618:1618:1618)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1618:1618:1618)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1611:1611:1611)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1327:1327:1327) (1341:1341:1341)) + (PORT datab (908:908:908) (940:940:940)) + (PORT datac (1088:1088:1088) (1077:1077:1077)) + (PORT datad (1560:1560:1560) (1534:1534:1534)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1400:1400:1400) (1441:1441:1441)) + (PORT datab (909:909:909) (941:941:941)) + (PORT datac (1580:1580:1580) (1576:1576:1576)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (1130:1130:1130) (1141:1141:1141)) + (PORT datac (1529:1529:1529) (1526:1526:1526)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (1282:1282:1282) (1254:1254:1254)) + (PORT datab (1295:1295:1295) (1272:1272:1272)) + (PORT datac (787:787:787) (812:812:812)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~99) + (DELAY + (ABSOLUTE + (PORT dataa (758:758:758) (752:752:752)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (945:945:945)) + (PORT datab (961:961:961) (952:952:952)) + (PORT datac (212:212:212) (261:261:261)) + (PORT datad (883:883:883) (890:890:890)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (656:656:656) (656:656:656)) + (PORT datac (212:212:212) (277:277:277)) + (PORT datad (327:327:327) (343:343:343)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (903:903:903)) + (PORT datab (849:849:849) (863:863:863)) + (PORT datac (755:755:755) (734:734:734)) + (PORT datad (817:817:817) (825:825:825)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1366:1366:1366)) + (PORT asdata (535:535:535) (588:588:588)) + (PORT clrn (1390:1390:1390) (1361:1361:1361)) + (PORT ena (1363:1363:1363) (1319:1319:1319)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1188:1188:1188)) + (PORT datab (795:795:795) (797:797:797)) + (PORT datac (798:798:798) (786:786:786)) + (PORT datad (1753:1753:1753) (1750:1750:1750)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1407:1407:1407) (1373:1373:1373)) + (PORT ena (745:745:745) (752:752:752)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|use_ixiy) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (970:970:970)) + (PORT datac (852:852:852) (909:909:909)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1111:1111:1111)) + (PORT datab (918:918:918) (981:981:981)) + (PORT datac (602:602:602) (641:641:641)) + (PORT datad (1150:1150:1150) (1209:1209:1209)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (821:821:821)) + (PORT datab (613:613:613) (611:611:611)) + (PORT datac (833:833:833) (862:862:862)) + (PORT datad (334:334:334) (344:344:344)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1094:1094:1094)) + (PORT datab (1490:1490:1490) (1461:1461:1461)) + (PORT datac (568:568:568) (582:582:582)) + (PORT datad (1010:1010:1010) (1002:1002:1002)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1204:1204:1204)) + (PORT datab (424:424:424) (464:464:464)) + (PORT datac (1567:1567:1567) (1577:1577:1577)) + (PORT datad (239:239:239) (288:288:288)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (397:397:397)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (998:998:998) (998:998:998)) + (PORT datad (184:184:184) (209:209:209)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1095:1095:1095)) + (PORT datab (533:533:533) (540:540:540)) + (PORT datac (1016:1016:1016) (1014:1014:1014)) + (PORT datad (295:295:295) (304:304:304)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (800:800:800)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (542:542:542) (547:547:547)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (247:247:247)) + (PORT datab (598:598:598) (592:592:592)) + (PORT datac (175:175:175) (217:217:217)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (820:820:820)) + (PORT datab (1037:1037:1037) (1034:1034:1034)) + (PORT datac (1298:1298:1298) (1314:1314:1314)) + (PORT datad (830:830:830) (865:865:865)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (816:816:816)) + (PORT datab (871:871:871) (884:884:884)) + (PORT datac (882:882:882) (920:920:920)) + (PORT datad (1026:1026:1026) (1026:1026:1026)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (822:822:822)) + (PORT datab (806:806:806) (804:804:804)) + (PORT datac (1022:1022:1022) (1012:1012:1012)) + (PORT datad (307:307:307) (310:310:310)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1451:1451:1451) (1494:1494:1494)) + (PORT datab (188:188:188) (221:221:221)) + (PORT datac (1752:1752:1752) (1765:1765:1765)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1040:1040:1040) (1132:1132:1132)) + (PORT datab (922:922:922) (956:956:956)) + (PORT datac (1511:1511:1511) (1516:1516:1516)) + (PORT datad (1079:1079:1079) (1103:1103:1103)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1315:1315:1315) (1302:1302:1302)) + (PORT datab (1038:1038:1038) (1036:1036:1036)) + (PORT datac (967:967:967) (957:957:957)) + (PORT datad (309:309:309) (319:319:319)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (550:550:550) (538:538:538)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (569:569:569)) + (PORT datab (965:965:965) (976:976:976)) + (PORT datac (533:533:533) (512:512:512)) + (PORT datad (553:553:553) (572:572:572)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~48) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (847:847:847)) + (PORT datab (1109:1109:1109) (1102:1102:1102)) + (PORT datac (1394:1394:1394) (1410:1410:1410)) + (PORT datad (622:622:622) (636:636:636)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1241:1241:1241)) + (PORT datab (792:792:792) (785:785:785)) + (PORT datac (992:992:992) (970:970:970)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (802:802:802) (854:854:854)) + (PORT datab (867:867:867) (916:916:916)) + (PORT datac (1446:1446:1446) (1424:1424:1424)) + (PORT datad (1118:1118:1118) (1102:1102:1102)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (802:802:802)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (746:746:746) (736:736:736)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1902:1902:1902) (1935:1935:1935)) + (PORT datab (1116:1116:1116) (1117:1117:1117)) + (PORT datac (1048:1048:1048) (1072:1072:1072)) + (PORT datad (1067:1067:1067) (1091:1091:1091)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (2313:2313:2313) (2349:2349:2349)) + (PORT datab (542:542:542) (526:526:526)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (911:911:911) (916:916:916)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1541:1541:1541) (1491:1491:1491)) + (PORT datab (770:770:770) (809:809:809)) + (PORT datac (953:953:953) (981:981:981)) + (PORT datad (712:712:712) (733:733:733)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (961:961:961) (932:932:932)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (761:761:761) (783:783:783)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (801:801:801)) + (PORT datab (182:182:182) (213:213:213)) + (PORT datac (758:758:758) (780:780:780)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT datab (907:907:907) (921:921:921)) + (PORT datac (885:885:885) (921:921:921)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (935:935:935) (965:965:965)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1102:1102:1102) (1088:1088:1088)) + (PORT d[1] (2237:2237:2237) (2392:2392:2392)) + (PORT d[2] (1622:1622:1622) (1627:1627:1627)) + (PORT d[3] (936:936:936) (958:958:958)) + (PORT d[4] (2428:2428:2428) (2538:2538:2538)) + (PORT d[5] (3242:3242:3242) (3357:3357:3357)) + (PORT d[6] (950:950:950) (981:981:981)) + (PORT d[7] (2952:2952:2952) (3001:3001:3001)) + (PORT d[8] (1157:1157:1157) (1143:1143:1143)) + (PORT d[9] (950:950:950) (974:974:974)) + (PORT d[10] (1217:1217:1217) (1248:1248:1248)) + (PORT d[11] (2323:2323:2323) (2395:2395:2395)) + (PORT d[12] (1207:1207:1207) (1237:1237:1237)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (863:863:863) (813:813:813)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (1543:1543:1543) (1494:1494:1494)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (659:659:659) (684:684:684)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (892:892:892) (908:908:908)) + (PORT d[1] (2746:2746:2746) (2901:2901:2901)) + (PORT d[2] (1143:1143:1143) (1158:1158:1158)) + (PORT d[3] (1198:1198:1198) (1236:1236:1236)) + (PORT d[4] (2401:2401:2401) (2505:2505:2505)) + (PORT d[5] (2764:2764:2764) (2904:2904:2904)) + (PORT d[6] (643:643:643) (644:644:644)) + (PORT d[7] (654:654:654) (659:659:659)) + (PORT d[8] (938:938:938) (949:949:949)) + (PORT d[9] (667:667:667) (672:672:672)) + (PORT d[10] (962:962:962) (987:987:987)) + (PORT d[11] (2364:2364:2364) (2465:2465:2465)) + (PORT d[12] (1168:1168:1168) (1176:1176:1176)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (885:885:885) (852:852:852)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (1900:1900:1900) (1848:1848:1848)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (670:670:670)) + (PORT datab (626:626:626) (667:667:667)) + (PORT datac (735:735:735) (706:706:706)) + (PORT datad (796:796:796) (797:797:797)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (651:651:651) (672:672:672)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2935:2935:2935) (2963:2963:2963)) + (PORT d[1] (2718:2718:2718) (2863:2863:2863)) + (PORT d[2] (893:893:893) (888:888:888)) + (PORT d[3] (1235:1235:1235) (1270:1270:1270)) + (PORT d[4] (2431:2431:2431) (2549:2549:2549)) + (PORT d[5] (2464:2464:2464) (2593:2593:2593)) + (PORT d[6] (888:888:888) (891:891:891)) + (PORT d[7] (1176:1176:1176) (1191:1191:1191)) + (PORT d[8] (1345:1345:1345) (1346:1346:1346)) + (PORT d[9] (900:900:900) (906:906:906)) + (PORT d[10] (956:956:956) (956:956:956)) + (PORT d[11] (2665:2665:2665) (2768:2768:2768)) + (PORT d[12] (895:895:895) (910:910:910)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1141:1141:1141) (1101:1101:1101)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (1845:1845:1845) (1794:1794:1794)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (692:692:692) (704:704:704)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2955:2955:2955) (2983:2983:2983)) + (PORT d[1] (2482:2482:2482) (2633:2633:2633)) + (PORT d[2] (1195:1195:1195) (1176:1176:1176)) + (PORT d[3] (1239:1239:1239) (1274:1274:1274)) + (PORT d[4] (2434:2434:2434) (2550:2550:2550)) + (PORT d[5] (2483:2483:2483) (2619:2619:2619)) + (PORT d[6] (1142:1142:1142) (1146:1146:1146)) + (PORT d[7] (1054:1054:1054) (1040:1040:1040)) + (PORT d[8] (1372:1372:1372) (1377:1377:1377)) + (PORT d[9] (1432:1432:1432) (1452:1452:1452)) + (PORT d[10] (675:675:675) (689:689:689)) + (PORT d[11] (2649:2649:2649) (2760:2760:2760)) + (PORT d[12] (899:899:899) (923:923:923)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1127:1127:1127) (1106:1106:1106)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (PORT d[0] (1644:1644:1644) (1629:1629:1629)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1145:1145:1145) (1184:1184:1184)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (893:893:893) (908:908:908)) + (PORT datad (1017:1017:1017) (1005:1005:1005)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1341:1341:1341) (1331:1331:1331)) - (PORT clk (1645:1645:1645) (1672:1672:1672)) + (PORT d[0] (695:695:695) (707:707:707)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) ) ) (TIMINGCHECK @@ -33576,20 +35429,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1003:1003:1003) (1059:1059:1059)) - (PORT d[1] (1563:1563:1563) (1615:1615:1615)) - (PORT d[2] (3671:3671:3671) (3853:3853:3853)) - (PORT d[3] (3129:3129:3129) (3289:3289:3289)) - (PORT d[4] (2051:2051:2051) (2099:2099:2099)) - (PORT d[5] (1197:1197:1197) (1228:1228:1228)) - (PORT d[6] (1080:1080:1080) (1078:1078:1078)) - (PORT d[7] (2250:2250:2250) (2308:2308:2308)) - (PORT d[8] (1206:1206:1206) (1223:1223:1223)) - (PORT d[9] (4317:4317:4317) (4315:4315:4315)) - (PORT d[10] (1247:1247:1247) (1280:1280:1280)) - (PORT d[11] (3589:3589:3589) (3669:3669:3669)) - (PORT d[12] (2231:2231:2231) (2256:2256:2256)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT d[0] (2694:2694:2694) (2715:2715:2715)) + (PORT d[1] (2202:2202:2202) (2342:2342:2342)) + (PORT d[2] (1461:1461:1461) (1446:1446:1446)) + (PORT d[3] (1823:1823:1823) (1876:1876:1876)) + (PORT d[4] (2718:2718:2718) (2847:2847:2847)) + (PORT d[5] (2496:2496:2496) (2625:2625:2625)) + (PORT d[6] (1171:1171:1171) (1200:1200:1200)) + (PORT d[7] (1210:1210:1210) (1238:1238:1238)) + (PORT d[8] (1623:1623:1623) (1628:1628:1628)) + (PORT d[9] (1439:1439:1439) (1440:1440:1440)) + (PORT d[10] (2000:2000:2000) (2046:2046:2046)) + (PORT d[11] (3000:3000:3000) (3059:3059:3059)) + (PORT d[12] (1185:1185:1185) (1206:1206:1206)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) ) ) (TIMINGCHECK @@ -33601,8 +35454,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1135:1135:1135) (1081:1081:1081)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT d[0] (2714:2714:2714) (2633:2633:2633)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) ) ) (TIMINGCHECK @@ -33614,8 +35467,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (PORT d[0] (2120:2120:2120) (2098:2098:2098)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) + (PORT d[0] (2818:2818:2818) (2820:2820:2820)) ) ) ) @@ -33624,7 +35477,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT clk (1640:1640:1640) (1666:1666:1666)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -33634,7 +35487,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT clk (1640:1640:1640) (1666:1666:1666)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -33644,7 +35497,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT clk (1640:1640:1640) (1666:1666:1666)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -33654,7 +35507,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT clk (1640:1640:1640) (1666:1666:1666)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -33664,7 +35517,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1604:1604:1604) (1602:1602:1602)) + (PORT clk (1598:1598:1598) (1595:1595:1595)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -33678,8 +35531,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2584:2584:2584) (2564:2564:2564)) - (PORT clk (1612:1612:1612) (1609:1609:1609)) + (PORT d[0] (1970:1970:1970) (1951:1951:1951)) + (PORT clk (1606:1606:1606) (1602:1602:1602)) ) ) (TIMINGCHECK @@ -33691,20 +35544,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1748:1748:1748) (1796:1796:1796)) - (PORT d[1] (1716:1716:1716) (1766:1766:1766)) - (PORT d[2] (1736:1736:1736) (1781:1781:1781)) - (PORT d[3] (1694:1694:1694) (1753:1753:1753)) - (PORT d[4] (1746:1746:1746) (1801:1801:1801)) - (PORT d[5] (1656:1656:1656) (1708:1708:1708)) - (PORT d[6] (1696:1696:1696) (1767:1767:1767)) - (PORT d[7] (1760:1760:1760) (1851:1851:1851)) - (PORT d[8] (1791:1791:1791) (1855:1855:1855)) - (PORT d[9] (1849:1849:1849) (1863:1863:1863)) - (PORT d[10] (1755:1755:1755) (1791:1791:1791)) - (PORT d[11] (1847:1847:1847) (1876:1876:1876)) - (PORT d[12] (1717:1717:1717) (1753:1753:1753)) - (PORT clk (1609:1609:1609) (1606:1606:1606)) + (PORT d[0] (4076:4076:4076) (3965:3965:3965)) + (PORT d[1] (3875:3875:3875) (3743:3743:3743)) + (PORT d[2] (3989:3989:3989) (3887:3887:3887)) + (PORT d[3] (4083:4083:4083) (3937:3937:3937)) + (PORT d[4] (4070:4070:4070) (3924:3924:3924)) + (PORT d[5] (4108:4108:4108) (3942:3942:3942)) + (PORT d[6] (4311:4311:4311) (4264:4264:4264)) + (PORT d[7] (4148:4148:4148) (3989:3989:3989)) + (PORT d[8] (4132:4132:4132) (3981:3981:3981)) + (PORT d[9] (4173:4173:4173) (4216:4216:4216)) + (PORT d[10] (4116:4116:4116) (4015:4015:4015)) + (PORT d[11] (4192:4192:4192) (4103:4103:4103)) + (PORT d[12] (4115:4115:4115) (4104:4104:4104)) + (PORT clk (1603:1603:1603) (1599:1599:1599)) ) ) (TIMINGCHECK @@ -33716,7 +35569,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1612:1612:1612) (1609:1609:1609)) + (PORT clk (1606:1606:1606) (1602:1602:1602)) ) ) ) @@ -33725,7 +35578,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1613:1613:1613) (1610:1610:1610)) + (PORT clk (1607:1607:1607) (1603:1603:1603)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -33735,7 +35588,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1613:1613:1613) (1610:1610:1610)) + (PORT clk (1607:1607:1607) (1603:1603:1603)) ) ) ) @@ -33744,7 +35597,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1613:1613:1613) (1610:1610:1610)) + (PORT clk (1607:1607:1607) (1603:1603:1603)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -33754,57 +35607,29 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1613:1613:1613) (1610:1610:1610)) + (PORT clk (1607:1607:1607) (1603:1603:1603)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (1095:1095:1095) (1102:1102:1102)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1365:1365:1365)) - (PORT asdata (1131:1131:1131) (1144:1144:1144)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2532:2532:2532) (2592:2592:2592)) - (PORT d[1] (1454:1454:1454) (1487:1487:1487)) - (PORT d[2] (2720:2720:2720) (2872:2872:2872)) - (PORT d[3] (2408:2408:2408) (2526:2526:2526)) - (PORT d[4] (2156:2156:2156) (2245:2245:2245)) - (PORT d[5] (2108:2108:2108) (2110:2110:2110)) - (PORT d[6] (2235:2235:2235) (2279:2279:2279)) - (PORT d[7] (4662:4662:4662) (4700:4700:4700)) - (PORT d[8] (2797:2797:2797) (2874:2874:2874)) - (PORT d[9] (3036:3036:3036) (3031:3031:3031)) - (PORT d[10] (2408:2408:2408) (2499:2499:2499)) - (PORT d[11] (2334:2334:2334) (2416:2416:2416)) - (PORT d[12] (3346:3346:3346) (3395:3395:3395)) + (PORT d[0] (2389:2389:2389) (2383:2383:2383)) + (PORT d[1] (1886:1886:1886) (1981:1981:1981)) + (PORT d[2] (2142:2142:2142) (2224:2224:2224)) + (PORT d[3] (2338:2338:2338) (2394:2394:2394)) + (PORT d[4] (2742:2742:2742) (2871:2871:2871)) + (PORT d[5] (2111:2111:2111) (2197:2197:2197)) + (PORT d[6] (1722:1722:1722) (1770:1770:1770)) + (PORT d[7] (2347:2347:2347) (2335:2335:2335)) + (PORT d[8] (2572:2572:2572) (2670:2670:2670)) + (PORT d[9] (1628:1628:1628) (1651:1651:1651)) + (PORT d[10] (1407:1407:1407) (1425:1425:1425)) + (PORT d[11] (3201:3201:3201) (3238:3238:3238)) + (PORT d[12] (1429:1429:1429) (1464:1464:1464)) (PORT clk (1654:1654:1654) (1681:1681:1681)) ) ) @@ -33818,7 +35643,7 @@ (DELAY (ABSOLUTE (PORT clk (1654:1654:1654) (1681:1681:1681)) - (PORT d[0] (1819:1819:1819) (1812:1812:1812)) + (PORT d[0] (2025:2025:2025) (2024:2024:2024)) ) ) ) @@ -33889,20 +35714,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (702:702:702) (731:731:731)) - (PORT d[1] (2871:2871:2871) (3032:3032:3032)) - (PORT d[2] (2051:2051:2051) (2108:2108:2108)) - (PORT d[3] (934:934:934) (973:973:973)) - (PORT d[4] (2885:2885:2885) (2988:2988:2988)) - (PORT d[5] (888:888:888) (898:898:898)) - (PORT d[6] (2709:2709:2709) (2741:2741:2741)) - (PORT d[7] (2450:2450:2450) (2499:2499:2499)) - (PORT d[8] (3738:3738:3738) (3855:3855:3855)) - (PORT d[9] (2786:2786:2786) (2789:2789:2789)) - (PORT d[10] (2681:2681:2681) (2772:2772:2772)) - (PORT d[11] (2067:2067:2067) (2173:2173:2173)) - (PORT d[12] (1944:1944:1944) (1952:1952:1952)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) + (PORT d[0] (1399:1399:1399) (1397:1397:1397)) + (PORT d[1] (2487:2487:2487) (2630:2630:2630)) + (PORT d[2] (915:915:915) (928:928:928)) + (PORT d[3] (1548:1548:1548) (1584:1584:1584)) + (PORT d[4] (2415:2415:2415) (2530:2530:2530)) + (PORT d[5] (2516:2516:2516) (2652:2652:2652)) + (PORT d[6] (901:901:901) (917:917:917)) + (PORT d[7] (894:894:894) (904:904:904)) + (PORT d[8] (1329:1329:1329) (1335:1335:1335)) + (PORT d[9] (1448:1448:1448) (1474:1474:1474)) + (PORT d[10] (2291:2291:2291) (2346:2346:2346)) + (PORT d[11] (2678:2678:2678) (2795:2795:2795)) + (PORT d[12] (1175:1175:1175) (1180:1180:1180)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) ) ) (TIMINGCHECK @@ -33914,8 +35739,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (PORT d[0] (2095:2095:2095) (2089:2089:2089)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT d[0] (779:779:779) (793:793:793)) ) ) ) @@ -33924,7 +35749,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1636:1636:1636) (1664:1664:1664)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -33934,7 +35759,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) + (PORT clk (1608:1608:1608) (1635:1635:1635)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -33948,7 +35773,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) + (PORT clk (879:879:879) (882:882:882)) ) ) ) @@ -33957,7 +35782,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) + (PORT clk (880:880:880) (883:883:883)) ) ) ) @@ -33966,7 +35791,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) + (PORT clk (880:880:880) (883:883:883)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -33976,34 +35801,18 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) + (PORT clk (880:880:880) (883:883:883)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (301:301:301)) - (PORT datab (212:212:212) (266:266:266)) - (PORT datac (206:206:206) (251:251:251)) - (PORT datad (1078:1078:1078) (1095:1095:1095)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1706:1706:1706) (1705:1705:1705)) - (PORT clk (1653:1653:1653) (1680:1680:1680)) + (PORT d[0] (865:865:865) (830:830:830)) + (PORT clk (1642:1642:1642) (1669:1669:1669)) ) ) (TIMINGCHECK @@ -34015,20 +35824,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2304:2304:2304) (2366:2366:2366)) - (PORT d[1] (1249:1249:1249) (1293:1293:1293)) - (PORT d[2] (2862:2862:2862) (3036:3036:3036)) - (PORT d[3] (2498:2498:2498) (2635:2635:2635)) - (PORT d[4] (2422:2422:2422) (2501:2501:2501)) - (PORT d[5] (1926:1926:1926) (1966:1966:1966)) - (PORT d[6] (1943:1943:1943) (1987:1987:1987)) - (PORT d[7] (2504:2504:2504) (2587:2587:2587)) - (PORT d[8] (1940:1940:1940) (1967:1967:1967)) - (PORT d[9] (3487:3487:3487) (3477:3477:3477)) - (PORT d[10] (2092:2092:2092) (2176:2176:2176)) - (PORT d[11] (2875:2875:2875) (2956:2956:2956)) - (PORT d[12] (3115:3115:3115) (3174:3174:3174)) - (PORT clk (1650:1650:1650) (1678:1678:1678)) + (PORT d[0] (2940:2940:2940) (2959:2959:2959)) + (PORT d[1] (2474:2474:2474) (2624:2624:2624)) + (PORT d[2] (1461:1461:1461) (1436:1436:1436)) + (PORT d[3] (1564:1564:1564) (1602:1602:1602)) + (PORT d[4] (2707:2707:2707) (2850:2850:2850)) + (PORT d[5] (2515:2515:2515) (2652:2652:2652)) + (PORT d[6] (902:902:902) (918:918:918)) + (PORT d[7] (1429:1429:1429) (1432:1432:1432)) + (PORT d[8] (2832:2832:2832) (2949:2949:2949)) + (PORT d[9] (924:924:924) (939:939:939)) + (PORT d[10] (2294:2294:2294) (2352:2352:2352)) + (PORT d[11] (2654:2654:2654) (2768:2768:2768)) + (PORT d[12] (2065:2065:2065) (2107:2107:2107)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) ) ) (TIMINGCHECK @@ -34040,8 +35849,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1869:1869:1869) (1845:1845:1845)) - (PORT clk (1650:1650:1650) (1678:1678:1678)) + (PORT d[0] (2843:2843:2843) (2788:2788:2788)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) ) ) (TIMINGCHECK @@ -34053,8 +35862,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (PORT d[0] (2887:2887:2887) (2881:2881:2881)) + (PORT clk (1642:1642:1642) (1669:1669:1669)) + (PORT d[0] (1605:1605:1605) (1615:1615:1615)) ) ) ) @@ -34063,7 +35872,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -34073,7 +35882,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -34083,7 +35892,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -34093,7 +35902,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -34103,7 +35912,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1612:1612:1612) (1610:1610:1610)) + (PORT clk (1601:1601:1601) (1599:1599:1599)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -34117,8 +35926,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (3428:3428:3428) (3423:3423:3423)) - (PORT clk (1620:1620:1620) (1617:1617:1617)) + (PORT d[0] (2235:2235:2235) (2216:2216:2216)) + (PORT clk (1609:1609:1609) (1606:1606:1606)) ) ) (TIMINGCHECK @@ -34130,20 +35939,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1761:1761:1761) (1809:1809:1809)) - (PORT d[1] (1826:1826:1826) (1888:1888:1888)) - (PORT d[2] (1698:1698:1698) (1707:1707:1707)) - (PORT d[3] (1776:1776:1776) (1865:1865:1865)) - (PORT d[4] (1701:1701:1701) (1730:1730:1730)) - (PORT d[5] (2029:2029:2029) (2077:2077:2077)) - (PORT d[6] (1874:1874:1874) (1860:1860:1860)) - (PORT d[7] (1850:1850:1850) (1849:1849:1849)) - (PORT d[8] (1934:1934:1934) (1927:1927:1927)) - (PORT d[9] (1806:1806:1806) (1792:1792:1792)) - (PORT d[10] (1990:1990:1990) (2007:2007:2007)) - (PORT d[11] (1876:1876:1876) (1908:1908:1908)) - (PORT d[12] (1748:1748:1748) (1778:1778:1778)) - (PORT clk (1617:1617:1617) (1614:1614:1614)) + (PORT d[0] (4297:4297:4297) (4178:4178:4178)) + (PORT d[1] (3968:3968:3968) (3900:3900:3900)) + (PORT d[2] (3965:3965:3965) (3856:3856:3856)) + (PORT d[3] (4092:4092:4092) (3987:3987:3987)) + (PORT d[4] (4044:4044:4044) (3897:3897:3897)) + (PORT d[5] (4223:4223:4223) (4114:4114:4114)) + (PORT d[6] (4401:4401:4401) (4356:4356:4356)) + (PORT d[7] (4190:4190:4190) (4089:4089:4089)) + (PORT d[8] (4127:4127:4127) (3976:3976:3976)) + (PORT d[9] (4184:4184:4184) (4235:4235:4235)) + (PORT d[10] (4172:4172:4172) (4085:4085:4085)) + (PORT d[11] (4109:4109:4109) (3983:3983:3983)) + (PORT d[12] (4090:4090:4090) (3988:3988:3988)) + (PORT clk (1606:1606:1606) (1603:1603:1603)) ) ) (TIMINGCHECK @@ -34155,7 +35964,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) + (PORT clk (1609:1609:1609) (1606:1606:1606)) ) ) ) @@ -34164,7 +35973,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -34174,7 +35983,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) ) ) @@ -34184,7 +35993,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -34194,7 +36003,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -34204,7 +36013,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1613:1613:1613) (1611:1611:1611)) + (PORT clk (1602:1602:1602) (1600:1600:1600)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -34218,10 +36027,10 @@ (INSTANCE Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (1103:1103:1103) (1104:1104:1104)) - (PORT datab (261:261:261) (344:344:344)) - (PORT datac (835:835:835) (825:825:825)) - (PORT datad (1433:1433:1433) (1464:1464:1464)) + (PORT dataa (619:619:619) (651:651:651)) + (PORT datab (1099:1099:1099) (1121:1121:1121)) + (PORT datac (777:777:777) (756:756:756)) + (PORT datad (820:820:820) (810:810:810)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -34234,10 +36043,10 @@ (INSTANCE Selector1\~1) (DELAY (ABSOLUTE - (PORT dataa (1125:1125:1125) (1137:1137:1137)) - (PORT datab (264:264:264) (348:348:348)) - (PORT datac (1427:1427:1427) (1456:1456:1456)) - (PORT datad (159:159:159) (180:180:180)) + (PORT dataa (1108:1108:1108) (1094:1094:1094)) + (PORT datab (1099:1099:1099) (1121:1121:1121)) + (PORT datac (1392:1392:1392) (1407:1407:1407)) + (PORT datad (157:157:157) (178:178:178)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -34247,31 +36056,177 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~22) + (INSTANCE D\[1\]\~103) (DELAY (ABSOLUTE - (PORT dataa (876:876:876) (895:895:895)) - (PORT datab (895:895:895) (902:902:902)) - (PORT datac (972:972:972) (952:952:952)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (1626:1626:1626) (1633:1633:1633)) + (PORT datab (1300:1300:1300) (1339:1339:1339)) + (PORT datac (595:595:595) (621:621:621)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~23) + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_DAT\~input) (DELAY (ABSOLUTE - (PORT dataa (1707:1707:1707) (1716:1716:1716)) - (PORT datab (1976:1976:1976) (2049:2049:2049)) - (PORT datac (3020:3020:3020) (3086:3086:3086)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (768:768:768) (767:767:767)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (256:256:256) (347:347:347)) + (PORT datab (261:261:261) (345:345:345)) + (PORT datad (220:220:220) (289:289:289)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_CLK\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (2920:2920:2920) (3165:3165:3165)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (204:204:204) (265:265:265)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (208:208:208) (270:270:270)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (218:218:218) (276:276:276)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (305:305:305)) + (PORT datab (229:229:229) (299:299:299)) + (PORT datac (352:352:352) (390:390:390)) + (PORT datad (206:206:206) (266:266:266)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -34279,15 +36234,325 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~29) + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (647:647:647) (693:693:693)) - (PORT datab (316:316:316) (331:331:331)) - (PORT datac (640:640:640) (657:657:657)) - (PORT datad (809:809:809) (795:795:795)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT datad (207:207:207) (267:267:267)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (208:208:208) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (204:204:204) (266:266:266)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (230:230:230) (301:301:301)) + (PORT datac (203:203:203) (273:273:273)) + (PORT datad (207:207:207) (267:267:267)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (204:204:204) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) + (DELAY + (ABSOLUTE + (PORT datab (189:189:189) (225:225:225)) + (PORT datad (207:207:207) (267:267:267)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) + (DELAY + (ABSOLUTE + (PORT datab (189:189:189) (226:226:226)) + (PORT datac (197:197:197) (265:265:265)) + (PORT datad (204:204:204) (263:263:263)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1369:1369:1369)) + (PORT ena (1851:1851:1851) (1843:1843:1843)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) + (DELAY + (ABSOLUTE + (PORT dataa (257:257:257) (347:347:347)) + (PORT datab (261:261:261) (345:345:345)) + (PORT datad (217:217:217) (282:282:282)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1369:1369:1369)) + (PORT ena (1851:1851:1851) (1843:1843:1843)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (252:252:252) (332:332:332)) + (PORT datad (220:220:220) (286:286:286)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1369:1369:1369)) + (PORT ena (1851:1851:1851) (1843:1843:1843)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (424:424:424)) + (PORT datab (253:253:253) (334:334:334)) + (PORT datad (220:220:220) (287:287:287)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1369:1369:1369)) + (PORT ena (1851:1851:1851) (1843:1843:1843)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (338:338:338)) + (PORT datab (257:257:257) (338:338:338)) + (PORT datac (2974:2974:2974) (3250:3250:3250)) + (PORT datad (226:226:226) (296:296:296)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT datab (259:259:259) (343:343:343)) + (PORT datac (225:225:225) (310:310:310)) + (PORT datad (223:223:223) (292:292:292)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -34295,31 +36560,253 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (651:651:651) (681:681:681)) - (PORT datab (1112:1112:1112) (1148:1148:1148)) - (PORT datac (355:355:355) (389:389:389)) - (PORT datad (566:566:566) (556:556:556)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (241:241:241) (316:316:316)) + (PORT datac (1265:1265:1265) (1274:1274:1274)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT asdata (3472:3472:3472) (3720:3720:3720)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT ena (1120:1120:1120) (1082:1082:1082)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT asdata (506:506:506) (568:568:568)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT ena (1120:1120:1120) (1082:1082:1082)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT asdata (540:540:540) (613:613:613)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT ena (1120:1120:1120) (1082:1082:1082)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT asdata (530:530:530) (596:596:596)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT ena (1120:1120:1120) (1082:1082:1082)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT asdata (875:875:875) (902:902:902)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT ena (1102:1102:1102) (1092:1092:1092)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT asdata (887:887:887) (901:901:901)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT ena (1120:1120:1120) (1082:1082:1082)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT asdata (872:872:872) (902:902:902)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT ena (1102:1102:1102) (1092:1092:1092)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT asdata (694:694:694) (750:750:750)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT ena (1102:1102:1102) (1092:1092:1092)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT asdata (705:705:705) (769:769:769)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT ena (1102:1102:1102) (1092:1092:1092)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (948:948:948)) + (PORT datab (620:620:620) (670:670:670)) + (PORT datac (696:696:696) (773:773:773)) + (PORT datad (707:707:707) (791:791:791)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (1217:1217:1217) (1267:1267:1267)) - (PORT datab (1166:1166:1166) (1191:1191:1191)) - (PORT datac (759:759:759) (739:739:739)) - (PORT datad (528:528:528) (518:518:518)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (1301:1301:1301) (1379:1379:1379)) + (PORT datab (856:856:856) (908:908:908)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (703:703:703) (782:782:782)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT datab (980:980:980) (1034:1034:1034)) + (PORT datad (732:732:732) (716:716:716)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (644:644:644)) + (PORT datab (259:259:259) (336:336:336)) + (PORT datad (770:770:770) (786:786:786)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (726:726:726)) + (PORT datab (617:617:617) (658:658:658)) + (PORT datac (597:597:597) (631:631:631)) + (PORT datad (407:407:407) (451:451:451)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -34327,14 +36814,309 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) (DELAY (ABSOLUTE - (PORT dataa (1072:1072:1072) (1088:1088:1088)) - (PORT datab (1005:1005:1005) (1020:1020:1020)) - (PORT datac (1094:1094:1094) (1144:1144:1144)) - (PORT datad (977:977:977) (957:957:957)) + (PORT datab (621:621:621) (646:646:646)) + (PORT datac (323:323:323) (326:326:326)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (230:230:230)) + (PORT datab (2992:2992:2992) (3284:3284:3284)) + (PORT datac (1265:1265:1265) (1274:1274:1274)) + (PORT datad (335:335:335) (348:348:348)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1369:1369:1369)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|extended) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (PORT ena (1618:1618:1618) (1613:1613:1613)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (660:660:660)) + (PORT datab (620:620:620) (628:628:628)) + (PORT datac (231:231:231) (309:309:309)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (495:495:495)) + (PORT datac (1250:1250:1250) (1305:1305:1305)) + (PORT datad (782:782:782) (772:772:772)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1146:1146:1146)) + (PORT datac (586:586:586) (609:609:609)) + (PORT datad (837:837:837) (881:881:881)) (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (385:385:385)) + (PORT datac (565:565:565) (594:594:594)) + (PORT datad (673:673:673) (704:704:704)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (648:648:648)) + (PORT datab (618:618:618) (630:630:630)) + (PORT datad (1230:1230:1230) (1225:1225:1225)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (500:500:500)) + (PORT datab (607:607:607) (656:656:656)) + (PORT datac (560:560:560) (597:597:597)) + (PORT datad (236:236:236) (299:299:299)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (223:223:223)) + (PORT datac (382:382:382) (444:444:444)) + (PORT datad (605:605:605) (640:640:640)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (547:547:547)) + (PORT datab (394:394:394) (454:454:454)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (747:747:747)) + (PORT datab (911:911:911) (954:954:954)) + (PORT datad (887:887:887) (928:928:928)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT datab (690:690:690) (758:758:758)) + (PORT datac (684:684:684) (751:751:751)) + (PORT datad (679:679:679) (744:744:744)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (348:348:348)) + (PORT datab (185:185:185) (218:218:218)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (884:884:884) (934:934:934)) + (PORT datad (679:679:679) (743:743:743)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (741:741:741)) + (PORT datab (259:259:259) (336:336:336)) + (PORT datac (596:596:596) (634:634:634)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (608:608:608) (641:641:641)) + (PORT datac (367:367:367) (415:415:415)) + (PORT datad (604:604:604) (638:638:638)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -34343,91 +37125,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) (DELAY (ABSOLUTE - (PORT dataa (737:737:737) (736:736:736)) - (PORT datab (1004:1004:1004) (1021:1021:1021)) - (PORT datac (162:162:162) (197:197:197)) - (PORT datad (951:951:951) (915:915:915)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1562:1562:1562) (1529:1529:1529)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1173:1173:1173)) - (PORT datac (1065:1065:1065) (1047:1047:1047)) - (PORT datad (947:947:947) (935:935:935)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1515:1515:1515) (1485:1485:1485)) - (PORT datab (964:964:964) (939:939:939)) - (PORT datac (648:648:648) (712:712:712)) - (PORT datad (627:627:627) (654:654:654)) + (PORT dataa (352:352:352) (371:371:371)) + (PORT datab (201:201:201) (243:243:243)) + (PORT datac (599:599:599) (634:634:634)) + (PORT datad (402:402:402) (446:446:446)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1082:1082:1082) (1066:1066:1066)) - (PORT datab (702:702:702) (692:692:692)) - (PORT datac (161:161:161) (194:194:194)) - (PORT datad (1132:1132:1132) (1174:1174:1174)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (548:548:548)) - (PORT datac (713:713:713) (709:709:709)) - (PORT datad (176:176:176) (197:197:197)) - (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -34435,14 +37141,207 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~13) + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) (DELAY (ABSOLUTE - (PORT dataa (849:849:849) (872:872:872)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (569:569:569) (580:580:580)) - (PORT datad (593:593:593) (607:607:607)) - (IOPATH dataa combout (265:265:265) (269:269:269)) + (PORT dataa (205:205:205) (243:243:243)) + (PORT datab (574:574:574) (597:597:597)) + (PORT datad (887:887:887) (926:926:926)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1075:1075:1075) (1096:1096:1096)) + (PORT datab (220:220:220) (287:287:287)) + (PORT datac (195:195:195) (261:261:261)) + (PORT datad (511:511:511) (509:509:509)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (924:924:924)) + (PORT datac (825:825:825) (873:873:873)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1298:1298:1298) (1375:1375:1375)) + (PORT datab (636:636:636) (660:660:660)) + (PORT datac (882:882:882) (922:922:922)) + (PORT datad (171:171:171) (202:202:202)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (909:909:909) (952:952:952)) + (PORT datac (663:663:663) (734:734:734)) + (PORT datad (679:679:679) (745:745:745)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (815:815:815)) + (PORT datab (615:615:615) (612:612:612)) + (PORT datad (468:468:468) (456:456:456)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1293:1293:1293) (1369:1369:1369)) + (PORT datab (194:194:194) (232:232:232)) + (PORT datac (608:608:608) (629:629:629)) + (PORT datad (706:706:706) (778:778:778)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (731:731:731)) + (PORT datab (331:331:331) (353:353:353)) + (PORT datac (658:658:658) (726:726:726)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1436:1436:1436) (1485:1485:1485)) + (PORT datab (909:909:909) (926:926:926)) + (PORT datad (485:485:485) (469:469:469)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~0) + (DELAY + (ABSOLUTE + (PORT datab (1374:1374:1374) (1416:1416:1416)) + (PORT datac (846:846:846) (881:881:881)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (391:391:391) (450:450:450)) + (PORT datac (1029:1029:1029) (1039:1039:1039)) + (PORT datad (605:605:605) (641:641:641)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -34451,95 +37350,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) (DELAY (ABSOLUTE - (PORT dataa (641:641:641) (660:660:660)) - (PORT datab (1026:1026:1026) (1001:1001:1001)) - (PORT datac (541:541:541) (564:564:564)) - (PORT datad (948:948:948) (934:934:934)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1752:1752:1752) (1674:1674:1674)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1346:1346:1346)) - (PORT datab (1414:1414:1414) (1353:1353:1353)) - (PORT datac (1176:1176:1176) (1148:1148:1148)) - (PORT datad (1272:1272:1272) (1283:1283:1283)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (368:368:368)) - (PORT datab (1109:1109:1109) (1115:1115:1115)) - (PORT datac (869:869:869) (886:886:886)) - (PORT datad (1434:1434:1434) (1424:1424:1424)) - (IOPATH dataa combout (272:272:272) (269:269:269)) + (PORT dataa (651:651:651) (689:689:689)) + (PORT datab (375:375:375) (438:438:438)) + (PORT datac (562:562:562) (598:598:598)) + (PORT datad (238:238:238) (303:303:303)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT datac (254:254:254) (343:343:343)) - (PORT datad (265:265:265) (344:344:344)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -34547,29 +37366,92 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) (DELAY (ABSOLUTE - (PORT dataa (372:372:372) (412:412:412)) - (PORT datab (1266:1266:1266) (1278:1278:1278)) - (PORT datac (1253:1253:1253) (1265:1265:1265)) - (PORT datad (1927:1927:1927) (1923:1923:1923)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (436:436:436) (502:502:502)) + (PORT datab (608:608:608) (658:658:658)) + (PORT datac (463:463:463) (456:456:456)) + (PORT datad (609:609:609) (642:642:642)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) (DELAY (ABSOLUTE - (PORT dataa (1043:1043:1043) (1040:1040:1040)) - (PORT datab (863:863:863) (883:883:883)) - (PORT datac (1873:1873:1873) (1893:1893:1893)) - (PORT datad (1089:1089:1089) (1102:1102:1102)) + (PORT dataa (553:553:553) (546:546:546)) + (PORT datab (183:183:183) (215:215:215)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (680:680:680)) + (PORT datab (1141:1141:1141) (1156:1156:1156)) + (PORT datac (403:403:403) (453:453:453)) + (PORT datad (985:985:985) (970:970:970)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (749:749:749)) + (PORT datab (1279:1279:1279) (1336:1336:1336)) + (PORT datac (842:842:842) (874:874:874)) + (PORT datad (796:796:796) (814:814:814)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (254:254:254)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (678:678:678) (745:745:745)) + (PORT datad (1423:1423:1423) (1456:1456:1456)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -34579,29 +37461,424 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) (DELAY (ABSOLUTE - (PORT dataa (1020:1020:1020) (1020:1020:1020)) - (PORT datab (818:818:818) (808:808:808)) - (PORT datac (1176:1176:1176) (1148:1148:1148)) - (PORT datad (332:332:332) (332:332:332)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT datab (491:491:491) (476:476:476)) + (PORT datad (870:870:870) (892:892:892)) (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (745:745:745) (752:752:752)) + (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (649:649:649)) + (PORT datab (1042:1042:1042) (1062:1062:1062)) + (PORT datac (587:587:587) (615:615:615)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (676:676:676)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (176:176:176) (208:208:208)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (443:443:443) (492:492:492)) + (PORT datab (1139:1139:1139) (1158:1158:1158)) + (PORT datac (680:680:680) (750:750:750)) + (PORT datad (782:782:782) (771:771:771)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (774:774:774)) + (PORT datab (835:835:835) (872:872:872)) + (PORT datac (1026:1026:1026) (1029:1029:1029)) + (PORT datad (652:652:652) (707:707:707)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (354:354:354)) + (PORT datac (641:641:641) (699:699:699)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (779:779:779)) + (PORT datab (834:834:834) (870:870:870)) + (PORT datac (606:606:606) (657:657:657)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datad (162:162:162) (183:183:183)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (628:628:628)) + (PORT datab (450:450:450) (517:517:517)) + (PORT datac (368:368:368) (413:413:413)) + (PORT datad (563:563:563) (566:566:566)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (755:755:755) (835:835:835)) + (PORT datab (859:859:859) (909:909:909)) + (PORT datac (697:697:697) (774:774:774)) + (PORT datad (704:704:704) (777:777:777)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (830:830:830)) + (PORT datab (724:724:724) (796:796:796)) + (PORT datad (703:703:703) (783:783:783)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (753:753:753) (833:833:833)) + (PORT datab (856:856:856) (908:908:908)) + (PORT datac (696:696:696) (771:771:771)) + (PORT datad (703:703:703) (782:782:782)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (251:251:251)) + (PORT datab (860:860:860) (910:910:910)) + (PORT datac (294:294:294) (304:304:304)) + (PORT datad (1278:1278:1278) (1340:1340:1340)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1381:1381:1381)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (858:858:858) (889:889:889)) + (PORT datad (486:486:486) (471:471:471)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (358:358:358)) + (PORT datab (248:248:248) (320:320:320)) + (PORT datad (555:555:555) (562:562:562)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1286:1286:1286) (1286:1286:1286)) + (PORT datab (382:382:382) (420:420:420)) + (PORT datac (1267:1267:1267) (1269:1269:1269)) + (PORT datad (539:539:539) (559:559:559)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (723:723:723)) + (PORT datab (3109:3109:3109) (3117:3117:3117)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1571:1571:1571) (1565:1565:1565)) + (PORT datab (1140:1140:1140) (1173:1173:1173)) + (PORT datac (587:587:587) (604:604:604)) + (PORT datad (1059:1059:1059) (1058:1058:1058)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1399:1399:1399) (1419:1419:1419)) + (PORT datab (1141:1141:1141) (1174:1174:1174)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (1149:1149:1149) (1213:1213:1213)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (945:945:945)) + (PORT datab (598:598:598) (605:605:605)) + (PORT datac (212:212:212) (262:262:262)) + (PORT datad (1541:1541:1541) (1544:1544:1544)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (846:846:846) (848:848:848)) + (PORT datac (872:872:872) (898:898:898)) + (PORT datad (200:200:200) (230:230:230)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (279:279:279)) + (PORT datab (656:656:656) (683:683:683)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (188:188:188) (217:217:217)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (178:178:178) (199:199:199)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1395:1395:1395) (1367:1367:1367)) + (PORT ena (1130:1130:1130) (1103:1103:1103)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -34613,15 +37890,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) + (INSTANCE z80_\|pla_decode_\|Equal40\~0) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1301:1301:1301)) - (PORT datab (1206:1206:1206) (1216:1216:1216)) - (PORT datac (255:255:255) (343:343:343)) - (PORT datad (266:266:266) (343:343:343)) + (PORT dataa (257:257:257) (345:345:345)) + (PORT datac (836:836:836) (862:862:862)) + (PORT datad (853:853:853) (877:877:877)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -34629,13 +37904,127 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) + (INSTANCE z80_\|pla_decode_\|Equal21\~1) (DELAY (ABSOLUTE - (PORT dataa (1150:1150:1150) (1211:1211:1211)) - (PORT datac (637:637:637) (703:703:703)) - (PORT datad (770:770:770) (763:763:763)) - (IOPATH dataa combout (287:287:287) (289:289:289)) + (PORT dataa (1308:1308:1308) (1362:1362:1362)) + (PORT datab (817:817:817) (820:820:820)) + (PORT datac (843:843:843) (887:887:887)) + (PORT datad (792:792:792) (800:800:800)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1453:1453:1453) (1518:1518:1518)) + (PORT datab (2173:2173:2173) (2172:2172:2172)) + (PORT datac (613:613:613) (644:644:644)) + (PORT datad (2549:2549:2549) (2541:2541:2541)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (207:207:207) (255:255:255)) + (PORT datac (174:174:174) (213:213:213)) + (PORT datad (348:348:348) (354:354:354)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (576:576:576)) + (PORT datab (395:395:395) (417:417:417)) + (PORT datac (511:511:511) (505:505:505)) + (PORT datad (1080:1080:1080) (1089:1089:1089)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1376:1376:1376) (1411:1411:1411)) + (PORT datab (409:409:409) (421:421:421)) + (PORT datac (858:858:858) (881:881:881)) + (PORT datad (191:191:191) (220:220:220)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (927:927:927)) + (PORT datab (1034:1034:1034) (1042:1042:1042)) + (PORT datac (1148:1148:1148) (1192:1192:1192)) + (PORT datad (1252:1252:1252) (1251:1251:1251)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1017:1017:1017) (1011:1011:1011)) + (PORT datab (888:888:888) (937:937:937)) + (PORT datac (1150:1150:1150) (1193:1193:1193)) + (PORT datad (1112:1112:1112) (1148:1148:1148)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1399:1399:1399) (1353:1353:1353)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (796:796:796) (768:768:768)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -34643,14 +38032,785 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) (DELAY (ABSOLUTE - (PORT dataa (503:503:503) (512:512:512)) - (PORT datab (864:864:864) (892:892:892)) - (PORT datac (1416:1416:1416) (1404:1404:1404)) - (PORT datad (572:572:572) (577:577:577)) + (PORT dataa (1484:1484:1484) (1470:1470:1470)) + (PORT datab (771:771:771) (770:770:770)) + (PORT datad (963:963:963) (922:922:922)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1446:1446:1446) (1433:1433:1433)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (596:596:596) (611:611:611)) + (PORT datad (514:514:514) (514:514:514)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (594:594:594)) + (PORT datab (519:519:519) (506:506:506)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (349:349:349) (349:349:349)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~21) + (DELAY + (ABSOLUTE + (PORT dataa (2085:2085:2085) (2088:2088:2088)) + (PORT datab (1436:1436:1436) (1471:1471:1471)) + (PORT datac (826:826:826) (842:842:842)) + (PORT datad (1068:1068:1068) (1049:1049:1049)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT datab (205:205:205) (250:250:250)) + (PORT datac (317:317:317) (325:325:325)) + (PORT datad (346:346:346) (349:349:349)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1228:1228:1228)) + (PORT datab (862:862:862) (890:890:890)) + (PORT datac (1793:1793:1793) (1848:1848:1848)) + (PORT datad (1891:1891:1891) (1998:1998:1998)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (807:807:807)) + (PORT datab (206:206:206) (250:250:250)) + (PORT datac (175:175:175) (215:215:215)) + (PORT datad (347:347:347) (349:349:349)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1056:1056:1056)) + (PORT datab (181:181:181) (215:215:215)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (199:199:199) (241:241:241)) + (PORT datac (180:180:180) (213:213:213)) + (PORT datad (202:202:202) (226:226:226)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1784:1784:1784) (1819:1819:1819)) + (PORT datab (2405:2405:2405) (2428:2428:2428)) + (PORT datad (1328:1328:1328) (1372:1372:1372)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (643:643:643)) + (PORT datab (640:640:640) (670:670:670)) + (PORT datac (1015:1015:1015) (996:996:996)) + (PORT datad (595:595:595) (619:619:619)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (229:229:229)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (567:567:567) (559:559:559)) + (PORT datad (727:727:727) (716:716:716)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (790:790:790)) + (PORT datab (309:309:309) (327:327:327)) + (PORT datac (348:348:348) (352:352:352)) + (PORT datad (565:565:565) (566:566:566)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1673:1673:1673) (1700:1700:1700)) + (PORT datab (850:850:850) (888:888:888)) + (PORT datac (842:842:842) (887:887:887)) + (PORT datad (395:395:395) (415:415:415)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (859:859:859)) + (PORT datac (837:837:837) (829:829:829)) + (PORT datad (1282:1282:1282) (1295:1295:1295)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (399:399:399)) + (PORT datac (173:173:173) (204:204:204)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1072:1072:1072) (1102:1102:1102)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (554:554:554) (559:559:559)) + (PORT datad (340:340:340) (356:356:356)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1073:1073:1073) (1100:1100:1100)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datad (807:807:807) (826:826:826)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (1332:1332:1332) (1350:1350:1350)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2259:2259:2259) (2263:2263:2263)) + (PORT datab (1492:1492:1492) (1553:1553:1553)) + (PORT datac (1648:1648:1648) (1714:1714:1714)) + (PORT datad (1531:1531:1531) (1547:1547:1547)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1324:1324:1324) (1370:1370:1370)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (970:970:970) (992:992:992)) + (PORT datad (1241:1241:1241) (1202:1202:1202)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1036:1036:1036) (1128:1128:1128)) + (PORT datac (822:822:822) (852:852:852)) + (PORT datad (882:882:882) (922:922:922)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (841:841:841)) + (PORT datab (867:867:867) (913:913:913)) + (PORT datac (549:549:549) (540:540:540)) + (PORT datad (502:502:502) (480:480:480)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (783:783:783) (768:768:768)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (175:175:175) (205:205:205)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1073:1073:1073) (1121:1121:1121)) + (PORT datab (233:233:233) (308:308:308)) + (PORT datac (194:194:194) (260:260:260)) + (PORT datad (540:540:540) (539:539:539)) (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (531:531:531)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (550:550:550) (563:563:563)) + (PORT datad (561:561:561) (538:538:538)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1449:1449:1449) (1544:1544:1544)) + (PORT datab (2385:2385:2385) (2384:2384:2384)) + (PORT datac (987:987:987) (972:972:972)) + (PORT datad (794:794:794) (809:809:809)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1016:1016:1016) (1000:1000:1000)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1096:1096:1096) (1117:1117:1117)) + (PORT datad (524:524:524) (510:510:510)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (823:823:823)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (210:210:210) (251:251:251)) + (PORT datad (551:551:551) (547:547:547)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (913:913:913)) + (PORT datab (236:236:236) (278:278:278)) + (PORT datac (1287:1287:1287) (1301:1301:1301)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (851:851:851)) + (PORT datab (1045:1045:1045) (1074:1074:1074)) + (PORT datac (818:818:818) (827:827:827)) + (PORT datad (937:937:937) (906:906:906)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) + (DELAY + (ABSOLUTE + (PORT dataa (441:441:441) (457:457:457)) + (PORT datab (831:831:831) (816:816:816)) + (PORT datac (841:841:841) (886:886:886)) + (PORT datad (374:374:374) (385:385:385)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT datab (983:983:983) (967:967:967)) + (PORT datac (187:187:187) (227:227:227)) + (PORT datad (190:190:190) (217:217:217)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (483:483:483) (492:492:492)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (550:550:550) (547:547:547)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (531:531:531) (513:513:513)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (657:657:657)) + (PORT datab (601:601:601) (632:632:632)) + (PORT datac (822:822:822) (816:816:816)) + (PORT datad (826:826:826) (831:831:831)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1067:1067:1067) (1074:1074:1074)) + (PORT datad (577:577:577) (571:571:571)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (363:363:363)) + (PORT datab (603:603:603) (604:604:604)) + (PORT datac (807:807:807) (813:813:813)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (647:647:647)) + (PORT datab (880:880:880) (876:876:876)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (193:193:193) (226:226:226)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (686:686:686)) + (PORT datac (1028:1028:1028) (1027:1027:1027)) + (PORT datad (680:680:680) (743:743:743)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (771:771:771)) + (PORT datab (665:665:665) (720:720:720)) + (PORT datac (1028:1028:1028) (1028:1028:1028)) + (PORT datad (653:653:653) (704:704:704)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (222:222:222)) + (PORT datab (837:837:837) (875:875:875)) + (PORT datac (1028:1028:1028) (1028:1028:1028)) + (PORT datad (313:313:313) (315:315:315)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (237:237:237)) + (PORT datab (183:183:183) (216:216:216)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (717:717:717)) + (PORT datab (908:908:908) (950:950:950)) + (PORT datac (664:664:664) (735:735:735)) + (PORT datad (679:679:679) (744:744:744)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (811:811:811)) + (PORT datab (672:672:672) (736:736:736)) + (PORT datac (658:658:658) (726:726:726)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (345:345:345)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datad (315:315:315) (314:314:314)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1075:1075:1075) (1095:1095:1095)) + (PORT datab (670:670:670) (717:717:717)) + (PORT datac (194:194:194) (261:261:261)) + (PORT datad (513:513:513) (512:512:512)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (905:905:905)) + (PORT datab (714:714:714) (780:780:780)) + (PORT datac (1248:1248:1248) (1310:1310:1310)) + (PORT datad (1100:1100:1100) (1121:1121:1121)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~76) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (337:337:337)) + (PORT datab (256:256:256) (326:326:326)) + (PORT datac (861:861:861) (853:853:853)) + (PORT datad (1380:1380:1380) (1419:1419:1419)) + (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -34659,13 +38819,3932 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~73) (DELAY (ABSOLUTE - (PORT dataa (583:583:583) (597:597:597)) - (PORT datab (1080:1080:1080) (1067:1067:1067)) - (PORT datac (520:520:520) (520:520:520)) - (PORT datad (1591:1591:1591) (1616:1616:1616)) + (PORT datac (680:680:680) (749:749:749)) + (PORT datad (1100:1100:1100) (1125:1125:1125)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (703:703:703) (772:772:772)) + (PORT datab (668:668:668) (725:725:725)) + (PORT datac (808:808:808) (845:845:845)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (696:696:696) (748:748:748)) + (PORT datab (1393:1393:1393) (1427:1427:1427)) + (PORT datac (841:841:841) (877:877:877)) + (PORT datad (794:794:794) (812:812:812)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~74) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (552:552:552)) + (PORT datab (320:320:320) (328:328:328)) + (PORT datac (1249:1249:1249) (1304:1304:1304)) + (PORT datad (1423:1423:1423) (1456:1456:1456)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (221:221:221)) + (PORT datab (184:184:184) (218:218:218)) + (PORT datac (407:407:407) (460:460:460)) + (PORT datad (782:782:782) (772:772:772)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (507:507:507)) + (PORT datab (311:311:311) (328:328:328)) + (PORT datad (678:678:678) (741:741:741)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (765:765:765)) + (PORT datab (673:673:673) (738:738:738)) + (PORT datac (304:304:304) (328:328:328)) + (PORT datad (1044:1044:1044) (1061:1061:1061)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) + (DELAY + (ABSOLUTE + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (662:662:662) (728:728:728)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (406:406:406)) + (PORT datab (1045:1045:1045) (1066:1066:1066)) + (PORT datac (590:590:590) (619:619:619)) + (PORT datad (581:581:581) (606:606:606)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (1438:1438:1438) (1484:1484:1484)) + (PORT datab (907:907:907) (923:923:923)) + (PORT datad (482:482:482) (467:467:467)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (501:501:501)) + (PORT datac (561:561:561) (596:596:596)) + (PORT datad (237:237:237) (299:299:299)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (380:380:380)) + (PORT datab (785:785:785) (759:759:759)) + (PORT datad (676:676:676) (737:737:737)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~1) + (DELAY + (ABSOLUTE + (PORT datab (1378:1378:1378) (1422:1422:1422)) + (PORT datac (321:321:321) (369:369:369)) + (PORT datad (844:844:844) (870:870:870)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (194:194:194) (261:261:261)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~1) + (DELAY + (ABSOLUTE + (PORT datac (985:985:985) (1045:1045:1045)) + (PORT datad (950:950:950) (998:998:998)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (1296:1296:1296) (1372:1372:1372)) + (PORT datab (724:724:724) (795:795:795)) + (PORT datac (883:883:883) (919:919:919)) + (PORT datad (704:704:704) (784:784:784)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (231:231:231)) + (PORT datab (620:620:620) (630:630:630)) + (PORT datac (562:562:562) (552:552:552)) + (PORT datad (828:828:828) (861:861:861)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) + (DELAY + (ABSOLUTE + (PORT datab (889:889:889) (937:937:937)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT datac (595:595:595) (633:633:633)) + (PORT datad (586:586:586) (621:621:621)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT datab (606:606:606) (639:639:639)) + (PORT datac (625:625:625) (684:684:684)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (233:233:233)) + (PORT datab (443:443:443) (484:484:484)) + (PORT datac (592:592:592) (619:619:619)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (250:250:250)) + (PORT datab (607:607:607) (657:657:657)) + (PORT datad (604:604:604) (646:646:646)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (829:829:829)) + (PORT datab (203:203:203) (237:237:237)) + (PORT datac (314:314:314) (325:325:325)) + (PORT datad (504:504:504) (497:497:497)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (731:731:731)) + (PORT datad (871:871:871) (888:888:888)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1287:1287:1287) (1283:1283:1283)) + (PORT datab (555:555:555) (582:582:582)) + (PORT datac (1267:1267:1267) (1266:1266:1266)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (722:722:722)) + (PORT datab (3110:3110:3110) (3118:3118:3118)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (827:827:827) (822:822:822)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1142:1142:1142) (1152:1152:1152)) + (PORT d[1] (912:912:912) (937:937:937)) + (PORT d[2] (890:890:890) (884:884:884)) + (PORT d[3] (943:943:943) (966:966:966)) + (PORT d[4] (2421:2421:2421) (2524:2524:2524)) + (PORT d[5] (955:955:955) (960:960:960)) + (PORT d[6] (919:919:919) (944:944:944)) + (PORT d[7] (883:883:883) (901:901:901)) + (PORT d[8] (969:969:969) (983:983:983)) + (PORT d[9] (923:923:923) (948:948:948)) + (PORT d[10] (973:973:973) (1007:1007:1007)) + (PORT d[11] (2392:2392:2392) (2487:2487:2487)) + (PORT d[12] (1206:1206:1206) (1236:1236:1236)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (871:871:871) (835:835:835)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (1334:1334:1334) (1304:1304:1304)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (905:905:905) (887:887:887)) + (PORT clk (1646:1646:1646) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (655:655:655) (654:654:654)) + (PORT d[1] (2216:2216:2216) (2370:2370:2370)) + (PORT d[2] (1386:1386:1386) (1401:1401:1401)) + (PORT d[3] (909:909:909) (925:925:925)) + (PORT d[4] (2407:2407:2407) (2520:2520:2520)) + (PORT d[5] (3216:3216:3216) (3328:3328:3328)) + (PORT d[6] (1174:1174:1174) (1189:1189:1189)) + (PORT d[7] (2944:2944:2944) (2982:2982:2982)) + (PORT d[8] (644:644:644) (645:645:645)) + (PORT d[9] (1480:1480:1480) (1519:1519:1519)) + (PORT d[10] (1247:1247:1247) (1289:1289:1289)) + (PORT d[11] (2074:2074:2074) (2159:2159:2159)) + (PORT d[12] (1446:1446:1446) (1472:1472:1472)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (612:612:612) (573:573:573)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT d[0] (1332:1332:1332) (1279:1279:1279)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1637:1637:1637)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1018:1018:1018) (1000:1000:1000)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (908:908:908) (912:912:912)) + (PORT d[1] (3190:3190:3190) (3345:3345:3345)) + (PORT d[2] (1153:1153:1153) (1157:1157:1157)) + (PORT d[3] (1182:1182:1182) (1204:1204:1204)) + (PORT d[4] (2395:2395:2395) (2506:2506:2506)) + (PORT d[5] (3231:3231:3231) (3348:3348:3348)) + (PORT d[6] (1217:1217:1217) (1267:1267:1267)) + (PORT d[7] (1126:1126:1126) (1137:1137:1137)) + (PORT d[8] (929:929:929) (929:929:929)) + (PORT d[9] (1442:1442:1442) (1473:1473:1473)) + (PORT d[10] (1257:1257:1257) (1304:1304:1304)) + (PORT d[11] (2094:2094:2094) (2179:2179:2179)) + (PORT d[12] (1480:1480:1480) (1518:1518:1518)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (881:881:881) (829:829:829)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (PORT d[0] (1526:1526:1526) (1472:1472:1472)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (362:362:362)) + (PORT datab (624:624:624) (664:664:664)) + (PORT datac (603:603:603) (641:641:641)) + (PORT datad (598:598:598) (583:583:583)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1105:1105:1105) (1088:1088:1088)) + (PORT clk (1637:1637:1637) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3379:3379:3379) (3446:3446:3446)) + (PORT d[1] (1268:1268:1268) (1347:1347:1347)) + (PORT d[2] (1861:1861:1861) (1882:1882:1882)) + (PORT d[3] (2267:2267:2267) (2330:2330:2330)) + (PORT d[4] (2046:2046:2046) (2106:2106:2106)) + (PORT d[5] (1246:1246:1246) (1306:1306:1306)) + (PORT d[6] (1355:1355:1355) (1373:1373:1373)) + (PORT d[7] (3098:3098:3098) (3120:3120:3120)) + (PORT d[8] (3347:3347:3347) (3464:3464:3464)) + (PORT d[9] (2928:2928:2928) (2995:2995:2995)) + (PORT d[10] (2921:2921:2921) (2980:2980:2980)) + (PORT d[11] (1660:1660:1660) (1694:1694:1694)) + (PORT d[12] (1319:1319:1319) (1343:1343:1343)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1505:1505:1505) (1437:1437:1437)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1665:1665:1665)) + (PORT d[0] (2529:2529:2529) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (936:936:936)) + (PORT datab (1299:1299:1299) (1349:1349:1349)) + (PORT datac (502:502:502) (483:483:483)) + (PORT datad (1089:1089:1089) (1062:1062:1062)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1522:1522:1522) (1552:1552:1552)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2671:2671:2671) (2689:2689:2689)) + (PORT d[1] (1867:1867:1867) (1957:1957:1957)) + (PORT d[2] (1810:1810:1810) (1839:1839:1839)) + (PORT d[3] (1758:1758:1758) (1816:1816:1816)) + (PORT d[4] (2803:2803:2803) (2841:2841:2841)) + (PORT d[5] (2060:2060:2060) (2153:2153:2153)) + (PORT d[6] (1591:1591:1591) (1614:1614:1614)) + (PORT d[7] (1980:1980:1980) (2023:2023:2023)) + (PORT d[8] (2256:2256:2256) (2327:2327:2327)) + (PORT d[9] (1564:1564:1564) (1597:1597:1597)) + (PORT d[10] (1345:1345:1345) (1361:1361:1361)) + (PORT d[11] (1607:1607:1607) (1625:1625:1625)) + (PORT d[12] (2124:2124:2124) (2140:2140:2140)) + (PORT clk (1640:1640:1640) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2368:2368:2368) (2344:2344:2344)) + (PORT clk (1640:1640:1640) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (3338:3338:3338) (3343:3343:3343)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1601:1601:1601)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1885:1885:1885) (1823:1823:1823)) + (PORT clk (1610:1610:1610) (1608:1608:1608)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4094:4094:4094) (4004:4004:4004)) + (PORT d[1] (3872:3872:3872) (3773:3773:3773)) + (PORT d[2] (3969:3969:3969) (3885:3885:3885)) + (PORT d[3] (4229:4229:4229) (4158:4158:4158)) + (PORT d[4] (4027:4027:4027) (3879:3879:3879)) + (PORT d[5] (4301:4301:4301) (4209:4209:4209)) + (PORT d[6] (4101:4101:4101) (4071:4071:4071)) + (PORT d[7] (4030:4030:4030) (3869:3869:3869)) + (PORT d[8] (4251:4251:4251) (4163:4163:4163)) + (PORT d[9] (4115:4115:4115) (4191:4191:4191)) + (PORT d[10] (4389:4389:4389) (4323:4323:4323)) + (PORT d[11] (4066:4066:4066) (3954:3954:3954)) + (PORT d[12] (4192:4192:4192) (4207:4207:4207)) + (PORT clk (1607:1607:1607) (1605:1605:1605)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1608:1608:1608)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1602:1602:1602)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2638:2638:2638) (2644:2644:2644)) + (PORT d[1] (1609:1609:1609) (1700:1700:1700)) + (PORT d[2] (1788:1788:1788) (1834:1834:1834)) + (PORT d[3] (1753:1753:1753) (1800:1800:1800)) + (PORT d[4] (2573:2573:2573) (2629:2629:2629)) + (PORT d[5] (2062:2062:2062) (2159:2159:2159)) + (PORT d[6] (1861:1861:1861) (1879:1879:1879)) + (PORT d[7] (1974:1974:1974) (2042:2042:2042)) + (PORT d[8] (2218:2218:2218) (2298:2298:2298)) + (PORT d[9] (1820:1820:1820) (1861:1861:1861)) + (PORT d[10] (1844:1844:1844) (1851:1851:1851)) + (PORT d[11] (1877:1877:1877) (1899:1899:1899)) + (PORT d[12] (2378:2378:2378) (2399:2399:2399)) + (PORT clk (1644:1644:1644) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (PORT d[0] (2530:2530:2530) (2508:2508:2508)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1503:1503:1503) (1531:1531:1531)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2666:2666:2666) (2687:2687:2687)) + (PORT d[1] (1897:1897:1897) (1996:1996:1996)) + (PORT d[2] (1753:1753:1753) (1779:1779:1779)) + (PORT d[3] (1747:1747:1747) (1800:1800:1800)) + (PORT d[4] (2818:2818:2818) (2858:2858:2858)) + (PORT d[5] (1809:1809:1809) (1901:1901:1901)) + (PORT d[6] (1611:1611:1611) (1617:1617:1617)) + (PORT d[7] (1692:1692:1692) (1718:1718:1718)) + (PORT d[8] (2251:2251:2251) (2328:2328:2328)) + (PORT d[9] (1828:1828:1828) (1861:1861:1861)) + (PORT d[10] (1856:1856:1856) (1882:1882:1882)) + (PORT d[11] (2347:2347:2347) (2365:2365:2365)) + (PORT d[12] (2075:2075:2075) (2105:2105:2105)) + (PORT clk (1638:1638:1638) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2330:2330:2330) (2279:2279:2279)) + (PORT clk (1638:1638:1638) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT d[0] (3368:3368:3368) (3356:3356:3356)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1599:1599:1599)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1887:1887:1887) (1819:1819:1819)) + (PORT clk (1608:1608:1608) (1606:1606:1606)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4135:4135:4135) (4045:4045:4045)) + (PORT d[1] (3941:3941:3941) (3838:3838:3838)) + (PORT d[2] (3995:3995:3995) (3898:3898:3898)) + (PORT d[3] (4226:4226:4226) (4152:4152:4152)) + (PORT d[4] (4046:4046:4046) (3907:3907:3907)) + (PORT d[5] (4290:4290:4290) (4190:4190:4190)) + (PORT d[6] (4375:4375:4375) (4339:4339:4339)) + (PORT d[7] (4037:4037:4037) (3866:3866:3866)) + (PORT d[8] (4167:4167:4167) (4039:4039:4039)) + (PORT d[9] (4129:4129:4129) (4216:4216:4216)) + (PORT d[10] (4314:4314:4314) (4238:4238:4238)) + (PORT d[11] (4075:4075:4075) (3952:3952:3952)) + (PORT d[12] (4191:4191:4191) (4206:4206:4206)) + (PORT clk (1605:1605:1605) (1603:1603:1603)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1606:1606:1606)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1129:1129:1129) (1172:1172:1172)) + (PORT datab (1335:1335:1335) (1318:1318:1318)) + (PORT datac (1047:1047:1047) (1062:1062:1062)) + (PORT datad (1324:1324:1324) (1319:1319:1319)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3372:3372:3372) (3445:3445:3445)) + (PORT d[1] (2443:2443:2443) (2564:2564:2564)) + (PORT d[2] (1520:1520:1520) (1542:1542:1542)) + (PORT d[3] (1998:1998:1998) (2040:2040:2040)) + (PORT d[4] (2014:2014:2014) (2036:2036:2036)) + (PORT d[5] (1537:1537:1537) (1604:1604:1604)) + (PORT d[6] (1058:1058:1058) (1070:1070:1070)) + (PORT d[7] (1084:1084:1084) (1098:1098:1098)) + (PORT d[8] (2012:2012:2012) (2097:2097:2097)) + (PORT d[9] (2103:2103:2103) (2157:2157:2157)) + (PORT d[10] (2374:2374:2374) (2416:2416:2416)) + (PORT d[11] (865:865:865) (853:853:853)) + (PORT d[12] (1628:1628:1628) (1646:1646:1646)) + (PORT clk (1634:1634:1634) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1662:1662:1662)) + (PORT d[0] (3098:3098:3098) (3083:3083:3083)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1628:1628:1628)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (875:875:875)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1097:1097:1097)) + (PORT datab (995:995:995) (975:975:975)) + (PORT datac (164:164:164) (198:198:198)) + (PORT datad (1280:1280:1280) (1263:1263:1263)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1401:1401:1401) (1430:1430:1430)) + (PORT datab (885:885:885) (897:897:897)) + (PORT datac (162:162:162) (196:196:196)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (693:693:693)) + (PORT datab (1093:1093:1093) (1105:1105:1105)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1837:1837:1837) (1832:1832:1832)) + (PORT datab (1053:1053:1053) (1081:1081:1081)) + (PORT datac (162:162:162) (196:196:196)) + (PORT datad (772:772:772) (778:778:778)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (1840:1840:1840) (1833:1833:1833)) + (PORT datab (606:606:606) (628:628:628)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1526:1526:1526) (1471:1471:1471)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (945:945:945)) + (PORT datab (855:855:855) (862:862:862)) + (PORT datac (216:216:216) (266:266:266)) + (PORT datad (1460:1460:1460) (1444:1444:1444)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (378:378:378)) + (PORT datac (376:376:376) (415:415:415)) + (PORT datad (621:621:621) (623:623:623)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (903:903:903)) + (PORT datab (1282:1282:1282) (1230:1230:1230)) + (PORT datac (822:822:822) (840:840:840)) + (PORT datad (825:825:825) (819:819:819)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT asdata (1401:1401:1401) (1394:1394:1394)) + (PORT clrn (1395:1395:1395) (1365:1365:1365)) + (PORT ena (1378:1378:1378) (1338:1338:1338)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1846:1846:1846) (1909:1909:1909)) + (PORT datab (1410:1410:1410) (1459:1459:1459)) + (PORT datac (201:201:201) (246:246:246)) + (PORT datad (1020:1020:1020) (1031:1031:1031)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (DELAY + (ABSOLUTE + (PORT dataa (1375:1375:1375) (1453:1453:1453)) + (PORT datab (1351:1351:1351) (1420:1420:1420)) + (PORT datac (1699:1699:1699) (1699:1699:1699)) + (PORT datad (370:370:370) (391:391:391)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (455:455:455)) + (PORT datab (660:660:660) (673:673:673)) + (PORT datac (1335:1335:1335) (1367:1367:1367)) + (PORT datad (1200:1200:1200) (1268:1268:1268)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (645:645:645)) + (PORT datac (1068:1068:1068) (1072:1072:1072)) + (PORT datad (842:842:842) (842:842:842)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (601:601:601) (632:632:632)) + (PORT datac (807:807:807) (818:818:818)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (496:496:496)) + (PORT datab (836:836:836) (845:845:845)) + (PORT datac (545:545:545) (540:540:540)) + (PORT datad (1067:1067:1067) (1073:1073:1073)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (605:605:605)) + (PORT datab (879:879:879) (876:876:876)) + (PORT datac (585:585:585) (610:610:610)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (838:838:838)) + (PORT datab (218:218:218) (262:262:262)) + (PORT datac (568:568:568) (598:598:598)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (761:761:761)) + (PORT datab (666:666:666) (734:734:734)) + (PORT datac (1056:1056:1056) (1114:1114:1114)) + (PORT datad (840:840:840) (880:880:880)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (643:643:643)) + (PORT datab (321:321:321) (330:330:330)) + (PORT datac (658:658:658) (727:727:727)) + (PORT datad (670:670:670) (741:741:741)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (811:811:811)) + (PORT datac (645:645:645) (709:709:709)) + (PORT datad (1063:1063:1063) (1109:1109:1109)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (219:219:219)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (472:472:472)) + (PORT datab (606:606:606) (652:652:652)) + (PORT datad (670:670:670) (705:705:705)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~136) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (520:520:520)) + (PORT datab (419:419:419) (464:464:464)) + (PORT datad (605:605:605) (640:640:640)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (665:665:665)) + (PORT datab (618:618:618) (627:627:627)) + (PORT datad (770:770:770) (787:787:787)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (731:731:731) (812:812:812)) + (PORT datab (589:589:589) (595:595:595)) + (PORT datad (570:570:570) (566:566:566)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (811:811:811)) + (PORT datab (817:817:817) (808:808:808)) + (PORT datac (568:568:568) (598:598:598)) + (PORT datad (599:599:599) (627:627:627)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (832:832:832)) + (PORT datab (636:636:636) (659:659:659)) + (PORT datac (882:882:882) (920:920:920)) + (PORT datad (1276:1276:1276) (1339:1339:1339)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (925:925:925)) + (PORT datab (723:723:723) (794:794:794)) + (PORT datac (826:826:826) (874:874:874)) + (PORT datad (707:707:707) (785:785:785)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (342:342:342)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datad (839:839:839) (871:871:871)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (564:564:564)) + (PORT datab (885:885:885) (931:931:931)) + (PORT datad (530:530:530) (517:517:517)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1470:1470:1470) (1502:1502:1502)) + (PORT datac (684:684:684) (754:754:754)) + (PORT datad (654:654:654) (709:709:709)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (649:649:649)) + (PORT datab (1142:1142:1142) (1157:1157:1157)) + (PORT datac (845:845:845) (875:875:875)) + (PORT datad (305:305:305) (312:312:312)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (235:235:235)) + (PORT datab (886:886:886) (933:933:933)) + (PORT datad (329:329:329) (342:342:342)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1240:1240:1240)) + (PORT datab (1134:1134:1134) (1154:1154:1154)) + (PORT datac (196:196:196) (263:263:263)) + (PORT datad (198:198:198) (256:256:256)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (474:474:474)) + (PORT datab (603:603:603) (651:651:651)) + (PORT datad (672:672:672) (706:706:706)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (536:536:536)) + (PORT datab (668:668:668) (733:733:733)) + (PORT datac (1424:1424:1424) (1480:1480:1480)) + (PORT datad (544:544:544) (543:543:543)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (631:631:631)) + (PORT datab (688:688:688) (759:759:759)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~3) + (DELAY + (ABSOLUTE + (PORT datab (1409:1409:1409) (1437:1437:1437)) + (PORT datac (813:813:813) (846:846:846)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (405:405:405)) + (PORT datab (580:580:580) (576:576:576)) + (PORT datac (1257:1257:1257) (1255:1255:1255)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (811:811:811)) + (PORT datac (639:639:639) (702:702:702)) + (PORT datad (1057:1057:1057) (1101:1101:1101)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1147:1147:1147)) + (PORT datab (670:670:670) (736:736:736)) + (PORT datac (586:586:586) (610:610:610)) + (PORT datad (836:836:836) (879:879:879)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (369:369:369)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datad (166:166:166) (193:193:193)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (533:533:533)) + (PORT datab (332:332:332) (353:353:353)) + (PORT datad (661:661:661) (725:725:725)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1042:1042:1042) (1038:1038:1038)) + (PORT datab (1066:1066:1066) (1079:1079:1079)) + (PORT datac (590:590:590) (626:626:626)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1497:1497:1497) (1479:1479:1479)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3117:3117:3117) (3202:3202:3202)) + (PORT d[1] (1492:1492:1492) (1570:1570:1570)) + (PORT d[2] (2221:2221:2221) (2276:2276:2276)) + (PORT d[3] (1745:1745:1745) (1779:1779:1779)) + (PORT d[4] (1772:1772:1772) (1805:1805:1805)) + (PORT d[5] (1930:1930:1930) (2022:2022:2022)) + (PORT d[6] (2105:2105:2105) (2140:2140:2140)) + (PORT d[7] (2005:2005:2005) (2010:2010:2010)) + (PORT d[8] (2724:2724:2724) (2779:2779:2779)) + (PORT d[9] (2094:2094:2094) (2123:2123:2123)) + (PORT d[10] (3714:3714:3714) (3823:3823:3823)) + (PORT d[11] (1664:1664:1664) (1694:1694:1694)) + (PORT d[12] (2152:2152:2152) (2211:2211:2211)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (PORT d[0] (2258:2258:2258) (2250:2250:2250)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1398:1398:1398) (1418:1418:1418)) + (PORT clk (1634:1634:1634) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3220:3220:3220) (3238:3238:3238)) + (PORT d[1] (1562:1562:1562) (1647:1647:1647)) + (PORT d[2] (1668:1668:1668) (1669:1669:1669)) + (PORT d[3] (1976:1976:1976) (2007:2007:2007)) + (PORT d[4] (2050:2050:2050) (2095:2095:2095)) + (PORT d[5] (1525:1525:1525) (1602:1602:1602)) + (PORT d[6] (1345:1345:1345) (1352:1352:1352)) + (PORT d[7] (1353:1353:1353) (1377:1377:1377)) + (PORT d[8] (2698:2698:2698) (2781:2781:2781)) + (PORT d[9] (2098:2098:2098) (2149:2149:2149)) + (PORT d[10] (2137:2137:2137) (2175:2175:2175)) + (PORT d[11] (1988:1988:1988) (2028:2028:2028)) + (PORT d[12] (1876:1876:1876) (1897:1897:1897)) + (PORT clk (1631:1631:1631) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2643:2643:2643) (2613:2613:2613)) + (PORT clk (1631:1631:1631) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1662:1662:1662)) + (PORT d[0] (3917:3917:3917) (3913:3913:3913)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1593:1593:1593) (1592:1592:1592)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1614:1614:1614) (1543:1543:1543)) + (PORT clk (1601:1601:1601) (1599:1599:1599)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4103:4103:4103) (3997:3997:3997)) + (PORT d[1] (3955:3955:3955) (3883:3883:3883)) + (PORT d[2] (4006:4006:4006) (3895:3895:3895)) + (PORT d[3] (4212:4212:4212) (4117:4117:4117)) + (PORT d[4] (4315:4315:4315) (4187:4187:4187)) + (PORT d[5] (4021:4021:4021) (3945:3945:3945)) + (PORT d[6] (4378:4378:4378) (4355:4355:4355)) + (PORT d[7] (3996:3996:3996) (3938:3938:3938)) + (PORT d[8] (4192:4192:4192) (4072:4072:4072)) + (PORT d[9] (4141:4141:4141) (4229:4229:4229)) + (PORT d[10] (4080:4080:4080) (4007:4007:4007)) + (PORT d[11] (4096:4096:4096) (3973:3973:3973)) + (PORT d[12] (4047:4047:4047) (3950:3950:3950)) + (PORT clk (1598:1598:1598) (1596:1596:1596)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1599:1599:1599)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3890:3890:3890) (3959:3959:3959)) + (PORT d[1] (2668:2668:2668) (2802:2802:2802)) + (PORT d[2] (2492:2492:2492) (2533:2533:2533)) + (PORT d[3] (2120:2120:2120) (2205:2205:2205)) + (PORT d[4] (2339:2339:2339) (2426:2426:2426)) + (PORT d[5] (2353:2353:2353) (2440:2440:2440)) + (PORT d[6] (1749:1749:1749) (1794:1794:1794)) + (PORT d[7] (2139:2139:2139) (2164:2164:2164)) + (PORT d[8] (2895:2895:2895) (3020:3020:3020)) + (PORT d[9] (2427:2427:2427) (2496:2496:2496)) + (PORT d[10] (4456:4456:4456) (4549:4549:4549)) + (PORT d[11] (1768:1768:1768) (1835:1835:1835)) + (PORT d[12] (2036:2036:2036) (2099:2099:2099)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT d[0] (3246:3246:3246) (3296:3296:3296)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1457:1457:1457) (1477:1477:1477)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2802:2802:2802) (2864:2864:2864)) + (PORT d[1] (2141:2141:2141) (2242:2242:2242)) + (PORT d[2] (2014:2014:2014) (2042:2042:2042)) + (PORT d[3] (1762:1762:1762) (1815:1815:1815)) + (PORT d[4] (2261:2261:2261) (2299:2299:2299)) + (PORT d[5] (1802:1802:1802) (1892:1892:1892)) + (PORT d[6] (1621:1621:1621) (1629:1629:1629)) + (PORT d[7] (2205:2205:2205) (2254:2254:2254)) + (PORT d[8] (2686:2686:2686) (2758:2758:2758)) + (PORT d[9] (1843:1843:1843) (1889:1889:1889)) + (PORT d[10] (1872:1872:1872) (1913:1913:1913)) + (PORT d[11] (2261:2261:2261) (2308:2308:2308)) + (PORT d[12] (2373:2373:2373) (2396:2396:2396)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2375:2375:2375) (2364:2364:2364)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (3627:3627:3627) (3623:3623:3623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1594:1594:1594) (1592:1592:1592)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1898:1898:1898) (1812:1812:1812)) + (PORT clk (1602:1602:1602) (1599:1599:1599)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4101:4101:4101) (4000:4000:4000)) + (PORT d[1] (3952:3952:3952) (3866:3866:3866)) + (PORT d[2] (4011:4011:4011) (3918:3918:3918)) + (PORT d[3] (4159:4159:4159) (4067:4067:4067)) + (PORT d[4] (4060:4060:4060) (3935:3935:3935)) + (PORT d[5] (4328:4328:4328) (4228:4228:4228)) + (PORT d[6] (4144:4144:4144) (4120:4120:4120)) + (PORT d[7] (4041:4041:4041) (3982:3982:3982)) + (PORT d[8] (4200:4200:4200) (4067:4067:4067)) + (PORT d[9] (4128:4128:4128) (4213:4213:4213)) + (PORT d[10] (4041:4041:4041) (3946:3946:3946)) + (PORT d[11] (4367:4367:4367) (4242:4242:4242)) + (PORT d[12] (4125:4125:4125) (4113:4113:4113)) + (PORT clk (1599:1599:1599) (1596:1596:1596)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1599:1599:1599)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1595:1595:1595) (1593:1593:1593)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1099:1099:1099)) + (PORT datab (881:881:881) (891:891:891)) + (PORT datac (1292:1292:1292) (1266:1266:1266)) + (PORT datad (1335:1335:1335) (1322:1322:1322)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1213:1213:1213) (1224:1224:1224)) + (PORT datab (886:886:886) (898:898:898)) + (PORT datac (1327:1327:1327) (1349:1349:1349)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (851:851:851) (853:853:853)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3109:3109:3109) (3183:3183:3183)) + (PORT d[1] (1610:1610:1610) (1709:1709:1709)) + (PORT d[2] (1852:1852:1852) (1867:1867:1867)) + (PORT d[3] (2001:2001:2001) (2036:2036:2036)) + (PORT d[4] (1710:1710:1710) (1718:1718:1718)) + (PORT d[5] (1262:1262:1262) (1314:1314:1314)) + (PORT d[6] (1355:1355:1355) (1362:1362:1362)) + (PORT d[7] (3106:3106:3106) (3141:3141:3141)) + (PORT d[8] (2266:2266:2266) (2361:2361:2361)) + (PORT d[9] (3248:3248:3248) (3329:3329:3329)) + (PORT d[10] (2702:2702:2702) (2780:2780:2780)) + (PORT d[11] (1389:1389:1389) (1395:1395:1395)) + (PORT d[12] (1360:1360:1360) (1386:1386:1386)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3094:3094:3094) (3034:3034:3034)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (1771:1771:1771) (1681:1681:1681)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1374:1374:1374) (1380:1380:1380)) + (PORT clk (1626:1626:1626) (1655:1655:1655)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3408:3408:3408) (3498:3498:3498)) + (PORT d[1] (1569:1569:1569) (1663:1663:1663)) + (PORT d[2] (3026:3026:3026) (3089:3089:3089)) + (PORT d[3] (2000:2000:2000) (2020:2020:2020)) + (PORT d[4] (2357:2357:2357) (2411:2411:2411)) + (PORT d[5] (1547:1547:1547) (1619:1619:1619)) + (PORT d[6] (1669:1669:1669) (1713:1713:1713)) + (PORT d[7] (1572:1572:1572) (1598:1598:1598)) + (PORT d[8] (3085:3085:3085) (3197:3197:3197)) + (PORT d[9] (2632:2632:2632) (2690:2690:2690)) + (PORT d[10] (3216:3216:3216) (3306:3306:3306)) + (PORT d[11] (1667:1667:1667) (1701:1701:1701)) + (PORT d[12] (1605:1605:1605) (1642:1642:1642)) + (PORT clk (1623:1623:1623) (1653:1653:1653)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1801:1801:1801) (1740:1740:1740)) + (PORT clk (1623:1623:1623) (1653:1653:1653)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1626:1626:1626) (1655:1655:1655)) + (PORT d[0] (2539:2539:2539) (2489:2489:2489)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1590:1590:1590) (1619:1619:1619)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (861:861:861) (866:866:866)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1169:1169:1169) (1177:1177:1177)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3109:3109:3109) (3181:3181:3181)) + (PORT d[1] (1236:1236:1236) (1300:1300:1300)) + (PORT d[2] (1799:1799:1799) (1833:1833:1833)) + (PORT d[3] (1433:1433:1433) (1450:1450:1450)) + (PORT d[4] (1740:1740:1740) (1757:1757:1757)) + (PORT d[5] (1521:1521:1521) (1560:1560:1560)) + (PORT d[6] (1100:1100:1100) (1121:1121:1121)) + (PORT d[7] (1350:1350:1350) (1384:1384:1384)) + (PORT d[8] (2320:2320:2320) (2418:2418:2418)) + (PORT d[9] (3238:3238:3238) (3316:3316:3316)) + (PORT d[10] (2664:2664:2664) (2731:2731:2731)) + (PORT d[11] (1162:1162:1162) (1161:1161:1161)) + (PORT d[12] (1034:1034:1034) (1044:1044:1044)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2652:2652:2652) (2627:2627:2627)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (2959:2959:2959) (2958:2958:2958)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1637:1637:1637) (1639:1639:1639)) + (PORT clk (1637:1637:1637) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3128:3128:3128) (3214:3214:3214)) + (PORT d[1] (1579:1579:1579) (1666:1666:1666)) + (PORT d[2] (2493:2493:2493) (2551:2551:2551)) + (PORT d[3] (1985:1985:1985) (2021:2021:2021)) + (PORT d[4] (2035:2035:2035) (2070:2070:2070)) + (PORT d[5] (2222:2222:2222) (2345:2345:2345)) + (PORT d[6] (1954:1954:1954) (2014:2014:2014)) + (PORT d[7] (2290:2290:2290) (2303:2303:2303)) + (PORT d[8] (2819:2819:2819) (2916:2916:2916)) + (PORT d[9] (2386:2386:2386) (2432:2432:2432)) + (PORT d[10] (3501:3501:3501) (3612:3612:3612)) + (PORT d[11] (1655:1655:1655) (1668:1668:1668)) + (PORT d[12] (2144:2144:2144) (2185:2185:2185)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2095:2095:2095) (2041:2041:2041)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1665:1665:1665)) + (PORT d[0] (2457:2457:2457) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1690:1690:1690) (1647:1647:1647)) + (PORT datab (1084:1084:1084) (1080:1080:1080)) + (PORT datad (1566:1566:1566) (1563:1563:1563)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1382:1382:1382)) + (PORT datab (1365:1365:1365) (1350:1350:1350)) + (PORT datac (1957:1957:1957) (1959:1959:1959)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (693:693:693)) + (PORT datab (1093:1093:1093) (1105:1105:1105)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (822:822:822)) + (PORT datab (1441:1441:1441) (1442:1442:1442)) + (PORT datac (1357:1357:1357) (1385:1385:1385)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (1076:1076:1076) (1121:1121:1121)) + (PORT datab (1558:1558:1558) (1503:1503:1503)) + (PORT datac (1358:1358:1358) (1385:1385:1385)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (937:937:937)) + (PORT datab (1408:1408:1408) (1363:1363:1363)) + (PORT datac (209:209:209) (258:258:258)) + (PORT datad (1071:1071:1071) (1059:1059:1059)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -34673,16 +42752,170 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (415:415:415)) + (PORT datab (355:355:355) (377:377:377)) + (PORT datad (619:619:619) (624:624:624)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (906:906:906)) + (PORT datab (856:856:856) (848:848:848)) + (PORT datac (821:821:821) (838:838:838)) + (PORT datad (826:826:826) (841:841:841)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1390:1390:1390) (1361:1361:1361)) + (PORT ena (1363:1363:1363) (1319:1319:1319)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~0) + (DELAY + (ABSOLUTE + (PORT datac (1315:1315:1315) (1385:1385:1385)) + (PORT datad (1349:1349:1349) (1412:1412:1412)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1284:1284:1284) (1279:1279:1279)) + (PORT datab (917:917:917) (931:931:931)) + (PORT datac (1485:1485:1485) (1580:1580:1580)) + (PORT datad (1131:1131:1131) (1161:1161:1161)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1184:1184:1184) (1229:1229:1229)) + (PORT datab (1408:1408:1408) (1433:1433:1433)) + (PORT datac (762:762:762) (748:748:748)) + (PORT datad (183:183:183) (207:207:207)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT datab (1421:1421:1421) (1477:1477:1477)) + (PORT datac (1249:1249:1249) (1279:1279:1279)) + (PORT datad (2264:2264:2264) (2402:2402:2402)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (822:822:822)) + (PORT datab (856:856:856) (852:852:852)) + (PORT datac (1586:1586:1586) (1591:1591:1591)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (409:409:409)) + (PORT datab (1095:1095:1095) (1125:1125:1125)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (333:333:333) (345:345:345)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_mWrite\~11) (DELAY (ABSOLUTE - (PORT dataa (1379:1379:1379) (1399:1399:1399)) - (PORT datab (1330:1330:1330) (1340:1340:1340)) - (PORT datac (594:594:594) (609:609:609)) - (PORT datad (1265:1265:1265) (1246:1246:1246)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (854:854:854) (888:888:888)) + (PORT datab (574:574:574) (600:600:600)) + (PORT datac (820:820:820) (837:837:837)) + (PORT datad (822:822:822) (813:813:813)) + (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -34694,12 +42927,12 @@ (INSTANCE z80_\|execute_\|ctl_mWrite\~12) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (1200:1200:1200) (1170:1170:1170)) - (PORT datac (1483:1483:1483) (1451:1451:1451)) - (PORT datad (167:167:167) (193:193:193)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (1837:1837:1837) (1846:1846:1846)) + (PORT datab (1056:1056:1056) (1022:1022:1022)) + (PORT datac (788:788:788) (768:768:768)) + (PORT datad (591:591:591) (611:611:611)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -34710,10 +42943,10 @@ (INSTANCE z80_\|execute_\|ctl_mWrite\~13) (DELAY (ABSOLUTE - (PORT dataa (518:518:518) (515:515:515)) - (PORT datab (190:190:190) (225:225:225)) - (PORT datac (1191:1191:1191) (1169:1169:1169)) - (PORT datad (744:744:744) (711:711:711)) + (PORT dataa (184:184:184) (219:219:219)) + (PORT datab (559:559:559) (548:548:548)) + (PORT datac (497:497:497) (488:488:488)) + (PORT datad (165:165:165) (188:188:188)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -34721,18 +42954,34 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1451:1451:1451) (1497:1497:1497)) + (PORT datab (800:800:800) (797:797:797)) + (PORT datac (1353:1353:1353) (1351:1351:1351)) + (PORT datad (989:989:989) (953:953:953)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_mWrite\~15) (DELAY (ABSOLUTE - (PORT dataa (629:629:629) (634:634:634)) - (PORT datab (569:569:569) (601:601:601)) - (PORT datac (1220:1220:1220) (1202:1202:1202)) - (PORT datad (728:728:728) (729:729:729)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (592:592:592) (581:581:581)) + (PORT datab (809:809:809) (826:826:826)) + (PORT datac (793:793:793) (777:777:777)) + (PORT datad (1104:1104:1104) (1100:1100:1100)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -34742,10 +42991,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1376:1376:1376)) + (PORT clk (1357:1357:1357) (1378:1378:1378)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (1344:1344:1344) (1326:1326:1326)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1189:1189:1189) (1191:1191:1191)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -34760,7 +43009,7 @@ (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) (DELAY (ABSOLUTE - (PORT datad (199:199:199) (256:256:256)) + (PORT datad (200:200:200) (258:258:258)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -34770,10 +43019,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_mwr) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1368:1368:1368)) + (PORT clk (1364:1364:1364) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (1318:1318:1318) (1291:1291:1291)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1217:1217:1217) (1223:1223:1223)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -34783,31 +43032,21 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|mwr_wr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (206:206:206) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|mwr_wr) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (1318:1318:1318) (1291:1291:1291)) + (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT asdata (511:511:511) (578:578:578)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1217:1217:1217) (1223:1223:1223)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -34816,24 +43055,23 @@ (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) (DELAY (ABSOLUTE - (PORT datab (225:225:225) (295:295:295)) - (PORT datac (932:932:932) (904:904:904)) - (PORT datad (182:182:182) (206:206:206)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (804:804:804) (796:796:796)) + (PORT datab (331:331:331) (348:348:348)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~30) + (INSTANCE D\[5\]\~84) (DELAY (ABSOLUTE - (PORT dataa (2257:2257:2257) (2345:2345:2345)) - (PORT datab (1413:1413:1413) (1416:1416:1416)) - (PORT datac (2791:2791:2791) (2901:2901:2901)) - (PORT datad (1520:1520:1520) (1537:1537:1537)) + (PORT dataa (1623:1623:1623) (1655:1655:1655)) + (PORT datab (1476:1476:1476) (1530:1530:1530)) + (PORT datac (1099:1099:1099) (1117:1117:1117)) + (PORT datad (1134:1134:1134) (1160:1160:1160)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -34843,10 +43081,35 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1790:1790:1790) (1758:1758:1758)) + (PORT d[0] (1084:1084:1084) (1083:1083:1083)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3903:3903:3903) (3984:3984:3984)) + (PORT d[1] (2655:2655:2655) (2790:2790:2790)) + (PORT d[2] (2992:2992:2992) (3016:3016:3016)) + (PORT d[3] (2356:2356:2356) (2437:2437:2437)) + (PORT d[4] (2074:2074:2074) (2161:2161:2161)) + (PORT d[5] (2391:2391:2391) (2481:2481:2481)) + (PORT d[6] (1728:1728:1728) (1769:1769:1769)) + (PORT d[7] (2149:2149:2149) (2178:2178:2178)) + (PORT d[8] (2888:2888:2888) (3027:3027:3027)) + (PORT d[9] (2688:2688:2688) (2747:2747:2747)) + (PORT d[10] (4446:4446:4446) (4545:4545:4545)) + (PORT d[11] (2033:2033:2033) (2092:2092:2092)) + (PORT d[12] (2027:2027:2027) (2085:2085:2085)) (PORT clk (1640:1640:1640) (1668:1668:1668)) ) ) @@ -34856,98 +43119,73 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1735:1735:1735) (1794:1794:1794)) - (PORT d[1] (2260:2260:2260) (2381:2381:2381)) - (PORT d[2] (2188:2188:2188) (2271:2271:2271)) - (PORT d[3] (1643:1643:1643) (1653:1653:1653)) - (PORT d[4] (2076:2076:2076) (2134:2134:2134)) - (PORT d[5] (4487:4487:4487) (4647:4647:4647)) - (PORT d[6] (2131:2131:2131) (2147:2147:2147)) - (PORT d[7] (1998:1998:1998) (1981:1981:1981)) - (PORT d[8] (2844:2844:2844) (2941:2941:2941)) - (PORT d[9] (2658:2658:2658) (2694:2694:2694)) - (PORT d[10] (1826:1826:1826) (1903:1903:1903)) - (PORT d[11] (1964:1964:1964) (2014:2014:2014)) - (PORT d[12] (1248:1248:1248) (1205:1205:1205)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1848:1848:1848) (1786:1786:1786)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) (DELAY (ABSOLUTE + (PORT d[0] (1812:1812:1812) (1737:1737:1737)) (PORT clk (1640:1640:1640) (1668:1668:1668)) - (PORT d[0] (2370:2370:2370) (2350:2350:2350)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (2104:2104:2104) (2069:2069:2069)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT clk (1644:1644:1644) (1671:1671:1671)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT clk (1644:1644:1644) (1671:1671:1671)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT clk (1644:1644:1644) (1671:1671:1671)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT clk (1644:1644:1644) (1671:1671:1671)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1604:1604:1604) (1632:1632:1632)) + (PORT clk (1607:1607:1607) (1634:1634:1634)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -34958,49 +43196,49 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) + (PORT clk (878:878:878) (881:881:881)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) + (PORT clk (879:879:879) (882:882:882)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) + (PORT clk (879:879:879) (882:882:882)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) + (PORT clk (879:879:879) (882:882:882)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2063:2063:2063) (2022:2022:2022)) - (PORT clk (1636:1636:1636) (1663:1663:1663)) + (PORT d[0] (1106:1106:1106) (1100:1100:1100)) + (PORT clk (1644:1644:1644) (1670:1670:1670)) ) ) (TIMINGCHECK @@ -35009,23 +43247,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2062:2062:2062) (2129:2129:2129)) - (PORT d[1] (2491:2491:2491) (2603:2603:2603)) - (PORT d[2] (2172:2172:2172) (2273:2273:2273)) - (PORT d[3] (3578:3578:3578) (3782:3782:3782)) - (PORT d[4] (2060:2060:2060) (2106:2106:2106)) - (PORT d[5] (4235:4235:4235) (4406:4406:4406)) - (PORT d[6] (2096:2096:2096) (2102:2102:2102)) - (PORT d[7] (2038:2038:2038) (2036:2036:2036)) - (PORT d[8] (2859:2859:2859) (2959:2959:2959)) - (PORT d[9] (2619:2619:2619) (2650:2650:2650)) - (PORT d[10] (2128:2128:2128) (2229:2229:2229)) - (PORT d[11] (2243:2243:2243) (2312:2312:2312)) - (PORT d[12] (1492:1492:1492) (1462:1462:1462)) - (PORT clk (1633:1633:1633) (1661:1661:1661)) + (PORT d[0] (3898:3898:3898) (3977:3977:3977)) + (PORT d[1] (2675:2675:2675) (2810:2810:2810)) + (PORT d[2] (2544:2544:2544) (2585:2585:2585)) + (PORT d[3] (2356:2356:2356) (2433:2433:2433)) + (PORT d[4] (2094:2094:2094) (2182:2182:2182)) + (PORT d[5] (2365:2365:2365) (2452:2452:2452)) + (PORT d[6] (1754:1754:1754) (1791:1791:1791)) + (PORT d[7] (2123:2123:2123) (2149:2149:2149)) + (PORT d[8] (2905:2905:2905) (3041:3041:3041)) + (PORT d[9] (2410:2410:2410) (2473:2473:2473)) + (PORT d[10] (4441:4441:4441) (4538:4538:4538)) + (PORT d[11] (1762:1762:1762) (1827:1827:1827)) + (PORT d[12] (2035:2035:2035) (2098:2098:2098)) + (PORT clk (1641:1641:1641) (1668:1668:1668)) ) ) (TIMINGCHECK @@ -35034,11 +43272,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1969:1969:1969) (1955:1955:1955)) - (PORT clk (1633:1633:1633) (1661:1661:1661)) + (PORT d[0] (2200:2200:2200) (2122:2122:2122)) + (PORT clk (1641:1641:1641) (1668:1668:1668)) ) ) (TIMINGCHECK @@ -35047,57 +43285,6231 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (PORT d[0] (2501:2501:2501) (2514:2514:2514)) + (PORT clk (1644:1644:1644) (1670:1670:1670)) + (PORT d[0] (2614:2614:2614) (2527:2527:2527)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1637:1637:1637) (1664:1664:1664)) + (PORT clk (1645:1645:1645) (1671:1671:1671)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1637:1637:1637) (1664:1664:1664)) + (PORT clk (1645:1645:1645) (1671:1671:1671)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1637:1637:1637) (1664:1664:1664)) + (PORT clk (1645:1645:1645) (1671:1671:1671)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1637:1637:1637) (1664:1664:1664)) + (PORT clk (1645:1645:1645) (1671:1671:1671)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (817:817:817) (820:820:820)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1228:1228:1228) (1255:1255:1255)) + (PORT d[1] (1897:1897:1897) (2022:2022:2022)) + (PORT d[2] (2775:2775:2775) (2823:2823:2823)) + (PORT d[3] (2397:2397:2397) (2495:2495:2495)) + (PORT d[4] (2384:2384:2384) (2480:2480:2480)) + (PORT d[5] (2636:2636:2636) (2730:2730:2730)) + (PORT d[6] (1805:1805:1805) (1869:1869:1869)) + (PORT d[7] (2410:2410:2410) (2444:2444:2444)) + (PORT d[8] (3147:3147:3147) (3288:3288:3288)) + (PORT d[9] (2709:2709:2709) (2776:2776:2776)) + (PORT d[10] (4723:4723:4723) (4808:4808:4808)) + (PORT d[11] (1794:1794:1794) (1853:1853:1853)) + (PORT d[12] (1761:1761:1761) (1812:1812:1812)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1125:1125:1125) (1096:1096:1096)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (2299:2299:2299) (2237:2237:2237)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1313:1313:1313) (1351:1351:1351)) + (PORT datab (897:897:897) (941:941:941)) + (PORT datac (1013:1013:1013) (988:988:988)) + (PORT datad (779:779:779) (758:758:758)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1106:1106:1106) (1110:1110:1110)) + (PORT clk (1636:1636:1636) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3118:3118:3118) (3206:3206:3206)) + (PORT d[1] (1574:1574:1574) (1682:1682:1682)) + (PORT d[2] (2764:2764:2764) (2820:2820:2820)) + (PORT d[3] (2036:2036:2036) (2067:2067:2067)) + (PORT d[4] (2319:2319:2319) (2363:2363:2363)) + (PORT d[5] (2234:2234:2234) (2357:2357:2357)) + (PORT d[6] (1950:1950:1950) (2007:2007:2007)) + (PORT d[7] (2300:2300:2300) (2311:2311:2311)) + (PORT d[8] (2804:2804:2804) (2907:2907:2907)) + (PORT d[9] (2345:2345:2345) (2391:2391:2391)) + (PORT d[10] (3492:3492:3492) (3594:3594:3594)) + (PORT d[11] (1620:1620:1620) (1617:1617:1617)) + (PORT d[12] (2158:2158:2158) (2197:2197:2197)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2044:2044:2044) (1984:1984:1984)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1662:1662:1662)) + (PORT d[0] (2515:2515:2515) (2442:2442:2442)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1343:1343:1343)) + (PORT datab (1065:1065:1065) (1048:1048:1048)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (1316:1316:1316) (1315:1315:1315)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1655:1655:1655) (1653:1653:1653)) + (PORT clk (1631:1631:1631) (1657:1657:1657)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3090:3090:3090) (3149:3149:3149)) + (PORT d[1] (2170:2170:2170) (2280:2280:2280)) + (PORT d[2] (2054:2054:2054) (2074:2074:2074)) + (PORT d[3] (1760:1760:1760) (1812:1812:1812)) + (PORT d[4] (2275:2275:2275) (2299:2299:2299)) + (PORT d[5] (1818:1818:1818) (1900:1900:1900)) + (PORT d[6] (1325:1325:1325) (1345:1345:1345)) + (PORT d[7] (1367:1367:1367) (1391:1391:1391)) + (PORT d[8] (2695:2695:2695) (2775:2775:2775)) + (PORT d[9] (1844:1844:1844) (1890:1890:1890)) + (PORT d[10] (1848:1848:1848) (1885:1885:1885)) + (PORT d[11] (1347:1347:1347) (1357:1357:1357)) + (PORT d[12] (1878:1878:1878) (1897:1897:1897)) + (PORT clk (1628:1628:1628) (1655:1655:1655)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2618:2618:2618) (2589:2589:2589)) + (PORT clk (1628:1628:1628) (1655:1655:1655)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1657:1657:1657)) + (PORT d[0] (3631:3631:3631) (3630:3630:3630)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1658:1658:1658)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1658:1658:1658)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1658:1658:1658)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1658:1658:1658)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1590:1590:1590) (1587:1587:1587)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1120:1120:1120) (1076:1076:1076)) + (PORT clk (1598:1598:1598) (1594:1594:1594)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4121:4121:4121) (4013:4013:4013)) + (PORT d[1] (3945:3945:3945) (3855:3855:3855)) + (PORT d[2] (4002:4002:4002) (3896:3896:3896)) + (PORT d[3] (4214:4214:4214) (4129:4129:4129)) + (PORT d[4] (4041:4041:4041) (3914:3914:3914)) + (PORT d[5] (4057:4057:4057) (3974:3974:3974)) + (PORT d[6] (4333:4333:4333) (4305:4305:4305)) + (PORT d[7] (4082:4082:4082) (4025:4025:4025)) + (PORT d[8] (4208:4208:4208) (4078:4078:4078)) + (PORT d[9] (4362:4362:4362) (4432:4432:4432)) + (PORT d[10] (4090:4090:4090) (4015:4015:4015)) + (PORT d[11] (4073:4073:4073) (3949:3949:3949)) + (PORT d[12] (4364:4364:4364) (4258:4258:4258)) + (PORT clk (1595:1595:1595) (1591:1591:1591)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1594:1594:1594)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1595:1595:1595)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1595:1595:1595)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1595:1595:1595)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2416:2416:2416) (2419:2419:2419)) + (PORT d[1] (1915:1915:1915) (2042:2042:2042)) + (PORT d[2] (2107:2107:2107) (2177:2177:2177)) + (PORT d[3] (2104:2104:2104) (2154:2154:2154)) + (PORT d[4] (2750:2750:2750) (2873:2873:2873)) + (PORT d[5] (1930:1930:1930) (2036:2036:2036)) + (PORT d[6] (1710:1710:1710) (1749:1749:1749)) + (PORT d[7] (2359:2359:2359) (2360:2360:2360)) + (PORT d[8] (2561:2561:2561) (2682:2682:2682)) + (PORT d[9] (1438:1438:1438) (1472:1472:1472)) + (PORT d[10] (1709:1709:1709) (1741:1741:1741)) + (PORT d[11] (2675:2675:2675) (2708:2708:2708)) + (PORT d[12] (1424:1424:1424) (1457:1457:1457)) + (PORT clk (1652:1652:1652) (1680:1680:1680)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1680:1680:1680)) + (PORT d[0] (2018:2018:2018) (2009:2009:2009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1619:1619:1619) (1646:1646:1646)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (890:890:890) (893:893:893)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (891:891:891) (894:894:894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (891:891:891) (894:894:894)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (891:891:891) (894:894:894)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3298:3298:3298) (3351:3351:3351)) + (PORT d[1] (1592:1592:1592) (1680:1680:1680)) + (PORT d[2] (2484:2484:2484) (2533:2533:2533)) + (PORT d[3] (1975:1975:1975) (2004:2004:2004)) + (PORT d[4] (1767:1767:1767) (1818:1818:1818)) + (PORT d[5] (2208:2208:2208) (2318:2318:2318)) + (PORT d[6] (2159:2159:2159) (2202:2202:2202)) + (PORT d[7] (2280:2280:2280) (2283:2283:2283)) + (PORT d[8] (2504:2504:2504) (2584:2584:2584)) + (PORT d[9] (2330:2330:2330) (2362:2362:2362)) + (PORT d[10] (3529:3529:3529) (3646:3646:3646)) + (PORT d[11] (1688:1688:1688) (1708:1708:1708)) + (PORT d[12] (2198:2198:2198) (2247:2247:2247)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (PORT d[0] (2249:2249:2249) (2258:2258:2258)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1532:1532:1532) (1559:1559:1559)) + (PORT clk (1646:1646:1646) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2702:2702:2702) (2726:2726:2726)) + (PORT d[1] (2194:2194:2194) (2333:2333:2333)) + (PORT d[2] (2394:2394:2394) (2459:2459:2459)) + (PORT d[3] (1855:1855:1855) (1909:1909:1909)) + (PORT d[4] (2716:2716:2716) (2843:2843:2843)) + (PORT d[5] (2202:2202:2202) (2319:2319:2319)) + (PORT d[6] (1727:1727:1727) (1746:1746:1746)) + (PORT d[7] (1517:1517:1517) (1555:1555:1555)) + (PORT d[8] (2811:2811:2811) (2896:2896:2896)) + (PORT d[9] (1130:1130:1130) (1151:1151:1151)) + (PORT d[10] (1994:1994:1994) (2037:2037:2037)) + (PORT d[11] (3422:3422:3422) (3471:3471:3471)) + (PORT d[12] (1753:1753:1753) (1782:1782:1782)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2584:2584:2584) (2522:2522:2522)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT d[0] (2819:2819:2819) (2825:2825:2825)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1603:1603:1603)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2024:2024:2024) (2022:2022:2022)) + (PORT clk (1613:1613:1613) (1610:1610:1610)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4286:4286:4286) (4176:4176:4176)) + (PORT d[1] (3889:3889:3889) (3754:3754:3754)) + (PORT d[2] (3922:3922:3922) (3831:3831:3831)) + (PORT d[3] (4387:4387:4387) (4236:4236:4236)) + (PORT d[4] (4059:4059:4059) (3930:3930:3930)) + (PORT d[5] (4137:4137:4137) (3982:3982:3982)) + (PORT d[6] (4314:4314:4314) (4255:4255:4255)) + (PORT d[7] (3900:3900:3900) (3727:3727:3727)) + (PORT d[8] (4378:4378:4378) (4223:4223:4223)) + (PORT d[9] (4245:4245:4245) (4309:4309:4309)) + (PORT d[10] (4110:4110:4110) (4007:4007:4007)) + (PORT d[11] (4188:4188:4188) (4097:4097:4097)) + (PORT d[12] (4162:4162:4162) (4084:4084:4084)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1610:1610:1610)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1604:1604:1604)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1324:1324:1324) (1337:1337:1337)) + (PORT datab (912:912:912) (946:946:946)) + (PORT datac (1320:1320:1320) (1311:1311:1311)) + (PORT datad (1291:1291:1291) (1297:1297:1297)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1403:1403:1403) (1437:1437:1437)) + (PORT datab (910:910:910) (944:944:944)) + (PORT datac (1361:1361:1361) (1365:1365:1365)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (1368:1368:1368) (1422:1422:1422)) + (PORT datab (1129:1129:1129) (1138:1138:1138)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (1282:1282:1282) (1254:1254:1254)) + (PORT datab (819:819:819) (858:858:858)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (1259:1259:1259) (1238:1238:1238)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~102) + (DELAY + (ABSOLUTE + (PORT datac (173:173:173) (203:203:203)) + (PORT datad (735:735:735) (718:718:718)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (904:904:904)) + (PORT datab (208:208:208) (245:245:245)) + (PORT datac (211:211:211) (256:256:256)) + (PORT datad (796:796:796) (802:802:802)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (1079:1079:1079) (1089:1089:1089)) + (PORT datac (877:877:877) (911:911:911)) + (PORT datad (335:335:335) (347:347:347)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (317:317:317)) + (PORT datab (659:659:659) (657:657:657)) + (PORT datac (811:811:811) (793:793:793)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (492:492:492) (524:524:524)) + (PORT clrn (1398:1398:1398) (1368:1368:1368)) + (PORT ena (1378:1378:1378) (1346:1346:1346)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (730:730:730)) + (PORT datab (1151:1151:1151) (1204:1204:1204)) + (PORT datac (893:893:893) (932:932:932)) + (PORT datad (1224:1224:1224) (1307:1307:1307)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (668:668:668)) + (PORT datab (914:914:914) (979:979:979)) + (PORT datac (1059:1059:1059) (1078:1078:1078)) + (PORT datad (1084:1084:1084) (1127:1127:1127)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (694:694:694)) + (PORT datab (350:350:350) (370:370:370)) + (PORT datac (1024:1024:1024) (1011:1011:1011)) + (PORT datad (1602:1602:1602) (1608:1608:1608)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (931:931:931)) + (PORT datab (1056:1056:1056) (1041:1041:1041)) + (PORT datac (1025:1025:1025) (1039:1039:1039)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1599:1599:1599) (1605:1605:1605)) + (PORT datab (978:978:978) (1056:1056:1056)) + (PORT datac (1110:1110:1110) (1156:1156:1156)) + (PORT datad (1056:1056:1056) (1063:1063:1063)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1596:1596:1596) (1601:1601:1601)) + (PORT datab (346:346:346) (372:372:372)) + (PORT datac (1391:1391:1391) (1462:1462:1462)) + (PORT datad (1019:1019:1019) (1003:1003:1003)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (253:253:253)) + (PORT datab (953:953:953) (995:995:995)) + (PORT datac (1024:1024:1024) (1012:1012:1012)) + (PORT datad (997:997:997) (1023:1023:1023)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (820:820:820)) + (PORT datab (1391:1391:1391) (1379:1379:1379)) + (PORT datac (770:770:770) (763:763:763)) + (PORT datad (803:803:803) (799:799:799)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT datac (987:987:987) (1048:1048:1048)) + (PORT datad (950:950:950) (998:998:998)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (386:386:386)) + (PORT datab (889:889:889) (937:937:937)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (254:254:254)) + (PORT datab (711:711:711) (776:776:776)) + (PORT datac (1249:1249:1249) (1305:1305:1305)) + (PORT datad (1421:1421:1421) (1458:1458:1458)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (341:341:341)) + (PORT datab (202:202:202) (235:235:235)) + (PORT datad (681:681:681) (739:739:739)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (2135:2135:2135) (2209:2209:2209)) + (PORT datab (220:220:220) (287:287:287)) + (PORT datac (536:536:536) (557:557:557)) + (PORT datad (1219:1219:1219) (1194:1194:1194)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (887:887:887) (941:941:941)) + (PORT datad (678:678:678) (747:747:747)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (574:574:574) (596:596:596)) + (PORT datad (886:886:886) (928:928:928)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (501:501:501)) + (PORT datab (607:607:607) (656:656:656)) + (PORT datac (560:560:560) (595:595:595)) + (PORT datad (668:668:668) (700:700:700)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~131) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (475:475:475)) + (PORT datab (324:324:324) (338:338:338)) + (PORT datad (237:237:237) (302:302:302)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (815:815:815)) + (PORT datab (1010:1010:1010) (988:988:988)) + (PORT datad (570:570:570) (568:568:568)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1071:1071:1071) (1090:1090:1090)) + (PORT datab (219:219:219) (286:286:286)) + (PORT datac (529:529:529) (551:551:551)) + (PORT datad (515:515:515) (511:511:511)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT datac (987:987:987) (1045:1045:1045)) + (PORT datad (950:950:950) (994:994:994)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (259:259:259)) + (PORT datab (363:363:363) (370:370:370)) + (PORT datac (843:843:843) (874:874:874)) + (PORT datad (303:303:303) (310:310:310)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT datab (890:890:890) (939:939:939)) + (PORT datad (315:315:315) (314:314:314)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (388:388:388)) + (PORT datab (890:890:890) (939:939:939)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (294:294:294)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datac (527:527:527) (527:527:527)) + (PORT datad (522:522:522) (510:510:510)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (918:918:918)) + (PORT datab (728:728:728) (803:803:803)) + (PORT datac (828:828:828) (877:877:877)) + (PORT datad (704:704:704) (778:778:778)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (354:354:354)) + (PORT datab (677:677:677) (738:738:738)) + (PORT datad (543:543:543) (537:537:537)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (238:238:238)) + (PORT datab (184:184:184) (218:218:218)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT datac (220:220:220) (290:290:290)) + (PORT datad (769:769:769) (789:789:789)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (681:681:681)) + (PORT datab (326:326:326) (337:337:337)) + (PORT datac (599:599:599) (636:636:636)) + (PORT datad (588:588:588) (618:618:618)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (233:233:233)) + (PORT datab (441:441:441) (481:481:481)) + (PORT datac (327:327:327) (340:340:340)) + (PORT datad (176:176:176) (209:209:209)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (724:724:724)) + (PORT datab (447:447:447) (513:513:513)) + (PORT datac (534:534:534) (537:537:537)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (748:748:748)) + (PORT datab (714:714:714) (779:779:779)) + (PORT datad (884:884:884) (922:922:922)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (331:331:331)) + (PORT datad (579:579:579) (592:592:592)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1543:1543:1543) (1518:1518:1518)) + (PORT datab (574:574:574) (597:597:597)) + (PORT datac (982:982:982) (1004:1004:1004)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (590:590:590) (591:591:591)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (546:546:546) (535:535:535)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~104) + (DELAY + (ABSOLUTE + (PORT datab (1135:1135:1135) (1151:1151:1151)) + (PORT datac (605:605:605) (649:649:649)) + (PORT datad (1287:1287:1287) (1270:1270:1270)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (878:878:878) (882:882:882)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1228:1228:1228) (1255:1255:1255)) + (PORT d[1] (1824:1824:1824) (1948:1948:1948)) + (PORT d[2] (2820:2820:2820) (2872:2872:2872)) + (PORT d[3] (2632:2632:2632) (2723:2723:2723)) + (PORT d[4] (2364:2364:2364) (2459:2459:2459)) + (PORT d[5] (2640:2640:2640) (2736:2736:2736)) + (PORT d[6] (1780:1780:1780) (1841:1841:1841)) + (PORT d[7] (2392:2392:2392) (2429:2429:2429)) + (PORT d[8] (3173:3173:3173) (3316:3316:3316)) + (PORT d[9] (1484:1484:1484) (1527:1527:1527)) + (PORT d[10] (4703:4703:4703) (4804:4804:4804)) + (PORT d[11] (1778:1778:1778) (1847:1847:1847)) + (PORT d[12] (1760:1760:1760) (1812:1812:1812)) + (PORT clk (1631:1631:1631) (1661:1661:1661)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1120:1120:1120) (1091:1091:1091)) + (PORT clk (1631:1631:1631) (1661:1661:1661)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1663:1663:1663)) + (PORT d[0] (2292:2292:2292) (2214:2214:2214)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1627:1627:1627)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (656:656:656) (645:645:645)) + (PORT clk (1644:1644:1644) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1171:1171:1171) (1169:1169:1169)) + (PORT d[1] (1948:1948:1948) (2094:2094:2094)) + (PORT d[2] (1153:1153:1153) (1155:1155:1155)) + (PORT d[3] (1204:1204:1204) (1226:1226:1226)) + (PORT d[4] (2425:2425:2425) (2533:2533:2533)) + (PORT d[5] (3217:3217:3217) (3322:3322:3322)) + (PORT d[6] (1222:1222:1222) (1272:1272:1272)) + (PORT d[7] (2666:2666:2666) (2711:2711:2711)) + (PORT d[8] (913:913:913) (921:921:921)) + (PORT d[9] (1196:1196:1196) (1239:1239:1239)) + (PORT d[10] (1257:1257:1257) (1305:1305:1305)) + (PORT d[11] (2298:2298:2298) (2368:2368:2368)) + (PORT d[12] (1485:1485:1485) (1525:1525:1525)) + (PORT clk (1641:1641:1641) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (895:895:895) (859:859:859)) + (PORT clk (1641:1641:1641) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1670:1670:1670)) + (PORT d[0] (1342:1342:1342) (1309:1309:1309)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (877:877:877) (875:875:875)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1236:1236:1236) (1266:1266:1266)) + (PORT d[1] (2925:2925:2925) (3075:3075:3075)) + (PORT d[2] (3248:3248:3248) (3283:3283:3283)) + (PORT d[3] (2633:2633:2633) (2727:2727:2727)) + (PORT d[4] (2375:2375:2375) (2474:2474:2474)) + (PORT d[5] (2666:2666:2666) (2765:2765:2765)) + (PORT d[6] (1549:1549:1549) (1579:1579:1579)) + (PORT d[7] (1389:1389:1389) (1407:1407:1407)) + (PORT d[8] (3197:3197:3197) (3346:3346:3346)) + (PORT d[9] (2980:2980:2980) (3056:3056:3056)) + (PORT d[10] (4704:4704:4704) (4809:4809:4809)) + (PORT d[11] (1809:1809:1809) (1884:1884:1884)) + (PORT d[12] (1752:1752:1752) (1799:1799:1799)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1579:1579:1579) (1512:1512:1512)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (1851:1851:1851) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1083:1083:1083) (1033:1033:1033)) + (PORT clk (1636:1636:1636) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3407:3407:3407) (3481:3481:3481)) + (PORT d[1] (1566:1566:1566) (1666:1666:1666)) + (PORT d[2] (1830:1830:1830) (1838:1838:1838)) + (PORT d[3] (1999:1999:1999) (2026:2026:2026)) + (PORT d[4] (2024:2024:2024) (2084:2084:2084)) + (PORT d[5] (1272:1272:1272) (1335:1335:1335)) + (PORT d[6] (1389:1389:1389) (1420:1420:1420)) + (PORT d[7] (1608:1608:1608) (1645:1645:1645)) + (PORT d[8] (3346:3346:3346) (3464:3464:3464)) + (PORT d[9] (2907:2907:2907) (2973:2973:2973)) + (PORT d[10] (2940:2940:2940) (3016:3016:3016)) + (PORT d[11] (1927:1927:1927) (1965:1965:1965)) + (PORT d[12] (1320:1320:1320) (1344:1344:1344)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1539:1539:1539) (1481:1481:1481)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1662:1662:1662)) + (PORT d[0] (2458:2458:2458) (2384:2384:2384)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (936:936:936)) + (PORT datab (1093:1093:1093) (1105:1105:1105)) + (PORT datac (774:774:774) (756:756:756)) + (PORT datad (976:976:976) (927:927:927)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1054:1054:1054)) + (PORT datab (1477:1477:1477) (1526:1526:1526)) + (PORT datac (1073:1073:1073) (1031:1031:1031)) + (PORT datad (287:287:287) (294:294:294)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2822:2822:2822) (2879:2879:2879)) + (PORT d[1] (2681:2681:2681) (2799:2799:2799)) + (PORT d[2] (1535:1535:1535) (1571:1571:1571)) + (PORT d[3] (1402:1402:1402) (1421:1421:1421)) + (PORT d[4] (1732:1732:1732) (1763:1763:1763)) + (PORT d[5] (1242:1242:1242) (1306:1306:1306)) + (PORT d[6] (1064:1064:1064) (1065:1065:1065)) + (PORT d[7] (1371:1371:1371) (1406:1406:1406)) + (PORT d[8] (2287:2287:2287) (2382:2382:2382)) + (PORT d[9] (3533:3533:3533) (3626:3626:3626)) + (PORT d[10] (2388:2388:2388) (2442:2442:2442)) + (PORT d[11] (1677:1677:1677) (1703:1703:1703)) + (PORT d[12] (1891:1891:1891) (1909:1909:1909)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (PORT d[0] (1181:1181:1181) (1144:1144:1144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1503:1503:1503) (1520:1520:1520)) + (PORT clk (1652:1652:1652) (1679:1679:1679)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2412:2412:2412) (2426:2426:2426)) + (PORT d[1] (1923:1923:1923) (2051:2051:2051)) + (PORT d[2] (2374:2374:2374) (2419:2419:2419)) + (PORT d[3] (2086:2086:2086) (2133:2133:2133)) + (PORT d[4] (2745:2745:2745) (2877:2877:2877)) + (PORT d[5] (1944:1944:1944) (2061:2061:2061)) + (PORT d[6] (1451:1451:1451) (1492:1492:1492)) + (PORT d[7] (2608:2608:2608) (2591:2591:2591)) + (PORT d[8] (2597:2597:2597) (2711:2711:2711)) + (PORT d[9] (1918:1918:1918) (1943:1943:1943)) + (PORT d[10] (1715:1715:1715) (1750:1750:1750)) + (PORT d[11] (3415:3415:3415) (3446:3446:3446)) + (PORT d[12] (1742:1742:1742) (1761:1761:1761)) + (PORT clk (1649:1649:1649) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2934:2934:2934) (2838:2838:2838)) + (PORT clk (1649:1649:1649) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1679:1679:1679)) + (PORT d[0] (2618:2618:2618) (2605:2605:2605)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2009:2009:2009) (2009:2009:2009)) + (PORT clk (1619:1619:1619) (1616:1616:1616)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4228:4228:4228) (4049:4049:4049)) + (PORT d[1] (4048:4048:4048) (3926:3926:3926)) + (PORT d[2] (4235:4235:4235) (4146:4146:4146)) + (PORT d[3] (4160:4160:4160) (4050:4050:4050)) + (PORT d[4] (4027:4027:4027) (3872:3872:3872)) + (PORT d[5] (4063:4063:4063) (3983:3983:3983)) + (PORT d[6] (4304:4304:4304) (4248:4248:4248)) + (PORT d[7] (3871:3871:3871) (3708:3708:3708)) + (PORT d[8] (4136:4136:4136) (4016:4016:4016)) + (PORT d[9] (4278:4278:4278) (4341:4341:4341)) + (PORT d[10] (4175:4175:4175) (4089:4089:4089)) + (PORT d[11] (4347:4347:4347) (4198:4198:4198)) + (PORT d[12] (4172:4172:4172) (4111:4111:4111)) + (PORT clk (1616:1616:1616) (1613:1613:1613)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1619:1619:1619) (1616:1616:1616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1237:1237:1237)) + (PORT datab (250:250:250) (328:328:328)) + (PORT datac (1247:1247:1247) (1214:1214:1214)) + (PORT datad (1361:1361:1361) (1371:1371:1371)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1461:1461:1461) (1472:1472:1472)) + (PORT clk (1656:1656:1656) (1683:1683:1683)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2158:2158:2158) (2147:2147:2147)) + (PORT d[1] (1907:1907:1907) (2023:2023:2023)) + (PORT d[2] (2137:2137:2137) (2217:2217:2217)) + (PORT d[3] (2113:2113:2113) (2196:2196:2196)) + (PORT d[4] (2735:2735:2735) (2857:2857:2857)) + (PORT d[5] (2220:2220:2220) (2324:2324:2324)) + (PORT d[6] (1719:1719:1719) (1765:1765:1765)) + (PORT d[7] (2330:2330:2330) (2325:2325:2325)) + (PORT d[8] (2908:2908:2908) (3035:3035:3035)) + (PORT d[9] (1649:1649:1649) (1670:1670:1670)) + (PORT d[10] (1675:1675:1675) (1693:1693:1693)) + (PORT d[11] (2723:2723:2723) (2755:2755:2755)) + (PORT d[12] (1741:1741:1741) (1769:1769:1769)) + (PORT clk (1653:1653:1653) (1681:1681:1681)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2037:2037:2037) (1970:1970:1970)) + (PORT clk (1653:1653:1653) (1681:1681:1681)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (PORT d[0] (2843:2843:2843) (2837:2837:2837)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1684:1684:1684)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1684:1684:1684)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1684:1684:1684)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1684:1684:1684)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1613:1613:1613)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2299:2299:2299) (2304:2304:2304)) + (PORT clk (1623:1623:1623) (1620:1620:1620)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4203:4203:4203) (4062:4062:4062)) + (PORT d[1] (3847:3847:3847) (3718:3718:3718)) + (PORT d[2] (4210:4210:4210) (4080:4080:4080)) + (PORT d[3] (4242:4242:4242) (4139:4139:4139)) + (PORT d[4] (4247:4247:4247) (4105:4105:4105)) + (PORT d[5] (4340:4340:4340) (4259:4259:4259)) + (PORT d[6] (4317:4317:4317) (4290:4290:4290)) + (PORT d[7] (3916:3916:3916) (3762:3762:3762)) + (PORT d[8] (4362:4362:4362) (4253:4253:4253)) + (PORT d[9] (4208:4208:4208) (4238:4238:4238)) + (PORT d[10] (4238:4238:4238) (4121:4121:4121)) + (PORT d[11] (4183:4183:4183) (4093:4093:4093)) + (PORT d[12] (4275:4275:4275) (4202:4202:4202)) + (PORT clk (1620:1620:1620) (1617:1617:1617)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1623:1623:1623) (1620:1620:1620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1624:1624:1624) (1621:1621:1621)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1624:1624:1624) (1621:1621:1621)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1624:1624:1624) (1621:1621:1621)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1624:1624:1624) (1621:1621:1621)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1616:1616:1616) (1614:1614:1614)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (911:911:911) (929:929:929)) + (PORT d[1] (916:916:916) (933:933:933)) + (PORT d[2] (1136:1136:1136) (1138:1138:1138)) + (PORT d[3] (1217:1217:1217) (1244:1244:1244)) + (PORT d[4] (2415:2415:2415) (2527:2527:2527)) + (PORT d[5] (2765:2765:2765) (2905:2905:2905)) + (PORT d[6] (908:908:908) (915:915:915)) + (PORT d[7] (1185:1185:1185) (1202:1202:1202)) + (PORT d[8] (958:958:958) (970:970:970)) + (PORT d[9] (901:901:901) (908:908:908)) + (PORT d[10] (1223:1223:1223) (1237:1237:1237)) + (PORT d[11] (2375:2375:2375) (2471:2471:2471)) + (PORT d[12] (1196:1196:1196) (1217:1217:1217)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (515:515:515) (535:535:535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1192:1192:1192) (1154:1154:1154)) + (PORT datab (816:816:816) (796:796:796)) + (PORT datac (802:802:802) (785:785:785)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (230:230:230)) + (PORT datab (253:253:253) (331:331:331)) + (PORT datac (1507:1507:1507) (1487:1487:1487)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (855:855:855) (894:894:894)) + (PORT datac (1100:1100:1100) (1115:1115:1115)) + (PORT datad (531:531:531) (535:535:535)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (368:368:368)) + (PORT datab (210:210:210) (250:250:250)) + (PORT datac (163:163:163) (196:196:196)) + (PORT datad (168:168:168) (192:192:192)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (443:443:443)) + (PORT datab (210:210:210) (251:251:251)) + (PORT datac (1059:1059:1059) (1047:1047:1047)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (934:934:934)) + (PORT datab (593:593:593) (598:598:598)) + (PORT datac (552:552:552) (544:544:544)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1141:1141:1141) (1105:1105:1105)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (852:852:852) (848:848:848)) + (PORT datac (871:871:871) (900:900:900)) + (PORT datad (199:199:199) (229:229:229)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (449:449:449)) + (PORT datab (215:215:215) (253:253:253)) + (PORT datac (203:203:203) (251:251:251)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1395:1395:1395) (1367:1367:1367)) + (PORT ena (1130:1130:1130) (1103:1103:1103)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT datac (1336:1336:1336) (1363:1363:1363)) + (PORT datad (2097:2097:2097) (2151:2151:2151)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (871:871:871)) + (PORT datab (866:866:866) (898:898:898)) + (PORT datac (1486:1486:1486) (1580:1580:1580)) + (PORT datad (1135:1135:1135) (1165:1165:1165)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (198:198:198) (231:231:231)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (781:781:781) (779:779:779)) + (PORT datab (1913:1913:1913) (1971:1971:1971)) + (PORT datac (1168:1168:1168) (1229:1229:1229)) + (PORT datad (1001:1001:1001) (989:989:989)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1413:1413:1413) (1379:1379:1379)) + (PORT ena (1556:1556:1556) (1512:1512:1512)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1162:1162:1162)) + (PORT datab (1910:1910:1910) (1969:1969:1969)) + (PORT datac (1180:1180:1180) (1261:1261:1261)) + (PORT datad (1734:1734:1734) (1725:1725:1725)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1408:1408:1408) (1374:1374:1374)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT datab (230:230:230) (301:301:301)) + (PORT datad (207:207:207) (267:267:267)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (PORT ena (1790:1790:1790) (1839:1839:1839)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (314:314:314)) + (PORT datac (1030:1030:1030) (1031:1031:1031)) + (PORT datad (1041:1041:1041) (1032:1032:1032)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (PORT ena (1790:1790:1790) (1839:1839:1839)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x3) + (DELAY + (ABSOLUTE + (PORT dataa (2203:2203:2203) (2261:2261:2261)) + (PORT datac (217:217:217) (284:284:284)) + (PORT datad (1256:1256:1256) (1355:1355:1355)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1667:1667:1667) (1646:1646:1646)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1453:1453:1453) (1482:1482:1482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1060:1060:1060) (1064:1064:1064)) + (PORT datab (255:255:255) (332:332:332)) + (PORT datad (1047:1047:1047) (1037:1037:1037)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~3) + (DELAY + (ABSOLUTE + (PORT datac (968:968:968) (1046:1046:1046)) + (PORT datad (1866:1866:1866) (1882:1882:1882)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1349:1349:1349) (1370:1370:1370)) + (PORT datab (785:785:785) (802:802:802)) + (PORT datac (735:735:735) (729:729:729)) + (PORT datad (611:611:611) (629:629:629)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (957:957:957)) + (PORT datab (617:617:617) (624:624:624)) + (PORT datac (880:880:880) (892:892:892)) + (PORT datad (2085:2085:2085) (2090:2090:2090)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (809:809:809)) + (PORT datab (780:780:780) (771:771:771)) + (PORT datac (859:859:859) (884:884:884)) + (PORT datad (372:372:372) (382:382:382)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (644:644:644)) + (PORT datab (310:310:310) (327:327:327)) + (PORT datac (1356:1356:1356) (1374:1374:1374)) + (PORT datad (1918:1918:1918) (1931:1931:1931)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (380:380:380)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (165:165:165) (190:190:190)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1847:1847:1847) (1878:1878:1878)) + (PORT datab (798:798:798) (792:792:792)) + (PORT datac (1341:1341:1341) (1341:1341:1341)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (249:249:249)) + (PORT datab (212:212:212) (254:254:254)) + (PORT datac (326:326:326) (340:340:340)) + (PORT datad (982:982:982) (970:970:970)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (252:252:252)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (915:915:915) (941:941:941)) + (PORT datad (730:730:730) (727:727:727)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT datab (1021:1021:1021) (1030:1030:1030)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (296:296:296) (297:297:297)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT datac (715:715:715) (700:700:700)) + (PORT datad (563:563:563) (569:569:569)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~5) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (226:226:226)) + (PORT datab (1883:1883:1883) (1863:1863:1863)) + (PORT datac (580:580:580) (600:600:600)) + (PORT datad (316:316:316) (307:307:307)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (748:748:748)) + (PORT datab (808:808:808) (829:829:829)) + (PORT datac (950:950:950) (937:937:937)) + (PORT datad (496:496:496) (489:489:489)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (320:320:320)) + (PORT datac (1029:1029:1029) (1026:1026:1026)) + (PORT datad (1051:1051:1051) (1039:1039:1039)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (PORT ena (1790:1790:1790) (1839:1839:1839)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (1053:1053:1053) (1051:1051:1051)) + (PORT datac (222:222:222) (293:293:293)) + (PORT datad (1051:1051:1051) (1043:1043:1043)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (PORT ena (1790:1790:1790) (1839:1839:1839)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT datab (241:241:241) (310:310:310)) + (PORT datac (1013:1013:1013) (1010:1010:1010)) + (PORT datad (1055:1055:1055) (1045:1045:1045)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (PORT ena (1790:1790:1790) (1839:1839:1839)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (569:569:569)) + (PORT datab (816:816:816) (818:818:818)) + (PORT datac (549:549:549) (564:564:564)) + (PORT datad (849:849:849) (880:880:880)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal77\~1) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (1007:1007:1007)) + (PORT datab (1100:1100:1100) (1122:1122:1122)) + (PORT datac (599:599:599) (635:635:635)) + (PORT datad (1151:1151:1151) (1207:1207:1207)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (639:639:639)) + (PORT datab (1532:1532:1532) (1512:1512:1512)) + (PORT datac (807:807:807) (801:801:801)) + (PORT datad (793:793:793) (792:792:792)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~14) + (DELAY + (ABSOLUTE + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (589:589:589) (602:602:602)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~41) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (398:398:398)) + (PORT datac (998:998:998) (981:981:981)) + (PORT datad (184:184:184) (208:208:208)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (887:887:887)) + (PORT datab (1013:1013:1013) (1053:1053:1053)) + (PORT datac (372:372:372) (402:402:402)) + (PORT datad (2321:2321:2321) (2343:2343:2343)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1847:1847:1847) (1918:1918:1918)) + (PORT datab (712:712:712) (752:752:752)) + (PORT datac (885:885:885) (901:901:901)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (838:838:838)) + (PORT datab (326:326:326) (348:348:348)) + (PORT datac (182:182:182) (216:216:216)) + (PORT datad (704:704:704) (684:684:684)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (361:361:361)) + (PORT datab (969:969:969) (965:965:965)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (1210:1210:1210) (1195:1195:1195)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1039:1039:1039) (1043:1043:1043)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (180:180:180) (214:214:214)) + (PORT datad (166:166:166) (193:193:193)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (780:780:780)) + (PORT datab (1460:1460:1460) (1549:1549:1549)) + (PORT datac (577:577:577) (576:576:576)) + (PORT datad (1557:1557:1557) (1605:1605:1605)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~7) + (DELAY + (ABSOLUTE + (PORT datab (794:794:794) (821:821:821)) + (PORT datac (823:823:823) (838:838:838)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1334:1334:1334) (1334:1334:1334)) + (PORT datab (803:803:803) (797:797:797)) + (PORT datac (811:811:811) (824:824:824)) + (PORT datad (577:577:577) (578:578:578)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1375:1375:1375) (1454:1454:1454)) + (PORT datab (1812:1812:1812) (1844:1844:1844)) + (PORT datac (1240:1240:1240) (1288:1288:1288)) + (PORT datad (1027:1027:1027) (1026:1026:1026)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (239:239:239)) + (PORT datab (1045:1045:1045) (1040:1040:1040)) + (PORT datac (478:478:478) (466:466:466)) + (PORT datad (591:591:591) (606:606:606)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~11) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (1127:1127:1127) (1133:1133:1133)) + (PORT datac (938:938:938) (948:948:948)) + (PORT datad (320:320:320) (321:321:321)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (601:601:601)) + (PORT datab (967:967:967) (963:963:963)) + (PORT datac (1852:1852:1852) (1836:1836:1836)) + (PORT datad (572:572:572) (581:581:581)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (588:588:588)) + (PORT datab (857:857:857) (877:877:877)) + (PORT datac (1676:1676:1676) (1729:1729:1729)) + (PORT datad (818:818:818) (827:827:827)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (357:357:357)) + (PORT datab (1132:1132:1132) (1137:1137:1137)) + (PORT datac (1298:1298:1298) (1315:1315:1315)) + (PORT datad (776:776:776) (761:761:761)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (811:811:811)) + (PORT datab (847:847:847) (854:854:854)) + (PORT datac (836:836:836) (830:830:830)) + (PORT datad (782:782:782) (783:783:783)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (882:882:882)) + (PORT datab (337:337:337) (351:351:351)) + (PORT datac (796:796:796) (810:810:810)) + (PORT datad (1018:1018:1018) (1013:1013:1013)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (548:548:548)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (832:832:832) (844:844:844)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1041:1041:1041) (1098:1098:1098)) + (PORT datac (574:574:574) (578:578:578)) + (PORT datad (1463:1463:1463) (1509:1509:1509)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (802:802:802) (826:826:826)) + (PORT datab (1442:1442:1442) (1485:1485:1485)) + (PORT datac (796:796:796) (808:808:808)) + (PORT datad (1033:1033:1033) (1055:1055:1055)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (642:642:642)) + (PORT datab (616:616:616) (622:622:622)) + (PORT datac (1876:1876:1876) (1825:1825:1825)) + (PORT datad (875:875:875) (914:914:914)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (591:591:591) (617:617:617)) + (PORT datad (618:618:618) (657:657:657)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~22) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (885:885:885)) + (PORT datab (835:835:835) (821:821:821)) + (PORT datac (818:818:818) (833:833:833)) + (PORT datad (573:573:573) (585:585:585)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1599:1599:1599) (1658:1658:1658)) + (PORT datab (1429:1429:1429) (1495:1495:1495)) + (PORT datac (1123:1123:1123) (1162:1162:1162)) + (PORT datad (1378:1378:1378) (1406:1406:1406)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~53) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (922:922:922)) + (PORT datab (857:857:857) (886:886:886)) + (PORT datac (597:597:597) (611:611:611)) + (PORT datad (1199:1199:1199) (1205:1205:1205)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~23) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (337:337:337) (357:357:357)) + (PORT datac (1413:1413:1413) (1418:1418:1418)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (367:367:367)) + (PORT datab (915:915:915) (914:914:914)) + (PORT datac (1406:1406:1406) (1456:1456:1456)) + (PORT datad (176:176:176) (198:198:198)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (576:576:576)) + (PORT datab (645:645:645) (668:668:668)) + (PORT datac (601:601:601) (626:626:626)) + (PORT datad (1213:1213:1213) (1266:1266:1266)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (615:615:615)) + (PORT datab (1087:1087:1087) (1081:1081:1081)) + (PORT datac (803:803:803) (828:828:828)) + (PORT datad (559:559:559) (573:573:573)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~34) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (580:580:580)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (287:287:287) (302:302:302)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~52) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (294:294:294) (298:298:298)) + (PORT datad (896:896:896) (948:948:948)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1054:1054:1054)) + (PORT datac (221:221:221) (291:291:291)) + (PORT datad (1054:1054:1054) (1045:1045:1045)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (PORT ena (1790:1790:1790) (1839:1839:1839)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (DELAY + (ABSOLUTE + (PORT datac (910:910:910) (962:962:962)) + (PORT datad (1249:1249:1249) (1347:1347:1347)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (455:455:455)) + (PORT datac (1095:1095:1095) (1138:1138:1138)) + (PORT datad (248:248:248) (314:314:314)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (624:624:624)) + (PORT datab (1469:1469:1469) (1435:1435:1435)) + (PORT datad (583:583:583) (604:604:604)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (937:937:937)) + (PORT datab (1083:1083:1083) (1086:1086:1086)) + (PORT datac (627:627:627) (644:644:644)) + (PORT datad (584:584:584) (600:600:600)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1034:1034:1034) (1114:1114:1114)) + (PORT datab (920:920:920) (954:954:954)) + (PORT datac (1064:1064:1064) (1070:1070:1070)) + (PORT datad (810:810:810) (834:834:834)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (387:387:387)) + (PORT datab (634:634:634) (662:662:662)) + (PORT datac (824:824:824) (850:850:850)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (1009:1009:1009) (991:991:991)) + (PORT datad (598:598:598) (594:594:594)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (237:237:237)) + (PORT datab (879:879:879) (890:890:890)) + (PORT datac (592:592:592) (588:588:588)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (278:278:278)) + (PORT datac (871:871:871) (897:897:897)) + (PORT datad (319:319:319) (319:319:319)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (259:259:259)) + (PORT datab (715:715:715) (783:783:783)) + (PORT datac (1250:1250:1250) (1311:1311:1311)) + (PORT datad (524:524:524) (516:516:516)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (590:590:590)) + (PORT datab (676:676:676) (742:742:742)) + (PORT datad (662:662:662) (727:727:727)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (757:757:757)) + (PORT datab (1089:1089:1089) (1147:1147:1147)) + (PORT datac (667:667:667) (731:731:731)) + (PORT datad (673:673:673) (744:744:744)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (225:225:225)) + (PORT datab (191:191:191) (227:227:227)) + (PORT datad (169:169:169) (193:193:193)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1042:1042:1042) (1038:1038:1038)) + (PORT datab (1068:1068:1068) (1080:1080:1080)) + (PORT datac (195:195:195) (262:262:262)) + (PORT datad (332:332:332) (369:369:369)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~99) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (773:773:773)) + (PORT datab (669:669:669) (726:726:726)) + (PORT datac (809:809:809) (846:846:846)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (341:341:341)) + (PORT datab (184:184:184) (216:216:216)) + (PORT datad (677:677:677) (738:738:738)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (751:751:751)) + (PORT datab (911:911:911) (964:964:964)) + (PORT datad (861:861:861) (908:908:908)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (759:759:759)) + (PORT datab (668:668:668) (738:738:738)) + (PORT datac (1059:1059:1059) (1118:1118:1118)) + (PORT datad (838:838:838) (881:881:881)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~133) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (639:639:639)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datac (668:668:668) (734:734:734)) + (PORT datad (668:668:668) (738:738:738)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (220:220:220)) + (PORT datad (303:303:303) (304:304:304)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1379:1379:1379)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (558:558:558)) + (PORT datab (394:394:394) (426:426:426)) + (PORT datac (525:525:525) (528:528:528)) + (PORT datad (576:576:576) (609:609:609)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (728:728:728)) + (PORT datab (672:672:672) (738:738:738)) + (PORT datac (660:660:660) (729:729:729)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (221:221:221)) + (PORT datab (335:335:335) (355:355:355)) + (PORT datad (661:661:661) (726:726:726)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (1301:1301:1301) (1378:1378:1378)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (882:882:882) (920:920:920)) + (PORT datad (186:186:186) (212:212:212)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (715:715:715)) + (PORT datab (613:613:613) (653:653:653)) + (PORT datac (599:599:599) (635:635:635)) + (PORT datad (402:402:402) (445:445:445)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (253:253:253)) + (PORT datab (374:374:374) (437:437:437)) + (PORT datac (577:577:577) (623:623:623)) + (PORT datad (374:374:374) (422:422:422)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~134) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (360:360:360)) + (PORT datab (357:357:357) (355:355:355)) + (PORT datad (771:771:771) (785:785:785)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (738:738:738)) + (PORT datab (563:563:563) (574:574:574)) + (PORT datac (574:574:574) (594:594:594)) + (PORT datad (490:490:490) (478:478:478)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~135) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (742:742:742)) + (PORT datab (248:248:248) (322:322:322)) + (PORT datad (1012:1012:1012) (1017:1017:1017)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (221:221:221)) + (PORT datab (344:344:344) (366:366:366)) + (PORT datad (161:161:161) (181:181:181)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (294:294:294)) + (PORT datab (1116:1116:1116) (1127:1127:1127)) + (PORT datac (580:580:580) (615:615:615)) + (PORT datad (725:725:725) (703:703:703)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (792:792:792)) + (PORT datab (200:200:200) (243:243:243)) + (PORT datac (592:592:592) (617:617:617)) + (PORT datad (302:302:302) (303:303:303)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (716:716:716)) + (PORT datab (184:184:184) (218:218:218)) + (PORT datac (531:531:531) (535:535:535)) + (PORT datad (420:420:420) (476:476:476)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) + (DELAY + (ABSOLUTE + (PORT datab (530:530:530) (510:510:510)) + (PORT datad (810:810:810) (810:810:810)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1389:1389:1389) (1370:1370:1370)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (719:719:719)) + (PORT datab (606:606:606) (639:639:639)) + (PORT datac (592:592:592) (618:618:618)) + (PORT datad (743:743:743) (755:755:755)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (719:719:719)) + (PORT datab (202:202:202) (246:246:246)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (587:587:587) (622:622:622)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~137) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (735:735:735)) + (PORT datab (311:311:311) (328:328:328)) + (PORT datad (320:320:320) (332:332:332)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~138) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1042:1042:1042)) + (PORT datab (617:617:617) (625:625:625)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (DELAY + (ABSOLUTE + (PORT datab (1289:1289:1289) (1294:1294:1294)) + (PORT datac (1505:1505:1505) (1522:1522:1522)) + (PORT datad (1100:1100:1100) (1138:1138:1138)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (250:250:250)) + (PORT datab (1109:1109:1109) (1116:1116:1116)) + (PORT datac (1094:1094:1094) (1124:1124:1124)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (1044:1044:1044) (1051:1051:1051)) + (PORT datab (3054:3054:3054) (3103:3103:3103)) + (PORT datac (1064:1064:1064) (1065:1065:1065)) + (PORT datad (522:522:522) (508:508:508)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (980:980:980) (986:986:986)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3707:3707:3707) (3804:3804:3804)) + (PORT d[1] (1578:1578:1578) (1672:1672:1672)) + (PORT d[2] (1570:1570:1570) (1580:1580:1580)) + (PORT d[3] (1744:1744:1744) (1781:1781:1781)) + (PORT d[4] (2000:2000:2000) (2056:2056:2056)) + (PORT d[5] (1252:1252:1252) (1314:1314:1314)) + (PORT d[6] (1393:1393:1393) (1427:1427:1427)) + (PORT d[7] (3116:3116:3116) (3137:3137:3137)) + (PORT d[8] (3368:3368:3368) (3477:3477:3477)) + (PORT d[9] (1365:1365:1365) (1402:1402:1402)) + (PORT d[10] (2948:2948:2948) (3034:3034:3034)) + (PORT d[11] (1950:1950:1950) (1990:1990:1990)) + (PORT d[12] (1611:1611:1611) (1636:1636:1636)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2373:2373:2373) (2344:2344:2344)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (2716:2716:2716) (2716:2716:2716)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (630:630:630) (628:628:628)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2822:2822:2822) (2886:2886:2886)) + (PORT d[1] (1278:1278:1278) (1342:1342:1342)) + (PORT d[2] (1874:1874:1874) (1890:1890:1890)) + (PORT d[3] (2022:2022:2022) (2058:2058:2058)) + (PORT d[4] (1456:1456:1456) (1471:1471:1471)) + (PORT d[5] (1295:1295:1295) (1333:1333:1333)) + (PORT d[6] (1113:1113:1113) (1134:1134:1134)) + (PORT d[7] (3108:3108:3108) (3147:3147:3147)) + (PORT d[8] (2300:2300:2300) (2397:2397:2397)) + (PORT d[9] (3216:3216:3216) (3294:3294:3294)) + (PORT d[10] (2671:2671:2671) (2745:2745:2745)) + (PORT d[11] (1652:1652:1652) (1662:1662:1662)) + (PORT d[12] (1326:1326:1326) (1338:1338:1338)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1816:1816:1816) (1750:1750:1750)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (2737:2737:2737) (2658:2658:2658)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (922:922:922) (927:927:927)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2795:2795:2795) (2848:2848:2848)) + (PORT d[1] (1266:1266:1266) (1343:1343:1343)) + (PORT d[2] (1514:1514:1514) (1548:1548:1548)) + (PORT d[3] (1400:1400:1400) (1414:1414:1414)) + (PORT d[4] (1779:1779:1779) (1814:1814:1814)) + (PORT d[5] (1512:1512:1512) (1565:1565:1565)) + (PORT d[6] (1276:1276:1276) (1252:1252:1252)) + (PORT d[7] (1343:1343:1343) (1370:1370:1370)) + (PORT d[8] (1995:1995:1995) (2080:2080:2080)) + (PORT d[9] (3525:3525:3525) (3617:3617:3617)) + (PORT d[10] (2413:2413:2413) (2469:2469:2469)) + (PORT d[11] (1699:1699:1699) (1726:1726:1726)) + (PORT d[12] (1884:1884:1884) (1885:1885:1885)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1540:1540:1540) (1489:1489:1489)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (2009:2009:2009) (1976:1976:1976)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (583:583:583)) + (PORT datab (1241:1241:1241) (1253:1253:1253)) + (PORT datac (822:822:822) (826:826:826)) + (PORT datad (1069:1069:1069) (1093:1093:1093)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1194:1194:1194) (1213:1213:1213)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3401:3401:3401) (3484:3484:3484)) + (PORT d[1] (1574:1574:1574) (1681:1681:1681)) + (PORT d[2] (2794:2794:2794) (2844:2844:2844)) + (PORT d[3] (2020:2020:2020) (2045:2045:2045)) + (PORT d[4] (2098:2098:2098) (2151:2151:2151)) + (PORT d[5] (2235:2235:2235) (2358:2358:2358)) + (PORT d[6] (1916:1916:1916) (1960:1960:1960)) + (PORT d[7] (2559:2559:2559) (2570:2570:2570)) + (PORT d[8] (2818:2818:2818) (2924:2924:2924)) + (PORT d[9] (2371:2371:2371) (2420:2420:2420)) + (PORT d[10] (3473:3473:3473) (3560:3560:3560)) + (PORT d[11] (1678:1678:1678) (1707:1707:1707)) + (PORT d[12] (1889:1889:1889) (1941:1941:1941)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2582:2582:2582) (2504:2504:2504)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (2502:2502:2502) (2419:2419:2419)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1126:1126:1126)) + (PORT datab (871:871:871) (890:890:890)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1322:1322:1322) (1324:1324:1324)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3379:3379:3379) (3440:3440:3440)) + (PORT d[1] (2405:2405:2405) (2528:2528:2528)) + (PORT d[2] (1530:1530:1530) (1562:1562:1562)) + (PORT d[3] (1999:1999:1999) (2040:2040:2040)) + (PORT d[4] (1736:1736:1736) (1773:1773:1773)) + (PORT d[5] (1249:1249:1249) (1314:1314:1314)) + (PORT d[6] (1072:1072:1072) (1078:1078:1078)) + (PORT d[7] (1356:1356:1356) (1369:1369:1369)) + (PORT d[8] (2015:2015:2015) (2100:2100:2100)) + (PORT d[9] (3546:3546:3546) (3640:3640:3640)) + (PORT d[10] (2382:2382:2382) (2434:2434:2434)) + (PORT d[11] (1950:1950:1950) (1977:1977:1977)) + (PORT d[12] (1872:1872:1872) (1878:1878:1878)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (3104:3104:3104) (3115:3115:3115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1628:1628:1628)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (875:875:875)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1369:1369:1369) (1374:1374:1374)) + (PORT clk (1631:1631:1631) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3108:3108:3108) (3171:3171:3171)) + (PORT d[1] (2132:2132:2132) (2244:2244:2244)) + (PORT d[2] (2028:2028:2028) (2054:2054:2054)) + (PORT d[3] (1703:1703:1703) (1741:1741:1741)) + (PORT d[4] (2005:2005:2005) (2050:2050:2050)) + (PORT d[5] (1526:1526:1526) (1603:1603:1603)) + (PORT d[6] (1381:1381:1381) (1387:1387:1387)) + (PORT d[7] (1387:1387:1387) (1412:1412:1412)) + (PORT d[8] (2698:2698:2698) (2780:2780:2780)) + (PORT d[9] (2115:2115:2115) (2160:2160:2160)) + (PORT d[10] (2120:2120:2120) (2141:2141:2141)) + (PORT d[11] (2296:2296:2296) (2349:2349:2349)) + (PORT d[12] (1833:1833:1833) (1854:1854:1854)) + (PORT clk (1628:1628:1628) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2623:2623:2623) (2592:2592:2592)) + (PORT clk (1628:1628:1628) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1660:1660:1660)) + (PORT d[0] (3652:3652:3652) (3652:3652:3652)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1590:1590:1590) (1590:1590:1590)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2131:2131:2131) (2069:2069:2069)) + (PORT clk (1598:1598:1598) (1597:1597:1597)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4055:4055:4055) (3966:3966:3966)) + (PORT d[1] (3960:3960:3960) (3871:3871:3871)) + (PORT d[2] (3972:3972:3972) (3879:3879:3879)) + (PORT d[3] (4222:4222:4222) (4150:4150:4150)) + (PORT d[4] (3999:3999:3999) (3860:3860:3860)) + (PORT d[5] (4046:4046:4046) (3954:3954:3954)) + (PORT d[6] (4173:4173:4173) (4155:4155:4155)) + (PORT d[7] (4052:4052:4052) (3984:3984:3984)) + (PORT d[8] (4288:4288:4288) (4117:4117:4117)) + (PORT d[9] (4142:4142:4142) (4230:4230:4230)) + (PORT d[10] (4065:4065:4065) (3987:3987:3987)) + (PORT d[11] (4060:4060:4060) (3947:3947:3947)) + (PORT d[12] (4312:4312:4312) (4202:4202:4202)) + (PORT clk (1595:1595:1595) (1594:1594:1594)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1597:1597:1597)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (847:847:847)) + (PORT datab (1559:1559:1559) (1578:1578:1578)) + (PORT datac (849:849:849) (860:860:860)) + (PORT datad (1100:1100:1100) (1108:1108:1108)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3343:3343:3343) (3403:3403:3403)) + (PORT d[1] (2414:2414:2414) (2527:2527:2527)) + (PORT d[2] (1429:1429:1429) (1441:1441:1441)) + (PORT d[3] (1966:1966:1966) (2008:2008:2008)) + (PORT d[4] (2008:2008:2008) (2048:2048:2048)) + (PORT d[5] (1520:1520:1520) (1595:1595:1595)) + (PORT d[6] (1309:1309:1309) (1307:1307:1307)) + (PORT d[7] (1368:1368:1368) (1386:1386:1386)) + (PORT d[8] (1998:1998:1998) (2066:2066:2066)) + (PORT d[9] (2127:2127:2127) (2184:2184:2184)) + (PORT d[10] (2112:2112:2112) (2157:2157:2157)) + (PORT d[11] (1966:1966:1966) (2005:2005:2005)) + (PORT d[12] (2122:2122:2122) (2139:2139:2139)) + (PORT clk (1633:1633:1633) (1661:1661:1661)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (PORT d[0] (3092:3092:3092) (3079:3079:3079)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1662:1662:1662)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1600:1600:1600) (1627:1627:1627)) @@ -35111,7 +49523,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (871:871:871) (874:874:874)) @@ -35120,7 +49532,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) (DELAY (ABSOLUTE (PORT clk (872:872:872) (875:875:875)) @@ -35129,7 +49541,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (872:872:872) (875:875:875)) @@ -35139,7 +49551,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (872:872:872) (875:875:875)) @@ -35149,27 +49561,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12) + (INSTANCE D\[3\]\~71) (DELAY (ABSOLUTE - (PORT dataa (298:298:298) (411:411:411)) - (PORT datab (1437:1437:1437) (1474:1474:1474)) - (PORT datac (1060:1060:1060) (1093:1093:1093)) - (PORT datad (1144:1144:1144) (1142:1142:1142)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (209:209:209) (250:250:250)) + (PORT datab (847:847:847) (835:835:835)) + (PORT datac (1051:1051:1051) (1049:1049:1049)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1404:1404:1404) (1395:1395:1395)) - (PORT clk (1649:1649:1649) (1676:1676:1676)) + (PORT d[0] (1450:1450:1450) (1449:1449:1449)) + (PORT clk (1648:1648:1648) (1675:1675:1675)) ) ) (TIMINGCHECK @@ -35178,23 +49590,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1247:1247:1247) (1283:1283:1283)) - (PORT d[1] (2870:2870:2870) (3026:3026:3026)) - (PORT d[2] (1505:1505:1505) (1571:1571:1571)) - (PORT d[3] (664:664:664) (683:683:683)) - (PORT d[4] (643:643:643) (648:648:648)) - (PORT d[5] (1453:1453:1453) (1484:1484:1484)) - (PORT d[6] (2747:2747:2747) (2765:2765:2765)) - (PORT d[7] (2142:2142:2142) (2158:2158:2158)) - (PORT d[8] (3471:3471:3471) (3566:3566:3566)) - (PORT d[9] (639:639:639) (638:638:638)) - (PORT d[10] (2378:2378:2378) (2452:2452:2452)) - (PORT d[11] (2064:2064:2064) (2170:2170:2170)) - (PORT d[12] (2458:2458:2458) (2472:2472:2472)) - (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (2348:2348:2348) (2361:2361:2361)) + (PORT d[1] (1826:1826:1826) (1904:1904:1904)) + (PORT d[2] (1810:1810:1810) (1851:1851:1851)) + (PORT d[3] (1736:1736:1736) (1783:1783:1783)) + (PORT d[4] (2527:2527:2527) (2584:2584:2584)) + (PORT d[5] (2063:2063:2063) (2160:2160:2160)) + (PORT d[6] (1896:1896:1896) (1915:1915:1915)) + (PORT d[7] (2227:2227:2227) (2299:2299:2299)) + (PORT d[8] (2227:2227:2227) (2294:2294:2294)) + (PORT d[9] (1856:1856:1856) (1895:1895:1895)) + (PORT d[10] (1573:1573:1573) (1593:1593:1593)) + (PORT d[11] (1905:1905:1905) (1933:1933:1933)) + (PORT d[12] (2334:2334:2334) (2363:2363:2363)) + (PORT clk (1645:1645:1645) (1673:1673:1673)) ) ) (TIMINGCHECK @@ -35203,11 +49615,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1990:1990:1990) (1919:1919:1919)) - (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (2467:2467:2467) (2383:2383:2383)) + (PORT clk (1645:1645:1645) (1673:1673:1673)) ) ) (TIMINGCHECK @@ -35216,60 +49628,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1675:1675:1675)) + (PORT d[0] (3048:3048:3048) (3059:3059:3059)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1649:1649:1649) (1676:1676:1676)) - (PORT d[0] (2293:2293:2293) (2239:2239:2239)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1650:1650:1650) (1677:1677:1677)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1650:1650:1650) (1677:1677:1677)) + (PORT clk (1649:1649:1649) (1676:1676:1676)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1650:1650:1650) (1677:1677:1677)) + (PORT clk (1649:1649:1649) (1676:1676:1676)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1650:1650:1650) (1677:1677:1677)) + (PORT clk (1649:1649:1649) (1676:1676:1676)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1613:1613:1613) (1640:1640:1640)) + (PORT clk (1607:1607:1607) (1605:1605:1605)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -35280,49 +49692,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (884:884:884) (887:887:887)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (885:885:885) (888:888:888)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (885:885:885) (888:888:888)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (885:885:885) (888:888:888)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2581:2581:2581) (2548:2548:2548)) - (PORT clk (1633:1633:1633) (1662:1662:1662)) + (PORT d[0] (1916:1916:1916) (1862:1862:1862)) + (PORT clk (1615:1615:1615) (1612:1612:1612)) ) ) (TIMINGCHECK @@ -35331,23 +49705,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (3482:3482:3482) (3632:3632:3632)) - (PORT d[1] (1965:1965:1965) (2079:2079:2079)) - (PORT d[2] (3740:3740:3740) (3845:3845:3845)) - (PORT d[3] (3048:3048:3048) (3226:3226:3226)) - (PORT d[4] (2677:2677:2677) (2776:2776:2776)) - (PORT d[5] (3670:3670:3670) (3812:3812:3812)) - (PORT d[6] (1565:1565:1565) (1553:1553:1553)) - (PORT d[7] (2863:2863:2863) (2893:2893:2893)) - (PORT d[8] (2303:2303:2303) (2385:2385:2385)) - (PORT d[9] (2641:2641:2641) (2647:2647:2647)) - (PORT d[10] (2423:2423:2423) (2511:2511:2511)) - (PORT d[11] (1415:1415:1415) (1457:1457:1457)) - (PORT d[12] (2048:2048:2048) (2042:2042:2042)) - (PORT clk (1630:1630:1630) (1660:1660:1660)) + (PORT d[0] (4316:4316:4316) (4210:4210:4210)) + (PORT d[1] (3963:3963:3963) (3872:3872:3872)) + (PORT d[2] (4234:4234:4234) (4138:4138:4138)) + (PORT d[3] (4142:4142:4142) (4039:4039:4039)) + (PORT d[4] (4033:4033:4033) (3901:3901:3901)) + (PORT d[5] (4276:4276:4276) (4177:4177:4177)) + (PORT d[6] (4393:4393:4393) (4366:4366:4366)) + (PORT d[7] (4261:4261:4261) (4171:4171:4171)) + (PORT d[8] (4248:4248:4248) (4146:4146:4146)) + (PORT d[9] (4156:4156:4156) (4242:4242:4242)) + (PORT d[10] (4088:4088:4088) (4006:4006:4006)) + (PORT d[11] (4322:4322:4322) (4216:4216:4216)) + (PORT d[12] (4272:4272:4272) (4307:4307:4307)) + (PORT clk (1612:1612:1612) (1609:1609:1609)) ) ) (TIMINGCHECK @@ -35356,738 +49730,59 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1305:1305:1305) (1224:1224:1224)) - (PORT clk (1630:1630:1630) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1662:1662:1662)) - (PORT d[0] (1740:1740:1740) (1665:1665:1665)) + (PORT clk (1615:1615:1615) (1612:1612:1612)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1634:1634:1634) (1663:1663:1663)) + (PORT clk (1616:1616:1616) (1613:1613:1613)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1634:1634:1634) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1597:1597:1597) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (303:303:303) (408:408:408)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (1786:1786:1786) (1751:1751:1751)) - (PORT datad (853:853:853) (843:843:843)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (709:709:709) (720:720:720)) - (PORT clk (1646:1646:1646) (1674:1674:1674)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (701:701:701) (735:735:735)) - (PORT d[1] (1837:1837:1837) (1903:1903:1903)) - (PORT d[2] (1178:1178:1178) (1216:1216:1216)) - (PORT d[3] (3424:3424:3424) (3589:3589:3589)) - (PORT d[4] (2650:2650:2650) (2738:2738:2738)) - (PORT d[5] (924:924:924) (944:944:944)) - (PORT d[6] (2945:2945:2945) (3019:3019:3019)) - (PORT d[7] (2492:2492:2492) (2556:2556:2556)) - (PORT d[8] (922:922:922) (931:931:931)) - (PORT d[9] (2510:2510:2510) (2500:2500:2500)) - (PORT d[10] (951:951:951) (964:964:964)) - (PORT d[11] (2361:2361:2361) (2466:2466:2466)) - (PORT d[12] (1939:1939:1939) (1950:1950:1950)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (848:848:848) (792:792:792)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1674:1674:1674)) - (PORT d[0] (1344:1344:1344) (1299:1299:1299)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1605:1605:1605) (1604:1604:1604)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2021:2021:2021) (2001:2001:2001)) - (PORT clk (1613:1613:1613) (1611:1611:1611)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1748:1748:1748) (1810:1810:1810)) - (PORT d[1] (1827:1827:1827) (1889:1889:1889)) - (PORT d[2] (1751:1751:1751) (1788:1788:1788)) - (PORT d[3] (1848:1848:1848) (1941:1941:1941)) - (PORT d[4] (1807:1807:1807) (1882:1882:1882)) - (PORT d[5] (1724:1724:1724) (1787:1787:1787)) - (PORT d[6] (1673:1673:1673) (1718:1718:1718)) - (PORT d[7] (1736:1736:1736) (1800:1800:1800)) - (PORT d[8] (1760:1760:1760) (1818:1818:1818)) - (PORT d[9] (1748:1748:1748) (1786:1786:1786)) - (PORT d[10] (1762:1762:1762) (1811:1811:1811)) - (PORT d[11] (1898:1898:1898) (1937:1937:1937)) - (PORT d[12] (1742:1742:1742) (1777:1777:1777)) - (PORT clk (1610:1610:1610) (1608:1608:1608)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1611:1611:1611)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1612:1612:1612)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1612:1612:1612)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1612:1612:1612)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1612:1612:1612)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3494:3494:3494) (3650:3650:3650)) - (PORT d[1] (2224:2224:2224) (2340:2340:2340)) - (PORT d[2] (3997:3997:3997) (4105:4105:4105)) - (PORT d[3] (3329:3329:3329) (3524:3524:3524)) - (PORT d[4] (2960:2960:2960) (3062:3062:3062)) - (PORT d[5] (3683:3683:3683) (3833:3833:3833)) - (PORT d[6] (2374:2374:2374) (2404:2404:2404)) - (PORT d[7] (2593:2593:2593) (2611:2611:2611)) - (PORT d[8] (3385:3385:3385) (3496:3496:3496)) - (PORT d[9] (2034:2034:2034) (2039:2039:2039)) - (PORT d[10] (1465:1465:1465) (1486:1486:1486)) - (PORT d[11] (1430:1430:1430) (1465:1465:1465)) - (PORT d[12] (2035:2035:2035) (2021:2021:2021)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1663:1663:1663)) - (PORT d[0] (1199:1199:1199) (1165:1165:1165)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (702:702:702) (720:720:720)) - (PORT d[1] (641:641:641) (642:642:642)) - (PORT d[2] (1480:1480:1480) (1530:1530:1530)) - (PORT d[3] (3701:3701:3701) (3881:3881:3881)) - (PORT d[4] (2623:2623:2623) (2718:2718:2718)) - (PORT d[5] (629:629:629) (640:640:640)) - (PORT d[6] (2984:2984:2984) (3024:3024:3024)) - (PORT d[7] (2443:2443:2443) (2488:2488:2488)) - (PORT d[8] (924:924:924) (919:919:919)) - (PORT d[9] (2432:2432:2432) (2383:2383:2383)) - (PORT d[10] (903:903:903) (902:902:902)) - (PORT d[11] (1356:1356:1356) (1367:1367:1367)) - (PORT d[12] (1625:1625:1625) (1614:1614:1614)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (PORT d[0] (2379:2379:2379) (2361:2361:2361)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (685:685:685) (705:705:705)) - (PORT clk (1646:1646:1646) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1006:1006:1006) (1053:1053:1053)) - (PORT d[1] (1830:1830:1830) (1889:1889:1889)) - (PORT d[2] (1217:1217:1217) (1260:1260:1260)) - (PORT d[3] (3420:3420:3420) (3584:3584:3584)) - (PORT d[4] (2327:2327:2327) (2400:2400:2400)) - (PORT d[5] (908:908:908) (929:929:929)) - (PORT d[6] (841:841:841) (822:822:822)) - (PORT d[7] (2514:2514:2514) (2580:2580:2580)) - (PORT d[8] (1104:1104:1104) (1089:1089:1089)) - (PORT d[9] (2490:2490:2490) (2482:2482:2482)) - (PORT d[10] (1208:1208:1208) (1228:1228:1228)) - (PORT d[11] (2375:2375:2375) (2485:2485:2485)) - (PORT d[12] (1918:1918:1918) (1928:1928:1928)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1086:1086:1086) (1028:1028:1028)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1672:1672:1672)) - (PORT d[0] (2108:2108:2108) (2112:2112:2112)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1605:1605:1605) (1602:1602:1602)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2586:2586:2586) (2557:2557:2557)) - (PORT clk (1613:1613:1613) (1609:1609:1609)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1743:1743:1743) (1798:1798:1798)) - (PORT d[1] (1823:1823:1823) (1885:1885:1885)) - (PORT d[2] (1766:1766:1766) (1804:1804:1804)) - (PORT d[3] (1838:1838:1838) (1944:1944:1944)) - (PORT d[4] (1763:1763:1763) (1759:1759:1759)) - (PORT d[5] (1695:1695:1695) (1754:1754:1754)) - (PORT d[6] (1690:1690:1690) (1728:1728:1728)) - (PORT d[7] (1707:1707:1707) (1767:1767:1767)) - (PORT d[8] (1810:1810:1810) (1880:1880:1880)) - (PORT d[9] (1863:1863:1863) (1887:1887:1887)) - (PORT d[10] (1757:1757:1757) (1801:1801:1801)) - (PORT d[11] (1894:1894:1894) (1933:1933:1933)) - (PORT d[12] (1815:1815:1815) (1811:1811:1811)) - (PORT clk (1610:1610:1610) (1606:1606:1606)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1609:1609:1609)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1610:1610:1610)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1610:1610:1610)) + (PORT clk (1616:1616:1616) (1613:1613:1613)) (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1614:1614:1614) (1610:1610:1610)) + (PORT clk (1616:1616:1616) (1613:1613:1613)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1614:1614:1614) (1610:1610:1610)) + (PORT clk (1616:1616:1616) (1613:1613:1613)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1606:1606:1606) (1603:1603:1603)) + (PORT clk (1608:1608:1608) (1606:1606:1606)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -36098,13 +49793,479 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector6\~0) + (INSTANCE D\[3\]\~72) (DELAY (ABSOLUTE - (PORT dataa (1100:1100:1100) (1104:1104:1104)) - (PORT datab (589:589:589) (574:574:574)) - (PORT datad (880:880:880) (878:878:878)) + (PORT dataa (828:828:828) (850:850:850)) + (PORT datab (189:189:189) (224:224:224)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1365:1365:1365) (1368:1368:1368)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (1483:1483:1483) (1482:1482:1482)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1506:1506:1506) (1523:1523:1523)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (1305:1305:1305) (1292:1292:1292)) + (PORT datac (1230:1230:1230) (1217:1217:1217)) + (PORT datad (316:316:316) (319:319:319)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (1518:1518:1518) (1480:1480:1480)) + (PORT datab (1303:1303:1303) (1289:1289:1289)) + (PORT datac (1032:1032:1032) (1052:1052:1052)) + (PORT datad (298:298:298) (295:295:295)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (946:946:946)) + (PORT datab (1541:1541:1541) (1532:1532:1532)) + (PORT datac (211:211:211) (260:260:260)) + (PORT datad (820:820:820) (816:816:816)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (279:279:279)) + (PORT datab (604:604:604) (646:646:646)) + (PORT datad (194:194:194) (223:223:223)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (908:908:908)) + (PORT datab (837:837:837) (858:858:858)) + (PORT datac (817:817:817) (833:833:833)) + (PORT datad (850:850:850) (853:853:853)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1390:1390:1390) (1361:1361:1361)) + (PORT ena (1363:1363:1363) (1319:1319:1319)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1349:1349:1349) (1408:1408:1408)) + (PORT datab (1083:1083:1083) (1086:1086:1086)) + (PORT datac (1096:1096:1096) (1157:1157:1157)) + (PORT datad (1293:1293:1293) (1285:1285:1285)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (868:868:868)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (821:821:821) (822:822:822)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1294:1294:1294) (1268:1268:1268)) + (PORT datab (581:581:581) (603:603:603)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (524:524:524) (587:587:587)) + (PORT sload (1033:1033:1033) (1049:1049:1049)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (820:820:820)) + (PORT datab (1053:1053:1053) (1083:1083:1083)) + (PORT datac (162:162:162) (196:196:196)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (889:889:889)) + (PORT datab (601:601:601) (626:626:626)) + (PORT datac (1532:1532:1532) (1518:1518:1518)) + (PORT datad (305:305:305) (310:310:310)) (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (1333:1333:1333) (1327:1327:1327)) + (PORT datac (767:767:767) (762:762:762)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (1305:1305:1305) (1307:1307:1307)) + (PORT datab (871:871:871) (918:918:918)) + (PORT datac (894:894:894) (961:961:961)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (370:370:370)) + (PORT datac (162:162:162) (196:196:196)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (441:441:441)) + (PORT datab (209:209:209) (250:250:250)) + (PORT datac (1058:1058:1058) (1046:1046:1046)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (236:236:236)) + (PORT datac (1230:1230:1230) (1219:1219:1219)) + (PORT datad (180:180:180) (202:202:202)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (1040:1040:1040) (1082:1082:1082)) + (PORT datab (1068:1068:1068) (1064:1064:1064)) + (PORT datac (1432:1432:1432) (1391:1391:1391)) + (PORT datad (304:304:304) (309:309:309)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (823:823:823)) + (PORT datab (1439:1439:1439) (1439:1439:1439)) + (PORT datad (166:166:166) (189:189:189)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (895:895:895)) + (PORT datab (1330:1330:1330) (1350:1350:1350)) + (PORT datac (1533:1533:1533) (1516:1516:1516)) + (PORT datad (306:306:306) (314:314:314)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~92) + (DELAY + (ABSOLUTE + (PORT datab (1278:1278:1278) (1232:1232:1232)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (893:893:893)) + (PORT datab (824:824:824) (860:860:860)) + (PORT datac (1532:1532:1532) (1521:1521:1521)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~3) + (DELAY + (ABSOLUTE + (PORT datab (1270:1270:1270) (1359:1359:1359)) + (PORT datac (2167:2167:2167) (2222:2222:2222)) + (PORT datad (516:516:516) (508:508:508)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1378:1378:1378)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1189:1189:1189) (1191:1191:1191)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (220:220:220) (279:279:279)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1217:1217:1217) (1223:1223:1223)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) + (DELAY + (ABSOLUTE + (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT asdata (511:511:511) (578:578:578)) + (PORT clrn (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1217:1217:1217) (1223:1223:1223)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (302:302:302)) + (PORT datab (228:228:228) (299:299:299)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -36113,32 +50274,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~70) + (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (848:848:848) (832:832:832)) - (PORT datab (701:701:701) (739:739:739)) - (PORT datac (960:960:960) (915:915:915)) - (PORT datad (561:561:561) (551:551:551)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (720:720:720) (702:702:702)) - (PORT datab (819:819:819) (825:825:825)) - (PORT datac (1384:1384:1384) (1397:1397:1397)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (850:850:850) (873:873:873)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -36154,29 +50298,218 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (INSTANCE ula_\|i2c_loader_\|divider\[0\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1218:1218:1218) (1272:1272:1272)) - (PORT datab (1168:1168:1168) (1194:1194:1194)) - (PORT datac (770:770:770) (760:760:760)) - (PORT datad (757:757:757) (748:748:748)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (309:309:309)) + (PORT datab (228:228:228) (301:301:301)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[3\]) + (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1371:1371:1371)) + (PORT clk (1683:1683:1683) (1697:1697:1697)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1562:1562:1562) (1529:1529:1529)) + (PORT clrn (1396:1396:1396) (1376:1376:1376)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (306:306:306)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (301:301:301)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (301:301:301)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT datad (205:205:205) (267:267:267)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (306:306:306)) + (PORT datab (229:229:229) (303:303:303)) + (PORT datac (201:201:201) (271:271:271)) + (PORT datad (205:205:205) (266:266:266)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|WideAnd0) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (298:298:298)) + (PORT datac (158:158:158) (188:188:188)) + (PORT datad (204:204:204) (264:264:264)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Idle) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (PORT ena (1273:1273:1273) (1300:1300:1300)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK @@ -36186,56 +50519,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~64) + (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datac (868:868:868) (902:902:902)) - (PORT datad (1032:1032:1032) (1042:1042:1042)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (903:903:903)) - (PORT datab (848:848:848) (873:873:873)) - (PORT datac (753:753:753) (724:724:724)) - (PORT datad (612:612:612) (665:665:665)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (950:950:950)) - (PORT datab (645:645:645) (691:691:691)) - (PORT datac (172:172:172) (212:212:212)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (560:560:560)) - (PORT datad (655:655:655) (707:707:707)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT datad (223:223:223) (282:282:282)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36243,148 +50530,30 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT datab (901:901:901) (935:935:935)) - (PORT datac (1065:1065:1065) (1082:1082:1082)) - (PORT datad (633:633:633) (689:689:689)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1150:1150:1150)) - (PORT datab (432:432:432) (480:480:480)) - (PORT datac (1042:1042:1042) (1056:1056:1056)) - (PORT datad (862:862:862) (884:884:884)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~135) - (DELAY - (ABSOLUTE - (PORT dataa (1040:1040:1040) (1064:1064:1064)) - (PORT datab (1223:1223:1223) (1204:1204:1204)) - (PORT datad (297:297:297) (293:293:293)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (359:359:359)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (PORT ena (1273:1273:1273) (1300:1300:1300)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~55) + (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT dataa (843:843:843) (856:856:856)) - (PORT datab (219:219:219) (287:287:287)) - (PORT datac (802:802:802) (809:809:809)) - (PORT datad (520:520:520) (524:524:524)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (443:443:443) (509:509:509)) - (PORT datac (858:858:858) (883:883:883)) - (PORT datad (539:539:539) (526:526:526)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (755:755:755) (750:750:750)) - (PORT datab (875:875:875) (927:927:927)) - (PORT datac (848:848:848) (862:862:862)) - (PORT datad (538:538:538) (527:527:527)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT datab (291:291:291) (392:392:392)) + (PORT datad (225:225:225) (285:285:285)) (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (923:923:923)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36392,31 +50561,52 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (INSTANCE ula_\|i2c_loader_\|phase\[1\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1378:1378:1378)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (PORT ena (1273:1273:1273) (1300:1300:1300)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) + (INSTANCE ula_\|i2c_loader_\|nbit\~5) (DELAY (ABSOLUTE - (PORT dataa (658:658:658) (711:711:711)) - (PORT datab (837:837:837) (866:866:866)) - (PORT datac (875:875:875) (905:905:905)) - (PORT datad (847:847:847) (892:892:892)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (592:592:592) (633:633:633)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (274:274:274) (356:356:356)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|Mux42\~0) + (DELAY + (ABSOLUTE + (PORT datac (645:645:645) (686:686:686)) + (PORT datad (631:631:631) (667:667:667)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36424,29 +50614,51 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~97) + (INSTANCE ula_\|i2c_loader_\|nbyte\~4) (DELAY (ABSOLUTE - (PORT dataa (874:874:874) (920:920:920)) - (PORT datab (874:874:874) (927:927:927)) - (PORT datad (369:369:369) (423:423:423)) - (IOPATH dataa combout (318:318:318) (307:307:307)) + (PORT dataa (259:259:259) (342:342:342)) + (PORT datab (294:294:294) (395:395:395)) + (PORT datad (591:591:591) (624:624:624)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~99) + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (948:948:948) (931:931:931)) - (PORT datab (1105:1105:1105) (1098:1098:1098)) - (PORT datac (848:848:848) (865:865:865)) - (PORT datad (850:850:850) (892:892:892)) + (PORT datab (261:261:261) (338:338:338)) + (PORT datac (541:541:541) (554:554:554)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE I2C_SDAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (461:461:461) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (341:341:341)) + (PORT datab (246:246:246) (321:321:321)) + (PORT datac (262:262:262) (362:362:362)) + (PORT datad (473:473:473) (454:454:454)) (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36454,14 +50666,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~100) + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (186:186:186) (224:224:224)) - (PORT datab (204:204:204) (239:239:239)) - (PORT datad (181:181:181) (203:203:203)) - (IOPATH dataa combout (287:287:287) (289:289:289)) + (PORT dataa (615:615:615) (661:661:661)) + (PORT datab (608:608:608) (607:607:607)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (783:783:783) (753:753:753)) + (PORT datac (390:390:390) (436:436:436)) + (PORT datad (159:159:159) (179:179:179)) (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (PORT ena (745:745:745) (752:752:752)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (676:676:676)) + (PORT datab (653:653:653) (687:687:687)) + (PORT datac (227:227:227) (300:300:300)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (548:548:548)) + (PORT datab (232:232:232) (282:282:282)) + (PORT datad (318:318:318) (318:318:318)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36469,12 +50743,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1378:1378:1378)) + (PORT clk (1351:1351:1351) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT clrn (1397:1397:1397) (1377:1377:1377)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36485,14 +50759,287 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~54) + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) (DELAY (ABSOLUTE - (PORT dataa (792:792:792) (776:776:776)) - (PORT datab (221:221:221) (289:289:289)) - (PORT datac (193:193:193) (259:259:259)) - (PORT datad (2104:2104:2104) (2063:2063:2063)) + (PORT dataa (263:263:263) (348:348:348)) + (PORT datab (236:236:236) (312:312:312)) + (PORT datac (209:209:209) (285:285:285)) + (PORT datad (530:530:530) (549:549:549)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (633:633:633)) + (PORT datab (243:243:243) (317:317:317)) + (PORT datad (214:214:214) (280:280:280)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (PORT ena (1089:1089:1089) (1068:1068:1068)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (314:314:314)) + (PORT datab (226:226:226) (299:299:299)) + (PORT datac (561:561:561) (597:597:597)) + (PORT datad (216:216:216) (281:281:281)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (357:357:357)) + (PORT datab (345:345:345) (352:352:352)) + (PORT datac (846:846:846) (866:866:866)) + (PORT datad (307:307:307) (310:310:310)) (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (223:223:223)) + (PORT datab (526:526:526) (534:534:534)) + (PORT datad (406:406:406) (459:459:459)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1377:1377:1377)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (342:342:342)) + (PORT datab (245:245:245) (318:318:318)) + (PORT datac (263:263:263) (363:363:363)) + (PORT datad (474:474:474) (451:451:451)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (436:436:436)) + (PORT datab (551:551:551) (569:569:569)) + (PORT datac (792:792:792) (757:757:757)) + (PORT datad (289:289:289) (294:294:294)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (1044:1044:1044) (1030:1030:1030)) + (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT sload (959:959:959) (944:944:944)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (265:265:265) (350:350:350)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (1045:1045:1045) (1032:1032:1032)) + (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT sload (959:959:959) (944:944:944)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (261:261:261) (339:339:339)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT sload (959:959:959) (944:944:944)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (273:273:273) (360:360:360)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (1045:1045:1045) (1032:1032:1032)) + (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT sload (959:959:959) (944:944:944)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (453:453:453)) + (PORT datab (266:266:266) (350:350:350)) + (PORT datac (245:245:245) (323:323:323)) + (PORT datad (248:248:248) (324:324:324)) + (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -36501,59 +51048,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) (DELAY (ABSOLUTE - (PORT dataa (860:860:860) (891:891:891)) - (PORT datab (902:902:902) (920:920:920)) - (PORT datac (874:874:874) (894:894:894)) - (PORT datad (801:801:801) (826:826:826)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (703:703:703)) - (PORT datac (865:865:865) (899:899:899)) - (PORT datad (1030:1030:1030) (1040:1040:1040)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (255:255:255) (334:334:334)) - (PORT datab (887:887:887) (917:917:917)) - (PORT datad (512:512:512) (500:500:500)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~136) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (845:845:845)) - (PORT datab (184:184:184) (218:218:218)) - (PORT datac (859:859:859) (893:893:893)) - (PORT datad (1040:1040:1040) (1047:1047:1047)) - (IOPATH dataa combout (272:272:272) (269:269:269)) + (PORT dataa (660:660:660) (713:713:713)) + (PORT datab (237:237:237) (313:313:313)) + (PORT datac (649:649:649) (690:690:690)) + (PORT datad (234:234:234) (300:300:300)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -36562,31 +51064,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) + (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) (DELAY (ABSOLUTE - (PORT dataa (589:589:589) (596:596:596)) - (PORT datab (535:535:535) (533:533:533)) - (PORT datac (858:858:858) (889:889:889)) - (PORT datad (1038:1038:1038) (1045:1045:1045)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (278:278:278) (369:369:369)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH cin combout (408:408:408) (387:387:387)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~109) + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) (DELAY (ABSOLUTE - (PORT dataa (426:426:426) (484:484:484)) - (PORT datab (532:532:532) (519:519:519)) - (PORT datac (1094:1094:1094) (1110:1110:1110)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT sload (959:959:959) (944:944:944)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT datab (583:583:583) (569:569:569)) + (PORT datac (313:313:313) (323:323:323)) + (PORT datad (612:612:612) (632:632:632)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36594,107 +51110,440 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~137) + (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) (DELAY (ABSOLUTE - (PORT dataa (417:417:417) (467:467:467)) - (PORT datab (640:640:640) (683:683:683)) - (PORT datac (841:841:841) (859:859:859)) - (PORT datad (851:851:851) (885:885:885)) + (PORT dataa (203:203:203) (240:240:240)) + (PORT datab (258:258:258) (335:335:335)) + (PORT datac (208:208:208) (282:282:282)) + (PORT datad (461:461:461) (431:431:431)) (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (330:330:330)) + (PORT datab (234:234:234) (288:288:288)) + (PORT datac (236:236:236) (319:319:319)) + (PORT datad (385:385:385) (435:435:435)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (335:335:335)) + (PORT datab (554:554:554) (543:543:543)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Pause) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1377:1377:1377)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~25) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (315:315:315)) + (PORT datab (235:235:235) (289:289:289)) + (PORT datad (383:383:383) (431:431:431)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Start) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1377:1377:1377)) + (PORT ena (1069:1069:1069) (1069:1069:1069)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~0) + (DELAY + (ABSOLUTE + (PORT datab (290:290:290) (389:389:389)) + (PORT datad (587:587:587) (620:620:620)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (PORT ena (745:745:745) (752:752:752)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (670:670:670)) + (PORT datac (625:625:625) (655:655:655)) + (PORT datad (404:404:404) (459:459:459)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (966:966:966)) + (PORT datab (449:449:449) (502:502:502)) + (PORT datac (229:229:229) (302:302:302)) + (PORT datad (614:614:614) (648:648:648)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (547:547:547) (572:572:572)) + (PORT datad (305:305:305) (307:307:307)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (342:342:342)) + (PORT datab (231:231:231) (283:283:283)) + (PORT datac (522:522:522) (513:513:513)) + (PORT datad (388:388:388) (434:434:434)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (PORT ena (1060:1060:1060) (1026:1026:1026)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (630:630:630)) + (PORT datad (218:218:218) (284:284:284)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (PORT ena (1089:1089:1089) (1068:1068:1068)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (317:317:317)) + (PORT datab (228:228:228) (302:302:302)) + (PORT datad (218:218:218) (284:284:284)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~27) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (707:707:707)) + (PORT datac (646:646:646) (687:687:687)) + (PORT datad (460:460:460) (431:431:431)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (675:675:675)) + (PORT datab (654:654:654) (686:686:686)) + (PORT datac (224:224:224) (296:296:296)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~26) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (712:712:712)) + (PORT datac (647:647:647) (689:689:689)) + (PORT datad (326:326:326) (325:325:325)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (224:224:224)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Data) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (516:516:516) (563:563:563)) + (PORT clrn (1397:1397:1397) (1377:1377:1377)) + (PORT sload (789:789:789) (905:905:905)) + (PORT ena (1069:1069:1069) (1069:1069:1069)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|scl_out\~0) + (DELAY + (ABSOLUTE + (PORT datab (261:261:261) (339:339:339)) + (PORT datac (570:570:570) (586:586:586)) + (PORT datad (209:209:209) (276:276:276)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (528:528:528) (517:517:517)) - (PORT datab (606:606:606) (598:598:598)) - (PORT datad (595:595:595) (600:600:600)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (PORT ena (1273:1273:1273) (1300:1300:1300)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~106) + (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT datab (620:620:620) (657:657:657)) - (PORT datac (612:612:612) (651:651:651)) - (PORT datad (1055:1055:1055) (1054:1054:1054)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (614:614:614) (660:660:660)) + (PORT datab (290:290:290) (387:387:387)) + (PORT datac (232:232:232) (310:310:310)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~107) + (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (617:617:617) (683:683:683)) - (PORT datab (832:832:832) (825:825:825)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (597:597:597) (609:609:609)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datad (586:586:586) (618:618:618)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (INSTANCE ula_\|i2c_loader_\|scl_out) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1377:1377:1377)) + (PORT clk (1306:1306:1306) (1319:1319:1319)) + (PORT d (850:850:850) (915:915:915)) + (PORT aload (1507:1507:1507) (1553:1553:1553)) + (PORT ena (798:798:798) (813:813:813)) + (IOPATH (posedge clk) q (549:549:549) (552:552:552)) + (IOPATH (posedge aload) q (455:455:455) (458:458:458)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (75:75:75)) + (SETUP ena (posedge clk) (75:75:75)) + (HOLD d (posedge clk) (89:89:89)) + (HOLD ena (posedge clk) (89:89:89)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|sda_out\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (PORT ena (1273:1273:1273) (1300:1300:1300)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~56) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (599:599:599) (635:635:635)) - (PORT datab (1771:1771:1771) (1762:1762:1762)) - (PORT datac (814:814:814) (824:824:824)) - (PORT datad (634:634:634) (664:664:664)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT datac (811:811:811) (844:844:844)) + (PORT datad (569:569:569) (594:594:594)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36702,14 +51551,72 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~115) + (INSTANCE ula_\|i2c_loader_\|Mux35\~0) (DELAY (ABSOLUTE - (PORT dataa (1126:1126:1126) (1141:1141:1141)) - (PORT datab (382:382:382) (436:436:436)) - (PORT datac (856:856:856) (887:887:887)) - (PORT datad (1037:1037:1037) (1042:1042:1042)) - (IOPATH dataa combout (272:272:272) (269:269:269)) + (PORT dataa (412:412:412) (464:464:464)) + (PORT datab (422:422:422) (464:464:464)) + (PORT datac (364:364:364) (401:401:401)) + (PORT datad (365:365:365) (408:408:408)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (277:277:277) (366:366:366)) + (PORT datab (266:266:266) (347:347:347)) + (PORT datac (246:246:246) (327:327:327)) + (PORT datad (235:235:235) (302:302:302)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) + (DELAY + (ABSOLUTE + (PORT datac (248:248:248) (333:333:333)) + (PORT datad (236:236:236) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (224:224:224)) + (PORT datab (274:274:274) (361:361:361)) + (PORT datac (246:246:246) (329:329:329)) + (PORT datad (180:180:180) (203:203:203)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (421:421:421) (464:464:464)) + (PORT datac (814:814:814) (846:846:846)) + (PORT datad (387:387:387) (428:428:428)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -36718,1573 +51625,139 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~116) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (608:608:608)) - (PORT datab (328:328:328) (337:337:337)) - (PORT datac (227:227:227) (302:302:302)) - (PORT datad (790:790:790) (799:799:799)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~139) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (499:499:499)) - (PORT datab (633:633:633) (635:635:635)) - (PORT datad (401:401:401) (448:448:448)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (895:895:895)) - (PORT datab (896:896:896) (917:917:917)) - (PORT datac (366:366:366) (422:422:422)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~140) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (665:665:665)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datad (328:328:328) (334:334:334)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) - (DELAY - (ABSOLUTE - (PORT datab (890:890:890) (924:924:924)) - (PORT datac (570:570:570) (611:611:611)) - (PORT datad (616:616:616) (651:651:651)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT datab (597:597:597) (629:629:629)) - (PORT datad (575:575:575) (613:613:613)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (1124:1124:1124) (1142:1142:1142)) - (PORT datab (741:741:741) (721:721:721)) - (PORT datac (562:562:562) (565:565:565)) - (PORT datad (572:572:572) (570:570:570)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) - (DELAY - (ABSOLUTE - (PORT dataa (429:429:429) (483:483:483)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (227:227:227) (301:301:301)) - (PORT datad (594:594:594) (597:597:597)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (234:234:234)) - (PORT datad (159:159:159) (181:181:181)) + (PORT dataa (658:658:658) (710:710:710)) + (PORT datac (646:646:646) (690:690:690)) + (PORT datad (235:235:235) (304:304:304)) (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (406:406:406)) - (PORT datab (351:351:351) (402:402:402)) - (PORT datac (618:618:618) (640:640:640)) - (PORT datad (1208:1208:1208) (1198:1198:1198)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (520:520:520) (524:524:524)) - (PORT datab (795:795:795) (788:788:788)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (557:557:557) (554:554:554)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1572:1572:1572) (1587:1587:1587)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2919:2919:2919) (3051:3051:3051)) - (PORT d[1] (1933:1933:1933) (2042:2042:2042)) - (PORT d[2] (2127:2127:2127) (2249:2249:2249)) - (PORT d[3] (2466:2466:2466) (2621:2621:2621)) - (PORT d[4] (2369:2369:2369) (2436:2436:2436)) - (PORT d[5] (3125:3125:3125) (3245:3245:3245)) - (PORT d[6] (2129:2129:2129) (2180:2180:2180)) - (PORT d[7] (3198:3198:3198) (3247:3247:3247)) - (PORT d[8] (2024:2024:2024) (2076:2076:2076)) - (PORT d[9] (2340:2340:2340) (2340:2340:2340)) - (PORT d[10] (1831:1831:1831) (1899:1899:1899)) - (PORT d[11] (1736:1736:1736) (1805:1805:1805)) - (PORT d[12] (2609:2609:2609) (2628:2628:2628)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2345:2345:2345) (2278:2278:2278)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (2585:2585:2585) (2558:2558:2558)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2078:2078:2078) (2067:2067:2067)) - (PORT clk (1641:1641:1641) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3213:3213:3213) (3356:3356:3356)) - (PORT d[1] (2171:2171:2171) (2264:2264:2264)) - (PORT d[2] (3198:3198:3198) (3303:3303:3303)) - (PORT d[3] (2760:2760:2760) (2922:2922:2922)) - (PORT d[4] (2384:2384:2384) (2463:2463:2463)) - (PORT d[5] (3077:3077:3077) (3193:3193:3193)) - (PORT d[6] (1546:1546:1546) (1523:1523:1523)) - (PORT d[7] (3145:3145:3145) (3190:3190:3190)) - (PORT d[8] (2051:2051:2051) (2123:2123:2123)) - (PORT d[9] (2858:2858:2858) (2895:2895:2895)) - (PORT d[10] (2134:2134:2134) (2213:2213:2213)) - (PORT d[11] (1760:1760:1760) (1821:1821:1821)) - (PORT d[12] (2337:2337:2337) (2346:2346:2346)) - (PORT clk (1638:1638:1638) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2046:2046:2046) (1966:1966:1966)) - (PORT clk (1638:1638:1638) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (PORT d[0] (2717:2717:2717) (2731:2731:2731)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1605:1605:1605) (1633:1633:1633)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (877:877:877) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (877:877:877) (881:881:881)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (877:877:877) (881:881:881)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2163:2163:2163) (2186:2186:2186)) - (PORT clk (1645:1645:1645) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2611:2611:2611) (2725:2725:2725)) - (PORT d[1] (1635:1635:1635) (1729:1729:1729)) - (PORT d[2] (2421:2421:2421) (2525:2525:2525)) - (PORT d[3] (2135:2135:2135) (2252:2252:2252)) - (PORT d[4] (2089:2089:2089) (2131:2131:2131)) - (PORT d[5] (2543:2543:2543) (2627:2627:2627)) - (PORT d[6] (1839:1839:1839) (1872:1872:1872)) - (PORT d[7] (4016:4016:4016) (4084:4084:4084)) - (PORT d[8] (2263:2263:2263) (2331:2331:2331)) - (PORT d[9] (2636:2636:2636) (2647:2647:2647)) - (PORT d[10] (1808:1808:1808) (1865:1865:1865)) - (PORT d[11] (1758:1758:1758) (1812:1812:1812)) - (PORT d[12] (3145:3145:3145) (3178:3178:3178)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2275:2275:2275) (2224:2224:2224)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (PORT d[0] (2613:2613:2613) (2587:2587:2587)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2165:2165:2165) (2189:2189:2189)) - (PORT clk (1633:1633:1633) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3490:3490:3490) (3642:3642:3642)) - (PORT d[1] (1961:1961:1961) (2064:2064:2064)) - (PORT d[2] (3740:3740:3740) (3846:3846:3846)) - (PORT d[3] (3049:3049:3049) (3227:3227:3227)) - (PORT d[4] (2967:2967:2967) (3059:3059:3059)) - (PORT d[5] (3695:3695:3695) (3839:3839:3839)) - (PORT d[6] (1569:1569:1569) (1558:1558:1558)) - (PORT d[7] (2573:2573:2573) (2591:2591:2591)) - (PORT d[8] (2582:2582:2582) (2651:2651:2651)) - (PORT d[9] (1832:1832:1832) (1821:1821:1821)) - (PORT d[10] (1476:1476:1476) (1512:1512:1512)) - (PORT d[11] (1432:1432:1432) (1461:1461:1461)) - (PORT d[12] (2068:2068:2068) (2063:2063:2063)) - (PORT clk (1630:1630:1630) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2467:2467:2467) (2460:2460:2460)) - (PORT clk (1630:1630:1630) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1662:1662:1662)) - (PORT d[0] (2547:2547:2547) (2577:2577:2577)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1597:1597:1597) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (308:308:308) (417:417:417)) - (PORT datab (1666:1666:1666) (1678:1678:1678)) - (PORT datac (1068:1068:1068) (1104:1104:1104)) - (PORT datad (834:834:834) (830:830:830)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1523:1523:1523) (1500:1500:1500)) - (PORT datab (878:878:878) (905:905:905)) - (PORT datac (1530:1530:1530) (1500:1500:1500)) - (PORT datad (960:960:960) (943:943:943)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (653:653:653) (676:676:676)) - (PORT clk (1646:1646:1646) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1021:1021:1021) (1080:1080:1080)) - (PORT d[1] (1544:1544:1544) (1594:1594:1594)) - (PORT d[2] (1462:1462:1462) (1517:1517:1517)) - (PORT d[3] (3114:3114:3114) (3275:3275:3275)) - (PORT d[4] (1813:1813:1813) (1893:1893:1893)) - (PORT d[5] (1157:1157:1157) (1176:1176:1176)) - (PORT d[6] (2681:2681:2681) (2741:2741:2741)) - (PORT d[7] (2459:2459:2459) (2504:2504:2504)) - (PORT d[8] (1237:1237:1237) (1265:1265:1265)) - (PORT d[9] (2740:2740:2740) (2731:2731:2731)) - (PORT d[10] (1222:1222:1222) (1251:1251:1251)) - (PORT d[11] (3814:3814:3814) (3899:3899:3899)) - (PORT d[12] (2248:2248:2248) (2275:2275:2275)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1621:1621:1621) (1583:1583:1583)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1672:1672:1672)) - (PORT d[0] (2129:2129:2129) (2117:2117:2117)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1605:1605:1605) (1602:1602:1602)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2588:2588:2588) (2565:2565:2565)) - (PORT clk (1613:1613:1613) (1609:1609:1609)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1737:1737:1737) (1783:1783:1783)) - (PORT d[1] (1791:1791:1791) (1834:1834:1834)) - (PORT d[2] (1735:1735:1735) (1756:1756:1756)) - (PORT d[3] (1791:1791:1791) (1900:1900:1900)) - (PORT d[4] (1782:1782:1782) (1826:1826:1826)) - (PORT d[5] (1711:1711:1711) (1756:1756:1756)) - (PORT d[6] (1747:1747:1747) (1822:1822:1822)) - (PORT d[7] (1699:1699:1699) (1738:1738:1738)) - (PORT d[8] (1842:1842:1842) (1916:1916:1916)) - (PORT d[9] (1858:1858:1858) (1880:1880:1880)) - (PORT d[10] (1772:1772:1772) (1816:1816:1816)) - (PORT d[11] (1876:1876:1876) (1905:1905:1905)) - (PORT d[12] (1720:1720:1720) (1759:1759:1759)) - (PORT clk (1610:1610:1610) (1606:1606:1606)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1609:1609:1609)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1610:1610:1610)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1610:1610:1610)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1610:1610:1610)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1610:1610:1610)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (998:998:998) (1010:1010:1010)) - (PORT d[1] (906:906:906) (918:918:918)) - (PORT d[2] (1490:1490:1490) (1544:1544:1544)) - (PORT d[3] (3681:3681:3681) (3869:3869:3869)) - (PORT d[4] (2632:2632:2632) (2719:2719:2719)) - (PORT d[5] (917:917:917) (920:920:920)) - (PORT d[6] (2981:2981:2981) (3055:3055:3055)) - (PORT d[7] (1080:1080:1080) (1039:1039:1039)) - (PORT d[8] (639:639:639) (639:639:639)) - (PORT d[9] (2212:2212:2212) (2177:2177:2177)) - (PORT d[10] (913:913:913) (922:922:922)) - (PORT d[11] (1086:1086:1086) (1070:1070:1070)) - (PORT d[12] (2163:2163:2163) (2144:2144:2144)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (PORT d[0] (2361:2361:2361) (2380:2380:2380)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1637:1637:1637)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (719:719:719) (756:756:756)) - (PORT d[1] (1838:1838:1838) (1904:1904:1904)) - (PORT d[2] (1478:1478:1478) (1522:1522:1522)) - (PORT d[3] (3401:3401:3401) (3579:3579:3579)) - (PORT d[4] (2636:2636:2636) (2730:2730:2730)) - (PORT d[5] (925:925:925) (942:942:942)) - (PORT d[6] (2948:2948:2948) (3011:3011:3011)) - (PORT d[7] (2199:2199:2199) (2259:2259:2259)) - (PORT d[8] (935:935:935) (933:933:933)) - (PORT d[9] (2477:2477:2477) (2454:2454:2454)) - (PORT d[10] (925:925:925) (935:935:935)) - (PORT d[11] (1094:1094:1094) (1082:1082:1082)) - (PORT d[12] (1957:1957:1957) (1963:1963:1963)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1672:1672:1672)) - (PORT d[0] (729:729:729) (765:765:765)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1638:1638:1638)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1448:1448:1448) (1495:1495:1495)) - (PORT clk (1656:1656:1656) (1683:1683:1683)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2781:2781:2781) (2838:2838:2838)) - (PORT d[1] (1294:1294:1294) (1348:1348:1348)) - (PORT d[2] (3111:3111:3111) (3274:3274:3274)) - (PORT d[3] (2454:2454:2454) (2562:2562:2562)) - (PORT d[4] (2452:2452:2452) (2531:2531:2531)) - (PORT d[5] (1938:1938:1938) (1990:1990:1990)) - (PORT d[6] (2161:2161:2161) (2202:2202:2202)) - (PORT d[7] (2721:2721:2721) (2799:2799:2799)) - (PORT d[8] (2776:2776:2776) (2845:2845:2845)) - (PORT d[9] (3269:3269:3269) (3260:3260:3260)) - (PORT d[10] (2371:2371:2371) (2462:2462:2462)) - (PORT d[11] (2844:2844:2844) (2918:2918:2918)) - (PORT d[12] (3101:3101:3101) (3162:3162:3162)) - (PORT clk (1653:1653:1653) (1681:1681:1681)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1875:1875:1875) (1853:1853:1853)) - (PORT clk (1653:1653:1653) (1681:1681:1681)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1656:1656:1656) (1683:1683:1683)) - (PORT d[0] (2898:2898:2898) (2890:2890:2890)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1657:1657:1657) (1684:1684:1684)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1657:1657:1657) (1684:1684:1684)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1657:1657:1657) (1684:1684:1684)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1657:1657:1657) (1684:1684:1684)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1615:1615:1615) (1613:1613:1613)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3905:3905:3905) (3874:3874:3874)) - (PORT clk (1623:1623:1623) (1620:1620:1620)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1707:1707:1707) (1713:1713:1713)) - (PORT d[1] (1772:1772:1772) (1840:1840:1840)) - (PORT d[2] (1658:1658:1658) (1664:1664:1664)) - (PORT d[3] (1781:1781:1781) (1873:1873:1873)) - (PORT d[4] (1713:1713:1713) (1740:1740:1740)) - (PORT d[5] (1920:1920:1920) (1956:1956:1956)) - (PORT d[6] (1803:1803:1803) (1800:1800:1800)) - (PORT d[7] (1716:1716:1716) (1743:1743:1743)) - (PORT d[8] (1918:1918:1918) (1932:1932:1932)) - (PORT d[9] (1823:1823:1823) (1814:1814:1814)) - (PORT d[10] (1970:1970:1970) (2007:2007:2007)) - (PORT d[11] (1936:1936:1936) (1991:1991:1991)) - (PORT d[12] (1907:1907:1907) (1937:1937:1937)) - (PORT clk (1620:1620:1620) (1617:1617:1617)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1623:1623:1623) (1620:1620:1620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1624:1624:1624) (1621:1621:1621)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1624:1624:1624) (1621:1621:1621)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1624:1624:1624) (1621:1621:1621)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1624:1624:1624) (1621:1621:1621)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1616:1616:1616) (1614:1614:1614)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (363:363:363)) - (PORT datab (617:617:617) (641:641:641)) - (PORT datac (929:929:929) (980:980:980)) - (PORT datad (1333:1333:1333) (1348:1348:1348)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (831:831:831)) - (PORT datab (957:957:957) (1007:1007:1007)) - (PORT datac (603:603:603) (603:603:603)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1327:1327:1327) (1333:1333:1333)) - (PORT datab (211:211:211) (251:251:251)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (2254:2254:2254) (2345:2345:2345)) - (PORT datab (1415:1415:1415) (1418:1418:1418)) - (PORT datac (2789:2789:2789) (2905:2905:2905)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (729:729:729)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (186:186:186) (227:227:227)) - (PORT datad (506:506:506) (493:493:493)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1394:1394:1394) (1402:1402:1402)) - (PORT datab (1557:1557:1557) (1572:1572:1572)) - (PORT datac (173:173:173) (204:204:204)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|always0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1945:1945:1945) (1891:1891:1891)) - (PORT datab (2817:2817:2817) (2930:2930:2930)) - (PORT datac (2043:2043:2043) (2092:2092:2092)) + (PORT dataa (266:266:266) (352:352:352)) + (PORT datab (231:231:231) (281:281:281)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (329:329:329) (327:327:327)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|always0\~1) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) (DELAY (ABSOLUTE - (PORT dataa (2252:2252:2252) (2340:2340:2340)) - (PORT datab (1418:1418:1418) (1425:1425:1425)) - (PORT datac (2788:2788:2788) (2900:2900:2900)) - (PORT datad (157:157:157) (178:178:178)) + (PORT datab (410:410:410) (470:470:470)) + (PORT datac (523:523:523) (517:517:517)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT sclr (1021:1021:1021) (1080:1080:1080)) + (PORT ena (1279:1279:1279) (1235:1235:1235)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (276:276:276) (365:365:365)) + (PORT datab (272:272:272) (355:355:355)) + (PORT datac (246:246:246) (327:327:327)) + (PORT datad (234:234:234) (302:302:302)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (358:358:358)) + (PORT datab (349:349:349) (357:357:357)) + (PORT datac (364:364:364) (400:400:400)) + (PORT datad (391:391:391) (431:431:431)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (298:298:298)) + (PORT datac (817:817:817) (848:848:848)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (692:692:692)) + (PORT datab (445:445:445) (501:501:501)) + (PORT datac (545:545:545) (575:575:575)) + (PORT datad (180:180:180) (202:202:202)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (963:963:963)) + (PORT datab (525:525:525) (530:530:530)) + (PORT datac (847:847:847) (866:866:866)) + (PORT datad (160:160:160) (181:181:181)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -38294,13 +51767,15 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[13\]) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (735:735:735) (734:734:734)) + (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT ena (1112:1112:1112) (1084:1084:1084)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK @@ -38308,6 +51783,371 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (275:275:275) (366:366:366)) + (PORT datab (270:270:270) (356:356:356)) + (PORT datac (242:242:242) (322:322:322)) + (PORT datad (238:238:238) (311:311:311)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (466:466:466)) + (PORT datab (388:388:388) (440:440:440)) + (PORT datac (286:286:286) (299:299:299)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (300:300:300)) + (PORT datac (811:811:811) (842:842:842)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT ena (1112:1112:1112) (1084:1084:1084)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (450:450:450)) + (PORT datab (266:266:266) (347:347:347)) + (PORT datac (248:248:248) (332:332:332)) + (PORT datad (247:247:247) (319:319:319)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (470:470:470)) + (PORT datab (419:419:419) (462:462:462)) + (PORT datac (467:467:467) (451:451:451)) + (PORT datad (326:326:326) (334:334:334)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (630:630:630)) + (PORT datab (222:222:222) (291:291:291)) + (PORT datac (812:812:812) (843:843:843)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT ena (1112:1112:1112) (1084:1084:1084)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (626:626:626) (663:663:663)) + (PORT datac (571:571:571) (592:592:592)) + (PORT datad (340:340:340) (371:371:371)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT ena (1301:1301:1301) (1268:1268:1268)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (499:499:499)) + (PORT datab (451:451:451) (499:499:499)) + (PORT datad (334:334:334) (372:372:372)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1377:1377:1377)) + (PORT sload (1099:1099:1099) (1160:1160:1160)) + (PORT ena (735:735:735) (734:734:734)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) + (DELAY + (ABSOLUTE + (PORT datab (592:592:592) (640:640:640)) + (PORT datac (816:816:816) (848:848:848)) + (PORT datad (181:181:181) (203:203:203)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT sclr (1021:1021:1021) (1080:1080:1080)) + (PORT ena (1112:1112:1112) (1084:1084:1084)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (811:811:811) (843:843:843)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1379:1379:1379)) + (PORT sclr (1021:1021:1021) (1080:1080:1080)) + (PORT ena (1279:1279:1279) (1235:1235:1235)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|sda_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (669:669:669)) + (PORT datab (384:384:384) (437:437:437)) + (PORT datac (523:523:523) (541:541:541)) + (PORT datad (357:357:357) (391:391:391)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|sda_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (497:497:497)) + (PORT datab (286:286:286) (385:385:385)) + (PORT datac (324:324:324) (326:326:326)) + (PORT datad (473:473:473) (451:451:451)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|sda_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (308:308:308)) + (PORT datab (288:288:288) (386:386:386)) + (PORT datac (232:232:232) (308:308:308)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|sda_out\~3) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (312:312:312)) + (PORT datab (286:286:286) (382:382:382)) + (PORT datac (233:233:233) (308:308:308)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|sda_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (657:657:657)) + (PORT datab (746:746:746) (747:747:747)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|sda_out) + (DELAY + (ABSOLUTE + (PORT clk (1307:1307:1307) (1321:1321:1321)) + (PORT d (612:612:612) (666:666:666)) + (PORT aload (1521:1521:1521) (1568:1568:1568)) + (PORT ena (1129:1129:1129) (1199:1199:1199)) + (IOPATH (posedge clk) q (549:549:549) (552:552:552)) + (IOPATH (posedge aload) q (455:455:455) (458:458:458)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (75:75:75)) + (SETUP ena (posedge clk) (75:75:75)) + (HOLD d (posedge clk) (89:89:89)) + (HOLD ena (posedge clk) (89:89:89)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|mclk_r\~0) @@ -38322,9 +52162,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1670:1670:1670) (1690:1690:1690)) + (PORT clk (1675:1675:1675) (1695:1695:1695)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1389:1389:1389) (1370:1370:1370)) + (PORT clrn (1392:1392:1392) (1374:1374:1374)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -38333,12 +52173,29 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|mclk_r) + (DELAY + (ABSOLUTE + (PORT clk (1332:1332:1332) (1349:1349:1349)) + (PORT d (2140:2140:2140) (2106:2106:2106)) + (PORT clrn (1565:1565:1565) (1601:1601:1601)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT dataa (654:654:654) (700:700:700)) + (PORT dataa (636:636:636) (678:678:678)) (IOPATH dataa cout (376:376:376) (275:275:275)) ) ) @@ -38348,7 +52205,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (229:229:229) (303:303:303)) + (PORT datab (228:228:228) (301:301:301)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -38362,10 +52219,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT datac (182:182:182) (218:218:218)) - (PORT datad (162:162:162) (184:184:184)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (209:209:209) (250:250:250)) + (PORT datac (158:158:158) (190:190:190)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -38374,9 +52231,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1670:1670:1670) (1692:1692:1692)) + (PORT clk (1674:1674:1674) (1694:1694:1694)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1372:1372:1372)) + (PORT clrn (1391:1391:1391) (1373:1373:1373)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -38390,7 +52247,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (406:406:406) (443:443:443)) + (PORT dataa (370:370:370) (423:423:423)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -38404,8 +52261,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datac (282:282:282) (296:296:296)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datad (304:304:304) (309:309:309)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -38414,9 +52271,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1670:1670:1670) (1692:1692:1692)) + (PORT clk (1674:1674:1674) (1694:1694:1694)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1372:1372:1372)) + (PORT clrn (1391:1391:1391) (1373:1373:1373)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -38430,7 +52287,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (363:363:363) (414:414:414)) + (PORT datab (365:365:365) (408:408:408)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -38444,8 +52301,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datad (552:552:552) (538:538:538)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (324:324:324) (326:326:326)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -38454,9 +52311,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1670:1670:1670) (1692:1692:1692)) + (PORT clk (1674:1674:1674) (1695:1695:1695)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1372:1372:1372)) + (PORT clrn (1392:1392:1392) (1374:1374:1374)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -38470,7 +52327,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (228:228:228) (299:299:299)) + (PORT datab (227:227:227) (301:301:301)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -38484,8 +52341,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (249:249:249)) - (PORT datac (157:157:157) (188:188:188)) + (PORT dataa (211:211:211) (254:254:254)) + (PORT datac (156:156:156) (185:185:185)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (220:220:220) (216:216:216)) ) @@ -38496,9 +52353,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1670:1670:1670) (1692:1692:1692)) + (PORT clk (1674:1674:1674) (1694:1694:1694)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1372:1372:1372)) + (PORT clrn (1391:1391:1391) (1373:1373:1373)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -38512,9 +52369,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (415:415:415)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (229:229:229) (301:301:301)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -38526,8 +52383,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datac (296:296:296) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -38536,9 +52393,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1670:1670:1670) (1691:1691:1691)) + (PORT clk (1674:1674:1674) (1694:1694:1694)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1389:1389:1389) (1371:1371:1371)) + (PORT clrn (1391:1391:1391) (1373:1373:1373)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -38547,12 +52404,28 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (424:424:424)) + (PORT datab (228:228:228) (302:302:302)) + (PORT datac (340:340:340) (382:382:382)) + (PORT datad (205:205:205) (268:268:268)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (368:368:368) (418:418:418)) + (PORT dataa (396:396:396) (438:438:438)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -38566,8 +52439,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datac (323:323:323) (329:329:329)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datad (316:316:316) (315:315:315)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -38576,9 +52449,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1670:1670:1670) (1691:1691:1691)) + (PORT clk (1674:1674:1674) (1695:1695:1695)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1389:1389:1389) (1371:1371:1371)) + (PORT clrn (1392:1392:1392) (1374:1374:1374)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -38592,7 +52465,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (393:393:393) (435:435:435)) + (PORT dataa (411:411:411) (446:446:446)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -38606,8 +52479,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datac (324:324:324) (326:326:326)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datad (309:309:309) (315:315:315)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -38616,9 +52489,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1670:1670:1670) (1691:1691:1691)) + (PORT clk (1674:1674:1674) (1694:1694:1694)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1389:1389:1389) (1371:1371:1371)) + (PORT clrn (1391:1391:1391) (1373:1373:1373)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -38632,9 +52505,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~16) (DELAY (ABSOLUTE - (PORT datab (633:633:633) (656:656:656)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (371:371:371) (416:416:416)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -38646,10 +52519,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datac (528:528:528) (526:526:526)) - (PORT datad (530:530:530) (516:516:516)) + (PORT datab (353:353:353) (353:353:353)) + (PORT datac (357:357:357) (365:365:365)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -38658,9 +52531,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1682:1682:1682) (1701:1701:1701)) + (PORT clk (1674:1674:1674) (1695:1695:1695)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT clrn (1392:1392:1392) (1374:1374:1374)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -38674,7 +52547,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (205:205:205) (267:267:267)) + (PORT datad (353:353:353) (394:394:394)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -38685,7 +52558,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datad (160:160:160) (181:181:181)) + (PORT datad (314:314:314) (314:314:314)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -38695,9 +52568,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1670:1670:1670) (1692:1692:1692)) + (PORT clk (1674:1674:1674) (1695:1695:1695)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1372:1372:1372)) + (PORT clrn (1392:1392:1392) (1374:1374:1374)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -38711,29 +52584,13 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (415:415:415)) - (PORT datab (227:227:227) (297:297:297)) - (PORT datac (355:355:355) (400:400:400)) - (PORT datad (592:592:592) (618:618:618)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (447:447:447)) - (PORT datab (357:357:357) (409:409:409)) - (PORT datac (342:342:342) (381:381:381)) - (PORT datad (202:202:202) (262:262:262)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (372:372:372) (418:418:418)) + (PORT datab (394:394:394) (432:432:432)) + (PORT datac (361:361:361) (405:405:405)) + (PORT datad (361:361:361) (398:398:398)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -38743,10 +52600,10 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) + (PORT dataa (182:182:182) (219:219:219)) (PORT datab (225:225:225) (297:297:297)) - (PORT datac (614:614:614) (662:662:662)) - (PORT datad (295:295:295) (295:295:295)) + (PORT datac (606:606:606) (644:644:644)) + (PORT datad (162:162:162) (183:183:183)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -38754,6 +52611,78 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) + (DELAY + (ABSOLUTE + (PORT datad (180:180:180) (203:203:203)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) + (DELAY + (ABSOLUTE + (PORT datab (826:826:826) (840:840:840)) + (PORT datad (213:213:213) (274:274:274)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrclk_r) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (2112:2112:2112) (2168:2168:2168)) + (PORT clrn (1563:1563:1563) (1599:1599:1599)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1348:1348:1348)) + (PORT d (2331:2331:2331) (2378:2378:2378)) + (PORT clrn (1564:1564:1564) (1600:1600:1600)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) @@ -38765,336 +52694,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (309:309:309)) - (PORT datab (229:229:229) (302:302:302)) - (PORT datac (202:202:202) (273:273:273)) - (PORT datad (205:205:205) (267:267:267)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) - (DELAY - (ABSOLUTE - (PORT datab (247:247:247) (326:326:326)) - (PORT datac (220:220:220) (290:290:290)) - (PORT datad (185:185:185) (208:208:208)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~7) - (DELAY - (ABSOLUTE - (PORT datab (246:246:246) (331:331:331)) - (IOPATH datab cout (385:385:385) (280:280:280)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~8) - (DELAY - (ABSOLUTE - (PORT datab (227:227:227) (301:301:301)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~20) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (328:328:328)) - (PORT datab (245:245:245) (331:331:331)) - (PORT datac (1381:1381:1381) (1403:1403:1403)) - (PORT datad (190:190:190) (221:221:221)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1681:1681:1681) (1701:1701:1701)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1401:1401:1401) (1381:1381:1381)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (305:305:305)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~17) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (382:382:382)) - (PORT datab (184:184:184) (217:217:217)) - (PORT datac (188:188:188) (227:227:227)) - (PORT datad (1385:1385:1385) (1403:1403:1403)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1681:1681:1681) (1701:1701:1701)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1401:1401:1401) (1381:1381:1381)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (305:305:305)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~19) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (333:333:333)) - (PORT datab (246:246:246) (329:329:329)) - (PORT datac (1381:1381:1381) (1406:1406:1406)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1681:1681:1681) (1701:1701:1701)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1401:1401:1401) (1381:1381:1381)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~14) - (DELAY - (ABSOLUTE - (PORT datad (206:206:206) (267:267:267)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~16) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (382:382:382)) - (PORT datab (1407:1407:1407) (1432:1432:1432)) - (PORT datac (188:188:188) (227:227:227)) - (PORT datad (289:289:289) (294:294:294)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1681:1681:1681) (1701:1701:1701)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1401:1401:1401) (1381:1381:1381)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (302:302:302)) - (PORT datab (229:229:229) (302:302:302)) - (PORT datac (204:204:204) (276:276:276)) - (PORT datad (205:205:205) (265:265:265)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (429:429:429)) - (PORT datab (244:244:244) (330:330:330)) - (PORT datac (515:515:515) (499:499:499)) - (PORT datad (182:182:182) (213:213:213)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1450:1450:1450)) - (PORT datab (217:217:217) (257:257:257)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1681:1681:1681) (1701:1701:1701)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1401:1401:1401) (1381:1381:1381)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT datab (248:248:248) (335:335:335)) - (PORT datad (185:185:185) (213:213:213)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (369:369:369) (377:377:377)) - (PORT datac (220:220:220) (301:301:301)) - (PORT datad (1166:1166:1166) (1193:1193:1193)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) - (DELAY - (ABSOLUTE - (PORT datad (531:531:531) (513:513:513)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT clk (1348:1348:1348) (1365:1365:1365)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1401:1401:1401) (1381:1381:1381)) + (PORT clrn (1394:1394:1394) (1375:1375:1375)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39108,11 +52715,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1189:1189:1189) (1230:1230:1230)) - (PORT datac (221:221:221) (302:302:302)) - (PORT datad (345:345:345) (348:348:348)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (208:208:208) (255:255:255)) + (PORT datac (805:805:805) (797:797:797)) + (PORT datad (220:220:220) (284:284:284)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -39122,11 +52729,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT clk (1348:1348:1348) (1365:1365:1365)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (655:655:655) (660:660:660)) - (PORT clrn (1401:1401:1401) (1381:1381:1381)) - (PORT sload (1717:1717:1717) (1786:1786:1786)) + (PORT asdata (2512:2512:2512) (2492:2492:2492)) + (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (PORT sload (1349:1349:1349) (1372:1372:1372)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -39158,11 +52765,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT clk (1348:1348:1348) (1365:1365:1365)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (654:654:654) (659:659:659)) - (PORT clrn (1401:1401:1401) (1381:1381:1381)) - (PORT sload (1717:1717:1717) (1786:1786:1786)) + (PORT asdata (2511:2511:2511) (2491:2491:2491)) + (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (PORT sload (1349:1349:1349) (1372:1372:1372)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -39194,11 +52801,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT clk (1348:1348:1348) (1365:1365:1365)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (654:654:654) (659:659:659)) - (PORT clrn (1401:1401:1401) (1381:1381:1381)) - (PORT sload (1717:1717:1717) (1786:1786:1786)) + (PORT asdata (2510:2510:2510) (2491:2491:2491)) + (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (PORT sload (1349:1349:1349) (1372:1372:1372)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -39216,7 +52823,7 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (229:229:229) (307:307:307)) + (PORT dataa (230:230:230) (307:307:307)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -39230,11 +52837,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT clk (1348:1348:1348) (1365:1365:1365)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (653:653:653) (658:658:658)) - (PORT clrn (1401:1401:1401) (1381:1381:1381)) - (PORT sload (1717:1717:1717) (1786:1786:1786)) + (PORT asdata (2510:2510:2510) (2490:2490:2490)) + (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (PORT sload (1349:1349:1349) (1372:1372:1372)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -39247,12 +52854,28 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (306:306:306)) + (PORT datab (229:229:229) (302:302:302)) + (PORT datac (201:201:201) (272:272:272)) + (PORT datad (205:205:205) (267:267:267)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) (DELAY (ABSOLUTE - (PORT datab (247:247:247) (319:319:319)) + (PORT datab (241:241:241) (318:318:318)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -39263,11 +52886,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT clk (1348:1348:1348) (1365:1365:1365)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (652:652:652) (658:658:658)) - (PORT clrn (1401:1401:1401) (1381:1381:1381)) - (PORT sload (1717:1717:1717) (1786:1786:1786)) + (PORT asdata (2509:2509:2509) (2490:2490:2490)) + (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (PORT sload (1349:1349:1349) (1372:1372:1372)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -39280,18 +52903,386 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (427:427:427) (477:477:477)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (308:308:308)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~20) + (DELAY + (ABSOLUTE + (PORT dataa (429:429:429) (479:479:479)) + (PORT datab (826:826:826) (840:840:840)) + (PORT datac (184:184:184) (220:220:220)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (418:418:418)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~17) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (259:259:259)) + (PORT datab (208:208:208) (257:257:257)) + (PORT datac (805:805:805) (799:799:799)) + (PORT datad (315:315:315) (317:317:317)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~19) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (479:479:479)) + (PORT datab (827:827:827) (841:841:841)) + (PORT datac (185:185:185) (221:221:221)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT datad (336:336:336) (373:373:373)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (260:260:260)) + (PORT datab (208:208:208) (260:260:260)) + (PORT datac (805:805:805) (800:800:800)) + (PORT datad (316:316:316) (317:317:317)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (309:309:309)) + (PORT datab (229:229:229) (303:303:303)) + (PORT datac (345:345:345) (385:385:385)) + (PORT datad (335:335:335) (371:371:371)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (315:315:315)) + (PORT datab (195:195:195) (237:237:237)) + (PORT datac (215:215:215) (292:292:292)) + (PORT datad (350:350:350) (354:354:354)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (831:831:831)) + (PORT datab (208:208:208) (258:258:258)) + (PORT datad (352:352:352) (355:355:355)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datac (358:358:358) (401:401:401)) + (PORT datad (348:348:348) (351:351:351)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) + (DELAY + (ABSOLUTE + (PORT datab (195:195:195) (237:237:237)) + (PORT datac (213:213:213) (291:291:291)) + (PORT datad (217:217:217) (281:281:281)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (258:258:258)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (799:799:799) (786:786:786)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bclk_r) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1347:1347:1347)) + (PORT d (2095:2095:2095) (2177:2177:2177)) + (PORT clrn (1562:1562:1562) (1599:1599:1599)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outl\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (795:795:795) (814:814:814)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1662:1662:1662)) + (PORT datab (1477:1477:1477) (1531:1531:1531)) + (PORT datac (1100:1100:1100) (1115:1115:1115)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|always0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (680:680:680)) + (PORT datab (1157:1157:1157) (1194:1194:1194)) + (PORT datac (1107:1107:1107) (1125:1125:1125)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1849:1849:1849) (1846:1846:1846)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (388:388:388) (438:438:438)) - (PORT datab (250:250:250) (333:333:333)) - (PORT datac (342:342:342) (351:351:351)) - (PORT datad (184:184:184) (208:208:208)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (206:206:206) (254:254:254)) + (PORT datab (194:194:194) (234:234:234)) + (PORT datac (215:215:215) (292:292:292)) + (PORT datad (219:219:219) (283:283:283)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -39310,9 +53301,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (366:366:366)) - (PORT datab (1285:1285:1285) (1358:1358:1358)) - (PORT datad (708:708:708) (680:680:680)) + (PORT dataa (1260:1260:1260) (1257:1257:1257)) + (PORT datab (1218:1218:1218) (1254:1254:1254)) + (PORT datad (705:705:705) (672:672:672)) (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -39325,9 +53316,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1653:1653:1653) (1663:1663:1663)) + (PORT clk (1658:1658:1658) (1671:1671:1671)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39341,23 +53332,23 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT datac (1253:1253:1253) (1328:1328:1328)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (223:223:223) (291:291:291)) + (PORT datad (1171:1171:1171) (1205:1205:1205)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]\~2) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~2) (DELAY (ABSOLUTE - (PORT dataa (1191:1191:1191) (1231:1231:1231)) - (PORT datac (220:220:220) (302:302:302)) - (PORT datad (346:346:346) (350:350:350)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (207:207:207) (255:255:255)) + (PORT datac (805:805:805) (796:796:796)) + (PORT datad (220:220:220) (284:284:284)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -39367,10 +53358,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) - (PORT ena (1103:1103:1103) (1083:1083:1083)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39385,9 +53376,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (1256:1256:1256) (1334:1334:1334)) - (PORT datad (201:201:201) (258:258:258)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datac (196:196:196) (263:263:263)) + (PORT datad (1171:1171:1171) (1213:1213:1213)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -39397,10 +53388,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) - (PORT ena (1103:1103:1103) (1083:1083:1083)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39415,9 +53406,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datac (1256:1256:1256) (1332:1332:1332)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (223:223:223) (293:293:293)) + (PORT datad (1179:1179:1179) (1213:1213:1213)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -39427,10 +53418,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) - (PORT ena (1103:1103:1103) (1083:1083:1083)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39445,9 +53436,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datac (1256:1256:1256) (1331:1331:1331)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (224:224:224) (294:294:294)) + (PORT datad (1188:1188:1188) (1224:1224:1224)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -39457,10 +53448,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) - (PORT ena (1103:1103:1103) (1083:1083:1083)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39475,10 +53466,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (224:224:224) (298:298:298)) - (PORT datac (1255:1255:1255) (1335:1335:1335)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (223:223:223) (293:293:293)) + (PORT datad (1187:1187:1187) (1223:1223:1223)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -39487,10 +53478,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) - (PORT ena (1103:1103:1103) (1083:1083:1083)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39505,9 +53496,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT datac (1257:1257:1257) (1335:1335:1335)) - (PORT datad (200:200:200) (257:257:257)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (225:225:225) (298:298:298)) + (PORT datad (1181:1181:1181) (1219:1219:1219)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -39517,10 +53508,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) - (PORT ena (1103:1103:1103) (1083:1083:1083)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39536,9 +53527,9 @@ (DELAY (ABSOLUTE (PORT datab (223:223:223) (292:292:292)) - (PORT datac (1256:1256:1256) (1336:1336:1336)) + (PORT datad (1168:1168:1168) (1206:1206:1206)) (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -39547,10 +53538,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) - (PORT ena (1103:1103:1103) (1083:1083:1083)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39565,9 +53556,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datac (1254:1254:1254) (1331:1331:1331)) - (PORT datad (200:200:200) (258:258:258)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datac (195:195:195) (262:262:262)) + (PORT datad (1169:1169:1169) (1206:1206:1206)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -39577,10 +53568,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) - (PORT ena (1103:1103:1103) (1083:1083:1083)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39595,9 +53586,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datac (1250:1250:1250) (1330:1330:1330)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (223:223:223) (292:292:292)) + (PORT datad (1170:1170:1170) (1215:1215:1215)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -39607,10 +53598,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) - (PORT ena (1103:1103:1103) (1083:1083:1083)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39625,10 +53616,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datab (225:225:225) (295:295:295)) - (PORT datac (1257:1257:1257) (1332:1332:1332)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datac (198:198:198) (265:265:265)) + (PORT datad (1186:1186:1186) (1225:1225:1225)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -39637,10 +53628,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) - (PORT ena (1103:1103:1103) (1083:1083:1083)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39655,10 +53646,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT dataa (226:226:226) (300:300:300)) - (PORT datac (1256:1256:1256) (1330:1330:1330)) + (PORT dataa (224:224:224) (297:297:297)) + (PORT datad (1188:1188:1188) (1223:1223:1223)) (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -39667,10 +53658,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) - (PORT ena (1103:1103:1103) (1083:1083:1083)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39685,9 +53676,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) (DELAY (ABSOLUTE - (PORT datac (1255:1255:1255) (1335:1335:1335)) - (PORT datad (200:200:200) (256:256:256)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (223:223:223) (292:292:292)) + (PORT datad (1185:1185:1185) (1226:1226:1226)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -39697,10 +53688,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) - (PORT ena (1103:1103:1103) (1083:1083:1083)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39710,54 +53701,16 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) - (DELAY - (ABSOLUTE - (PORT datab (1069:1069:1069) (1085:1085:1085)) - (PORT datad (222:222:222) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT datad (502:502:502) (490:490:490)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (783:783:783) (807:807:807)) - (PORT datab (1075:1075:1075) (1091:1091:1091)) - (PORT datad (353:353:353) (397:397:397)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (1297:1297:1297) (1331:1331:1331)) + (PORT datab (821:821:821) (835:835:835)) + (PORT datad (212:212:212) (272:272:272)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -39768,9 +53721,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1368:1368:1368)) + (PORT clk (1347:1347:1347) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (PORT clrn (1393:1393:1393) (1374:1374:1374)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39781,11 +53734,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ula_data\~0) + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) (DELAY (ABSOLUTE - (PORT datac (818:818:818) (836:836:836)) - (PORT datad (639:639:639) (690:690:690)) + (PORT dataa (1296:1296:1296) (1330:1330:1330)) + (PORT datab (821:821:821) (835:835:835)) + (PORT datad (212:212:212) (272:272:272)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outr\~0) + (DELAY + (ABSOLUTE + (PORT datac (198:198:198) (266:266:266)) + (PORT datad (200:200:200) (258:258:258)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -39796,9 +53780,9 @@ (INSTANCE ula_\|pcm_outl\[12\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1379:1379:1379)) + (PORT clk (1349:1349:1349) (1365:1365:1365)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1365:1365:1365) (1315:1315:1315)) + (PORT ena (1939:1939:1939) (1935:1935:1935)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -39812,12 +53796,12 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (298:298:298)) - (PORT datab (1830:1830:1830) (1871:1871:1871)) - (PORT datac (1258:1258:1258) (1335:1335:1335)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT datab (1224:1224:1224) (1262:1262:1262)) + (PORT datac (197:197:197) (264:264:264)) + (PORT datad (1242:1242:1242) (1258:1258:1258)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -39826,10 +53810,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1381:1381:1381)) - (PORT ena (1103:1103:1103) (1083:1083:1083)) + (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39844,12 +53828,12 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT dataa (676:676:676) (720:720:720)) - (PORT datab (1077:1077:1077) (1093:1093:1093)) - (PORT datac (2004:2004:2004) (2033:2033:2033)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (1134:1134:1134) (1192:1192:1192)) + (PORT datac (196:196:196) (262:262:262)) + (PORT datad (1187:1187:1187) (1227:1227:1227)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -39858,2362 +53842,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) (DELAY (ABSOLUTE - (PORT clk (1651:1651:1651) (1661:1661:1661)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (PORT ena (2545:2545:2545) (2516:2516:2516)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (430:430:430)) - (PORT datab (1078:1078:1078) (1093:1093:1093)) - (PORT datad (223:223:223) (283:283:283)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (774:774:774)) - (PORT datab (1414:1414:1414) (1425:1425:1425)) - (PORT datac (213:213:213) (280:280:280)) - (PORT datad (216:216:216) (273:273:273)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (3007:3007:3007) (3083:3083:3083)) - (PORT datab (783:783:783) (764:764:764)) - (PORT datac (156:156:156) (185:185:185)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (2115:2115:2115) (2166:2166:2166)) - (PORT datab (1072:1072:1072) (1108:1108:1108)) - (PORT datac (535:535:535) (557:557:557)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (682:682:682)) - (PORT datab (347:347:347) (357:357:357)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (1218:1218:1218) (1265:1265:1265)) - (PORT datab (1164:1164:1164) (1188:1188:1188)) - (PORT datac (766:766:766) (747:747:747)) - (PORT datad (197:197:197) (219:219:219)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1562:1562:1562) (1529:1529:1529)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1134:1134:1134) (1176:1176:1176)) - (PORT datac (570:570:570) (582:582:582)) - (PORT datad (952:952:952) (932:932:932)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (654:654:654)) - (PORT datab (845:845:845) (867:867:867)) - (PORT datac (570:570:570) (581:581:581)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1752:1752:1752) (1674:1674:1674)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1301:1301:1301)) - (PORT datab (1206:1206:1206) (1220:1220:1220)) - (PORT datad (264:264:264) (344:344:344)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1041:1041:1041)) - (PORT datab (1033:1033:1033) (1026:1026:1026)) - (PORT datac (1241:1241:1241) (1247:1247:1247)) - (PORT datad (1317:1317:1317) (1372:1372:1372)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (250:250:250)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (1250:1250:1250) (1237:1237:1237)) - (PORT datad (176:176:176) (206:206:206)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1239:1239:1239) (1213:1213:1213)) - (PORT datab (990:990:990) (943:943:943)) - (PORT datac (952:952:952) (910:910:910)) - (PORT datad (1009:1009:1009) (996:996:996)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1006:1006:1006) (1019:1019:1019)) - (PORT datab (212:212:212) (252:252:252)) - (PORT datad (573:573:573) (575:575:575)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (1247:1247:1247) (1229:1229:1229)) - (PORT datac (1472:1472:1472) (1459:1459:1459)) - (PORT datad (524:524:524) (524:524:524)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (660:660:660)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (760:760:760) (750:750:750)) - (PORT datad (588:588:588) (606:606:606)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (778:778:778)) - (PORT datab (667:667:667) (715:715:715)) - (PORT datac (1475:1475:1475) (1458:1458:1458)) - (PORT datad (591:591:591) (606:606:606)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (978:978:978) (967:967:967)) - (PORT datab (1010:1010:1010) (992:992:992)) - (PORT datac (802:802:802) (789:789:789)) - (PORT datad (196:196:196) (227:227:227)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (771:771:771) (753:753:753)) - (PORT datab (616:616:616) (619:619:619)) - (PORT datac (1175:1175:1175) (1138:1138:1138)) - (PORT datad (607:607:607) (623:623:623)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (258:258:258)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (166:166:166) (192:192:192)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1172:1172:1172)) - (PORT datac (303:303:303) (318:318:318)) - (PORT datad (947:947:947) (930:930:930)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (668:668:668)) - (PORT datac (881:881:881) (913:913:913)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (220:220:220)) - (PORT datab (190:190:190) (227:227:227)) - (PORT datad (652:652:652) (701:701:701)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1379:1379:1379)) + (PORT clk (1687:1687:1687) (1708:1708:1708)) (PORT d (67:67:67) (78:78:78)) (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1126:1126:1126)) - (PORT datab (917:917:917) (943:943:943)) - (PORT datac (224:224:224) (297:297:297)) - (PORT datad (583:583:583) (610:610:610)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1111:1111:1111)) - (PORT datab (605:605:605) (634:634:634)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (635:635:635)) - (PORT datab (643:643:643) (697:697:697)) - (PORT datad (302:302:302) (312:312:312)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (337:337:337)) - (PORT datab (900:900:900) (932:932:932)) - (PORT datad (307:307:307) (308:308:308)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (828:828:828)) - (PORT datab (1733:1733:1733) (1708:1708:1708)) - (PORT datac (194:194:194) (259:259:259)) - (PORT datad (507:507:507) (522:522:522)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT datab (614:614:614) (649:649:649)) - (PORT datac (612:612:612) (650:650:650)) - (PORT datad (1058:1058:1058) (1055:1055:1055)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (650:650:650)) - (PORT datab (896:896:896) (909:909:909)) - (PORT datac (506:506:506) (501:501:501)) - (PORT datad (504:504:504) (493:493:493)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT datac (1064:1064:1064) (1095:1095:1095)) - (PORT datad (408:408:408) (455:455:455)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (243:243:243)) - (PORT datab (690:690:690) (740:740:740)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (651:651:651)) - (PORT datac (506:506:506) (504:504:504)) - (PORT datad (856:856:856) (876:876:876)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT datab (445:445:445) (494:494:494)) - (PORT datac (1066:1066:1066) (1097:1097:1097)) - (PORT datad (503:503:503) (495:495:495)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (222:222:222)) - (PORT datab (690:690:690) (738:738:738)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (836:836:836)) - (PORT datab (219:219:219) (287:287:287)) - (PORT datac (194:194:194) (260:260:260)) - (PORT datad (800:800:800) (816:816:816)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (952:952:952)) - (PORT datab (209:209:209) (248:248:248)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (566:566:566)) - (PORT datad (649:649:649) (699:699:699)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT datab (1136:1136:1136) (1157:1157:1157)) - (PORT datac (884:884:884) (915:915:915)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (366:366:366)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datad (654:654:654) (706:706:706)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (993:993:993)) - (PORT datab (219:219:219) (287:287:287)) - (PORT datac (1702:1702:1702) (1685:1685:1685)) - (PORT datad (199:199:199) (257:257:257)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (563:563:563)) - (PORT datab (1070:1070:1070) (1078:1078:1078)) - (PORT datac (864:864:864) (895:895:895)) - (PORT datad (878:878:878) (913:913:913)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (237:237:237)) - (PORT datab (779:779:779) (749:749:749)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (616:616:616) (659:659:659)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (624:624:624)) - (PORT datab (345:345:345) (352:352:352)) - (PORT datac (256:256:256) (341:341:341)) - (PORT datad (593:593:593) (624:624:624)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (222:222:222)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~68) - (DELAY - (ABSOLUTE - (PORT datab (391:391:391) (455:455:455)) - (PORT datac (636:636:636) (694:694:694)) - (PORT datad (684:684:684) (742:742:742)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (779:779:779)) - (PORT datab (904:904:904) (927:927:927)) - (PORT datac (872:872:872) (894:894:894)) - (PORT datad (804:804:804) (832:832:832)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT datac (833:833:833) (865:865:865)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (733:733:733)) - (PORT datab (190:190:190) (226:226:226)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (670:670:670)) - (PORT datab (790:790:790) (790:790:790)) - (PORT datac (570:570:570) (591:591:591)) - (PORT datad (848:848:848) (861:861:861)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (354:354:354) (354:354:354)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (714:714:714) (703:703:703)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (796:796:796)) - (PORT datab (3061:3061:3061) (3159:3159:3159)) - (PORT datac (1120:1120:1120) (1129:1129:1129)) - (PORT datad (649:649:649) (683:683:683)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2680:2680:2680) (2697:2697:2697)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3473:3473:3473) (3627:3627:3627)) - (PORT d[1] (2214:2214:2214) (2331:2331:2331)) - (PORT d[2] (4008:4008:4008) (4108:4108:4108)) - (PORT d[3] (3031:3031:3031) (3215:3215:3215)) - (PORT d[4] (2977:2977:2977) (3077:3077:3077)) - (PORT d[5] (3687:3687:3687) (3839:3839:3839)) - (PORT d[6] (1855:1855:1855) (1832:1832:1832)) - (PORT d[7] (2593:2593:2593) (2612:2612:2612)) - (PORT d[8] (2586:2586:2586) (2666:2666:2666)) - (PORT d[9] (2045:2045:2045) (2041:2041:2041)) - (PORT d[10] (1453:1453:1453) (1485:1485:1485)) - (PORT d[11] (1430:1430:1430) (1467:1467:1467)) - (PORT d[12] (2067:2067:2067) (2062:2062:2062)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2206:2206:2206) (2214:2214:2214)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (2544:2544:2544) (2572:2572:2572)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2422:2422:2422) (2431:2431:2431)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3246:3246:3246) (3387:3387:3387)) - (PORT d[1] (1973:1973:1973) (2088:2088:2088)) - (PORT d[2] (3717:3717:3717) (3804:3804:3804)) - (PORT d[3] (2743:2743:2743) (2909:2909:2909)) - (PORT d[4] (2660:2660:2660) (2761:2761:2761)) - (PORT d[5] (3404:3404:3404) (3539:3539:3539)) - (PORT d[6] (2382:2382:2382) (2437:2437:2437)) - (PORT d[7] (2924:2924:2924) (2963:2963:2963)) - (PORT d[8] (2053:2053:2053) (2127:2127:2127)) - (PORT d[9] (2385:2385:2385) (2405:2405:2405)) - (PORT d[10] (2410:2410:2410) (2501:2501:2501)) - (PORT d[11] (1598:1598:1598) (1632:1632:1632)) - (PORT d[12] (2330:2330:2330) (2337:2337:2337)) - (PORT clk (1639:1639:1639) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1803:1803:1803) (1734:1734:1734)) - (PORT clk (1639:1639:1639) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (PORT d[0] (2439:2439:2439) (2442:2442:2442)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (877:877:877) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (416:416:416)) - (PORT datab (845:845:845) (840:840:840)) - (PORT datac (1065:1065:1065) (1099:1099:1099)) - (PORT datad (1078:1078:1078) (1074:1074:1074)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1870:1870:1870) (1877:1877:1877)) - (PORT clk (1636:1636:1636) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2934:2934:2934) (3065:3065:3065)) - (PORT d[1] (1953:1953:1953) (2063:2063:2063)) - (PORT d[2] (2157:2157:2157) (2273:2273:2273)) - (PORT d[3] (2485:2485:2485) (2635:2635:2635)) - (PORT d[4] (2075:2075:2075) (2143:2143:2143)) - (PORT d[5] (3114:3114:3114) (3234:3234:3234)) - (PORT d[6] (2124:2124:2124) (2173:2173:2173)) - (PORT d[7] (3412:3412:3412) (3457:3457:3457)) - (PORT d[8] (2016:2016:2016) (2073:2073:2073)) - (PORT d[9] (2602:2602:2602) (2629:2629:2629)) - (PORT d[10] (1835:1835:1835) (1905:1905:1905)) - (PORT d[11] (1739:1739:1739) (1811:1811:1811)) - (PORT d[12] (2614:2614:2614) (2636:2636:2636)) - (PORT clk (1633:1633:1633) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2811:2811:2811) (2777:2777:2777)) - (PORT clk (1633:1633:1633) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1664:1664:1664)) - (PORT d[0] (3151:3151:3151) (3135:3135:3135)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1600:1600:1600) (1628:1628:1628)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (875:875:875)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (876:876:876)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (876:876:876)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2140:2140:2140) (2150:2150:2150)) - (PORT clk (1642:1642:1642) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3225:3225:3225) (3364:3364:3364)) - (PORT d[1] (2181:2181:2181) (2275:2275:2275)) - (PORT d[2] (3467:3467:3467) (3568:3568:3568)) - (PORT d[3] (2761:2761:2761) (2923:2923:2923)) - (PORT d[4] (2364:2364:2364) (2443:2443:2443)) - (PORT d[5] (3390:3390:3390) (3521:3521:3521)) - (PORT d[6] (1566:1566:1566) (1527:1527:1527)) - (PORT d[7] (3137:3137:3137) (3172:3172:3172)) - (PORT d[8] (2052:2052:2052) (2126:2126:2126)) - (PORT d[9] (2375:2375:2375) (2380:2380:2380)) - (PORT d[10] (2114:2114:2114) (2193:2193:2193)) - (PORT d[11] (1755:1755:1755) (1820:1820:1820)) - (PORT d[12] (2336:2336:2336) (2345:2345:2345)) - (PORT clk (1639:1639:1639) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1613:1613:1613) (1567:1567:1567)) - (PORT clk (1639:1639:1639) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1669:1669:1669)) - (PORT d[0] (2844:2844:2844) (2822:2822:2822)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1633:1633:1633)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (877:877:877) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (303:303:303) (411:411:411)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (1359:1359:1359) (1386:1386:1386)) - (PORT datad (1093:1093:1093) (1094:1094:1094)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (933:933:933) (946:946:946)) - (PORT clk (1646:1646:1646) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1217:1217:1217) (1247:1247:1247)) - (PORT d[1] (1843:1843:1843) (1890:1890:1890)) - (PORT d[2] (1465:1465:1465) (1524:1524:1524)) - (PORT d[3] (3403:3403:3403) (3577:3577:3577)) - (PORT d[4] (2689:2689:2689) (2794:2794:2794)) - (PORT d[5] (1168:1168:1168) (1166:1166:1166)) - (PORT d[6] (1042:1042:1042) (1003:1003:1003)) - (PORT d[7] (2487:2487:2487) (2545:2545:2545)) - (PORT d[8] (1206:1206:1206) (1223:1223:1223)) - (PORT d[9] (4322:4322:4322) (4343:4343:4343)) - (PORT d[10] (1215:1215:1215) (1242:1242:1242)) - (PORT d[11] (3844:3844:3844) (3930:3930:3930)) - (PORT d[12] (2453:2453:2453) (2456:2456:2456)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1601:1601:1601) (1568:1568:1568)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1672:1672:1672)) - (PORT d[0] (2115:2115:2115) (2103:2103:2103)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1605:1605:1605) (1602:1602:1602)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2568:2568:2568) (2549:2549:2549)) - (PORT clk (1613:1613:1613) (1609:1609:1609)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1737:1737:1737) (1783:1783:1783)) - (PORT d[1] (1727:1727:1727) (1773:1773:1773)) - (PORT d[2] (1756:1756:1756) (1797:1797:1797)) - (PORT d[3] (1861:1861:1861) (1971:1971:1971)) - (PORT d[4] (1787:1787:1787) (1782:1782:1782)) - (PORT d[5] (1718:1718:1718) (1776:1776:1776)) - (PORT d[6] (1655:1655:1655) (1691:1691:1691)) - (PORT d[7] (1727:1727:1727) (1782:1782:1782)) - (PORT d[8] (1816:1816:1816) (1887:1887:1887)) - (PORT d[9] (1883:1883:1883) (1908:1908:1908)) - (PORT d[10] (1744:1744:1744) (1779:1779:1779)) - (PORT d[11] (1865:1865:1865) (1891:1891:1891)) - (PORT d[12] (1924:1924:1924) (1946:1946:1946)) - (PORT clk (1610:1610:1610) (1606:1606:1606)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1609:1609:1609)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1610:1610:1610)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1610:1610:1610)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1610:1610:1610)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1610:1610:1610)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (686:686:686) (704:704:704)) - (PORT d[1] (3105:3105:3105) (3272:3272:3272)) - (PORT d[2] (1504:1504:1504) (1569:1569:1569)) - (PORT d[3] (3661:3661:3661) (3847:3847:3847)) - (PORT d[4] (2902:2902:2902) (2997:2997:2997)) - (PORT d[5] (1144:1144:1144) (1143:1143:1143)) - (PORT d[6] (3018:3018:3018) (3063:3063:3063)) - (PORT d[7] (2462:2462:2462) (2509:2509:2509)) - (PORT d[8] (939:939:939) (948:948:948)) - (PORT d[9] (2538:2538:2538) (2537:2537:2537)) - (PORT d[10] (1145:1145:1145) (1132:1132:1132)) - (PORT d[11] (1368:1368:1368) (1377:1377:1377)) - (PORT d[12] (1931:1931:1931) (1935:1935:1935)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (PORT d[0] (986:986:986) (1020:1020:1020)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (925:925:925) (954:954:954)) - (PORT clk (1644:1644:1644) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1291:1291:1291) (1358:1358:1358)) - (PORT d[1] (1538:1538:1538) (1585:1585:1585)) - (PORT d[2] (3403:3403:3403) (3594:3594:3594)) - (PORT d[3] (3135:3135:3135) (3286:3286:3286)) - (PORT d[4] (2102:2102:2102) (2161:2161:2161)) - (PORT d[5] (1211:1211:1211) (1235:1235:1235)) - (PORT d[6] (1105:1105:1105) (1105:1105:1105)) - (PORT d[7] (2481:2481:2481) (2533:2533:2533)) - (PORT d[8] (1372:1372:1372) (1386:1386:1386)) - (PORT d[9] (2752:2752:2752) (2749:2749:2749)) - (PORT d[10] (1809:1809:1809) (1843:1843:1843)) - (PORT d[11] (2472:2472:2472) (2558:2558:2558)) - (PORT d[12] (2211:2211:2211) (2236:2236:2236)) - (PORT clk (1641:1641:1641) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1403:1403:1403) (1355:1355:1355)) - (PORT clk (1641:1641:1641) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (PORT d[0] (1846:1846:1846) (1864:1864:1864)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1601:1601:1601)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2861:2861:2861) (2834:2834:2834)) - (PORT clk (1611:1611:1611) (1608:1608:1608)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1731:1731:1731) (1801:1801:1801)) - (PORT d[1] (1707:1707:1707) (1750:1750:1750)) - (PORT d[2] (1702:1702:1702) (1755:1755:1755)) - (PORT d[3] (1697:1697:1697) (1741:1741:1741)) - (PORT d[4] (1743:1743:1743) (1790:1790:1790)) - (PORT d[5] (1656:1656:1656) (1707:1707:1707)) - (PORT d[6] (1680:1680:1680) (1752:1752:1752)) - (PORT d[7] (1710:1710:1710) (1756:1756:1756)) - (PORT d[8] (1770:1770:1770) (1808:1808:1808)) - (PORT d[9] (1741:1741:1741) (1781:1781:1781)) - (PORT d[10] (1738:1738:1738) (1781:1781:1781)) - (PORT d[11] (1846:1846:1846) (1875:1875:1875)) - (PORT d[12] (1716:1716:1716) (1754:1754:1754)) - (PORT clk (1608:1608:1608) (1605:1605:1605)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1612:1612:1612) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1612:1612:1612) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1612:1612:1612) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1612:1612:1612) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1602:1602:1602)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (846:846:846)) - (PORT datab (1136:1136:1136) (1130:1130:1130)) - (PORT datac (235:235:235) (319:319:319)) - (PORT datad (1083:1083:1083) (1088:1088:1088)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (682:682:682) (711:711:711)) - (PORT d[1] (2870:2870:2870) (3031:3031:3031)) - (PORT d[2] (2026:2026:2026) (2084:2084:2084)) - (PORT d[3] (932:932:932) (969:969:969)) - (PORT d[4] (3142:3142:3142) (3249:3249:3249)) - (PORT d[5] (1199:1199:1199) (1214:1214:1214)) - (PORT d[6] (2682:2682:2682) (2711:2711:2711)) - (PORT d[7] (2165:2165:2165) (2204:2204:2204)) - (PORT d[8] (3712:3712:3712) (3835:3835:3835)) - (PORT d[9] (2816:2816:2816) (2825:2825:2825)) - (PORT d[10] (2656:2656:2656) (2746:2746:2746)) - (PORT d[11] (2085:2085:2085) (2189:2189:2189)) - (PORT d[12] (2226:2226:2226) (2242:2242:2242)) - (PORT clk (1631:1631:1631) (1661:1661:1661)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1661:1661:1661)) - (PORT d[0] (2083:2083:2083) (2087:2087:2087)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1662:1662:1662)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1627:1627:1627)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (875:875:875)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (875:875:875)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (875:875:875)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (452:452:452)) - (PORT datab (1124:1124:1124) (1112:1112:1112)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1059:1059:1059) (1054:1054:1054)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (897:897:897)) - (PORT datab (896:896:896) (899:899:899)) - (PORT datac (953:953:953) (927:927:927)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1705:1705:1705) (1714:1714:1714)) - (PORT datab (3048:3048:3048) (3112:3112:3112)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (1952:1952:1952) (2019:2019:2019)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1142:1142:1142)) - (PORT datab (1101:1101:1101) (1142:1142:1142)) - (PORT datac (1078:1078:1078) (1086:1086:1086)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (584:584:584)) - (PORT datac (616:616:616) (645:645:645)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (1222:1222:1222) (1276:1276:1276)) - (PORT datab (1174:1174:1174) (1202:1202:1202)) - (PORT datac (183:183:183) (217:217:217)) - (PORT datad (763:763:763) (754:754:754)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1562:1562:1562) (1529:1529:1529)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (601:601:601) (610:610:610)) - (PORT datac (1068:1068:1068) (1069:1069:1069)) - (PORT datad (596:596:596) (613:613:613)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1752:1752:1752) (1674:1674:1674)) + (PORT ena (1950:1950:1950) (1961:1961:1961)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -42223,11390 +53855,14 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1499:1499:1499) (1513:1513:1513)) - (PORT datad (1474:1474:1474) (1476:1476:1476)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1111:1111:1111)) - (PORT datab (2443:2443:2443) (2429:2429:2429)) - (PORT datac (778:778:778) (759:759:759)) - (PORT datad (1747:1747:1747) (1723:1723:1723)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) - (DELAY - (ABSOLUTE - (PORT dataa (518:518:518) (515:515:515)) - (PORT datab (1658:1658:1658) (1688:1688:1688)) - (PORT datac (845:845:845) (860:860:860)) - (PORT datad (846:846:846) (852:852:852)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1374:1374:1374)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1367:1367:1367)) - (PORT ena (1421:1421:1421) (1410:1410:1410)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (399:399:399) (447:447:447)) - (PORT datab (1021:1021:1021) (1023:1023:1023)) - (PORT datac (572:572:572) (604:604:604)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1237:1237:1237) (1244:1244:1244)) - (PORT datab (565:565:565) (588:588:588)) - (PORT datac (1351:1351:1351) (1344:1344:1344)) - (PORT datad (872:872:872) (888:888:888)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (829:829:829) (860:860:860)) - (PORT datab (1035:1035:1035) (998:998:998)) - (PORT datac (920:920:920) (881:881:881)) - (PORT datad (972:972:972) (930:930:930)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (867:867:867)) - (PORT datab (194:194:194) (232:232:232)) - (PORT datac (969:969:969) (943:943:943)) - (PORT datad (976:976:976) (941:941:941)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) - (DELAY - (ABSOLUTE - (PORT datab (607:607:607) (620:620:620)) - (PORT datad (547:547:547) (550:550:550)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (655:655:655)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (1023:1023:1023) (997:997:997)) - (PORT datac (673:673:673) (656:656:656)) - (PORT datad (949:949:949) (933:933:933)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (948:948:948) (918:918:918)) - (PORT datac (520:520:520) (518:518:518)) - (PORT datad (739:739:739) (715:715:715)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (777:777:777)) - (PORT datab (902:902:902) (922:922:922)) - (PORT datac (832:832:832) (861:861:861)) - (PORT datad (802:802:802) (828:828:828)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datab (904:904:904) (922:922:922)) - (PORT datac (713:713:713) (702:702:702)) - (PORT datad (685:685:685) (744:744:744)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT datab (190:190:190) (228:228:228)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (467:467:467)) - (PORT datac (631:631:631) (679:679:679)) - (PORT datad (850:850:850) (887:887:887)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (709:709:709)) - (PORT datab (1016:1016:1016) (1040:1040:1040)) - (PORT datac (876:876:876) (904:904:904)) - (PORT datad (813:813:813) (832:832:832)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (223:223:223)) - (PORT datab (189:189:189) (227:227:227)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (426:426:426)) - (PORT datab (1331:1331:1331) (1328:1328:1328)) - (PORT datac (785:785:785) (800:800:800)) - (PORT datad (198:198:198) (254:254:254)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (673:673:673)) - (PORT datab (359:359:359) (363:363:363)) - (PORT datad (419:419:419) (475:475:475)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (671:671:671)) - (PORT datab (523:523:523) (510:510:510)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (402:402:402)) - (PORT datab (838:838:838) (852:852:852)) - (PORT datac (194:194:194) (260:260:260)) - (PORT datad (749:749:749) (740:740:740)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~134) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1139:1139:1139)) - (PORT datab (889:889:889) (919:919:919)) - (PORT datad (513:513:513) (502:502:502)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT datac (820:820:820) (842:842:842)) - (PORT datad (617:617:617) (653:653:653)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (701:701:701)) - (PORT datab (322:322:322) (330:330:330)) - (PORT datac (170:170:170) (209:209:209)) - (PORT datad (876:876:876) (910:910:910)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (467:467:467)) - (PORT datab (312:312:312) (332:332:332)) - (PORT datac (473:473:473) (463:463:463)) - (PORT datad (576:576:576) (580:580:580)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (643:643:643)) - (PORT datad (296:296:296) (295:295:295)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datab (1137:1137:1137) (1157:1157:1157)) - (PORT datac (879:879:879) (910:910:910)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1152:1152:1152)) - (PORT datab (618:618:618) (646:646:646)) - (PORT datac (588:588:588) (635:635:635)) - (PORT datad (552:552:552) (569:569:569)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (879:879:879)) - (PORT datab (558:558:558) (547:547:547)) - (PORT datac (165:165:165) (201:201:201)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datad (650:650:650) (704:704:704)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (439:439:439)) - (PORT datab (799:799:799) (802:802:802)) - (PORT datac (596:596:596) (624:624:624)) - (PORT datad (1029:1029:1029) (1007:1007:1007)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1014:1014:1014) (1030:1030:1030)) - (PORT datab (892:892:892) (911:911:911)) - (PORT datac (569:569:569) (600:600:600)) - (PORT datad (866:866:866) (894:894:894)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~77) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (284:284:284) (367:367:367)) - (PORT datac (569:569:569) (564:564:564)) - (PORT datad (549:549:549) (580:580:580)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1014:1014:1014) (1027:1027:1027)) - (PORT datab (896:896:896) (917:917:917)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (702:702:702)) - (PORT datab (1071:1071:1071) (1078:1078:1078)) - (PORT datac (868:868:868) (897:897:897)) - (PORT datad (615:615:615) (651:651:651)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~75) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (701:701:701)) - (PORT datab (209:209:209) (248:248:248)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (880:880:880) (912:912:912)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (284:284:284) (370:370:370)) - (PORT datac (576:576:576) (591:591:591)) - (PORT datad (307:307:307) (314:314:314)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (456:456:456)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (682:682:682)) - (PORT datab (1081:1081:1081) (1087:1087:1087)) - (PORT datac (591:591:591) (629:629:629)) - (PORT datad (794:794:794) (790:790:790)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (687:687:687)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (534:534:534) (572:572:572)) - (PORT datab (206:206:206) (244:244:244)) - (PORT datac (1868:1868:1868) (1844:1844:1844)) - (PORT datad (198:198:198) (254:254:254)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (809:809:809)) - (PORT datab (308:308:308) (326:326:326)) - (PORT datac (492:492:492) (482:482:482)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2080:2080:2080) (2094:2094:2094)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2648:2648:2648) (2765:2765:2765)) - (PORT d[1] (1669:1669:1669) (1771:1771:1771)) - (PORT d[2] (2435:2435:2435) (2548:2548:2548)) - (PORT d[3] (2191:2191:2191) (2333:2333:2333)) - (PORT d[4] (1827:1827:1827) (1888:1888:1888)) - (PORT d[5] (2844:2844:2844) (2954:2954:2954)) - (PORT d[6] (1844:1844:1844) (1881:1881:1881)) - (PORT d[7] (3736:3736:3736) (3806:3806:3806)) - (PORT d[8] (2299:2299:2299) (2359:2359:2359)) - (PORT d[9] (2596:2596:2596) (2615:2615:2615)) - (PORT d[10] (1761:1761:1761) (1798:1798:1798)) - (PORT d[11] (1771:1771:1771) (1839:1839:1839)) - (PORT d[12] (2880:2880:2880) (2910:2910:2910)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2558:2558:2558) (2525:2525:2525)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (2892:2892:2892) (2879:2879:2879)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1494:1494:1494) (1542:1542:1542)) - (PORT clk (1641:1641:1641) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1813:1813:1813) (1877:1877:1877)) - (PORT d[1] (2270:2270:2270) (2385:2385:2385)) - (PORT d[2] (1917:1917:1917) (2025:2025:2025)) - (PORT d[3] (1199:1199:1199) (1229:1229:1229)) - (PORT d[4] (2285:2285:2285) (2335:2335:2335)) - (PORT d[5] (4501:4501:4501) (4672:4672:4672)) - (PORT d[6] (1867:1867:1867) (1864:1864:1864)) - (PORT d[7] (1551:1551:1551) (1552:1552:1552)) - (PORT d[8] (2544:2544:2544) (2616:2616:2616)) - (PORT d[9] (2879:2879:2879) (2913:2913:2913)) - (PORT d[10] (1818:1818:1818) (1901:1901:1901)) - (PORT d[11] (1963:1963:1963) (2003:2003:2003)) - (PORT d[12] (1266:1266:1266) (1224:1224:1224)) - (PORT clk (1638:1638:1638) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1578:1578:1578) (1531:1531:1531)) - (PORT clk (1638:1638:1638) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (PORT d[0] (2729:2729:2729) (2660:2660:2660)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1605:1605:1605) (1633:1633:1633)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (877:877:877) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (877:877:877) (881:881:881)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (877:877:877) (881:881:881)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1512:1512:1512) (1552:1552:1552)) - (PORT clk (1640:1640:1640) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1784:1784:1784) (1840:1840:1840)) - (PORT d[1] (2501:2501:2501) (2625:2625:2625)) - (PORT d[2] (1906:1906:1906) (2020:2020:2020)) - (PORT d[3] (1410:1410:1410) (1409:1409:1409)) - (PORT d[4] (2056:2056:2056) (2113:2113:2113)) - (PORT d[5] (4498:4498:4498) (4666:4666:4666)) - (PORT d[6] (2072:2072:2072) (2053:2053:2053)) - (PORT d[7] (1781:1781:1781) (1763:1763:1763)) - (PORT d[8] (2859:2859:2859) (2949:2949:2949)) - (PORT d[9] (2876:2876:2876) (2893:2893:2893)) - (PORT d[10] (1814:1814:1814) (1881:1881:1881)) - (PORT d[11] (1962:1962:1962) (2013:2013:2013)) - (PORT d[12] (1049:1049:1049) (1022:1022:1022)) - (PORT clk (1637:1637:1637) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2038:2038:2038) (1957:1957:1957)) - (PORT clk (1637:1637:1637) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1669:1669:1669)) - (PORT d[0] (2374:2374:2374) (2352:2352:2352)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1633:1633:1633)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (881:881:881)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (881:881:881)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1698:1698:1698) (1721:1721:1721)) - (PORT clk (1631:1631:1631) (1659:1659:1659)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2307:2307:2307) (2384:2384:2384)) - (PORT d[1] (2513:2513:2513) (2626:2626:2626)) - (PORT d[2] (1940:1940:1940) (2045:2045:2045)) - (PORT d[3] (3609:3609:3609) (3813:3813:3813)) - (PORT d[4] (1789:1789:1789) (1834:1834:1834)) - (PORT d[5] (4221:4221:4221) (4381:4381:4381)) - (PORT d[6] (2109:2109:2109) (2124:2124:2124)) - (PORT d[7] (2279:2279:2279) (2273:2273:2273)) - (PORT d[8] (3123:3123:3123) (3229:3229:3229)) - (PORT d[9] (2355:2355:2355) (2378:2378:2378)) - (PORT d[10] (2118:2118:2118) (2216:2216:2216)) - (PORT d[11] (2257:2257:2257) (2328:2328:2328)) - (PORT d[12] (1498:1498:1498) (1470:1470:1470)) - (PORT clk (1628:1628:1628) (1657:1657:1657)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1889:1889:1889) (1868:1868:1868)) - (PORT clk (1628:1628:1628) (1657:1657:1657)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (PORT d[0] (2580:2580:2580) (2608:2608:2608)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1595:1595:1595) (1623:1623:1623)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (867:867:867) (871:871:871)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (867:867:867) (871:871:871)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (867:867:867) (871:871:871)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (303:303:303) (415:415:415)) - (PORT datab (1414:1414:1414) (1422:1422:1422)) - (PORT datac (1068:1068:1068) (1103:1103:1103)) - (PORT datad (1075:1075:1075) (1061:1061:1061)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (305:305:305) (410:410:410)) - (PORT datab (1618:1618:1618) (1624:1624:1624)) - (PORT datac (1322:1322:1322) (1327:1327:1327)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (977:977:977) (1007:1007:1007)) - (PORT d[1] (3093:3093:3093) (3233:3233:3233)) - (PORT d[2] (2018:2018:2018) (2091:2091:2091)) - (PORT d[3] (931:931:931) (968:968:968)) - (PORT d[4] (668:668:668) (699:699:699)) - (PORT d[5] (1162:1162:1162) (1184:1184:1184)) - (PORT d[6] (2698:2698:2698) (2720:2720:2720)) - (PORT d[7] (2185:2185:2185) (2224:2224:2224)) - (PORT d[8] (3708:3708:3708) (3829:3829:3829)) - (PORT d[9] (2817:2817:2817) (2826:2826:2826)) - (PORT d[10] (2648:2648:2648) (2730:2730:2730)) - (PORT d[11] (2077:2077:2077) (2172:2172:2172)) - (PORT d[12] (2242:2242:2242) (2257:2257:2257)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (PORT d[0] (1267:1267:1267) (1236:1236:1236)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1692:1692:1692) (1708:1708:1708)) - (PORT clk (1646:1646:1646) (1673:1673:1673)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2515:2515:2515) (2581:2581:2581)) - (PORT d[1] (1259:1259:1259) (1309:1309:1309)) - (PORT d[2] (3148:3148:3148) (3328:3328:3328)) - (PORT d[3] (2538:2538:2538) (2674:2674:2674)) - (PORT d[4] (2391:2391:2391) (2474:2474:2474)) - (PORT d[5] (1684:1684:1684) (1728:1728:1728)) - (PORT d[6] (2452:2452:2452) (2477:2477:2477)) - (PORT d[7] (3004:3004:3004) (3065:3065:3065)) - (PORT d[8] (1748:1748:1748) (1772:1772:1772)) - (PORT d[9] (3794:3794:3794) (3800:3800:3800)) - (PORT d[10] (1774:1774:1774) (1824:1824:1824)) - (PORT d[11] (2089:2089:2089) (2190:2190:2190)) - (PORT d[12] (2834:2834:2834) (2884:2884:2884)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1615:1615:1615) (1575:1575:1575)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (PORT d[0] (2654:2654:2654) (2645:2645:2645)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1605:1605:1605) (1603:1603:1603)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3159:3159:3159) (3155:3155:3155)) - (PORT clk (1613:1613:1613) (1610:1610:1610)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1733:1733:1733) (1776:1776:1776)) - (PORT d[1] (1673:1673:1673) (1720:1720:1720)) - (PORT d[2] (1667:1667:1667) (1692:1692:1692)) - (PORT d[3] (1828:1828:1828) (1927:1927:1927)) - (PORT d[4] (1740:1740:1740) (1793:1793:1793)) - (PORT d[5] (1964:1964:1964) (1990:1990:1990)) - (PORT d[6] (1899:1899:1899) (1903:1903:1903)) - (PORT d[7] (1719:1719:1719) (1750:1750:1750)) - (PORT d[8] (1762:1762:1762) (1819:1819:1819)) - (PORT d[9] (1872:1872:1872) (1899:1899:1899)) - (PORT d[10] (1750:1750:1750) (1788:1788:1788)) - (PORT d[11] (1793:1793:1793) (1803:1803:1803)) - (PORT d[12] (1762:1762:1762) (1810:1810:1810)) - (PORT clk (1610:1610:1610) (1607:1607:1607)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1610:1610:1610)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (696:696:696) (724:724:724)) - (PORT d[1] (3143:3143:3143) (3297:3297:3297)) - (PORT d[2] (1758:1758:1758) (1822:1822:1822)) - (PORT d[3] (934:934:934) (974:974:974)) - (PORT d[4] (2911:2911:2911) (3011:3011:3011)) - (PORT d[5] (887:887:887) (897:897:897)) - (PORT d[6] (2689:2689:2689) (2720:2720:2720)) - (PORT d[7] (2482:2482:2482) (2530:2530:2530)) - (PORT d[8] (915:915:915) (920:920:920)) - (PORT d[9] (2539:2539:2539) (2538:2538:2538)) - (PORT d[10] (2707:2707:2707) (2793:2793:2793)) - (PORT d[11] (2293:2293:2293) (2407:2407:2407)) - (PORT d[12] (1943:1943:1943) (1951:1951:1951)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1666:1666:1666)) - (PORT d[0] (2096:2096:2096) (2089:2089:2089)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1632:1632:1632)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1434:1434:1434) (1466:1466:1466)) - (PORT clk (1649:1649:1649) (1677:1677:1677)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1576:1576:1576) (1650:1650:1650)) - (PORT d[1] (1605:1605:1605) (1667:1667:1667)) - (PORT d[2] (3383:3383:3383) (3553:3553:3553)) - (PORT d[3] (2543:2543:2543) (2673:2673:2673)) - (PORT d[4] (2422:2422:2422) (2506:2506:2506)) - (PORT d[5] (1652:1652:1652) (1685:1685:1685)) - (PORT d[6] (2403:2403:2403) (2449:2449:2449)) - (PORT d[7] (2783:2783:2783) (2862:2862:2862)) - (PORT d[8] (1913:1913:1913) (1947:1947:1947)) - (PORT d[9] (3764:3764:3764) (3764:3764:3764)) - (PORT d[10] (2051:2051:2051) (2100:2100:2100)) - (PORT d[11] (2806:2806:2806) (2875:2875:2875)) - (PORT d[12] (2809:2809:2809) (2857:2857:2857)) - (PORT clk (1646:1646:1646) (1675:1675:1675)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1635:1635:1635) (1607:1607:1607)) - (PORT clk (1646:1646:1646) (1675:1675:1675)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1649:1649:1649) (1677:1677:1677)) - (PORT d[0] (2612:2612:2612) (2619:2619:2619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1650:1650:1650) (1678:1678:1678)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1650:1650:1650) (1678:1678:1678)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1650:1650:1650) (1678:1678:1678)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1650:1650:1650) (1678:1678:1678)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1607:1607:1607)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3165:3165:3165) (3163:3163:3163)) - (PORT clk (1616:1616:1616) (1614:1614:1614)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1702:1702:1702) (1745:1745:1745)) - (PORT d[1] (1628:1628:1628) (1628:1628:1628)) - (PORT d[2] (1728:1728:1728) (1735:1735:1735)) - (PORT d[3] (1766:1766:1766) (1854:1854:1854)) - (PORT d[4] (1772:1772:1772) (1825:1825:1825)) - (PORT d[5] (1991:1991:1991) (2037:2037:2037)) - (PORT d[6] (1869:1869:1869) (1863:1863:1863)) - (PORT d[7] (1711:1711:1711) (1740:1740:1740)) - (PORT d[8] (1916:1916:1916) (1901:1901:1901)) - (PORT d[9] (1762:1762:1762) (1734:1734:1734)) - (PORT d[10] (1719:1719:1719) (1754:1754:1754)) - (PORT d[11] (1793:1793:1793) (1802:1802:1802)) - (PORT d[12] (1789:1789:1789) (1820:1820:1820)) - (PORT clk (1613:1613:1613) (1611:1611:1611)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1616:1616:1616) (1614:1614:1614)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1617:1617:1617) (1615:1615:1615)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1617:1617:1617) (1615:1615:1615)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1617:1617:1617) (1615:1615:1615)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1617:1617:1617) (1615:1615:1615)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1608:1608:1608)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1102:1102:1102)) - (PORT datab (265:265:265) (350:350:350)) - (PORT datac (830:830:830) (820:820:820)) - (PORT datad (1587:1587:1587) (1593:1593:1593)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1129:1129:1129)) - (PORT datab (265:265:265) (350:350:350)) - (PORT datac (1343:1343:1343) (1339:1339:1339)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (894:894:894)) - (PORT datab (896:896:896) (899:899:899)) - (PORT datac (1137:1137:1137) (1083:1083:1083)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1704:1704:1704) (1711:1711:1711)) - (PORT datab (1979:1979:1979) (2053:2053:2053)) - (PORT datac (3020:3020:3020) (3083:3083:3083)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (658:658:658)) - (PORT datab (207:207:207) (245:245:245)) - (PORT datac (1229:1229:1229) (1192:1192:1192)) - (PORT datad (652:652:652) (686:686:686)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (682:682:682)) - (PORT datab (1111:1111:1111) (1150:1150:1150)) - (PORT datac (232:232:232) (300:300:300)) - (PORT datad (521:521:521) (513:513:513)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (1218:1218:1218) (1271:1271:1271)) - (PORT datab (207:207:207) (243:243:243)) - (PORT datac (1139:1139:1139) (1167:1167:1167)) - (PORT datad (813:813:813) (785:785:785)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1562:1562:1562) (1529:1529:1529)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (655:655:655)) - (PORT datac (852:852:852) (870:870:870)) - (PORT datad (951:951:951) (939:939:939)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1128:1128:1128) (1167:1167:1167)) - (PORT datab (184:184:184) (217:217:217)) - (PORT datac (564:564:564) (572:572:572)) - (PORT datad (756:756:756) (730:730:730)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1752:1752:1752) (1674:1674:1674)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT datab (1986:1986:1986) (1992:1992:1992)) - (PORT datac (1280:1280:1280) (1307:1307:1307)) - (PORT datad (1269:1269:1269) (1280:1280:1280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1218:1218:1218)) - (PORT datab (672:672:672) (736:736:736)) - (PORT datac (1221:1221:1221) (1207:1207:1207)) - (PORT datad (771:771:771) (768:768:768)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1264:1264:1264) (1244:1244:1244)) - (PORT datab (1505:1505:1505) (1472:1472:1472)) - (PORT datac (782:782:782) (769:769:769)) - (PORT datad (592:592:592) (614:614:614)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) - (DELAY - (ABSOLUTE - (PORT datab (573:573:573) (593:593:593)) - (PORT datac (181:181:181) (215:215:215)) - (PORT datad (516:516:516) (508:508:508)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (815:815:815)) - (PORT datab (601:601:601) (609:609:609)) - (PORT datac (785:785:785) (772:772:772)) - (PORT datad (757:757:757) (736:736:736)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (244:244:244)) - (PORT datab (194:194:194) (233:233:233)) - (PORT datac (782:782:782) (784:784:784)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) - (DELAY - (ABSOLUTE - (PORT datab (1005:1005:1005) (981:981:981)) - (PORT datac (942:942:942) (927:927:927)) - (PORT datad (194:194:194) (225:225:225)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1143:1143:1143)) - (PORT datab (621:621:621) (617:617:617)) - (PORT datac (978:978:978) (991:991:991)) - (PORT datad (190:190:190) (221:221:221)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (416:416:416)) - (PORT datab (824:824:824) (800:800:800)) - (PORT datac (785:785:785) (783:783:783)) - (PORT datad (212:212:212) (242:242:242)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1248:1248:1248) (1240:1240:1240)) - (PORT datab (595:595:595) (615:615:615)) - (PORT datac (588:588:588) (596:596:596)) - (PORT datad (620:620:620) (664:664:664)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (244:244:244)) - (PORT datab (594:594:594) (582:582:582)) - (PORT datac (798:798:798) (807:807:807)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (224:224:224)) - (PORT datab (632:632:632) (638:638:638)) - (PORT datac (759:759:759) (749:749:749)) - (PORT datad (576:576:576) (592:592:592)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (1942:1942:1942) (1886:1886:1886)) - (PORT datab (1412:1412:1412) (1415:1415:1415)) - (PORT datac (2791:2791:2791) (2905:2905:2905)) - (PORT datad (2232:2232:2232) (2307:2307:2307)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1734:1734:1734) (1796:1796:1796)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3206:3206:3206) (3346:3346:3346)) - (PORT d[1] (2232:2232:2232) (2332:2332:2332)) - (PORT d[2] (2121:2121:2121) (2239:2239:2239)) - (PORT d[3] (3055:3055:3055) (3235:3235:3235)) - (PORT d[4] (2671:2671:2671) (2770:2770:2770)) - (PORT d[5] (3379:3379:3379) (3511:3511:3511)) - (PORT d[6] (1581:1581:1581) (1557:1557:1557)) - (PORT d[7] (2898:2898:2898) (2935:2935:2935)) - (PORT d[8] (2315:2315:2315) (2382:2382:2382)) - (PORT d[9] (2393:2393:2393) (2408:2408:2408)) - (PORT d[10] (2440:2440:2440) (2528:2528:2528)) - (PORT d[11] (1419:1419:1419) (1466:1466:1466)) - (PORT d[12] (2323:2323:2323) (2325:2325:2325)) - (PORT clk (1639:1639:1639) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1855:1855:1855) (1816:1816:1816)) - (PORT clk (1639:1639:1639) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (PORT d[0] (3119:3119:3119) (3097:3097:3097)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (877:877:877) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2080:2080:2080) (2159:2159:2159)) - (PORT clk (1631:1631:1631) (1659:1659:1659)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2066:2066:2066) (2152:2152:2152)) - (PORT d[1] (2542:2542:2542) (2657:2657:2657)) - (PORT d[2] (4023:4023:4023) (4134:4134:4134)) - (PORT d[3] (3322:3322:3322) (3510:3510:3510)) - (PORT d[4] (1482:1482:1482) (1520:1520:1520)) - (PORT d[5] (3958:3958:3958) (4118:4118:4118)) - (PORT d[6] (2148:2148:2148) (2181:2181:2181)) - (PORT d[7] (2339:2339:2339) (2351:2351:2351)) - (PORT d[8] (3406:3406:3406) (3516:3516:3516)) - (PORT d[9] (2066:2066:2066) (2077:2077:2077)) - (PORT d[10] (1477:1477:1477) (1506:1506:1506)) - (PORT d[11] (1446:1446:1446) (1493:1493:1493)) - (PORT d[12] (1782:1782:1782) (1768:1768:1768)) - (PORT clk (1628:1628:1628) (1657:1657:1657)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2406:2406:2406) (2345:2345:2345)) - (PORT clk (1628:1628:1628) (1657:1657:1657)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (PORT d[0] (2116:2116:2116) (2091:2091:2091)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1595:1595:1595) (1623:1623:1623)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (867:867:867) (871:871:871)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (867:867:867) (871:871:871)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (867:867:867) (871:871:871)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2639:2639:2639) (2663:2663:2663)) - (PORT clk (1644:1644:1644) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2876:2876:2876) (2966:2966:2966)) - (PORT d[1] (1606:1606:1606) (1690:1690:1690)) - (PORT d[2] (2676:2676:2676) (2766:2766:2766)) - (PORT d[3] (2140:2140:2140) (2246:2246:2246)) - (PORT d[4] (2098:2098:2098) (2150:2150:2150)) - (PORT d[5] (2531:2531:2531) (2626:2626:2626)) - (PORT d[6] (1856:1856:1856) (1883:1883:1883)) - (PORT d[7] (3982:3982:3982) (4048:4048:4048)) - (PORT d[8] (2260:2260:2260) (2326:2326:2326)) - (PORT d[9] (2599:2599:2599) (2627:2627:2627)) - (PORT d[10] (1793:1793:1793) (1851:1851:1851)) - (PORT d[11] (1781:1781:1781) (1848:1848:1848)) - (PORT d[12] (3201:3201:3201) (3239:3239:3239)) - (PORT clk (1641:1641:1641) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1831:1831:1831) (1801:1801:1801)) - (PORT clk (1641:1641:1641) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (PORT d[0] (2432:2432:2432) (2451:2451:2451)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1635:1635:1635)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1980:1980:1980) (2025:2025:2025)) - (PORT clk (1654:1654:1654) (1680:1680:1680)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2518:2518:2518) (2586:2586:2586)) - (PORT d[1] (1497:1497:1497) (1525:1525:1525)) - (PORT d[2] (2868:2868:2868) (3029:3029:3029)) - (PORT d[3] (2418:2418:2418) (2532:2532:2532)) - (PORT d[4] (2165:2165:2165) (2251:2251:2251)) - (PORT d[5] (2168:2168:2168) (2205:2205:2205)) - (PORT d[6] (2162:2162:2162) (2202:2202:2202)) - (PORT d[7] (2529:2529:2529) (2609:2609:2609)) - (PORT d[8] (2809:2809:2809) (2878:2878:2878)) - (PORT d[9] (3293:3293:3293) (3271:3271:3271)) - (PORT d[10] (2382:2382:2382) (2470:2470:2470)) - (PORT d[11] (2585:2585:2585) (2672:2672:2672)) - (PORT d[12] (3323:3323:3323) (3377:3377:3377)) - (PORT clk (1651:1651:1651) (1678:1678:1678)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1876:1876:1876) (1837:1837:1837)) - (PORT clk (1651:1651:1651) (1678:1678:1678)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1680:1680:1680)) - (PORT d[0] (2280:2280:2280) (2223:2223:2223)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1655:1655:1655) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1655:1655:1655) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1655:1655:1655) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1655:1655:1655) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1618:1618:1618) (1644:1644:1644)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (889:889:889) (891:891:891)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (890:890:890) (892:892:892)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (890:890:890) (892:892:892)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (890:890:890) (892:892:892)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1851:1851:1851) (1844:1844:1844)) - (PORT datab (1099:1099:1099) (1133:1133:1133)) - (PORT datac (2055:2055:2055) (2014:2014:2014)) - (PORT datad (281:281:281) (376:376:376)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (854:854:854)) - (PORT datab (871:871:871) (880:880:880)) - (PORT datac (1064:1064:1064) (1098:1098:1098)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1255:1255:1255) (1305:1305:1305)) - (PORT d[1] (2625:2625:2625) (2794:2794:2794)) - (PORT d[2] (1847:1847:1847) (1905:1905:1905)) - (PORT d[3] (378:378:378) (398:398:398)) - (PORT d[4] (611:611:611) (623:623:623)) - (PORT d[5] (1434:1434:1434) (1463:1463:1463)) - (PORT d[6] (2741:2741:2741) (2751:2751:2751)) - (PORT d[7] (2151:2151:2151) (2168:2168:2168)) - (PORT d[8] (3707:3707:3707) (3801:3801:3801)) - (PORT d[9] (848:848:848) (835:835:835)) - (PORT d[10] (2143:2143:2143) (2219:2219:2219)) - (PORT d[11] (2065:2065:2065) (2170:2170:2170)) - (PORT d[12] (1034:1034:1034) (1010:1010:1010)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (PORT d[0] (1565:1565:1565) (1546:1546:1546)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1637:1637:1637)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1464:1464:1464) (1502:1502:1502)) - (PORT clk (1639:1639:1639) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1275:1275:1275) (1340:1340:1340)) - (PORT d[1] (1897:1897:1897) (1968:1968:1968)) - (PORT d[2] (1986:1986:1986) (2053:2053:2053)) - (PORT d[3] (2848:2848:2848) (2991:2991:2991)) - (PORT d[4] (2414:2414:2414) (2508:2508:2508)) - (PORT d[5] (1438:1438:1438) (1476:1476:1476)) - (PORT d[6] (2382:2382:2382) (2418:2418:2418)) - (PORT d[7] (2517:2517:2517) (2582:2582:2582)) - (PORT d[8] (1659:1659:1659) (1682:1682:1682)) - (PORT d[9] (4051:4051:4051) (4046:4046:4046)) - (PORT d[10] (1762:1762:1762) (1802:1802:1802)) - (PORT d[11] (3324:3324:3324) (3403:3403:3403)) - (PORT d[12] (2501:2501:2501) (2534:2534:2534)) - (PORT clk (1636:1636:1636) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1397:1397:1397) (1347:1347:1347)) - (PORT clk (1636:1636:1636) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1665:1665:1665)) - (PORT d[0] (2646:2646:2646) (2635:2635:2635)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1595:1595:1595)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2877:2877:2877) (2863:2863:2863)) - (PORT clk (1606:1606:1606) (1602:1602:1602)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1722:1722:1722) (1781:1781:1781)) - (PORT d[1] (1777:1777:1777) (1843:1843:1843)) - (PORT d[2] (1737:1737:1737) (1777:1777:1777)) - (PORT d[3] (1699:1699:1699) (1744:1744:1744)) - (PORT d[4] (1995:1995:1995) (2011:2011:2011)) - (PORT d[5] (1969:1969:1969) (1995:1995:1995)) - (PORT d[6] (1655:1655:1655) (1697:1697:1697)) - (PORT d[7] (1756:1756:1756) (1843:1843:1843)) - (PORT d[8] (1781:1781:1781) (1846:1846:1846)) - (PORT d[9] (1803:1803:1803) (1785:1785:1785)) - (PORT d[10] (1741:1741:1741) (1777:1777:1777)) - (PORT d[11] (1872:1872:1872) (1907:1907:1907)) - (PORT d[12] (1756:1756:1756) (1802:1802:1802)) - (PORT clk (1603:1603:1603) (1599:1599:1599)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1602:1602:1602)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (987:987:987) (1028:1028:1028)) - (PORT d[1] (2866:2866:2866) (3016:3016:3016)) - (PORT d[2] (1499:1499:1499) (1554:1554:1554)) - (PORT d[3] (680:680:680) (713:713:713)) - (PORT d[4] (889:889:889) (903:903:903)) - (PORT d[5] (1169:1169:1169) (1193:1193:1193)) - (PORT d[6] (2444:2444:2444) (2468:2468:2468)) - (PORT d[7] (2151:2151:2151) (2190:2190:2190)) - (PORT d[8] (2943:2943:2943) (3074:3074:3074)) - (PORT d[9] (2790:2790:2790) (2782:2782:2782)) - (PORT d[10] (2439:2439:2439) (2527:2527:2527)) - (PORT d[11] (2044:2044:2044) (2154:2154:2154)) - (PORT d[12] (2242:2242:2242) (2258:2258:2258)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1666:1666:1666)) - (PORT d[0] (1806:1806:1806) (1810:1810:1810)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1632:1632:1632)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1451:1451:1451) (1479:1479:1479)) - (PORT clk (1639:1639:1639) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1295:1295:1295) (1360:1360:1360)) - (PORT d[1] (1276:1276:1276) (1320:1320:1320)) - (PORT d[2] (1740:1740:1740) (1810:1810:1810)) - (PORT d[3] (2849:2849:2849) (2992:2992:2992)) - (PORT d[4] (2685:2685:2685) (2776:2776:2776)) - (PORT d[5] (1393:1393:1393) (1412:1412:1412)) - (PORT d[6] (2416:2416:2416) (2467:2467:2467)) - (PORT d[7] (2491:2491:2491) (2552:2552:2552)) - (PORT d[8] (1516:1516:1516) (1549:1549:1549)) - (PORT d[9] (4035:4035:4035) (4043:4043:4043)) - (PORT d[10] (1778:1778:1778) (1812:1812:1812)) - (PORT d[11] (3325:3325:3325) (3404:3404:3404)) - (PORT d[12] (2521:2521:2521) (2547:2547:2547)) - (PORT clk (1636:1636:1636) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1377:1377:1377) (1338:1338:1338)) - (PORT clk (1636:1636:1636) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (PORT d[0] (1880:1880:1880) (1891:1891:1891)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1597:1597:1597)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2876:2876:2876) (2863:2863:2863)) - (PORT clk (1606:1606:1606) (1604:1604:1604)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1728:1728:1728) (1789:1789:1789)) - (PORT d[1] (1767:1767:1767) (1829:1829:1829)) - (PORT d[2] (1699:1699:1699) (1749:1749:1749)) - (PORT d[3] (1703:1703:1703) (1751:1751:1751)) - (PORT d[4] (1720:1720:1720) (1747:1747:1747)) - (PORT d[5] (1644:1644:1644) (1686:1686:1686)) - (PORT d[6] (1671:1671:1671) (1718:1718:1718)) - (PORT d[7] (1758:1758:1758) (1849:1849:1849)) - (PORT d[8] (1752:1752:1752) (1793:1793:1793)) - (PORT d[9] (1894:1894:1894) (1904:1904:1904)) - (PORT d[10] (1743:1743:1743) (1788:1788:1788)) - (PORT d[11] (1855:1855:1855) (1866:1866:1866)) - (PORT d[12] (1760:1760:1760) (1783:1783:1783)) - (PORT clk (1603:1603:1603) (1601:1601:1601)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1604:1604:1604)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1605:1605:1605)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1605:1605:1605)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1605:1605:1605)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1605:1605:1605)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1598:1598:1598)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (643:643:643)) - (PORT datab (902:902:902) (930:930:930)) - (PORT datac (906:906:906) (961:961:961)) - (PORT datad (1377:1377:1377) (1397:1397:1397)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (992:992:992)) - (PORT datab (920:920:920) (933:933:933)) - (PORT datac (1317:1317:1317) (1323:1323:1323)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (950:950:950) (947:947:947)) - (PORT datab (1123:1123:1123) (1138:1138:1138)) - (PORT datac (2469:2469:2469) (2543:2543:2543)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (861:861:861)) - (PORT datab (1122:1122:1122) (1163:1163:1163)) - (PORT datac (1293:1293:1293) (1296:1296:1296)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~80) - (DELAY - (ABSOLUTE - (PORT datac (855:855:855) (881:881:881)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (1221:1221:1221) (1268:1268:1268)) - (PORT datab (1172:1172:1172) (1199:1199:1199)) - (PORT datac (799:799:799) (783:783:783)) - (PORT datad (824:824:824) (828:828:828)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1562:1562:1562) (1529:1529:1529)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (994:994:994) (972:972:972)) - (PORT datab (1052:1052:1052) (1050:1050:1050)) - (PORT datad (591:591:591) (608:608:608)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1167:1167:1167)) - (PORT datab (790:790:790) (793:793:793)) - (PORT datac (564:564:564) (572:572:572)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1752:1752:1752) (1674:1674:1674)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2133:2133:2133) (2114:2114:2114)) - (PORT datab (1731:1731:1731) (1728:1728:1728)) - (PORT datac (1870:1870:1870) (1883:1883:1883)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1311:1311:1311) (1327:1327:1327)) - (PORT datab (855:855:855) (872:872:872)) - (PORT datad (1219:1219:1219) (1204:1204:1204)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (937:937:937)) - (PORT datab (618:618:618) (630:630:630)) - (PORT datac (1066:1066:1066) (1061:1061:1061)) - (PORT datad (763:763:763) (762:762:762)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (885:885:885)) - (PORT datab (641:641:641) (662:662:662)) - (PORT datac (763:763:763) (781:781:781)) - (PORT datad (554:554:554) (546:546:546)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (762:762:762) (750:750:750)) - (PORT datab (610:610:610) (615:615:615)) - (PORT datac (792:792:792) (800:800:800)) - (PORT datad (949:949:949) (923:923:923)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (323:323:323) (344:344:344)) - (PORT datab (354:354:354) (356:356:356)) - (PORT datac (176:176:176) (208:208:208)) - (PORT datad (789:789:789) (782:782:782)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (638:638:638)) - (PORT datab (960:960:960) (1003:1003:1003)) - (PORT datac (176:176:176) (207:207:207)) - (PORT datad (496:496:496) (490:490:490)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1238:1238:1238) (1240:1240:1240)) - (PORT datab (573:573:573) (598:598:598)) - (PORT datac (1351:1351:1351) (1339:1339:1339)) - (PORT datad (868:868:868) (884:884:884)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (763:763:763) (769:769:769)) - (PORT datab (645:645:645) (672:672:672)) - (PORT datac (1660:1660:1660) (1605:1605:1605)) - (PORT datad (987:987:987) (981:981:981)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (851:851:851)) - (PORT datab (1040:1040:1040) (1025:1025:1025)) - (PORT datac (367:367:367) (383:383:383)) - (PORT datad (599:599:599) (597:597:597)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1119:1119:1119)) - (PORT datab (1041:1041:1041) (1023:1023:1023)) - (PORT datac (1459:1459:1459) (1435:1435:1435)) - (PORT datad (1042:1042:1042) (1039:1039:1039)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (222:222:222)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (167:167:167) (194:194:194)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (915:915:915)) - (PORT datab (619:619:619) (650:650:650)) - (PORT datac (1454:1454:1454) (1414:1414:1414)) - (PORT datad (857:857:857) (912:912:912)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (689:689:689)) - (PORT datab (539:539:539) (545:545:545)) - (PORT datac (1454:1454:1454) (1416:1416:1416)) - (PORT datad (585:585:585) (617:617:617)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (603:603:603) (616:616:616)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1216:1216:1216)) - (PORT datab (569:569:569) (585:585:585)) - (PORT datac (1223:1223:1223) (1205:1205:1205)) - (PORT datad (771:771:771) (766:766:766)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (538:538:538) (537:537:537)) - (PORT datab (1061:1061:1061) (1080:1080:1080)) - (PORT datac (757:757:757) (752:752:752)) - (PORT datad (521:521:521) (510:510:510)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1403:1403:1403) (1433:1433:1433)) - (PORT datab (898:898:898) (918:918:918)) - (PORT datac (1121:1121:1121) (1069:1069:1069)) - (PORT datad (204:204:204) (236:236:236)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (542:542:542)) - (PORT datab (1063:1063:1063) (1082:1082:1082)) - (PORT datac (578:578:578) (589:589:589)) - (PORT datad (294:294:294) (294:294:294)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1029:1029:1029) (1010:1010:1010)) - (PORT datab (988:988:988) (997:997:997)) - (PORT datac (577:577:577) (572:572:572)) - (PORT datad (1030:1030:1030) (1008:1008:1008)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (549:549:549)) - (PORT datab (519:519:519) (520:520:520)) - (PORT datac (1392:1392:1392) (1345:1345:1345)) - (PORT datad (520:520:520) (511:511:511)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (231:231:231)) - (PORT datab (1630:1630:1630) (1652:1652:1652)) - (PORT datac (1350:1350:1350) (1375:1375:1375)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1049:1049:1049) (1059:1059:1059)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datac (156:156:156) (185:185:185)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (772:772:772)) - (PORT datab (778:778:778) (779:779:779)) - (PORT datac (763:763:763) (743:743:743)) - (PORT datad (565:565:565) (562:562:562)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (649:649:649)) - (PORT datab (369:369:369) (396:396:396)) - (PORT datac (941:941:941) (906:906:906)) - (PORT datad (302:302:302) (312:312:312)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (817:817:817)) - (PORT datab (1420:1420:1420) (1385:1385:1385)) - (PORT datac (929:929:929) (916:916:916)) - (PORT datad (960:960:960) (920:920:920)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~39) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (238:238:238)) - (PORT datab (1258:1258:1258) (1210:1210:1210)) - (PORT datac (793:793:793) (795:795:795)) - (PORT datad (991:991:991) (954:954:954)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (615:615:615)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datac (540:540:540) (544:544:544)) - (PORT datad (1179:1179:1179) (1152:1152:1152)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (576:576:576) (604:604:604)) - (PORT datac (468:468:468) (458:458:458)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) - (DELAY - (ABSOLUTE - (PORT dataa (995:995:995) (962:962:962)) - (PORT datab (190:190:190) (226:226:226)) - (PORT datad (978:978:978) (986:986:986)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1593:1593:1593) (1674:1674:1674)) - (PORT clk (1632:1632:1632) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2653:2653:2653) (2774:2774:2774)) - (PORT d[1] (1655:1655:1655) (1757:1757:1757)) - (PORT d[2] (2167:2167:2167) (2288:2288:2288)) - (PORT d[3] (2493:2493:2493) (2646:2646:2646)) - (PORT d[4] (2069:2069:2069) (2134:2134:2134)) - (PORT d[5] (2831:2831:2831) (2938:2938:2938)) - (PORT d[6] (1849:1849:1849) (1888:1888:1888)) - (PORT d[7] (3446:3446:3446) (3502:3502:3502)) - (PORT d[8] (2004:2004:2004) (2066:2066:2066)) - (PORT d[9] (2591:2591:2591) (2603:2603:2603)) - (PORT d[10] (1815:1815:1815) (1870:1870:1870)) - (PORT d[11] (1732:1732:1732) (1800:1800:1800)) - (PORT d[12] (2904:2904:2904) (2936:2936:2936)) - (PORT clk (1629:1629:1629) (1656:1656:1656)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2086:2086:2086) (2018:2018:2018)) - (PORT clk (1629:1629:1629) (1656:1656:1656)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1658:1658:1658)) - (PORT d[0] (2573:2573:2573) (2537:2537:2537)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1596:1596:1596) (1622:1622:1622)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (867:867:867) (869:869:869)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (870:870:870)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (870:870:870)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (870:870:870)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1813:1813:1813) (1876:1876:1876)) - (PORT clk (1634:1634:1634) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2924:2924:2924) (3045:3045:3045)) - (PORT d[1] (1921:1921:1921) (2032:2032:2032)) - (PORT d[2] (2922:2922:2922) (3022:3022:3022)) - (PORT d[3] (2484:2484:2484) (2634:2634:2634)) - (PORT d[4] (2095:2095:2095) (2164:2164:2164)) - (PORT d[5] (2811:2811:2811) (2920:2920:2920)) - (PORT d[6] (2136:2136:2136) (2176:2176:2176)) - (PORT d[7] (3420:3420:3420) (3474:3474:3474)) - (PORT d[8] (2001:2001:2001) (2061:2061:2061)) - (PORT d[9] (2600:2600:2600) (2623:2623:2623)) - (PORT d[10] (1829:1829:1829) (1897:1897:1897)) - (PORT d[11] (1739:1739:1739) (1811:1811:1811)) - (PORT d[12] (2918:2918:2918) (2944:2944:2944)) - (PORT clk (1631:1631:1631) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1847:1847:1847) (1820:1820:1820)) - (PORT clk (1631:1631:1631) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1662:1662:1662)) - (PORT d[0] (2903:2903:2903) (2899:2899:2899)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1594:1594:1594) (1580:1580:1580)) - (PORT clk (1628:1628:1628) (1657:1657:1657)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2059:2059:2059) (2143:2143:2143)) - (PORT d[1] (2514:2514:2514) (2635:2635:2635)) - (PORT d[2] (1905:1905:1905) (2006:2006:2006)) - (PORT d[3] (3316:3316:3316) (3512:3512:3512)) - (PORT d[4] (1774:1774:1774) (1807:1807:1807)) - (PORT d[5] (3959:3959:3959) (4119:4119:4119)) - (PORT d[6] (2123:2123:2123) (2151:2151:2151)) - (PORT d[7] (2318:2318:2318) (2328:2328:2328)) - (PORT d[8] (3120:3120:3120) (3226:3226:3226)) - (PORT d[9] (2336:2336:2336) (2343:2343:2343)) - (PORT d[10] (1460:1460:1460) (1496:1496:1496)) - (PORT d[11] (2519:2519:2519) (2591:2591:2591)) - (PORT d[12] (1776:1776:1776) (1760:1760:1760)) - (PORT clk (1625:1625:1625) (1655:1655:1655)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1946:1946:1946) (1951:1951:1951)) - (PORT clk (1625:1625:1625) (1655:1655:1655)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1628:1628:1628) (1657:1657:1657)) - (PORT d[0] (2548:2548:2548) (2579:2579:2579)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1629:1629:1629) (1658:1658:1658)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1629:1629:1629) (1658:1658:1658)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1629:1629:1629) (1658:1658:1658)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1629:1629:1629) (1658:1658:1658)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1592:1592:1592) (1621:1621:1621)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (863:863:863) (868:868:868)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (864:864:864) (869:869:869)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (864:864:864) (869:869:869)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (864:864:864) (869:869:869)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (301:301:301) (405:405:405)) - (PORT datab (1373:1373:1373) (1398:1398:1398)) - (PORT datac (1063:1063:1063) (1095:1095:1095)) - (PORT datad (860:860:860) (862:862:862)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1305:1305:1305) (1305:1305:1305)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2575:2575:2575) (2647:2647:2647)) - (PORT d[1] (2225:2225:2225) (2340:2340:2340)) - (PORT d[2] (4022:4022:4022) (4133:4133:4133)) - (PORT d[3] (3326:3326:3326) (3508:3508:3508)) - (PORT d[4] (2960:2960:2960) (3063:3063:3063)) - (PORT d[5] (3945:3945:3945) (4093:4093:4093)) - (PORT d[6] (2374:2374:2374) (2403:2403:2403)) - (PORT d[7] (2559:2559:2559) (2564:2564:2564)) - (PORT d[8] (3384:3384:3384) (3495:3495:3495)) - (PORT d[9] (2065:2065:2065) (2076:2076:2076)) - (PORT d[10] (1209:1209:1209) (1243:1243:1243)) - (PORT d[11] (1443:1443:1443) (1480:1480:1480)) - (PORT d[12] (1783:1783:1783) (1769:1769:1769)) - (PORT clk (1629:1629:1629) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2400:2400:2400) (2347:2347:2347)) - (PORT clk (1629:1629:1629) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (PORT d[0] (2049:2049:2049) (2019:2019:2019)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1596:1596:1596) (1624:1624:1624)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (867:867:867) (871:871:871)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1394:1394:1394) (1402:1402:1402)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (1062:1062:1062) (1095:1095:1095)) - (PORT datad (803:803:803) (766:766:766)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1264:1264:1264) (1328:1328:1328)) - (PORT clk (1642:1642:1642) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1323:1323:1323) (1386:1386:1386)) - (PORT d[1] (1549:1549:1549) (1587:1587:1587)) - (PORT d[2] (1731:1731:1731) (1801:1801:1801)) - (PORT d[3] (2819:2819:2819) (2956:2956:2956)) - (PORT d[4] (2434:2434:2434) (2532:2532:2532)) - (PORT d[5] (1373:1373:1373) (1412:1412:1412)) - (PORT d[6] (2442:2442:2442) (2496:2496:2496)) - (PORT d[7] (2465:2465:2465) (2524:2524:2524)) - (PORT d[8] (1507:1507:1507) (1532:1532:1532)) - (PORT d[9] (2776:2776:2776) (2777:2777:2777)) - (PORT d[10] (1683:1683:1683) (1689:1689:1689)) - (PORT d[11] (3585:3585:3585) (3663:3663:3663)) - (PORT d[12] (2543:2543:2543) (2582:2582:2582)) - (PORT clk (1639:1639:1639) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1369:1369:1369) (1329:1329:1329)) - (PORT clk (1639:1639:1639) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1669:1669:1669)) - (PORT d[0] (1872:1872:1872) (1845:1845:1845)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1599:1599:1599)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2871:2871:2871) (2854:2854:2854)) - (PORT clk (1609:1609:1609) (1606:1606:1606)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1725:1725:1725) (1793:1793:1793)) - (PORT d[1] (1732:1732:1732) (1795:1795:1795)) - (PORT d[2] (1713:1713:1713) (1769:1769:1769)) - (PORT d[3] (1733:1733:1733) (1788:1788:1788)) - (PORT d[4] (1755:1755:1755) (1793:1793:1793)) - (PORT d[5] (1678:1678:1678) (1722:1722:1722)) - (PORT d[6] (1706:1706:1706) (1781:1781:1781)) - (PORT d[7] (1756:1756:1756) (1845:1845:1845)) - (PORT d[8] (1900:1900:1900) (1928:1928:1928)) - (PORT d[9] (1887:1887:1887) (1893:1893:1893)) - (PORT d[10] (1763:1763:1763) (1809:1809:1809)) - (PORT d[11] (1819:1819:1819) (1841:1841:1841)) - (PORT d[12] (1838:1838:1838) (1919:1919:1919)) - (PORT clk (1606:1606:1606) (1603:1603:1603)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1606:1606:1606)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1257:1257:1257) (1311:1311:1311)) - (PORT d[1] (2625:2625:2625) (2795:2795:2795)) - (PORT d[2] (1576:1576:1576) (1643:1643:1643)) - (PORT d[3] (604:604:604) (599:599:599)) - (PORT d[4] (612:612:612) (633:633:633)) - (PORT d[5] (1434:1434:1434) (1464:1464:1464)) - (PORT d[6] (2473:2473:2473) (2483:2483:2483)) - (PORT d[7] (2131:2131:2131) (2163:2163:2163)) - (PORT d[8] (2950:2950:2950) (3067:3067:3067)) - (PORT d[9] (851:851:851) (832:832:832)) - (PORT d[10] (2112:2112:2112) (2187:2187:2187)) - (PORT d[11] (2638:2638:2638) (2630:2630:2630)) - (PORT d[12] (1066:1066:1066) (1035:1035:1035)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1672:1672:1672)) - (PORT d[0] (1543:1543:1543) (1524:1524:1524)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1638:1638:1638)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (973:973:973) (1016:1016:1016)) - (PORT d[1] (2580:2580:2580) (2714:2714:2714)) - (PORT d[2] (1846:1846:1846) (1913:1913:1913)) - (PORT d[3] (895:895:895) (923:923:923)) - (PORT d[4] (665:665:665) (693:693:693)) - (PORT d[5] (1169:1169:1169) (1194:1194:1194)) - (PORT d[6] (2785:2785:2785) (2805:2805:2805)) - (PORT d[7] (2167:2167:2167) (2199:2199:2199)) - (PORT d[8] (3467:3467:3467) (3576:3576:3576)) - (PORT d[9] (3071:3071:3071) (3077:3077:3077)) - (PORT d[10] (2413:2413:2413) (2498:2498:2498)) - (PORT d[11] (2053:2053:2053) (2148:2148:2148)) - (PORT d[12] (2209:2209:2209) (2217:2217:2217)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (PORT d[0] (1805:1805:1805) (1809:1809:1809)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1254:1254:1254) (1304:1304:1304)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1562:1562:1562) (1625:1625:1625)) - (PORT d[1] (1896:1896:1896) (1968:1968:1968)) - (PORT d[2] (3138:3138:3138) (3322:3322:3322)) - (PORT d[3] (2778:2778:2778) (2912:2912:2912)) - (PORT d[4] (2122:2122:2122) (2218:2218:2218)) - (PORT d[5] (1619:1619:1619) (1655:1655:1655)) - (PORT d[6] (2156:2156:2156) (2203:2203:2203)) - (PORT d[7] (2745:2745:2745) (2798:2798:2798)) - (PORT d[8] (1637:1637:1637) (1662:1662:1662)) - (PORT d[9] (3770:3770:3770) (3773:3773:3773)) - (PORT d[10] (1770:1770:1770) (1818:1818:1818)) - (PORT d[11] (2065:2065:2065) (2163:2163:2163)) - (PORT d[12] (2481:2481:2481) (2513:2513:2513)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1654:1654:1654) (1603:1603:1603)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (2660:2660:2660) (2662:2662:2662)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3149:3149:3149) (3135:3135:3135)) - (PORT clk (1610:1610:1610) (1607:1607:1607)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1742:1742:1742) (1797:1797:1797)) - (PORT d[1] (1672:1672:1672) (1719:1719:1719)) - (PORT d[2] (1722:1722:1722) (1763:1763:1763)) - (PORT d[3] (1805:1805:1805) (1900:1900:1900)) - (PORT d[4] (1713:1713:1713) (1735:1735:1735)) - (PORT d[5] (1725:1725:1725) (1764:1764:1764)) - (PORT d[6] (1903:1903:1903) (1909:1909:1909)) - (PORT d[7] (1771:1771:1771) (1847:1847:1847)) - (PORT d[8] (1912:1912:1912) (1923:1923:1923)) - (PORT d[9] (1892:1892:1892) (1919:1919:1919)) - (PORT d[10] (1724:1724:1724) (1761:1761:1761)) - (PORT d[11] (1849:1849:1849) (1882:1882:1882)) - (PORT d[12] (1736:1736:1736) (1781:1781:1781)) - (PORT clk (1607:1607:1607) (1604:1604:1604)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1601:1601:1601)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (996:996:996)) - (PORT datab (902:902:902) (931:931:931)) - (PORT datac (829:829:829) (831:831:831)) - (PORT datad (1342:1342:1342) (1351:1351:1351)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (991:991:991)) - (PORT datab (1376:1376:1376) (1389:1389:1389)) - (PORT datac (1043:1043:1043) (1037:1037:1037)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (2533:2533:2533) (2614:2614:2614)) - (PORT datab (1118:1118:1118) (1134:1134:1134)) - (PORT datac (908:908:908) (900:900:900)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (870:870:870)) - (PORT datab (1124:1124:1124) (1162:1162:1162)) - (PORT datac (814:814:814) (826:826:826)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (915:915:915)) - (PORT datac (175:175:175) (206:206:206)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (1222:1222:1222) (1276:1276:1276)) - (PORT datab (1173:1173:1173) (1200:1200:1200)) - (PORT datac (764:764:764) (755:755:755)) - (PORT datad (592:592:592) (621:621:621)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1562:1562:1562) (1529:1529:1529)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (604:604:604)) - (PORT datac (1096:1096:1096) (1140:1140:1140)) - (PORT datad (951:951:951) (939:939:939)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (858:858:858)) - (PORT datab (597:597:597) (603:603:603)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (591:591:591) (604:604:604)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1752:1752:1752) (1674:1674:1674)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1302:1302:1302)) - (PORT datab (1208:1208:1208) (1216:1216:1216)) - (PORT datac (250:250:250) (338:338:338)) - (PORT datad (262:262:262) (338:338:338)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (615:615:615)) - (PORT datab (1033:1033:1033) (998:998:998)) - (PORT datac (527:527:527) (524:524:524)) - (PORT datad (2617:2617:2617) (2588:2588:2588)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1367:1367:1367)) - (PORT asdata (611:611:611) (616:616:616)) - (PORT clrn (1388:1388:1388) (1360:1360:1360)) - (PORT ena (1792:1792:1792) (1756:1756:1756)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (552:552:552) (544:544:544)) - (PORT datab (237:237:237) (306:306:306)) - (PORT datad (1114:1114:1114) (1173:1173:1173)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (547:547:547)) - (PORT datab (616:616:616) (617:617:617)) - (PORT datac (975:975:975) (991:991:991)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1082:1082:1082) (1065:1065:1065)) - (PORT datab (703:703:703) (692:692:692)) - (PORT datac (160:160:160) (193:193:193)) - (PORT datad (1132:1132:1132) (1174:1174:1174)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (973:973:973)) - (PORT datab (823:823:823) (843:843:843)) - (PORT datad (591:591:591) (603:603:603)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (600:600:600) (609:609:609)) - (PORT datac (1095:1095:1095) (1139:1139:1139)) - (PORT datad (991:991:991) (963:963:963)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1752:1752:1752) (1674:1674:1674)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (1961:1961:1961) (1975:1975:1975)) - (PORT datad (2192:2192:2192) (2177:2177:2177)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1287:1287:1287) (1278:1278:1278)) - (PORT datab (1489:1489:1489) (1517:1517:1517)) - (PORT datac (807:807:807) (815:815:815)) - (PORT datad (566:566:566) (573:573:573)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (308:308:308) (412:412:412)) - (PORT datab (279:279:279) (368:368:368)) - (PORT datac (228:228:228) (302:302:302)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (240:240:240)) - (PORT datab (1031:1031:1031) (1028:1028:1028)) - (PORT datad (161:161:161) (181:181:181)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1374:1374:1374)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1366:1366:1366)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1217:1217:1217)) - (PORT datab (566:566:566) (585:585:585)) - (PORT datac (645:645:645) (711:711:711)) - (PORT datad (773:773:773) (767:767:767)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (544:544:544) (551:551:551)) - (PORT datab (516:516:516) (522:522:522)) - (PORT datac (958:958:958) (971:971:971)) - (PORT datad (1202:1202:1202) (1174:1174:1174)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1056:1056:1056) (1058:1058:1058)) - (PORT datab (673:673:673) (697:697:697)) - (PORT datac (1741:1741:1741) (1715:1715:1715)) - (PORT datad (765:765:765) (736:736:736)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (229:229:229)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (162:162:162) (195:195:195)) - (PORT datad (875:875:875) (882:882:882)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (606:606:606)) - (PORT datab (1166:1166:1166) (1226:1226:1226)) - (PORT datac (793:793:793) (778:778:778)) - (PORT datad (1203:1203:1203) (1174:1174:1174)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (819:819:819)) - (PORT datab (1489:1489:1489) (1482:1482:1482)) - (PORT datac (981:981:981) (986:986:986)) - (PORT datad (513:513:513) (499:499:499)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (544:544:544) (550:550:550)) - (PORT datab (804:804:804) (801:801:801)) - (PORT datac (1049:1049:1049) (1036:1036:1036)) - (PORT datad (815:815:815) (811:811:811)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (526:526:526) (510:510:510)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (951:951:951)) - (PORT datab (646:646:646) (692:692:692)) - (PORT datac (865:865:865) (895:895:895)) - (PORT datad (1036:1036:1036) (1048:1048:1048)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~125) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (465:465:465)) - (PORT datab (184:184:184) (218:218:218)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~126) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1133:1133:1133)) - (PORT datab (888:888:888) (928:928:928)) - (PORT datad (573:573:573) (611:611:611)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (445:445:445) (490:490:490)) - (PORT datac (994:994:994) (1001:1001:1001)) - (PORT datad (501:501:501) (492:492:492)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (361:361:361) (365:365:365)) - (PORT datad (649:649:649) (702:702:702)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (660:660:660)) - (PORT datab (1732:1732:1732) (1711:1711:1711)) - (PORT datac (194:194:194) (261:261:261)) - (PORT datad (796:796:796) (793:793:793)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (726:726:726)) - (PORT datab (604:604:604) (633:633:633)) - (PORT datac (1062:1062:1062) (1079:1079:1079)) - (PORT datad (582:582:582) (613:613:613)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~138) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1131:1131:1131)) - (PORT datab (248:248:248) (318:318:318)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (347:347:347)) - (PORT datab (314:314:314) (331:331:331)) - (PORT datad (862:862:862) (896:896:896)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (1067:1067:1067) (1084:1084:1084)) - (PORT datab (432:432:432) (482:482:482)) - (PORT datac (597:597:597) (642:642:642)) - (PORT datad (861:861:861) (881:881:881)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (285:285:285)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~122) - (DELAY - (ABSOLUTE - (PORT dataa (1134:1134:1134) (1152:1152:1152)) - (PORT datab (416:416:416) (477:477:477)) - (PORT datac (1195:1195:1195) (1176:1176:1176)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~123) - (DELAY - (ABSOLUTE - (PORT datab (606:606:606) (620:620:620)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (852:852:852)) - (PORT datab (385:385:385) (424:424:424)) - (PORT datac (762:762:762) (755:755:755)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~129) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (229:229:229)) - (PORT datab (671:671:671) (735:735:735)) - (PORT datad (329:329:329) (330:330:330)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (956:956:956)) - (PORT datab (641:641:641) (693:693:693)) - (PORT datac (865:865:865) (901:901:901)) - (PORT datad (1033:1033:1033) (1048:1048:1048)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (463:463:463)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datad (179:179:179) (205:205:205)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1379:1379:1379)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (631:631:631)) - (PORT datab (822:822:822) (845:845:845)) - (PORT datac (872:872:872) (885:885:885)) - (PORT datad (761:761:761) (785:785:785)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (238:238:238)) - (PORT datab (597:597:597) (605:605:605)) - (PORT datad (338:338:338) (336:336:336)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (688:688:688)) - (PORT datab (835:835:835) (826:826:826)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (660:660:660)) - (PORT datab (205:205:205) (242:242:242)) - (PORT datac (1871:1871:1871) (1845:1845:1845)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (836:836:836)) - (PORT datab (568:568:568) (580:580:580)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (539:539:539) (547:547:547)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2268:2268:2268) (2324:2324:2324)) - (PORT clk (1646:1646:1646) (1673:1673:1673)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2634:2634:2634) (2752:2752:2752)) - (PORT d[1] (1638:1638:1638) (1740:1740:1740)) - (PORT d[2] (2623:2623:2623) (2718:2718:2718)) - (PORT d[3] (2121:2121:2121) (2249:2249:2249)) - (PORT d[4] (1799:1799:1799) (1850:1850:1850)) - (PORT d[5] (2308:2308:2308) (2375:2375:2375)) - (PORT d[6] (1862:1862:1862) (1898:1898:1898)) - (PORT d[7] (4015:4015:4015) (4092:4092:4092)) - (PORT d[8] (2264:2264:2264) (2332:2332:2332)) - (PORT d[9] (2555:2555:2555) (2559:2559:2559)) - (PORT d[10] (1783:1783:1783) (1838:1838:1838)) - (PORT d[11] (1763:1763:1763) (1831:1831:1831)) - (PORT d[12] (3145:3145:3145) (3179:3179:3179)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2483:2483:2483) (2435:2435:2435)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (PORT d[0] (2354:2354:2354) (2332:2332:2332)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1637:1637:1637)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2508:2508:2508) (2574:2574:2574)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2632:2632:2632) (2751:2751:2751)) - (PORT d[1] (1654:1654:1654) (1756:1756:1756)) - (PORT d[2] (2697:2697:2697) (2785:2785:2785)) - (PORT d[3] (2191:2191:2191) (2334:2334:2334)) - (PORT d[4] (2079:2079:2079) (2135:2135:2135)) - (PORT d[5] (2856:2856:2856) (2966:2966:2966)) - (PORT d[6] (1848:1848:1848) (1888:1888:1888)) - (PORT d[7] (3472:3472:3472) (3531:3531:3531)) - (PORT d[8] (2005:2005:2005) (2067:2067:2067)) - (PORT d[9] (2604:2604:2604) (2635:2635:2635)) - (PORT d[10] (1575:1575:1575) (1652:1652:1652)) - (PORT d[11] (1787:1787:1787) (1853:1853:1853)) - (PORT d[12] (2915:2915:2915) (2945:2945:2945)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2098:2098:2098) (2044:2044:2044)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (2340:2340:2340) (2307:2307:2307)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2765:2765:2765) (2834:2834:2834)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3223:3223:3223) (3356:3356:3356)) - (PORT d[1] (1964:1964:1964) (2069:2069:2069)) - (PORT d[2] (3169:3169:3169) (3259:3259:3259)) - (PORT d[3] (2769:2769:2769) (2934:2934:2934)) - (PORT d[4] (2358:2358:2358) (2434:2434:2434)) - (PORT d[5] (3100:3100:3100) (3217:3217:3217)) - (PORT d[6] (2129:2129:2129) (2181:2181:2181)) - (PORT d[7] (3172:3172:3172) (3218:3218:3218)) - (PORT d[8] (2016:2016:2016) (2072:2072:2072)) - (PORT d[9] (2332:2332:2332) (2320:2320:2320)) - (PORT d[10] (2147:2147:2147) (2229:2229:2229)) - (PORT d[11] (1727:1727:1727) (1789:1789:1789)) - (PORT d[12] (2601:2601:2601) (2610:2610:2610)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2116:2116:2116) (2052:2052:2052)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (PORT d[0] (2727:2727:2727) (2737:2737:2737)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1632:1632:1632)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2233:2233:2233) (2296:2296:2296)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2638:2638:2638) (2745:2745:2745)) - (PORT d[1] (1618:1618:1618) (1707:1707:1707)) - (PORT d[2] (2446:2446:2446) (2562:2562:2562)) - (PORT d[3] (2163:2163:2163) (2303:2303:2303)) - (PORT d[4] (2103:2103:2103) (2157:2157:2157)) - (PORT d[5] (2539:2539:2539) (2637:2637:2637)) - (PORT d[6] (1835:1835:1835) (1862:1862:1862)) - (PORT d[7] (3744:3744:3744) (3813:3813:3813)) - (PORT d[8] (2297:2297:2297) (2362:2362:2362)) - (PORT d[9] (2594:2594:2594) (2621:2621:2621)) - (PORT d[10] (1766:1766:1766) (1818:1818:1818)) - (PORT d[11] (1748:1748:1748) (1816:1816:1816)) - (PORT d[12] (2881:2881:2881) (2911:2911:2911)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2121:2121:2121) (2078:2078:2078)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (PORT d[0] (2437:2437:2437) (2443:2443:2443)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1632:1632:1632)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1330:1330:1330) (1376:1376:1376)) - (PORT datab (587:587:587) (572:572:572)) - (PORT datac (871:871:871) (920:920:920)) - (PORT datad (1075:1075:1075) (1063:1063:1063)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1353:1353:1353) (1367:1367:1367)) - (PORT datab (897:897:897) (947:947:947)) - (PORT datac (1056:1056:1056) (1036:1036:1036)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (995:995:995) (1038:1038:1038)) - (PORT d[1] (2632:2632:2632) (2791:2791:2791)) - (PORT d[2] (1846:1846:1846) (1913:1913:1913)) - (PORT d[3] (673:673:673) (703:703:703)) - (PORT d[4] (656:656:656) (671:671:671)) - (PORT d[5] (1469:1469:1469) (1484:1484:1484)) - (PORT d[6] (2739:2739:2739) (2754:2754:2754)) - (PORT d[7] (1886:1886:1886) (1927:1927:1927)) - (PORT d[8] (3711:3711:3711) (3803:3803:3803)) - (PORT d[9] (800:800:800) (779:779:779)) - (PORT d[10] (2387:2387:2387) (2469:2469:2469)) - (PORT d[11] (2087:2087:2087) (2184:2184:2184)) - (PORT d[12] (1274:1274:1274) (1223:1223:1223)) - (PORT clk (1641:1641:1641) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1668:1668:1668)) - (PORT d[0] (1797:1797:1797) (1791:1791:1791)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1460:1460:1460) (1501:1501:1501)) - (PORT clk (1652:1652:1652) (1679:1679:1679)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1556:1556:1556) (1629:1629:1629)) - (PORT d[1] (1604:1604:1604) (1666:1666:1666)) - (PORT d[2] (3146:3146:3146) (3319:3319:3319)) - (PORT d[3] (2393:2393:2393) (2494:2494:2494)) - (PORT d[4] (2409:2409:2409) (2496:2496:2496)) - (PORT d[5] (1692:1692:1692) (1739:1739:1739)) - (PORT d[6] (2118:2118:2118) (2151:2151:2151)) - (PORT d[7] (2766:2766:2766) (2850:2850:2850)) - (PORT d[8] (1930:1930:1930) (1955:1955:1955)) - (PORT d[9] (3781:3781:3781) (3773:3773:3773)) - (PORT d[10] (2061:2061:2061) (2121:2121:2121)) - (PORT d[11] (2854:2854:2854) (2951:2951:2951)) - (PORT d[12] (3084:3084:3084) (3131:3131:3131)) - (PORT clk (1649:1649:1649) (1677:1677:1677)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1597:1597:1597) (1565:1565:1565)) - (PORT clk (1649:1649:1649) (1677:1677:1677)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1652:1652:1652) (1679:1679:1679)) - (PORT d[0] (2384:2384:2384) (2368:2368:2368)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3165:3165:3165) (3164:3164:3164)) - (PORT clk (1619:1619:1619) (1616:1616:1616)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1802:1802:1802) (1851:1851:1851)) - (PORT d[1] (1802:1802:1802) (1857:1857:1857)) - (PORT d[2] (1685:1685:1685) (1708:1708:1708)) - (PORT d[3] (1788:1788:1788) (1867:1867:1867)) - (PORT d[4] (1752:1752:1752) (1805:1805:1805)) - (PORT d[5] (1982:1982:1982) (2026:2026:2026)) - (PORT d[6] (1647:1647:1647) (1639:1639:1639)) - (PORT d[7] (1885:1885:1885) (1946:1946:1946)) - (PORT d[8] (1877:1877:1877) (1876:1876:1876)) - (PORT d[9] (1906:1906:1906) (1876:1876:1876)) - (PORT d[10] (1982:1982:1982) (2019:2019:2019)) - (PORT d[11] (1789:1789:1789) (1796:1796:1796)) - (PORT d[12] (1747:1747:1747) (1777:1777:1777)) - (PORT clk (1616:1616:1616) (1613:1613:1613)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1619:1619:1619) (1616:1616:1616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (397:397:397) (417:417:417)) - (PORT d[1] (3133:3133:3133) (3302:3302:3302)) - (PORT d[2] (1765:1765:1765) (1818:1818:1818)) - (PORT d[3] (3695:3695:3695) (3883:3883:3883)) - (PORT d[4] (2883:2883:2883) (2987:2987:2987)) - (PORT d[5] (916:916:916) (921:921:921)) - (PORT d[6] (2984:2984:2984) (3024:3024:3024)) - (PORT d[7] (599:599:599) (600:600:600)) - (PORT d[8] (911:911:911) (914:914:914)) - (PORT d[9] (2525:2525:2525) (2520:2520:2520)) - (PORT d[10] (857:857:857) (844:844:844)) - (PORT d[11] (1367:1367:1367) (1377:1377:1377)) - (PORT d[12] (1926:1926:1926) (1920:1920:1920)) - (PORT clk (1641:1641:1641) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1668:1668:1668)) - (PORT d[0] (2372:2372:2372) (2356:2356:2356)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1760:1760:1760) (1812:1812:1812)) - (PORT clk (1655:1655:1655) (1682:1682:1682)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2750:2750:2750) (2807:2807:2807)) - (PORT d[1] (1579:1579:1579) (1630:1630:1630)) - (PORT d[2] (3078:3078:3078) (3224:3224:3224)) - (PORT d[3] (2213:2213:2213) (2345:2345:2345)) - (PORT d[4] (2431:2431:2431) (2493:2493:2493)) - (PORT d[5] (1956:1956:1956) (2005:2005:2005)) - (PORT d[6] (2181:2181:2181) (2216:2216:2216)) - (PORT d[7] (2737:2737:2737) (2795:2795:2795)) - (PORT d[8] (2235:2235:2235) (2273:2273:2273)) - (PORT d[9] (3511:3511:3511) (3505:3505:3505)) - (PORT d[10] (2339:2339:2339) (2388:2388:2388)) - (PORT d[11] (2535:2535:2535) (2600:2600:2600)) - (PORT d[12] (3121:3121:3121) (3182:3182:3182)) - (PORT clk (1652:1652:1652) (1680:1680:1680)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1895:1895:1895) (1873:1873:1873)) - (PORT clk (1652:1652:1652) (1680:1680:1680)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1655:1655:1655) (1682:1682:1682)) - (PORT d[0] (2886:2886:2886) (2881:2881:2881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1656:1656:1656) (1683:1683:1683)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1656:1656:1656) (1683:1683:1683)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1656:1656:1656) (1683:1683:1683)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1656:1656:1656) (1683:1683:1683)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1612:1612:1612)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3437:3437:3437) (3446:3446:3446)) - (PORT clk (1622:1622:1622) (1619:1619:1619)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1697:1697:1697) (1708:1708:1708)) - (PORT d[1] (1813:1813:1813) (1877:1877:1877)) - (PORT d[2] (1922:1922:1922) (1920:1920:1920)) - (PORT d[3] (1801:1801:1801) (1893:1893:1893)) - (PORT d[4] (1733:1733:1733) (1760:1760:1760)) - (PORT d[5] (1645:1645:1645) (1677:1677:1677)) - (PORT d[6] (1885:1885:1885) (1878:1878:1878)) - (PORT d[7] (1711:1711:1711) (1725:1725:1725)) - (PORT d[8] (1910:1910:1910) (1902:1902:1902)) - (PORT d[9] (1837:1837:1837) (1835:1835:1835)) - (PORT d[10] (2004:2004:2004) (2045:2045:2045)) - (PORT d[11] (1909:1909:1909) (1962:1962:1962)) - (PORT d[12] (2019:2019:2019) (2065:2065:2065)) - (PORT clk (1619:1619:1619) (1616:1616:1616)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1622:1622:1622) (1619:1619:1619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1623:1623:1623) (1620:1620:1620)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1623:1623:1623) (1620:1620:1620)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1623:1623:1623) (1620:1620:1620)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1623:1623:1623) (1620:1620:1620)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1615:1615:1615) (1613:1613:1613)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (916:916:916)) - (PORT datab (547:547:547) (529:529:529)) - (PORT datac (863:863:863) (892:892:892)) - (PORT datad (1312:1312:1312) (1300:1300:1300)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~1) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (925:925:925)) - (PORT datab (892:892:892) (898:898:898)) - (PORT datac (1512:1512:1512) (1488:1488:1488)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (725:725:725)) - (PORT datab (1498:1498:1498) (1510:1510:1510)) - (PORT datac (578:578:578) (597:597:597)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (1403:1403:1403) (1411:1411:1411)) - (PORT datab (3062:3062:3062) (3152:3152:3152)) - (PORT datac (1679:1679:1679) (1709:1709:1709)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (205:205:205) (242:242:242)) - (PORT datac (315:315:315) (320:320:320)) - (PORT datad (652:652:652) (687:687:687)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (581:581:581)) - (PORT datab (238:238:238) (307:307:307)) - (PORT datac (611:611:611) (642:642:642)) - (PORT datad (1086:1086:1086) (1113:1113:1113)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) - (DELAY - (ABSOLUTE - (PORT dataa (1221:1221:1221) (1268:1268:1268)) - (PORT datab (1172:1172:1172) (1199:1199:1199)) - (PORT datac (821:821:821) (818:818:818)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1562:1562:1562) (1529:1529:1529)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (654:654:654)) - (PORT datac (866:866:866) (895:895:895)) - (PORT datad (949:949:949) (939:939:939)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1168:1168:1168)) - (PORT datab (380:380:380) (378:378:378)) - (PORT datac (565:565:565) (573:573:573)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1752:1752:1752) (1674:1674:1674)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) - (DELAY - (ABSOLUTE - (PORT datab (900:900:900) (946:946:946)) - (PORT datac (881:881:881) (929:929:929)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1044:1044:1044) (1040:1040:1040)) - (PORT datab (864:864:864) (883:883:883)) - (PORT datac (1873:1873:1873) (1892:1892:1892)) - (PORT datad (1061:1061:1061) (1071:1071:1071)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1446:1446:1446) (1415:1415:1415)) - (PORT datab (201:201:201) (234:234:234)) - (PORT datac (862:862:862) (878:878:878)) - (PORT datad (752:752:752) (757:757:757)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1374:1374:1374)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1366:1366:1366)) - (PORT ena (875:875:875) (869:869:869)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (312:312:312) (419:419:419)) - (PORT datab (865:865:865) (883:883:883)) - (PORT datac (833:833:833) (859:859:859)) - (PORT datad (254:254:254) (331:331:331)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1374:1374:1374)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1366:1366:1366)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) - (DELAY - (ABSOLUTE - (PORT datab (812:812:812) (829:829:829)) - (PORT datad (203:203:203) (262:262:262)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (PORT ena (1120:1120:1120) (1095:1095:1095)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT datab (250:250:250) (324:324:324)) - (PORT datac (812:812:812) (831:831:831)) - (PORT datad (809:809:809) (818:818:818)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (PORT ena (1120:1120:1120) (1095:1095:1095)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (880:880:880)) - (PORT datac (216:216:216) (283:283:283)) - (PORT datad (808:808:808) (814:814:814)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (PORT ena (1120:1120:1120) (1095:1095:1095)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (249:249:249) (320:320:320)) - (PORT datac (824:824:824) (843:843:843)) - (PORT datad (804:804:804) (813:813:813)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (PORT ena (1120:1120:1120) (1095:1095:1095)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1336:1336:1336)) - (PORT datac (1062:1062:1062) (1103:1103:1103)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (492:492:492)) - (PORT datad (1241:1241:1241) (1194:1194:1194)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (258:258:258)) - (PORT datab (207:207:207) (245:245:245)) - (PORT datac (1572:1572:1572) (1533:1533:1533)) - (PORT datad (163:163:163) (187:187:187)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1081:1081:1081)) - (PORT datab (800:800:800) (811:811:811)) - (PORT datac (161:161:161) (193:193:193)) - (PORT datad (752:752:752) (745:745:745)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (552:552:552) (549:549:549)) - (PORT datab (1547:1547:1547) (1537:1537:1537)) - (PORT datac (1496:1496:1496) (1496:1496:1496)) - (PORT datad (1713:1713:1713) (1771:1771:1771)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1035:1035:1035) (1010:1010:1010)) - (PORT datab (822:822:822) (825:825:825)) - (PORT datac (723:723:723) (718:718:718)) - (PORT datad (1751:1751:1751) (1642:1642:1642)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT datab (1171:1171:1171) (1149:1149:1149)) - (PORT datac (946:946:946) (911:911:911)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (627:627:627)) - (PORT datab (619:619:619) (646:646:646)) - (PORT datac (163:163:163) (198:198:198)) - (PORT datad (537:537:537) (551:551:551)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (246:246:246)) - (PORT datab (897:897:897) (913:913:913)) - (PORT datac (180:180:180) (213:213:213)) - (PORT datad (206:206:206) (237:237:237)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (630:630:630)) - (PORT datab (939:939:939) (925:925:925)) - (PORT datac (1047:1047:1047) (1056:1056:1056)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1085:1085:1085) (1091:1091:1091)) - (PORT datab (1089:1089:1089) (1068:1068:1068)) - (PORT datac (748:748:748) (760:760:760)) - (PORT datad (940:940:940) (917:917:917)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (221:221:221)) - (PORT datab (572:572:572) (599:599:599)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (561:561:561)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (760:760:760) (758:758:758)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (888:888:888)) - (PORT datad (796:796:796) (808:808:808)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (317:317:317)) - (PORT datac (811:811:811) (837:837:837)) - (PORT datad (808:808:808) (817:817:817)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (PORT ena (1120:1120:1120) (1095:1095:1095)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1224:1224:1224) (1197:1197:1197)) - (PORT datab (1247:1247:1247) (1235:1235:1235)) - (PORT datad (1054:1054:1054) (1037:1037:1037)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1211:1211:1211) (1161:1161:1161)) - (PORT datab (1275:1275:1275) (1282:1282:1282)) - (PORT datac (946:946:946) (912:912:912)) - (PORT datad (799:799:799) (800:800:800)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (812:812:812) (804:804:804)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (835:835:835) (842:842:842)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (597:597:597)) - (PORT datab (208:208:208) (243:243:243)) - (PORT datac (1098:1098:1098) (1115:1115:1115)) - (PORT datad (1418:1418:1418) (1378:1378:1378)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1172:1172:1172) (1143:1143:1143)) - (PORT datab (1246:1246:1246) (1224:1224:1224)) - (PORT datac (588:588:588) (576:576:576)) - (PORT datad (767:767:767) (757:757:757)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) - (DELAY - (ABSOLUTE - (PORT datab (915:915:915) (858:858:858)) - (PORT datac (942:942:942) (898:898:898)) - (PORT datad (162:162:162) (187:187:187)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) - (DELAY - (ABSOLUTE - (PORT dataa (727:727:727) (704:704:704)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (680:680:680) (650:650:650)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (800:800:800) (787:787:787)) - (PORT datac (588:588:588) (611:611:611)) - (PORT datad (952:952:952) (923:923:923)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) - (DELAY - (ABSOLUTE - (PORT dataa (790:790:790) (832:832:832)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (183:183:183) (209:209:209)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1313:1313:1313) (1349:1349:1349)) - (PORT datab (1490:1490:1490) (1484:1484:1484)) - (PORT datac (1701:1701:1701) (1708:1708:1708)) - (PORT datad (1707:1707:1707) (1765:1765:1765)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1300:1300:1300)) - (PORT datab (847:847:847) (819:819:819)) - (PORT datac (1246:1246:1246) (1258:1258:1258)) - (PORT datad (815:815:815) (818:818:818)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~12) - (DELAY - (ABSOLUTE - (PORT dataa (953:953:953) (922:922:922)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (504:504:504) (502:502:502)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (631:631:631)) - (PORT datab (1003:1003:1003) (1005:1005:1005)) - (PORT datac (829:829:829) (852:852:852)) - (PORT datad (829:829:829) (827:827:827)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT datab (209:209:209) (244:244:244)) - (PORT datac (513:513:513) (499:499:499)) - (PORT datad (1038:1038:1038) (1048:1048:1048)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (779:779:779) (789:789:789)) - (PORT datab (1225:1225:1225) (1201:1201:1201)) - (PORT datac (1027:1027:1027) (1032:1032:1032)) - (PORT datad (717:717:717) (699:699:699)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (226:226:226)) - (PORT datab (192:192:192) (230:230:230)) - (PORT datac (601:601:601) (629:629:629)) - (PORT datad (1248:1248:1248) (1231:1231:1231)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1078:1078:1078)) - (PORT datab (975:975:975) (957:957:957)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (719:719:719) (707:707:707)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (772:772:772) (788:788:788)) - (PORT datab (585:585:585) (604:604:604)) - (PORT datac (955:955:955) (936:936:936)) - (PORT datad (1751:1751:1751) (1642:1642:1642)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1077:1077:1077) (1088:1088:1088)) - (PORT datab (1011:1011:1011) (998:998:998)) - (PORT datac (1806:1806:1806) (1827:1827:1827)) - (PORT datad (308:308:308) (311:311:311)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1162:1162:1162) (1209:1209:1209)) - (PORT datab (1066:1066:1066) (1116:1116:1116)) - (PORT datac (543:543:543) (571:571:571)) - (PORT datad (201:201:201) (259:259:259)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1341:1341:1341)) - (PORT datab (900:900:900) (949:949:949)) - (PORT datac (1167:1167:1167) (1123:1123:1123)) - (PORT datad (884:884:884) (942:942:942)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1451:1451:1451)) - (PORT datab (857:857:857) (888:888:888)) - (PORT datac (779:779:779) (768:768:768)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (803:803:803)) - (PORT datab (239:239:239) (308:308:308)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (993:993:993) (954:954:954)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (237:237:237)) - (PORT datab (854:854:854) (882:882:882)) - (PORT datac (1247:1247:1247) (1236:1236:1236)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~28) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (938:938:938)) - (PORT datab (957:957:957) (957:957:957)) - (PORT datac (1580:1580:1580) (1621:1621:1621)) - (PORT datad (557:557:557) (557:557:557)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (607:607:607)) - (PORT datab (1100:1100:1100) (1107:1107:1107)) - (PORT datac (162:162:162) (198:198:198)) - (PORT datad (1040:1040:1040) (1059:1059:1059)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) - (DELAY - (ABSOLUTE - (PORT dataa (977:977:977) (971:971:971)) - (PORT datab (1002:1002:1002) (1005:1005:1005)) - (PORT datac (938:938:938) (943:943:943)) - (PORT datad (777:777:777) (763:763:763)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~29) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (598:598:598)) - (PORT datab (1195:1195:1195) (1170:1170:1170)) - (PORT datac (511:511:511) (506:506:506)) - (PORT datad (508:508:508) (502:502:502)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (533:533:533) (513:513:513)) - (PORT datab (910:910:910) (940:940:940)) - (PORT datac (179:179:179) (212:212:212)) - (PORT datad (961:961:961) (920:920:920)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~34) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (784:784:784) (775:775:775)) - (PORT datac (508:508:508) (496:496:496)) - (PORT datad (775:775:775) (755:755:755)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~54) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (823:823:823)) - (PORT datab (1074:1074:1074) (1066:1066:1066)) - (PORT datac (1281:1281:1281) (1291:1291:1291)) - (PORT datad (1250:1250:1250) (1226:1226:1226)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1203:1203:1203)) - (PORT datab (808:808:808) (836:836:836)) - (PORT datac (945:945:945) (911:911:911)) - (PORT datad (777:777:777) (770:770:770)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (822:822:822)) - (PORT datab (520:520:520) (511:511:511)) - (PORT datac (915:915:915) (887:887:887)) - (PORT datad (985:985:985) (984:984:984)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~35) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (154:154:154) (185:185:185)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1266:1266:1266) (1260:1260:1260)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (291:291:291) (300:300:300)) - (PORT datad (725:725:725) (713:713:713)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (871:871:871)) - (PORT datab (256:256:256) (331:331:331)) - (PORT datad (807:807:807) (817:817:817)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT datac (635:635:635) (703:703:703)) - (PORT datad (934:934:934) (988:988:988)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (667:667:667)) - (PORT datab (1496:1496:1496) (1462:1462:1462)) - (PORT datac (1642:1642:1642) (1622:1622:1622)) - (PORT datad (966:966:966) (943:943:943)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (238:238:238)) - (PORT datab (1615:1615:1615) (1603:1603:1603)) - (PORT datac (752:752:752) (754:754:754)) - (PORT datad (187:187:187) (218:218:218)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (811:811:811)) - (PORT datab (1265:1265:1265) (1263:1263:1263)) - (PORT datac (748:748:748) (749:749:749)) - (PORT datad (996:996:996) (988:988:988)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~37) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (211:211:211) (250:250:250)) - (PORT datac (776:776:776) (776:776:776)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1025:1025:1025)) - (PORT datab (342:342:342) (350:350:350)) - (PORT datac (1206:1206:1206) (1196:1196:1196)) - (PORT datad (777:777:777) (777:777:777)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (230:230:230)) - (PORT datab (1291:1291:1291) (1290:1290:1290)) - (PORT datac (515:515:515) (521:521:521)) - (PORT datad (989:989:989) (977:977:977)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (551:551:551)) - (PORT datab (1292:1292:1292) (1292:1292:1292)) - (PORT datac (592:592:592) (604:604:604)) - (PORT datad (1191:1191:1191) (1162:1162:1162)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (230:230:230)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datac (752:752:752) (753:753:753)) - (PORT datad (762:762:762) (739:739:739)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (727:727:727)) - (PORT datab (765:765:765) (741:741:741)) - (PORT datac (641:641:641) (677:677:677)) - (PORT datad (700:700:700) (672:672:672)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (570:570:570)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datad (1426:1426:1426) (1464:1464:1464)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (699:699:699) (741:741:741)) - (PORT sload (1544:1544:1544) (1580:1580:1580)) - (PORT ena (1951:1951:1951) (1924:1924:1924)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (662:662:662)) - (PORT datab (3066:3066:3066) (3158:3158:3158)) - (PORT datac (1120:1120:1120) (1126:1126:1126)) - (PORT datad (646:646:646) (678:678:678)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (801:801:801) (803:803:803)) - (PORT datab (1106:1106:1106) (1144:1144:1144)) - (PORT datac (655:655:655) (684:684:684)) - (PORT datad (176:176:176) (197:197:197)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (688:688:688)) - (PORT datab (2061:2061:2061) (2115:2115:2115)) - (PORT datac (292:292:292) (309:309:309)) - (PORT datad (2768:2768:2768) (2876:2876:2876)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1135:1135:1135)) - (PORT datab (628:628:628) (671:671:671)) - (PORT datac (530:530:530) (536:536:536)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (2065:2065:2065) (2117:2117:2117)) - (PORT datab (213:213:213) (252:252:252)) - (PORT datac (2789:2789:2789) (2901:2901:2901)) - (PORT datad (164:164:164) (189:189:189)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1400:1400:1400)) - (PORT datab (1557:1557:1557) (1571:1571:1571)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (3063:3063:3063) (3152:3152:3152)) - (PORT datac (1122:1122:1122) (1132:1132:1132)) - (PORT datad (653:653:653) (687:687:687)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (856:856:856)) - (PORT datab (1369:1369:1369) (1363:1363:1363)) - (PORT datac (156:156:156) (188:188:188)) - (PORT datad (176:176:176) (197:197:197)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~3) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (884:884:884)) - (PORT datab (245:245:245) (319:319:319)) - (PORT datac (225:225:225) (299:299:299)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (PORT ena (1120:1120:1120) (1095:1095:1095)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (606:606:606) (644:644:644)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1369:1369:1369)) - (PORT ena (1125:1125:1125) (1125:1125:1125)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1368:1368:1368)) - (PORT asdata (825:825:825) (839:839:839)) - (PORT clrn (1398:1398:1398) (1369:1369:1369)) - (PORT ena (1318:1318:1318) (1291:1291:1291)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (563:563:563)) - (PORT datab (229:229:229) (300:300:300)) - (PORT datad (203:203:203) (264:264:264)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (316:316:316)) - (PORT datab (188:188:188) (226:226:226)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[0\]\~15) - (DELAY - (ABSOLUTE - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1684:1684:1684) (1698:1698:1698)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (308:308:308)) - (PORT datab (229:229:229) (300:300:300)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1684:1684:1684) (1698:1698:1698)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (301:301:301)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1684:1684:1684) (1698:1698:1698)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (228:228:228) (302:302:302)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1684:1684:1684) (1698:1698:1698)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (303:303:303)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1684:1684:1684) (1698:1698:1698)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (306:306:306)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH cin combout (408:408:408) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1684:1684:1684) (1698:1698:1698)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (306:306:306)) - (PORT datab (228:228:228) (302:302:302)) - (PORT datac (201:201:201) (271:271:271)) - (PORT datad (204:204:204) (266:266:266)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|WideAnd0) - (DELAY - (ABSOLUTE - (PORT datab (227:227:227) (299:299:299)) - (PORT datac (202:202:202) (273:273:273)) - (PORT datad (162:162:162) (183:183:183)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Idle) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (PORT ena (925:925:925) (895:895:895)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|phase\~0) - (DELAY - (ABSOLUTE - (PORT datad (244:244:244) (313:313:313)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|phase\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (PORT ena (925:925:925) (895:895:895)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|phase\~1) - (DELAY - (ABSOLUTE - (PORT dataa (270:270:270) (350:350:350)) - (PORT datad (222:222:222) (284:284:284)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|phase\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (PORT ena (925:925:925) (895:895:895)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Mux42\~0) - (DELAY - (ABSOLUTE - (PORT datac (1038:1038:1038) (1045:1045:1045)) - (PORT datad (613:613:613) (649:649:649)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~6) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (332:332:332)) - (PORT datab (805:805:805) (841:841:841)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1080:1080:1080)) - (PORT datab (697:697:697) (745:745:745)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT datac (396:396:396) (451:451:451)) - (PORT datad (614:614:614) (648:648:648)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE I2C_SDAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (461:461:461) (708:708:708)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (457:457:457)) - (PORT datab (1011:1011:1011) (998:998:998)) - (PORT datac (395:395:395) (439:439:439)) - (PORT datad (465:465:465) (444:444:444)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (215:215:215) (252:252:252)) - (PORT datac (665:665:665) (715:715:715)) - (PORT datad (305:305:305) (309:309:309)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT datab (648:648:648) (682:682:682)) - (PORT datac (731:731:731) (720:720:720)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1392:1392:1392)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (429:429:429) (471:471:471)) - (PORT datab (804:804:804) (840:840:840)) - (PORT datad (372:372:372) (413:413:413)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1037:1037:1037) (1034:1034:1034)) - (PORT datab (804:804:804) (840:840:840)) - (PORT datac (592:592:592) (637:637:637)) - (PORT datad (636:636:636) (672:672:672)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (781:781:781) (805:805:805)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (332:332:332)) - (PORT datab (748:748:748) (757:757:757)) - (PORT datac (188:188:188) (228:228:228)) - (PORT datad (609:609:609) (648:648:648)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1689:1689:1689) (1703:1703:1703)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1392:1392:1392)) - (PORT ena (1041:1041:1041) (1005:1005:1005)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (333:333:333)) - (PORT datab (229:229:229) (303:303:303)) - (PORT datac (770:770:770) (801:801:801)) - (PORT datad (211:211:211) (275:275:275)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (324:324:324)) - (PORT datab (245:245:245) (318:318:318)) - (PORT datac (219:219:219) (288:288:288)) - (PORT datad (230:230:230) (293:293:293)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (592:592:592)) - (PORT datab (186:186:186) (220:220:220)) - (PORT datac (729:729:729) (721:721:721)) - (PORT datad (244:244:244) (313:313:313)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~2) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (366:366:366)) - (PORT datab (393:393:393) (407:407:407)) - (PORT datad (231:231:231) (292:292:292)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (325:325:325)) - (PORT datac (397:397:397) (453:453:453)) - (PORT datad (717:717:717) (719:719:719)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (242:242:242)) - (PORT datac (1041:1041:1041) (1043:1043:1043)) - (PORT datad (615:615:615) (649:649:649)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT datab (250:250:250) (322:322:322)) - (PORT datac (475:475:475) (464:464:464)) - (PORT datad (362:362:362) (400:400:400)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT datab (563:563:563) (559:559:559)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1043:1043:1043) (1031:1031:1031)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (PORT sload (780:780:780) (882:882:882)) - (PORT ena (925:925:925) (895:895:895)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~5) - (DELAY - (ABSOLUTE - (PORT datab (806:806:806) (842:842:842)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1689:1689:1689) (1703:1703:1703)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1392:1392:1392)) - (PORT ena (1041:1041:1041) (1005:1005:1005)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~0) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (805:805:805) (841:841:841)) - (PORT datad (211:211:211) (274:274:274)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1689:1689:1689) (1703:1703:1703)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1392:1392:1392)) - (PORT ena (1041:1041:1041) (1005:1005:1005)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (303:303:303)) - (PORT datac (219:219:219) (302:302:302)) - (PORT datad (212:212:212) (275:275:275)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (324:324:324)) - (PORT datab (315:315:315) (337:337:337)) - (PORT datac (473:473:473) (461:461:461)) - (PORT datad (230:230:230) (291:291:291)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (593:593:593)) - (PORT datab (256:256:256) (330:330:330)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (244:244:244) (314:314:314)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (695:695:695)) - (PORT datab (583:583:583) (612:612:612)) - (PORT datac (652:652:652) (712:712:712)) - (PORT datad (976:976:976) (970:970:970)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (402:402:402) (457:457:457)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (588:588:588)) - (PORT datab (818:818:818) (829:829:829)) - (PORT datac (555:555:555) (575:575:575)) - (PORT datad (670:670:670) (629:629:629)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (816:816:816)) - (PORT datab (579:579:579) (609:609:609)) - (PORT datac (718:718:718) (704:704:704)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1680:1680:1680) (1692:1692:1692)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2145:2145:2145) (2141:2141:2141)) - (PORT clrn (1407:1407:1407) (1391:1391:1391)) - (PORT sload (1530:1530:1530) (1578:1578:1578)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (354:354:354)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1680:1680:1680) (1692:1692:1692)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2145:2145:2145) (2141:2141:2141)) - (PORT clrn (1407:1407:1407) (1391:1391:1391)) - (PORT sload (1530:1530:1530) (1578:1578:1578)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT datab (266:266:266) (349:349:349)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1680:1680:1680) (1692:1692:1692)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1391:1391:1391)) - (PORT sload (1530:1530:1530) (1578:1578:1578)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (268:268:268) (345:345:345)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1680:1680:1680) (1692:1692:1692)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2146:2146:2146) (2142:2142:2142)) - (PORT clrn (1407:1407:1407) (1391:1391:1391)) - (PORT sload (1530:1530:1530) (1578:1578:1578)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (632:632:632)) - (PORT datab (429:429:429) (466:466:466)) - (PORT datac (369:369:369) (424:424:424)) - (PORT datad (378:378:378) (412:412:412)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT datad (243:243:243) (313:313:313)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1680:1680:1680) (1692:1692:1692)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1391:1391:1391)) - (PORT sload (1530:1530:1530) (1578:1578:1578)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) - (DELAY - (ABSOLUTE - (PORT datab (184:184:184) (218:218:218)) - (PORT datac (159:159:159) (191:191:191)) - (PORT datad (385:385:385) (421:421:421)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (219:219:219)) - (PORT datab (397:397:397) (409:409:409)) - (PORT datad (553:553:553) (541:541:541)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Pause) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~25) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (322:322:322)) - (PORT datab (759:759:759) (752:752:752)) - (PORT datad (245:245:245) (313:313:313)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Start) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (PORT ena (925:925:925) (895:895:895)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1077:1077:1077) (1077:1077:1077)) - (PORT datab (702:702:702) (752:752:752)) - (PORT datad (719:719:719) (723:723:723)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1392:1392:1392)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (331:331:331)) - (PORT datac (394:394:394) (449:449:449)) - (PORT datad (713:713:713) (716:716:716)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (596:596:596)) - (PORT datab (393:393:393) (408:408:408)) - (PORT datad (289:289:289) (298:298:298)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Stop) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|scl_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (245:245:245) (318:318:318)) - (PORT datac (219:219:219) (289:289:289)) - (PORT datad (230:230:230) (290:290:290)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1717:1717:1717) (1735:1735:1735)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1392:1392:1392)) - (PORT ena (1197:1197:1197) (1201:1201:1201)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|scl_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1037:1037:1037) (1034:1034:1034)) - (PORT datab (223:223:223) (293:293:293)) - (PORT datac (784:784:784) (808:808:808)) - (PORT datad (636:636:636) (673:673:673)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|scl_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (555:555:555)) - (PORT datac (781:781:781) (803:803:803)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|scl_out) - (DELAY - (ABSOLUTE - (PORT clk (1306:1306:1306) (1319:1319:1319)) - (PORT d (852:852:852) (916:916:916)) - (PORT aload (1520:1520:1520) (1565:1565:1565)) - (PORT ena (626:626:626) (628:628:628)) - (IOPATH (posedge clk) q (549:549:549) (552:552:552)) - (IOPATH (posedge aload) q (455:455:455) (458:458:458)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (75:75:75)) - (SETUP ena (posedge clk) (75:75:75)) - (HOLD d (posedge clk) (89:89:89)) - (HOLD ena (posedge clk) (89:89:89)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|sda_out\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1717:1717:1717) (1735:1735:1735)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1392:1392:1392)) - (PORT ena (1197:1197:1197) (1201:1201:1201)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Mux35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (627:627:627)) - (PORT datab (429:429:429) (463:463:463)) - (PORT datac (369:369:369) (420:420:420)) - (PORT datad (377:377:377) (412:412:412)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (684:684:684) (740:740:740)) - (PORT datac (369:369:369) (424:424:424)) - (PORT datad (377:377:377) (416:416:416)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (668:668:668)) - (PORT datac (1037:1037:1037) (1040:1040:1040)) - (PORT datad (605:605:605) (645:645:645)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (239:239:239)) - (PORT datab (701:701:701) (751:751:751)) - (PORT datac (188:188:188) (227:227:227)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (749:749:749) (757:757:757)) - (PORT datad (609:609:609) (648:648:648)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1392:1392:1392)) - (PORT sclr (1096:1096:1096) (1181:1181:1181)) - (PORT ena (864:864:864) (848:848:848)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sclr (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) - (DELAY - (ABSOLUTE - (PORT datac (804:804:804) (817:817:817)) - (PORT datad (786:786:786) (800:800:800)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (629:629:629)) - (PORT datab (420:420:420) (453:453:453)) - (PORT datac (369:369:369) (421:421:421)) - (PORT datad (378:378:378) (412:412:412)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (494:494:494)) - (PORT datab (430:430:430) (465:465:465)) - (PORT datac (370:370:370) (421:421:421)) - (PORT datad (162:162:162) (183:183:183)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (298:298:298)) - (PORT datac (654:654:654) (713:713:713)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (664:664:664)) - (PORT datab (697:697:697) (746:746:746)) - (PORT datac (172:172:172) (214:214:214)) - (PORT datad (615:615:615) (651:651:651)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (221:221:221)) - (PORT datab (749:749:749) (752:752:752)) - (PORT datac (1037:1037:1037) (1042:1042:1042)) - (PORT datad (608:608:608) (644:644:644)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1392:1392:1392)) - (PORT ena (919:919:919) (911:911:911)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (352:352:352)) - (PORT datab (268:268:268) (348:348:348)) - (PORT datac (374:374:374) (426:426:426)) - (PORT datad (242:242:242) (310:310:310)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (338:338:338)) - (PORT datab (265:265:265) (347:347:347)) - (PORT datac (376:376:376) (423:423:423)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (298:298:298)) - (PORT datac (652:652:652) (712:712:712)) - (PORT datad (316:316:316) (317:317:317)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1392:1392:1392)) - (PORT ena (919:919:919) (911:911:911)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) - (DELAY - (ABSOLUTE - (PORT datac (238:238:238) (322:322:322)) - (PORT datad (242:242:242) (310:310:310)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (264:264:264) (349:349:349)) - (PORT datab (269:269:269) (349:349:349)) - (PORT datac (238:238:238) (319:319:319)) - (PORT datad (244:244:244) (312:312:312)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (238:238:238)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (375:375:375) (424:424:424)) - (PORT datad (244:244:244) (312:312:312)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (730:730:730)) - (PORT datab (224:224:224) (293:293:293)) - (PORT datac (653:653:653) (713:713:713)) - (PORT datad (302:302:302) (303:303:303)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1392:1392:1392)) - (PORT ena (919:919:919) (911:911:911)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (349:349:349)) - (PORT datab (264:264:264) (346:346:346)) - (PORT datac (373:373:373) (422:422:422)) - (PORT datad (241:241:241) (311:311:311)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (235:235:235)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (374:374:374) (422:422:422)) - (PORT datad (242:242:242) (312:312:312)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (725:725:725)) - (PORT datab (223:223:223) (293:293:293)) - (PORT datac (648:648:648) (703:703:703)) - (PORT datad (317:317:317) (319:319:319)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1392:1392:1392)) - (PORT ena (919:919:919) (911:911:911)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (358:358:358)) - (PORT datab (759:759:759) (786:786:786)) - (PORT datad (358:358:358) (392:392:392)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1392:1392:1392)) - (PORT sload (1304:1304:1304) (1361:1361:1361)) - (PORT ena (735:735:735) (734:734:734)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (406:406:406)) - (PORT datac (649:649:649) (709:709:709)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1392:1392:1392)) - (PORT sclr (1096:1096:1096) (1181:1181:1181)) - (PORT ena (919:919:919) (911:911:911)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sclr (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT datac (655:655:655) (715:715:715)) - (PORT datad (200:200:200) (258:258:258)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1392:1392:1392)) - (PORT sclr (1096:1096:1096) (1181:1181:1181)) - (PORT ena (864:864:864) (848:848:848)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sclr (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|sda_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (405:405:405)) - (PORT datab (686:686:686) (743:743:743)) - (PORT datac (548:548:548) (576:576:576)) - (PORT datad (975:975:975) (966:966:966)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|sda_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (495:495:495) (483:483:483)) - (PORT datab (530:530:530) (516:516:516)) - (PORT datac (1013:1013:1013) (1006:1006:1006)) - (PORT datad (466:466:466) (443:443:443)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|sda_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (310:310:310)) - (PORT datab (677:677:677) (710:710:710)) - (PORT datac (1013:1013:1013) (1006:1006:1006)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|sda_out\~3) - (DELAY - (ABSOLUTE - (PORT dataa (233:233:233) (312:312:312)) - (PORT datab (674:674:674) (713:713:713)) - (PORT datac (1010:1010:1010) (1007:1007:1007)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|sda_out\~4) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (560:560:560)) - (PORT datab (813:813:813) (837:837:837)) - (PORT datac (159:159:159) (190:190:190)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|sda_out) - (DELAY - (ABSOLUTE - (PORT clk (1307:1307:1307) (1321:1321:1321)) - (PORT d (613:613:613) (667:667:667)) - (PORT aload (1531:1531:1531) (1581:1581:1581)) - (PORT ena (969:969:969) (993:993:993)) - (IOPATH (posedge clk) q (549:549:549) (552:552:552)) - (IOPATH (posedge aload) q (455:455:455) (458:458:458)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (75:75:75)) - (SETUP ena (posedge clk) (75:75:75)) - (HOLD d (posedge clk) (89:89:89)) - (HOLD ena (posedge clk) (89:89:89)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|mclk_r) - (DELAY - (ABSOLUTE - (PORT clk (1332:1332:1332) (1349:1349:1349)) - (PORT d (2050:2050:2050) (2113:2113:2113)) - (PORT clrn (1565:1565:1565) (1601:1601:1601)) - (IOPATH (posedge clk) q (524:524:524) (534:534:534)) - (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (77:77:77)) - (HOLD d (posedge clk) (86:86:86)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrclk_r) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1348:1348:1348)) - (PORT d (2638:2638:2638) (2696:2696:2696)) - (PORT clrn (1563:1563:1563) (1599:1599:1599)) - (IOPATH (posedge clk) q (524:524:524) (534:534:534)) - (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (77:77:77)) - (HOLD d (posedge clk) (86:86:86)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1331:1331:1331) (1348:1348:1348)) - (PORT d (3012:3012:3012) (3033:3033:3033)) - (PORT clrn (1564:1564:1564) (1600:1600:1600)) - (IOPATH (posedge clk) q (524:524:524) (534:534:534)) - (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (77:77:77)) - (HOLD d (posedge clk) (86:86:86)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bclk_r) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1347:1347:1347)) - (PORT d (1372:1372:1372) (1414:1414:1414)) - (PORT clrn (1562:1562:1562) (1599:1599:1599)) - (IOPATH (posedge clk) q (524:524:524) (534:534:534)) - (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (77:77:77)) - (HOLD d (posedge clk) (86:86:86)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|pcm_outl\[14\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1377:1377:1377)) + (PORT clk (1346:1346:1346) (1363:1363:1363)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1134:1134:1134) (1119:1119:1119)) + (PORT ena (2079:2079:2079) (2031:2031:2031)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -53620,11 +53876,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (381:381:381) (433:433:433)) - (PORT datab (1069:1069:1069) (1091:1091:1091)) - (PORT datad (340:340:340) (377:377:377)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1121:1121:1121) (1163:1163:1163)) + (PORT datac (903:903:903) (960:960:960)) + (PORT datad (609:609:609) (605:605:605)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53634,10 +53890,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1651:1651:1651) (1661:1661:1661)) + (PORT clk (1679:1679:1679) (1704:1704:1704)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (PORT ena (2545:2545:2545) (2516:2516:2516)) + (PORT clrn (1395:1395:1395) (1376:1376:1376)) + (PORT ena (1059:1059:1059) (1025:1025:1025)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53652,10 +53908,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) (DELAY (ABSOLUTE - (PORT datab (1070:1070:1070) (1090:1090:1090)) - (PORT datac (547:547:547) (571:571:571)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datac (196:196:196) (262:262:262)) + (PORT datad (610:610:610) (609:609:609)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -53664,10 +53920,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1651:1651:1651) (1661:1661:1661)) + (PORT clk (1349:1349:1349) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (PORT ena (2545:2545:2545) (2516:2516:2516)) + (PORT clrn (1395:1395:1395) (1376:1376:1376)) + (PORT ena (1094:1094:1094) (1068:1068:1068)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53682,10 +53938,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (1072:1072:1072) (1086:1086:1086)) - (PORT datac (335:335:335) (374:374:374)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datad (606:606:606) (607:607:607)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -53695,9 +53951,9 @@ (DELAY (ABSOLUTE (PORT clk (1334:1334:1334) (1351:1351:1351)) - (PORT d (1792:1792:1792) (1833:1833:1833)) + (PORT d (1371:1371:1371) (1418:1418:1418)) (PORT clrn (1567:1567:1567) (1603:1603:1603)) - (PORT ena (798:798:798) (781:781:781)) + (PORT ena (1582:1582:1582) (1591:1591:1591)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) ) @@ -53711,10 +53967,106 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[1\]\~feeder) + (INSTANCE ula_\|video_\|LessThan2\~0) (DELAY (ABSOLUTE - (PORT datad (527:527:527) (520:520:520)) + (PORT dataa (264:264:264) (341:341:341)) + (PORT datab (246:246:246) (316:316:316)) + (PORT datac (236:236:236) (305:305:305)) + (PORT datad (222:222:222) (283:283:283)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (310:310:310)) + (PORT datab (237:237:237) (305:305:305)) + (PORT datac (230:230:230) (298:298:298)) + (PORT datad (216:216:216) (274:274:274)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (479:479:479)) + (PORT datab (244:244:244) (316:316:316)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (337:337:337) (335:335:335)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (343:343:343)) + (PORT datab (220:220:220) (254:254:254)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (323:323:323)) + (PORT datab (238:238:238) (306:306:306)) + (PORT datad (224:224:224) (287:287:287)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~0) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (385:385:385) (430:430:430)) + (PORT datad (608:608:608) (642:642:642)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~1) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (236:236:236)) + (PORT datab (189:189:189) (227:227:227)) + (PORT datad (324:324:324) (328:328:328)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53724,23 +54076,86 @@ (INSTANCE ula_\|border\[1\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1134:1134:1134) (1119:1119:1119)) + (PORT clk (1349:1349:1349) (1365:1365:1365)) + (PORT asdata (485:485:485) (512:512:512)) + (PORT ena (1939:1939:1939) (1935:1935:1935)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (479:479:479)) + (PORT datab (429:429:429) (487:487:487)) + (PORT datac (394:394:394) (447:447:447)) + (PORT datad (384:384:384) (395:395:395)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (322:322:322)) + (PORT datab (248:248:248) (320:320:320)) + (PORT datad (214:214:214) (271:271:271)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (463:463:463)) + (PORT datab (426:426:426) (480:480:480)) + (PORT datac (508:508:508) (501:501:501)) + (PORT datad (602:602:602) (632:632:632)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (667:667:667)) + (PORT datab (450:450:450) (495:495:495)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (330:330:330) (328:328:328)) + (PORT datad (1363:1363:1363) (1338:1338:1338)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53750,10 +54165,10 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (1099:1099:1099) (1116:1116:1116)) - (PORT datab (1375:1375:1375) (1366:1366:1366)) - (PORT datac (1098:1098:1098) (1112:1112:1112)) - (PORT datad (805:805:805) (827:827:827)) + (PORT dataa (1152:1152:1152) (1187:1187:1187)) + (PORT datab (893:893:893) (951:951:951)) + (PORT datac (887:887:887) (938:938:938)) + (PORT datad (256:256:256) (324:324:324)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -53766,9 +54181,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1692:1692:1692) (1712:1712:1712)) + (PORT clk (1725:1725:1725) (1744:1744:1744)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1343:1343:1343) (1305:1305:1305)) + (PORT ena (1341:1341:1341) (1316:1316:1316)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -53777,25 +54192,15 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (811:811:811) (823:823:823)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (811:811:811) (832:832:832)) - (PORT datab (1117:1117:1117) (1119:1119:1119)) - (PORT datac (866:866:866) (889:889:889)) - (PORT datad (1064:1064:1064) (1063:1063:1063)) + (PORT dataa (1153:1153:1153) (1187:1187:1187)) + (PORT datab (894:894:894) (950:950:950)) + (PORT datac (887:887:887) (937:937:937)) + (PORT datad (256:256:256) (325:325:325)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -53808,14 +54213,14 @@ (INSTANCE ula_\|video_\|attr\[1\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1091:1091:1091) (1049:1049:1049)) + (PORT clk (1357:1357:1357) (1372:1372:1372)) + (PORT asdata (1649:1649:1649) (1651:1651:1651)) + (PORT ena (1303:1303:1303) (1280:1280:1280)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -53824,7 +54229,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (612:612:612) (605:605:605)) + (PORT datad (1431:1431:1431) (1390:1390:1390)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53834,9 +54239,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1723:1723:1723) (1742:1742:1742)) + (PORT clk (1725:1725:1725) (1744:1744:1744)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1155:1155:1155) (1124:1124:1124)) + (PORT ena (1341:1341:1341) (1316:1316:1316)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -53850,9 +54255,9 @@ (INSTANCE ula_\|video_\|attr\[4\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (1571:1571:1571) (1561:1561:1561)) - (PORT ena (1347:1347:1347) (1311:1311:1311)) + (PORT clk (1357:1357:1357) (1372:1372:1372)) + (PORT asdata (929:929:929) (964:964:964)) + (PORT ena (1303:1303:1303) (1280:1280:1280)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -53861,226 +54266,12 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (576:576:576) (563:563:563)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Decoder0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1118:1118:1118)) - (PORT datab (1378:1378:1378) (1365:1365:1365)) - (PORT datac (1096:1096:1096) (1110:1110:1110)) - (PORT datad (810:810:810) (829:829:829)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1688:1688:1688) (1707:1707:1707)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (2178:2178:2178) (2168:2168:2168)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (1884:1884:1884) (1927:1927:1927)) - (PORT ena (1347:1347:1347) (1311:1311:1311)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (612:612:612) (605:605:605)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1695:1695:1695) (1710:1710:1710)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1192:1192:1192) (1180:1180:1180)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (1147:1147:1147) (1166:1166:1166)) - (PORT ena (1347:1347:1347) (1311:1311:1311)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (592:592:592) (583:583:583)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1681:1681:1681) (1702:1702:1702)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1920:1920:1920) (1902:1902:1902)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (1624:1624:1624) (1649:1649:1649)) - (PORT ena (1347:1347:1347) (1311:1311:1311)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (325:325:325) (326:326:326)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1682:1682:1682) (1701:1701:1701)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (2135:2135:2135) (2132:2132:2132)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (1433:1433:1433) (1455:1455:1455)) - (PORT ena (1347:1347:1347) (1311:1311:1311)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (451:451:451)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (380:380:380) (417:417:417)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (450:450:450)) - (PORT datab (361:361:361) (401:401:401)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (326:326:326) (326:326:326)) + (PORT datad (1117:1117:1117) (1124:1124:1124)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54090,9 +54281,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1654:1654:1654) (1665:1665:1665)) + (PORT clk (1725:1725:1725) (1744:1744:1744)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1629:1629:1629) (1616:1616:1616)) + (PORT ena (1341:1341:1341) (1316:1316:1316)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54106,9 +54297,9 @@ (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (1337:1337:1337) (1352:1352:1352)) - (PORT ena (1347:1347:1347) (1311:1311:1311)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (927:927:927) (957:957:957)) + (PORT ena (1309:1309:1309) (1287:1287:1287)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54122,9 +54313,9 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT datad (1260:1260:1260) (1207:1207:1207)) + (PORT dataa (577:577:577) (563:563:563)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -54133,7 +54324,7 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT clk (1360:1360:1360) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -54147,8 +54338,8 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (622:622:622) (648:648:648)) - (PORT datab (553:553:553) (587:587:587)) + (PORT dataa (568:568:568) (589:589:589)) + (PORT datab (222:222:222) (290:290:290)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datab combout (306:306:306) (324:324:324)) @@ -54162,14 +54353,14 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (875:875:875) (862:862:862)) - (PORT ena (1596:1596:1596) (1527:1527:1527)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1137:1137:1137) (1114:1114:1114)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -54178,9 +54369,9 @@ (INSTANCE ula_\|video_\|frame\[2\]\~6) (DELAY (ABSOLUTE - (PORT datab (1000:1000:1000) (979:979:979)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (222:222:222) (295:295:295)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -54192,14 +54383,14 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (1716:1716:1716) (1734:1734:1734)) - (PORT asdata (1124:1124:1124) (1089:1089:1089)) - (PORT ena (1301:1301:1301) (1250:1250:1250)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1137:1137:1137) (1114:1114:1114)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -54208,9 +54399,9 @@ (INSTANCE ula_\|video_\|frame\[3\]\~8) (DELAY (ABSOLUTE - (PORT dataa (364:364:364) (413:413:413)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (221:221:221) (290:290:290)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -54222,9 +54413,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1179:1179:1179) (1159:1159:1159)) + (PORT ena (1137:1137:1137) (1114:1114:1114)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54238,8 +54429,8 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT datad (206:206:206) (266:266:266)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (241:241:241) (315:315:315)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH cin combout (408:408:408) (387:387:387)) ) ) @@ -54249,14 +54440,14 @@ (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (606:606:606) (607:607:607)) - (PORT ena (1179:1179:1179) (1159:1159:1159)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1137:1137:1137) (1114:1114:1114)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -54265,7 +54456,7 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (204:204:204) (261:261:261)) + (PORT datad (346:346:346) (380:380:380)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54273,22 +54464,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) + (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (330:330:330) (329:329:329)) + (PORT datad (1072:1072:1072) (1077:1077:1077)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Decoder0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1184:1184:1184)) + (PORT datab (895:895:895) (950:950:950)) + (PORT datac (886:886:886) (939:939:939)) + (PORT datad (254:254:254) (323:323:323)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[2\]) + (INSTANCE ula_\|video_\|bits_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1683:1683:1683) (1702:1702:1702)) + (PORT clk (1697:1697:1697) (1712:1712:1712)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (2118:2118:2118) (2100:2100:2100)) + (PORT ena (1345:1345:1345) (1319:1319:1319)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (568:568:568) (601:601:601)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1309:1309:1309) (1287:1287:1287)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1430:1430:1430) (1388:1388:1388)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1345:1345:1345) (1319:1319:1319)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54299,12 +54558,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[2\]) + (INSTANCE ula_\|video_\|bits\[4\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (1632:1632:1632) (1645:1645:1645)) - (PORT ena (1347:1347:1347) (1311:1311:1311)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (915:915:915) (943:943:943)) + (PORT ena (1309:1309:1309) (1287:1287:1287)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54313,12 +54572,188 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (876:876:876) (871:871:871)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1345:1345:1345) (1319:1319:1319)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (600:600:600) (633:633:633)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1309:1309:1309) (1287:1287:1287)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1123:1123:1123) (1128:1128:1128)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1345:1345:1345) (1319:1319:1319)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (1123:1123:1123) (1142:1142:1142)) + (PORT ena (1309:1309:1309) (1287:1287:1287)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (409:409:409)) + (PORT datab (258:258:258) (340:340:340)) + (PORT datad (592:592:592) (624:624:624)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (294:294:294)) + (PORT datab (255:255:255) (335:335:335)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (817:817:817) (812:812:812)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1345:1345:1345) (1319:1319:1319)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (590:590:590) (620:620:620)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1309:1309:1309) (1287:1287:1287)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (330:330:330) (328:328:328)) + (PORT datad (1359:1359:1359) (1296:1296:1296)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54328,9 +54763,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1688:1688:1688) (1708:1708:1708)) + (PORT clk (1697:1697:1697) (1712:1712:1712)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (2141:2141:2141) (2139:2139:2139)) + (PORT ena (1345:1345:1345) (1319:1319:1319)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54344,9 +54779,9 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (1105:1105:1105) (1132:1132:1132)) - (PORT ena (1347:1347:1347) (1311:1311:1311)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (902:902:902) (926:926:926)) + (PORT ena (1309:1309:1309) (1287:1287:1287)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54360,7 +54795,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (330:330:330) (328:328:328)) + (PORT datad (1360:1360:1360) (1334:1334:1334)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54370,9 +54805,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1664:1664:1664) (1675:1675:1675)) + (PORT clk (1697:1697:1697) (1712:1712:1712)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (2444:2444:2444) (2453:2453:2453)) + (PORT ena (1345:1345:1345) (1319:1319:1319)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54386,7 +54821,7 @@ (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (764:764:764) (785:785:785)) + (PORT datad (591:591:591) (619:619:619)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54396,9 +54831,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1091:1091:1091) (1049:1049:1049)) + (PORT ena (1309:1309:1309) (1287:1287:1287)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54412,8 +54847,8 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datac (584:584:584) (570:570:570)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datad (1179:1179:1179) (1117:1117:1117)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -54422,9 +54857,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT clk (1697:1697:1697) (1712:1712:1712)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1409:1409:1409) (1374:1374:1374)) + (PORT ena (1345:1345:1345) (1319:1319:1319)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54438,9 +54873,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (897:897:897) (932:932:932)) - (PORT ena (1347:1347:1347) (1311:1311:1311)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (1335:1335:1335) (1311:1311:1311)) + (PORT ena (1309:1309:1309) (1287:1287:1287)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54454,11 +54889,11 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (396:396:396) (452:452:452)) - (PORT datab (393:393:393) (428:428:428)) - (PORT datad (383:383:383) (418:418:418)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (221:221:221) (293:293:293)) + (PORT datab (255:255:255) (335:335:335)) + (PORT datad (589:589:589) (620:620:620)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54469,9 +54904,9 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (394:394:394) (452:452:452)) - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (160:160:160) (182:182:182)) + (PORT dataa (221:221:221) (293:293:293)) + (PORT datab (258:258:258) (340:340:340)) + (PORT datad (161:161:161) (182:182:182)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -54484,12 +54919,12 @@ (INSTANCE ula_\|video_\|cindex\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (867:867:867) (885:885:885)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (377:377:377) (425:425:425)) + (PORT datab (181:181:181) (215:215:215)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (299:299:299) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54500,195 +54935,25 @@ (INSTANCE ula_\|video_\|cindex\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (403:403:403) (437:437:437)) - (PORT datad (185:185:185) (209:209:209)) + (PORT dataa (223:223:223) (296:296:296)) + (PORT datad (322:322:322) (326:326:326)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (314:314:314)) - (PORT datab (238:238:238) (308:308:308)) - (PORT datac (212:212:212) (277:277:277)) - (PORT datad (214:214:214) (271:271:271)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (411:411:411) (458:458:458)) - (PORT datab (264:264:264) (338:338:338)) - (PORT datac (376:376:376) (420:420:420)) - (PORT datad (340:340:340) (341:341:341)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (459:459:459)) - (PORT datab (248:248:248) (319:319:319)) - (PORT datac (219:219:219) (290:290:290)) - (PORT datad (373:373:373) (414:414:414)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (667:667:667)) - (PORT datab (390:390:390) (439:439:439)) - (PORT datac (601:601:601) (635:635:635)) - (PORT datad (527:527:527) (523:523:523)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~1) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (677:677:677)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (827:827:827) (827:827:827)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (343:343:343)) - (PORT datab (247:247:247) (318:318:318)) - (PORT datac (238:238:238) (308:308:308)) - (PORT datad (240:240:240) (300:300:300)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (432:432:432) (475:475:475)) - (PORT datab (262:262:262) (334:334:334)) - (PORT datac (182:182:182) (219:219:219)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (208:208:208) (244:244:244)) - (PORT datac (393:393:393) (437:437:437)) - (PORT datad (222:222:222) (283:283:283)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT datab (237:237:237) (305:305:305)) - (PORT datad (219:219:219) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~0) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (320:320:320)) - (PORT datab (239:239:239) (308:308:308)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~1) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datad (587:587:587) (586:586:586)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (2048:2048:2048) (2089:2089:2089)) - (PORT datab (188:188:188) (224:224:224)) - (PORT datac (1352:1352:1352) (1341:1341:1341)) - (PORT datad (531:531:531) (521:521:521)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (372:372:372) (405:405:405)) + (PORT datab (1379:1379:1379) (1403:1403:1403)) + (PORT datac (212:212:212) (254:254:254)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54699,7 +54964,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (575:575:575) (559:559:559)) + (PORT datad (1074:1074:1074) (1080:1080:1080)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54709,9 +54974,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1659:1659:1659) (1670:1670:1670)) + (PORT clk (1725:1725:1725) (1744:1744:1744)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (2228:2228:2228) (2238:2238:2238)) + (PORT ena (1341:1341:1341) (1316:1316:1316)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54725,9 +54990,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) - (PORT asdata (1880:1880:1880) (1894:1894:1894)) - (PORT ena (1354:1354:1354) (1325:1325:1325)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT asdata (1117:1117:1117) (1123:1123:1123)) + (PORT ena (1513:1513:1513) (1457:1457:1457)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54741,11 +55006,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (613:613:613) (598:598:598)) - (PORT datab (596:596:596) (579:579:579)) - (PORT datad (587:587:587) (586:586:586)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (194:194:194) (237:237:237)) + (PORT datab (189:189:189) (228:228:228)) + (PORT datad (325:325:325) (328:328:328)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54756,11 +55021,11 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1380:1380:1380) (1374:1374:1374)) - (PORT datab (188:188:188) (226:226:226)) - (PORT datad (300:300:300) (310:310:310)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (243:243:243) (290:290:290)) + (PORT datac (364:364:364) (382:382:382)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54770,9 +55035,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1377:1377:1377)) - (PORT asdata (490:490:490) (518:518:518)) - (PORT ena (1134:1134:1134) (1119:1119:1119)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (882:882:882) (867:867:867)) + (PORT ena (735:735:735) (734:734:734)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54786,7 +55051,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (325:325:325) (326:326:326)) + (PORT datad (817:817:817) (811:811:811)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54796,9 +55061,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1654:1654:1654) (1665:1665:1665)) + (PORT clk (1725:1725:1725) (1744:1744:1744)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1923:1923:1923) (1927:1927:1927)) + (PORT ena (1341:1341:1341) (1316:1316:1316)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54812,9 +55077,9 @@ (INSTANCE ula_\|video_\|attr\[2\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (1598:1598:1598) (1624:1624:1624)) - (PORT ena (1347:1347:1347) (1311:1311:1311)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (1104:1104:1104) (1120:1120:1120)) + (PORT ena (1309:1309:1309) (1287:1287:1287)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54828,7 +55093,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (592:592:592) (581:581:581)) + (PORT datad (874:874:874) (869:869:869)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54838,9 +55103,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1652:1652:1652) (1665:1665:1665)) + (PORT clk (1725:1725:1725) (1744:1744:1744)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1733:1733:1733) (1738:1738:1738)) + (PORT ena (1341:1341:1341) (1316:1316:1316)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54854,9 +55119,9 @@ (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (1427:1427:1427) (1478:1478:1478)) - (PORT ena (1347:1347:1347) (1311:1311:1311)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (910:910:910) (932:932:932)) + (PORT ena (1309:1309:1309) (1287:1287:1287)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54870,9 +55135,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (294:294:294)) - (PORT datad (187:187:187) (212:212:212)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datad (185:185:185) (209:209:209)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54883,13 +55148,13 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1890:1890:1890) (1959:1959:1959)) - (PORT datab (555:555:555) (554:554:554)) - (PORT datac (1353:1353:1353) (1342:1342:1342)) - (PORT datad (168:168:168) (195:195:195)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (2150:2150:2150) (2222:2222:2222)) + (PORT datab (379:379:379) (407:407:407)) + (PORT datac (355:355:355) (376:376:376)) + (PORT datad (510:510:510) (500:500:500)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54899,33 +55164,49 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1381:1381:1381) (1372:1372:1372)) - (PORT datab (192:192:192) (228:228:228)) - (PORT datad (300:300:300) (308:308:308)) + (PORT dataa (594:594:594) (592:592:592)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datad (352:352:352) (352:352:352)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (184:184:184) (209:209:209)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1377:1377:1377)) + (PORT clk (1349:1349:1349) (1365:1365:1365)) + (PORT asdata (1352:1352:1352) (1356:1356:1356)) + (PORT ena (1939:1939:1939) (1935:1935:1935)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1358:1358:1358) (1299:1299:1299)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1725:1725:1725) (1744:1744:1744)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1134:1134:1134) (1119:1119:1119)) + (PORT ena (1341:1341:1341) (1316:1316:1316)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54936,22 +55217,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (INSTANCE ula_\|video_\|attr\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (330:330:330) (328:328:328)) + (PORT datad (782:782:782) (789:789:789)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (INSTANCE ula_\|video_\|attr\[0\]) (DELAY (ABSOLUTE - (PORT clk (1660:1660:1660) (1671:1671:1671)) + (PORT clk (1357:1357:1357) (1372:1372:1372)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1409:1409:1409) (1402:1402:1402)) + (PORT ena (1303:1303:1303) (1280:1280:1280)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1179:1179:1179) (1118:1118:1118)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1725:1725:1725) (1744:1744:1744)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1341:1341:1341) (1316:1316:1316)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54960,46 +55267,14 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (1119:1119:1119) (1138:1138:1138)) - (PORT ena (1091:1091:1091) (1049:1049:1049)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1659:1659:1659) (1668:1668:1668)) - (PORT asdata (1141:1141:1141) (1111:1111:1111)) - (PORT ena (1647:1647:1647) (1628:1628:1628)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1372:1372:1372)) - (PORT asdata (823:823:823) (844:844:844)) - (PORT ena (1091:1091:1091) (1049:1049:1049)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (884:884:884) (917:917:917)) + (PORT ena (1309:1309:1309) (1287:1287:1287)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55013,9 +55288,9 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (293:293:293)) - (PORT datad (326:326:326) (332:332:332)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT datab (358:358:358) (403:403:403)) + (PORT datad (186:186:186) (210:210:210)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55026,13 +55301,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (2030:2030:2030) (2083:2083:2083)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (506:506:506) (491:491:491)) - (PORT datad (491:491:491) (480:480:480)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (372:372:372) (405:405:405)) + (PORT datab (1541:1541:1541) (1559:1559:1559)) + (PORT datac (210:210:210) (254:254:254)) + (PORT datad (311:311:311) (320:320:320)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55042,9 +55317,9 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (801:801:801) (767:767:767)) - (PORT datac (532:532:532) (530:530:530)) - (PORT datad (540:540:540) (537:537:537)) + (PORT dataa (243:243:243) (290:290:290)) + (PORT datac (364:364:364) (381:381:381)) + (PORT datad (316:316:316) (325:325:325)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -55056,11 +55331,11 @@ (INSTANCE ula_\|video_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (1425:1425:1425) (1443:1443:1443)) - (PORT datac (1091:1091:1091) (1119:1119:1119)) - (PORT datad (1077:1077:1077) (1092:1092:1092)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (636:636:636) (662:662:662)) + (PORT datab (256:256:256) (325:325:325)) + (PORT datad (601:601:601) (629:629:629)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55070,7 +55345,7 @@ (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT clk (1357:1357:1357) (1372:1372:1372)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -55084,11 +55359,11 @@ (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (322:322:322) (336:336:336)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datad (186:186:186) (209:209:209)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (946:946:946) (919:919:919)) + (PORT datab (207:207:207) (244:244:244)) + (PORT datad (529:529:529) (511:511:511)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55100,7 +55375,7 @@ (DELAY (ABSOLUTE (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (1571:1571:1571) (1611:1611:1611)) + (PORT d (1573:1573:1573) (1534:1534:1534)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -55114,7 +55389,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT clk (1360:1360:1360) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -55128,11 +55403,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (242:242:242)) - (PORT datab (671:671:671) (707:707:707)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (576:576:576) (562:562:562)) + (PORT datab (1088:1088:1088) (1059:1059:1059)) + (PORT datad (635:635:635) (679:679:679)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55144,7 +55419,7 @@ (DELAY (ABSOLUTE (PORT clk (1333:1333:1333) (1351:1351:1351)) - (PORT d (1432:1432:1432) (1496:1496:1496)) + (PORT d (1652:1652:1652) (1646:1646:1646)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -55158,7 +55433,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (233:233:233) (296:296:296)) + (PORT datad (576:576:576) (598:598:598)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55168,10 +55443,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) + (PORT clk (1359:1359:1359) (1380:1380:1380)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (PORT ena (1120:1120:1120) (1095:1095:1095)) + (PORT clrn (1405:1405:1405) (1376:1376:1376)) + (PORT ena (1358:1358:1358) (1339:1339:1339)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55186,10 +55461,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) + (PORT clk (1359:1359:1359) (1380:1380:1380)) (PORT asdata (507:507:507) (569:569:569)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (PORT ena (1120:1120:1120) (1095:1095:1095)) + (PORT clrn (1405:1405:1405) (1376:1376:1376)) + (PORT ena (1358:1358:1358) (1339:1339:1339)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55204,7 +55479,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (227:227:227) (289:289:289)) + (PORT datad (577:577:577) (598:598:598)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55215,9 +55490,9 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT dataa (629:629:629) (703:703:703)) - (PORT datad (230:230:230) (292:292:292)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT datac (1191:1191:1191) (1223:1223:1223)) + (PORT datad (578:578:578) (601:601:601)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55227,12 +55502,10 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT dataa (769:769:769) (763:763:763)) - (PORT datab (845:845:845) (862:862:862)) - (PORT datac (800:800:800) (804:804:804)) - (PORT datad (639:639:639) (688:688:688)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datab (1602:1602:1602) (1633:1633:1633)) + (PORT datac (2798:2798:2798) (3004:3004:3004)) + (PORT datad (1172:1172:1172) (1181:1181:1181)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55243,9 +55516,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1379:1379:1379)) + (PORT clk (1337:1337:1337) (1355:1355:1355)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1365:1365:1365) (1315:1315:1315)) + (PORT ena (2376:2376:2376) (2363:2363:2363)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo index f4799e2..ef4a25d 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/31/2022 14:04:23" +// DATE "04/01/2022 18:55:51" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -49,14 +49,15 @@ module spectrum ( VGA_VS, SW, GPIO_1, - buzzer_out); + buzzer_out, + raw_loader_in); output [7:0] LED; input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -inout I2C_SCLK; -inout I2C_SDAT; +output I2C_SCLK; +output I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -71,6 +72,7 @@ output VGA_VS; input [3:0] SW; output [33:0] GPIO_1; output buzzer_out; +input raw_loader_in; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -141,10 +143,11 @@ output buzzer_out; // I2C_SDAT => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[1] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: Default // SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// raw_loader_in => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: Default // KEY[0] => Location: PIN_J15, I/O Standard: 3.3-V LVTTL, Current Strength: Default // CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default -// KEY[1] => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_DAT => Location: PIN_B7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// KEY[1] => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_CLK => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default // AUD_ADCDAT => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -175,7 +178,692 @@ wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; +wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; wire \z80_|sequencer_|ena_M~combout ; +wire \KEY[1]~input_o ; +wire \z80_|interrupts_|nmi_armed~feeder_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; +wire \z80_|interrupts_|nmi_armed~q ; +wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~q ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~q ; +wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal1~7_combout ; +wire \z80_|pla_decode_|Equal2~0_combout ; +wire \z80_|pla_decode_|Equal36~0_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|pla_decode_|Equal2~1_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_sw_1d~8_combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~1_combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; +wire \z80_|execute_|ctl_state_iy_set~2_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|pla_decode_|Equal50~0_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|execute_|ixy_d~17_combout ; +wire \z80_|execute_|ixy_d~5_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~15_combout ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|execute_|ctl_ir_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~14_combout ; +wire \z80_|execute_|ctl_mWrite~2_combout ; +wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|ctl_reg_in_hi~5_combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|pla_decode_|Equal9~0_combout ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|pla_decode_|Equal9~1_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|pla_decode_|Equal1~4_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; +wire \z80_|pla_decode_|Equal24~1_combout ; +wire \z80_|pla_decode_|Equal34~0_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|sequencer_|M5~0_combout ; +wire \z80_|sequencer_|M5~q ; +wire \z80_|execute_|ctl_reg_in_hi~2_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; +wire \z80_|execute_|ctl_ir_we~7_combout ; +wire \z80_|pla_decode_|Equal52~1_combout ; +wire \z80_|execute_|ctl_state_alu~14_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|execute_|fMRead~17_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|fMRead~16_combout ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_flags_alu~6_combout ; +wire \z80_|execute_|ctl_ir_we~6_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_reg_in_hi~3_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; +wire \z80_|execute_|ctl_mRead~36_combout ; +wire \z80_|execute_|ctl_alu_op_low~9_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|execute_|ctl_alu_op_low~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|alu_|db_low[2]~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|pla_decode_|Equal1~5_combout ; +wire \z80_|execute_|ctl_alu_op_low~14_combout ; +wire \z80_|execute_|ctl_alu_op_low~12_combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~11_combout ; +wire \z80_|execute_|nextM~2_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_oe~3_combout ; +wire \z80_|execute_|ctl_alu_op_low~15_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~13_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|ctl_flags_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op_low~13_combout ; +wire \z80_|execute_|ctl_flags_bus~15_combout ; +wire \z80_|execute_|ctl_flags_bus~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|execute_|ctl_flags_bus~12_combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_bus_db_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|execute_|ctl_alu_op_low~10_combout ; +wire \z80_|execute_|fMWrite~11_combout ; +wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|execute_|ctl_alu_op_low~22_combout ; +wire \z80_|execute_|ctl_alu_op_low~16_combout ; +wire \z80_|execute_|ctl_alu_op_low~17_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_gp_sel~36_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_alu_op_low~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~19_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_alu_op_low~20_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~14_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|execute_|ctl_flags_alu~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|pla_decode_|Equal11~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; +wire \z80_|execute_|ctl_alu_oe~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_oe~15_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; +wire \z80_|alu_|db_low[2]~24_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_alu_oe~12_combout ; +wire \z80_|execute_|ctl_alu_oe~13_combout ; +wire \z80_|execute_|ctl_alu_oe~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; +wire \z80_|execute_|ctl_reg_out_hi~8_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|execute_|ctl_sw_2u~1_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_inc_cy~35_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_mWrite~6_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_sw_2u~0_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~7_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|execute_|ctl_inc_cy~34_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~92_combout ; +wire \z80_|pla_decode_|Equal19~1_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_inc_cy~38_combout ; +wire \z80_|execute_|ctl_inc_cy~93_combout ; +wire \z80_|execute_|ctl_inc_cy~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; +wire \z80_|execute_|ctl_reg_gp_we~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|fMRead~3_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; +wire \z80_|execute_|ctl_inc_cy~94_combout ; +wire \z80_|execute_|ctl_inc_cy~87_combout ; +wire \z80_|execute_|ctl_inc_cy~42_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|pla_decode_|Equal1~6_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~12_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~13_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|fMWrite~3_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~7_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_sw_1d~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|execute_|setM1~47_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_al_we~13_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_reg_in_hi~13_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_inc_cy~40_combout ; +wire \z80_|execute_|ctl_inc_dec~2_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_inc_cy~43_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_state_alu~13_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_state_alu~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|reg_control_|reg_sel_de2~5_combout ; +wire \z80_|reg_control_|reg_sel_de2~6_combout ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_al_we~14_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|ctl_flags_bus~13_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|pc_inc_hold~49_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|fMRead~5_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; +wire \z80_|execute_|pc_inc_hold~29_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|execute_|ctl_reg_in_hi~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; +wire \z80_|execute_|fMRead~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; +wire \z80_|execute_|fMRead~1_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|ctl_sw_4d~1_combout ; +wire \z80_|execute_|ctl_sw_4d~0_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|execute_|fMRead~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; wire \KEY[0]~input_o ; wire \reset~combout ; @@ -184,801 +872,92 @@ wire \z80_|fpga_reset~feeder_combout ; wire \z80_|fpga_reset~q ; wire \z80_|fpga_reset~clkctrl_outclk ; wire \z80_|resets_|x1~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \KEY[1]~input_o ; -wire \z80_|interrupts_|nmi_armed~feeder_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; -wire \z80_|interrupts_|nmi_armed~q ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|execute_|ctl_ir_we~4_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|pla_decode_|Equal9~0_combout ; -wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|sequencer_|M5~0_combout ; -wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; -wire \z80_|execute_|ctl_mWrite~3_combout ; -wire \z80_|execute_|ctl_mWrite~16_combout ; -wire \z80_|execute_|ixy_d~4_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|pla_decode_|Equal41~1_combout ; -wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ixy_d~8_combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|pla_decode_|Equal19~0_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|execute_|ctl_state_alu~2_combout ; -wire \z80_|execute_|ctl_inc_cy~36_combout ; -wire \z80_|execute_|ctl_inc_dec~0_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|fMWrite~0_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|pla_decode_|Equal19~1_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; -wire \z80_|execute_|ctl_state_alu~3_combout ; -wire \z80_|execute_|ctl_inc_cy~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|execute_|ctl_inc_cy~30_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|fMWrite~1_combout ; -wire \z80_|execute_|fMWrite~2_combout ; -wire \z80_|execute_|fMWrite~3_combout ; -wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|execute_|ctl_inc_cy~34_combout ; -wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|execute_|ctl_inc_cy~35_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|execute_|ctl_mRead~38_combout ; -wire \z80_|execute_|fIOWrite~1_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|execute_|fMRead~2_combout ; -wire \z80_|execute_|ctl_mWrite~2_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|execute_|ctl_inc_cy~32_combout ; -wire \z80_|execute_|ctl_inc_cy~33_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; -wire \z80_|address_pins_|abus[0]~18_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|WideOr16~5_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|WideOr16~7_combout ; -wire \ula_|zx_keyboard_|WideOr16~6_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|pc_inc_hold~19_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|ctl_inc_cy~37_combout ; -wire \z80_|execute_|ctl_inc_dec~1_combout ; -wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; wire \z80_|resets_|clrpc_int~0_combout ; wire \z80_|resets_|clrpc_int~q ; wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|execute_|ctl_inc_cy~47_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|execute_|ctl_inc_cy~38_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|fMRead~12_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~3_combout ; -wire \z80_|execute_|fMRead~13_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~25_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|nextM~11_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~8_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_reg_in_hi~13_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_we~9_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_we~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~8_combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_sel~5_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|pla_decode_|Equal11~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|ctl_iorw~12_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; -wire \z80_|execute_|ctl_bus_db_oe~2_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|pla_decode_|Equal76~0_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~7_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; -wire \z80_|execute_|setM1~56_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~40_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|pc_inc_hold~18_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ; -wire \z80_|execute_|pc_inc_hold~40_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~11_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|ctl_alu_op_low~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_flags_alu~6_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_flags_alu~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~19_combout ; -wire \z80_|execute_|ctl_flags_alu~7_combout ; -wire \z80_|execute_|ctl_flags_alu~9_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|reg_control_|reg_sel_de2~6_combout ; -wire \z80_|reg_control_|reg_sel_de2~5_combout ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~22_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; -wire \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~23_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~24_combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~26_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~25_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~39_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|fMRead~11_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~28_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~29_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~30_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_bus_db_oe~6_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|fMRead~9_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|alu_|db[7]~19_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~52_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~53_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~56_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_file_|db_hi_as[3]~13_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|db_hi_as[3]~14_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; wire \z80_|execute_|ctl_apin_mux~1_combout ; wire \z80_|execute_|ctl_al_we~6_combout ; wire \z80_|execute_|ctl_al_we~7_combout ; wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; wire \z80_|execute_|ctl_al_we~11_combout ; wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|execute_|ctl_inc_cy~78_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|reg_file_|db_hi_as[3]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~57_combout ; -wire \z80_|alu_|db[3]~13_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_sz_we~5_combout ; -wire \z80_|execute_|ctl_flags_sz_we~6_combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_flags_xy_we~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~14_combout ; -wire \z80_|execute_|ctl_flags_xy_we~15_combout ; -wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[3]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|Add0~15 ; wire \ula_|video_|Add0~16_combout ; wire \ula_|video_|vga_hc~2_combout ; wire \ula_|video_|Add0~17 ; wire \ula_|video_|Add0~18_combout ; wire \ula_|video_|vga_hc~1_combout ; -wire \ula_|video_|Equal0~0_combout ; -wire \ula_|video_|Equal0~1_combout ; -wire \ula_|video_|Equal1~0_combout ; +wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; wire \ula_|video_|Add0~1 ; wire \ula_|video_|Add0~2_combout ; +wire \ula_|video_|vga_hc[1]~feeder_combout ; wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; -wire \ula_|video_|vga_hc[2]~feeder_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; +wire \ula_|video_|vga_hc[3]~feeder_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; +wire \ula_|video_|Equal0~0_combout ; +wire \ula_|video_|Equal0~1_combout ; +wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add0~9 ; wire \ula_|video_|Add0~10_combout ; wire \ula_|video_|vga_hc~0_combout ; @@ -987,8 +966,6 @@ wire \ula_|video_|Add0~12_combout ; wire \ula_|video_|Add0~13 ; wire \ula_|video_|Add0~14_combout ; wire \ula_|video_|Add1~0_combout ; -wire \ula_|video_|vga_vc[0]~0_combout ; -wire \ula_|video_|Add1~1 ; wire \ula_|video_|Add1~3 ; wire \ula_|video_|Add1~4_combout ; wire \ula_|video_|vga_vc[2]~2_combout ; @@ -1010,22 +987,24 @@ wire \ula_|video_|vga_vc[7]~6_combout ; wire \ula_|video_|Add1~15 ; wire \ula_|video_|Add1~16_combout ; wire \ula_|video_|vga_vc[8]~7_combout ; -wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Add1~17 ; wire \ula_|video_|Add1~18_combout ; wire \ula_|video_|vga_vc[9]~9_combout ; +wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~0_combout ; wire \ula_|video_|Equal3~1_combout ; +wire \ula_|video_|vga_vc[0]~0_combout ; +wire \ula_|video_|Add1~1 ; wire \ula_|video_|Add1~2_combout ; wire \ula_|video_|vga_vc[1]~1_combout ; wire \SW[1]~input_o ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|iff1~0_combout ; wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; wire \z80_|interrupts_|DFFE_instIFF2~q ; +wire \z80_|interrupts_|iff1~0_combout ; wire \z80_|interrupts_|iff1~1_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; wire \z80_|interrupts_|iff1~q ; @@ -1033,875 +1012,787 @@ wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|interrupts_|int_armed~q ; -wire \z80_|interrupts_|DFFE_inst44~feeder_combout ; wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_cy~49_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~22_combout ; -wire \z80_|execute_|pc_inc_hold~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~23_combout ; -wire \z80_|execute_|pc_inc_hold~25_combout ; -wire \z80_|execute_|pc_inc_hold~20_combout ; -wire \z80_|execute_|pc_inc_hold~41_combout ; -wire \z80_|execute_|pc_inc_hold~21_combout ; -wire \z80_|execute_|pc_inc_hold~26_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|ctl_inc_cy~43_combout ; -wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~42_combout ; -wire \z80_|execute_|pc_inc_hold~27_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|ctl_inc_cy~40_combout ; -wire \z80_|execute_|ctl_inc_cy~41_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~42_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; -wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|pc_inc_hold~38_combout ; +wire \z80_|execute_|ctl_inc_cy~91_combout ; +wire \z80_|execute_|pc_inc_hold~45_combout ; +wire \z80_|execute_|pc_inc_hold~44_combout ; +wire \z80_|execute_|pc_inc_hold~46_combout ; +wire \z80_|execute_|pc_inc_hold~37_combout ; +wire \z80_|execute_|pc_inc_hold~50_combout ; wire \z80_|execute_|pc_inc_hold~33_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~31_combout ; +wire \z80_|execute_|pc_inc_hold~32_combout ; +wire \z80_|execute_|pc_inc_hold~34_combout ; +wire \z80_|execute_|pc_inc_hold~51_combout ; +wire \z80_|execute_|pc_inc_hold~30_combout ; +wire \z80_|execute_|pc_inc_hold~52_combout ; +wire \z80_|execute_|pc_inc_hold~35_combout ; +wire \z80_|execute_|pc_inc_hold~36_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|pc_inc_hold~43_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_inc_cy~46_combout ; +wire \z80_|execute_|pc_inc_hold~53_combout ; +wire \z80_|execute_|pc_inc_hold~39_combout ; +wire \z80_|execute_|pc_inc_hold~47_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|execute_|ctl_inc_cy~78_combout ; +wire \z80_|execute_|ctl_inc_cy~79_combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~82_combout ; +wire \z80_|execute_|ctl_inc_cy~83_combout ; +wire \z80_|execute_|ctl_inc_cy~84_combout ; +wire \z80_|execute_|pc_inc_hold~42_combout ; +wire \z80_|execute_|ctl_inc_cy~90_combout ; +wire \z80_|execute_|pc_inc_hold~41_combout ; wire \z80_|execute_|ctl_inc_cy~66_combout ; wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~31_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op_low~39_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|pla_decode_|Equal72~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~0_combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; -wire \z80_|execute_|ctl_flags_nf_we~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|execute_|ctl_alu_op_low~38_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_alu_core_R~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~35_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|alu_|db_high[3]~0_combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|alu_|db_high[3]~1_combout ; -wire \z80_|alu_|db_low[3]~2_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|alu_|db_low[3]~3_combout ; -wire \z80_|alu_|db_low[3]~4_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|db_high[2]~25_combout ; -wire \z80_|reg_file_|db_hi_as[6]~0_combout ; -wire \z80_|reg_file_|db_hi_as[6]~1_combout ; -wire \z80_|reg_file_|db_hi_as[6]~3_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~14_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~8_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~21_combout ; -wire \z80_|interrupts_|im2~feeder_combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|sw1_|db_down[6]~0_combout ; -wire \z80_|alu_|db_low[1]~10_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|alu_|db_high[1]~3_combout ; -wire \z80_|alu_|db_high[1]~2_combout ; -wire \z80_|alu_|db[7]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~74_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~75_combout ; -wire \z80_|alu_|db[5]~23_combout ; -wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~22_combout ; -wire \z80_|reg_file_|db_hi_as[4]~23_combout ; -wire \z80_|reg_file_|db_hi_as[4]~24_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~77_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~79_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~82_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~84_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_inc_cy~36_combout ; +wire \z80_|execute_|ctl_inc_cy~37_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~41_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~89_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|execute_|ctl_inc_cy~48_combout ; +wire \z80_|execute_|pc_inc_hold~40_combout ; +wire \z80_|execute_|ctl_inc_cy~61_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|ctl_inc_cy~85_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|address_latch_|Q[0]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_|alu_op1[2]~2_combout ; -wire \z80_|alu_|alu_op1[1]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|db[1]~15_combout ; -wire \z80_|alu_|db[1]~16_combout ; -wire \z80_|reg_file_|db_hi_as[0]~10_combout ; -wire \z80_|reg_file_|db_hi_as[0]~11_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; -wire \z80_|reg_file_|db_lo_as[6]~19_combout ; -wire \z80_|reg_file_|db_lo_as[6]~20_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; -wire \z80_|reg_file_|db_lo_as[5]~16_combout ; -wire \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|db_lo_as[5]~17_combout ; -wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|Q[5]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|db_lo_as[6]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|address_latch_|Q[7]~feeder_combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; +wire \z80_|address_latch_|Q[2]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; +wire \z80_|execute_|ctl_inc_cy~86_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; +wire \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|db_hi_as[1]~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|reg_file_|db_hi_as[0]~2_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~41_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~44_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~45_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~43_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~46_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~40_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~47_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~48_combout ; -wire \z80_|alu_|db[0]~17_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_low[0]~16_combout ; -wire \z80_|alu_|db_low[0]~17_combout ; -wire \z80_|alu_|db_low[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|reg_file_|db_hi_as[0]~4_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[1]~3_combout ; +wire \z80_|address_latch_|Q[9]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; +wire \z80_|reg_file_|db_hi_as[2]~7_combout ; +wire \z80_|reg_file_|db_hi_as[2]~8_combout ; +wire \z80_|reg_file_|db_hi_as[2]~9_combout ; +wire \z80_|address_latch_|Q[10]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|db_hi_as[3]~10_combout ; +wire \z80_|reg_file_|db_hi_as[3]~11_combout ; +wire \z80_|reg_file_|db_hi_as[3]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|alu_|alu_op1[3]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~20_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~21_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_flags_sz_we~4_combout ; +wire \z80_|pla_decode_|Equal71~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; +wire \z80_|pla_decode_|Equal72~2_combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|execute_|ctl_flags_nf_we~1_combout ; +wire \z80_|execute_|ctl_flags_nf_we~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; +wire \z80_|execute_|ctl_flags_sz_we~5_combout ; +wire \z80_|execute_|ctl_flags_sz_we~6_combout ; +wire \z80_|execute_|ctl_flags_nf_we~4_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|ctl_flags_xy_we~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~7_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; +wire \z80_|execute_|ctl_flags_alu~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~19_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|alu_|alu_op2[1]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~38_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~43_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|execute_|ctl_alu_core_hf~42_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~41_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~44_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~39_combout ; +wire \z80_|execute_|ctl_alu_core_hf~40_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ; +wire \z80_|alu_|alu_op2[3]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; wire \z80_|execute_|ctl_flags_hf_we~3_combout ; wire \z80_|execute_|ctl_flags_hf_we~4_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_alu_core_hf~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|execute_|ctl_alu_core_hf~16_combout ; -wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; -wire \z80_|execute_|ctl_flags_nf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~9_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|execute_|ctl_alu_core_hf~15_combout ; -wire \z80_|execute_|ctl_alu_core_hf~17_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|execute_|ctl_alu_core_hf~39_combout ; -wire \z80_|execute_|ctl_alu_core_hf~40_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; -wire \z80_|alu_|db_high[0]~8_combout ; -wire \z80_|alu_|db_high[0]~9_combout ; -wire \z80_|alu_|db_high[0]~10_combout ; -wire \z80_|alu_|db_high[0]~11_combout ; -wire \z80_|alu_|db_high[0]~12_combout ; -wire \z80_|alu_|db_high[0]~13_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|alu_|alu_op2[0]~1_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_low[0]~18_combout ; -wire \z80_|alu_|db_low[0]~20_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|address_latch_|Q[12]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[4]~16_combout ; +wire \z80_|reg_file_|db_hi_as[4]~17_combout ; +wire \z80_|reg_file_|db_hi_as[4]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; +wire \z80_|alu_|db[4]~16_combout ; +wire \z80_|alu_|db[7]~26_combout ; +wire \z80_|alu_|db[4]~17_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|db_high[0]~26_combout ; wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|alu_op1[0]~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|alu_|alu_op1[0]~1_combout ; wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|alu_op1[1]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|alu_|alu_op1[2]~2_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|alu_|db_low[2]~7_combout ; -wire \z80_|alu_|db_low[2]~8_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~63_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~61_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~64_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~58_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~65_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~66_combout ; -wire \z80_|alu_|db[2]~11_combout ; -wire \z80_|alu_|db[2]~12_combout ; -wire \z80_|alu_|db_low[2]~5_combout ; -wire \z80_|alu_|db_low[2]~6_combout ; -wire \z80_|alu_|db_low[2]~9_combout ; -wire \z80_|alu_|db_low[2]~22_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|alu_control_|db[2]~19_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; +wire \z80_|reg_file_|db_hi_as[7]~19_combout ; +wire \z80_|reg_file_|db_hi_as[7]~20_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; +wire \z80_|reg_file_|db_hi_as[5]~13_combout ; +wire \z80_|reg_file_|db_hi_as[5]~14_combout ; +wire \z80_|reg_file_|db_hi_as[5]~15_combout ; +wire \z80_|address_latch_|Q[13]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; +wire \z80_|reg_file_|db_hi_as[6]~22_combout ; +wire \z80_|reg_file_|db_hi_as[6]~23_combout ; +wire \z80_|reg_file_|db_hi_as[6]~24_combout ; +wire \z80_|address_latch_|Q[14]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|reg_file_|db_hi_as[7]~21_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; +wire \z80_|alu_|db[7]~20_combout ; +wire \z80_|alu_|db[7]~21_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~4_combout ; +wire \z80_|alu_|db_high[3]~27_combout ; +wire \z80_|alu_|db_high[3]~7_combout ; +wire \z80_|alu_|db_high[3]~8_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ; +wire \z80_|alu_|db_low[3]~9_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|alu_|db_low[3]~10_combout ; +wire \z80_|alu_|db_low[3]~7_combout ; +wire \z80_|alu_|db_low[3]~8_combout ; +wire \z80_|alu_|db_low[3]~11_combout ; +wire \z80_|alu_|db_low[3]~25_combout ; +wire \z80_|alu_|db[3]~10_combout ; +wire \z80_|alu_|db[3]~11_combout ; wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|alu_control_|db[1]~23_combout ; -wire \z80_|alu_control_|db[1]~24_combout ; -wire \z80_|alu_control_|db[1]~25_combout ; -wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|Q[1]~feeder_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; -wire \z80_|alu_control_|db[4]~30_combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \z80_|alu_|db[4]~8_combout ; -wire \z80_|alu_|db[4]~10_combout ; -wire \z80_|alu_|db_high[1]~4_combout ; -wire \z80_|alu_|db_high[1]~5_combout ; -wire \z80_|alu_|db_high[1]~6_combout ; -wire \z80_|alu_|db_high[1]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|alu_op2[1]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; -wire \z80_|alu_|db_low[1]~11_combout ; -wire \z80_|alu_|db_low[1]~12_combout ; -wire \z80_|alu_|db_low[1]~13_combout ; -wire \z80_|alu_|db_low[1]~14_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_control_|db[6]~13_combout ; -wire \z80_|alu_control_|db[6]~14_combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; +wire \z80_|execute_|ctl_flags_xy_we~13_combout ; +wire \z80_|execute_|ctl_flags_xy_we~14_combout ; +wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|alu_flags_|flags_xf~q ; +wire \z80_|alu_control_|db[3]~33_combout ; wire \z80_|execute_|ctl_reg_out_lo~3_combout ; wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; wire \z80_|execute_|ctl_reg_out_lo~4_combout ; wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; -wire \z80_|alu_control_|db[6]~15_combout ; -wire \z80_|alu_|db[6]~21_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db_high[2]~20_combout ; -wire \z80_|alu_|db_high[2]~21_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout ; -wire \z80_|alu_|db_high[2]~22_combout ; -wire \z80_|alu_|db_high[2]~23_combout ; -wire \z80_|alu_|db_high[2]~24_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|alu_op2[2]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~37_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~11_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|alu_control_|db[0]~8_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~9_combout ; -wire \z80_|alu_control_|db[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|sw1_|db_down[3]~1_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; -wire \z80_|sw1_|db_down[3]~2_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|alu_|db[3]~14_combout ; -wire \z80_|alu_|db_low[3]~0_combout ; -wire \z80_|alu_|db_low[3]~1_combout ; -wire \z80_|alu_|db_low[3]~23_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout ; -wire \z80_|alu_|alu_op2[3]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ; -wire \z80_|alu_|db_high[3]~14_combout ; -wire \z80_|alu_|db_high[3]~15_combout ; -wire \z80_|alu_|db_high[3]~16_combout ; -wire \z80_|alu_|db_high[3]~17_combout ; -wire \z80_|alu_|db_high[3]~18_combout ; -wire \z80_|alu_|db_high[3]~19_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_control_|db[7]~16_combout ; -wire \z80_|reg_file_|db_lo_ds[7]~1_combout ; +wire \z80_|reg_file_|db_lo_as[3]~10_combout ; +wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|reg_file_|db_lo_as[3]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; +wire \z80_|reg_file_|db_lo_as[4]~13_combout ; +wire \z80_|reg_file_|db_lo_as[4]~14_combout ; +wire \z80_|reg_file_|db_lo_as[4]~15_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; +wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; +wire \z80_|reg_file_|db_lo_as[5]~16_combout ; +wire \z80_|reg_file_|db_lo_as[5]~17_combout ; +wire \z80_|reg_file_|db_lo_as[5]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|db_lo_as[6]~19_combout ; +wire \z80_|reg_file_|db_lo_as[6]~20_combout ; +wire \z80_|reg_file_|db_lo_as[6]~21_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; +wire \z80_|reg_file_|db_lo_ds[7]~0_combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; wire \z80_|alu_control_|db[7]~17_combout ; +wire \z80_|alu_control_|db[7]~16_combout ; wire \z80_|alu_control_|db[7]~18_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; -wire \z80_|alu_|alu_parity_out~0_combout ; -wire \z80_|alu_|alu_parity_out~combout ; -wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; wire \z80_|execute_|ctl_flags_pf_we~5_combout ; wire \z80_|execute_|ctl_flags_pf_we~6_combout ; wire \z80_|execute_|ctl_flags_pf_we~7_combout ; wire \z80_|execute_|ctl_flags_pf_we~8_combout ; wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~11_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; wire \z80_|decode_state_|DFFE_instNonRep~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; +wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|alu_parity_out~0_combout ; +wire \z80_|alu_|alu_parity_out~combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~14_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~13_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; +wire \z80_|alu_control_|sel[1]~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; +wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; wire \z80_|alu_control_|flags_cond_true~0_combout ; wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~32_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~33_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~36_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~34_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~35_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~37_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~38_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~39_combout ; -wire \z80_|reg_file_|db_hi_as[1]~7_combout ; -wire \z80_|reg_file_|db_hi_as[1]~8_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~9_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[2]~16_combout ; -wire \z80_|reg_file_|db_hi_as[2]~17_combout ; -wire \z80_|reg_file_|db_hi_as[2]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[5]~19_combout ; -wire \z80_|reg_file_|db_hi_as[5]~20_combout ; -wire \z80_|reg_file_|db_hi_as[5]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~4_combout ; -wire \z80_|reg_file_|db_hi_as[7]~5_combout ; -wire \z80_|reg_file_|db_hi_as[7]~6_combout ; -wire \z80_|execute_|ctl_apin_mux~2_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; -wire \z80_|execute_|ctl_apin_mux2~0_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|fIORead~3_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; -wire \z80_|address_pins_|abus[15]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; -wire \z80_|address_pins_|abus[14]~16_combout ; -wire \D[1]~27_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~19_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; -wire \z80_|address_pins_|abus[10]~22_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; -wire \z80_|address_pins_|abus[11]~21_combout ; -wire \D[1]~25_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~24_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; -wire \z80_|address_pins_|abus[13]~23_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \D[1]~26_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~20_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \ula_|zx_keyboard_|keys[1][1]~20_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~21_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \D[1]~24_combout ; -wire \D[1]~28_combout ; -wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; -wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; -wire \z80_|memory_ifc_|wait_iorqinta~q ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|ctl_iorw~8_combout ; -wire \z80_|execute_|ctl_iorw~9_combout ; -wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; -wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; -wire \z80_|memory_ifc_|wait_iorq~q ; -wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; -wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|memory_ifc_|nIORQ_out~0_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|execute_|setM1~57_combout ; -wire \z80_|execute_|setM1~39_combout ; -wire \z80_|execute_|ctl_mRead~36_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|ctl_mRead~35_combout ; -wire \z80_|execute_|ctl_mRead~40_combout ; -wire \z80_|execute_|ctl_mRead~39_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|nextM~4_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; +wire \z80_|reg_file_|db_lo_ds[1]~1_combout ; +wire \z80_|alu_control_|db[1]~25_combout ; +wire \z80_|alu_control_|db[1]~24_combout ; +wire \z80_|alu_control_|db[1]~26_combout ; +wire \z80_|alu_|db[1]~12_combout ; +wire \z80_|alu_|db[1]~13_combout ; +wire \z80_|alu_|db_low[0]~21_combout ; +wire \z80_|alu_|db_low[0]~22_combout ; +wire \z80_|alu_|db_low[0]~18_combout ; +wire \z80_|alu_|db_low[0]~19_combout ; +wire \z80_|alu_|db_low[0]~20_combout ; +wire \z80_|alu_|db_low[0]~23_combout ; +wire \z80_|alu_|db[0]~18_combout ; +wire \z80_|alu_|db[0]~19_combout ; +wire \z80_|alu_|db_low[1]~15_combout ; +wire \z80_|alu_|db_low[1]~16_combout ; +wire \z80_|alu_|db_low[1]~12_combout ; +wire \z80_|alu_|db_low[1]~13_combout ; +wire \z80_|alu_|db_low[1]~14_combout ; +wire \z80_|alu_|db_low[1]~17_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|db[2]~23_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|alu_control_|db[2]~27_combout ; +wire \z80_|alu_control_|db[2]~29_combout ; +wire \z80_|alu_|db[2]~14_combout ; +wire \z80_|alu_|db[2]~15_combout ; +wire \z80_|alu_|db_low[2]~2_combout ; +wire \z80_|alu_|db_low[2]~3_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ; +wire \z80_|alu_|db_low[2]~5_combout ; +wire \z80_|alu_|db_low[2]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ; +wire \z80_|alu_|alu_op2[2]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|alu_|db_high[2]~14_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|alu_|db[6]~23_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_control_|db[6]~19_combout ; +wire \z80_|alu_control_|db[6]~20_combout ; +wire \z80_|alu_control_|db[6]~21_combout ; +wire \z80_|alu_control_|db[6]~22_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|interrupts_|im1~q ; +wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; +wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; +wire \z80_|bus_control_|db[0]~4_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; wire \z80_|execute_|ctl_mRead~37_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|setM1~55_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|nextM~3_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|execute_|ctl_mRead~35_combout ; wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; wire \z80_|memory_ifc_|wait_mrd~q ; wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|execute_|nextM~4_combout ; +wire \z80_|execute_|ctl_iorw~12_combout ; +wire \z80_|execute_|ctl_iorw~8_combout ; +wire \z80_|execute_|ctl_iorw~9_combout ; +wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; +wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; +wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; +wire \z80_|memory_ifc_|wait_iorq~q ; +wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; +wire \z80_|memory_ifc_|iorq~0_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|fIORead~3_combout ; wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; wire \z80_|memory_ifc_|nRD_out~0_combout ; wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \Equal2~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~0_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|execute_|fMWrite~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; +wire \z80_|execute_|fMWrite~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|execute_|fMWrite~8_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; +wire \z80_|execute_|fMWrite~10_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; +wire \z80_|clk_delay_|DFF_inst5~q ; +wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; +wire \z80_|memory_ifc_|wait_iorqinta~q ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; +wire \z80_|memory_ifc_|nIORQ_out~0_combout ; wire \Equal2~0_combout ; -wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; wire \ExtRamWE~0_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \z80_|execute_|ctl_apin_mux2~0_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; +wire \z80_|address_pins_|abus[13]~20_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; +wire \z80_|address_pins_|abus[14]~23_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; +wire \z80_|address_pins_|abus[15]~22_combout ; wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \z80_|address_pins_|abus[0]~16_combout ; wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|address_pins_|abus[1]~25_combout ; wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; @@ -1916,18 +1807,29 @@ wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; wire \z80_|address_pins_|abus[6]~30_combout ; wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; wire \z80_|address_pins_|abus[7]~31_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~18_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~17_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; +wire \z80_|address_pins_|abus[10]~24_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|address_pins_|abus[11]~19_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~21_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \D[6]~90_combout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \D[6]~91_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; wire \CLOCK_50~inputclkctrl_outclk ; wire \~GND~combout ; +wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; @@ -1940,9 +1842,9 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; wire \ula_|video_|vram_address[9]~1_combout ; wire \ula_|video_|Add4~13 ; @@ -1954,505 +1856,469 @@ wire \ula_|video_|vram_address[10]~2_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \Selector1~0_combout ; -wire \Selector1~1_combout ; -wire \D[1]~22_combout ; -wire \D[1]~23_combout ; -wire \D[1]~29_combout ; -wire \D[1]~31_combout ; -wire \z80_|pin_control_|bus_db_pin_re~2_combout ; -wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[1]~12_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|bus_control_|db[0]~6_combout ; -wire \z80_|bus_control_|db[1]~13_combout ; -wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; -wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~feeder_combout ; -wire \z80_|memory_ifc_|mwr_wr~q ; -wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \D[0]~30_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \D[6]~87_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \Selector6~0_combout ; -wire \D[6]~70_combout ; -wire \D[6]~71_combout ; -wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; -wire \ula_|zx_keyboard_|keys[5][4]~64_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~135_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \D[3]~55_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~95_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~96_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~97_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~99_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~q ; -wire \D[3]~54_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~136_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~109_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~137_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~110_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \ula_|zx_keyboard_|keys[5][3]~106_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \D[3]~56_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~115_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~116_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~139_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~140_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; -wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \D[3]~57_combout ; -wire \D[3]~58_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \Selector3~0_combout ; -wire \Selector3~1_combout ; -wire \D[3]~52_combout ; -wire \D[3]~53_combout ; -wire \D[3]~76_combout ; -wire \D[3]~77_combout ; -wire \ula_|always0~0_combout ; -wire \ula_|always0~1_combout ; -wire \ula_|i2s_intf_|mclk_r~0_combout ; -wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|Add0~1_cout ; -wire \ula_|i2s_intf_|Add0~2_combout ; -wire \ula_|i2s_intf_|lrdivider~2_combout ; -wire \ula_|i2s_intf_|Add0~3 ; -wire \ula_|i2s_intf_|Add0~4_combout ; -wire \ula_|i2s_intf_|lrdivider[2]~8_combout ; -wire \ula_|i2s_intf_|Add0~5 ; -wire \ula_|i2s_intf_|Add0~6_combout ; -wire \ula_|i2s_intf_|lrdivider[3]~7_combout ; -wire \ula_|i2s_intf_|Add0~7 ; -wire \ula_|i2s_intf_|Add0~8_combout ; -wire \ula_|i2s_intf_|lrdivider~1_combout ; -wire \ula_|i2s_intf_|Add0~9 ; -wire \ula_|i2s_intf_|Add0~10_combout ; -wire \ula_|i2s_intf_|lrdivider[5]~6_combout ; -wire \ula_|i2s_intf_|Add0~11 ; -wire \ula_|i2s_intf_|Add0~12_combout ; -wire \ula_|i2s_intf_|lrdivider[6]~5_combout ; -wire \ula_|i2s_intf_|Add0~13 ; -wire \ula_|i2s_intf_|Add0~14_combout ; -wire \ula_|i2s_intf_|lrdivider[7]~4_combout ; -wire \ula_|i2s_intf_|Add0~15 ; -wire \ula_|i2s_intf_|Add0~16_combout ; -wire \ula_|i2s_intf_|lrdivider~0_combout ; -wire \ula_|i2s_intf_|Add0~17 ; -wire \ula_|i2s_intf_|Add0~18_combout ; -wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; -wire \ula_|i2s_intf_|Equal0~0_combout ; -wire \ula_|i2s_intf_|Equal0~1_combout ; -wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|bitcount[0]~5_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; -wire \ula_|i2s_intf_|bclk_r~0_combout ; -wire \ula_|i2s_intf_|Add2~7_cout ; -wire \ula_|i2s_intf_|Add2~8_combout ; -wire \ula_|i2s_intf_|Add2~20_combout ; -wire \ula_|i2s_intf_|Add2~9 ; -wire \ula_|i2s_intf_|Add2~10_combout ; -wire \ula_|i2s_intf_|Add2~17_combout ; -wire \ula_|i2s_intf_|Add2~11 ; -wire \ula_|i2s_intf_|Add2~12_combout ; -wire \ula_|i2s_intf_|Add2~19_combout ; -wire \ula_|i2s_intf_|Add2~13 ; -wire \ula_|i2s_intf_|Add2~14_combout ; -wire \ula_|i2s_intf_|Add2~16_combout ; -wire \ula_|i2s_intf_|Equal1~0_combout ; -wire \ula_|i2s_intf_|shiftreg[8]~1_combout ; -wire \ula_|i2s_intf_|Add2~18_combout ; -wire \ula_|i2s_intf_|Equal1~1_combout ; -wire \ula_|i2s_intf_|bclk_r~1_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|bitcount[4]~15_combout ; -wire \ula_|i2s_intf_|bitcount[0]~6 ; -wire \ula_|i2s_intf_|bitcount[1]~7_combout ; -wire \ula_|i2s_intf_|bitcount[1]~8 ; -wire \ula_|i2s_intf_|bitcount[2]~9_combout ; -wire \ula_|i2s_intf_|bitcount[2]~10 ; -wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|bitcount[3]~12 ; -wire \ula_|i2s_intf_|bitcount[4]~13_combout ; -wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; -wire \AUD_ADCDAT~input_o ; -wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; -wire \ula_|i2s_intf_|shiftreg~18_combout ; -wire \ula_|i2s_intf_|shiftreg[8]~2_combout ; -wire \ula_|i2s_intf_|shiftreg~17_combout ; -wire \ula_|i2s_intf_|shiftreg~16_combout ; -wire \ula_|i2s_intf_|shiftreg~15_combout ; -wire \ula_|i2s_intf_|shiftreg~14_combout ; -wire \ula_|i2s_intf_|shiftreg~13_combout ; -wire \ula_|i2s_intf_|shiftreg~12_combout ; -wire \ula_|i2s_intf_|shiftreg~11_combout ; -wire \ula_|i2s_intf_|shiftreg~10_combout ; -wire \ula_|i2s_intf_|shiftreg~9_combout ; -wire \ula_|i2s_intf_|shiftreg~8_combout ; -wire \ula_|i2s_intf_|shiftreg~7_combout ; -wire \ula_|i2s_intf_|lrclk_r~0_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; -wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; -wire \ula_|ula_data~0_combout ; -wire \ula_|i2s_intf_|shiftreg~6_combout ; -wire \ula_|i2s_intf_|shiftreg~5_combout ; -wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; -wire \D[6]~72_combout ; -wire \D[6]~73_combout ; -wire \D[6]~74_combout ; -wire \D[6]~81_combout ; -wire \z80_|bus_control_|db[6]~5_combout ; -wire \z80_|bus_control_|db[6]~7_combout ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|alu_control_|db[6]~10_combout ; -wire \z80_|alu_control_|db[6]~11_combout ; -wire \z80_|alu_control_|db[2]~20_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; -wire \z80_|alu_control_|db[2]~21_combout ; -wire \z80_|alu_control_|db[2]~22_combout ; -wire \z80_|bus_control_|db[2]~10_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~59_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~133_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~132_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~34_combout ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~55_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \D[2]~33_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~48_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \D[2]~32_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~63_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~67_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \ula_|zx_keyboard_|keys[5][0]~68_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~71_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; -wire \D[2]~35_combout ; -wire \D[2]~36_combout ; -wire \D[2]~83_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \Selector0~0_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \Selector0~1_combout ; -wire \D[2]~37_combout ; -wire \D[2]~38_combout ; -wire \D[2]~39_combout ; -wire \D[2]~40_combout ; -wire \z80_|bus_control_|db[2]~11_combout ; -wire \z80_|pla_decode_|Equal3~1_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|execute_|ctl_bus_db_oe~4_combout ; -wire \z80_|execute_|ctl_bus_db_oe~5_combout ; -wire \z80_|execute_|ctl_bus_db_oe~combout ; -wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \D[0]~45_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \D[0]~44_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~134_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~93_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \D[0]~46_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~77_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~74_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~75_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~76_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~73_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \D[0]~43_combout ; -wire \D[0]~47_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \Selector2~0_combout ; -wire \Selector2~1_combout ; -wire \D[0]~41_combout ; -wire \D[0]~42_combout ; -wire \D[0]~48_combout ; -wire \D[0]~49_combout ; -wire \z80_|bus_control_|db[0]~14_combout ; -wire \z80_|bus_control_|db[0]~15_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|sw1_|db_down[5]~1_combout ; +wire \D[6]~88_combout ; +wire \D[6]~89_combout ; +wire \D[6]~111_combout ; +wire \raw_loader_in~input_o ; +wire \D[6]~86_combout ; +wire \D[6]~100_combout ; +wire \D[6]~101_combout ; +wire \z80_|pin_control_|bus_db_pin_re~2_combout ; +wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; +wire \z80_|bus_control_|db[6]~9_combout ; +wire \z80_|ir_|opcode[6]~feeder_combout ; +wire \z80_|execute_|ctl_ir_we~13_combout ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal41~1_combout ; +wire \z80_|pla_decode_|Equal41~2_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|db_high[1]~20_combout ; +wire \z80_|alu_|db[5]~24_combout ; +wire \z80_|alu_|db[5]~25_combout ; +wire \z80_|sw1_|db_down[5]~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; wire \z80_|alu_flags_|flags_yf~q ; -wire \z80_|alu_control_|db[5]~27_combout ; -wire \z80_|alu_control_|db[5]~28_combout ; -wire \z80_|alu_control_|db[5]~29_combout ; -wire \D[5]~68_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \z80_|alu_control_|db[5]~13_combout ; +wire \z80_|alu_control_|db[5]~14_combout ; +wire \z80_|alu_control_|db[5]~15_combout ; +wire \D[0]~107_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \Mux2~0_combout ; wire \Mux2~1_combout ; -wire \D[5]~88_combout ; -wire \D[5]~69_combout ; -wire \D[5]~80_combout ; -wire \z80_|bus_control_|db[5]~16_combout ; -wire \z80_|bus_control_|db[5]~17_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; -wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|fMRead~28_combout ; -wire \z80_|execute_|fMRead~30_combout ; +wire \D[5]~110_combout ; +wire \D[5]~85_combout ; +wire \D[5]~99_combout ; +wire \z80_|bus_control_|db[5]~14_combout ; +wire \z80_|bus_control_|db[5]~15_combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|fMRead~34_combout ; wire \z80_|execute_|fMRead~31_combout ; wire \z80_|execute_|fMRead~29_combout ; +wire \z80_|execute_|fMRead~30_combout ; +wire \z80_|execute_|fMRead~28_combout ; wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~37_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~35_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; +wire \z80_|execute_|fMRead~14_combout ; wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~11_combout ; +wire \z80_|execute_|fMRead~12_combout ; +wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|fMRead~15_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|pc_inc_hold~48_combout ; wire \z80_|execute_|fMRead~22_combout ; +wire \z80_|execute_|fMRead~21_combout ; wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|pc_inc_hold~39_combout ; wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|fMRead~36_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|fMRead~35_combout ; wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \Mux0~0_combout ; -wire \Mux0~1_combout ; -wire \D[7]~89_combout ; -wire \D[7]~75_combout ; -wire \D[7]~82_combout ; -wire \z80_|bus_control_|db[7]~8_combout ; -wire \z80_|bus_control_|db[7]~9_combout ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; -wire \z80_|interrupts_|im1~q ; -wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; -wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|pla_decode_|Equal21~0_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; -wire \z80_|execute_|ctl_bus_db_we~4_combout ; -wire \z80_|execute_|ctl_bus_db_we~6_combout ; -wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; -wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[4][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~128_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \D[4]~64_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~138_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \Selector1~0_combout ; +wire \Selector1~1_combout ; +wire \D[1]~103_combout ; +wire \PS2_DAT~input_o ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; +wire \ula_|zx_keyboard_|shifted~0_combout ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~23_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \D[1]~30_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \ula_|zx_keyboard_|key_row~0_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~19_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~21_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \D[1]~28_combout ; +wire \D[1]~29_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; +wire \ula_|zx_keyboard_|WideOr16~5_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|WideOr16~7_combout ; +wire \ula_|zx_keyboard_|WideOr16~6_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; +wire \D[1]~31_combout ; +wire \D[1]~32_combout ; +wire \D[1]~33_combout ; +wire \D[1]~34_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; +wire \z80_|bus_control_|db[1]~11_combout ; +wire \z80_|ir_|opcode[1]~feeder_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|execute_|ctl_flags_cf_set~0_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|alu_control_|db[0]~8_combout ; +wire \z80_|sw2_|db_up[0]~0_combout ; +wire \z80_|alu_control_|db[0]~9_combout ; +wire \z80_|alu_control_|db[0]~12_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~67_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \D[0]~49_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys~76_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~73_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~74_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; +wire \ula_|zx_keyboard_|keys[1][0]~71_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \D[0]~47_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \ula_|zx_keyboard_|keys[3][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \ula_|zx_keyboard_|key_row~1_combout ; +wire \D[0]~48_combout ; +wire \ula_|zx_keyboard_|shifted~1_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|keys[5][4]~63_combout ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~132_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \D[0]~50_combout ; +wire \D[0]~51_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~55_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \D[0]~56_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \D[0]~52_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~53_combout ; +wire \D[0]~54_combout ; +wire \D[0]~106_combout ; +wire \D[0]~57_combout ; +wire \D[0]~58_combout ; +wire \z80_|bus_control_|db[0]~16_combout ; +wire \z80_|bus_control_|db[0]~17_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|alu_control_|db[6]~10_combout ; +wire \z80_|alu_control_|db[6]~11_combout ; +wire \z80_|alu_control_|db[4]~30_combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \z80_|alu_control_|db[4]~32_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~95_combout ; wire \ula_|zx_keyboard_|keys[2][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~123_combout ; wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \D[4]~63_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~129_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \ula_|zx_keyboard_|keys[6][4]~130_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~131_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~136_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~130_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \D[4]~78_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~128_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~129_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \ula_|zx_keyboard_|keys[6][4]~127_combout ; wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \D[4]~65_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~118_combout ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \D[4]~79_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \ula_|zx_keyboard_|key_row~3_combout ; +wire \D[4]~80_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~97_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~116_combout ; wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~115_combout ; wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~62_combout ; -wire \D[4]~66_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \D[4]~77_combout ; +wire \D[4]~81_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; wire \Selector4~0_combout ; wire \Selector4~1_combout ; -wire \D[4]~60_combout ; -wire \D[4]~61_combout ; -wire \D[4]~78_combout ; -wire \D[4]~79_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ; +wire \D[4]~109_combout ; +wire \D[4]~97_combout ; +wire \D[4]~98_combout ; wire \z80_|bus_control_|db[4]~18_combout ; wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|pla_decode_|Equal21~0_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_mWrite~13_combout ; +wire \z80_|execute_|ctl_mWrite~14_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; +wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; +wire \z80_|memory_ifc_|wait_mwr~q ; +wire \z80_|memory_ifc_|mwr_wr~q ; +wire \z80_|memory_ifc_|nWR_out~0_combout ; +wire \D[5]~84_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Mux0~0_combout ; +wire \Mux0~1_combout ; +wire \D[7]~112_combout ; +wire \D[7]~94_combout ; +wire \D[7]~102_combout ; +wire \z80_|bus_control_|db[7]~5_combout ; +wire \z80_|bus_control_|db[7]~7_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|execute_|ctl_mWrite~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_bus_db_we~8_combout ; +wire \z80_|execute_|ctl_bus_db_we~2_combout ; +wire \z80_|execute_|ctl_bus_db_we~4_combout ; +wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_bus_db_we~7_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \ula_|zx_keyboard_|keys[3][3]~48_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \D[2]~35_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~131_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \D[2]~37_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \D[2]~36_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \D[2]~38_combout ; +wire \D[2]~39_combout ; +wire \D[2]~104_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \D[2]~43_combout ; +wire \D[2]~44_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \D[2]~40_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \D[2]~41_combout ; +wire \D[2]~42_combout ; +wire \D[2]~105_combout ; +wire \D[2]~45_combout ; +wire \D[2]~46_combout ; +wire \z80_|bus_control_|db[2]~12_combout ; +wire \z80_|bus_control_|db[2]~13_combout ; +wire \z80_|pla_decode_|Equal3~1_combout ; wire \z80_|pla_decode_|Equal43~0_combout ; wire \z80_|interrupts_|test1~2_combout ; wire \z80_|interrupts_|test1~3_combout ; @@ -2463,83 +2329,151 @@ wire \z80_|clk_delay_|hold_clk_iorq~combout ; wire \z80_|sequencer_|DFFE_T1_ff~q ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; -wire \z80_|sequencer_|DFFE_T3_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|setM1~53_combout ; -wire \z80_|execute_|nextM~3_combout ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; +wire \z80_|execute_|ctl_mWrite~3_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|execute_|nextM~8_combout ; wire \z80_|execute_|nextM~9_combout ; wire \z80_|execute_|nextM~10_combout ; wire \z80_|execute_|nextM~12_combout ; wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~5_combout ; +wire \z80_|execute_|nextM~6_combout ; wire \z80_|execute_|nextM~7_combout ; -wire \z80_|execute_|nextM~8_combout ; wire \z80_|execute_|nextM~13_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|nextM~5_combout ; wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; wire \z80_|sequencer_|T6~q ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~41_combout ; wire \z80_|execute_|setM1~42_combout ; wire \z80_|execute_|setM1~43_combout ; wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~16_combout ; wire \z80_|execute_|setM1~50_combout ; wire \z80_|execute_|setM1~51_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~6_combout ; +wire \z80_|execute_|setM1~7_combout ; wire \z80_|execute_|setM1~8_combout ; wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~53_combout ; +wire \z80_|execute_|setM1~23_combout ; wire \z80_|execute_|setM1~18_combout ; wire \z80_|execute_|setM1~19_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~54_combout ; wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~34_combout ; wire \z80_|execute_|setM1~52_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_inc_cy~39_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~37_combout ; -wire \z80_|execute_|pc_inc_hold~38_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; +wire \z80_|sequencer_|DFFE_T3_ff~q ; +wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|execute_|ctl_bus_db_oe~2_combout ; +wire \z80_|execute_|ctl_bus_db_oe~5_combout ; +wire \z80_|execute_|ctl_bus_db_oe~6_combout ; +wire \z80_|execute_|ctl_bus_db_oe~4_combout ; +wire \z80_|execute_|ctl_bus_db_oe~combout ; +wire \z80_|bus_control_|db[0]~6_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~q ; +wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~q ; +wire \D[3]~65_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~133_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \D[3]~66_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~134_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~135_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \D[3]~67_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~q ; +wire \ula_|zx_keyboard_|keys[6][3]~109_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~110_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~137_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~138_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \ula_|zx_keyboard_|key_row~2_combout ; +wire \D[3]~68_combout ; +wire \D[3]~69_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \D[3]~73_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \D[3]~74_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \D[3]~70_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~71_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~72_combout ; +wire \D[3]~108_combout ; +wire \D[3]~95_combout ; +wire \D[3]~96_combout ; +wire \z80_|bus_control_|db[3]~20_combout ; +wire \z80_|bus_control_|db[3]~21_combout ; +wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \z80_|execute_|ctl_apin_mux~2_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~84_combout ; -wire \D[0]~50_combout ; -wire \D[1]~85_combout ; -wire \D[1]~51_combout ; -wire \D[3]~86_combout ; -wire \D[3]~59_combout ; -wire \D[4]~87_combout ; -wire \D[4]~67_combout ; +wire \D[0]~59_combout ; +wire \D[0]~60_combout ; +wire \D[1]~61_combout ; +wire \D[1]~62_combout ; +wire \D[2]~63_combout ; +wire \D[2]~64_combout ; +wire \D[3]~75_combout ; +wire \D[3]~76_combout ; +wire \D[4]~82_combout ; +wire \D[4]~83_combout ; +wire \D[6]~92_combout ; +wire \D[6]~93_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2547,6 +2481,7 @@ wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ; wire \z80_|memory_ifc_|DFFE_mreq_ff2~q ; wire \z80_|memory_ifc_|nMREQ_out~0_combout ; wire \z80_|memory_ifc_|nMREQ_out~1_combout ; +wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|divider[0]~15_combout ; wire \ula_|i2c_loader_|divider[1]~5_combout ; @@ -2563,35 +2498,24 @@ wire \ula_|i2c_loader_|WideAnd0~combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; +wire \ula_|i2c_loader_|nbit~5_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|Mux42~0_combout ; -wire \ula_|i2c_loader_|nbit~6_combout ; -wire \ula_|i2c_loader_|nbyte~0_combout ; +wire \ula_|i2c_loader_|nbyte~4_combout ; wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; wire \I2C_SDAT~input_o ; wire \ula_|i2c_loader_|nbyte[0]~1_combout ; wire \ula_|i2c_loader_|nbyte[0]~2_combout ; wire \ula_|i2c_loader_|nbyte[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~4_combout ; +wire \ula_|i2c_loader_|state.Stop~0_combout ; +wire \ula_|i2c_loader_|state.Stop~1_combout ; +wire \ula_|i2c_loader_|state.Stop~q ; +wire \ula_|i2c_loader_|state.Idle~0_combout ; +wire \ula_|i2c_loader_|nbit~0_combout ; wire \ula_|i2c_loader_|state.Done~0_combout ; wire \ula_|i2c_loader_|state.Ack~0_combout ; wire \ula_|i2c_loader_|state.Ack~1_combout ; -wire \ula_|i2c_loader_|state.Ack~2_combout ; wire \ula_|i2c_loader_|state.Ack~q ; -wire \ula_|i2c_loader_|state~24_combout ; -wire \ula_|i2c_loader_|state~26_combout ; -wire \ula_|i2c_loader_|state~27_combout ; -wire \ula_|i2c_loader_|state.Data~0_combout ; -wire \ula_|i2c_loader_|state.Data~q ; -wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|nbit~0_combout ; -wire \ula_|i2c_loader_|state.Done~1_combout ; -wire \ula_|i2c_loader_|state.Done~2_combout ; -wire \ula_|i2c_loader_|state.Pause~2_combout ; -wire \ula_|i2c_loader_|state.Pause~0_combout ; -wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|nbyte[1]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; @@ -2601,29 +2525,43 @@ wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; wire \ula_|i2c_loader_|Equal2~0_combout ; +wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|state.Done~2_combout ; +wire \ula_|i2c_loader_|state.Pause~2_combout ; wire \ula_|i2c_loader_|state.Pause~3_combout ; wire \ula_|i2c_loader_|state.Pause~q ; wire \ula_|i2c_loader_|state~25_combout ; wire \ula_|i2c_loader_|state.Start~q ; -wire \ula_|i2c_loader_|nbyte~4_combout ; -wire \ula_|i2c_loader_|state.Stop~0_combout ; -wire \ula_|i2c_loader_|state.Stop~1_combout ; -wire \ula_|i2c_loader_|state.Stop~q ; +wire \ula_|i2c_loader_|nbyte~0_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit[0]~4_combout ; +wire \ula_|i2c_loader_|nbit~6_combout ; +wire \ula_|i2c_loader_|state.Done~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; +wire \ula_|i2c_loader_|state~24_combout ; +wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|state.Data~0_combout ; +wire \ula_|i2c_loader_|state.Data~q ; wire \ula_|i2c_loader_|scl_out~0_combout ; wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|scl_out~1_combout ; wire \ula_|i2c_loader_|scl_out~2_combout ; wire \ula_|i2c_loader_|scl_out~q ; wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; +wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|Mux35~0_combout ; +wire \ula_|i2c_loader_|shiftreg~13_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~15_combout ; wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|shiftreg~21_combout ; wire \ula_|i2c_loader_|shiftreg~22_combout ; wire \ula_|i2c_loader_|shiftreg~23_combout ; @@ -2632,12 +2570,9 @@ wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; wire \ula_|i2c_loader_|shiftreg~18_combout ; wire \ula_|i2c_loader_|shiftreg~19_combout ; wire \ula_|i2c_loader_|shiftreg~20_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; wire \ula_|i2c_loader_|shiftreg~16_combout ; wire \ula_|i2c_loader_|shiftreg~17_combout ; wire \ula_|i2c_loader_|shiftreg~26_combout ; -wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~15_combout ; wire \ula_|i2c_loader_|shiftreg~25_combout ; wire \ula_|i2c_loader_|shiftreg~12_combout ; wire \ula_|i2c_loader_|shiftreg~9_combout ; @@ -2648,31 +2583,120 @@ wire \ula_|i2c_loader_|sda_out~2_combout ; wire \ula_|i2c_loader_|sda_out~3_combout ; wire \ula_|i2c_loader_|sda_out~4_combout ; wire \ula_|i2c_loader_|sda_out~q ; +wire \ula_|i2s_intf_|mclk_r~0_combout ; +wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|mclk_r~q ; +wire \ula_|i2s_intf_|Add0~1_cout ; +wire \ula_|i2s_intf_|Add0~2_combout ; +wire \ula_|i2s_intf_|lrdivider~2_combout ; +wire \ula_|i2s_intf_|Add0~3 ; +wire \ula_|i2s_intf_|Add0~4_combout ; +wire \ula_|i2s_intf_|lrdivider[2]~8_combout ; +wire \ula_|i2s_intf_|Add0~5 ; +wire \ula_|i2s_intf_|Add0~6_combout ; +wire \ula_|i2s_intf_|lrdivider[3]~7_combout ; +wire \ula_|i2s_intf_|Add0~7 ; +wire \ula_|i2s_intf_|Add0~8_combout ; +wire \ula_|i2s_intf_|lrdivider~1_combout ; +wire \ula_|i2s_intf_|Add0~9 ; +wire \ula_|i2s_intf_|Add0~10_combout ; +wire \ula_|i2s_intf_|lrdivider[5]~6_combout ; +wire \ula_|i2s_intf_|Equal0~1_combout ; +wire \ula_|i2s_intf_|Add0~11 ; +wire \ula_|i2s_intf_|Add0~12_combout ; +wire \ula_|i2s_intf_|lrdivider[6]~5_combout ; +wire \ula_|i2s_intf_|Add0~13 ; +wire \ula_|i2s_intf_|Add0~14_combout ; +wire \ula_|i2s_intf_|lrdivider[7]~4_combout ; +wire \ula_|i2s_intf_|Add0~15 ; +wire \ula_|i2s_intf_|Add0~16_combout ; +wire \ula_|i2s_intf_|lrdivider~0_combout ; +wire \ula_|i2s_intf_|Add0~17 ; +wire \ula_|i2s_intf_|Add0~18_combout ; +wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; +wire \ula_|i2s_intf_|Equal0~0_combout ; +wire \ula_|i2s_intf_|Equal0~2_combout ; +wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; +wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; +wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|bitcount[0]~5_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|bitcount[4]~15_combout ; +wire \ula_|i2s_intf_|bitcount[0]~6 ; +wire \ula_|i2s_intf_|bitcount[1]~7_combout ; +wire \ula_|i2s_intf_|bitcount[1]~8 ; +wire \ula_|i2s_intf_|bitcount[2]~9_combout ; +wire \ula_|i2s_intf_|bitcount[2]~10 ; +wire \ula_|i2s_intf_|bitcount[3]~11_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|bitcount[3]~12 ; +wire \ula_|i2s_intf_|bitcount[4]~13_combout ; +wire \ula_|i2s_intf_|Add2~7_cout ; +wire \ula_|i2s_intf_|Add2~8_combout ; +wire \ula_|i2s_intf_|Add2~20_combout ; +wire \ula_|i2s_intf_|Add2~9 ; +wire \ula_|i2s_intf_|Add2~10_combout ; +wire \ula_|i2s_intf_|Add2~17_combout ; +wire \ula_|i2s_intf_|Add2~11 ; +wire \ula_|i2s_intf_|Add2~12_combout ; +wire \ula_|i2s_intf_|Add2~19_combout ; +wire \ula_|i2s_intf_|Add2~13 ; +wire \ula_|i2s_intf_|Add2~14_combout ; +wire \ula_|i2s_intf_|Add2~16_combout ; +wire \ula_|i2s_intf_|Equal1~0_combout ; +wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; +wire \ula_|i2s_intf_|Add2~18_combout ; +wire \ula_|i2s_intf_|Equal1~1_combout ; +wire \ula_|i2s_intf_|bclk_r~0_combout ; +wire \ula_|i2s_intf_|bclk_r~1_combout ; wire \ula_|i2s_intf_|bclk_r~q ; +wire \ula_|pcm_outl[13]~feeder_combout ; +wire \ula_|always0~2_combout ; +wire \ula_|always0~3_combout ; +wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; +wire \AUD_ADCDAT~input_o ; +wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; +wire \ula_|i2s_intf_|shiftreg~18_combout ; +wire \ula_|i2s_intf_|shiftreg[4]~2_combout ; +wire \ula_|i2s_intf_|shiftreg~17_combout ; +wire \ula_|i2s_intf_|shiftreg~16_combout ; +wire \ula_|i2s_intf_|shiftreg~15_combout ; +wire \ula_|i2s_intf_|shiftreg~14_combout ; +wire \ula_|i2s_intf_|shiftreg~13_combout ; +wire \ula_|i2s_intf_|shiftreg~12_combout ; +wire \ula_|i2s_intf_|shiftreg~11_combout ; +wire \ula_|i2s_intf_|shiftreg~10_combout ; +wire \ula_|i2s_intf_|shiftreg~9_combout ; +wire \ula_|i2s_intf_|shiftreg~8_combout ; +wire \ula_|i2s_intf_|shiftreg~7_combout ; +wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; +wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; +wire \ula_|pcm_outr~0_combout ; +wire \ula_|i2s_intf_|shiftreg~6_combout ; +wire \ula_|i2s_intf_|shiftreg~5_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|border[1]~feeder_combout ; +wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|video_|LessThan6~0_combout ; +wire \ula_|video_|LessThan2~1_combout ; +wire \ula_|video_|LessThan3~0_combout ; +wire \ula_|video_|LessThan0~0_combout ; +wire \ula_|video_|disp_enable~0_combout ; +wire \ula_|video_|disp_enable~1_combout ; +wire \ula_|video_|LessThan6~1_combout ; +wire \ula_|video_|LessThan4~0_combout ; +wire \ula_|video_|screen_en~0_combout ; +wire \ula_|video_|screen_en~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|Decoder0~1_combout ; -wire \ula_|video_|attr[1]~feeder_combout ; wire \ula_|video_|Decoder0~0_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[4]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[6]~feeder_combout ; -wire \ula_|video_|Decoder0~2_combout ; -wire \ula_|video_|bits_prefetch[4]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[5]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[7]~feeder_combout ; -wire \ula_|video_|Mux0~0_combout ; -wire \ula_|video_|Mux0~1_combout ; wire \ula_|video_|attr_prefetch[7]~feeder_combout ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; @@ -2683,8 +2707,20 @@ wire \ula_|video_|frame[3]~8_combout ; wire \ula_|video_|frame[3]~9 ; wire \ula_|video_|frame[4]~10_combout ; wire \ula_|video_|inverted~combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[6]~feeder_combout ; +wire \ula_|video_|Decoder0~2_combout ; +wire \ula_|video_|bits[6]~feeder_combout ; +wire \ula_|video_|bits_prefetch[4]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[5]~feeder_combout ; +wire \ula_|video_|bits[5]~feeder_combout ; +wire \ula_|video_|bits_prefetch[7]~feeder_combout ; +wire \ula_|video_|Mux0~0_combout ; +wire \ula_|video_|Mux0~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[2]~feeder_combout ; +wire \ula_|video_|bits[2]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[0]~feeder_combout ; wire \ula_|video_|bits_prefetch[1]~feeder_combout ; @@ -2695,17 +2731,6 @@ wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; wire \ula_|video_|cindex[1]~0_combout ; wire \ula_|video_|cindex[1]~1_combout ; -wire \ula_|video_|LessThan6~0_combout ; -wire \ula_|video_|LessThan6~1_combout ; -wire \ula_|video_|LessThan4~0_combout ; -wire \ula_|video_|screen_en~0_combout ; -wire \ula_|video_|screen_en~1_combout ; -wire \ula_|video_|LessThan2~0_combout ; -wire \ula_|video_|LessThan2~1_combout ; -wire \ula_|video_|LessThan3~0_combout ; -wire \ula_|video_|LessThan0~0_combout ; -wire \ula_|video_|disp_enable~0_combout ; -wire \ula_|video_|disp_enable~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; @@ -2715,8 +2740,9 @@ wire \ula_|video_|attr_prefetch[5]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; -wire \ula_|border[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[0]~feeder_combout ; +wire \ula_|video_|attr[0]~feeder_combout ; +wire \ula_|video_|attr_prefetch[3]~feeder_combout ; wire \ula_|video_|cindex[0]~3_combout ; wire \ula_|video_|VGA_B[0]~1_combout ; wire \ula_|video_|VGA_B[1]~2_combout ; @@ -2751,13 +2777,11 @@ wire [4:0] \ula_|video_|frame ; wire [7:0] \ula_|video_|bits_prefetch ; wire [7:0] \ula_|video_|attr_prefetch ; wire [7:0] \ula_|ps2_keyboard_|clk_filter ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; @@ -2768,9 +2792,10 @@ wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; wire [3:0] \z80_|alu_|op2_low ; wire [3:0] \z80_|alu_|op1_low ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; -wire [15:0] \z80_|address_latch_|abusz ; -wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [15:0] \z80_|address_latch_|Q ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; +wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [7:0] \z80_|data_pins_|dout ; wire [7:0] \z80_|ir_|opcode ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; @@ -2790,11 +2815,13 @@ wire [7:0] \ula_|video_|bits ; wire [7:0] \ula_|video_|attr ; wire [8:0] \ula_|ps2_keyboard_|shiftreg ; wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; @@ -2806,10 +2833,9 @@ wire [3:0] \z80_|alu_|result_lo ; wire [3:0] \z80_|alu_|op2_high ; wire [3:0] \z80_|alu_|op1_high ; wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; -wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; -wire [7:0] \z80_|data_pins_|dout ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; +wire [15:0] \z80_|address_latch_|abusz ; +wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; @@ -2821,33 +2847,33 @@ wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_b wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; @@ -2866,15 +2892,15 @@ wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_b wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; @@ -2909,60 +2935,60 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; @@ -2999,24 +3025,24 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; @@ -3245,8 +3271,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~50_combout ), - .oe(\D[0]~30_combout ), + .i(\D[0]~60_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3258,8 +3284,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~51_combout ), - .oe(\D[0]~30_combout ), + .i(\D[1]~62_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3271,8 +3297,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~39_combout ), - .oe(\D[0]~30_combout ), + .i(\D[2]~64_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3284,8 +3310,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~59_combout ), - .oe(\D[0]~30_combout ), + .i(\D[3]~76_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3297,8 +3323,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~67_combout ), - .oe(\D[0]~30_combout ), + .i(\D[4]~83_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3310,8 +3336,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~69_combout ), - .oe(\D[0]~30_combout ), + .i(\D[5]~85_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3323,8 +3349,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~74_combout ), - .oe(\D[0]~30_combout ), + .i(\D[6]~93_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3336,8 +3362,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~75_combout ), - .oe(\D[0]~30_combout ), + .i(\D[7]~94_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -3440,7 +3466,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(gnd), + .i(\raw_loader_in~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -4080,7 +4106,7 @@ defparam \ula_|clocks_|clk_cpu .is_wysiwyg = "true"; defparam \ula_|clocks_|clk_cpu .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G10 +// Location: CLKCTRL_G14 cycloneive_clkctrl \ula_|clocks_|clk_cpu~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\ula_|clocks_|clk_cpu~q }), @@ -4093,7 +4119,24 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N0 +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N12 cycloneive_lcell_comb \z80_|sequencer_|ena_M ( // Equation(s): // \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout ) @@ -4110,6 +4153,11802 @@ defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; // synopsys translate_on +// Location: IOIBUF_X0_Y16_N8 +cycloneive_io_ibuf \KEY[1]~input ( + .i(KEY[1]), + .ibar(gnd), + .o(\KEY[1]~input_o )); +// synopsys translate_off +defparam \KEY[1]~input .bus_hold = "false"; +defparam \KEY[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( +// Equation(s): +// \z80_|interrupts_|nmi_armed~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; +defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N2 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hAAFF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y15_N7 +dffeas \z80_|interrupts_|nmi_armed ( + .clk(!\KEY[1]~input_o ), + .d(\z80_|interrupts_|nmi_armed~feeder_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|nmi_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|nmi_armed .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N12 +cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( +// Equation(s): +// \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|interrupts_|nmi_armed~q ), + .cin(gnd), + .combout(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( +// Equation(s): +// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h1100; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N31 +dffeas \z80_|sequencer_|DFFE_M3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( +// Equation(s): +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hD0D0; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N2 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N3 +dffeas \z80_|sequencer_|DFFE_M4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h00CC; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( +// Equation(s): +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|decode_state_|table_xx~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal36~0_combout )))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|pla_decode_|Equal36~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal36~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hB3A0; +defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EA; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X41_Y17_N29 +dffeas \z80_|decode_state_|DFFE_instCB ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instCB~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X41_Y17_N17 +dffeas \z80_|decode_state_|DFFE_instED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) + + .dataa(\z80_|ir_|opcode [7]), + .datab(gnd), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout )) + + .dataa(gnd), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal49~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [3])) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~8_combout = (((!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h4FFF; +defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N12 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h0055; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hEF00; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( +// Equation(s): +// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal3~2_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( +// Equation(s): +// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( +// Equation(s): +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( +// Equation(s): +// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( +// Equation(s): +// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~8_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( +// Equation(s): +// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal44~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( +// Equation(s): +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( +// Equation(s): +// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|execute_|ixy_d~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(gnd), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal50~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( +// Equation(s): +// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|pla_decode_|Equal50~0_combout & ((!\z80_|pla_decode_|Equal33~2_combout )))) # (!\z80_|decode_state_|DFFE_inst4~q & (((!\z80_|pla_decode_|Equal50~0_combout & +// !\z80_|pla_decode_|Equal33~2_combout )) # (!\z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0537; +defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( +// Equation(s): +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & +// (!\z80_|execute_|ixy_d~13_combout & (\z80_|execute_|ixy_d~17_combout ))) + + .dataa(\z80_|execute_|ixy_d~12_combout ), + .datab(\z80_|execute_|ixy_d~13_combout ), + .datac(\z80_|execute_|ixy_d~17_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h30BA; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( +// Equation(s): +// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( +// Equation(s): +// \z80_|execute_|ixy_d~15_combout = ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|execute_|ixy_d~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & +// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N23 +dffeas \z80_|decode_state_|DFFE_instIY1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_iy_set~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instIY1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0500; +defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_mRead~26_combout & !\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ctl_mRead~27_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h5D00; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal12~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0500; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( +// Equation(s): +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|comb~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|comb~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~17_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~18_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal32~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|reg_control_|reg_sys_we_lo~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|pla_decode_|Equal24~1_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~3_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|reg_control_|reg_sys_we_lo~3_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h153F; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~20_combout ), + .datab(\z80_|execute_|ctl_mRead~21_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~18_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~18_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( +// Equation(s): +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|M5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N17 +dffeas \z80_|sequencer_|M5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|M5~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|M5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|M5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & +// (((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'h0777; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout +// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~29_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~7_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~14_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_state_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~14_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & +// (((!\z80_|execute_|ctl_state_alu~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'h115F; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F3F; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|pla_decode_|Equal29~0_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Equation(s): +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_state_alu~8_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~8_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'h7000; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & +// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mRead~18_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal41~0_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal46~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_flags_alu~17_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0505; +defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~6_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_alu~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~17_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_mWrite~8_combout ))) + + .dataa(\z80_|execute_|fMRead~17_combout ), + .datab(\z80_|execute_|ctl_sw_2d~4_combout ), + .datac(\z80_|execute_|fMRead~16_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_mRead~24_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~18_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~24_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|fMRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~36_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~9_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~3_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h007F; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ixy_d~6_combout & +// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~4_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal46~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & (((!\z80_|execute_|ctl_ir_we~12_combout ) # +// (!\z80_|execute_|ctl_mWrite~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0577; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datab(\z80_|execute_|ctl_sw_2d~7_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|fMRead~19_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|ctl_sw_2d~8_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), + .datab(\z80_|execute_|fMRead~19_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datad(\z80_|execute_|ctl_sw_2d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_sw_2d~9_combout ))) + + .dataa(\z80_|execute_|ctl_im_we~combout ), + .datab(\z80_|execute_|ctl_sw_1d~5_combout ), + .datac(\z80_|execute_|ctl_sw_1d~4_combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout ))) # (!\z80_|execute_|ctl_sw_1d~6_combout ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7333; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0111; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~4 ( +// Equation(s): +// \z80_|alu_|db_low[2]~4_combout = ((\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~4 .lut_mask = 16'h555D; +defparam \z80_|alu_|db_low[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_sw_4u~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # +// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~29_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) + + .dataa(\z80_|ir_|opcode [4]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00AA; +defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~2 ( +// Equation(s): +// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0011; +defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0103; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0D0; +defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~15_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0F3F; +defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_ir_we~7_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~15_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & !\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_mWrite~16_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~13 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_alu_bs_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_alu_bs_oe~13_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~13_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|pla_decode_|Equal68~2_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_flags_bus~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'hAFBF; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~10_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_flags_bus~8_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_flags_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~11_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~14_combout ), + .datab(\z80_|execute_|ctl_flags_bus~11_combout ), + .datac(\z80_|execute_|ctl_flags_bus~10_combout ), + .datad(\z80_|execute_|ctl_flags_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_state_alu~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) # +// (!\z80_|execute_|ctl_mWrite~3_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h3030; +defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|pla_decode_|Equal41~2_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1100; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[2]~14_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N17 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88C8; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~11 ( +// Equation(s): +// \z80_|execute_|fMWrite~11_combout = ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~11 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~21_combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_alu_op_low~9_combout ))) # (!\z80_|execute_|fMWrite~11_combout ) + + .dataa(\z80_|execute_|fMWrite~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~22_combout = ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h7737; +defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~16_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~36 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (\z80_|execute_|ctl_state_alu~8_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datab(\z80_|execute_|ctl_state_alu~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_mWrite~3_combout & +// (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~19_combout = ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'h77F7; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_mRead~36_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op_low~22_combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|execute_|ixy_d~5_combout & +// (\z80_|pla_decode_|Equal40~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hEAE0; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFF08; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = ((\z80_|execute_|ctl_alu_op_low~24_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~26_combout ) # (\z80_|execute_|ctl_mRead~27_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) + + .dataa(\z80_|execute_|ctl_mRead~26_combout ), + .datab(\z80_|execute_|ctl_mRead~27_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hEF0F; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = (\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (((\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = (\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hF200; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3F20; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~22_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0CEC; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h32F0; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h22EA; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~14_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~14 .lut_mask = 16'hC0C8; +defparam \z80_|execute_|ctl_alu_bs_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~14_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00EA; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & +// (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~4_combout +// & (\z80_|execute_|ctl_ir_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEAC8; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|execute_|ctl_alu_bs_oe~10_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (!\z80_|execute_|ctl_alu_bs_oe~11_combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h00CF; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~32_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_alu_shift_oe~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF51; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~7_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # +// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h3F20; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~12_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~26_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|pla_decode_|Equal48~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h1300; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0C00; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & +// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal11~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_alu~9_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~9_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~10_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_ir_we~14_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout ) # +// (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'h0377; +defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~25_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~13_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'h3331; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h5557; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h7000; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|ctl_state_alu~7_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~3_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & +// (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~3_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'h8C88; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~2_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(gnd), + .datac(\z80_|alu_|db_high[3]~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hFAFA; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~24 ( +// Equation(s): +// \z80_|alu_|db_low[2]~24_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~3_combout & (\z80_|alu_|db_low[2]~6_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~3_combout & +// \z80_|alu_|db_low[2]~6_combout )) # (!\z80_|alu_|db_high[3]~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[2]~3_combout ), + .datac(\z80_|alu_|db_low[2]~6_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~24 .lut_mask = 16'hC0D5; +defparam \z80_|alu_|db_low[2]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h0AAA; +defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|reg_control_|reg_sys_we_lo~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~43_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & \z80_|execute_|ctl_bus_inc_oe~25_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|execute_|ctl_alu_oe~8_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~8_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mWrite~16_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & +// (((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (((!\z80_|execute_|ctl_mRead~27_combout & !\z80_|execute_|ctl_mRead~26_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~27_combout ), + .datac(\z80_|execute_|ctl_mRead~26_combout ), + .datad(\z80_|execute_|ctl_alu_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|execute_|ctl_alu_oe~11_combout ) # (((!\z80_|execute_|ctl_alu_oe~7_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|execute_|ctl_alu_oe~5_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_alu_oe~12_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~12_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_oe~13_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hF5F5; +defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & +// (((!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mRead~26_combout ))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|nextM~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'h8C00; +defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( +// Equation(s): +// \z80_|execute_|setM1~54_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'hABFF; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~7_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_alu_oe~3_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout )) # +// (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_alu_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_sw_2u~4_combout )) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~1_combout ), + .datad(\z80_|execute_|ctl_sw_2u~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~36_combout & (\z80_|execute_|comb~0_combout $ ((!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_reg_gp_sel~36_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & +// (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~35_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_inc_cy~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(\z80_|execute_|ctl_sw_2u~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h7878; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & +// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (!\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h5AAA; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h0444; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~14_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~10_combout ), + .datab(\z80_|execute_|ctl_sw_2d~14_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEAA; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~11_combout ), + .datac(\z80_|execute_|ctl_sw_2d~12_combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_alu_oe~2_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|pla_decode_|Equal38~2_combout & ((!\z80_|pla_decode_|Equal37~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|pla_decode_|Equal38~2_combout +// & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~75_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal29~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~48_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|execute_|ctl_bus_inc_oe~48_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & +// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~92_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~38_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal3~1_combout )) # (!\z80_|pla_decode_|Equal19~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal19~1_combout ), + .datac(\z80_|execute_|ctl_sw_4u~0_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~93_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~93_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~93_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~24_combout = (\z80_|execute_|ctl_inc_cy~92_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~39_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~92_combout ), + .datac(\z80_|execute_|ctl_inc_cy~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~1_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (\z80_|execute_|ctl_bus_inc_oe~46_combout & (\z80_|execute_|ctl_inc_cy~53_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~53_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~44_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_sw_4u~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .datad(\z80_|execute_|ctl_sw_4u~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( +// Equation(s): +// \z80_|execute_|fMRead~3_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ctl_state_alu~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # +// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~15_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_state_alu~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_sw_4u~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~94_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~94_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~87_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~94_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ctl_inc_cy~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (\z80_|execute_|fMRead~3_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) + + .dataa(\z80_|execute_|fMRead~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout ))) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~5_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~6_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal1~5_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~6_combout & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal1~6_combout ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N23 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N27 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal2~1_combout ), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hC888; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~12_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal50~0_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( +// Equation(s): +// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFAF; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( +// Equation(s): +// \z80_|execute_|fMRead~2_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_flags_bus~5_combout )) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~14_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h1010; +defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|fMWrite~3_combout & (\z80_|execute_|fMRead~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|fMWrite~3_combout ), + .datac(\z80_|execute_|fMRead~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h00C0; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h50F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hC5CD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout & ((\z80_|execute_|ctl_ir_we~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hCAC0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [4]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~47_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~8_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~47_combout & \z80_|execute_|nextM~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~21_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~5_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_sw_1d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & +// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hAB00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~20_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|pla_decode_|Equal49~0_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .lut_mask = 16'h0101; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~22_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'h0032; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout & \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~36_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00CC; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h20AA; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0505; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|pla_decode_|Equal68~2_combout & (!\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_flags_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~48_combout )))) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|ctl_flags_oe~1_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0070; +defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~40_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (\z80_|execute_|ctl_inc_cy~43_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_inc_cy~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal29~0_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & +// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0357; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & +// !\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h111F; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|fMRead~7_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h10F0; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .datac(\z80_|execute_|fMRead~6_combout ), + .datad(\z80_|execute_|fMRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|execute_|ctl_state_alu~8_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~8_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'h3331; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) # +// (!\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|pla_decode_|Equal52~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (\z80_|execute_|ctl_state_alu~14_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|execute_|ctl_state_alu~14_combout & (\z80_|pla_decode_|Equal52~1_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'hF3A2; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~9_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hFD00; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~4_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h373F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~9_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00FD; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal64~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hEEFF; +defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .datac(\z80_|execute_|ctl_alu_oe~7_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_state_alu~14_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|pla_decode_|Equal52~1_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~15 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|ctl_state_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (\z80_|execute_|ctl_state_alu~15_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )) + + .dataa(\z80_|execute_|ctl_state_alu~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ) # (((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout & \z80_|ir_|opcode [5])) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & +// ((\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hFF70; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hF7F7; +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h22A2; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; +defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h0F0B; +defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N15 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) + + .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hAC00; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_state_alu~15_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_state_alu~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h1100; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout & ((!\z80_|execute_|ctl_iorw~10_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout +// )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|pla_decode_|Equal25~0_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout & !\z80_|execute_|ctl_sw_1d~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), + .datad(\z80_|execute_|ctl_sw_1d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_reg_gp_we~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~5_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .datab(\z80_|execute_|ctl_sw_4u~3_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~7_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; +defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_flags_oe~1_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h1033; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ctl_al_we~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFBF0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h40CC; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (((\z80_|execute_|ctl_ir_we~7_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_iorw~11_combout ) # ((\z80_|execute_|ctl_state_alu~14_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~14_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~25_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & +// (((\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )) # (!\z80_|execute_|setM1~48_combout ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hCD05; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~9_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout )) # +// (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h1357; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h1155; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~40_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h1101; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout +// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_gp_we~5_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_mRead~22_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00B0; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) + + .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N21 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (!\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_control_|bank_af~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h1000; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_control_|bank_af~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout ) # +// (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'h035F; +defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hF8F8; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_bus~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h0777; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~7_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~24_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), + .datab(\z80_|execute_|fMRead~24_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3777; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|fMRead~3_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7757; +defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ixy_d~16_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ixy_d~16_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h557F; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & +// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|execute_|ctl_mRead~17_combout )))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h0222; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sel_pc~10_combout & (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datab(\z80_|execute_|ctl_inc_cy~94_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ctl_inc_cy~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & +// !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|ir_|opcode [5]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h5455; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~49 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~49_combout = (!\z80_|pla_decode_|Equal35~0_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~49 .lut_mask = 16'h00FD; +defparam \z80_|execute_|pc_inc_hold~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) + + .dataa(\z80_|execute_|pc_inc_hold~49_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0A00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|pla_decode_|Equal33~2_combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0515; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'h0003; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( +// Equation(s): +// \z80_|execute_|setM1~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_mRead~9_combout & (\z80_|execute_|pc_inc_hold~28_combout & \z80_|execute_|setM1~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|setM1~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~36 .lut_mask = 16'h2000; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( +// Equation(s): +// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|setM1~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0100; +defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA222; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hC8C8; +defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(gnd), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEE00; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~49_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|pc_inc_hold~49_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hF0B0; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~3_combout = (((\z80_|execute_|ctl_reg_sys_we~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout )) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|execute_|ctl_reg_sys_we~3_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEFFF; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF5D; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~34_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~34_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'h8CCC; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal3~1_combout ) # (!\z80_|pla_decode_|Equal19~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal19~1_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h5777; +defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; +defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h80C0; +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|execute_|ctl_mRead~36_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_al_we~13_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (\z80_|execute_|setM1~52_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datac(\z80_|execute_|setM1~52_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ctl_mRead~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h2022; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~0 ( +// Equation(s): +// \z80_|execute_|fMRead~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~0 .lut_mask = 16'h5D5D; +defparam \z80_|execute_|fMRead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal52~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0030; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h050F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h0FAF; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_reg_sys_hilo~20_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # +// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datac(\z80_|execute_|ctl_inc_dec~4_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hD0DD; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_ir_we~14_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout +// )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00C4; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~49_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~49_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h08CC; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h4455; +defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~0_combout ) # ((!\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|pc_inc_hold~28_combout )))) + + .dataa(\z80_|execute_|fMRead~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00BA; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_al_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4404; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_state_alu~14_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~49_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h0222; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~45_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~1 ( +// Equation(s): +// \z80_|execute_|fMRead~1_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~1 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMRead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMRead~1_combout ))) + + .dataa(\z80_|execute_|fMRead~1_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~46_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~45_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~39_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout ) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_inc_cy~76_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # +// (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~2_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~53_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), + .datab(\z80_|execute_|ctl_inc_cy~77_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & +// (((!\z80_|execute_|ctl_alu_oe~2_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'hA0F3; +defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_sel_wz~10_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & +// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~6_combout ), + .datad(\z80_|execute_|fMRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_reg_sel_wz~11_combout & (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~4_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .datab(\z80_|execute_|ctl_sw_4d~3_combout ), + .datac(\z80_|execute_|ctl_sw_4d~4_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~19_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~19_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~45_combout & !\z80_|execute_|ctl_mWrite~6_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_al_we~13_combout ), + .datac(\z80_|execute_|setM1~45_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h00C0; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~1_combout = ((!\z80_|decode_state_|use_ixiy~combout & ((\z80_|pla_decode_|Equal50~0_combout ) # (\z80_|pla_decode_|Equal49~0_combout )))) # (!\z80_|execute_|setM1~46_combout ) + + .dataa(\z80_|pla_decode_|Equal50~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|setM1~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'h32FF; +defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_al_we~14_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = ((\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout & \z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~5_combout ), + .datab(\z80_|execute_|ctl_sw_4d~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_sw_4d~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( +// Equation(s): +// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; +defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|fMRead~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h5DFF; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & (((\z80_|decode_state_|table_xx~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h00DF; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5010; +defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|setM1~36_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .datad(\z80_|execute_|fMRead~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hF0F7; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((!\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h4FFF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (\z80_|execute_|ctl_reg_sel_pc~18_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0800; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|execute_|ctl_sw_4d~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hF030; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N26 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N27 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N9 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N29 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + // Location: IOIBUF_X53_Y14_N1 cycloneive_io_ibuf \KEY[0]~input ( .i(KEY[0]), @@ -4120,7 +15959,7 @@ defparam \KEY[0]~input .bus_hold = "false"; defparam \KEY[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N6 +// Location: LCCOMB_X52_Y14_N4 cycloneive_lcell_comb reset( // Equation(s): // \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) @@ -4137,7 +15976,7 @@ defparam reset.lut_mask = 16'h0FFF; defparam reset.sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N22 +// Location: LCCOMB_X35_Y13_N26 cycloneive_lcell_comb \z80_|resets_|x1~0 ( // Equation(s): // \z80_|resets_|x1~0_combout = !\reset~combout @@ -4203,7 +16042,7 @@ defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X52_Y17_N23 +// Location: FF_X35_Y13_N27 dffeas \z80_|resets_|x1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|x1~0_combout ), @@ -4222,4021 +16061,25 @@ defparam \z80_|resets_|x1 .is_wysiwyg = "true"; defparam \z80_|resets_|x1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N8 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|x3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hFF44; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y17_N9 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G7 -cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y16_N8 -cycloneive_io_ibuf \KEY[1]~input ( - .i(KEY[1]), - .ibar(gnd), - .o(\KEY[1]~input_o )); -// synopsys translate_off -defparam \KEY[1]~input .bus_hold = "false"; -defparam \KEY[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N12 -cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( -// Equation(s): -// \z80_|interrupts_|nmi_armed~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; -defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N14 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y15_N13 -dffeas \z80_|interrupts_|nmi_armed ( - .clk(!\KEY[1]~input_o ), - .d(\z80_|interrupts_|nmi_armed~feeder_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|nmi_armed~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|nmi_armed .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N26 -cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( -// Equation(s): -// \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|interrupts_|nmi_armed~q ), - .cin(gnd), - .combout(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N24 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h5500; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N20 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N21 -dffeas \z80_|sequencer_|DFFE_M3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N6 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N7 -dffeas \z80_|sequencer_|DFFE_M4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h0303; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0030; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N28 -cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( -// Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|M5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N29 -dffeas \z80_|sequencer_|M5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|M5~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|M5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|M5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~12_combout & -// ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|decode_state_|DFFE_instCB~q & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal46~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [6] & \z80_|ir_|opcode [7]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hC0C0; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0303; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (((!\z80_|execute_|ixy_d~7_combout )) # -// (!\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_alu_core_S~10_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~49_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout )) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|ir_|opcode [7] & (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [6] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ixy_d~4_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ctl_mWrite~16_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_bus_inc_oe~49_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N10 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N11 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|pla_decode_|Equal41~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal33~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC080; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~13_combout & (!\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ixy_d~12_combout ))) # (!\z80_|execute_|ixy_d~13_combout & ((\z80_|execute_|ixy_d~17_combout ) # ((!\z80_|execute_|ixy_d~4_combout -// & \z80_|execute_|ixy_d~12_combout )))) - - .dataa(\z80_|execute_|ixy_d~13_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ixy_d~12_combout ), - .datad(\z80_|execute_|ixy_d~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h7530; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (!\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'h0300; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hC8CC; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h0A00; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|execute_|ixy_d~11_combout & (\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|execute_|ixy_d~14_combout ), - .datab(\z80_|execute_|ixy_d~11_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'hD555; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N4 -cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|ir_|opcode [5] & -// \z80_|pla_decode_|Equal3~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h5530; -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N5 -dffeas \z80_|decode_state_|DFFE_inst4 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_inst4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N20 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( -// Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) - - .dataa(gnd), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFCC; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~9_combout & !\z80_|execute_|ctl_mWrite~4_combout )) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h0011; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hF000; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~36_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~0 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~0_combout = (\z80_|execute_|ctl_inc_cy~36_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_inc_cy~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~0 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_inc_dec~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ctl_inc_dec~0_combout & ((\z80_|execute_|fMWrite~5_combout ) # ((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|fMWrite~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~0_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hFE00; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~12_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout & -// (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~12_combout )) # (!\z80_|execute_|ctl_sw_4u~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|ctl_mRead~12_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hC000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'h007F; -defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( -// Equation(s): -// \z80_|execute_|fIOWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'h5755; -defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( -// Equation(s): -// \z80_|execute_|fMWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h1F1F; -defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal46~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hFF2F; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N8 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|fIOWrite~5_combout & (((\z80_|execute_|fMWrite~0_combout ) # (\z80_|execute_|fMWrite~6_combout )))) # (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|ctl_mWrite~6_combout & -// ((\z80_|execute_|fMWrite~0_combout ) # (\z80_|execute_|fMWrite~6_combout )))) - - .dataa(\z80_|execute_|fIOWrite~5_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|fMWrite~0_combout ), - .datad(\z80_|execute_|fMWrite~6_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'hBBB0; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = ((!\z80_|ir_|opcode [7]) # (!\z80_|execute_|ctl_ir_we~5_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|ir_|opcode [7]), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h3FFF; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal33~1_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N16 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|fMRead~3_combout & ((!\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~8_combout ) # -// (!\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h03AF; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~7_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~1_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal19~1_combout ) # (!\z80_|pla_decode_|Equal3~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h1F3F; -defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N18 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (!\z80_|execute_|fMWrite~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) - - .dataa(\z80_|execute_|fMWrite~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h4000; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (!\z80_|execute_|fMWrite~8_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & \z80_|pin_control_|bus_db_pin_oe~11_combout ))) - - .dataa(\z80_|execute_|fMWrite~8_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h4000; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N12 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h135F; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'hAA2A; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h2A00; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~3_combout = (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~31 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~31_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~31 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|execute_|ctl_inc_cy~31_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|execute_|ctl_inc_cy~31_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h8AAA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~30 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~30_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & -// (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_inc_cy~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_inc_cy~30_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( -// Equation(s): -// \z80_|execute_|fMWrite~1_combout = (!\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = (!\z80_|execute_|fMWrite~1_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|fMWrite~0_combout )))) - - .dataa(\z80_|execute_|fMWrite~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|fMWrite~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h5545; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h3F33; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h3332; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~34_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal19~1_combout )) # (!\z80_|pla_decode_|Equal3~1_combout ) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (((!\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_inc_cy~86_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_inc_cy~85_combout & (\z80_|execute_|ctl_inc_cy~34_combout & \z80_|execute_|ctl_inc_cy~35_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|execute_|ctl_inc_cy~34_combout ), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( -// Equation(s): -// \z80_|execute_|fIOWrite~3_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'hB0B0; -defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal21~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~38 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~38_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~38 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'h7575; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( -// Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|fIOWrite~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|execute_|fIOWrite~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h5F0F; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = (\z80_|execute_|ctl_iorw~10_combout & (((\z80_|execute_|ctl_mWrite~2_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|fMRead~2_combout ))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'hFD00; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( -// Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~0_combout ) # ((\z80_|execute_|fIOWrite~3_combout & \z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|fIOWrite~3_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|fIOWrite~2_combout ), - .datad(\z80_|execute_|fIOWrite~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (!\z80_|execute_|fMWrite~2_combout & (!\z80_|execute_|fMWrite~4_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & !\z80_|execute_|fIOWrite~4_combout ))) - - .dataa(\z80_|execute_|fMWrite~2_combout ), - .datab(\z80_|execute_|fMWrite~4_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h0010; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~32 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~32_combout = ((!\z80_|execute_|ixy_d~4_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~32 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_inc_cy~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~33 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~33_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~32_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_sw_2u~0_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~33 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_inc_cy~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~13_combout & (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~3_combout & \z80_|execute_|ctl_inc_cy~33_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datab(\z80_|execute_|ctl_apin_mux~0_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .datad(\z80_|execute_|ctl_inc_cy~33_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFFAA; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~15_combout = (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|execute_|fIOWrite~4_combout ) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout & \z80_|pin_control_|bus_db_pin_oe~2_combout )))) # (!\z80_|sequencer_|DFFE_T4_ff~q & -// (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|pin_control_|bus_db_pin_oe~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'hBA30; -defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G5 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [2] & !\ula_|ps2_keyboard_|bit_count [1])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0507; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: FF_X25_Y23_N21 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_CLK~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y23_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|clk_filter [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N25 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N7 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [5]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [6]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [4]), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [1] & (!\ula_|ps2_keyboard_|clk_filter [2] & (\ula_|ps2_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|clk_filter [3]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [1]), - .datab(\ula_|ps2_keyboard_|clk_filter [2]), - .datac(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0010; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h00FF; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFA50; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N27 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) - - .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0A00; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N29 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y15_N3 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [0]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1450; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N5 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & -// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N7 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N13 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [2]) # (\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hAAA0; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|always1~0_combout ), - .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h3010; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N27 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N21 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N19 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N15 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N23 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N31 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y15_N3 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~0_combout $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hA55A; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & \ula_|ps2_keyboard_|WideXor0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|clk_edge~q ), - .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N9 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|Equal0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF500; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N15 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~45_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0010; -defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hF830; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [1]) # (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; -defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h1004; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & ((!\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hC0E2; -defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|WideOr16~5_combout & (\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~5_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|WideOr16~7_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF088; -defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N7 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h00C0; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hAA88; -defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|pc_inc_hold~19_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|pc_inc_hold~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hEA00; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~9_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~9_combout )) # -// (!\z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h131F; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & (!\z80_|execute_|ctl_reg_sys_we~0_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~34_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4040; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~13_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~1 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~1_combout = (\z80_|execute_|ctl_inc_cy~37_combout & (((!\z80_|pla_decode_|Equal19~1_combout ) # (!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_inc_cy~37_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~1 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_inc_dec~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_dec~1_combout & (\z80_|execute_|ctl_inc_dec~0_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3F0F; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|fIOWrite~5_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|fIOWrite~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~38_combout ))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|execute_|ctl_mWrite~3_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h1F5F; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_inc_dec~4_combout ) # (((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_inc_dec~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .datad(\z80_|execute_|ctl_inc_dec~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'hCEFF; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (((\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )) # (!\z80_|execute_|ctl_inc_dec~7_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|execute_|ctl_inc_dec~2_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N28 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h00FF; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N29 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N22 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N23 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X51_Y12_N27 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N0 +// Location: LCCOMB_X29_Y17_N18 cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( // Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|resets_|clrpc_int~q & ((!\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|resets_|clrpc_int~q & -// (!\z80_|resets_|x1~q & \z80_|sequencer_|DFFE_T2_ff~q )))) +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # +// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|resets_|x1~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), .datac(\z80_|resets_|clrpc_int~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|resets_|x1~q ), .cin(gnd), .combout(\z80_|resets_|clrpc_int~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hA1F0; +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X51_Y12_N1 +// Location: FF_X29_Y17_N19 dffeas \z80_|resets_|clrpc_int ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|clrpc_int~0_combout ), @@ -8255,13 +16098,13 @@ defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; defparam \z80_|resets_|clrpc_int .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y12_N26 +// Location: LCCOMB_X29_Y17_N28 cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( // Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), .datac(\z80_|resets_|DFFE_intr_ff3~q ), .datad(\z80_|resets_|clrpc_int~q ), .cin(gnd), @@ -8272,9478 +16115,181 @@ defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .lut_mask = 16'h1300; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|pla_decode_|Equal38~2_combout & (!\z80_|execute_|ixy_d~4_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~4_combout & -// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_inc_cy~76_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ixy_d~4_combout ))) # (!\z80_|execute_|ctl_mRead~18_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & -// !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0357; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~50_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hF000; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|ir_|opcode [3]))) - - .dataa(\z80_|execute_|comb~1_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .datab(\z80_|pla_decode_|Equal4~0_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (\z80_|execute_|ctl_inc_cy~47_combout & (\z80_|execute_|ctl_bus_inc_oe~48_combout & \z80_|execute_|ctl_bus_inc_oe~26_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~77_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3])) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|pla_decode_|Equal56~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0101; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~4_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_sw_4u~2_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_sw_4u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (((\z80_|ir_|opcode [5]) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0F07; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~38_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'hAFBF; -defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout = (\z80_|execute_|ctl_inc_cy~82_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~87_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~82_combout ), - .datab(\z80_|execute_|ctl_inc_cy~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~87_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout = (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout -// )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'h040C; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0003; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hC0C0; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~34_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~34 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout & \z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal1~5_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal1~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'hFDDD; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (((\z80_|execute_|ctl_sw_4u~4_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~16_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .datac(\z80_|execute_|ctl_sw_4u~4_combout ), - .datad(\z80_|execute_|ctl_apin_mux~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~19_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( -// Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal29~0_combout & (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|pla_decode_|Equal29~0_combout & -// !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~3_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~13_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~3 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( -// Equation(s): -// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|execute_|ctl_mRead~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( -// Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|fMRead~13_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'h3070; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~25_combout = (\z80_|execute_|fMRead~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~3_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|fMRead~14_combout ))) - - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datad(\z80_|execute_|fMRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_mRead~13_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( -// Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h01FF; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~25_combout )) - - .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hBBFF; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N22 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h0303; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5515; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal12~0_combout ) - - .dataa(\z80_|pla_decode_|Equal12~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h2020; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~16_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0011; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_sw_1d~8_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|decode_state_|DFFE_instCB~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~3_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFBB; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|ir_|opcode [1])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|execute_|ctl_flags_oe~0_combout & \z80_|execute_|ctl_al_we~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_flags_oe~0_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hAFAF; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & !\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~8_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & (!\z80_|pla_decode_|Equal68~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|pla_decode_|Equal68~2_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal46~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|pla_decode_|Equal20~0_combout & !\z80_|execute_|ctl_ir_we~8_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h000F; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_hf_cpl~8_combout & (\z80_|execute_|setM1~47_combout & (\z80_|execute_|nextM~2_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datab(\z80_|execute_|setM1~47_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|setM1~48_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~1_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h004C; -defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_in_hi~8_combout & (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_mRead~19_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout -// & (((!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_mRead~19_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~18_combout & -// (((!\z80_|execute_|ctl_mRead~19_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~2_combout = (\z80_|execute_|ctl_mRead~27_combout & (\z80_|execute_|setM1~30_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|setM1~30_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~2 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & ((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|pla_decode_|Equal21~1_combout -// )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0007; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h035F; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h3233; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & \z80_|execute_|ctl_state_alu~9_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout -// & (\z80_|execute_|ctl_state_alu~5_combout & (\z80_|execute_|ctl_state_alu~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|pla_decode_|Equal52~1_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hF5C4; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal3~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout = ((!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .lut_mask = 16'h337F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h5551; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal64~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hFAFF; -defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal3~1_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_alu_oe~9_combout & (((!\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_mRead~28_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mRead~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & \z80_|execute_|ctl_alu_oe~10_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|execute_|ctl_alu_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_mRead~20_combout ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout & \z80_|execute_|ctl_reg_gp_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_we~5_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~2_combout & \z80_|execute_|ctl_reg_gp_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~8_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~9_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|execute_|setM1~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .lut_mask = 16'h8AFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_alu_op_low~19_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'h3233; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hCC04; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~51_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~51 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ctl_mRead~7_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~4_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .lut_mask = 16'h4C44; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h6A6A; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .lut_mask = 16'hFAFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h3FC0; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~10_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_sw_2u~0_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~50_combout = (\z80_|execute_|ctl_sw_2u~3_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|sequencer_|M5~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_sw_2u~3_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~50 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~5_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_gp_sel~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_2u~5_combout ) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ) # (((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .lut_mask = 16'hBFAF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout ) # -// (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h0757; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|pla_decode_|Equal4~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h030F; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|pla_decode_|Equal2~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|setM1~41_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h0023; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~25_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_state_alu~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h000C; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (!\z80_|execute_|ctl_mRead~15_combout & (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_ir_we~12_combout & \z80_|execute_|fMRead~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|fMWrite~1_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (((\z80_|ir_|opcode [7]) # (!\z80_|decode_state_|DFFE_instED~q )) # (!\z80_|ir_|opcode [6])) # (!\z80_|pla_decode_|Equal1~4_combout ) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_mRead~21_combout & (\z80_|execute_|ctl_iorw~12_combout & (!\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ctl_al_we~13_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~21_combout ), - .datab(\z80_|execute_|ctl_iorw~12_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h0800; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h3BBB; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal44~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~38_combout & !\z80_|execute_|ctl_iorw~11_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (\z80_|execute_|ctl_alu_shift_oe~26_combout & ((!\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal32~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|execute_|ixy_d~10_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_flags_bus~6_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_flags_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal76~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal76~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4])) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal76~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = ((!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|pla_decode_|Equal76~0_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|pla_decode_|Equal76~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|execute_|ctl_alu_op_low~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_flags_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~7_combout & (\z80_|execute_|ctl_flags_bus~8_combout & (\z80_|execute_|ctl_flags_bus~14_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), - .datab(\z80_|execute_|ctl_flags_bus~8_combout ), - .datac(\z80_|execute_|ctl_flags_bus~14_combout ), - .datad(\z80_|execute_|ctl_flags_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout & \z80_|execute_|ctl_flags_bus~10_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_flags_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h1115; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h0111; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~7_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~22_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|execute_|ctl_mRead~22_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~7 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & \z80_|execute_|ctl_reg_gp_sel[0]~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datab(\z80_|execute_|nextM~11_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal21~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # (\z80_|sequencer_|M5~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h0302; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~34_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~34 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((!\z80_|pla_decode_|Equal12~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hB0F5; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & (\z80_|execute_|ctl_ir_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~6_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hF808; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~2_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~34_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h80F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # (\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ))) # -// (!\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal2~1_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal4~0_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'hA8A0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'h0F0E; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # ((\z80_|execute_|ctl_mRead~38_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~56 ( -// Equation(s): -// \z80_|execute_|setM1~56_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~56 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout = (\z80_|execute_|setM1~56_combout & (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|setM1~56_combout ), - .datab(\z80_|execute_|ctl_sw_2u~1_combout ), - .datac(\z80_|execute_|ctl_sw_2u~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|ir_|opcode [2] & !\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~26_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~5_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~26 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~7_combout & (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout & \z80_|execute_|ctl_reg_gp_sel[0]~26_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~25_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_mRead~38_combout ) # ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'h3377; -defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_ir_we~12_combout & \z80_|execute_|fMRead~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|fMWrite~1_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # (!\z80_|execute_|ctl_mRead~29_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_mRead~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hB3F3; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~29 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~24_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~24 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_reg_sys_hilo~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ctl_reg_sys_hilo~24_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h22A2; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~31_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & -// ((\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~31 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~31_combout ) # ((\z80_|ir_|opcode [1] & !\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~31_combout ), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'hAAEE; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~28_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal1~5_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N18 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|pla_decode_|Equal1~6_combout & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|pla_decode_|Equal1~6_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hF078; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N19 -dffeas \z80_|reg_control_|bank_exx ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0200; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0200; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFFEE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N0 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((\z80_|pla_decode_|Equal32~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal21~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N1 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|reg_control_|bank_af~q & (!\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0200; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_control_|bank_af~q & (!\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h0800; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h4400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|pla_decode_|Equal19~0_combout )) # -// (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h07FF; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal29~0_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal38~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~11_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_sel_wz~6_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & \z80_|execute_|ctl_reg_in_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|execute_|ctl_mRead~11_combout & -// ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h45CF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # ((\z80_|execute_|ctl_mRead~19_combout ) # (\z80_|pla_decode_|Equal34~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_mRead~19_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~4_combout ) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal25~0_combout ), - .datac(\z80_|pla_decode_|Equal12~1_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h55F7; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ixy_d~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ixy_d~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|execute_|ixy_d~4_combout & -// (((!\z80_|execute_|ixy_d~16_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (!\z80_|execute_|ctl_reg_sel_pc~9_combout & (\z80_|execute_|ctl_reg_sel_pc~7_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h1050; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout = (\z80_|execute_|ctl_inc_cy~82_combout & (\z80_|execute_|ctl_inc_cy~38_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~87_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~82_combout ), - .datab(\z80_|execute_|ctl_inc_cy~38_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datad(\z80_|execute_|ctl_inc_cy~87_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_mWrite~16_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_sel_pc~11_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ixy_d~16_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ixy_d~16_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~40_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~40 .lut_mask = 16'h4050; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_ir_we~6_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~18_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'h001F; -defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (!\z80_|execute_|ctl_mRead~19_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h00AF; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (!\z80_|execute_|ctl_reg_sel_wz~7_combout & ((\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00FE; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & ((\z80_|execute_|fMRead~2_combout ) # ((!\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|pc_inc_hold~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|fMRead~2_combout ), - .datac(\z80_|execute_|pc_inc_hold~18_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h00DC; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal40~0_combout ) - - .dataa(\z80_|pla_decode_|Equal40~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h57FF; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout = (!\z80_|pla_decode_|Equal24~1_combout & (!\z80_|pla_decode_|Equal19~0_combout & (!\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~1_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .lut_mask = 16'h050F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~40_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h3323; -defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0101; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (\z80_|pla_decode_|Equal33~3_combout & (\z80_|execute_|ctl_inc_dec~3_combout & ((\z80_|execute_|ctl_reg_sys_hilo~24_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )))) # -// (!\z80_|pla_decode_|Equal33~3_combout & (((\z80_|execute_|ctl_reg_sys_hilo~24_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_inc_dec~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'hF531; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4500; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & (((\z80_|execute_|pc_inc_hold~40_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~40_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h3B00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h4500; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~16_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (!\z80_|execute_|ctl_reg_sys_hilo~20_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hA8AA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h8C0C; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (\z80_|execute_|setM1~52_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout & \z80_|execute_|ctl_reg_sel_pc~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~20_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~19_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h5444; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # (((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~10_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_ir_we~4_combout & (((\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~7_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((\z80_|execute_|ctl_reg_sel_wz~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hCF05; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & \z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~19_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'hFFDC; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal38~2_combout ) # (\z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N4 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .datac(\z80_|pla_decode_|Equal24~1_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N4 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|reg_control_|reg_sys_we_lo~1_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h0777; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # (\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~24_combout & !\z80_|execute_|ctl_mRead~23_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~24_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datad(\z80_|execute_|ctl_mRead~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h01FF; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~3_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h2A00; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~25_combout & (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal13~1_combout )) # (!\z80_|pla_decode_|Equal13~0_combout ) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'hEAEA; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~11_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_bus~4_combout ), - .datad(\z80_|execute_|ctl_flags_bus~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'hCC4C; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( -// Equation(s): -// \z80_|execute_|fMRead~27_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_alu_shift_oe~28_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_flags_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~12_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~27_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~12_combout ), - .datab(\z80_|execute_|fMRead~27_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~7_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .lut_mask = 16'hBABB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~36_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & \z80_|execute_|ctl_alu_op_low~36_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_state_alu~7_combout & !\z80_|execute_|ctl_alu_shift_oe~15_combout )) - - .dataa(\z80_|execute_|ctl_sw_2u~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'h0088; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (\z80_|execute_|ctl_alu_op_low~21_combout & (!\z80_|execute_|ctl_reg_gp_sel~5_combout & (\z80_|execute_|setM1~17_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datac(\z80_|execute_|setM1~17_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_mRead~38_combout & (!\z80_|execute_|ctl_mRead~13_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_mRead~38_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~27_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hC8CC; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~2_combout = (\z80_|execute_|ctl_flags_cf_we~7_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_flags_use_cf2~13_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_pf_sel[0]~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & (\z80_|execute_|ctl_alu_oe~6_combout & \z80_|execute_|ctl_flags_pf_we~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~6_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~11_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|ir_|opcode [5] & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mRead~38_combout )))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mWrite~7_combout & ((!\z80_|execute_|ctl_mWrite~2_combout )))) # (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_ir_we~11_combout )) -// # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datad(\z80_|pla_decode_|Equal20~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_xy_we~16_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~13_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ctl_reg_use_sp~1_combout & \z80_|execute_|ctl_flags_alu~14_combout ))) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1010; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T5_ff~q )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal10~0_combout & ((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (((!\z80_|execute_|ixy_d~5_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & \z80_|execute_|ctl_flags_alu~10_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~11_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datab(\z80_|execute_|ctl_flags_alu~11_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~6_combout = (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~8_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|execute_|ctl_flags_alu~6_combout & \z80_|execute_|ctl_flags_alu~17_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_alu~6_combout ), - .datad(\z80_|execute_|ctl_flags_alu~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal56~0_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal1~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal1~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hEFCC; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~19_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~19_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~9_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_flags_alu~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout ))) # (!\z80_|execute_|ctl_flags_alu~8_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .datac(\z80_|execute_|ctl_flags_alu~7_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (((\z80_|execute_|ctl_flags_alu~9_combout ) # (!\z80_|execute_|ctl_flags_alu~12_combout )) # (!\z80_|execute_|ctl_flags_alu~15_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_alu~15_combout ), - .datac(\z80_|execute_|ctl_flags_alu~12_combout ), - .datad(\z80_|execute_|ctl_flags_alu~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFFE0; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~6_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|execute_|ctl_reg_gp_sel~5_combout & (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|execute_|comb~0_combout -// $ (!\z80_|ir_|opcode [0])))) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'hD00D; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout & !\z80_|execute_|ctl_sw_2u~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ), - .datad(\z80_|execute_|ctl_sw_2u~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|execute_|nextM~2_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hC040; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = (((\z80_|execute_|ctl_reg_out_hi~8_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N20 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N21 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~28_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h3323; -defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & !\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; -defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h3120; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h3210; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N12 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N13 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de2~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hC840; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~22_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~22 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de2~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hC480; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_hl2~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~23_combout = (\z80_|reg_file_|gdfx_temp1[7]~22_combout & (\z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~23 .lut_mask = 16'hC400; -defparam \z80_|reg_file_|gdfx_temp1[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_af~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_control_|bank_exx~q & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|reg_control_|bank_exx~q & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~24 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h1115; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_mRead~7_combout -// & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h2020; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (\z80_|execute_|ctl_reg_in_hi~10_combout & (\z80_|execute_|ctl_reg_in_hi~7_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = ((\z80_|execute_|ctl_reg_in_hi~9_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~11_combout ) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~26_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[7]~20_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~26 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|decode_state_|DFFE_inst4~q & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~25_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~25 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (!\z80_|pla_decode_|Equal33~3_combout & (!\z80_|pla_decode_|Equal24~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal6~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|pla_decode_|Equal24~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|execute_|ctl_mWrite~16_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~32_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hBFAF; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~1_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hDDD5; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (!\z80_|execute_|ctl_mRead~16_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~0_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~39_combout = (\z80_|execute_|pc_inc_hold~18_combout & (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|pc_inc_hold~18_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~39 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_reg_sys_hilo~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (\z80_|execute_|setM1~36_combout & (\z80_|execute_|ctl_reg_sys_hilo~39_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ))) - - .dataa(\z80_|execute_|setM1~36_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~39_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h0800; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( -// Equation(s): -// \z80_|execute_|fMRead~11_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~37_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'h0004; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (((\z80_|execute_|ctl_bus_inc_oe~31_combout & \z80_|execute_|fMRead~11_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datac(\z80_|execute_|fMRead~11_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h80AA; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFDFF; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~17_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~27 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[7]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~28_combout = (\z80_|reg_file_|gdfx_temp1[7]~24_combout & (\z80_|reg_file_|gdfx_temp1[7]~26_combout & (\z80_|reg_file_|gdfx_temp1[7]~25_combout & \z80_|reg_file_|gdfx_temp1[7]~27_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~27_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_32 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~29_combout = (\z80_|reg_file_|gdfx_temp1[7]~23_combout & (\z80_|reg_file_|gdfx_temp1[7]~28_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~23_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datac(\z80_|reg_file_|gdfx_temp1[7]~28_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~29 .lut_mask = 16'h80A0; -defparam \z80_|reg_file_|gdfx_temp1[7]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~30_combout = ((\z80_|reg_file_|gdfx_temp1[7]~29_combout & ((\z80_|reg_file_|db_hi_as[7]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~29_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~30 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp1[7]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_shift_oe~15_combout ) # (\z80_|execute_|ctl_alu_op_low~20_combout )))) - - .dataa(\z80_|execute_|rsel3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~16_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h3133; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_iorw~10_combout & \z80_|execute_|rsel3~combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hB030; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_sw_2d~14_combout ), - .datad(\z80_|execute_|ctl_sw_2d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hFF2A; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = (\z80_|execute_|ctl_flags_alu~19_combout & (((!\z80_|execute_|ctl_mRead~28_combout & !\z80_|execute_|ctl_mRead~22_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_mRead~28_combout ), - .datac(\z80_|execute_|ctl_flags_alu~19_combout ), - .datad(\z80_|execute_|ctl_mRead~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~6_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~7_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h7030; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (\z80_|execute_|ixy_d~15_combout & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h070F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~13_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~7_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~7_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_sw_2d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & \z80_|execute_|ctl_sw_2d~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|ctl_sw_2d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~25_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~20_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~25_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h40C0; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_flags_alu~6_combout & \z80_|execute_|ctl_flags_alu~17_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_flags_alu~6_combout ), - .datad(\z80_|execute_|ctl_flags_alu~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|execute_|ctl_mRead~20_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (((!\z80_|execute_|ctl_mRead~20_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|ctl_sw_2d~4_combout ))) - - .dataa(\z80_|execute_|fMRead~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~9_combout ), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|ctl_sw_2d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( -// Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_mRead~26_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~2_combout & \z80_|execute_|fMRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & (\z80_|execute_|ctl_sw_2d~8_combout & \z80_|execute_|fMRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datac(\z80_|execute_|ctl_sw_2d~8_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~12_combout ) # ((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~12_combout ), - .datac(\z80_|execute_|ctl_sw_2d~11_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N0 -cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( -// Equation(s): -// \z80_|alu_|db[7]~19_combout = (\z80_|alu_control_|db[7]~18_combout & (((\z80_|reg_file_|gdfx_temp1[7]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_control_|db[7]~18_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[7]~30_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[7]~18_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_alu_oe~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hCF8F; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_alu_oe~12_combout ) # ((\z80_|execute_|ctl_alu_oe~11_combout ) # (!\z80_|execute_|ctl_alu_oe~10_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_oe~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h3F00; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_reg_in_hi~7_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_mWrite~8_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mRead~22_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_alu_oe~7_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|ctl_bus_db_we~5_combout & \z80_|execute_|ctl_alu_oe~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_alu_oe~8_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~13_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_alu_oe~8_combout ), - .datad(\z80_|execute_|ctl_flags_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout -// & (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_ir_we~7_combout & (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & \z80_|execute_|ctl_flags_sz_we~0_combout -// ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~1_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal1~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal1~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op_low~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_mRead~38_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # -// (!\z80_|execute_|ctl_mRead~38_combout & (((!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~31_combout & (\z80_|execute_|ctl_alu_shift_oe~30_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h0507; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|execute_|ctl_mWrite~2_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout -// & (((!\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~5_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout & \z80_|execute_|ctl_alu_op1_sel_bus~6_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~12_combout & (\z80_|execute_|ctl_flags_xy_we~12_combout & ((!\z80_|pla_decode_|Equal48~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) # (((!\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~4_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_66_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[3]~19_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~19_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00A0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFAA; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N13 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_hl2~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~49_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~49 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~50_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout & (\z80_|reg_file_|gdfx_temp1[3]~49_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datad(\z80_|reg_file_|gdfx_temp1[3]~49_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~50 .lut_mask = 16'hC400; -defparam \z80_|reg_file_|gdfx_temp1[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~52 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~51 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~54 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[3]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~53_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[3]~14_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[3]~14_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~53 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~55_combout = (\z80_|reg_file_|gdfx_temp1[3]~52_combout & (\z80_|reg_file_|gdfx_temp1[3]~51_combout & (\z80_|reg_file_|gdfx_temp1[3]~54_combout & \z80_|reg_file_|gdfx_temp1[3]~53_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~52_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~54_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~56_combout = (\z80_|reg_file_|gdfx_temp1[3]~50_combout & (\z80_|reg_file_|gdfx_temp1[3]~55_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datab(\z80_|reg_file_|gdfx_temp1[3]~50_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~55_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~56 .lut_mask = 16'h80C0; -defparam \z80_|reg_file_|gdfx_temp1[3]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_bus_inc_oe~32_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~11_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal21~1_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'h000F; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|setM1~37_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~15_combout )))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datac(\z80_|execute_|setM1~37_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'hFF15; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_al_we~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sel_wz~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~4_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0C00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h2FFF; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~18_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # (\z80_|execute_|ctl_reg_sel_pc~17_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (\z80_|reg_control_|reg_sel_pc~2_combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h2000; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0200; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|reg_control_|reg_sel_pc~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h0F0A; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = (\z80_|execute_|ctl_reg_sel_ir~0_combout ) # (((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hCFEF; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hF777; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEEFF; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|setM1~46_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|setM1~46_combout ), - .datac(\z80_|execute_|ctl_alu_oe~5_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_flags_bus~5_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h0DDD; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~3_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|fMRead~14_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|fMRead~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|fMRead~14_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|fMRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~4_combout & (\z80_|execute_|ctl_reg_sel_wz~13_combout & (\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datac(\z80_|execute_|ctl_sw_4d~3_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_4d~0_combout ), - .datac(\z80_|execute_|ctl_sw_4d~1_combout ), - .datad(\z80_|execute_|ctl_sw_4d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hF700; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [3] & ((\z80_|reg_file_|gdfx_temp1[3]~57_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[3]~57_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|reg_control_|reg_sel_pc~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~14_combout = (\z80_|reg_file_|db_hi_as[3]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~13_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~14 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~15_combout ) +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) .dataa(gnd), .datab(gnd), .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~15_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), + .combout(\z80_|address_latch_|abusz [7]), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_ir_we~4_combout & (((!\z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_state_alu~4_combout & -// ((!\z80_|execute_|ctl_al_we~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h32FA; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~9_combout ) # (((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) - - .dataa(\z80_|execute_|ctl_al_we~9_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N20 +// Location: LCCOMB_X37_Y17_N14 cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), .combout(\z80_|execute_|ctl_apin_mux~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h3322; +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N2 +// Location: LCCOMB_X37_Y17_N26 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( // Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((!\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )) # (!\z80_|execute_|ctl_al_we~5_combout ))) - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_al_we~5_combout ), - .datad(\z80_|execute_|ctl_apin_mux~1_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|execute_|ctl_al_we~14_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hAA2A; defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y18_N4 +// Location: LCCOMB_X40_Y17_N8 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( // Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = (((!\z80_|execute_|ctl_al_we~4_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) +// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & (\z80_|execute_|ctl_ir_we~4_combout & +// ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datab(\z80_|execute_|ctl_alu_oe~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_al_we~13_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h0EEE; defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y17_N18 +// Location: LCCOMB_X40_Y17_N30 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( // Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_al_we~7_combout ) # (!\z80_|execute_|ctl_iorw~12_combout )) # (!\z80_|execute_|ctl_mRead~21_combout ))) +// \z80_|execute_|ctl_al_we~8_combout = ((\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - .dataa(\z80_|execute_|ctl_mRead~21_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ctl_iorw~12_combout ), - .datad(\z80_|execute_|ctl_al_we~7_combout ), + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_al_we~7_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBF3; defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N16 +// Location: LCCOMB_X34_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = (((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout )) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), + .datab(\z80_|execute_|ctl_al_we~4_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_al_we~9_combout ) # (!\z80_|execute_|setM1~45_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|setM1~45_combout ), + .datad(\z80_|execute_|ctl_al_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEEAE; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N0 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( // Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~10_combout ) # ((\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) +// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - .dataa(\z80_|execute_|ctl_al_we~10_combout ), - .datab(\z80_|execute_|ctl_al_we~6_combout ), + .dataa(\z80_|execute_|ctl_al_we~6_combout ), + .datab(gnd), .datac(\z80_|execute_|ctl_sw_4d~5_combout ), - .datad(\z80_|execute_|ctl_al_we~8_combout ), + .datad(\z80_|execute_|ctl_al_we~10_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFAF; defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N18 +// Location: LCCOMB_X41_Y18_N4 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( // Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = ((\z80_|execute_|ctl_al_we~11_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|setM1~52_combout ) +// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|setM1~52_combout )) - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_al_we~11_combout ), .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hEFCF; defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N5 -dffeas \z80_|address_latch_|Q[11] ( +// Location: FF_X30_Y16_N5 +dffeas \z80_|address_latch_|Q[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), + .d(\z80_|address_latch_|abusz [7]), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -17752,724 +16298,119 @@ dffeas \z80_|address_latch_|Q[11] ( .ena(\z80_|execute_|ctl_al_we~12_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), + .q(\z80_|address_latch_|Q [7]), .prn(vcc)); // synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Location: LCCOMB_X35_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) +// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - .dataa(gnd), - .datab(\z80_|address_latch_|Q [11]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h33CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Location: LCCOMB_X36_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) +// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|execute_|ctl_inc_cy~77_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_inc_cy~47_combout & \z80_|execute_|ctl_inc_cy~78_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_inc_cy~78_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|fMRead~3_combout ))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (\z80_|execute_|ctl_bus_inc_oe~39_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~48_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # (\z80_|execute_|ctl_bus_inc_oe~37_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~45_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFD55; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~46_combout ) # (\z80_|execute_|ctl_bus_inc_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = (((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~15_combout = ((\z80_|reg_file_|db_hi_as[3]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[3]~14_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~15 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_hi_as[3]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~57_combout = ((\z80_|reg_file_|gdfx_temp1[3]~56_combout & ((\z80_|reg_file_|db_hi_as[3]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~56_combout ), - .datab(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~57 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|gdfx_temp1[3]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N28 -cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( -// Equation(s): -// \z80_|alu_|db[3]~13_combout = (\z80_|alu_|db_low[3]~23_combout & (((\z80_|reg_file_|gdfx_temp1[3]~57_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_|db_low[3]~23_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & -// ((\z80_|reg_file_|gdfx_temp1[3]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_|db_low[3]~23_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|setM1~48_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h040C; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_flags_alu~16_combout & ((\z80_|alu_|db_low[3]~23_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[3]~35_combout )))) # -// (!\z80_|execute_|ctl_flags_alu~16_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[3]~35_combout )))) - - .dataa(\z80_|execute_|ctl_flags_alu~16_combout ), - .datab(\z80_|alu_|db_low[3]~23_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .combout(\z80_|execute_|fIOWrite~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFFCF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3373; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Location: LCCOMB_X36_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( // Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & \z80_|execute_|ctl_flags_sz_we~5_combout )))) # -// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_alu_core_R~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout ))) +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_inc_dec~4_combout ))) - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|execute_|ctl_inc_dec~4_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Location: LCCOMB_X36_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( // Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) +// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~0_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_inc_dec~3_combout ), + .datad(\z80_|execute_|ctl_inc_dec~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hFF4F; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF3F3; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( // Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) +// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # (((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout )) # -// (!\z80_|execute_|ctl_flags_xy_we~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_flags_xy_we~13_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~7_combout ) # (!\z80_|execute_|ctl_flags_xy_we~16_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = ((\z80_|execute_|ctl_flags_xy_we~14_combout ) # ((!\z80_|execute_|ctl_flags_pf_we~4_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y15_N19 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N28 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( -// Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( -// Equation(s): -// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_flags_|flags_xf~q ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF300; -defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~30_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|M5~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_inc_cy~30_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal48~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .lut_mask = 16'hBAAA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~35_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout & \z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~35 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~42_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~42 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h55FF; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( +// Location: FF_X31_Y17_N17 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -18478,28 +16419,1319 @@ dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Location: LCCOMB_X26_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N1 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hCA00; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h1000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2A2; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[2]~29_combout & +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|alu_control_|db[2]~29_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datac(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8CAF; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0020; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[2]~42_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N31 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[0]~12_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .datad(\z80_|alu_control_|db[0]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~16_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & \z80_|reg_file_|gdfx_temp0[0]~13_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|reg_file_|gdfx_temp0[0]~22_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; // synopsys translate_on // Location: CLKCTRL_G18 @@ -18515,25 +17747,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N6 -cycloneive_lcell_comb \ula_|video_|Add0~0 ( -// Equation(s): -// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) -// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add0~0_combout ), - .cout(\ula_|video_|Add0~1 )); -// synopsys translate_off -defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; -defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N20 +// Location: LCCOMB_X39_Y33_N16 cycloneive_lcell_comb \ula_|video_|Add0~14 ( // Equation(s): // \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) @@ -18551,50 +17765,50 @@ defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N22 +// Location: LCCOMB_X39_Y33_N18 cycloneive_lcell_comb \ula_|video_|Add0~16 ( // Equation(s): // \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) // \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [8]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~15 ), .combout(\ula_|video_|Add0~16_combout ), .cout(\ula_|video_|Add0~17 )); // synopsys translate_off -defparam \ula_|video_|Add0~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N0 +// Location: LCCOMB_X39_Y33_N26 cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( // Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) - .dataa(\ula_|video_|Add0~16_combout ), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~16_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hAA00; +defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y31_N15 +// Location: FF_X39_Y33_N27 dffeas \ula_|video_|vga_hc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~2_combout ), + .d(\ula_|video_|vga_hc~2_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18605,32 +17819,32 @@ defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N24 +// Location: LCCOMB_X39_Y33_N20 cycloneive_lcell_comb \ula_|video_|Add0~18 ( // Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|vga_hc [9] $ (\ula_|video_|Add0~17 ) +// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) .dataa(gnd), - .datab(\ula_|video_|vga_hc [9]), + .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|vga_hc [9]), .cin(\ula_|video_|Add0~17 ), .combout(\ula_|video_|Add0~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h3C3C; +defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N4 +// Location: LCCOMB_X37_Y33_N20 cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( // Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) .dataa(gnd), - .datab(\ula_|video_|Add0~18_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~18_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~1_combout ), .cout()); @@ -18639,15 +17853,15 @@ defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y31_N29 +// Location: FF_X37_Y33_N21 dffeas \ula_|video_|vga_hc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~1_combout ), + .d(\ula_|video_|vga_hc~1_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18658,58 +17872,25 @@ defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N20 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Location: LCCOMB_X39_Y33_N2 +cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [0] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) +// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) +// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - .dataa(\ula_|video_|vga_hc [2]), + .dataa(gnd), .datab(\ula_|video_|vga_hc [0]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), + .datac(gnd), + .datad(vcc), .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); + .combout(\ula_|video_|Add0~0_combout ), + .cout(\ula_|video_|Add0~1 )); // synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N14 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & (\ula_|video_|vga_hc [5] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [4]), - .datac(\ula_|video_|vga_hc [5]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h1000; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N24 -cycloneive_lcell_comb \ula_|video_|Equal1~0 ( -// Equation(s): -// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|Equal0~1_combout ), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hFF7F; -defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N6 +// Location: LCCOMB_X34_Y31_N0 cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( // Equation(s): // \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) @@ -18726,15 +17907,15 @@ defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N11 +// Location: FF_X34_Y31_N1 dffeas \ula_|video_|vga_hc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~3_combout ), + .d(\ula_|video_|vga_hc~3_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18745,7 +17926,7 @@ defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N8 +// Location: LCCOMB_X39_Y33_N4 cycloneive_lcell_comb \ula_|video_|Add0~2 ( // Equation(s): // \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) @@ -18763,15 +17944,32 @@ defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y31_N17 +// Location: LCCOMB_X36_Y33_N16 +cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( +// Equation(s): +// \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Add0~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N17 dffeas \ula_|video_|vga_hc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~2_combout ), + .d(\ula_|video_|vga_hc[1]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18782,50 +17980,33 @@ defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N10 +// Location: LCCOMB_X39_Y33_N6 cycloneive_lcell_comb \ula_|video_|Add0~4 ( // Equation(s): // \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) // \ula_|video_|Add0~5 = CARRY((\ula_|video_|vga_hc [2] & !\ula_|video_|Add0~3 )) - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~3 ), .combout(\ula_|video_|Add0~4_combout ), .cout(\ula_|video_|Add0~5 )); // synopsys translate_off -defparam \ula_|video_|Add0~4 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N22 -cycloneive_lcell_comb \ula_|video_|vga_hc[2]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[2]~feeder_combout = \ula_|video_|Add0~4_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~4_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y31_N23 +// Location: FF_X39_Y33_N23 dffeas \ula_|video_|vga_hc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[2]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|Add0~4_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18836,7 +18017,7 @@ defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N12 +// Location: LCCOMB_X39_Y33_N8 cycloneive_lcell_comb \ula_|video_|Add0~6 ( // Equation(s): // \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) @@ -18854,10 +18035,27 @@ defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N13 +// Location: LCCOMB_X36_Y33_N8 +cycloneive_lcell_comb \ula_|video_|vga_hc[3]~feeder ( +// Equation(s): +// \ula_|video_|vga_hc[3]~feeder_combout = \ula_|video_|Add0~6_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Add0~6_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vga_hc[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N9 dffeas \ula_|video_|vga_hc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add0~6_combout ), + .d(\ula_|video_|vga_hc[3]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -18873,25 +18071,25 @@ defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N14 +// Location: LCCOMB_X39_Y33_N10 cycloneive_lcell_comb \ula_|video_|Add0~8 ( // Equation(s): // \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) // \ula_|video_|Add0~9 = CARRY((\ula_|video_|vga_hc [4] & !\ula_|video_|Add0~7 )) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [4]), + .dataa(\ula_|video_|vga_hc [4]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~7 ), .combout(\ula_|video_|Add0~8_combout ), .cout(\ula_|video_|Add0~9 )); // synopsys translate_off -defparam \ula_|video_|Add0~8 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N3 +// Location: FF_X39_Y33_N31 dffeas \ula_|video_|vga_hc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18910,7 +18108,58 @@ defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N16 +// Location: LCCOMB_X34_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N30 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( +// Equation(s): +// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) + + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|vga_hc [4]), + .datad(\ula_|video_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0200; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y33_N16 +cycloneive_lcell_comb \ula_|video_|Equal1~0 ( +// Equation(s): +// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; +defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N12 cycloneive_lcell_comb \ula_|video_|Add0~10 ( // Equation(s): // \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) @@ -18928,32 +18177,32 @@ defparam \ula_|video_|Add0~10 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N26 +// Location: LCCOMB_X39_Y33_N0 cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( // Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) - .dataa(\ula_|video_|Add0~10_combout ), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~10_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hAA00; +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y31_N1 +// Location: FF_X39_Y33_N1 dffeas \ula_|video_|vga_hc[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~0_combout ), + .d(\ula_|video_|vga_hc~0_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18964,7 +18213,7 @@ defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N18 +// Location: LCCOMB_X39_Y33_N14 cycloneive_lcell_comb \ula_|video_|Add0~12 ( // Equation(s): // \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) @@ -18982,7 +18231,7 @@ defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N5 +// Location: FF_X39_Y33_N29 dffeas \ula_|video_|vga_hc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -19001,7 +18250,7 @@ defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X31_Y31_N27 +// Location: FF_X39_Y33_N25 dffeas \ula_|video_|vga_hc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -19020,61 +18269,25 @@ defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N2 +// Location: LCCOMB_X35_Y33_N0 cycloneive_lcell_comb \ula_|video_|Add1~0 ( // Equation(s): // \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) // \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) - .dataa(\ula_|video_|vga_vc [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [0]), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\ula_|video_|Add1~0_combout ), .cout(\ula_|video_|Add1~1 )); // synopsys translate_off -defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; +defparam \ula_|video_|Add1~0 .lut_mask = 16'h33CC; defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N8 -cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( -// Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [0])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~0_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Add1~0_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y31_N9 -dffeas \ula_|video_|vga_vc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[0]~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N4 +// Location: LCCOMB_X35_Y33_N2 cycloneive_lcell_comb \ula_|video_|Add1~2 ( // Equation(s): // \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) @@ -19092,42 +18305,42 @@ defparam \ula_|video_|Add1~2 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N6 +// Location: LCCOMB_X35_Y33_N4 cycloneive_lcell_comb \ula_|video_|Add1~4 ( // Equation(s): // \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) // \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), + .dataa(\ula_|video_|vga_vc [2]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~3 ), .combout(\ula_|video_|Add1~4_combout ), .cout(\ula_|video_|Add1~5 )); // synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N24 +// Location: LCCOMB_X38_Y33_N12 cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( // Equation(s): // \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), .datab(\ula_|video_|Add1~4_combout ), .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N25 +// Location: FF_X38_Y33_N13 dffeas \ula_|video_|vga_vc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[2]~2_combout ), @@ -19146,7 +18359,7 @@ defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N8 +// Location: LCCOMB_X35_Y33_N6 cycloneive_lcell_comb \ula_|video_|Add1~6 ( // Equation(s): // \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) @@ -19164,7 +18377,7 @@ defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N2 +// Location: LCCOMB_X35_Y33_N20 cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( // Equation(s): // \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) @@ -19181,15 +18394,15 @@ defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h5140; defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N3 +// Location: FF_X38_Y33_N3 dffeas \ula_|video_|vga_vc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[3]~3_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|vga_vc[3]~3_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -19200,42 +18413,42 @@ defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N10 +// Location: LCCOMB_X35_Y33_N8 cycloneive_lcell_comb \ula_|video_|Add1~8 ( // Equation(s): // \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) // \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - .dataa(\ula_|video_|vga_vc [4]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~7 ), .combout(\ula_|video_|Add1~8_combout ), .cout(\ula_|video_|Add1~9 )); // synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N20 +// Location: LCCOMB_X38_Y33_N20 cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( // Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [4])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~8_combout ))))) +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~8_combout ), .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Add1~8_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[4]~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N21 +// Location: FF_X38_Y33_N21 dffeas \ula_|video_|vga_vc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[4]~5_combout ), @@ -19254,50 +18467,50 @@ defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N12 +// Location: LCCOMB_X35_Y33_N10 cycloneive_lcell_comb \ula_|video_|Add1~10 ( // Equation(s): // \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) // \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~9 ), .combout(\ula_|video_|Add1~10_combout ), .cout(\ula_|video_|Add1~11 )); // synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N0 +// Location: LCCOMB_X35_Y33_N22 cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( // Equation(s): // \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|vga_vc [5]), .datad(\ula_|video_|Add1~10_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[5]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5140; defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N1 +// Location: FF_X38_Y33_N17 dffeas \ula_|video_|vga_vc[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[5]~8_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|vga_vc[5]~8_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -19308,42 +18521,42 @@ defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N14 +// Location: LCCOMB_X35_Y33_N12 cycloneive_lcell_comb \ula_|video_|Add1~12 ( // Equation(s): // \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) // \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~11 ), .combout(\ula_|video_|Add1~12_combout ), .cout(\ula_|video_|Add1~13 )); // synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N6 +// Location: LCCOMB_X38_Y33_N6 cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( // Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [6])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~12_combout ))))) +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~12_combout ), .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Add1~12_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[6]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N7 +// Location: FF_X38_Y33_N7 dffeas \ula_|video_|vga_vc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[6]~4_combout ), @@ -19362,42 +18575,42 @@ defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N16 +// Location: LCCOMB_X35_Y33_N14 cycloneive_lcell_comb \ula_|video_|Add1~14 ( // Equation(s): // \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) // \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) - .dataa(\ula_|video_|vga_vc [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~13 ), .combout(\ula_|video_|Add1~14_combout ), .cout(\ula_|video_|Add1~15 )); // synopsys translate_off -defparam \ula_|video_|Add1~14 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N22 +// Location: LCCOMB_X38_Y33_N14 cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( // Equation(s): // \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), .datab(\ula_|video_|Add1~14_combout ), .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[7]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N23 +// Location: FF_X38_Y33_N15 dffeas \ula_|video_|vga_vc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[7]~6_combout ), @@ -19416,7 +18629,7 @@ defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N18 +// Location: LCCOMB_X35_Y33_N16 cycloneive_lcell_comb \ula_|video_|Add1~16 ( // Equation(s): // \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) @@ -19434,24 +18647,24 @@ defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N0 +// Location: LCCOMB_X38_Y33_N24 cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( // Equation(s): -// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [8])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~16_combout ))))) +// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~16_combout ), .datac(\ula_|video_|vga_vc [8]), - .datad(\ula_|video_|Add1~16_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[8]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N1 +// Location: FF_X38_Y33_N25 dffeas \ula_|video_|vga_vc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[8]~7_combout ), @@ -19470,24 +18683,7 @@ defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N10 -cycloneive_lcell_comb \ula_|video_|Equal2~0 ( -// Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N20 +// Location: LCCOMB_X35_Y33_N18 cycloneive_lcell_comb \ula_|video_|Add1~18 ( // Equation(s): // \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) @@ -19504,24 +18700,24 @@ defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N28 +// Location: LCCOMB_X38_Y33_N10 cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( // Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [9])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~18_combout ))))) +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~18_combout ), .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Add1~18_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[9]~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N29 +// Location: FF_X38_Y33_N11 dffeas \ula_|video_|vga_vc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[9]~9_combout ), @@ -19540,58 +18736,111 @@ defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N26 +// Location: LCCOMB_X38_Y33_N18 +cycloneive_lcell_comb \ula_|video_|Equal2~0 ( +// Equation(s): +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(\ula_|video_|vga_vc [4]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [8]), + .cin(gnd), + .combout(\ula_|video_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N30 cycloneive_lcell_comb \ula_|video_|Equal3~0 ( // Equation(s): -// \ula_|video_|Equal3~0_combout = (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [2] & \ula_|video_|vga_vc [3]))) +// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0]))) - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [0]), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|vga_vc [3]), + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|vga_vc [0]), .cin(gnd), .combout(\ula_|video_|Equal3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h4000; +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0800; defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N16 +// Location: LCCOMB_X37_Y33_N18 cycloneive_lcell_comb \ula_|video_|Equal3~1 ( // Equation(s): -// \ula_|video_|Equal3~1_combout = (\ula_|video_|Equal2~0_combout & (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & \ula_|video_|Equal3~0_combout ))) +// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal2~0_combout & \ula_|video_|Equal3~0_combout ))) - .dataa(\ula_|video_|Equal2~0_combout ), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [9]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|Equal2~0_combout ), .datad(\ula_|video_|Equal3~0_combout ), .cin(gnd), .combout(\ula_|video_|Equal3~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal3~1 .lut_mask = 16'h2000; +defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N30 +// Location: LCCOMB_X38_Y33_N28 +cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( +// Equation(s): +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~0_combout ), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y33_N29 +dffeas \ula_|video_|vga_vc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N22 cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( // Equation(s): // \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), .datab(\ula_|video_|Add1~2_combout ), .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N31 +// Location: FF_X38_Y33_N23 dffeas \ula_|video_|vga_vc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[1]~1_combout ), @@ -19620,14 +18869,14 @@ defparam \SW[1]~input .bus_hold = "false"; defparam \SW[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N16 +// Location: LCCOMB_X34_Y33_N30 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & (!\ula_|video_|vga_hc [8] & !\ula_|video_|vga_hc [9]))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & !\ula_|video_|vga_hc [9]))) - .dataa(\ula_|video_|vga_vc [1]), - .datab(\SW[1]~input_o ), - .datac(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [8]), + .datab(\ula_|video_|vga_vc [1]), + .datac(\SW[1]~input_o ), .datad(\ula_|video_|vga_hc [9]), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), @@ -19637,15 +18886,15 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N0 +// Location: LCCOMB_X35_Y17_N30 cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( // Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [5]), + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), .combout(\z80_|pla_decode_|Equal79~0_combout ), .cout()); @@ -19654,34 +18903,16 @@ defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N26 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( -// Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )) - - .dataa(\z80_|interrupts_|iff1~q ), - .datab(\z80_|pla_decode_|Equal79~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hE2AA; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N16 +// Location: LCCOMB_X35_Y17_N16 cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( // Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|DFFE_instIFF2~q +// ))))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal79~0_combout ), .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .cin(gnd), .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), .cout()); @@ -19690,24 +18921,24 @@ defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N24 +// Location: LCCOMB_X32_Y15_N28 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( // Equation(s): // \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h5F0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h7733; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: CLKCTRL_G8 +// Location: CLKCTRL_G16 cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), @@ -19720,7 +18951,7 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clo defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X46_Y10_N17 +// Location: FF_X35_Y17_N17 dffeas \z80_|interrupts_|DFFE_instIFF2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), @@ -19739,42 +18970,60 @@ defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N10 +// Location: LCCOMB_X35_Y17_N2 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|interrupts_|iff1~q ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hEC4C; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N18 cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( // Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )) +// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|iff1~0_combout ))))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|interrupts_|iff1~0_combout )))) - .dataa(\z80_|interrupts_|iff1~0_combout ), + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|interrupts_|iff1~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|iff1~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hCAAA; +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hDF80; defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N6 +// Location: LCCOMB_X38_Y18_N12 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFAF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X46_Y10_N11 +// Location: FF_X35_Y17_N19 dffeas \z80_|interrupts_|iff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|iff1~1_combout ), @@ -19793,15 +19042,15 @@ defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; defparam \z80_|interrupts_|iff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N22 +// Location: LCCOMB_X37_Y33_N4 cycloneive_lcell_comb \ula_|video_|Equal2~1 ( // Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [3]))) +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [0]))) - .dataa(\ula_|video_|vga_vc [2]), - .datab(\ula_|video_|vga_vc [0]), + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|vga_vc [2]), .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [0]), .cin(gnd), .combout(\ula_|video_|Equal2~1_combout ), .cout()); @@ -19810,24 +19059,24 @@ defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N12 +// Location: LCCOMB_X37_Y33_N14 cycloneive_lcell_comb \ula_|video_|Equal2~2 ( // Equation(s): -// \ula_|video_|Equal2~2_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~1_combout & \ula_|video_|Equal2~0_combout )) +// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (\ula_|video_|Equal2~0_combout & !\ula_|video_|vga_vc [5])) .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|Equal2~1_combout ), - .datad(\ula_|video_|Equal2~0_combout ), + .datab(\ula_|video_|Equal2~1_combout ), + .datac(\ula_|video_|Equal2~0_combout ), + .datad(\ula_|video_|vga_vc [5]), .cin(gnd), .combout(\ula_|video_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h3000; +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h00C0; defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y20_N20 +// Location: LCCOMB_X35_Y31_N28 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( // Equation(s): // \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (\z80_|interrupts_|iff1~q & \ula_|video_|Equal2~2_combout ))) @@ -19844,7 +19093,7 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y20_N21 +// Location: FF_X35_Y31_N29 dffeas \z80_|interrupts_|int_armed ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), @@ -19863,32 +19112,15 @@ defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; defparam \z80_|interrupts_|int_armed .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N28 -cycloneive_lcell_comb \z80_|interrupts_|DFFE_inst44~feeder ( -// Equation(s): -// \z80_|interrupts_|DFFE_inst44~feeder_combout = \z80_|interrupts_|int_armed~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|interrupts_|int_armed~q ), - .cin(gnd), - .combout(\z80_|interrupts_|DFFE_inst44~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_inst44~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|DFFE_inst44~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X50_Y12_N29 +// Location: FF_X32_Y15_N11 dffeas \z80_|interrupts_|DFFE_inst44 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|DFFE_inst44~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|interrupts_|int_armed~q ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|interrupts_|test1~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -19899,127 +19131,163 @@ defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Location: LCCOMB_X32_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) +// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datab(gnd), .datac(\z80_|decode_state_|in_halt~q ), - .datad(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .combout(\z80_|execute_|pc_inc_hold~38_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Location: LCCOMB_X35_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~6_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~7_combout ) +// \z80_|execute_|ctl_inc_cy~91_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .combout(\z80_|execute_|ctl_inc_cy~91_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Location: LCCOMB_X35_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~45 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|pc_inc_hold~40_combout ))) +// \z80_|execute_|pc_inc_hold~45_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & +// (((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|pc_inc_hold~40_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .combout(\z80_|execute_|pc_inc_hold~45_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~45 .lut_mask = 16'hF888; +defparam \z80_|execute_|pc_inc_hold~45 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Location: LCCOMB_X35_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~44 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (((\z80_|execute_|ctl_alu_op_low~14_combout & -// \z80_|execute_|ctl_mRead~38_combout )))) +// \z80_|execute_|pc_inc_hold~44_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~49_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~44 .lut_mask = 16'h8CCC; +defparam \z80_|execute_|pc_inc_hold~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~46 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~46_combout = (\z80_|execute_|pc_inc_hold~45_combout ) # ((\z80_|execute_|pc_inc_hold~44_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~49_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~45_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|pc_inc_hold~44_combout ), + .datad(\z80_|execute_|pc_inc_hold~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~46 .lut_mask = 16'hFAFE; +defparam \z80_|execute_|pc_inc_hold~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & +// (\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), + .datab(\z80_|pla_decode_|Equal52~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), + .combout(\z80_|execute_|pc_inc_hold~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hF8A8; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Location: LCCOMB_X35_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~50 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = (((\z80_|execute_|ctl_inc_cy~49_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~11_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ) +// \z80_|execute_|pc_inc_hold~50_combout = (\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datad(\z80_|execute_|ctl_inc_cy~49_combout ), + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|pc_inc_hold~37_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .combout(\z80_|execute_|pc_inc_hold~50_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~50 .lut_mask = 16'hECCC; +defparam \z80_|execute_|pc_inc_hold~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Location: LCCOMB_X36_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_inc_cy~51_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout )) +// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_mRead~10_combout & (((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal6~1_combout & +// ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) - .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), - .datab(\z80_|execute_|ctl_inc_cy~50_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .combout(\z80_|execute_|pc_inc_hold~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Location: LCCOMB_X36_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = (\z80_|execute_|ctl_inc_cy~52_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # (!\z80_|execute_|fMRead~11_combout )))) +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~52_combout ), - .datac(\z80_|execute_|fMRead~11_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hEFCC; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N8 +// Location: LCCOMB_X34_Y17_N26 cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( // Equation(s): // \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~2_combout ))) @@ -20036,4853 +19304,1086 @@ defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|pc_inc_hold~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datad(\z80_|execute_|pc_inc_hold~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hF8FC; -defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~24_combout = (\z80_|execute_|ixy_d~4_combout & (((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) # (!\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & -// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ixy_d~4_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (((\z80_|execute_|ctl_mRead~17_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ixy_d~4_combout & -// (\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hECE0; -defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~25_combout = (\z80_|execute_|pc_inc_hold~22_combout ) # ((\z80_|execute_|pc_inc_hold~24_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # (\z80_|execute_|pc_inc_hold~23_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~22_combout ), - .datab(\z80_|execute_|pc_inc_hold~24_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datad(\z80_|execute_|pc_inc_hold~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~20_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal25~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFF37; -defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~10_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hA080; -defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~21_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~19_combout ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'h37FF; -defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~26_combout = (!\z80_|execute_|pc_inc_hold~25_combout & (\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|pc_inc_hold~21_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(\z80_|execute_|pc_inc_hold~20_combout ), - .datac(\z80_|execute_|pc_inc_hold~41_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'h0400; -defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & -// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|execute_|ctl_inc_cy~44_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~13_combout )) # (!\z80_|execute_|ctl_inc_cy~87_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ctl_inc_cy~45_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~43_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~85_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'hBBB3; -defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~43_combout ) # (!\z80_|execute_|ctl_inc_cy~47_combout ))) # (!\z80_|execute_|ctl_inc_cy~33_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~33_combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~47_combout ), - .datad(\z80_|execute_|ctl_inc_cy~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|execute_|pc_inc_hold~30_combout & (((\z80_|execute_|pc_inc_hold~26_combout & \z80_|execute_|ctl_inc_cy~48_combout )))) # (!\z80_|execute_|pc_inc_hold~30_combout & ((\z80_|execute_|ctl_inc_cy~54_combout ) # -// ((\z80_|execute_|ctl_inc_cy~48_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~30_combout ), - .datab(\z80_|execute_|ctl_inc_cy~54_combout ), - .datac(\z80_|execute_|pc_inc_hold~26_combout ), - .datad(\z80_|execute_|ctl_inc_cy~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hF544; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ixy_d~10_combout & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~42_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hA800; -defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|pc_inc_hold~19_combout & \z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout & -// (\z80_|execute_|pc_inc_hold~19_combout & (\z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|pc_inc_hold~19_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|execute_|pc_inc_hold~27_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|pc_inc_hold~27_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|pc_inc_hold~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .datab(\z80_|execute_|pc_inc_hold~26_combout ), - .datac(\z80_|execute_|pc_inc_hold~42_combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'h0004; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout & (((\z80_|execute_|ctl_inc_cy~39_combout & \z80_|execute_|pc_inc_hold~29_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'hB030; -defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|pc_inc_hold~42_combout & (\z80_|execute_|pc_inc_hold~26_combout & (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout & !\z80_|execute_|pc_inc_hold~28_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~42_combout ), - .datab(\z80_|execute_|pc_inc_hold~26_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|execute_|ctl_inc_cy~41_combout ) # ((\z80_|execute_|ctl_inc_cy~83_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # (!\z80_|execute_|pc_inc_hold~30_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~41_combout ), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|ctl_inc_cy~83_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hFABA; -defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (!\z80_|decode_state_|in_halt~q & \z80_|execute_|ctl_mRead~16_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~62_combout ) # ((!\z80_|execute_|pc_inc_hold~22_combout & !\z80_|execute_|ctl_reg_sys_hilo~24_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~22_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~62_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'hC0C4; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N20 +// Location: LCCOMB_X36_Y19_N26 cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~23_combout ) # ((\z80_|execute_|pc_inc_hold~22_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ixy_d~4_combout ))) +// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout )))) - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|pc_inc_hold~23_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|pc_inc_hold~22_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|pc_inc_hold~28_combout ), .cin(gnd), .combout(\z80_|execute_|pc_inc_hold~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hECEE; defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|pc_inc_hold~31_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~63_combout ), - .datad(\z80_|execute_|pc_inc_hold~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'hF0F8; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal33~1_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = ((!\z80_|execute_|pc_inc_hold~22_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout & \z80_|execute_|ctl_inc_cy~58_combout ))) # (!\z80_|execute_|pc_inc_hold~30_combout ) - - .dataa(\z80_|execute_|pc_inc_hold~22_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_inc_cy~58_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'h1F0F; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~12_combout ) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|execute_|pc_inc_hold~25_combout & (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_inc_cy~59_combout ))) # (!\z80_|execute_|pc_inc_hold~25_combout & -// (((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & \z80_|execute_|ctl_inc_cy~59_combout )) # (!\z80_|execute_|ctl_inc_cy~60_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_inc_cy~59_combout ), - .datad(\z80_|execute_|ctl_inc_cy~60_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'hC0D5; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N8 +// Location: LCCOMB_X36_Y19_N12 cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|pc_inc_hold~25_combout ) # ((\z80_|execute_|pc_inc_hold~41_combout ) # (!\z80_|execute_|pc_inc_hold~20_combout )) +// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|execute_|ctl_mRead~15_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(gnd), - .datac(\z80_|execute_|pc_inc_hold~41_combout ), - .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), .cin(gnd), .combout(\z80_|execute_|pc_inc_hold~32_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hFAFF; +defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hEEA0; defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N2 +// Location: LCCOMB_X36_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~31_combout ) # (\z80_|execute_|pc_inc_hold~32_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~33_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~31_combout ), + .datad(\z80_|execute_|pc_inc_hold~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~51 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~51_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~51 .lut_mask = 16'h57FF; +defparam \z80_|execute_|pc_inc_hold~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~52 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~52_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~52 .lut_mask = 16'hA800; +defparam \z80_|execute_|pc_inc_hold~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~35_combout = (!\z80_|execute_|pc_inc_hold~34_combout & (\z80_|execute_|pc_inc_hold~51_combout & (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~52_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~34_combout ), + .datab(\z80_|execute_|pc_inc_hold~51_combout ), + .datac(\z80_|execute_|pc_inc_hold~30_combout ), + .datad(\z80_|execute_|pc_inc_hold~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'h0040; +defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|pc_inc_hold~35_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hCF8F; +defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~10_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_inc_cy~44_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~50_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|ctl_inc_cy~44_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~43 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~43_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~43 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~91_combout & (!\z80_|execute_|pc_inc_hold~46_combout & (\z80_|execute_|ctl_inc_cy~45_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), + .datab(\z80_|execute_|pc_inc_hold~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~45_combout ), + .datad(\z80_|execute_|pc_inc_hold~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~72_combout & \z80_|execute_|ctl_inc_cy~71_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_inc_cy~72_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~71_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_mWrite~16_combout & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h8C00; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~53 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~53_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~53 .lut_mask = 16'hE000; +defparam \z80_|execute_|pc_inc_hold~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~39_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~53_combout & (\z80_|execute_|pc_inc_hold~35_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~50_combout ), + .datab(\z80_|execute_|pc_inc_hold~53_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'h0010; +defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~47 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~47_combout = (\z80_|execute_|pc_inc_hold~46_combout ) # ((\z80_|execute_|pc_inc_hold~43_combout ) # ((!\z80_|execute_|ctl_inc_cy~44_combout ) # (!\z80_|execute_|pc_inc_hold~39_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~46_combout ), + .datab(\z80_|execute_|pc_inc_hold~43_combout ), + .datac(\z80_|execute_|pc_inc_hold~39_combout ), + .datad(\z80_|execute_|ctl_inc_cy~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~47 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|pc_inc_hold~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~34_combout )) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~43_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~43_combout ), + .datab(\z80_|execute_|ctl_inc_cy~35_combout ), + .datac(\z80_|execute_|ctl_inc_cy~34_combout ), + .datad(\z80_|execute_|ctl_inc_cy~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = ((\z80_|execute_|ctl_inc_cy~74_combout ) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~39_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~39_combout ), + .datac(\z80_|execute_|ctl_inc_cy~77_combout ), + .datad(\z80_|execute_|ctl_inc_cy~74_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|pc_inc_hold~47_combout & \z80_|execute_|ctl_inc_cy~91_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~47_combout ), + .datab(\z80_|execute_|ctl_inc_cy~78_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~91_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h4C0C; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|pc_inc_hold~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal19~1_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|pla_decode_|Equal19~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hA800; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|ctl_inc_cy~81_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|pc_inc_hold~47_combout & (!\z80_|execute_|pc_inc_hold~38_combout & ((\z80_|execute_|ctl_inc_cy~82_combout ) # (!\z80_|execute_|ctl_inc_cy~38_combout )))) # (!\z80_|execute_|pc_inc_hold~47_combout +// & ((\z80_|execute_|ctl_inc_cy~82_combout ) # ((!\z80_|execute_|ctl_inc_cy~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~47_combout ), + .datab(\z80_|execute_|ctl_inc_cy~82_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h4C5F; +defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N26 cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout )) - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ctl_inc_cy~80_combout ), + .datad(\z80_|execute_|ctl_inc_cy~83_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_inc_cy~84_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hFFFC; defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Location: LCCOMB_X37_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~64_combout ) # ((\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|pc_inc_hold~32_combout & !\z80_|execute_|ctl_inc_cy~84_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), - .datab(\z80_|execute_|ctl_inc_cy~61_combout ), - .datac(\z80_|execute_|pc_inc_hold~32_combout ), - .datad(\z80_|execute_|ctl_inc_cy~84_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = ((!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h575F; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = (!\z80_|execute_|ctl_inc_cy~56_combout & (!\z80_|execute_|pc_inc_hold~42_combout & \z80_|execute_|pc_inc_hold~26_combout )) +// \z80_|execute_|pc_inc_hold~42_combout = ((\z80_|execute_|pc_inc_hold~34_combout ) # (\z80_|execute_|pc_inc_hold~52_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ) .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~56_combout ), - .datac(\z80_|execute_|pc_inc_hold~42_combout ), - .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .datab(\z80_|execute_|pc_inc_hold~30_combout ), + .datac(\z80_|execute_|pc_inc_hold~34_combout ), + .datad(\z80_|execute_|pc_inc_hold~52_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .combout(\z80_|execute_|pc_inc_hold~42_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'h0300; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( +// Location: LCCOMB_X37_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|pc_inc_hold~30_combout & ((\z80_|execute_|pc_inc_hold~25_combout ) # (!\z80_|execute_|pc_inc_hold~20_combout ))) +// \z80_|execute_|ctl_inc_cy~90_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(gnd), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), + .combout(\z80_|execute_|ctl_inc_cy~90_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hA0F0; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N2 +// Location: LCCOMB_X36_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~31_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|pc_inc_hold~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N18 cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = (\z80_|execute_|ctl_inc_cy~65_combout ) # ((\z80_|execute_|ctl_inc_cy~57_combout ) # ((!\z80_|execute_|pc_inc_hold~33_combout & !\z80_|execute_|ctl_inc_cy~38_combout ))) +// \z80_|execute_|ctl_inc_cy~66_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q ))) - .dataa(\z80_|execute_|ctl_inc_cy~65_combout ), - .datab(\z80_|execute_|ctl_inc_cy~57_combout ), - .datac(\z80_|execute_|pc_inc_hold~33_combout ), - .datad(\z80_|execute_|ctl_inc_cy~38_combout ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), .combout(\z80_|execute_|ctl_inc_cy~66_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hEEEF; +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h0004; defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N20 +// Location: LCCOMB_X36_Y19_N4 cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~40_combout ) # ((\z80_|execute_|ctl_inc_cy~42_combout ) # (\z80_|execute_|ctl_inc_cy~66_combout ))) +// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & !\z80_|execute_|pc_inc_hold~31_combout )))) - .dataa(\z80_|execute_|ctl_inc_cy~55_combout ), - .datab(\z80_|execute_|ctl_inc_cy~40_combout ), - .datac(\z80_|execute_|ctl_inc_cy~42_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datac(\z80_|execute_|pc_inc_hold~31_combout ), .datad(\z80_|execute_|ctl_inc_cy~66_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_inc_cy~67_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hAA02; defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Location: LCCOMB_X36_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = (((!\z80_|execute_|ctl_inc_cy~37_combout ) # (!\z80_|execute_|ctl_inc_cy~31_combout )) # (!\z80_|execute_|ctl_inc_cy~36_combout )) # (!\z80_|execute_|ctl_inc_cy~30_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~30_combout ), - .datab(\z80_|execute_|ctl_inc_cy~36_combout ), - .datac(\z80_|execute_|ctl_inc_cy~31_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~75_combout ) # ((!\z80_|execute_|ctl_inc_cy~35_combout ) # (!\z80_|execute_|ctl_inc_cy~78_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_inc_cy~78_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'hBBFF; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = ((\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_inc_cy~72_combout & \z80_|pla_decode_|Equal19~1_combout ))) # (!\z80_|execute_|ctl_inc_cy~34_combout ) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_inc_cy~34_combout ), - .datac(\z80_|execute_|ctl_inc_cy~72_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'hB333; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|ctl_mRead~15_combout ))) .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|pc_inc_hold~41_combout ), + .datac(\z80_|execute_|ctl_inc_cy~67_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Location: LCCOMB_X36_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & (!\z80_|execute_|pc_inc_hold~34_combout & \z80_|execute_|pc_inc_hold~29_combout ))) +// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~31_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~73_combout & ((!\z80_|execute_|pc_inc_hold~30_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_inc_cy~73_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'hFF4C; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~74_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout & ((\z80_|execute_|ctl_inc_cy~68_combout ) # (!\z80_|execute_|pc_inc_hold~30_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~68_combout ), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_inc_cy~74_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hFF8C; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = (!\z80_|execute_|ctl_inc_dec~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'h5F5F; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .lut_mask = 16'h2F00; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~53_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_flags_oe~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~53 .lut_mask = 16'h050D; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .lut_mask = 16'hECFC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal25~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~54 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~54_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~54 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~27_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ), - .datac(\z80_|execute_|ctl_mRead~27_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~20_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~20 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # (((\z80_|execute_|ctl_ir_we~15_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo~24_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout = (\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & ((\z80_|execute_|rsel0~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// (((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|rsel0~combout )) # (!\z80_|execute_|setM1~48_combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|execute_|rsel0~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .lut_mask = 16'hCD05; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~47 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) # (!\z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .datac(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = (\z80_|pla_decode_|Equal40~1_combout & (((\z80_|execute_|ixy_d~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal40~1_combout & (\z80_|pla_decode_|Equal39~0_combout & -// ((\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFAC0; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0A00; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hA8A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout )) # (!\z80_|execute_|ctl_alu_op_low~21_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ixy_d~4_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|execute_|ctl_mRead~38_combout )))) # (!\z80_|execute_|ixy_d~4_combout & (((\z80_|execute_|ctl_eval_cond~0_combout & -// \z80_|execute_|ctl_mRead~38_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFC88; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h55F7; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~23_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal44~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_state_alu~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel~5_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hFF0F; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~17_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~17_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~39_combout = (((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~18_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'h7F77; -defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op_low~39_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout & ((\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'hF0E0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal56~0_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~38_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~38_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h0777; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~10_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h0155; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hEEEC; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_flags_cf_cpl~2_combout & ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hEF00; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mWrite~2_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout & -// (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (!\z80_|execute_|ctl_flags_cf_cpl~3_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h0200; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_alu_op_low~30_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC800; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = ((\z80_|execute_|ctl_reg_gp_sel~5_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal72~2_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~11_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal72~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|pla_decode_|Equal61~2_combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal61~2_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~11_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal21~0_combout ) # ((\z80_|pla_decode_|Equal3~0_combout )))) # (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_eval_cond~0_combout & -// ((\z80_|pla_decode_|Equal21~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .lut_mask = 16'hFAC8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout -// ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .lut_mask = 16'hFFF8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (\z80_|execute_|ctl_alu_op_low~36_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~36_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'h4000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (!\z80_|pla_decode_|Equal72~2_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal72~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & \z80_|execute_|ctl_flags_nf_we~1_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~38_combout = (\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'h8880; -defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|execute_|ctl_alu_op_low~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~38_combout ) # (\z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_alu_op_low~32_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|pla_decode_|Equal64~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h00C4; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|pla_decode_|Equal20~0_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (\z80_|execute_|ctl_flags_use_cf2~9_combout ))) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|execute_|ctl_flags_bus~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hBAFA; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_mRead~38_combout & \z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|pc_inc_hold~31_combout ), .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Location: LCCOMB_X37_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = (((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (\z80_|execute_|ctl_flags_cf_we~5_combout )) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (((\z80_|ir_|opcode [3]) # (!\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'hF700; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|execute_|ctl_alu_core_R~2_combout ) # ((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|execute_|ctl_alu_op_low~25_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # (((\z80_|execute_|ctl_alu_op_low~33_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout )) # (!\z80_|execute_|ctl_alu_op_low~39_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~34_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hCC40; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hA0A8; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h54F0; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~18_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h5C4C; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~19_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h5F08; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_mWrite~2_combout ) # (\z80_|execute_|ctl_alu_shift_oe~20_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~20_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h5F40; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~21_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout -// & ((\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hEEC0; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_ir_we~7_combout )))) # (!\z80_|execute_|ctl_bus_db_oe~7_combout & ((\z80_|execute_|ixy_d~7_combout ) -// # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'hDC50; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_alu_shift_oe~24_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~44_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ) # (\z80_|execute_|ctl_alu_shift_oe~16_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0F0E; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~23_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF45; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hC4C0; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) +// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|pc_inc_hold~34_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_sw_4u~0_combout )))) .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|pc_inc_hold~34_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0C08; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Location: LCCOMB_X37_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( // Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~22_combout ) # (\z80_|execute_|ctl_mRead~28_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) +// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_inc_cy~64_combout ), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hFFC4; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_inc_cy~68_combout ) # ((\z80_|execute_|ctl_inc_cy~65_combout ) # ((!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|ctl_inc_cy~90_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~42_combout ), + .datab(\z80_|execute_|ctl_inc_cy~90_combout ), + .datac(\z80_|execute_|ctl_inc_cy~68_combout ), + .datad(\z80_|execute_|ctl_inc_cy~65_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~49_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_inc_cy~92_combout ) .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|execute_|ctl_mRead~28_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_inc_cy~92_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Location: LCCOMB_X35_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( // Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) +// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ixy_d~9_combout & +// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h5F40; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_flags_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~22_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~42_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hB0A0; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( -// Equation(s): -// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .dataa(\z80_|execute_|ixy_d~9_combout ), .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Location: LCCOMB_X36_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~2_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~10_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_ir_we~10_combout ))) +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_inc_cy~94_combout )) - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|execute_|ctl_inc_cy~94_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Location: LCCOMB_X35_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) +// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|pla_decode_|Equal11~0_combout ))) - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~51_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Location: LCCOMB_X36_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( // Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_mWrite~3_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) +// \z80_|execute_|ctl_inc_cy~36_combout = ((!\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .combout(\z80_|execute_|ctl_inc_cy~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_alu_res_oe~1_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( -// Equation(s): -// \z80_|alu_|db_high[3]~1_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # ((\z80_|alu_|db_high[3]~0_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~0_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFEFF; -defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~2 ( -// Equation(s): -// \z80_|alu_|db_low[3]~2_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [3]), - .datac(\z80_|alu_|op2_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~2 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db_low[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hC0C0; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N26 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~3 ( -// Equation(s): -// \z80_|alu_|db_low[3]~3_combout = (\z80_|alu_|db_low[3]~2_combout & (((!\z80_|bus_control_|db[5]~17_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|alu_|db_low[3]~2_combout ), - .datab(\z80_|bus_control_|db[5]~17_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~3 .lut_mask = 16'h2A0A; -defparam \z80_|alu_|db_low[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y16_N13 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( -// Equation(s): -// \z80_|alu_|db_low[3]~4_combout = (\z80_|alu_|db_low[3]~3_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|alu_|db_low[3]~3_combout ), - .datab(\z80_|alu_|result_lo [3]), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hAA88; -defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (((\z80_|alu_|db_low[3]~1_combout & \z80_|alu_|db_low[3]~4_combout )) # (!\z80_|alu_|db_high[3]~1_combout ))) - - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .lut_mask = 16'hB030; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|alu_|db_high[3]~19_combout ), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .lut_mask = 16'h00F8; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_low~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N29 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[3]~3_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|alu_|alu_op2[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFCD; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = ((!\z80_|execute_|ctl_alu_core_S~11_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h3FFF; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|pla_decode_|Equal62~2_combout & \z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFBBB; -defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ) # (\z80_|execute_|ctl_alu_core_S~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~25 ( -// Equation(s): -// \z80_|alu_|db_high[2]~25_combout = (\z80_|alu_|db_high[2]~24_combout ) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_high[3]~1_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|alu_|db_high[2]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~25 .lut_mask = 16'hFF55; -defparam \z80_|alu_|db_high[2]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [6] & ((\z80_|reg_file_|gdfx_temp1[6]~21_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[6]~21_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~0 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|db_hi_as[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~1_combout = (\z80_|reg_file_|db_hi_as[6]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[6]~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~1 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|db_hi_as[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N29 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [14]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [13]))))) - - .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~3_combout = ((\z80_|reg_file_|db_hi_as[6]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[6]~1_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~3 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_hi_as[6]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X36_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 ( +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( // Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) +// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~36_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_sw_2u~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~36_combout ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), + .combout(\z80_|execute_|ctl_inc_cy~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Location: LCCOMB_X35_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) +// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout ))) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_inc_cy~52_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~9 ( +// Location: LCCOMB_X39_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) +// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|ctl_mRead~17_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~9_combout ), + .combout(\z80_|execute_|ctl_inc_cy~41_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~9 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~9 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0045; +defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~10 ( +// Location: LCCOMB_X39_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) +// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout )) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~10 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~11_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~11 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~12_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[6]~22_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~12 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~14_combout = (\z80_|reg_file_|gdfx_temp1[6]~10_combout & (\z80_|reg_file_|gdfx_temp1[6]~11_combout & (\z80_|reg_file_|gdfx_temp1[6]~13_combout & \z80_|reg_file_|gdfx_temp1[6]~12_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~10_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~11_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~13_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~21_combout - - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), + .datad(\z80_|execute_|ctl_inc_cy~41_combout ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hEEFF; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~8 ( +// Location: LCCOMB_X35_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~8_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) +// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & +// ((\z80_|execute_|ctl_mRead~36_combout )))) - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~8_combout ), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~8 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[6]~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~15 ( +// Location: LCCOMB_X38_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~15_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout & (\z80_|reg_file_|gdfx_temp1[6]~9_combout & (\z80_|reg_file_|gdfx_temp1[6]~14_combout & \z80_|reg_file_|gdfx_temp1[6]~8_combout ))) +// \z80_|execute_|ctl_inc_cy~56_combout = (((!\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|fMRead~3_combout ) - .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~8_combout ), + .dataa(\z80_|execute_|fMRead~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~15_combout ), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~21 ( +// Location: LCCOMB_X39_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~21_combout = ((\z80_|reg_file_|gdfx_temp1[6]~15_combout & ((\z80_|reg_file_|db_hi_as[6]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) +// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - .dataa(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), + .combout(\z80_|execute_|ctl_inc_cy~89_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~21 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp1[6]~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hA020; +defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N24 -cycloneive_lcell_comb \z80_|interrupts_|im2~feeder ( +// Location: LCCOMB_X39_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( // Equation(s): -// \z80_|interrupts_|im2~feeder_combout = \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout +// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~56_combout ) # (\z80_|execute_|ctl_inc_cy~89_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ctl_inc_cy~55_combout ), + .datac(\z80_|execute_|ctl_inc_cy~56_combout ), + .datad(\z80_|execute_|ctl_inc_cy~89_combout ), .cin(gnd), - .combout(\z80_|interrupts_|im2~feeder_combout ), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|im2~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|im2~feeder .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y12_N25 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|im2~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Location: LCCOMB_X39_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( // Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) +// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~57_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~58_combout ) # (!\z80_|execute_|fMRead~5_combout )))) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_inc_cy~58_combout ), + .datac(\z80_|execute_|fMRead~5_combout ), + .datad(\z80_|execute_|ctl_inc_cy~57_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hFF8A; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Location: LCCOMB_X37_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( // Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|execute_|ctl_mRead~14_combout & (\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|pc_inc_hold~38_combout & (\z80_|execute_|pc_inc_hold~35_combout & (\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|pc_inc_hold~38_combout & (((\z80_|execute_|ctl_inc_cy~54_combout ) # +// (\z80_|execute_|ctl_inc_cy~59_combout )))) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|pc_inc_hold~35_combout ), + .datac(\z80_|execute_|ctl_inc_cy~54_combout ), + .datad(\z80_|execute_|ctl_inc_cy~59_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hD5D0; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N0 -cycloneive_lcell_comb \z80_|sw1_|db_down[6]~0 ( +// Location: LCCOMB_X35_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( // Equation(s): -// \z80_|sw1_|db_down[6]~0_combout = ((\z80_|bus_control_|db[6]~7_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) +// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|pc_inc_hold~50_combout ))) - .dataa(gnd), - .datab(\z80_|bus_control_|db[6]~7_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~50_combout ), .cin(gnd), - .combout(\z80_|sw1_|db_down[6]~0_combout ), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), .cout()); // synopsys translate_off -defparam \z80_|sw1_|db_down[6]~0 .lut_mask = 16'h0CFF; -defparam \z80_|sw1_|db_down[6]~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~10 ( +// Location: LCCOMB_X37_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( // Equation(s): -// \z80_|alu_|db_low[1]~10_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & !\z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~10 .lut_mask = 16'h3373; -defparam \z80_|alu_|db_low[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) +// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .combout(\z80_|execute_|ctl_inc_cy~88_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hAA08; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y17_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 ( +// Location: LCCOMB_X37_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( // Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout = (\z80_|alu_|db_low[1]~15_combout & \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) +// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_inc_cy~88_combout & ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~39_combout ), + .datab(\z80_|execute_|ctl_inc_cy~47_combout ), + .datac(\z80_|execute_|ctl_inc_cy~88_combout ), + .datad(\z80_|execute_|pc_inc_hold~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hECFC; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~40_combout = (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~34_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|pc_inc_hold~30_combout ), + .datac(\z80_|execute_|pc_inc_hold~34_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h3200; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|ctl_inc_cy~42_combout & ((\z80_|execute_|pc_inc_hold~40_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|pc_inc_hold~40_combout ), + .datac(\z80_|execute_|ctl_inc_cy~61_combout ), + .datad(\z80_|execute_|ctl_inc_cy~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hF0FD; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~48_combout ) # (\z80_|execute_|ctl_inc_cy~62_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), + .datab(\z80_|execute_|ctl_inc_cy~60_combout ), + .datac(\z80_|execute_|ctl_inc_cy~48_combout ), + .datad(\z80_|execute_|ctl_inc_cy~62_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~85_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~70_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), + .datab(\z80_|execute_|ctl_inc_cy~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~84_combout ), + .datad(\z80_|execute_|ctl_inc_cy~70_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (\z80_|execute_|ctl_inc_cy~85_combout ) .dataa(gnd), .datab(gnd), - .datac(\z80_|alu_|db_low[1]~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_cy~85_combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .lut_mask = 16'hF000; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( // Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .dataa(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFCF8; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hAF2F; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~12 ( +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( // Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~12_combout = (((!\z80_|execute_|nextM~11_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout )) # (!\z80_|execute_|ctl_reg_use_sp~0_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|ctl_mRead~38_combout -// & (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~13_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[1]~15_combout ) # ((\z80_|alu_|db_high[1]~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_high[1]~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(\z80_|alu_|db_high[1]~7_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|db_low[1]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) +// \z80_|address_latch_|abusz [0] = (\z80_|reg_file_|db_lo_as[0]~3_combout & !\z80_|resets_|clrpc~0_combout ) .dataa(gnd), - .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] + + .dataa(gnd), + .datab(gnd), .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|address_latch_|abusz [0]), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout ), + .combout(\z80_|address_latch_|Q[0]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1 .lut_mask = 16'h00CC; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # (\z80_|execute_|ctl_alu_op2_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N13 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[1]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[1]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00A0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N1 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~3 ( -// Equation(s): -// \z80_|alu_|db_high[1]~3_combout = (\z80_|alu_|op2_high [1] & (((\z80_|alu_|op1_high [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_high [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [1]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [1]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~3 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~2 ( -// Equation(s): -// \z80_|alu_|db_high[1]~2_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~2 .lut_mask = 16'h7333; -defparam \z80_|alu_|db_high[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N2 -cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( -// Equation(s): -// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_sw_2d~13_combout ) # ((\z80_|execute_|ctl_alu_oe~14_combout ) # (\z80_|execute_|ctl_reg_out_hi~7_combout )) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFEE; -defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( +// Location: FF_X31_Y16_N23 +dffeas \z80_|address_latch_|Q[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~70 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~72 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~71_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[5]~24_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~71 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~69 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~73_combout = (\z80_|reg_file_|gdfx_temp1[5]~70_combout & (\z80_|reg_file_|gdfx_temp1[5]~72_combout & (\z80_|reg_file_|gdfx_temp1[5]~71_combout & \z80_|reg_file_|gdfx_temp1[5]~69_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~70_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~72_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~71_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~69_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~67_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~67 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N27 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~16 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~68 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~74_combout = (\z80_|reg_file_|gdfx_temp1[5]~73_combout & (\z80_|reg_file_|gdfx_temp1[5]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout & \z80_|reg_file_|gdfx_temp1[5]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~75_combout = ((\z80_|reg_file_|gdfx_temp1[5]~74_combout & ((\z80_|reg_file_|db_hi_as[5]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~74_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~75 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp1[5]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N4 -cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( -// Equation(s): -// \z80_|alu_|db[5]~23_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[5]~29_combout & ((\z80_|reg_file_|gdfx_temp1[5]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// (((\z80_|reg_file_|gdfx_temp1[5]~75_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|alu_control_|db[5]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N6 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_high[1]~7_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db[5]~23_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_mWrite~2_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~24_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y11_N25 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [12]), + .d(\z80_|address_latch_|Q[0]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -24891,815 +20392,31 @@ dffeas \z80_|address_latch_|Q[12] ( .ena(\z80_|execute_|ctl_al_we~12_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), + .q(\z80_|address_latch_|Q [0]), .prn(vcc)); // synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [11] $ -// (\z80_|execute_|ctl_inc_dec~8_combout ))))) +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - .dataa(\z80_|address_latch_|Q [12]), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [4] & ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~22 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|db_hi_as[4]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~23_combout = (\z80_|reg_file_|db_hi_as[4]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~22_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~23 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[4]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~24_combout = ((\z80_|reg_file_|db_hi_as[4]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~24 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~17 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~77 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~76 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~79 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~78 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~80_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[4]~10_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[4]~10_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~80 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~81 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~82_combout = (\z80_|reg_file_|gdfx_temp1[4]~79_combout & (\z80_|reg_file_|gdfx_temp1[4]~78_combout & (\z80_|reg_file_|gdfx_temp1[4]~80_combout & \z80_|reg_file_|gdfx_temp1[4]~81_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~79_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~78_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~80_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~81_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~83_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout & (\z80_|reg_file_|gdfx_temp1[4]~77_combout & (\z80_|reg_file_|gdfx_temp1[4]~76_combout & \z80_|reg_file_|gdfx_temp1[4]~82_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~76_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~84_combout = ((\z80_|reg_file_|gdfx_temp1[4]~83_combout & ((\z80_|reg_file_|db_hi_as[4]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~83_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~84 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp1[4]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~2_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~19_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # (\z80_|execute_|ctl_sw_4u~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & \z80_|decode_state_|DFFE_inst4~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # (\z80_|execute_|ctl_inc_cy~80_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~70_combout ), - .datab(\z80_|execute_|ctl_inc_cy~67_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~81_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), - .datab(\z80_|address_latch_|Q [1]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h66CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N11 +// Location: FF_X31_Y17_N5 dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), @@ -25718,5802 +20435,7 @@ defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hFAD8; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N13 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_alu_op_low~32_combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~32_combout & (\z80_|alu_|op1_high [2])))) # -// (!\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|alu_|op1_low [2])))) - - .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hF0D8; -defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[1]~1_combout = (\z80_|execute_|ctl_alu_op_low~32_combout & (((\z80_|alu_|op1_low [1])))) # (!\z80_|execute_|ctl_alu_op_low~32_combout & ((\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|alu_|op1_high [1])) # -// (!\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|alu_|op1_low [1]))))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[1]~1 .lut_mask = 16'hE2F0; -defparam \z80_|alu_|alu_op1[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op2[1]~0_combout & \z80_|alu_|alu_op1[1]~1_combout )) - - .dataa(\z80_|alu_|alu_op2[1]~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~combout ), - .datac(gnd), - .datad(\z80_|alu_|alu_op1[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hEECC; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[1]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [1]))))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|alu_|alu_op2[1]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0027; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N8 -cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( -// Equation(s): -// \z80_|alu_|db[1]~15_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[1]~26_combout & ((\z80_|reg_file_|gdfx_temp1[1]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// (((\z80_|reg_file_|gdfx_temp1[1]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N10 -cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( -// Equation(s): -// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~15_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db[1]~15_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~48_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[0]~48_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~10 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~11_combout = (\z80_|reg_file_|db_hi_as[0]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~11 .lut_mask = 16'hB0B0; -defparam \z80_|reg_file_|db_hi_as[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0020; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[6]~15_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datad(\z80_|alu_control_|db[6]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|decode_state_|DFFE_inst4~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~75_combout & (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~78_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout & (\z80_|reg_file_|gdfx_temp0[6]~74_combout & \z80_|reg_file_|gdfx_temp0[6]~73_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (\z80_|reg_file_|db_lo_as[4]~15_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N11 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [4]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [4]) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h3C3C; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ -// (\z80_|execute_|ctl_inc_dec~8_combout ))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|Q [4]), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|Q [5]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'hD728; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X39_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~29_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[5]~29_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|alu_control_|db[5]~29_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~67_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~63_combout & (\z80_|reg_file_|gdfx_temp0[5]~64_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datac(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout = \z80_|reg_file_|db_lo_as[5]~18_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (\z80_|reg_file_|db_lo_as[5]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|address_latch_|Q[5]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[5]~feeder_combout = \z80_|address_latch_|abusz [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [5]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N9 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[5]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (\z80_|execute_|ctl_inc_dec~6_combout )) # (!\z80_|execute_|ctl_inc_dec~7_combout ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h5559; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N15 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~8_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & -// (\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_inc_dec~8_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2 .lut_mask = 16'h0BB0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[7]~18_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (\z80_|reg_file_|db_lo_as[7]~24_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[7]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[7]~feeder_combout = \z80_|address_latch_|abusz [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [7]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N5 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[7]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~12_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N31 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [7]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hD728; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~12_combout = ((\z80_|reg_file_|db_hi_as[0]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~11_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~12 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_hi_as[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~41 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~14 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~42 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~44_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[0]~18_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[0]~18_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~44 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[0]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~45 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[0]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~43_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~46_combout = (\z80_|reg_file_|gdfx_temp1[0]~42_combout & (\z80_|reg_file_|gdfx_temp1[0]~44_combout & (\z80_|reg_file_|gdfx_temp1[0]~45_combout & \z80_|reg_file_|gdfx_temp1[0]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~42_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~44_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~45_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~40 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[0]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~47_combout = (\z80_|reg_file_|gdfx_temp1[0]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout & (\z80_|reg_file_|gdfx_temp1[0]~46_combout & \z80_|reg_file_|gdfx_temp1[0]~40_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~41_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~46_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~48_combout = ((\z80_|reg_file_|gdfx_temp1[0]~47_combout & ((\z80_|reg_file_|db_hi_as[0]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~47_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~48 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp1[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N24 -cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( -// Equation(s): -// \z80_|alu_|db[0]~17_combout = (\z80_|alu_|db_low[0]~21_combout & (((\z80_|reg_file_|gdfx_temp1[0]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_|db_low[0]~21_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & -// ((\z80_|reg_file_|gdfx_temp1[0]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_|db_low[0]~21_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N22 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|alu_|db[0]~17_combout ), - .datac(\z80_|alu_control_|db[0]~12_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4FF; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N2 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [3] & ((\z80_|ir_|opcode [5] & ((\z80_|alu_|db[7]~20_combout ))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_|db[0]~18_combout )))) # (!\z80_|ir_|opcode [3] & -// (((\z80_|alu_|db[7]~20_combout & !\z80_|ir_|opcode [5])))) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hC0AC; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N4 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N20 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((!\z80_|ir_|opcode [4] & \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout )) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datac(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hF4F4; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~16 ( -// Equation(s): -// \z80_|alu_|db_low[0]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[1]~16_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~16 .lut_mask = 16'hF5A0; -defparam \z80_|alu_|db_low[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~17 ( -// Equation(s): -// \z80_|alu_|db_low[0]~17_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~16_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~18_combout )))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db_low[0]~16_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(\z80_|alu_|db[0]~18_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~17 .lut_mask = 16'hB8FF; -defparam \z80_|alu_|db_low[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( -// Equation(s): -// \z80_|alu_|db_low[0]~19_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [0] & ((\z80_|alu_|op1_low [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [0])) -// # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|alu_|op2_low [0]), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hF351; -defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # -// (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h57FF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~16_combout )))) # -// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~16_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & -// (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hEEC0; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # ((!\z80_|execute_|ctl_flags_alu~15_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & ((\z80_|execute_|ctl_flags_hf_we~2_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hB8AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y14_N23 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~14_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~11_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~11_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'h55F7; -defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & !\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal61~2_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFFA8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_control_|db[1]~26_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFFEC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|alu_|db_high[3]~19_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) - - .dataa(\z80_|alu_|db_high[3]~19_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFBF3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hB0F0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'h40C0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~16_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout )) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout & (\z80_|execute_|ctl_alu_core_hf~16_combout & \z80_|execute_|ctl_flags_nf_we~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal61~2_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~4_combout = ((\z80_|execute_|ctl_flags_nf_we~3_combout ) # ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_alu_core_hf~16_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hF000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N8 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (((!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0133; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout & (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'hB830; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X44_Y15_N29 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~9_combout = (\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_flags_hf_cpl~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (\z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_hf_cpl~10_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~8_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'h4404; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N0 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h0FB4; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_core_hf~16_combout & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~14_combout )) # (!\z80_|execute_|ctl_alu_core_hf~17_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (!\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|execute_|ctl_alu_core_hf~15_combout ) # ((!\z80_|execute_|ctl_alu_op_low~38_combout & \z80_|execute_|ctl_alu_core_hf~18_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'h3130; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hF400; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'hDCFC; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~20_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hFFF4; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout & (((!\z80_|execute_|ctl_alu_op_low~27_combout & \z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_op_low~34_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~23_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (\z80_|execute_|ctl_alu_core_hf~21_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h30BA; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_op_low~18_combout & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_alu_op_low~33_combout & ((\z80_|execute_|ctl_alu_core_hf~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~17_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_mWrite~2_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h8A88; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) # (!\z80_|execute_|ctl_mRead~8_combout & -// (\z80_|sequencer_|DFFE_M2_ff~q & ((!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (((\z80_|execute_|ctl_alu_op_low~17_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ixy_d~7_combout & -// (!\z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hF022; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (!\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout ))) # -// (!\z80_|pla_decode_|Equal56~0_combout & (\z80_|execute_|ctl_alu_core_hf~29_combout & \z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'h5440; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout & ((\z80_|execute_|ctl_alu_core_hf~31_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal10~0_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (!\z80_|execute_|ctl_alu_op_low~20_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~26_combout ) # (\z80_|execute_|ctl_alu_core_hf~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h0054; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout & !\z80_|execute_|ctl_alu_op_low~26_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ixy_d~5_combout ) # ((!\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ixy_d~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hF3F0; -defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~39_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~4_combout & \z80_|pla_decode_|Equal40~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hD0C0; -defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_alu_core_hf~24_combout ) # ((\z80_|execute_|ctl_alu_core_hf~33_combout ) # ((\z80_|execute_|ctl_alu_core_hf~40_combout & !\z80_|execute_|ctl_alu_op_low~30_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_core_hf~19_combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N30 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~35_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~35_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_flags_|flags_hf~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hCCAA; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~8 ( -// Equation(s): -// \z80_|alu_|db_high[0]~8_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~8 .lut_mask = 16'h3733; -defparam \z80_|alu_|db_high[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[0]~13_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00A0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N27 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~9 ( -// Equation(s): -// \z80_|alu_|db_high[0]~9_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [0] & ((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_high -// [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datab(\z80_|alu_|op2_high [0]), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op1_high [0]), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~9 .lut_mask = 16'hDD0D; -defparam \z80_|alu_|db_high[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~10 ( -// Equation(s): -// \z80_|alu_|db_high[0]~10_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~10 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_high[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~11 ( -// Equation(s): -// \z80_|alu_|db_high[0]~11_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~10_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~10_combout )) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~11 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_high[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~12 ( -// Equation(s): -// \z80_|alu_|db_high[0]~12_combout = (\z80_|alu_|db_high[0]~8_combout & (\z80_|alu_|db_high[0]~9_combout & ((\z80_|alu_|db_high[0]~11_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~8_combout ), - .datab(\z80_|alu_|db_high[0]~9_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[0]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~12 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~13 ( -// Equation(s): -// \z80_|alu_|db_high[0]~13_combout = ((\z80_|alu_|db_high[0]~12_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datab(\z80_|alu_|db_high[0]~12_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~13 .lut_mask = 16'hC8FF; -defparam \z80_|alu_|db_high[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[0]~13_combout ) # ((\z80_|alu_|db_low[0]~21_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((\z80_|alu_|db_low[0]~21_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_high[0]~13_combout ), - .datac(\z80_|alu_|db_low[0]~21_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N15 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_bus_inc_oe~44_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|pla_decode_|Equal61~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ) # (!\z80_|execute_|ctl_alu_op_low~39_combout -// ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # (((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # (((\z80_|execute_|ctl_alu_sel_op2_neg~12_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N20 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datab(\z80_|alu_|op2_low [0]), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~1 .lut_mask = 16'h1BE4; -defparam \z80_|alu_|alu_op2[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~0_combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op2[0]~1_combout -// )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & (\z80_|alu_|alu_op1[0]~0_combout & (\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op2[0]~1_combout ))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datab(\z80_|alu_|alu_op1[0]~0_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op2[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hEAA8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N17 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( -// Equation(s): -// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & !\z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h3337; -defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( -// Equation(s): -// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~19_combout & (\z80_|alu_|db_low[0]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|db_low[0]~19_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|alu_|db_low[0]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'hC800; -defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = ((\z80_|alu_|db_low[0]~17_combout & \z80_|alu_|db_low[0]~20_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(gnd), - .datab(\z80_|alu_|db_low[0]~17_combout ), - .datac(\z80_|alu_|db_low[0]~20_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hC0FF; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[0]~13_combout ) # ((\z80_|alu_|db_low[0]~21_combout & \z80_|execute_|ctl_alu_op1_sel_bus~14_combout )))) # -// (!\z80_|execute_|ctl_alu_op1_sel_low~combout & (\z80_|alu_|db_low[0]~21_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|alu_|db_low[0]~21_combout ), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N11 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|alu_|op1_high [0]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~0 .lut_mask = 16'hF3C0; -defparam \z80_|alu_|alu_op1[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_low[0]~21_combout ) # ((\z80_|alu_|alu_op1[0]~0_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|alu_|alu_op1[0]~0_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|alu_op1[0]~0_combout ), - .datac(\z80_|alu_|db_low[0]~21_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(gnd), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0C0C; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N29 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(gnd), - .datab(\z80_|alu_|op2_low [0]), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~0_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & !\z80_|execute_|ctl_alu_core_S~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hCCCF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # -// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h2223; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & \z80_|alu_|alu_op2[2]~2_combout )) - - .dataa(\z80_|alu_|alu_op1[2]~2_combout ), - .datab(gnd), - .datac(\z80_|alu_|alu_op2[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFA0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h33BF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op1[2]~2_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op2[2]~2_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op1[2]~2_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[2]~2_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[2]~2_combout ), - .datab(\z80_|alu_|alu_op2[2]~2_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hFE80; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y16_N11 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h3030; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N26 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~7 ( -// Equation(s): -// \z80_|alu_|db_low[2]~7_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|op2_low [2]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~7 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db_low[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~8 ( -// Equation(s): -// \z80_|alu_|db_low[2]~8_combout = (\z80_|alu_|db_low[2]~7_combout & (((!\z80_|bus_control_|db[5]~17_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~17_combout ), - .datab(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_low[2]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~8 .lut_mask = 16'h4F00; -defparam \z80_|alu_|db_low[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~59 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~62_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[2]~12_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[2]~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~62 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~63 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~61_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~61 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~60 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~64_combout = (\z80_|reg_file_|gdfx_temp1[2]~62_combout & (\z80_|reg_file_|gdfx_temp1[2]~63_combout & (\z80_|reg_file_|gdfx_temp1[2]~61_combout & \z80_|reg_file_|gdfx_temp1[2]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~62_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~63_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~61_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~15 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~58_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~58 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~65_combout = (\z80_|reg_file_|gdfx_temp1[2]~59_combout & (\z80_|reg_file_|gdfx_temp1[2]~64_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout & \z80_|reg_file_|gdfx_temp1[2]~58_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~59_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~64_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~58_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~66_combout = ((\z80_|reg_file_|gdfx_temp1[2]~65_combout & ((\z80_|reg_file_|db_hi_as[2]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~65_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~66 .lut_mask = 16'hDD5D; -defparam \z80_|reg_file_|gdfx_temp1[2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( -// Equation(s): -// \z80_|alu_|db[2]~11_combout = (\z80_|alu_control_|db[2]~22_combout & ((\z80_|reg_file_|gdfx_temp1[2]~66_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[2]~22_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[2]~66_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[2]~22_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~11 .lut_mask = 16'h8ACF; -defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N14 -cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( -// Equation(s): -// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~22_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[2]~11_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db_low[2]~22_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( -// Equation(s): -// \z80_|alu_|db_low[2]~5_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( -// Equation(s): -// \z80_|alu_|db_low[2]~6_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~5_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~12_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_|db_low[2]~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'hCAFF; -defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N2 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( -// Equation(s): -// \z80_|alu_|db_low[2]~9_combout = (\z80_|alu_|db_low[2]~8_combout & (\z80_|alu_|db_low[2]~6_combout & ((\z80_|alu_|result_lo [2]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|result_lo [2]), - .datab(\z80_|alu_|db_low[2]~8_combout ), - .datac(\z80_|alu_|db_low[2]~6_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hC080; -defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~22 ( -// Equation(s): -// \z80_|alu_|db_low[2]~22_combout = (\z80_|alu_|db_low[2]~9_combout ) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_low[2]~9_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~22 .lut_mask = 16'hF3F3; -defparam \z80_|alu_|db_low[2]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & ((\z80_|alu_|db_low[2]~22_combout ) # ((\z80_|alu_|db_high[2]~25_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[2]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(\z80_|alu_|db_high[2]~25_combout ), - .datac(\z80_|alu_|db_low[2]~22_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N19 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N24 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hFC00; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~19 ( -// Equation(s): -// \z80_|alu_control_|db[2]~19_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|alu_flags_|flags_hf2~q ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_66_oe~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~19 .lut_mask = 16'hFFEF; -defparam \z80_|alu_control_|db[2]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~8_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~23 ( -// Equation(s): -// \z80_|alu_control_|db[1]~23_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|alu_|db[1]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_oe~2_combout ) # -// ((!\z80_|alu_|db[1]~16_combout & \z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~23 .lut_mask = 16'h7350; -defparam \z80_|alu_control_|db[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( -// Equation(s): -// \z80_|alu_control_|db[1]~24_combout = (\z80_|alu_control_|db[2]~19_combout & (!\z80_|alu_control_|db[1]~23_combout & ((\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|db[2]~19_combout ), - .datac(\z80_|alu_control_|db[1]~23_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0C04; -defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|alu_control_|db[1]~24_combout & (((\z80_|bus_control_|db[1]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[1]~13_combout ), - .datab(\z80_|alu_control_|db[1]~24_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h08CC; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = (\z80_|alu_control_|db[1]~25_combout ) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_control_|db[1]~25_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'hF0FF; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[1]~26_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .datad(\z80_|alu_control_|db[1]~26_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~29_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~25_combout & \z80_|reg_file_|gdfx_temp0[1]~28_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N3 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N29 +// Location: FF_X31_Y13_N23 dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -31532,101 +20454,101 @@ defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N28 +// Location: LCCOMB_X31_Y13_N22 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[1]~32_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hA2F3; defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N12 +// Location: LCCOMB_X31_Y17_N26 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( // Equation(s): // \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hAF00; +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF300; defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N10 +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~85_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_cy~85_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h6A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N4 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .dataa(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hAF2F; defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N2 +// Location: LCCOMB_X30_Y17_N14 cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( // Equation(s): -// \z80_|address_latch_|abusz [1] = (\z80_|reg_file_|db_lo_as[1]~6_combout & !\z80_|resets_|clrpc~0_combout ) +// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - .dataa(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), .cin(gnd), .combout(\z80_|address_latch_|abusz [1]), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h00AA; +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h3300; defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[1]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[1]~feeder_combout = \z80_|address_latch_|abusz [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N23 +// Location: FF_X30_Y17_N19 dffeas \z80_|address_latch_|Q[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[1]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [1]), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|execute_|ctl_al_we~12_combout ), .devclrn(devclrn), .devpor(devpor), @@ -31637,30 +20559,13 @@ defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; defparam \z80_|address_latch_|Q[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hFF0F; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 +// Location: LCCOMB_X30_Y17_N6 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ))) +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), .datac(\z80_|address_latch_|Q [1]), .datad(\z80_|execute_|ctl_inc_dec~10_combout ), .cin(gnd), @@ -31671,493 +20576,16 @@ defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .lut_mask = defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[2]~22_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|alu_control_|db[2]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~35_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~37_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[2]~42_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 +// Location: LCCOMB_X29_Y17_N22 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & -// \z80_|execute_|ctl_inc_cy~81_combout )))) +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|execute_|ctl_inc_cy~85_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datab(\z80_|execute_|ctl_inc_cy~85_combout ), .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|execute_|ctl_inc_cy~81_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), .cout()); @@ -32166,44 +20594,61 @@ defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N4 +// Location: LCCOMB_X31_Y17_N16 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - .dataa(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'h8FAF; +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hF575; defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N16 +// Location: LCCOMB_X29_Y17_N12 cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( // Equation(s): -// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) +// \z80_|address_latch_|abusz [2] = (\z80_|reg_file_|db_lo_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - .dataa(gnd), + .dataa(\z80_|reg_file_|db_lo_as[2]~9_combout ), .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), .cin(gnd), .combout(\z80_|address_latch_|abusz [2]), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h00AA; defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N17 +// Location: LCCOMB_X29_Y17_N14 +cycloneive_lcell_comb \z80_|address_latch_|Q[2]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[2]~feeder_combout = \z80_|address_latch_|abusz [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [2]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N15 dffeas \z80_|address_latch_|Q[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [2]), + .d(\z80_|address_latch_|Q[2]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -32219,2641 +20664,112 @@ defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; defparam \z80_|address_latch_|Q[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y10_N28 +// Location: LCCOMB_X30_Y17_N2 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ))) +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|address_latch_|Q [2]), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h0F87; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h40BF; defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Location: LCCOMB_X35_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( // Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) +// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ctl_inc_cy~80_combout ), + .datad(\z80_|execute_|ctl_inc_cy~83_combout ), .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), + .combout(\z80_|execute_|ctl_inc_cy~86_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N13 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [3]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [4]) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(gnd), - .datac(\z80_|address_latch_|Q [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hAF00; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hDD00; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X39_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~59_combout & (\z80_|reg_file_|gdfx_temp0[4]~58_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .datab(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .datac(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h80A0; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & (\z80_|reg_file_|gdfx_temp0[4]~56_combout & \z80_|reg_file_|gdfx_temp0[4]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( -// Equation(s): -// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~10_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~10_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; -defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (!\z80_|alu_control_|db[4]~30_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_control_|db[4]~30_combout ), - .datab(\z80_|alu_flags_|flags_hf~combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h4500; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|alu_control_|db[4]~31_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hC4FF; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( -// Equation(s): -// \z80_|alu_|db[4]~8_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[4]~32_combout & ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .datac(\z80_|alu_control_|db[4]~32_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~8 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N16 -cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( -// Equation(s): -// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[4]~8_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~4 ( -// Equation(s): -// \z80_|alu_|db_high[1]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~22_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~10_combout )) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~4 .lut_mask = 16'hCACA; -defparam \z80_|alu_|db_high[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~5 ( -// Equation(s): -// \z80_|alu_|db_high[1]~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[1]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~5 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_high[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~6 ( -// Equation(s): -// \z80_|alu_|db_high[1]~6_combout = (\z80_|alu_|db_high[1]~3_combout & (\z80_|alu_|db_high[1]~2_combout & ((\z80_|alu_|db_high[1]~5_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~3_combout ), - .datab(\z80_|alu_|db_high[1]~2_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[1]~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~6 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~7 ( -// Equation(s): -// \z80_|alu_|db_high[1]~7_combout = ((\z80_|alu_|db_high[1]~6_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_high[3]~1_combout ), - .datab(\z80_|alu_|db_high[1]~6_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~7 .lut_mask = 16'hDDD5; -defparam \z80_|alu_|db_high[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), - .datac(\z80_|alu_|db_high[1]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'h00EC; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N9 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hC480; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~15_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) - - .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datab(\z80_|alu_|db_low[1]~15_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N11 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|alu_|op2_high [1]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~0 .lut_mask = 16'h3C5A; -defparam \z80_|alu_|alu_op2[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h7773; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & -// \z80_|alu_|alu_op1[1]~1_combout )))) # (!\z80_|alu_|alu_op2[1]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~1_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[1]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .datad(\z80_|alu_|alu_op1[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hF2B0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y16_N29 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~11 ( -// Equation(s): -// \z80_|alu_|db_low[1]~11_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [1] & ((\z80_|alu_|op2_low [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op2_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~11 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db_low[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( -// Equation(s): -// \z80_|alu_|db_low[1]~12_combout = (\z80_|alu_|db_low[1]~10_combout & (\z80_|alu_|db_low[1]~11_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~10_combout ), - .datab(\z80_|alu_|result_lo [1]), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_low[1]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( -// Equation(s): -// \z80_|alu_|db_low[1]~13_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_|db[0]~18_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hAACC; -defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( -// Equation(s): -// \z80_|alu_|db_low[1]~14_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~13_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~16_combout )) - - .dataa(\z80_|alu_|db[1]~16_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_low[1]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = ((\z80_|alu_|db_low[1]~12_combout & ((\z80_|alu_|db_low[1]~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_low[1]~12_combout ), - .datab(\z80_|alu_|db_low[1]~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'h8AFF; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (\z80_|alu_|db_high[3]~1_combout & (!\z80_|alu_|db_low[2]~9_combout & ((!\z80_|alu_|db_low[3]~4_combout ) # (!\z80_|alu_|db_low[3]~1_combout )))) - - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_low[2]~9_combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~15_combout & (\z80_|execute_|ctl_flags_alu~16_combout & (!\z80_|alu_|db_low[0]~21_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(\z80_|execute_|ctl_flags_alu~16_combout ), - .datac(\z80_|alu_|db_low[0]~21_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[0]~13_combout & !\z80_|alu_|db_high[1]~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|alu_|db_high[1]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h000F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & (!\z80_|alu_|db_high[2]~25_combout & !\z80_|alu_|db_high[3]~19_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .datac(\z80_|alu_|db_high[2]~25_combout ), - .datad(\z80_|alu_|db_high[3]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .lut_mask = 16'h0008; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal13~0_combout ) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hDFFF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[6]~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[6]~15_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hF800; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y15_N13 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N2 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_control_|out[6]~0_combout & \z80_|alu_|op1_high [0]))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|alu_|op1_high [0]), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFFEA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N14 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) - - .dataa(\z80_|alu_control_|out[6]~1_combout ), - .datab(\z80_|execute_|ctl_66_oe~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|alu_|op1_high [3]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~13 ( -// Equation(s): -// \z80_|alu_control_|db[6]~13_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|out[6]~2_combout ) # (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) # -// (!\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|alu_control_|out[6]~2_combout ) # (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~13 .lut_mask = 16'hDDD0; -defparam \z80_|alu_control_|db[6]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~14 ( -// Equation(s): -// \z80_|alu_control_|db[6]~14_combout = (\z80_|alu_control_|db[6]~13_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(\z80_|alu_control_|db[6]~13_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~14 .lut_mask = 16'h88AA; -defparam \z80_|alu_control_|db[6]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_reg_out_lo~2_combout ))) - - .dataa(\z80_|execute_|rsel3~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFFC8; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hF4F0; -defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~15 ( -// Equation(s): -// \z80_|alu_control_|db[6]~15_combout = ((\z80_|sw1_|db_down[6]~0_combout & (\z80_|alu_control_|db[6]~14_combout & \z80_|reg_file_|db_lo_ds[6]~0_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|sw1_|db_down[6]~0_combout ), - .datab(\z80_|alu_control_|db[6]~14_combout ), - .datac(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~15 .lut_mask = 16'h80FF; -defparam \z80_|alu_control_|db[6]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N20 -cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( -// Equation(s): -// \z80_|alu_|db[6]~21_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[6]~15_combout & ((\z80_|reg_file_|gdfx_temp1[6]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// (((\z80_|reg_file_|gdfx_temp1[6]~21_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .datad(\z80_|alu_control_|db[6]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N26 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_high[2]~25_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[6]~21_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~20 ( -// Equation(s): -// \z80_|alu_|db_high[2]~20_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~20_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|alu_|db[7]~20_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~20 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_high[2]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~21 ( -// Equation(s): -// \z80_|alu_|db_high[2]~21_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~20_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[2]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~21 .lut_mask = 16'hFD5D; -defparam \z80_|alu_|db_high[2]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[2]~9_combout ) # (!\z80_|alu_|db_high[3]~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(gnd), - .datac(\z80_|alu_|db_low[2]~9_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6 .lut_mask = 16'hA0AA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ) # ((\z80_|alu_|db_high[2]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|db_high[2]~25_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7 .lut_mask = 16'h5540; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N21 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~22 ( -// Equation(s): -// \z80_|alu_|db_high[2]~22_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [2] & ((\z80_|alu_|op1_high [2]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high -// [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~22 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db_high[2]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~23 ( -// Equation(s): -// \z80_|alu_|db_high[2]~23_combout = (\z80_|alu_|db_high[2]~22_combout & (((\z80_|bus_control_|db[5]~17_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~17_combout ), - .datab(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_high[2]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~23 .lut_mask = 16'h8F00; -defparam \z80_|alu_|db_high[2]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~24 ( -// Equation(s): -// \z80_|alu_|db_high[2]~24_combout = (\z80_|alu_|db_high[2]~21_combout & (\z80_|alu_|db_high[2]~23_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_high[2]~21_combout ), - .datab(\z80_|alu_|db_high[2]~23_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~24 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_high[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|db_high[2]~24_combout ) # (!\z80_|alu_|db_high[3]~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(\z80_|alu_|db_high[2]~24_combout ), - .datac(\z80_|alu_|db_high[3]~1_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h008A; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N7 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'hE400; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_low[2]~22_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) - - .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .datab(\z80_|alu_|db_low[2]~22_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N7 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [2]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [2])))) - - .dataa(\z80_|alu_|op2_low [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~2 .lut_mask = 16'h3C66; -defparam \z80_|alu_|alu_op2[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [2]))))) - - .dataa(\z80_|alu_|alu_op2[2]~2_combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [2]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1015; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hCCEF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hCFCE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~12_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout -// & ((\z80_|execute_|ctl_flags_alu~16_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~12_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_flags_alu~16_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hF444; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~0_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~0 .lut_mask = 16'h2202; -defparam \z80_|execute_|ctl_flags_cf2_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~1_combout = (((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_we~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_we~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~1 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_flags_cf2_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~1_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0D8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y14_N23 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|alu_|db[0]~18_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hE4E4; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # -// (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & -// ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h4472; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout $ ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout & \z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y14_N1 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hFE10; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = (\z80_|execute_|ctl_state_alu~11_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'h8500; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|pla_decode_|Equal10~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'hCECC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_alu_op_low~37_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~27_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'hFFD5; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) # ((\z80_|execute_|ctl_alu_op_low~32_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'hFFEA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~18_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'h7775; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|pla_decode_|Equal9~0_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & -// (((\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFCB8; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hFF20; -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~11_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~11 .lut_mask = 16'hF0F8; -defparam \z80_|execute_|ctl_flags_cf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~11_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_alu_op_low~33_combout & \z80_|execute_|ctl_alu_op_low~18_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~11_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout & \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N14 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~10_combout ))))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0A28; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( -// Equation(s): -// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~15_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|bus_control_|db[0]~15_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h5D00; -defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N28 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|db[0]~18_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hF0FF; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( -// Equation(s): -// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~8_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'hA200; -defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( -// Equation(s): -// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_control_|db[0]~9_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'h8CFF; -defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[0]~12_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .datad(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hC040; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~13_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .datab(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y11_N29 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [0]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~7_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 +// Location: LCCOMB_X29_Y17_N0 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # -// (\z80_|execute_|ctl_inc_cy~80_combout )))) +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~86_combout ) # +// (\z80_|execute_|ctl_inc_cy~70_combout )))) - .dataa(\z80_|execute_|ctl_inc_cy~70_combout ), - .datab(\z80_|execute_|ctl_inc_cy~67_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datab(\z80_|execute_|ctl_inc_cy~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~86_combout ), + .datad(\z80_|execute_|ctl_inc_cy~70_combout ), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hFE00; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hAAA8; defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y10_N16 +// Location: LCCOMB_X30_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|execute_|ctl_inc_cy~85_combout & ((\z80_|address_latch_|Q [1] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q [0])) # (!\z80_|address_latch_|Q +// [1] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [0])))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_cy~85_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'h2400; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N10 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout +// ))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), + .dataa(gnd), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), .datad(\z80_|address_latch_|Q [3]), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h7F80; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h3FC0; defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N3 +// Location: FF_X28_Y10_N15 dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -34872,7 +20788,7 @@ defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y11_N21 +// Location: FF_X28_Y10_N21 dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -34891,7 +20807,7 @@ defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y11_N2 +// Location: LCCOMB_X28_Y10_N14 cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( // Equation(s): // \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # @@ -34909,15 +20825,32 @@ defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y12_N19 +// Location: LCCOMB_X29_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N27 dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -34928,7 +20861,7 @@ defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X38_Y12_N3 +// Location: FF_X30_Y11_N11 dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -34947,123 +20880,33 @@ defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N2 +// Location: LCCOMB_X30_Y11_N10 cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) +// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), .cin(gnd), .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hB0BB; defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[3]~35_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|alu_control_|db[3]~35_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N13 +// Location: FF_X30_Y10_N5 dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), .devclrn(devclrn), .devpor(devpor), @@ -35074,7 +20917,7 @@ defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X39_Y12_N29 +// Location: FF_X30_Y10_N11 dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -35093,345 +20936,3536 @@ defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y12_N28 +// Location: LCCOMB_X30_Y10_N10 cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) +// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), .cin(gnd), .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~47_combout & \z80_|reg_file_|gdfx_temp0[3]~49_combout ))) +// \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N6 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~2 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~2_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~2 .lut_mask = 16'hF8FC; -defparam \z80_|sw1_|db_down[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~2_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[3]~33_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datad(\z80_|sw1_|db_down[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hA200; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[3]~34_combout ), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hD5DD; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N18 -cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( -// Equation(s): -// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|alu_|db[3]~13_combout ), - .datac(\z80_|alu_control_|db[3]~35_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hC4FF; -defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~0 ( -// Equation(s): -// \z80_|alu_|db_low[3]~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) - - .dataa(\z80_|alu_|db[2]~12_combout ), + .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~0 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~1 ( -// Equation(s): -// \z80_|alu_|db_low[3]~1_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~14_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[3]~14_combout ), - .datab(\z80_|alu_|db_low[3]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~1 .lut_mask = 16'hCAFF; -defparam \z80_|alu_|db_low[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~23 ( -// Equation(s): -// \z80_|alu_|db_low[3]~23_combout = ((\z80_|alu_|db_low[3]~1_combout & \z80_|alu_|db_low[3]~4_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), .datac(gnd), - .datad(\z80_|alu_|db_low[3]~4_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .cin(gnd), - .combout(\z80_|alu_|db_low[3]~23_combout ), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|db_low[3]~23 .lut_mask = 16'hBB33; -defparam \z80_|alu_|db_low[3]~23 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))))) +// Location: FF_X29_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(\z80_|alu_|op1_low [3]), - .datac(\z80_|alu_|op1_high [3]), +// Location: FF_X30_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h3F3B; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~29_combout ) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|setM1~29_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_al_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hB3F3; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|execute_|setM1~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h5DDD; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # (!\z80_|execute_|ctl_reg_gp_we~2_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB3FF; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (\z80_|execute_|ctl_reg_in_hi~11_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~4_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|alu_|db[3]~11_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[3]~11_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[3]~11_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h4444; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|execute_|ctl_reg_gp_we~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5450; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~3_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hFB33; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (\z80_|execute_|ctl_reg_sys_we~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF3; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0002; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0008; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & (\z80_|reg_file_|gdfx_temp1[3]~45_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~40_combout & (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout & \z80_|reg_file_|gdfx_temp1[3]~46_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~13_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~13_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[1]~13_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout & (\z80_|reg_file_|gdfx_temp1[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'h8AAA; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h96CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~19_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~19_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[0]~19_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~24_combout & (\z80_|reg_file_|gdfx_temp1[0]~26_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & \z80_|reg_file_|gdfx_temp1[0]~27_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~6_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N9 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [7] & (\z80_|address_latch_|Q [8] & !\z80_|execute_|ctl_inc_dec~11_combout +// )) # (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [8] & \z80_|execute_|ctl_inc_dec~11_combout )))) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1800; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0C0C; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N5 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[9]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [9]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|alu_|db[2]~15_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[2]~15_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[2]~15_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N15 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~35_combout & (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~33_combout & \z80_|reg_file_|gdfx_temp1[2]~36_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~32_combout & (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .datab(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'h8FAF; +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hCC44; +defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (\z80_|reg_file_|db_hi_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|Q[10]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[10]~feeder_combout = \z80_|address_latch_|abusz [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [10]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N27 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[10]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [10] & (\z80_|address_latch_|Q [9] & +// !\z80_|execute_|ctl_inc_dec~11_combout )) # (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [9] & \z80_|execute_|ctl_inc_dec~11_combout )))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [9]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h1800; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N15 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [11]) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(gnd), + .datac(\z80_|address_latch_|Q [11]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|alu_|db_low[3]~11_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'h888A; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~8_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N7 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~3 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~3_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])) + + .dataa(gnd), + .datab(\z80_|alu_|op1_high [3]), + .datac(\z80_|alu_|op1_low [3]), .datad(\z80_|execute_|ctl_alu_op_low~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .combout(\z80_|alu_|alu_op1[3]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'h88A0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_|alu_op1[3]~3 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|alu_op1[3]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( +// Location: LCCOMB_X38_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( // Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|alu_|db_low[3]~23_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high +// [2])))) - .dataa(\z80_|alu_|db_low[3]~23_combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|alu_op2[2]~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h00EC; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0305; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y17_N5 -dffeas \z80_|alu_|op2_low[3] ( +// Location: LCCOMB_X39_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = ((\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mWrite~2_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAAFB; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # +// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[1]~17_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_high[1]~20_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'h5050; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N1 +dffeas \z80_|alu_|op2_high[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -35440,51 +24474,1928 @@ dffeas \z80_|alu_|op2_low[3] ( .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), + .q(\z80_|alu_|op2_high [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4 ( +// Location: LCCOMB_X36_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( // Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[3]~1_combout & \z80_|alu_|db_low[3]~4_combout )) # (!\z80_|alu_|db_high[3]~1_combout ))) +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~20_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[1]~20_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4 .lut_mask = 16'hB030; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ) # ((\z80_|alu_|db_high[3]~19_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) +// Location: FF_X36_Y10_N23 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ), - .datab(\z80_|alu_|db_high[3]~19_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), +// Location: LCCOMB_X37_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'h8C80; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N21 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~20_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal68~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # ((\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|execute_|ctl_state_alu~8_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~9_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~12_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h7577; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal61~2_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hFC00; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~20_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~21_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout & (((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout +// ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .lut_mask = 16'hC4CC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~12_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_alu_core_hf~20_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & !\z80_|pla_decode_|Equal71~2_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|pla_decode_|Equal71~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|pla_decode_|Equal21~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal3~0_combout & +// ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'hFCA8; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal13~1_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & \z80_|pla_decode_|Equal63~0_combout +// ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hFFEC; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|execute_|ctl_alu_op_low~31_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal72~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (!\z80_|pla_decode_|Equal72~2_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datab(\z80_|pla_decode_|Equal72~2_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout )) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFAFF; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_flags_sz_we~5_combout & \z80_|execute_|ctl_alu_core_R~0_combout )))) # +// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~4_combout = (((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (\z80_|execute_|ctl_flags_sz_we~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'h5000; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( +// Equation(s): +// \z80_|execute_|setM1~16_combout = (\z80_|execute_|setM1~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~31_combout ))) + + .dataa(\z80_|execute_|setM1~15_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0200; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|setM1~16_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|execute_|setM1~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_alu_oe~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (\z80_|execute_|ctl_flags_xy_we~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal11~1_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal11~1_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBAA; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; +defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~8_combout = ((\z80_|execute_|ctl_flags_alu~7_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~8_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_flags_alu~6_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_alu~7_combout ), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0070; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_xy_we~16_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datac(\z80_|execute_|ctl_sw_2d~4_combout ), + .datad(\z80_|execute_|ctl_flags_alu~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_flags_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|execute_|ctl_flags_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = ((\z80_|execute_|ctl_flags_alu~8_combout ) # ((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_alu~8_combout ), + .datac(\z80_|execute_|ctl_flags_alu~14_combout ), + .datad(\z80_|execute_|ctl_flags_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), + .datac(\z80_|alu_control_|db[1]~26_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEEE; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_high[3]~8_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFFB3; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h3070; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'h0800; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'hD850; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y9_N27 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|sequencer_|DFFE_M2_ff~q & +// (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'h7707; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = ((\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'hB3BB; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~15_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal13~2_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) + + .dataa(\z80_|alu_|op2_high [1]), + .datab(\z80_|alu_|op2_low [1]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h5A3C; +defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [1]))))) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(\z80_|alu_|op1_low [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = (((\z80_|pla_decode_|Equal71~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datad(\z80_|pla_decode_|Equal71~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|db_high[0]~26_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|alu_|db_high[0]~26_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) + + .dataa(\z80_|alu_|db_high[0]~26_combout ), + .datab(\z80_|alu_|db_low[0]~23_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout ), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .lut_mask = 16'h00F0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y17_N31 +// Location: FF_X37_Y10_N7 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|alu_|op2_high [0]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h3C5A; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & ((\z80_|ir_|opcode [3]) # ((!\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal62~2_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'hB0F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & \z80_|execute_|ctl_alu_core_S~7_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~9_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # +// (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h37FF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_alu_core_hf~20_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_core_hf~18_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hA0E0; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout & (((\z80_|execute_|ctl_alu_core_hf~19_combout & !\z80_|execute_|ctl_alu_op_low~29_combout )) # (!\z80_|execute_|ctl_alu_op_low~28_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~22_combout & (\z80_|execute_|ctl_alu_core_hf~19_combout & (!\z80_|execute_|ctl_alu_op_low~29_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0CAE; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hFF30; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hDFCC; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~20_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h22F2; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datab(\z80_|execute_|ctl_state_alu~13_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & !\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~7_combout & +// ((!\z80_|execute_|ctl_mWrite~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hC0CA; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~43_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~6_combout & (\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # +// ((\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~43 .lut_mask = 16'hD5C0; +defparam \z80_|execute_|ctl_alu_core_hf~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (!\z80_|execute_|ctl_alu_core_hf~43_combout & ((\z80_|execute_|ctl_alu_core_hf~32_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~32_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'h00E8; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~42_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~42 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_core_hf~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~42_combout & ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # (\z80_|execute_|ctl_alu_core_hf~33_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~41_combout = (!\z80_|execute_|ctl_state_alu~4_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal10~0_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~41 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_core_hf~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & +// (\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal11~1_combout & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal11~1_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~41_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~41_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .datad(\z80_|execute_|ctl_mWrite~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h0054; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~44_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~44 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & ((\z80_|execute_|ctl_alu_core_hf~44_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~44_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'h0E0A; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # ((!\z80_|execute_|ctl_alu_op_low~30_combout & \z80_|execute_|ctl_alu_core_hf~35_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~24_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFCFE; +defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~39_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = (\z80_|execute_|ctl_alu_core_R~2_combout ) # (((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[3]~11_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .lut_mask = 16'hC0D0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[3]~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), + .datad(\z80_|alu_|db_high[3]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .lut_mask = 16'h5450; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N9 dffeas \z80_|alu_|op2_high[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -35500,649 +26411,2610 @@ defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; defparam \z80_|alu_|op2_high[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y16_N20 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~3 ( +// Location: LCCOMB_X37_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 ( // Equation(s): -// \z80_|alu_|alu_op2[3]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) - - .dataa(\z80_|alu_|op2_low [3]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|op2_high [3]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~3 .lut_mask = 16'h3C66; -defparam \z80_|alu_|alu_op2[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~3_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [3])))) +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|alu_|alu_op2[3]~3_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), .datac(\z80_|execute_|ctl_alu_op_low~combout ), .datad(\z80_|alu_|op1_low [3]), .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), + .datac(\z80_|alu_|db_low[3]~25_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N19 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) + + .dataa(\z80_|alu_|op2_high [3]), + .datab(\z80_|alu_|op2_low [3]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h5A3C; +defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[3]~3_combout & \z80_|alu_|alu_op2[3]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) + + .dataa(\z80_|alu_|alu_op1[3]~3_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|alu_|alu_op2[3]~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high +// [3])))) + + .dataa(\z80_|alu_|alu_op2[3]~2_combout ), + .datab(\z80_|alu_|op1_high [3]), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0131; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0511; defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N24 +// Location: LCCOMB_X39_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hAFAE; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # +// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[4]~32_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|pla_decode_|Equal10~0_combout & +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hFC88; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~14_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~14_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N7 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ctl_state_alu~14_combout )) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|alu_flags_|DFFE_inst_latch_nf~q ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N8 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( +// Equation(s): +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h559A; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N30 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~40_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~40_combout & (\z80_|alu_flags_|flags_cf~combout )) + + .dataa(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(gnd), + .datad(\z80_|alu_flags_|flags_hf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hEE44; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~1_combout )))) +// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~1_combout )))) + + .dataa(\z80_|alu_|alu_op2[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~25_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|alu_|db[3]~11_combout ), + .datac(\z80_|alu_|db[5]~25_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hE4E4; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0C0C; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|Q[12]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[12]~feeder_combout = \z80_|address_latch_|abusz [12] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [12]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[12]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[12]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N15 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[12]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ +// (\z80_|address_latch_|Q [11]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .datad(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~12_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~17_combout )) # (!\z80_|execute_|ctl_reg_in_hi~12_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|alu_|db[4]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y11_N29 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & (\z80_|reg_file_|gdfx_temp1[4]~61_combout & \z80_|reg_file_|gdfx_temp1[4]~60_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|db[4]~16 ( +// Equation(s): +// \z80_|alu_|db[4]~16_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[4]~32_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[4]~32_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~16 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|db[7]~26 ( +// Equation(s): +// \z80_|alu_|db[7]~26_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_alu_oe~13_combout ), + .datac(\z80_|execute_|ctl_alu_oe~9_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~26 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|db[7]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( +// Equation(s): +// \z80_|alu_|db[4]~17_combout = ((\z80_|alu_|db[4]~16_combout & ((\z80_|alu_|db_high[0]~26_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[4]~16_combout ), + .datab(\z80_|alu_|db[7]~26_combout ), + .datac(\z80_|alu_|db_high[0]~26_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h00C8; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~6_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[0]~23_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[4]~17_combout ))) + + .dataa(\z80_|alu_|db_high[0]~23_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[4]~17_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hAAF0; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'h5575; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~26_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[0]~26_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N21 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op1_high [0] & (((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [0] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [0]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [0]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~22_combout & ((\z80_|alu_|db_high[0]~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[0]~24_combout ), + .datab(\z80_|alu_|db_high[0]~21_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'h8C00; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~26 ( +// Equation(s): +// \z80_|alu_|db_high[0]~26_combout = ((\z80_|alu_|db_high[0]~25_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~26 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) # +// (!\z80_|alu_|db_low[0]~23_combout & (((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) + + .dataa(\z80_|alu_|db_low[0]~23_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datad(\z80_|alu_|db_high[0]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h00F0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFEFE; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N31 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|alu_|op1_high [0]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) # +// (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_low[0]~23_combout )))) + + .dataa(\z80_|alu_|alu_op1[0]~1_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h5050; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N15 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(gnd), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0AA; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~9_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & +// \z80_|execute_|ctl_alu_core_S~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_low [1]), + .datac(gnd), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hDD88; +defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[1]~0_combout & \z80_|alu_|alu_op2[1]~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datac(\z80_|alu_|alu_op1[1]~0_combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFBBB; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # +// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F01; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( +// Equation(s): +// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(gnd), + .datad(\z80_|alu_|op1_low [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hEE22; +defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op2[2]~0_combout & \z80_|alu_|alu_op1[2]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|alu_|alu_op1[2]~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hFF0B; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N14 cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( // Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|execute_|ctl_alu_core_R~5_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ))) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op1[3]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & +// \z80_|alu_|alu_op2[3]~2_combout )))) # (!\z80_|alu_|alu_op1[3]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .dataa(\z80_|alu_|alu_op1[3]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|alu_|alu_op2[3]~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), .cin(gnd), .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'h152F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFB20; defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 ( +// Location: LCCOMB_X28_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder ( // Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout -// )) +// \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout .dataa(gnd), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .lut_mask = 16'hCCFC; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~14 ( -// Equation(s): -// \z80_|alu_|db_high[3]~14_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~14 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_high[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~15 ( -// Equation(s): -// \z80_|alu_|db_high[3]~15_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~14_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~20_combout )))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db_high[3]~14_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~15 .lut_mask = 16'hACFF; -defparam \z80_|alu_|db_high[3]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~16 ( -// Equation(s): -// \z80_|alu_|db_high[3]~16_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_high [3] & ((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high -// [3]) # ((!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op2_high [3]), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~16 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db_high[3]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~17 ( -// Equation(s): -// \z80_|alu_|db_high[3]~17_combout = (\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[5]~17_combout )) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~17 .lut_mask = 16'hC000; -defparam \z80_|alu_|db_high[3]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~18 ( -// Equation(s): -// \z80_|alu_|db_high[3]~18_combout = (\z80_|alu_|db_high[3]~15_combout & (\z80_|alu_|db_high[3]~16_combout & ((\z80_|alu_|db_high[3]~17_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) - - .dataa(\z80_|alu_|db_high[3]~15_combout ), - .datab(\z80_|alu_|db_high[3]~16_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_high[3]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~18 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[3]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~19 ( -// Equation(s): -// \z80_|alu_|db_high[3]~19_combout = ((\z80_|alu_|db_high[3]~18_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_high[3]~18_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~19 .lut_mask = 16'hF3B3; -defparam \z80_|alu_|db_high[3]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N30 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~19_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_high[3]~19_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( -// Equation(s): -// \z80_|alu_control_|db[7]~16_combout = (\z80_|alu_flags_|DFFE_inst_latch_sf~q & (!\z80_|alu_|db[7]~20_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q & ((\z80_|execute_|ctl_flags_oe~2_combout ) # -// ((!\z80_|alu_|db[7]~20_combout & \z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h7350; -defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[7]~1_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[7]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[7]~1 .lut_mask = 16'hFF40; -defparam \z80_|reg_file_|db_lo_ds[7]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( -// Equation(s): -// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~1_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~9_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datab(\z80_|reg_file_|db_lo_ds[7]~1_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h4C0C; -defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = ((!\z80_|alu_control_|db[7]~16_combout & (\z80_|alu_control_|db[7]~17_combout & \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[7]~16_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_control_|db[7]~17_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h7333; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|execute_|ctl_flags_alu~16_combout & \z80_|alu_|db_high[3]~19_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (\z80_|execute_|ctl_flags_alu~16_combout & ((\z80_|alu_|db_high[3]~19_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|execute_|ctl_flags_alu~16_combout ), - .datac(\z80_|alu_control_|db[7]~18_combout ), - .datad(\z80_|alu_|db_high[3]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hECA0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y15_N5 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( +// Location: FF_X28_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N18 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal40~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) +// Location: FF_X28_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), +// Location: LCCOMB_X28_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N28 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ) # ((\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|ir_|opcode [4] & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// !\z80_|alu_control_|sel[1]~0_combout )))) +// Location: FF_X27_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|alu_control_|sel[1]~0_combout ), +// Location: FF_X27_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hAAD8; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ))) +// Location: FF_X27_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), +// Location: FF_X28_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N10 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q ))) +// Location: FF_X28_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|alu_|alu_parity_out~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), +// Location: LCCOMB_X28_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|alu_|db[7]~21_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[7]~21_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[7]~21_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~69_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & (\z80_|reg_file_|gdfx_temp1[7]~72_combout & \z80_|reg_file_|gdfx_temp1[7]~71_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout & \z80_|reg_file_|gdfx_temp1[7]~68_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~75_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & +// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [13]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|alu_|db[5]~25_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[5]~25_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[5]~25_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~52_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N9 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~50_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), .datad(gnd), .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), + .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h5656; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X41_Y13_N11 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( // Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~11_combout ))) +// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), + .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout ) +// \z80_|address_latch_|abusz [13] = (\z80_|reg_file_|db_hi_as[5]~15_combout & !\z80_|resets_|clrpc~0_combout ) - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal62~3_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .combout(\z80_|address_latch_|abusz [13]), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'hFFFD; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0C0C; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|Q[13]~feeder ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h7000; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|alu_control_|DFFE_latch_pf_tmp~q ) # (\z80_|execute_|ctl_alu_op_low~combout ))))) - - .dataa(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|alu_parity_out~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h1E00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~38_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = ((\z80_|execute_|ctl_flags_pf_we~5_combout ) # ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_flags_xy_we~11_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & \z80_|execute_|ctl_flags_alu~16_combout ) +// \z80_|address_latch_|Q[13]~feeder_combout = \z80_|address_latch_|abusz [13] .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [13]), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .combout(\z80_|address_latch_|Q[13]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'hF000; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|Q[13]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[13]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~19_combout )) +// Location: FF_X28_Y16_N23 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[13]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ) + + .dataa(gnd), .datab(gnd), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|address_latch_|Q [13]), + .datad(\z80_|execute_|ctl_inc_dec~11_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'h000A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~11 ( +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~11_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout )) # (!\z80_|pla_decode_|Equal69~0_combout ))) +// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~21_combout & !\z80_|resets_|clrpc~0_combout ) - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout ), + .combout(\z80_|address_latch_|abusz [15]), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~11 .lut_mask = 16'h8A0A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~11 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [9] & (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & !\z80_|address_latch_|Q [8]))) - - .dataa(\z80_|address_latch_|Q [9]), - .datab(\z80_|address_latch_|Q [10]), - .datac(\z80_|address_latch_|Q [11]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [1] & (!\z80_|address_latch_|Q [2] & !\z80_|address_latch_|Q [3]))) - - .dataa(\z80_|address_latch_|Q [0]), - .datab(\z80_|address_latch_|Q [1]), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [7] & !\z80_|address_latch_|Q [5]))) - - .dataa(\z80_|address_latch_|Q [6]), - .datab(\z80_|address_latch_|Q [4]), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|Q [5]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N15 +// Location: FF_X28_Y16_N27 dffeas \z80_|address_latch_|Q[15] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_latch_|abusz [15]), @@ -36161,15 +29033,4509 @@ defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; defparam \z80_|address_latch_|Q[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N0 +// Location: LCCOMB_X28_Y16_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|execute_|ctl_inc_dec~11_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|alu_|db[6]~23_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[6]~23_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[6]~23_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & (\z80_|reg_file_|gdfx_temp1[6]~78_combout & \z80_|reg_file_|gdfx_temp1[6]~81_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~76_combout & (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .datab(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|Q[14]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[14]~feeder_combout = \z80_|address_latch_|abusz [14] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [14]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N5 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[14]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [14]), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3363; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( +// Equation(s): +// \z80_|alu_|db[7]~20_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .datad(\z80_|alu_control_|db[7]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db[7]~21 ( +// Equation(s): +// \z80_|alu_|db[7]~21_combout = ((\z80_|alu_|db[7]~20_combout & ((\z80_|alu_|db_high[3]~8_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|alu_|db[7]~26_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~21 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[7]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N22 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~21_combout & ((\z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & +// (\z80_|alu_|db[7]~21_combout )))) + + .dataa(\z80_|alu_|db[7]~21_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_|db[0]~19_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB822; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|alu_control_|db[0]~12_combout & (\z80_|execute_|ctl_flags_bus~combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & +// ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[0]~12_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hD5C0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hE000; +defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y9_N3 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N0 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N4 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) + + .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCCEE; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~23_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(\z80_|alu_|db[6]~23_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~5_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~21_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(\z80_|alu_|db_high[3]~5_combout ), + .datac(\z80_|alu_|db[7]~21_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op2_high [3] & (((\z80_|alu_|op1_high [3])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_high [3] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [3]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_high [3]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~27 ( +// Equation(s): +// \z80_|alu_|db_high[3]~27_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~27 .lut_mask = 16'hD555; +defparam \z80_|alu_|db_high[3]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~27_combout & ((\z80_|alu_|db_high[3]~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[3]~6_combout ), + .datab(\z80_|alu_|db_high[3]~4_combout ), + .datac(\z80_|alu_|db_high[3]~27_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'h80C0; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~8 ( +// Equation(s): +// \z80_|alu_|db_high[3]~8_combout = ((\z80_|alu_|db_high[3]~7_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~8 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~8_combout )))) + + .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .lut_mask = 16'h00EA; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N15 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~9 ( +// Equation(s): +// \z80_|alu_|db_low[3]~9_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~9 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_low[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~10 ( +// Equation(s): +// \z80_|alu_|db_low[3]~10_combout = (\z80_|alu_|db_low[3]~9_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~15_combout ), + .datab(\z80_|alu_|db_low[3]~9_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~10 .lut_mask = 16'h4C0C; +defparam \z80_|alu_|db_low[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N15 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( +// Equation(s): +// \z80_|alu_|db_low[3]~7_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~17_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) + + .dataa(\z80_|alu_|db[4]~17_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( +// Equation(s): +// \z80_|alu_|db_low[3]~8_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~7_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~11_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|alu_|db[3]~11_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_low[3]~7_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~11 ( +// Equation(s): +// \z80_|alu_|db_low[3]~11_combout = (\z80_|alu_|db_low[3]~10_combout & (\z80_|alu_|db_low[3]~8_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[3]~10_combout ), + .datab(\z80_|alu_|result_lo [3]), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|db_low[3]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~11 .lut_mask = 16'hA800; +defparam \z80_|alu_|db_low[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( +// Equation(s): +// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_high[3]~2_combout ), + .datac(\z80_|alu_|db_low[3]~11_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hF1F1; +defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N12 +cycloneive_lcell_comb \z80_|alu_|db[3]~10 ( +// Equation(s): +// \z80_|alu_|db[3]~10_combout = (\z80_|execute_|ctl_alu_oe~14_combout & (\z80_|alu_|db_low[3]~25_combout & ((\z80_|reg_file_|gdfx_temp1[3]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~14_combout & +// (((\z80_|reg_file_|gdfx_temp1[3]~48_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datad(\z80_|alu_|db_low[3]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~10 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|db[3]~11 ( +// Equation(s): +// \z80_|alu_|db[3]~11_combout = ((\z80_|alu_|db[3]~10_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[3]~10_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[3]~35_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~11 .lut_mask = 16'hA2FF; +defparam \z80_|alu_|db[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~9_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~3_combout ), + .datac(\z80_|execute_|ctl_alu_oe~9_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0070; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~14_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|setM1~49_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_|db_low[3]~25_combout & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[3]~35_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_low[3]~25_combout & +// (\z80_|alu_control_|db[3]~35_combout & (\z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_|db_low[3]~25_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hEAC0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00CC; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|pla_decode_|Equal56~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # +// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N31 +dffeas \z80_|alu_flags_|flags_xf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_xf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( +// Equation(s): +// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|alu_flags_|flags_xf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF030; +defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N16 +cycloneive_lcell_comb \z80_|sw1_|db_down[3]~1 ( +// Equation(s): +// \z80_|sw1_|db_down[3]~1_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[3]~1 .lut_mask = 16'hFF8C; +defparam \z80_|sw1_|db_down[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( +// Equation(s): +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~1_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datab(\z80_|alu_control_|db[3]~33_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|sw1_|db_down[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8C00; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~11_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_|db[3]~11_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[3]~34_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N3 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N17 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [3]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h40BF; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout )))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h6AAA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N27 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N9 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|alu_control_|db[4]~32_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~59_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & \z80_|reg_file_|gdfx_temp0[4]~56_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp0[4]~62_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hCC0C; +defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N23 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [4]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|address_latch_|Q [4]), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0F4B; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout +// ))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h6A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N5 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|alu_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N3 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~68_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hF050; +defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N27 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5595; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|alu_control_|db[6]~22_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N5 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & \z80_|reg_file_|gdfx_temp0[6]~75_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N23 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout ))))) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h001E; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hF575; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|alu_control_|db[7]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[7]~0_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[7]~0 .lut_mask = 16'hF0F8; +defparam \z80_|reg_file_|db_lo_ds[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N11 +dffeas \z80_|interrupts_|im2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|interrupts_|im2~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( +// Equation(s): +// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|reg_file_|db_lo_ds[7]~0_combout ), + .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|bus_control_|db[7]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2A0A; +defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( +// Equation(s): +// \z80_|alu_control_|db[7]~16_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[7]~21_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (\z80_|execute_|ctl_sw_2u~7_combout & (!\z80_|alu_|db[7]~21_combout ))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_|db[7]~21_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h0CAE; +defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( +// Equation(s): +// \z80_|alu_control_|db[7]~18_combout = ((\z80_|alu_control_|db[7]~17_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & !\z80_|alu_control_|db[7]~16_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[7]~17_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|alu_control_|db[7]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h33B3; +defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[7]~18_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y9_N9 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal62~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h008C; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (\z80_|execute_|ctl_flags_pf_we~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_pf_sel[0]~3_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~11_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & (\z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[2]~29_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datad(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'h88F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal62~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3070; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h152A; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h3B00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N24 cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( // Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [15] & (!\z80_|address_latch_|Q [13] & !\z80_|address_latch_|Q [12]))) +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [13]))) .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|address_latch_|Q [15]), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|Q [12]), + .datab(\z80_|address_latch_|Q [12]), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|Q [13]), .cin(gnd), .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), .cout()); @@ -36178,15 +33544,66 @@ defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y12_N0 +// Location: LCCOMB_X30_Y17_N16 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [2]))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|address_latch_|Q [3]), + .datad(\z80_|address_latch_|Q [2]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0004; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & !\z80_|address_latch_|Q [4]))) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(\z80_|address_latch_|Q [6]), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|address_latch_|Q [4]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [8]))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [11]), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [8]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N18 cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( // Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~0_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~1_combout ))) - .dataa(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .dataa(\z80_|decode_state_|DFFE_instNonRep~0_combout ), .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), .datac(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~1_combout ), .cin(gnd), .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), .cout()); @@ -36195,7 +33612,7 @@ defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N28 +// Location: LCCOMB_X32_Y16_N16 cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( // Equation(s): // \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & @@ -36213,7 +33630,7 @@ defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X41_Y13_N29 +// Location: FF_X32_Y16_N17 dffeas \z80_|decode_state_|DFFE_instNonRep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), @@ -36232,133 +33649,220 @@ defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~12 ( +// Location: LCCOMB_X32_Y16_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout & (((!\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout & -// (((\z80_|decode_state_|DFFE_instNonRep~q )))) +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout ), - .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~12 .lut_mask = 16'h7F2A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'h02AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N8 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .dataa(\z80_|pla_decode_|Equal62~3_combout ), .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h152A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0040; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'h40CC; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~14 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~14_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~14 .lut_mask = 16'hFF01; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N0 +// Location: LCCOMB_X32_Y16_N10 cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[2]~22_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datab(\z80_|execute_|ctl_flags_bus~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|alu_control_|db[2]~22_combout ), + .dataa(\z80_|interrupts_|DFFE_instIFF2~q ), + .datab(\z80_|decode_state_|DFFE_instNonRep~q ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), .cin(gnd), .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hD850; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hA030; defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~13 ( +// Location: LCCOMB_X32_Y16_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~13_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # (\z80_|alu_flags_|DFFE_inst_latch_pf~14_combout -// )))) +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h808C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N23 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & +// \z80_|alu_|alu_op1[1]~0_combout )))) # (!\z80_|alu_|alu_op2[1]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|alu_op1[1]~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hFB20; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hA55A; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( +// Equation(s): +// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datad(\z80_|alu_|alu_parity_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out .lut_mask = 16'hA956; +defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal62~3_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFEF; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h20A0; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datac(\z80_|alu_|alu_parity_out~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~13_combout ), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~13 .lut_mask = 16'hFFC8; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~13 .sum_lutc_input = "datac"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X41_Y15_N27 +// Location: LCCOMB_X36_Y11_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hECCC; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N15 dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~13_combout ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -36374,34 +33878,190 @@ defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N26 +// Location: LCCOMB_X37_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[1]~20_combout & (!\z80_|alu_|db_high[3]~8_combout & (!\z80_|alu_|db_high[2]~14_combout & !\z80_|alu_|db_high[0]~26_combout ))) + + .dataa(\z80_|alu_|db_high[1]~20_combout ), + .datab(\z80_|alu_|db_high[3]~8_combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|alu_|db_high[0]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) + + .dataa(\z80_|alu_control_|db[6]~22_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hAA00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~11_combout & (\z80_|alu_|db_high[3]~3_combout & ((!\z80_|alu_|db_low[2]~3_combout ) # (!\z80_|alu_|db_low[2]~6_combout )))) + + .dataa(\z80_|alu_|db_low[2]~6_combout ), + .datab(\z80_|alu_|db_low[3]~11_combout ), + .datac(\z80_|alu_|db_low[2]~3_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h1300; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~17_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[0]~23_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) + + .dataa(\z80_|alu_|db_low[1]~17_combout ), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|alu_|db_low[0]~23_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hEC00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N27 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] +// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N18 cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( // Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ) # ((!\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|alu_control_|sel[1]~0_combout )))) +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|alu_control_|sel[1]~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), .cin(gnd), .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hB8CC; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N24 +// Location: LCCOMB_X37_Y11_N20 cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( // Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout $ (((!\z80_|ir_|opcode [3]))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & // (((\z80_|alu_control_|flags_cond_true~q )))) - .dataa(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .dataa(\z80_|ir_|opcode [3]), .datab(\z80_|execute_|ctl_eval_cond~0_combout ), .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), .cin(gnd), .combout(\z80_|alu_control_|flags_cond_true~0_combout ), .cout()); @@ -36410,7 +34070,7 @@ defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y16_N25 +// Location: FF_X37_Y11_N21 dffeas \z80_|alu_control_|flags_cond_true ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|alu_control_|flags_cond_true~0_combout ), @@ -36429,32 +34089,32 @@ defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Location: LCCOMB_X35_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( // Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ixy_d~5_combout ) +// \z80_|execute_|ctl_reg_sel_wz~13_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - .dataa(\z80_|execute_|ixy_d~5_combout ), + .dataa(\z80_|pla_decode_|Equal35~0_combout ), .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), .datad(\z80_|pla_decode_|Equal34~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y15_N16 +// Location: LCCOMB_X35_Y16_N18 cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( // Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~10_combout ) +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - .dataa(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~13_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), .cout()); @@ -36463,3091 +34123,2050 @@ defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'hF7FF; defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y15_N4 +// Location: LCCOMB_X34_Y14_N0 cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( // Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (((\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~16_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) - .dataa(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~11_combout ), .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hBFFF; defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~17_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Location: LCCOMB_X30_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Location: LCCOMB_X29_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Location: LCCOMB_X30_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~16_combout ) # ((\z80_|execute_|ctl_sw_4u~5_combout ) # (\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( +// Location: FF_X30_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( +// Location: FF_X31_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~32 ( +// Location: LCCOMB_X31_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~32_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~32 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~32 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( +// Location: FF_X31_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~13 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) +// Location: FF_X30_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), +// Location: FF_X30_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~13 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~13 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~33 ( +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~33_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~33 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~33 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( +// Location: FF_X30_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y15_N3 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~36 ( +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|alu_control_|db[1]~26_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~36_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~36 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~36 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( +// Location: FF_X28_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X35_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~34 ( +// Location: LCCOMB_X28_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~34 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~35_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[1]~16_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~35 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~37_combout = (\z80_|reg_file_|gdfx_temp1[1]~33_combout & (\z80_|reg_file_|gdfx_temp1[1]~36_combout & (\z80_|reg_file_|gdfx_temp1[1]~34_combout & \z80_|reg_file_|gdfx_temp1[1]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~33_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~36_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~34_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~39_combout +// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( +// Location: FF_X28_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~31 ( +// Location: LCCOMB_X28_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~31_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~31_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~31 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[1]~31 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~38 ( +// Location: LCCOMB_X31_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~38_combout = (\z80_|reg_file_|gdfx_temp1[1]~32_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~37_combout & \z80_|reg_file_|gdfx_temp1[1]~31_combout ))) +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~29_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - .dataa(\z80_|reg_file_|gdfx_temp1[1]~32_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~37_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~31_combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~38_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~38 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~39 ( +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~39_combout = ((\z80_|reg_file_|gdfx_temp1[1]~38_combout & ((\z80_|reg_file_|db_hi_as[1]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~39 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp1[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~7_combout = (\z80_|reg_file_|gdfx_temp1[1]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[1]~39_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~7 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~8_combout = (\z80_|reg_file_|db_hi_as[1]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[1]~7_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~8 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|execute_|ctl_inc_dec~8_combout & (!\z80_|address_latch_|Q [7] & !\z80_|address_latch_|Q -// [8])) # (!\z80_|execute_|ctl_inc_dec~8_combout & (\z80_|address_latch_|Q [7] & \z80_|address_latch_|Q [8])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) +// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout .dataa(gnd), .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~9_combout = ((\z80_|reg_file_|db_hi_as[1]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[1]~8_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~9 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~9_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y11_N27 -dffeas \z80_|address_latch_|Q[9] ( +// Location: FF_X29_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [9]), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q -// [9]))))) - - .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), - .datab(\z80_|address_latch_|Q [10]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( +// Location: FF_X29_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~18_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~16 ( +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( // Equation(s): -// \z80_|reg_file_|db_hi_as[2]~16_combout = (\z80_|reg_file_|gdfx_temp1[2]~66_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[2]~66_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - .dataa(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~16_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~16 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[2]~16 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( +// Location: FF_X30_Y13_N23 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~18_combout ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hF733; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hF0F8; +defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( +// Equation(s): +// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|bus_control_|db[1]~11_combout ), + .datab(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0C8C; +defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( +// Equation(s): +// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[1]~13_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[1]~13_combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_|db[1]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0ACE; +defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( +// Equation(s): +// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~23_combout & !\z80_|alu_control_|db[1]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[1]~25_combout ), + .datab(\z80_|alu_control_|db[2]~23_combout ), + .datac(\z80_|alu_control_|db[6]~11_combout ), + .datad(\z80_|alu_control_|db[1]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h0F8F; +defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|db[1]~12 ( +// Equation(s): +// \z80_|alu_|db[1]~12_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[1]~26_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[1]~26_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~12 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db[1]~13 ( +// Equation(s): +// \z80_|alu_|db[1]~13_combout = ((\z80_|alu_|db[1]~12_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[1]~12_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~13 .lut_mask = 16'hA2FF; +defparam \z80_|alu_|db[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( +// Equation(s): +// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~13_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|alu_|db[1]~13_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF5A0; +defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( +// Equation(s): +// \z80_|alu_|db_low[0]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~19_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[0]~21_combout ), + .datac(\z80_|alu_|db[0]~19_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( +// Equation(s): +// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h5557; +defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( +// Equation(s): +// \z80_|alu_|db_low[0]~19_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op1_low [0]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N25 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( +// Equation(s): +// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~18_combout & (\z80_|alu_|db_low[0]~19_combout & ((\z80_|alu_|result_lo [0]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[0]~18_combout ), + .datab(\z80_|alu_|db_low[0]~19_combout ), + .datac(\z80_|alu_|result_lo [0]), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( +// Equation(s): +// \z80_|alu_|db_low[0]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & ((\z80_|alu_|db_low[0]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~20_combout ) # +// (!\z80_|alu_|db_high[3]~2_combout )))) + + .dataa(\z80_|alu_|db_low[0]~22_combout ), + .datab(\z80_|alu_|db_high[3]~2_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[0]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hAF03; +defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( +// Equation(s): +// \z80_|alu_|db[0]~18_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_|db_low[0]~23_combout ) # ((!\z80_|execute_|ctl_alu_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_|db_low[0]~23_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db[0]~19 ( +// Equation(s): +// \z80_|alu_|db[0]~19_combout = ((\z80_|alu_|db[0]~18_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[0]~12_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~19 .lut_mask = 16'hA2FF; +defparam \z80_|alu_|db[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( +// Equation(s): +// \z80_|alu_|db_low[1]~15_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~19_combout )) + + .dataa(\z80_|alu_|db[0]~19_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( +// Equation(s): +// \z80_|alu_|db_low[1]~16_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[1]~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[1]~13_combout ))) + + .dataa(\z80_|alu_|db_low[1]~15_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[1]~13_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAAF0; +defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( +// Equation(s): +// \z80_|alu_|db_low[1]~12_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'h5755; +defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( +// Equation(s): +// \z80_|alu_|db_low[1]~13_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op1_low [1]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N21 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( +// Equation(s): +// \z80_|alu_|db_low[1]~14_combout = (\z80_|alu_|db_low[1]~12_combout & (\z80_|alu_|db_low[1]~13_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[1]~12_combout ), + .datab(\z80_|alu_|db_low[1]~13_combout ), + .datac(\z80_|alu_|result_lo [1]), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( +// Equation(s): +// \z80_|alu_|db_low[1]~17_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~16_combout & \z80_|alu_|db_low[1]~14_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~14_combout )) # +// (!\z80_|alu_|db_high[3]~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_high[3]~2_combout ), + .datac(\z80_|alu_|db_low[1]~16_combout ), + .datad(\z80_|alu_|db_low[1]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hF511; +defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_low[1]~17_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[1]~20_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00F0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N1 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .q(\z80_|alu_|op1_low [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~17 ( +// Location: LCCOMB_X36_Y10_N28 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( // Equation(s): -// \z80_|reg_file_|db_hi_as[2]~17_combout = (\z80_|reg_file_|db_hi_as[2]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) - .dataa(\z80_|reg_file_|db_hi_as[2]~16_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .dataa(gnd), + .datab(\z80_|alu_|op1_low [1]), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|alu_|op1_low [2]), .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~17_combout ), + .combout(\z80_|alu_control_|out[6]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~17 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[2]~17 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0C0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~18 ( +// Location: LCCOMB_X36_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( // Equation(s): -// \z80_|reg_file_|db_hi_as[2]~18_combout = ((\z80_|reg_file_|db_hi_as[2]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout ) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~17_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~18 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_hi_as[2]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~18_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), + .dataa(gnd), .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[2]~18_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N8 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|alu_control_|db[4]~32_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N9 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( +// Equation(s): +// \z80_|alu_control_|db[2]~23_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|alu_flags_|flags_hf2~q ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~combout ), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|alu_flags_|flags_hf2~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFEF; +defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|bus_control_|db[2]~13_combout ), + .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h2F00; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( +// Equation(s): +// \z80_|alu_control_|db[2]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[2]~15_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (!\z80_|alu_|db[2]~15_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|alu_|db[2]~15_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h3B0A; +defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( +// Equation(s): +// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~23_combout & (\z80_|alu_control_|db[2]~28_combout & !\z80_|alu_control_|db[2]~27_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[6]~11_combout ), + .datab(\z80_|alu_control_|db[2]~23_combout ), + .datac(\z80_|alu_control_|db[2]~28_combout ), + .datad(\z80_|alu_control_|db[2]~27_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h55D5; +defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db[2]~14 ( +// Equation(s): +// \z80_|alu_|db[2]~14_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~39_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[2]~29_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[2]~29_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~14 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[2]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( +// Equation(s): +// \z80_|alu_|db[2]~15_combout = ((\z80_|alu_|db[2]~14_combout & ((\z80_|alu_|db_low[2]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db_low[2]~24_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[2]~14_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~2 ( +// Equation(s): +// \z80_|alu_|db_low[2]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~13_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|alu_|db[3]~11_combout ), + .datac(\z80_|alu_|db[1]~13_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), + .combout(\z80_|alu_|db_low[2]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~2 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|db_low[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N31 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [10]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Location: LCCOMB_X35_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~3 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~8_combout & (!\z80_|address_latch_|Q [10] & -// !\z80_|address_latch_|Q [9])) # (!\z80_|execute_|ctl_inc_dec~8_combout & (\z80_|address_latch_|Q [10] & \z80_|address_latch_|Q [9])))) +// \z80_|alu_|db_low[2]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~15_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), - .datab(\z80_|address_latch_|Q [10]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .dataa(\z80_|alu_|db[2]~15_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_low[2]~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .combout(\z80_|alu_|db_low[2]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h4200; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~3 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_low[2]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Location: LCCOMB_X35_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [11] & (!\z80_|execute_|ctl_inc_dec~8_combout & -// \z80_|address_latch_|Q [12])) # (!\z80_|address_latch_|Q [11] & (\z80_|execute_|ctl_inc_dec~8_combout & !\z80_|address_latch_|Q [12])))) +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|Q [12]), + .dataa(\z80_|alu_|db_low[2]~6_combout ), + .datab(\z80_|alu_|db_high[3]~3_combout ), + .datac(\z80_|alu_|db_low[2]~3_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0820; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hB300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Location: LCCOMB_X36_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - .dataa(gnd), - .datab(\z80_|address_latch_|Q [13]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h33CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3222; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [5] & ((\z80_|reg_file_|gdfx_temp1[5]~75_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[5]~75_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~19 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[5]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~20_combout = (\z80_|reg_file_|db_hi_as[5]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datad(\z80_|reg_file_|db_hi_as[5]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~20 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_hi_as[5]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~21_combout = ((\z80_|reg_file_|db_hi_as[5]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~21 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[5]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~21_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N27 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [13]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [13]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|Q [13]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~7_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~4_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [7] & ((\z80_|reg_file_|gdfx_temp1[7]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[7]~30_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~4 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|db_hi_as[7]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~5_combout = (\z80_|reg_file_|db_hi_as[7]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[7]~4_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~5 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[7]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~6_combout = ((\z80_|reg_file_|db_hi_as[7]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .datab(\z80_|reg_file_|db_hi_as[7]~5_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~6 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_hi_as[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~6_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h0A0A; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|execute_|ctl_inc_dec~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|execute_|ctl_apin_mux~1_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'hF333; -defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|address_latch_|abusz [15]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0D0D; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ctl_mWrite~2_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~15_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & !\z80_|execute_|fIOWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|fIORead~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( -// Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|ctl_mRead~7_combout & \z80_|execute_|fIOWrite~3_combout ))) - - .dataa(\z80_|execute_|fIORead~2_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|fIOWrite~3_combout ), - .datad(\z80_|execute_|fIORead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N14 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fMRead~36_combout ) # (((\z80_|execute_|fIORead~3_combout ) # (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )) - - .dataa(\z80_|execute_|fMRead~36_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFBF; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout ) # -// ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h4F44; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( +// Location: FF_X36_Y10_N25 +dffeas \z80_|alu_|op1_low[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~17 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[15]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~15_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0030; -defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h0202; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg -// [6] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|WideOr17~0_combout & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|WideOr17~0_combout ), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0088; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~0_combout ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N13 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), + .q(\z80_|alu_|op1_low [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Location: LCCOMB_X37_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [2])) +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [2]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Location: LCCOMB_X37_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~41_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q ))) +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ) # ((\z80_|alu_|db_low[2]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|extended~q ), + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), + .datac(\z80_|alu_|db_low[2]~24_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|zx_keyboard_|keys[6][1]~42_combout & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & (!\ula_|zx_keyboard_|keys[6][1]~40_combout )) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & ((\ula_|zx_keyboard_|keys[6][1]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N31 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( +// Location: FF_X37_Y10_N13 +dffeas \z80_|alu_|op2_low[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~16 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[14]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \D[1]~27 ( -// Equation(s): -// \D[1]~27_combout = (\ula_|zx_keyboard_|keys[7][1]~q & (\z80_|address_pins_|abus[15]~17_combout & ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[7][1]~q & -// (((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~q ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\z80_|address_pins_|abus[14]~16_combout ), - .cin(gnd), - .combout(\D[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~27 .lut_mask = 16'hDD0D; -defparam \D[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~19_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~19 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|keys[7][1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hF000; -defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|keys[5][4]~24_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~26_combout = (\ula_|zx_keyboard_|keys[1][4]~25_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h0C00; -defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N11 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .q(\z80_|alu_|op2_low [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Location: LCCOMB_X38_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) +// \z80_|alu_|db_low[2]~5_combout = (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - .dataa(\z80_|address_latch_|abusz [10]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .dataa(\z80_|alu_|op2_low [2]), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .combout(\z80_|alu_|db_low[2]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'h8ACF; +defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), +// Location: FF_X39_Y10_N13 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [10]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~22 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[10]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00A0; -defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~28_combout = (\ula_|zx_keyboard_|keys[5][4]~24_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[7][1]~19_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N9 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .q(\z80_|alu_|result_lo [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Location: LCCOMB_X35_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) +// \z80_|alu_|db_low[2]~6_combout = (\z80_|alu_|db_low[2]~4_combout & (\z80_|alu_|db_low[2]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2])))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|address_latch_|abusz [11]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|alu_|db_low[2]~4_combout ), + .datab(\z80_|alu_|db_low[2]~5_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|result_lo [2]), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .combout(\z80_|alu_|db_low[2]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N23 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( +// Location: LCCOMB_X35_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) + + .dataa(\z80_|alu_|db_low[2]~6_combout ), + .datab(\z80_|alu_|db_low[2]~3_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h80F0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N27 +dffeas \z80_|alu_|op2_high[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [11]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~21 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[11]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N2 -cycloneive_lcell_comb \D[1]~25 ( -// Equation(s): -// \D[1]~25_combout = (\ula_|zx_keyboard_|keys[2][1]~q & (\z80_|address_pins_|abus[10]~22_combout & ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) # (!\ula_|zx_keyboard_|keys[2][1]~q & -// (((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[2][1]~q ), - .datab(\z80_|address_pins_|abus[10]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\z80_|address_pins_|abus[11]~21_combout ), - .cin(gnd), - .combout(\D[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~25 .lut_mask = 16'hDD0D; -defparam \D[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~31_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h5050; -defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~32_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h1100; -defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][2]~32_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N5 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .q(\z80_|alu_|op2_high [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Location: LCCOMB_X38_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [12]))) +// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [12]), + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|alu_|op2_low [2]), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .combout(\z80_|alu_|alu_op2[2]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h4B78; +defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y2_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~24 ( +// Location: LCCOMB_X39_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( // Equation(s): -// \z80_|address_pins_|abus[12]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [12]), + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~24_combout ), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[12]~24 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[12]~24 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0BFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Location: LCCOMB_X39_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [13])) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~2_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - .dataa(\z80_|address_latch_|abusz [13]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|alu_op1[2]~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N3 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~23 ( +// Location: LCCOMB_X34_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( // Equation(s): -// \z80_|address_pins_|abus[13]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_|db_high[2]~9_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - .dataa(gnd), + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'h55D5; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~21_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~25_combout )) + + .dataa(\z80_|ir_|opcode [3]), .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|alu_|db[5]~25_combout ), + .datad(\z80_|alu_|db[7]~21_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~23_combout ), + .combout(\z80_|alu_|db_high[2]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[13]~23 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[13]~23 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hFA50; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( +// Location: LCCOMB_X35_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0011; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|ps2_keyboard_|shiftreg [4])) +// \z80_|alu_|db_high[2]~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[2]~11_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[6]~23_combout ))) .dataa(gnd), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\z80_|alu_|db_high[2]~11_combout ), + .datac(\z80_|alu_|db[6]~23_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .combout(\z80_|alu_|db_high[2]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0030; -defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Location: LCCOMB_X38_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [6])) +// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_high [2]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .combout(\z80_|alu_|db_high[2]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'h8800; -defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Location: LCCOMB_X34_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) +// \z80_|alu_|db_high[2]~13_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~12_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(gnd), + .dataa(\z80_|alu_|db_high[2]~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[2]~12_combout ), + .datad(\z80_|alu_|db_high[2]~10_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .combout(\z80_|alu_|db_high[2]~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( +// Location: LCCOMB_X35_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~14 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~38_combout & ((\ula_|zx_keyboard_|keys[5][1]~37_combout & ((!\ula_|zx_keyboard_|keys[5][1]~35_combout ))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & -// (\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) +// \z80_|alu_|db_high[2]~14_combout = ((\z80_|alu_|db_high[2]~13_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - .dataa(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .datab(\z80_|alu_|db_high[3]~3_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|db_high[2]~13_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .combout(\z80_|alu_|db_high[2]~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~14 .lut_mask = 16'hFB33; +defparam \z80_|alu_|db_high[2]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y13_N29 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \D[1]~26 ( +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( // Equation(s): -// \D[1]~26_combout = (\ula_|zx_keyboard_|keys[4][1]~q & (\z80_|address_pins_|abus[12]~24_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\ula_|zx_keyboard_|keys[4][1]~q & -// (((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) +// \z80_|alu_|db[6]~22_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - .dataa(\ula_|zx_keyboard_|keys[4][1]~q ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[5][1]~q ), + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .datad(\z80_|alu_control_|db[6]~22_combout ), .cin(gnd), - .combout(\D[1]~26_combout ), + .combout(\z80_|alu_|db[6]~22_combout ), .cout()); // synopsys translate_off -defparam \D[1]~26 .lut_mask = 16'hD0DD; -defparam \D[1]~26 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db[6]~23 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [9])) +// \z80_|alu_|db[6]~23_combout = ((\z80_|alu_|db[6]~22_combout & ((\z80_|alu_|db_high[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - .dataa(\z80_|address_latch_|abusz [9]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|alu_|db_high[2]~14_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .combout(\z80_|alu_|db[6]~23_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db[6]~23 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[6]~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y3_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~19 ( +// Location: LCCOMB_X36_Y10_N10 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( // Equation(s): -// \z80_|address_pins_|abus[9]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|alu_|op1_high [1]), + .datad(\z80_|alu_control_|out[6]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N26 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) + + .dataa(\z80_|execute_|ctl_66_oe~combout ), + .datab(\z80_|alu_control_|out[6]~1_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEA; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~19 ( +// Equation(s): +// \z80_|alu_control_|db[6]~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & +// (!\z80_|execute_|ctl_flags_oe~2_combout & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|out[6]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~19 .lut_mask = 16'hAF8C; +defparam \z80_|alu_control_|db[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( +// Equation(s): +// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_control_|db[6]~19_combout & ((\z80_|alu_|db[6]~23_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [9]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|alu_|db[6]~23_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[6]~19_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~19_combout ), + .combout(\z80_|alu_control_|db[6]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[9]~19 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[9]~19 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'hCF00; +defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Location: LCCOMB_X34_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) +// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|db[6]~20_combout & (((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - .dataa(\z80_|address_latch_|abusz [8]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|bus_control_|db[6]~9_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|alu_control_|db[6]~20_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .combout(\z80_|alu_control_|db[6]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h30B0; +defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N27 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~20 ( +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( // Equation(s): -// \z80_|address_pins_|abus[8]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_control_|db[6]~22_combout = ((\z80_|alu_control_|db[6]~21_combout & ((\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [8]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|alu_control_|db[6]~11_combout ), + .datab(\z80_|alu_control_|db[6]~21_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~20_combout ), + .combout(\z80_|alu_control_|db[6]~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[8]~20 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[8]~20 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hD5DD; +defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Location: LCCOMB_X39_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) +// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - .dataa(gnd), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hF0F3; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0028; -defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2400; -defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & -// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N1 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~20_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~20 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|keys[1][1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~21 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~21_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~21 .lut_mask = 16'h3000; -defparam \ula_|zx_keyboard_|keys[6][4]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~21_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~23_combout = (\ula_|zx_keyboard_|keys[1][1]~20_combout & ((\ula_|zx_keyboard_|keys[1][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~22_combout & ((\ula_|zx_keyboard_|keys[1][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[1][1]~20_combout & (((\ula_|zx_keyboard_|keys[1][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[1][1]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~23 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[1][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y14_N7 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~23_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N0 -cycloneive_lcell_comb \D[1]~24 ( -// Equation(s): -// \D[1]~24_combout = (\z80_|address_pins_|abus[9]~19_combout & ((\z80_|address_pins_|abus[8]~20_combout ) # ((!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\z80_|address_pins_|abus[9]~19_combout & (!\ula_|zx_keyboard_|keys[1][1]~q & -// ((\z80_|address_pins_|abus[8]~20_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~19_combout ), - .datab(\z80_|address_pins_|abus[8]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[1][1]~q ), - .cin(gnd), - .combout(\D[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~24 .lut_mask = 16'h8ACF; -defparam \D[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N4 -cycloneive_lcell_comb \D[1]~28 ( -// Equation(s): -// \D[1]~28_combout = (\D[1]~27_combout & (\D[1]~25_combout & (\D[1]~26_combout & \D[1]~24_combout ))) - - .dataa(\D[1]~27_combout ), - .datab(\D[1]~25_combout ), - .datac(\D[1]~26_combout ), - .datad(\D[1]~24_combout ), - .cin(gnd), - .combout(\D[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~28 .lut_mask = 16'h8000; -defparam \D[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y14_N0 -cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( -// Equation(s): -// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; -defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y14_N1 -dffeas \z80_|clk_delay_|DFF_inst5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|DFF_inst5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y14_N26 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y14_N27 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; -// synopsys translate_on - -// Location: FF_X52_Y14_N5 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = ((!\z80_|execute_|ctl_mRead~38_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'h337F; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_iorw~12_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_iorw~12_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), + .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hC800; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Location: LCCOMB_X34_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( // Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~13_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~6_combout ) +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) - .dataa(\z80_|execute_|nextM~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[3]~21_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h00CC; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N25 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( +// Location: FF_X34_Y10_N9 +dffeas \z80_|interrupts_|im1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(\z80_|execute_|ctl_im_we~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .q(\z80_|interrupts_|im1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( +// Location: LCCOMB_X32_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( // Equation(s): -// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|interrupts_|im1~q ), + .datac(\z80_|interrupts_|im2~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hDC00; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h40EE; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( +// Equation(s): +// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hFF31; +defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), + .combout(\z80_|bus_control_|db[6]~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N13 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N8 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Location: LCCOMB_X37_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( // Equation(s): -// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q +// \z80_|execute_|ctl_mRead~37_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .combout(\z80_|execute_|ctl_mRead~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N9 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X50_Y16_N3 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N2 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Location: LCCOMB_X37_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( // Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) +// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~37_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .dataa(\z80_|execute_|ctl_mRead~37_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), + .combout(\z80_|execute_|ctl_mRead~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N4 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Location: LCCOMB_X37_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( // Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ctl_mRead~28_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) - .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), - .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), + .dataa(\z80_|execute_|ctl_mRead~28_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .combout(\z80_|execute_|ctl_mRead~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( -// Equation(s): -// \z80_|execute_|setM1~38_combout = (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|fMRead~4_combout & !\z80_|pla_decode_|Equal9~1_combout )) - - .dataa(\z80_|pla_decode_|Equal29~0_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0404; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~57 ( -// Equation(s): -// \z80_|execute_|setM1~57_combout = (!\z80_|execute_|ctl_mRead~16_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~57 .lut_mask = 16'h00EF; -defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~57_combout & (\z80_|execute_|setM1~37_combout & !\z80_|execute_|ctl_mRead~18_combout ))) - - .dataa(\z80_|execute_|setM1~38_combout ), - .datab(\z80_|execute_|setM1~57_combout ), - .datac(\z80_|execute_|setM1~37_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & ((!\z80_|execute_|setM1~39_combout ) # (!\z80_|execute_|ctl_mRead~21_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_mRead~21_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h1050; -defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~35_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~14_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hEEAA; -defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~40 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~40_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal38~2_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~40 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_mRead~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~39 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~39_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~38_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~39 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_mRead~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N0 +// Location: LCCOMB_X35_Y16_N28 cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( // Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~27_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )))) +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~29_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_mRead~27_combout ), + .dataa(\z80_|execute_|ctl_mRead~29_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'h0080; defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Location: LCCOMB_X38_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( // Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~40_combout & (\z80_|execute_|ctl_mRead~26_combout & (\z80_|execute_|ctl_mRead~39_combout & \z80_|execute_|ctl_mRead~30_combout ))) +// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|ctl_al_we~4_combout & \z80_|execute_|ctl_inc_cy~41_combout ))) - .dataa(\z80_|execute_|ctl_mRead~40_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_mRead~39_combout ), - .datad(\z80_|execute_|ctl_mRead~30_combout ), + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|execute_|ctl_inc_cy~41_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), + .combout(\z80_|execute_|setM1~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~37 .lut_mask = 16'h1000; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Location: LCCOMB_X40_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( // Equation(s): -// \z80_|execute_|nextM~4_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) +// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'h3233; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (!\z80_|execute_|ctl_mRead~16_combout & (\z80_|execute_|setM1~37_combout & (\z80_|execute_|setM1~55_combout & \z80_|execute_|setM1~36_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|setM1~37_combout ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|execute_|setM1~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'h4000; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|setM1~38_combout ))) + + .dataa(\z80_|execute_|setM1~38_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|nextM~3 ( +// Equation(s): +// \z80_|execute_|nextM~3_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) .dataa(gnd), .datab(\z80_|pla_decode_|Equal41~2_combout ), .datac(\z80_|execute_|ixy_d~10_combout ), .datad(\z80_|execute_|ixy_d~16_combout ), .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), + .combout(\z80_|execute_|nextM~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0003; +defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Location: LCCOMB_X40_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( // Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|nextM~4_combout ))) +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|nextM~4_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|ctl_mRead~32_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFC0; defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( +// Location: LCCOMB_X43_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( // Equation(s): -// \z80_|execute_|ctl_mRead~37_combout = (\z80_|execute_|ctl_mRead~36_combout ) # ((\z80_|execute_|ctl_mRead~35_combout ) # ((\z80_|execute_|ctl_mRead~33_combout ) # (!\z80_|execute_|ctl_mRead~31_combout ))) +// \z80_|execute_|ctl_mRead~35_combout = ((\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (\z80_|execute_|ctl_mRead~33_combout ))) # (!\z80_|execute_|ctl_mRead~30_combout ) - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ctl_mRead~35_combout ), + .dataa(\z80_|execute_|ctl_mRead~30_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), .datac(\z80_|execute_|ctl_mRead~31_combout ), .datad(\z80_|execute_|ctl_mRead~33_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~37_combout ), + .combout(\z80_|execute_|ctl_mRead~35_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X49_Y16_N15 +// Location: FF_X43_Y17_N23 dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~37_combout ), + .d(\z80_|execute_|ctl_mRead~35_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -39563,7 +36182,7 @@ defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N22 +// Location: LCCOMB_X46_Y15_N24 cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( // Equation(s): // \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q @@ -39580,7 +36199,7 @@ defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N23 +// Location: FF_X46_Y15_N25 dffeas \z80_|memory_ifc_|wait_mrd ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), @@ -39599,7 +36218,7 @@ defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; // synopsys translate_on -// Location: FF_X50_Y16_N15 +// Location: FF_X43_Y17_N3 dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -39618,28 +36237,151 @@ defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N26 +// Location: LCCOMB_X43_Y17_N8 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( // Equation(s): // \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) .dataa(\z80_|memory_ifc_|wait_mrd~q ), .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datad(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nRD_out~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0505; +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N7 -dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( +// Location: LCCOMB_X40_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout ) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|nextM~4_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ctl_iorw~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N7 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_iorw~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( +// Equation(s): +// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N27 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y17_N9 +dffeas \z80_|memory_ifc_|wait_iorq ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|execute_|setM1~52_combout ), + .asdata(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), @@ -39647,6 +36389,129 @@ dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y17_N13 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|wait_iorq~q ), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hA800; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|fIORead~1_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFF2; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Equation(s): +// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hA080; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|fIOWrite~1_combout ), + .datab(\z80_|execute_|fIORead~2_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|fIORead~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X41_Y17_N25 +dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|setM1~52_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), .prn(vcc)); // synopsys translate_off @@ -39654,7 +36519,7 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N30 +// Location: LCCOMB_X43_Y17_N14 cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( // Equation(s): // \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q @@ -39671,7 +36536,7 @@ defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N31 +// Location: FF_X43_Y17_N15 dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), @@ -39690,7 +36555,7 @@ defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; // synopsys translate_on -// Location: FF_X50_Y16_N17 +// Location: FF_X43_Y17_N21 dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -39709,139 +36574,817 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N16 +// Location: LCCOMB_X43_Y17_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( // Equation(s): -// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & (((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|interrupts_|DFFE_inst44~q ))) # (!\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & -// (\z80_|memory_ifc_|DFFE_m1_ff3~q & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|interrupts_|DFFE_inst44~q )))) +// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|DFFE_inst44~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|DFFE_inst44~q & +// ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - .dataa(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), + .dataa(\z80_|interrupts_|DFFE_inst44~q ), + .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nRD_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFA32; +defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFC54; defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N20 +// Location: LCCOMB_X43_Y17_N18 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( // Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) +// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) .dataa(\z80_|memory_ifc_|nRD_out~1_combout ), - .datab(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|memory_ifc_|iorq~0_combout ), .datac(\z80_|execute_|fIORead~3_combout ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nRD_out~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFDDD; +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFFD5; defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N4 -cycloneive_lcell_comb \Equal2~0 ( +// Location: LCCOMB_X31_Y12_N24 +cycloneive_lcell_comb \Equal2~1 ( // Equation(s): -// \Equal2~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) +// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) - .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), .datab(\z80_|memory_ifc_|nRD_out~2_combout ), .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .datad(gnd), .cin(gnd), - .combout(\Equal2~0_combout ), + .combout(\Equal2~1_combout ), .cout()); // synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h0080; -defparam \Equal2~0 .sum_lutc_input = "datac"; +defparam \Equal2~1 .lut_mask = 16'h4040; +defparam \Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y13_N21 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N12 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~0 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram1|altsyncram_component|auto_generated|address_reg_a [0] +// \z80_|pin_control_|bus_db_pin_oe~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~0 .lut_mask = 16'hFFAA; +defparam \z80_|pin_control_|bus_db_pin_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3F33; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) + + .dataa(\z80_|execute_|fMWrite~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'h5554; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( +// Equation(s): +// \z80_|execute_|fMWrite~2_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h555F; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fMWrite~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h00EF; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~1 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~1_combout = (\z80_|execute_|ctl_bus_inc_oe~24_combout & (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|fMWrite~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .datab(\z80_|execute_|fIOWrite~5_combout ), + .datac(\z80_|execute_|fMWrite~6_combout ), + .datad(\z80_|execute_|fMWrite~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~1 .lut_mask = 16'h0002; +defparam \z80_|pin_control_|bus_db_pin_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'h135F; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|pin_control_|bus_db_pin_oe~2_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'hA2AA; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_mRead~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'h0003; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~7_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|fMWrite~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hCD00; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h0777; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|fMRead~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout )) # +// (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|fMRead~1_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h3715; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~9 ( +// Equation(s): +// \z80_|execute_|fMWrite~9_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout )) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal46~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~9 .lut_mask = 16'hCEFF; +defparam \z80_|execute_|fMWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & +// (((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fMWrite~9_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hDDD0; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|execute_|fMWrite~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout )) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datab(\z80_|execute_|fMWrite~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0808; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_state_alu~6_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & (\z80_|execute_|ctl_reg_sel_wz~5_combout & (!\z80_|execute_|fMWrite~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~5_combout ), + .datac(\z80_|execute_|fMWrite~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h0800; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~7_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~5_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|fMWrite~10 ( +// Equation(s): +// \z80_|execute_|fMWrite~10_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & +// ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~10 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & (!\z80_|execute_|fMWrite~10_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .datac(\z80_|execute_|fMWrite~10_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h0800; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2A00; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~1_combout & (\z80_|pin_control_|bus_db_pin_oe~12_combout & \z80_|execute_|ctl_inc_cy~37_combout ))) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout ))) # +// (!\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|fIOWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'hF222; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y15_N0 +cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( +// Equation(s): +// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; +defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y13_N13 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( +// Location: FF_X43_Y15_N1 +dffeas \z80_|clk_delay_|DFF_inst5 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .q(\z80_|clk_delay_|DFF_inst5~q ), .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \ExtRamWE~0 ( +// Location: LCCOMB_X43_Y15_N22 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( // Equation(s): -// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|memory_ifc_|nIORQ_out~0_combout & !\z80_|memory_ifc_|nRD_out~2_combout ))) +// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|clk_delay_|DFF_inst5~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y15_N23 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y15_N13 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y15_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datad(\z80_|memory_ifc_|iorq~0_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nIORQ_out~0_combout ))) .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datad(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h4000; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), .cin(gnd), .combout(\ExtRamWE~0_combout ), .cout()); // synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h0008; +defparam \ExtRamWE~0 .lut_mask = 16'h0020; defparam \ExtRamWE~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N10 +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [13]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0B0B; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~2_combout = (((\z80_|execute_|fMRead~35_combout ) # (\z80_|execute_|fIORead~3_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .datac(\z80_|execute_|fMRead~35_combout ), + .datad(\z80_|execute_|fIORead~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFF7; +defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pin_control_|bus_ab_pin_we~2_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T3_ff~q & +// (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h3B0A; +defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [14]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N4 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [15]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[15]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hF3F3; +defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N8 cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), .cin(gnd), .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .cout()); @@ -39850,24 +37393,41 @@ defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_m defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N8 +// Location: LCCOMB_X32_Y14_N22 cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) .dataa(gnd), .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), .cin(gnd), .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h0C00; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00C0; defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N8 +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) @@ -39884,7 +37444,7 @@ defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hDD88; defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N9 +// Location: FF_X31_Y17_N29 dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), @@ -39903,41 +37463,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N4 +// Location: LCCOMB_X31_Y18_N20 cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( // Equation(s): // \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(gnd), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [1]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [1]), .cin(gnd), .combout(\z80_|address_pins_|abus[1]~25_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hFF55; defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N8 +// Location: LCCOMB_X31_Y17_N18 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [2]))) +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [2]), .datac(gnd), - .datad(\z80_|address_latch_|abusz [2]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N9 +// Location: FF_X31_Y17_N19 dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), @@ -39956,7 +37516,7 @@ defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N16 +// Location: LCCOMB_X31_Y18_N26 cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( // Equation(s): // \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) @@ -39973,24 +37533,24 @@ defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N30 +// Location: LCCOMB_X31_Y17_N0 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) - .dataa(\z80_|address_latch_|abusz [3]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [3]), .datac(gnd), .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N31 +// Location: FF_X31_Y17_N1 dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), @@ -40009,41 +37569,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y2_N22 +// Location: LCCOMB_X31_Y18_N12 cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( // Equation(s): // \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\z80_|address_pins_|DFFE_apin_latch [3]), .cin(gnd), .combout(\z80_|address_pins_|abus[3]~27_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N4 +// Location: LCCOMB_X31_Y17_N30 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) - .dataa(\z80_|address_latch_|abusz [4]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [4]), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N5 +// Location: FF_X31_Y17_N31 dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), @@ -40062,41 +37622,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y3_N22 +// Location: LCCOMB_X31_Y18_N2 cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( // Equation(s): // \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [4]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [4]), .cin(gnd), .combout(\z80_|address_pins_|abus[4]~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N12 +// Location: LCCOMB_X30_Y16_N12 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - .dataa(\z80_|address_latch_|abusz [5]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [5]), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y13_N13 +// Location: FF_X30_Y16_N13 dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), @@ -40115,41 +37675,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N10 +// Location: LCCOMB_X29_Y17_N20 cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( // Equation(s): // \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|address_pins_|DFFE_apin_latch [5]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(gnd), .cin(gnd), .combout(\z80_|address_pins_|abus[5]~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF3F3; defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N6 +// Location: LCCOMB_X30_Y16_N10 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [6]), + .dataa(\z80_|address_latch_|abusz [6]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hCCAA; defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N7 +// Location: FF_X30_Y16_N11 dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), @@ -40168,41 +37728,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N8 +// Location: LCCOMB_X31_Y18_N28 cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( // Equation(s): // \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [6]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [6]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|address_pins_|abus[6]~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N22 +// Location: LCCOMB_X30_Y16_N30 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - .dataa(\z80_|address_latch_|abusz [7]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [7]), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y13_N23 +// Location: FF_X30_Y16_N31 dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), @@ -40221,2261 +37781,289 @@ defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N24 +// Location: LCCOMB_X31_Y18_N22 cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( // Equation(s): // \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\z80_|address_pins_|DFFE_apin_latch [7]), .cin(gnd), .combout(\z80_|address_pins_|abus[7]~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y29_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X29_Y14_N27 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~16_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N23 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (!\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), + .dataa(\z80_|address_latch_|abusz [8]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0400; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N21 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [8]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [14] & !\z80_|address_pins_|DFFE_apin_latch [13])) +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: FF_X31_Y16_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N30 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (!\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h4000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [14] & !\z80_|address_pins_|DFFE_apin_latch [13])) +// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .combout(\z80_|address_pins_|abus[9]~17_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h00C0; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N16 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout & -// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEA4A; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & !\z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N20 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datab(\z80_|address_latch_|abusz [10]), .datac(gnd), - .datad(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), - .combout(\~GND~combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), .cout()); // synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y30_N2 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) - - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0028; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N21 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y30_N25 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N2 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h00FF; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N3 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N0 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [7] $ (\ula_|video_|vga_hc [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N1 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N30 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [7]))) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'hA555; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N31 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N8 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N10 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N12 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N14 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N15 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N16 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N17 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N18 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N19 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N20 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N28 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFC30; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y30_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( -// Equation(s): -// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) - - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[9]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0028; -defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N29 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N22 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [8]), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N26 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|Add4~2_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hF3C0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N27 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N2 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [0]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h1020; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|Add4~4_combout ), - .datab(\ula_|video_|vram_address[10]~2_combout ), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hB830; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y31_N29 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N4 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N5 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N6 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|Add4~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFCFC; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N7 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y20_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X30_Y13_N27 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y13_N9 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: M9K_X33_Y9_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (!\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & !\z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0040; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y29_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \Selector1~0 ( -// Equation(s): -// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~16_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\Selector1~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~0 .lut_mask = 16'hBA98; -defparam \Selector1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \Selector1~1 ( -// Equation(s): -// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\Selector1~0_combout ), - .cin(gnd), - .combout(\Selector1~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~1 .lut_mask = 16'hBBC0; -defparam \Selector1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \D[1]~22 ( -// Equation(s): -// \D[1]~22_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector1~1_combout ))))) - - .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .datad(\Selector1~1_combout ), - .cin(gnd), - .combout(\D[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~22 .lut_mask = 16'h5140; -defparam \D[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \D[1]~23 ( -// Equation(s): -// \D[1]~23_combout = ((\z80_|memory_ifc_|nWR_out~0_combout ) # ((\D[1]~22_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[1]~22_combout ), - .cin(gnd), - .combout(\D[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~23 .lut_mask = 16'hFFDF; -defparam \D[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \D[1]~29 ( -// Equation(s): -// \D[1]~29_combout = (\D[1]~23_combout ) # ((\Equal2~0_combout & ((\z80_|address_pins_|abus[0]~18_combout ) # (\D[1]~28_combout )))) - - .dataa(\z80_|address_pins_|abus[0]~18_combout ), - .datab(\D[1]~28_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[1]~23_combout ), - .cin(gnd), - .combout(\D[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~29 .lut_mask = 16'hFFE0; -defparam \D[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \D[1]~31 ( -// Equation(s): -// \D[1]~31_combout = ((\D[1]~29_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\D[0]~30_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\D[1]~29_combout ), - .cin(gnd), - .combout(\D[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'hF755; -defparam \D[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N6 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[1]~31_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[1]~13_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[1]~13_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[1]~13_combout ), - .datad(\D[1]~31_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N8 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T3_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hAE0C; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N22 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .datad(\z80_|execute_|fMRead~36_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFEFA; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N7 -dffeas \z80_|data_pins_|dout[1] ( +// Location: FF_X31_Y16_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .asdata(vcc), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [1]), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[1] .power_up = "low"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~12 ( +// Location: LCCOMB_X30_Y20_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( // Equation(s): -// \z80_|bus_control_|db[1]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~12 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h0203; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( -// Equation(s): -// \z80_|bus_control_|db[0]~6_combout = ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (\z80_|execute_|ctl_bus_db_oe~combout )) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFFF5; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~13 ( -// Equation(s): -// \z80_|bus_control_|db[1]~13_combout = ((\z80_|bus_control_|db[1]~12_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [1]), - .datab(\z80_|bus_control_|db[1]~12_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~13 .lut_mask = 16'h8FCF; -defparam \z80_|bus_control_|db[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~5_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hFB33; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N17 -dffeas \z80_|ir_|opcode[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[1]~13_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y15_N29 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N20 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) +// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), + .combout(\z80_|address_pins_|abus[10]~24_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFF0; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y15_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( // Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [0]))) +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [0]), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datab(\z80_|address_latch_|abusz [11]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal36~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal36~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal36~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hAE0C; -defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y15_N27 -dffeas \z80_|decode_state_|DFFE_instCB ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), +// Location: FF_X31_Y16_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instCB~q ), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), .prn(vcc)); // synopsys translate_off -defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y15_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Location: LCCOMB_X30_Y20_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( // Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0004; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|pla_decode_|Equal50~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q ))) # (!\z80_|pla_decode_|Equal50~0_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & -// !\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal33~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0357; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mRead~9_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_mRead~9_combout & -// (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~11_combout & (\z80_|execute_|ctl_mWrite~9_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mWrite~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~11_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~3_combout & (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_bus_db_oe~6_combout & \z80_|execute_|ctl_mWrite~12_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_mWrite~14_combout ) # (((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~14_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hDCFF; -defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X50_Y16_N29 -dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~15_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N18 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q - - .dataa(gnd), + .dataa(\z80_|address_pins_|DFFE_apin_latch [11]), .datab(gnd), .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .combout(\z80_|address_pins_|abus[11]~19_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N19 -dffeas \z80_|memory_ifc_|wait_mwr ( +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) + + .dataa(\z80_|address_latch_|abusz [12]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mwr~q ), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N0 -cycloneive_lcell_comb \z80_|memory_ifc_|mwr_wr~feeder ( +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( // Equation(s): -// \z80_|memory_ifc_|mwr_wr~feeder_combout = \z80_|memory_ifc_|wait_mwr~q +// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(gnd), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mwr~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [12]), .cin(gnd), - .combout(\z80_|memory_ifc_|mwr_wr~feeder_combout ), + .combout(\z80_|address_pins_|abus[12]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|mwr_wr~feeder .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N1 -dffeas \z80_|memory_ifc_|mwr_wr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|mwr_wr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|mwr_wr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N4 -cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~4_combout & \z80_|memory_ifc_|iorq~0_combout )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|mwr_wr~q ), - .datac(\z80_|execute_|fIOWrite~4_combout ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nWR_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hFCCC; -defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N30 -cycloneive_lcell_comb \D[0]~30 ( -// Equation(s): -// \D[0]~30_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cin(gnd), - .combout(\D[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~30 .lut_mask = 16'hFF40; -defparam \D[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 +// Location: M9K_X33_Y11_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -42483,7 +38071,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .ena1(vcc), @@ -42491,10 +38079,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -42532,26 +38120,1177 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), - .cout()); +// Location: FF_X32_Y14_N31 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[13]~20_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hE6C4; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y16_N0 +// Location: FF_X32_Y14_N1 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0200; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: FF_X29_Y14_N5 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0C00; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \D[6]~90 ( +// Equation(s): +// \D[6]~90_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\D[6]~90_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~90 .lut_mask = 16'hCCE2; +defparam \D[6]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N16 +cycloneive_lcell_comb \D[6]~91 ( +// Equation(s): +// \D[6]~91_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~90_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~90_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~90_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[6]~90_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\D[6]~91_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~91 .lut_mask = 16'hF838; +defparam \D[6]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0020; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y24_N16 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N20 +cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [4]), + .cin(gnd), + .combout(\ula_|video_|vram_address[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N4 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N21 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y33_N19 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N0 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N1 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N26 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N27 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N28 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'hA50F; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N29 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N2 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N4 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N6 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N8 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y33_N9 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N10 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y33_N11 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N12 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y33_N13 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N14 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N22 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) + + .dataa(gnd), + .datab(\ula_|video_|Add4~12_combout ), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hCCF0; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N14 +cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( +// Equation(s): +// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N23 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N16 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [8]), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) + + .dataa(\ula_|video_|Add4~14_combout ), + .datab(gnd), + .datac(\ula_|video_|Add4~2_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hAAF0; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N21 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N30 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & (\ula_|video_|vga_hc [1]))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|Add4~4_combout ), + .datab(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|vram_address[10]~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N31 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) + + .dataa(gnd), + .datab(\ula_|video_|Add4~12_combout ), + .datac(gnd), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFCC; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N17 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N26 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|Add4~14_combout ) # (\ula_|video_|vga_hc [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|Add4~14_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N27 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N23 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y14_N1 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -42561,16 +39300,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -42624,7 +39363,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y13_N0 +// Location: M9K_X33_Y33_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(vcc), .portare(vcc), @@ -42634,16 +39373,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -42682,7 +39421,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; // synopsys translate_on -// Location: M9K_X33_Y13_N0 +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \D[6]~87 ( +// Equation(s): +// \D[6]~87_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\D[6]~87_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~87 .lut_mask = 16'hE6A2; +defparam \D[6]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y1_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portawe(vcc), .portare(vcc), @@ -42692,16 +39449,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -42740,3739 +39497,175 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; // synopsys translate_on -// Location: M9K_X33_Y17_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \Selector6~0 ( -// Equation(s): -// \Selector6~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector6~0 .lut_mask = 16'hAEA4; -defparam \Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N0 -cycloneive_lcell_comb \D[6]~70 ( -// Equation(s): -// \D[6]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector6~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\Selector6~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector6~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datad(\Selector6~0_combout ), - .cin(gnd), - .combout(\D[6]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~70 .lut_mask = 16'hBBC0; -defparam \D[6]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \D[6]~71 ( -// Equation(s): -// \D[6]~71_combout = ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\D[6]~70_combout )))) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\z80_|memory_ifc_|nRD_out~2_combout ), - .datad(\D[6]~70_combout ), - .cin(gnd), - .combout(\D[6]~71_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~71 .lut_mask = 16'hBF8F; -defparam \D[6]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G19 -cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2]}), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk )); -// synopsys translate_off -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock"; -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~77_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[3]~21_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[3]~21_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\D[3]~77_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N11 -dffeas \z80_|data_pins_|dout[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~64 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~64_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~64 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[5][4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~101_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[5][4]~64_combout & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~101_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~101 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[3][3]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~102 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~102_combout = (\ula_|zx_keyboard_|keys[3][3]~101_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~101_combout & (\ula_|zx_keyboard_|keys[3][3]~q )) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~101_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~102_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~102 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[3][3]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N3 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~102_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'hCCCF; -defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~104 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~104_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~104 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[2][3]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~135 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~135_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[2][3]~104_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[2][3]~104_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~135_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~135 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[2][3]~135 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~105_combout = (\ula_|zx_keyboard_|keys[2][3]~135_combout & (!\ula_|zx_keyboard_|keys[2][3]~103_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~135_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~135_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~105 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N17 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~105_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \D[3]~55 ( -// Equation(s): -// \D[3]~55_combout = (\z80_|address_pins_|abus[11]~21_combout & (((\z80_|address_pins_|abus[10]~22_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~21_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~22_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~21_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~q ), - .datac(\z80_|address_pins_|abus[10]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[2][3]~q ), - .cin(gnd), - .combout(\D[3]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~55 .lut_mask = 16'hB0BB; -defparam \D[3]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~21_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~95_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][3]~94_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~95 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[1][3]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~96_combout = (\ula_|zx_keyboard_|keys[1][3]~95_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][3]~95_combout & ((\ula_|zx_keyboard_|keys[1][3]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|keys[1][3]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~96_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~96 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[1][3]~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N9 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~96_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~97 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~97_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~97 .lut_mask = 16'hAAEE; -defparam \ula_|zx_keyboard_|keys[2][4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~99_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [6])))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~99_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~99 .lut_mask = 16'h0220; -defparam \ula_|zx_keyboard_|keys[0][4]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~100 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~100_combout = (\ula_|zx_keyboard_|keys[0][3]~98_combout & ((\ula_|zx_keyboard_|keys[0][4]~99_combout & (!\ula_|zx_keyboard_|keys[2][4]~97_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~99_combout & -// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][3]~98_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~99_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~100 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N31 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~100_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \D[3]~54 ( -// Equation(s): -// \D[3]~54_combout = (\z80_|address_pins_|abus[8]~20_combout & (((\z80_|address_pins_|abus[9]~19_combout )) # (!\ula_|zx_keyboard_|keys[1][3]~q ))) # (!\z80_|address_pins_|abus[8]~20_combout & (!\ula_|zx_keyboard_|keys[0][3]~q & -// ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[1][3]~q ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\z80_|address_pins_|abus[9]~19_combout ), - .cin(gnd), - .combout(\D[3]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~54 .lut_mask = 16'hAF23; -defparam \D[3]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~79_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[3][0]~79_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~136 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~136_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), - .datab(\ula_|zx_keyboard_|Selector5~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~136_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~136 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~136 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~109 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~109_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~108_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~136_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[4][3]~136_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~108_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~109_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~109 .lut_mask = 16'hEA40; -defparam \ula_|zx_keyboard_|keys[4][3]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~137 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~137_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~137_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~137 .lut_mask = 16'hFF02; -defparam \ula_|zx_keyboard_|keys[4][3]~137 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~110 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~110_combout = (\ula_|zx_keyboard_|keys[4][3]~109_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|zx_keyboard_|keys[4][3]~137_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & -// ((\ula_|zx_keyboard_|keys[4][3]~q ))))) # (!\ula_|zx_keyboard_|keys[4][3]~109_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~109_combout ), - .datab(\ula_|zx_keyboard_|keys[4][3]~137_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~110_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~110 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][3]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N19 -dffeas \ula_|zx_keyboard_|keys[4][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][3]~110_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~106 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~106_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~106 .lut_mask = 16'h00C0; -defparam \ula_|zx_keyboard_|keys[5][3]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~107 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~107_combout = (\ula_|zx_keyboard_|keys[1][4]~25_combout & ((\ula_|zx_keyboard_|keys[5][3]~106_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][3]~106_combout & ((\ula_|zx_keyboard_|keys[5][3]~q -// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|keys[5][3]~106_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~107_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~107 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][3]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y14_N17 -dffeas \ula_|zx_keyboard_|keys[5][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~107_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N26 -cycloneive_lcell_comb \D[3]~56 ( -// Equation(s): -// \D[3]~56_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][3]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[5][3]~q ), - .cin(gnd), - .combout(\D[3]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~56 .lut_mask = 16'h8ACF; -defparam \D[3]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~115 ( +cycloneive_lcell_comb \D[6]~88 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~115_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) +// \D[6]~88_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~87_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~87_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~87_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~115_combout ), + .combout(\D[6]~88_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~115 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][3]~115 .sum_lutc_input = "datac"; +defparam \D[6]~88 .lut_mask = 16'h22D8; +defparam \D[6]~88 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~116 ( +cycloneive_lcell_comb \D[6]~89 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~116_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~115_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[7][2]~32_combout & ((\ula_|ps2_keyboard_|shiftreg [2])))) +// \D[6]~89_combout = (\D[6]~87_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~88_combout )))) # (!\D[6]~87_combout & +// (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \D[6]~88_combout )))) - .dataa(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datab(\ula_|zx_keyboard_|keys[6][3]~115_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\D[6]~87_combout ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\D[6]~88_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~116_combout ), + .combout(\D[6]~89_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~116 .lut_mask = 16'hCCA0; -defparam \ula_|zx_keyboard_|keys[6][3]~116 .sum_lutc_input = "datac"; +defparam \D[6]~89 .lut_mask = 16'hC3C8; +defparam \D[6]~89 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~139 ( +cycloneive_lcell_comb \D[6]~111 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~139_combout = (((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout )) # (!\ula_|zx_keyboard_|keys[6][3]~116_combout ) +// \D[6]~111_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[6]~91_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[6]~89_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[6]~91_combout )) - .dataa(\ula_|zx_keyboard_|keys[6][3]~116_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), + .dataa(\D[6]~91_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\D[6]~89_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~139_combout ), + .combout(\D[6]~111_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~139 .lut_mask = 16'hFF7F; -defparam \ula_|zx_keyboard_|keys[6][3]~139 .sum_lutc_input = "datac"; +defparam \D[6]~111 .lut_mask = 16'hAEA2; +defparam \D[6]~111 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(gnd), +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \D[6]~86 ( +// Equation(s): +// \D[6]~86_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(gnd), + .datac(\raw_loader_in~input_o ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector13~0_combout ), + .combout(\D[6]~86_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hF2F2; -defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; +defparam \D[6]~86 .lut_mask = 16'hFAFF; +defparam \D[6]~86 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~140 ( +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \D[6]~100 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~140_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~139_combout & (\ula_|zx_keyboard_|keys[6][3]~q )) # (!\ula_|zx_keyboard_|keys[6][3]~139_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout -// ))))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) +// \D[6]~100_combout = ((\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout ))) # (!\Equal2~1_combout ) - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[6][3]~139_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), + .dataa(\Equal2~1_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[6]~111_combout ), + .datad(\D[6]~86_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~140_combout ), + .combout(\D[6]~100_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~140 .lut_mask = 16'hD0F2; -defparam \ula_|zx_keyboard_|keys[6][3]~140 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N9 -dffeas \ula_|zx_keyboard_|keys[6][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~140_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFCF0; -defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h00CC; -defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~62_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hF080; -defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; +defparam \D[6]~100 .lut_mask = 16'hFD75; +defparam \D[6]~100 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( +cycloneive_lcell_comb \D[6]~101 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & ((\ula_|zx_keyboard_|keys[7][3]~q ))) +// \D[6]~101_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [6] & \D[6]~100_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[6]~100_combout )) # (!\Equal2~1_combout ))) - .dataa(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [6]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[6]~100_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .combout(\D[6]~101_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; +defparam \D[6]~101 .lut_mask = 16'hCF05; +defparam \D[6]~101 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N5 -dffeas \ula_|zx_keyboard_|keys[7][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N16 -cycloneive_lcell_comb \D[3]~57 ( -// Equation(s): -// \D[3]~57_combout = (\ula_|zx_keyboard_|keys[6][3]~q & (\z80_|address_pins_|abus[14]~16_combout & ((\z80_|address_pins_|abus[15]~17_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~q & -// (((\z80_|address_pins_|abus[15]~17_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[6][3]~q ), - .datab(\ula_|zx_keyboard_|keys[7][3]~q ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\D[3]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~57 .lut_mask = 16'hF531; -defparam \D[3]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N16 -cycloneive_lcell_comb \D[3]~58 ( -// Equation(s): -// \D[3]~58_combout = (\D[3]~55_combout & (\D[3]~54_combout & (\D[3]~56_combout & \D[3]~57_combout ))) - - .dataa(\D[3]~55_combout ), - .datab(\D[3]~54_combout ), - .datac(\D[3]~56_combout ), - .datad(\D[3]~57_combout ), - .cin(gnd), - .combout(\D[3]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~58 .lut_mask = 16'h8000; -defparam \D[3]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y31_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hBBC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; -// synopsys translate_on - -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; -// synopsys translate_on - -// Location: M9K_X33_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N18 -cycloneive_lcell_comb \Selector3~0 ( -// Equation(s): -// \Selector3~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector3~0 .lut_mask = 16'hCEC2; -defparam \Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N12 -cycloneive_lcell_comb \Selector3~1 ( -// Equation(s): -// \Selector3~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\Selector3~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector3~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\Selector3~0_combout ), - .cin(gnd), - .combout(\Selector3~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector3~1 .lut_mask = 16'hBBC0; -defparam \Selector3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N6 -cycloneive_lcell_comb \D[3]~52 ( -// Equation(s): -// \D[3]~52_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector3~1_combout ))))) - - .dataa(\z80_|address_pins_|abus[15]~17_combout ), - .datab(\Equal2~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), - .datad(\Selector3~1_combout ), - .cin(gnd), - .combout(\D[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~52 .lut_mask = 16'h3120; -defparam \D[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N20 -cycloneive_lcell_comb \D[3]~53 ( -// Equation(s): -// \D[3]~53_combout = (\z80_|memory_ifc_|nWR_out~0_combout ) # (((\D[3]~52_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|memory_ifc_|nRD_out~2_combout )) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~52_combout ), - .cin(gnd), - .combout(\D[3]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~53 .lut_mask = 16'hFFBF; -defparam \D[3]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N10 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\D[3]~53_combout ) # ((\Equal2~0_combout & ((\z80_|address_pins_|abus[0]~18_combout ) # (\D[3]~58_combout )))) - - .dataa(\z80_|address_pins_|abus[0]~18_combout ), - .datab(\D[3]~58_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[3]~53_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'hFFE0; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N24 -cycloneive_lcell_comb \D[3]~77 ( -// Equation(s): -// \D[3]~77_combout = ((\D[3]~76_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\z80_|data_pins_|dout [3]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[0]~30_combout ), - .datad(\D[3]~76_combout ), - .cin(gnd), - .combout(\D[3]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~77 .lut_mask = 16'hBF0F; -defparam \D[3]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N0 -cycloneive_lcell_comb \ula_|always0~0 ( -// Equation(s): -// \ula_|always0~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [0])) - - .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|always0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|always0~0 .lut_mask = 16'h0808; -defparam \ula_|always0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N2 -cycloneive_lcell_comb \ula_|always0~1 ( -// Equation(s): -// \ula_|always0~1_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|always0~0_combout ), - .cin(gnd), - .combout(\ula_|always0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|always0~1 .lut_mask = 16'h2000; -defparam \ula_|always0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y15_N25 -dffeas \ula_|pcm_outl[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[3]~77_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|pcm_outl [13]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y17_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|mclk_r~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y17_N5 -dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|mclk_r~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) - - .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add0~1_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; -defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) -// \ula_|i2s_intf_|Add0~3 = CARRY((!\ula_|i2s_intf_|lrdivider [1] & !\ula_|i2s_intf_|Add0~1_cout )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~1_cout ), - .combout(\ula_|i2s_intf_|Add0~2_combout ), - .cout(\ula_|i2s_intf_|Add0~3 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add0~2_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N29 -dffeas \ula_|i2s_intf_|lrdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) -// \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) - - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~3 ), - .combout(\ula_|i2s_intf_|Add0~4_combout ), - .cout(\ula_|i2s_intf_|Add0~5 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~4_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N5 -dffeas \ula_|i2s_intf_|lrdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) -// \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~5 ), - .combout(\ula_|i2s_intf_|Add0~6_combout ), - .cout(\ula_|i2s_intf_|Add0~7 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; -defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~6_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; -defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y15_N1 -dffeas \ula_|i2s_intf_|lrdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) -// \ula_|i2s_intf_|Add0~9 = CARRY((\ula_|i2s_intf_|lrdivider [4]) # (!\ula_|i2s_intf_|Add0~7 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~7 ), - .combout(\ula_|i2s_intf_|Add0~8_combout ), - .cout(\ula_|i2s_intf_|Add0~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; -defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N25 -dffeas \ula_|i2s_intf_|lrdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) -// \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) - - .dataa(\ula_|i2s_intf_|lrdivider [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~9 ), - .combout(\ula_|i2s_intf_|Add0~10_combout ), - .cout(\ula_|i2s_intf_|Add0~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; -defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[5]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y16_N17 -dffeas \ula_|i2s_intf_|lrdivider[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) -// \ula_|i2s_intf_|Add0~13 = CARRY((!\ula_|i2s_intf_|Add0~11 ) # (!\ula_|i2s_intf_|lrdivider [6])) - - .dataa(\ula_|i2s_intf_|lrdivider [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~11 ), - .combout(\ula_|i2s_intf_|Add0~12_combout ), - .cout(\ula_|i2s_intf_|Add0~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~12_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[6]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y16_N15 -dffeas \ula_|i2s_intf_|lrdivider[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) -// \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) - - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~13 ), - .combout(\ula_|i2s_intf_|Add0~14_combout ), - .cout(\ula_|i2s_intf_|Add0~15 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; -defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y16_N1 -dffeas \ula_|i2s_intf_|lrdivider[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) -// \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [8]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~15 ), - .combout(\ula_|i2s_intf_|Add0~16_combout ), - .cout(\ula_|i2s_intf_|Add0~17 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add0~16_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N25 -dffeas \ula_|i2s_intf_|lrdivider[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrdivider [9]), - .cin(\ula_|i2s_intf_|Add0~17 ), - .combout(\ula_|i2s_intf_|Add0~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; -defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~18_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; -defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N21 -dffeas \ula_|i2s_intf_|lrdivider[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|lrdivider [8]))) - - .dataa(\ula_|i2s_intf_|lrdivider [6]), - .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [7]), - .datad(\ula_|i2s_intf_|lrdivider [8]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0080; -defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( -// Equation(s): -// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|lrdivider [4]))) - - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(\ula_|i2s_intf_|lrdivider [3]), - .datac(\ula_|i2s_intf_|lrdivider [5]), - .datad(\ula_|i2s_intf_|lrdivider [4]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h0080; -defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( -// Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~0_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~1_combout ))) - - .dataa(\ula_|i2s_intf_|Equal0~0_combout ), - .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; -defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] -// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .cout(\ula_|i2s_intf_|bitcount[0]~6 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; -defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(\ula_|i2s_intf_|bitcount [2]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h33C3; -defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add2~7_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0033; -defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) -// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~7_cout ), - .combout(\ula_|i2s_intf_|Add2~8_combout ), - .cout(\ula_|i2s_intf_|Add2~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (\ula_|i2s_intf_|Add2~8_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|Add2~8_combout ), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h020A; -defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N25 -dffeas \ula_|i2s_intf_|bdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) -// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) - - .dataa(\ula_|i2s_intf_|bdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~9 ), - .combout(\ula_|i2s_intf_|Add2~10_combout ), - .cout(\ula_|i2s_intf_|Add2~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[8]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|Add2~10_combout ), - .datac(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h000B; -defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N13 -dffeas \ula_|i2s_intf_|bdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) -// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - - .dataa(\ula_|i2s_intf_|bdivider [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~11 ), - .combout(\ula_|i2s_intf_|Add2~12_combout ), - .cout(\ula_|i2s_intf_|Add2~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|Add2~12_combout ), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h020A; -defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N27 -dffeas \ula_|i2s_intf_|bdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~19_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(\ula_|i2s_intf_|Add2~13 ), - .combout(\ula_|i2s_intf_|Add2~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; -defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[8]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .datad(\ula_|i2s_intf_|Add2~14_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N11 -dffeas \ula_|i2s_intf_|bdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (\ula_|i2s_intf_|bdivider [4] & (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & \ula_|i2s_intf_|bdivider [2]))) - - .dataa(\ula_|i2s_intf_|bdivider [4]), - .datab(\ula_|i2s_intf_|bdivider [1]), - .datac(\ula_|i2s_intf_|bdivider [3]), - .datad(\ula_|i2s_intf_|bdivider [2]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0200; -defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[8]~1 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[8]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bitcount [4]), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(\ula_|i2s_intf_|LessThan0~0_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8]~1 .lut_mask = 16'hC400; -defparam \ula_|i2s_intf_|shiftreg[8]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[8]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .datac(\ula_|i2s_intf_|bdivider [0]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; -defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N29 -dffeas \ula_|i2s_intf_|bdivider[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; -defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) - - .dataa(\ula_|i2s_intf_|bclk_r~0_combout ), - .datab(\ula_|i2s_intf_|Equal1~1_combout ), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00B8; -defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bclk_r~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N15 -dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[8]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hAFAA; -defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N1 -dffeas \ula_|i2s_intf_|bitcount[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) -// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[0]~6 ), - .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .cout(\ula_|i2s_intf_|bitcount[1]~8 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N3 -dffeas \ula_|i2s_intf_|bitcount[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) -// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[1]~8 ), - .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .cout(\ula_|i2s_intf_|bitcount[2]~10 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N5 -dffeas \ula_|i2s_intf_|bitcount[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) -// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[2]~10 ), - .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .cout(\ula_|i2s_intf_|bitcount[3]~12 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N7 -dffeas \ula_|i2s_intf_|bitcount[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [4]), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2s_intf_|bitcount[3]~12 ), - .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; -defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N9 -dffeas \ula_|i2s_intf_|bitcount[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~19_combout = (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & (\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bitcount [4]), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|Equal1~1_combout ), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h3010; -defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X23_Y34_N22 -cycloneive_io_ibuf \AUD_ADCDAT~input ( - .i(AUD_ADCDAT), - .ibar(gnd), - .o(\AUD_ADCDAT~input_o )); -// synopsys translate_off -defparam \AUD_ADCDAT~input .bus_hold = "false"; -defparam \AUD_ADCDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) - - .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [0]), - .datad(\AUD_ADCDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; -defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N3 -dffeas \ula_|i2s_intf_|shiftreg[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[8]~2 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[8]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[8]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8]~2 .lut_mask = 16'hFAAA; -defparam \ula_|i2s_intf_|shiftreg[8]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N1 -dffeas \ula_|i2s_intf_|shiftreg[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N19 -dffeas \ula_|i2s_intf_|shiftreg[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N29 -dffeas \ula_|i2s_intf_|shiftreg[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N27 -dffeas \ula_|i2s_intf_|shiftreg[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~15_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(\ula_|i2s_intf_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0A0A; -defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N21 -dffeas \ula_|i2s_intf_|shiftreg[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~14_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N15 -dffeas \ula_|i2s_intf_|shiftreg[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~13_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [6]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N25 -dffeas \ula_|i2s_intf_|shiftreg[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~11_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [7]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N11 -dffeas \ula_|i2s_intf_|shiftreg[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~11_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [8]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N9 -dffeas \ula_|i2s_intf_|shiftreg[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~10_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [9]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N31 -dffeas \ula_|i2s_intf_|shiftreg[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~9_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(\ula_|i2s_intf_|shiftreg [10]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0A0A; -defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N13 -dffeas \ula_|i2s_intf_|shiftreg[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~8_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~7_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [11]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [11]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N23 -dffeas \ula_|i2s_intf_|shiftreg[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~7_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; -defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N21 -dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( -// Equation(s): -// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|PCM_INR [14])))) # -// (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (((\ula_|i2s_intf_|PCM_INR [14])))) - - .dataa(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|shiftreg [14]), - .cin(gnd), - .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hF870; -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N19 -dffeas \ula_|i2s_intf_|PCM_INR[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|PCM_INR [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \ula_|ula_data~0 ( -// Equation(s): -// \ula_|ula_data~0_combout = (\ula_|i2s_intf_|PCM_INL [14]) # (\ula_|i2s_intf_|PCM_INR [14]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|PCM_INR [14]), - .cin(gnd), - .combout(\ula_|ula_data~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ula_data~0 .lut_mask = 16'hFFF0; -defparam \ula_|ula_data~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N3 -dffeas \ula_|pcm_outl[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ula_data~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|pcm_outl [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) - - .dataa(\ula_|i2s_intf_|shiftreg [12]), - .datab(\ula_|pcm_outl [12]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hCACA; -defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N17 -dffeas \ula_|i2s_intf_|shiftreg[13] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [13]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) - - .dataa(\ula_|pcm_outl [13]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [13]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hB8B8; -defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N9 -dffeas \ula_|i2s_intf_|shiftreg[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( -// Equation(s): -// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) - - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N5 -dffeas \ula_|i2s_intf_|PCM_INL[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|PCM_INL [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \D[6]~72 ( -// Equation(s): -// \D[6]~72_combout = (!\z80_|address_pins_|abus[0]~18_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (!\ula_|i2s_intf_|PCM_INL [14] & !\ula_|i2s_intf_|PCM_INR [14]))) - - .dataa(\z80_|address_pins_|abus[0]~18_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|PCM_INR [14]), - .cin(gnd), - .combout(\D[6]~72_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~72 .lut_mask = 16'h0004; -defparam \D[6]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \D[6]~73 ( -// Equation(s): -// \D[6]~73_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Equal2~0_combout & ((\D[6]~72_combout ))) # (!\Equal2~0_combout & (!\D[6]~71_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\Equal2~0_combout ), - .datac(\D[6]~71_combout ), - .datad(\D[6]~72_combout ), - .cin(gnd), - .combout(\D[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~73 .lut_mask = 16'h8A02; -defparam \D[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \D[6]~74 ( -// Equation(s): -// \D[6]~74_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (((\z80_|data_pins_|dout [6])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) # (!\z80_|memory_ifc_|nWR_out~0_combout & (!\D[6]~73_combout & ((\z80_|data_pins_|dout [6]) # -// (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\D[6]~73_combout ), - .cin(gnd), - .combout(\D[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~74 .lut_mask = 16'hA2F3; -defparam \D[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 -cycloneive_lcell_comb \D[6]~81 ( -// Equation(s): -// \D[6]~81_combout = (\D[6]~74_combout ) # (!\D[0]~30_combout ) - - .dataa(\D[0]~30_combout ), - .datab(\D[6]~74_combout ), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\D[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~81 .lut_mask = 16'hDDDD; -defparam \D[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 +// Location: LCCOMB_X32_Y13_N12 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~81_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~7_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[6]~7_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~101_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & +// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[6]~7_combout ), - .datad(\D[6]~81_combout ), + .datab(\D[6]~101_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[6]~9_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N1 +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # +// ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|fIORead~3_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|fIORead~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hDC50; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|execute_|fMRead~35_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N13 dffeas \z80_|data_pins_|dout[6] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), @@ -46491,44 +39684,61 @@ defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~5 ( +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( // Equation(s): -// \z80_|bus_control_|db[6]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|db[6]~15_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~5 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[6]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~7 ( -// Equation(s): -// \z80_|bus_control_|db[6]~7_combout = ((\z80_|bus_control_|db[6]~5_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(\z80_|bus_control_|db[6]~8_combout ), .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[6]~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[6]~7_combout ), + .combout(\z80_|bus_control_|db[6]~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[6]~7 .lut_mask = 16'hDF0F; -defparam \z80_|bus_control_|db[6]~7 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'h8AFF; +defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N19 +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~9_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[6]~9_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N9 dffeas \z80_|ir_|opcode[6] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[6]~7_combout ), + .d(\z80_|ir_|opcode[6]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -46544,3371 +39754,239 @@ defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y15_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( +// Location: LCCOMB_X37_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( // Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), + .combout(\z80_|pla_decode_|Equal41~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h4400; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Location: LCCOMB_X38_Y16_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( // Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) +// \z80_|pla_decode_|Equal41~1_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [5]))) - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), + .combout(\z80_|pla_decode_|Equal41~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Location: LCCOMB_X38_Y16_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( // Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) +// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_sw_1d~8_combout ), + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal41~1_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .combout(\z80_|pla_decode_|Equal41~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X40_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( // Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_2d~9_combout & \z80_|execute_|ctl_sw_1d~4_combout ))) +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal41~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_1d~5_combout ), - .datac(\z80_|execute_|ctl_sw_2d~9_combout ), - .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFF08; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Location: LCCOMB_X34_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( // Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|execute_|ctl_66_oe~2_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) +// \z80_|alu_|db_high[1]~15_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'h7555; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_high [1]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~23_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~17_combout ))) + + .dataa(\z80_|alu_|db[6]~23_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[4]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[1]~17_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[5]~25_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[1]~17_combout ), + .datac(\z80_|alu_|db[5]~25_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = (\z80_|alu_|db_high[1]~15_combout & (\z80_|alu_|db_high[1]~16_combout & ((\z80_|alu_|db_high[1]~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[1]~15_combout ), + .datab(\z80_|alu_|db_high[1]~16_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[1]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~20 ( +// Equation(s): +// \z80_|alu_|db_high[1]~20_combout = ((\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~20 .lut_mask = 16'hA8FF; +defparam \z80_|alu_|db_high[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[5]~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db[5]~25 ( +// Equation(s): +// \z80_|alu_|db[5]~25_combout = ((\z80_|alu_|db[5]~24_combout & ((\z80_|alu_|db_high[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db_high[1]~20_combout ), + .datab(\z80_|alu_|db[7]~26_combout ), + .datac(\z80_|alu_|db[5]~24_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~25 .lut_mask = 16'hB3F3; +defparam \z80_|alu_|db[5]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N14 +cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Equation(s): +// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7733; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( -// Equation(s): -// \z80_|alu_control_|db[6]~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_flags_oe~2_combout ) # (\z80_|execute_|ctl_66_oe~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_66_oe~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFFC; -defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( -// Equation(s): -// \z80_|alu_control_|db[6]~11_combout = (\z80_|execute_|ctl_sw_1d~7_combout ) # ((\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_reg_out_lo~8_combout ) # (\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|alu_control_|db[6]~10_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFFFE; -defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~20 ( -// Equation(s): -// \z80_|alu_control_|db[2]~20_combout = (\z80_|alu_|db[2]~12_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & (\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_|db[2]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~20 .lut_mask = 16'h7530; -defparam \z80_|alu_control_|db[2]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hF4F0; -defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~21 ( -// Equation(s): -// \z80_|alu_control_|db[2]~21_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[2]~11_combout ), - .datab(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~21 .lut_mask = 16'h08CC; -defparam \z80_|alu_control_|db[2]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~22 ( -// Equation(s): -// \z80_|alu_control_|db[2]~22_combout = ((!\z80_|alu_control_|db[2]~20_combout & (\z80_|alu_control_|db[2]~21_combout & \z80_|alu_control_|db[2]~19_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[2]~20_combout ), - .datac(\z80_|alu_control_|db[2]~21_combout ), - .datad(\z80_|alu_control_|db[2]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~22 .lut_mask = 16'h7555; -defparam \z80_|alu_control_|db[2]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~10 ( -// Equation(s): -// \z80_|bus_control_|db[2]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|db[2]~22_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~10 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h0A0A; -defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~59 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~59_combout = (\ula_|zx_keyboard_|keys[5][2]~58_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][2]~58_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~59_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~59 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][2]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \ula_|zx_keyboard_|keys[5][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~59_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~133_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][2]~60_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~133 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[4][2]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~132_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~132 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][4]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~61 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~61_combout = (\ula_|zx_keyboard_|keys[4][2]~133_combout & ((\ula_|zx_keyboard_|keys[3][4]~132_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~132_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~133_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][2]~133_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~132_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~61 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N23 -dffeas \ula_|zx_keyboard_|keys[4][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~61_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N6 -cycloneive_lcell_comb \D[2]~34 ( -// Equation(s): -// \D[2]~34_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|keys[4][2]~q ), - .cin(gnd), - .combout(\D[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~34 .lut_mask = 16'h8CAF; -defparam \D[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h000C; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~51_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N21 -dffeas \ula_|zx_keyboard_|keys[3][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~55_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~55 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[1][4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~56_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|Equal0~2_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h3000; -defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~57_combout = (\ula_|zx_keyboard_|keys[1][4]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~56_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~56_combout & ((\ula_|zx_keyboard_|keys[2][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~55_combout & (((\ula_|zx_keyboard_|keys[2][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][4]~55_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~57_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~57 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[2][2]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \ula_|zx_keyboard_|keys[2][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~57_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \D[2]~33 ( -// Equation(s): -// \D[2]~33_combout = (\z80_|address_pins_|abus[10]~22_combout & (((\z80_|address_pins_|abus[11]~21_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) # (!\z80_|address_pins_|abus[10]~22_combout & (!\ula_|zx_keyboard_|keys[2][2]~q & -// ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\z80_|address_pins_|abus[10]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[3][2]~q ), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\z80_|address_pins_|abus[11]~21_combout ), - .cin(gnd), - .combout(\D[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~33 .lut_mask = 16'hAF23; -defparam \D[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~48 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~48_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[6][4]~21_combout & \ula_|zx_keyboard_|keys[6][4]~47_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~48 .lut_mask = 16'h4400; -defparam \ula_|zx_keyboard_|keys[1][2]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[1][2]~48_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][2]~48_combout & (\ula_|zx_keyboard_|keys[1][2]~q )) - - .dataa(\ula_|zx_keyboard_|keys[1][2]~48_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h0303; -defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & (\ula_|zx_keyboard_|keys[0][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N1 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N26 -cycloneive_lcell_comb \D[2]~32 ( -// Equation(s): -// \D[2]~32_combout = (\z80_|address_pins_|abus[8]~20_combout & (((\z80_|address_pins_|abus[9]~19_combout )) # (!\ula_|zx_keyboard_|keys[1][2]~q ))) # (!\z80_|address_pins_|abus[8]~20_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & -// ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[1][2]~q ), - .datac(\z80_|address_pins_|abus[9]~19_combout ), - .datad(\ula_|zx_keyboard_|keys[0][2]~q ), - .cin(gnd), - .combout(\D[2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~32 .lut_mask = 16'hA2F3; -defparam \D[2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~63_combout = (\ula_|zx_keyboard_|keys[7][2]~62_combout & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~63 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~65_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~63_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~64_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[7][2]~63_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'hF800; -defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (\ula_|zx_keyboard_|keys[7][2]~65_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~67_combout = (\ula_|zx_keyboard_|keys[7][2]~66_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~66_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][2]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~67 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][2]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N29 -dffeas \ula_|zx_keyboard_|keys[7][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~67_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~68 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~68_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~68_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~68 .lut_mask = 16'hF3F0; -defparam \ula_|zx_keyboard_|keys[5][0]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~70_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~69_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~71_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & ((\ula_|zx_keyboard_|keys[6][2]~70_combout & (!\ula_|zx_keyboard_|keys[5][0]~68_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~70_combout & -// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~41_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~68_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~71 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][2]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N29 -dffeas \ula_|zx_keyboard_|keys[6][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~71_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N30 -cycloneive_lcell_comb \D[2]~35 ( -// Equation(s): -// \D[2]~35_combout = (\ula_|zx_keyboard_|keys[7][2]~q & (\z80_|address_pins_|abus[15]~17_combout & ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~q & -// (((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~q ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(\z80_|address_pins_|abus[14]~16_combout ), - .cin(gnd), - .combout(\D[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~35 .lut_mask = 16'hDD0D; -defparam \D[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \D[2]~36 ( -// Equation(s): -// \D[2]~36_combout = (\D[2]~34_combout & (\D[2]~33_combout & (\D[2]~32_combout & \D[2]~35_combout ))) - - .dataa(\D[2]~34_combout ), - .datab(\D[2]~33_combout ), - .datac(\D[2]~32_combout ), - .datad(\D[2]~35_combout ), - .cin(gnd), - .combout(\D[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~36 .lut_mask = 16'h8000; -defparam \D[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \D[2]~83 ( -// Equation(s): -// \D[2]~83_combout = (\Equal2~0_combout & ((\D[2]~36_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) - - .dataa(\D[2]~36_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[2]~83_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~83 .lut_mask = 16'hFB00; -defparam \D[2]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hF4A4; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y23_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .lut_mask = 16'hEC64; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; -// synopsys translate_on - -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \Selector0~0 ( -// Equation(s): -// \Selector0~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .cin(gnd), - .combout(\Selector0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector0~0 .lut_mask = 16'hCEC2; -defparam \Selector0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \Selector0~1 ( -// Equation(s): -// \Selector0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\Selector0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector0~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datac(\Selector0~0_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\Selector0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector0~1 .lut_mask = 16'hDAD0; -defparam \Selector0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N30 -cycloneive_lcell_comb \D[2]~37 ( -// Equation(s): -// \D[2]~37_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector0~1_combout ))))) - - .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), - .datad(\Selector0~1_combout ), - .cin(gnd), - .combout(\D[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~37 .lut_mask = 16'h5140; -defparam \D[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \D[2]~38 ( -// Equation(s): -// \D[2]~38_combout = (((\D[2]~37_combout ) # (\z80_|memory_ifc_|nWR_out~0_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[2]~37_combout ), - .datad(\z80_|memory_ifc_|nWR_out~0_combout ), - .cin(gnd), - .combout(\D[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~38 .lut_mask = 16'hFFF7; -defparam \D[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \D[2]~39 ( -// Equation(s): -// \D[2]~39_combout = (\D[2]~83_combout & (((\z80_|data_pins_|dout [2])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) # (!\D[2]~83_combout & (\D[2]~38_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) - - .dataa(\D[2]~83_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\D[2]~38_combout ), - .cin(gnd), - .combout(\D[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~39 .lut_mask = 16'hF3A2; -defparam \D[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \D[2]~40 ( -// Equation(s): -// \D[2]~40_combout = (\D[2]~39_combout ) # (!\D[0]~30_combout ) - - .dataa(\D[2]~39_combout ), - .datab(gnd), - .datac(\D[0]~30_combout ), - .datad(gnd), - .cin(gnd), - .combout(\D[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~40 .lut_mask = 16'hAFAF; -defparam \D[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[2]~40_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[2]~11_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~11_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\D[2]~40_combout ), - .datad(\z80_|bus_control_|db[2]~11_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N31 -dffeas \z80_|data_pins_|dout[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~11 ( -// Equation(s): -// \z80_|bus_control_|db[2]~11_combout = ((\z80_|bus_control_|db[2]~10_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[2]~10_combout ), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~11 .lut_mask = 16'hB3BB; -defparam \z80_|bus_control_|db[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N31 -dffeas \z80_|ir_|opcode[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[2]~11_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00AA; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|pla_decode_|Equal3~2_combout & (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal3~2_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N3 -dffeas \z80_|decode_state_|DFFE_instIY1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_inst4~q )) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0404; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (!\z80_|execute_|ctl_bus_db_oe~2_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h33FF; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_bus_db_oe~4_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & ((\z80_|execute_|ctl_bus_db_oe~3_combout ) # ((\z80_|execute_|ctl_bus_db_oe~5_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), .datad(\z80_|execute_|ctl_sw_1d~6_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .combout(\z80_|sw1_|db_down[5]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hEFCC; +defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h2080; -defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~84 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~84_combout = (\ula_|zx_keyboard_|keys[5][0]~83_combout & (!\ula_|zx_keyboard_|keys[5][0]~68_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~83_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[5][0]~68_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~84 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[5][0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N3 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~84_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'hFF50; -defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'h0160; -defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~87_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~85_combout & (!\ula_|zx_keyboard_|keys[4][0]~86_combout )) # (!\ula_|zx_keyboard_|keys[4][0]~85_combout & -// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~87 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N21 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~87_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N14 -cycloneive_lcell_comb \D[0]~45 ( -// Equation(s): -// \D[0]~45_combout = (\ula_|zx_keyboard_|keys[5][0]~q & (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~q ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[4][0]~q ), - .cin(gnd), - .combout(\D[0]~45_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~45 .lut_mask = 16'hC4F5; -defparam \D[0]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~81_combout = (\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][0]~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|zx_keyboard_|released~q )))) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & (((\ula_|zx_keyboard_|keys[2][0]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~81 .lut_mask = 16'hF074; -defparam \ula_|zx_keyboard_|keys[2][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N21 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~81_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~80_combout = (\ula_|zx_keyboard_|keys[3][0]~79_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][0]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][0]~79_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~80 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N31 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N22 -cycloneive_lcell_comb \D[0]~44 ( -// Equation(s): -// \D[0]~44_combout = (\ula_|zx_keyboard_|keys[2][0]~q & (\z80_|address_pins_|abus[10]~22_combout & ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\ula_|zx_keyboard_|keys[2][0]~q & -// (((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[2][0]~q ), - .datab(\z80_|address_pins_|abus[10]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\z80_|address_pins_|abus[11]~21_combout ), - .cin(gnd), - .combout(\D[0]~44_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~44 .lut_mask = 16'hDD0D; -defparam \D[0]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~134 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~134_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[3][0]~79_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~134_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~134 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[7][0]~134 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h000F; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|WideOr16~3_combout & (\ula_|zx_keyboard_|keys[5][4]~64_combout & !\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|WideOr16~3_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & ((\ula_|zx_keyboard_|keys[7][0]~134_combout ) # (\ula_|zx_keyboard_|keys[7][0]~88_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[7][0]~134_combout ), - .datac(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'hA800; -defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~90 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~90_combout = (\ula_|zx_keyboard_|keys[7][0]~89_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~89_combout & ((\ula_|zx_keyboard_|keys[7][0]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~90_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~90 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[7][0]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N31 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~90_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0C0C; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|shifted~1_combout & \ula_|zx_keyboard_|keys[6][0]~91_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datac(\ula_|zx_keyboard_|shifted~1_combout ), - .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~93_combout = (\ula_|zx_keyboard_|keys[6][0]~92_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][0]~92_combout & (\ula_|zx_keyboard_|keys[6][0]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~93 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N15 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~93_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \D[0]~46 ( -// Equation(s): -// \D[0]~46_combout = (\ula_|zx_keyboard_|keys[7][0]~q & (\z80_|address_pins_|abus[15]~17_combout & ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][0]~q )))) # (!\ula_|zx_keyboard_|keys[7][0]~q & -// ((\z80_|address_pins_|abus[14]~16_combout ) # ((!\ula_|zx_keyboard_|keys[6][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~q ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\D[0]~46_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~46 .lut_mask = 16'hCF45; -defparam \D[0]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg -// [1] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8180; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~77_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~77 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~74_combout = (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~74 .lut_mask = 16'h8888; -defparam \ula_|zx_keyboard_|keys[4][3]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// ((\ula_|ps2_keyboard_|shiftreg [2]))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0510; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~75_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~21_combout )) # (!\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .datac(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~75 .lut_mask = 16'h0F77; -defparam \ula_|zx_keyboard_|keys~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~76_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~74_combout & !\ula_|zx_keyboard_|keys~75_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~74_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|keys~75_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~76 .lut_mask = 16'h30B0; -defparam \ula_|zx_keyboard_|keys[0][0]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~78 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~78_combout = (\ula_|zx_keyboard_|keys~77_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~77_combout & ((\ula_|zx_keyboard_|keys[0][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[0][0]~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys~77_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~76_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~78_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~78 .lut_mask = 16'hD1F0; -defparam \ula_|zx_keyboard_|keys[0][0]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N7 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~78_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~25_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~73 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~73_combout = (\ula_|zx_keyboard_|keys[1][0]~72_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~72_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~73_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~73 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[1][0]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y14_N11 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~73_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N24 -cycloneive_lcell_comb \D[0]~43 ( -// Equation(s): -// \D[0]~43_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~20_combout & ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & -// (((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), - .datab(\z80_|address_pins_|abus[8]~20_combout ), - .datac(\z80_|address_pins_|abus[9]~19_combout ), - .datad(\ula_|zx_keyboard_|keys[1][0]~q ), - .cin(gnd), - .combout(\D[0]~43_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~43 .lut_mask = 16'hD0DD; -defparam \D[0]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \D[0]~47 ( -// Equation(s): -// \D[0]~47_combout = (\D[0]~45_combout & (\D[0]~44_combout & (\D[0]~46_combout & \D[0]~43_combout ))) - - .dataa(\D[0]~45_combout ), - .datab(\D[0]~44_combout ), - .datac(\D[0]~46_combout ), - .datad(\D[0]~43_combout ), - .cin(gnd), - .combout(\D[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~47 .lut_mask = 16'h8000; -defparam \D[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .lut_mask = 16'hF588; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \Selector2~0 ( -// Equation(s): -// \Selector2~0_combout = (\z80_|address_pins_|abus[14]~16_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector2~0 .lut_mask = 16'hBA98; -defparam \Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \Selector2~1 ( -// Equation(s): -// \Selector2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector2~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\Selector2~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector2~0_combout )))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datad(\Selector2~0_combout ), - .cin(gnd), - .combout(\Selector2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector2~1 .lut_mask = 16'hF388; -defparam \Selector2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \D[0]~41 ( -// Equation(s): -// \D[0]~41_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector2~1_combout ))))) - - .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), - .datad(\Selector2~1_combout ), - .cin(gnd), - .combout(\D[0]~41_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~41 .lut_mask = 16'h5140; -defparam \D[0]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \D[0]~42 ( -// Equation(s): -// \D[0]~42_combout = ((\z80_|memory_ifc_|nWR_out~0_combout ) # ((\D[0]~41_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[0]~41_combout ), - .cin(gnd), - .combout(\D[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~42 .lut_mask = 16'hFFDF; -defparam \D[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N18 -cycloneive_lcell_comb \D[0]~48 ( -// Equation(s): -// \D[0]~48_combout = (\D[0]~42_combout ) # ((\Equal2~0_combout & ((\D[0]~47_combout ) # (\z80_|address_pins_|abus[0]~18_combout )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|address_pins_|abus[0]~18_combout ), - .datac(\D[0]~42_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~48 .lut_mask = 16'hFEF0; -defparam \D[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \D[0]~49 ( -// Equation(s): -// \D[0]~49_combout = ((\D[0]~48_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\D[0]~30_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\D[0]~48_combout ), - .cin(gnd), - .combout(\D[0]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~49 .lut_mask = 16'hF755; -defparam \D[0]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[0]~49_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[0]~15_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[0]~15_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[0]~49_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~15_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N15 -dffeas \z80_|data_pins_|dout[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~14 ( -// Equation(s): -// \z80_|bus_control_|db[0]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(gnd), - .datac(\z80_|data_pins_|dout [0]), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~14 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~15 ( -// Equation(s): -// \z80_|bus_control_|db[0]~15_combout = ((\z80_|bus_control_|db[0]~14_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~14_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~15 .lut_mask = 16'hCF4F; -defparam \z80_|bus_control_|db[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N1 -dffeas \z80_|ir_|opcode[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[0]~15_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hAB00; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mWrite~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # -// (!\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~4_combout & (\z80_|execute_|setM1~56_combout & \z80_|execute_|ctl_sw_2u~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~4_combout ), - .datac(\z80_|execute_|setM1~56_combout ), - .datad(\z80_|execute_|ctl_sw_2u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((\z80_|execute_|ctl_sw_2u~5_combout & !\z80_|execute_|ctl_reg_gp_sel~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h3B00; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N8 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[5]~1_combout = (\z80_|bus_control_|db[5]~17_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|bus_control_|db[5]~17_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|execute_|ctl_sw_1d~6_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[5]~1 .lut_mask = 16'hFBAA; -defparam \z80_|sw1_|db_down[5]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N0 +// Location: LCCOMB_X36_Y11_N22 cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( // Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[5]~29_combout ) # ((\z80_|alu_|db_high[1]~7_combout & \z80_|execute_|ctl_flags_alu~16_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (\z80_|alu_|db_high[1]~7_combout & ((\z80_|execute_|ctl_flags_alu~16_combout )))) +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|alu_control_|db[5]~15_combout +// & (\z80_|alu_|db_high[1]~20_combout & ((\z80_|execute_|ctl_flags_alu~15_combout )))) - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_|db_high[1]~7_combout ), - .datac(\z80_|alu_control_|db[5]~29_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .dataa(\z80_|alu_control_|db[5]~15_combout ), + .datab(\z80_|alu_|db_high[1]~20_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), .cin(gnd), .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), .cout()); @@ -49917,7 +39995,7 @@ defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y15_N1 +// Location: FF_X36_Y11_N23 dffeas \z80_|alu_flags_|flags_yf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), @@ -49936,133 +40014,76 @@ defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; defparam \z80_|alu_flags_|flags_yf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~27 ( +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( // Equation(s): -// \z80_|alu_control_|db[5]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) +// \z80_|alu_control_|db[5]~13_combout = (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|flags_yf~q & (!\z80_|execute_|ctl_flags_oe~2_combout & +// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .dataa(\z80_|alu_flags_|flags_yf~q ), .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|flags_yf~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|out[6]~2_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~27_combout ), + .combout(\z80_|alu_control_|db[5]~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~27 .lut_mask = 16'hFC54; -defparam \z80_|alu_control_|db[5]~27 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hAF8C; +defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~28 ( +// Location: LCCOMB_X34_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( // Equation(s): -// \z80_|alu_control_|db[5]~28_combout = (\z80_|sw1_|db_down[5]~1_combout & (\z80_|alu_control_|db[5]~27_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) +// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|sw1_|db_down[5]~1_combout ), + .dataa(\z80_|sw1_|db_down[5]~0_combout ), + .datab(\z80_|alu_control_|db[5]~13_combout ), .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datad(\z80_|alu_control_|db[5]~27_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~28_combout ), + .combout(\z80_|alu_control_|db[5]~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~28 .lut_mask = 16'hC400; -defparam \z80_|alu_control_|db[5]~28 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; +defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~29 ( +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( // Equation(s): -// \z80_|alu_control_|db[5]~29_combout = ((\z80_|alu_control_|db[5]~28_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) +// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~25_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(\z80_|alu_control_|db[5]~28_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_|db[5]~24_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .dataa(\z80_|alu_control_|db[6]~11_combout ), + .datab(\z80_|alu_|db[5]~25_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[5]~14_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~29_combout ), + .combout(\z80_|alu_control_|db[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~29 .lut_mask = 16'hB3BB; -defparam \z80_|alu_control_|db[5]~29 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hDF55; +defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N28 -cycloneive_lcell_comb \D[5]~68 ( +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \D[0]~107 ( // Equation(s): -// \D[5]~68_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) +// \D[0]~107_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout ))) - .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), .cin(gnd), - .combout(\D[5]~68_combout ), + .combout(\D[0]~107_combout ), .cout()); // synopsys translate_off -defparam \D[5]~68 .lut_mask = 16'h0040; -defparam \D[5]~68 .sum_lutc_input = "datac"; +defparam \D[0]~107 .lut_mask = 16'hFF40; +defparam \D[0]~107 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y11_N0 +// Location: M9K_X22_Y6_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -50070,7 +40091,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), .ena1(vcc), @@ -50078,10 +40099,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50119,7 +40140,7 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y30_N0 +// Location: M9K_X22_Y9_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -50127,7 +40148,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), .ena1(vcc), @@ -50135,10 +40156,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50176,7 +40197,7 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; // synopsys translate_on -// Location: M9K_X33_Y32_N0 +// Location: M9K_X22_Y7_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -50184,7 +40205,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .ena1(vcc), @@ -50192,10 +40213,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50233,103 +40254,102 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Location: LCCOMB_X29_Y10_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hFC22; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hAFC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(vcc), +// Location: M9K_X33_Y23_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y24_N0 +// Location: LCCOMB_X29_Y10_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -50339,16 +40359,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -50402,7 +40422,65 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y6_N0 +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -50412,16 +40490,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50460,7 +40538,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: M9K_X33_Y23_N0 +// Location: M9K_X33_Y29_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), .portare(vcc), @@ -50470,16 +40548,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -50532,104 +40610,104 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N6 +// Location: LCCOMB_X29_Y10_N0 cycloneive_lcell_comb \Mux2~0 ( // Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) +// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .cin(gnd), .combout(\Mux2~0_combout ), .cout()); // synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hCEC2; +defparam \Mux2~0 .lut_mask = 16'hBA98; defparam \Mux2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N12 +// Location: LCCOMB_X29_Y10_N2 cycloneive_lcell_comb \Mux2~1 ( // Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # (!\Mux2~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) +// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), .datad(\Mux2~0_combout ), .cin(gnd), .combout(\Mux2~1_combout ), .cout()); // synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hF588; +defparam \Mux2~1 .lut_mask = 16'hBBC0; defparam \Mux2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N2 -cycloneive_lcell_comb \D[5]~88 ( +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \D[5]~110 ( // Equation(s): -// \D[5]~88_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux2~1_combout ))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )))) +// \D[5]~110_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), .datad(\Mux2~1_combout ), .cin(gnd), - .combout(\D[5]~88_combout ), + .combout(\D[5]~110_combout ), .cout()); // synopsys translate_off -defparam \D[5]~88 .lut_mask = 16'hBA8A; -defparam \D[5]~88 .sum_lutc_input = "datac"; +defparam \D[5]~110 .lut_mask = 16'hAEA2; +defparam \D[5]~110 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N10 -cycloneive_lcell_comb \D[5]~69 ( +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \D[5]~85 ( // Equation(s): -// \D[5]~69_combout = (\D[5]~68_combout & (\D[5]~88_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~68_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) +// \D[5]~85_combout = (\D[5]~84_combout & (\D[5]~110_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout ))) - .dataa(\D[5]~68_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .dataa(\D[5]~84_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), .datac(\z80_|data_pins_|dout [5]), - .datad(\D[5]~88_combout ), + .datad(\D[5]~110_combout ), .cin(gnd), - .combout(\D[5]~69_combout ), + .combout(\D[5]~85_combout ), .cout()); // synopsys translate_off -defparam \D[5]~69 .lut_mask = 16'hF351; -defparam \D[5]~69 .sum_lutc_input = "datac"; +defparam \D[5]~85 .lut_mask = 16'hF351; +defparam \D[5]~85 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N14 -cycloneive_lcell_comb \D[5]~80 ( +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \D[5]~99 ( // Equation(s): -// \D[5]~80_combout = (\D[5]~69_combout ) # (!\D[0]~30_combout ) +// \D[5]~99_combout = (\D[5]~85_combout ) # (!\D[0]~107_combout ) - .dataa(gnd), + .dataa(\D[0]~107_combout ), .datab(gnd), - .datac(\D[0]~30_combout ), - .datad(\D[5]~69_combout ), + .datac(gnd), + .datad(\D[5]~85_combout ), .cin(gnd), - .combout(\D[5]~80_combout ), + .combout(\D[5]~99_combout ), .cout()); // synopsys translate_off -defparam \D[5]~80 .lut_mask = 16'hFF0F; -defparam \D[5]~80 .sum_lutc_input = "datac"; +defparam \D[5]~99 .lut_mask = 16'hFF55; +defparam \D[5]~99 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N22 +// Location: LCCOMB_X32_Y13_N14 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[5]~80_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~17_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[5]~17_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[5]~15_combout ) # ((\D[5]~99_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[5]~99_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[5]~17_combout ), - .datad(\D[5]~80_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[5]~99_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), .cout()); @@ -50638,7 +40716,7 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N23 +// Location: FF_X32_Y13_N15 dffeas \z80_|data_pins_|dout[5] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), @@ -50657,49 +40735,49 @@ defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~16 ( +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( // Equation(s): -// \z80_|bus_control_|db[5]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|bus_control_|db[0]~4_combout ), - .datab(\z80_|data_pins_|dout [5]), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [5]), + .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~16_combout ), + .combout(\z80_|bus_control_|db[5]~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~16 .lut_mask = 16'h88AA; -defparam \z80_|bus_control_|db[5]~16 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF300; +defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~17 ( +// Location: LCCOMB_X34_Y10_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( // Equation(s): -// \z80_|bus_control_|db[5]~17_combout = ((\z80_|bus_control_|db[5]~16_combout & ((\z80_|alu_control_|db[5]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|alu_control_|db[5]~29_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[5]~16_combout ), + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|alu_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[5]~14_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~17_combout ), + .combout(\z80_|bus_control_|db[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~17 .lut_mask = 16'hDF0F; -defparam \z80_|bus_control_|db[5]~17 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hF755; +defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N3 +// Location: FF_X34_Y10_N13 dffeas \z80_|ir_|opcode[5] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[5]~17_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|bus_control_|db[5]~15_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), @@ -50710,642 +40788,513 @@ defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( +// Location: LCCOMB_X37_Y15_N20 +cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( // Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [5])) +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|ir_|opcode [5] & +// ((\z80_|pla_decode_|Equal3~2_combout )))) - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3350; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N21 +dffeas \z80_|decode_state_|DFFE_inst4 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_inst4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N4 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Equation(s): +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), + .combout(\z80_|decode_state_|use_ixiy~combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h2020; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Location: LCCOMB_X34_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( // Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) +// \z80_|execute_|ctl_mRead~23_combout = (!\z80_|decode_state_|use_ixiy~combout & (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sel_wz~7_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~20_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( -// Equation(s): -// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|ctl_ir_we~12_combout ) # (((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|fMWrite~1_combout )) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|fMWrite~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hCFEF; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|fMRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .datab(\z80_|execute_|fMRead~15_combout ), - .datac(\z80_|execute_|fMRead~11_combout ), - .datad(\z80_|execute_|fMRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hAAEF; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( -// Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ctl_mRead~16_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|fMRead~27_combout ) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|fMRead~27_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'h0F8F; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( -// Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), .datad(\z80_|pla_decode_|Equal33~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), + .combout(\z80_|execute_|ctl_mRead~23_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hC800; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( -// Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|fMRead~30_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout ) # (\z80_|execute_|ctl_ir_we~9_combout )))) - - .dataa(\z80_|execute_|fMRead~30_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( -// Equation(s): -// \z80_|execute_|fMRead~29_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|execute_|nextM~6_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|nextM~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( -// Equation(s): -// \z80_|execute_|fMRead~32_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( -// Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~29_combout ) # ((\z80_|execute_|fMRead~32_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ))) - - .dataa(\z80_|execute_|fMRead~31_combout ), - .datab(\z80_|execute_|fMRead~29_combout ), - .datac(\z80_|execute_|fMRead~32_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( -// Equation(s): -// \z80_|execute_|fMRead~37_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~17_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h00A8; -defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N12 +// Location: LCCOMB_X39_Y18_N16 cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( // Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|ctl_mRead~17_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )))) # -// (!\z80_|execute_|ctl_alu_shift_oe~14_combout & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) +// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMWrite~3_combout )) - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|execute_|fMWrite~3_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~34_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFBFF; defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Location: LCCOMB_X41_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( // Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|fMRead~37_combout ) # (!\z80_|execute_|fMRead~34_combout ))) +// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) - .dataa(\z80_|execute_|fMRead~28_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~37_combout ), - .datad(\z80_|execute_|fMRead~34_combout ), + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), + .combout(\z80_|execute_|fMRead~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Location: LCCOMB_X37_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( // Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) +// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), + .combout(\z80_|execute_|fMRead~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC800; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Location: LCCOMB_X37_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( // Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~17_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_mRead~32_combout ))) +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) - .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|fMRead~29_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .datab(\z80_|execute_|fMRead~31_combout ), + .datac(\z80_|execute_|fMRead~30_combout ), + .datad(\z80_|execute_|fMRead~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~53_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datab(\z80_|execute_|ctl_inc_cy~77_combout ), + .datac(\z80_|execute_|ctl_inc_cy~53_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_mRead~23_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~23_combout ), .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), + .combout(\z80_|execute_|fMRead~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( -// Equation(s): -// \z80_|execute_|fMRead~20_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|fMRead~19_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|fMWrite~3_combout ), - .datad(\z80_|execute_|fMRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h0F0E; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N22 +// Location: LCCOMB_X39_Y18_N18 cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( // Equation(s): -// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~7_combout & !\z80_|pla_decode_|Equal6~1_combout ))) +// \z80_|execute_|fMRead~10_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0002; +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0100; defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Location: LCCOMB_X39_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( // Equation(s): -// \z80_|execute_|fMRead~17_combout = (((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~32_combout )) # (!\z80_|execute_|pc_inc_hold~18_combout )) # (!\z80_|execute_|nextM~4_combout ) +// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|pc_inc_hold~28_combout )) - .dataa(\z80_|execute_|nextM~4_combout ), - .datab(\z80_|execute_|pc_inc_hold~18_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|nextM~3_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), + .combout(\z80_|execute_|fMRead~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Location: LCCOMB_X39_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( // Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~17_combout )) # (!\z80_|execute_|fMRead~10_combout ))) - - .dataa(\z80_|execute_|fMRead~10_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( -// Equation(s): -// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~18_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|fMRead~21_combout ))) +// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|fMRead~10_combout ))) .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~21_combout ), - .datac(\z80_|execute_|fMRead~20_combout ), - .datad(\z80_|execute_|fMRead~18_combout ), + .datab(\z80_|execute_|fMRead~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|fMRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hAAA2; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fMRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_mRead~6_combout )))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|fMWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h00FE; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|fMRead~14_combout ), + .datab(\z80_|execute_|fMRead~11_combout ), + .datac(\z80_|execute_|fMRead~13_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Equation(s): +// \z80_|execute_|fMRead~20_combout = (((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~19_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datab(\z80_|execute_|fMRead~19_combout ), + .datac(\z80_|execute_|fMRead~15_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~48 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~48_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~48 .lut_mask = 16'hE0C0; +defparam \z80_|execute_|pc_inc_hold~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( +// Equation(s): +// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_mRead~18_combout & +// ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_mRead~18_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFAC8; defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y14_N8 +// Location: LCCOMB_X38_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|fMRead~2_combout ))) + + .dataa(\z80_|execute_|fMRead~2_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|fMRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N10 cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( // Equation(s): -// \z80_|execute_|fMRead~23_combout = (((\z80_|execute_|fMRead~22_combout ) # (!\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) +// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|pc_inc_hold~48_combout ) # ((\z80_|execute_|fMRead~22_combout ) # (\z80_|execute_|fMRead~21_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|pc_inc_hold~48_combout ), .datac(\z80_|execute_|fMRead~22_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), + .datad(\z80_|execute_|fMRead~21_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~23_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hFFFD; defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_mRead~38_combout ) # ((!\z80_|execute_|fMRead~5_combout ) # (!\z80_|execute_|fMRead~4_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|fMRead~4_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( -// Equation(s): -// \z80_|execute_|fMRead~25_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (((\z80_|execute_|ctl_mRead~20_combout ) # (\z80_|execute_|ctl_mRead~19_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (\z80_|execute_|ctl_ir_we~4_combout & -// ((\z80_|execute_|ctl_mRead~20_combout ) # (\z80_|execute_|ctl_mRead~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~39_combout = (\z80_|execute_|ixy_d~4_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'hF800; -defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N2 +// Location: LCCOMB_X36_Y12_N8 cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( // Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout ))) +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - .dataa(\z80_|execute_|fMRead~24_combout ), - .datab(\z80_|execute_|fMRead~25_combout ), - .datac(\z80_|execute_|pc_inc_hold~39_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hCCEC; defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( +// Location: LCCOMB_X38_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( // Equation(s): -// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~16_combout ) # ((\z80_|execute_|fMRead~35_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~26_combout ))) +// \z80_|execute_|fMRead~25_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|fMRead~24_combout ) - .dataa(\z80_|execute_|fMRead~16_combout ), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|execute_|fMRead~23_combout ), - .datad(\z80_|execute_|fMRead~26_combout ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|fMRead~24_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~36_combout ), + .combout(\z80_|execute_|fMRead~25_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'h2F0F; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y13_N28 +// Location: LCCOMB_X37_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~26_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|execute_|fMRead~3_combout ) + + .dataa(\z80_|execute_|fMRead~26_combout ), + .datab(\z80_|execute_|fMRead~3_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|fMRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~27_combout ))) + + .dataa(\z80_|execute_|fMRead~32_combout ), + .datab(\z80_|execute_|fMRead~20_combout ), + .datac(\z80_|execute_|fMRead~23_combout ), + .datad(\z80_|execute_|fMRead~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Equation(s): +// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|fMRead~0_combout ))) + + .dataa(\z80_|execute_|fMRead~34_combout ), + .datab(\z80_|execute_|fMRead~33_combout ), + .datac(\z80_|execute_|fMRead~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N30 cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( // Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~36_combout & \z80_|sequencer_|DFFE_T2_ff~q )) +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q )) - .dataa(\z80_|execute_|fMRead~36_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .dataa(gnd), + .datab(\z80_|execute_|fMRead~35_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), .cin(gnd), .combout(\z80_|pin_control_|bus_db_pin_re~combout ), .cout()); // synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hEECC; +defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y24_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), .ena1(vcc), @@ -51353,75 +41302,132 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), +// Location: LCCOMB_X32_Y14_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), .ena1(vcc), @@ -51429,68 +41435,125 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N2 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ) # -// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout )) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hBC8C; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC64; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), .portaaddrstall(gnd), @@ -51499,16 +41562,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51516,54 +41579,54 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -51572,56 +41635,56 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; // synopsys translate_on -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -51630,56 +41693,56 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; // synopsys translate_on -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), .portare(vcc), .portaaddrstall(gnd), @@ -51688,16 +41751,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51705,161 +41768,2152 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N0 -cycloneive_lcell_comb \Mux0~0 ( +// Location: LCCOMB_X32_Y18_N0 +cycloneive_lcell_comb \Selector1~0 ( // Equation(s): -// \Mux0~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~16_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~16_combout & -// ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) # (!\z80_|address_pins_|abus[14]~16_combout & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) +// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .cin(gnd), - .combout(\Mux0~0_combout ), + .combout(\Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hDC98; -defparam \Mux0~0 .sum_lutc_input = "datac"; +defparam \Selector1~0 .lut_mask = 16'hBA98; +defparam \Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N18 -cycloneive_lcell_comb \Mux0~1 ( +// Location: LCCOMB_X32_Y18_N2 +cycloneive_lcell_comb \Selector1~1 ( // Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) +// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\Selector1~0_combout ), .cin(gnd), - .combout(\Mux0~1_combout ), + .combout(\Selector1~1_combout ), .cout()); // synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hDDA0; -defparam \Mux0~1 .sum_lutc_input = "datac"; +defparam \Selector1~1 .lut_mask = 16'hBBC0; +defparam \Selector1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N24 -cycloneive_lcell_comb \D[7]~89 ( +// Location: LCCOMB_X32_Y18_N12 +cycloneive_lcell_comb \D[1]~103 ( // Equation(s): -// \D[7]~89_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )))) +// \D[1]~103_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector1~1_combout +// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), - .datad(\Mux0~1_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .datad(\Selector1~1_combout ), .cin(gnd), - .combout(\D[7]~89_combout ), + .combout(\D[1]~103_combout ), .cout()); // synopsys translate_off -defparam \D[7]~89 .lut_mask = 16'hF2D0; -defparam \D[7]~89 .sum_lutc_input = "datac"; +defparam \D[1]~103 .lut_mask = 16'hF2D0; +defparam \D[1]~103 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N8 -cycloneive_lcell_comb \D[7]~75 ( -// Equation(s): -// \D[7]~75_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~89_combout ) # (!\D[5]~68_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[7]~89_combout ) # (!\D[5]~68_combout )))) +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[5]~68_combout ), - .datad(\D[7]~89_combout ), +// Location: CLKCTRL_G5 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), .cin(gnd), - .combout(\D[7]~75_combout ), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), .cout()); // synopsys translate_off -defparam \D[7]~75 .lut_mask = 16'hBB0B; -defparam \D[7]~75 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N16 -cycloneive_lcell_comb \D[7]~82 ( -// Equation(s): -// \D[7]~82_combout = (\D[7]~75_combout ) # (!\D[0]~30_combout ) +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on - .dataa(\D[0]~30_combout ), +// Location: LCCOMB_X20_Y26_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), .datab(gnd), - .datac(\D[7]~75_combout ), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N1 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N7 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N21 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [5] & !\ula_|ps2_keyboard_|clk_filter [4]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [6]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [5]), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N29 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N23 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [3]))) + + .dataa(\ula_|ps2_keyboard_|Equal0~0_combout ), + .datab(\ula_|ps2_keyboard_|clk_filter [2]), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0002; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), .datad(gnd), .cin(gnd), - .combout(\D[7]~82_combout ), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), .cout()); // synopsys translate_off -defparam \D[7]~82 .lut_mask = 16'hF5F5; -defparam \D[7]~82 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Location: FF_X20_Y26_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[7]~82_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[7]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[7]~9_combout ))) +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[7]~9_combout ), - .datad(\D[7]~82_combout ), + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFC30; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N27 -dffeas \z80_|data_pins_|dout[7] ( +// Location: FF_X20_Y26_N27 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0C00; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N5 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N3 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N1 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & +// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N17 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & +// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [3]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N27 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\PS2_DAT~input_o ), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCCC0; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|always1~0_combout ), + .datab(\ula_|ps2_keyboard_|bit_count [0]), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00D0; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N9 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N15 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [8]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N11 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N11 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N25 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N29 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N1 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [1]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|Equal0~0_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF300; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) + + .dataa(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datab(\PS2_DAT~input_o ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N9 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y20_N1 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~15_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & !\ula_|ps2_keyboard_|shiftreg [7])) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0202; +defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[0][0]~15_combout )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q )) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( +// Equation(s): +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|released~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hC8F0; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N19 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y21_N3 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hFF88; +defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0003; +defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[5][1]~38_combout & (!\ula_|zx_keyboard_|keys[5][1]~35_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & +// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N19 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~31_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h00CC; +defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~23_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~23 .lut_mask = 16'h1010; +defparam \ula_|zx_keyboard_|keys[7][1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[7][2]~32_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q +// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), + .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N9 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \D[1]~30 ( +// Equation(s): +// \D[1]~30_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][1]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~30 .lut_mask = 16'hBB0B; +defparam \D[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hA0A0; +defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~24_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00C0; +defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N17 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & \ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h4040; +defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N17 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; +defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0060; +defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2040; +defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & +// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y21_N7 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|scan_code_ready~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~19 .lut_mask = 16'h0100; +defparam \ula_|zx_keyboard_|keys[7][4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~20 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~20 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[6][4]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~21 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~21_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[6][4]~20_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~21 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[1][1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|zx_keyboard_|keys[1][1]~21_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][1]~21_combout & (\ula_|zx_keyboard_|keys[1][1]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[1][1]~21_combout ), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N13 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~22_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N2 +cycloneive_lcell_comb \D[1]~28 ( +// Equation(s): +// \D[1]~28_combout = (\ula_|zx_keyboard_|keys[0][1]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) # (!\ula_|zx_keyboard_|keys[0][1]~q & +// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][1]~q ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\ula_|zx_keyboard_|keys[1][1]~q ), + .cin(gnd), + .combout(\D[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~28 .lut_mask = 16'hD0DD; +defparam \D[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N26 +cycloneive_lcell_comb \D[1]~29 ( +// Equation(s): +// \D[1]~29_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~28_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~q ), + .datab(\ula_|zx_keyboard_|key_row~0_combout ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\D[1]~28_combout ), + .cin(gnd), + .combout(\D[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~29 .lut_mask = 16'hC400; +defparam \D[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~41_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~42_combout )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; +defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & ((!\ula_|zx_keyboard_|keys[6][1]~40_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N25 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~45_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [7]))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [7]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0002; +defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; +defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0044; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0140; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hF022; +defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~5_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|WideOr16~5_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF808; +defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N31 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N20 +cycloneive_lcell_comb \D[1]~31 ( +// Equation(s): +// \D[1]~31_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~q ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\ula_|zx_keyboard_|keys[7][1]~q ), + .cin(gnd), + .combout(\D[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~31 .lut_mask = 16'hB0BB; +defparam \D[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N18 +cycloneive_lcell_comb \D[1]~32 ( +// Equation(s): +// \D[1]~32_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~30_combout & (\D[1]~29_combout & \D[1]~31_combout ))) + + .dataa(\D[1]~30_combout ), + .datab(\z80_|address_pins_|abus[0]~16_combout ), + .datac(\D[1]~29_combout ), + .datad(\D[1]~31_combout ), + .cin(gnd), + .combout(\D[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~32 .lut_mask = 16'hECCC; +defparam \D[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N4 +cycloneive_lcell_comb \D[1]~33 ( +// Equation(s): +// \D[1]~33_combout = ((\Equal2~0_combout & ((\D[1]~32_combout ))) # (!\Equal2~0_combout & (\D[1]~103_combout ))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[1]~103_combout ), + .datad(\D[1]~32_combout ), + .cin(gnd), + .combout(\D[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~33 .lut_mask = 16'hFB73; +defparam \D[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N8 +cycloneive_lcell_comb \D[1]~34 ( +// Equation(s): +// \D[1]~34_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout & \z80_|data_pins_|dout [1])))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[1]~33_combout ), + .datad(\z80_|data_pins_|dout [1]), + .cin(gnd), + .combout(\D[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~34 .lut_mask = 16'hF151; +defparam \D[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[1]~11_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\D[1]~34_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N19 +dffeas \z80_|data_pins_|dout[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -51868,51 +43922,68 @@ dffeas \z80_|data_pins_|dout[7] ( .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [7]), + .q(\z80_|data_pins_|dout [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[7] .power_up = "low"; +defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~8 ( +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( // Equation(s): -// \z80_|bus_control_|db[7]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - .dataa(\z80_|alu_control_|db[7]~18_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\z80_|alu_control_|db[1]~26_combout ), .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~8_combout ), + .combout(\z80_|bus_control_|db[1]~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~8 .lut_mask = 16'hAF00; -defparam \z80_|bus_control_|db[7]~8 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~9 ( +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( // Equation(s): -// \z80_|bus_control_|db[7]~9_combout = ((\z80_|bus_control_|db[7]~8_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|bus_control_|db[7]~8_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|bus_control_|db[1]~10_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~9_combout ), + .combout(\z80_|bus_control_|db[1]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~9 .lut_mask = 16'hB3F3; -defparam \z80_|bus_control_|db[7]~9 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD0FF; +defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N9 -dffeas \z80_|ir_|opcode[7] ( +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|ir_|opcode[1]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[1]~feeder_combout = \z80_|bus_control_|db[1]~11_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[1]~11_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N15 +dffeas \z80_|ir_|opcode[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[7]~9_combout ), + .d(\z80_|ir_|opcode[1]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -51921,666 +43992,2542 @@ dffeas \z80_|ir_|opcode[7] ( .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [7]), + .q(\z80_|ir_|opcode [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[7] .power_up = "low"; +defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y15_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( // Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), + .combout(\z80_|pla_decode_|Equal40~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Location: LCCOMB_X37_Y11_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( // Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0]))) +// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|ir_|opcode [0]), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .combout(\z80_|pla_decode_|Equal21~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y12_N19 -dffeas \z80_|interrupts_|im1 ( +// Location: LCCOMB_X39_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hC080; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~28_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|pla_decode_|Equal64~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h001F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h153F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0088; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h4000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_flags_cf_cpl~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h040C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout = (((!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .lut_mask = 16'h777F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h0F0C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC0E0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAA8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_nf_we~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & !\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ))) + + .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h0008; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h20A0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal10~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hCECC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~20_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFB3; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'h8500; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~21_combout )) + + .dataa(\z80_|alu_|db[7]~21_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[0]~19_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hF0AA; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout +// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h11D8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y9_N31 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0B00; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~14_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout )) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout )) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hF0E4; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout & \z80_|execute_|ctl_alu_op_low~28_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~12_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFF40; +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~19_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (\z80_|execute_|ctl_state_alu~7_combout )))) # (!\z80_|execute_|ctl_state_alu~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_state_alu~15_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h3F3B; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal68~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF32; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~12_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC0CC; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N4 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~9_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( +// Equation(s): +// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~17_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|bus_control_|db[0]~17_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h22A2; +defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N20 +cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( +// Equation(s): +// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~19_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_|db[0]~19_combout ), + .cin(gnd), + .combout(\z80_|sw2_|db_up[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hFF0F; +defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( +// Equation(s): +// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[0]~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|sw2_|db_up[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8A00; +defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( +// Equation(s): +// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[0]~9_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; +defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~67_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~67 .lut_mask = 16'hFF50; +defparam \ula_|zx_keyboard_|keys[5][0]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0420; +defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[5][0]~81_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h2800; +defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), + .datab(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h7474; +defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N11 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~83_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h0160; +defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'hBABA; +defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~84_combout & ((!\ula_|zx_keyboard_|keys[4][0]~85_combout ))) # (!\ula_|zx_keyboard_|keys[4][0]~84_combout & +// (\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N27 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~86_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \D[0]~49 ( +// Equation(s): +// \D[0]~49_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[5][0]~q ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[0]~49_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~49 .lut_mask = 16'hBB0B; +defparam \D[0]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|ps2_keyboard_|shiftreg [6])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & +// (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8810; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~76_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) + + .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~76 .lut_mask = 16'h3313; +defparam \ula_|zx_keyboard_|keys~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~73 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~73_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~73_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~73 .lut_mask = 16'hF000; +defparam \ula_|zx_keyboard_|keys[4][3]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// ((\ula_|ps2_keyboard_|shiftreg [2]))))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0310; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~74_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h353F; +defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~73_combout & !\ula_|zx_keyboard_|keys~74_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~73_combout ), + .datab(\ula_|zx_keyboard_|keys~74_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'h2F00; +defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~77_combout = (\ula_|zx_keyboard_|keys~76_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~75_combout & ((!\ula_|zx_keyboard_|released~q ))) # +// (!\ula_|zx_keyboard_|keys[0][0]~75_combout & (\ula_|zx_keyboard_|keys[0][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys~76_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~77 .lut_mask = 16'hB0F4; +defparam \ula_|zx_keyboard_|keys[0][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N15 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~71_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~71 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[1][0]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|zx_keyboard_|keys[1][0]~71_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][0]~71_combout & (\ula_|zx_keyboard_|keys[1][0]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[1][0]~71_combout ), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N17 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~72_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N30 +cycloneive_lcell_comb \D[0]~47 ( +// Equation(s): +// \D[0]~47_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & +// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\ula_|zx_keyboard_|keys[1][0]~q ), + .cin(gnd), + .combout(\D[0]~47_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~47 .lut_mask = 16'hD0DD; +defparam \D[0]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~80 .lut_mask = 16'hB1F0; +defparam \ula_|zx_keyboard_|keys[2][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N23 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~80_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~78 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|keys[3][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~79_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (\ula_|zx_keyboard_|keys[3][0]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][0]~78_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N5 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~79_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~1_combout = ((\z80_|address_pins_|DFFE_apin_latch [11]) # (!\ula_|zx_keyboard_|keys[3][0]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [11]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hFF3F; +defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N4 +cycloneive_lcell_comb \D[0]~48 ( +// Equation(s): +// \D[0]~48_combout = (\D[0]~47_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) + + .dataa(\D[0]~47_combout ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|key_row~1_combout ), + .cin(gnd), + .combout(\D[0]~48_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~48 .lut_mask = 16'h8A00; +defparam \D[0]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|shifted~1_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[6][0]~90_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|shifted~1_combout ), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|zx_keyboard_|keys[6][0]~91_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~91_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N21 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~92_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~63_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~63 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[5][4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0303; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[5][4]~63_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|WideOr16~3_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~132 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~132_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~132_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~132 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[7][0]~132 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & ((\ula_|zx_keyboard_|keys[7][0]~87_combout ) # (\ula_|zx_keyboard_|keys[7][0]~132_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~132_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h8880; +defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|zx_keyboard_|keys[7][0]~88_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~88_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) + + .dataa(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N7 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~89_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N28 +cycloneive_lcell_comb \D[0]~50 ( +// Equation(s): +// \D[0]~50_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~q ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~q ), + .cin(gnd), + .combout(\D[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~50 .lut_mask = 16'hB0BB; +defparam \D[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N10 +cycloneive_lcell_comb \D[0]~51 ( +// Equation(s): +// \D[0]~51_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~49_combout & (\D[0]~48_combout & \D[0]~50_combout ))) + + .dataa(\D[0]~49_combout ), + .datab(\z80_|address_pins_|abus[0]~16_combout ), + .datac(\D[0]~48_combout ), + .datad(\D[0]~50_combout ), + .cin(gnd), + .combout(\D[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~51 .lut_mask = 16'hECCC; +defparam \D[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N14 +cycloneive_lcell_comb \D[0]~55 ( +// Equation(s): +// \D[0]~55_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\D[0]~55_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~55 .lut_mask = 16'hE3E0; +defparam \D[0]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \D[0]~56 ( +// Equation(s): +// \D[0]~56_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~55_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\D[0]~55_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~55_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[0]~55_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\D[0]~56_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~56 .lut_mask = 16'hBCB0; +defparam \D[0]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \D[0]~52 ( +// Equation(s): +// \D[0]~52_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~23_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\D[0]~52_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~52 .lut_mask = 16'hF858; +defparam \D[0]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \D[0]~53 ( +// Equation(s): +// \D[0]~53_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ ((\D[0]~52_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & (((!\D[0]~52_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\z80_|address_pins_|abus[15]~22_combout ), + .datac(\D[0]~52_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\D[0]~53_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~53 .lut_mask = 16'h4B48; +defparam \D[0]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \D[0]~54 ( +// Equation(s): +// \D[0]~54_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~52_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~52_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~53_combout )) # (!\D[0]~52_combout & ((\D[0]~53_combout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[0]~52_combout ), + .datad(\D[0]~53_combout ), + .cin(gnd), + .combout(\D[0]~54_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~54 .lut_mask = 16'hC3E0; +defparam \D[0]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \D[0]~106 ( +// Equation(s): +// \D[0]~106_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~56_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~54_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[0]~56_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[0]~56_combout ), + .datad(\D[0]~54_combout ), + .cin(gnd), + .combout(\D[0]~106_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~106 .lut_mask = 16'hF4B0; +defparam \D[0]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \D[0]~57 ( +// Equation(s): +// \D[0]~57_combout = ((\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~1_combout ), + .datab(\D[0]~51_combout ), + .datac(\D[0]~106_combout ), + .datad(\Equal2~0_combout ), + .cin(gnd), + .combout(\D[0]~57_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~57 .lut_mask = 16'hDDF5; +defparam \D[0]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \D[0]~58 ( +// Equation(s): +// \D[0]~58_combout = (\D[0]~57_combout & (((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[0]~57_combout & (!\Equal2~1_combout & ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\D[0]~57_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\D[0]~58_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~58 .lut_mask = 16'hC0F5; +defparam \D[0]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~17_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\D[0]~58_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N1 +dffeas \z80_|data_pins_|dout[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Equation(s): +// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|data_pins_|dout [0]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hC0CC; +defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N28 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Equation(s): +// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~16_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF55; +defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y13_N27 +dffeas \z80_|ir_|opcode[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .asdata(\z80_|bus_control_|db[0]~17_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|im2~q ), - .datac(\z80_|interrupts_|im1~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hF400; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h5D50; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hCECF; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( -// Equation(s): -// \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|bus_control_|db[0]~4_combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'h88AA; -defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( -// Equation(s): -// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[3]~20_combout ), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hBB3B; -defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N23 -dffeas \z80_|ir_|opcode[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[3]~21_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [3]), + .q(\z80_|ir_|opcode [0]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[3] .power_up = "low"; +defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( +// Location: LCCOMB_X39_Y16_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( // Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .dataa(\z80_|ir_|opcode [0]), .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~1_combout ), + .combout(\z80_|pla_decode_|Equal63~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N20 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Location: LCCOMB_X40_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( // Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N20 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h070F; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( +// Equation(s): +// \z80_|alu_control_|db[6]~10_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) + + .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFF5; +defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( +// Equation(s): +// \z80_|alu_control_|db[6]~11_combout = (\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_sw_1d~7_combout ) # (\z80_|execute_|ctl_reg_out_lo~8_combout )) + + .dataa(\z80_|alu_control_|db[6]~10_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), + .combout(\z80_|alu_control_|db[6]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h1010; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFEFE; +defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N8 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( // Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|decode_state_|in_halt~q ))) +// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~17_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~17_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - .dataa(\z80_|pla_decode_|Equal77~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|decode_state_|in_halt~0_combout ), + .dataa(\z80_|alu_|db[4]~17_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), .cin(gnd), - .combout(\z80_|decode_state_|in_halt~1_combout ), + .combout(\z80_|alu_control_|db[4]~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hFF08; -defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; +defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y12_N9 -dffeas \z80_|decode_state_|in_halt ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|in_halt~1_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|in_halt~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; -defparam \z80_|decode_state_|in_halt .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal77~0_combout ))) +// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|alu_control_|db[4]~30_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .combout(\z80_|alu_control_|db[4]~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h00B0; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Location: LCCOMB_X32_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) +// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[4]~31_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .combout(\z80_|alu_control_|db[4]~32_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) +// \ula_|zx_keyboard_|keys[2][4]~119_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h0420; +defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Location: LCCOMB_X29_Y18_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = ((\z80_|execute_|ctl_bus_db_we~4_combout ) # ((!\z80_|execute_|ctl_apin_mux~0_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout ))) # (!\z80_|execute_|ctl_bus_db_we~5_combout ) +// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - .dataa(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datac(\z80_|execute_|ctl_sw_2u~3_combout ), - .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datab(\ula_|zx_keyboard_|keys[2][4]~119_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Location: LCCOMB_X29_Y18_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~95 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h2220; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_ir_we~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFE0; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~6_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_db_we~3_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~124_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~124 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[5][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~125 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~125_combout = (\ula_|zx_keyboard_|keys[5][4]~124_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & ((\ula_|zx_keyboard_|keys[5][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][4]~124_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) +// \ula_|zx_keyboard_|keys[2][4]~95_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[5][4]~124_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~125_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~125 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][4]~125 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N17 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~126_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [6])) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|shiftreg -// [6])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(gnd), + .datab(gnd), + .datac(\ula_|zx_keyboard_|shifted~q ), .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~126_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~95_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~126 .lut_mask = 16'h4422; -defparam \ula_|zx_keyboard_|keys[4][4]~126 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~95 .lut_mask = 16'hAFAA; +defparam \ula_|zx_keyboard_|keys[2][4]~95 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~127_combout = (\ula_|zx_keyboard_|keys[4][4]~126_combout & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[4][4]~126_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~127 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~128_combout = (\ula_|zx_keyboard_|keys[4][4]~127_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (\ula_|zx_keyboard_|keys[4][4]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][4]~127_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][4]~127_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~128 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][4]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N23 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~128_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \D[4]~64 ( -// Equation(s): -// \D[4]~64_combout = (\ula_|zx_keyboard_|keys[5][4]~q & (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][4]~q )))) # (!\ula_|zx_keyboard_|keys[5][4]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\D[4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~64 .lut_mask = 16'hCF45; -defparam \D[4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~119_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg -// [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~119 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[3][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~138 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~138_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|keys[3][4]~119_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~138_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~138 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[3][4]~138 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~120 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~120_combout = (\ula_|zx_keyboard_|keys[3][4]~132_combout & ((\ula_|zx_keyboard_|keys[3][4]~138_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][4]~138_combout & -// (\ula_|zx_keyboard_|keys[3][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][4]~132_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][4]~132_combout ), - .datab(\ula_|zx_keyboard_|keys[3][4]~138_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~120_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~120 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][4]~120 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N29 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~120_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 +// Location: LCCOMB_X29_Y18_N22 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~121 ( // Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|zx_keyboard_|keys[2][4]~120_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~120_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\ula_|zx_keyboard_|keys[2][4]~120_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[2][4]~121_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h50FA; defparam \ula_|zx_keyboard_|keys[2][4]~121 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y15_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|zx_keyboard_|keys[2][4]~121_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~122 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[2][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~123_combout = (\ula_|zx_keyboard_|keys[2][4]~122_combout & (!\ula_|zx_keyboard_|keys[2][4]~97_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~122_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[2][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~122_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~123 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N19 +// Location: FF_X29_Y18_N23 dffeas \ula_|zx_keyboard_|keys[2][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~123_combout ), + .d(\ula_|zx_keyboard_|keys[2][4]~121_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52596,46 +46543,80 @@ defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \D[4]~63 ( +// Location: LCCOMB_X29_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( // Equation(s): -// \D[4]~63_combout = (\z80_|address_pins_|abus[10]~22_combout & (((\z80_|address_pins_|abus[11]~21_combout )) # (!\ula_|zx_keyboard_|keys[3][4]~q ))) # (!\z80_|address_pins_|abus[10]~22_combout & (!\ula_|zx_keyboard_|keys[2][4]~q & -// ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][4]~q )))) +// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|extended~q ))) - .dataa(\z80_|address_pins_|abus[10]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[3][4]~q ), - .datac(\z80_|address_pins_|abus[11]~21_combout ), - .datad(\ula_|zx_keyboard_|keys[2][4]~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\D[4]~63_combout ), + .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), .cout()); // synopsys translate_off -defparam \D[4]~63 .lut_mask = 16'hA2F3; -defparam \D[4]~63 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~129 ( +// Location: LCCOMB_X29_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~136 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~129_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) +// \ula_|zx_keyboard_|keys[3][4]~136_combout = (\ula_|zx_keyboard_|keys[3][4]~117_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [4]))) - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .dataa(\ula_|zx_keyboard_|keys[3][4]~117_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~129_combout ), + .combout(\ula_|zx_keyboard_|keys[3][4]~136_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~129 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][4]~129 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][4]~136 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[3][4]~136 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y15_N25 -dffeas \ula_|zx_keyboard_|keys[7][4] ( +// Location: LCCOMB_X28_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~130_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~130 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[3][4]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|zx_keyboard_|keys[3][4]~136_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[3][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~136_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~136_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N9 +dffeas \ula_|zx_keyboard_|keys[3][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~129_combout ), + .d(\ula_|zx_keyboard_|keys[3][4]~118_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52644,52 +46625,124 @@ dffeas \ula_|zx_keyboard_|keys[7][4] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~130 ( +// Location: LCCOMB_X29_Y19_N18 +cycloneive_lcell_comb \D[4]~78 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~130_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) +// \D[4]~78_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~q ), + .cin(gnd), + .combout(\D[4]~78_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~78 .lut_mask = 16'h8ACF; +defparam \D[4]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~126_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~130_combout ), + .combout(\ula_|zx_keyboard_|keys[5][4]~128_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~130 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[6][4]~130 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][4]~128 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[5][4]~128 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~131 ( +// Location: LCCOMB_X28_Y19_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~129 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~131_combout = (\ula_|zx_keyboard_|keys[6][4]~130_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~130_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) +// \ula_|zx_keyboard_|keys[5][4]~129_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[5][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~128_combout & +// (\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[6][4]~130_combout ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~128_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~131_combout ), + .combout(\ula_|zx_keyboard_|keys[5][4]~129_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~131 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[6][4]~131 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][4]~129 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][4]~129 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y14_N31 +// Location: FF_X28_Y19_N9 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~129_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~127_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~20_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~20_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~127 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[6][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N5 dffeas \ula_|zx_keyboard_|keys[6][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~131_combout ), + .d(\ula_|zx_keyboard_|keys[6][4]~127_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52705,46 +46758,257 @@ defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \D[4]~65 ( +// Location: LCCOMB_X28_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( // Equation(s): -// \D[4]~65_combout = (\z80_|address_pins_|abus[15]~17_combout & (((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~17_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & -// ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) +// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - .dataa(\z80_|address_pins_|abus[15]~17_combout ), - .datab(\ula_|zx_keyboard_|keys[7][4]~q ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\ula_|zx_keyboard_|keys[6][4]~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), .cin(gnd), - .combout(\D[4]~65_combout ), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \D[4]~65 .lut_mask = 16'hB0BB; -defparam \D[4]~65 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~118 ( +// Location: LCCOMB_X28_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~118_combout = (\ula_|zx_keyboard_|keys[0][4]~99_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~99_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) +// \ula_|zx_keyboard_|keys[7][4]~51_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - .dataa(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~99_combout ), + .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) +// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~1_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N11 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N30 +cycloneive_lcell_comb \D[4]~79 ( +// Equation(s): +// \D[4]~79_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & +// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .cin(gnd), + .combout(\D[4]~79_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~79 .lut_mask = 16'h8ACF; +defparam \D[4]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & +// \ula_|zx_keyboard_|extended~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h4422; +defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][4]~122_combout ))) + + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N25 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\ula_|zx_keyboard_|keys[4][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [12]), + .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hF3FF; +defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N8 +cycloneive_lcell_comb \D[4]~80 ( +// Equation(s): +// \D[4]~80_combout = (\D[4]~79_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), + .datab(\D[4]~79_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|key_row~3_combout ), + .cin(gnd), + .combout(\D[4]~80_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~80 .lut_mask = 16'hC400; +defparam \D[4]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFAAA; +defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~97_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~97 .lut_mask = 16'h0060; +defparam \ula_|zx_keyboard_|keys[0][4]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~116_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & +// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~111_combout ), .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .datad(\ula_|zx_keyboard_|keys[0][4]~97_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~118_combout ), + .combout(\ula_|zx_keyboard_|keys[0][4]~116_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~118 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[0][4]~118 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[0][4]~116 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][4]~116 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N3 +// Location: FF_X29_Y18_N11 dffeas \ula_|zx_keyboard_|keys[0][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~118_combout ), + .d(\ula_|zx_keyboard_|keys[0][4]~116_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52760,28 +47024,28 @@ defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~117 ( +// Location: LCCOMB_X29_Y19_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~115 ( // Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~117_combout = (\ula_|zx_keyboard_|keys[1][4]~25_combout & ((\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # -// (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) +// \ula_|zx_keyboard_|keys[1][4]~115_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # +// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - .dataa(\ula_|zx_keyboard_|released~q ), + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~117_combout ), + .combout(\ula_|zx_keyboard_|keys[1][4]~115_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~117 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[1][4]~117 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[1][4]~115 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][4]~115 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y14_N3 +// Location: FF_X29_Y19_N7 dffeas \ula_|zx_keyboard_|keys[1][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~117_combout ), + .d(\ula_|zx_keyboard_|keys[1][4]~115_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52797,308 +47061,42 @@ defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N4 -cycloneive_lcell_comb \D[4]~62 ( +// Location: LCCOMB_X29_Y19_N28 +cycloneive_lcell_comb \D[4]~77 ( // Equation(s): -// \D[4]~62_combout = (\ula_|zx_keyboard_|keys[0][4]~q & (\z80_|address_pins_|abus[8]~20_combout & ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][4]~q )))) # (!\ula_|zx_keyboard_|keys[0][4]~q & -// (((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][4]~q )))) +// \D[4]~77_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - .dataa(\ula_|zx_keyboard_|keys[0][4]~q ), - .datab(\z80_|address_pins_|abus[8]~20_combout ), - .datac(\z80_|address_pins_|abus[9]~19_combout ), + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), .datad(\ula_|zx_keyboard_|keys[1][4]~q ), .cin(gnd), - .combout(\D[4]~62_combout ), + .combout(\D[4]~77_combout ), .cout()); // synopsys translate_off -defparam \D[4]~62 .lut_mask = 16'hD0DD; -defparam \D[4]~62 .sum_lutc_input = "datac"; +defparam \D[4]~77 .lut_mask = 16'h8ACF; +defparam \D[4]~77 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \D[4]~66 ( +// Location: LCCOMB_X29_Y19_N26 +cycloneive_lcell_comb \D[4]~81 ( // Equation(s): -// \D[4]~66_combout = (\D[4]~64_combout & (\D[4]~63_combout & (\D[4]~65_combout & \D[4]~62_combout ))) +// \D[4]~81_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~78_combout & (\D[4]~80_combout & \D[4]~77_combout ))) - .dataa(\D[4]~64_combout ), - .datab(\D[4]~63_combout ), - .datac(\D[4]~65_combout ), - .datad(\D[4]~62_combout ), + .dataa(\z80_|address_pins_|abus[0]~16_combout ), + .datab(\D[4]~78_combout ), + .datac(\D[4]~80_combout ), + .datad(\D[4]~77_combout ), .cin(gnd), - .combout(\D[4]~66_combout ), + .combout(\D[4]~81_combout ), .cout()); // synopsys translate_off -defparam \D[4]~66 .lut_mask = 16'h8000; -defparam \D[4]~66 .sum_lutc_input = "datac"; +defparam \D[4]~81 .lut_mask = 16'hEAAA; +defparam \D[4]~81 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y32_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y21_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X23_Y21_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y21_N2 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hF388; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y4_N0 +// Location: M9K_X22_Y1_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portawe(vcc), .portare(vcc), @@ -53108,16 +47106,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -53156,7 +47154,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: M9K_X33_Y28_N0 +// Location: M9K_X22_Y22_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -53166,16 +47164,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -53229,7 +47227,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y12_N0 +// Location: M9K_X33_Y3_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(vcc), .portare(vcc), @@ -53239,16 +47237,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -53287,7 +47285,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: M9K_X33_Y30_N0 +// Location: M9K_X22_Y25_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), .portare(vcc), @@ -53297,16 +47295,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -53359,120 +47357,370 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N12 +// Location: LCCOMB_X29_Y14_N2 cycloneive_lcell_comb \Selector4~0 ( // Equation(s): -// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) +// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), .cin(gnd), .combout(\Selector4~0_combout ), .cout()); // synopsys translate_off -defparam \Selector4~0 .lut_mask = 16'hAEA4; +defparam \Selector4~0 .lut_mask = 16'hBA98; defparam \Selector4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N2 +// Location: LCCOMB_X29_Y14_N26 cycloneive_lcell_comb \Selector4~1 ( // Equation(s): // \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & // (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), .datad(\Selector4~0_combout ), .cin(gnd), .combout(\Selector4~1_combout ), .cout()); // synopsys translate_off -defparam \Selector4~1 .lut_mask = 16'hF588; +defparam \Selector4~1 .lut_mask = 16'hF388; defparam \Selector4~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \D[4]~60 ( +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 ( // Equation(s): -// \D[4]~60_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector4~1_combout ))))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .lut_mask = 16'hE5E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .lut_mask = 16'hAFC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \D[4]~109 ( +// Equation(s): +// \D[4]~109_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Selector4~1_combout +// )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ))))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Selector4~1_combout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), + .cin(gnd), + .combout(\D[4]~109_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~109 .lut_mask = 16'hFB40; +defparam \D[4]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \D[4]~97 ( +// Equation(s): +// \D[4]~97_combout = ((\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout )))) # (!\Equal2~1_combout ) .dataa(\Equal2~0_combout ), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), - .datac(\z80_|address_pins_|abus[15]~17_combout ), - .datad(\Selector4~1_combout ), + .datab(\D[4]~81_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[4]~109_combout ), .cin(gnd), - .combout(\D[4]~60_combout ), + .combout(\D[4]~97_combout ), .cout()); // synopsys translate_off -defparam \D[4]~60 .lut_mask = 16'h4540; -defparam \D[4]~60 .sum_lutc_input = "datac"; +defparam \D[4]~97 .lut_mask = 16'hDF8F; +defparam \D[4]~97 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \D[4]~61 ( +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \D[4]~98 ( // Equation(s): -// \D[4]~61_combout = (((\z80_|memory_ifc_|nWR_out~0_combout ) # (\D[4]~60_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|memory_ifc_|nRD_out~2_combout ) +// \D[4]~98_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~97_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[4]~97_combout ) # (!\Equal2~1_combout )))) - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nWR_out~0_combout ), - .datad(\D[4]~60_combout ), + .dataa(\z80_|data_pins_|dout [4]), + .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[4]~97_combout ), .cin(gnd), - .combout(\D[4]~61_combout ), + .combout(\D[4]~98_combout ), .cout()); // synopsys translate_off -defparam \D[4]~61 .lut_mask = 16'hFFF7; -defparam \D[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \D[4]~78 ( -// Equation(s): -// \D[4]~78_combout = (\D[4]~61_combout ) # ((\Equal2~0_combout & ((\D[4]~66_combout ) # (\z80_|address_pins_|abus[0]~18_combout )))) - - .dataa(\D[4]~66_combout ), - .datab(\z80_|address_pins_|abus[0]~18_combout ), - .datac(\D[4]~61_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~78 .lut_mask = 16'hFEF0; -defparam \D[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \D[4]~79 ( -// Equation(s): -// \D[4]~79_combout = ((\D[4]~78_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\D[4]~78_combout ), - .datab(\z80_|data_pins_|dout [4]), - .datac(\D[0]~30_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cin(gnd), - .combout(\D[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~79 .lut_mask = 16'h8FAF; -defparam \D[4]~79 .sum_lutc_input = "datac"; +defparam \D[4]~98 .lut_mask = 16'hBB03; +defparam \D[4]~98 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X32_Y13_N24 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[4]~79_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[4]~19_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[4]~19_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[4]~19_combout ) # ((\D[4]~98_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[4]~98_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\D[4]~79_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[4]~98_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), .cout()); @@ -53500,41 +47748,41 @@ defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N20 +// Location: LCCOMB_X32_Y13_N20 cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( // Equation(s): // \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(gnd), - .datac(\z80_|data_pins_|dout [4]), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|data_pins_|dout [4]), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), .combout(\z80_|bus_control_|db[4]~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hF500; +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88CC; defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N4 +// Location: LCCOMB_X34_Y10_N18 cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( // Equation(s): // \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .dataa(\z80_|bus_control_|db[0]~6_combout ), .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[4]~19_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF0F; +defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF55; defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N5 +// Location: FF_X34_Y10_N19 dffeas \z80_|ir_|opcode[4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|bus_control_|db[4]~19_combout ), @@ -53553,32 +47801,2546 @@ defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X41_Y11_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Location: LCCOMB_X40_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( // Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) +// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), + .datab(gnd), .datac(\z80_|ir_|opcode [3]), - .datad(gnd), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), + .combout(\z80_|pla_decode_|Equal21~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h3030; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N12 +// Location: LCCOMB_X35_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( +// Equation(s): +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|fMRead~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|fMRead~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Equation(s): +// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F0F; +defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( +// Equation(s): +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|fIOWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( +// Equation(s): +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~5_combout ))) + + .dataa(\z80_|execute_|fIOWrite~1_combout ), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|fIOWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & +// (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~15_combout = ((\z80_|execute_|ctl_mWrite~14_combout ) # ((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout ))) # (!\z80_|execute_|ctl_mWrite~13_combout ) + + .dataa(\z80_|execute_|ixy_d~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~13_combout ), + .datac(\z80_|execute_|ctl_mWrite~14_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF7F3; +defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N29 +dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mWrite~15_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N4 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N5 +dffeas \z80_|memory_ifc_|wait_mwr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mwr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y17_N17 +dffeas \z80_|memory_ifc_|mwr_wr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|mwr_wr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N16 +cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(\z80_|memory_ifc_|iorq~0_combout ), + .datac(\z80_|memory_ifc_|mwr_wr~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|memory_ifc_|nWR_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; +defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \D[5]~84 ( +// Equation(s): +// \D[5]~84_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cin(gnd), + .combout(\D[5]~84_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~84 .lut_mask = 16'h0040; +defparam \D[5]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF858; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~0 .lut_mask = 16'hBA98; +defparam \Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \Mux0~1 ( +// Equation(s): +// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datad(\Mux0~0_combout ), + .cin(gnd), + .combout(\Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~1 .lut_mask = 16'hBBC0; +defparam \Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N22 +cycloneive_lcell_comb \D[7]~112 ( +// Equation(s): +// \D[7]~112_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux0~1_combout ))) +// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~112_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~112 .lut_mask = 16'hF4B0; +defparam \D[7]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N30 +cycloneive_lcell_comb \D[7]~94 ( +// Equation(s): +// \D[7]~94_combout = (\D[5]~84_combout & (\D[7]~112_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) + + .dataa(\D[5]~84_combout ), + .datab(\z80_|data_pins_|dout [7]), + .datac(\D[7]~112_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\D[7]~94_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~94 .lut_mask = 16'hC4F5; +defparam \D[7]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \D[7]~102 ( +// Equation(s): +// \D[7]~102_combout = (\D[7]~94_combout ) # (!\D[0]~107_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\D[7]~94_combout ), + .datad(\D[0]~107_combout ), + .cin(gnd), + .combout(\D[7]~102_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~102 .lut_mask = 16'hF0FF; +defparam \D[7]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\D[7]~102_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[7]~7_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[7]~102_combout & (\z80_|bus_control_|db[7]~7_combout +// & ((\z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[7]~102_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N27 +dffeas \z80_|data_pins_|dout[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Equation(s): +// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[7]~18_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N8 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Equation(s): +// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|data_pins_|dout [7]), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|bus_control_|db[7]~5_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hBF0F; +defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N21 +dffeas \z80_|ir_|opcode[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[7]~7_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_ir_we~4_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h3020; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC8C0; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~6_combout = (((\z80_|execute_|ctl_bus_db_we~4_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~2_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~3_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h000F; +defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & ((\ula_|zx_keyboard_|keys[0][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N17 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~48_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~48 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[3][3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), + .datab(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N23 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N22 +cycloneive_lcell_comb \D[2]~35 ( +// Equation(s): +// \D[2]~35_combout = (\z80_|address_pins_|abus[8]~18_combout & (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\z80_|address_pins_|abus[8]~18_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & +// ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) + + .dataa(\z80_|address_pins_|abus[8]~18_combout ), + .datab(\ula_|zx_keyboard_|keys[0][2]~q ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\z80_|address_pins_|abus[9]~17_combout ), + .cin(gnd), + .combout(\D[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~35 .lut_mask = 16'hBB0B; +defparam \D[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h3300; +defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|zx_keyboard_|keys[5][2]~57_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[5][2]~57_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N15 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h0420; +defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[4][2]~59_combout & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~131 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[4][2]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|zx_keyboard_|keys[4][2]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~131_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[4][2]~131_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N15 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \D[2]~37 ( +// Equation(s): +// \D[2]~37_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[5][2]~q ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~37 .lut_mask = 16'hBB0B; +defparam \D[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~55 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[2][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~56_combout = (\ula_|zx_keyboard_|keys[2][2]~55_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][2]~q ), + .datad(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N27 +dffeas \ula_|zx_keyboard_|keys[2][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N29 +dffeas \ula_|zx_keyboard_|keys[3][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N8 +cycloneive_lcell_comb \D[2]~36 ( +// Equation(s): +// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~24_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & +// (((\z80_|address_pins_|abus[11]~19_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), + .datab(\ula_|zx_keyboard_|keys[3][2]~q ), + .datac(\z80_|address_pins_|abus[10]~24_combout ), + .datad(\z80_|address_pins_|abus[11]~19_combout ), + .cin(gnd), + .combout(\D[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~36 .lut_mask = 16'hF531; +defparam \D[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h0180; +defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~68_combout )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~70_combout = (\ula_|zx_keyboard_|keys[6][2]~69_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~69_combout & ((\ula_|zx_keyboard_|keys[6][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), + .datab(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .datac(\ula_|zx_keyboard_|keys[6][2]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h7474; +defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N1 +dffeas \ula_|zx_keyboard_|keys[6][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[7][2]~61_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~62_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~63_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[7][2]~62_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'hC8C0; +defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~65_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & \ula_|zx_keyboard_|keys[7][2]~64_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector13~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF22; +defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[7][2]~65_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~65_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][2]~q ), + .datad(\ula_|zx_keyboard_|Selector13~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N13 +dffeas \ula_|zx_keyboard_|keys[7][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N0 +cycloneive_lcell_comb \D[2]~38 ( +// Equation(s): +// \D[2]~38_combout = (\z80_|address_pins_|abus[15]~22_combout & (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][2]~q & +// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\ula_|zx_keyboard_|keys[6][2]~q ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~q ), + .cin(gnd), + .combout(\D[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~38 .lut_mask = 16'hA2F3; +defparam \D[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N14 +cycloneive_lcell_comb \D[2]~39 ( +// Equation(s): +// \D[2]~39_combout = (\D[2]~35_combout & (\D[2]~37_combout & (\D[2]~36_combout & \D[2]~38_combout ))) + + .dataa(\D[2]~35_combout ), + .datab(\D[2]~37_combout ), + .datac(\D[2]~36_combout ), + .datad(\D[2]~38_combout ), + .cin(gnd), + .combout(\D[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~39 .lut_mask = 16'h8000; +defparam \D[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \D[2]~104 ( +// Equation(s): +// \D[2]~104_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\D[2]~39_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [0]), + .datad(\D[2]~39_combout ), + .cin(gnd), + .combout(\D[2]~104_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~104 .lut_mask = 16'hFFF3; +defparam \D[2]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \D[2]~43 ( +// Equation(s): +// \D[2]~43_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\D[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~43 .lut_mask = 16'hB9A8; +defparam \D[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \D[2]~44 ( +// Equation(s): +// \D[2]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~43_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout )) # (!\D[2]~43_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~43_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\D[2]~43_combout ), + .cin(gnd), + .combout(\D[2]~44_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~44 .lut_mask = 16'hBBC0; +defparam \D[2]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \D[2]~40 ( +// Equation(s): +// \D[2]~40_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\D[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~40 .lut_mask = 16'hEA62; +defparam \D[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \D[2]~41 ( +// Equation(s): +// \D[2]~41_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ (\D[2]~40_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & ((!\D[2]~40_combout )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\D[2]~40_combout ), + .cin(gnd), + .combout(\D[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~41 .lut_mask = 16'h0AE4; +defparam \D[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \D[2]~42 ( +// Equation(s): +// \D[2]~42_combout = (\D[2]~40_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~41_combout )))) # (!\D[2]~40_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~41_combout )))) + + .dataa(\D[2]~40_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\D[2]~41_combout ), + .cin(gnd), + .combout(\D[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~42 .lut_mask = 16'h99A8; +defparam \D[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \D[2]~105 ( +// Equation(s): +// \D[2]~105_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[2]~44_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~42_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[2]~44_combout )))) + + .dataa(\D[2]~44_combout ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\D[2]~42_combout ), + .cin(gnd), + .combout(\D[2]~105_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~105 .lut_mask = 16'hBA8A; +defparam \D[2]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N28 +cycloneive_lcell_comb \D[2]~45 ( +// Equation(s): +// \D[2]~45_combout = ((\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[2]~104_combout ), + .datad(\D[2]~105_combout ), + .cin(gnd), + .combout(\D[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~45 .lut_mask = 16'hF7B3; +defparam \D[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N30 +cycloneive_lcell_comb \D[2]~46 ( +// Equation(s): +// \D[2]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~45_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[2]~45_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[2]~45_combout ), + .cin(gnd), + .combout(\D[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~46 .lut_mask = 16'hAF03; +defparam \D[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N2 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[2]~46_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[2]~46_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\D[2]~46_combout ), + .datad(\z80_|bus_control_|db[2]~13_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N3 +dffeas \z80_|data_pins_|dout[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( +// Equation(s): +// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[2]~29_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( +// Equation(s): +// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|bus_control_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hBF33; +defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N13 +dffeas \z80_|ir_|opcode[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[2]~13_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N26 cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( // Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) +// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal43~0_combout ), .cout()); @@ -53587,14 +50349,14 @@ defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N14 +// Location: LCCOMB_X35_Y17_N24 cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( // Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal79~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & !\z80_|pla_decode_|Equal36~0_combout ))) +// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) .dataa(\z80_|pla_decode_|Equal43~0_combout ), - .datab(\z80_|pla_decode_|Equal79~0_combout ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datab(\z80_|pla_decode_|Equal3~2_combout ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), .datad(\z80_|pla_decode_|Equal36~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|test1~2_combout ), @@ -53604,24 +50366,24 @@ defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N22 +// Location: LCCOMB_X43_Y15_N26 cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( // Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & (((\z80_|interrupts_|test1~2_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) +// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|interrupts_|test1~2_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|interrupts_|test1~2_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|interrupts_|test1~2_combout ), .cin(gnd), .combout(\z80_|interrupts_|test1~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h00FD; +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h5545; defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y12_N27 +// Location: FF_X32_Y15_N13 dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), @@ -53640,7 +50402,7 @@ defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N16 +// Location: LCCOMB_X43_Y15_N2 cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( // Equation(s): // \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) @@ -53657,7 +50419,7 @@ defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y12_N17 +// Location: FF_X43_Y15_N3 dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), @@ -53676,7 +50438,7 @@ defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N2 +// Location: LCCOMB_X43_Y15_N20 cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( // Equation(s): // \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) @@ -53693,7 +50455,7 @@ defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0033; defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N1 +// Location: FF_X32_Y17_N13 dffeas \z80_|sequencer_|DFFE_T1_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|ena_M~combout ), @@ -53712,24 +50474,24 @@ defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N26 +// Location: LCCOMB_X32_Y17_N4 cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( // Equation(s): // \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), .datac(\z80_|execute_|setM1~52_combout ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0030; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N27 +// Location: FF_X32_Y17_N5 dffeas \z80_|sequencer_|DFFE_T2_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), @@ -53748,318 +50510,56 @@ defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N16 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|resets_|x3 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - .dataa(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datac(\z80_|resets_|x1~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .combout(\z80_|resets_|x3~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +defparam \z80_|resets_|x3 .lut_mask = 16'hF0FA; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N17 -dffeas \z80_|sequencer_|DFFE_T3_ff ( +// Location: FF_X35_Y13_N11 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .d(\z80_|resets_|x3~combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N14 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N15 -dffeas \z80_|sequencer_|DFFE_T4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), +// Location: CLKCTRL_G7 +cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), + .clkselect(2'b00), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), - .prn(vcc)); + .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X44_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( -// Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (\z80_|execute_|setM1~39_combout & !\z80_|execute_|ctl_mWrite~5_combout ) - - .dataa(\z80_|execute_|setM1~39_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h00AA; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~53 ( -// Equation(s): -// \z80_|execute_|setM1~53_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & \z80_|execute_|ctl_mRead~29_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~53_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h2AAA; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'hA800; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ctl_mRead~38_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|execute_|nextM~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|ctl_alu_op_low~37_combout ) # (\z80_|execute_|nextM~10_combout )) # (!\z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|nextM~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~37_combout ), - .datad(\z80_|execute_|nextM~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|fMRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'h8808; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (((\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|nextM~4_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|nextM~4_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~5_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~6_combout ) - - .dataa(\z80_|execute_|nextM~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|nextM~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( -// Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ixy_d~8_combout & (((!\z80_|alu_control_|flags_cond_true~q & \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|ixy_d~8_combout & -// (((!\z80_|alu_control_|flags_cond_true~q & \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout )))) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h2F22; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # ((\z80_|execute_|nextM~7_combout ) # (\z80_|execute_|nextM~8_combout ))) - - .dataa(\z80_|execute_|nextM~12_combout ), - .datab(\z80_|execute_|nextM~15_combout ), - .datac(\z80_|execute_|nextM~7_combout ), - .datad(\z80_|execute_|nextM~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~3_combout ) # ((\z80_|execute_|nextM~13_combout ) # ((!\z80_|execute_|ctl_mWrite~13_combout ) # (!\z80_|execute_|ctl_mRead~31_combout ))) - - .dataa(\z80_|execute_|nextM~3_combout ), - .datab(\z80_|execute_|nextM~13_combout ), - .datac(\z80_|execute_|ctl_mRead~31_combout ), - .datad(\z80_|execute_|ctl_mWrite~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N4 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; -defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N5 +// Location: FF_X32_Y17_N21 dffeas \z80_|sequencer_|DFFE_M1_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), @@ -54078,644 +50578,7 @@ defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N24 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N25 -dffeas \z80_|sequencer_|T6 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|T6~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|T6 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~9_combout )) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0011; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~43 ( -// Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0004; -defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~42_combout & (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|setM1~43_combout & !\z80_|pla_decode_|Equal21~1_combout ))) - - .dataa(\z80_|execute_|setM1~42_combout ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|setM1~43_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0020; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (\z80_|execute_|setM1~44_combout & (\z80_|execute_|setM1~41_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|execute_|setM1~44_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0888; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & -// (((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal21~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & !\z80_|pla_decode_|Equal1~6_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal77~1_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|pla_decode_|Equal1~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (!\z80_|pla_decode_|Equal2~2_combout & (\z80_|execute_|setM1~15_combout & (\z80_|execute_|setM1~14_combout & \z80_|interrupts_|test1~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|execute_|setM1~15_combout ), - .datac(\z80_|execute_|setM1~14_combout ), - .datad(\z80_|interrupts_|test1~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~49_combout & (\z80_|execute_|setM1~46_combout & \z80_|execute_|setM1~16_combout ))) - - .dataa(\z80_|execute_|setM1~45_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|execute_|setM1~46_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|setM1~41_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & -// (\z80_|execute_|setM1~40_combout ))) - - .dataa(\z80_|sequencer_|T6~q ), - .datab(\z80_|execute_|setM1~50_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'hC0EA; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hCDCC; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal6~1_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout ) # (\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|fMWrite~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|fMWrite~1_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~11_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|setM1~11_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|setM1~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & ((\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hDC50; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = ((\z80_|execute_|setM1~8_combout & \z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|execute_|setM1~8_combout ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF333; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( -// Equation(s): -// \z80_|execute_|setM1~13_combout = (\z80_|execute_|setM1~9_combout ) # (((\z80_|execute_|setM1~12_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) - - .dataa(\z80_|execute_|setM1~12_combout ), - .datab(\z80_|execute_|setM1~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'hECFF; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (\z80_|execute_|setM1~17_combout & (\z80_|execute_|ctl_alu_op_low~36_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|setM1~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~36_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0008; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~13_combout ) # (((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|setM1~16_combout )) # (!\z80_|execute_|setM1~18_combout )) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|setM1~16_combout ), - .datac(\z80_|execute_|setM1~13_combout ), - .datad(\z80_|execute_|setM1~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hF2FF; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = (\z80_|alu_control_|flags_cond_true~q & (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) # (!\z80_|alu_control_|flags_cond_true~q & -// ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((!\z80_|execute_|ctl_mRead~14_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'h7350; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|execute_|fMWrite~6_combout ))) - - .dataa(\z80_|execute_|fMWrite~1_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|fMWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0200; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'hFF02; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( -// Equation(s): -// \z80_|execute_|setM1~55_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~22_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~22_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'hC888; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~55_combout )) # (!\z80_|execute_|setM1~23_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~55_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|setM1~23_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~55_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h2F22; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hBAFF; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = ((\z80_|execute_|setM1~26_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datad(\z80_|execute_|setM1~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|setM1~27_combout ))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~24_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|setM1~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_mRead~38_combout & \z80_|execute_|setM1~11_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|setM1~11_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~20_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ctl_mRead~20_combout & -// (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|setM1~29_combout & \z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|setM1~30_combout )) # (!\z80_|execute_|setM1~56_combout ) - - .dataa(\z80_|execute_|setM1~29_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|setM1~56_combout ), - .datad(\z80_|execute_|setM1~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~33_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|setM1~33_combout ), - .datac(\z80_|execute_|setM1~32_combout ), - .datad(\z80_|execute_|setM1~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = ((\z80_|execute_|ctl_iorw~10_combout & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hD555; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~13_combout & (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~13_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20AA; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|execute_|setM1~20_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hECCC; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~34_combout ) # ((\z80_|execute_|setM1~54_combout ) # (\z80_|execute_|setM1~21_combout ))) - - .dataa(\z80_|execute_|setM1~28_combout ), - .datab(\z80_|execute_|setM1~34_combout ), - .datac(\z80_|execute_|setM1~54_combout ), - .datad(\z80_|execute_|setM1~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( -// Equation(s): -// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~19_combout & (!\z80_|execute_|setM1~35_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|setM1~51_combout ), - .datac(\z80_|execute_|setM1~19_combout ), - .datad(\z80_|execute_|setM1~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'h000B; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N18 +// Location: LCCOMB_X32_Y17_N10 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( // Equation(s): // \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) @@ -54732,7 +50595,7 @@ defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N19 +// Location: FF_X32_Y17_N11 dffeas \z80_|sequencer_|DFFE_M2_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), @@ -54751,195 +50614,2625 @@ defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( // Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .combout(\z80_|execute_|ctl_mWrite~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Location: LCCOMB_X41_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~39_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) +// \z80_|execute_|nextM~11_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ctl_mWrite~3_combout ) - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .combout(\z80_|execute_|nextM~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Location: LCCOMB_X40_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = (\z80_|execute_|pc_inc_hold~19_combout & ((\z80_|execute_|ctl_mRead~38_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|pc_inc_hold~19_combout & -// (((\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ixy_d~4_combout )))) +// \z80_|execute_|nextM~8_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout +// ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~19_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ixy_d~8_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .combout(\z80_|execute_|nextM~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~8 .lut_mask = 16'h44F4; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Location: LCCOMB_X39_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (((\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_bus_db_oe~7_combout )) # (!\z80_|execute_|pc_inc_hold~40_combout ))) +// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ixy_d~6_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~40_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .combout(\z80_|execute_|nextM~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~9 .lut_mask = 16'h8880; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( +// Location: LCCOMB_X40_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|execute_|pc_inc_hold~36_combout ) # ((\z80_|execute_|pc_inc_hold~35_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|pc_inc_hold~40_combout ))) +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|ixy_d~9_combout ))) - .dataa(\z80_|execute_|pc_inc_hold~36_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|pc_inc_hold~40_combout ), - .datad(\z80_|execute_|pc_inc_hold~35_combout ), + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datab(\z80_|execute_|nextM~9_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~37_combout ), + .combout(\z80_|execute_|nextM~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( +// Location: LCCOMB_X40_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~38_combout = ((\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|pc_inc_hold~34_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout ))) # (!\z80_|execute_|ctl_inc_cy~39_combout ) +// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|ctl_alu_op_low~32_combout ))) # (!\z80_|execute_|nextM~11_combout ) - .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), - .datab(\z80_|execute_|pc_inc_hold~37_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .dataa(\z80_|execute_|nextM~11_combout ), + .datab(\z80_|execute_|nextM~8_combout ), + .datac(\z80_|execute_|nextM~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~38_combout ), + .combout(\z80_|execute_|nextM~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Location: LCCOMB_X39_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (!\z80_|execute_|pc_inc_hold~38_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) +// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|fMRead~10_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .combout(\z80_|execute_|nextM~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~15 .lut_mask = 16'h80A0; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Location: LCCOMB_X40_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) +// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|nM1_int~2_combout ), + .dataa(\z80_|execute_|ixy_d~17_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'hDF5F; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ixy_d~8_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|execute_|nextM~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # (\z80_|execute_|nextM~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(\z80_|execute_|nextM~15_combout ), + .datad(\z80_|execute_|nextM~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (!\z80_|execute_|ctl_mWrite~5_combout & \z80_|execute_|setM1~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|setM1~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0F00; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~45_combout ) # (!\z80_|execute_|nextM~2_combout )) # (!\z80_|execute_|setM1~39_combout ))) + + .dataa(\z80_|execute_|setM1~39_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|setM1~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~13_combout ) # (((\z80_|execute_|nextM~5_combout ) # (!\z80_|execute_|ctl_mRead~30_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) + + .dataa(\z80_|execute_|nextM~13_combout ), + .datab(\z80_|execute_|ctl_mWrite~13_combout ), + .datac(\z80_|execute_|ctl_mRead~30_combout ), + .datad(\z80_|execute_|nextM~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N14 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|setM1~52_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N15 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N18 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N19 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N26 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|setM1~52_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N27 +dffeas \z80_|sequencer_|T6 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|T6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|T6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal21~2_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & +// (((!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal21~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'h153F; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal77~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~1_combout ), + .datab(\z80_|execute_|ctl_alu_oe~3_combout ), + .datac(\z80_|pla_decode_|Equal1~6_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~13_combout & (\z80_|interrupts_|test1~2_combout & \z80_|execute_|setM1~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~13_combout ), + .datac(\z80_|interrupts_|test1~2_combout ), + .datad(\z80_|execute_|setM1~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'hC000; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0005; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0100; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~43 ( +// Equation(s): +// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~41_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~42_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|setM1~41_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|setM1~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0400; +defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (\z80_|execute_|setM1~40_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|execute_|setM1~40_combout ), + .datad(\z80_|pla_decode_|Equal2~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h20A0; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~14_combout & (\z80_|execute_|setM1~44_combout & \z80_|execute_|setM1~49_combout ))) + + .dataa(\z80_|execute_|setM1~46_combout ), + .datab(\z80_|execute_|setM1~14_combout ), + .datac(\z80_|execute_|setM1~44_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~39_combout )) # (!\z80_|execute_|setM1~40_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & +// ((\z80_|execute_|setM1~39_combout )))) + + .dataa(\z80_|sequencer_|T6~q ), + .datab(\z80_|execute_|setM1~50_combout ), + .datac(\z80_|execute_|setM1~40_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'hCE0A; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~6 ( +// Equation(s): +// \z80_|execute_|setM1~6_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & (\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & +// \z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~6 .lut_mask = 16'hD5C0; +defparam \z80_|execute_|setM1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~7 ( +// Equation(s): +// \z80_|execute_|setM1~7_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|setM1~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~7 .lut_mask = 16'hF333; +defparam \z80_|execute_|setM1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~8 ( +// Equation(s): +// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|fMWrite~3_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~8 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~9 ( +// Equation(s): +// \z80_|execute_|setM1~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF1F0; +defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = ((\z80_|execute_|setM1~8_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~9_combout ))) # (!\z80_|execute_|nextM~2_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~16_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|setM1~8_combout ), + .datad(\z80_|execute_|setM1~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = (\z80_|execute_|setM1~7_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~10_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) + + .dataa(\z80_|execute_|setM1~7_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|setM1~10_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = ((\z80_|execute_|setM1~11_combout ) # ((!\z80_|execute_|setM1~14_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~16_combout ) + + .dataa(\z80_|execute_|setM1~16_combout ), + .datab(\z80_|execute_|setM1~14_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'hFF75; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~18_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & +// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~18_combout )))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hECA0; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|setM1~28_combout )) # (!\z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~54_combout ) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|execute_|setM1~29_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|setM1~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'hF777; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|setM1~9_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|setM1~9_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~32_combout ))) + + .dataa(\z80_|execute_|setM1~31_combout ), + .datab(\z80_|execute_|setM1~30_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|setM1~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'hAF0F; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_mRead~12_combout ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & ((!\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|alu_control_|flags_cond_true~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|setM1~25_combout ) # (\z80_|execute_|setM1~26_combout )))) + + .dataa(\z80_|execute_|setM1~25_combout ), + .datab(\z80_|execute_|setM1~26_combout ), + .datac(\z80_|execute_|setM1~24_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|execute_|fMWrite~9_combout & (!\z80_|execute_|ctl_mRead~8_combout & \z80_|execute_|fMWrite~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|fMWrite~9_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'h0400; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF1F0; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~53 ( +// Equation(s): +// \z80_|execute_|setM1~53_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~21_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|setM1~21_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~53 .lut_mask = 16'hC888; +defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~22_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # +// ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) + + .dataa(\z80_|execute_|setM1~22_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'h4F44; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|execute_|ctl_flags_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'h08CC; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~18_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) + + .dataa(\z80_|execute_|setM1~18_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'hEAAA; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = ((\z80_|execute_|setM1~19_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|ctl_mWrite~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~3_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datad(\z80_|execute_|setM1~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|setM1~23_combout ) # (\z80_|execute_|setM1~20_combout ))) + + .dataa(\z80_|execute_|setM1~33_combout ), + .datab(\z80_|execute_|setM1~27_combout ), + .datac(\z80_|execute_|setM1~23_combout ), + .datad(\z80_|execute_|setM1~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~17_combout & (!\z80_|execute_|setM1~34_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|setM1~34_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'h0301; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N24 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N25 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N24 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Equation(s): +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|decode_state_|in_halt~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0050; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( +// Equation(s): +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|decode_state_|in_halt~0_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|pla_decode_|Equal77~1_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|in_halt~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hCECC; +defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N25 +dffeas \z80_|decode_state_|in_halt ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|in_halt~1_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|in_halt~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; +defparam \z80_|decode_state_|in_halt .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_zero_oe~0_combout & (!\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0031; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), .datad(\z80_|pla_decode_|Equal41~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'h010F; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~68_combout & \z80_|execute_|ctl_inc_cy~69_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ))) +// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - .dataa(\z80_|execute_|ctl_inc_cy~68_combout ), - .datab(\z80_|execute_|ctl_inc_cy~69_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'h8F00; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # (\z80_|execute_|ctl_inc_cy~80_combout )))) +// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - .dataa(\z80_|execute_|ctl_inc_cy~70_combout ), - .datab(\z80_|execute_|ctl_inc_cy~67_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~80_combout ), + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0F1E; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N20 +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Equation(s): +// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; +defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|zx_keyboard_|keys[1][3]~93_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][3]~93_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N31 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~94_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|zx_keyboard_|keys[0][3]~96_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & +// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~97_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N1 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~98_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N4 +cycloneive_lcell_comb \D[3]~65 ( +// Equation(s): +// \D[3]~65_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][3]~q ), + .cin(gnd), + .combout(\D[3]~65_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~65 .lut_mask = 16'h8CAF; +defparam \D[3]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~99_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~99 .lut_mask = 16'h4040; +defparam \ula_|zx_keyboard_|keys[3][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~100 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~100_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[3][3]~99_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~99_combout & (\ula_|zx_keyboard_|keys[3][3]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), + .datab(\ula_|zx_keyboard_|keys[3][3]~99_combout ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~100_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~100 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][3]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N9 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~100_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'hCCDD; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~133 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~133_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][3]~102_combout & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~133_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~133 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[2][3]~133 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|keys[2][3]~133_combout & (!\ula_|zx_keyboard_|keys[2][3]~101_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~133_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][3]~133_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N3 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~103_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N28 +cycloneive_lcell_comb \D[3]~66 ( +// Equation(s): +// \D[3]~66_combout = (\z80_|address_pins_|abus[11]~19_combout & (((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[3][3]~q ), + .datac(\z80_|address_pins_|abus[10]~24_combout ), + .datad(\ula_|zx_keyboard_|keys[2][3]~q ), + .cin(gnd), + .combout(\D[3]~66_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~66 .lut_mask = 16'hB0BB; +defparam \D[3]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[5][3]~q +// )))) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N23 +dffeas \ula_|zx_keyboard_|keys[5][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|WideOr16~2_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~134 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~134_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), + .datab(\ula_|zx_keyboard_|Selector5~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~134 .lut_mask = 16'hCECC; +defparam \ula_|zx_keyboard_|keys[4][3]~134 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~106_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][3]~134_combout )))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~135 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~135_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~135 .lut_mask = 16'hCDCC; +defparam \ula_|zx_keyboard_|keys[4][3]~135 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|keys[4][3]~135_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & +// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N23 +dffeas \ula_|zx_keyboard_|keys[4][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][3]~108_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N20 +cycloneive_lcell_comb \D[3]~67 ( +// Equation(s): +// \D[3]~67_combout = (\ula_|zx_keyboard_|keys[5][3]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][3]~q & +// (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][3]~q ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[3]~67_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~67 .lut_mask = 16'hDD0D; +defparam \D[3]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~61_combout )))) + + .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hA888; +defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & ((!\ula_|zx_keyboard_|keys[0][4]~111_combout ))) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & (\ula_|zx_keyboard_|keys[7][3]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y20_N9 +dffeas \ula_|zx_keyboard_|keys[7][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~109_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~109 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[6][3]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~110_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~109_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~32_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~110 .lut_mask = 16'hF088; +defparam \ula_|zx_keyboard_|keys[6][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~137 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~137_combout = (\ula_|zx_keyboard_|extended~q ) # (((!\ula_|zx_keyboard_|keys[0][0]~15_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~110_combout )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~137 .lut_mask = 16'hBFFF; +defparam \ula_|zx_keyboard_|keys[6][3]~137 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~138 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~138_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~137_combout & ((\ula_|zx_keyboard_|keys[6][3]~q ))) # (!\ula_|zx_keyboard_|keys[6][3]~137_combout & +// (!\ula_|zx_keyboard_|Selector13~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~138 .lut_mask = 16'hF072; +defparam \ula_|zx_keyboard_|keys[6][3]~138 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N29 +dffeas \ula_|zx_keyboard_|keys[6][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # ((!\ula_|zx_keyboard_|keys[6][3]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[6][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \D[3]~68 ( +// Equation(s): +// \D[3]~68_combout = (\D[3]~67_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\D[3]~67_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|key_row~2_combout ), + .cin(gnd), + .combout(\D[3]~68_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~68 .lut_mask = 16'h8C00; +defparam \D[3]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \D[3]~69 ( +// Equation(s): +// \D[3]~69_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~65_combout & (\D[3]~66_combout & \D[3]~68_combout ))) + + .dataa(\D[3]~65_combout ), + .datab(\z80_|address_pins_|abus[0]~16_combout ), + .datac(\D[3]~66_combout ), + .datad(\D[3]~68_combout ), + .cin(gnd), + .combout(\D[3]~69_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~69 .lut_mask = 16'hECCC; +defparam \D[3]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \D[3]~73 ( +// Equation(s): +// \D[3]~73_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\D[3]~73_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~73 .lut_mask = 16'hCCE2; +defparam \D[3]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \D[3]~74 ( +// Equation(s): +// \D[3]~74_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[3]~73_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ))) # (!\D[3]~73_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~73_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datac(\D[3]~73_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .cin(gnd), + .combout(\D[3]~74_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~74 .lut_mask = 16'hF858; +defparam \D[3]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \D[3]~70 ( +// Equation(s): +// \D[3]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~23_combout )) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\D[3]~70_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~70 .lut_mask = 16'hEC64; +defparam \D[3]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \D[3]~71 ( +// Equation(s): +// \D[3]~71_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout $ (((\D[3]~70_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & !\D[3]~70_combout )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\D[3]~70_combout ), + .cin(gnd), + .combout(\D[3]~71_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~71 .lut_mask = 16'h22D8; +defparam \D[3]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \D[3]~72 ( +// Equation(s): +// \D[3]~72_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~70_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~70_combout & (!\D[3]~71_combout & +// \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )) # (!\D[3]~70_combout & (\D[3]~71_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\D[3]~70_combout ), + .datac(\D[3]~71_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\D[3]~72_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~72 .lut_mask = 16'h9C98; +defparam \D[3]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \D[3]~108 ( +// Equation(s): +// \D[3]~108_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[3]~74_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[3]~72_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[3]~74_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\D[3]~74_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\D[3]~72_combout ), + .cin(gnd), + .combout(\D[3]~108_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~108 .lut_mask = 16'hDC8C; +defparam \D[3]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \D[3]~95 ( +// Equation(s): +// \D[3]~95_combout = ((\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[3]~69_combout ), + .datab(\Equal2~1_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[3]~108_combout ), + .cin(gnd), + .combout(\D[3]~95_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~95 .lut_mask = 16'hBFB3; +defparam \D[3]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \D[3]~96 ( +// Equation(s): +// \D[3]~96_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [3] & \D[3]~95_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[3]~95_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [3]), + .datad(\D[3]~95_combout ), + .cin(gnd), + .combout(\D[3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~96 .lut_mask = 16'hF511; +defparam \D[3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\D[3]~96_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[3]~96_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[3]~96_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N7 +dffeas \z80_|data_pins_|dout[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( +// Equation(s): +// \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(\z80_|data_pins_|dout [3]), + .datac(gnd), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hDD00; +defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( +// Equation(s): +// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N1 +dffeas \z80_|ir_|opcode[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[3]~21_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_apin_mux~1_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ctl_apin_mux~1_combout ), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h8F8F; +defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N18 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .datab(\z80_|address_latch_|abusz [0]), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|abusz [0]), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N21 +// Location: FF_X31_Y16_N19 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -54958,160 +53251,228 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \D[0]~84 ( +// Location: LCCOMB_X29_Y14_N12 +cycloneive_lcell_comb \D[0]~59 ( // Equation(s): -// \D[0]~84_combout = (\Equal2~0_combout & ((\D[0]~47_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~84 .lut_mask = 16'hFB00; -defparam \D[0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \D[0]~50 ( -// Equation(s): -// \D[0]~50_combout = (\D[0]~84_combout & (((\z80_|data_pins_|dout [0])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) # (!\D[0]~84_combout & (\D[0]~42_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) - - .dataa(\D[0]~84_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\D[0]~42_combout ), - .cin(gnd), - .combout(\D[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~50 .lut_mask = 16'hF3A2; -defparam \D[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N30 -cycloneive_lcell_comb \D[1]~85 ( -// Equation(s): -// \D[1]~85_combout = (\Equal2~0_combout & ((\z80_|address_pins_|DFFE_apin_latch [0]) # ((\D[1]~28_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \D[0]~59_combout = (\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout ))) .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\D[1]~28_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\D[0]~51_combout ), + .datac(\D[0]~106_combout ), + .datad(gnd), .cin(gnd), - .combout(\D[1]~85_combout ), + .combout(\D[0]~59_combout ), .cout()); // synopsys translate_off -defparam \D[1]~85 .lut_mask = 16'hA8AA; -defparam \D[1]~85 .sum_lutc_input = "datac"; +defparam \D[0]~59 .lut_mask = 16'hD8D8; +defparam \D[0]~59 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \D[1]~51 ( +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \D[0]~60 ( // Equation(s): -// \D[1]~51_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~85_combout ) # (\D[1]~23_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[1]~85_combout ) # (\D[1]~23_combout )))) +// \D[0]~60_combout = (\Equal2~1_combout & (\D[0]~59_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [0]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\D[1]~85_combout ), - .datad(\D[1]~23_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[0]~59_combout ), .cin(gnd), - .combout(\D[1]~51_combout ), + .combout(\D[0]~60_combout ), .cout()); // synopsys translate_off -defparam \D[1]~51 .lut_mask = 16'hDDD0; -defparam \D[1]~51 .sum_lutc_input = "datac"; +defparam \D[0]~60 .lut_mask = 16'hCF45; +defparam \D[0]~60 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N22 -cycloneive_lcell_comb \D[3]~86 ( +// Location: LCCOMB_X32_Y18_N20 +cycloneive_lcell_comb \D[1]~61 ( // Equation(s): -// \D[3]~86_combout = (\Equal2~0_combout & ((\z80_|address_pins_|DFFE_apin_latch [0]) # ((\D[3]~58_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \D[1]~61_combout = (\Equal2~0_combout & (\D[1]~32_combout )) # (!\Equal2~0_combout & ((\D[1]~103_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(\Equal2~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~58_combout ), + .dataa(\Equal2~0_combout ), + .datab(gnd), + .datac(\D[1]~32_combout ), + .datad(\D[1]~103_combout ), .cin(gnd), - .combout(\D[3]~86_combout ), + .combout(\D[1]~61_combout ), .cout()); // synopsys translate_off -defparam \D[3]~86 .lut_mask = 16'hCC8C; -defparam \D[3]~86 .sum_lutc_input = "datac"; +defparam \D[1]~61 .lut_mask = 16'hF5A0; +defparam \D[1]~61 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N14 -cycloneive_lcell_comb \D[3]~59 ( +// Location: LCCOMB_X32_Y18_N22 +cycloneive_lcell_comb \D[1]~62 ( // Equation(s): -// \D[3]~59_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~86_combout ) # (\D[3]~53_combout )))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[3]~86_combout ) # (\D[3]~53_combout )))) +// \D[1]~62_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~61_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~61_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [1]), + .datad(\D[1]~61_combout ), + .cin(gnd), + .combout(\D[1]~62_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~62 .lut_mask = 16'hF531; +defparam \D[1]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \D[2]~63 ( +// Equation(s): +// \D[2]~63_combout = (\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout ))) + + .dataa(\Equal2~0_combout ), + .datab(gnd), + .datac(\D[2]~104_combout ), + .datad(\D[2]~105_combout ), + .cin(gnd), + .combout(\D[2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~63 .lut_mask = 16'hF5A0; +defparam \D[2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \D[2]~64 ( +// Equation(s): +// \D[2]~64_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~63_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[2]~63_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[2]~63_combout ), + .cin(gnd), + .combout(\D[2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~64 .lut_mask = 16'hAF23; +defparam \D[2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \D[3]~75 ( +// Equation(s): +// \D[3]~75_combout = (\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout ))) + + .dataa(\D[3]~69_combout ), + .datab(gnd), + .datac(\Equal2~0_combout ), + .datad(\D[3]~108_combout ), + .cin(gnd), + .combout(\D[3]~75_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~75 .lut_mask = 16'hAFA0; +defparam \D[3]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \D[3]~76 ( +// Equation(s): +// \D[3]~76_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~75_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[3]~75_combout ) # (!\Equal2~1_combout )))) .dataa(\z80_|data_pins_|dout [3]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[3]~86_combout ), - .datad(\D[3]~53_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[3]~75_combout ), .cin(gnd), - .combout(\D[3]~59_combout ), + .combout(\D[3]~76_combout ), .cout()); // synopsys translate_off -defparam \D[3]~59 .lut_mask = 16'hBBB0; -defparam \D[3]~59 .sum_lutc_input = "datac"; +defparam \D[3]~76 .lut_mask = 16'hAF23; +defparam \D[3]~76 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \D[4]~87 ( +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \D[4]~82 ( // Equation(s): -// \D[4]~87_combout = (\Equal2~0_combout & ((\D[4]~66_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \D[4]~82_combout = (\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout ))) - .dataa(\D[4]~66_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\Equal2~0_combout ), + .dataa(\Equal2~0_combout ), + .datab(\D[4]~81_combout ), + .datac(gnd), + .datad(\D[4]~109_combout ), .cin(gnd), - .combout(\D[4]~87_combout ), + .combout(\D[4]~82_combout ), .cout()); // synopsys translate_off -defparam \D[4]~87 .lut_mask = 16'hFB00; -defparam \D[4]~87 .sum_lutc_input = "datac"; +defparam \D[4]~82 .lut_mask = 16'hDD88; +defparam \D[4]~82 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N4 -cycloneive_lcell_comb \D[4]~67 ( +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \D[4]~83 ( // Equation(s): -// \D[4]~67_combout = (\z80_|data_pins_|dout [4] & (((\D[4]~87_combout ) # (\D[4]~61_combout )))) # (!\z80_|data_pins_|dout [4] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[4]~87_combout ) # (\D[4]~61_combout )))) +// \D[4]~83_combout = (\Equal2~1_combout & (\D[4]~82_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[4]~87_combout ), - .datad(\D[4]~61_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[4]~82_combout ), .cin(gnd), - .combout(\D[4]~67_combout ), + .combout(\D[4]~83_combout ), .cout()); // synopsys translate_off -defparam \D[4]~67 .lut_mask = 16'hBBB0; -defparam \D[4]~67 .sum_lutc_input = "datac"; +defparam \D[4]~83 .lut_mask = 16'hCF45; +defparam \D[4]~83 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N2 +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \D[6]~92 ( +// Equation(s): +// \D[6]~92_combout = (\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout )) + + .dataa(gnd), + .datab(\Equal2~0_combout ), + .datac(\D[6]~111_combout ), + .datad(\D[6]~86_combout ), + .cin(gnd), + .combout(\D[6]~92_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~92 .lut_mask = 16'hFC30; +defparam \D[6]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \D[6]~93 ( +// Equation(s): +// \D[6]~93_combout = (\Equal2~1_combout & (\D[6]~92_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [6]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [6]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[6]~92_combout ), + .cin(gnd), + .combout(\D[6]~93_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~93 .lut_mask = 16'hCF45; +defparam \D[6]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N0 cycloneive_lcell_comb \z80_|nM1_int~3 ( // Equation(s): // \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) - .dataa(\z80_|execute_|setM1~52_combout ), + .dataa(gnd), .datab(\z80_|sequencer_|DFFE_T1_ff~q ), .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), + .datad(\z80_|execute_|setM1~52_combout ), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hA8A8; +defparam \z80_|nM1_int~3 .lut_mask = 16'hFC00; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N3 +// Location: FF_X43_Y17_N1 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -55130,7 +53491,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y16_N24 +// Location: LCCOMB_X43_Y17_N30 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -55147,7 +53508,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y16_N25 +// Location: FF_X43_Y17_N31 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -55166,7 +53527,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X50_Y16_N11 +// Location: FF_X43_Y17_N25 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -55185,7 +53546,7 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N10 +// Location: LCCOMB_X43_Y17_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) @@ -55202,15 +53563,15 @@ defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N14 +// Location: LCCOMB_X43_Y17_N2 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nRD_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nMREQ_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nRD_out~0_combout ))) .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datad(\z80_|memory_ifc_|nMREQ_out~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), .cout()); @@ -55219,7 +53580,20 @@ defparam \z80_|memory_ifc_|nMREQ_out~1 .lut_mask = 16'h0001; defparam \z80_|memory_ifc_|nMREQ_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N10 +// Location: CLKCTRL_G19 +cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk )); +// synopsys translate_off +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock"; +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( // Equation(s): // \ula_|i2c_loader_|state.Idle~feeder_combout = VCC @@ -55236,7 +53610,7 @@ defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N12 +// Location: LCCOMB_X4_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -55253,7 +53627,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N13 +// Location: FF_X4_Y24_N1 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -55272,14 +53646,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X4_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) - .dataa(\ula_|i2c_loader_|divider [0]), - .datab(\ula_|i2c_loader_|divider [1]), + .dataa(\ula_|i2c_loader_|divider [1]), + .datab(\ula_|i2c_loader_|divider [0]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -55290,7 +53664,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N15 +// Location: FF_X4_Y24_N11 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -55309,25 +53683,25 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N16 +// Location: LCCOMB_X4_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) // \ula_|i2c_loader_|divider[2]~8 = CARRY((!\ula_|i2c_loader_|divider[1]~6 ) # (!\ula_|i2c_loader_|divider [2])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [2]), + .dataa(\ula_|i2c_loader_|divider [2]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[1]~6 ), .combout(\ula_|i2c_loader_|divider[2]~7_combout ), .cout(\ula_|i2c_loader_|divider[2]~8 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N17 +// Location: FF_X4_Y24_N13 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -55346,7 +53720,7 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N18 +// Location: LCCOMB_X4_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) @@ -55364,7 +53738,7 @@ defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hC30C; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N19 +// Location: FF_X4_Y24_N15 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -55383,7 +53757,7 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N20 +// Location: LCCOMB_X4_Y24_N16 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) @@ -55401,7 +53775,7 @@ defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N21 +// Location: FF_X4_Y24_N17 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -55420,24 +53794,24 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N22 +// Location: LCCOMB_X4_Y24_N18 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): -// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider [5] $ (!\ula_|i2c_loader_|divider[4]~12 ) +// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) - .dataa(\ula_|i2c_loader_|divider [5]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|i2c_loader_|divider [5]), .cin(\ula_|i2c_loader_|divider[4]~12 ), .combout(\ula_|i2c_loader_|divider[5]~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N23 +// Location: FF_X4_Y24_N19 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -55456,14 +53830,14 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N2 +// Location: LCCOMB_X4_Y24_N22 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0]) +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [1]) - .dataa(\ula_|i2c_loader_|divider [0]), - .datab(\ula_|i2c_loader_|divider [3]), - .datac(\ula_|i2c_loader_|divider [1]), + .dataa(\ula_|i2c_loader_|divider [1]), + .datab(\ula_|i2c_loader_|divider [0]), + .datac(\ula_|i2c_loader_|divider [3]), .datad(\ula_|i2c_loader_|divider [2]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), @@ -55473,24 +53847,24 @@ defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N28 +// Location: LCCOMB_X4_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [5])) # (!\ula_|i2c_loader_|divider [4]) +// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [4]), - .datac(\ula_|i2c_loader_|divider [5]), - .datad(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datab(\ula_|i2c_loader_|divider [5]), + .datac(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datad(\ula_|i2c_loader_|divider [4]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hFF3F; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hF3FF; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N11 +// Location: FF_X1_Y23_N1 dffeas \ula_|i2c_loader_|state.Idle ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), @@ -55509,7 +53883,7 @@ defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N2 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( // Equation(s): // \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) @@ -55526,7 +53900,7 @@ defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N3 +// Location: FF_X1_Y23_N5 dffeas \ula_|i2c_loader_|phase[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~0_combout ), @@ -55545,24 +53919,24 @@ defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N8 +// Location: LCCOMB_X1_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( // Equation(s): -// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [1] $ (\ula_|i2c_loader_|phase [0]))) +// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) - .dataa(\ula_|i2c_loader_|state.Idle~q ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|phase~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h0AA0; +defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N9 +// Location: FF_X1_Y23_N15 dffeas \ula_|i2c_loader_|phase[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~1_combout ), @@ -55581,558 +53955,24 @@ defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( -// Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux42~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [0] $ (!\ula_|i2c_loader_|nbit [1])) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|nbit [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hB7B7; -defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|nbyte [0])) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|nbyte [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h0202; -defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|phase [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y23_N1 -cycloneive_io_ibuf \I2C_SDAT~input ( - .i(I2C_SDAT), - .ibar(gnd), - .o(\I2C_SDAT~input_o )); -// synopsys translate_off -defparam \I2C_SDAT~input .bus_hold = "false"; -defparam \I2C_SDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|thisbyte[0]~7_combout & ((\ula_|i2c_loader_|nbyte[0]~1_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hCAC0; -defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h0C00; -defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y23_N5 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [1] & (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbyte [0])) - - .dataa(\ula_|i2c_loader_|nbyte [1]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(gnd), - .datad(\ula_|i2c_loader_|nbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0011; -defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; -defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|state.Done~0_combout ) # (\ula_|i2c_loader_|nbit[0]~2_combout )))) - - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|state.Done~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; -defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|Mux42~0_combout & \ula_|i2c_loader_|state.Idle~q ))) - - .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|Mux42~0_combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h1000; -defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N17 -dffeas \ula_|i2c_loader_|nbit[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [0] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) - - .dataa(\ula_|i2c_loader_|nbit [0]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~0_combout = (!\ula_|i2c_loader_|state.Pause~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Start~q ))) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'h0001; -defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Ack~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Done~0_combout ), - .datab(\ula_|i2c_loader_|state.Ack~0_combout ), - .datac(\ula_|i2c_loader_|Mux42~0_combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hB0FF; -defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~2_combout = (\ula_|i2c_loader_|state.Ack~1_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # -// (!\ula_|i2c_loader_|state.Ack~1_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|state.Ack~1_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~2 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Ack~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N31 -dffeas \ula_|i2c_loader_|state.Ack ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Ack~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Ack~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( -// Equation(s): -// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [1]) # (\ula_|i2c_loader_|nbyte [0]))) - - .dataa(\ula_|i2c_loader_|nbyte [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|nbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hF0A0; -defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( -// Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|state~24_combout & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1])) - - .dataa(\ula_|i2c_loader_|state~24_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; -defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( -// Equation(s): -// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|phase [1]) # (!\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|phase [0]) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|state.Done~1_combout ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h3FFF; -defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~27_combout ))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~26_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state~26_combout ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state~27_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Data~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hFC0C; -defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N21 -dffeas \ula_|i2c_loader_|state.Data ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Data~0_combout ), - .asdata(\ula_|i2c_loader_|Mux42~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Data~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Data .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N26 +// Location: LCCOMB_X3_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( // Equation(s): // \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|nbit [0]) # (!\ula_|i2c_loader_|state.Data~q ) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(gnd), .datac(\ula_|i2c_loader_|nbit [0]), .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|nbit~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h3F3F; +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h5F5F; defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N27 -dffeas \ula_|i2c_loader_|nbit[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|nbit [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|nbit [2]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF3B7; -defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N21 -dffeas \ula_|i2c_loader_|nbit[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|nbit [0]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0003; -defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|state.Pause~q & (((!\ula_|i2c_loader_|state.Done~1_combout & \ula_|i2c_loader_|state.Data~q )))) # (!\ula_|i2c_loader_|state.Pause~q & ((\ula_|i2c_loader_|scl_out~0_combout ) # -// ((!\ula_|i2c_loader_|state.Done~1_combout & \ula_|i2c_loader_|state.Data~q )))) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|scl_out~0_combout ), - .datac(\ula_|i2c_loader_|state.Done~1_combout ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h4F44; -defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Done~2_combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h8AFF; -defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|phase [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5CFC; -defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N10 +// Location: LCCOMB_X2_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) @@ -56150,332 +53990,119 @@ defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Location: LCCOMB_X1_Y24_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|phase [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Mux42~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) .dataa(\ula_|i2c_loader_|nbyte [0]), .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; -defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y23_N11 -dffeas \ula_|i2c_loader_|thisbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), - .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h5A5F; -defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N13 -dffeas \ula_|i2c_loader_|thisbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) -// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), - .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; -defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N15 -dffeas \ula_|i2c_loader_|thisbyte[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), - .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N17 -dffeas \ula_|i2c_loader_|thisbyte[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte[3]~15 $ (!\ula_|i2c_loader_|thisbyte [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), - .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hF00F; -defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N19 -dffeas \ula_|i2c_loader_|thisbyte[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Pause~0_combout ), - .datac(\ula_|i2c_loader_|Equal2~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h0CCC; -defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Pause~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~1_combout ))))) # -// (!\ula_|i2c_loader_|state.Pause~2_combout & (((\ula_|i2c_loader_|state.Pause~q )))) - - .dataa(\ula_|i2c_loader_|state.Pause~2_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Pause~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N7 -dffeas \ula_|i2c_loader_|state.Pause ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Pause~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Pause~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( -// Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # -// (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; -defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N17 -dffeas \ula_|i2c_loader_|state.Start ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state~25_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Start~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Start .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [1] $ (!\ula_|i2c_loader_|nbyte [0])))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hECCE; +defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hFF84; defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N31 +// Location: LCCOMB_X1_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N1 +cycloneive_io_ibuf \I2C_SDAT~input ( + .i(I2C_SDAT), + .ibar(gnd), + .o(\I2C_SDAT~input_o )); +// synopsys translate_off +defparam \I2C_SDAT~input .bus_hold = "false"; +defparam \I2C_SDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hEFE0; +defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; +defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~3_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbyte[0]~2_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h3000; +defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N29 dffeas \ula_|i2c_loader_|nbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbyte~4_combout ), @@ -56494,42 +54121,42 @@ defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 +// Location: LCCOMB_X2_Y24_N18 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [1] & (\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|nbyte [0])) +// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) - .dataa(\ula_|i2c_loader_|nbyte [1]), - .datab(gnd), + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|nbyte [0]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|state.Stop~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0050; +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h1010; defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N24 +// Location: LCCOMB_X1_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( // Equation(s): -// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Stop~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))))) # -// (!\ula_|i2c_loader_|Mux42~0_combout & (((\ula_|i2c_loader_|state.Stop~q )))) +// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))) # +// (!\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~q )))) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), .datac(\ula_|i2c_loader_|state.Stop~q ), .datad(\ula_|i2c_loader_|state.Stop~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Stop~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF4B0; defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N25 +// Location: FF_X1_Y24_N3 dffeas \ula_|i2c_loader_|state.Stop ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Stop~1_combout ), @@ -56548,16 +54175,763 @@ defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Location: LCCOMB_X1_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Ack~q ))) - .dataa(gnd), + .dataa(\ula_|i2c_loader_|state.Start~q ), .datab(\ula_|i2c_loader_|state.Stop~q ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; +defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|nbit [2]), + .datad(\ula_|i2c_loader_|nbit [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N1 +dffeas \ula_|i2c_loader_|nbit[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [0]))) + + .dataa(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|nbit [2]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Idle~0_combout ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|state.Done~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hAF2F; +defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), .datac(\ula_|i2c_loader_|state.Ack~q ), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N31 +dffeas \ula_|i2c_loader_|state.Ack ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Ack~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Ack~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hEFE0; +defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N15 +dffeas \ula_|i2c_loader_|thisbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), + .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N17 +dffeas \ula_|i2c_loader_|thisbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) +// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), + .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N19 +dffeas \ula_|i2c_loader_|thisbyte[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), + .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N21 +dffeas \ula_|i2c_loader_|thisbyte[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Stop~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5FCC; +defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), + .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N23 +dffeas \ula_|i2c_loader_|thisbyte[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|Equal2~0_combout ), + .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h30F0; +defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & +// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Done~1_combout )))) + + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Done~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0ACE; +defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Done~2_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hC4FF; +defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~2_combout & (\ula_|i2c_loader_|state.Pause~1_combout )) # +// (!\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) + + .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Pause~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hE2F0; +defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N23 +dffeas \ula_|i2c_loader_|state.Pause ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Pause~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Pause~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( +// Equation(s): +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; +defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N31 +dffeas \ula_|i2c_loader_|state.Start ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Start~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Start .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; +defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N11 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0005; +defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|phase [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; +defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) + + .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Done~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; +defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) + + .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0400; +defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N3 +dffeas \ula_|i2c_loader_|nbit[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF55F; +defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N13 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & !\ula_|i2c_loader_|nbit [0])) + + .dataa(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|nbit [2]), + .datac(gnd), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( +// Equation(s): +// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Done~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Done~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; +defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( +// Equation(s): +// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hE0E0; +defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( +// Equation(s): +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; +defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) + + .dataa(\ula_|i2c_loader_|state~27_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state~26_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Data~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hAFA0; +defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N29 +dffeas \ula_|i2c_loader_|state.Data ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Data~0_combout ), + .asdata(\ula_|i2c_loader_|Mux42~0_combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2c_loader_|state.Start~q ), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Data~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Data .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Stop~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|state.Stop~q ), + .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~0_combout ), .cout()); // synopsys translate_off @@ -56565,7 +54939,7 @@ defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N9 +// Location: FF_X1_Y23_N13 dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|scl_out~2_combout ), @@ -56584,38 +54958,38 @@ defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N28 +// Location: LCCOMB_X1_Y23_N16 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ ((!\ula_|i2c_loader_|state.Start~q )))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # -// ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q & \ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # +// ((\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|scl_out~_Duplicate_1_q )))) - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hD7C2; +defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hBA74; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N8 +// Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|scl_out~1_combout ))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|scl_out~1_combout )) +// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & ((\ula_|i2c_loader_|state.Start~q ))) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|state.Start~q )) .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|scl_out~1_combout ), + .datab(\ula_|i2c_loader_|scl_out~1_combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hF005; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hCC11; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56638,7 +55012,7 @@ defparam \ula_|i2c_loader_|scl_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out .power_up = "high"; // synopsys translate_on -// Location: FF_X1_Y23_N31 +// Location: FF_X1_Y23_N23 dffeas \ula_|i2c_loader_|sda_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|sda_out~4_combout ), @@ -56657,88 +55031,156 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N6 +// Location: LCCOMB_X3_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state.Start~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; +defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte [0] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [2]), .cin(gnd), .combout(\ula_|i2c_loader_|Mux35~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h20A0; +defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h2A00; defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X2_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h001A; +defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h00F0; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|shiftreg~14_combout ))) + + .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~14_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hAABA; +defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: LCCOMB_X3_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3])) +// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0030; +defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0300; defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 +// Location: LCCOMB_X1_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [0] & !\ula_|i2c_loader_|phase [1])) +// \ula_|i2c_loader_|shiftreg[0]~6_combout = (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Data~q )) - .dataa(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|phase [1]), .datab(gnd), .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h00A0; +defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h5000; defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N26 +// Location: LCCOMB_X1_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state~24_combout ) # (\ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) - .dataa(\ula_|i2c_loader_|state~24_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|Mux42~0_combout ), - .datad(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .datad(\ula_|i2c_loader_|state~24_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFFE0; +defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFCF8; defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N20 +// Location: LCCOMB_X1_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|shiftreg[0]~7_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q )) +// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|shiftreg[0]~7_combout )) - .dataa(\ula_|i2c_loader_|shiftreg[0]~7_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h2200; +defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h0C00; defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56761,54 +55203,37 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; -defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N24 +// Location: LCCOMB_X2_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [3]))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte [2]))) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2])))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [4]), + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [2]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hA010; +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hC010; defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N2 +// Location: LCCOMB_X3_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~21_combout ), + .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), + .datab(\ula_|i2c_loader_|shiftreg~4_combout ), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~22_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'hAA08; +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h88C8; defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56829,33 +55254,33 @@ defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N10 +// Location: LCCOMB_X2_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|phase [1]))))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q -// ) # (\ula_|i2c_loader_|state~24_combout )))) +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q +// & (!\ula_|i2c_loader_|state.Start~q ))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state~24_combout ), - .datad(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state~24_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hDC22; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hA6A4; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N24 +// Location: LCCOMB_X2_Y24_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|shiftreg[6]~10_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ))) +// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|shiftreg[6]~10_combout ))) - .dataa(\ula_|i2c_loader_|shiftreg[6]~10_combout ), + .dataa(\ula_|i2c_loader_|phase [0]), .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .cout()); @@ -56883,41 +55308,41 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N20 +// Location: LCCOMB_X2_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) +// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [1]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [3])))) - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(\ula_|i2c_loader_|thisbyte [4]), + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h4070; +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h10B0; defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N22 +// Location: LCCOMB_X3_Y23_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0])) # (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|shiftreg~18_combout )))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .dataa(\ula_|i2c_loader_|thisbyte [0]), .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~18_combout ), + .datac(\ula_|i2c_loader_|shiftreg~18_combout ), + .datad(\ula_|i2c_loader_|shiftreg~4_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h7F5D; +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h74FF; defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N16 +// Location: LCCOMB_X3_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) @@ -56934,7 +55359,7 @@ defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hAF00; defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N17 +// Location: FF_X3_Y23_N3 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~20_combout ), @@ -56953,58 +55378,41 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|thisbyte [2]), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0F00; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N0 +// Location: LCCOMB_X2_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(\ula_|i2c_loader_|thisbyte [4]), - .datac(\ula_|i2c_loader_|thisbyte [2]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h04F4; +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h10BA; defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N2 +// Location: LCCOMB_X3_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|shiftreg~14_combout & ((\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [3] & ((!\ula_|i2c_loader_|shiftreg~14_combout )))) - .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), - .datab(\ula_|i2c_loader_|shiftreg~16_combout ), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|shiftreg~16_combout ), + .datad(\ula_|i2c_loader_|shiftreg~14_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hC5C0; +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hA0E4; defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 +// Location: LCCOMB_X3_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg~17_combout )))) @@ -57021,7 +55429,7 @@ defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hC5C0; defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X3_Y23_N7 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~26_combout ), @@ -57040,58 +55448,24 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [4])) # (!\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4]))))) - - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h0310; -defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|shiftreg~14_combout & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), - .datab(\ula_|i2c_loader_|shiftreg~13_combout ), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hCCDC; -defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N4 +// Location: LCCOMB_X2_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|shiftreg~15_combout )))) +// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|shiftreg [3]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~15_combout ), + .dataa(\ula_|i2c_loader_|shiftreg~15_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|shiftreg [3]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hCFCA; +defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE32; defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N5 +// Location: FF_X2_Y23_N1 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~25_combout ), @@ -57110,7 +55484,7 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N8 +// Location: LCCOMB_X2_Y24_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) @@ -57127,7 +55501,7 @@ defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hEE22; defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N9 +// Location: FF_X2_Y24_N5 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~12_combout ), @@ -57146,24 +55520,24 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 +// Location: LCCOMB_X3_Y23_N18 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) - .dataa(\ula_|i2c_loader_|shiftreg [5]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg [5]), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|Mux35~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hAFA0; +defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hCFC0; defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N11 +// Location: FF_X3_Y23_N19 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~9_combout ), @@ -57182,7 +55556,7 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N28 +// Location: LCCOMB_X3_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( // Equation(s): // \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) @@ -57199,7 +55573,7 @@ defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N29 +// Location: FF_X3_Y23_N5 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), @@ -57218,21 +55592,21 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N26 +// Location: LCCOMB_X2_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|shiftreg [7]))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|state.Data~q & // (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|shiftreg [7]), - .datab(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|shiftreg [7]), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hB8F0; +defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hF870; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57241,67 +55615,67 @@ cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): // \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|sda_out~0_combout ), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|sda_out~0_combout ), .datad(\I2C_SDAT~input_o ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hA0A8; +defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hC0E0; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N4 +// Location: LCCOMB_X1_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h5054; +defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N10 +// Location: LCCOMB_X1_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|sda_out~1_combout )))) # (!\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|phase [0] -// & ((!\ula_|i2c_loader_|sda_out~1_combout ))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )))) +// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase +// [0] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|sda_out~1_combout )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'h8EBA; +defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2AE; defparam \ula_|i2c_loader_|sda_out~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N30 +// Location: LCCOMB_X1_Y23_N22 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~4 ( // Equation(s): // \ula_|i2c_loader_|sda_out~4_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|sda_out~2_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & ((\ula_|i2c_loader_|sda_out~3_combout )))) - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|scl_out~0_combout ), .datac(\ula_|i2c_loader_|sda_out~2_combout ), .datad(\ula_|i2c_loader_|sda_out~3_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1D0C; +defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1B0A; defparam \ula_|i2c_loader_|sda_out~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57324,6 +55698,42 @@ defparam \ula_|i2c_loader_|sda_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out .power_up = "high"; // synopsys translate_on +// Location: LCCOMB_X27_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|mclk_r~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N17 +dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|mclk_r~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + // Location: DDIOOUTCELL_X20_Y34_N25 dffeas \ula_|i2s_intf_|mclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -57343,6 +55753,612 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X29_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) + + .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add0~1_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) +// \ula_|i2s_intf_|Add0~3 = CARRY((!\ula_|i2s_intf_|lrdivider [1] & !\ula_|i2s_intf_|Add0~1_cout )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~1_cout ), + .combout(\ula_|i2s_intf_|Add0~2_combout ), + .cout(\ula_|i2s_intf_|Add0~3 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y23_N29 +dffeas \ula_|i2s_intf_|lrdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) +// \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) + + .dataa(\ula_|i2s_intf_|lrdivider [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~3 ), + .combout(\ula_|i2s_intf_|Add0~4_combout ), + .cout(\ula_|i2s_intf_|Add0~5 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~4_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y23_N7 +dffeas \ula_|i2s_intf_|lrdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) +// \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~5 ), + .combout(\ula_|i2s_intf_|Add0~6_combout ), + .cout(\ula_|i2s_intf_|Add0~7 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N7 +dffeas \ula_|i2s_intf_|lrdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) +// \ula_|i2s_intf_|Add0~9 = CARRY((\ula_|i2s_intf_|lrdivider [4]) # (!\ula_|i2s_intf_|Add0~7 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~7 ), + .combout(\ula_|i2s_intf_|Add0~8_combout ), + .cout(\ula_|i2s_intf_|Add0~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y23_N5 +dffeas \ula_|i2s_intf_|lrdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) +// \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~9 ), + .combout(\ula_|i2s_intf_|Add0~10_combout ), + .cout(\ula_|i2s_intf_|Add0~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~10_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[5]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y23_N3 +dffeas \ula_|i2s_intf_|lrdivider[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) + + .dataa(\ula_|i2s_intf_|lrdivider [2]), + .datab(\ula_|i2s_intf_|lrdivider [4]), + .datac(\ula_|i2s_intf_|lrdivider [3]), + .datad(\ula_|i2s_intf_|lrdivider [5]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) +// \ula_|i2s_intf_|Add0~13 = CARRY((!\ula_|i2s_intf_|Add0~11 ) # (!\ula_|i2s_intf_|lrdivider [6])) + + .dataa(\ula_|i2s_intf_|lrdivider [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~11 ), + .combout(\ula_|i2s_intf_|Add0~12_combout ), + .cout(\ula_|i2s_intf_|Add0~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~12_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N27 +dffeas \ula_|i2s_intf_|lrdivider[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) +// \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) + + .dataa(\ula_|i2s_intf_|lrdivider [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~13 ), + .combout(\ula_|i2s_intf_|Add0~14_combout ), + .cout(\ula_|i2s_intf_|Add0~15 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y23_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~14_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y23_N5 +dffeas \ula_|i2s_intf_|lrdivider[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) +// \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) + + .dataa(\ula_|i2s_intf_|lrdivider [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~15 ), + .combout(\ula_|i2s_intf_|Add0~16_combout ), + .cout(\ula_|i2s_intf_|Add0~17 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h5AAF; +defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Add0~16_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0C0C; +defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N17 +dffeas \ula_|i2s_intf_|lrdivider[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|lrdivider [9]), + .cin(\ula_|i2s_intf_|Add0~17 ), + .combout(\ula_|i2s_intf_|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; +defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~18_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N25 +dffeas \ula_|i2s_intf_|lrdivider[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal0~0_combout = (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [6] & \ula_|i2s_intf_|lrdivider [7]))) + + .dataa(\ula_|i2s_intf_|lrdivider [8]), + .datab(\ula_|i2s_intf_|lrdivider [9]), + .datac(\ula_|i2s_intf_|lrdivider [6]), + .datad(\ula_|i2s_intf_|lrdivider [7]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h4000; +defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( +// Equation(s): +// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) + + .dataa(\ula_|i2s_intf_|Equal0~1_combout ), + .datab(\ula_|i2s_intf_|lrdivider [1]), + .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( +// Equation(s): +// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N25 +dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; +defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X16_Y34_N18 dffeas \ula_|i2s_intf_|lrclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -57381,6 +56397,596 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X31_Y22_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] +// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .cout(\ula_|i2s_intf_|bitcount[0]~6 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; +defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N11 +dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bclk_r~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF0FC; +defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N1 +dffeas \ula_|i2s_intf_|bitcount[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) +// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[0]~6 ), + .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .cout(\ula_|i2s_intf_|bitcount[1]~8 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N3 +dffeas \ula_|i2s_intf_|bitcount[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) +// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[1]~8 ), + .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .cout(\ula_|i2s_intf_|bitcount[2]~10 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N5 +dffeas \ula_|i2s_intf_|bitcount[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) +// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) + + .dataa(\ula_|i2s_intf_|bitcount [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[2]~10 ), + .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .cout(\ula_|i2s_intf_|bitcount[3]~12 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; +defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N7 +dffeas \ula_|i2s_intf_|bitcount[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) + + .dataa(\ula_|i2s_intf_|bitcount [3]), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(\ula_|i2s_intf_|bitcount [2]), + .datad(\ula_|i2s_intf_|bitcount [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [4]), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2s_intf_|bitcount[3]~12 ), + .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; +defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N9 +dffeas \ula_|i2s_intf_|bitcount[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add2~7_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) +// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~7_cout ), + .combout(\ula_|i2s_intf_|Add2~8_combout ), + .cout(\ula_|i2s_intf_|Add2~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; +defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|Add2~8_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1300; +defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N13 +dffeas \ula_|i2s_intf_|bdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) +// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) + + .dataa(\ula_|i2s_intf_|bdivider [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~9 ), + .combout(\ula_|i2s_intf_|Add2~10_combout ), + .cout(\ula_|i2s_intf_|Add2~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Add2~10_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0203; +defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N17 +dffeas \ula_|i2s_intf_|bdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) +// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~11 ), + .combout(\ula_|i2s_intf_|Add2~12_combout ), + .cout(\ula_|i2s_intf_|Add2~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~19_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~12_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|Add2~12_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h1300; +defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N3 +dffeas \ula_|i2s_intf_|bdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(\ula_|i2s_intf_|Add2~13 ), + .combout(\ula_|i2s_intf_|Add2~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; +defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Add2~14_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; +defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N19 +dffeas \ula_|i2s_intf_|bdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & \ula_|i2s_intf_|bdivider [4]))) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(\ula_|i2s_intf_|bdivider [2]), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h1000; +defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~1 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[4]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8A00; +defparam \ula_|i2s_intf_|shiftreg[4]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N13 +dffeas \ula_|i2s_intf_|bdivider[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hF000; +defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h30CF; +defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|bclk_r~0_combout ), + .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00D8; +defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X14_Y34_N18 dffeas \ula_|i2s_intf_|bclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -57400,16 +57006,781 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y13_N29 -dffeas \ula_|pcm_outl[14] ( +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( +// Equation(s): +// \ula_|pcm_outl[13]~feeder_combout = \D[3]~96_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[3]~96_combout ), + .cin(gnd), + .combout(\ula_|pcm_outl[13]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; +defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N2 +cycloneive_lcell_comb \ula_|always0~2 ( +// Equation(s): +// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|always0~2 .lut_mask = 16'h2020; +defparam \ula_|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \ula_|always0~3 ( +// Equation(s): +// \ula_|always0~3_combout = (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|always0~2_combout ), + .cin(gnd), + .combout(\ula_|always0~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|always0~3 .lut_mask = 16'h4000; +defparam \ula_|always0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N25 +dffeas \ula_|pcm_outl[13] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[4]~79_combout ), + .d(\ula_|pcm_outl[13]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|always0~1_combout ), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|pcm_outl [13]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h008A; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y34_N22 +cycloneive_io_ibuf \AUD_ADCDAT~input ( + .i(AUD_ADCDAT), + .ibar(gnd), + .o(\AUD_ADCDAT~input_o )); +// synopsys translate_off +defparam \AUD_ADCDAT~input .bus_hold = "false"; +defparam \AUD_ADCDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # +// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) + + .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [0]), + .datad(\AUD_ADCDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N21 +dffeas \ula_|i2s_intf_|shiftreg[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~18_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~2 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFCF0; +defparam \ula_|i2s_intf_|shiftreg[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N27 +dffeas \ula_|i2s_intf_|shiftreg[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [1] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [1]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N25 +dffeas \ula_|i2s_intf_|shiftreg[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N19 +dffeas \ula_|i2s_intf_|shiftreg[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~15_combout = (\ula_|i2s_intf_|shiftreg [3] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [3]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N1 +dffeas \ula_|i2s_intf_|shiftreg[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~15_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [4]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N11 +dffeas \ula_|i2s_intf_|shiftreg[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~14_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~13_combout = (\ula_|i2s_intf_|shiftreg [5] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(\ula_|i2s_intf_|shiftreg [5]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N17 +dffeas \ula_|i2s_intf_|shiftreg[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~13_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [6]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N31 +dffeas \ula_|i2s_intf_|shiftreg[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [7]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N29 +dffeas \ula_|i2s_intf_|shiftreg[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~11_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~10_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [8]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N23 +dffeas \ula_|i2s_intf_|shiftreg[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~10_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [9]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N13 +dffeas \ula_|i2s_intf_|shiftreg[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~9_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(\ula_|i2s_intf_|shiftreg [10]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N3 +dffeas \ula_|i2s_intf_|shiftreg[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~8_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [11]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N9 +dffeas \ula_|i2s_intf_|shiftreg[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~7_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( +// Equation(s): +// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # +// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) + + .dataa(\ula_|i2s_intf_|shiftreg [14]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N31 +dffeas \ula_|i2s_intf_|PCM_INR[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|PCM_INR [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( +// Equation(s): +// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # +// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) + + .dataa(\ula_|i2s_intf_|shiftreg [14]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|PCM_INL [14]), + .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N29 +dffeas \ula_|i2s_intf_|PCM_INL[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|PCM_INL [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N6 +cycloneive_lcell_comb \ula_|pcm_outr~0 ( +// Equation(s): +// \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datad(\ula_|i2s_intf_|PCM_INL [14]), + .cin(gnd), + .combout(\ula_|pcm_outr~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; +defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N7 +dffeas \ula_|pcm_outl[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|pcm_outr~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|pcm_outl [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [12]), + .datad(\ula_|pcm_outl [12]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N15 +dffeas \ula_|i2s_intf_|shiftreg[13] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [13]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) + + .dataa(gnd), + .datab(\ula_|pcm_outl [13]), + .datac(\ula_|i2s_intf_|shiftreg [13]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCCF0; +defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N5 +dffeas \ula_|i2s_intf_|shiftreg[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N31 +dffeas \ula_|pcm_outl[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\D[4]~98_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|pcm_outl [14]), @@ -57419,24 +57790,24 @@ defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y13_N22 +// Location: LCCOMB_X28_Y22_N4 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|pcm_outl [14]), + .datab(gnd), + .datac(\ula_|pcm_outl [14]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hEE22; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF0AA; defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y13_N23 +// Location: FF_X28_Y22_N5 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~4_combout ), @@ -57445,7 +57816,7 @@ dffeas \ula_|i2s_intf_|shiftreg[15] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [15]), @@ -57455,24 +57826,24 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y13_N24 +// Location: LCCOMB_X28_Y22_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) +// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|shiftreg [15] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), .datac(\ula_|i2s_intf_|shiftreg [15]), - .datad(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h3030; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h00F0; defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y13_N25 +// Location: FF_X28_Y22_N1 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~3_combout ), @@ -57481,7 +57852,7 @@ dffeas \ula_|i2s_intf_|shiftreg[16] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [16]), @@ -57491,20 +57862,20 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y13_N30 +// Location: LCCOMB_X28_Y22_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [16]) +// \ula_|i2s_intf_|shiftreg~0_combout = (\ula_|i2s_intf_|shiftreg [16] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [16]), - .datad(gnd), + .datab(\ula_|i2s_intf_|shiftreg [16]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h3030; +defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h00CC; defparam \ula_|i2s_intf_|shiftreg~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57517,7 +57888,7 @@ dffeas \ula_|i2s_intf_|shiftreg[17] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [17]), @@ -57527,33 +57898,136 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \ula_|border[1]~feeder ( +// Location: LCCOMB_X38_Y33_N8 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( // Equation(s): -// \ula_|border[1]~feeder_combout = \D[1]~31_combout +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [6]))) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[1]~31_combout ), + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [6]), .cin(gnd), - .combout(\ula_|border[1]~feeder_combout ), + .combout(\ula_|video_|LessThan2~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N13 +// Location: LCCOMB_X38_Y33_N4 +cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( +// Equation(s): +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(\ula_|video_|vga_vc [3]), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0111; +defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N30 +cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( +// Equation(s): +// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|vga_vc [4]), + .datac(\ula_|video_|LessThan2~0_combout ), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7050; +defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N16 +cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( +// Equation(s): +// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|LessThan6~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|LessThan6~0_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h5D55; +defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N22 +cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( +// Equation(s): +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [5])) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [6]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0011; +defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N24 +cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( +// Equation(s): +// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((\ula_|video_|LessThan0~0_combout & !\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # +// ((!\ula_|video_|LessThan0~0_combout & \ula_|video_|vga_hc [7])))) + + .dataa(\ula_|video_|LessThan0~0_combout ), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [7]), + .datad(\ula_|video_|vga_hc [9]), + .cin(gnd), + .combout(\ula_|video_|disp_enable~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h3BDC; +defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N2 +cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( +// Equation(s): +// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) + + .dataa(\ula_|video_|LessThan2~1_combout ), + .datab(\ula_|video_|LessThan3~0_combout ), + .datac(gnd), + .datad(\ula_|video_|disp_enable~0_combout ), + .cin(gnd), + .combout(\ula_|video_|disp_enable~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; +defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N11 dffeas \ula_|border[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[1]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[1]~34_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), + .sload(vcc), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|border [1]), @@ -57563,7 +58037,76 @@ defparam \ula_|border[1] .is_wysiwyg = "true"; defparam \ula_|border[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y29_N4 +// Location: LCCOMB_X37_Y33_N8 +cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( +// Equation(s): +// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; +defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N28 +cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( +// Equation(s): +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [5]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; +defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y33_N10 +cycloneive_lcell_comb \ula_|video_|screen_en~0 ( +// Equation(s): +// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|LessThan4~0_combout ), + .datad(\ula_|video_|vga_hc [8]), + .cin(gnd), + .combout(\ula_|video_|screen_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1121; +defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y33_N22 +cycloneive_lcell_comb \ula_|video_|screen_en~1 ( +// Equation(s): +// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # +// (!\ula_|video_|LessThan6~1_combout ))))) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|LessThan6~1_combout ), + .datad(\ula_|video_|screen_en~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; +defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N28 cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -57580,14 +58123,14 @@ defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y30_N10 +// Location: LCCOMB_X34_Y31_N10 cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( // Equation(s): -// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) +// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), .datad(\ula_|video_|vga_hc [0]), .cin(gnd), .combout(\ula_|video_|Decoder0~1_combout ), @@ -57597,7 +58140,7 @@ defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y29_N5 +// Location: FF_X32_Y33_N29 dffeas \ula_|video_|attr_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), @@ -57616,32 +58159,15 @@ defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N4 -cycloneive_lcell_comb \ula_|video_|attr[1]~feeder ( -// Equation(s): -// \ula_|video_|attr[1]~feeder_combout = \ula_|video_|attr_prefetch [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|attr_prefetch [1]), - .cin(gnd), - .combout(\ula_|video_|attr[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y30_N0 +// Location: LCCOMB_X34_Y31_N12 cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( // Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & \ula_|video_|vga_hc [3]))) +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & \ula_|video_|vga_hc [0]))) - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [3]), + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), .cin(gnd), .combout(\ula_|video_|Decoder0~0_combout ), .cout()); @@ -57650,15 +58176,15 @@ defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y31_N5 +// Location: FF_X37_Y33_N27 dffeas \ula_|video_|attr[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr[1]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [1]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -57669,7 +58195,7 @@ defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N0 +// Location: LCCOMB_X32_Y33_N10 cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 @@ -57686,7 +58212,7 @@ defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y30_N1 +// Location: FF_X32_Y33_N11 dffeas \ula_|video_|attr_prefetch[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), @@ -57705,7 +58231,7 @@ defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N15 +// Location: FF_X37_Y33_N13 dffeas \ula_|video_|attr[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -57724,278 +58250,7 @@ defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; defparam \ula_|video_|attr[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N0 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y30_N0 -cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( -// Equation(s): -// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0020; -defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N1 -dffeas \ula_|video_|bits_prefetch[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N7 -dffeas \ula_|video_|bits[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N2 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N3 -dffeas \ula_|video_|bits_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N13 -dffeas \ula_|video_|bits[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y23_N16 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y23_N17 -dffeas \ula_|video_|bits_prefetch[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N25 -dffeas \ula_|video_|bits[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y25_N28 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y25_N29 -dffeas \ula_|video_|bits_prefetch[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N19 -dffeas \ula_|video_|bits[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y31_N18 -cycloneive_lcell_comb \ula_|video_|Mux0~0 ( -// Equation(s): -// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [5]), - .datac(\ula_|video_|bits [7]), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE50; -defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y31_N12 -cycloneive_lcell_comb \ula_|video_|Mux0~1 ( -// Equation(s): -// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [6]), - .datac(\ula_|video_|bits [4]), - .datad(\ula_|video_|Mux0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; -defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y25_N26 +// Location: LCCOMB_X32_Y33_N24 cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58012,7 +58267,7 @@ defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y25_N27 +// Location: FF_X32_Y33_N25 dffeas \ula_|video_|attr_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), @@ -58031,7 +58286,7 @@ defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N27 +// Location: FF_X36_Y33_N5 dffeas \ula_|video_|attr[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58050,24 +58305,24 @@ defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N28 +// Location: LCCOMB_X34_Y33_N22 cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( // Equation(s): -// \ula_|video_|frame[0]~12_combout = \ula_|video_|frame [0] $ (\ula_|video_|Equal3~1_combout ) +// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) - .dataa(gnd), + .dataa(\ula_|video_|Equal3~1_combout ), .datab(gnd), .datac(\ula_|video_|frame [0]), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|frame[0]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h0FF0; +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h5A5A; defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N29 +// Location: FF_X34_Y33_N23 dffeas \ula_|video_|frame[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[0]~12_combout ), @@ -58086,14 +58341,14 @@ defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; defparam \ula_|video_|frame[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N4 +// Location: LCCOMB_X35_Y33_N24 cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( // Equation(s): -// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [1] & (\ula_|video_|frame [0] $ (VCC))) # (!\ula_|video_|frame [1] & (\ula_|video_|frame [0] & VCC)) -// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [1] & \ula_|video_|frame [0])) +// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) +// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [0] & \ula_|video_|frame [1])) - .dataa(\ula_|video_|frame [1]), - .datab(\ula_|video_|frame [0]), + .dataa(\ula_|video_|frame [0]), + .datab(\ula_|video_|frame [1]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -58104,15 +58359,15 @@ defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y30_N13 +// Location: FF_X35_Y33_N25 dffeas \ula_|video_|frame[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[1]~4_combout ), + .d(\ula_|video_|frame[1]~4_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58123,33 +58378,33 @@ defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; defparam \ula_|video_|frame[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N6 +// Location: LCCOMB_X35_Y33_N26 cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( // Equation(s): // \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) // \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - .dataa(gnd), - .datab(\ula_|video_|frame [2]), + .dataa(\ula_|video_|frame [2]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[1]~5 ), .combout(\ula_|video_|frame[2]~6_combout ), .cout(\ula_|video_|frame[2]~7 )); // synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h5A5F; defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N21 +// Location: FF_X35_Y33_N27 dffeas \ula_|video_|frame[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[2]~6_combout ), + .d(\ula_|video_|frame[2]~6_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58160,25 +58415,25 @@ defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; defparam \ula_|video_|frame[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N8 +// Location: LCCOMB_X35_Y33_N28 cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( // Equation(s): // \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) // \ula_|video_|frame[3]~9 = CARRY((\ula_|video_|frame [3] & !\ula_|video_|frame[2]~7 )) - .dataa(\ula_|video_|frame [3]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|frame [3]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[2]~7 ), .combout(\ula_|video_|frame[3]~8_combout ), .cout(\ula_|video_|frame[3]~9 )); // synopsys translate_off -defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X36_Y31_N9 +// Location: FF_X35_Y33_N29 dffeas \ula_|video_|frame[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[3]~8_combout ), @@ -58197,32 +58452,32 @@ defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; defparam \ula_|video_|frame[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N10 +// Location: LCCOMB_X35_Y33_N30 cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( // Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame [4] $ (\ula_|video_|frame[3]~9 ) - .dataa(gnd), + .dataa(\ula_|video_|frame [4]), .datab(gnd), .datac(gnd), - .datad(\ula_|video_|frame [4]), + .datad(gnd), .cin(\ula_|video_|frame[3]~9 ), .combout(\ula_|video_|frame[4]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h5A5A; defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X36_Y31_N17 +// Location: FF_X35_Y33_N31 dffeas \ula_|video_|frame[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[4]~10_combout ), + .d(\ula_|video_|frame[4]~10_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58233,7 +58488,7 @@ defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; defparam \ula_|video_|frame[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N26 +// Location: LCCOMB_X36_Y33_N4 cycloneive_lcell_comb \ula_|video_|inverted ( // Equation(s): // \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) @@ -58250,7 +58505,312 @@ defparam \ula_|video_|inverted .lut_mask = 16'hF000; defparam \ula_|video_|inverted .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y21_N0 +// Location: LCCOMB_X32_Y33_N12 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( +// Equation(s): +// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0008; +defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N13 +dffeas \ula_|video_|bits_prefetch[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N6 +cycloneive_lcell_comb \ula_|video_|bits[6]~feeder ( +// Equation(s): +// \ula_|video_|bits[6]~feeder_combout = \ula_|video_|bits_prefetch [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [6]), + .cin(gnd), + .combout(\ula_|video_|bits[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N7 +dffeas \ula_|video_|bits[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N22 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N23 +dffeas \ula_|video_|bits_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y33_N23 +dffeas \ula_|video_|bits[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N18 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N19 +dffeas \ula_|video_|bits_prefetch[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N18 +cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( +// Equation(s): +// \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [5]), + .cin(gnd), + .combout(\ula_|video_|bits[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N19 +dffeas \ula_|video_|bits[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N0 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N1 +dffeas \ula_|video_|bits_prefetch[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y33_N1 +dffeas \ula_|video_|bits[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N0 +cycloneive_lcell_comb \ula_|video_|Mux0~0 ( +// Equation(s): +// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) + + .dataa(\ula_|video_|bits [5]), + .datab(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|bits [7]), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N22 +cycloneive_lcell_comb \ula_|video_|Mux0~1 ( +// Equation(s): +// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) + + .dataa(\ula_|video_|bits [6]), + .datab(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|bits [4]), + .datad(\ula_|video_|Mux0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N16 cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58267,7 +58827,7 @@ defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y21_N1 +// Location: FF_X32_Y33_N17 dffeas \ula_|video_|bits_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), @@ -58286,15 +58846,32 @@ defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N5 +// Location: LCCOMB_X36_Y33_N12 +cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( +// Equation(s): +// \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [2]), + .cin(gnd), + .combout(\ula_|video_|bits[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N13 dffeas \ula_|video_|bits[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [2]), + .d(\ula_|video_|bits[2]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58305,7 +58882,7 @@ defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y27_N4 +// Location: LCCOMB_X32_Y33_N14 cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -58322,7 +58899,7 @@ defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y27_N5 +// Location: FF_X32_Y33_N15 dffeas \ula_|video_|bits_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), @@ -58341,7 +58918,7 @@ defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N21 +// Location: FF_X36_Y33_N3 dffeas \ula_|video_|bits[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58360,7 +58937,7 @@ defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y29_N6 +// Location: LCCOMB_X32_Y33_N6 cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -58377,7 +58954,7 @@ defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y29_N7 +// Location: FF_X32_Y33_N7 dffeas \ula_|video_|bits_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), @@ -58396,7 +58973,7 @@ defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N24 +// Location: LCCOMB_X36_Y33_N26 cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( // Equation(s): // \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] @@ -58413,7 +58990,7 @@ defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y31_N25 +// Location: FF_X36_Y33_N27 dffeas \ula_|video_|bits[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[1]~feeder_combout ), @@ -58432,24 +59009,24 @@ defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N18 +// Location: LCCOMB_X32_Y33_N4 cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), - .datad(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), .cin(gnd), .combout(\ula_|video_|bits_prefetch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hF0F0; +defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y31_N19 +// Location: FF_X32_Y33_N5 dffeas \ula_|video_|bits_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), @@ -58468,7 +59045,7 @@ defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N3 +// Location: FF_X36_Y33_N25 dffeas \ula_|video_|bits[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58487,58 +59064,58 @@ defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N2 +// Location: LCCOMB_X36_Y33_N24 cycloneive_lcell_comb \ula_|video_|Mux0~2 ( // Equation(s): // \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [1]), + .dataa(\ula_|video_|bits [1]), + .datab(\ula_|video_|vga_hc [1]), .datac(\ula_|video_|bits [3]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE30; defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N20 +// Location: LCCOMB_X36_Y33_N2 cycloneive_lcell_comb \ula_|video_|Mux0~3 ( // Equation(s): // \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [2]), + .dataa(\ula_|video_|bits [2]), + .datab(\ula_|video_|vga_hc [1]), .datac(\ula_|video_|bits [0]), .datad(\ula_|video_|Mux0~2_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF388; defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N28 +// Location: LCCOMB_X36_Y33_N10 cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( // Equation(s): // \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - .dataa(\ula_|video_|Mux0~1_combout ), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|inverted~combout ), + .dataa(\ula_|video_|vga_hc [3]), + .datab(\ula_|video_|inverted~combout ), + .datac(\ula_|video_|Mux0~1_combout ), .datad(\ula_|video_|Mux0~3_combout ), .cin(gnd), .combout(\ula_|video_|cindex[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h1ED2; +defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h369C; defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N14 +// Location: LCCOMB_X37_Y33_N12 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): // \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) @@ -58555,213 +59132,24 @@ defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N4 -cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( -// Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|vga_vc [3]), - .cin(gnd), - .combout(\ula_|video_|LessThan6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0013; -defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N24 -cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( -// Equation(s): -// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan6~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; -defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N30 -cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( -// Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [6])) # (!\ula_|video_|vga_hc [7]) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|LessThan4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; -defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N22 -cycloneive_lcell_comb \ula_|video_|screen_en~0 ( -// Equation(s): -// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|vga_hc [9]), - .datad(\ula_|video_|LessThan4~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1203; -defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N26 -cycloneive_lcell_comb \ula_|video_|screen_en~1 ( -// Equation(s): -// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # -// (!\ula_|video_|LessThan6~1_combout ))))) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(\ula_|video_|LessThan6~1_combout ), - .datac(\ula_|video_|screen_en~0_combout ), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|screen_en~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~1 .lut_mask = 16'hD0B0; -defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N12 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( -// Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N26 -cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( -// Equation(s): -// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|LessThan6~0_combout ), - .datad(\ula_|video_|LessThan2~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7500; -defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N14 -cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( -// Equation(s): -// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|Equal2~0_combout & (\ula_|video_|LessThan6~0_combout & !\ula_|video_|vga_vc [5]))) # (!\ula_|video_|vga_vc [9]) - - .dataa(\ula_|video_|Equal2~0_combout ), - .datab(\ula_|video_|LessThan6~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|vga_vc [9]), - .cin(gnd), - .combout(\ula_|video_|LessThan3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h08FF; -defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N2 -cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( -// Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [6]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|vga_hc [5]), - .cin(gnd), - .combout(\ula_|video_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0003; -defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N28 -cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( -// Equation(s): -// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & -// !\ula_|video_|LessThan0~0_combout )))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [9]), - .datad(\ula_|video_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|disp_enable~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; -defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N16 -cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( -// Equation(s): -// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) - - .dataa(\ula_|video_|LessThan2~1_combout ), - .datab(\ula_|video_|LessThan3~0_combout ), - .datac(gnd), - .datad(\ula_|video_|disp_enable~0_combout ), - .cin(gnd), - .combout(\ula_|video_|disp_enable~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; -defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y31_N22 +// Location: LCCOMB_X37_Y33_N24 cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( // Equation(s): // \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - .dataa(\ula_|border [1]), - .datab(\ula_|video_|cindex[1]~1_combout ), + .dataa(\ula_|video_|disp_enable~1_combout ), + .datab(\ula_|border [1]), .datac(\ula_|video_|screen_en~1_combout ), - .datad(\ula_|video_|disp_enable~1_combout ), + .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hCA00; +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hA808; defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N14 +// Location: LCCOMB_X32_Y33_N26 cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 @@ -58778,7 +59166,7 @@ defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N15 +// Location: FF_X32_Y33_N27 dffeas \ula_|video_|attr_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), @@ -58797,7 +59185,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X35_Y31_N19 +// Location: FF_X38_Y33_N1 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58816,50 +59204,50 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N18 +// Location: LCCOMB_X38_Y33_N0 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): -// \ula_|video_|VGA_B[1]~0_combout = (\ula_|video_|LessThan3~0_combout & (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) +// \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) - .dataa(\ula_|video_|LessThan3~0_combout ), - .datab(\ula_|video_|LessThan2~1_combout ), + .dataa(\ula_|video_|LessThan2~1_combout ), + .datab(\ula_|video_|LessThan3~0_combout ), .datac(\ula_|video_|attr [6]), .datad(\ula_|video_|disp_enable~0_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h2000; +defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N16 +// Location: LCCOMB_X37_Y33_N2 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): -// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[1]~1_combout & \ula_|video_|VGA_B[1]~0_combout )) +// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[1]~1_combout )) .dataa(\ula_|video_|screen_en~1_combout ), - .datab(\ula_|video_|cindex[1]~1_combout ), - .datac(gnd), - .datad(\ula_|video_|VGA_B[1]~0_combout ), + .datab(gnd), + .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8800; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N3 +// Location: FF_X31_Y12_N17 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\D[2]~40_combout ), + .asdata(\D[2]~46_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\ula_|always0~1_combout ), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|border [2]), @@ -58869,7 +59257,7 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y21_N30 +// Location: LCCOMB_X32_Y33_N8 cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58886,7 +59274,7 @@ defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y21_N31 +// Location: FF_X32_Y33_N9 dffeas \ula_|video_|attr_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), @@ -58905,7 +59293,7 @@ defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N11 +// Location: FF_X36_Y33_N21 dffeas \ula_|video_|attr[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58924,7 +59312,7 @@ defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y23_N14 +// Location: LCCOMB_X32_Y33_N30 cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -58941,7 +59329,7 @@ defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y23_N15 +// Location: FF_X32_Y33_N31 dffeas \ula_|video_|attr_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), @@ -58960,7 +59348,7 @@ defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N1 +// Location: FF_X36_Y33_N15 dffeas \ula_|video_|attr[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58979,49 +59367,49 @@ defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N0 +// Location: LCCOMB_X36_Y33_N14 cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( // Equation(s): // \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) - .dataa(\ula_|video_|attr [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|attr [2]), .datac(\ula_|video_|attr [5]), .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N30 +// Location: LCCOMB_X38_Y33_N26 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) .dataa(\ula_|border [2]), - .datab(\ula_|video_|disp_enable~1_combout ), - .datac(\ula_|video_|screen_en~1_combout ), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hC808; +defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hE020; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N24 +// Location: LCCOMB_X36_Y33_N20 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|VGA_B[1]~0_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|screen_en~1_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), .datab(\ula_|video_|cindex[2]~2_combout ), .datac(gnd), - .datad(\ula_|video_|VGA_B[1]~0_combout ), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), .cout()); @@ -59030,33 +59418,16 @@ defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \ula_|border[0]~feeder ( -// Equation(s): -// \ula_|border[0]~feeder_combout = \D[0]~49_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[0]~49_combout ), - .cin(gnd), - .combout(\ula_|border[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N9 +// Location: FF_X32_Y22_N1 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[0]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[0]~58_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), + .sload(vcc), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|border [0]), @@ -59066,7 +59437,7 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y27_N6 +// Location: LCCOMB_X32_Y33_N20 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -59083,7 +59454,7 @@ defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y27_N7 +// Location: FF_X32_Y33_N21 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -59102,15 +59473,32 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y31_N7 +// Location: LCCOMB_X37_Y33_N28 +cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( +// Equation(s): +// \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|attr_prefetch [0]), + .cin(gnd), + .combout(\ula_|video_|attr[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y33_N29 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [0]), + .d(\ula_|video_|attr[0]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59121,15 +59509,32 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X34_Y31_N13 +// Location: LCCOMB_X32_Y33_N2 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N3 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59140,7 +59545,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y31_N9 +// Location: FF_X36_Y33_N29 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59159,49 +59564,49 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N8 +// Location: LCCOMB_X36_Y33_N28 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): // \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) - .dataa(\ula_|video_|attr [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|attr [0]), .datac(\ula_|video_|attr [3]), .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N2 +// Location: LCCOMB_X37_Y33_N30 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) - .dataa(\ula_|border [0]), - .datab(\ula_|video_|cindex[0]~3_combout ), - .datac(\ula_|video_|disp_enable~1_combout ), - .datad(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|video_|disp_enable~1_combout ), + .datab(\ula_|border [0]), + .datac(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hC0A0; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hA808; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y31_N0 +// Location: LCCOMB_X37_Y33_N0 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[0]~3_combout & \ula_|video_|VGA_B[1]~0_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[0]~3_combout )) .dataa(\ula_|video_|screen_en~1_combout ), .datab(gnd), - .datac(\ula_|video_|cindex[0]~3_combout ), - .datad(\ula_|video_|VGA_B[1]~0_combout ), + .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~2_combout ), .cout()); @@ -59210,24 +59615,24 @@ defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N4 +// Location: LCCOMB_X37_Y33_N26 cycloneive_lcell_comb \ula_|video_|Equal0~2 ( // Equation(s): -// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_hc [8] & \ula_|video_|vga_hc [6])) +// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [9] & !\ula_|video_|vga_hc [8])) - .dataa(\ula_|video_|vga_hc [9]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [6]), + .dataa(\ula_|video_|vga_hc [6]), + .datab(\ula_|video_|vga_hc [9]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [8]), .cin(gnd), .combout(\ula_|video_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0500; +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0022; defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y31_N9 +// Location: FF_X37_Y33_N7 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -59246,21 +59651,21 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N8 +// Location: LCCOMB_X37_Y33_N6 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): -// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|VGA_HS~_Duplicate_1_q & \ula_|video_|Equal1~0_combout )))) # (!\ula_|video_|Equal0~2_combout & (((\ula_|video_|VGA_HS~_Duplicate_1_q -// & \ula_|video_|Equal1~0_combout )))) +// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & +// (\ula_|video_|VGA_HS~_Duplicate_1_q ))) .dataa(\ula_|video_|Equal0~2_combout ), - .datab(\ula_|video_|Equal0~1_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|VGA_HS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal0~1_combout ), .cin(gnd), .combout(\ula_|video_|Selector0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector0~0 .lut_mask = 16'hF888; +defparam \ula_|video_|Selector0~0 .lut_mask = 16'hEAC0; defparam \ula_|video_|Selector0~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59283,7 +59688,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y31_N31 +// Location: FF_X34_Y33_N25 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -59302,21 +59707,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N30 +// Location: LCCOMB_X34_Y33_N24 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1]) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|Equal2~2_combout & (((\ula_|video_|VGA_VS~_Duplicate_1_q & -// !\ula_|video_|Equal3~1_combout )))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal3~1_combout & (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1])))) # (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|VGA_VS~_Duplicate_1_q ) # ((\ula_|video_|Equal2~2_combout & +// \ula_|video_|vga_vc [1])))) - .dataa(\ula_|video_|Equal2~2_combout ), - .datab(\ula_|video_|vga_vc [1]), + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Equal2~2_combout ), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'hDC50; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59339,7 +59744,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N30 +// Location: LCCOMB_X47_Y17_N4 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -59356,7 +59761,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N31 +// Location: FF_X47_Y17_N5 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -59375,7 +59780,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X52_Y13_N9 +// Location: FF_X47_Y17_N25 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -59394,7 +59799,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N8 +// Location: LCCOMB_X47_Y17_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -59411,41 +59816,41 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N22 +// Location: LCCOMB_X47_Y17_N26 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(gnd), .datab(gnd), - .datac(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nM1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF55; +defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y16_N4 +// Location: LCCOMB_X23_Y26_N0 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[3]~77_combout $ (\D[4]~79_combout $ (((\ula_|i2s_intf_|PCM_INL [14]) # (\ula_|i2s_intf_|PCM_INR [14])))) +// \ula_|beep~0_combout = \D[4]~98_combout $ (\raw_loader_in~input_o $ (\D[3]~96_combout )) - .dataa(\D[3]~77_combout ), - .datab(\ula_|i2s_intf_|PCM_INL [14]), - .datac(\D[4]~79_combout ), - .datad(\ula_|i2s_intf_|PCM_INR [14]), + .dataa(gnd), + .datab(\D[4]~98_combout ), + .datac(\raw_loader_in~input_o ), + .datad(\D[3]~96_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hA596; +defparam \ula_|beep~0 .lut_mask = 16'hC33C; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y16_N5 +// Location: FF_X23_Y26_N1 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), @@ -59454,7 +59859,7 @@ dffeas \ula_|beep ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|always0~1_combout ), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|beep~q ), diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo index 7fb926a..55e5471 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/31/2022 14:04:24") + (DATE "04/01/2022 18:55:52") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1853:1853:1853) (1919:1919:1919)) - (PORT oe (644:644:644) (703:703:703)) + (PORT i (2109:2109:2109) (2123:2123:2123)) + (PORT oe (1638:1638:1638) (1708:1708:1708)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1537:1537:1537) (1634:1634:1634)) - (PORT oe (2188:2188:2188) (2280:2280:2280)) + (PORT i (2133:2133:2133) (2174:2174:2174)) + (PORT oe (1897:1897:1897) (1931:1931:1931)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1289:1289:1289) (1340:1340:1340)) - (PORT oe (2188:2188:2188) (2280:2280:2280)) + (PORT i (1984:1984:1984) (2083:2083:2083)) + (PORT oe (1897:1897:1897) (1931:1931:1931)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1619:1619:1619) (1697:1697:1697)) - (PORT oe (2381:2381:2381) (2531:2531:2531)) + (PORT i (2218:2218:2218) (2284:2284:2284)) + (PORT oe (2147:2147:2147) (2236:2236:2236)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1337:1337:1337) (1380:1380:1380)) - (PORT oe (2381:2381:2381) (2531:2531:2531)) + (PORT i (2271:2271:2271) (2432:2432:2432)) + (PORT oe (2147:2147:2147) (2236:2236:2236)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1140:1140:1140) (1226:1226:1226)) - (PORT oe (2357:2357:2357) (2509:2509:2509)) + (PORT i (1973:1973:1973) (2011:2011:2011)) + (PORT oe (1910:1910:1910) (2005:2005:2005)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1346:1346:1346) (1430:1430:1430)) - (PORT oe (2357:2357:2357) (2509:2509:2509)) + (PORT i (1640:1640:1640) (1716:1716:1716)) + (PORT oe (1910:1910:1910) (2005:2005:2005)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (912:912:912) (998:998:998)) - (PORT oe (2357:2357:2357) (2509:2509:2509)) + (PORT i (1960:1960:1960) (2148:2148:2148)) + (PORT oe (1910:1910:1910) (2005:2005:2005)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (967:967:967) (1038:1038:1038)) - (PORT oe (2358:2358:2358) (2514:2514:2514)) + (PORT i (976:976:976) (1064:1064:1064)) + (PORT oe (2161:2161:2161) (2266:2266:2266)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1086:1086:1086) (1162:1162:1162)) - (PORT oe (2358:2358:2358) (2514:2514:2514)) + (PORT i (1717:1717:1717) (1803:1803:1803)) + (PORT oe (2161:2161:2161) (2266:2266:2266)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1125:1125:1125) (1197:1197:1197)) - (PORT oe (2572:2572:2572) (2731:2731:2731)) + (PORT i (1939:1939:1939) (1996:1996:1996)) + (PORT oe (2404:2404:2404) (2537:2537:2537)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) (IOPATH oe o (4578:4578:4578) (4159:4159:4159)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1099:1099:1099) (1171:1171:1171)) - (PORT oe (2358:2358:2358) (2514:2514:2514)) + (PORT i (1417:1417:1417) (1462:1462:1462)) + (PORT oe (2161:2161:2161) (2266:2266:2266)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (1576:1576:1576) (1626:1626:1626)) - (PORT oe (2182:2182:2182) (2276:2276:2276)) + (PORT i (2181:2181:2181) (2209:2209:2209)) + (PORT oe (1700:1700:1700) (1736:1736:1736)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (1096:1096:1096) (1169:1169:1169)) - (PORT oe (2572:2572:2572) (2731:2731:2731)) + (PORT i (2231:2231:2231) (2361:2361:2361)) + (PORT oe (2404:2404:2404) (2537:2537:2537)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1418:1418:1418) (1503:1503:1503)) - (PORT oe (2361:2361:2361) (2521:2521:2521)) + (PORT i (1625:1625:1625) (1715:1715:1715)) + (PORT oe (2140:2140:2140) (2250:2250:2250)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1101:1101:1101) (1148:1148:1148)) - (PORT oe (2383:2383:2383) (2521:2521:2521)) + (PORT i (1724:1724:1724) (1854:1854:1854)) + (PORT oe (1916:1916:1916) (1948:1948:1948)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (1099:1099:1099) (1117:1117:1117)) - (PORT oe (2807:2807:2807) (2896:2896:2896)) + (PORT i (1202:1202:1202) (1265:1265:1265)) + (PORT oe (2441:2441:2441) (2523:2523:2523)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (1133:1133:1133) (1158:1158:1158)) - (PORT oe (2742:2742:2742) (2835:2835:2835)) + (PORT i (1216:1216:1216) (1287:1287:1287)) + (PORT oe (2442:2442:2442) (2524:2524:2524)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (1198:1198:1198) (1245:1245:1245)) - (PORT oe (2463:2463:2463) (2537:2537:2537)) + (PORT i (1118:1118:1118) (1163:1163:1163)) + (PORT oe (2137:2137:2137) (2196:2196:2196)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (1153:1153:1153) (1202:1202:1202)) - (PORT oe (2807:2807:2807) (2896:2896:2896)) + (PORT i (1161:1161:1161) (1237:1237:1237)) + (PORT oe (2441:2441:2441) (2523:2523:2523)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (1463:1463:1463) (1514:1514:1514)) - (PORT oe (2461:2461:2461) (2522:2522:2522)) + (PORT i (1455:1455:1455) (1530:1530:1530)) + (PORT oe (2096:2096:2096) (2158:2158:2158)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (953:953:953) (993:993:993)) - (PORT oe (2462:2462:2462) (2536:2536:2536)) + (PORT i (1343:1343:1343) (1352:1352:1352)) + (PORT oe (2136:2136:2136) (2195:2195:2195)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (1327:1327:1327) (1390:1390:1390)) - (PORT oe (2391:2391:2391) (2467:2467:2467)) + (PORT i (1213:1213:1213) (1275:1275:1275)) + (PORT oe (2035:2035:2035) (2069:2069:2069)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (875:875:875) (909:909:909)) - (PORT oe (2767:2767:2767) (2861:2861:2861)) + (PORT i (1131:1131:1131) (1146:1146:1146)) + (PORT oe (2405:2405:2405) (2466:2466:2466)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (1301:1301:1301) (1303:1303:1303)) - (PORT oe (1210:1210:1210) (1309:1309:1309)) + (PORT i (1412:1412:1412) (1417:1417:1417)) + (PORT oe (1643:1643:1643) (1693:1693:1693)) (IOPATH i o (2378:2378:2378) (2455:2455:2455)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1480:1480:1480) (1473:1473:1473)) - (PORT oe (2383:2383:2383) (2521:2521:2521)) + (PORT i (1794:1794:1794) (1688:1688:1688)) + (PORT oe (1916:1916:1916) (1948:1948:1948)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -353,8 +353,8 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (628:628:628) (613:613:613)) - (PORT oe (919:919:919) (1023:1023:1023)) + (PORT i (1533:1533:1533) (1531:1531:1531)) + (PORT oe (1352:1352:1352) (1405:1405:1405)) (IOPATH i o (2502:2502:2502) (2582:2582:2582)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (772:772:772) (757:757:757)) - (PORT oe (676:676:676) (754:754:754)) + (PORT i (1050:1050:1050) (1062:1062:1062)) + (PORT oe (1327:1327:1327) (1369:1369:1369)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -377,7 +377,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1607:1607:1607) (1503:1503:1503)) + (PORT i (1615:1615:1615) (1516:1516:1516)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -392,6 +392,16 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1304:1304:1304) (1340:1340:1340)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_obuf") (INSTANCE AUD_XCK\~output) @@ -442,7 +452,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1198:1198:1198) (1239:1239:1239)) + (PORT i (1164:1164:1164) (1204:1204:1204)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -452,7 +462,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1239:1239:1239) (1278:1278:1278)) + (PORT i (1073:1073:1073) (1104:1104:1104)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -462,7 +472,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (530:530:530) (528:528:528)) + (PORT i (774:774:774) (751:751:751)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -472,7 +482,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1168:1168:1168) (1217:1217:1217)) + (PORT i (986:986:986) (968:968:968)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -482,7 +492,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (855:855:855) (854:854:854)) + (PORT i (972:972:972) (958:958:958)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -492,7 +502,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (822:822:822) (804:804:804)) + (PORT i (721:721:721) (699:699:699)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -502,7 +512,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1071:1071:1071) (1094:1094:1094)) + (PORT i (843:843:843) (812:812:812)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -512,7 +522,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1071:1071:1071) (1094:1094:1094)) + (PORT i (843:843:843) (812:812:812)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -522,7 +532,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (743:743:743) (735:735:735)) + (PORT i (717:717:717) (702:702:702)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) ) ) @@ -532,7 +542,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (509:509:509) (504:504:504)) + (PORT i (692:692:692) (667:667:667)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -542,7 +552,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1044:1044:1044) (1021:1021:1021)) + (PORT i (952:952:952) (940:940:940)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -552,7 +562,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1424:1424:1424) (1395:1395:1395)) + (PORT i (1378:1378:1378) (1350:1350:1350)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -580,7 +590,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (1273:1273:1273) (1178:1178:1178)) + (PORT i (2048:2048:2048) (1957:1957:1957)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -590,7 +600,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (630:630:630) (599:599:599)) + (PORT i (1307:1307:1307) (1281:1281:1281)) (IOPATH i o (4127:4127:4127) (4477:4477:4477)) ) ) @@ -600,7 +610,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (310:310:310) (317:317:317)) + (PORT i (927:927:927) (923:923:923)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -610,7 +620,7 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (1794:1794:1794) (1912:1912:1912)) + (PORT i (1348:1348:1348) (1373:1373:1373)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -724,7 +734,20 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (752:752:752) (781:781:781)) + (PORT inclk[0] (716:716:716) (747:747:747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1158:1158:1158)) + (PORT datad (1110:1110:1110) (1159:1159:1159)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -733,13 +756,10589 @@ (INSTANCE z80_\|sequencer_\|ena_M) (DELAY (ABSOLUTE - (PORT datac (900:900:900) (935:935:935)) - (PORT datad (855:855:855) (910:910:910)) + (PORT datac (1094:1094:1094) (1132:1132:1132)) + (PORT datad (1106:1106:1106) (1160:1160:1160)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE KEY\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (481:481:481) (733:733:733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (490:490:490)) + (PORT datad (1994:1994:1994) (2109:2109:2109)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|nmi_armed) + (DELAY + (ABSOLUTE + (PORT clk (1476:1476:1476) (1490:1490:1490)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1325:1325:1325) (1320:1320:1320)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (790:790:790) (826:826:826)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT datac (243:243:243) (323:323:323)) + (PORT datad (252:252:252) (325:325:325)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2418:2418:2418) (2567:2567:2567)) + (PORT datab (2411:2411:2411) (2541:2541:2541)) + (PORT datad (1577:1577:1577) (1737:1737:1737)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1160:1160:1160)) + (PORT datab (408:408:408) (481:481:481)) + (PORT datad (1111:1111:1111) (1161:1161:1161)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1355:1355:1355) (1381:1381:1381)) + (PORT datab (1537:1537:1537) (1647:1647:1647)) + (PORT datac (1348:1348:1348) (1441:1441:1441)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1178:1178:1178)) + (PORT datab (413:413:413) (488:488:488)) + (PORT datad (1104:1104:1104) (1156:1156:1156)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (DELAY + (ABSOLUTE + (PORT datab (393:393:393) (466:466:466)) + (PORT datad (667:667:667) (742:742:742)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) + (DELAY + (ABSOLUTE + (PORT datab (2598:2598:2598) (2742:2742:2742)) + (PORT datad (1607:1607:1607) (1729:1729:1729)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1365:1365:1365) (1484:1484:1484)) + (PORT datad (1197:1197:1197) (1317:1317:1317)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1675:1675:1675) (1712:1712:1712)) + (PORT datab (945:945:945) (983:983:983)) + (PORT datac (2134:2134:2134) (2287:2287:2287)) + (PORT datad (1162:1162:1162) (1232:1232:1232)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT datac (1459:1459:1459) (1537:1537:1537)) + (PORT datad (2262:2262:2262) (2332:2332:2332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1246:1246:1246) (1343:1343:1343)) + (PORT datab (1671:1671:1671) (1786:1786:1786)) + (PORT datac (906:906:906) (959:959:959)) + (PORT datad (943:943:943) (998:998:998)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (1739:1739:1739) (1786:1786:1786)) + (PORT datab (1426:1426:1426) (1455:1455:1455)) + (PORT datac (846:846:846) (882:882:882)) + (PORT datad (789:789:789) (792:792:792)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1224:1224:1224) (1329:1329:1329)) + (PORT datab (2644:2644:2644) (2764:2764:2764)) + (PORT datac (844:844:844) (879:879:879)) + (PORT datad (972:972:972) (1035:1035:1035)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1588:1588:1588) (1563:1563:1563)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (808:808:808)) + (PORT datab (1233:1233:1233) (1347:1347:1347)) + (PORT datac (988:988:988) (1067:1067:1067)) + (PORT datad (1323:1323:1323) (1441:1441:1441)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2337:2337:2337) (2490:2490:2490)) + (PORT datab (1667:1667:1667) (1786:1786:1786)) + (PORT datac (905:905:905) (957:957:957)) + (PORT datad (672:672:672) (720:720:720)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (DELAY + (ABSOLUTE + (PORT dataa (1761:1761:1761) (1838:1838:1838)) + (PORT datab (839:839:839) (854:854:854)) + (PORT datac (1396:1396:1396) (1420:1420:1420)) + (PORT datad (2042:2042:2042) (2106:2106:2106)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instED) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1588:1588:1588) (1563:1563:1563)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (810:810:810)) + (PORT datac (981:981:981) (1058:1058:1058)) + (PORT datad (1323:1323:1323) (1434:1434:1434)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2169:2169:2169) (2327:2327:2327)) + (PORT datac (1460:1460:1460) (1537:1537:1537)) + (PORT datad (2263:2263:2263) (2329:2329:2329)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (636:636:636)) + (PORT datab (1050:1050:1050) (1169:1169:1169)) + (PORT datac (1337:1337:1337) (1469:1469:1469)) + (PORT datad (915:915:915) (959:959:959)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT datab (997:997:997) (1105:1105:1105)) + (PORT datac (656:656:656) (719:719:719)) + (PORT datad (1244:1244:1244) (1328:1328:1328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1410:1410:1410) (1499:1499:1499)) + (PORT datab (1489:1489:1489) (1614:1614:1614)) + (PORT datac (1433:1433:1433) (1524:1524:1524)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (809:809:809)) + (PORT datab (1233:1233:1233) (1347:1347:1347)) + (PORT datac (989:989:989) (1067:1067:1067)) + (PORT datad (1323:1323:1323) (1441:1441:1441)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1301:1301:1301)) + (PORT datab (1273:1273:1273) (1368:1368:1368)) + (PORT datad (711:711:711) (773:773:773)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2639:2639:2639) (2814:2814:2814)) + (PORT datab (899:899:899) (934:934:934)) + (PORT datac (1110:1110:1110) (1167:1167:1167)) + (PORT datad (1150:1150:1150) (1194:1194:1194)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (1033:1033:1033)) + (PORT datab (1561:1561:1561) (1662:1662:1662)) + (PORT datac (1411:1411:1411) (1476:1476:1476)) + (PORT datad (201:201:201) (238:238:238)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1239:1239:1239)) + (PORT datad (2109:2109:2109) (2254:2254:2254)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1149:1149:1149)) + (PORT datab (1113:1113:1113) (1123:1123:1123)) + (PORT datac (333:333:333) (359:359:359)) + (PORT datad (689:689:689) (743:743:743)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datac (1439:1439:1439) (1545:1545:1545)) + (PORT datad (1464:1464:1464) (1551:1551:1551)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1247:1247:1247) (1335:1335:1335)) + (PORT datab (1669:1669:1669) (1782:1782:1782)) + (PORT datac (1700:1700:1700) (1785:1785:1785)) + (PORT datad (944:944:944) (1001:1001:1001)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT datac (1974:1974:1974) (2154:2154:2154)) + (PORT datad (1235:1235:1235) (1306:1306:1306)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1939:1939:1939) (2060:2060:2060)) + (PORT datac (2560:2560:2560) (2661:2661:2661)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (937:937:937)) + (PORT datab (1029:1029:1029) (1093:1093:1093)) + (PORT datac (849:849:849) (913:913:913)) + (PORT datad (929:929:929) (973:973:973)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~1) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (941:941:941)) + (PORT datab (898:898:898) (917:917:917)) + (PORT datac (919:919:919) (1011:1011:1011)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (940:940:940)) + (PORT datab (901:901:901) (913:913:913)) + (PORT datac (920:920:920) (1009:1009:1009)) + (PORT datad (1166:1166:1166) (1216:1216:1216)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (896:896:896)) + (PORT datac (977:977:977) (1048:1048:1048)) + (PORT datad (1170:1170:1170) (1184:1184:1184)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2169:2169:2169) (2322:2322:2322)) + (PORT datac (1461:1461:1461) (1534:1534:1534)) + (PORT datad (2261:2261:2261) (2326:2326:2326)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (972:972:972)) + (PORT datab (1721:1721:1721) (1812:1812:1812)) + (PORT datac (1148:1148:1148) (1153:1153:1153)) + (PORT datad (650:650:650) (690:690:690)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (975:975:975)) + (PORT datab (2317:2317:2317) (2471:2471:2471)) + (PORT datac (1702:1702:1702) (1788:1788:1788)) + (PORT datad (669:669:669) (716:716:716)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1211:1211:1211) (1331:1331:1331)) + (PORT datab (2075:2075:2075) (2256:2256:2256)) + (PORT datac (862:862:862) (881:881:881)) + (PORT datad (1458:1458:1458) (1561:1561:1561)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT datab (1418:1418:1418) (1489:1489:1489)) + (PORT datac (1562:1562:1562) (1631:1631:1631)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~6) + (DELAY + (ABSOLUTE + (PORT datac (1595:1595:1595) (1686:1686:1686)) + (PORT datad (1897:1897:1897) (2018:2018:2018)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~9) + (DELAY + (ABSOLUTE + (PORT datac (1033:1033:1033) (1103:1103:1103)) + (PORT datad (985:985:985) (1046:1046:1046)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1060:1060:1060)) + (PORT datab (989:989:989) (1052:1052:1052)) + (PORT datac (903:903:903) (941:941:941)) + (PORT datad (2055:2055:2055) (2108:2108:2108)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (461:461:461)) + (PORT datab (1160:1160:1160) (1195:1195:1195)) + (PORT datac (623:623:623) (685:685:685)) + (PORT datad (1108:1108:1108) (1138:1138:1138)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal44\~0) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (810:810:810)) + (PORT datab (1238:1238:1238) (1352:1352:1352)) + (PORT datac (982:982:982) (1059:1059:1059)) + (PORT datad (1323:1323:1323) (1435:1435:1435)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~16) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1074:1074:1074)) + (PORT datab (1336:1336:1336) (1358:1358:1358)) + (PORT datac (931:931:931) (1016:1016:1016)) + (PORT datad (1108:1108:1108) (1132:1132:1132)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT datab (836:836:836) (897:897:897)) + (PORT datac (619:619:619) (671:671:671)) + (PORT datad (213:213:213) (245:245:245)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal50\~0) + (DELAY + (ABSOLUTE + (PORT datab (998:998:998) (1107:1107:1107)) + (PORT datac (656:656:656) (717:717:717)) + (PORT datad (1193:1193:1193) (1255:1255:1255)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1300:1300:1300)) + (PORT datab (1273:1273:1273) (1368:1368:1368)) + (PORT datad (711:711:711) (773:773:773)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~17) + (DELAY + (ABSOLUTE + (PORT dataa (967:967:967) (1063:1063:1063)) + (PORT datab (1112:1112:1112) (1107:1107:1107)) + (PORT datac (928:928:928) (1011:1011:1011)) + (PORT datad (1085:1085:1085) (1082:1082:1082)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datac (1607:1607:1607) (1722:1722:1722)) + (PORT datad (984:984:984) (1047:1047:1047)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (674:674:674)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (199:199:199) (237:237:237)) + (PORT datad (1103:1103:1103) (1112:1112:1112)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1593:1593:1593) (1671:1671:1671)) + (PORT datab (1420:1420:1420) (1492:1492:1492)) + (PORT datac (372:372:372) (399:399:399)) + (PORT datad (1786:1786:1786) (1904:1904:1904)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1089:1089:1089) (1107:1107:1107)) + (PORT datab (236:236:236) (282:282:282)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1399:1399:1399)) + (PORT datab (1499:1499:1499) (1604:1604:1604)) + (PORT datac (1460:1460:1460) (1551:1551:1551)) + (PORT datad (2054:2054:2054) (2222:2222:2222)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1586:1586:1586) (1563:1563:1563)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (960:960:960)) + (PORT datac (643:643:643) (708:708:708)) + (PORT datad (1365:1365:1365) (1481:1481:1481)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1368:1368:1368)) + (PORT datab (463:463:463) (524:524:524)) + (PORT datac (1699:1699:1699) (1754:1754:1754)) + (PORT datad (267:267:267) (321:321:321)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (805:805:805)) + (PORT datab (1019:1019:1019) (1101:1101:1101)) + (PORT datac (676:676:676) (769:769:769)) + (PORT datad (1322:1322:1322) (1435:1435:1435)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1717:1717:1717)) + (PORT datab (1533:1533:1533) (1585:1585:1585)) + (PORT datac (1709:1709:1709) (1830:1830:1830)) + (PORT datad (1494:1494:1494) (1626:1626:1626)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1299:1299:1299) (1388:1388:1388)) + (PORT datab (1243:1243:1243) (1323:1323:1323)) + (PORT datac (1034:1034:1034) (1082:1082:1082)) + (PORT datad (1678:1678:1678) (1738:1738:1738)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT datac (685:685:685) (734:734:734)) + (PORT datad (1734:1734:1734) (1851:1851:1851)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (666:666:666)) + (PORT datac (1102:1102:1102) (1151:1151:1151)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (252:252:252)) + (PORT datab (244:244:244) (291:291:291)) + (PORT datac (669:669:669) (688:688:688)) + (PORT datad (2054:2054:2054) (2107:2107:2107)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1065:1065:1065)) + (PORT datab (1219:1219:1219) (1281:1281:1281)) + (PORT datac (688:688:688) (740:740:740)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1031:1031:1031)) + (PORT datab (1557:1557:1557) (1661:1661:1661)) + (PORT datac (1407:1407:1407) (1474:1474:1474)) + (PORT datad (203:203:203) (238:238:238)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (386:386:386)) + (PORT datac (902:902:902) (964:964:964)) + (PORT datad (928:928:928) (984:984:984)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1762:1762:1762) (1872:1872:1872)) + (PORT datac (1146:1146:1146) (1226:1226:1226)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (664:664:664)) + (PORT datab (1178:1178:1178) (1215:1215:1215)) + (PORT datac (934:934:934) (1030:1030:1030)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (723:723:723)) + (PORT datab (653:653:653) (674:674:674)) + (PORT datac (936:936:936) (1036:1036:1036)) + (PORT datad (898:898:898) (943:943:943)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (958:958:958)) + (PORT datab (1199:1199:1199) (1222:1222:1222)) + (PORT datac (1813:1813:1813) (1890:1890:1890)) + (PORT datad (871:871:871) (910:910:910)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1687:1687:1687) (1746:1746:1746)) + (PORT datac (1659:1659:1659) (1737:1737:1737)) + (PORT datad (1165:1165:1165) (1209:1209:1209)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datac (826:826:826) (880:880:880)) + (PORT datad (900:900:900) (971:971:971)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1685:1685:1685) (1750:1750:1750)) + (PORT datab (1691:1691:1691) (1776:1776:1776)) + (PORT datac (1479:1479:1479) (1575:1575:1575)) + (PORT datad (1244:1244:1244) (1311:1311:1311)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1537:1537:1537)) + (PORT datab (1233:1233:1233) (1318:1318:1318)) + (PORT datac (1424:1424:1424) (1514:1514:1514)) + (PORT datad (825:825:825) (838:838:838)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (914:914:914)) + (PORT datab (1241:1241:1241) (1279:1279:1279)) + (PORT datac (1377:1377:1377) (1384:1384:1384)) + (PORT datad (1263:1263:1263) (1301:1301:1301)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (657:657:657)) + (PORT datab (963:963:963) (1059:1059:1059)) + (PORT datad (1154:1154:1154) (1176:1176:1176)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1565:1565:1565) (1659:1659:1659)) + (PORT datab (982:982:982) (1039:1039:1039)) + (PORT datac (1634:1634:1634) (1749:1749:1749)) + (PORT datad (1216:1216:1216) (1293:1293:1293)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1460:1460:1460) (1559:1559:1559)) + (PORT datab (1540:1540:1540) (1676:1676:1676)) + (PORT datac (1379:1379:1379) (1439:1439:1439)) + (PORT datad (1566:1566:1566) (1596:1596:1596)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (913:913:913)) + (PORT datab (1819:1819:1819) (1900:1900:1900)) + (PORT datac (867:867:867) (883:883:883)) + (PORT datad (1475:1475:1475) (1552:1552:1552)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1220:1220:1220) (1307:1307:1307)) + (PORT datac (948:948:948) (1024:1024:1024)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (969:969:969)) + (PORT datab (936:936:936) (992:992:992)) + (PORT datac (1633:1633:1633) (1753:1753:1753)) + (PORT datad (1215:1215:1215) (1294:1294:1294)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT datac (1720:1720:1720) (1792:1792:1792)) + (PORT datad (2039:2039:2039) (2100:2100:2100)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (1158:1158:1158) (1201:1201:1201)) + (PORT datac (1618:1618:1618) (1607:1607:1607)) + (PORT datad (1454:1454:1454) (1538:1538:1538)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1564:1564:1564) (1657:1657:1657)) + (PORT datab (978:978:978) (1038:1038:1038)) + (PORT datac (1634:1634:1634) (1759:1759:1759)) + (PORT datad (1220:1220:1220) (1302:1302:1302)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2169:2169:2169) (2326:2326:2326)) + (PORT datab (948:948:948) (988:988:988)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (416:416:416) (461:461:461)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (500:500:500)) + (PORT datab (942:942:942) (982:982:982)) + (PORT datac (2138:2138:2138) (2282:2282:2282)) + (PORT datad (1141:1141:1141) (1176:1176:1176)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (504:504:504)) + (PORT datab (946:946:946) (982:982:982)) + (PORT datac (2134:2134:2134) (2284:2284:2284)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal38\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1627:1627:1627) (1717:1717:1717)) + (PORT datab (1533:1533:1533) (1663:1663:1663)) + (PORT datac (1709:1709:1709) (1827:1827:1827)) + (PORT datad (1445:1445:1445) (1492:1492:1492)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1114:1114:1114) (1137:1137:1137)) + (PORT datab (1107:1107:1107) (1172:1172:1172)) + (PORT datac (580:580:580) (611:611:611)) + (PORT datad (895:895:895) (945:945:945)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (927:927:927)) + (PORT datab (1362:1362:1362) (1426:1426:1426)) + (PORT datac (584:584:584) (617:617:617)) + (PORT datad (583:583:583) (602:602:602)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datab (1940:1940:1940) (2011:2011:2011)) + (PORT datac (1163:1163:1163) (1222:1222:1222)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (507:507:507)) + (PORT datab (949:949:949) (988:988:988)) + (PORT datac (2135:2135:2135) (2282:2282:2282)) + (PORT datad (364:364:364) (385:385:385)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1360:1360:1360)) + (PORT datab (1193:1193:1193) (1242:1242:1242)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (1264:1264:1264) (1365:1365:1365)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (717:717:717)) + (PORT datab (639:639:639) (661:661:661)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (1158:1158:1158) (1203:1203:1203)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (959:959:959)) + (PORT datab (231:231:231) (282:282:282)) + (PORT datac (629:629:629) (651:651:651)) + (PORT datad (649:649:649) (681:681:681)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (1447:1447:1447) (1493:1493:1493)) + (PORT datab (1229:1229:1229) (1315:1315:1315)) + (PORT datac (680:680:680) (717:717:717)) + (PORT datad (1141:1141:1141) (1161:1161:1161)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (708:708:708) (759:759:759)) + (PORT datab (1141:1141:1141) (1169:1169:1169)) + (PORT datac (1819:1819:1819) (1896:1896:1896)) + (PORT datad (588:588:588) (613:613:613)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1461:1461:1461) (1560:1560:1560)) + (PORT datab (1137:1137:1137) (1179:1179:1179)) + (PORT datac (1192:1192:1192) (1287:1287:1287)) + (PORT datad (655:655:655) (686:686:686)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1468:1468:1468) (1566:1566:1566)) + (PORT datab (683:683:683) (725:725:725)) + (PORT datac (1193:1193:1193) (1278:1278:1278)) + (PORT datad (1406:1406:1406) (1445:1445:1445)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|M5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1173:1173:1173)) + (PORT datab (267:267:267) (350:350:350)) + (PORT datad (1104:1104:1104) (1160:1160:1160)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|M5) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) + (DELAY + (ABSOLUTE + (PORT datab (1589:1589:1589) (1719:1719:1719)) + (PORT datac (2606:2606:2606) (2704:2704:2704)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~29) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (665:665:665)) + (PORT datab (931:931:931) (978:978:978)) + (PORT datac (1004:1004:1004) (1061:1061:1061)) + (PORT datad (662:662:662) (691:691:691)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1946:1946:1946) (2050:2050:2050)) + (PORT datab (687:687:687) (729:729:729)) + (PORT datac (658:658:658) (709:709:709)) + (PORT datad (585:585:585) (615:615:615)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1904:1904:1904) (1999:1999:1999)) + (PORT datab (898:898:898) (961:961:961)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (187:187:187) (219:219:219)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1371:1371:1371)) + (PORT datab (464:464:464) (522:522:522)) + (PORT datac (1696:1696:1696) (1755:1755:1755)) + (PORT datad (268:268:268) (323:323:323)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1481:1481:1481)) + (PORT datab (934:934:934) (992:992:992)) + (PORT datac (958:958:958) (990:990:990)) + (PORT datad (1201:1201:1201) (1318:1318:1318)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1071:1071:1071)) + (PORT datab (1335:1335:1335) (1360:1360:1360)) + (PORT datac (927:927:927) (1015:1015:1015)) + (PORT datad (1107:1107:1107) (1130:1130:1130)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (679:679:679)) + (PORT datab (1262:1262:1262) (1301:1301:1301)) + (PORT datac (566:566:566) (573:573:573)) + (PORT datad (1626:1626:1626) (1701:1701:1701)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (708:708:708) (808:808:808)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (255:255:255) (343:343:343)) + (PORT datad (881:881:881) (941:941:941)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (933:933:933)) + (PORT datab (1109:1109:1109) (1175:1175:1175)) + (PORT datac (1089:1089:1089) (1121:1121:1121)) + (PORT datad (673:673:673) (713:713:713)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (492:492:492)) + (PORT datab (1938:1938:1938) (2051:2051:2051)) + (PORT datac (1035:1035:1035) (1084:1084:1084)) + (PORT datad (1561:1561:1561) (1612:1612:1612)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (1000:1000:1000)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (895:895:895) (945:945:945)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (683:683:683)) + (PORT datab (1196:1196:1196) (1213:1213:1213)) + (PORT datac (208:208:208) (248:248:248)) + (PORT datad (624:624:624) (642:642:642)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (458:458:458)) + (PORT datab (1170:1170:1170) (1201:1201:1201)) + (PORT datac (620:620:620) (684:684:684)) + (PORT datad (1113:1113:1113) (1142:1142:1142)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1626:1626:1626) (1717:1717:1717)) + (PORT datab (1533:1533:1533) (1584:1584:1584)) + (PORT datac (1703:1703:1703) (1827:1827:1827)) + (PORT datad (1490:1490:1490) (1625:1625:1625)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1719:1719:1719)) + (PORT datab (1534:1534:1534) (1581:1581:1581)) + (PORT datac (1711:1711:1711) (1826:1826:1826)) + (PORT datad (1494:1494:1494) (1620:1620:1620)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1688:1688:1688) (1727:1727:1727)) + (PORT datab (1470:1470:1470) (1564:1564:1564)) + (PORT datac (2563:2563:2563) (2660:2660:2660)) + (PORT datad (1901:1901:1901) (2013:2013:2013)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (682:682:682)) + (PORT datab (1262:1262:1262) (1302:1302:1302)) + (PORT datac (1116:1116:1116) (1135:1135:1135)) + (PORT datad (553:553:553) (571:571:571)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1370:1370:1370)) + (PORT datab (464:464:464) (521:521:521)) + (PORT datac (1697:1697:1697) (1755:1755:1755)) + (PORT datad (267:267:267) (323:323:323)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1153:1153:1153)) + (PORT datab (1145:1145:1145) (1184:1184:1184)) + (PORT datac (548:548:548) (563:563:563)) + (PORT datad (609:609:609) (634:634:634)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (358:358:358)) + (PORT datab (465:465:465) (519:519:519)) + (PORT datac (191:191:191) (223:223:223)) + (PORT datad (1368:1368:1368) (1479:1479:1479)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal46\~0) + (DELAY + (ABSOLUTE + (PORT dataa (286:286:286) (382:382:382)) + (PORT datab (952:952:952) (1018:1018:1018)) + (PORT datac (903:903:903) (963:963:963)) + (PORT datad (1192:1192:1192) (1312:1312:1312)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1367:1367:1367)) + (PORT datab (866:866:866) (891:891:891)) + (PORT datac (1704:1704:1704) (1755:1755:1755)) + (PORT datad (263:263:263) (316:316:316)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2111:2111:2111) (2254:2254:2254)) + (PORT datab (2048:2048:2048) (2161:2161:2161)) + (PORT datac (986:986:986) (1043:1043:1043)) + (PORT datad (1210:1210:1210) (1253:1253:1253)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1380:1380:1380) (1424:1424:1424)) + (PORT datab (1059:1059:1059) (1143:1143:1143)) + (PORT datac (754:754:754) (762:762:762)) + (PORT datad (1235:1235:1235) (1269:1269:1269)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1061:1061:1061)) + (PORT datac (1148:1148:1148) (1203:1203:1203)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (369:369:369)) + (PORT datab (465:465:465) (518:518:518)) + (PORT datac (1197:1197:1197) (1289:1289:1289)) + (PORT datad (1363:1363:1363) (1476:1476:1476)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1248:1248:1248)) + (PORT datab (2197:2197:2197) (2296:2296:2296)) + (PORT datac (1334:1334:1334) (1445:1445:1445)) + (PORT datad (959:959:959) (1022:1022:1022)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1792:1792:1792) (1883:1883:1883)) + (PORT datab (1288:1288:1288) (1337:1337:1337)) + (PORT datac (1377:1377:1377) (1384:1384:1384)) + (PORT datad (883:883:883) (905:905:905)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (635:635:635)) + (PORT datac (550:550:550) (559:559:559)) + (PORT datad (1232:1232:1232) (1290:1290:1290)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (861:861:861) (876:876:876)) + (PORT datad (848:848:848) (889:889:889)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) + (DELAY + (ABSOLUTE + (PORT datac (2061:2061:2061) (2184:2184:2184)) + (PORT datad (959:959:959) (1014:1014:1014)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1615:1615:1615) (1714:1714:1714)) + (PORT datab (1532:1532:1532) (1580:1580:1580)) + (PORT datac (1706:1706:1706) (1825:1825:1825)) + (PORT datad (1489:1489:1489) (1621:1621:1621)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (717:717:717)) + (PORT datab (1494:1494:1494) (1553:1553:1553)) + (PORT datac (1138:1138:1138) (1205:1205:1205)) + (PORT datad (1383:1383:1383) (1432:1432:1432)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (2148:2148:2148) (2325:2325:2325)) + (PORT datab (675:675:675) (746:746:746)) + (PORT datac (1715:1715:1715) (1794:1794:1794)) + (PORT datad (205:205:205) (235:235:235)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1299:1299:1299) (1399:1399:1399)) + (PORT datad (2046:2046:2046) (2211:2211:2211)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (999:999:999)) + (PORT datab (454:454:454) (482:482:482)) + (PORT datac (408:408:408) (448:448:448)) + (PORT datad (1564:1564:1564) (1622:1622:1622)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (651:651:651)) + (PORT datab (1155:1155:1155) (1200:1200:1200)) + (PORT datac (1451:1451:1451) (1502:1502:1502)) + (PORT datad (337:337:337) (358:358:358)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) + (DELAY + (ABSOLUTE + (PORT datac (1520:1520:1520) (1613:1613:1613)) + (PORT datad (1159:1159:1159) (1225:1225:1225)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1261:1261:1261) (1371:1371:1371)) + (PORT datab (865:865:865) (889:889:889)) + (PORT datac (1688:1688:1688) (1749:1749:1749)) + (PORT datad (267:267:267) (323:323:323)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1371:1371:1371)) + (PORT datab (465:465:465) (519:519:519)) + (PORT datac (1689:1689:1689) (1752:1752:1752)) + (PORT datad (268:268:268) (320:320:320)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1420:1420:1420) (1451:1451:1451)) + (PORT datab (1101:1101:1101) (1122:1122:1122)) + (PORT datac (1072:1072:1072) (1084:1084:1084)) + (PORT datad (939:939:939) (973:973:973)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (719:719:719)) + (PORT datab (1167:1167:1167) (1240:1240:1240)) + (PORT datac (1455:1455:1455) (1509:1509:1509)) + (PORT datad (1468:1468:1468) (1520:1520:1520)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (420:420:420)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (623:623:623) (666:666:666)) + (PORT datad (189:189:189) (220:220:220)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (593:593:593)) + (PORT datab (860:860:860) (886:886:886)) + (PORT datac (854:854:854) (889:889:889)) + (PORT datad (805:805:805) (822:822:822)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1163:1163:1163)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (186:186:186) (228:228:228)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (483:483:483)) + (PORT datab (1218:1218:1218) (1272:1272:1272)) + (PORT datac (679:679:679) (709:709:709)) + (PORT datad (1295:1295:1295) (1387:1387:1387)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) + (DELAY + (ABSOLUTE + (PORT datab (2915:2915:2915) (3094:3094:3094)) + (PORT datac (2028:2028:2028) (2098:2098:2098)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1889:1889:1889) (1934:1934:1934)) + (PORT datab (2084:2084:2084) (2215:2215:2215)) + (PORT datac (1111:1111:1111) (1144:1144:1144)) + (PORT datad (208:208:208) (238:238:238)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (1234:1234:1234) (1326:1326:1326)) + (PORT datad (625:625:625) (665:665:665)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1232:1232:1232)) + (PORT datab (906:906:906) (961:961:961)) + (PORT datac (2032:2032:2032) (2056:2056:2056)) + (PORT datad (1479:1479:1479) (1541:1541:1541)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) + (DELAY + (ABSOLUTE + (PORT dataa (1057:1057:1057) (1151:1151:1151)) + (PORT datab (2381:2381:2381) (2493:2493:2493)) + (PORT datad (2113:2113:2113) (2257:2257:2257)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1487:1487:1487) (1536:1536:1536)) + (PORT datab (1011:1011:1011) (1078:1078:1078)) + (PORT datac (900:900:900) (921:921:921)) + (PORT datad (1172:1172:1172) (1187:1187:1187)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1479:1479:1479)) + (PORT datab (1137:1137:1137) (1178:1178:1178)) + (PORT datac (337:337:337) (365:365:365)) + (PORT datad (1137:1137:1137) (1159:1159:1159)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (412:412:412)) + (PORT datab (1088:1088:1088) (1114:1114:1114)) + (PORT datac (1575:1575:1575) (1617:1617:1617)) + (PORT datad (811:811:811) (828:828:828)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1206:1206:1206)) + (PORT datab (1169:1169:1169) (1204:1204:1204)) + (PORT datac (835:835:835) (863:863:863)) + (PORT datad (800:800:800) (827:827:827)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1212:1212:1212)) + (PORT datab (286:286:286) (351:351:351)) + (PORT datac (253:253:253) (312:312:312)) + (PORT datad (252:252:252) (297:297:297)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) + (DELAY + (ABSOLUTE + (PORT datac (948:948:948) (1024:1024:1024)) + (PORT datad (2023:2023:2023) (2146:2146:2146)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (897:897:897)) + (PORT datab (1012:1012:1012) (1081:1081:1081)) + (PORT datac (1223:1223:1223) (1284:1284:1284)) + (PORT datad (1171:1171:1171) (1183:1183:1183)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (257:257:257)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1230:1230:1230)) + (PORT datab (1013:1013:1013) (1082:1082:1082)) + (PORT datac (2030:2030:2030) (2056:2056:2056)) + (PORT datad (1479:1479:1479) (1543:1543:1543)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1377:1377:1377)) + (PORT datab (1170:1170:1170) (1231:1231:1231)) + (PORT datac (840:840:840) (887:887:887)) + (PORT datad (1322:1322:1322) (1434:1434:1434)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (984:984:984)) + (PORT datab (941:941:941) (1009:1009:1009)) + (PORT datac (1210:1210:1210) (1289:1289:1289)) + (PORT datad (658:658:658) (688:688:688)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1353:1353:1353) (1482:1482:1482)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (382:382:382) (410:410:410)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal69\~0) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (968:968:968)) + (PORT datab (1718:1718:1718) (1808:1808:1808)) + (PORT datac (1144:1144:1144) (1148:1148:1148)) + (PORT datad (653:653:653) (693:693:693)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1290:1290:1290)) + (PORT datad (1198:1198:1198) (1259:1259:1259)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1044:1044:1044)) + (PORT datab (2023:2023:2023) (2060:2060:2060)) + (PORT datac (1148:1148:1148) (1153:1153:1153)) + (PORT datad (650:650:650) (690:690:690)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1758:1758:1758) (1876:1876:1876)) + (PORT datab (915:915:915) (977:977:977)) + (PORT datad (216:216:216) (242:242:242)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (725:725:725)) + (PORT datab (1178:1178:1178) (1215:1215:1215)) + (PORT datac (934:934:934) (1029:1029:1029)) + (PORT datad (903:903:903) (950:950:950)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1467:1467:1467) (1537:1537:1537)) + (PORT datab (1228:1228:1228) (1312:1312:1312)) + (PORT datac (1432:1432:1432) (1520:1520:1520)) + (PORT datad (820:820:820) (833:833:833)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~2) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (845:845:845)) + (PORT datab (854:854:854) (887:887:887)) + (PORT datad (673:673:673) (693:693:693)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2011:2011:2011) (2114:2114:2114)) + (PORT datab (2111:2111:2111) (2221:2221:2221)) + (PORT datac (547:547:547) (569:569:569)) + (PORT datad (1739:1739:1739) (1782:1782:1782)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (882:882:882)) + (PORT datab (952:952:952) (1011:1011:1011)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (1472:1472:1472) (1533:1533:1533)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT datac (1162:1162:1162) (1174:1174:1174)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1237:1237:1237) (1303:1303:1303)) + (PORT datab (992:992:992) (1101:1101:1101)) + (PORT datac (657:657:657) (716:716:716)) + (PORT datad (1239:1239:1239) (1323:1323:1323)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) + (DELAY + (ABSOLUTE + (PORT datab (1082:1082:1082) (1193:1193:1193)) + (PORT datac (1465:1465:1465) (1548:1548:1548)) + (PORT datad (2348:2348:2348) (2497:2497:2497)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (726:726:726)) + (PORT datab (1800:1800:1800) (1830:1830:1830)) + (PORT datac (988:988:988) (1048:1048:1048)) + (PORT datad (1210:1210:1210) (1257:1257:1257)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1084:1084:1084)) + (PORT datab (1248:1248:1248) (1292:1292:1292)) + (PORT datac (1097:1097:1097) (1128:1128:1128)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (983:983:983)) + (PORT datab (1091:1091:1091) (1163:1163:1163)) + (PORT datac (985:985:985) (1050:1050:1050)) + (PORT datad (1157:1157:1157) (1206:1206:1206)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1013:1013:1013) (1086:1086:1086)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datac (1253:1253:1253) (1320:1320:1320)) + (PORT datad (1054:1054:1054) (1123:1123:1123)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT datab (1514:1514:1514) (1650:1650:1650)) + (PORT datac (1504:1504:1504) (1617:1617:1617)) + (PORT datad (1306:1306:1306) (1325:1325:1325)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (831:831:831)) + (PORT datab (860:860:860) (870:870:870)) + (PORT datac (1242:1242:1242) (1262:1262:1262)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1454:1454:1454)) + (PORT datab (2084:2084:2084) (2114:2114:2114)) + (PORT datac (835:835:835) (859:859:859)) + (PORT datad (788:788:788) (798:798:798)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal48\~0) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (968:968:968)) + (PORT datab (1718:1718:1718) (1807:1807:1807)) + (PORT datac (1144:1144:1144) (1148:1148:1148)) + (PORT datad (654:654:654) (693:693:693)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (998:998:998)) + (PORT datab (900:900:900) (985:985:985)) + (PORT datac (966:966:966) (1015:1015:1015)) + (PORT datad (1295:1295:1295) (1365:1365:1365)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1246:1246:1246) (1336:1336:1336)) + (PORT datab (1005:1005:1005) (1056:1056:1056)) + (PORT datac (209:209:209) (248:248:248)) + (PORT datad (1195:1195:1195) (1244:1244:1244)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1847:1847:1847) (1960:1960:1960)) + (PORT datab (1294:1294:1294) (1397:1397:1397)) + (PORT datac (2030:2030:2030) (2118:2118:2118)) + (PORT datad (836:836:836) (843:843:843)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1251:1251:1251)) + (PORT datab (1013:1013:1013) (1076:1076:1076)) + (PORT datac (621:621:621) (659:659:659)) + (PORT datad (1176:1176:1176) (1188:1188:1188)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (945:945:945)) + (PORT datab (1062:1062:1062) (1128:1128:1128)) + (PORT datac (579:579:579) (602:602:602)) + (PORT datad (1089:1089:1089) (1104:1104:1104)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1618:1618:1618) (1711:1711:1711)) + (PORT datab (1527:1527:1527) (1658:1658:1658)) + (PORT datac (1710:1710:1710) (1825:1825:1825)) + (PORT datad (1448:1448:1448) (1496:1496:1496)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1670:1670:1670) (1753:1753:1753)) + (PORT datab (1528:1528:1528) (1617:1617:1617)) + (PORT datac (966:966:966) (1014:1014:1014)) + (PORT datad (1159:1159:1159) (1218:1218:1218)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (622:622:622)) + (PORT datab (923:923:923) (944:944:944)) + (PORT datac (969:969:969) (1018:1018:1018)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1638:1638:1638) (1764:1764:1764)) + (PORT datab (1075:1075:1075) (1149:1149:1149)) + (PORT datac (1806:1806:1806) (1948:1948:1948)) + (PORT datad (942:942:942) (974:974:974)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1241:1241:1241) (1294:1294:1294)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (972:972:972) (992:992:992)) + (PORT datad (902:902:902) (955:955:955)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1348:1348:1348) (1398:1398:1398)) + (PORT datab (1002:1002:1002) (1057:1057:1057)) + (PORT datac (575:575:575) (596:596:596)) + (PORT datad (637:637:637) (681:681:681)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1988:1988:1988) (2128:2128:2128)) + (PORT datab (1534:1534:1534) (1632:1632:1632)) + (PORT datac (227:227:227) (272:272:272)) + (PORT datad (1108:1108:1108) (1149:1149:1149)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1617:1617:1617) (1711:1711:1711)) + (PORT datab (1528:1528:1528) (1657:1657:1657)) + (PORT datac (1709:1709:1709) (1824:1824:1824)) + (PORT datad (1448:1448:1448) (1496:1496:1496)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (983:983:983)) + (PORT datab (1427:1427:1427) (1510:1510:1510)) + (PORT datac (1333:1333:1333) (1448:1448:1448)) + (PORT datad (1550:1550:1550) (1659:1659:1659)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (721:721:721)) + (PORT datab (1637:1637:1637) (1642:1642:1642)) + (PORT datac (1298:1298:1298) (1314:1314:1314)) + (PORT datad (1443:1443:1443) (1563:1563:1563)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1580:1580:1580) (1703:1703:1703)) + (PORT datab (1365:1365:1365) (1479:1479:1479)) + (PORT datac (1152:1152:1152) (1186:1186:1186)) + (PORT datad (832:832:832) (834:834:834)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (729:729:729)) + (PORT datab (995:995:995) (1057:1057:1057)) + (PORT datac (1074:1074:1074) (1196:1196:1196)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) + (DELAY + (ABSOLUTE + (PORT dataa (2265:2265:2265) (2414:2414:2414)) + (PORT datab (848:848:848) (886:886:886)) + (PORT datac (2113:2113:2113) (2221:2221:2221)) + (PORT datad (669:669:669) (694:694:694)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (996:996:996)) + (PORT datab (1005:1005:1005) (1060:1060:1060)) + (PORT datac (1413:1413:1413) (1487:1487:1487)) + (PORT datad (1522:1522:1522) (1622:1622:1622)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (684:684:684)) + (PORT datab (440:440:440) (477:477:477)) + (PORT datac (202:202:202) (238:238:238)) + (PORT datad (1428:1428:1428) (1432:1432:1432)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (662:662:662)) + (PORT datab (1001:1001:1001) (1053:1053:1053)) + (PORT datac (870:870:870) (914:914:914)) + (PORT datad (809:809:809) (854:854:854)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (392:392:392)) + (PORT datab (331:331:331) (360:360:360)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (228:228:228) (271:271:271)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (657:657:657)) + (PORT datab (1415:1415:1415) (1491:1491:1491)) + (PORT datac (638:638:638) (658:658:658)) + (PORT datad (1624:1624:1624) (1706:1706:1706)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (702:702:702)) + (PORT datab (995:995:995) (1056:1056:1056)) + (PORT datac (1075:1075:1075) (1194:1194:1194)) + (PORT datad (2306:2306:2306) (2342:2342:2342)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (980:980:980)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (346:346:346) (371:371:371)) + (PORT datad (2307:2307:2307) (2344:2344:2344)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~4) + (DELAY + (ABSOLUTE + (PORT datab (1060:1060:1060) (1178:1178:1178)) + (PORT datac (1452:1452:1452) (1530:1530:1530)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1453:1453:1453)) + (PORT datab (942:942:942) (993:993:993)) + (PORT datac (1045:1045:1045) (1115:1115:1115)) + (PORT datad (1421:1421:1421) (1470:1470:1470)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1009:1009:1009)) + (PORT datab (1445:1445:1445) (1500:1500:1500)) + (PORT datac (972:972:972) (995:995:995)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1123:1123:1123)) + (PORT datab (1196:1196:1196) (1246:1246:1246)) + (PORT datac (663:663:663) (712:712:712)) + (PORT datad (879:879:879) (931:931:931)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (616:616:616)) + (PORT datac (573:573:573) (593:593:593)) + (PORT datad (531:531:531) (543:543:543)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (303:303:303)) + (PORT datab (1244:1244:1244) (1269:1269:1269)) + (PORT datac (1174:1174:1174) (1214:1214:1214)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (925:925:925)) + (PORT datab (852:852:852) (865:865:865)) + (PORT datac (342:342:342) (367:367:367)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1987:1987:1987) (2132:2132:2132)) + (PORT datab (903:903:903) (955:955:955)) + (PORT datac (224:224:224) (269:269:269)) + (PORT datad (1402:1402:1402) (1466:1466:1466)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT dataa (1798:1798:1798) (1933:1933:1933)) + (PORT datab (1613:1613:1613) (1726:1726:1726)) + (PORT datad (1409:1409:1409) (1475:1475:1475)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2050:2050:2050) (2089:2089:2089)) + (PORT datab (946:946:946) (1023:1023:1023)) + (PORT datac (1099:1099:1099) (1158:1158:1158)) + (PORT datad (914:914:914) (1002:1002:1002)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1335:1335:1335) (1354:1354:1354)) + (PORT datab (1166:1166:1166) (1239:1239:1239)) + (PORT datac (1485:1485:1485) (1514:1514:1514)) + (PORT datad (1468:1468:1468) (1520:1520:1520)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (1144:1144:1144) (1189:1189:1189)) + (PORT datab (222:222:222) (269:269:269)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (836:836:836) (868:868:868)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT datab (963:963:963) (1010:1010:1010)) + (PORT datac (601:601:601) (607:607:607)) + (PORT datad (676:676:676) (718:718:718)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT datac (928:928:928) (973:973:973)) + (PORT datad (680:680:680) (720:720:720)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1064:1064:1064)) + (PORT datab (717:717:717) (774:774:774)) + (PORT datac (903:903:903) (944:944:944)) + (PORT datad (1740:1740:1740) (1858:1858:1858)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1494:1494:1494) (1600:1600:1600)) + (PORT datab (1475:1475:1475) (1582:1582:1582)) + (PORT datac (1847:1847:1847) (1916:1916:1916)) + (PORT datad (402:402:402) (439:439:439)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1306:1306:1306)) + (PORT datac (943:943:943) (1021:1021:1021)) + (PORT datad (1208:1208:1208) (1293:1293:1293)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1221:1221:1221) (1285:1285:1285)) + (PORT datab (1430:1430:1430) (1456:1456:1456)) + (PORT datac (1096:1096:1096) (1116:1116:1116)) + (PORT datad (1325:1325:1325) (1332:1332:1332)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) + (DELAY + (ABSOLUTE + (PORT datab (934:934:934) (968:968:968)) + (PORT datac (531:531:531) (544:544:544)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (1063:1063:1063)) + (PORT datab (717:717:717) (773:773:773)) + (PORT datac (901:901:901) (942:942:942)) + (PORT datad (1738:1738:1738) (1857:1857:1857)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1397:1397:1397)) + (PORT datab (917:917:917) (962:962:962)) + (PORT datad (619:619:619) (654:654:654)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (915:915:915)) + (PORT datab (1463:1463:1463) (1548:1548:1548)) + (PORT datac (1313:1313:1313) (1405:1405:1405)) + (PORT datad (2215:2215:2215) (2336:2336:2336)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~36) + (DELAY + (ABSOLUTE + (PORT dataa (2340:2340:2340) (2463:2463:2463)) + (PORT datab (901:901:901) (951:951:951)) + (PORT datac (370:370:370) (398:398:398)) + (PORT datad (1461:1461:1461) (1558:1558:1558)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (258:258:258)) + (PORT datab (239:239:239) (284:284:284)) + (PORT datac (839:839:839) (874:874:874)) + (PORT datad (554:554:554) (572:572:572)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (DELAY + (ABSOLUTE + (PORT datac (2441:2441:2441) (2623:2623:2623)) + (PORT datad (1996:1996:1996) (2085:2085:2085)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1464:1464:1464) (1521:1521:1521)) + (PORT datab (843:843:843) (881:881:881)) + (PORT datac (916:916:916) (966:966:966)) + (PORT datad (669:669:669) (689:689:689)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1438:1438:1438) (1467:1467:1467)) + (PORT datab (1349:1349:1349) (1381:1381:1381)) + (PORT datac (855:855:855) (867:867:867)) + (PORT datad (805:805:805) (815:815:815)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1088:1088:1088) (1119:1119:1119)) + (PORT datab (2571:2571:2571) (2668:2668:2668)) + (PORT datac (1529:1529:1529) (1666:1666:1666)) + (PORT datad (1710:1710:1710) (1831:1831:1831)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) + (DELAY + (ABSOLUTE + (PORT datac (207:207:207) (248:248:248)) + (PORT datad (209:209:209) (239:239:239)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1221:1221:1221) (1290:1290:1290)) + (PORT datab (1275:1275:1275) (1382:1382:1382)) + (PORT datac (1752:1752:1752) (1793:1793:1793)) + (PORT datad (851:851:851) (865:865:865)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (427:427:427)) + (PORT datab (401:401:401) (428:428:428)) + (PORT datac (370:370:370) (396:396:396)) + (PORT datad (207:207:207) (244:244:244)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1486:1486:1486) (1538:1538:1538)) + (PORT datab (1265:1265:1265) (1379:1379:1379)) + (PORT datac (900:900:900) (922:922:922)) + (PORT datad (1168:1168:1168) (1190:1190:1190)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) + (DELAY + (ABSOLUTE + (PORT dataa (708:708:708) (754:754:754)) + (PORT datab (2783:2783:2783) (2910:2910:2910)) + (PORT datac (1297:1297:1297) (1413:1413:1413)) + (PORT datad (574:574:574) (587:587:587)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (898:898:898)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (196:196:196) (240:240:240)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (677:677:677)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (572:572:572) (582:582:582)) + (PORT datad (1423:1423:1423) (1458:1458:1458)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1380:1380:1380) (1439:1439:1439)) + (PORT datab (1847:1847:1847) (1876:1876:1876)) + (PORT datac (1135:1135:1135) (1170:1170:1170)) + (PORT datad (1756:1756:1756) (1776:1776:1776)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1865:1865:1865) (1941:1941:1941)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1135:1135:1135) (1190:1190:1190)) + (PORT datad (605:605:605) (619:619:619)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (655:655:655)) + (PORT datab (1026:1026:1026) (1124:1124:1124)) + (PORT datac (873:873:873) (908:908:908)) + (PORT datad (1598:1598:1598) (1712:1712:1712)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (363:363:363) (397:397:397)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (1031:1031:1031) (1049:1049:1049)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1437:1437:1437) (1449:1449:1449)) + (PORT datab (1437:1437:1437) (1503:1503:1503)) + (PORT datac (611:611:611) (628:628:628)) + (PORT datad (899:899:899) (951:951:951)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1639:1639:1639) (1765:1765:1765)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1806:1806:1806) (1948:1948:1948)) + (PORT datad (906:906:906) (958:958:958)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1436:1436:1436) (1449:1449:1449)) + (PORT datab (1436:1436:1436) (1504:1504:1504)) + (PORT datac (1048:1048:1048) (1116:1116:1116)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1814:1814:1814) (1847:1847:1847)) + (PORT datab (337:337:337) (365:365:365)) + (PORT datac (1045:1045:1045) (1115:1115:1115)) + (PORT datad (1199:1199:1199) (1246:1246:1246)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1419:1419:1419) (1450:1450:1450)) + (PORT datab (1438:1438:1438) (1497:1497:1497)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (938:938:938) (969:969:969)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (979:979:979) (1010:1010:1010)) + (PORT datac (1074:1074:1074) (1085:1085:1085)) + (PORT datad (1198:1198:1198) (1245:1245:1245)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1963:1963:1963) (2070:2070:2070)) + (PORT datab (1844:1844:1844) (1871:1871:1871)) + (PORT datac (1132:1132:1132) (1168:1168:1168)) + (PORT datad (1980:1980:1980) (2108:2108:2108)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (408:408:408)) + (PORT datab (1844:1844:1844) (1872:1872:1872)) + (PORT datac (1584:1584:1584) (1600:1600:1600)) + (PORT datad (187:187:187) (220:220:220)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (666:666:666)) + (PORT datab (1003:1003:1003) (1051:1051:1051)) + (PORT datac (1298:1298:1298) (1337:1337:1337)) + (PORT datad (805:805:805) (832:832:832)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (672:672:672)) + (PORT datac (1050:1050:1050) (1065:1065:1065)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1008:1008:1008)) + (PORT datab (1439:1439:1439) (1498:1498:1498)) + (PORT datac (975:975:975) (990:990:990)) + (PORT datad (1202:1202:1202) (1250:1250:1250)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (415:415:415)) + (PORT datab (213:213:213) (258:258:258)) + (PORT datac (354:354:354) (387:387:387)) + (PORT datad (344:344:344) (367:367:367)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT datab (642:642:642) (686:686:686)) + (PORT datac (872:872:872) (919:919:919)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (614:614:614)) + (PORT datab (892:892:892) (907:907:907)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (841:841:841)) + (PORT datab (697:697:697) (728:728:728)) + (PORT datac (916:916:916) (968:968:968)) + (PORT datad (816:816:816) (839:839:839)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datab (869:869:869) (890:890:890)) + (PORT datad (810:810:810) (826:826:826)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT datab (215:215:215) (259:259:259)) + (PORT datac (355:355:355) (387:387:387)) + (PORT datad (345:345:345) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1639:1639:1639) (1766:1766:1766)) + (PORT datab (1825:1825:1825) (1925:1925:1925)) + (PORT datac (1804:1804:1804) (1951:1951:1951)) + (PORT datad (941:941:941) (965:965:965)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1437:1437:1437) (1451:1451:1451)) + (PORT datab (1439:1439:1439) (1497:1497:1497)) + (PORT datac (974:974:974) (995:995:995)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1814:1814:1814) (1850:1850:1850)) + (PORT datab (1003:1003:1003) (1029:1029:1029)) + (PORT datac (315:315:315) (336:336:336)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (706:706:706)) + (PORT datab (608:608:608) (621:621:621)) + (PORT datac (813:813:813) (840:840:840)) + (PORT datad (337:337:337) (356:356:356)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1357:1357:1357)) + (PORT datab (986:986:986) (1070:1070:1070)) + (PORT datac (1073:1073:1073) (1153:1153:1153)) + (PORT datad (966:966:966) (1077:1077:1077)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1463:1463:1463) (1478:1478:1478)) + (PORT datab (1379:1379:1379) (1398:1398:1398)) + (PORT datac (1618:1618:1618) (1662:1662:1662)) + (PORT datad (1263:1263:1263) (1327:1327:1327)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1231:1231:1231)) + (PORT datab (1048:1048:1048) (1149:1149:1149)) + (PORT datad (1348:1348:1348) (1490:1490:1490)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (736:736:736)) + (PORT datab (1001:1001:1001) (1033:1033:1033)) + (PORT datac (553:553:553) (568:568:568)) + (PORT datad (222:222:222) (249:249:249)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (798:798:798)) + (PORT datab (948:948:948) (1025:1025:1025)) + (PORT datac (1099:1099:1099) (1159:1159:1159)) + (PORT datad (909:909:909) (998:998:998)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1225:1225:1225) (1294:1294:1294)) + (PORT datab (224:224:224) (271:271:271)) + (PORT datac (2351:2351:2351) (2449:2449:2449)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT datab (2076:2076:2076) (2143:2143:2143)) + (PORT datac (1719:1719:1719) (1796:1796:1796)) + (PORT datad (1155:1155:1155) (1236:1236:1236)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1501:1501:1501)) + (PORT datab (1425:1425:1425) (1462:1462:1462)) + (PORT datac (836:836:836) (865:865:865)) + (PORT datad (394:394:394) (429:429:429)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (894:894:894)) + (PORT datab (1197:1197:1197) (1223:1223:1223)) + (PORT datac (981:981:981) (1043:1043:1043)) + (PORT datad (972:972:972) (1036:1036:1036)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2006:2006:2006) (2147:2147:2147)) + (PORT datab (450:450:450) (480:480:480)) + (PORT datac (1000:1000:1000) (1045:1045:1045)) + (PORT datad (900:900:900) (950:950:950)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~1) + (DELAY + (ABSOLUTE + (PORT datac (1589:1589:1589) (1676:1676:1676)) + (PORT datad (1494:1494:1494) (1621:1621:1621)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (1016:1016:1016)) + (PORT datab (1194:1194:1194) (1223:1223:1223)) + (PORT datac (1942:1942:1942) (2000:2000:2000)) + (PORT datad (641:641:641) (693:693:693)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (627:627:627) (662:662:662)) + (PORT datac (1683:1683:1683) (1789:1789:1789)) + (PORT datad (633:633:633) (651:651:651)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1500:1500:1500) (1575:1575:1575)) + (PORT datab (362:362:362) (397:397:397)) + (PORT datac (2091:2091:2091) (2220:2220:2220)) + (PORT datad (590:590:590) (607:607:607)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (800:800:800)) + (PORT datab (947:947:947) (1025:1025:1025)) + (PORT datac (1098:1098:1098) (1158:1158:1158)) + (PORT datad (911:911:911) (1001:1001:1001)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1539:1539:1539)) + (PORT datab (1227:1227:1227) (1318:1318:1318)) + (PORT datac (1459:1459:1459) (1517:1517:1517)) + (PORT datad (1138:1138:1138) (1159:1159:1159)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1840:1840:1840) (1939:1939:1939)) + (PORT datab (2068:2068:2068) (2187:2187:2187)) + (PORT datac (1327:1327:1327) (1336:1336:1336)) + (PORT datad (2013:2013:2013) (2125:2125:2125)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1215:1215:1215)) + (PORT datab (653:653:653) (674:674:674)) + (PORT datac (1214:1214:1214) (1294:1294:1294)) + (PORT datad (596:596:596) (619:619:619)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1170:1170:1170)) + (PORT datab (841:841:841) (864:864:864)) + (PORT datad (579:579:579) (590:590:590)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) + (DELAY + (ABSOLUTE + (PORT datac (1753:1753:1753) (1873:1873:1873)) + (PORT datad (1571:1571:1571) (1694:1694:1694)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1056:1056:1056)) + (PORT datab (1039:1039:1039) (1096:1096:1096)) + (PORT datac (1052:1052:1052) (1117:1117:1117)) + (PORT datad (625:625:625) (651:651:651)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1726:1726:1726)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (1053:1053:1053) (1117:1117:1117)) + (PORT datad (1795:1795:1795) (1930:1930:1930)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1272:1272:1272)) + (PORT datab (689:689:689) (706:706:706)) + (PORT datac (1267:1267:1267) (1395:1395:1395)) + (PORT datad (1570:1570:1570) (1720:1720:1720)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (1265:1265:1265) (1395:1395:1395)) + (PORT datad (1573:1573:1573) (1723:1723:1723)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1230:1230:1230) (1277:1277:1277)) + (PORT datab (1647:1647:1647) (1673:1673:1673)) + (PORT datac (777:777:777) (786:786:786)) + (PORT datad (581:581:581) (600:600:600)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (652:652:652)) + (PORT datab (656:656:656) (711:711:711)) + (PORT datac (680:680:680) (730:730:730)) + (PORT datad (800:800:800) (871:871:871)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (1087:1087:1087)) + (PORT datab (1683:1683:1683) (1741:1741:1741)) + (PORT datac (1582:1582:1582) (1690:1690:1690)) + (PORT datad (964:964:964) (1004:1004:1004)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1342:1342:1342)) + (PORT datab (935:935:935) (949:949:949)) + (PORT datac (978:978:978) (1043:1043:1043)) + (PORT datad (1176:1176:1176) (1188:1188:1188)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (390:390:390)) + (PORT datab (1476:1476:1476) (1506:1506:1506)) + (PORT datac (1080:1080:1080) (1084:1084:1084)) + (PORT datad (1360:1360:1360) (1375:1375:1375)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (392:392:392)) + (PORT datab (238:238:238) (276:276:276)) + (PORT datac (1044:1044:1044) (1080:1080:1080)) + (PORT datad (1386:1386:1386) (1428:1428:1428)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (907:907:907)) + (PORT datab (364:364:364) (400:400:400)) + (PORT datac (656:656:656) (701:701:701)) + (PORT datad (837:837:837) (878:878:878)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (810:810:810)) + (PORT datab (933:933:933) (988:988:988)) + (PORT datac (981:981:981) (1058:1058:1058)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1552:1552:1552)) + (PORT datab (614:614:614) (644:644:644)) + (PORT datac (1197:1197:1197) (1258:1258:1258)) + (PORT datad (844:844:844) (855:855:855)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (588:588:588) (608:608:608)) + (PORT datad (876:876:876) (896:896:896)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (1250:1250:1250)) + (PORT datab (965:965:965) (1013:1013:1013)) + (PORT datac (1049:1049:1049) (1111:1111:1111)) + (PORT datad (1444:1444:1444) (1477:1477:1477)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1082:1082:1082) (1153:1153:1153)) + (PORT datab (970:970:970) (1019:1019:1019)) + (PORT datac (308:308:308) (334:334:334)) + (PORT datad (628:628:628) (654:654:654)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1085:1085:1085)) + (PORT datab (1386:1386:1386) (1414:1414:1414)) + (PORT datac (1180:1180:1180) (1211:1211:1211)) + (PORT datad (1209:1209:1209) (1252:1252:1252)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (1246:1246:1246) (1296:1296:1296)) + (PORT datac (984:984:984) (1048:1048:1048)) + (PORT datad (625:625:625) (654:654:654)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (910:910:910)) + (PORT datab (1428:1428:1428) (1466:1466:1466)) + (PORT datac (1688:1688:1688) (1726:1726:1726)) + (PORT datad (2057:2057:2057) (2190:2190:2190)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (642:642:642)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (1398:1398:1398) (1422:1422:1422)) + (PORT datad (1424:1424:1424) (1462:1462:1462)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1803:1803:1803) (1945:1945:1945)) + (PORT datab (847:847:847) (858:858:858)) + (PORT datac (838:838:838) (869:869:869)) + (PORT datad (2056:2056:2056) (2191:2191:2191)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (847:847:847)) + (PORT datab (783:783:783) (809:809:809)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (382:382:382)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (539:539:539) (561:561:561)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (1004:1004:1004)) + (PORT datab (876:876:876) (893:893:893)) + (PORT datac (1689:1689:1689) (1781:1781:1781)) + (PORT datad (1175:1175:1175) (1232:1232:1232)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1346:1346:1346) (1340:1340:1340)) + (PORT datab (1176:1176:1176) (1219:1219:1219)) + (PORT datac (1123:1123:1123) (1137:1137:1137)) + (PORT datad (665:665:665) (719:719:719)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1247:1247:1247)) + (PORT datac (582:582:582) (614:614:614)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1190:1190:1190) (1242:1242:1242)) + (PORT datab (650:650:650) (679:679:679)) + (PORT datac (191:191:191) (237:237:237)) + (PORT datad (607:607:607) (635:635:635)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (274:274:274)) + (PORT datac (2094:2094:2094) (2219:2219:2219)) + (PORT datad (1462:1462:1462) (1527:1527:1527)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (461:461:461)) + (PORT datab (1161:1161:1161) (1190:1190:1190)) + (PORT datac (1460:1460:1460) (1518:1518:1518)) + (PORT datad (1106:1106:1106) (1136:1136:1136)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1080:1080:1080) (1147:1147:1147)) + (PORT datab (1037:1037:1037) (1105:1105:1105)) + (PORT datac (1180:1180:1180) (1210:1210:1210)) + (PORT datad (1210:1210:1210) (1252:1252:1252)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (919:919:919)) + (PORT datab (661:661:661) (705:705:705)) + (PORT datac (1104:1104:1104) (1117:1117:1117)) + (PORT datad (766:766:766) (786:786:786)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1156:1156:1156)) + (PORT datab (1528:1528:1528) (1657:1657:1657)) + (PORT datac (609:609:609) (665:665:665)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (762:762:762)) + (PORT datab (849:849:849) (885:885:885)) + (PORT datac (787:787:787) (804:804:804)) + (PORT datad (670:670:670) (694:694:694)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1084:1084:1084)) + (PORT datab (969:969:969) (1019:1019:1019)) + (PORT datac (192:192:192) (223:223:223)) + (PORT datad (1444:1444:1444) (1475:1475:1475)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1298:1298:1298) (1390:1390:1390)) + (PORT datab (968:968:968) (1017:1017:1017)) + (PORT datac (1050:1050:1050) (1110:1110:1110)) + (PORT datad (1553:1553:1553) (1682:1682:1682)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1298:1298:1298) (1391:1391:1391)) + (PORT datab (1247:1247:1247) (1291:1291:1291)) + (PORT datac (985:985:985) (1043:1043:1043)) + (PORT datad (1553:1553:1553) (1682:1682:1682)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (579:579:579)) + (PORT datab (244:244:244) (288:288:288)) + (PORT datac (543:543:543) (551:551:551)) + (PORT datad (1454:1454:1454) (1511:1511:1511)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1400:1400:1400) (1422:1422:1422)) + (PORT datac (572:572:572) (596:596:596)) + (PORT datad (602:602:602) (630:630:630)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (737:737:737)) + (PORT datab (1115:1115:1115) (1164:1164:1164)) + (PORT datac (969:969:969) (1001:1001:1001)) + (PORT datad (1160:1160:1160) (1223:1223:1223)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (984:984:984)) + (PORT datab (941:941:941) (1009:1009:1009)) + (PORT datac (1210:1210:1210) (1289:1289:1289)) + (PORT datad (381:381:381) (406:406:406)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1765:1765:1765) (1808:1808:1808)) + (PORT datab (1620:1620:1620) (1658:1658:1658)) + (PORT datac (1305:1305:1305) (1421:1421:1421)) + (PORT datad (1541:1541:1541) (1677:1677:1677)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1103:1103:1103) (1119:1119:1119)) + (PORT datab (1046:1046:1046) (1094:1094:1094)) + (PORT datac (952:952:952) (984:984:984)) + (PORT datad (819:819:819) (844:844:844)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1023:1023:1023)) + (PORT datab (700:700:700) (721:721:721)) + (PORT datac (216:216:216) (260:260:260)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (874:874:874)) + (PORT datab (648:648:648) (669:669:669)) + (PORT datac (877:877:877) (899:899:899)) + (PORT datad (813:813:813) (834:834:834)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (363:363:363) (397:397:397)) + (PORT datac (964:964:964) (1033:1033:1033)) + (PORT datad (590:590:590) (607:607:607)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datac (1711:1711:1711) (1773:1773:1773)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (296:296:296)) + (PORT datab (1200:1200:1200) (1240:1240:1240)) + (PORT datac (1213:1213:1213) (1232:1232:1232)) + (PORT datad (559:559:559) (571:571:571)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1102:1102:1102) (1121:1121:1121)) + (PORT datab (246:246:246) (294:294:294)) + (PORT datac (901:901:901) (943:943:943)) + (PORT datad (1975:1975:1975) (2012:2012:2012)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (840:840:840)) + (PORT datab (850:850:850) (877:877:877)) + (PORT datac (595:595:595) (617:617:617)) + (PORT datad (811:811:811) (824:824:824)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (2154:2154:2154) (2304:2304:2304)) + (PORT datab (1756:1756:1756) (1875:1875:1875)) + (PORT datac (868:868:868) (905:905:905)) + (PORT datad (2343:2343:2343) (2450:2450:2450)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1025:1025:1025)) + (PORT datab (2108:2108:2108) (2222:2222:2222)) + (PORT datac (548:548:548) (573:573:573)) + (PORT datad (1982:1982:1982) (2069:2069:2069)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1779:1779:1779) (1888:1888:1888)) + (PORT datab (1077:1077:1077) (1152:1152:1152)) + (PORT datac (971:971:971) (991:991:991)) + (PORT datad (2049:2049:2049) (2156:2156:2156)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1244:1244:1244)) + (PORT datab (1192:1192:1192) (1241:1241:1241)) + (PORT datac (610:610:610) (626:626:626)) + (PORT datad (2306:2306:2306) (2345:2345:2345)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1033:1033:1033)) + (PORT datab (1150:1150:1150) (1177:1177:1177)) + (PORT datac (346:346:346) (385:385:385)) + (PORT datad (630:630:630) (669:669:669)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (890:890:890)) + (PORT datac (839:839:839) (858:858:858)) + (PORT datad (520:520:520) (531:531:531)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (288:288:288)) + (PORT datab (250:250:250) (300:300:300)) + (PORT datac (1960:1960:1960) (2089:2089:2089)) + (PORT datad (202:202:202) (238:238:238)) + (IOPATH dataa combout (303:303:303) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1478:1478:1478)) + (PORT datab (1346:1346:1346) (1363:1363:1363)) + (PORT datac (870:870:870) (896:896:896)) + (PORT datad (1449:1449:1449) (1511:1511:1511)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1189:1189:1189)) + (PORT datab (685:685:685) (754:754:754)) + (PORT datac (958:958:958) (1039:1039:1039)) + (PORT datad (613:613:613) (629:629:629)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (664:664:664)) + (PORT datab (973:973:973) (1069:1069:1069)) + (PORT datac (1733:1733:1733) (1832:1832:1832)) + (PORT datad (1149:1149:1149) (1173:1173:1173)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1999:1999:1999) (2036:2036:2036)) + (PORT datab (872:872:872) (899:899:899)) + (PORT datac (1356:1356:1356) (1432:1432:1432)) + (PORT datad (1348:1348:1348) (1396:1396:1396)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (650:650:650)) + (PORT datab (1061:1061:1061) (1123:1123:1123)) + (PORT datac (208:208:208) (247:247:247)) + (PORT datad (864:864:864) (923:923:923)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (632:632:632)) + (PORT datab (203:203:203) (245:245:245)) + (PORT datac (877:877:877) (914:914:914)) + (PORT datad (853:853:853) (874:874:874)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1749:1749:1749) (1769:1769:1769)) + (PORT datab (1064:1064:1064) (1181:1181:1181)) + (PORT datac (1204:1204:1204) (1273:1273:1273)) + (PORT datad (860:860:860) (875:875:875)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (719:719:719)) + (PORT datab (1166:1166:1166) (1236:1236:1236)) + (PORT datac (1485:1485:1485) (1511:1511:1511)) + (PORT datad (1469:1469:1469) (1516:1516:1516)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (880:880:880)) + (PORT datab (1385:1385:1385) (1395:1395:1395)) + (PORT datac (777:777:777) (796:796:796)) + (PORT datad (1739:1739:1739) (1779:1779:1779)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (1404:1404:1404) (1480:1480:1480)) + (PORT datab (2358:2358:2358) (2492:2492:2492)) + (PORT datac (1133:1133:1133) (1174:1174:1174)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (1016:1016:1016)) + (PORT datab (1031:1031:1031) (1053:1053:1053)) + (PORT datac (181:181:181) (219:219:219)) + (PORT datad (652:652:652) (692:692:692)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (616:616:616)) + (PORT datab (672:672:672) (701:701:701)) + (PORT datac (510:510:510) (522:522:522)) + (PORT datad (840:840:840) (853:853:853)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (256:256:256)) + (PORT datab (884:884:884) (911:911:911)) + (PORT datac (866:866:866) (930:930:930)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT dataa (2169:2169:2169) (2322:2322:2322)) + (PORT datac (1461:1461:1461) (1534:1534:1534)) + (PORT datad (2260:2260:2260) (2326:2326:2326)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (DELAY + (ABSOLUTE + (PORT datab (924:924:924) (1011:1011:1011)) + (PORT datac (1545:1545:1545) (1672:1672:1672)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (747:747:747)) + (PORT datab (868:868:868) (890:890:890)) + (PORT datac (1285:1285:1285) (1378:1378:1378)) + (PORT datad (896:896:896) (936:936:936)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1484:1484:1484) (1547:1547:1547)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (988:988:988) (1034:1034:1034)) + (PORT datad (1031:1031:1031) (1081:1081:1081)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (286:286:286)) + (PORT datab (373:373:373) (398:398:398)) + (PORT datac (599:599:599) (641:641:641)) + (PORT datad (200:200:200) (235:235:235)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1623:1623:1623) (1713:1713:1713)) + (PORT datab (1529:1529:1529) (1662:1662:1662)) + (PORT datac (1705:1705:1705) (1826:1826:1826)) + (PORT datad (1447:1447:1447) (1495:1495:1495)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1779:1779:1779) (1826:1826:1826)) + (PORT datab (681:681:681) (732:732:732)) + (PORT datac (551:551:551) (571:571:571)) + (PORT datad (1134:1134:1134) (1177:1177:1177)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (759:759:759)) + (PORT datab (1001:1001:1001) (1109:1109:1109)) + (PORT datac (192:192:192) (226:226:226)) + (PORT datad (1242:1242:1242) (1328:1328:1328)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (630:630:630)) + (PORT datab (875:875:875) (920:920:920)) + (PORT datac (338:338:338) (364:364:364)) + (PORT datad (685:685:685) (739:739:739)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (707:707:707)) + (PORT datab (950:950:950) (1008:1008:1008)) + (PORT datac (590:590:590) (605:605:605)) + (PORT datad (654:654:654) (692:692:692)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1171:1171:1171)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (566:566:566) (595:595:595)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (494:494:494)) + (PORT datab (1299:1299:1299) (1396:1396:1396)) + (PORT datac (680:680:680) (764:764:764)) + (PORT datad (1300:1300:1300) (1391:1391:1391)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1626:1626:1626)) + (PORT datab (906:906:906) (950:950:950)) + (PORT datac (1263:1263:1263) (1320:1320:1320)) + (PORT datad (1666:1666:1666) (1688:1688:1688)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (401:401:401)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (653:653:653) (714:714:714)) + (PORT datad (1668:1668:1668) (1689:1689:1689)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1373:1373:1373)) + (PORT datab (1184:1184:1184) (1235:1235:1235)) + (PORT datac (1139:1139:1139) (1197:1197:1197)) + (PORT datad (1323:1323:1323) (1433:1433:1433)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (940:940:940)) + (PORT datab (380:380:380) (410:410:410)) + (PORT datac (654:654:654) (698:698:698)) + (PORT datad (1204:1204:1204) (1277:1277:1277)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1116:1116:1116)) + (PORT datab (917:917:917) (963:963:963)) + (PORT datac (1010:1010:1010) (1060:1060:1060)) + (PORT datad (924:924:924) (954:954:954)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (251:251:251)) + (PORT datab (964:964:964) (1061:1061:1061)) + (PORT datac (844:844:844) (886:886:886)) + (PORT datad (905:905:905) (950:950:950)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1084:1084:1084)) + (PORT datab (1205:1205:1205) (1272:1272:1272)) + (PORT datac (1579:1579:1579) (1687:1687:1687)) + (PORT datad (1138:1138:1138) (1195:1195:1195)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (653:653:653)) + (PORT datab (2073:2073:2073) (2252:2252:2252)) + (PORT datac (861:861:861) (894:894:894)) + (PORT datad (1257:1257:1257) (1349:1349:1349)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (961:961:961)) + (PORT datab (916:916:916) (955:955:955)) + (PORT datac (1131:1131:1131) (1156:1156:1156)) + (PORT datad (926:926:926) (955:955:955)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1147:1147:1147)) + (PORT datab (1588:1588:1588) (1723:1723:1723)) + (PORT datac (637:637:637) (656:656:656)) + (PORT datad (1691:1691:1691) (1790:1790:1790)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2337:2337:2337) (2490:2490:2490)) + (PORT datab (1668:1668:1668) (1785:1785:1785)) + (PORT datac (905:905:905) (956:956:956)) + (PORT datad (672:672:672) (720:720:720)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1130:1130:1130)) + (PORT datad (1542:1542:1542) (1657:1657:1657)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1373:1373:1373)) + (PORT datab (656:656:656) (703:703:703)) + (PORT datac (1351:1351:1351) (1409:1409:1409)) + (PORT datad (881:881:881) (908:908:908)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1148:1148:1148)) + (PORT datab (1720:1720:1720) (1825:1825:1825)) + (PORT datac (1557:1557:1557) (1685:1685:1685)) + (PORT datad (1001:1001:1001) (1102:1102:1102)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1478:1478:1478)) + (PORT datab (827:827:827) (854:854:854)) + (PORT datac (1113:1113:1113) (1149:1149:1149)) + (PORT datad (635:635:635) (687:687:687)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) + (DELAY + (ABSOLUTE + (PORT datab (1169:1169:1169) (1230:1230:1230)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (851:851:851) (919:919:919)) + (PORT datac (194:194:194) (241:241:241)) + (PORT datad (673:673:673) (732:732:732)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (1052:1052:1052)) + (PORT datab (936:936:936) (1006:1006:1006)) + (PORT datac (1407:1407:1407) (1449:1449:1449)) + (PORT datad (537:537:537) (548:548:548)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (620:620:620)) + (PORT datab (867:867:867) (902:902:902)) + (PORT datac (1366:1366:1366) (1470:1470:1470)) + (PORT datad (1496:1496:1496) (1606:1606:1606)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (985:985:985)) + (PORT datab (916:916:916) (957:957:957)) + (PORT datac (915:915:915) (950:950:950)) + (PORT datad (1540:1540:1540) (1625:1625:1625)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1214:1214:1214)) + (PORT datab (649:649:649) (694:694:694)) + (PORT datac (902:902:902) (950:950:950)) + (PORT datad (338:338:338) (355:355:355)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (DELAY + (ABSOLUTE + (PORT datab (1511:1511:1511) (1618:1618:1618)) + (PORT datac (1726:1726:1726) (1837:1837:1837)) + (PORT datad (1072:1072:1072) (1082:1082:1082)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (734:734:734)) + (PORT datab (1163:1163:1163) (1210:1210:1210)) + (PORT datac (852:852:852) (881:881:881)) + (PORT datad (1173:1173:1173) (1254:1254:1254)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (1001:1001:1001)) + (PORT datab (946:946:946) (986:986:986)) + (PORT datac (632:632:632) (678:678:678)) + (PORT datad (1150:1150:1150) (1195:1195:1195)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT datab (865:865:865) (918:918:918)) + (PORT datac (179:179:179) (213:213:213)) + (PORT datad (851:851:851) (896:896:896)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1077:1077:1077)) + (PORT datab (1450:1450:1450) (1521:1521:1521)) + (PORT datac (1291:1291:1291) (1321:1321:1321)) + (PORT datad (856:856:856) (875:875:875)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1685:1685:1685) (1750:1750:1750)) + (PORT datab (1695:1695:1695) (1779:1779:1779)) + (PORT datac (1479:1479:1479) (1576:1576:1576)) + (PORT datad (855:855:855) (874:874:874)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (1444:1444:1444) (1505:1505:1505)) + (PORT datab (1695:1695:1695) (1774:1774:1774)) + (PORT datac (1653:1653:1653) (1704:1704:1704)) + (PORT datad (1165:1165:1165) (1208:1208:1208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (902:902:902)) + (PORT datab (612:612:612) (626:626:626)) + (PORT datac (1486:1486:1486) (1525:1525:1525)) + (PORT datad (572:572:572) (587:587:587)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (953:953:953)) + (PORT datab (920:920:920) (939:939:939)) + (PORT datac (888:888:888) (933:933:933)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) + (DELAY + (ABSOLUTE + (PORT dataa (1805:1805:1805) (1846:1846:1846)) + (PORT datab (1718:1718:1718) (1824:1824:1824)) + (PORT datac (1560:1560:1560) (1684:1684:1684)) + (PORT datad (1003:1003:1003) (1103:1103:1103)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1617:1617:1617) (1736:1736:1736)) + (PORT datac (2516:2516:2516) (2621:2621:2621)) + (PORT datad (1496:1496:1496) (1610:1610:1610)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1204:1204:1204)) + (PORT datab (1153:1153:1153) (1208:1208:1208)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (861:861:861) (880:880:880)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (684:684:684) (709:709:709)) + (PORT datac (378:378:378) (413:413:413)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (494:494:494)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (807:807:807) (827:827:827)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (413:413:413)) + (PORT datab (907:907:907) (914:914:914)) + (PORT datac (619:619:619) (656:656:656)) + (PORT datad (1190:1190:1190) (1243:1243:1243)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1250:1250:1250) (1344:1344:1344)) + (PORT datab (1673:1673:1673) (1790:1790:1790)) + (PORT datac (909:909:909) (958:958:958)) + (PORT datad (940:940:940) (995:995:995)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1458:1458:1458) (1556:1556:1556)) + (PORT datab (1664:1664:1664) (1735:1735:1735)) + (PORT datac (847:847:847) (861:861:861)) + (PORT datad (654:654:654) (683:683:683)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1407:1407:1407) (1552:1552:1552)) + (PORT datab (901:901:901) (929:929:929)) + (PORT datad (2354:2354:2354) (2501:2501:2501)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1575:1575:1575) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1200:1200:1200)) + (PORT datab (1193:1193:1193) (1243:1243:1243)) + (PORT datad (1206:1206:1206) (1288:1288:1288)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1553:1553:1553)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1593:1593:1593) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (961:961:961)) + (PORT datab (2051:2051:2051) (2083:2083:2083)) + (PORT datac (805:805:805) (817:817:817)) + (PORT datad (336:336:336) (360:360:360)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (998:998:998)) + (PORT datab (1733:1733:1733) (1770:1770:1770)) + (PORT datac (1229:1229:1229) (1327:1327:1327)) + (PORT datad (1151:1151:1151) (1194:1194:1194)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (785:785:785)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1230:1230:1230) (1329:1329:1329)) + (PORT datad (1542:1542:1542) (1627:1627:1627)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1298:1298:1298)) + (PORT datab (1276:1276:1276) (1367:1367:1367)) + (PORT datac (1156:1156:1156) (1195:1195:1195)) + (PORT datad (711:711:711) (777:777:777)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (656:656:656)) + (PORT datab (603:603:603) (615:615:615)) + (PORT datac (902:902:902) (950:950:950)) + (PORT datad (1750:1750:1750) (1806:1806:1806)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (985:985:985)) + (PORT datab (359:359:359) (388:388:388)) + (PORT datac (1182:1182:1182) (1242:1242:1242)) + (PORT datad (2028:2028:2028) (2153:2153:2153)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (372:372:372)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (878:878:878) (913:913:913)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1069:1069:1069)) + (PORT datab (913:913:913) (1002:1002:1002)) + (PORT datac (1084:1084:1084) (1074:1074:1074)) + (PORT datad (1060:1060:1060) (1062:1062:1062)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1344:1344:1344) (1441:1441:1441)) + (PORT datab (898:898:898) (946:946:946)) + (PORT datac (669:669:669) (692:692:692)) + (PORT datad (1162:1162:1162) (1228:1228:1228)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2046:2046:2046) (2143:2143:2143)) + (PORT datac (1652:1652:1652) (1690:1690:1690)) + (PORT datad (1726:1726:1726) (1766:1766:1766)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1068:1068:1068)) + (PORT datab (1320:1320:1320) (1358:1358:1358)) + (PORT datac (1320:1320:1320) (1375:1375:1375)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT datab (667:667:667) (677:677:677)) + (PORT datac (650:650:650) (674:674:674)) + (PORT datad (899:899:899) (937:937:937)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (691:691:691)) + (PORT datab (711:711:711) (745:745:745)) + (PORT datac (675:675:675) (730:730:730)) + (PORT datad (832:832:832) (843:843:843)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (889:889:889)) + (PORT datac (1915:1915:1915) (1982:1982:1982)) + (PORT datad (200:200:200) (239:239:239)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (677:677:677)) + (PORT datab (864:864:864) (932:932:932)) + (PORT datac (1099:1099:1099) (1123:1123:1123)) + (PORT datad (830:830:830) (852:852:852)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1166:1166:1166)) + (PORT datab (1000:1000:1000) (1115:1115:1115)) + (PORT datac (1411:1411:1411) (1477:1477:1477)) + (PORT datad (203:203:203) (239:239:239)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1061:1061:1061) (1166:1166:1166)) + (PORT datab (1976:1976:1976) (2065:2065:2065)) + (PORT datac (1151:1151:1151) (1205:1205:1205)) + (PORT datad (941:941:941) (1012:1012:1012)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (2603:2603:2603) (2772:2772:2772)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (1032:1032:1032)) + (PORT datac (1109:1109:1109) (1164:1164:1164)) + (PORT datad (1148:1148:1148) (1191:1191:1191)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1040:1040:1040)) + (PORT datab (845:845:845) (850:850:850)) + (PORT datac (2021:2021:2021) (2050:2050:2050)) + (PORT datad (1388:1388:1388) (1426:1426:1426)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1582:1582:1582) (1703:1703:1703)) + (PORT datab (917:917:917) (971:971:971)) + (PORT datac (929:929:929) (1008:1008:1008)) + (PORT datad (1530:1530:1530) (1630:1630:1630)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (674:674:674)) + (PORT datab (871:871:871) (890:890:890)) + (PORT datac (598:598:598) (661:661:661)) + (PORT datad (809:809:809) (825:825:825)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1239:1239:1239)) + (PORT datac (1383:1383:1383) (1458:1458:1458)) + (PORT datad (2108:2108:2108) (2253:2253:2253)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (968:968:968)) + (PORT datab (1559:1559:1559) (1655:1655:1655)) + (PORT datac (211:211:211) (252:252:252)) + (PORT datad (618:618:618) (634:634:634)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1375:1375:1375) (1445:1445:1445)) + (PORT datab (619:619:619) (640:640:640)) + (PORT datac (776:776:776) (799:799:799)) + (PORT datad (597:597:597) (614:614:614)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1683:1683:1683) (1739:1739:1739)) + (PORT datab (1115:1115:1115) (1125:1125:1125)) + (PORT datac (1054:1054:1054) (1110:1110:1110)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1324:1324:1324) (1411:1411:1411)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (592:592:592) (627:627:627)) + (PORT datad (1466:1466:1466) (1538:1538:1538)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (604:604:604)) + (PORT datab (614:614:614) (675:675:675)) + (PORT datac (611:611:611) (636:636:636)) + (PORT datad (573:573:573) (586:586:586)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (2248:2248:2248) (2386:2386:2386)) + (PORT datab (260:260:260) (341:341:341)) + (PORT datac (1161:1161:1161) (1218:1218:1218)) + (PORT datad (235:235:235) (303:303:303)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (874:874:874) (909:909:909)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (208:208:208) (250:250:250)) + (PORT datad (663:663:663) (707:707:707)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (266:266:266)) + (PORT datab (1027:1027:1027) (1068:1068:1068)) + (PORT datac (332:332:332) (358:358:358)) + (PORT datad (688:688:688) (740:740:740)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1247:1247:1247)) + (PORT datac (887:887:887) (944:944:944)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) + (DELAY + (ABSOLUTE + (PORT datac (663:663:663) (747:747:747)) + (PORT datad (890:890:890) (915:915:915)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1435:1435:1435) (1516:1516:1516)) + (PORT datab (619:619:619) (646:646:646)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (1126:1126:1126) (1172:1172:1172)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~47) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (640:640:640)) + (PORT datab (648:648:648) (672:672:672)) + (PORT datac (891:891:891) (929:929:929)) + (PORT datad (873:873:873) (908:908:908)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (385:385:385)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (616:616:616) (658:658:658)) + (PORT datad (1046:1046:1046) (1069:1069:1069)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (2048:2048:2048) (2143:2143:2143)) + (PORT datac (1652:1652:1652) (1688:1688:1688)) + (PORT datad (1726:1726:1726) (1766:1766:1766)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1331:1331:1331) (1424:1424:1424)) + (PORT datab (1098:1098:1098) (1141:1141:1141)) + (PORT datac (923:923:923) (945:945:945)) + (PORT datad (569:569:569) (578:578:578)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (278:278:278)) + (PORT datab (229:229:229) (272:272:272)) + (PORT datac (1186:1186:1186) (1234:1234:1234)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (855:855:855)) + (PORT datab (1257:1257:1257) (1326:1326:1326)) + (PORT datac (1798:1798:1798) (1932:1932:1932)) + (PORT datad (2112:2112:2112) (2257:2257:2257)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (632:632:632) (652:652:652)) + (PORT datac (595:595:595) (618:618:618)) + (PORT datad (847:847:847) (860:860:860)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1484:1484:1484)) + (PORT datab (742:742:742) (806:806:806)) + (PORT datac (873:873:873) (902:902:902)) + (PORT datad (887:887:887) (943:943:943)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (916:916:916)) + (PORT datab (683:683:683) (749:749:749)) + (PORT datac (971:971:971) (1032:1032:1032)) + (PORT datad (1783:1783:1783) (1858:1858:1858)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1298:1298:1298) (1401:1401:1401)) + (PORT datab (881:881:881) (925:925:925)) + (PORT datac (637:637:637) (657:657:657)) + (PORT datad (1737:1737:1737) (1788:1788:1788)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1486:1486:1486)) + (PORT datab (643:643:643) (709:709:709)) + (PORT datac (874:874:874) (901:901:901)) + (PORT datad (380:380:380) (406:406:406)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (953:953:953)) + (PORT datab (685:685:685) (750:750:750)) + (PORT datac (967:967:967) (1028:1028:1028)) + (PORT datad (629:629:629) (639:639:639)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1456:1456:1456) (1534:1534:1534)) + (PORT datab (926:926:926) (971:971:971)) + (PORT datac (191:191:191) (224:224:224)) + (PORT datad (1396:1396:1396) (1442:1442:1442)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1587:1587:1587) (1654:1654:1654)) + (PORT datab (1578:1578:1578) (1625:1625:1625)) + (PORT datac (1000:1000:1000) (1045:1045:1045)) + (PORT datad (1562:1562:1562) (1620:1620:1620)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1452:1452:1452) (1526:1526:1526)) + (PORT datab (898:898:898) (959:959:959)) + (PORT datac (823:823:823) (876:876:876)) + (PORT datad (584:584:584) (613:613:613)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1449:1449:1449) (1523:1523:1523)) + (PORT datab (899:899:899) (962:962:962)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (914:914:914) (977:977:977)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (613:613:613)) + (PORT datab (864:864:864) (919:919:919)) + (PORT datac (792:792:792) (849:849:849)) + (PORT datad (781:781:781) (835:835:835)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (665:665:665)) + (PORT datab (238:238:238) (284:284:284)) + (PORT datac (1314:1314:1314) (1404:1404:1404)) + (PORT datad (2218:2218:2218) (2338:2338:2338)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1788:1788:1788) (1938:1938:1938)) + (PORT datab (1645:1645:1645) (1766:1766:1766)) + (PORT datac (1304:1304:1304) (1398:1398:1398)) + (PORT datad (2565:2565:2565) (2702:2702:2702)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1317:1317:1317)) + (PORT datab (870:870:870) (893:893:893)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (588:588:588) (606:606:606)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1443:1443:1443) (1548:1548:1548)) + (PORT datab (263:263:263) (309:309:309)) + (PORT datac (1197:1197:1197) (1255:1255:1255)) + (PORT datad (842:842:842) (854:854:854)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~2) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (910:910:910)) + (PORT datab (891:891:891) (912:912:912)) + (PORT datac (859:859:859) (877:877:877)) + (PORT datad (902:902:902) (978:978:978)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (921:921:921)) + (PORT datab (937:937:937) (1012:1012:1012)) + (PORT datac (195:195:195) (239:239:239)) + (PORT datad (1152:1152:1152) (1199:1199:1199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1470:1470:1470) (1476:1476:1476)) + (PORT datab (1497:1497:1497) (1569:1569:1569)) + (PORT datac (1102:1102:1102) (1120:1120:1120)) + (PORT datad (400:400:400) (436:436:436)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (906:906:906)) + (PORT datab (893:893:893) (913:913:913)) + (PORT datac (861:861:861) (879:879:879)) + (PORT datad (904:904:904) (979:979:979)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (805:805:805)) + (PORT datab (775:775:775) (880:880:880)) + (PORT datad (1178:1178:1178) (1197:1197:1197)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (619:619:619)) + (PORT datab (1166:1166:1166) (1207:1207:1207)) + (PORT datac (854:854:854) (905:905:905)) + (PORT datad (902:902:902) (956:956:956)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1440:1440:1440) (1550:1550:1550)) + (PORT datab (866:866:866) (895:895:895)) + (PORT datac (1284:1284:1284) (1336:1336:1336)) + (PORT datad (1607:1607:1607) (1729:1729:1729)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1494:1494:1494) (1601:1601:1601)) + (PORT datab (1439:1439:1439) (1451:1451:1451)) + (PORT datac (1444:1444:1444) (1551:1551:1551)) + (PORT datad (402:402:402) (439:439:439)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1017:1017:1017) (1057:1057:1057)) + (PORT datac (793:793:793) (802:802:802)) + (PORT datad (1022:1022:1022) (1048:1048:1048)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (397:397:397) (440:440:440)) + (PORT datac (980:980:980) (992:992:992)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (373:373:373)) + (PORT datab (198:198:198) (235:235:235)) + (PORT datac (586:586:586) (613:613:613)) + (PORT datad (1522:1522:1522) (1622:1622:1622)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1222:1222:1222) (1272:1272:1272)) + (PORT datab (1222:1222:1222) (1263:1263:1263)) + (PORT datac (892:892:892) (922:922:922)) + (PORT datad (1507:1507:1507) (1624:1624:1624)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (886:886:886)) + (PORT datab (227:227:227) (274:274:274)) + (PORT datac (1160:1160:1160) (1222:1222:1222)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1685:1685:1685) (1744:1744:1744)) + (PORT datab (1695:1695:1695) (1779:1779:1779)) + (PORT datac (1482:1482:1482) (1577:1577:1577)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (1034:1034:1034)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (1192:1192:1192) (1254:1254:1254)) + (PORT datad (882:882:882) (917:917:917)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (1193:1193:1193) (1230:1230:1230)) + (PORT datac (1251:1251:1251) (1308:1308:1308)) + (PORT datad (780:780:780) (799:799:799)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (976:976:976)) + (PORT datab (940:940:940) (1022:1022:1022)) + (PORT datac (1140:1140:1140) (1178:1178:1178)) + (PORT datad (375:375:375) (417:417:417)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1284:1284:1284) (1345:1345:1345)) + (PORT datab (1189:1189:1189) (1228:1228:1228)) + (PORT datac (1135:1135:1135) (1177:1177:1177)) + (PORT datad (780:780:780) (799:799:799)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (343:343:343)) + (PORT datab (224:224:224) (272:272:272)) + (PORT datac (342:342:342) (371:371:371)) + (PORT datad (1219:1219:1219) (1301:1301:1301)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1203:1203:1203)) + (PORT datab (1191:1191:1191) (1242:1242:1242)) + (PORT datad (1220:1220:1220) (1299:1299:1299)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1553:1553:1553)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1593:1593:1593) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (405:405:405)) + (PORT datab (224:224:224) (269:269:269)) + (PORT datac (222:222:222) (302:302:302)) + (PORT datad (1202:1202:1202) (1285:1285:1285)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (586:586:586)) + (PORT datab (1028:1028:1028) (1073:1073:1073)) + (PORT datac (338:338:338) (364:364:364)) + (PORT datad (686:686:686) (739:739:739)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (687:687:687)) + (PORT datab (1720:1720:1720) (1802:1802:1802)) + (PORT datad (879:879:879) (876:876:876)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (2640:2640:2640) (2740:2740:2740)) + (PORT datab (1718:1718:1718) (1823:1823:1823)) + (PORT datac (1017:1017:1017) (1049:1049:1049)) + (PORT datad (1534:1534:1534) (1564:1564:1564)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (277:277:277)) + (PORT datab (894:894:894) (923:923:923)) + (PORT datac (1486:1486:1486) (1564:1564:1564)) + (PORT datad (1217:1217:1217) (1256:1256:1256)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1038:1038:1038)) + (PORT datab (204:204:204) (246:246:246)) + (PORT datac (946:946:946) (1014:1014:1014)) + (PORT datad (209:209:209) (240:240:240)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla30npla13M5T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (1011:1011:1011)) + (PORT datab (229:229:229) (278:278:278)) + (PORT datac (1408:1408:1408) (1479:1479:1479)) + (PORT datad (1499:1499:1499) (1550:1550:1550)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1181:1181:1181)) + (PORT datab (1549:1549:1549) (1573:1573:1573)) + (PORT datac (592:592:592) (626:626:626)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (391:391:391)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (178:178:178) (207:207:207)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (934:934:934)) + (PORT datab (654:654:654) (689:689:689)) + (PORT datac (1104:1104:1104) (1117:1117:1117)) + (PORT datad (766:766:766) (786:786:786)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1711:1711:1711)) + (PORT datab (1531:1531:1531) (1582:1582:1582)) + (PORT datac (1704:1704:1704) (1824:1824:1824)) + (PORT datad (1073:1073:1073) (1075:1075:1075)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (2002:2002:2002) (2195:2195:2195)) + (PORT datab (1455:1455:1455) (1549:1549:1549)) + (PORT datac (1508:1508:1508) (1592:1592:1592)) + (PORT datad (1918:1918:1918) (1978:1978:1978)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (965:965:965)) + (PORT datab (871:871:871) (909:909:909)) + (PORT datac (803:803:803) (870:870:870)) + (PORT datad (1526:1526:1526) (1620:1620:1620)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (664:664:664)) + (PORT datab (678:678:678) (735:735:735)) + (PORT datac (919:919:919) (966:966:966)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (728:728:728)) + (PORT datab (1191:1191:1191) (1244:1244:1244)) + (PORT datac (669:669:669) (694:694:694)) + (PORT datad (1304:1304:1304) (1397:1397:1397)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1369:1369:1369) (1431:1431:1431)) + (PORT datab (643:643:643) (680:680:680)) + (PORT datac (1322:1322:1322) (1362:1362:1362)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1190:1190:1190)) + (PORT datab (1820:1820:1820) (1897:1897:1897)) + (PORT datad (966:966:966) (1074:1074:1074)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (932:932:932)) + (PORT datab (680:680:680) (741:741:741)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (2206:2206:2206) (2251:2251:2251)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1348:1348:1348)) + (PORT datab (1492:1492:1492) (1598:1598:1598)) + (PORT datac (1226:1226:1226) (1277:1277:1277)) + (PORT datad (1231:1231:1231) (1263:1263:1263)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1906:1906:1906) (2000:2000:2000)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (869:869:869) (926:926:926)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (635:635:635)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (898:898:898) (931:931:931)) + (PORT datad (816:816:816) (860:860:860)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (881:881:881)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (561:561:561) (575:575:575)) + (PORT datad (613:613:613) (668:668:668)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (889:889:889)) + (PORT datac (208:208:208) (251:251:251)) + (PORT datad (202:202:202) (238:238:238)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1368:1368:1368)) + (PORT datab (614:614:614) (640:640:640)) + (PORT datac (842:842:842) (872:872:872)) + (PORT datad (607:607:607) (635:635:635)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1417:1417:1417) (1464:1464:1464)) + (PORT datab (910:910:910) (954:954:954)) + (PORT datac (1136:1136:1136) (1177:1177:1177)) + (PORT datad (1173:1173:1173) (1255:1255:1255)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1757:1757:1757) (1831:1831:1831)) + (PORT datab (836:836:836) (849:849:849)) + (PORT datac (2018:2018:2018) (2050:2050:2050)) + (PORT datad (2040:2040:2040) (2102:2102:2102)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~40) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (961:961:961)) + (PORT datab (1098:1098:1098) (1150:1150:1150)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (566:566:566)) + (PORT datab (662:662:662) (694:694:694)) + (PORT datac (2000:2000:2000) (2031:2031:2031)) + (PORT datad (538:538:538) (549:549:549)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (852:852:852) (924:924:924)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (855:855:855) (863:863:863)) + (PORT datac (568:568:568) (591:591:591)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (1191:1191:1191) (1227:1227:1227)) + (PORT datab (1050:1050:1050) (1057:1057:1057)) + (PORT datac (1185:1185:1185) (1207:1207:1207)) + (PORT datad (1343:1343:1343) (1388:1388:1388)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (338:338:338)) + (PORT datab (223:223:223) (268:268:268)) + (PORT datac (337:337:337) (367:367:367)) + (PORT datad (1203:1203:1203) (1285:1285:1285)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT datab (1384:1384:1384) (1432:1432:1432)) + (PORT datac (1179:1179:1179) (1200:1200:1200)) + (PORT datad (594:594:594) (610:610:610)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) + (DELAY + (ABSOLUTE + (PORT datac (900:900:900) (943:943:943)) + (PORT datad (1328:1328:1328) (1383:1383:1383)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1261:1261:1261)) + (PORT datab (223:223:223) (270:270:270)) + (PORT datac (1141:1141:1141) (1178:1178:1178)) + (PORT datad (671:671:671) (721:721:721)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (769:769:769)) + (PORT datab (1469:1469:1469) (1552:1552:1552)) + (PORT datac (1145:1145:1145) (1180:1180:1180)) + (PORT datad (199:199:199) (235:235:235)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (766:766:766)) + (PORT datab (1471:1471:1471) (1557:1557:1557)) + (PORT datac (1138:1138:1138) (1176:1176:1176)) + (PORT datad (196:196:196) (232:232:232)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1346:1346:1346) (1411:1411:1411)) + (PORT datab (869:869:869) (903:903:903)) + (PORT datac (1807:1807:1807) (1896:1896:1896)) + (PORT datad (1570:1570:1570) (1608:1608:1608)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datad (868:868:868) (885:885:885)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1092:1092:1092)) + (PORT datab (657:657:657) (681:681:681)) + (PORT datac (908:908:908) (975:975:975)) + (PORT datad (1438:1438:1438) (1536:1536:1536)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1154:1154:1154)) + (PORT datab (701:701:701) (782:782:782)) + (PORT datac (1444:1444:1444) (1551:1551:1551)) + (PORT datad (1465:1465:1465) (1554:1554:1554)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (634:634:634)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (622:622:622) (651:651:651)) + (PORT datad (1082:1082:1082) (1107:1107:1107)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (419:419:419)) + (PORT datab (1179:1179:1179) (1229:1229:1229)) + (PORT datac (351:351:351) (380:380:380)) + (PORT datad (1087:1087:1087) (1108:1108:1108)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1246:1246:1246) (1335:1335:1335)) + (PORT datab (1577:1577:1577) (1714:1714:1714)) + (PORT datac (2188:2188:2188) (2312:2312:2312)) + (PORT datad (1069:1069:1069) (1164:1164:1164)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (1012:1012:1012)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1253:1253:1253) (1293:1293:1293)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (660:660:660)) + (PORT datac (659:659:659) (688:688:688)) + (PORT datad (550:550:550) (559:559:559)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1144:1144:1144) (1180:1180:1180)) + (PORT datab (218:218:218) (265:265:265)) + (PORT datac (1135:1135:1135) (1168:1168:1168)) + (PORT datad (665:665:665) (712:712:712)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~2) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (938:938:938)) + (PORT datab (900:900:900) (913:913:913)) + (PORT datac (920:920:920) (1008:1008:1008)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (751:751:751)) + (PORT datab (1166:1166:1166) (1198:1198:1198)) + (PORT datad (948:948:948) (968:968:968)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1184:1184:1184)) + (PORT datab (248:248:248) (332:332:332)) + (PORT datac (1144:1144:1144) (1179:1179:1179)) + (PORT datad (672:672:672) (720:720:720)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (703:703:703)) + (PORT datab (1351:1351:1351) (1386:1386:1386)) + (PORT datad (908:908:908) (958:958:958)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1183:1183:1183)) + (PORT datab (250:250:250) (335:335:335)) + (PORT datac (1137:1137:1137) (1173:1173:1173)) + (PORT datad (664:664:664) (718:718:718)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (1721:1721:1721) (1780:1780:1780)) + (PORT datab (1170:1170:1170) (1223:1223:1223)) + (PORT datad (792:792:792) (797:797:797)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (761:761:761)) + (PORT datab (914:914:914) (975:975:975)) + (PORT datac (1817:1817:1817) (1896:1896:1896)) + (PORT datad (1153:1153:1153) (1178:1178:1178)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1482:1482:1482) (1581:1581:1581)) + (PORT datac (1016:1016:1016) (1055:1055:1055)) + (PORT datad (321:321:321) (344:344:344)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1428:1428:1428) (1487:1487:1487)) + (PORT datab (1168:1168:1168) (1215:1215:1215)) + (PORT datac (2035:2035:2035) (2124:2124:2124)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1200:1200:1200)) + (PORT datab (2031:2031:2031) (2127:2127:2127)) + (PORT datac (969:969:969) (1020:1020:1020)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (902:902:902)) + (PORT datab (1517:1517:1517) (1560:1560:1560)) + (PORT datac (1294:1294:1294) (1324:1324:1324)) + (PORT datad (862:862:862) (880:880:880)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (272:272:272)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (1544:1544:1544) (1653:1653:1653)) + (PORT datac (208:208:208) (246:246:246)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (620:620:620)) + (PORT datab (876:876:876) (893:893:893)) + (PORT datac (1384:1384:1384) (1444:1444:1444)) + (PORT datad (1947:1947:1947) (1977:1977:1977)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (266:266:266)) + (PORT datab (2017:2017:2017) (2075:2075:2075)) + (PORT datac (804:804:804) (827:827:827)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (740:740:740)) + (PORT datab (1445:1445:1445) (1514:1514:1514)) + (PORT datac (360:360:360) (389:389:389)) + (PORT datad (1121:1121:1121) (1177:1177:1177)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (277:277:277)) + (PORT datab (558:558:558) (578:578:578)) + (PORT datac (804:804:804) (818:818:818)) + (PORT datad (595:595:595) (633:633:633)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1170:1170:1170) (1229:1229:1229)) + (PORT datab (599:599:599) (614:614:614)) + (PORT datac (654:654:654) (698:698:698)) + (PORT datad (866:866:866) (893:893:893)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (692:692:692) (737:737:737)) + (PORT datab (1195:1195:1195) (1210:1210:1210)) + (PORT datac (1157:1157:1157) (1193:1193:1193)) + (PORT datad (590:590:590) (602:602:602)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (936:936:936)) + (PORT datab (1199:1199:1199) (1253:1253:1253)) + (PORT datac (889:889:889) (931:931:931)) + (PORT datad (630:630:630) (687:687:687)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (601:601:601)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (951:951:951)) + (PORT datab (1199:1199:1199) (1252:1252:1252)) + (PORT datac (361:361:361) (394:394:394)) + (PORT datad (1118:1118:1118) (1176:1176:1176)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1230:1230:1230)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1158:1158:1158) (1196:1196:1196)) + (PORT datad (863:863:863) (892:892:892)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (252:252:252)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (652:652:652) (697:697:697)) + (PORT datad (845:845:845) (894:894:894)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (637:637:637)) + (PORT datab (686:686:686) (707:707:707)) + (PORT datac (378:378:378) (410:410:410)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (607:607:607) (625:625:625)) + (PORT datac (530:530:530) (542:542:542)) + (PORT datad (838:838:838) (876:876:876)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (962:962:962)) + (PORT datab (1558:1558:1558) (1661:1661:1661)) + (PORT datac (1407:1407:1407) (1474:1474:1474)) + (PORT datad (200:200:200) (235:235:235)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (660:660:660)) + (PORT datab (965:965:965) (1060:1060:1060)) + (PORT datac (1732:1732:1732) (1835:1835:1835)) + (PORT datad (1150:1150:1150) (1179:1179:1179)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1102:1102:1102) (1150:1150:1150)) + (PORT datab (1473:1473:1473) (1583:1583:1583)) + (PORT datac (1614:1614:1614) (1681:1681:1681)) + (PORT datad (1173:1173:1173) (1219:1219:1219)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1405:1405:1405) (1418:1418:1418)) + (PORT datab (1241:1241:1241) (1276:1276:1276)) + (PORT datac (1251:1251:1251) (1275:1275:1275)) + (PORT datad (1260:1260:1260) (1298:1298:1298)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1121:1121:1121) (1151:1151:1151)) + (PORT datac (613:613:613) (636:636:636)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (284:284:284)) + (PORT datab (219:219:219) (256:256:256)) + (PORT datac (1148:1148:1148) (1190:1190:1190)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~35) + (DELAY + (ABSOLUTE + (PORT datab (2004:2004:2004) (2134:2134:2134)) + (PORT datac (1351:1351:1351) (1365:1365:1365)) + (PORT datad (859:859:859) (872:872:872)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (267:267:267)) + (PORT datab (910:910:910) (941:941:941)) + (PORT datac (621:621:621) (645:645:645)) + (PORT datad (924:924:924) (962:962:962)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1513:1513:1513) (1596:1596:1596)) + (PORT datab (1166:1166:1166) (1202:1202:1202)) + (PORT datac (1104:1104:1104) (1142:1142:1142)) + (PORT datad (548:548:548) (560:560:560)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (650:650:650)) + (PORT datab (234:234:234) (278:278:278)) + (PORT datac (1132:1132:1132) (1164:1164:1164)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1646:1646:1646) (1763:1763:1763)) + (PORT datab (1008:1008:1008) (1101:1101:1101)) + (PORT datac (1033:1033:1033) (1107:1107:1107)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1208:1208:1208)) + (PORT datab (1537:1537:1537) (1621:1621:1621)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (923:923:923)) + (PORT datab (570:570:570) (590:590:590)) + (PORT datac (603:603:603) (628:628:628)) + (PORT datad (595:595:595) (619:619:619)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1229:1229:1229) (1305:1305:1305)) + (PORT datab (1275:1275:1275) (1372:1372:1372)) + (PORT datac (1155:1155:1155) (1192:1192:1192)) + (PORT datad (709:709:709) (772:772:772)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (719:719:719)) + (PORT datab (1344:1344:1344) (1367:1367:1367)) + (PORT datac (1222:1222:1222) (1269:1269:1269)) + (PORT datad (1654:1654:1654) (1748:1748:1748)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1089:1089:1089)) + (PORT datab (887:887:887) (923:923:923)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (221:221:221) (249:249:249)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1035:1035:1035) (1133:1133:1133)) + (PORT datac (2185:2185:2185) (2272:2272:2272)) + (PORT datad (654:654:654) (711:711:711)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (782:782:782)) + (PORT datab (1135:1135:1135) (1159:1159:1159)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1153:1153:1153) (1186:1186:1186)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1016:1016:1016) (1112:1112:1112)) + (PORT datab (668:668:668) (685:685:685)) + (PORT datac (1012:1012:1012) (1113:1113:1113)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (933:933:933) (975:975:975)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (278:278:278) (366:366:366)) + (PORT datac (241:241:241) (319:319:319)) + (PORT datad (246:246:246) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (971:971:971)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (1095:1095:1095) (1116:1116:1116)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1192:1192:1192)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (650:650:650) (716:716:716)) + (PORT datad (966:966:966) (1077:1077:1077)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (2563:2563:2563) (2705:2705:2705)) + (PORT datab (1595:1595:1595) (1711:1711:1711)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (218:218:218) (258:258:258)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1067:1067:1067) (1148:1148:1148)) + (PORT datab (204:204:204) (245:245:245)) + (PORT datac (880:880:880) (911:911:911)) + (PORT datad (824:824:824) (834:834:834)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (931:931:931) (1002:1002:1002)) + (PORT datad (625:625:625) (662:662:662)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (663:663:663)) + (PORT datab (924:924:924) (986:986:986)) + (PORT datac (1079:1079:1079) (1113:1113:1113)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (951:951:951)) + (PORT datab (902:902:902) (933:933:933)) + (PORT datac (628:628:628) (672:672:672)) + (PORT datad (883:883:883) (909:909:909)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (1992:1992:1992) (2133:2133:2133)) + (PORT datab (907:907:907) (958:958:958)) + (PORT datac (224:224:224) (265:265:265)) + (PORT datad (1139:1139:1139) (1178:1178:1178)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (951:951:951)) + (PORT datab (917:917:917) (970:970:970)) + (PORT datac (879:879:879) (911:911:911)) + (PORT datad (593:593:593) (627:627:627)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (926:926:926)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1121:1121:1121)) + (PORT datab (894:894:894) (950:950:950)) + (PORT datac (601:601:601) (665:665:665)) + (PORT datad (855:855:855) (908:908:908)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2419:2419:2419) (2569:2569:2569)) + (PORT datab (1823:1823:1823) (1925:1925:1925)) + (PORT datac (1074:1074:1074) (1067:1067:1067)) + (PORT datad (1576:1576:1576) (1735:1735:1735)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (849:849:849)) + (PORT datab (912:912:912) (944:944:944)) + (PORT datac (835:835:835) (868:868:868)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2421:2421:2421) (2571:2571:2571)) + (PORT datab (2408:2408:2408) (2540:2540:2540)) + (PORT datac (1413:1413:1413) (1473:1473:1473)) + (PORT datad (1573:1573:1573) (1734:1734:1734)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (229:229:229) (272:272:272)) + (PORT datac (202:202:202) (241:241:241)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1310:1310:1310)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (832:832:832) (831:831:831)) + (PORT datad (872:872:872) (917:917:917)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (898:898:898)) + (PORT datab (237:237:237) (281:281:281)) + (PORT datac (619:619:619) (671:671:671)) + (PORT datad (1350:1350:1350) (1391:1391:1391)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1318:1318:1318)) + (PORT datab (1384:1384:1384) (1497:1497:1497)) + (PORT datac (857:857:857) (917:917:917)) + (PORT datad (831:831:831) (860:860:860)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2065:2065:2065) (2136:2136:2136)) + (PORT datab (2504:2504:2504) (2706:2706:2706)) + (PORT datac (2886:2886:2886) (3058:3058:3058)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (845:845:845) (894:894:894)) + (PORT datac (990:990:990) (1030:1030:1030)) + (PORT datad (1379:1379:1379) (1425:1425:1425)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (268:268:268)) + (PORT datac (663:663:663) (700:700:700)) + (PORT datad (1031:1031:1031) (1094:1094:1094)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1328:1328:1328) (1447:1447:1447)) + (PORT datac (1179:1179:1179) (1239:1239:1239)) + (PORT datad (2024:2024:2024) (2146:2146:2146)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1166:1166:1166)) + (PORT datab (226:226:226) (266:266:266)) + (PORT datac (604:604:604) (622:622:622)) + (PORT datad (1151:1151:1151) (1191:1191:1191)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1230:1230:1230)) + (PORT datac (1131:1131:1131) (1168:1168:1168)) + (PORT datad (957:957:957) (1017:1017:1017)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT datab (2109:2109:2109) (2224:2224:2224)) + (PORT datac (925:925:925) (983:983:983)) + (PORT datad (1982:1982:1982) (2072:2072:2072)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1250:1250:1250)) + (PORT datab (599:599:599) (617:617:617)) + (PORT datac (871:871:871) (913:913:913)) + (PORT datad (1143:1143:1143) (1193:1193:1193)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1120:1120:1120) (1154:1154:1154)) + (PORT datab (595:595:595) (609:609:609)) + (PORT datac (1115:1115:1115) (1174:1174:1174)) + (PORT datad (878:878:878) (910:910:910)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1801:1801:1801) (1843:1843:1843)) + (PORT datab (1573:1573:1573) (1608:1608:1608)) + (PORT datad (985:985:985) (1020:1020:1020)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (957:957:957)) + (PORT datab (1162:1162:1162) (1232:1232:1232)) + (PORT datac (1480:1480:1480) (1554:1554:1554)) + (PORT datad (1102:1102:1102) (1119:1119:1119)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (740:740:740)) + (PORT datab (913:913:913) (942:942:942)) + (PORT datac (618:618:618) (642:642:642)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1512:1512:1512) (1540:1540:1540)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (959:959:959)) + (PORT datab (887:887:887) (953:953:953)) + (PORT datac (185:185:185) (226:226:226)) + (PORT datad (885:885:885) (902:902:902)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1725:1725:1725) (1783:1783:1783)) + (PORT datad (330:330:330) (351:351:351)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1198:1198:1198) (1240:1240:1240)) + (PORT datab (835:835:835) (861:861:861)) + (PORT datac (841:841:841) (865:865:865)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1551:1551:1551) (1610:1610:1610)) + (PORT datab (1763:1763:1763) (1826:1826:1826)) + (PORT datac (2606:2606:2606) (2704:2704:2704)) + (PORT datad (1157:1157:1157) (1177:1177:1177)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (2641:2641:2641) (2744:2744:2744)) + (PORT datab (1587:1587:1587) (1722:1722:1722)) + (PORT datac (639:639:639) (659:659:659)) + (PORT datad (202:202:202) (233:233:233)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (638:638:638)) + (PORT datab (653:653:653) (683:683:683)) + (PORT datac (637:637:637) (684:684:684)) + (PORT datad (847:847:847) (906:906:906)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT datab (707:707:707) (739:739:739)) + (PORT datac (1055:1055:1055) (1068:1068:1068)) + (PORT datad (921:921:921) (956:956:956)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (401:401:401)) + (PORT datab (1114:1114:1114) (1146:1146:1146)) + (PORT datac (1038:1038:1038) (1080:1080:1080)) + (PORT datad (853:853:853) (854:854:854)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1748:1748:1748) (1768:1768:1768)) + (PORT datab (881:881:881) (907:907:907)) + (PORT datac (1501:1501:1501) (1630:1630:1630)) + (PORT datad (1129:1129:1129) (1199:1199:1199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1137:1137:1137) (1170:1170:1170)) + (PORT datab (1651:1651:1651) (1721:1721:1721)) + (PORT datac (1148:1148:1148) (1186:1186:1186)) + (PORT datad (212:212:212) (247:247:247)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (702:702:702)) + (PORT datab (1148:1148:1148) (1207:1207:1207)) + (PORT datac (1182:1182:1182) (1237:1237:1237)) + (PORT datad (969:969:969) (1043:1043:1043)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~1) + (DELAY + (ABSOLUTE + (PORT dataa (294:294:294) (365:365:365)) + (PORT datac (1702:1702:1702) (1757:1757:1757)) + (PORT datad (437:437:437) (482:482:482)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (685:685:685)) + (PORT datab (1154:1154:1154) (1208:1208:1208)) + (PORT datac (1484:1484:1484) (1544:1544:1544)) + (PORT datad (1270:1270:1270) (1331:1331:1331)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1443:1443:1443) (1501:1501:1501)) + (PORT datab (912:912:912) (961:961:961)) + (PORT datac (896:896:896) (925:925:925)) + (PORT datad (962:962:962) (988:988:988)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (897:897:897)) + (PORT datac (992:992:992) (1045:1045:1045)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1139:1139:1139)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1089:1089:1089) (1116:1116:1116)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (374:374:374)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (345:345:345) (385:385:385)) + (PORT datad (858:858:858) (866:866:866)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1408:1408:1408) (1444:1444:1444)) + (PORT datab (814:814:814) (844:844:844)) + (PORT datac (1711:1711:1711) (1730:1730:1730)) + (PORT datad (911:911:911) (949:949:949)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1097:1097:1097) (1124:1124:1124)) + (PORT datab (662:662:662) (693:693:693)) + (PORT datac (868:868:868) (892:892:892)) + (PORT datad (871:871:871) (914:914:914)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (275:275:275)) + (PORT datab (642:642:642) (663:663:663)) + (PORT datac (1367:1367:1367) (1431:1431:1431)) + (PORT datad (1132:1132:1132) (1158:1158:1158)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1764:1764:1764)) + (PORT datab (1009:1009:1009) (1098:1098:1098)) + (PORT datac (1939:1939:1939) (1965:1965:1965)) + (PORT datad (1664:1664:1664) (1726:1726:1726)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (264:264:264)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (646:646:646) (703:703:703)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (275:275:275)) + (PORT datab (645:645:645) (669:669:669)) + (PORT datac (199:199:199) (236:236:236)) + (PORT datad (1191:1191:1191) (1215:1215:1215)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (1028:1028:1028) (1084:1084:1084)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (593:593:593) (617:617:617)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (960:960:960)) + (PORT datab (1128:1128:1128) (1156:1156:1156)) + (PORT datac (886:886:886) (918:918:918)) + (PORT datad (1142:1142:1142) (1198:1198:1198)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) + (DELAY + (ABSOLUTE + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (593:593:593) (653:653:653)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (264:264:264)) + (PORT datac (557:557:557) (571:571:571)) + (PORT datad (812:812:812) (882:882:882)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1301:1301:1301) (1363:1363:1363)) + (PORT datab (670:670:670) (695:695:695)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (1179:1179:1179) (1216:1216:1216)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (585:585:585)) + (PORT datac (793:793:793) (849:849:849)) + (PORT datad (781:781:781) (835:835:835)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (932:932:932)) + (PORT datab (670:670:670) (713:713:713)) + (PORT datac (371:371:371) (406:406:406)) + (PORT datad (595:595:595) (643:643:643)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (677:677:677)) + (PORT datab (867:867:867) (880:880:880)) + (PORT datac (866:866:866) (892:892:892)) + (PORT datad (646:646:646) (680:680:680)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~46) + (DELAY + (ABSOLUTE + (PORT datab (821:821:821) (842:842:842)) + (PORT datac (201:201:201) (237:237:237)) + (PORT datad (1425:1425:1425) (1509:1509:1509)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (610:610:610)) + (PORT datab (926:926:926) (956:956:956)) + (PORT datac (586:586:586) (596:596:596)) + (PORT datad (582:582:582) (613:613:613)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1011:1011:1011)) + (PORT datab (1561:1561:1561) (1659:1659:1659)) + (PORT datac (842:842:842) (876:876:876)) + (PORT datad (371:371:371) (400:400:400)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (251:251:251)) + (PORT datab (340:340:340) (371:371:371)) + (PORT datac (211:211:211) (252:252:252)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (963:963:963)) + (PORT datac (857:857:857) (921:921:921)) + (PORT datad (828:828:828) (859:859:859)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (681:681:681)) + (PORT datab (1486:1486:1486) (1550:1550:1550)) + (PORT datac (820:820:820) (856:856:856)) + (PORT datad (815:815:815) (871:871:871)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (504:504:504)) + (PORT datab (946:946:946) (986:986:986)) + (PORT datac (374:374:374) (405:405:405)) + (PORT datad (1915:1915:1915) (2040:2040:2040)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) + (DELAY + (ABSOLUTE + (PORT dataa (2472:2472:2472) (2661:2661:2661)) + (PORT datab (554:554:554) (575:575:575)) + (PORT datac (892:892:892) (956:956:956)) + (PORT datad (1125:1125:1125) (1142:1142:1142)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (677:677:677)) + (PORT datab (581:581:581) (596:596:596)) + (PORT datac (785:785:785) (834:834:834)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (619:619:619)) + (PORT datab (876:876:876) (893:893:893)) + (PORT datac (1988:1988:1988) (2046:2046:2046)) + (PORT datad (596:596:596) (620:620:620)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1167:1167:1167)) + (PORT datab (1567:1567:1567) (1688:1688:1688)) + (PORT datac (635:635:635) (692:692:692)) + (PORT datad (604:604:604) (642:642:642)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (914:914:914)) + (PORT datab (562:562:562) (571:571:571)) + (PORT datac (611:611:611) (649:649:649)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (663:663:663)) + (PORT datab (925:925:925) (986:986:986)) + (PORT datac (532:532:532) (538:538:538)) + (PORT datad (873:873:873) (880:880:880)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (276:276:276)) + (PORT datab (643:643:643) (675:675:675)) + (PORT datac (842:842:842) (864:864:864)) + (PORT datad (344:344:344) (366:366:366)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT datab (1438:1438:1438) (1508:1508:1508)) + (PORT datac (915:915:915) (945:945:945)) + (PORT datad (819:819:819) (835:835:835)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (1330:1330:1330) (1334:1334:1334)) + (PORT datac (1375:1375:1375) (1393:1393:1393)) + (PORT datad (312:312:312) (330:330:330)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT datab (949:949:949) (999:999:999)) + (PORT datac (1439:1439:1439) (1498:1498:1498)) + (PORT datad (671:671:671) (702:702:702)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (974:974:974) (1028:1028:1028)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1880:1880:1880) (1905:1905:1905)) + (PORT datab (702:702:702) (730:730:730)) + (PORT datad (1198:1198:1198) (1238:1238:1238)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT datab (709:709:709) (737:737:737)) + (PORT datac (1057:1057:1057) (1070:1070:1070)) + (PORT datad (923:923:923) (954:954:954)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (738:738:738) (772:772:772)) + (PORT datac (609:609:609) (659:659:659)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT datac (1990:1990:1990) (2095:2095:2095)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (1548:1548:1548) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (1548:1548:1548) (1550:1550:1550)) + (PORT asdata (567:567:567) (646:646:646)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1548:1548:1548) (1550:1550:1550)) + (PORT asdata (569:569:569) (648:648:648)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE KEY\[0\]\~input) @@ -754,8 +11353,8 @@ (INSTANCE reset) (DELAY (ABSOLUTE - (PORT datac (1948:1948:1948) (1769:1769:1769)) - (PORT datad (820:820:820) (846:846:846)) + (PORT datac (1566:1566:1566) (1527:1527:1527)) + (PORT datad (531:531:531) (524:524:524)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -766,7 +11365,7 @@ (INSTANCE z80_\|resets_\|x1\~0) (DELAY (ABSOLUTE - (PORT datad (198:198:198) (224:224:224)) + (PORT datad (1474:1474:1474) (1549:1549:1549)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -776,7 +11375,7 @@ (INSTANCE z80_\|fpga_reset) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1542:1542:1542)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -799,9 +11398,9 @@ (INSTANCE z80_\|resets_\|x1) (DELAY (ABSOLUTE - (PORT clk (1550:1550:1550) (1550:1550:1550)) + (PORT clk (1523:1523:1523) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1547:1547:1547)) + (PORT clrn (1883:1883:1883) (1869:1869:1869)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -810,3451 +11409,16 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) - (DELAY - (ABSOLUTE - (PORT dataa (1134:1134:1134) (1226:1226:1226)) - (PORT datab (1058:1058:1058) (1141:1141:1141)) - (PORT datad (370:370:370) (433:433:433)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1559:1559:1559)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (597:597:597) (652:652:652)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE KEY\[1\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (481:481:481) (733:733:733)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT datac (3754:3754:3754) (3979:3979:3979)) - (PORT datad (1117:1117:1117) (1199:1199:1199)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|nmi_armed) - (DELAY - (ABSOLUTE - (PORT clk (1830:1830:1830) (1898:1898:1898)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (766:766:766) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1064:1064:1064) (1127:1127:1127)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT datac (1277:1277:1277) (1336:1336:1336)) - (PORT datad (1203:1203:1203) (1310:1310:1310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) - (DELAY - (ABSOLUTE - (PORT dataa (1302:1302:1302) (1430:1430:1430)) - (PORT datad (1381:1381:1381) (1462:1462:1462)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (969:969:969)) - (PORT datab (274:274:274) (360:360:360)) - (PORT datad (861:861:861) (911:911:911)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (983:983:983)) - (PORT datab (266:266:266) (349:349:349)) - (PORT datad (856:856:856) (905:905:905)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1395:1395:1395) (1486:1486:1486)) - (PORT datac (857:857:857) (940:940:940)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datac (1391:1391:1391) (1465:1465:1465)) - (PORT datad (1374:1374:1374) (1422:1422:1422)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datab (992:992:992) (1063:1063:1063)) - (PORT datac (966:966:966) (1044:1044:1044)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1204:1204:1204) (1276:1276:1276)) - (PORT datab (1359:1359:1359) (1348:1348:1348)) - (PORT datac (2035:2035:2035) (2074:2074:2074)) - (PORT datad (917:917:917) (942:942:942)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1411:1411:1411) (1462:1462:1462)) - (PORT datab (1304:1304:1304) (1363:1363:1363)) - (PORT datac (285:285:285) (382:382:382)) - (PORT datad (291:291:291) (380:380:380)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT datab (1399:1399:1399) (1485:1485:1485)) - (PORT datac (1720:1720:1720) (1815:1815:1815)) - (PORT datad (1704:1704:1704) (1780:1780:1780)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1424:1424:1424)) - (PORT datab (881:881:881) (912:912:912)) - (PORT datac (1062:1062:1062) (1123:1123:1123)) - (PORT datad (1135:1135:1135) (1189:1189:1189)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|M5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (966:966:966)) - (PORT datab (408:408:408) (478:478:478)) - (PORT datad (862:862:862) (914:914:914)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|M5) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1438:1438:1438) (1510:1510:1510)) - (PORT datac (1315:1315:1315) (1368:1368:1368)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) - (DELAY - (ABSOLUTE - (PORT datac (1157:1157:1157) (1248:1248:1248)) - (PORT datad (1780:1780:1780) (1841:1841:1841)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (920:920:920)) - (PORT datab (1641:1641:1641) (1693:1693:1693)) - (PORT datac (1019:1019:1019) (1067:1067:1067)) - (PORT datad (886:886:886) (909:909:909)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1392:1392:1392)) - (PORT datab (628:628:628) (668:668:668)) - (PORT datac (1462:1462:1462) (1490:1490:1490)) - (PORT datad (930:930:930) (960:960:960)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1436:1436:1436) (1512:1512:1512)) - (PORT datab (2151:2151:2151) (2203:2203:2203)) - (PORT datac (288:288:288) (387:387:387)) - (PORT datad (1377:1377:1377) (1417:1417:1417)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1528:1528:1528)) - (PORT datab (1294:1294:1294) (1345:1345:1345)) - (PORT datac (603:603:603) (638:638:638)) - (PORT datad (598:598:598) (638:638:638)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1502:1502:1502) (1523:1523:1523)) - (PORT datab (1184:1184:1184) (1251:1251:1251)) - (PORT datac (1601:1601:1601) (1677:1677:1677)) - (PORT datad (1668:1668:1668) (1705:1705:1705)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) - (DELAY - (ABSOLUTE - (PORT datab (1364:1364:1364) (1423:1423:1423)) - (PORT datac (1357:1357:1357) (1418:1418:1418)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (668:668:668)) - (PORT datab (620:620:620) (658:658:658)) - (PORT datac (696:696:696) (786:786:786)) - (PORT datad (936:936:936) (966:966:966)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1377:1377:1377) (1433:1433:1433)) - (PORT datab (1180:1180:1180) (1248:1248:1248)) - (PORT datac (1596:1596:1596) (1673:1673:1673)) - (PORT datad (1303:1303:1303) (1345:1345:1345)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1337:1337:1337) (1394:1394:1394)) - (PORT datab (635:635:635) (675:675:675)) - (PORT datac (1461:1461:1461) (1493:1493:1493)) - (PORT datad (932:932:932) (962:962:962)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT datab (1367:1367:1367) (1429:1429:1429)) - (PORT datac (1362:1362:1362) (1425:1425:1425)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (664:664:664) (699:699:699)) - (PORT datab (641:641:641) (680:680:680)) - (PORT datac (691:691:691) (782:782:782)) - (PORT datad (931:931:931) (959:959:959)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT datac (1124:1124:1124) (1202:1202:1202)) - (PORT datad (1175:1175:1175) (1289:1289:1289)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1115:1115:1115) (1188:1188:1188)) - (PORT datab (637:637:637) (663:663:663)) - (PORT datac (1557:1557:1557) (1548:1548:1548)) - (PORT datad (1147:1147:1147) (1165:1165:1165)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1101:1101:1101) (1131:1131:1131)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (3095:3095:3095) (3190:3190:3190)) - (PORT datab (2163:2163:2163) (2276:2276:2276)) - (PORT datac (964:964:964) (1028:1028:1028)) - (PORT datad (1038:1038:1038) (1065:1065:1065)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1193:1193:1193) (1283:1283:1283)) - (PORT datab (1159:1159:1159) (1236:1236:1236)) - (PORT datac (1168:1168:1168) (1278:1278:1278)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1406:1406:1406) (1460:1460:1460)) - (PORT datab (322:322:322) (426:426:426)) - (PORT datac (1274:1274:1274) (1326:1326:1326)) - (PORT datad (1325:1325:1325) (1362:1362:1362)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1877:1877:1877) (2007:2007:2007)) - (PORT datab (1737:1737:1737) (1823:1823:1823)) - (PORT datac (1716:1716:1716) (1809:1809:1809)) - (PORT datad (1373:1373:1373) (1449:1449:1449)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) - (DELAY - (ABSOLUTE - (PORT datac (1141:1141:1141) (1242:1242:1242)) - (PORT datad (1357:1357:1357) (1427:1427:1427)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1355:1355:1355) (1399:1399:1399)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (649:649:649) (701:701:701)) - (PORT datad (1848:1848:1848) (1913:1913:1913)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (655:655:655)) - (PORT datab (655:655:655) (705:705:705)) - (PORT datac (170:170:170) (204:204:204)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datab (1345:1345:1345) (1418:1418:1418)) - (PORT datad (1361:1361:1361) (1443:1443:1443)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (980:980:980)) - (PORT datac (238:238:238) (316:316:316)) - (PORT datad (857:857:857) (914:914:914)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2115:2115:2115) (2168:2168:2168)) - (PORT datab (1358:1358:1358) (1402:1402:1402)) - (PORT datac (1398:1398:1398) (1475:1475:1475)) - (PORT datad (1373:1373:1373) (1419:1419:1419)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1545:1545:1545) (1551:1551:1551)) - (PORT datab (262:262:262) (316:316:316)) - (PORT datac (344:344:344) (371:371:371)) - (PORT datad (1091:1091:1091) (1101:1101:1101)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1606:1606:1606) (1656:1656:1656)) - (PORT datab (235:235:235) (278:278:278)) - (PORT datac (708:708:708) (782:782:782)) - (PORT datad (585:585:585) (605:605:605)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1407:1407:1407) (1464:1464:1464)) - (PORT datab (1304:1304:1304) (1365:1365:1365)) - (PORT datac (290:290:290) (388:388:388)) - (PORT datad (297:297:297) (387:387:387)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (715:715:715)) - (PORT datab (814:814:814) (858:858:858)) - (PORT datac (870:870:870) (893:893:893)) - (PORT datad (397:397:397) (461:461:461)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT datab (644:644:644) (683:683:683)) - (PORT datac (818:818:818) (837:837:837)) - (PORT datad (591:591:591) (609:609:609)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datac (1371:1371:1371) (1445:1445:1445)) - (PORT datad (1609:1609:1609) (1666:1666:1666)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) - (DELAY - (ABSOLUTE - (PORT datac (947:947:947) (1022:1022:1022)) - (PORT datad (909:909:909) (984:984:984)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (885:885:885)) - (PORT datab (1292:1292:1292) (1333:1333:1333)) - (PORT datac (851:851:851) (858:858:858)) - (PORT datad (682:682:682) (739:739:739)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (1082:1082:1082) (1100:1100:1100)) - (PORT datac (531:531:531) (535:535:535)) - (PORT datad (202:202:202) (233:233:233)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT datab (1538:1538:1538) (1625:1625:1625)) - (PORT datac (961:961:961) (1079:1079:1079)) - (PORT datad (1782:1782:1782) (1844:1844:1844)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (690:690:690)) - (PORT datab (665:665:665) (736:736:736)) - (PORT datac (589:589:589) (641:641:641)) - (PORT datad (680:680:680) (731:731:731)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1363:1363:1363) (1379:1379:1379)) - (PORT datac (881:881:881) (959:959:959)) - (PORT datad (793:793:793) (809:809:809)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (940:940:940) (971:971:971)) - (PORT datad (223:223:223) (258:258:258)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datac (1130:1130:1130) (1183:1183:1183)) - (PORT datad (1028:1028:1028) (1045:1045:1045)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1062:1062:1062)) - (PORT datab (1794:1794:1794) (1838:1838:1838)) - (PORT datac (522:522:522) (535:535:535)) - (PORT datad (1014:1014:1014) (1025:1025:1025)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (984:984:984)) - (PORT datab (1059:1059:1059) (1144:1144:1144)) - (PORT datac (1098:1098:1098) (1144:1144:1144)) - (PORT datad (1105:1105:1105) (1181:1181:1181)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) - (PORT ena (1555:1555:1555) (1575:1575:1575)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) - (DELAY - (ABSOLUTE - (PORT datab (937:937:937) (1003:1003:1003)) - (PORT datad (1522:1522:1522) (1568:1568:1568)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1604:1604:1604) (1658:1658:1658)) - (PORT datab (747:747:747) (827:827:827)) - (PORT datac (1316:1316:1316) (1365:1365:1365)) - (PORT datad (580:580:580) (604:604:604)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (2413:2413:2413) (2489:2489:2489)) - (PORT datab (2848:2848:2848) (2922:2922:2922)) - (PORT datac (1120:1120:1120) (1192:1192:1192)) - (PORT datad (1057:1057:1057) (1089:1089:1089)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1867:1867:1867) (1894:1894:1894)) - (PORT datab (849:849:849) (887:887:887)) - (PORT datad (1308:1308:1308) (1320:1320:1320)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT datab (1542:1542:1542) (1635:1635:1635)) - (PORT datac (1212:1212:1212) (1291:1291:1291)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1149:1149:1149)) - (PORT datab (946:946:946) (980:980:980)) - (PORT datac (2035:2035:2035) (2068:2068:2068)) - (PORT datad (1149:1149:1149) (1164:1164:1164)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datac (1819:1819:1819) (1866:1866:1866)) - (PORT datad (1656:1656:1656) (1707:1707:1707)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2151:2151:2151) (2215:2215:2215)) - (PORT datab (262:262:262) (316:316:316)) - (PORT datac (369:369:369) (422:422:422)) - (PORT datad (1037:1037:1037) (1057:1057:1057)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (458:458:458)) - (PORT datab (264:264:264) (318:318:318)) - (PORT datac (2117:2117:2117) (2172:2172:2172)) - (PORT datad (1536:1536:1536) (1558:1558:1558)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1310:1310:1310)) - (PORT datac (1508:1508:1508) (1597:1597:1597)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1149:1149:1149)) - (PORT datab (689:689:689) (752:752:752)) - (PORT datac (1183:1183:1183) (1262:1262:1262)) - (PORT datad (1423:1423:1423) (1460:1460:1460)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1217:1217:1217) (1301:1301:1301)) - (PORT datab (653:653:653) (688:688:688)) - (PORT datac (887:887:887) (952:952:952)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (796:796:796)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (619:619:619) (626:626:626)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (900:900:900)) - (PORT datab (1161:1161:1161) (1177:1177:1177)) - (PORT datac (1062:1062:1062) (1095:1095:1095)) - (PORT datad (1425:1425:1425) (1480:1480:1480)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1423:1423:1423) (1492:1492:1492)) - (PORT datad (935:935:935) (1028:1028:1028)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT datac (1102:1102:1102) (1165:1165:1165)) - (PORT datad (934:934:934) (1024:1024:1024)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1316:1316:1316)) - (PORT datab (1639:1639:1639) (1692:1692:1692)) - (PORT datac (543:543:543) (551:551:551)) - (PORT datad (1664:1664:1664) (1713:1713:1713)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2003:2003:2003) (2045:2045:2045)) - (PORT datab (1218:1218:1218) (1230:1230:1230)) - (PORT datac (828:828:828) (847:847:847)) - (PORT datad (839:839:839) (862:862:862)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT datab (1402:1402:1402) (1488:1488:1488)) - (PORT datac (1718:1718:1718) (1812:1812:1812)) - (PORT datad (1705:1705:1705) (1781:1781:1781)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1341:1341:1341)) - (PORT datab (1412:1412:1412) (1481:1481:1481)) - (PORT datac (2490:2490:2490) (2528:2528:2528)) - (PORT datad (2375:2375:2375) (2441:2441:2441)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1605:1605:1605) (1663:1663:1663)) - (PORT datab (754:754:754) (834:834:834)) - (PORT datac (817:817:817) (834:834:834)) - (PORT datad (1344:1344:1344) (1388:1388:1388)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1562:1562:1562) (1626:1626:1626)) - (PORT datab (941:941:941) (1011:1011:1011)) - (PORT datac (1321:1321:1321) (1340:1340:1340)) - (PORT datad (829:829:829) (839:839:839)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (962:962:962)) - (PORT datab (1204:1204:1204) (1261:1261:1261)) - (PORT datac (1534:1534:1534) (1590:1590:1590)) - (PORT datad (876:876:876) (959:959:959)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (2058:2058:2058) (2114:2114:2114)) - (PORT datab (885:885:885) (938:938:938)) - (PORT datac (1276:1276:1276) (1345:1345:1345)) - (PORT datad (1126:1126:1126) (1182:1182:1182)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1561:1561:1561) (1623:1623:1623)) - (PORT datab (1205:1205:1205) (1265:1265:1265)) - (PORT datac (848:848:848) (908:908:908)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1497:1497:1497) (1534:1534:1534)) - (PORT datab (1297:1297:1297) (1349:1349:1349)) - (PORT datac (586:586:586) (621:621:621)) - (PORT datad (594:594:594) (633:633:633)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (414:414:414)) - (PORT datab (1336:1336:1336) (1386:1386:1386)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (326:326:326) (348:348:348)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT datab (974:974:974) (999:999:999)) - (PORT datac (588:588:588) (623:623:623)) - (PORT datad (1271:1271:1271) (1309:1309:1309)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1605:1605:1605) (1662:1662:1662)) - (PORT datab (238:238:238) (283:283:283)) - (PORT datac (718:718:718) (794:794:794)) - (PORT datad (581:581:581) (600:600:600)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (424:424:424)) - (PORT datab (1150:1150:1150) (1211:1211:1211)) - (PORT datac (613:613:613) (635:635:635)) - (PORT datad (838:838:838) (884:884:884)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1156:1156:1156)) - (PORT datab (2630:2630:2630) (2710:2710:2710)) - (PORT datac (839:839:839) (858:858:858)) - (PORT datad (1609:1609:1609) (1688:1688:1688)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1228:1228:1228)) - (PORT datab (684:684:684) (751:751:751)) - (PORT datac (960:960:960) (949:949:949)) - (PORT datad (629:629:629) (648:648:648)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (2348:2348:2348) (2418:2418:2418)) - (PORT datab (896:896:896) (926:926:926)) - (PORT datac (560:560:560) (574:574:574)) - (PORT datad (1062:1062:1062) (1090:1090:1090)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1692:1692:1692) (1758:1758:1758)) - (PORT datab (1638:1638:1638) (1688:1688:1688)) - (PORT datac (1624:1624:1624) (1660:1660:1660)) - (PORT datad (1174:1174:1174) (1183:1183:1183)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT datac (807:807:807) (852:852:852)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (366:366:366)) - (PORT datab (208:208:208) (251:251:251)) - (PORT datac (784:784:784) (817:817:817)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (902:902:902)) - (PORT datab (890:890:890) (906:906:906)) - (PORT datac (873:873:873) (905:905:905)) - (PORT datad (614:614:614) (662:662:662)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1877:1877:1877) (2008:2008:2008)) - (PORT datab (1729:1729:1729) (1814:1814:1814)) - (PORT datac (1724:1724:1724) (1821:1821:1821)) - (PORT datad (1358:1358:1358) (1437:1437:1437)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1244:1244:1244) (1332:1332:1332)) - (PORT datab (879:879:879) (901:901:901)) - (PORT datac (1574:1574:1574) (1584:1584:1584)) - (PORT datad (1371:1371:1371) (1418:1418:1418)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (996:996:996) (1099:1099:1099)) - (PORT datac (849:849:849) (864:864:864)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (881:881:881) (903:903:903)) - (PORT datac (1603:1603:1603) (1633:1633:1633)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~3) - (DELAY - (ABSOLUTE - (PORT datab (1035:1035:1035) (1113:1113:1113)) - (PORT datad (919:919:919) (1024:1024:1024)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1090:1090:1090)) - (PORT datab (684:684:684) (744:744:744)) - (PORT datac (1078:1078:1078) (1083:1083:1083)) - (PORT datad (1003:1003:1003) (1007:1007:1007)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (945:945:945) (1002:1002:1002)) - (PORT datac (1362:1362:1362) (1459:1459:1459)) - (PORT datad (631:631:631) (652:652:652)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1134:1134:1134) (1198:1198:1198)) - (PORT datab (683:683:683) (744:744:744)) - (PORT datac (622:622:622) (630:630:630)) - (PORT datad (1090:1090:1090) (1107:1107:1107)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (922:922:922)) - (PORT datab (1427:1427:1427) (1495:1495:1495)) - (PORT datac (847:847:847) (882:882:882)) - (PORT datad (819:819:819) (851:851:851)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1591:1591:1591) (1608:1608:1608)) - (PORT datab (1991:1991:1991) (2037:2037:2037)) - (PORT datac (854:854:854) (878:878:878)) - (PORT datad (1151:1151:1151) (1202:1202:1202)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1206:1206:1206)) - (PORT datab (857:857:857) (880:880:880)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (752:752:752) (761:761:761)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT datab (942:942:942) (1011:1011:1011)) - (PORT datac (1171:1171:1171) (1231:1231:1231)) - (PORT datad (874:874:874) (959:959:959)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (620:620:620)) - (PORT datab (654:654:654) (679:679:679)) - (PORT datac (1033:1033:1033) (1079:1079:1079)) - (PORT datad (594:594:594) (623:623:623)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (666:666:666)) - (PORT datab (970:970:970) (1062:1062:1062)) - (PORT datac (1102:1102:1102) (1165:1165:1165)) - (PORT datad (1382:1382:1382) (1445:1445:1445)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1188:1188:1188) (1227:1227:1227)) - (PORT datab (680:680:680) (738:738:738)) - (PORT datac (862:862:862) (864:864:864)) - (PORT datad (629:629:629) (646:646:646)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (1423:1423:1423) (1492:1492:1492)) - (PORT datab (1617:1617:1617) (1667:1667:1667)) - (PORT datac (1099:1099:1099) (1161:1161:1161)) - (PORT datad (937:937:937) (1028:1028:1028)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1098:1098:1098) (1124:1124:1124)) - (PORT datab (1105:1105:1105) (1138:1138:1138)) - (PORT datac (1440:1440:1440) (1492:1492:1492)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (626:626:626) (664:664:664)) - (PORT datad (195:195:195) (219:219:219)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (988:988:988)) - (PORT datab (654:654:654) (698:698:698)) - (PORT datac (920:920:920) (995:995:995)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1277:1277:1277)) - (PORT datab (1363:1363:1363) (1386:1386:1386)) - (PORT datac (2031:2031:2031) (2070:2070:2070)) - (PORT datad (916:916:916) (941:941:941)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1877:1877:1877) (2007:2007:2007)) - (PORT datab (1736:1736:1736) (1819:1819:1819)) - (PORT datac (1714:1714:1714) (1803:1803:1803)) - (PORT datad (1375:1375:1375) (1450:1450:1450)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1286:1286:1286)) - (PORT datab (1175:1175:1175) (1253:1253:1253)) - (PORT datac (1145:1145:1145) (1253:1253:1253)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1372:1372:1372) (1431:1431:1431)) - (PORT datab (235:235:235) (280:280:280)) - (PORT datac (1726:1726:1726) (1733:1733:1733)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1416:1416:1416) (1519:1519:1519)) - (PORT datac (1495:1495:1495) (1561:1561:1561)) - (PORT datad (1338:1338:1338) (1413:1413:1413)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~2) - (DELAY - (ABSOLUTE - (PORT datac (1373:1373:1373) (1450:1450:1450)) - (PORT datad (1324:1324:1324) (1390:1390:1390)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1679:1679:1679) (1758:1758:1758)) - (PORT datab (1682:1682:1682) (1746:1746:1746)) - (PORT datac (1078:1078:1078) (1119:1119:1119)) - (PORT datad (1847:1847:1847) (1902:1902:1902)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1598:1598:1598) (1605:1605:1605)) - (PORT datab (222:222:222) (262:262:262)) - (PORT datac (1716:1716:1716) (1808:1808:1808)) - (PORT datad (1125:1125:1125) (1166:1166:1166)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (773:773:773) (781:781:781)) - (PORT datab (1934:1934:1934) (1975:1975:1975)) - (PORT datac (780:780:780) (805:805:805)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1242:1242:1242) (1320:1320:1320)) - (PORT datab (746:746:746) (744:744:744)) - (PORT datac (743:743:743) (755:755:755)) - (PORT datad (814:814:814) (815:815:815)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1047:1047:1047) (1066:1066:1066)) - (PORT datab (568:568:568) (589:589:589)) - (PORT datac (679:679:679) (744:744:744)) - (PORT datad (849:849:849) (866:866:866)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1280:1280:1280) (1301:1301:1301)) - (PORT datab (1781:1781:1781) (1854:1854:1854)) - (PORT datac (1635:1635:1635) (1727:1727:1727)) - (PORT datad (849:849:849) (868:868:868)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~33) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1039:1039:1039)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (1247:1247:1247) (1262:1262:1262)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1079:1079:1079) (1114:1114:1114)) - (PORT datab (878:878:878) (893:893:893)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (542:542:542) (554:554:554)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1228:1228:1228)) - (PORT datad (1049:1049:1049) (1107:1107:1107)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1076:1076:1076) (1146:1146:1146)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (818:818:818) (818:818:818)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (1246:1246:1246) (1311:1311:1311)) - (PORT datad (3285:3285:3285) (3516:3516:3516)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_DAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (574:574:574) (571:571:571)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (380:380:380)) - (PORT datab (279:279:279) (371:371:371)) - (PORT datad (248:248:248) (325:325:325)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_CLK\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT asdata (3742:3742:3742) (4083:4083:4083)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (240:240:240) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (300:300:300)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT asdata (569:569:569) (647:647:647)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (300:300:300)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (480:480:480)) - (PORT datab (251:251:251) (335:335:335)) - (PORT datac (225:225:225) (304:304:304)) - (PORT datad (223:223:223) (295:295:295)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (344:344:344)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (225:225:225) (298:298:298)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (261:261:261)) - (PORT datad (227:227:227) (300:300:300)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) - (DELAY - (ABSOLUTE - (PORT dataa (212:212:212) (261:261:261)) - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (227:227:227) (300:300:300)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (PORT ena (1590:1590:1590) (1670:1670:1670)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (381:381:381)) - (PORT datab (265:265:265) (356:356:356)) - (PORT datad (245:245:245) (325:325:325)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (PORT ena (1590:1590:1590) (1670:1670:1670)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (381:381:381)) - (PORT datab (277:277:277) (371:371:371)) - (PORT datad (239:239:239) (317:317:317)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (PORT ena (1590:1590:1590) (1670:1670:1670)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (277:277:277) (376:376:376)) - (PORT datab (280:280:280) (375:375:375)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (PORT ena (1590:1590:1590) (1670:1670:1670)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (277:277:277) (380:380:380)) - (PORT datab (277:277:277) (373:373:373)) - (PORT datac (3561:3561:3561) (3920:3920:3920)) - (PORT datad (247:247:247) (328:328:328)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (276:276:276) (380:380:380)) - (PORT datac (249:249:249) (338:338:338)) - (PORT datad (248:248:248) (328:328:328)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (938:938:938) (1038:1038:1038)) - (PORT datad (242:242:242) (321:321:321)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT asdata (3947:3947:3947) (4298:4298:4298)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1255:1255:1255) (1259:1259:1259)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT asdata (560:560:560) (634:634:634)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1255:1255:1255) (1259:1259:1259)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT asdata (592:592:592) (679:679:679)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1255:1255:1255) (1259:1259:1259)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT asdata (1280:1280:1280) (1341:1341:1341)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1687:1687:1687) (1736:1736:1736)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT asdata (950:950:950) (1017:1017:1017)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1255:1255:1255) (1259:1259:1259)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT asdata (1532:1532:1532) (1590:1590:1590)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1687:1687:1687) (1736:1736:1736)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT asdata (935:935:935) (997:997:997)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1687:1687:1687) (1736:1736:1736)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT asdata (1492:1492:1492) (1552:1552:1552)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1255:1255:1255) (1259:1259:1259)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT asdata (1428:1428:1428) (1495:1495:1495)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1253:1253:1253) (1261:1261:1261)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1245:1245:1245) (1303:1303:1303)) - (PORT datab (457:457:457) (531:531:531)) - (PORT datac (648:648:648) (721:721:721)) - (PORT datad (1168:1168:1168) (1228:1228:1228)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (714:714:714)) - (PORT datab (279:279:279) (374:374:374)) - (PORT datad (628:628:628) (692:692:692)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (413:413:413)) - (PORT datac (550:550:550) (554:554:554)) - (PORT datad (246:246:246) (317:317:317)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) - (DELAY - (ABSOLUTE - (PORT dataa (973:973:973) (1081:1081:1081)) - (PORT datab (210:210:210) (252:252:252)) - (PORT datac (3561:3561:3561) (3918:3918:3918)) - (PORT datad (521:521:521) (533:533:533)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1281:1281:1281)) - (PORT datab (646:646:646) (712:712:712)) - (PORT datac (248:248:248) (337:337:337)) - (PORT datad (916:916:916) (976:976:976)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (274:274:274) (363:363:363)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (1152:1152:1152) (1213:1213:1213)) - (PORT datad (626:626:626) (689:689:689)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1057:1057:1057)) - (PORT datad (643:643:643) (661:661:661)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|extended) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1740:1740:1740) (1806:1806:1806)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (720:720:720)) - (PORT datab (278:278:278) (373:373:373)) - (PORT datac (672:672:672) (732:732:732)) - (PORT datad (702:702:702) (772:772:772)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1058:1058:1058)) - (PORT datab (1128:1128:1128) (1217:1217:1217)) - (PORT datad (643:643:643) (661:661:661)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1248:1248:1248) (1306:1306:1306)) - (PORT datab (449:449:449) (527:527:527)) - (PORT datac (653:653:653) (728:728:728)) - (PORT datad (1163:1163:1163) (1227:1227:1227)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1242:1242:1242) (1306:1306:1306)) - (PORT datac (649:649:649) (723:723:723)) - (PORT datad (424:424:424) (494:494:494)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1243:1243:1243) (1305:1305:1305)) - (PORT datab (457:457:457) (532:532:532)) - (PORT datac (649:649:649) (722:722:722)) - (PORT datad (1167:1167:1167) (1228:1228:1228)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (269:269:269)) - (PORT datab (471:471:471) (542:542:542)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (1163:1163:1163) (1227:1227:1227)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (471:471:471) (543:543:543)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (680:680:680) (743:743:743)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (981:981:981) (1047:1047:1047)) - (PORT datad (322:322:322) (340:340:340)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1488:1488:1488)) - (PORT datab (1195:1195:1195) (1239:1239:1239)) - (PORT datac (796:796:796) (820:820:820)) - (PORT datad (937:937:937) (1025:1025:1025)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1877:1877:1877) (2013:2013:2013)) - (PORT datab (1731:1731:1731) (1817:1817:1817)) - (PORT datac (1725:1725:1725) (1821:1821:1821)) - (PORT datad (1358:1358:1358) (1432:1432:1432)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT datab (1398:1398:1398) (1482:1482:1482)) - (PORT datac (1724:1724:1724) (1817:1817:1817)) - (PORT datad (1699:1699:1699) (1780:1780:1780)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1308:1308:1308)) - (PORT datab (1174:1174:1174) (1249:1249:1249)) - (PORT datad (1362:1362:1362) (1430:1430:1430)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (915:915:915)) - (PORT datab (925:925:925) (945:945:945)) - (PORT datac (794:794:794) (818:818:818)) - (PORT datad (783:783:783) (805:805:805)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (916:916:916)) - (PORT datab (1152:1152:1152) (1198:1198:1198)) - (PORT datac (799:799:799) (826:826:826)) - (PORT datad (211:211:211) (243:243:243)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1206:1206:1206) (1317:1317:1317)) - (PORT datab (1158:1158:1158) (1237:1237:1237)) - (PORT datac (542:542:542) (575:575:575)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (870:870:870)) - (PORT datab (873:873:873) (886:886:886)) - (PORT datac (543:543:543) (559:559:559)) - (PORT datad (853:853:853) (879:879:879)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (960:960:960) (1060:1060:1060)) - (PORT datad (1182:1182:1182) (1276:1276:1276)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1151:1151:1151)) - (PORT datab (684:684:684) (747:747:747)) - (PORT datac (1130:1130:1130) (1169:1169:1169)) - (PORT datad (1040:1040:1040) (1067:1067:1067)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1225:1225:1225)) - (PORT datab (204:204:204) (245:245:245)) - (PORT datac (1130:1130:1130) (1169:1169:1169)) - (PORT datad (628:628:628) (644:644:644)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (917:917:917) (986:986:986)) - (PORT datac (1127:1127:1127) (1173:1173:1173)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT datab (1164:1164:1164) (1236:1236:1236)) - (PORT datac (1315:1315:1315) (1380:1380:1380)) - (PORT datad (1151:1151:1151) (1223:1223:1223)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (667:667:667)) - (PORT datab (828:828:828) (884:884:884)) - (PORT datac (1223:1223:1223) (1221:1221:1221)) - (PORT datad (847:847:847) (865:865:865)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1724:1724:1724) (1799:1799:1799)) - (PORT datab (948:948:948) (1037:1037:1037)) - (PORT datac (1187:1187:1187) (1228:1228:1228)) - (PORT datad (1718:1718:1718) (1734:1734:1734)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (2306:2306:2306) (2356:2356:2356)) - (PORT datab (923:923:923) (939:939:939)) - (PORT datac (924:924:924) (1014:1014:1014)) - (PORT datad (943:943:943) (1006:1006:1006)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (251:251:251)) - (PORT datab (878:878:878) (898:898:898)) - (PORT datac (964:964:964) (1076:1076:1076)) - (PORT datad (964:964:964) (1056:1056:1056)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (264:264:264)) - (PORT datab (1265:1265:1265) (1294:1294:1294)) - (PORT datac (1858:1858:1858) (1882:1882:1882)) - (PORT datad (902:902:902) (916:916:916)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1249:1249:1249) (1331:1331:1331)) - (PORT datac (1305:1305:1305) (1403:1403:1403)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1039:1039:1039)) - (PORT datab (1102:1102:1102) (1119:1119:1119)) - (PORT datac (1381:1381:1381) (1423:1423:1423)) - (PORT datad (922:922:922) (967:967:967)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) - (DELAY - (ABSOLUTE - (PORT dataa (2350:2350:2350) (2446:2446:2446)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (657:657:657) (673:673:673)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1296:1296:1296) (1312:1312:1312)) - (PORT datab (1119:1119:1119) (1161:1161:1161)) - (PORT datac (1238:1238:1238) (1234:1234:1234)) - (PORT datad (1063:1063:1063) (1086:1086:1086)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datad (1149:1149:1149) (1260:1260:1260)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1542:1542:1542)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (298:298:298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1542:1542:1542)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1542:1542:1542)) - (PORT asdata (566:566:566) (644:644:644)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|resets_\|clrpc_int\~0) (DELAY (ABSOLUTE - (PORT dataa (939:939:939) (1000:1000:1000)) - (PORT datab (941:941:941) (1038:1038:1038)) - (PORT datad (908:908:908) (963:963:963)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (649:649:649) (728:728:728)) + (PORT datab (605:605:605) (665:665:665)) + (PORT datad (1168:1168:1168) (1217:1217:1217)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -4265,9 +11429,9 @@ (INSTANCE z80_\|resets_\|clrpc_int) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1542:1542:1542)) + (PORT clk (1548:1548:1548) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) + (PORT clrn (1597:1597:1597) (1572:1572:1572)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -4281,9 +11445,9 @@ (INSTANCE z80_\|resets_\|clrpc\~0) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (340:340:340)) - (PORT datab (248:248:248) (332:332:332)) - (PORT datad (219:219:219) (288:288:288)) + (PORT dataa (251:251:251) (340:340:340)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datad (217:217:217) (285:285:285)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -4293,8444 +11457,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (INSTANCE z80_\|address_latch_\|abusz\[7\]) (DELAY (ABSOLUTE - (PORT datab (573:573:573) (612:612:612)) - (PORT datac (1129:1129:1129) (1205:1205:1205)) - (PORT datad (1308:1308:1308) (1372:1372:1372)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1720:1720:1720) (1795:1795:1795)) - (PORT datab (808:808:808) (835:835:835)) - (PORT datac (1287:1287:1287) (1327:1327:1327)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal38\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2173:2173:2173) (2229:2229:2229)) - (PORT datab (1872:1872:1872) (1963:1963:1963)) - (PORT datac (1447:1447:1447) (1461:1461:1461)) - (PORT datad (1644:1644:1644) (1691:1691:1691)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) - (DELAY - (ABSOLUTE - (PORT datac (1800:1800:1800) (1850:1850:1850)) - (PORT datad (1608:1608:1608) (1625:1625:1625)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (463:463:463)) - (PORT datab (262:262:262) (312:312:312)) - (PORT datac (2122:2122:2122) (2177:2177:2177)) - (PORT datad (1377:1377:1377) (1380:1380:1380)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (953:953:953)) - (PORT datab (701:701:701) (754:754:754)) - (PORT datac (1019:1019:1019) (1030:1030:1030)) - (PORT datad (1648:1648:1648) (1732:1732:1732)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1149:1149:1149)) - (PORT datab (941:941:941) (973:973:973)) - (PORT datac (605:605:605) (631:631:631)) - (PORT datad (1608:1608:1608) (1686:1686:1686)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1686:1686:1686) (1775:1775:1775)) - (PORT datab (198:198:198) (235:235:235)) - (PORT datac (824:824:824) (871:871:871)) - (PORT datad (667:667:667) (717:717:717)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1929:1929:1929) (1987:1987:1987)) - (PORT datab (566:566:566) (574:574:574)) - (PORT datac (1183:1183:1183) (1216:1216:1216)) - (PORT datad (2316:2316:2316) (2385:2385:2385)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (883:883:883)) - (PORT datab (1669:1669:1669) (1765:1765:1765)) - (PORT datac (1248:1248:1248) (1260:1260:1260)) - (PORT datad (853:853:853) (876:876:876)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1505:1505:1505) (1560:1560:1560)) - (PORT datab (1271:1271:1271) (1295:1295:1295)) - (PORT datac (2137:2137:2137) (2227:2227:2227)) - (PORT datad (909:909:909) (984:984:984)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT datac (2486:2486:2486) (2523:2523:2523)) - (PORT datad (2373:2373:2373) (2439:2439:2439)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (821:821:821)) - (PORT datab (1216:1216:1216) (1248:1248:1248)) - (PORT datac (528:528:528) (548:548:548)) - (PORT datad (2318:2318:2318) (2388:2388:2388)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (946:946:946) (1019:1019:1019)) - (PORT datad (1312:1312:1312) (1370:1370:1370)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (654:654:654)) - (PORT datab (637:637:637) (661:661:661)) - (PORT datac (816:816:816) (850:850:850)) - (PORT datad (1029:1029:1029) (1043:1043:1043)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (974:974:974)) - (PORT datac (1082:1082:1082) (1129:1129:1129)) - (PORT datad (1852:1852:1852) (1910:1910:1910)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1246:1246:1246)) - (PORT datab (1056:1056:1056) (1096:1096:1096)) - (PORT datac (1273:1273:1273) (1310:1310:1310)) - (PORT datad (2941:2941:2941) (2984:2984:2984)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (908:908:908)) - (PORT datab (2463:2463:2463) (2519:2519:2519)) - (PORT datac (865:865:865) (889:889:889)) - (PORT datad (2937:2937:2937) (2979:2979:2979)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (940:940:940)) - (PORT datab (1144:1144:1144) (1213:1213:1213)) - (PORT datac (1648:1648:1648) (1729:1729:1729)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (961:961:961)) - (PORT datab (949:949:949) (1040:1040:1040)) - (PORT datac (1287:1287:1287) (1327:1327:1327)) - (PORT datad (1178:1178:1178) (1219:1219:1219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (263:263:263)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1038:1038:1038) (1097:1097:1097)) - (PORT datab (1401:1401:1401) (1490:1490:1490)) - (PORT datac (1717:1717:1717) (1811:1811:1811)) - (PORT datad (1706:1706:1706) (1780:1780:1780)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1337:1337:1337) (1395:1395:1395)) - (PORT datab (636:636:636) (676:676:676)) - (PORT datac (1460:1460:1460) (1490:1490:1490)) - (PORT datad (932:932:932) (963:963:963)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1214:1214:1214)) - (PORT datac (576:576:576) (612:612:612)) - (PORT datad (1351:1351:1351) (1408:1408:1408)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (394:394:394)) - (PORT datab (882:882:882) (920:920:920)) - (PORT datac (1134:1134:1134) (1185:1185:1185)) - (PORT datad (1583:1583:1583) (1638:1638:1638)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1117:1117:1117)) - (PORT datac (1023:1023:1023) (1033:1033:1033)) - (PORT datad (959:959:959) (1056:1056:1056)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2966:2966:2966) (3024:3024:3024)) - (PORT datab (2463:2463:2463) (2524:2524:2524)) - (PORT datac (822:822:822) (873:873:873)) - (PORT datad (1152:1152:1152) (1205:1205:1205)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) - (DELAY - (ABSOLUTE - (PORT dataa (961:961:961) (1025:1025:1025)) - (PORT datab (1314:1314:1314) (1346:1346:1346)) - (PORT datac (822:822:822) (871:871:871)) - (PORT datad (1621:1621:1621) (1735:1735:1735)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (887:887:887)) - (PORT datab (884:884:884) (932:932:932)) - (PORT datac (833:833:833) (862:862:862)) - (PORT datad (619:619:619) (633:633:633)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1244:1244:1244)) - (PORT datab (1061:1061:1061) (1102:1102:1102)) - (PORT datac (1268:1268:1268) (1305:1305:1305)) - (PORT datad (2936:2936:2936) (2978:2978:2978)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (769:769:769) (869:869:869)) - (PORT datab (1055:1055:1055) (1137:1137:1137)) - (PORT datac (662:662:662) (756:756:756)) - (PORT datad (993:993:993) (1019:1019:1019)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (679:679:679)) - (PORT datab (861:861:861) (876:876:876)) - (PORT datad (819:819:819) (847:847:847)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1083:1083:1083)) - (PORT datab (643:643:643) (662:662:662)) - (PORT datac (1021:1021:1021) (1013:1013:1013)) - (PORT datad (887:887:887) (905:905:905)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2352:2352:2352) (2443:2443:2443)) - (PORT datab (955:955:955) (1005:1005:1005)) - (PORT datac (1491:1491:1491) (1535:1535:1535)) - (PORT datad (799:799:799) (819:819:819)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1322:1322:1322)) - (PORT datab (208:208:208) (251:251:251)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (845:845:845) (864:864:864)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (939:939:939)) - (PORT datab (838:838:838) (877:877:877)) - (PORT datac (520:520:520) (532:532:532)) - (PORT datad (807:807:807) (823:823:823)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT datab (1403:1403:1403) (1491:1491:1491)) - (PORT datac (1716:1716:1716) (1807:1807:1807)) - (PORT datad (1704:1704:1704) (1782:1782:1782)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (715:715:715)) - (PORT datab (868:868:868) (900:900:900)) - (PORT datac (902:902:902) (992:992:992)) - (PORT datad (1823:1823:1823) (1888:1888:1888)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datab (1003:1003:1003) (1074:1074:1074)) - (PORT datac (962:962:962) (1040:1040:1040)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (939:939:939) (1029:1029:1029)) - (PORT datab (870:870:870) (897:897:897)) - (PORT datac (1154:1154:1154) (1172:1172:1172)) - (PORT datad (1822:1822:1822) (1885:1885:1885)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1852:1852:1852) (1933:1933:1933)) - (PORT datab (868:868:868) (898:898:898)) - (PORT datac (902:902:902) (992:992:992)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1427:1427:1427)) - (PORT datab (873:873:873) (892:892:892)) - (PORT datac (970:970:970) (1026:1026:1026)) - (PORT datad (1222:1222:1222) (1261:1261:1261)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1428:1428:1428)) - (PORT datab (1250:1250:1250) (1300:1300:1300)) - (PORT datac (977:977:977) (1031:1031:1031)) - (PORT datad (1141:1141:1141) (1164:1164:1164)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (202:202:202) (239:239:239)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT datac (2490:2490:2490) (2531:2531:2531)) - (PORT datad (2377:2377:2377) (2445:2445:2445)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (276:276:276)) - (PORT datab (1413:1413:1413) (1479:1479:1479)) - (PORT datac (1266:1266:1266) (1304:1304:1304)) - (PORT datad (212:212:212) (245:245:245)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (913:913:913)) - (PORT datab (1076:1076:1076) (1092:1092:1092)) - (PORT datac (734:734:734) (756:756:756)) - (PORT datad (1072:1072:1072) (1089:1089:1089)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (698:698:698)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (539:539:539) (542:542:542)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (3094:3094:3094) (3188:3188:3188)) - (PORT datab (2162:2162:2162) (2272:2272:2272)) - (PORT datac (837:837:837) (865:865:865)) - (PORT datad (1017:1017:1017) (1050:1050:1050)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (908:908:908)) - (PORT datab (1601:1601:1601) (1676:1676:1676)) - (PORT datac (815:815:815) (882:882:882)) - (PORT datad (886:886:886) (959:959:959)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (1281:1281:1281) (1284:1284:1284)) - (PORT datac (1019:1019:1019) (1067:1067:1067)) - (PORT datad (687:687:687) (750:750:750)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1270:1270:1270) (1342:1342:1342)) - (PORT datab (893:893:893) (934:934:934)) - (PORT datac (860:860:860) (927:927:927)) - (PORT datad (1689:1689:1689) (1742:1742:1742)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1319:1319:1319)) - (PORT datab (1778:1778:1778) (1851:1851:1851)) - (PORT datac (1019:1019:1019) (1042:1042:1042)) - (PORT datad (806:806:806) (850:850:850)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1271:1271:1271) (1342:1342:1342)) - (PORT datab (1259:1259:1259) (1275:1275:1275)) - (PORT datac (827:827:827) (862:862:862)) - (PORT datad (1689:1689:1689) (1741:1741:1741)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1271:1271:1271) (1346:1346:1346)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1687:1687:1687) (1744:1744:1744)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (856:856:856) (875:875:875)) - (PORT datac (1062:1062:1062) (1063:1063:1063)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (870:870:870)) - (PORT datab (583:583:583) (596:596:596)) - (PORT datac (736:736:736) (747:747:747)) - (PORT datad (1298:1298:1298) (1372:1372:1372)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (943:943:943)) - (PORT datab (1683:1683:1683) (1759:1759:1759)) - (PORT datac (1219:1219:1219) (1307:1307:1307)) - (PORT datad (1122:1122:1122) (1176:1176:1176)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (937:937:937)) - (PORT datab (1144:1144:1144) (1212:1212:1212)) - (PORT datac (1647:1647:1647) (1729:1729:1729)) - (PORT datad (879:879:879) (931:931:931)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (656:656:656) (702:702:702)) - (PORT datac (638:638:638) (695:695:695)) - (PORT datad (1045:1045:1045) (1048:1048:1048)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (869:869:869)) - (PORT datab (615:615:615) (625:625:625)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT datab (1267:1267:1267) (1389:1389:1389)) - (PORT datac (1170:1170:1170) (1280:1280:1280)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1383:1383:1383) (1413:1413:1413)) - (PORT datab (364:364:364) (401:401:401)) - (PORT datac (1219:1219:1219) (1212:1212:1212)) - (PORT datad (794:794:794) (827:827:827)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1207:1207:1207)) - (PORT datab (1118:1118:1118) (1162:1162:1162)) - (PORT datac (1103:1103:1103) (1174:1174:1174)) - (PORT datad (1015:1015:1015) (1048:1048:1048)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (2158:2158:2158) (2273:2273:2273)) - (PORT datac (838:838:838) (868:868:868)) - (PORT datad (1035:1035:1035) (1061:1061:1061)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (864:864:864)) - (PORT datab (713:713:713) (786:786:786)) - (PORT datac (635:635:635) (664:664:664)) - (PORT datad (1021:1021:1021) (1034:1034:1034)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1050:1050:1050)) - (PORT datab (2169:2169:2169) (2212:2212:2212)) - (PORT datac (2222:2222:2222) (2256:2256:2256)) - (PORT datad (1453:1453:1453) (1583:1583:1583)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal69\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1342:1342:1342)) - (PORT datab (1413:1413:1413) (1485:1485:1485)) - (PORT datac (2490:2490:2490) (2529:2529:2529)) - (PORT datad (2374:2374:2374) (2444:2444:2444)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1379:1379:1379)) - (PORT datab (1147:1147:1147) (1218:1218:1218)) - (PORT datac (859:859:859) (889:889:889)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (700:700:700)) - (PORT datab (259:259:259) (305:305:305)) - (PORT datad (204:204:204) (235:235:235)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1879:1879:1879) (1963:1963:1963)) - (PORT datab (221:221:221) (268:268:268)) - (PORT datac (552:552:552) (573:573:573)) - (PORT datad (188:188:188) (221:221:221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (323:323:323) (428:428:428)) - (PORT datab (240:240:240) (279:279:279)) - (PORT datac (523:523:523) (526:526:526)) - (PORT datad (297:297:297) (385:385:385)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (717:717:717)) - (PORT datab (816:816:816) (859:859:859)) - (PORT datac (868:868:868) (896:896:896)) - (PORT datad (398:398:398) (464:464:464)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1208:1208:1208) (1225:1225:1225)) - (PORT datab (1091:1091:1091) (1117:1117:1117)) - (PORT datac (1235:1235:1235) (1364:1364:1364)) - (PORT datad (1374:1374:1374) (1428:1428:1428)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1373:1373:1373) (1425:1425:1425)) - (PORT datab (595:595:595) (614:614:614)) - (PORT datac (1065:1065:1065) (1122:1122:1122)) - (PORT datad (2820:2820:2820) (2882:2882:2882)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1459:1459:1459) (1481:1481:1481)) - (PORT datab (2372:2372:2372) (2462:2462:2462)) - (PORT datac (1473:1473:1473) (1527:1527:1527)) - (PORT datad (2372:2372:2372) (2454:2454:2454)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1671:1671:1671) (1731:1731:1731)) - (PORT datab (1845:1845:1845) (1972:1972:1972)) - (PORT datad (2133:2133:2133) (2181:2181:2181)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1678:1678:1678) (1761:1761:1761)) - (PORT datab (1680:1680:1680) (1745:1745:1745)) - (PORT datac (1076:1076:1076) (1116:1116:1116)) - (PORT datad (1844:1844:1844) (1900:1900:1900)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (284:284:284)) - (PORT datab (1212:1212:1212) (1266:1266:1266)) - (PORT datac (857:857:857) (879:879:879)) - (PORT datad (1147:1147:1147) (1198:1198:1198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT datab (1729:1729:1729) (1822:1822:1822)) - (PORT datac (1724:1724:1724) (1819:1819:1819)) - (PORT datad (1834:1834:1834) (1966:1966:1966)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1296:1296:1296)) - (PORT datab (868:868:868) (899:899:899)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (613:613:613) (636:636:636)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1176:1176:1176)) - (PORT datab (1187:1187:1187) (1217:1217:1217)) - (PORT datac (1775:1775:1775) (1849:1849:1849)) - (PORT datad (1018:1018:1018) (1052:1052:1052)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1929:1929:1929) (1985:1985:1985)) - (PORT datab (1110:1110:1110) (1162:1162:1162)) - (PORT datac (1129:1129:1129) (1182:1182:1182)) - (PORT datad (1807:1807:1807) (1864:1864:1864)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT dataa (2669:2669:2669) (2767:2767:2767)) - (PORT datac (529:529:529) (547:547:547)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (457:457:457)) - (PORT datab (1367:1367:1367) (1424:1424:1424)) - (PORT datac (1361:1361:1361) (1425:1425:1425)) - (PORT datad (379:379:379) (399:399:399)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (632:632:632)) - (PORT datab (935:935:935) (983:983:983)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1138:1138:1138) (1192:1192:1192)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1492:1492:1492) (1528:1528:1528)) - (PORT datab (1294:1294:1294) (1344:1344:1344)) - (PORT datac (602:602:602) (637:637:637)) - (PORT datad (598:598:598) (636:636:636)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1661:1661:1661) (1717:1717:1717)) - (PORT datab (1367:1367:1367) (1414:1414:1414)) - (PORT datac (528:528:528) (545:545:545)) - (PORT datad (633:633:633) (674:674:674)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1422:1422:1422)) - (PORT datab (591:591:591) (610:610:610)) - (PORT datac (1061:1061:1061) (1121:1121:1121)) - (PORT datad (2824:2824:2824) (2889:2889:2889)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT datac (557:557:557) (583:583:583)) - (PORT datad (1067:1067:1067) (1062:1062:1062)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (923:923:923) (987:987:987)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (613:613:613)) - (PORT datab (1046:1046:1046) (1127:1127:1127)) - (PORT datac (1253:1253:1253) (1275:1275:1275)) - (PORT datad (1107:1107:1107) (1184:1184:1184)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (909:909:909)) - (PORT datab (652:652:652) (676:676:676)) - (PORT datac (1117:1117:1117) (1132:1132:1132)) - (PORT datad (1302:1302:1302) (1291:1291:1291)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1781:1781:1781) (1836:1836:1836)) - (PORT datab (712:712:712) (783:783:783)) - (PORT datac (357:357:357) (383:383:383)) - (PORT datad (1244:1244:1244) (1239:1239:1239)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (418:418:418)) - (PORT datab (1084:1084:1084) (1123:1123:1123)) - (PORT datac (1018:1018:1018) (1065:1065:1065)) - (PORT datad (1245:1245:1245) (1240:1240:1240)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1187:1187:1187)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (852:852:852) (865:865:865)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (1903:1903:1903) (2027:2027:2027)) - (PORT datab (238:238:238) (284:284:284)) - (PORT datac (1331:1331:1331) (1407:1407:1407)) - (PORT datad (877:877:877) (897:897:897)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (1957:1957:1957) (2084:2084:2084)) - (PORT datab (921:921:921) (940:940:940)) - (PORT datac (925:925:925) (1017:1017:1017)) - (PORT datad (943:943:943) (1008:1008:1008)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1187:1187:1187)) - (PORT datab (1069:1069:1069) (1129:1129:1129)) - (PORT datac (1133:1133:1133) (1184:1184:1184)) - (PORT datad (999:999:999) (1031:1031:1031)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1200:1200:1200) (1213:1213:1213)) - (PORT datab (1200:1200:1200) (1267:1267:1267)) - (PORT datac (1388:1388:1388) (1438:1438:1438)) - (PORT datad (1062:1062:1062) (1080:1080:1080)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (289:289:289)) - (PORT datab (1424:1424:1424) (1519:1519:1519)) - (PORT datac (1231:1231:1231) (1361:1361:1361)) - (PORT datad (1161:1161:1161) (1174:1174:1174)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1401:1401:1401) (1470:1470:1470)) - (PORT datab (1263:1263:1263) (1395:1395:1395)) - (PORT datac (1392:1392:1392) (1486:1486:1486)) - (PORT datad (1170:1170:1170) (1275:1275:1275)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1216:1216:1216)) - (PORT datab (885:885:885) (940:940:940)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (1204:1204:1204) (1255:1255:1255)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1097:1097:1097) (1122:1122:1122)) - (PORT datab (1090:1090:1090) (1122:1122:1122)) - (PORT datac (822:822:822) (854:854:854)) - (PORT datad (1162:1162:1162) (1170:1170:1170)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2061:2061:2061) (2126:2126:2126)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (188:188:188) (228:228:228)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (713:713:713)) - (PORT datab (1147:1147:1147) (1201:1201:1201)) - (PORT datac (1368:1368:1368) (1378:1378:1378)) - (PORT datad (2367:2367:2367) (2456:2456:2456)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1281:1281:1281)) - (PORT datab (1931:1931:1931) (1944:1944:1944)) - (PORT datac (2031:2031:2031) (2070:2070:2070)) - (PORT datad (915:915:915) (939:939:939)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1564:1564:1564)) - (PORT datab (1498:1498:1498) (1596:1596:1596)) - (PORT datac (1145:1145:1145) (1174:1174:1174)) - (PORT datad (1597:1597:1597) (1652:1652:1652)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2065:2065:2065) (2130:2130:2130)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (186:186:186) (224:224:224)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1287:1287:1287) (1405:1405:1405)) - (PORT datac (1390:1390:1390) (1483:1483:1483)) - (PORT datad (846:846:846) (837:837:837)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (1473:1473:1473) (1565:1565:1565)) - (PORT datab (1334:1334:1334) (1380:1380:1380)) - (PORT datac (1334:1334:1334) (1385:1385:1385)) - (PORT datad (2128:2128:2128) (2227:2227:2227)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (1512:1512:1512) (1566:1566:1566)) - (PORT datab (1494:1494:1494) (1598:1598:1598)) - (PORT datac (2147:2147:2147) (2227:2227:2227)) - (PORT datad (2375:2375:2375) (2456:2456:2456)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1006:1006:1006)) - (PORT datab (252:252:252) (302:302:302)) - (PORT datac (1431:1431:1431) (1522:1522:1522)) - (PORT datad (550:550:550) (558:558:558)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT datac (1277:1277:1277) (1316:1316:1316)) - (PORT datad (783:783:783) (837:837:837)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT datac (1277:1277:1277) (1315:1315:1315)) - (PORT datad (782:782:782) (837:837:837)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (970:970:970)) - (PORT datab (849:849:849) (876:876:876)) - (PORT datac (844:844:844) (880:880:880)) - (PORT datad (817:817:817) (825:825:825)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (704:704:704)) - (PORT datab (865:865:865) (910:910:910)) - (PORT datac (523:523:523) (539:539:539)) - (PORT datad (595:595:595) (606:606:606)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1083:1083:1083)) - (PORT datab (1001:1001:1001) (1073:1073:1073)) - (PORT datac (2234:2234:2234) (2299:2299:2299)) - (PORT datad (1324:1324:1324) (1358:1358:1358)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1290:1290:1290) (1414:1414:1414)) - (PORT datab (1210:1210:1210) (1326:1326:1326)) - (PORT datad (865:865:865) (879:879:879)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1436:1436:1436) (1508:1508:1508)) - (PORT datab (1341:1341:1341) (1399:1399:1399)) - (PORT datac (811:811:811) (822:822:822)) - (PORT datad (799:799:799) (806:806:806)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (820:820:820)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (895:895:895)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1072:1072:1072) (1081:1081:1081)) - (PORT datad (178:178:178) (206:206:206)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1083:1083:1083)) - (PORT datab (597:597:597) (609:609:609)) - (PORT datac (359:359:359) (391:391:391)) - (PORT datad (345:345:345) (369:369:369)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1898:1898:1898) (2022:2022:2022)) - (PORT datab (1399:1399:1399) (1458:1458:1458)) - (PORT datac (1391:1391:1391) (1464:1464:1464)) - (PORT datad (884:884:884) (921:921:921)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1234:1234:1234)) - (PORT datab (655:655:655) (721:721:721)) - (PORT datac (847:847:847) (858:858:858)) - (PORT datad (637:637:637) (657:657:657)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1643:1643:1643) (1678:1678:1678)) - (PORT datab (752:752:752) (834:834:834)) - (PORT datac (210:210:210) (250:250:250)) - (PORT datad (1562:1562:1562) (1614:1614:1614)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1318:1318:1318)) - (PORT datab (637:637:637) (658:658:658)) - (PORT datac (1360:1360:1360) (1450:1450:1450)) - (PORT datad (829:829:829) (839:839:839)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1075:1075:1075) (1117:1117:1117)) - (PORT datab (2877:2877:2877) (2935:2935:2935)) - (PORT datac (886:886:886) (936:936:936)) - (PORT datad (1009:1009:1009) (1042:1042:1042)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (577:577:577)) - (PORT datab (393:393:393) (418:418:418)) - (PORT datac (657:657:657) (674:674:674)) - (PORT datad (1139:1139:1139) (1181:1181:1181)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (1015:1015:1015)) - (PORT datab (1153:1153:1153) (1237:1237:1237)) - (PORT datac (803:803:803) (848:848:848)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1529:1529:1529)) - (PORT datab (654:654:654) (724:724:724)) - (PORT datac (1129:1129:1129) (1194:1194:1194)) - (PORT datad (1002:1002:1002) (1004:1004:1004)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1878:1878:1878) (1960:1960:1960)) - (PORT datab (239:239:239) (278:278:278)) - (PORT datac (553:553:553) (571:571:571)) - (PORT datad (195:195:195) (230:230:230)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1012:1012:1012) (1026:1026:1026)) - (PORT datab (897:897:897) (948:948:948)) - (PORT datac (1362:1362:1362) (1415:1415:1415)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (1000:1000:1000) (1086:1086:1086)) - (PORT datab (995:995:995) (1065:1065:1065)) - (PORT datac (2238:2238:2238) (2300:2300:2300)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (219:219:219) (259:259:259)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1263:1263:1263) (1278:1278:1278)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT datab (1692:1692:1692) (1749:1749:1749)) - (PORT datac (1818:1818:1818) (1865:1865:1865)) - (PORT datad (2806:2806:2806) (2871:2871:2871)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (866:866:866)) - (PORT datab (833:833:833) (851:851:851)) - (PORT datac (1249:1249:1249) (1292:1292:1292)) - (PORT datad (642:642:642) (674:674:674)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1076:1076:1076) (1090:1090:1090)) - (PORT datab (534:534:534) (551:551:551)) - (PORT datac (1393:1393:1393) (1486:1486:1486)) - (PORT datad (1289:1289:1289) (1273:1273:1273)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1282:1282:1282)) - (PORT datab (856:856:856) (917:917:917)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (1273:1273:1273) (1262:1262:1262)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~5) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (464:464:464)) - (PORT datab (259:259:259) (312:312:312)) - (PORT datac (566:566:566) (577:577:577)) - (PORT datad (1091:1091:1091) (1086:1086:1086)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (264:264:264)) - (PORT datab (226:226:226) (267:267:267)) - (PORT datac (835:835:835) (893:893:893)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (902:902:902)) - (PORT datab (214:214:214) (258:258:258)) - (PORT datac (627:627:627) (643:643:643)) - (PORT datad (179:179:179) (209:209:209)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (947:947:947)) - (PORT datab (842:842:842) (867:867:867)) - (PORT datac (1638:1638:1638) (1683:1683:1683)) - (PORT datad (1289:1289:1289) (1310:1310:1310)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT datab (656:656:656) (711:711:711)) - (PORT datac (185:185:185) (224:224:224)) - (PORT datad (578:578:578) (600:600:600)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1423:1423:1423)) - (PORT datab (2851:2851:2851) (2926:2926:2926)) - (PORT datac (849:849:849) (863:863:863)) - (PORT datad (1061:1061:1061) (1093:1093:1093)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1170:1170:1170)) - (PORT datab (601:601:601) (615:615:615)) - (PORT datac (1404:1404:1404) (1456:1456:1456)) - (PORT datad (1793:1793:1793) (1847:1847:1847)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~1) - (DELAY - (ABSOLUTE - (PORT datac (1814:1814:1814) (1891:1891:1891)) - (PORT datad (1795:1795:1795) (1848:1848:1848)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (1004:1004:1004) (1080:1080:1080)) - (PORT datab (2180:2180:2180) (2304:2304:2304)) - (PORT datac (1407:1407:1407) (1457:1457:1457)) - (PORT datad (187:187:187) (216:216:216)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (827:827:827)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (571:571:571) (579:579:579)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (330:330:330) (360:360:360)) - (PORT datac (961:961:961) (1013:1013:1013)) - (PORT datad (316:316:316) (332:332:332)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (574:574:574)) - (PORT datab (974:974:974) (1006:1006:1006)) - (PORT datac (1521:1521:1521) (1565:1565:1565)) - (PORT datad (911:911:911) (967:967:967)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (959:959:959) (1022:1022:1022)) - (PORT datab (2463:2463:2463) (2519:2519:2519)) - (PORT datac (821:821:821) (867:867:867)) - (PORT datad (1278:1278:1278) (1305:1305:1305)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT datab (866:866:866) (899:899:899)) - (PORT datac (1252:1252:1252) (1262:1262:1262)) - (PORT datad (1770:1770:1770) (1779:1779:1779)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1721:1721:1721) (1769:1769:1769)) - (PORT datab (228:228:228) (269:269:269)) - (PORT datac (1179:1179:1179) (1235:1235:1235)) - (PORT datad (331:331:331) (348:348:348)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1430:1430:1430)) - (PORT datab (1364:1364:1364) (1427:1427:1427)) - (PORT datac (1357:1357:1357) (1421:1421:1421)) - (PORT datad (383:383:383) (447:447:447)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~46) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (397:397:397)) - (PORT datab (847:847:847) (861:861:861)) - (PORT datac (795:795:795) (828:828:828)) - (PORT datad (617:617:617) (641:641:641)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1272:1272:1272) (1346:1346:1346)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (1498:1498:1498) (1531:1531:1531)) - (PORT datad (615:615:615) (658:658:658)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1337:1337:1337)) - (PORT datab (1413:1413:1413) (1484:1484:1484)) - (PORT datac (2490:2490:2490) (2531:2531:2531)) - (PORT datad (2377:2377:2377) (2445:2445:2445)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1198:1198:1198)) - (PORT datab (1019:1019:1019) (1040:1040:1040)) - (PORT datac (1117:1117:1117) (1193:1193:1193)) - (PORT datad (1048:1048:1048) (1040:1040:1040)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1035:1035:1035) (1048:1048:1048)) - (PORT datac (832:832:832) (859:859:859)) - (PORT datad (1075:1075:1075) (1074:1074:1074)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1658:1658:1658) (1752:1752:1752)) - (PORT datab (227:227:227) (267:267:267)) - (PORT datac (836:836:836) (861:861:861)) - (PORT datad (1059:1059:1059) (1061:1061:1061)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1207:1207:1207) (1224:1224:1224)) - (PORT datab (1076:1076:1076) (1098:1098:1098)) - (PORT datac (1234:1234:1234) (1363:1363:1363)) - (PORT datad (1123:1123:1123) (1194:1194:1194)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1153:1153:1153)) - (PORT datab (883:883:883) (903:903:903)) - (PORT datac (1019:1019:1019) (1030:1030:1030)) - (PORT datad (1552:1552:1552) (1602:1602:1602)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (459:459:459)) - (PORT datab (260:260:260) (313:313:313)) - (PORT datac (2117:2117:2117) (2172:2172:2172)) - (PORT datad (1145:1145:1145) (1174:1174:1174)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (924:924:924)) - (PORT datab (944:944:944) (989:989:989)) - (PORT datac (818:818:818) (836:836:836)) - (PORT datad (1306:1306:1306) (1312:1312:1312)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1239:1239:1239) (1291:1291:1291)) - (PORT datab (845:845:845) (863:863:863)) - (PORT datac (660:660:660) (686:686:686)) - (PORT datad (209:209:209) (243:243:243)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1353:1353:1353)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (652:652:652) (692:692:692)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1077:1077:1077) (1079:1079:1079)) - (PORT datab (1553:1553:1553) (1612:1612:1612)) - (PORT datac (528:528:528) (548:548:548)) - (PORT datad (1098:1098:1098) (1101:1101:1101)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1222:1222:1222)) - (PORT datab (841:841:841) (865:865:865)) - (PORT datac (871:871:871) (881:881:881)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal76\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2191:2191:2191) (2270:2270:2270)) - (PORT datac (1460:1460:1460) (1513:1513:1513)) - (PORT datad (2376:2376:2376) (2457:2457:2457)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (593:593:593)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (973:973:973) (1039:1039:1039)) - (PORT datad (1320:1320:1320) (1362:1362:1362)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1357:1357:1357)) - (PORT datab (591:591:591) (616:616:616)) - (PORT datac (904:904:904) (951:951:951)) - (PORT datad (1110:1110:1110) (1164:1164:1164)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1093:1093:1093)) - (PORT datab (1135:1135:1135) (1200:1200:1200)) - (PORT datac (1356:1356:1356) (1424:1424:1424)) - (PORT datad (1069:1069:1069) (1066:1066:1066)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1221:1221:1221)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (565:565:565) (587:587:587)) - (PORT datad (562:562:562) (580:580:580)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1069:1069:1069) (1121:1121:1121)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (891:891:891)) - (PORT datab (347:347:347) (383:383:383)) - (PORT datac (826:826:826) (864:864:864)) - (PORT datad (612:612:612) (633:633:633)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) - (DELAY - (ABSOLUTE - (PORT dataa (1511:1511:1511) (1565:1565:1565)) - (PORT datab (1002:1002:1002) (1072:1072:1072)) - (PORT datac (2146:2146:2146) (2228:2228:2228)) - (PORT datad (2372:2372:2372) (2456:2456:2456)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (628:628:628)) - (PORT datab (1015:1015:1015) (1086:1086:1086)) - (PORT datac (812:812:812) (843:843:843)) - (PORT datad (1823:1823:1823) (1841:1841:1841)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1053:1053:1053) (1078:1078:1078)) - (PORT datac (1088:1088:1088) (1146:1146:1146)) - (PORT datad (1053:1053:1053) (1094:1094:1094)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (965:965:965)) - (PORT datab (360:360:360) (393:393:393)) - (PORT datac (898:898:898) (942:942:942)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1207:1207:1207)) - (PORT datad (783:783:783) (810:810:810)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1444:1444:1444)) - (PORT datab (239:239:239) (285:285:285)) - (PORT datac (2356:2356:2356) (2436:2436:2436)) - (PORT datad (1862:1862:1862) (1982:1982:1982)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (882:882:882)) - (PORT datab (883:883:883) (937:937:937)) - (PORT datac (862:862:862) (909:909:909)) - (PORT datad (1166:1166:1166) (1193:1193:1193)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1005:1005:1005)) - (PORT datab (1629:1629:1629) (1632:1632:1632)) - (PORT datac (1625:1625:1625) (1657:1657:1657)) - (PORT datad (820:820:820) (855:855:855)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (608:608:608)) - (PORT datab (1301:1301:1301) (1347:1347:1347)) - (PORT datac (835:835:835) (885:885:885)) - (PORT datad (1094:1094:1094) (1129:1129:1129)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1324:1324:1324)) - (PORT datab (244:244:244) (290:290:290)) - (PORT datac (1240:1240:1240) (1342:1342:1342)) - (PORT datad (1522:1522:1522) (1607:1607:1607)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (535:535:535) (553:553:553)) - (PORT datab (855:855:855) (900:900:900)) - (PORT datac (1042:1042:1042) (1039:1039:1039)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) - (DELAY - (ABSOLUTE - (PORT datac (1661:1661:1661) (1762:1762:1762)) - (PORT datad (1637:1637:1637) (1691:1691:1691)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1153:1153:1153) (1221:1221:1221)) - (PORT datab (325:325:325) (428:428:428)) - (PORT datac (291:291:291) (389:389:389)) - (PORT datad (900:900:900) (966:966:966)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1435:1435:1435) (1511:1511:1511)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (1302:1302:1302) (1383:1383:1383)) - (PORT datad (1377:1377:1377) (1421:1421:1421)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (2072:2072:2072) (2159:2159:2159)) - (PORT datab (852:852:852) (895:895:895)) - (PORT datac (1503:1503:1503) (1574:1574:1574)) - (PORT datad (869:869:869) (922:922:922)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2073:2073:2073) (2161:2161:2161)) - (PORT datab (1365:1365:1365) (1429:1429:1429)) - (PORT datac (1361:1361:1361) (1424:1424:1424)) - (PORT datad (868:868:868) (921:921:921)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (227:227:227) (269:269:269)) - (PORT datac (2122:2122:2122) (2174:2174:2174)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (967:967:967)) - (PORT datab (1235:1235:1235) (1321:1321:1321)) - (PORT datac (1156:1156:1156) (1232:1232:1232)) - (PORT datad (1333:1333:1333) (1382:1382:1382)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (678:678:678)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (793:793:793) (825:825:825)) - (PORT datad (525:525:525) (541:541:541)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (746:746:746) (753:753:753)) - (PORT datab (839:839:839) (854:854:854)) - (PORT datac (2499:2499:2499) (2525:2525:2525)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (649:649:649)) - (PORT datab (673:673:673) (698:698:698)) - (PORT datac (1857:1857:1857) (1882:1882:1882)) - (PORT datad (815:815:815) (827:827:827)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla21M3T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (954:954:954) (1034:1034:1034)) - (PORT datab (1346:1346:1346) (1415:1415:1415)) - (PORT datac (1134:1134:1134) (1205:1205:1205)) - (PORT datad (1151:1151:1151) (1236:1236:1236)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (266:266:266)) - (PORT datab (808:808:808) (831:831:831)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1186:1186:1186) (1209:1209:1209)) - (PORT datab (1217:1217:1217) (1245:1245:1245)) - (PORT datac (187:187:187) (225:225:225)) - (PORT datad (1535:1535:1535) (1550:1550:1550)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1416:1416:1416) (1502:1502:1502)) - (PORT datab (915:915:915) (940:940:940)) - (PORT datac (546:546:546) (561:561:561)) - (PORT datad (836:836:836) (851:851:851)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (679:679:679)) - (PORT datab (918:918:918) (941:941:941)) - (PORT datac (811:811:811) (853:853:853)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~56) - (DELAY - (ABSOLUTE - (PORT dataa (1381:1381:1381) (1411:1411:1411)) - (PORT datab (1205:1205:1205) (1259:1259:1259)) - (PORT datac (1133:1133:1133) (1200:1200:1200)) - (PORT datad (794:794:794) (827:827:827)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1104:1104:1104)) - (PORT datab (917:917:917) (972:972:972)) - (PORT datac (1630:1630:1630) (1678:1678:1678)) - (PORT datad (1138:1138:1138) (1191:1191:1191)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (396:396:396)) - (PORT datab (596:596:596) (609:609:609)) - (PORT datac (592:592:592) (638:638:638)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1221:1221:1221)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1390:1390:1390) (1467:1467:1467)) - (PORT datad (906:906:906) (957:957:957)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT datab (863:863:863) (888:888:888)) - (PORT datac (1081:1081:1081) (1086:1086:1086)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1069:1069:1069) (1125:1125:1125)) - (PORT datab (1326:1326:1326) (1330:1330:1330)) - (PORT datac (824:824:824) (865:865:865)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (651:651:651) (675:675:675)) - (PORT datac (1115:1115:1115) (1131:1131:1131)) - (PORT datad (605:605:605) (619:619:619)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (847:847:847) (876:876:876)) - (PORT datac (178:178:178) (214:214:214)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1974:1974:1974) (1981:1981:1981)) - (PORT datab (975:975:975) (1004:1004:1004)) - (PORT datac (555:555:555) (567:567:567)) - (PORT datad (222:222:222) (258:258:258)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1209:1209:1209)) - (PORT datab (822:822:822) (852:852:852)) - (PORT datad (1041:1041:1041) (1102:1102:1102)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT datab (230:230:230) (272:272:272)) - (PORT datac (1180:1180:1180) (1234:1234:1234)) - (PORT datad (331:331:331) (351:351:351)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (876:876:876)) - (PORT datab (848:848:848) (891:891:891)) - (PORT datac (372:372:372) (414:414:414)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (645:645:645) (672:672:672)) - (PORT datac (650:650:650) (701:701:701)) - (PORT datad (818:818:818) (838:838:838)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~24) - (DELAY - (ABSOLUTE - (PORT datab (922:922:922) (973:973:973)) - (PORT datac (2499:2499:2499) (2525:2525:2525)) - (PORT datad (1299:1299:1299) (1371:1371:1371)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (2359:2359:2359) (2446:2446:2446)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1190:1190:1190) (1243:1243:1243)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (647:647:647)) - (PORT datab (952:952:952) (1038:1038:1038)) - (PORT datac (638:638:638) (662:662:662)) - (PORT datad (900:900:900) (912:912:912)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1094:1094:1094) (1127:1127:1127)) - (PORT datab (1397:1397:1397) (1459:1459:1459)) - (PORT datad (906:906:906) (957:957:957)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (254:254:254)) - (PORT datac (646:646:646) (699:699:699)) - (PORT datad (616:616:616) (641:641:641)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1012:1012:1012) (1033:1033:1033)) - (PORT datab (938:938:938) (945:945:945)) - (PORT datac (1159:1159:1159) (1228:1228:1228)) - (PORT datad (772:772:772) (800:800:800)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1279:1279:1279)) - (PORT datab (848:848:848) (866:866:866)) - (PORT datac (873:873:873) (913:913:913)) - (PORT datad (1243:1243:1243) (1277:1277:1277)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1319:1319:1319) (1382:1382:1382)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datad (1205:1205:1205) (1312:1312:1312)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1570:1570:1570) (1551:1551:1551)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1595:1595:1595) (1715:1715:1715)) - (PORT datab (1294:1294:1294) (1371:1371:1371)) - (PORT datac (1004:1004:1004) (1038:1038:1038)) - (PORT datad (906:906:906) (911:911:911)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1761:1761:1761) (1889:1889:1889)) - (PORT datab (811:811:811) (844:844:844)) - (PORT datac (1795:1795:1795) (1847:1847:1847)) - (PORT datad (1249:1249:1249) (1332:1332:1332)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) - (DELAY - (ABSOLUTE - (PORT dataa (1181:1181:1181) (1246:1246:1246)) - (PORT datac (1625:1625:1625) (1694:1694:1694)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1591:1591:1591) (1710:1710:1710)) - (PORT datab (1290:1290:1290) (1369:1369:1369)) - (PORT datac (1001:1001:1001) (1034:1034:1034)) - (PORT datad (903:903:903) (909:909:909)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (418:418:418)) - (PORT datab (220:220:220) (260:260:260)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1853:1853:1853) (1930:1930:1930)) - (PORT datab (866:866:866) (895:895:895)) - (PORT datac (904:904:904) (995:995:995)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (890:890:890)) - (PORT datab (241:241:241) (287:287:287)) - (PORT datad (828:828:828) (856:856:856)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1570:1570:1570) (1551:1551:1551)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1644:1644:1644) (1718:1718:1718)) - (PORT datab (252:252:252) (337:337:337)) - (PORT datac (1019:1019:1019) (1061:1061:1061)) - (PORT datad (1503:1503:1503) (1529:1529:1529)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1644:1644:1644) (1721:1721:1721)) - (PORT datab (250:250:250) (336:336:336)) - (PORT datac (1017:1017:1017) (1058:1058:1058)) - (PORT datad (1502:1502:1502) (1528:1528:1528)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (1695:1695:1695) (1803:1803:1803)) - (PORT datab (1079:1079:1079) (1108:1108:1108)) - (PORT datad (1636:1636:1636) (1692:1692:1692)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (964:964:964)) - (PORT datab (1117:1117:1117) (1155:1155:1155)) - (PORT datac (847:847:847) (882:882:882)) - (PORT datad (1230:1230:1230) (1240:1240:1240)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1642:1642:1642) (1701:1701:1701)) - (PORT datab (572:572:572) (595:595:595)) - (PORT datac (1349:1349:1349) (1418:1418:1418)) - (PORT datad (963:963:963) (1040:1040:1040)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1276:1276:1276)) - (PORT datab (2633:2633:2633) (2709:2709:2709)) - (PORT datac (840:840:840) (856:856:856)) - (PORT datad (1612:1612:1612) (1688:1688:1688)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1048:1048:1048)) - (PORT datab (1092:1092:1092) (1102:1102:1102)) - (PORT datac (1017:1017:1017) (1026:1026:1026)) - (PORT datad (1126:1126:1126) (1151:1151:1151)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1575:1575:1575) (1575:1575:1575)) - (PORT datab (854:854:854) (905:905:905)) - (PORT datac (1275:1275:1275) (1268:1268:1268)) - (PORT datad (1126:1126:1126) (1150:1150:1150)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (953:953:953)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1125:1125:1125) (1154:1154:1154)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1186:1186:1186)) - (PORT datab (723:723:723) (778:778:778)) - (PORT datac (868:868:868) (874:874:874)) - (PORT datad (662:662:662) (702:702:702)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (661:661:661)) - (PORT datab (653:653:653) (679:679:679)) - (PORT datac (1088:1088:1088) (1120:1120:1120)) - (PORT datad (844:844:844) (861:861:861)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1358:1358:1358) (1407:1407:1407)) - (PORT datab (1429:1429:1429) (1470:1470:1470)) - (PORT datac (648:648:648) (694:694:694)) - (PORT datad (805:805:805) (811:811:811)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (899:899:899) (906:906:906)) - (PORT datac (1500:1500:1500) (1532:1532:1532)) - (PORT datad (344:344:344) (366:366:366)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1115:1115:1115) (1131:1131:1131)) - (PORT datab (1311:1311:1311) (1377:1377:1377)) - (PORT datac (1523:1523:1523) (1593:1593:1593)) - (PORT datad (673:673:673) (713:713:713)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1923:1923:1923) (1946:1946:1946)) - (PORT datab (578:578:578) (602:602:602)) - (PORT datac (330:330:330) (364:364:364)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1632:1632:1632) (1712:1712:1712)) - (PORT datad (797:797:797) (835:835:835)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1533:1533:1533) (1618:1618:1618)) - (PORT datab (1105:1105:1105) (1138:1138:1138)) - (PORT datac (1063:1063:1063) (1096:1096:1096)) - (PORT datad (863:863:863) (873:873:873)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1124:1124:1124) (1153:1153:1153)) - (PORT datab (875:875:875) (901:901:901)) - (PORT datac (798:798:798) (808:808:808)) - (PORT datad (840:840:840) (859:859:859)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1692:1692:1692) (1758:1758:1758)) - (PORT datab (882:882:882) (899:899:899)) - (PORT datac (1083:1083:1083) (1113:1113:1113)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (857:857:857)) - (PORT datab (911:911:911) (941:941:941)) - (PORT datac (735:735:735) (740:740:740)) - (PORT datad (1793:1793:1793) (1802:1802:1802)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1153:1153:1153)) - (PORT datab (911:911:911) (945:945:945)) - (PORT datac (1609:1609:1609) (1652:1652:1652)) - (PORT datad (634:634:634) (660:660:660)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (371:371:371)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (661:661:661)) - (PORT datab (427:427:427) (465:465:465)) - (PORT datac (811:811:811) (833:833:833)) - (PORT datad (1434:1434:1434) (1466:1466:1466)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (675:675:675)) - (PORT datab (859:859:859) (872:872:872)) - (PORT datac (195:195:195) (229:229:229)) - (PORT datad (824:824:824) (851:851:851)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1356:1356:1356) (1399:1399:1399)) - (PORT datab (909:909:909) (971:971:971)) - (PORT datac (891:891:891) (932:932:932)) - (PORT datad (863:863:863) (904:904:904)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (800:800:800) (818:818:818)) - (PORT datad (813:813:813) (827:827:827)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (929:929:929)) - (PORT datab (1473:1473:1473) (1554:1554:1554)) - (PORT datac (1068:1068:1068) (1115:1115:1115)) - (PORT datad (1152:1152:1152) (1195:1195:1195)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1450:1450:1450)) - (PORT datab (1187:1187:1187) (1213:1213:1213)) - (PORT datac (1496:1496:1496) (1563:1563:1563)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (463:463:463)) - (PORT datab (1145:1145:1145) (1195:1195:1195)) - (PORT datac (567:567:567) (580:580:580)) - (PORT datad (205:205:205) (235:235:235)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~18) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (574:574:574)) - (PORT datab (975:975:975) (1007:1007:1007)) - (PORT datac (788:788:788) (802:802:802)) - (PORT datad (615:615:615) (629:629:629)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (885:885:885)) - (PORT datac (833:833:833) (859:859:859)) - (PORT datad (981:981:981) (1007:1007:1007)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1081:1081:1081) (1079:1079:1079)) - (PORT datab (1175:1175:1175) (1237:1237:1237)) - (PORT datac (1696:1696:1696) (1766:1766:1766)) - (PORT datad (811:811:811) (830:830:830)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1042:1042:1042)) - (PORT datab (226:226:226) (267:267:267)) - (PORT datac (1144:1144:1144) (1155:1155:1155)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1188:1188:1188)) - (PORT datab (1934:1934:1934) (1940:1940:1940)) - (PORT datac (1296:1296:1296) (1334:1334:1334)) - (PORT datad (578:578:578) (600:600:600)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (940:940:940)) - (PORT datab (1391:1391:1391) (1410:1410:1410)) - (PORT datac (1892:1892:1892) (1901:1901:1901)) - (PORT datad (809:809:809) (833:833:833)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1282:1282:1282)) - (PORT datab (1357:1357:1357) (1344:1344:1344)) - (PORT datac (2031:2031:2031) (2065:2065:2065)) - (PORT datad (914:914:914) (936:936:936)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1691:1691:1691) (1754:1754:1754)) - (PORT datab (1639:1639:1639) (1688:1688:1688)) - (PORT datac (636:636:636) (648:648:648)) - (PORT datad (841:841:841) (860:860:860)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (928:928:928)) - (PORT datab (891:891:891) (922:922:922)) - (PORT datac (818:818:818) (835:835:835)) - (PORT datad (542:542:542) (539:539:539)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (251:251:251)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (622:622:622) (670:670:670)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1665:1665:1665) (1784:1784:1784)) - (PORT datab (936:936:936) (967:967:967)) - (PORT datac (550:550:550) (567:567:567)) - (PORT datad (2426:2426:2426) (2479:2479:2479)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1589:1589:1589) (1589:1589:1589)) - (PORT datab (1063:1063:1063) (1059:1059:1059)) - (PORT datac (602:602:602) (631:631:631)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1605:1605:1605) (1657:1657:1657)) - (PORT datab (745:745:745) (827:827:827)) - (PORT datac (1317:1317:1317) (1366:1366:1366)) - (PORT datad (580:580:580) (601:601:601)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (379:379:379)) - (PORT datab (1669:1669:1669) (1764:1764:1764)) - (PORT datac (608:608:608) (631:631:631)) - (PORT datad (1423:1423:1423) (1472:1472:1472)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (206:206:206) (249:249:249)) - (PORT datac (1262:1262:1262) (1297:1297:1297)) - (PORT datad (601:601:601) (619:619:619)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (980:980:980)) - (PORT datab (1374:1374:1374) (1464:1464:1464)) - (PORT datac (1362:1362:1362) (1377:1377:1377)) - (PORT datad (873:873:873) (940:940:940)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1364:1364:1364) (1428:1428:1428)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (939:939:939) (1008:1008:1008)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1314:1314:1314)) - (PORT datab (1644:1644:1644) (1723:1723:1723)) - (PORT datac (2121:2121:2121) (2229:2229:2229)) - (PORT datad (631:631:631) (664:664:664)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (1004:1004:1004) (1018:1018:1018)) - (PORT datac (1032:1032:1032) (1044:1044:1044)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1329:1329:1329)) - (PORT datab (1542:1542:1542) (1632:1632:1632)) - (PORT datac (2120:2120:2120) (2229:2229:2229)) - (PORT datad (1608:1608:1608) (1685:1685:1685)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (883:883:883)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (631:631:631) (648:648:648)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT dataa (959:959:959) (1010:1010:1010)) - (PORT datab (965:965:965) (1026:1026:1026)) - (PORT datac (1321:1321:1321) (1338:1338:1338)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (383:383:383)) - (PORT datab (556:556:556) (574:574:574)) - (PORT datac (617:617:617) (672:672:672)) - (PORT datad (620:620:620) (667:667:667)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1050:1050:1050) (1080:1080:1080)) - (PORT datab (1085:1085:1085) (1123:1123:1123)) - (PORT datac (631:631:631) (666:666:666)) - (PORT datad (1244:1244:1244) (1240:1240:1240)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1173:1173:1173)) - (PORT datab (1077:1077:1077) (1091:1091:1091)) - (PORT datac (1059:1059:1059) (1072:1072:1072)) - (PORT datad (867:867:867) (900:900:900)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (2348:2348:2348) (2418:2418:2418)) - (PORT datab (894:894:894) (928:928:928)) - (PORT datac (1117:1117:1117) (1190:1190:1190)) - (PORT datad (1061:1061:1061) (1094:1094:1094)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1088:1088:1088) (1112:1112:1112)) - (PORT datab (1393:1393:1393) (1455:1455:1455)) - (PORT datac (1360:1360:1360) (1442:1442:1442)) - (PORT datad (838:838:838) (904:904:904)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1309:1309:1309) (1334:1334:1334)) - (PORT datab (1115:1115:1115) (1156:1156:1156)) - (PORT datac (975:975:975) (981:981:981)) - (PORT datad (545:545:545) (567:567:567)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (916:916:916)) - (PORT datab (857:857:857) (882:882:882)) - (PORT datac (497:497:497) (506:506:506)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (653:653:653) (687:687:687)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1186:1186:1186)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (1263:1263:1263) (1298:1298:1298)) - (PORT datad (1072:1072:1072) (1097:1097:1097)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT datac (320:320:320) (345:345:345)) - (PORT datad (601:601:601) (640:640:640)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1048:1048:1048) (1073:1073:1073)) - (PORT datab (932:932:932) (967:967:967)) - (PORT datac (635:635:635) (661:661:661)) - (PORT datad (1246:1246:1246) (1245:1245:1245)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (867:867:867)) - (PORT datab (825:825:825) (873:873:873)) - (PORT datac (1335:1335:1335) (1356:1356:1356)) - (PORT datad (903:903:903) (932:932:932)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (619:619:619)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (352:352:352) (378:378:378)) - (PORT datad (359:359:359) (377:377:377)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1777:1777:1777) (1833:1833:1833)) - (PORT datab (638:638:638) (655:655:655)) - (PORT datac (1085:1085:1085) (1095:1095:1095)) - (PORT datad (690:690:690) (747:747:747)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (971:971:971)) - (PORT datab (1640:1640:1640) (1693:1693:1693)) - (PORT datac (630:630:630) (665:665:665)) - (PORT datad (1349:1349:1349) (1404:1404:1404)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1782:1782:1782) (1839:1839:1839)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1237:1237:1237)) - (PORT datab (1385:1385:1385) (1468:1468:1468)) - (PORT datac (1313:1313:1313) (1371:1371:1371)) - (PORT datad (1597:1597:1597) (1690:1690:1690)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1431:1431:1431)) - (PORT datab (1251:1251:1251) (1304:1304:1304)) - (PORT datac (978:978:978) (1037:1037:1037)) - (PORT datad (205:205:205) (235:235:235)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (665:665:665)) - (PORT datab (849:849:849) (891:891:891)) - (PORT datac (2131:2131:2131) (2211:2211:2211)) - (PORT datad (883:883:883) (916:916:916)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1057:1057:1057) (1071:1071:1071)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (1301:1301:1301) (1374:1374:1374)) - (PORT datad (1080:1080:1080) (1109:1109:1109)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1341:1341:1341)) - (PORT datab (1411:1411:1411) (1480:1480:1480)) - (PORT datac (2485:2485:2485) (2523:2523:2523)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (1015:1015:1015)) - (PORT datab (1276:1276:1276) (1286:1286:1286)) - (PORT datac (1041:1041:1041) (1074:1074:1074)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1659:1659:1659) (1680:1680:1680)) - (PORT datab (1983:1983:1983) (1979:1979:1979)) - (PORT datac (814:814:814) (828:828:828)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (620:620:620)) - (PORT datab (1556:1556:1556) (1605:1605:1605)) - (PORT datac (663:663:663) (735:735:735)) - (PORT datad (1158:1158:1158) (1200:1200:1200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (892:892:892)) - (PORT datab (650:650:650) (673:673:673)) - (PORT datac (827:827:827) (865:865:865)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datab (1450:1450:1450) (1524:1524:1524)) - (PORT datac (859:859:859) (903:903:903)) - (PORT datad (805:805:805) (828:828:828)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1413:1413:1413) (1432:1432:1432)) - (PORT datac (972:972:972) (1032:1032:1032)) - (PORT datad (1223:1223:1223) (1265:1265:1265)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1398:1398:1398) (1483:1483:1483)) - (PORT datab (793:793:793) (810:810:810)) - (PORT datac (834:834:834) (841:841:841)) - (PORT datad (1046:1046:1046) (1116:1116:1116)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1206:1206:1206) (1224:1224:1224)) - (PORT datab (1090:1090:1090) (1116:1116:1116)) - (PORT datac (823:823:823) (852:852:852)) - (PORT datad (846:846:846) (900:900:900)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1423:1423:1423)) - (PORT datab (2162:2162:2162) (2264:2264:2264)) - (PORT datac (1308:1308:1308) (1352:1352:1352)) - (PORT datad (1606:1606:1606) (1598:1598:1598)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT dataa (2969:2969:2969) (3028:3028:3028)) - (PORT datab (1383:1383:1383) (1410:1410:1410)) - (PORT datac (867:867:867) (890:890:890)) - (PORT datad (1031:1031:1031) (1060:1060:1060)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (873:873:873)) - (PORT datab (856:856:856) (927:927:927)) - (PORT datac (861:861:861) (945:945:945)) - (PORT datad (1273:1273:1273) (1296:1296:1296)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT datac (647:647:647) (708:708:708)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (657:657:657)) - (PORT datab (656:656:656) (681:681:681)) - (PORT datad (563:563:563) (590:590:590)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) - (DELAY - (ABSOLUTE - (PORT dataa (2183:2183:2183) (2259:2259:2259)) - (PORT datab (1443:1443:1443) (1461:1461:1461)) - (PORT datac (1476:1476:1476) (1531:1531:1531)) - (PORT datad (2369:2369:2369) (2448:2448:2448)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (888:888:888) (940:940:940)) - (PORT datac (180:180:180) (218:218:218)) - (PORT datad (1342:1342:1342) (1383:1383:1383)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (979:979:979)) - (PORT datab (1307:1307:1307) (1335:1335:1335)) - (PORT datac (1569:1569:1569) (1598:1598:1598)) - (PORT datad (1351:1351:1351) (1402:1402:1402)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1588:1588:1588) (1590:1590:1590)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (1447:1447:1447) (1548:1548:1548)) - (PORT datad (1128:1128:1128) (1202:1202:1202)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1194:1194:1194) (1317:1317:1317)) - (PORT datab (854:854:854) (878:878:878)) - (PORT datac (1359:1359:1359) (1448:1448:1448)) - (PORT datad (1273:1273:1273) (1293:1293:1293)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1455:1455:1455)) - (PORT datab (854:854:854) (894:894:894)) - (PORT datac (1306:1306:1306) (1349:1349:1349)) - (PORT datad (1522:1522:1522) (1658:1658:1658)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (959:959:959)) - (PORT datab (1138:1138:1138) (1207:1207:1207)) - (PORT datac (1131:1131:1131) (1224:1224:1224)) - (PORT datad (1323:1323:1323) (1402:1402:1402)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (255:255:255)) - (PORT datab (256:256:256) (308:308:308)) - (PORT datad (1120:1120:1120) (1146:1146:1146)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1059:1059:1059) (1092:1092:1092)) - (PORT datab (219:219:219) (256:256:256)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (650:650:650) (701:701:701)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (667:667:667)) - (PORT datab (901:901:901) (931:931:931)) - (PORT datac (540:540:540) (563:563:563)) - (PORT datad (857:857:857) (878:878:878)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1217:1217:1217) (1309:1309:1309)) - (PORT datab (896:896:896) (910:910:910)) - (PORT datad (323:323:323) (343:343:343)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) - (DELAY - (ABSOLUTE - (PORT datac (637:637:637) (698:698:698)) - (PORT datad (1041:1041:1041) (1047:1047:1047)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1152:1152:1152)) - (PORT datab (882:882:882) (936:936:936)) - (PORT datac (867:867:867) (916:916:916)) - (PORT datad (1167:1167:1167) (1192:1192:1192)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (1343:1343:1343) (1415:1415:1415)) - (PORT datab (863:863:863) (907:907:907)) - (PORT datac (1234:1234:1234) (1274:1274:1274)) - (PORT datad (1190:1190:1190) (1218:1218:1218)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (267:267:267)) - (PORT datab (1193:1193:1193) (1234:1234:1234)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (1617:1617:1617) (1667:1667:1667)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (648:648:648)) - (PORT datab (1169:1169:1169) (1211:1211:1211)) - (PORT datac (1162:1162:1162) (1233:1233:1233)) - (PORT datad (1039:1039:1039) (1067:1067:1067)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1394:1394:1394) (1460:1460:1460)) - (PORT datab (847:847:847) (897:897:897)) - (PORT datac (1269:1269:1269) (1283:1283:1283)) - (PORT datad (1192:1192:1192) (1220:1220:1220)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (951:951:951)) - (PORT datab (1328:1328:1328) (1352:1352:1352)) - (PORT datac (1165:1165:1165) (1242:1242:1242)) - (PORT datad (1298:1298:1298) (1384:1384:1384)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1456:1456:1456) (1555:1555:1555)) - (PORT datab (854:854:854) (904:904:904)) - (PORT datac (1388:1388:1388) (1439:1439:1439)) - (PORT datad (1058:1058:1058) (1093:1093:1093)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2187:2187:2187) (2263:2263:2263)) - (PORT datab (1443:1443:1443) (1466:1466:1466)) - (PORT datac (1474:1474:1474) (1528:1528:1528)) - (PORT datad (2372:2372:2372) (2450:2450:2450)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1657:1657:1657) (1774:1774:1774)) - (PORT datab (1786:1786:1786) (1846:1846:1846)) - (PORT datac (872:872:872) (889:889:889)) - (PORT datad (1122:1122:1122) (1155:1155:1155)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (220:220:220) (260:260:260)) - (PORT datac (605:605:605) (646:646:646)) - (PORT datad (201:201:201) (230:230:230)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (910:910:910)) - (PORT datab (1115:1115:1115) (1173:1173:1173)) - (PORT datac (633:633:633) (660:660:660)) - (PORT datad (609:609:609) (623:623:623)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1502:1502:1502) (1555:1555:1555)) - (PORT datab (1499:1499:1499) (1599:1599:1599)) - (PORT datac (2151:2151:2151) (2229:2229:2229)) - (PORT datad (2376:2376:2376) (2457:2457:2457)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1413:1413:1413)) - (PORT datab (1207:1207:1207) (1324:1324:1324)) - (PORT datac (1498:1498:1498) (1562:1562:1562)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (663:663:663)) - (PORT datab (881:881:881) (892:892:892)) - (PORT datac (1280:1280:1280) (1329:1329:1329)) - (PORT datad (1078:1078:1078) (1109:1109:1109)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1081:1081:1081)) - (PORT datab (1330:1330:1330) (1350:1350:1350)) - (PORT datac (582:582:582) (602:602:602)) - (PORT datad (537:537:537) (553:553:553)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1848:1848:1848) (1880:1880:1880)) - (PORT datab (2180:2180:2180) (2304:2304:2304)) - (PORT datac (1640:1640:1640) (1697:1697:1697)) - (PORT datad (863:863:863) (896:896:896)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (868:868:868) (867:867:867)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (598:598:598)) - (PORT datab (802:802:802) (820:820:820)) - (PORT datac (1301:1301:1301) (1375:1375:1375)) - (PORT datad (1078:1078:1078) (1110:1110:1110)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1503:1503:1503) (1526:1526:1526)) - (PORT datab (1125:1125:1125) (1234:1234:1234)) - (PORT datac (1152:1152:1152) (1259:1259:1259)) - (PORT datad (1668:1668:1668) (1700:1700:1700)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1196:1196:1196)) - (PORT datab (1078:1078:1078) (1085:1085:1085)) - (PORT datac (1139:1139:1139) (1248:1248:1248)) - (PORT datad (1075:1075:1075) (1078:1078:1078)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1587:1587:1587) (1586:1586:1586)) - (PORT datab (1357:1357:1357) (1457:1457:1457)) - (PORT datac (605:605:605) (629:629:629)) - (PORT datad (1350:1350:1350) (1406:1406:1406)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (965:965:965)) - (PORT datac (870:870:870) (904:904:904)) - (PORT datad (637:637:637) (685:685:685)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) - (DELAY - (ABSOLUTE - (PORT datab (1532:1532:1532) (1595:1595:1595)) - (PORT datac (1385:1385:1385) (1482:1482:1482)) - (PORT datad (1361:1361:1361) (1408:1408:1408)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1492:1492:1492)) - (PORT datab (2176:2176:2176) (2297:2297:2297)) - (PORT datac (1644:1644:1644) (1702:1702:1702)) - (PORT datad (189:189:189) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1346:1346:1346)) - (PORT datab (1414:1414:1414) (1480:1480:1480)) - (PORT datac (1381:1381:1381) (1465:1465:1465)) - (PORT datad (212:212:212) (245:245:245)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1469:1469:1469)) - (PORT datab (561:561:561) (576:576:576)) - (PORT datac (1184:1184:1184) (1295:1295:1295)) - (PORT datad (192:192:192) (226:226:226)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1213:1213:1213)) - (PORT datab (1152:1152:1152) (1227:1227:1227)) - (PORT datac (603:603:603) (634:634:634)) - (PORT datad (1386:1386:1386) (1420:1420:1420)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1233:1233:1233) (1322:1322:1322)) - (PORT datab (657:657:657) (691:691:691)) - (PORT datac (1116:1116:1116) (1184:1184:1184)) - (PORT datad (1102:1102:1102) (1139:1139:1139)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (532:532:532) (560:560:560)) - (PORT datab (854:854:854) (891:891:891)) - (PORT datac (574:574:574) (600:600:600)) - (PORT datad (884:884:884) (916:916:916)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (608:608:608)) - (PORT datab (616:616:616) (633:633:633)) - (PORT datac (546:546:546) (567:567:567)) - (PORT datad (554:554:554) (552:552:552)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (627:627:627)) - (PORT datab (671:671:671) (711:711:711)) - (PORT datac (886:886:886) (936:936:936)) - (PORT datad (193:193:193) (219:219:219)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (604:604:604)) - (PORT datab (626:626:626) (647:647:647)) - (PORT datac (331:331:331) (347:347:347)) - (PORT datad (1269:1269:1269) (1265:1265:1265)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (265:265:265)) - (PORT datab (866:866:866) (921:921:921)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (2801:2801:2801) (2867:2867:2867)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (573:573:573)) - (PORT datab (552:552:552) (571:571:571)) - (PORT datac (627:627:627) (646:646:646)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1249:1249:1249)) - (PORT datab (1099:1099:1099) (1160:1160:1160)) - (PORT datac (1066:1066:1066) (1128:1128:1128)) - (PORT datad (1043:1043:1043) (1088:1088:1088)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (864:864:864)) - (PORT datab (1474:1474:1474) (1492:1492:1492)) - (PORT datac (169:169:169) (201:201:201)) - (PORT datad (1333:1333:1333) (1332:1332:1332)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1133:1133:1133) (1156:1156:1156)) - (PORT datab (943:943:943) (976:976:976)) - (PORT datac (2031:2031:2031) (2065:2065:2065)) - (PORT datad (1174:1174:1174) (1236:1236:1236)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (772:772:772) (799:799:799)) - (PORT datab (238:238:238) (284:284:284)) - (PORT datad (276:276:276) (361:361:361)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1570:1570:1570) (1551:1551:1551)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (253:253:253)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (650:650:650) (701:701:701)) - (PORT datad (613:613:613) (639:639:639)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1544:1544:1544) (1572:1572:1572)) - (PORT datab (2184:2184:2184) (2256:2256:2256)) - (PORT datac (1616:1616:1616) (1684:1684:1684)) - (PORT datad (1753:1753:1753) (1842:1842:1842)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (470:470:470)) - (PORT datab (301:301:301) (397:397:397)) - (PORT datac (827:827:827) (872:872:872)) - (PORT datad (194:194:194) (230:230:230)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (1774:1774:1774) (1891:1891:1891)) - (PORT datac (1054:1054:1054) (1086:1086:1086)) - (PORT datad (1611:1611:1611) (1671:1671:1671)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (467:467:467)) - (PORT datab (300:300:300) (392:392:392)) - (PORT datac (830:830:830) (875:875:875)) - (PORT datad (194:194:194) (228:228:228)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1371:1371:1371)) - (PORT datac (1354:1354:1354) (1406:1406:1406)) - (PORT datad (1567:1567:1567) (1612:1612:1612)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1487:1487:1487) (1528:1528:1528)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (1088:1088:1088) (1107:1107:1107)) - (PORT datac (1737:1737:1737) (1857:1857:1857)) - (PORT datad (1611:1611:1611) (1671:1671:1671)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (774:774:774) (801:801:801)) - (PORT datab (240:240:240) (286:286:286)) - (PORT datad (277:277:277) (361:361:361)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1570:1570:1570) (1551:1551:1551)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (249:249:249) (338:338:338)) - (PORT datab (301:301:301) (396:396:396)) - (PORT datac (827:827:827) (870:870:870)) - (PORT datad (192:192:192) (226:226:226)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (1341:1341:1341) (1381:1381:1381)) - (PORT datac (1343:1343:1343) (1408:1408:1408)) - (PORT datad (1864:1864:1864) (1915:1915:1915)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1490:1490:1490) (1532:1532:1532)) - (PORT ena (1011:1011:1011) (1021:1021:1021)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (1344:1344:1344) (1389:1389:1389)) - (PORT datac (1354:1354:1354) (1405:1405:1405)) - (PORT datad (1567:1567:1567) (1612:1612:1612)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (688:688:688) (758:758:758)) - (PORT datad (231:231:231) (265:265:265)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) - (DELAY - (ABSOLUTE - (PORT datab (1770:1770:1770) (1887:1887:1887)) - (PORT datac (1056:1056:1056) (1087:1087:1087)) - (PORT datad (1611:1611:1611) (1672:1672:1672)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1232:1232:1232) (1238:1238:1238)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (250:250:250) (339:339:339)) - (PORT datab (302:302:302) (395:395:395)) - (PORT datac (827:827:827) (871:871:871)) - (PORT datad (193:193:193) (227:227:227)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT dataa (1094:1094:1094) (1112:1112:1112)) - (PORT datab (1656:1656:1656) (1746:1746:1746)) - (PORT datad (1643:1643:1643) (1702:1702:1702)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1228:1228:1228) (1234:1234:1234)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[7\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1098:1098:1098) (1117:1117:1117)) - (PORT datab (1660:1660:1660) (1751:1751:1751)) - (PORT datad (1641:1641:1641) (1701:1701:1701)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (470:470:470)) - (PORT datab (632:632:632) (690:690:690)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT datab (1384:1384:1384) (1453:1453:1453)) - (PORT datac (1177:1177:1177) (1238:1238:1238)) - (PORT datad (1861:1861:1861) (1918:1918:1918)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1249:1249:1249) (1247:1247:1247)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) - (DELAY - (ABSOLUTE - (PORT datac (1626:1626:1626) (1699:1699:1699)) - (PORT datad (1140:1140:1140) (1199:1199:1199)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1074:1074:1074)) - (PORT datab (1288:1288:1288) (1364:1364:1364)) - (PORT datac (1553:1553:1553) (1671:1671:1671)) - (PORT datad (197:197:197) (233:233:233)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (945:945:945) (961:961:961)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1074:1074:1074)) - (PORT datab (1290:1290:1290) (1364:1364:1364)) - (PORT datac (1553:1553:1553) (1671:1671:1671)) - (PORT datad (197:197:197) (233:233:233)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (954:954:954) (969:969:969)) - (PORT ena (1525:1525:1525) (1527:1527:1527)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (484:484:484)) - (PORT datab (425:425:425) (467:467:467)) - (PORT datad (626:626:626) (681:681:681)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1313:1313:1313) (1336:1336:1336)) - (PORT datab (1115:1115:1115) (1155:1155:1155)) - (PORT datac (846:846:846) (877:877:877)) - (PORT datad (549:549:549) (569:569:569)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (688:688:688) (722:722:722)) - (PORT datac (852:852:852) (924:924:924)) - (PORT datad (1090:1090:1090) (1119:1119:1119)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (731:731:731) (756:756:756)) - (PORT datab (605:605:605) (623:623:623)) - (PORT datac (1037:1037:1037) (1053:1053:1053)) - (PORT datad (615:615:615) (648:648:648)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1418:1418:1418)) - (PORT datab (1268:1268:1268) (1393:1393:1393)) - (PORT datac (1035:1035:1035) (1081:1081:1081)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (865:865:865)) - (PORT datab (604:604:604) (609:609:609)) - (PORT datac (361:361:361) (389:389:389)) - (PORT datad (562:562:562) (567:567:567)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (348:348:348) (370:370:370)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (374:374:374) (398:398:398)) - (PORT datac (200:200:200) (238:238:238)) - (PORT datad (1037:1037:1037) (1034:1034:1034)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (1695:1695:1695) (1808:1808:1808)) - (PORT datab (1079:1079:1079) (1111:1111:1111)) - (PORT datad (1637:1637:1637) (1694:1694:1694)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (954:954:954) (969:969:969)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1336:1336:1336) (1360:1360:1360)) - (PORT datab (1023:1023:1023) (1079:1079:1079)) - (PORT datad (387:387:387) (413:413:413)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) - (DELAY - (ABSOLUTE - (PORT dataa (1184:1184:1184) (1249:1249:1249)) - (PORT datac (1622:1622:1622) (1693:1693:1693)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1486:1486:1486) (1505:1505:1505)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1194:1194:1194) (1268:1268:1268)) - (PORT datab (218:218:218) (265:265:265)) - (PORT datac (1797:1797:1797) (1847:1847:1847)) - (PORT datad (778:778:778) (803:803:803)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1488:1488:1488) (1508:1508:1508)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1265:1265:1265)) - (PORT datab (809:809:809) (840:840:840)) - (PORT datac (1798:1798:1798) (1847:1847:1847)) - (PORT datad (901:901:901) (906:906:906)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (425:425:425) (488:488:488)) - (PORT datab (661:661:661) (684:684:684)) - (PORT datad (626:626:626) (645:645:645)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1241:1241:1241)) - (PORT datab (656:656:656) (708:708:708)) - (PORT datac (529:529:529) (548:548:548)) - (PORT datad (1121:1121:1121) (1153:1153:1153)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (885:885:885)) - (PORT datab (234:234:234) (275:275:275)) - (PORT datac (1127:1127:1127) (1169:1169:1169)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (895:895:895)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (620:620:620) (642:642:642)) - (PORT datad (1430:1430:1430) (1460:1460:1460)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (945:945:945) (977:977:977)) - (PORT datac (2012:2012:2012) (2094:2094:2094)) - (PORT datad (2028:2028:2028) (2075:2075:2075)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (908:908:908)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1079:1079:1079) (1127:1127:1127)) - (PORT datad (1095:1095:1095) (1160:1160:1160)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (411:411:411)) - (PORT datab (1153:1153:1153) (1193:1193:1193)) - (PORT datac (857:857:857) (889:889:889)) - (PORT datad (588:588:588) (637:637:637)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (396:396:396)) - (PORT datab (702:702:702) (729:729:729)) - (PORT datac (1594:1594:1594) (1637:1637:1637)) - (PORT datad (1586:1586:1586) (1641:1641:1641)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1079:1079:1079)) - (PORT datab (387:387:387) (417:417:417)) - (PORT datac (1143:1143:1143) (1154:1154:1154)) - (PORT datad (913:913:913) (945:945:945)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (875:875:875)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1359:1359:1359) (1374:1374:1374)) - (PORT datad (625:625:625) (673:673:673)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1137:1137:1137)) - (PORT datab (909:909:909) (928:928:928)) - (PORT datac (1315:1315:1315) (1300:1300:1300)) - (PORT datad (1235:1235:1235) (1240:1240:1240)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (894:894:894)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (637:637:637) (696:696:696)) - (PORT datad (856:856:856) (880:880:880)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (429:429:429)) - (PORT datab (817:817:817) (843:843:843)) - (PORT datac (348:348:348) (374:374:374)) - (PORT datad (816:816:816) (859:859:859)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1106:1106:1106)) - (PORT datab (968:968:968) (997:997:997)) - (PORT datad (1014:1014:1014) (1024:1024:1024)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (960:960:960) (979:979:979)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1010:1010:1010) (1032:1032:1032)) - (PORT datab (1291:1291:1291) (1372:1372:1372)) - (PORT datac (1001:1001:1001) (1035:1035:1035)) - (PORT datad (195:195:195) (231:231:231)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (960:960:960) (981:981:981)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (516:516:516)) - (PORT datab (242:242:242) (325:325:325)) - (PORT datad (666:666:666) (698:698:698)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (654:654:654)) - (PORT datab (376:376:376) (399:399:399)) - (PORT datac (339:339:339) (359:359:359)) - (PORT datad (619:619:619) (642:642:642)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_32) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1223:1223:1223)) - (PORT datac (1665:1665:1665) (1766:1766:1766)) - (PORT datad (1640:1640:1640) (1695:1695:1695)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (641:641:641)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (650:650:650)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (329:329:329) (364:364:364)) - (PORT datad (1296:1296:1296) (1415:1415:1415)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (875:875:875)) - (PORT datab (598:598:598) (631:631:631)) - (PORT datac (997:997:997) (1030:1030:1030)) - (PORT datad (1344:1344:1344) (1385:1385:1385)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1362:1362:1362) (1374:1374:1374)) - (PORT datab (257:257:257) (303:303:303)) - (PORT datac (883:883:883) (959:959:959)) - (PORT datad (791:791:791) (806:806:806)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (730:730:730)) - (PORT datab (897:897:897) (950:950:950)) - (PORT datac (580:580:580) (599:599:599)) - (PORT datad (1264:1264:1264) (1277:1277:1277)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1878:1878:1878) (1960:1960:1960)) - (PORT datab (219:219:219) (266:266:266)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (905:905:905)) - (PORT datab (841:841:841) (861:861:861)) - (PORT datac (543:543:543) (568:568:568)) - (PORT datad (823:823:823) (840:840:840)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1312:1312:1312) (1357:1357:1357)) - (PORT datab (722:722:722) (780:780:780)) - (PORT datac (1286:1286:1286) (1296:1296:1296)) - (PORT datad (837:837:837) (845:845:845)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT datab (1246:1246:1246) (1261:1261:1261)) - (PORT datad (833:833:833) (906:906:906)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1286:1286:1286)) - (PORT datab (1754:1754:1754) (1769:1769:1769)) - (PORT datac (837:837:837) (859:859:859)) - (PORT datad (1358:1358:1358) (1431:1431:1431)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1307:1307:1307) (1308:1308:1308)) - (PORT datab (904:904:904) (943:943:943)) - (PORT datac (1266:1266:1266) (1288:1288:1288)) - (PORT datad (1126:1126:1126) (1153:1153:1153)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1408:1408:1408) (1524:1524:1524)) - (PORT datab (680:680:680) (705:705:705)) - (PORT datac (1127:1127:1127) (1149:1149:1149)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1049:1049:1049)) - (PORT datab (650:650:650) (695:695:695)) - (PORT datac (845:845:845) (889:889:889)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1056:1056:1056) (1086:1086:1086)) - (PORT datab (717:717:717) (791:791:791)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1390:1390:1390) (1447:1447:1447)) - (PORT datab (655:655:655) (695:695:695)) - (PORT datac (619:619:619) (645:645:645)) - (PORT datad (1356:1356:1356) (1363:1363:1363)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (962:962:962)) - (PORT datab (371:371:371) (405:405:405)) - (PORT datac (871:871:871) (905:905:905)) - (PORT datad (638:638:638) (686:686:686)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1388:1388:1388) (1444:1444:1444)) - (PORT datab (1084:1084:1084) (1097:1097:1097)) - (PORT datac (1272:1272:1272) (1281:1281:1281)) - (PORT datad (1289:1289:1289) (1294:1294:1294)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (598:598:598) (633:633:633)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (415:415:415)) - (PORT datab (839:839:839) (862:862:862)) - (PORT datac (1562:1562:1562) (1555:1555:1555)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (677:677:677)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (613:613:613) (627:627:627)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1081:1081:1081) (1077:1077:1077)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (806:806:806) (805:805:805)) - (PORT datad (1609:1609:1609) (1578:1578:1578)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1314:1314:1314) (1360:1360:1360)) - (PORT datab (1187:1187:1187) (1205:1205:1205)) - (PORT datac (853:853:853) (859:859:859)) - (PORT datad (1083:1083:1083) (1098:1098:1098)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1148:1148:1148) (1204:1204:1204)) - (PORT datab (1090:1090:1090) (1150:1150:1150)) - (PORT datac (543:543:543) (565:565:565)) - (PORT datad (1569:1569:1569) (1616:1616:1616)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (965:965:965)) - (PORT datab (864:864:864) (896:896:896)) - (PORT datac (841:841:841) (877:877:877)) - (PORT datad (1188:1188:1188) (1242:1242:1242)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1354:1354:1354) (1373:1373:1373)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (584:584:584) (630:630:630)) - (PORT datad (616:616:616) (650:650:650)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) - (DELAY - (ABSOLUTE - (PORT datab (1114:1114:1114) (1151:1151:1151)) - (PORT datac (1301:1301:1301) (1377:1377:1377)) - (PORT datad (190:190:190) (223:223:223)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1353:1353:1353)) - (PORT datab (551:551:551) (570:570:570)) - (PORT datac (810:810:810) (824:824:824)) - (PORT datad (849:849:849) (850:850:850)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (953:953:953)) - (PORT datab (699:699:699) (719:719:719)) - (PORT datac (1041:1041:1041) (1078:1078:1078)) - (PORT datad (810:810:810) (816:816:816)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (728:728:728)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (2137:2137:2137) (2231:2231:2231)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (564:564:564) (579:579:579)) - (PORT datac (179:179:179) (218:218:218)) - (PORT datad (624:624:624) (668:668:668)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (409:409:409)) - (PORT datab (228:228:228) (268:268:268)) - (PORT datac (891:891:891) (924:924:924)) - (PORT datad (778:778:778) (782:782:782)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1327:1327:1327) (1395:1395:1395)) - (PORT datab (606:606:606) (624:624:624)) - (PORT datac (1604:1604:1604) (1594:1594:1594)) - (PORT datad (1332:1332:1332) (1391:1391:1391)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1332:1332:1332) (1395:1395:1395)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1220:1220:1220) (1288:1288:1288)) - (PORT datad (1332:1332:1332) (1391:1391:1391)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1505:1505:1505) (1528:1528:1528)) - (PORT datab (606:606:606) (623:623:623)) - (PORT datac (1605:1605:1605) (1594:1594:1594)) - (PORT datad (1666:1666:1666) (1703:1703:1703)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1507:1507:1507) (1528:1528:1528)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (1219:1219:1219) (1289:1289:1289)) - (PORT datad (1667:1667:1667) (1699:1699:1699)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT datab (1782:1782:1782) (1840:1840:1840)) - (PORT datac (1623:1623:1623) (1732:1732:1732)) - (PORT datad (1367:1367:1367) (1421:1421:1421)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1179:1179:1179)) - (PORT datab (683:683:683) (734:734:734)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (824:824:824) (862:862:862)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (696:696:696)) - (PORT datab (1115:1115:1115) (1173:1173:1173)) - (PORT datac (1249:1249:1249) (1271:1271:1271)) - (PORT datad (864:864:864) (897:897:897)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla83M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (954:954:954) (1048:1048:1048)) - (PORT datab (1410:1410:1410) (1485:1485:1485)) - (PORT datac (1262:1262:1262) (1303:1303:1303)) - (PORT datad (211:211:211) (243:243:243)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1903:1903:1903) (1982:1982:1982)) - (PORT datab (1495:1495:1495) (1600:1600:1600)) - (PORT datac (1370:1370:1370) (1425:1425:1425)) - (PORT datad (562:562:562) (590:590:590)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (936:936:936)) - (PORT datab (1395:1395:1395) (1443:1443:1443)) - (PORT datac (1396:1396:1396) (1464:1464:1464)) - (PORT datad (1184:1184:1184) (1234:1234:1234)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (873:873:873)) - (PORT datab (654:654:654) (689:689:689)) - (PORT datac (581:581:581) (627:627:627)) - (PORT datad (1036:1036:1036) (1049:1049:1049)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (913:913:913)) - (PORT datab (853:853:853) (885:885:885)) - (PORT datac (734:734:734) (757:757:757)) - (PORT datad (1072:1072:1072) (1090:1090:1090)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (977:977:977)) - (PORT datab (1312:1312:1312) (1339:1339:1339)) - (PORT datac (1751:1751:1751) (1781:1781:1781)) - (PORT datad (1355:1355:1355) (1406:1406:1406)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (1598:1598:1598) (1626:1626:1626)) - (PORT datac (733:733:733) (754:754:754)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (956:956:956)) - (PORT datab (1162:1162:1162) (1211:1211:1211)) - (PORT datac (817:817:817) (831:831:831)) - (PORT datad (1633:1633:1633) (1709:1709:1709)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1592:1592:1592) (1592:1592:1592)) - (PORT datab (1069:1069:1069) (1109:1109:1109)) - (PORT datac (604:604:604) (630:630:630)) - (PORT datad (1608:1608:1608) (1656:1656:1656)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (827:827:827) (838:838:838)) - (PORT datad (1607:1607:1607) (1659:1659:1659)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (923:923:923)) - (PORT datac (807:807:807) (833:833:833)) - (PORT datad (1031:1031:1031) (1073:1073:1073)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (944:944:944)) - (PORT datab (1092:1092:1092) (1109:1109:1109)) - (PORT datac (830:830:830) (831:831:831)) - (PORT datad (645:645:645) (690:690:690)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (206:206:206) (249:249:249)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2184:2184:2184) (2261:2261:2261)) - (PORT datab (1444:1444:1444) (1463:1463:1463)) - (PORT datac (1477:1477:1477) (1532:1532:1532)) - (PORT datad (2371:2371:2371) (2448:2448:2448)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (923:923:923)) - (PORT datab (649:649:649) (702:702:702)) - (PORT datac (1639:1639:1639) (1635:1635:1635)) - (PORT datad (1038:1038:1038) (1046:1046:1046)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1177:1177:1177)) - (PORT datac (1096:1096:1096) (1133:1133:1133)) - (PORT datad (879:879:879) (942:942:942)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1173:1173:1173)) - (PORT datad (880:880:880) (947:947:947)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1249:1249:1249) (1247:1247:1247)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1494:1494:1494) (1511:1511:1511)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1114:1114:1114)) - (PORT datab (1658:1658:1658) (1748:1748:1748)) - (PORT datad (1642:1642:1642) (1705:1705:1705)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1494:1494:1494) (1509:1509:1509)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (986:986:986) (1015:1015:1015)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (985:985:985) (1016:1016:1016)) - (PORT ena (1011:1011:1011) (1021:1021:1021)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (463:463:463)) - (PORT datab (690:690:690) (762:762:762)) - (PORT datad (231:231:231) (270:270:270)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (476:476:476)) - (PORT datab (334:334:334) (367:367:367)) - (PORT datad (605:605:605) (653:653:653)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1467:1467:1467) (1485:1485:1485)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1470:1470:1470) (1487:1487:1487)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (703:703:703)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (631:631:631) (649:649:649)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1172:1172:1172) (1191:1191:1191)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1170:1170:1170) (1191:1191:1191)) - (PORT ena (979:979:979) (971:971:971)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (478:478:478)) - (PORT datab (426:426:426) (468:468:468)) - (PORT datad (217:217:217) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (937:937:937) (963:963:963)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (936:936:936) (963:963:963)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (478:478:478) (511:511:511)) - (PORT datab (696:696:696) (733:733:733)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1472:1472:1472) (1486:1486:1486)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1364:1364:1364)) - (PORT datab (923:923:923) (944:944:944)) - (PORT datad (388:388:388) (413:413:413)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (369:369:369)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (609:609:609) (630:630:630)) - (PORT datad (598:598:598) (610:610:610)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (639:639:639) (662:662:662)) - (PORT datac (860:860:860) (871:871:871)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (907:907:907)) - (PORT datab (636:636:636) (661:661:661)) - (PORT datac (1864:1864:1864) (1958:1958:1958)) - (PORT datad (562:562:562) (575:575:575)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT datac (1315:1315:1315) (1300:1300:1300)) - (PORT datad (1081:1081:1081) (1091:1091:1091)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (898:898:898)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (876:876:876) (893:893:893)) - (PORT datad (322:322:322) (341:341:341)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) - (DELAY - (ABSOLUTE - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (1161:1161:1161) (1184:1184:1184)) - (PORT datad (812:812:812) (832:832:832)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (782:782:782)) - (PORT datab (844:844:844) (888:888:888)) - (PORT datac (822:822:822) (833:833:833)) - (PORT datad (616:616:616) (626:626:626)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (886:886:886)) - (PORT datab (785:785:785) (787:787:787)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (871:871:871) (921:921:921)) - (PORT datab (977:977:977) (1058:1058:1058)) - (PORT datac (1313:1313:1313) (1404:1404:1404)) - (PORT datad (550:550:550) (572:572:572)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (903:903:903)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (647:647:647) (670:670:670)) - (PORT datad (1082:1082:1082) (1119:1119:1119)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (866:866:866) (880:880:880)) - (PORT datac (2155:2155:2155) (2103:2103:2103)) - (PORT datad (1102:1102:1102) (1105:1105:1105)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) - (DELAY - (ABSOLUTE - (PORT datab (1215:1215:1215) (1288:1288:1288)) - (PORT datac (1012:1012:1012) (1021:1021:1021)) - (PORT datad (1676:1676:1676) (1698:1698:1698)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1183:1183:1183) (1291:1291:1291)) - (PORT datac (1379:1379:1379) (1462:1462:1462)) - (PORT datad (1949:1949:1949) (2061:2061:2061)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (274:274:274)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (861:861:861) (884:884:884)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) - (DELAY - (ABSOLUTE - (PORT datab (1057:1057:1057) (1075:1075:1075)) - (PORT datac (1012:1012:1012) (1024:1024:1024)) - (PORT datad (1178:1178:1178) (1252:1252:1252)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (813:813:813) (834:834:834)) - (PORT datab (536:536:536) (556:556:556)) - (PORT datac (647:647:647) (699:699:699)) - (PORT datad (1920:1920:1920) (2003:2003:2003)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (816:816:816) (843:843:843)) - (PORT datad (815:815:815) (860:860:860)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1243:1243:1243) (1347:1347:1347)) - (PORT datab (742:742:742) (820:820:820)) - (PORT datac (1318:1318:1318) (1367:1367:1367)) - (PORT datad (819:819:819) (850:850:850)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1271:1271:1271) (1341:1341:1341)) - (PORT datab (641:641:641) (696:696:696)) - (PORT datac (642:642:642) (694:694:694)) - (PORT datad (851:851:851) (894:894:894)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1716:1716:1716) (1784:1784:1784)) - (PORT datab (648:648:648) (675:675:675)) - (PORT datac (557:557:557) (579:579:579)) - (PORT datad (1053:1053:1053) (1059:1059:1059)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1642:1642:1642) (1687:1687:1687)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (861:861:861) (928:928:928)) - (PORT datad (1010:1010:1010) (1030:1030:1030)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT datab (857:857:857) (877:877:877)) - (PORT datac (352:352:352) (376:376:376)) - (PORT datad (316:316:316) (332:332:332)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (800:800:800) (834:834:834)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (625:625:625) (650:650:650)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1192:1192:1192)) - (PORT datab (1229:1229:1229) (1292:1292:1292)) - (PORT datac (1224:1224:1224) (1248:1248:1248)) - (PORT datad (1247:1247:1247) (1246:1246:1246)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT datab (1055:1055:1055) (1075:1075:1075)) - (PORT datac (1012:1012:1012) (1023:1023:1023)) - (PORT datad (1178:1178:1178) (1253:1253:1253)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (886:886:886) (892:892:892)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (260:260:260) (330:330:330)) - (PORT datab (937:937:937) (1002:1002:1002)) - (PORT datad (624:624:624) (648:648:648)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) - (DELAY - (ABSOLUTE - (PORT datab (1214:1214:1214) (1293:1293:1293)) - (PORT datac (1012:1012:1012) (1023:1023:1023)) - (PORT datad (1676:1676:1676) (1697:1697:1697)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (455:455:455) (484:484:484)) - (PORT datac (313:313:313) (331:331:331)) - (PORT datad (215:215:215) (284:284:284)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[11\]) - (DELAY - (ABSOLUTE - (PORT datac (1521:1521:1521) (1611:1611:1611)) - (PORT datad (628:628:628) (664:664:664)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (947:947:947)) - (PORT datab (886:886:886) (917:917:917)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (634:634:634) (652:652:652)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (884:884:884) (917:917:917)) - (PORT datac (1650:1650:1650) (1651:1651:1651)) - (PORT datad (1575:1575:1575) (1615:1615:1615)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT datac (657:657:657) (695:695:695)) + (PORT datad (609:609:609) (638:638:638)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12741,11 +11472,11 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) (DELAY (ABSOLUTE - (PORT dataa (1229:1229:1229) (1316:1316:1316)) - (PORT datab (1647:1647:1647) (1728:1728:1728)) - (PORT datad (893:893:893) (992:992:992)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (2470:2470:2470) (2664:2664:2664)) + (PORT datac (891:891:891) (959:959:959)) + (PORT datad (1997:1997:1997) (2087:2087:2087)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -12755,12 +11486,12 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~6) (DELAY (ABSOLUTE - (PORT dataa (659:659:659) (725:725:725)) - (PORT datab (648:648:648) (668:668:668)) - (PORT datac (628:628:628) (654:654:654)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (364:364:364) (394:394:394)) + (PORT datab (558:558:558) (580:580:580)) + (PORT datac (844:844:844) (879:879:879)) + (PORT datad (1124:1124:1124) (1141:1141:1141)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12771,12 +11502,12 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~7) (DELAY (ABSOLUTE - (PORT dataa (593:593:593) (609:609:609)) - (PORT datab (909:909:909) (956:956:956)) - (PORT datac (178:178:178) (217:217:217)) - (PORT datad (186:186:186) (218:218:218)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (1113:1113:1113) (1149:1149:1149)) + (PORT datab (1162:1162:1162) (1184:1184:1184)) + (PORT datac (794:794:794) (810:810:810)) + (PORT datad (642:642:642) (654:654:654)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12787,12 +11518,60 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~8) (DELAY (ABSOLUTE - (PORT dataa (355:355:355) (401:401:401)) - (PORT datab (402:402:402) (449:449:449)) - (PORT datac (820:820:820) (831:831:831)) - (PORT datad (752:752:752) (764:764:764)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (985:985:985) (1053:1053:1053)) + (PORT datab (1645:1645:1645) (1657:1657:1657)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1141:1141:1141) (1167:1167:1167)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1303:1303:1303)) + (PORT datab (1001:1001:1001) (1111:1111:1111)) + (PORT datac (655:655:655) (722:722:722)) + (PORT datad (1242:1242:1242) (1330:1330:1330)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (798:798:798)) + (PORT datab (653:653:653) (676:676:676)) + (PORT datac (834:834:834) (870:870:870)) + (PORT datad (1032:1032:1032) (1091:1091:1091)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (714:714:714) (749:749:749)) + (PORT datac (201:201:201) (236:236:236)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12803,12 +11582,10 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~11) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (662:662:662) (683:683:683)) - (PORT datad (340:340:340) (361:361:361)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (202:202:202) (246:246:246)) + (PORT datac (180:180:180) (218:218:218)) + (PORT datad (538:538:538) (562:562:562)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12819,12 +11596,12 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~12) (DELAY (ABSOLUTE - (PORT dataa (961:961:961) (1013:1013:1013)) - (PORT datab (967:967:967) (1028:1028:1028)) - (PORT datac (1321:1321:1321) (1338:1338:1338)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (1254:1254:1254) (1307:1307:1307)) + (PORT datab (845:845:845) (854:854:854)) + (PORT datac (835:835:835) (832:832:832)) + (PORT datad (874:874:874) (917:917:917)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12832,13 +11609,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[11\]) + (INSTANCE z80_\|address_latch_\|Q\[7\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1543:1543:1543)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1547:1547:1547)) - (PORT ena (2484:2484:2484) (2511:2511:2511)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2152:2152:2152) (2220:2220:2220)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -12850,25 +11627,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) (DELAY (ABSOLUTE - (PORT datab (470:470:470) (554:554:554)) - (PORT datad (546:546:546) (558:558:558)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (407:407:407) (434:434:434)) + (PORT datab (1814:1814:1814) (1895:1895:1895)) + (PORT datac (201:201:201) (236:236:236)) + (PORT datad (644:644:644) (699:699:699)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (INSTANCE z80_\|execute_\|fIOWrite\~0) (DELAY (ABSOLUTE - (PORT dataa (1101:1101:1101) (1125:1125:1125)) - (PORT datab (241:241:241) (280:280:280)) - (PORT datac (531:531:531) (534:534:534)) - (PORT datad (211:211:211) (243:243:243)) + (PORT dataa (1218:1218:1218) (1307:1307:1307)) + (PORT datab (2009:2009:2009) (2129:2129:2129)) + (PORT datac (1296:1296:1296) (1407:1407:1407)) + (PORT datad (2028:2028:2028) (2149:2149:2149)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (412:412:412)) + (PORT datab (213:213:213) (258:258:258)) + (PORT datac (1100:1100:1100) (1149:1149:1149)) + (PORT datad (1205:1205:1205) (1229:1229:1229)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -12878,325 +11675,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) (DELAY (ABSOLUTE - (PORT dataa (214:214:214) (265:265:265)) - (PORT datab (639:639:639) (662:662:662)) - (PORT datac (771:771:771) (809:809:809)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (425:425:425)) - (PORT datab (869:869:869) (876:876:876)) - (PORT datac (613:613:613) (636:636:636)) - (PORT datad (838:838:838) (883:883:883)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (892:892:892)) - (PORT datab (1629:1629:1629) (1659:1659:1659)) - (PORT datac (801:801:801) (804:804:804)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (727:727:727)) - (PORT datab (1163:1163:1163) (1238:1238:1238)) - (PORT datac (1317:1317:1317) (1383:1383:1383)) - (PORT datad (1177:1177:1177) (1218:1218:1218)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (675:675:675)) - (PORT datab (1149:1149:1149) (1207:1207:1207)) - (PORT datac (546:546:546) (569:569:569)) - (PORT datad (540:540:540) (557:557:557)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1351:1351:1351) (1376:1376:1376)) - (PORT datac (1969:1969:1969) (2008:2008:2008)) - (PORT datad (612:612:612) (623:623:623)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (691:691:691)) - (PORT datab (895:895:895) (991:991:991)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (904:904:904) (969:969:969)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1078:1078:1078) (1118:1118:1118)) - (PORT datab (877:877:877) (924:924:924)) - (PORT datac (1969:1969:1969) (2012:2012:2012)) - (PORT datad (1115:1115:1115) (1173:1173:1173)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (524:524:524) (547:547:547)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (870:870:870)) - (PORT datab (851:851:851) (899:899:899)) - (PORT datac (775:775:775) (808:808:808)) - (PORT datad (1274:1274:1274) (1316:1316:1316)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (335:335:335)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (1380:1380:1380) (1494:1494:1494)) - (PORT datad (889:889:889) (958:958:958)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (921:921:921) (956:956:956)) - (PORT datac (1664:1664:1664) (1793:1793:1793)) - (PORT datad (369:369:369) (393:393:393)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (599:599:599) (642:642:642)) - (PORT datac (331:331:331) (362:362:362)) - (PORT datad (1295:1295:1295) (1413:1413:1413)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (918:918:918)) - (PORT datab (1177:1177:1177) (1194:1194:1194)) - (PORT datac (842:842:842) (850:850:850)) - (PORT datad (848:848:848) (859:859:859)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1130:1130:1130)) - (PORT datab (637:637:637) (657:657:657)) - (PORT datac (1104:1104:1104) (1097:1097:1097)) - (PORT datad (1070:1070:1070) (1074:1074:1074)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1399:1399:1399)) - (PORT datab (803:803:803) (846:846:846)) - (PORT datac (1362:1362:1362) (1434:1434:1434)) - (PORT datad (634:634:634) (649:649:649)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (261:261:261) (318:318:318)) - (PORT datab (1093:1093:1093) (1122:1122:1122)) - (PORT datac (386:386:386) (431:431:431)) - (PORT datad (614:614:614) (629:629:629)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT datab (1164:1164:1164) (1272:1272:1272)) - (PORT datac (1188:1188:1188) (1298:1298:1298)) - (PORT datad (1142:1142:1142) (1245:1245:1245)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (218:218:218) (264:264:264)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (930:930:930) (1005:1005:1005)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datab (670:670:670) (725:725:725)) - (PORT datac (805:805:805) (823:823:823)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (865:865:865)) - (PORT datab (246:246:246) (287:287:287)) - (PORT datac (809:809:809) (835:835:835)) - (PORT datad (820:820:820) (826:826:826)) + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (1709:1709:1709) (1797:1797:1797)) + (PORT datac (549:549:549) (562:562:562)) + (PORT datad (173:173:173) (198:198:198)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13204,60 +11691,36 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) (DELAY (ABSOLUTE - (PORT dataa (887:887:887) (944:944:944)) - (PORT datab (863:863:863) (874:874:874)) - (PORT datac (516:516:516) (518:518:518)) - (PORT datad (815:815:815) (850:850:850)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (988:988:988) (1021:1021:1021)) + (PORT datac (1126:1126:1126) (1145:1145:1145)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (230:230:230) (272:272:272)) - (PORT datac (526:526:526) (532:532:532)) - (PORT datad (324:324:324) (346:346:346)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (619:619:619)) - (PORT datab (547:547:547) (561:561:561)) - (PORT datac (671:671:671) (706:706:706)) - (PORT datad (575:575:575) (586:586:586)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1002:1002:1002) (1072:1072:1072)) + (PORT datad (1126:1126:1126) (1143:1143:1143)) + (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1548:1548:1548)) + (PORT clk (1541:1541:1541) (1557:1557:1557)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13268,15 +11731,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) (DELAY (ABSOLUTE - (PORT dataa (1106:1106:1106) (1193:1193:1193)) - (PORT datab (918:918:918) (987:987:987)) - (PORT datac (1676:1676:1676) (1682:1682:1682)) - (PORT datad (1235:1235:1235) (1230:1230:1230)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (1546:1546:1546) (1602:1602:1602)) + (PORT datac (1206:1206:1206) (1268:1268:1268)) + (PORT datad (1073:1073:1073) (1099:1099:1099)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13284,61 +11745,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) (DELAY (ABSOLUTE - (PORT datab (1646:1646:1646) (1719:1719:1719)) - (PORT datac (619:619:619) (671:671:671)) - (PORT datad (338:338:338) (363:363:363)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1205:1205:1205) (1315:1315:1315)) - (PORT datab (1158:1158:1158) (1233:1233:1233)) - (PORT datac (801:801:801) (812:812:812)) - (PORT datad (548:548:548) (576:576:576)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (925:925:925)) - (PORT datab (1268:1268:1268) (1390:1390:1390)) - (PORT datac (1034:1034:1034) (1081:1081:1081)) - (PORT datad (1306:1306:1306) (1372:1372:1372)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (252:252:252)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1118:1118:1118) (1138:1138:1138)) - (PORT datad (3065:3065:3065) (3150:3150:3150)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (1543:1543:1543) (1602:1602:1602)) + (PORT datac (1215:1215:1215) (1279:1279:1279)) + (PORT datad (985:985:985) (1033:1033:1033)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13346,88 +11759,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~42) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) (DELAY (ABSOLUTE - (PORT dataa (888:888:888) (963:963:963)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1310:1310:1310) (1401:1401:1401)) - (PORT datad (1330:1330:1330) (1375:1375:1375)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1040:1040:1040)) - (PORT datab (575:575:575) (591:591:591)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT dataa (1169:1169:1169) (1196:1196:1196)) - (PORT datac (1218:1218:1218) (1241:1241:1241)) - (PORT datad (1390:1390:1390) (1409:1409:1409)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT datab (1254:1254:1254) (1277:1277:1277)) - (PORT datac (1273:1273:1273) (1283:1283:1283)) - (PORT datad (1391:1391:1391) (1411:1411:1411)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1268:1268:1268)) - (PORT datab (1448:1448:1448) (1562:1562:1562)) - (PORT datac (450:450:450) (488:488:488)) - (PORT datad (400:400:400) (427:427:427)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT datab (1254:1254:1254) (1276:1276:1276)) - (PORT datac (1273:1273:1273) (1282:1282:1282)) - (PORT datad (1390:1390:1390) (1410:1410:1410)) + (PORT datab (1542:1542:1542) (1602:1602:1602)) + (PORT datac (1217:1217:1217) (1279:1279:1279)) + (PORT datad (1074:1074:1074) (1100:1100:1100)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13436,11 +11773,705 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (719:719:719) (755:755:755)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1413:1413:1413) (1448:1448:1448)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT datab (1547:1547:1547) (1607:1607:1607)) + (PORT datac (1199:1199:1199) (1261:1261:1261)) + (PORT datad (990:990:990) (1037:1037:1037)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1413:1413:1413) (1447:1447:1447)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (916:916:916)) + (PORT datab (971:971:971) (1024:1024:1024)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT datab (1381:1381:1381) (1428:1428:1428)) + (PORT datac (1185:1185:1185) (1207:1207:1207)) + (PORT datad (589:589:589) (605:605:605)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (726:726:726) (753:753:753)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (407:407:407)) + (PORT datab (224:224:224) (272:272:272)) + (PORT datac (222:222:222) (301:301:301)) + (PORT datad (1218:1218:1218) (1299:1299:1299)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT datab (1209:1209:1209) (1234:1234:1234)) + (PORT datac (637:637:637) (665:665:665)) + (PORT datad (1346:1346:1346) (1393:1393:1393)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT datab (1212:1212:1212) (1239:1239:1239)) + (PORT datac (637:637:637) (665:665:665)) + (PORT datad (1342:1342:1342) (1391:1391:1391)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (725:725:725) (752:752:752)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (261:261:261) (314:314:314)) + (PORT datad (232:232:232) (270:270:270)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT datac (898:898:898) (941:941:941)) + (PORT datad (1326:1326:1326) (1381:1381:1381)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (770:770:770)) + (PORT datab (1175:1175:1175) (1215:1215:1215)) + (PORT datac (195:195:195) (238:238:238)) + (PORT datad (1436:1436:1436) (1519:1519:1519)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1192:1192:1192) (1227:1227:1227)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (765:765:765)) + (PORT datab (1172:1172:1172) (1214:1214:1214)) + (PORT datac (195:195:195) (237:237:237)) + (PORT datad (1438:1438:1438) (1518:1518:1518)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1193:1193:1193) (1225:1225:1225)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (505:505:505)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (640:640:640) (663:663:663)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (658:658:658)) + (PORT datab (950:950:950) (994:994:994)) + (PORT datad (672:672:672) (698:698:698)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (1673:1673:1673) (1678:1678:1678)) + (PORT ena (1499:1499:1499) (1507:1507:1507)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (674:674:674)) + (PORT datab (1409:1409:1409) (1424:1424:1424)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1144:1144:1144) (1180:1180:1180)) + (PORT datab (1171:1171:1171) (1213:1213:1213)) + (PORT datac (195:195:195) (238:238:238)) + (PORT datad (664:664:664) (715:715:715)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1225:1225:1225) (1263:1263:1263)) + (PORT ena (1220:1220:1220) (1214:1214:1214)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (962:962:962)) + (PORT datab (414:414:414) (473:473:473)) + (PORT datac (913:913:913) (963:963:963)) + (PORT datad (609:609:609) (629:629:629)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (973:973:973)) + (PORT datab (938:938:938) (1019:1019:1019)) + (PORT datac (1135:1135:1135) (1179:1179:1179)) + (PORT datad (378:378:378) (412:412:412)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT datab (929:929:929) (993:993:993)) + (PORT datac (1324:1324:1324) (1357:1357:1357)) + (PORT datad (891:891:891) (947:947:947)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1168:1168:1168) (1265:1265:1265)) + (PORT datab (1178:1178:1178) (1216:1216:1216)) + (PORT datac (195:195:195) (239:239:239)) + (PORT datad (671:671:671) (719:719:719)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (1674:1674:1674) (1676:1676:1676)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT dataa (1791:1791:1791) (1805:1805:1805)) + (PORT datab (916:916:916) (986:986:986)) + (PORT datad (905:905:905) (958:958:958)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1226:1226:1226) (1265:1265:1265)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (433:433:433) (465:465:465)) + (PORT datab (634:634:634) (665:665:665)) + (PORT datad (357:357:357) (410:410:410)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (1721:1721:1721) (1780:1780:1780)) + (PORT datab (1171:1171:1171) (1225:1225:1225)) + (PORT datad (792:792:792) (797:797:797)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1407:1407:1407) (1434:1434:1434)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (841:841:841) (868:868:868)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT datab (1032:1032:1032) (1065:1065:1065)) + (PORT datac (905:905:905) (951:951:951)) + (PORT datad (876:876:876) (937:937:937)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (468:468:468)) + (PORT datab (590:590:590) (630:630:630)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (530:530:530) (540:540:540)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (699:699:699)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (780:780:780) (810:810:810)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (397:397:397)) + (PORT datab (625:625:625) (654:654:654)) + (PORT datac (1393:1393:1393) (1416:1416:1416)) + (PORT datad (618:618:618) (673:673:673)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1402:1402:1402) (1441:1441:1441)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (264:264:264)) + (PORT datab (1232:1232:1232) (1270:1270:1270)) + (PORT datad (658:658:658) (688:688:688)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (671:671:671) (703:703:703)) + (PORT datac (1147:1147:1147) (1188:1188:1188)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1460:1460:1460) (1492:1492:1492)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1460:1460:1460) (1491:1491:1491)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (262:262:262) (315:315:315)) + (PORT datad (233:233:233) (271:271:271)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1185:1185:1185) (1213:1213:1213)) (PORT ena (816:816:816) (813:813:813)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13452,41 +12483,131 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1450:1450:1450) (1474:1474:1474)) - (PORT datab (244:244:244) (290:290:290)) - (PORT datad (1246:1246:1246) (1245:1245:1245)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1182:1182:1182) (1227:1227:1227)) + (PORT datab (1541:1541:1541) (1602:1602:1602)) + (PORT datad (1074:1074:1074) (1100:1100:1100)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT dataa (1168:1168:1168) (1197:1197:1197)) - (PORT datac (1221:1221:1221) (1244:1244:1244)) - (PORT datad (1391:1391:1391) (1414:1414:1414)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1483:1483:1483) (1519:1519:1519)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (688:688:688)) + (PORT datab (1088:1088:1088) (1097:1097:1097)) + (PORT datad (940:940:940) (980:980:980)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1236:1236:1236) (1247:1247:1247)) + (PORT ena (1220:1220:1220) (1214:1214:1214)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1237:1237:1237) (1246:1246:1246)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (696:696:696)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (367:367:367) (395:395:395)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1461:1461:1461) (1534:1534:1534)) + (PORT ena (1505:1505:1505) (1518:1518:1518)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (347:347:347) (372:372:372)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1021:1021:1021) (1037:1037:1037)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13496,14 +12617,217 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT datab (369:369:369) (407:407:407)) - (PORT datac (447:447:447) (483:483:483)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1458:1458:1458) (1530:1530:1530)) + (PORT ena (1407:1407:1407) (1382:1382:1382)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (499:499:499)) + (PORT datab (652:652:652) (676:676:676)) + (PORT datad (827:827:827) (837:837:837)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (1256:1256:1256)) + (PORT datab (919:919:919) (944:944:944)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (939:939:939) (964:964:964)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (491:491:491)) + (PORT datab (1133:1133:1133) (1178:1178:1178)) + (PORT datad (539:539:539) (559:559:559)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1719:1719:1719) (1765:1765:1765)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1719:1719:1719) (1768:1768:1768)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (470:470:470)) + (PORT datab (585:585:585) (623:623:623)) + (PORT datad (216:216:216) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (635:635:635)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (344:344:344) (368:368:368)) + (PORT datad (597:597:597) (607:607:607)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1235:1235:1235)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (1104:1104:1104) (1151:1151:1151)) + (PORT datad (820:820:820) (839:839:839)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1589:1589:1589) (1608:1608:1608)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1198:1198:1198)) + (PORT datab (697:697:697) (724:724:724)) + (PORT datad (1194:1194:1194) (1230:1230:1230)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (243:243:243) (325:325:325)) + (PORT datac (706:706:706) (737:737:737)) + (PORT datad (842:842:842) (876:876:876)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (985:985:985)) + (PORT datab (912:912:912) (985:985:985)) + (PORT datac (1500:1500:1500) (1547:1547:1547)) + (PORT datad (662:662:662) (730:730:730)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13518,24 +12842,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~0) - (DELAY - (ABSOLUTE - (PORT datab (663:663:663) (741:741:741)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~14) (DELAY (ABSOLUTE - (PORT datab (410:410:410) (485:485:485)) + (PORT datab (1393:1393:1393) (1462:1462:1462)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13549,9 +12861,9 @@ (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT datab (1265:1265:1265) (1315:1315:1315)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (265:265:265) (352:352:352)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13563,9 +12875,9 @@ (INSTANCE ula_\|video_\|vga_hc\~2) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datad (382:382:382) (409:409:409)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datac (830:830:830) (872:872:872)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13575,13 +12887,13 @@ (INSTANCE ula_\|video_\|vga_hc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) - (PORT asdata (1389:1389:1389) (1382:1382:1382)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL @@ -13589,8 +12901,8 @@ (INSTANCE ula_\|video_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datab (1519:1519:1519) (1605:1605:1605)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datad (660:660:660) (722:722:722)) + (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -13600,8 +12912,8 @@ (INSTANCE ula_\|video_\|vga_hc\~1) (DELAY (ABSOLUTE - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (382:382:382) (407:407:407)) + (PORT datab (230:230:230) (272:272:272)) + (PORT datad (560:560:560) (588:588:588)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13612,59 +12924,23 @@ (INSTANCE ula_\|video_\|vga_hc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) - (PORT asdata (663:663:663) (688:688:688)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~0) + (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT dataa (988:988:988) (1078:1078:1078)) - (PORT datab (705:705:705) (785:785:785)) - (PORT datac (1215:1215:1215) (1307:1307:1307)) - (PORT datad (682:682:682) (765:765:765)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1486:1486:1486)) - (PORT datab (644:644:644) (703:703:703)) - (PORT datac (1172:1172:1172) (1220:1220:1220)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1557:1557:1557) (1645:1645:1645)) - (PORT datab (1221:1221:1221) (1283:1283:1283)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (1160:1160:1160) (1229:1229:1229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (1071:1071:1071) (1110:1110:1110)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13674,8 +12950,8 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (310:310:310) (328:328:328)) - (PORT datad (203:203:203) (232:232:232)) + (PORT datac (830:830:830) (865:865:865)) + (PORT datad (903:903:903) (941:941:941)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13687,72 +12963,6 @@ (DELAY (ABSOLUTE (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT asdata (912:912:912) (917:917:917)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~2) - (DELAY - (ABSOLUTE - (PORT datab (703:703:703) (787:787:787)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (948:948:948) (966:966:966)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1069:1069:1069)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (871:871:871) (884:884:884)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13763,10 +12973,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~6) + (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (1202:1202:1202) (1248:1248:1248)) + (PORT datab (672:672:672) (727:727:727)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13775,12 +12985,88 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (590:590:590) (612:612:612)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT datab (410:410:410) (485:485:485)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT asdata (663:663:663) (679:679:679)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (693:693:693) (745:745:745)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (558:558:558) (581:581:581)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13794,9 +13080,9 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (408:408:408) (481:481:481)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (1094:1094:1094) (1127:1127:1127)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13808,8 +13094,8 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) - (PORT asdata (916:916:916) (926:926:926)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT asdata (662:662:662) (678:678:678)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13817,12 +13103,59 @@ (HOLD asdata (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1251:1251:1251) (1340:1340:1340)) + (PORT datab (983:983:983) (1062:1062:1062)) + (PORT datac (978:978:978) (1050:1050:1050)) + (PORT datad (282:282:282) (366:366:366)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (737:737:737)) + (PORT datab (1394:1394:1394) (1464:1464:1464)) + (PORT datad (941:941:941) (937:937:937)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (523:523:523)) + (PORT datab (684:684:684) (758:758:758)) + (PORT datac (646:646:646) (716:716:716)) + (PORT datad (570:570:570) (576:576:576)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (1410:1410:1410) (1451:1451:1451)) + (PORT dataa (684:684:684) (734:734:734)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13836,9 +13169,9 @@ (INSTANCE ula_\|video_\|vga_hc\~0) (DELAY (ABSOLUTE - (PORT dataa (344:344:344) (371:371:371)) - (PORT datad (377:377:377) (403:403:403)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datac (833:833:833) (875:875:875)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13848,13 +13181,13 @@ (INSTANCE ula_\|video_\|vga_hc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) - (PORT asdata (923:923:923) (933:933:933)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL @@ -13862,7 +13195,7 @@ (INSTANCE ula_\|video_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (424:424:424) (506:506:506)) + (PORT dataa (629:629:629) (686:686:686)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13876,8 +13209,8 @@ (INSTANCE ula_\|video_\|vga_hc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) - (PORT asdata (661:661:661) (685:685:685)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT asdata (516:516:516) (547:547:547)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13890,8 +13223,8 @@ (INSTANCE ula_\|video_\|vga_hc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) - (PORT asdata (841:841:841) (851:851:851)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT asdata (869:869:869) (872:872:872)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13904,48 +13237,19 @@ (INSTANCE ula_\|video_\|Add1\~0) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1310:1310:1310)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (720:720:720) (795:795:795)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (755:755:755) (812:812:812)) - (PORT datab (720:720:720) (780:780:780)) - (PORT datad (327:327:327) (342:342:342)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~2) (DELAY (ABSOLUTE - (PORT dataa (471:471:471) (547:547:547)) + (PORT dataa (707:707:707) (782:782:782)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13959,9 +13263,9 @@ (INSTANCE ula_\|video_\|Add1\~4) (DELAY (ABSOLUTE - (PORT datab (448:448:448) (518:518:518)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (679:679:679) (747:747:747)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13973,9 +13277,9 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (753:753:753) (811:811:811)) - (PORT datab (340:340:340) (362:362:362)) - (PORT datad (681:681:681) (733:733:733)) + (PORT dataa (517:517:517) (564:564:564)) + (PORT datab (595:595:595) (609:609:609)) + (PORT datad (899:899:899) (922:922:922)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13988,7 +13292,7 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14002,7 +13306,7 @@ (INSTANCE ula_\|video_\|Add1\~6) (DELAY (ABSOLUTE - (PORT dataa (680:680:680) (744:744:744)) + (PORT dataa (712:712:712) (782:782:782)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -14016,12 +13320,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (756:756:756) (813:813:813)) - (PORT datab (721:721:721) (780:780:780)) - (PORT datad (306:306:306) (319:319:319)) + (PORT dataa (616:616:616) (648:648:648)) + (PORT datab (645:645:645) (692:692:692)) + (PORT datac (679:679:679) (747:747:747)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14031,13 +13336,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1361:1361:1361) (1352:1352:1352)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -14045,9 +13350,9 @@ (INSTANCE ula_\|video_\|Add1\~8) (DELAY (ABSOLUTE - (PORT dataa (436:436:436) (515:515:515)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (680:680:680) (762:762:762)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -14059,11 +13364,11 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) (DELAY (ABSOLUTE - (PORT dataa (755:755:755) (813:813:813)) - (PORT datab (715:715:715) (772:772:772)) - (PORT datad (329:329:329) (346:346:346)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (516:516:516) (565:565:565)) + (PORT datab (625:625:625) (643:643:643)) + (PORT datad (899:899:899) (921:921:921)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14074,7 +13379,7 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14088,9 +13393,9 @@ (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT datab (291:291:291) (377:377:377)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (690:690:690) (785:785:785)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -14102,12 +13407,13 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) (DELAY (ABSOLUTE - (PORT dataa (674:674:674) (714:714:714)) - (PORT datab (1413:1413:1413) (1416:1416:1416)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (616:616:616) (645:645:645)) + (PORT datab (645:645:645) (689:689:689)) + (PORT datac (698:698:698) (778:778:778)) + (PORT datad (175:175:175) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14117,13 +13423,13 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (884:884:884) (883:883:883)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -14131,9 +13437,9 @@ (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT dataa (440:440:440) (520:520:520)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (720:720:720) (789:789:789)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -14145,11 +13451,11 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (755:755:755) (813:813:813)) - (PORT datab (720:720:720) (781:781:781)) - (PORT datad (311:311:311) (325:325:325)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (519:519:519) (562:562:562)) + (PORT datab (588:588:588) (607:607:607)) + (PORT datad (902:902:902) (917:917:917)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14160,7 +13466,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14174,9 +13480,9 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT dataa (707:707:707) (766:766:766)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (691:691:691) (762:762:762)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -14188,9 +13494,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (753:753:753) (812:812:812)) - (PORT datab (597:597:597) (602:602:602)) - (PORT datad (680:680:680) (734:734:734)) + (PORT dataa (517:517:517) (566:566:566)) + (PORT datab (1177:1177:1177) (1178:1178:1178)) + (PORT datad (900:900:900) (920:920:920)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -14203,7 +13509,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14217,7 +13523,7 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (473:473:473) (538:538:538)) + (PORT datab (743:743:743) (817:817:817)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -14231,11 +13537,11 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (757:757:757) (813:813:813)) - (PORT datab (722:722:722) (780:780:780)) - (PORT datad (310:310:310) (326:326:326)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (517:517:517) (558:558:558)) + (PORT datab (998:998:998) (1000:1000:1000)) + (PORT datad (899:899:899) (916:916:916)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14246,7 +13552,47 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datad (650:650:650) (707:707:707)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (518:518:518) (565:565:565)) + (PORT datab (1005:1005:1005) (1007:1007:1007)) + (PORT datad (899:899:899) (922:922:922)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14260,10 +13606,10 @@ (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (384:384:384)) - (PORT datab (291:291:291) (377:377:377)) - (PORT datac (264:264:264) (345:345:345)) - (PORT datad (263:263:263) (335:335:335)) + (PORT dataa (272:272:272) (361:361:361)) + (PORT datab (270:270:270) (356:356:356)) + (PORT datac (263:263:263) (343:343:343)) + (PORT datad (244:244:244) (317:317:317)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14273,25 +13619,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~18) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT datad (398:398:398) (466:466:466)) + (PORT dataa (1173:1173:1173) (1262:1262:1262)) + (PORT datab (846:846:846) (922:922:922)) + (PORT datac (628:628:628) (679:679:679)) + (PORT datad (673:673:673) (746:746:746)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) + (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (755:755:755) (813:813:813)) - (PORT datab (711:711:711) (770:770:770)) - (PORT datad (331:331:331) (347:347:347)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (635:635:635) (701:701:701)) + (PORT datab (664:664:664) (725:725:725)) + (PORT datac (564:564:564) (582:582:582)) + (PORT datad (306:306:306) (321:321:321)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (518:518:518) (561:561:561)) + (PORT datab (553:553:553) (567:567:567)) + (PORT datad (900:900:900) (915:915:915)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14299,10 +13666,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[9\]) + (INSTANCE ula_\|video_\|vga_vc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14311,46 +13678,14 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1435:1435:1435) (1511:1511:1511)) - (PORT datab (1290:1290:1290) (1361:1361:1361)) - (PORT datac (1227:1227:1227) (1310:1310:1310)) - (PORT datad (1136:1136:1136) (1184:1184:1184)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (714:714:714)) - (PORT datab (744:744:744) (812:812:812)) - (PORT datac (716:716:716) (780:780:780)) - (PORT datad (316:316:316) (336:336:336)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (755:755:755) (813:813:813)) - (PORT datab (336:336:336) (364:364:364)) - (PORT datad (682:682:682) (730:730:730)) + (PORT dataa (516:516:516) (560:560:560)) + (PORT datab (566:566:566) (575:575:575)) + (PORT datad (899:899:899) (916:916:916)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -14363,7 +13698,7 @@ (INSTANCE ula_\|video_\|vga_vc\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14386,10 +13721,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (1532:1532:1532) (1599:1599:1599)) - (PORT datab (1309:1309:1309) (1222:1222:1222)) - (PORT datac (1203:1203:1203) (1295:1295:1295)) - (PORT datad (1454:1454:1454) (1523:1523:1523)) + (PORT dataa (1420:1420:1420) (1497:1497:1497)) + (PORT datab (716:716:716) (801:801:801)) + (PORT datac (1844:1844:1844) (1733:1733:1733)) + (PORT datad (677:677:677) (732:732:732)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14402,10 +13737,10 @@ (INSTANCE z80_\|pla_decode_\|Equal79\~0) (DELAY (ABSOLUTE - (PORT dataa (1205:1205:1205) (1277:1277:1277)) - (PORT datab (947:947:947) (980:980:980)) - (PORT datac (1606:1606:1606) (1706:1706:1706)) - (PORT datad (1612:1612:1612) (1692:1692:1692)) + (PORT dataa (1251:1251:1251) (1348:1348:1348)) + (PORT datab (976:976:976) (1034:1034:1034)) + (PORT datac (1637:1637:1637) (1758:1758:1758)) + (PORT datad (1191:1191:1191) (1306:1306:1306)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -14413,30 +13748,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (267:267:267) (355:355:355)) - (PORT datab (828:828:828) (846:846:846)) - (PORT datac (2848:2848:2848) (2926:2926:2926)) - (PORT datad (997:997:997) (1010:1010:1010)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) (DELAY (ABSOLUTE - (PORT dataa (2853:2853:2853) (2937:2937:2937)) - (PORT datab (1022:1022:1022) (1050:1050:1050)) - (PORT datad (803:803:803) (811:811:811)) + (PORT dataa (1500:1500:1500) (1602:1602:1602)) + (PORT datab (361:361:361) (391:391:391)) + (PORT datad (665:665:665) (720:720:720)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -14449,11 +13768,11 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) (DELAY (ABSOLUTE - (PORT dataa (337:337:337) (453:453:453)) - (PORT datac (1158:1158:1158) (1272:1272:1272)) - (PORT datad (279:279:279) (363:363:363)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (357:357:357) (495:495:495)) + (PORT datab (2014:2014:2014) (2140:2140:2140)) + (PORT datad (275:275:275) (358:358:358)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14463,7 +13782,7 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (1270:1270:1270) (1279:1279:1279)) + (PORT inclk[0] (1586:1586:1586) (1625:1625:1625)) ) ) ) @@ -14472,9 +13791,9 @@ (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) + (PORT clk (1537:1537:1537) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1549:1549:1549) (1541:1541:1541)) + (PORT clrn (1552:1552:1552) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -14483,18 +13802,34 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (765:765:765)) + (PORT datab (266:266:266) (349:349:349)) + (PORT datac (204:204:204) (241:241:241)) + (PORT datad (1456:1456:1456) (1550:1550:1550)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|interrupts_\|iff1\~1) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (266:266:266) (350:350:350)) - (PORT datac (1580:1580:1580) (1636:1636:1636)) - (PORT datad (924:924:924) (968:968:968)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1287:1287:1287) (1330:1330:1330)) + (PORT datab (266:266:266) (349:349:349)) + (PORT datac (888:888:888) (913:913:913)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14504,11 +13839,11 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT dataa (342:342:342) (463:463:463)) - (PORT datac (1159:1159:1159) (1274:1274:1274)) - (PORT datad (285:285:285) (370:370:370)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (1431:1431:1431) (1492:1492:1492)) + (PORT datac (1518:1518:1518) (1551:1551:1551)) + (PORT datad (1267:1267:1267) (1335:1335:1335)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14518,9 +13853,9 @@ (INSTANCE z80_\|interrupts_\|iff1) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) + (PORT clk (1537:1537:1537) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1427:1427:1427) (1430:1430:1430)) + (PORT clrn (1403:1403:1403) (1412:1412:1412)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -14534,10 +13869,10 @@ (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (1257:1257:1257) (1348:1348:1348)) - (PORT datab (1289:1289:1289) (1358:1358:1358)) - (PORT datac (713:713:713) (778:778:778)) - (PORT datad (1135:1135:1135) (1184:1184:1184)) + (PORT dataa (1600:1600:1600) (1657:1657:1657)) + (PORT datab (843:843:843) (917:917:917)) + (PORT datac (633:633:633) (688:688:688)) + (PORT datad (427:427:427) (498:498:498)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14550,11 +13885,11 @@ (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT datab (743:743:743) (810:810:810)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (655:655:655) (666:666:666)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (565:565:565) (583:583:583)) + (PORT datad (436:436:436) (516:516:516)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14564,10 +13899,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT dataa (1513:1513:1513) (1645:1645:1645)) - (PORT datab (888:888:888) (917:917:917)) - (PORT datac (1865:1865:1865) (1978:1978:1978)) - (PORT datad (1421:1421:1421) (1479:1479:1479)) + (PORT dataa (1175:1175:1175) (1240:1240:1240)) + (PORT datab (630:630:630) (645:645:645)) + (PORT datac (1541:1541:1541) (1636:1636:1636)) + (PORT datad (848:848:848) (861:861:861)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -14580,9 +13915,9 @@ (INSTANCE z80_\|interrupts_\|int_armed) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1531:1531:1531) (1542:1542:1542)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (PORT clrn (1562:1562:1562) (1552:1552:1552)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -14591,59 +13926,33 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_inst44\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1408:1408:1408) (1517:1517:1517)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|interrupts_\|DFFE_inst44) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) - (PORT ena (957:957:957) (955:955:955)) + (PORT clk (1533:1533:1533) (1552:1552:1552)) + (PORT asdata (2158:2158:2158) (2284:2284:2284)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (1669:1669:1669) (1678:1678:1678)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (INSTANCE z80_\|execute_\|pc_inc_hold\~38) (DELAY (ABSOLUTE - (PORT dataa (337:337:337) (451:451:451)) - (PORT datab (305:305:305) (400:400:400)) - (PORT datac (251:251:251) (334:334:334)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (885:885:885)) - (PORT datab (954:954:954) (994:994:994)) - (PORT datac (922:922:922) (1000:1000:1000)) - (PORT datad (524:524:524) (533:533:533)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (355:355:355) (487:487:487)) + (PORT datac (1180:1180:1180) (1261:1261:1261)) + (PORT datad (269:269:269) (350:350:350)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14651,15 +13960,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) (DELAY (ABSOLUTE - (PORT dataa (1147:1147:1147) (1193:1193:1193)) - (PORT datab (426:426:426) (465:465:465)) - (PORT datac (1273:1273:1273) (1298:1298:1298)) - (PORT datad (1209:1209:1209) (1200:1200:1200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1671:1671:1671) (1790:1790:1790)) + (PORT datab (1251:1251:1251) (1347:1347:1347)) + (PORT datac (971:971:971) (1065:1065:1065)) + (PORT datad (862:862:862) (887:887:887)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14667,79 +13976,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (INSTANCE z80_\|execute_\|pc_inc_hold\~45) (DELAY (ABSOLUTE - (PORT dataa (1723:1723:1723) (1798:1798:1798)) - (PORT datab (1320:1320:1320) (1359:1359:1359)) - (PORT datac (1187:1187:1187) (1231:1231:1231)) - (PORT datad (1718:1718:1718) (1735:1735:1735)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT dataa (1089:1089:1089) (1139:1139:1139)) + (PORT datab (699:699:699) (765:765:765)) + (PORT datac (1191:1191:1191) (1271:1271:1271)) + (PORT datad (626:626:626) (668:668:668)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (875:875:875)) - (PORT datab (653:653:653) (676:676:676)) - (PORT datac (798:798:798) (819:819:819)) - (PORT datad (625:625:625) (660:660:660)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (198:198:198) (235:235:235)) - (PORT datac (812:812:812) (831:831:831)) - (PORT datad (1434:1434:1434) (1463:1463:1463)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (647:647:647) (702:702:702)) - (PORT datac (641:641:641) (699:699:699)) - (PORT datad (857:857:857) (884:884:884)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (741:741:741)) - (PORT datab (666:666:666) (737:737:737)) - (PORT datac (788:788:788) (800:800:800)) - (PORT datad (617:617:617) (630:630:630)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14747,15 +13992,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (INSTANCE z80_\|execute_\|pc_inc_hold\~44) (DELAY (ABSOLUTE - (PORT dataa (901:901:901) (949:949:949)) - (PORT datab (1469:1469:1469) (1501:1501:1501)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (300:300:300) (308:308:308)) + (PORT dataa (1090:1090:1090) (1140:1140:1140)) + (PORT datab (909:909:909) (981:981:981)) + (PORT datac (856:856:856) (898:898:898)) + (PORT datad (1096:1096:1096) (1107:1107:1107)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~46) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (372:372:372)) + (PORT datab (702:702:702) (770:770:770)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1101:1101:1101) (1112:1112:1112)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14763,13 +14024,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (INSTANCE z80_\|execute_\|pc_inc_hold\~37) (DELAY (ABSOLUTE - (PORT dataa (1151:1151:1151) (1227:1227:1227)) - (PORT datab (869:869:869) (891:891:891)) - (PORT datac (1143:1143:1143) (1157:1157:1157)) - (PORT datad (1572:1572:1572) (1594:1594:1594)) + (PORT dataa (1161:1161:1161) (1207:1207:1207)) + (PORT datab (884:884:884) (933:933:933)) + (PORT datac (1058:1058:1058) (1098:1098:1098)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~50) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (863:863:863)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1604:1604:1604) (1719:1719:1719)) + (PORT datad (2285:2285:2285) (2389:2389:2389)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (1151:1151:1151) (1219:1219:1219)) + (PORT datac (1080:1080:1080) (1126:1126:1126)) + (PORT datad (596:596:596) (629:629:629)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -14782,10 +14075,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) (DELAY (ABSOLUTE - (PORT dataa (916:916:916) (967:967:967)) - (PORT datab (1277:1277:1277) (1290:1290:1290)) - (PORT datac (1152:1152:1152) (1210:1210:1210)) - (PORT datad (1719:1719:1719) (1745:1745:1745)) + (PORT dataa (1685:1685:1685) (1750:1750:1750)) + (PORT datab (623:623:623) (672:672:672)) + (PORT datac (1663:1663:1663) (1743:1743:1743)) + (PORT datad (1164:1164:1164) (1212:1212:1212)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -14795,29 +14088,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) (DELAY (ABSOLUTE - (PORT dataa (1116:1116:1116) (1145:1145:1145)) - (PORT datab (721:721:721) (797:797:797)) - (PORT datac (563:563:563) (570:570:570)) - (PORT datad (1078:1078:1078) (1086:1086:1086)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (729:729:729) (825:825:825)) + (PORT datab (672:672:672) (761:761:761)) + (PORT datac (1148:1148:1148) (1186:1186:1186)) + (PORT datad (212:212:212) (247:247:247)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (INSTANCE z80_\|execute_\|pc_inc_hold\~31) (DELAY (ABSOLUTE - (PORT dataa (367:367:367) (402:402:402)) - (PORT datab (886:886:886) (944:944:944)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (181:181:181) (209:209:209)) + (PORT dataa (1112:1112:1112) (1165:1165:1165)) + (PORT datab (850:850:850) (866:866:866)) + (PORT datac (1208:1208:1208) (1236:1236:1236)) + (PORT datad (822:822:822) (834:834:834)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1168:1168:1168)) + (PORT datab (622:622:622) (673:673:673)) + (PORT datac (209:209:209) (250:250:250)) + (PORT datad (1641:1641:1641) (1711:1711:1711)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~34) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (193:193:193) (238:238:238)) + (PORT datad (180:180:180) (209:209:209)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -14827,15 +14152,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (INSTANCE z80_\|execute_\|pc_inc_hold\~51) (DELAY (ABSOLUTE - (PORT dataa (1117:1117:1117) (1146:1146:1146)) - (PORT datab (900:900:900) (910:910:910)) - (PORT datac (692:692:692) (761:761:761)) - (PORT datad (815:815:815) (820:820:820)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1149:1149:1149) (1191:1191:1191)) + (PORT datab (1399:1399:1399) (1505:1505:1505)) + (PORT datac (2514:2514:2514) (2618:2618:2618)) + (PORT datad (1497:1497:1497) (1611:1611:1611)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14843,47 +14168,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~41) + (INSTANCE z80_\|execute_\|pc_inc_hold\~30) (DELAY (ABSOLUTE - (PORT dataa (996:996:996) (1115:1115:1115)) - (PORT datab (993:993:993) (1093:1093:1093)) - (PORT datac (1204:1204:1204) (1289:1289:1289)) - (PORT datad (962:962:962) (1055:1055:1055)) + (PORT dataa (691:691:691) (738:738:738)) + (PORT datab (1144:1144:1144) (1210:1210:1210)) + (PORT datac (365:365:365) (393:393:393)) + (PORT datad (865:865:865) (890:890:890)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1521:1521:1521) (1648:1648:1648)) + (PORT datab (1395:1395:1395) (1501:1501:1501)) + (PORT datac (2518:2518:2518) (2621:2621:2621)) + (PORT datad (1054:1054:1054) (1086:1086:1086)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (406:406:406)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (619:619:619) (652:652:652)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1123:1123:1123)) + (PORT datab (643:643:643) (662:662:662)) + (PORT datac (625:625:625) (646:646:646)) + (PORT datad (1379:1379:1379) (1419:1419:1419)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~21) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (826:826:826)) - (PORT datab (1026:1026:1026) (1059:1059:1059)) - (PORT datac (706:706:706) (795:795:795)) - (PORT datad (1012:1012:1012) (1095:1095:1095)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~26) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (277:277:277)) - (PORT datab (215:215:215) (259:259:259)) - (PORT datac (614:614:614) (668:668:668)) - (PORT datad (608:608:608) (649:649:649)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14894,390 +14235,10 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) (DELAY (ABSOLUTE - (PORT dataa (968:968:968) (1041:1041:1041)) - (PORT datab (870:870:870) (888:888:888)) - (PORT datac (1021:1021:1021) (1043:1043:1043)) - (PORT datad (865:865:865) (864:864:864)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (406:406:406)) - (PORT datab (873:873:873) (907:907:907)) - (PORT datac (1040:1040:1040) (1071:1071:1071)) - (PORT datad (805:805:805) (851:851:851)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (1666:1666:1666) (1760:1760:1760)) - (PORT datac (935:935:935) (1001:1001:1001)) - (PORT datad (850:850:850) (850:850:850)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (663:663:663)) - (PORT datab (205:205:205) (248:248:248)) - (PORT datac (799:799:799) (823:823:823)) - (PORT datad (1427:1427:1427) (1479:1479:1479)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (192:192:192) (226:226:226)) - (PORT datad (793:793:793) (797:797:797)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (1124:1124:1124) (1152:1152:1152)) - (PORT datab (1101:1101:1101) (1127:1127:1127)) - (PORT datac (557:557:557) (566:566:566)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (1011:1011:1011)) - (PORT datac (737:737:737) (744:744:744)) - (PORT datad (913:913:913) (995:995:995)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1308:1308:1308)) - (PORT datab (1399:1399:1399) (1472:1472:1472)) - (PORT datac (1142:1142:1142) (1217:1217:1217)) - (PORT datad (1125:1125:1125) (1209:1209:1209)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~27) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (690:690:690)) - (PORT datab (1276:1276:1276) (1321:1321:1321)) - (PORT datac (777:777:777) (786:786:786)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (706:706:706)) - (PORT datab (939:939:939) (1032:1032:1032)) - (PORT datac (645:645:645) (689:689:689)) - (PORT datad (895:895:895) (965:965:965)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (674:674:674) (700:700:700)) - (PORT datac (1026:1026:1026) (1023:1023:1023)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1157:1157:1157)) - (PORT datab (843:843:843) (874:874:874)) - (PORT datac (597:597:597) (619:619:619)) - (PORT datad (826:826:826) (864:864:864)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1062:1062:1062)) - (PORT datab (675:675:675) (700:700:700)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1113:1113:1113)) - (PORT datab (993:993:993) (1093:1093:1093)) - (PORT datac (1024:1024:1024) (1036:1036:1036)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (870:870:870)) - (PORT datab (844:844:844) (880:880:880)) - (PORT datac (1079:1079:1079) (1127:1127:1127)) - (PORT datad (825:825:825) (861:861:861)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (458:458:458)) - (PORT datab (311:311:311) (410:410:410)) - (PORT datac (249:249:249) (330:330:330)) - (PORT datad (855:855:855) (894:894:894)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (403:403:403)) - (PORT datab (723:723:723) (798:798:798)) - (PORT datac (493:493:493) (502:502:502)) - (PORT datad (1632:1632:1632) (1662:1662:1662)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1106:1106:1106) (1130:1130:1130)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1085:1085:1085) (1108:1108:1108)) - (PORT datad (338:338:338) (359:359:359)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (606:606:606)) - (PORT datab (1180:1180:1180) (1235:1235:1235)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1247:1247:1247)) - (PORT datab (721:721:721) (797:797:797)) - (PORT datac (879:879:879) (927:927:927)) - (PORT datad (1718:1718:1718) (1745:1745:1745)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (402:402:402)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (1269:1269:1269) (1278:1278:1278)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1354:1354:1354) (1397:1397:1397)) - (PORT datab (695:695:695) (791:791:791)) - (PORT datac (726:726:726) (826:826:826)) - (PORT datad (1008:1008:1008) (1091:1091:1091)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (276:276:276)) - (PORT datab (542:542:542) (566:566:566)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (643:643:643) (689:689:689)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (279:279:279)) - (PORT datac (617:617:617) (670:670:670)) - (PORT datad (186:186:186) (218:218:218)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT dataa (769:769:769) (873:873:873)) - (PORT datab (1056:1056:1056) (1140:1140:1140)) - (PORT datac (663:663:663) (757:757:757)) - (PORT datad (1288:1288:1288) (1293:1293:1293)) + (PORT dataa (2071:2071:2071) (2185:2185:2185)) + (PORT datab (910:910:910) (981:981:981)) + (PORT datac (1397:1397:1397) (1483:1483:1483)) + (PORT datad (646:646:646) (677:677:677)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -15287,137 +14248,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (593:593:593) (644:644:644)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (1723:1723:1723) (1798:1798:1798)) - (PORT datab (1348:1348:1348) (1417:1417:1417)) - (PORT datac (1187:1187:1187) (1231:1231:1231)) - (PORT datad (1101:1101:1101) (1169:1169:1169)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT datab (847:847:847) (851:851:851)) - (PORT datac (996:996:996) (1014:1014:1014)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (279:279:279)) - (PORT datac (1266:1266:1266) (1273:1273:1273)) - (PORT datad (185:185:185) (217:217:217)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (169:169:169) (202:202:202)) - (PORT datad (587:587:587) (626:626:626)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (700:700:700)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (802:802:802) (827:827:827)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (529:529:529) (558:558:558)) - (PORT datab (204:204:204) (245:245:245)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (384:384:384)) - (PORT datab (800:800:800) (842:842:842)) - (PORT datad (837:837:837) (860:860:860)) + (PORT dataa (1333:1333:1333) (1437:1437:1437)) + (PORT datab (1764:1764:1764) (1881:1881:1881)) + (PORT datad (630:630:630) (685:685:685)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) (DELAY (ABSOLUTE - (PORT dataa (1134:1134:1134) (1199:1199:1199)) - (PORT datab (1163:1163:1163) (1206:1206:1206)) - (PORT datac (1177:1177:1177) (1255:1255:1255)) - (PORT datad (1003:1003:1003) (1008:1008:1008)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (216:216:216) (266:266:266)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (670:670:670) (716:716:716)) + (PORT datad (570:570:570) (590:590:590)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15425,45 +14278,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (INSTANCE z80_\|execute_\|pc_inc_hold\~43) (DELAY (ABSOLUTE - (PORT dataa (1188:1188:1188) (1225:1225:1225)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (631:631:631) (645:645:645)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1370:1370:1370) (1444:1444:1444)) - (PORT datab (239:239:239) (284:284:284)) - (PORT datac (2356:2356:2356) (2436:2436:2436)) - (PORT datad (1862:1862:1862) (1982:1982:1982)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (776:776:776)) - (PORT datab (1153:1153:1153) (1226:1226:1226)) - (PORT datac (1964:1964:1964) (2070:2070:2070)) - (PORT datad (726:726:726) (727:727:727)) + (PORT dataa (1409:1409:1409) (1454:1454:1454)) + (PORT datab (666:666:666) (697:697:697)) + (PORT datac (1989:1989:1989) (2085:2085:2085)) + (PORT datad (1246:1246:1246) (1294:1294:1294)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -15476,12 +14297,92 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) (DELAY (ABSOLUTE - (PORT dataa (1117:1117:1117) (1155:1155:1155)) - (PORT datab (883:883:883) (950:950:950)) - (PORT datac (1298:1298:1298) (1329:1329:1329)) - (PORT datad (826:826:826) (860:860:860)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (635:635:635) (682:682:682)) + (PORT datad (190:190:190) (223:223:223)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (421:421:421)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (637:637:637) (672:672:672)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (722:722:722)) + (PORT datab (699:699:699) (766:766:766)) + (PORT datac (639:639:639) (671:671:671)) + (PORT datad (1153:1153:1153) (1224:1224:1224)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1764:1764:1764)) + (PORT datab (1067:1067:1067) (1136:1136:1136)) + (PORT datac (612:612:612) (631:631:631)) + (PORT datad (973:973:973) (1058:1058:1058)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~39) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (264:264:264)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (623:623:623) (647:647:647)) + (PORT datad (565:565:565) (585:585:585)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~47) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (422:422:422)) + (PORT datab (212:212:212) (257:257:257)) + (PORT datac (620:620:620) (677:677:677)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15492,11 +14393,41 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (839:839:839) (841:841:841)) - (PORT datac (816:816:816) (848:848:848)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (881:881:881) (895:895:895)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (DELAY + (ABSOLUTE + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (636:636:636) (661:661:661)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (341:341:341) (376:376:376)) + (PORT datac (639:639:639) (674:674:674)) + (PORT datad (182:182:182) (213:213:213)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -15508,130 +14439,10 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (627:627:627) (644:644:644)) - (PORT datac (816:816:816) (843:843:843)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1309:1309:1309)) - (PORT datac (1245:1245:1245) (1243:1243:1243)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1021:1021:1021) (1037:1037:1037)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1882:1882:1882) (1962:1962:1962)) - (PORT datab (211:211:211) (255:255:255)) - (PORT datac (803:803:803) (846:846:846)) - (PORT datad (1265:1265:1265) (1277:1277:1277)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) - (DELAY - (ABSOLUTE - (PORT datab (820:820:820) (849:849:849)) - (PORT datad (1040:1040:1040) (1099:1099:1099)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (739:739:739)) - (PORT datab (1954:1954:1954) (2044:2044:2044)) - (PORT datac (799:799:799) (807:807:807)) - (PORT datad (1413:1413:1413) (1429:1429:1429)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1640:1640:1640) (1654:1654:1654)) - (PORT datab (1037:1037:1037) (1110:1110:1110)) - (PORT datac (347:347:347) (373:373:373)) - (PORT datad (921:921:921) (1022:1022:1022)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1360:1360:1360) (1425:1425:1425)) - (PORT datab (540:540:540) (561:561:561)) - (PORT datac (1156:1156:1156) (1231:1231:1231)) - (PORT datad (777:777:777) (800:800:800)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1285:1285:1285)) - (PORT datab (546:546:546) (574:574:574)) - (PORT datac (1293:1293:1293) (1341:1341:1341)) - (PORT datad (549:549:549) (563:563:563)) + (PORT dataa (676:676:676) (725:725:725)) + (PORT datab (911:911:911) (985:985:985)) + (PORT datac (1190:1190:1190) (1272:1272:1272)) + (PORT datad (188:188:188) (220:220:220)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -15641,111 +14452,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~54) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) (DELAY (ABSOLUTE - (PORT dataa (1181:1181:1181) (1204:1204:1204)) - (PORT datab (2164:2164:2164) (2257:2257:2257)) - (PORT datac (841:841:841) (881:881:881)) - (PORT datad (908:908:908) (981:981:981)) + (PORT dataa (868:868:868) (915:915:915)) + (PORT datab (682:682:682) (741:741:741)) + (PORT datac (965:965:965) (1027:1027:1027)) + (PORT datad (621:621:621) (668:668:668)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (684:684:684) (749:749:749)) + (PORT datac (972:972:972) (1033:1033:1033)) + (PORT datad (1668:1668:1668) (1690:1690:1690)) (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1315:1315:1315) (1336:1336:1336)) - (PORT datab (622:622:622) (670:670:670)) - (PORT datac (638:638:638) (664:664:664)) - (PORT datad (1121:1121:1121) (1173:1173:1173)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (1200:1200:1200) (1206:1206:1206)) - (PORT datac (834:834:834) (857:857:857)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1591:1591:1591) (1606:1606:1606)) - (PORT datab (877:877:877) (929:929:929)) - (PORT datac (861:861:861) (866:866:866)) - (PORT datad (1956:1956:1956) (1999:1999:1999)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1796:1796:1796) (1820:1820:1820)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (370:370:370) (412:412:412)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (560:560:560)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (523:523:523) (533:533:533)) - (PORT datad (885:885:885) (923:923:923)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (811:811:811) (847:847:847)) - (PORT datab (646:646:646) (665:665:665)) - (PORT datac (1084:1084:1084) (1128:1128:1128)) - (PORT datad (313:313:313) (333:333:333)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15753,14 +14484,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~39) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) (DELAY (ABSOLUTE - (PORT dataa (827:827:827) (838:838:838)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (534:534:534) (550:550:550)) - (PORT datad (186:186:186) (219:219:219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (340:340:340) (370:370:370)) + (PORT datac (638:638:638) (672:672:672)) + (PORT datad (357:357:357) (377:377:377)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -15769,577 +14500,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~47) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (545:545:545) (556:556:556)) - (PORT datad (598:598:598) (636:636:636)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (1696:1696:1696) (1806:1806:1806)) - (PORT datac (1608:1608:1608) (1655:1655:1655)) - (PORT datad (1487:1487:1487) (1516:1516:1516)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (994:994:994) (1047:1047:1047)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|db\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1697:1697:1697) (1800:1800:1800)) - (PORT datab (1937:1937:1937) (1973:1973:1973)) - (PORT datad (1488:1488:1488) (1516:1516:1516)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (1776:1776:1776) (1895:1895:1895)) - (PORT datac (1053:1053:1053) (1087:1087:1087)) - (PORT datad (1337:1337:1337) (1363:1363:1363)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (995:995:995) (1023:1023:1023)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT datab (1778:1778:1778) (1898:1898:1898)) - (PORT datac (1045:1045:1045) (1060:1060:1060)) - (PORT datad (1336:1336:1336) (1365:1365:1365)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT datab (1783:1783:1783) (1902:1902:1902)) - (PORT datac (1046:1046:1046) (1062:1062:1062)) - (PORT datad (1338:1338:1338) (1359:1359:1359)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (997:997:997) (1022:1022:1022)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT datab (1759:1759:1759) (1876:1876:1876)) - (PORT datac (1057:1057:1057) (1085:1085:1085)) - (PORT datad (1341:1341:1341) (1367:1367:1367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (329:329:329)) - (PORT datab (686:686:686) (717:717:717)) - (PORT datad (657:657:657) (694:694:694)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT datab (1091:1091:1091) (1107:1107:1107)) - (PORT datac (1723:1723:1723) (1842:1842:1842)) - (PORT datad (1341:1341:1341) (1360:1360:1360)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1551:1551:1551)) - (PORT asdata (995:995:995) (1021:1021:1021)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT datab (1088:1088:1088) (1109:1109:1109)) - (PORT datac (1731:1731:1731) (1850:1850:1850)) - (PORT datad (1336:1336:1336) (1365:1365:1365)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (400:400:400)) - (PORT datab (644:644:644) (664:664:664)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT datac (1902:1902:1902) (1994:1994:1994)) - (PORT datad (1021:1021:1021) (1040:1040:1040)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1528:1528:1528)) - (PORT datab (643:643:643) (724:724:724)) - (PORT datac (542:542:542) (566:566:566)) - (PORT datad (1270:1270:1270) (1300:1300:1300)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1011:1011:1011) (1075:1075:1075)) - (PORT datab (871:871:871) (890:890:890)) - (PORT datac (910:910:910) (962:962:962)) - (PORT datad (1141:1141:1141) (1166:1166:1166)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) - (DELAY - (ABSOLUTE - (PORT dataa (1412:1412:1412) (1433:1433:1433)) - (PORT datac (1203:1203:1203) (1332:1332:1332)) - (PORT datad (1325:1325:1325) (1407:1407:1407)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1413:1413:1413) (1428:1428:1428)) - (PORT datab (1397:1397:1397) (1483:1483:1483)) - (PORT datac (1314:1314:1314) (1347:1347:1347)) - (PORT datad (1320:1320:1320) (1382:1382:1382)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (685:685:685)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (872:872:872) (891:891:891)) - (PORT datad (857:857:857) (903:903:903)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (899:899:899)) - (PORT datab (1651:1651:1651) (1702:1702:1702)) - (PORT datac (866:866:866) (915:915:915)) - (PORT datad (1166:1166:1166) (1192:1192:1192)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1309:1309:1309) (1353:1353:1353)) - (PORT datab (1293:1293:1293) (1332:1332:1332)) - (PORT datac (3294:3294:3294) (3391:3391:3391)) - (PORT datad (683:683:683) (741:741:741)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1113:1113:1113)) - (PORT datab (920:920:920) (992:992:992)) - (PORT datad (1034:1034:1034) (1043:1043:1043)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1445:1445:1445) (1568:1568:1568)) - (PORT datab (1071:1071:1071) (1092:1092:1092)) - (PORT datac (1392:1392:1392) (1484:1484:1484)) - (PORT datad (1093:1093:1093) (1146:1146:1146)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (287:287:287)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (902:902:902) (934:934:934)) - (PORT datad (1058:1058:1058) (1090:1090:1090)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT datac (893:893:893) (974:974:974)) - (PORT datad (808:808:808) (814:814:814)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1250:1250:1250) (1341:1341:1341)) - (PORT datab (1685:1685:1685) (1758:1758:1758)) - (PORT datac (875:875:875) (893:893:893)) - (PORT datad (879:879:879) (929:929:929)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1207:1207:1207)) - (PORT datab (1447:1447:1447) (1535:1535:1535)) - (PORT datac (1400:1400:1400) (1504:1504:1504)) - (PORT datad (1166:1166:1166) (1255:1255:1255)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (328:328:328) (352:352:352)) - (PORT datad (931:931:931) (993:993:993)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (405:405:405)) - (PORT datab (540:540:540) (569:569:569)) - (PORT datac (552:552:552) (561:561:561)) - (PORT datad (650:650:650) (714:714:714)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (263:263:263)) - (PORT datab (222:222:222) (269:269:269)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (641:641:641) (662:662:662)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1345:1345:1345)) - (PORT datab (1682:1682:1682) (1762:1762:1762)) - (PORT datac (553:553:553) (578:578:578)) - (PORT datad (1132:1132:1132) (1191:1191:1191)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2256:2256:2256) (2343:2343:2343)) - (PORT datab (2177:2177:2177) (2301:2301:2301)) - (PORT datac (1405:1405:1405) (1455:1455:1455)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1096:1096:1096)) - (PORT datab (1388:1388:1388) (1480:1480:1480)) - (PORT datac (1724:1724:1724) (1821:1821:1821)) - (PORT datad (1700:1700:1700) (1777:1777:1777)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (948:948:948)) - (PORT datab (610:610:610) (654:654:654)) - (PORT datac (789:789:789) (812:812:812)) - (PORT datad (1506:1506:1506) (1605:1605:1605)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1128:1128:1128) (1176:1176:1176)) - (PORT datab (613:613:613) (677:677:677)) - (PORT datac (847:847:847) (883:883:883)) - (PORT datad (585:585:585) (633:633:633)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (953:953:953)) - (PORT datab (906:906:906) (934:934:934)) - (PORT datac (1271:1271:1271) (1286:1286:1286)) - (PORT datad (1262:1262:1262) (1280:1280:1280)) - (IOPATH dataa combout (341:341:341) (319:319:319)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (180:180:180) (207:207:207)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -16348,143 +14514,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (INSTANCE z80_\|execute_\|pc_inc_hold\~42) (DELAY (ABSOLUTE - (PORT dataa (359:359:359) (405:405:405)) - (PORT datab (684:684:684) (753:753:753)) - (PORT datac (552:552:552) (565:565:565)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1332:1332:1332) (1395:1395:1395)) - (PORT datab (881:881:881) (933:933:933)) - (PORT datac (1129:1129:1129) (1197:1197:1197)) - (PORT datad (1332:1332:1332) (1391:1391:1391)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1327:1327:1327) (1390:1390:1390)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (754:754:754) (766:766:766)) - (PORT datad (1330:1330:1330) (1387:1387:1387)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1514:1514:1514) (1568:1568:1568)) - (PORT datab (1498:1498:1498) (1595:1595:1595)) - (PORT datac (1147:1147:1147) (1177:1177:1177)) - (PORT datad (1404:1404:1404) (1426:1426:1426)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (383:383:383)) - (PORT datab (1248:1248:1248) (1338:1338:1338)) - (PORT datac (1162:1162:1162) (1271:1271:1271)) - (PORT datad (1038:1038:1038) (1031:1031:1031)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (925:925:925)) - (PORT datab (629:629:629) (665:665:665)) - (PORT datac (345:345:345) (377:377:377)) + (PORT datab (652:652:652) (687:687:687)) + (PORT datac (339:339:339) (370:370:370)) (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1011:1011:1011) (1017:1017:1017)) - (PORT datad (612:612:612) (665:665:665)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (999:999:999)) - (PORT datab (227:227:227) (269:269:269)) - (PORT datac (978:978:978) (1031:1031:1031)) - (PORT datad (640:640:640) (661:661:661)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (287:287:287)) - (PORT datab (936:936:936) (967:967:967)) - (PORT datac (187:187:187) (225:225:225)) - (PORT datad (186:186:186) (217:217:217)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16492,31 +14528,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal72\~2) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) (DELAY (ABSOLUTE - (PORT dataa (1000:1000:1000) (1085:1085:1085)) - (PORT datab (1001:1001:1001) (1073:1073:1073)) - (PORT datac (2236:2236:2236) (2302:2302:2302)) - (PORT datad (581:581:581) (621:621:621)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1117:1117:1117)) - (PORT datab (2183:2183:2183) (2322:2322:2322)) - (PORT datac (576:576:576) (621:621:621)) - (PORT datad (584:584:584) (612:612:612)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (1017:1017:1017) (1099:1099:1099)) + (PORT datab (1086:1086:1086) (1123:1123:1123)) + (PORT datac (1171:1171:1171) (1232:1232:1232)) + (PORT datad (1497:1497:1497) (1611:1611:1611)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16524,31 +14544,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (INSTANCE z80_\|execute_\|pc_inc_hold\~41) (DELAY (ABSOLUTE - (PORT dataa (1000:1000:1000) (1084:1084:1084)) - (PORT datab (999:999:999) (1067:1067:1067)) - (PORT datac (2234:2234:2234) (2302:2302:2302)) - (PORT datad (583:583:583) (619:619:619)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (227:227:227) (279:279:279)) + (PORT datab (627:627:627) (674:674:674)) + (PORT datac (208:208:208) (246:246:246)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~2) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) (DELAY (ABSOLUTE - (PORT dataa (1232:1232:1232) (1267:1267:1267)) - (PORT datab (1163:1163:1163) (1189:1189:1189)) - (PORT datac (864:864:864) (912:912:912)) - (PORT datad (1067:1067:1067) (1072:1072:1072)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (355:355:355) (494:494:494)) + (PORT datab (902:902:902) (935:935:935)) + (PORT datac (1178:1178:1178) (1261:1261:1261)) + (PORT datad (273:273:273) (355:355:355)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1166:1166:1166)) + (PORT datab (227:227:227) (270:270:270)) + (PORT datac (194:194:194) (242:242:242)) + (PORT datad (872:872:872) (923:923:923)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (1443:1443:1443) (1505:1505:1505)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1642:1642:1642) (1712:1712:1712)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16556,47 +14608,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~3) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) (DELAY (ABSOLUTE - (PORT dataa (1124:1124:1124) (1134:1134:1134)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (1006:1006:1006) (1002:1002:1002)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (661:661:661)) - (PORT datab (214:214:214) (257:257:257)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (1448:1448:1448) (1437:1437:1437)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (824:824:824)) - (PORT datab (645:645:645) (698:698:698)) - (PORT datac (863:863:863) (904:904:904)) - (PORT datad (643:643:643) (665:665:665)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT dataa (1110:1110:1110) (1166:1166:1166)) + (PORT datab (235:235:235) (278:278:278)) + (PORT datac (195:195:195) (241:241:241)) + (PORT datad (596:596:596) (630:630:630)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16604,15 +14624,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (888:888:888)) + (PORT datab (1133:1133:1133) (1145:1145:1145)) + (PORT datac (343:343:343) (372:372:372)) + (PORT datad (854:854:854) (886:886:886)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1221:1221:1221)) + (PORT datab (375:375:375) (398:398:398)) + (PORT datac (308:308:308) (325:325:325)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) (DELAY (ABSOLUTE (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (644:644:644) (687:687:687)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (626:626:626) (665:665:665)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (330:330:330) (348:348:348)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (715:715:715)) + (PORT datab (410:410:410) (440:440:440)) + (PORT datac (1131:1131:1131) (1156:1156:1156)) + (PORT datad (854:854:854) (887:887:887)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (719:719:719)) + (PORT datab (946:946:946) (985:985:985)) + (PORT datac (1123:1123:1123) (1165:1165:1165)) + (PORT datad (1721:1721:1721) (1778:1778:1778)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (395:395:395)) + (PORT datab (1129:1129:1129) (1184:1184:1184)) + (PORT datac (1040:1040:1040) (1054:1054:1054)) + (PORT datad (1204:1204:1204) (1229:1229:1229)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16620,77 +14720,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) (DELAY (ABSOLUTE - (PORT dataa (1412:1412:1412) (1431:1431:1431)) - (PORT datab (1345:1345:1345) (1422:1422:1422)) - (PORT datac (1567:1567:1567) (1628:1628:1628)) - (PORT datad (1325:1325:1325) (1407:1407:1407)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (701:701:701)) - (PORT datab (224:224:224) (272:272:272)) - (PORT datac (318:318:318) (349:349:349)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (396:396:396)) - (PORT datab (870:870:870) (878:878:878)) - (PORT datac (562:562:562) (572:572:572)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1413:1413:1413)) - (PORT datab (1157:1157:1157) (1246:1246:1246)) - (PORT datac (1129:1129:1129) (1208:1208:1208)) - (PORT datad (1170:1170:1170) (1285:1285:1285)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (247:247:247) (289:289:289)) - (PORT datac (1495:1495:1495) (1558:1558:1558)) - (PORT datad (539:539:539) (556:556:556)) + (PORT dataa (657:657:657) (717:717:717)) + (PORT datab (921:921:921) (959:959:959)) + (PORT datac (913:913:913) (949:949:949)) + (PORT datad (313:313:313) (331:331:331)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -16700,29 +14736,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) (DELAY (ABSOLUTE - (PORT dataa (1591:1591:1591) (1590:1590:1590)) - (PORT datab (638:638:638) (662:662:662)) - (PORT datac (827:827:827) (838:838:838)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (835:835:835)) - (PORT datab (854:854:854) (867:867:867)) - (PORT datac (1101:1101:1101) (1119:1119:1119)) - (PORT datad (516:516:516) (517:517:517)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (902:902:902) (981:981:981)) + (PORT datab (893:893:893) (932:932:932)) + (PORT datac (1434:1434:1434) (1470:1470:1470)) + (PORT datad (843:843:843) (890:890:890)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16730,79 +14752,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) (DELAY (ABSOLUTE - (PORT dataa (220:220:220) (264:264:264)) - (PORT datab (218:218:218) (258:258:258)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (932:932:932)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (830:830:830) (841:841:841)) - (PORT datad (858:858:858) (869:869:869)) + (PORT dataa (1466:1466:1466) (1512:1512:1512)) + (PORT datab (915:915:915) (968:968:968)) + (PORT datac (321:321:321) (356:356:356)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1116:1116:1116)) - (PORT datab (1112:1112:1112) (1172:1172:1172)) - (PORT datac (800:800:800) (828:828:828)) - (PORT datad (853:853:853) (887:887:887)) - (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (909:909:909)) - (PORT datab (1136:1136:1136) (1150:1150:1150)) - (PORT datac (1677:1677:1677) (1684:1684:1684)) - (PORT datad (1310:1310:1310) (1340:1340:1340)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (397:397:397) (421:421:421)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (1097:1097:1097) (1119:1119:1119)) - (PORT datad (1590:1590:1590) (1617:1617:1617)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16810,93 +14768,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) (DELAY (ABSOLUTE - (PORT dataa (589:589:589) (608:608:608)) - (PORT datab (253:253:253) (304:304:304)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (614:614:614)) - (PORT datab (221:221:221) (261:261:261)) + (PORT dataa (227:227:227) (280:280:280)) + (PORT datab (200:200:200) (239:239:239)) (PORT datac (170:170:170) (202:202:202)) - (PORT datad (811:811:811) (858:858:858)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (921:921:921)) - (PORT datab (2177:2177:2177) (2304:2304:2304)) - (PORT datac (1641:1641:1641) (1700:1700:1700)) - (PORT datad (863:863:863) (895:895:895)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (709:709:709)) - (PORT datab (2392:2392:2392) (2493:2493:2493)) - (PORT datac (1119:1119:1119) (1174:1174:1174)) - (PORT datad (644:644:644) (666:666:666)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (385:385:385)) - (PORT datab (375:375:375) (413:413:413)) - (PORT datac (603:603:603) (634:634:634)) - (PORT datad (807:807:807) (820:820:820)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (900:900:900)) - (PORT datab (585:585:585) (593:593:593)) - (PORT datac (883:883:883) (924:924:924)) - (PORT datad (822:822:822) (856:856:856)) + (PORT datad (588:588:588) (601:601:601)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -16906,93 +14784,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) (DELAY (ABSOLUTE - (PORT dataa (834:834:834) (856:856:856)) - (PORT datab (969:969:969) (1033:1033:1033)) - (PORT datac (889:889:889) (971:971:971)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (401:401:401)) - (PORT datab (874:874:874) (925:925:925)) - (PORT datac (553:553:553) (565:565:565)) - (PORT datad (612:612:612) (655:655:655)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (266:266:266)) - (PORT datab (223:223:223) (268:268:268)) - (PORT datac (786:786:786) (817:817:817)) - (PORT datad (602:602:602) (638:638:638)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (687:687:687)) - (PORT datab (691:691:691) (713:713:713)) - (PORT datac (200:200:200) (235:235:235)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) - (DELAY - (ABSOLUTE - (PORT dataa (2086:2086:2086) (2187:2187:2187)) - (PORT datab (359:359:359) (392:392:392)) - (PORT datac (1493:1493:1493) (1579:1579:1579)) - (PORT datad (645:645:645) (680:680:680)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (1188:1188:1188) (1234:1234:1234)) + (PORT datab (1144:1144:1144) (1214:1214:1214)) + (PORT datac (364:364:364) (396:396:396)) + (PORT datad (1141:1141:1141) (1188:1188:1188)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) (DELAY (ABSOLUTE - (PORT dataa (1656:1656:1656) (1755:1755:1755)) - (PORT datab (1175:1175:1175) (1283:1283:1283)) - (PORT datac (833:833:833) (859:859:859)) - (PORT datad (1180:1180:1180) (1288:1288:1288)) + (PORT dataa (1122:1122:1122) (1132:1132:1132)) + (PORT datab (1153:1153:1153) (1193:1193:1193)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (987:987:987)) + (PORT datab (921:921:921) (959:959:959)) + (PORT datac (635:635:635) (676:676:676)) + (PORT datad (1543:1543:1543) (1626:1626:1626)) (IOPATH dataa combout (341:341:341) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -17002,672 +14830,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) (DELAY (ABSOLUTE - (PORT dataa (654:654:654) (677:677:677)) - (PORT datab (1279:1279:1279) (1345:1345:1345)) - (PORT datac (1763:1763:1763) (1820:1820:1820)) - (PORT datad (1084:1084:1084) (1130:1130:1130)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1795:1795:1795) (1856:1856:1856)) - (PORT datab (1447:1447:1447) (1589:1589:1589)) - (PORT datac (1335:1335:1335) (1413:1413:1413)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1176:1176:1176)) - (PORT datab (1279:1279:1279) (1342:1342:1342)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1268:1268:1268) (1316:1316:1316)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (641:641:641)) - (PORT datab (949:949:949) (991:991:991)) - (PORT datac (518:518:518) (545:545:545)) - (PORT datad (1606:1606:1606) (1658:1658:1658)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (648:648:648)) - (PORT datab (1169:1169:1169) (1211:1211:1211)) - (PORT datac (1263:1263:1263) (1299:1299:1299)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (645:645:645)) - (PORT datab (1064:1064:1064) (1104:1104:1104)) - (PORT datac (578:578:578) (611:611:611)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1657:1657:1657) (1758:1758:1758)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (499:499:499) (509:509:509)) - (PORT datad (1160:1160:1160) (1211:1211:1211)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1087:1087:1087)) - (PORT datab (1091:1091:1091) (1095:1095:1095)) - (PORT datac (832:832:832) (857:857:857)) - (PORT datad (872:872:872) (911:911:911)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (391:391:391)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (186:186:186) (227:227:227)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1145:1145:1145)) - (PORT datab (1233:1233:1233) (1305:1305:1305)) - (PORT datac (846:846:846) (863:863:863)) - (PORT datad (1062:1062:1062) (1056:1056:1056)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datac (982:982:982) (1011:1011:1011)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (957:957:957)) - (PORT datab (203:203:203) (244:244:244)) - (PORT datac (1134:1134:1134) (1181:1181:1181)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (915:915:915)) - (PORT datab (826:826:826) (838:838:838)) - (PORT datac (823:823:823) (835:835:835)) - (PORT datad (178:178:178) (207:207:207)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (939:939:939)) - (PORT datab (608:608:608) (664:664:664)) - (PORT datac (615:615:615) (622:622:622)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1432:1432:1432)) - (PORT datab (930:930:930) (980:980:980)) - (PORT datac (1089:1089:1089) (1144:1144:1144)) - (PORT datad (1381:1381:1381) (1460:1460:1460)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (938:938:938)) - (PORT datab (893:893:893) (937:937:937)) - (PORT datac (1244:1244:1244) (1266:1266:1266)) - (PORT datad (1083:1083:1083) (1130:1130:1130)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1099:1099:1099) (1132:1132:1132)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (850:850:850) (907:907:907)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (907:907:907)) - (PORT datab (849:849:849) (877:877:877)) - (PORT datac (1082:1082:1082) (1084:1084:1084)) - (PORT datad (325:325:325) (347:347:347)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (686:686:686) (728:728:728)) - (PORT datac (804:804:804) (841:841:841)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (671:671:671)) - (PORT datab (270:270:270) (355:355:355)) - (PORT datac (250:250:250) (333:333:333)) - (PORT datad (245:245:245) (317:317:317)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (950:950:950)) - (PORT datab (1212:1212:1212) (1290:1290:1290)) - (PORT datac (1040:1040:1040) (1051:1051:1051)) - (PORT datad (982:982:982) (1007:1007:1007)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1147:1147:1147) (1197:1197:1197)) - (PORT datac (1043:1043:1043) (1049:1049:1049)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (576:576:576)) - (PORT datab (648:648:648) (672:672:672)) - (PORT datac (911:911:911) (963:963:963)) - (PORT datad (772:772:772) (788:788:788)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (844:844:844)) - (PORT datab (829:829:829) (857:857:857)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1177:1177:1177)) - (PORT datab (1878:1878:1878) (1947:1947:1947)) - (PORT datac (1230:1230:1230) (1236:1236:1236)) - (PORT datad (1653:1653:1653) (1642:1642:1642)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (268:268:268)) - (PORT datab (1536:1536:1536) (1562:1562:1562)) - (PORT datac (558:558:558) (587:587:587)) - (PORT datad (1302:1302:1302) (1340:1340:1340)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (898:898:898)) - (PORT datab (604:604:604) (609:609:609)) - (PORT datac (550:550:550) (573:573:573)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (985:985:985) (997:997:997)) - (PORT datad (860:860:860) (877:877:877)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (731:731:731) (752:752:752)) - (PORT datab (1095:1095:1095) (1100:1100:1100)) - (PORT datac (1129:1129:1129) (1193:1193:1193)) - (PORT datad (837:837:837) (864:864:864)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1504:1504:1504) (1527:1527:1527)) - (PORT datab (1695:1695:1695) (1739:1739:1739)) - (PORT datac (1129:1129:1129) (1194:1194:1194)) - (PORT datad (846:846:846) (896:896:896)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1507:1507:1507) (1533:1533:1533)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (754:754:754) (764:764:764)) - (PORT datad (1667:1667:1667) (1700:1700:1700)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (974:974:974)) - (PORT datab (1446:1446:1446) (1588:1588:1588)) - (PORT datac (1759:1759:1759) (1881:1881:1881)) - (PORT datad (1106:1106:1106) (1187:1187:1187)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (316:316:316) (335:335:335)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (921:921:921)) - (PORT datab (1088:1088:1088) (1149:1149:1149)) - (PORT datac (1107:1107:1107) (1163:1163:1163)) - (PORT datad (1572:1572:1572) (1620:1620:1620)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (860:860:860)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (193:193:193) (226:226:226)) + (PORT dataa (457:457:457) (498:498:498)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (805:805:805) (826:826:826)) (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1316:1316:1316) (1362:1362:1362)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1263:1263:1263) (1304:1304:1304)) - (PORT datad (832:832:832) (856:856:856)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (969:969:969)) - (PORT datab (728:728:728) (814:814:814)) - (PORT datac (663:663:663) (736:736:736)) - (PORT datad (1060:1060:1060) (1070:1070:1070)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT datab (1293:1293:1293) (1323:1323:1323)) - (PORT datac (636:636:636) (678:678:678)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (653:653:653)) - (PORT datab (1332:1332:1332) (1373:1373:1373)) - (PORT datac (1033:1033:1033) (1061:1061:1061)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2034:2034:2034) (2049:2049:2049)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~4) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (695:695:695) (780:780:780)) - (PORT datad (856:856:856) (905:905:905)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (707:707:707)) - (PORT datab (914:914:914) (952:952:952)) - (PORT datac (1086:1086:1086) (1099:1099:1099)) - (PORT datad (895:895:895) (949:949:949)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT dataa (1333:1333:1333) (1437:1437:1437)) + (PORT datab (1163:1163:1163) (1169:1169:1169)) + (PORT datac (1430:1430:1430) (1469:1469:1469)) + (PORT datad (844:844:844) (894:894:894)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -17676,119 +14862,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~1) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) (DELAY (ABSOLUTE - (PORT dataa (848:848:848) (893:893:893)) - (PORT datab (1126:1126:1126) (1167:1167:1167)) - (PORT datac (576:576:576) (586:586:586)) - (PORT datad (884:884:884) (949:949:949)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1172:1172:1172)) - (PORT datac (805:805:805) (846:846:846)) - (PORT datad (819:819:819) (846:846:846)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (732:732:732) (834:834:834)) - (PORT datab (206:206:206) (249:249:249)) - (PORT datac (1365:1365:1365) (1390:1390:1390)) - (PORT datad (701:701:701) (778:778:778)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1657:1657:1657) (1756:1756:1756)) - (PORT datab (1146:1146:1146) (1224:1224:1224)) - (PORT datac (989:989:989) (1008:1008:1008)) - (PORT datad (1180:1180:1180) (1289:1289:1289)) + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (828:828:828) (830:830:830)) + (PORT datac (314:314:314) (333:333:333)) + (PORT datad (172:172:172) (197:197:197)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) - (DELAY - (ABSOLUTE - (PORT datab (632:632:632) (670:670:670)) - (PORT datac (613:613:613) (645:645:645)) - (PORT datad (873:873:873) (922:922:922)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (1282:1282:1282) (1286:1286:1286)) - (PORT datac (617:617:617) (675:675:675)) - (PORT datad (849:849:849) (894:894:894)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT datac (323:323:323) (347:347:347)) - (PORT datad (570:570:570) (595:595:595)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -17796,71 +14878,62 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~25) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) (DELAY (ABSOLUTE - (PORT dataa (570:570:570) (606:606:606)) - (PORT datad (312:312:312) (334:334:334)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (907:907:907) (937:937:937)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (590:590:590) (602:602:602)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (879:879:879) (889:889:889)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~0) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (335:335:335)) - (PORT datab (643:643:643) (660:660:660)) - (PORT datad (890:890:890) (955:955:955)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1157:1157:1157) (1220:1220:1220)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (563:563:563) (566:566:566)) + (PORT datad (559:559:559) (582:582:582)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1096:1096:1096) (1139:1139:1139)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (1061:1061:1061) (1099:1099:1099)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~1) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) (DELAY (ABSOLUTE - (PORT datab (377:377:377) (400:400:400)) - (PORT datac (215:215:215) (291:291:291)) - (PORT datad (421:421:421) (450:450:450)) + (PORT dataa (1618:1618:1618) (1736:1736:1736)) + (PORT datab (867:867:867) (905:905:905)) + (PORT datac (2517:2517:2517) (2622:2622:2622)) + (PORT datad (1493:1493:1493) (1607:1607:1607)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -17869,25 +14942,155 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) (DELAY (ABSOLUTE - (PORT datac (1491:1491:1491) (1572:1572:1572)) - (PORT datad (617:617:617) (665:665:665)) + (PORT dataa (592:592:592) (611:611:611)) + (PORT datab (580:580:580) (593:593:593)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1133:1133:1133) (1184:1184:1184)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~40) + (DELAY + (ABSOLUTE + (PORT datab (652:652:652) (686:686:686)) + (PORT datac (338:338:338) (369:369:369)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (277:277:277)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (1058:1058:1058) (1099:1099:1099)) + (PORT datad (1134:1134:1134) (1161:1161:1161)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1225:1225:1225)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (551:551:551) (564:564:564)) + (PORT datad (399:399:399) (430:430:430)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (169:169:169) (201:201:201)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1138:1138:1138)) + (PORT datab (1105:1105:1105) (1122:1122:1122)) + (PORT datac (1065:1065:1065) (1088:1088:1088)) + (PORT datad (1172:1172:1172) (1217:1217:1217)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (700:700:700) (784:784:784)) + (PORT datad (365:365:365) (386:386:386)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (958:958:958) (1001:1001:1001)) + (PORT datac (681:681:681) (720:720:720)) + (PORT datad (339:339:339) (361:361:361)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[0\]) (DELAY (ABSOLUTE - (PORT clk (1523:1523:1523) (1544:1544:1544)) + (PORT datac (1006:1006:1006) (1012:1012:1012)) + (PORT datad (924:924:924) (943:943:943)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (179:179:179) (207:207:207)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1547:1547:1547)) - (PORT ena (2452:2452:2452) (2480:2480:2480)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2096:2096:2096) (2133:2133:2133)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -17899,14 +15102,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) (DELAY (ABSOLUTE - (PORT dataa (645:645:645) (720:720:720)) - (PORT datab (653:653:653) (676:676:676)) - (PORT datac (1106:1106:1106) (1167:1167:1167)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (1158:1158:1158) (1184:1184:1184)) + (PORT datab (989:989:989) (1022:1022:1022)) + (PORT datac (696:696:696) (778:778:778)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (985:985:985) (1033:1033:1033)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (396:396:396)) + (PORT datab (697:697:697) (726:726:726)) + (PORT datad (1194:1194:1194) (1231:1231:1231)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (740:740:740) (774:774:774)) + (PORT datac (217:217:217) (294:294:294)) + (PORT datad (608:608:608) (657:657:657)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -17915,14 +15179,210 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~3) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (644:644:644) (685:685:685)) - (PORT datac (1659:1659:1659) (1785:1785:1785)) - (PORT datad (376:376:376) (395:395:395)) - (IOPATH dataa combout (303:303:303) (308:308:308)) + (PORT dataa (845:845:845) (905:905:905)) + (PORT datab (402:402:402) (425:425:425)) + (PORT datac (194:194:194) (227:227:227)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (244:244:244)) + (PORT datab (959:959:959) (1000:1000:1000)) + (PORT datac (683:683:683) (721:721:721)) + (PORT datad (341:341:341) (359:359:359)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (421:421:421)) + (PORT datad (345:345:345) (371:371:371)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT asdata (537:537:537) (568:568:568)) + (PORT clrn (1597:1597:1597) (1572:1572:1572)) + (PORT ena (2143:2143:2143) (2210:2210:2210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1069:1069:1069)) + (PORT datab (1154:1154:1154) (1178:1178:1178)) + (PORT datac (812:812:812) (866:866:866)) + (PORT datad (359:359:359) (383:383:383)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (443:443:443)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (236:236:236) (311:311:311)) + (PORT datad (327:327:327) (348:348:348)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (758:758:758)) + (PORT datab (962:962:962) (1001:1001:1001)) + (PORT datac (617:617:617) (670:670:670)) + (PORT datad (532:532:532) (544:544:544)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (579:579:579)) + (PORT datad (214:214:214) (247:247:247)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (220:220:220)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1597:1597:1597) (1572:1572:1572)) + (PORT ena (2146:2146:2146) (2210:2210:2210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (424:424:424)) + (PORT datab (1154:1154:1154) (1182:1182:1182)) + (PORT datac (966:966:966) (1033:1033:1033)) + (PORT datad (394:394:394) (449:449:449)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (441:441:441)) + (PORT datab (1103:1103:1103) (1121:1121:1121)) + (PORT datac (1068:1068:1068) (1079:1079:1079)) + (PORT datad (1177:1177:1177) (1222:1222:1222)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1182:1182:1182)) + (PORT datab (983:983:983) (1021:1021:1021)) + (PORT datac (960:960:960) (1025:1025:1025)) + (PORT datad (1127:1127:1127) (1138:1138:1138)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -17930,13 +15390,59 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1261:1261:1261) (1322:1322:1322)) - (PORT ena (841:841:841) (846:846:846)) + (PORT dataa (846:846:846) (907:907:907)) + (PORT datab (1376:1376:1376) (1400:1400:1400)) + (PORT datac (695:695:695) (778:778:778)) + (PORT datad (369:369:369) (389:389:389)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (331:331:331) (357:357:357)) + (PORT datad (244:244:244) (316:316:316)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1394:1394:1394) (1425:1425:1425)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1396:1396:1396) (1427:1427:1427)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -17947,27 +15453,53 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~12) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) (DELAY (ABSOLUTE - (PORT dataa (1209:1209:1209) (1282:1282:1282)) - (PORT datab (1379:1379:1379) (1450:1450:1450)) - (PORT datad (1863:1863:1863) (1920:1920:1920)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (413:413:413) (478:478:478)) + (PORT datab (593:593:593) (633:633:633)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1267:1267:1267) (1292:1292:1292)) - (PORT ena (942:942:942) (926:926:926)) + (PORT datad (815:815:815) (857:857:857)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1407:1407:1407) (1382:1382:1382)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1165:1165:1165) (1197:1197:1197)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -17977,12 +15509,27 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1268:1268:1268) (1294:1294:1294)) + (PORT dataa (617:617:617) (678:678:678)) + (PORT datab (842:842:842) (870:870:870)) + (PORT datad (643:643:643) (672:672:672)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1201:1201:1201) (1243:1243:1243)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -17993,14 +15540,169 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT datab (1779:1779:1779) (1898:1898:1898)) - (PORT datac (1045:1045:1045) (1061:1061:1061)) - (PORT datad (1611:1611:1611) (1668:1668:1668)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1200:1200:1200) (1247:1247:1247)) + (PORT ena (1220:1220:1220) (1214:1214:1214)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (705:705:705)) + (PORT datab (245:245:245) (328:328:328)) + (PORT datad (369:369:369) (400:400:400)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (812:812:812) (855:855:855)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1505:1505:1505) (1518:1518:1518)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1168:1168:1168) (1200:1200:1200)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (963:963:963)) + (PORT datab (606:606:606) (617:617:617)) + (PORT datac (548:548:548) (570:570:570)) + (PORT datad (1519:1519:1519) (1633:1633:1633)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (1020:1020:1020)) + (PORT datab (580:580:580) (595:595:595)) + (PORT datac (1000:1000:1000) (1021:1021:1021)) + (PORT datad (861:861:861) (896:896:896)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (681:681:681) (737:737:737)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (562:562:562)) + (PORT datab (612:612:612) (638:638:638)) + (PORT datac (854:854:854) (888:888:888)) + (PORT datad (607:607:607) (635:635:635)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (687:687:687)) + (PORT datab (643:643:643) (681:681:681)) + (PORT datac (1161:1161:1161) (1210:1210:1210)) + (PORT datad (581:581:581) (616:616:616)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (603:603:603) (634:634:634)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18008,43 +15710,54 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~9) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) (DELAY (ABSOLUTE - (PORT dataa (422:422:422) (475:475:475)) - (PORT datab (241:241:241) (324:324:324)) - (PORT datad (397:397:397) (430:430:430)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datab (1437:1437:1437) (1505:1505:1505)) + (PORT datac (1211:1211:1211) (1273:1273:1273)) + (PORT datad (849:849:849) (886:886:886)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT datab (1435:1435:1435) (1506:1506:1506)) + (PORT datac (1214:1214:1214) (1277:1277:1277)) + (PORT datad (841:841:841) (870:870:870)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT datab (1431:1431:1431) (1499:1499:1499)) + (PORT datac (1202:1202:1202) (1265:1265:1265)) + (PORT datad (842:842:842) (868:868:868)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1316:1316:1316) (1355:1355:1355)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1316:1316:1316) (1355:1355:1355)) - (PORT ena (979:979:979) (971:971:971)) + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1009:1009:1009) (1065:1065:1065)) + (PORT ena (990:990:990) (994:994:994)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18055,12 +15768,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~10) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) (DELAY (ABSOLUTE - (PORT dataa (422:422:422) (485:485:485)) - (PORT datab (426:426:426) (467:467:467)) - (PORT datad (215:215:215) (283:283:283)) + (PORT datab (1431:1431:1431) (1500:1500:1500)) + (PORT datac (1204:1204:1204) (1267:1267:1267)) + (PORT datad (851:851:851) (887:887:887)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1012:1012:1012) (1067:1067:1067)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (523:523:523)) + (PORT datab (490:490:490) (541:541:541)) + (PORT datad (217:217:217) (285:285:285)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -18069,29 +15812,41 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1513:1513:1513) (1542:1542:1542)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT datab (1436:1436:1436) (1501:1501:1501)) + (PORT datac (1209:1209:1209) (1271:1271:1271)) + (PORT datad (1072:1072:1072) (1103:1103:1103)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT datab (1436:1436:1436) (1506:1506:1506)) + (PORT datac (1213:1213:1213) (1276:1276:1276)) + (PORT datad (987:987:987) (1036:1036:1036)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1516:1516:1516) (1546:1546:1546)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1181:1181:1181) (1200:1200:1200)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18102,12 +15857,192 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~11) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) (DELAY (ABSOLUTE - (PORT dataa (383:383:383) (461:461:461)) - (PORT datab (660:660:660) (683:683:683)) - (PORT datad (628:628:628) (649:649:649)) + (PORT datab (1437:1437:1437) (1502:1502:1502)) + (PORT datac (1212:1212:1212) (1275:1275:1275)) + (PORT datad (1074:1074:1074) (1101:1101:1101)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1183:1183:1183) (1203:1203:1203)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT datab (1438:1438:1438) (1503:1503:1503)) + (PORT datac (1218:1218:1218) (1279:1279:1279)) + (PORT datad (985:985:985) (1032:1032:1032)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (988:988:988)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datad (882:882:882) (948:948:948)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT datab (1221:1221:1221) (1292:1292:1292)) + (PORT datac (894:894:894) (941:941:941)) + (PORT datad (886:886:886) (945:945:945)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1204:1204:1204) (1243:1243:1243)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (997:997:997)) + (PORT datab (1221:1221:1221) (1285:1285:1285)) + (PORT datad (879:879:879) (935:935:935)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1217:1217:1217)) + (PORT datab (204:204:204) (246:246:246)) + (PORT datac (1821:1821:1821) (1898:1898:1898)) + (PORT datad (203:203:203) (239:239:239)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (899:899:899)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (601:601:601) (662:662:662)) + (PORT datad (870:870:870) (912:912:912)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT dataa (1473:1473:1473) (1527:1527:1527)) + (PORT datac (833:833:833) (838:838:838)) + (PORT datad (1122:1122:1122) (1157:1157:1157)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (981:981:981) (1026:1026:1026)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1527:1527:1527)) + (PORT datac (835:835:835) (838:838:838)) + (PORT datad (1125:1125:1125) (1158:1158:1158)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1099:1099:1099)) + (PORT datab (1166:1166:1166) (1217:1217:1217)) + (PORT datad (239:239:239) (279:279:279)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -18116,13 +16051,37 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT datad (656:656:656) (709:709:709)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (DELAY + (ABSOLUTE + (PORT datab (1122:1122:1122) (1149:1149:1149)) + (PORT datac (1397:1397:1397) (1448:1448:1448)) + (PORT datad (822:822:822) (857:857:857)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) + (PORT ena (790:790:790) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18131,79 +16090,29 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (1196:1196:1196) (1229:1229:1229)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~13) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) (DELAY (ABSOLUTE - (PORT dataa (487:487:487) (523:523:523)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (666:666:666) (690:690:690)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1003:1003:1003) (1039:1039:1039)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1353:1353:1353)) - (PORT datab (1355:1355:1355) (1387:1387:1387)) - (PORT datad (389:389:389) (407:407:407)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (929:929:929) (987:987:987)) + (PORT datab (1220:1220:1220) (1288:1288:1288)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~14) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (332:332:332) (363:363:363)) - (PORT datac (640:640:640) (657:657:657)) - (PORT datad (601:601:601) (615:615:615)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (403:403:403) (454:454:454)) + (PORT datab (944:944:944) (1025:1025:1025)) + (PORT datac (1146:1146:1146) (1186:1186:1186)) + (PORT datad (666:666:666) (686:686:686)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18211,38 +16120,40 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) (DELAY (ABSOLUTE - (PORT datad (1178:1178:1178) (1226:1226:1226)) + (PORT datac (1438:1438:1438) (1484:1484:1484)) + (PORT datad (1123:1123:1123) (1155:1155:1155)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1170:1170:1170) (1265:1265:1265)) + (PORT datab (813:813:813) (832:832:832)) + (PORT datac (1134:1134:1134) (1171:1171:1171)) + (PORT datad (664:664:664) (713:713:713)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1262:1262:1262) (1321:1321:1321)) - (PORT ena (816:816:816) (813:813:813)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1504:1504:1504) (1545:1545:1545)) + (PORT ena (1131:1131:1131) (1098:1098:1098)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18253,12 +16164,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~8) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) (DELAY (ABSOLUTE - (PORT dataa (422:422:422) (483:483:483)) - (PORT datab (406:406:406) (433:433:433)) - (PORT datad (655:655:655) (713:713:713)) + (PORT datab (1121:1121:1121) (1148:1148:1148)) + (PORT datac (1398:1398:1398) (1447:1447:1447)) + (PORT datad (821:821:821) (856:856:856)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (453:453:453)) + (PORT datab (887:887:887) (923:923:923)) + (PORT datad (364:364:364) (388:388:388)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -18268,13 +16193,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~15) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (645:645:645) (696:696:696)) - (PORT datac (581:581:581) (606:606:606)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (408:408:408) (464:464:464)) + (PORT datab (1404:1404:1404) (1437:1437:1437)) + (PORT datac (1139:1139:1139) (1179:1179:1179)) + (PORT datad (663:663:663) (683:683:683)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -18284,13 +16209,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~21) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (634:634:634)) - (PORT datab (1979:1979:1979) (2129:2129:2129)) - (PORT datac (614:614:614) (631:631:631)) - (PORT datad (570:570:570) (584:584:584)) + (PORT dataa (1146:1146:1146) (1180:1180:1180)) + (PORT datab (815:815:815) (833:833:833)) + (PORT datac (1143:1143:1143) (1180:1180:1180)) + (PORT datad (671:671:671) (721:721:721)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -18298,25 +16223,1369 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|im2\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (180:180:180) (208:208:208)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1544:1544:1544)) + (PORT clk (1535:1535:1535) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1570:1570:1570) (1550:1550:1550)) - (PORT ena (1954:1954:1954) (1960:1960:1960)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1782:1782:1782) (1906:1906:1906)) + (PORT datab (973:973:973) (1022:1022:1022)) + (PORT datac (1471:1471:1471) (1489:1489:1489)) + (PORT datad (1978:1978:1978) (2013:2013:2013)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (660:660:660)) + (PORT datab (1249:1249:1249) (1275:1275:1275)) + (PORT datac (1822:1822:1822) (1900:1900:1900)) + (PORT datad (1106:1106:1106) (1134:1134:1134)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (687:687:687)) + (PORT datab (905:905:905) (971:971:971)) + (PORT datac (861:861:861) (888:888:888)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1153:1153:1153) (1178:1178:1178)) + (PORT datad (204:204:204) (241:241:241)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (713:713:713) (766:766:766)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (346:346:346) (370:370:370)) + (PORT datad (1145:1145:1145) (1176:1176:1176)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (DELAY + (ABSOLUTE + (PORT datab (922:922:922) (944:944:944)) + (PORT datac (595:595:595) (615:615:615)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (900:900:900)) + (PORT datac (1144:1144:1144) (1163:1163:1163)) + (PORT datad (832:832:832) (861:861:861)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1506:1506:1506) (1545:1545:1545)) + (PORT ena (1261:1261:1261) (1299:1299:1299)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (899:899:899)) + (PORT datac (1138:1138:1138) (1159:1159:1159)) + (PORT datad (835:835:835) (861:861:861)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1149:1149:1149)) + (PORT datab (1280:1280:1280) (1386:1386:1386)) + (PORT datad (842:842:842) (869:869:869)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (693:693:693)) + (PORT datab (1259:1259:1259) (1346:1346:1346)) + (PORT datac (1146:1146:1146) (1187:1187:1187)) + (PORT datad (374:374:374) (412:412:412)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (990:990:990) (1035:1035:1035)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (462:462:462)) + (PORT datab (1258:1258:1258) (1341:1341:1341)) + (PORT datac (1142:1142:1142) (1186:1186:1186)) + (PORT datad (664:664:664) (686:686:686)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (696:696:696)) + (PORT datab (1255:1255:1255) (1339:1339:1339)) + (PORT datac (1141:1141:1141) (1184:1184:1184)) + (PORT datad (375:375:375) (413:413:413)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (989:989:989) (1035:1035:1035)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (457:457:457)) + (PORT datab (1258:1258:1258) (1344:1344:1344)) + (PORT datac (1146:1146:1146) (1187:1187:1187)) + (PORT datad (666:666:666) (682:682:682)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (485:485:485)) + (PORT datab (1600:1600:1600) (1653:1653:1653)) + (PORT datad (1181:1181:1181) (1221:1221:1221)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (634:634:634)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (787:787:787) (785:785:785)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (653:653:653)) + (PORT datab (336:336:336) (368:368:368)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (626:626:626) (642:642:642)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (988:988:988)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (618:618:618) (661:661:661)) + (PORT datad (787:787:787) (791:791:791)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1064:1064:1064) (1103:1103:1103)) + (PORT datab (836:836:836) (868:868:868)) + (PORT datac (218:218:218) (261:261:261)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (671:671:671)) + (PORT datab (834:834:834) (892:892:892)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (874:874:874) (899:899:899)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1547:1547:1547) (1564:1564:1564)) + (PORT datab (851:851:851) (910:910:910)) + (PORT datac (1130:1130:1130) (1151:1151:1151)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1399:1399:1399)) + (PORT datac (1141:1141:1141) (1164:1164:1164)) + (PORT datad (832:832:832) (866:866:866)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1308:1308:1308) (1303:1303:1303)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1187:1187:1187) (1229:1229:1229)) + (PORT ena (990:990:990) (994:994:994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1186:1186:1186) (1227:1227:1227)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (460:460:460) (523:523:523)) + (PORT datab (492:492:492) (541:541:541)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1950:1950:1950) (1996:1996:1996)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (991:991:991)) + (PORT datab (1222:1222:1222) (1291:1291:1291)) + (PORT datad (879:879:879) (935:935:935)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (545:545:545) (579:579:579)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1716:1716:1716) (1767:1767:1767)) + (PORT ena (1261:1261:1261) (1299:1299:1299)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1151:1151:1151)) + (PORT datab (648:648:648) (728:728:728)) + (PORT datad (845:845:845) (876:876:876)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (2219:2219:2219) (2260:2260:2260)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (881:881:881)) + (PORT datab (1166:1166:1166) (1218:1218:1218)) + (PORT datad (240:240:240) (280:280:280)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1976:1976:1976) (2020:2020:2020)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1977:1977:1977) (2023:2023:2023)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (466:466:466)) + (PORT datab (1593:1593:1593) (1643:1643:1643)) + (PORT datad (1180:1180:1180) (1216:1216:1216)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1715:1715:1715) (1766:1766:1766)) + (PORT ena (1131:1131:1131) (1098:1098:1098)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1611:1611:1611) (1650:1650:1650)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (433:433:433)) + (PORT datab (886:886:886) (923:923:923)) + (PORT datad (859:859:859) (925:925:925)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (632:632:632) (649:649:649)) + (PORT datac (338:338:338) (358:358:358)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (2372:2372:2372) (2423:2423:2423)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (2371:2371:2371) (2423:2423:2423)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (986:986:986)) + (PORT datab (911:911:911) (986:986:986)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (672:672:672)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (596:596:596) (613:613:613)) + (PORT datad (313:313:313) (323:323:323)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (944:944:944)) + (PORT datab (543:543:543) (563:563:563)) + (PORT datac (1049:1049:1049) (1102:1102:1102)) + (PORT datad (1297:1297:1297) (1338:1338:1338)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (911:911:911)) + (PORT datac (1138:1138:1138) (1159:1159:1159)) + (PORT datad (844:844:844) (869:869:869)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (909:909:909)) + (PORT datac (1140:1140:1140) (1164:1164:1164)) + (PORT datad (844:844:844) (871:871:871)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (1391:1391:1391) (1443:1443:1443)) + (PORT ena (935:935:935) (924:924:924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1171:1171:1171) (1195:1195:1195)) + (PORT datab (835:835:835) (855:855:855)) + (PORT datac (1143:1143:1143) (1163:1163:1163)) + (PORT datad (844:844:844) (868:868:868)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (276:276:276)) + (PORT datab (409:409:409) (450:450:450)) + (PORT datad (382:382:382) (419:419:419)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1398:1398:1398)) + (PORT datac (1141:1141:1141) (1165:1165:1165)) + (PORT datad (832:832:832) (866:866:866)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datac (762:762:762) (815:815:815)) + (PORT datad (642:642:642) (666:666:666)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (292:292:292)) + (PORT datab (235:235:235) (277:277:277)) + (PORT datac (1097:1097:1097) (1113:1113:1113)) + (PORT datad (212:212:212) (246:246:246)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (508:508:508)) + (PORT datab (279:279:279) (364:364:364)) + (PORT datac (1332:1332:1332) (1337:1337:1337)) + (PORT datad (184:184:184) (216:216:216)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (951:951:951) (975:975:975)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (951:951:951) (974:974:974)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (978:978:978)) + (PORT datab (914:914:914) (989:989:989)) + (PORT datad (214:214:214) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1393:1393:1393) (1432:1432:1432)) + (PORT ena (990:990:990) (994:994:994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1390:1390:1390) (1429:1429:1429)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (517:517:517)) + (PORT datab (496:496:496) (537:537:537)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1278:1278:1278) (1308:1308:1308)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1278:1278:1278) (1306:1306:1306)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (458:458:458)) + (PORT datab (1599:1599:1599) (1646:1646:1646)) + (PORT datad (1181:1181:1181) (1215:1215:1215)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1228:1228:1228) (1277:1277:1277)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1070:1070:1070)) + (PORT datab (1167:1167:1167) (1216:1216:1216)) + (PORT datad (237:237:237) (277:277:277)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (810:810:810) (862:862:862)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1214:1214:1214) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1259:1259:1259) (1290:1290:1290)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (243:243:243) (289:289:289)) + (PORT datad (875:875:875) (901:901:901)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (689:689:689) (709:709:709)) + (PORT ena (1404:1404:1404) (1382:1382:1382)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1474:1474:1474) (1488:1488:1488)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1072:1072:1072)) + (PORT datab (1270:1270:1270) (1360:1360:1360)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (872:872:872)) + (PORT datab (1030:1030:1030) (1072:1072:1072)) + (PORT datac (803:803:803) (856:856:856)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (969:969:969) (986:986:986)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (986:986:986)) + (PORT datab (1221:1221:1221) (1292:1292:1292)) + (PORT datad (887:887:887) (945:945:945)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (429:429:429)) + (PORT datab (829:829:829) (880:880:880)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (558:558:558) (582:582:582)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (864:864:864)) + (PORT datab (867:867:867) (903:903:903)) + (PORT datac (808:808:808) (862:862:862)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1554:1554:1554)) + (PORT asdata (881:881:881) (888:888:888)) + (PORT ena (940:940:940) (926:926:926)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (288:288:288)) + (PORT datab (905:905:905) (941:941:941)) + (PORT datad (211:211:211) (245:245:245)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (288:288:288)) + (PORT datac (214:214:214) (290:290:290)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1135:1135:1135) (1153:1153:1153)) + (PORT datab (827:827:827) (837:837:837)) + (PORT datac (199:199:199) (234:234:234)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (733:733:733)) + (PORT datac (799:799:799) (817:817:817)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2152:2152:2152) (2220:2220:2220)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -18328,13 +17597,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) (DELAY (ABSOLUTE - (PORT dataa (341:341:341) (458:458:458)) - (PORT datac (1002:1002:1002) (1025:1025:1025)) - (PORT datad (283:283:283) (369:369:369)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (422:422:422) (513:513:513)) + (PORT datab (280:280:280) (369:369:369)) + (PORT datac (1329:1329:1329) (1334:1334:1334)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18342,14 +17613,431 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (456:456:456)) - (PORT datab (349:349:349) (381:381:381)) - (PORT datac (1043:1043:1043) (1054:1054:1054)) - (PORT datad (1085:1085:1085) (1095:1095:1095)) - (IOPATH dataa combout (301:301:301) (299:299:299)) + (PORT datac (248:248:248) (337:337:337)) + (PORT datad (324:324:324) (346:346:346)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (712:712:712) (756:756:756)) + (PORT datac (810:810:810) (842:842:842)) + (PORT datad (578:578:578) (586:586:586)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datab (355:355:355) (385:385:385)) + (PORT datac (880:880:880) (911:911:911)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (554:554:554) (561:561:561)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2096:2096:2096) (2133:2133:2133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (268:268:268) (364:364:364)) + (PORT datab (279:279:279) (374:374:374)) + (PORT datac (1335:1335:1335) (1349:1349:1349)) + (PORT datad (325:325:325) (343:343:343)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1106:1106:1106) (1145:1145:1145)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1107:1107:1107) (1146:1146:1146)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (980:980:980)) + (PORT datab (914:914:914) (982:982:982)) + (PORT datad (216:216:216) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1947:1947:1947) (2004:2004:2004)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (827:827:827)) + (PORT datab (1168:1168:1168) (1216:1216:1216)) + (PORT datad (240:240:240) (281:281:281)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1439:1439:1439) (1508:1508:1508)) + (PORT ena (1131:1131:1131) (1098:1098:1098)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (778:778:778) (850:850:850)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (433:433:433)) + (PORT datab (886:886:886) (923:923:923)) + (PORT datad (350:350:350) (406:406:406)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1005:1005:1005) (1055:1055:1055)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1994:1994:1994) (2075:2075:2075)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (641:641:641)) + (PORT datab (1599:1599:1599) (1649:1649:1649)) + (PORT datad (1179:1179:1179) (1219:1219:1219)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1439:1439:1439) (1506:1506:1506)) + (PORT ena (1261:1261:1261) (1299:1299:1299)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1147:1147:1147)) + (PORT datab (678:678:678) (753:753:753)) + (PORT datad (849:849:849) (878:878:878)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (653:653:653)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (599:599:599) (617:617:617)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (2176:2176:2176) (2269:2269:2269)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (2177:2177:2177) (2273:2273:2273)) + (PORT ena (990:990:990) (994:994:994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (524:524:524)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datad (454:454:454) (497:497:497)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (2201:2201:2201) (2285:2285:2285)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (990:990:990)) + (PORT datab (1220:1220:1220) (1290:1290:1290)) + (PORT datad (884:884:884) (941:941:941)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (837:837:837)) + (PORT datab (560:560:560) (597:597:597)) + (PORT datac (558:558:558) (555:555:555)) + (PORT datad (850:850:850) (877:877:877)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -18358,13 +18046,92 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[6\]\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) (DELAY (ABSOLUTE - (PORT datab (564:564:564) (591:591:591)) - (PORT datac (1262:1262:1262) (1278:1278:1278)) - (PORT datad (673:673:673) (695:695:695)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (837:837:837) (909:909:909)) + (PORT datab (396:396:396) (421:421:421)) + (PORT datac (848:848:848) (907:907:907)) + (PORT datad (1297:1297:1297) (1337:1337:1337)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1554:1554:1554)) + (PORT asdata (545:545:545) (579:579:579)) + (PORT ena (940:940:940) (926:926:926)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1897:1897:1897) (1987:1987:1987)) + (PORT datab (235:235:235) (281:281:281)) + (PORT datad (211:211:211) (246:246:246)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (287:287:287)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (354:354:354) (413:413:413)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1139:1139:1139) (1156:1156:1156)) + (PORT datab (545:545:545) (561:561:561)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18372,15 +18139,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~10) + (INSTANCE z80_\|address_latch_\|abusz\[10\]) (DELAY (ABSOLUTE - (PORT dataa (676:676:676) (722:722:722)) - (PORT datab (1065:1065:1065) (1094:1094:1094)) - (PORT datac (1265:1265:1265) (1291:1291:1291)) - (PORT datad (1301:1301:1301) (1340:1340:1340)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datac (200:200:200) (235:235:235)) + (PORT datad (869:869:869) (899:899:899)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18388,27 +18151,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) + (INSTANCE z80_\|address_latch_\|Q\[10\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (1311:1311:1311) (1355:1355:1355)) - (PORT datab (1295:1295:1295) (1335:1335:1335)) - (PORT datac (3295:3295:3295) (3389:3389:3389)) - (PORT datad (684:684:684) (742:742:742)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (531:531:531) (546:546:546)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~4) + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) (DELAY (ABSOLUTE - (PORT datac (853:853:853) (893:893:893)) - (PORT datad (1100:1100:1100) (1131:1131:1131)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2096:2096:2096) (2133:2133:2133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (368:368:368)) + (PORT datab (276:276:276) (370:370:370)) + (PORT datac (1338:1338:1338) (1352:1352:1352)) + (PORT datad (324:324:324) (345:345:345)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18416,15 +18195,102 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (INSTANCE z80_\|address_latch_\|abusz\[11\]) (DELAY (ABSOLUTE - (PORT dataa (1371:1371:1371) (1473:1473:1473)) - (PORT datab (218:218:218) (264:264:264)) - (PORT datac (627:627:627) (663:663:663)) - (PORT datad (1145:1145:1145) (1247:1247:1247)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT datab (602:602:602) (632:632:632)) + (PORT datad (924:924:924) (945:945:945)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2096:2096:2096) (2133:2133:2133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datac (568:568:568) (632:632:632)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1308:1308:1308) (1303:1303:1303)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (738:738:738) (772:772:772)) + (PORT ena (935:935:935) (924:924:924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (407:407:407) (446:446:446)) + (PORT datad (388:388:388) (422:422:422)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (335:335:335)) + (PORT datac (823:823:823) (870:870:870)) + (PORT datad (639:639:639) (664:664:664)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18432,15 +18298,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~12) + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) (DELAY (ABSOLUTE - (PORT dataa (1022:1022:1022) (1061:1061:1061)) - (PORT datab (670:670:670) (731:731:731)) - (PORT datac (878:878:878) (926:926:926)) - (PORT datad (1043:1043:1043) (1048:1048:1048)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (565:565:565) (577:577:577)) + (PORT datab (846:846:846) (883:883:883)) + (PORT datac (679:679:679) (728:728:728)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18448,15 +18314,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) (DELAY (ABSOLUTE - (PORT dataa (930:930:930) (982:982:982)) - (PORT datab (1567:1567:1567) (1604:1604:1604)) - (PORT datac (1865:1865:1865) (1960:1960:1960)) - (PORT datad (1072:1072:1072) (1090:1090:1090)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (612:612:612) (644:644:644)) + (PORT datab (820:820:820) (880:880:880)) + (PORT datac (393:393:393) (430:430:430)) + (PORT datad (1301:1301:1301) (1333:1333:1333)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (916:916:916)) + (PORT datab (223:223:223) (272:272:272)) + (PORT datac (1159:1159:1159) (1203:1203:1203)) + (PORT datad (607:607:607) (634:634:634)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1068:1068:1068)) + (PORT datab (2092:2092:2092) (2152:2152:2152)) + (PORT datac (686:686:686) (739:739:739)) + (PORT datad (1737:1737:1737) (1857:1857:1857)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18464,13 +18362,89 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) (DELAY (ABSOLUTE - (PORT dataa (560:560:560) (576:576:576)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (607:607:607) (623:623:623)) - (PORT datad (174:174:174) (200:200:200)) + (PORT datab (964:964:964) (1009:1009:1009)) + (PORT datac (1166:1166:1166) (1163:1163:1163)) + (PORT datad (680:680:680) (717:717:717)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (652:652:652) (711:711:711)) + (PORT datac (647:647:647) (707:707:707)) + (PORT datad (634:634:634) (661:661:661)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (713:713:713)) + (PORT datab (641:641:641) (708:708:708)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (575:575:575) (599:599:599)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1169:1169:1169)) + (PORT datab (1268:1268:1268) (1379:1379:1379)) + (PORT datac (613:613:613) (634:634:634)) + (PORT datad (1131:1131:1131) (1134:1134:1134)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2003:2003:2003) (2192:2192:2192)) + (PORT datab (1271:1271:1271) (1346:1346:1346)) + (PORT datac (994:994:994) (1035:1035:1035)) + (PORT datad (1461:1461:1461) (1531:1531:1531)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -18480,15 +18454,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~0) + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) (DELAY (ABSOLUTE - (PORT dataa (1121:1121:1121) (1188:1188:1188)) - (PORT datab (674:674:674) (710:710:710)) - (PORT datac (1115:1115:1115) (1130:1130:1130)) - (PORT datad (864:864:864) (912:912:912)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1013:1013:1013) (1048:1048:1048)) + (PORT datab (1598:1598:1598) (1713:1713:1713)) + (PORT datac (1145:1145:1145) (1147:1147:1147)) + (PORT datad (654:654:654) (698:698:698)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2564:2564:2564) (2702:2702:2702)) + (PORT datab (1558:1558:1558) (1680:1680:1680)) + (PORT datac (866:866:866) (908:908:908)) + (PORT datad (191:191:191) (224:224:224)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18496,15 +18486,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) (DELAY (ABSOLUTE - (PORT dataa (1129:1129:1129) (1167:1167:1167)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (203:203:203) (240:240:240)) - (PORT datad (850:850:850) (873:873:873)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (385:385:385) (411:411:411)) + (PORT datab (804:804:804) (851:851:851)) + (PORT datac (829:829:829) (862:862:862)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18512,24 +18502,56 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~1) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) (DELAY (ABSOLUTE - (PORT datab (197:197:197) (236:236:236)) - (PORT datad (1141:1141:1141) (1191:1191:1191)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (647:647:647) (668:668:668)) + (PORT datab (1164:1164:1164) (1226:1226:1226)) + (PORT datac (562:562:562) (562:562:562)) + (PORT datad (595:595:595) (626:626:626)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (616:616:616)) + (PORT datab (1125:1125:1125) (1173:1173:1173)) + (PORT datac (561:561:561) (579:579:579)) + (PORT datad (905:905:905) (952:952:952)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (332:332:332)) + (PORT datac (170:170:170) (202:202:202)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) (DELAY (ABSOLUTE - (PORT dataa (1119:1119:1119) (1184:1184:1184)) - (PORT datac (1121:1121:1121) (1138:1138:1138)) - (PORT datad (1141:1141:1141) (1194:1194:1194)) + (PORT dataa (263:263:263) (339:339:339)) + (PORT datac (1090:1090:1090) (1144:1144:1144)) + (PORT datad (902:902:902) (951:951:951)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -18541,9 +18563,9 @@ (INSTANCE z80_\|alu_\|op2_high\[1\]) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) + (PORT clk (1529:1529:1529) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18557,10 +18579,10 @@ (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) (DELAY (ABSOLUTE - (PORT dataa (1132:1132:1132) (1171:1171:1171)) - (PORT datac (632:632:632) (657:657:657)) - (PORT datad (877:877:877) (940:940:940)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT datab (968:968:968) (1010:1010:1010)) + (PORT datac (370:370:370) (404:404:404)) + (PORT datad (675:675:675) (715:715:715)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18571,7 +18593,7 @@ (INSTANCE z80_\|alu_\|op1_high\[1\]) (DELAY (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) + (PORT clk (1530:1530:1530) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -18584,15 +18606,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~3) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (885:885:885) (960:960:960)) - (PORT datab (1015:1015:1015) (1029:1029:1029)) - (PORT datac (911:911:911) (959:959:959)) - (PORT datad (861:861:861) (877:877:877)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (676:676:676) (733:733:733)) + (PORT datab (1128:1128:1128) (1182:1182:1182)) + (PORT datac (588:588:588) (620:620:620)) + (PORT datad (380:380:380) (439:439:439)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (340:340:340)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (556:556:556) (578:578:578)) + (PORT datad (900:900:900) (949:949:949)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1468:1468:1468) (1479:1479:1479)) + (PORT datab (1497:1497:1497) (1572:1572:1572)) + (PORT datac (1847:1847:1847) (1915:1915:1915)) + (PORT datad (402:402:402) (438:438:438)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1433:1433:1433) (1518:1518:1518)) + (PORT datab (1643:1643:1643) (1769:1769:1769)) + (PORT datac (1052:1052:1052) (1102:1102:1102)) + (PORT datad (1294:1294:1294) (1385:1385:1385)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (898:898:898)) + (PORT datab (943:943:943) (983:983:983)) + (PORT datac (858:858:858) (877:877:877)) + (PORT datad (654:654:654) (664:664:664)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18600,14 +18702,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~2) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) (DELAY (ABSOLUTE - (PORT dataa (673:673:673) (725:725:725)) - (PORT datab (1066:1066:1066) (1098:1098:1098)) - (PORT datac (1264:1264:1264) (1298:1298:1298)) - (PORT datad (1299:1299:1299) (1342:1342:1342)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (480:480:480) (518:518:518)) + (PORT datab (1187:1187:1187) (1249:1249:1249)) + (PORT datac (925:925:925) (1011:1011:1011)) + (PORT datad (1383:1383:1383) (1482:1482:1482)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -18616,373 +18718,720 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~9) + (INSTANCE z80_\|pla_decode_\|Equal61\~2) (DELAY (ABSOLUTE - (PORT dataa (1111:1111:1111) (1142:1142:1142)) - (PORT datab (878:878:878) (903:903:903)) - (PORT datad (1149:1149:1149) (1165:1165:1165)) + (PORT dataa (1746:1746:1746) (1869:1869:1869)) + (PORT datab (1375:1375:1375) (1426:1426:1426)) + (PORT datac (1591:1591:1591) (1672:1672:1672)) + (PORT datad (1495:1495:1495) (1627:1627:1627)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT datab (1828:1828:1828) (1926:1926:1926)) + (PORT datac (1699:1699:1699) (1792:1792:1792)) + (PORT datad (926:926:926) (994:994:994)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1872:1872:1872) (1889:1889:1889)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (880:880:880) (886:886:886)) + (PORT datad (803:803:803) (814:814:814)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1342:1342:1342) (1440:1440:1440)) + (PORT datab (1765:1765:1765) (1873:1873:1873)) + (PORT datac (1447:1447:1447) (1536:1536:1536)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1520:1520:1520) (1609:1609:1609)) + (PORT datab (925:925:925) (988:988:988)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (262:262:262)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1766:1766:1766) (1808:1808:1808)) + (PORT datab (836:836:836) (862:862:862)) + (PORT datac (1306:1306:1306) (1421:1421:1421)) + (PORT datad (2555:2555:2555) (2677:2677:2677)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (614:614:614)) + (PORT datab (246:246:246) (286:286:286)) + (PORT datac (221:221:221) (257:257:257)) + (PORT datad (904:904:904) (976:976:976)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1051:1051:1051) (1075:1075:1075)) + (PORT datab (1615:1615:1615) (1655:1655:1655)) + (PORT datac (1187:1187:1187) (1227:1227:1227)) + (PORT datad (1742:1742:1742) (1769:1769:1769)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (921:921:921)) + (PORT datab (941:941:941) (1014:1014:1014)) + (PORT datac (219:219:219) (254:254:254)) + (PORT datad (903:903:903) (974:974:974)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (258:258:258)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1272:1272:1272)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (2061:2061:2061) (2171:2171:2171)) + (PORT datad (1409:1409:1409) (1503:1503:1503)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (718:718:718)) + (PORT datab (1484:1484:1484) (1542:1542:1542)) + (PORT datac (1486:1486:1486) (1511:1511:1511)) + (PORT datad (640:640:640) (654:654:654)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (857:857:857)) + (PORT datab (1485:1485:1485) (1542:1542:1542)) + (PORT datac (1608:1608:1608) (1613:1613:1613)) + (PORT datad (1444:1444:1444) (1563:1563:1563)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (213:213:213) (257:257:257)) + (PORT datac (838:838:838) (870:870:870)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1070:1070:1070) (1092:1092:1092)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal72\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1402:1402:1402) (1477:1477:1477)) + (PORT datab (2359:2359:2359) (2492:2492:2492)) + (PORT datac (1132:1132:1132) (1171:1171:1171)) + (PORT datad (855:855:855) (857:857:857)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2002:2002:2002) (2149:2149:2149)) + (PORT datab (1120:1120:1120) (1189:1189:1189)) + (PORT datac (1350:1350:1350) (1403:1403:1403)) + (PORT datad (855:855:855) (872:872:872)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (975:975:975) (1049:1049:1049)) + (PORT datab (960:960:960) (1047:1047:1047)) + (PORT datac (1782:1782:1782) (1803:1803:1803)) + (PORT datad (1450:1450:1450) (1533:1533:1533)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1044:1044:1044) (1059:1059:1059)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (616:616:616) (640:640:640)) + (PORT datad (601:601:601) (613:613:613)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1518:1518:1518) (1586:1586:1586)) + (PORT datab (1962:1962:1962) (1991:1991:1991)) + (PORT datac (1263:1263:1263) (1313:1313:1313)) + (PORT datad (933:933:933) (1002:1002:1002)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT datab (864:864:864) (893:893:893)) + (PORT datac (819:819:819) (853:853:853)) + (PORT datad (811:811:811) (845:845:845)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2565:2565:2565) (2704:2704:2704)) + (PORT datac (1529:1529:1529) (1648:1648:1648)) + (PORT datad (1533:1533:1533) (1667:1667:1667)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (304:304:304)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (1176:1176:1176) (1212:1212:1212)) + (PORT datad (191:191:191) (224:224:224)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (859:859:859)) + (PORT datab (618:618:618) (647:647:647)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (802:802:802) (881:881:881)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (957:957:957)) + (PORT datac (824:824:824) (856:856:856)) + (PORT datad (647:647:647) (680:680:680)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (960:960:960)) + (PORT datab (362:362:362) (394:394:394)) + (PORT datac (591:591:591) (619:619:619)) + (PORT datad (338:338:338) (357:357:357)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) + (DELAY + (ABSOLUTE + (PORT datac (891:891:891) (933:933:933)) + (PORT datad (831:831:831) (843:843:843)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (649:649:649)) + (PORT datab (1105:1105:1105) (1114:1114:1114)) + (PORT datac (753:753:753) (781:781:781)) + (PORT datad (613:613:613) (631:631:631)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (942:942:942)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2002:2002:2002) (2062:2062:2062)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (1707:1707:1707) (1823:1823:1823)) + (PORT datad (1505:1505:1505) (1539:1539:1539)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1137:1137:1137) (1211:1211:1211)) + (PORT datab (1568:1568:1568) (1705:1705:1705)) + (PORT datac (2532:2532:2532) (2663:2663:2663)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1063:1063:1063)) + (PORT datab (1299:1299:1299) (1349:1349:1349)) + (PORT datac (890:890:890) (914:914:914)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (665:665:665)) + (PORT datab (2303:2303:2303) (2383:2383:2383)) + (PORT datac (2057:2057:2057) (2199:2199:2199)) + (PORT datad (1163:1163:1163) (1186:1186:1186)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (640:640:640)) + (PORT datab (608:608:608) (638:638:638)) + (PORT datac (549:549:549) (557:557:557)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1068:1068:1068)) + (PORT datab (2030:2030:2030) (2166:2166:2166)) + (PORT datac (821:821:821) (831:831:831)) + (PORT datad (2503:2503:2503) (2629:2629:2629)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1546:1546:1546) (1624:1624:1624)) + (PORT datab (938:938:938) (1017:1017:1017)) + (PORT datac (601:601:601) (662:662:662)) + (PORT datad (580:580:580) (585:585:585)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (920:920:920)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (666:666:666) (685:685:685)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (680:680:680)) + (PORT datab (1172:1172:1172) (1198:1198:1198)) + (PORT datac (636:636:636) (693:693:693)) + (PORT datad (307:307:307) (324:324:324)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (694:694:694)) + (PORT datab (806:806:806) (876:876:876)) + (PORT datac (1101:1101:1101) (1130:1130:1130)) + (PORT datad (589:589:589) (627:627:627)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (667:667:667)) + (PORT datab (654:654:654) (679:679:679)) + (PORT datac (936:936:936) (1033:1033:1033)) + (PORT datad (830:830:830) (861:861:861)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1518:1518:1518) (1588:1588:1588)) + (PORT datab (1051:1051:1051) (1075:1075:1075)) + (PORT datac (1263:1263:1263) (1316:1316:1316)) + (PORT datad (930:930:930) (999:999:999)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1452:1452:1452) (1482:1482:1482)) + (PORT datab (1142:1142:1142) (1181:1181:1181)) + (PORT datac (1196:1196:1196) (1287:1287:1287)) + (PORT datad (1139:1139:1139) (1160:1160:1160)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (646:646:646)) + (PORT datab (1014:1014:1014) (1076:1076:1076)) + (PORT datac (798:798:798) (807:807:807)) + (PORT datad (619:619:619) (632:632:632)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1787:1787:1787) (1827:1827:1827)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1789:1789:1789) (1828:1828:1828)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~70) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) (DELAY (ABSOLUTE - (PORT dataa (672:672:672) (700:700:700)) - (PORT datab (244:244:244) (326:326:326)) - (PORT datad (632:632:632) (651:651:651)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (230:230:230) (276:276:276)) + (PORT datab (1030:1030:1030) (1067:1067:1067)) + (PORT datac (871:871:871) (866:866:866)) + (PORT datad (599:599:599) (614:614:614)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (1972:1972:1972) (2034:2034:2034)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~72) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) (DELAY (ABSOLUTE - (PORT dataa (486:486:486) (521:521:521)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (664:664:664) (693:693:693)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (705:705:705) (732:732:732)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (1337:1337:1337) (1364:1364:1364)) - (PORT datab (845:845:845) (875:875:875)) - (PORT datad (387:387:387) (410:410:410)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1778:1778:1778) (1814:1814:1814)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (1773:1773:1773) (1809:1809:1809)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (473:473:473)) - (PORT datab (429:429:429) (472:472:472)) - (PORT datad (363:363:363) (425:425:425)) + (PORT dataa (583:583:583) (619:619:619)) + (PORT datab (225:225:225) (273:273:273)) + (PORT datac (824:824:824) (846:846:846)) + (PORT datad (1377:1377:1377) (1491:1491:1491)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (618:618:618)) - (PORT datab (648:648:648) (667:667:667)) - (PORT datac (603:603:603) (617:617:617)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1610:1610:1610) (1660:1660:1660)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1613:1613:1613) (1663:1663:1663)) - (PORT ena (1011:1011:1011) (1021:1021:1021)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (332:332:332)) - (PORT datab (688:688:688) (758:758:758)) - (PORT datad (231:231:231) (265:265:265)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1429:1429:1429) (1453:1453:1453)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1210:1210:1210) (1276:1276:1276)) - (PORT datab (1385:1385:1385) (1453:1453:1453)) - (PORT datad (1859:1859:1859) (1914:1914:1914)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1240:1240:1240) (1258:1258:1258)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1243:1243:1243) (1262:1262:1262)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (420:420:420) (474:474:474)) - (PORT datab (436:436:436) (465:465:465)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (647:647:647)) - (PORT datab (330:330:330) (359:359:359)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (589:589:589) (638:638:638)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (658:658:658)) - (PORT datab (1983:1983:1983) (2132:2132:2132)) - (PORT datac (585:585:585) (606:606:606)) - (PORT datad (569:569:569) (584:584:584)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1149:1149:1149)) - (PORT datab (1192:1192:1192) (1209:1209:1209)) - (PORT datac (954:954:954) (998:998:998)) - (PORT datad (1694:1694:1694) (1741:1741:1741)) - (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -18991,15 +19440,172 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) (DELAY (ABSOLUTE - (PORT dataa (685:685:685) (716:716:716)) - (PORT datab (248:248:248) (305:305:305)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (846:846:846) (858:858:858)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT dataa (780:780:780) (837:837:837)) + (PORT datab (827:827:827) (864:864:864)) + (PORT datac (762:762:762) (835:835:835)) + (PORT datad (767:767:767) (810:810:810)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1230:1230:1230) (1277:1277:1277)) + (PORT datab (699:699:699) (755:755:755)) + (PORT datac (917:917:917) (964:964:964)) + (PORT datad (1070:1070:1070) (1101:1101:1101)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (667:667:667)) + (PORT datab (653:653:653) (673:673:673)) + (PORT datac (935:935:935) (1036:1036:1036)) + (PORT datad (387:387:387) (408:408:408)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (1042:1042:1042)) + (PORT datab (1807:1807:1807) (1835:1835:1835)) + (PORT datac (1262:1262:1262) (1315:1315:1315)) + (PORT datad (1069:1069:1069) (1081:1081:1081)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2018:2018:2018) (2105:2105:2105)) + (PORT datab (2408:2408:2408) (2537:2537:2537)) + (PORT datac (1381:1381:1381) (1441:1441:1441)) + (PORT datad (1576:1576:1576) (1733:1733:1733)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1517:1517:1517) (1579:1579:1579)) + (PORT datab (385:385:385) (404:404:404)) + (PORT datac (1263:1263:1263) (1308:1308:1308)) + (PORT datad (871:871:871) (923:923:923)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1269:1269:1269)) + (PORT datab (340:340:340) (375:375:375)) + (PORT datac (1057:1057:1057) (1084:1084:1084)) + (PORT datad (337:337:337) (358:358:358)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (385:385:385)) + (PORT datab (643:643:643) (665:665:665)) + (PORT datac (169:169:169) (201:201:201)) + (PORT datad (616:616:616) (624:624:624)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (887:887:887)) + (PORT datab (1118:1118:1118) (1197:1197:1197)) + (PORT datac (848:848:848) (898:898:898)) + (PORT datad (364:364:364) (426:426:426)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19007,15 +19613,203 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) (DELAY (ABSOLUTE - (PORT dataa (857:857:857) (879:879:879)) - (PORT datab (1474:1474:1474) (1579:1579:1579)) - (PORT datac (1557:1557:1557) (1550:1550:1550)) - (PORT datad (1116:1116:1116) (1188:1188:1188)) - (IOPATH dataa combout (303:303:303) (299:299:299)) + (PORT dataa (2563:2563:2563) (2705:2705:2705)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1385:1385:1385) (1391:1391:1391)) + (PORT datad (1888:1888:1888) (1980:1980:1980)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (529:529:529)) + (PORT datab (452:452:452) (522:522:522)) + (PORT datac (877:877:877) (897:897:897)) + (PORT datad (660:660:660) (680:680:680)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (573:573:573)) + (PORT datab (633:633:633) (685:685:685)) + (PORT datac (619:619:619) (639:639:639)) + (PORT datad (630:630:630) (672:672:672)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (850:850:850)) + (PORT datab (621:621:621) (640:640:640)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (823:823:823)) + (PORT datab (610:610:610) (633:633:633)) + (PORT datac (1092:1092:1092) (1142:1142:1142)) + (PORT datad (895:895:895) (948:948:948)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (232:232:232) (287:287:287)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (432:432:432) (521:521:521)) + (PORT datab (682:682:682) (739:739:739)) + (PORT datac (877:877:877) (897:897:897)) + (PORT datad (660:660:660) (685:685:685)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (922:922:922)) + (PORT datab (224:224:224) (269:269:269)) + (PORT datac (826:826:826) (848:848:848)) + (PORT datad (904:904:904) (974:974:974)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (842:842:842)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (1821:1821:1821) (1815:1815:1815)) + (PORT datad (790:790:790) (826:826:826)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (706:706:706)) + (PORT datab (1772:1772:1772) (1798:1798:1798)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (823:823:823) (837:837:837)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (DELAY + (ABSOLUTE + (PORT dataa (2390:2390:2390) (2544:2544:2544)) + (PORT datab (1497:1497:1497) (1581:1581:1581)) + (PORT datac (874:874:874) (897:897:897)) + (PORT datad (1014:1014:1014) (1128:1128:1128)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (605:605:605)) + (PORT datab (974:974:974) (1056:1056:1056)) + (PORT datac (672:672:672) (715:715:715)) + (PORT datad (819:819:819) (820:820:820)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19023,14 +19817,330 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) (DELAY (ABSOLUTE - (PORT dataa (1200:1200:1200) (1276:1276:1276)) - (PORT datab (1069:1069:1069) (1086:1086:1086)) - (PORT datac (691:691:691) (782:782:782)) - (PORT datad (931:931:931) (959:959:959)) + (PORT dataa (987:987:987) (1039:1039:1039)) + (PORT datab (434:434:434) (474:474:474)) + (PORT datac (947:947:947) (1015:1015:1015)) + (PORT datad (1175:1175:1175) (1235:1235:1235)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (285:285:285)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (208:208:208) (238:238:238)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (278:278:278)) + (PORT datac (193:193:193) (235:235:235)) + (PORT datad (374:374:374) (396:396:396)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (639:639:639) (661:661:661)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (DELAY + (ABSOLUTE + (PORT datab (1269:1269:1269) (1380:1380:1380)) + (PORT datac (901:901:901) (917:917:917)) + (PORT datad (1177:1177:1177) (1191:1191:1191)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1340:1340:1340)) + (PORT datab (1007:1007:1007) (1075:1075:1075)) + (PORT datac (1456:1456:1456) (1496:1496:1496)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (DELAY + (ABSOLUTE + (PORT dataa (2050:2050:2050) (2087:2087:2087)) + (PORT datab (943:943:943) (1022:1022:1022)) + (PORT datac (1211:1211:1211) (1239:1239:1239)) + (PORT datad (1083:1083:1083) (1126:1126:1126)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (949:949:949)) + (PORT datab (1060:1060:1060) (1085:1085:1085)) + (PORT datac (892:892:892) (934:934:934)) + (PORT datad (568:568:568) (571:571:571)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1490:1490:1490) (1592:1592:1592)) + (PORT datab (438:438:438) (472:472:472)) + (PORT datac (945:945:945) (997:997:997)) + (PORT datad (1178:1178:1178) (1233:1233:1233)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1493:1493:1493) (1597:1597:1597)) + (PORT datab (234:234:234) (278:278:278)) + (PORT datac (2021:2021:2021) (2050:2050:2050)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (609:609:609) (638:638:638)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (258:258:258)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (817:817:817) (862:862:862)) + (PORT datad (554:554:554) (572:572:572)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1462:1462:1462) (1525:1525:1525)) + (PORT datab (1404:1404:1404) (1424:1424:1424)) + (PORT datac (1574:1574:1574) (1618:1618:1618)) + (PORT datad (1065:1065:1065) (1079:1079:1079)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (759:759:759)) + (PORT datab (699:699:699) (730:730:730)) + (PORT datac (1599:1599:1599) (1604:1604:1604)) + (PORT datad (1436:1436:1436) (1479:1479:1479)) (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1343:1343:1343) (1425:1425:1425)) + (PORT datab (1086:1086:1086) (1110:1110:1110)) + (PORT datac (1574:1574:1574) (1614:1614:1614)) + (PORT datad (1794:1794:1794) (1911:1911:1911)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (843:843:843) (880:880:880)) + (PORT datac (1602:1602:1602) (1608:1608:1608)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~42) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (867:867:867)) + (PORT datab (1092:1092:1092) (1116:1116:1116)) + (PORT datac (2113:2113:2113) (2219:2219:2219)) + (PORT datad (1789:1789:1789) (1904:1904:1904)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1016:1016:1016) (1027:1027:1027)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~41) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (702:702:702)) + (PORT datab (2051:2051:2051) (2134:2134:2134)) + (PORT datac (1486:1486:1486) (1540:1540:1540)) + (PORT datad (1327:1327:1327) (1454:1454:1454)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1519:1519:1519) (1580:1580:1580)) + (PORT datab (1960:1960:1960) (1986:1986:1986)) + (PORT datac (1263:1263:1263) (1313:1313:1313)) + (PORT datad (869:869:869) (922:922:922)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1748:1748:1748) (1872:1872:1872)) + (PORT datab (1028:1028:1028) (1083:1083:1083)) + (PORT datac (199:199:199) (235:235:235)) + (PORT datad (1506:1506:1506) (1541:1541:1541)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -19039,28 +20149,509 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) (DELAY (ABSOLUTE - (PORT dataa (528:528:528) (555:555:555)) - (PORT datab (634:634:634) (673:673:673)) - (PORT datac (635:635:635) (664:664:664)) + (PORT dataa (1165:1165:1165) (1194:1194:1194)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1359:1359:1359) (1382:1382:1382)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~44) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (841:841:841)) + (PORT datab (1818:1818:1818) (1968:1968:1968)) + (PORT datac (1306:1306:1306) (1386:1386:1386)) + (PORT datad (1794:1794:1794) (1911:1911:1911)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (699:699:699) (733:733:733)) + (PORT datac (862:862:862) (901:901:901)) + (PORT datad (693:693:693) (717:717:717)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (551:551:551)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (641:641:641) (659:659:659)) (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (620:620:620)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (603:603:603) (622:622:622)) + (PORT datad (345:345:345) (359:359:359)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (917:917:917) (956:956:956)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (317:317:317) (337:337:337)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1666:1666:1666) (1754:1754:1754)) + (PORT datab (1416:1416:1416) (1493:1493:1493)) + (PORT datac (639:639:639) (659:659:659)) + (PORT datad (847:847:847) (875:875:875)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1506:1506:1506)) + (PORT datab (849:849:849) (859:859:859)) + (PORT datac (836:836:836) (864:864:864)) + (PORT datad (1389:1389:1389) (1423:1423:1423)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (869:869:869)) + (PORT datab (1772:1772:1772) (1798:1798:1798)) + (PORT datac (618:618:618) (638:638:638)) + (PORT datad (822:822:822) (837:837:837)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1198:1198:1198) (1248:1248:1248)) + (PORT datab (223:223:223) (268:268:268)) + (PORT datac (914:914:914) (947:947:947)) + (PORT datad (607:607:607) (631:631:631)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (334:334:334)) + (PORT datab (944:944:944) (991:991:991)) + (PORT datac (535:535:535) (545:545:545)) + (PORT datad (1139:1139:1139) (1125:1125:1125)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (673:673:673)) + (PORT datab (1125:1125:1125) (1173:1173:1173)) + (PORT datac (583:583:583) (615:615:615)) + (PORT datad (389:389:389) (443:443:443)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (340:340:340)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (559:559:559) (583:583:583)) + (PORT datad (901:901:901) (948:948:948)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (511:511:511)) + (PORT datab (419:419:419) (499:499:499)) + (PORT datac (878:878:878) (901:901:901)) + (PORT datad (657:657:657) (678:678:678)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (638:638:638) (659:659:659)) + (PORT datac (355:355:355) (378:378:378)) + (PORT datad (830:830:830) (837:837:837)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (419:419:419)) + (PORT datab (653:653:653) (711:711:711)) + (PORT datac (647:647:647) (707:707:707)) + (PORT datad (635:635:635) (659:659:659)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (443:443:443)) + (PORT datab (239:239:239) (284:284:284)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (742:742:742)) + (PORT datab (1178:1178:1178) (1274:1274:1274)) + (PORT datac (855:855:855) (865:865:865)) + (PORT datad (674:674:674) (693:693:693)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1358:1358:1358)) + (PORT datab (1962:1962:1962) (1990:1990:1990)) + (PORT datac (1486:1486:1486) (1545:1545:1545)) + (PORT datad (1495:1495:1495) (1557:1557:1557)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1144:1144:1144) (1179:1179:1179)) + (PORT datab (609:609:609) (638:638:638)) + (PORT datac (820:820:820) (842:842:842)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datad (798:798:798) (805:805:805)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1175:1175:1175)) + (PORT datac (567:567:567) (576:576:576)) + (PORT datad (1627:1627:1627) (1703:1703:1703)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (927:927:927)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1829:1829:1829) (1911:1911:1911)) + (PORT datad (562:562:562) (570:570:570)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (415:415:415)) + (PORT datab (2086:2086:2086) (2229:2229:2229)) + (PORT datac (1314:1314:1314) (1402:1402:1402)) + (PORT datad (902:902:902) (968:968:968)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (462:462:462)) + (PORT datab (612:612:612) (633:633:633)) + (PORT datac (1175:1175:1175) (1235:1235:1235)) + (PORT datad (822:822:822) (844:844:844)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (597:597:597)) + (PORT datab (615:615:615) (638:638:638)) + (PORT datad (567:567:567) (574:574:574)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (685:685:685)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (807:807:807) (808:808:808)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1698:1698:1698) (1789:1789:1789)) + (PORT datab (919:919:919) (952:952:952)) + (PORT datac (888:888:888) (909:909:909)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_latch_\|abusz\[12\]) (DELAY (ABSOLUTE - (PORT datac (1514:1514:1514) (1609:1609:1609)) - (PORT datad (634:634:634) (666:666:666)) + (PORT datab (403:403:403) (448:448:448)) + (PORT datac (885:885:885) (915:915:915)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[12\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (314:314:314) (333:333:333)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -19070,10 +20661,10 @@ (INSTANCE z80_\|address_latch_\|Q\[12\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1547:1547:1547)) - (PORT ena (2484:2484:2484) (2511:2511:2511)) + (PORT clrn (1581:1581:1581) (1561:1561:1561)) + (PORT ena (2058:2058:2058) (2109:2109:2109)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -19088,24 +20679,101 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) (DELAY (ABSOLUTE - (PORT dataa (454:454:454) (536:536:536)) - (PORT datab (470:470:470) (552:552:552)) - (PORT datac (989:989:989) (1029:1029:1029)) - (PORT datad (547:547:547) (558:558:558)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (625:625:625) (638:638:638)) + (PORT datab (903:903:903) (926:926:926)) + (PORT datac (240:240:240) (327:327:327)) + (PORT datad (577:577:577) (639:639:639)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1308:1308:1308) (1303:1303:1303)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1458:1458:1458) (1466:1466:1466)) + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (1270:1270:1270) (1318:1318:1318)) + (PORT ena (935:935:935) (924:924:924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (460:460:460)) + (PORT datab (412:412:412) (448:448:448)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (717:717:717)) + (PORT datac (216:216:216) (293:293:293)) + (PORT datad (775:775:775) (807:807:807)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (418:418:418)) + (PORT datab (838:838:838) (875:875:875)) + (PORT datac (679:679:679) (721:721:721)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (2041:2041:2041) (2053:2053:2053)) (PORT ena (790:790:790) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -19117,310 +20785,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~22) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (328:328:328)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datad (898:898:898) (963:963:963)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (456:456:456) (489:489:489)) - (PORT datac (304:304:304) (327:327:327)) - (PORT datad (217:217:217) (286:286:286)) + (PORT dataa (409:409:409) (437:437:437)) + (PORT datab (1165:1165:1165) (1216:1216:1216)) + (PORT datad (739:739:739) (751:751:751)) + (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (720:720:720)) - (PORT datab (400:400:400) (436:436:436)) - (PORT datac (1663:1663:1663) (1792:1792:1792)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1226:1226:1226) (1262:1262:1262)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1210:1210:1210) (1280:1280:1280)) - (PORT datab (1382:1382:1382) (1450:1450:1450)) - (PORT datad (1863:1863:1863) (1919:1919:1919)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1226:1226:1226) (1243:1243:1243)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1226:1226:1226) (1243:1243:1243)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (474:474:474)) - (PORT datab (434:434:434) (463:463:463)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1280:1280:1280) (1315:1315:1315)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1280:1280:1280) (1315:1315:1315)) - (PORT ena (1011:1011:1011) (1021:1021:1021)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (989:989:989)) - (PORT datab (239:239:239) (321:321:321)) - (PORT datad (233:233:233) (270:270:270)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1276:1276:1276) (1306:1306:1306)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1275:1275:1275) (1303:1303:1303)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (700:700:700)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (631:631:631) (646:646:646)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1219:1219:1219) (1247:1247:1247)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1219:1219:1219) (1247:1247:1247)) - (PORT ena (979:979:979) (971:971:971)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (483:483:483)) - (PORT datab (424:424:424) (466:466:466)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (936:936:936) (959:959:959)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1355:1355:1355)) - (PORT datab (842:842:842) (875:875:875)) - (PORT datad (388:388:388) (408:408:408)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19431,9 +20803,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) + (PORT clk (1535:1535:1535) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1397:1397:1397) (1426:1426:1426)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -19447,9 +20819,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (914:914:914) (940:940:940)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (2041:2041:2041) (2050:2050:2050)) + (PORT ena (1236:1236:1236) (1273:1273:1273)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -19460,14 +20832,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~81) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) (DELAY (ABSOLUTE - (PORT dataa (488:488:488) (524:524:524)) - (PORT datab (456:456:456) (530:530:530)) - (PORT datad (666:666:666) (691:691:691)) + (PORT dataa (692:692:692) (780:780:780)) + (PORT datab (884:884:884) (909:909:909)) + (PORT datad (866:866:866) (902:902:902)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1376:1376:1376) (1427:1427:1427)) + (PORT ena (1214:1214:1214) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1376:1376:1376) (1429:1429:1429)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (945:945:945)) + (PORT datab (244:244:244) (290:290:290)) + (PORT datad (216:216:216) (284:284:284)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19475,147 +20894,211 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~82) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (823:823:823) (868:868:868)) - (PORT datab (609:609:609) (659:659:659)) - (PORT datac (595:595:595) (612:612:612)) - (PORT datad (597:597:597) (611:611:611)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datad (1394:1394:1394) (1418:1418:1418)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~83) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT dataa (617:617:617) (673:673:673)) - (PORT datab (571:571:571) (589:589:589)) - (PORT datac (881:881:881) (883:883:883)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1721:1721:1721) (1742:1742:1742)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~84) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) (DELAY (ABSOLUTE - (PORT dataa (2010:2010:2010) (2149:2149:2149)) - (PORT datab (585:585:585) (602:602:602)) - (PORT datac (1114:1114:1114) (1125:1125:1125)) - (PORT datad (809:809:809) (855:855:855)) - (IOPATH dataa combout (325:325:325) (320:320:320)) + (PORT dataa (392:392:392) (467:467:467)) + (PORT datab (1593:1593:1593) (1645:1645:1645)) + (PORT datad (1180:1180:1180) (1215:1215:1215)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (809:809:809) (810:810:810)) + (PORT datad (610:610:610) (622:622:622)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT dataa (1698:1698:1698) (1799:1799:1799)) - (PORT datac (1608:1608:1608) (1653:1653:1653)) - (PORT datad (1487:1487:1487) (1510:1510:1510)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1872:1872:1872) (1943:1943:1943)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1872:1872:1872) (1942:1942:1942)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (991:991:991)) + (PORT datab (912:912:912) (981:981:981)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1938:1938:1938) (1952:1952:1952)) + (PORT ena (990:990:990) (994:994:994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1936:1936:1936) (1952:1952:1952)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (519:519:519)) + (PORT datab (492:492:492) (537:537:537)) + (PORT datad (217:217:217) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1867:1867:1867) (1935:1935:1935)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (988:988:988)) + (PORT datab (1221:1221:1221) (1295:1295:1295)) + (PORT datad (887:887:887) (943:943:943)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) (DELAY (ABSOLUTE - (PORT dataa (1087:1087:1087) (1125:1125:1125)) - (PORT datab (1070:1070:1070) (1088:1088:1088)) - (PORT datac (1727:1727:1727) (1848:1848:1848)) - (PORT datad (1340:1340:1340) (1359:1359:1359)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT datab (1778:1778:1778) (1897:1897:1897)) - (PORT datac (880:880:880) (892:892:892)) - (PORT datad (1337:1337:1337) (1358:1358:1358)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1081:1081:1081)) - (PORT datac (1198:1198:1198) (1225:1225:1225)) - (PORT datad (1354:1354:1354) (1396:1396:1396)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT datab (1936:1936:1936) (2029:2029:2029)) - (PORT datac (750:750:750) (755:755:755)) - (PORT datad (1021:1021:1021) (1039:1039:1039)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1214:1214:1214)) - (PORT datac (1662:1662:1662) (1757:1757:1757)) - (PORT datad (1487:1487:1487) (1515:1515:1515)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1054:1054:1054) (1096:1096:1096)) - (PORT datab (611:611:611) (627:627:627)) - (PORT datac (1033:1033:1033) (1063:1063:1063)) - (PORT datad (1423:1423:1423) (1509:1509:1509)) + (PORT dataa (644:644:644) (697:697:697)) + (PORT datab (331:331:331) (360:360:360)) + (PORT datac (577:577:577) (594:594:594)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -19625,15 +21108,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) (DELAY (ABSOLUTE - (PORT dataa (671:671:671) (698:698:698)) - (PORT datab (356:356:356) (387:387:387)) - (PORT datac (868:868:868) (910:910:910)) - (PORT datad (564:564:564) (588:588:588)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (883:883:883) (947:947:947)) + (PORT datab (844:844:844) (916:916:916)) + (PORT datac (840:840:840) (851:851:851)) + (PORT datad (1298:1298:1298) (1335:1335:1335)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1356:1356:1356)) + (PORT datab (968:968:968) (1024:1024:1024)) + (PORT datac (891:891:891) (908:908:908)) + (PORT datad (1445:1445:1445) (1454:1454:1454)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1289:1289:1289) (1337:1337:1337)) + (PORT datab (1225:1225:1225) (1251:1251:1251)) + (PORT datac (904:904:904) (947:947:947)) + (PORT datad (928:928:928) (986:986:986)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (251:251:251)) + (PORT datab (249:249:249) (305:305:305)) + (PORT datac (1067:1067:1067) (1064:1064:1064)) + (PORT datad (949:949:949) (996:996:996)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1286:1286:1286) (1354:1354:1354)) + (PORT datab (933:933:933) (990:990:990)) + (PORT datac (372:372:372) (402:402:402)) + (PORT datad (1200:1200:1200) (1314:1314:1314)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1230:1230:1230)) + (PORT datab (1831:1831:1831) (1921:1921:1921)) + (PORT datac (881:881:881) (935:935:935)) + (PORT datad (1554:1554:1554) (1661:1661:1661)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19641,13 +21204,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) (DELAY (ABSOLUTE - (PORT dataa (1661:1661:1661) (1780:1780:1780)) - (PORT datab (576:576:576) (598:598:598)) - (PORT datac (1732:1732:1732) (1776:1776:1776)) - (PORT datad (2426:2426:2426) (2480:2480:2480)) + (PORT dataa (923:923:923) (987:987:987)) + (PORT datab (637:637:637) (672:672:672)) + (PORT datac (1395:1395:1395) (1470:1470:1470)) + (PORT datad (580:580:580) (617:617:617)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -19657,31 +21220,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (740:740:740) (757:757:757)) - (PORT datac (562:562:562) (592:592:592)) - (PORT datad (1035:1035:1035) (1038:1038:1038)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1523:1523:1523)) - (PORT datab (639:639:639) (720:720:720)) - (PORT datac (542:542:542) (563:563:563)) - (PORT datad (1266:1266:1266) (1295:1295:1295)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (204:204:204) (249:249:249)) + (PORT datac (935:935:935) (965:965:965)) + (PORT datad (241:241:241) (282:282:282)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19689,15 +21234,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) (DELAY (ABSOLUTE - (PORT dataa (838:838:838) (885:885:885)) - (PORT datab (384:384:384) (412:412:412)) - (PORT datac (335:335:335) (361:361:361)) - (PORT datad (1833:1833:1833) (1945:1945:1945)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1179:1179:1179) (1212:1212:1212)) + (PORT datab (290:290:290) (355:355:355)) + (PORT datac (254:254:254) (314:314:314)) + (PORT datad (246:246:246) (292:292:292)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19705,88 +21250,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) (DELAY (ABSOLUTE - (PORT dataa (1266:1266:1266) (1361:1361:1361)) - (PORT datab (1624:1624:1624) (1653:1653:1653)) - (PORT datac (566:566:566) (574:574:574)) - (PORT datad (2330:2330:2330) (2371:2371:2371)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (654:654:654)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (367:367:367) (380:380:380)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (359:359:359) (395:395:395)) + (PORT datac (927:927:927) (982:982:982)) + (PORT datad (676:676:676) (714:714:714)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (725:725:725) (773:773:773)) - (PORT datab (703:703:703) (750:750:750)) - (PORT datac (581:581:581) (620:620:620)) - (PORT datad (590:590:590) (603:603:603)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (813:813:813)) - (PORT datab (818:818:818) (831:831:831)) - (PORT datac (724:724:724) (732:732:732)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (904:904:904) (999:999:999)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (INSTANCE z80_\|alu_\|op1_high\[0\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) + (PORT clk (1530:1530:1530) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1021:1021:1021) (1037:1037:1037)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -19797,11 +21280,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) (DELAY (ABSOLUTE - (PORT datac (1742:1742:1742) (1862:1862:1862)) - (PORT datad (1338:1338:1338) (1358:1358:1358)) + (PORT dataa (636:636:636) (695:695:695)) + (PORT datab (1175:1175:1175) (1218:1218:1218)) + (PORT datac (649:649:649) (707:707:707)) + (PORT datad (660:660:660) (719:719:719)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19809,119 +21296,208 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (INSTANCE z80_\|alu_\|db_high\[0\]\~25) (DELAY (ABSOLUTE - (PORT dataa (871:871:871) (888:888:888)) - (PORT datab (1062:1062:1062) (1095:1095:1095)) - (PORT datac (1018:1018:1018) (1057:1057:1057)) - (PORT datad (1424:1424:1424) (1509:1509:1509)) + (PORT dataa (598:598:598) (629:629:629)) + (PORT datab (329:329:329) (356:356:356)) + (PORT datac (1163:1163:1163) (1203:1203:1203)) + (PORT datad (530:530:530) (548:548:548)) (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (679:679:679)) + (PORT datab (998:998:998) (1032:1032:1032)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (220:220:220) (263:263:263)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (555:555:555) (585:585:585)) + (PORT dataa (594:594:594) (621:621:621)) + (PORT datab (963:963:963) (1009:1009:1009)) + (PORT datac (864:864:864) (907:907:907)) + (PORT datad (337:337:337) (357:357:357)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (674:674:674) (713:713:713)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (963:963:963)) + (PORT datab (719:719:719) (762:762:762)) + (PORT datac (929:929:929) (980:980:980)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) (PORT ena (790:790:790) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) (DELAY (ABSOLUTE - (PORT datac (776:776:776) (789:789:789)) - (PORT datad (228:228:228) (267:267:267)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (647:647:647) (678:678:678)) + (PORT datab (640:640:640) (697:697:697)) + (PORT datac (608:608:608) (646:646:646)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (648:648:648)) + (PORT datab (935:935:935) (984:984:984)) + (PORT datac (1093:1093:1093) (1149:1149:1149)) + (PORT datad (575:575:575) (595:595:595)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (869:869:869) (913:913:913)) - (PORT datab (219:219:219) (259:259:259)) - (PORT datad (605:605:605) (619:619:619)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (263:263:263) (339:339:339)) + (PORT datac (171:171:171) (204:204:204)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) + (INSTANCE z80_\|alu_\|op2_low\[0\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT clk (1529:1529:1529) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (845:845:845) (899:899:899)) - (PORT datab (730:730:730) (810:810:810)) - (PORT datac (674:674:674) (748:748:748)) - (PORT datad (1031:1031:1031) (1033:1033:1033)) + (PORT dataa (431:431:431) (524:524:524)) + (PORT datac (650:650:650) (711:711:711)) + (PORT datad (658:658:658) (684:684:684)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (600:600:600)) + (PORT datab (826:826:826) (830:830:830)) + (PORT datac (805:805:805) (806:806:806)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (712:712:712)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (203:203:203) (240:240:240)) + (PORT datad (818:818:818) (831:831:831)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (676:676:676)) + (PORT datab (632:632:632) (684:684:684)) + (PORT datad (630:630:630) (672:672:672)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1124:1124:1124) (1174:1174:1174)) - (PORT datab (1092:1092:1092) (1102:1102:1102)) - (PORT datac (686:686:686) (764:764:764)) - (PORT datad (817:817:817) (856:856:856)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (613:613:613)) - (PORT datab (604:604:604) (630:630:630)) - (PORT datad (574:574:574) (583:583:583)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -19931,28 +21507,12 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (1400:1400:1400) (1433:1433:1433)) - (PORT datab (717:717:717) (793:793:793)) - (PORT datac (1095:1095:1095) (1134:1134:1134)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1115:1115:1115) (1150:1150:1150)) - (PORT datab (1184:1184:1184) (1256:1256:1256)) - (PORT datac (1025:1025:1025) (1066:1066:1066)) - (PORT datad (1151:1151:1151) (1166:1166:1166)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (683:683:683) (704:704:704)) + (PORT datab (860:860:860) (876:876:876)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (515:515:515) (526:526:526)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19960,28 +21520,128 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~16) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) (DELAY (ABSOLUTE - (PORT dataa (765:765:765) (794:794:794)) - (PORT datab (250:250:250) (309:309:309)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (845:845:845) (863:863:863)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT dataa (206:206:206) (252:252:252)) + (PORT datab (213:213:213) (257:257:257)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (690:690:690)) + (PORT datab (662:662:662) (696:696:696)) + (PORT datad (604:604:604) (655:655:655)) + (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (405:405:405)) + (PORT datab (638:638:638) (659:659:659)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (830:830:830) (837:837:837)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (410:410:410)) + (PORT datab (394:394:394) (423:423:423)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (368:368:368) (390:390:390)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT datac (1740:1740:1740) (1766:1766:1766)) + (PORT datad (822:822:822) (836:836:836)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (410:410:410)) + (PORT datab (234:234:234) (279:279:279)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (236:236:236) (281:281:281)) + (PORT datac (354:354:354) (379:379:379)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) + (PORT datad (1068:1068:1068) (1102:1102:1102)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -19992,12 +21652,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (934:934:934) (951:951:951)) - (PORT ena (790:790:790) (782:782:782)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1435:1435:1435) (1482:1482:1482)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20008,209 +21668,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~10) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (328:328:328)) - (PORT datab (938:938:938) (1006:1006:1006)) - (PORT datad (574:574:574) (588:588:588)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (330:330:330)) - (PORT datab (454:454:454) (489:489:489)) - (PORT datac (332:332:332) (350:350:350)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT datab (1937:1937:1937) (2030:2030:2030)) - (PORT datac (750:750:750) (755:755:755)) - (PORT datad (1021:1021:1021) (1040:1040:1040)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1243:1243:1243) (1278:1278:1278)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (910:910:910)) - (PORT datab (1657:1657:1657) (1747:1747:1747)) - (PORT datad (1246:1246:1246) (1263:1263:1263)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1245:1245:1245) (1281:1281:1281)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (694:694:694)) - (PORT datab (878:878:878) (942:942:942)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1597:1597:1597) (1712:1712:1712)) - (PORT datab (1294:1294:1294) (1374:1374:1374)) - (PORT datac (1166:1166:1166) (1167:1167:1167)) - (PORT datad (778:778:778) (803:803:803)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (949:949:949) (986:986:986)) - (PORT ena (1450:1450:1450) (1505:1505:1505)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1591:1591:1591) (1714:1714:1714)) - (PORT datab (1291:1291:1291) (1369:1369:1369)) - (PORT datac (1168:1168:1168) (1169:1169:1169)) - (PORT datad (777:777:777) (805:805:805)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (946:946:946) (983:983:983)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (351:351:351)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (582:582:582) (611:611:611)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (1026:1026:1026) (1085:1085:1085)) - (PORT datac (1202:1202:1202) (1229:1229:1229)) - (PORT datad (1355:1355:1355) (1394:1394:1394)) + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (1596:1596:1596) (1648:1648:1648)) + (PORT datad (1179:1179:1179) (1221:1221:1221)) (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1543:1543:1543)) - (PORT asdata (906:906:906) (928:928:928)) - (PORT ena (816:816:816) (813:813:813)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1647:1647:1647) (1718:1718:1718)) + (PORT ena (1214:1214:1214) (1210:1210:1210)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20219,26 +21697,13 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT datab (367:367:367) (405:405:405)) - (PORT datad (216:216:216) (249:249:249)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (687:687:687) (706:706:706)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1644:1644:1644) (1714:1714:1714)) (PORT ena (790:790:790) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -20250,13 +21715,91 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) (DELAY (ABSOLUTE - (PORT dataa (588:588:588) (622:622:622)) - (PORT datab (260:260:260) (308:308:308)) - (PORT datad (1121:1121:1121) (1150:1150:1150)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (902:902:902) (942:942:942)) + (PORT datab (245:245:245) (290:290:290)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1405:1405:1405) (1471:1471:1471)) + (PORT ena (1236:1236:1236) (1273:1273:1273)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (798:798:798)) + (PORT datab (884:884:884) (909:909:909)) + (PORT datad (866:866:866) (902:902:902)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1404:1404:1404) (1472:1472:1472)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1418:1418:1418)) + (PORT datab (1167:1167:1167) (1217:1217:1217)) + (PORT datad (238:238:238) (279:279:279)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -20265,90 +21808,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) (DELAY (ABSOLUTE - (PORT dataa (1266:1266:1266) (1361:1361:1361)) - (PORT datab (1626:1626:1626) (1652:1652:1652)) - (PORT datac (584:584:584) (621:621:621)) - (PORT datad (2332:2332:2332) (2373:2373:2373)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (926:926:926) (946:946:946)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT datab (1781:1781:1781) (1900:1900:1900)) - (PORT datac (881:881:881) (893:893:893)) - (PORT datad (1338:1338:1338) (1358:1358:1358)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (928:928:928) (949:949:949)) - (PORT ena (1472:1472:1472) (1481:1481:1481)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (283:283:283) (349:349:349)) - (PORT datab (701:701:701) (739:739:739)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (858:858:858)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (348:348:348) (375:375:375)) - (PORT datad (575:575:575) (582:582:582)) + (PORT dataa (820:820:820) (843:843:843)) + (PORT datab (1070:1070:1070) (1130:1130:1130)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (172:172:172) (198:198:198)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -20358,12 +21824,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1242:1242:1242) (1269:1269:1269)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1442:1442:1442) (1490:1490:1490)) + (PORT ena (990:990:990) (994:994:994)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20374,12 +21840,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1238:1238:1238) (1265:1265:1265)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1439:1439:1439) (1490:1490:1490)) + (PORT ena (973:973:973) (964:964:964)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20390,13 +21856,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) (DELAY (ABSOLUTE - (PORT dataa (384:384:384) (462:462:462)) - (PORT datab (696:696:696) (732:732:732)) - (PORT datad (659:659:659) (676:676:676)) - (IOPATH dataa combout (339:339:339) (367:367:367)) + (PORT dataa (466:466:466) (523:523:523)) + (PORT datab (492:492:492) (536:536:536)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -20405,28 +21871,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1249:1249:1249) (1287:1287:1287)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1246:1246:1246) (1284:1284:1284)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1377:1377:1377) (1423:1423:1423)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20437,57 +21887,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~20) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (PORT datab (705:705:705) (754:754:754)) - (PORT datad (682:682:682) (728:728:728)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (561:561:561) (568:568:568)) - (PORT datad (837:837:837) (833:833:833)) + (PORT dataa (938:938:938) (994:994:994)) + (PORT datab (1222:1222:1222) (1294:1294:1294)) + (PORT datad (881:881:881) (941:941:941)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (1530:1530:1530) (1642:1642:1642)) - (PORT datab (365:365:365) (386:386:386)) - (PORT datac (807:807:807) (824:824:824)) - (PORT datad (601:601:601) (615:615:615)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (897:897:897) (916:916:916)) - (PORT ena (816:816:816) (813:813:813)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1195:1195:1195) (1249:1249:1249)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1195:1195:1195) (1248:1248:1248)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20498,12 +21934,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) (DELAY (ABSOLUTE - (PORT dataa (858:858:858) (899:899:899)) - (PORT datab (246:246:246) (294:294:294)) - (PORT datad (1247:1247:1247) (1246:1246:1246)) + (PORT dataa (924:924:924) (985:985:985)) + (PORT datab (910:910:910) (988:988:988)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (410:410:410)) + (PORT datab (634:634:634) (661:661:661)) + (PORT datac (637:637:637) (673:673:673)) + (PORT datad (789:789:789) (853:853:853)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (1138:1138:1138) (1178:1178:1178)) + (PORT ena (935:935:935) (924:924:924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (407:407:407) (446:446:446)) + (PORT datad (387:387:387) (422:422:422)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -20513,12 +21996,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1021:1021:1021) (1037:1037:1037)) + (PORT ena (1308:1308:1308) (1303:1303:1303)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20529,14 +22012,2644 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (860:860:860)) + (PORT datac (214:214:214) (289:289:289)) + (PORT datad (646:646:646) (672:672:672)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (634:634:634)) + (PORT datab (906:906:906) (933:933:933)) + (PORT datac (239:239:239) (322:322:322)) + (PORT datad (576:576:576) (636:636:636)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT datac (258:258:258) (345:345:345)) + (PORT datad (187:187:187) (220:220:220)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1405:1405:1405) (1477:1477:1477)) + (PORT ena (1261:1261:1261) (1299:1299:1299)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1151:1151:1151)) + (PORT datab (881:881:881) (915:915:915)) + (PORT datad (665:665:665) (744:744:744)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (2052:2052:2052) (2111:2111:2111)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1654:1654:1654)) + (PORT datab (1164:1164:1164) (1211:1211:1211)) + (PORT datad (231:231:231) (271:271:271)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1101:1101:1101) (1166:1166:1166)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1418:1418:1418) (1481:1481:1481)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (459:459:459)) + (PORT datab (1594:1594:1594) (1651:1651:1651)) + (PORT datad (1178:1178:1178) (1221:1221:1221)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1799:1799:1799) (1855:1855:1855)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1406:1406:1406) (1476:1476:1476)) + (PORT ena (1131:1131:1131) (1098:1098:1098)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (478:478:478)) + (PORT datab (881:881:881) (916:916:916)) + (PORT datad (364:364:364) (384:384:384)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (338:338:338) (368:368:368)) + (PORT datac (804:804:804) (808:808:808)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1448:1448:1448) (1498:1498:1498)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1448:1448:1448) (1501:1501:1501)) + (PORT ena (990:990:990) (994:994:994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (518:518:518)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (458:458:458) (504:504:504)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1721:1721:1721) (1779:1779:1779)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1723:1723:1723) (1782:1782:1782)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (989:989:989)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datad (883:883:883) (941:941:941)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1771:1771:1771) (1829:1829:1829)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (989:989:989)) + (PORT datab (1220:1220:1220) (1296:1296:1296)) + (PORT datad (884:884:884) (944:944:944)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (699:699:699)) + (PORT datab (825:825:825) (869:869:869)) + (PORT datac (606:606:606) (632:632:632)) + (PORT datad (842:842:842) (848:848:848)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (946:946:946)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datac (817:817:817) (863:863:863)) + (PORT datad (1298:1298:1298) (1332:1332:1332)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (1159:1159:1159) (1205:1205:1205)) + (PORT ena (935:935:935) (924:924:924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (459:459:459)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datad (386:386:386) (413:413:413)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1308:1308:1308) (1303:1303:1303)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (716:716:716)) + (PORT datab (379:379:379) (421:421:421)) + (PORT datac (215:215:215) (292:292:292)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (582:582:582)) + (PORT datab (844:844:844) (883:883:883)) + (PORT datac (682:682:682) (722:722:722)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT datab (383:383:383) (425:425:425)) + (PORT datac (886:886:886) (918:918:918)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (335:335:335) (352:352:352)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1561:1561:1561)) + (PORT ena (2058:2058:2058) (2109:2109:2109)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (DELAY + (ABSOLUTE + (PORT datac (258:258:258) (345:345:345)) + (PORT datad (869:869:869) (891:891:891)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (DELAY + (ABSOLUTE + (PORT datac (356:356:356) (377:377:377)) + (PORT datad (867:867:867) (889:889:889)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1561:1561:1561)) + (PORT ena (2058:2058:2058) (2109:2109:2109)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (385:385:385)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (245:245:245) (326:326:326)) + (PORT datad (866:866:866) (891:891:891)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1308:1308:1308) (1303:1303:1303)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (2284:2284:2284) (2422:2422:2422)) + (PORT ena (990:990:990) (994:994:994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (2284:2284:2284) (2422:2422:2422)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (524:524:524)) + (PORT datab (491:491:491) (541:541:541)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1879:1879:1879) (1975:1975:1975)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (835:835:835)) + (PORT datab (1168:1168:1168) (1216:1216:1216)) + (PORT datad (239:239:239) (281:281:281)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1192:1192:1192) (1258:1258:1258)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (2131:2131:2131) (2211:2211:2211)) + (PORT ena (1131:1131:1131) (1098:1098:1098)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (460:460:460)) + (PORT datab (883:883:883) (917:917:917)) + (PORT datad (364:364:364) (384:384:384)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1453:1453:1453) (1497:1497:1497)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1453:1453:1453) (1497:1497:1497)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1353:1353:1353)) + (PORT datab (1218:1218:1218) (1255:1255:1255)) + (PORT datad (214:214:214) (282:282:282)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (2133:2133:2133) (2211:2211:2211)) + (PORT ena (1261:1261:1261) (1299:1299:1299)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1146:1146:1146)) + (PORT datab (681:681:681) (756:756:756)) + (PORT datad (848:848:848) (874:874:874)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (624:624:624)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (595:595:595) (612:612:612)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1205:1205:1205) (1270:1270:1270)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1205:1205:1205) (1270:1270:1270)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (985:985:985)) + (PORT datab (912:912:912) (982:982:982)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (2162:2162:2162) (2212:2212:2212)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (997:997:997)) + (PORT datab (1220:1220:1220) (1296:1296:1296)) + (PORT datad (879:879:879) (940:940:940)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (650:650:650)) + (PORT datab (632:632:632) (657:657:657)) + (PORT datac (489:489:489) (507:507:507)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (944:944:944)) + (PORT datab (672:672:672) (688:688:688)) + (PORT datac (786:786:786) (839:839:839)) + (PORT datad (1301:1301:1301) (1333:1333:1333)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (1132:1132:1132) (1183:1183:1183)) + (PORT ena (935:935:935) (924:924:924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (466:466:466)) + (PORT datab (218:218:218) (258:258:258)) + (PORT datad (382:382:382) (412:412:412)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (332:332:332)) + (PORT datab (670:670:670) (688:688:688)) + (PORT datad (645:645:645) (672:672:672)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (401:401:401)) + (PORT datab (712:712:712) (754:754:754)) + (PORT datac (808:808:808) (840:840:840)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (955:955:955)) + (PORT datac (361:361:361) (395:395:395)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (320:320:320) (331:331:331)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1561:1561:1561)) + (PORT ena (2058:2058:2058) (2109:2109:2109)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1169:1169:1169)) + (PORT datab (404:404:404) (477:477:477)) + (PORT datac (1110:1110:1110) (1117:1117:1117)) + (PORT datad (632:632:632) (663:663:663)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (214:214:214) (258:258:258)) + (PORT datac (232:232:232) (316:316:316)) + (PORT datad (339:339:339) (360:360:360)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (417:417:417)) + (PORT datab (712:712:712) (760:760:760)) + (PORT datac (814:814:814) (847:847:847)) + (PORT datad (550:550:550) (569:569:569)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (950:950:950)) + (PORT datab (664:664:664) (704:704:704)) + (PORT datac (792:792:792) (834:834:834)) + (PORT datad (1297:1297:1297) (1337:1337:1337)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1347:1347:1347)) + (PORT datab (973:973:973) (1026:1026:1026)) + (PORT datac (1877:1877:1877) (1946:1946:1946)) + (PORT datad (831:831:831) (844:844:844)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (256:256:256) (314:314:314)) + (PORT datac (1193:1193:1193) (1204:1204:1204)) + (PORT datad (945:945:945) (989:989:989)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (970:970:970)) + (PORT datab (1223:1223:1223) (1296:1296:1296)) + (PORT datac (905:905:905) (924:924:924)) + (PORT datad (1385:1385:1385) (1451:1451:1451)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (902:902:902)) + (PORT datab (661:661:661) (697:697:697)) + (PORT datac (670:670:670) (697:697:697)) + (PORT datad (675:675:675) (694:694:694)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1512:1512:1512) (1612:1612:1612)) + (PORT datab (1393:1393:1393) (1508:1508:1508)) + (PORT datac (1411:1411:1411) (1459:1459:1459)) + (PORT datad (835:835:835) (870:870:870)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (635:635:635)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (1083:1083:1083) (1127:1127:1127)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1199:1199:1199)) + (PORT datab (1007:1007:1007) (1063:1063:1063)) + (PORT datac (212:212:212) (252:252:252)) + (PORT datad (1995:1995:1995) (2085:2085:2085)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (260:260:260)) + (PORT datab (634:634:634) (650:650:650)) + (PORT datac (599:599:599) (616:616:616)) + (PORT datad (610:610:610) (626:626:626)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (701:701:701) (761:761:761)) + (PORT datac (1331:1331:1331) (1352:1352:1352)) + (PORT datad (1148:1148:1148) (1179:1179:1179)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1693:1693:1693) (1732:1732:1732)) + (PORT datab (1474:1474:1474) (1569:1569:1569)) + (PORT datac (2562:2562:2562) (2664:2664:2664)) + (PORT datad (1898:1898:1898) (2017:2017:2017)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1942:1942:1942) (2062:2062:2062)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (918:918:918) (965:965:965)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (664:664:664)) + (PORT datab (640:640:640) (658:658:658)) + (PORT datad (880:880:880) (936:936:936)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1199:1199:1199) (1286:1286:1286)) + (PORT datab (255:255:255) (340:340:340)) + (PORT datac (1353:1353:1353) (1415:1415:1415)) + (PORT datad (1199:1199:1199) (1262:1262:1262)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datad (1171:1171:1171) (1244:1244:1244)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (259:259:259)) + (PORT datac (882:882:882) (919:919:919)) + (PORT datad (1382:1382:1382) (1453:1453:1453)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (442:442:442)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (896:896:896) (932:932:932)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (511:511:511)) + (PORT datab (1166:1166:1166) (1210:1210:1210)) + (PORT datac (593:593:593) (646:646:646)) + (PORT datad (662:662:662) (719:719:719)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1208:1208:1208)) + (PORT datab (281:281:281) (344:344:344)) + (PORT datac (245:245:245) (304:304:304)) + (PORT datad (256:256:256) (301:301:301)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (378:378:378)) + (PORT datab (802:802:802) (831:831:831)) + (PORT datac (498:498:498) (504:504:504)) + (PORT datad (1104:1104:1104) (1147:1147:1147)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (639:639:639)) + (PORT datab (999:999:999) (1033:1033:1033)) + (PORT datac (589:589:589) (604:604:604)) + (PORT datad (221:221:221) (264:264:264)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (404:404:404)) + (PORT datab (893:893:893) (942:942:942)) + (PORT datac (1167:1167:1167) (1166:1166:1166)) + (PORT datad (680:680:680) (715:715:715)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (756:756:756)) + (PORT datab (1177:1177:1177) (1222:1222:1222)) + (PORT datac (613:613:613) (678:678:678)) + (PORT datad (666:666:666) (725:725:725)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (DELAY + (ABSOLUTE + (PORT datab (288:288:288) (350:350:350)) + (PORT datad (251:251:251) (296:296:296)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (347:347:347)) + (PORT datab (620:620:620) (638:638:638)) + (PORT datac (1141:1141:1141) (1167:1167:1167)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1287:1287:1287)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (996:996:996)) + (PORT datac (1660:1660:1660) (1742:1742:1742)) + (PORT datad (1418:1418:1418) (1445:1445:1445)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1168:1168:1168)) + (PORT datab (1129:1129:1129) (1182:1182:1182)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (241:241:241) (282:282:282)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (538:538:538)) + (PORT datab (879:879:879) (956:956:956)) + (PORT datac (959:959:959) (990:990:990)) + (PORT datad (594:594:594) (608:608:608)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1243:1243:1243)) + (PORT datab (609:609:609) (645:645:645)) + (PORT datac (193:193:193) (235:235:235)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (695:695:695)) + (PORT datab (912:912:912) (959:959:959)) + (PORT datac (854:854:854) (883:883:883)) + (PORT datad (1144:1144:1144) (1179:1179:1179)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (678:678:678)) + (PORT datab (961:961:961) (1023:1023:1023)) + (PORT datac (1152:1152:1152) (1178:1178:1178)) + (PORT datad (225:225:225) (270:270:270)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (279:279:279)) + (PORT datab (1448:1448:1448) (1517:1517:1517)) + (PORT datac (1115:1115:1115) (1163:1163:1163)) + (PORT datad (178:178:178) (206:206:206)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1261:1261:1261)) + (PORT datab (930:930:930) (959:959:959)) + (PORT datac (533:533:533) (553:553:553)) + (PORT datad (844:844:844) (856:856:856)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1548:1548:1548)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (235:235:235) (277:277:277)) + (PORT datad (1401:1401:1401) (1453:1453:1453)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (663:663:663)) + (PORT datab (615:615:615) (664:664:664)) + (PORT datac (664:664:664) (693:693:693)) + (PORT datad (680:680:680) (701:701:701)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datab (614:614:614) (644:644:644)) + (PORT datad (801:801:801) (877:877:877)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (665:665:665)) + (PORT datab (2306:2306:2306) (2385:2385:2385)) + (PORT datac (2054:2054:2054) (2198:2198:2198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (426:426:426)) + (PORT datab (1624:1624:1624) (1701:1701:1701)) + (PORT datac (829:829:829) (848:848:848)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (877:877:877)) + (PORT datab (360:360:360) (396:396:396)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (1002:1002:1002)) + (PORT datab (692:692:692) (710:710:710)) + (PORT datac (563:563:563) (586:586:586)) + (PORT datad (616:616:616) (630:630:630)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (957:957:957) (981:981:981)) + (PORT datac (645:645:645) (694:694:694)) + (PORT datad (656:656:656) (712:712:712)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (378:378:378)) + (PORT datab (209:209:209) (251:251:251)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (652:652:652) (692:692:692)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (904:904:904)) + (PORT datab (994:994:994) (1026:1026:1026)) + (PORT datac (1433:1433:1433) (1520:1520:1520)) + (PORT datad (1142:1142:1142) (1160:1160:1160)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (697:697:697)) + (PORT datab (936:936:936) (950:950:950)) + (PORT datac (1455:1455:1455) (1497:1497:1497)) + (PORT datad (1163:1163:1163) (1183:1183:1183)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (638:638:638)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (881:881:881) (909:909:909)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT datab (1639:1639:1639) (1704:1704:1704)) + (PORT datac (1440:1440:1440) (1481:1481:1481)) + (PORT datad (1160:1160:1160) (1199:1199:1199)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (500:500:500)) + (PORT datab (1223:1223:1223) (1282:1282:1282)) + (PORT datac (1145:1145:1145) (1179:1179:1179)) + (PORT datad (899:899:899) (938:938:938)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (917:917:917)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (870:870:870) (900:900:900)) + (PORT datad (616:616:616) (665:665:665)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (647:647:647)) + (PORT datab (247:247:247) (295:295:295)) + (PORT datac (1154:1154:1154) (1184:1184:1184)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (512:512:512)) + (PORT datab (1141:1141:1141) (1188:1188:1188)) + (PORT datad (1463:1463:1463) (1479:1479:1479)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (486:486:486)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1618:1618:1618) (1617:1617:1617)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) + (DELAY + (ABSOLUTE + (PORT datab (353:353:353) (390:390:390)) + (PORT datac (784:784:784) (794:794:794)) + (PORT datad (320:320:320) (341:341:341)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (970:970:970) (1022:1022:1022)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (970:970:970) (1022:1022:1022)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (336:336:336)) + (PORT datab (975:975:975) (1029:1029:1029)) + (PORT datad (845:845:845) (875:875:875)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (868:868:868) (877:877:877)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (869:869:869) (877:877:877)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (333:333:333)) + (PORT datab (260:260:260) (314:314:314)) + (PORT datad (229:229:229) (267:267:267)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (870:870:870)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datac (607:607:607) (626:626:626)) + (PORT datad (625:625:625) (639:639:639)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (895:895:895)) + (PORT datab (609:609:609) (627:627:627)) + (PORT datac (332:332:332) (359:359:359)) + (PORT datad (1115:1115:1115) (1138:1138:1138)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (957:957:957) (1002:1002:1002)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1331:1331:1331) (1374:1374:1374)) + (PORT datab (697:697:697) (731:731:731)) + (PORT datad (1194:1194:1194) (1238:1238:1238)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (669:669:669)) + (PORT datac (704:704:704) (742:742:742)) + (PORT datad (220:220:220) (290:290:290)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (401:401:401)) + (PORT datab (960:960:960) (999:999:999)) + (PORT datac (683:683:683) (718:718:718)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT datab (240:240:240) (286:286:286)) + (PORT datac (548:548:548) (560:560:560)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT asdata (870:870:870) (882:882:882)) + (PORT clrn (1597:1597:1597) (1572:1572:1572)) + (PORT ena (2143:2143:2143) (2210:2210:2210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (429:429:429)) + (PORT datab (1153:1153:1153) (1183:1183:1183)) + (PORT datac (963:963:963) (1032:1032:1032)) + (PORT datad (244:244:244) (316:316:316)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (392:392:392)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (340:340:340) (367:367:367)) + (PORT datad (324:324:324) (346:346:346)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (352:352:352)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (332:332:332) (358:358:358)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1239:1239:1239) (1260:1260:1260)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1236:1236:1236) (1256:1256:1256)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (258:258:258) (310:310:310)) + (PORT datad (228:228:228) (266:266:266)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (663:663:663)) + (PORT datab (1133:1133:1133) (1182:1182:1182)) + (PORT datad (630:630:630) (644:644:644)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1202:1202:1202) (1222:1222:1222)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1206:1206:1206) (1227:1227:1227)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (466:466:466)) + (PORT datab (591:591:591) (631:631:631)) + (PORT datad (218:218:218) (288:288:288)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1505:1505:1505) (1518:1518:1518)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (958:958:958) (967:967:967)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (960:960:960) (969:969:969)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (505:505:505)) + (PORT datab (668:668:668) (703:703:703)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (665:665:665)) + (PORT datab (920:920:920) (943:943:943)) + (PORT datac (213:213:213) (288:288:288)) + (PORT datad (335:335:335) (356:356:356)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (993:993:993) (1020:1020:1020)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (995:995:995) (1022:1022:1022)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (922:922:922)) + (PORT datab (965:965:965) (1021:1021:1021)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (984:984:984) (1006:1006:1006)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (982:982:982) (1003:1003:1003)) + (PORT ena (1220:1220:1220) (1214:1214:1214)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (700:700:700)) + (PORT datab (396:396:396) (436:436:436)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (875:875:875) (882:882:882)) + (PORT ena (1407:1407:1407) (1382:1382:1382)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (547:547:547)) + (PORT datad (825:825:825) (835:835:835)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (377:377:377)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1018:1018:1018) (1019:1019:1019)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) (DELAY (ABSOLUTE (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (242:242:242) (281:281:281)) - (PORT datad (414:414:414) (486:486:486)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (856:856:856) (875:875:875)) + (PORT datac (1094:1094:1094) (1126:1126:1126)) + (PORT datad (1162:1162:1162) (1190:1190:1190)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1359:1359:1359) (1370:1370:1370)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (911:911:911)) + (PORT datab (1236:1236:1236) (1275:1275:1275)) + (PORT datad (664:664:664) (688:688:688)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (624:624:624) (675:675:675)) + (PORT datac (704:704:704) (739:739:739)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (401:401:401)) + (PORT datab (959:959:959) (1001:1001:1001)) + (PORT datac (682:682:682) (721:721:721)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -20546,9 +24659,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[4\]) (DELAY (ABSOLUTE - (PORT datac (873:873:873) (909:909:909)) - (PORT datad (1286:1286:1286) (1372:1372:1372)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (238:238:238) (283:283:283)) + (PORT datad (529:529:529) (540:540:540)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -20558,10 +24671,10 @@ (INSTANCE z80_\|address_latch_\|Q\[4\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1542:1542:1542)) - (PORT asdata (538:538:538) (569:569:569)) - (PORT clrn (1569:1569:1569) (1549:1549:1549)) - (PORT ena (2195:2195:2195) (2230:2230:2230)) + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT asdata (852:852:852) (858:858:858)) + (PORT clrn (1597:1597:1597) (1572:1572:1572)) + (PORT ena (2143:2143:2143) (2210:2210:2210)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -20576,10 +24689,13 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) (DELAY (ABSOLUTE - (PORT datab (1084:1084:1084) (1121:1121:1121)) - (PORT datac (858:858:858) (982:982:982)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1155:1155:1155) (1182:1182:1182)) + (PORT datab (985:985:985) (1022:1022:1022)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -20588,71 +24704,12 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) (DELAY (ABSOLUTE - (PORT dataa (902:902:902) (956:956:956)) - (PORT datab (888:888:888) (1023:1023:1023)) - (PORT datac (1051:1051:1051) (1089:1089:1089)) - (PORT datad (673:673:673) (758:758:758)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT dataa (710:710:710) (770:770:770)) + (PORT datab (1162:1162:1162) (1199:1199:1199)) + (PORT datac (626:626:626) (647:647:647)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (928:928:928) (951:951:951)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1228:1228:1228) (1255:1255:1255)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (709:709:709) (761:761:761)) - (PORT datad (681:681:681) (734:734:734)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -20661,9 +24718,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1855:1855:1855) (1878:1878:1878)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (879:879:879) (891:891:891)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20677,9 +24734,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1852:1852:1852) (1873:1873:1873)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (878:878:878) (893:893:893)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20693,9 +24750,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) (DELAY (ABSOLUTE - (PORT dataa (391:391:391) (463:463:463)) - (PORT datab (702:702:702) (741:741:741)) - (PORT datad (662:662:662) (685:685:685)) + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (966:966:966) (1022:1022:1022)) + (PORT datad (843:843:843) (873:873:873)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -20705,12 +24762,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1010:1010:1010) (1031:1031:1031)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (692:692:692) (715:715:715)) + (PORT ena (1477:1477:1477) (1472:1472:1472)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20721,12 +24778,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1010:1010:1010) (1030:1030:1030)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (692:692:692) (713:713:713)) + (PORT ena (1247:1247:1247) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20737,71 +24794,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) (DELAY (ABSOLUTE - (PORT dataa (664:664:664) (695:695:695)) - (PORT datab (871:871:871) (938:938:938)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1202:1202:1202) (1230:1230:1230)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1543:1543:1543)) - (PORT asdata (954:954:954) (977:977:977)) - (PORT ena (1455:1455:1455) (1491:1491:1491)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (677:677:677)) - (PORT datab (648:648:648) (697:697:697)) - (PORT datad (581:581:581) (600:600:600)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1095:1095:1095) (1134:1134:1134)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (658:658:658) (679:679:679)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20809,12 +24809,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (544:544:544) (580:580:580)) - (PORT ena (1475:1475:1475) (1471:1471:1471)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1437:1437:1437) (1460:1460:1460)) + (PORT ena (1505:1505:1505) (1518:1518:1518)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20823,45 +24823,14 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (927:927:927) (940:940:940)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (996:996:996)) - (PORT datab (901:901:901) (917:917:917)) - (PORT datad (235:235:235) (274:274:274)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (725:725:725) (752:752:752)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1457:1457:1457) (1472:1472:1472)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20875,11 +24844,24 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) (DELAY (ABSOLUTE - (PORT dataa (279:279:279) (351:351:351)) - (PORT datab (931:931:931) (974:974:974)) - (PORT datad (813:813:813) (836:836:836)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (458:458:458) (494:494:494)) + (PORT datab (1132:1132:1132) (1177:1177:1177)) + (PORT datad (626:626:626) (636:636:636)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT datab (918:918:918) (940:940:940)) + (PORT datad (338:338:338) (359:359:359)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20887,12 +24869,28 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1543:1543:1543)) - (PORT asdata (953:953:953) (974:974:974)) - (PORT ena (816:816:816) (813:813:813)) + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1214:1214:1214) (1217:1217:1217)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1214:1214:1214) (1215:1215:1215)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20903,12 +24901,128 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) (DELAY (ABSOLUTE - (PORT datab (370:370:370) (407:407:407)) - (PORT datad (216:216:216) (248:248:248)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (409:409:409) (467:467:467)) + (PORT datab (592:592:592) (632:632:632)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1471:1471:1471) (1477:1477:1477)) + (PORT ena (1220:1220:1220) (1214:1214:1214)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (607:607:607) (622:622:622)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (693:693:693)) + (PORT datab (390:390:390) (429:429:429)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (853:853:853) (859:859:859)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1407:1407:1407) (1382:1382:1382)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1457:1457:1457) (1474:1474:1474)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (638:638:638)) + (PORT datab (836:836:836) (860:860:860)) + (PORT datad (645:645:645) (669:669:669)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20919,10 +25033,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) (DELAY (ABSOLUTE - (PORT dataa (809:809:809) (864:864:864)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (343:343:343) (369:369:369)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (638:638:638) (656:656:656)) + (PORT datab (1118:1118:1118) (1148:1148:1148)) + (PORT datac (339:339:339) (359:359:359)) + (PORT datad (587:587:587) (601:601:601)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -20935,11 +25049,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) (DELAY (ABSOLUTE - (PORT dataa (856:856:856) (889:889:889)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datad (823:823:823) (843:843:843)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (372:372:372) (394:394:394)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -20949,13 +25063,13 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) (DELAY (ABSOLUTE - (PORT dataa (1335:1335:1335) (1358:1358:1358)) - (PORT datab (582:582:582) (598:598:598)) - (PORT datac (348:348:348) (373:373:373)) - (PORT datad (1286:1286:1286) (1413:1413:1413)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (639:639:639) (699:699:699)) + (PORT datab (929:929:929) (992:992:992)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1608:1608:1608) (1611:1611:1611)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -20965,9 +25079,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (691:691:691) (714:714:714)) - (PORT ena (816:816:816) (813:813:813)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1227:1227:1227) (1243:1243:1243)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20981,34 +25095,24 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (243:243:243) (289:289:289)) - (PORT datad (1247:1247:1247) (1245:1245:1245)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1190:1190:1190) (1197:1197:1197)) + (PORT datab (1236:1236:1236) (1275:1275:1275)) + (PORT datad (664:664:664) (688:688:688)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (194:194:194) (219:219:219)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1548:1548:1548)) + (PORT clk (1534:1534:1534) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1246:1246:1246) (1261:1261:1261)) + (PORT ena (811:811:811) (804:804:804)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21022,11 +25126,11 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) (DELAY (ABSOLUTE - (PORT dataa (381:381:381) (407:407:407)) - (PORT datac (391:391:391) (417:417:417)) + (PORT dataa (229:229:229) (275:275:275)) + (PORT datac (613:613:613) (632:632:632)) (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21036,11 +25140,11 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) (DELAY (ABSOLUTE - (PORT dataa (1278:1278:1278) (1351:1351:1351)) - (PORT datab (607:607:607) (636:636:636)) - (PORT datac (560:560:560) (589:589:589)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) + (PORT dataa (655:655:655) (670:670:670)) + (PORT datab (1331:1331:1331) (1335:1335:1335)) + (PORT datac (192:192:192) (224:224:224)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -21052,19 +25156,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[5\]) (DELAY (ABSOLUTE - (PORT datac (630:630:630) (659:659:659)) - (PORT datad (1287:1287:1287) (1376:1376:1376)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (194:194:194) (219:219:219)) + (PORT datac (653:653:653) (693:693:693)) + (PORT datad (834:834:834) (843:843:843)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21074,10 +25168,10 @@ (INSTANCE z80_\|address_latch_\|Q\[5\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1542:1542:1542)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1549:1549:1549)) - (PORT ena (2195:2195:2195) (2230:2230:2230)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2152:2152:2152) (2220:2220:2220)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -21089,15 +25183,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) (DELAY (ABSOLUTE - (PORT dataa (610:610:610) (686:686:686)) - (PORT datab (1118:1118:1118) (1165:1165:1165)) - (PORT datac (185:185:185) (228:228:228)) - (PORT datad (1060:1060:1060) (1086:1086:1086)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (369:369:369)) + (PORT dataa (920:920:920) (994:994:994)) + (PORT datab (1154:1154:1154) (1178:1178:1178)) + (PORT datac (960:960:960) (1026:1026:1026)) + (PORT datad (362:362:362) (387:387:387)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21108,10 +25202,10 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) (DELAY (ABSOLUTE - (PORT dataa (902:902:902) (957:957:957)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (607:607:607) (676:676:676)) - (PORT datad (864:864:864) (916:916:916)) + (PORT dataa (657:657:657) (687:687:687)) + (PORT datab (1161:1161:1161) (1198:1198:1198)) + (PORT datac (811:811:811) (865:865:865)) + (PORT datad (615:615:615) (643:643:643)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -21119,16 +25213,449 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1676:1676:1676) (1684:1684:1684)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1342:1342:1342) (1345:1345:1345)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (918:918:918)) + (PORT datab (966:966:966) (1020:1020:1020)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1896:1896:1896) (1881:1881:1881)) + (PORT ena (1477:1477:1477) (1472:1472:1472)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1893:1893:1893) (1878:1878:1878)) + (PORT ena (1247:1247:1247) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1133:1133:1133)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (654:654:654) (676:676:676)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (2168:2168:2168) (2154:2154:2154)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1053:1053:1053) (1073:1073:1073)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (470:470:470)) + (PORT datab (637:637:637) (669:669:669)) + (PORT datad (374:374:374) (432:432:432)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1463:1463:1463) (1454:1454:1454)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (771:771:771)) + (PORT datab (945:945:945) (995:995:995)) + (PORT datac (878:878:878) (894:894:894)) + (PORT datad (606:606:606) (625:625:625)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (2168:2168:2168) (2153:2153:2153)) + (PORT ena (1499:1499:1499) (1507:1507:1507)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1302:1302:1302) (1310:1310:1310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1608:1608:1608) (1628:1628:1628)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (503:503:503)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (640:640:640) (666:666:666)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT datab (1410:1410:1410) (1425:1425:1425)) + (PORT datad (563:563:563) (574:574:574)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1342:1342:1342) (1366:1366:1366)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1430:1430:1430) (1466:1466:1466)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (471:471:471)) + (PORT datab (584:584:584) (622:622:622)) + (PORT datad (835:835:835) (900:900:900)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (399:399:399)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (794:794:794) (791:791:791)) + (PORT datad (776:776:776) (774:774:774)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (625:625:625)) + (PORT datab (658:658:658) (716:716:716)) + (PORT datac (1393:1393:1393) (1416:1416:1416)) + (PORT datad (599:599:599) (618:618:618)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (967:967:967) (1025:1025:1025)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1322:1322:1322) (1350:1350:1350)) + (PORT datab (1232:1232:1232) (1270:1270:1270)) + (PORT datad (660:660:660) (687:687:687)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (673:673:673) (705:705:705)) + (PORT datac (668:668:668) (749:749:749)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) (DELAY (ABSOLUTE - (PORT dataa (617:617:617) (633:633:633)) - (PORT datab (1321:1321:1321) (1345:1345:1345)) - (PORT datac (579:579:579) (597:597:597)) - (PORT datad (1421:1421:1421) (1524:1524:1524)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (714:714:714) (760:760:760)) + (PORT datab (648:648:648) (689:689:689)) + (PORT datac (926:926:926) (965:965:965)) + (PORT datad (593:593:593) (644:644:644)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -21140,9 +25667,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[6\]) (DELAY (ABSOLUTE - (PORT datac (869:869:869) (887:887:887)) - (PORT datad (1213:1213:1213) (1311:1311:1311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datac (652:652:652) (694:694:694)) + (PORT datad (819:819:819) (838:838:838)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21152,10 +25679,10 @@ (INSTANCE z80_\|address_latch_\|Q\[6\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1548:1548:1548)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1564:1564:1564)) - (PORT ena (2593:2593:2593) (2662:2662:2662)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2152:2152:2152) (2220:2220:2220)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -21167,15 +25694,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~2) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) (DELAY (ABSOLUTE - (PORT dataa (1451:1451:1451) (1567:1567:1567)) - (PORT datab (1363:1363:1363) (1443:1443:1443)) - (PORT datac (624:624:624) (674:674:674)) - (PORT datad (600:600:600) (635:635:635)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (628:628:628) (670:670:670)) + (PORT datab (632:632:632) (673:673:673)) + (PORT datac (811:811:811) (863:863:863)) + (PORT datad (1165:1165:1165) (1193:1193:1193)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21186,10 +25713,10 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (662:662:662)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (870:870:870) (916:916:916)) - (PORT datad (863:863:863) (916:916:916)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1158:1158:1158) (1194:1194:1194)) + (PORT datac (628:628:628) (651:651:651)) + (PORT datad (616:616:616) (644:644:644)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -21202,35 +25729,25 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) (DELAY (ABSOLUTE - (PORT datac (902:902:902) (967:967:967)) - (PORT datad (612:612:612) (627:627:627)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (423:423:423) (515:515:515)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1236:1236:1236) (1262:1262:1262)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]\~feeder) + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) (DELAY (ABSOLUTE - (PORT datad (883:883:883) (906:906:906)) + (PORT dataa (708:708:708) (752:752:752)) + (PORT datab (962:962:962) (1002:1002:1002)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (619:619:619) (645:645:645)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21240,40 +25757,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (776:776:776)) - (PORT datab (709:709:709) (761:761:761)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1520:1520:1520) (1559:1559:1559)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1212:1212:1212) (1251:1251:1251)) + (PORT ena (1477:1477:1477) (1472:1472:1472)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21282,14 +25768,61 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1211:1211:1211) (1254:1254:1254)) + (PORT ena (1247:1247:1247) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1137:1137:1137)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (656:656:656) (679:679:679)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1519:1519:1519) (1558:1558:1558)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1408:1408:1408) (1437:1437:1437)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1410:1410:1410) (1439:1439:1439)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21303,11 +25836,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) (DELAY (ABSOLUTE - (PORT dataa (387:387:387) (459:459:459)) - (PORT datab (701:701:701) (738:738:738)) - (PORT datad (659:659:659) (681:681:681)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (876:876:876) (924:924:924)) + (PORT datab (963:963:963) (1013:1013:1013)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21318,9 +25851,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1510:1510:1510) (1548:1548:1548)) - (PORT ena (812:812:812) (804:804:804)) + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (1934:1934:1934) (1968:1968:1968)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21329,71 +25862,24 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1624:1624:1624) (1645:1645:1645)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1509:1509:1509) (1548:1548:1548)) - (PORT ena (1472:1472:1472) (1481:1481:1481)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (281:281:281) (346:346:346)) - (PORT datab (700:700:700) (743:743:743)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (690:690:690) (730:730:730)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (626:626:626) (649:649:649)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) + (PORT clk (1528:1528:1528) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21404,12 +25890,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (949:949:949)) - (PORT datab (354:354:354) (387:387:387)) - (PORT datad (618:618:618) (674:674:674)) + (PORT dataa (435:435:435) (469:469:469)) + (PORT datab (636:636:636) (669:669:669)) + (PORT datad (370:370:370) (429:429:429)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -21419,17 +25905,33 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1450:1450:1450) (1505:1505:1505)) + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (1932:1932:1932) (1967:1967:1967)) + (PORT ena (1499:1499:1499) (1507:1507:1507)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1954:1954:1954) (1989:1989:1989)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -21438,9 +25940,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (686:686:686) (713:713:713)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1954:1954:1954) (1989:1989:1989)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21454,9 +25956,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) (DELAY (ABSOLUTE - (PORT dataa (274:274:274) (345:345:345)) - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (585:585:585) (613:613:613)) + (PORT dataa (459:459:459) (495:495:495)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (640:640:640) (664:664:664)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -21465,13 +25967,42 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (693:693:693) (730:730:730)) - (PORT ena (1447:1447:1447) (1426:1426:1426)) + (PORT datab (1411:1411:1411) (1427:1427:1427)) + (PORT datad (587:587:587) (598:598:598)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1731:1731:1731) (1772:1772:1772)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1730:1730:1730) (1774:1774:1774)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21482,12 +26013,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) (DELAY (ABSOLUTE - (PORT dataa (344:344:344) (382:382:382)) - (PORT datad (632:632:632) (652:652:652)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (407:407:407) (467:467:467)) + (PORT datab (591:591:591) (631:631:631)) + (PORT datad (216:216:216) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21498,14 +26031,14 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (1766:1766:1766) (1777:1777:1777)) - (PORT ena (790:790:790) (782:782:782)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1463:1463:1463) (1454:1454:1454)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -21514,12 +26047,13 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) (DELAY (ABSOLUTE - (PORT dataa (591:591:591) (624:624:624)) - (PORT datab (258:258:258) (309:309:309)) - (PORT datad (619:619:619) (632:632:632)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (646:646:646) (738:738:738)) + (PORT datab (944:944:944) (996:996:996)) + (PORT datac (844:844:844) (845:845:845)) + (PORT datad (606:606:606) (623:623:623)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21529,10 +26063,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (368:368:368)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (558:558:558) (574:574:574)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (496:496:496) (503:503:503)) + (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -21545,11 +26079,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) (DELAY (ABSOLUTE - (PORT datab (606:606:606) (623:623:623)) - (PORT datac (594:594:594) (601:601:601)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (364:364:364) (385:385:385)) + (PORT datad (573:573:573) (586:586:586)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21559,73 +26093,12 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) (DELAY (ABSOLUTE - (PORT dataa (1283:1283:1283) (1398:1398:1398)) - (PORT datab (1613:1613:1613) (1619:1619:1619)) - (PORT datac (605:605:605) (623:623:623)) - (PORT datad (327:327:327) (344:344:344)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (659:659:659) (677:677:677)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (692:692:692)) - (PORT datab (247:247:247) (295:295:295)) - (PORT datad (1250:1250:1250) (1249:1249:1249)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1246:1246:1246) (1261:1261:1261)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (387:387:387)) - (PORT datac (390:390:390) (416:416:416)) - (PORT datad (215:215:215) (282:282:282)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (667:667:667) (723:723:723)) + (PORT datab (660:660:660) (704:704:704)) + (PORT datac (1391:1391:1391) (1414:1414:1414)) + (PORT datad (597:597:597) (618:618:618)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21633,51 +26106,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1279:1279:1279) (1348:1348:1348)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (561:561:561) (587:587:587)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT datac (614:614:614) (652:652:652)) - (PORT datad (1290:1290:1290) (1377:1377:1377)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (193:193:193) (218:218:218)) + (PORT dataa (1484:1484:1484) (1528:1528:1528)) + (PORT datab (1645:1645:1645) (1711:1711:1711)) + (PORT datac (872:872:872) (914:914:914)) + (PORT datad (1163:1163:1163) (1203:1203:1203)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) + (INSTANCE z80_\|interrupts_\|im2) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1542:1542:1542)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1549:1549:1549)) - (PORT ena (2195:2195:2195) (2230:2230:2230)) + (PORT clrn (1571:1571:1571) (1550:1550:1550)) + (PORT ena (1258:1258:1258) (1280:1280:1280)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -21689,799 +26140,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (INSTANCE z80_\|execute_\|ctl_mRead\~12) (DELAY (ABSOLUTE - (PORT datac (934:934:934) (978:978:978)) - (PORT datad (1211:1211:1211) (1308:1308:1308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1564:1564:1564)) - (PORT ena (2593:2593:2593) (2662:2662:2662)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (279:279:279)) - (PORT datab (1085:1085:1085) (1123:1123:1123)) - (PORT datac (656:656:656) (746:746:746)) - (PORT datad (389:389:389) (450:450:450)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (901:901:901) (912:912:912)) - (PORT datac (1660:1660:1660) (1788:1788:1788)) - (PORT datad (375:375:375) (399:399:399)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1696:1696:1696) (1727:1727:1727)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1696:1696:1696) (1730:1730:1730)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (471:471:471)) - (PORT datab (435:435:435) (466:466:466)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (924:924:924) (940:940:940)) - (PORT ena (1249:1249:1249) (1247:1247:1247)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1216:1216:1216)) - (PORT datab (1875:1875:1875) (1953:1953:1953)) - (PORT datad (1634:1634:1634) (1689:1689:1689)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (979:979:979) (1011:1011:1011)) - (PORT ena (979:979:979) (971:971:971)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (978:978:978) (1015:1015:1015)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (476:476:476)) - (PORT datab (428:428:428) (469:469:469)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1545:1545:1545) (1545:1545:1545)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1336:1336:1336) (1362:1362:1362)) - (PORT datab (1193:1193:1193) (1247:1247:1247)) - (PORT datad (392:392:392) (408:408:408)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (1157:1157:1157) (1167:1167:1167)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (516:516:516)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (665:665:665) (698:698:698)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1233:1233:1233) (1253:1253:1253)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1233:1233:1233) (1251:1251:1251)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (661:661:661) (684:684:684)) - (PORT datad (626:626:626) (645:645:645)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (661:661:661)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (316:316:316) (344:344:344)) - (PORT datad (566:566:566) (577:577:577)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1456:1456:1456) (1478:1478:1478)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1456:1456:1456) (1476:1476:1476)) - (PORT ena (1011:1011:1011) (1021:1021:1021)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (986:986:986)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (229:229:229) (266:266:266)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (661:661:661)) - (PORT datab (370:370:370) (393:393:393)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (795:795:795) (818:818:818)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (632:632:632)) - (PORT datab (1983:1983:1983) (2128:2128:2128)) - (PORT datac (541:541:541) (546:546:546)) - (PORT datad (569:569:569) (582:582:582)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (928:928:928)) - (PORT datab (875:875:875) (899:899:899)) - (PORT datac (1240:1240:1240) (1283:1283:1283)) - (PORT datad (1140:1140:1140) (1157:1157:1157)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1142:1142:1142)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (585:585:585) (607:607:607)) - (PORT datad (227:227:227) (273:273:273)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1171:1171:1171)) - (PORT datab (875:875:875) (926:926:926)) - (PORT datac (1191:1191:1191) (1288:1288:1288)) - (PORT datad (1037:1037:1037) (1115:1115:1115)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (750:750:750) (840:840:840)) - (PORT datab (908:908:908) (961:961:961)) - (PORT datac (1190:1190:1190) (1289:1289:1289)) - (PORT datad (1036:1036:1036) (1115:1115:1115)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (753:753:753) (844:844:844)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (206:206:206)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1231:1231:1231) (1328:1328:1328)) - (PORT datac (872:872:872) (894:894:894)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (1534:1534:1534) (1635:1635:1635)) - (PORT datac (1116:1116:1116) (1137:1137:1137)) - (PORT datad (1296:1296:1296) (1328:1328:1328)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1073:1073:1073) (1101:1101:1101)) - (PORT datab (913:913:913) (937:937:937)) - (PORT datac (919:919:919) (987:987:987)) - (PORT datad (234:234:234) (311:311:311)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (904:904:904)) - (PORT datab (606:606:606) (635:635:635)) - (PORT datac (816:816:816) (834:834:834)) - (PORT datad (819:819:819) (855:855:855)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (419:419:419) (468:468:468)) - (PORT datab (1085:1085:1085) (1112:1112:1112)) - (PORT datac (772:772:772) (787:787:787)) - (PORT datad (234:234:234) (274:274:274)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1545:1545:1545) (1647:1647:1647)) - (PORT datab (1017:1017:1017) (1086:1086:1086)) - (PORT datac (817:817:817) (844:844:844)) - (PORT datad (1826:1826:1826) (1840:1840:1840)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (847:847:847)) - (PORT datab (796:796:796) (840:840:840)) - (PORT datac (824:824:824) (850:850:850)) - (PORT datad (581:581:581) (591:591:591)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (403:403:403)) - (PORT datab (639:639:639) (656:656:656)) - (PORT datad (546:546:546) (556:556:556)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (666:666:666)) - (PORT datab (1369:1369:1369) (1415:1415:1415)) - (PORT datac (1087:1087:1087) (1124:1124:1124)) - (PORT datad (1100:1100:1100) (1103:1103:1103)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (254:254:254)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (899:899:899) (957:957:957)) - (PORT datad (229:229:229) (267:267:267)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1666:1666:1666) (1702:1702:1702)) - (PORT datab (1097:1097:1097) (1153:1153:1153)) - (PORT datac (1117:1117:1117) (1189:1189:1189)) - (PORT datad (2828:2828:2828) (2893:2893:2893)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (1631:1631:1631) (1675:1675:1675)) - (PORT datab (1017:1017:1017) (1087:1087:1087)) - (PORT datac (769:769:769) (779:779:779)) - (PORT datad (1777:1777:1777) (1826:1826:1826)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1548:1548:1548) (1653:1653:1653)) - (PORT datab (610:610:610) (655:655:655)) - (PORT datac (814:814:814) (842:842:842)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (696:696:696)) - (PORT datab (804:804:804) (830:830:830)) - (PORT datac (386:386:386) (427:427:427)) - (PORT datad (839:839:839) (856:856:856)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (868:868:868)) - (PORT datab (884:884:884) (930:930:930)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (231:231:231) (271:271:271)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1208:1208:1208)) - (PORT datab (1193:1193:1193) (1245:1245:1245)) - (PORT datac (823:823:823) (863:863:863)) - (PORT datad (1067:1067:1067) (1124:1124:1124)) + (PORT dataa (354:354:354) (492:492:492)) + (PORT datac (1227:1227:1227) (1295:1295:1295)) + (PORT datad (274:274:274) (356:356:356)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1654:1654:1654) (1773:1773:1773)) - (PORT datab (1786:1786:1786) (1844:1844:1844)) - (PORT datac (801:801:801) (813:813:813)) - (PORT datad (1365:1365:1365) (1419:1419:1419)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (712:712:712)) - (PORT datab (673:673:673) (691:691:691)) - (PORT datac (1202:1202:1202) (1209:1209:1209)) - (PORT datad (848:848:848) (897:897:897)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (2236:2236:2236) (2302:2302:2302)) - (PORT datad (581:581:581) (621:621:621)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -22489,291 +26154,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) (DELAY (ABSOLUTE - (PORT dataa (686:686:686) (713:713:713)) - (PORT datab (228:228:228) (268:268:268)) - (PORT datac (828:828:828) (850:850:850)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1549:1549:1549) (1648:1648:1648)) - (PORT datab (615:615:615) (649:649:649)) - (PORT datac (811:811:811) (841:841:841)) - (PORT datad (1821:1821:1821) (1838:1838:1838)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (640:640:640) (692:692:692)) - (PORT datac (806:806:806) (823:823:823)) - (PORT datad (632:632:632) (683:683:683)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) - (DELAY - (ABSOLUTE - (PORT datac (827:827:827) (853:853:853)) - (PORT datad (204:204:204) (234:234:234)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (946:946:946)) - (PORT datab (884:884:884) (906:906:906)) - (PORT datac (1650:1650:1650) (1728:1728:1728)) - (PORT datad (1132:1132:1132) (1178:1178:1178)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (895:895:895) (937:937:937)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (812:812:812) (850:850:850)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (538:538:538) (562:562:562)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1220:1220:1220)) - (PORT datab (855:855:855) (902:902:902)) - (PORT datad (1062:1062:1062) (1081:1081:1081)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (368:368:368)) - (PORT datab (877:877:877) (890:890:890)) - (PORT datac (1498:1498:1498) (1562:1562:1562)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (973:973:973)) - (PORT datab (900:900:900) (959:959:959)) - (PORT datac (1007:1007:1007) (1018:1018:1018)) - (PORT datad (1008:1008:1008) (1030:1030:1030)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (920:920:920)) - (PORT datab (1384:1384:1384) (1396:1396:1396)) - (PORT datac (215:215:215) (292:292:292)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1183:1183:1183)) - (PORT datab (833:833:833) (886:886:886)) - (PORT datac (986:986:986) (1032:1032:1032)) - (PORT datad (1047:1047:1047) (1094:1094:1094)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1031:1031:1031) (1055:1055:1055)) - (PORT datab (821:821:821) (852:852:852)) - (PORT datac (1064:1064:1064) (1128:1128:1128)) - (PORT datad (1042:1042:1042) (1102:1102:1102)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (917:917:917)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1075:1075:1075) (1098:1098:1098)) - (PORT datad (1428:1428:1428) (1508:1508:1508)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (684:684:684)) - (PORT datab (690:690:690) (711:711:711)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1500:1500:1500)) - (PORT datab (1662:1662:1662) (1684:1684:1684)) - (PORT datac (1606:1606:1606) (1632:1632:1632)) - (PORT datad (601:601:601) (635:635:635)) + (PORT dataa (356:356:356) (494:494:494)) + (PORT datab (716:716:716) (747:747:747)) + (PORT datac (192:192:192) (224:224:224)) + (PORT datad (1301:1301:1301) (1395:1395:1395)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (INSTANCE z80_\|alu_control_\|db\[7\]\~17) (DELAY (ABSOLUTE - (PORT dataa (864:864:864) (893:893:893)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (599:599:599) (634:634:634)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1519:1519:1519) (1574:1574:1574)) - (PORT datab (1443:1443:1443) (1467:1467:1467)) - (PORT datac (1148:1148:1148) (1178:1178:1178)) - (PORT datad (342:342:342) (363:363:363)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (881:881:881) (903:903:903)) + (PORT datab (928:928:928) (957:957:957)) + (PORT datac (631:631:631) (687:687:687)) + (PORT datad (632:632:632) (647:647:647)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -22782,143 +26186,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (INSTANCE z80_\|alu_control_\|db\[7\]\~16) (DELAY (ABSOLUTE - (PORT dataa (1237:1237:1237) (1328:1328:1328)) - (PORT datab (792:792:792) (812:812:812)) - (PORT datac (1586:1586:1586) (1627:1627:1627)) - (PORT datad (1780:1780:1780) (1830:1830:1830)) + (PORT dataa (841:841:841) (861:861:861)) + (PORT datab (852:852:852) (879:879:879)) + (PORT datac (900:900:900) (940:940:940)) + (PORT datad (639:639:639) (700:700:700)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (244:244:244) (291:291:291)) + (PORT datac (645:645:645) (698:698:698)) + (PORT datad (617:617:617) (628:628:628)) (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (539:539:539) (542:542:542)) - (PORT datad (611:611:611) (639:639:639)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (911:911:911)) - (PORT datab (684:684:684) (749:749:749)) - (PORT datac (594:594:594) (652:652:652)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1207:1207:1207)) - (PORT datab (1447:1447:1447) (1536:1536:1536)) - (PORT datac (1951:1951:1951) (2070:2070:2070)) - (PORT datad (1166:1166:1166) (1254:1254:1254)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (945:945:945)) - (PORT datab (226:226:226) (267:267:267)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (948:948:948) (1030:1030:1030)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1491:1491:1491) (1608:1608:1608)) - (PORT datab (856:856:856) (927:927:927)) - (PORT datac (1372:1372:1372) (1428:1428:1428)) - (PORT datad (563:563:563) (590:590:590)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) - (DELAY - (ABSOLUTE - (PORT dataa (913:913:913) (959:959:959)) - (PORT datab (820:820:820) (860:860:860)) - (PORT datac (1128:1128:1128) (1198:1198:1198)) - (PORT datad (1146:1146:1146) (1198:1198:1198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (960:960:960)) - (PORT datab (1138:1138:1138) (1208:1208:1208)) - (PORT datac (1128:1128:1128) (1199:1199:1199)) - (PORT datad (1171:1171:1171) (1285:1285:1285)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (1072:1072:1072)) - (PORT datab (917:917:917) (968:968:968)) - (PORT datac (881:881:881) (904:904:904)) - (PORT datad (2379:2379:2379) (2460:2460:2460)) - (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (738:738:738)) + (PORT datab (889:889:889) (932:932:932)) + (PORT datac (869:869:869) (862:862:862)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -22926,230 +26234,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (853:853:853) (863:863:863)) - (PORT datac (837:837:837) (883:883:883)) - (PORT datad (1625:1625:1625) (1671:1671:1671)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (665:665:665)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (539:539:539) (558:558:558)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1004:1004:1004) (1081:1081:1081)) - (PORT datab (1331:1331:1331) (1350:1350:1350)) - (PORT datac (1167:1167:1167) (1241:1241:1241)) - (PORT datad (1296:1296:1296) (1381:1381:1381)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1084:1084:1084)) - (PORT datab (1335:1335:1335) (1345:1345:1345)) - (PORT datac (859:859:859) (910:910:910)) - (PORT datad (2215:2215:2215) (2297:2297:2297)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (615:615:615)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (938:938:938) (991:991:991)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (611:611:611) (629:629:629)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) - (DELAY - (ABSOLUTE - (PORT datab (1120:1120:1120) (1154:1154:1154)) - (PORT datac (1197:1197:1197) (1192:1192:1192)) - (PORT datad (806:806:806) (838:838:838)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1121:1121:1121)) - (PORT datab (872:872:872) (919:919:919)) - (PORT datac (516:516:516) (526:526:526)) - (PORT datad (1080:1080:1080) (1085:1085:1085)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (683:683:683) (731:731:731)) - (PORT datac (793:793:793) (806:806:806)) + (PORT dataa (1252:1252:1252) (1344:1344:1344)) + (PORT datab (857:857:857) (911:911:911)) + (PORT datac (614:614:614) (652:652:652)) (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (661:661:661)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (2026:2026:2026) (2034:2034:2034)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (923:923:923)) - (PORT datab (209:209:209) (251:251:251)) - (PORT datad (550:550:550) (565:565:565)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (1563:1563:1563) (1570:1570:1570)) - (PORT datab (1404:1404:1404) (1478:1478:1478)) - (PORT datac (616:616:616) (628:628:628)) - (PORT datad (1609:1609:1609) (1666:1666:1666)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (722:722:722)) - (PORT datab (1063:1063:1063) (1095:1095:1095)) - (PORT datac (1261:1261:1261) (1291:1291:1291)) - (PORT datad (1295:1295:1295) (1334:1334:1334)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1174:1174:1174)) - (PORT datac (653:653:653) (694:694:694)) - (PORT datad (884:884:884) (949:949:949)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) (DELAY (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) + (PORT clk (1511:1511:1511) (1525:1525:1525)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) + (PORT ena (843:843:843) (856:856:856)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -23160,149 +26266,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~9) + (INSTANCE z80_\|pla_decode_\|Equal62\~3) (DELAY (ABSOLUTE - (PORT dataa (1069:1069:1069) (1092:1092:1092)) - (PORT datab (256:256:256) (342:342:342)) - (PORT datac (876:876:876) (895:895:895)) - (PORT datad (683:683:683) (775:775:775)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1232:1232:1232) (1327:1327:1327)) - (PORT datab (706:706:706) (741:741:741)) - (PORT datac (673:673:673) (709:709:709)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (958:958:958)) - (PORT datac (1505:1505:1505) (1609:1609:1609)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (656:656:656)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (1449:1449:1449) (1480:1480:1480)) - (PORT datad (626:626:626) (643:643:643)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (274:274:274)) - (PORT datab (345:345:345) (371:371:371)) - (PORT datac (816:816:816) (847:847:847)) - (PORT datad (824:824:824) (851:851:851)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1447:1447:1447)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (641:641:641) (682:682:682)) - (PORT datad (1053:1053:1053) (1066:1066:1066)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (904:904:904)) - (PORT datac (171:171:171) (204:204:204)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1241:1241:1241) (1256:1256:1256)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1386:1386:1386) (1432:1432:1432)) - (PORT datab (678:678:678) (744:744:744)) - (PORT datac (1028:1028:1028) (1055:1055:1055)) - (PORT datad (532:532:532) (548:548:548)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (206:206:206) (249:249:249)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (181:181:181) (210:210:210)) + (PORT dataa (1466:1466:1466) (1594:1594:1594)) + (PORT datab (1469:1469:1469) (1553:1553:1553)) + (PORT datac (1102:1102:1102) (1148:1148:1148)) + (PORT datad (647:647:647) (684:684:684)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -23312,15 +26282,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) (DELAY (ABSOLUTE - (PORT dataa (795:795:795) (815:815:815)) - (PORT datab (2151:2151:2151) (2249:2249:2249)) - (PORT datac (1587:1587:1587) (1632:1632:1632)) - (PORT datad (1778:1778:1778) (1826:1826:1826)) + (PORT dataa (1119:1119:1119) (1156:1156:1156)) + (PORT datab (747:747:747) (772:772:772)) + (PORT datac (1394:1394:1394) (1464:1464:1464)) + (PORT datad (1189:1189:1189) (1225:1225:1225)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (1006:1006:1006)) + (PORT datab (1150:1150:1150) (1220:1220:1220)) + (PORT datac (733:733:733) (829:829:829)) + (PORT datad (1883:1883:1883) (2044:2044:2044)) (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (802:802:802)) + (PORT datab (1392:1392:1392) (1509:1509:1509)) + (PORT datac (1112:1112:1112) (1157:1157:1157)) + (PORT datad (198:198:198) (235:235:235)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -23328,15 +26330,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) (DELAY (ABSOLUTE - (PORT dataa (1545:1545:1545) (1648:1648:1648)) - (PORT datab (346:346:346) (383:383:383)) - (PORT datac (575:575:575) (617:617:617)) - (PORT datad (1068:1068:1068) (1069:1069:1069)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (653:653:653) (668:668:668)) + (PORT datab (819:819:819) (840:840:840)) + (PORT datac (1123:1123:1123) (1137:1137:1137)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (696:696:696)) + (PORT datab (1031:1031:1031) (1083:1083:1083)) + (PORT datac (562:562:562) (584:584:584)) + (PORT datad (901:901:901) (957:957:957)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (741:741:741)) + (PORT datab (618:618:618) (633:633:633)) + (PORT datac (237:237:237) (315:315:315)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1120:1120:1120) (1156:1156:1156)) + (PORT datab (746:746:746) (770:770:770)) + (PORT datac (899:899:899) (956:956:956)) + (PORT datad (1169:1169:1169) (1206:1206:1206)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -23344,15 +26394,173 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) (DELAY (ABSOLUTE - (PORT dataa (1232:1232:1232) (1321:1321:1321)) - (PORT datab (1081:1081:1081) (1100:1100:1100)) - (PORT datac (816:816:816) (843:843:843)) - (PORT datad (1501:1501:1501) (1597:1597:1597)) - (IOPATH dataa combout (341:341:341) (319:319:319)) + (PORT dataa (1433:1433:1433) (1488:1488:1488)) + (PORT datab (677:677:677) (711:711:711)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1402:1402:1402) (1440:1440:1440)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1422:1422:1422) (1463:1463:1463)) + (PORT datab (746:746:746) (770:770:770)) + (PORT datac (1125:1125:1125) (1193:1193:1193)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (496:496:496)) + (PORT datab (268:268:268) (357:357:357)) + (PORT datac (230:230:230) (313:313:313)) + (PORT datad (609:609:609) (655:655:655)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (908:908:908)) + (PORT datab (730:730:730) (816:816:816)) + (PORT datad (395:395:395) (453:453:453)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (513:513:513)) + (PORT datab (390:390:390) (465:465:465)) + (PORT datac (675:675:675) (735:735:735)) + (PORT datad (679:679:679) (752:752:752)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (367:367:367)) + (PORT datab (598:598:598) (665:665:665)) + (PORT datac (245:245:245) (334:334:334)) + (PORT datad (371:371:371) (425:425:425)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (599:599:599)) + (PORT datab (914:914:914) (923:923:923)) + (PORT datac (565:565:565) (580:580:580)) + (PORT datad (307:307:307) (323:323:323)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1424:1424:1424) (1466:1466:1466)) + (PORT datab (1535:1535:1535) (1597:1597:1597)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1559:1559:1559)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1158:1158:1158)) + (PORT datab (675:675:675) (710:710:710)) + (PORT datac (900:900:900) (960:960:960)) + (PORT datad (1167:1167:1167) (1206:1206:1206)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1040:1040:1040)) + (PORT datab (271:271:271) (356:356:356)) + (PORT datac (1122:1122:1122) (1190:1190:1190)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -23360,47 +26568,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) (DELAY (ABSOLUTE (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (541:541:541) (561:561:561)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT datab (746:746:746) (769:769:769)) + (PORT datac (1390:1390:1390) (1425:1425:1425)) + (PORT datad (245:245:245) (316:316:316)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) (DELAY (ABSOLUTE - (PORT dataa (542:542:542) (562:562:562)) - (PORT datab (871:871:871) (931:931:931)) - (PORT datac (878:878:878) (913:913:913)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1518:1518:1518) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1287:1287:1287)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (1356:1356:1356) (1369:1369:1369)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (200:200:200) (237:237:237)) - (PORT datad (618:618:618) (631:631:631)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -23408,15 +26616,92 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (1085:1085:1085) (1134:1134:1134)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (545:545:545) (570:570:570)) + (PORT datab (213:213:213) (257:257:257)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (813:813:813) (826:826:826)) + (PORT datac (328:328:328) (358:358:358)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (381:381:381)) + (PORT datab (662:662:662) (697:697:697)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1161:1161:1161)) + (PORT datab (1154:1154:1154) (1224:1224:1224)) + (PORT datac (1392:1392:1392) (1427:1427:1427)) + (PORT datad (1169:1169:1169) (1209:1209:1209)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (998:998:998)) + (PORT datab (748:748:748) (772:772:772)) + (PORT datac (646:646:646) (675:675:675)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1374:1374:1374) (1429:1429:1429)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -23424,14 +26709,291 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[0\]\~1) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) (DELAY (ABSOLUTE - (PORT dataa (604:604:604) (640:640:640)) - (PORT datab (257:257:257) (345:345:345)) - (PORT datac (231:231:231) (314:314:314)) - (PORT datad (1113:1113:1113) (1159:1159:1159)) + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (341:341:341) (367:367:367)) + (PORT datac (1214:1214:1214) (1255:1255:1255)) + (PORT datad (677:677:677) (698:698:698)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (946:946:946)) + (PORT datab (2012:2012:2012) (2066:2066:2066)) + (PORT datac (919:919:919) (1015:1015:1015)) + (PORT datad (863:863:863) (877:877:877)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (447:447:447)) + (PORT datab (1195:1195:1195) (1198:1198:1198)) + (PORT datac (601:601:601) (607:607:607)) + (PORT datad (334:334:334) (359:359:359)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (855:855:855)) + (PORT datad (337:337:337) (354:354:354)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (278:278:278)) + (PORT datab (223:223:223) (271:271:271)) + (PORT datac (616:616:616) (645:645:645)) + (PORT datad (216:216:216) (258:258:258)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (621:621:621)) + (PORT datab (686:686:686) (701:701:701)) + (PORT datac (562:562:562) (583:583:583)) + (PORT datad (312:312:312) (322:322:322)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (661:661:661)) + (PORT datab (654:654:654) (674:674:674)) + (PORT datac (240:240:240) (317:317:317)) + (PORT datad (385:385:385) (407:407:407)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (692:692:692)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (610:610:610) (651:651:651)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1244:1244:1244) (1250:1250:1250)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1638:1638:1638) (1703:1703:1703)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (884:884:884) (949:949:949)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (747:747:747)) + (PORT datab (659:659:659) (717:717:717)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1816:1816:1816) (1911:1911:1911)) + (PORT datab (2014:2014:2014) (2068:2068:2068)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|flags_cond_true) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (663:663:663)) + (PORT datab (1772:1772:1772) (1863:1863:1863)) + (PORT datac (1815:1815:1815) (1893:1893:1893)) + (PORT datad (552:552:552) (570:570:570)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (230:230:230) (280:280:280)) + (PORT datac (563:563:563) (592:592:592)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (905:905:905)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (623:623:623) (650:650:650)) + (PORT datad (1193:1193:1193) (1247:1247:1247)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (658:658:658)) + (PORT datab (949:949:949) (994:994:994)) + (PORT datad (671:671:671) (699:699:699)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (694:694:694)) + (PORT datab (517:517:517) (537:537:537)) + (PORT datac (742:742:742) (744:744:744)) + (PORT datad (1107:1107:1107) (1107:1107:1107)) + (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -23440,264 +27002,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (852:852:852) (899:899:899)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (349:349:349) (376:376:376)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1545:1545:1545)) - (PORT asdata (544:544:544) (580:580:580)) - (PORT ena (1737:1737:1737) (1732:1732:1732)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (724:724:724)) - (PORT datab (1065:1065:1065) (1098:1098:1098)) - (PORT datac (1263:1263:1263) (1299:1299:1299)) - (PORT datad (1299:1299:1299) (1342:1342:1342)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (893:893:893)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datad (831:831:831) (833:833:833)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (892:892:892) (941:941:941)) - (PORT datac (578:578:578) (588:588:588)) - (PORT datad (1047:1047:1047) (1075:1075:1075)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (888:888:888)) - (PORT datab (864:864:864) (912:912:912)) - (PORT datac (656:656:656) (697:697:697)) - (PORT datad (1100:1100:1100) (1124:1124:1124)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (879:879:879) (943:943:943)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1118:1118:1118) (1145:1145:1145)) - (PORT datac (915:915:915) (980:980:980)) - (PORT datad (683:683:683) (777:777:777)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1413:1413:1413) (1443:1443:1443)) - (PORT datab (212:212:212) (257:257:257)) - (PORT datac (638:638:638) (679:679:679)) - (PORT datad (1056:1056:1056) (1068:1068:1068)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (816:816:816) (863:863:863)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1241:1241:1241) (1256:1256:1256)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datab (258:258:258) (345:345:345)) - (PORT datac (230:230:230) (313:313:313)) - (PORT datad (576:576:576) (596:596:596)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1149:1149:1149) (1194:1194:1194)) - (PORT datac (349:349:349) (375:375:375)) - (PORT datad (191:191:191) (225:225:225)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (224:224:224) (271:271:271)) - (PORT datac (817:817:817) (835:835:835)) - (PORT datad (570:570:570) (594:594:594)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) - (PORT datab (221:221:221) (267:267:267)) - (PORT datac (311:311:311) (335:335:335)) - (PORT datad (186:186:186) (218:218:218)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (905:905:905)) - (PORT datad (819:819:819) (855:855:855)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (578:578:578)) - (PORT datac (343:343:343) (364:364:364)) - (PORT datad (572:572:572) (594:594:594)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (545:545:545) (573:573:573)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (580:580:580) (606:606:606)) + (PORT datad (621:621:621) (643:643:643)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -23705,103 +27018,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) (DELAY (ABSOLUTE - (PORT dataa (383:383:383) (406:406:406)) - (PORT datab (228:228:228) (268:268:268)) - (PORT datac (186:186:186) (226:226:226)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (580:580:580)) - (PORT datab (371:371:371) (399:399:399)) - (PORT datac (187:187:187) (227:227:227)) - (PORT datad (312:312:312) (329:329:329)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (198:198:198) (242:242:242)) + (PORT datab (259:259:259) (310:310:310)) + (PORT datac (607:607:607) (617:617:617)) + (PORT datad (236:236:236) (276:276:276)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2034:2034:2034) (2049:2049:2049)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT datab (1292:1292:1292) (1323:1323:1323)) - (PORT datac (641:641:641) (682:682:682)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (983:983:983)) - (PORT datab (708:708:708) (787:787:787)) - (PORT datac (668:668:668) (731:731:731)) - (PORT datad (1067:1067:1067) (1080:1080:1080)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1217:1217:1217)) - (PORT datab (1106:1106:1106) (1121:1121:1121)) - (PORT datac (1267:1267:1267) (1309:1309:1309)) - (PORT datad (346:346:346) (366:366:366)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1209:1209:1209) (1217:1217:1217)) + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1881:1881:1881) (1885:1885:1885)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -23813,12 +27050,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1209:1209:1209) (1220:1220:1220)) - (PORT ena (942:942:942) (926:926:926)) + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (1836:1836:1836) (1841:1841:1841)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -23829,43 +27066,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~59) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) (DELAY (ABSOLUTE - (PORT dataa (422:422:422) (468:468:468)) - (PORT datab (438:438:438) (465:465:465)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (959:959:959) (984:984:984)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (1335:1335:1335) (1359:1359:1359)) - (PORT datab (861:861:861) (890:890:890)) - (PORT datad (388:388:388) (410:410:410)) + (PORT dataa (434:434:434) (465:465:465)) + (PORT datab (378:378:378) (448:448:448)) + (PORT datad (608:608:608) (629:629:629)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -23875,116 +27081,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (910:910:910) (930:930:930)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (522:522:522)) - (PORT datab (240:240:240) (321:321:321)) - (PORT datad (665:665:665) (689:689:689)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (906:906:906) (930:930:930)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1253:1253:1253) (1281:1281:1281)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (462:462:462)) - (PORT datab (657:657:657) (679:679:679)) - (PORT datad (631:631:631) (649:649:649)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1459:1459:1459) (1470:1470:1470)) - (PORT ena (962:962:962) (970:970:970)) + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (1836:1836:1836) (1841:1841:1841)) + (PORT ena (1499:1499:1499) (1507:1507:1507)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -23995,12 +27097,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1456:1456:1456) (1466:1466:1466)) - (PORT ena (979:979:979) (971:971:971)) + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (2122:2122:2122) (2138:2138:2138)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -24009,44 +27111,13 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (474:474:474)) - (PORT datab (428:428:428) (471:471:471)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (380:380:380) (404:404:404)) - (PORT datac (570:570:570) (578:578:578)) - (PORT datad (605:605:605) (619:619:619)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1705:1705:1705) (1727:1727:1727)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (2124:2124:2124) (2160:2160:2160)) (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -24058,14 +27129,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~15) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) (DELAY (ABSOLUTE - (PORT dataa (1209:1209:1209) (1276:1276:1276)) - (PORT datab (1384:1384:1384) (1452:1452:1452)) - (PORT datad (1859:1859:1859) (1915:1915:1915)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (462:462:462) (498:498:498)) + (PORT datab (667:667:667) (706:706:706)) + (PORT datad (632:632:632) (685:685:685)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24073,38 +27144,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) (DELAY (ABSOLUTE - (PORT datad (940:940:940) (972:972:972)) + (PORT datab (1411:1411:1411) (1423:1423:1423)) + (PORT datad (585:585:585) (594:594:594)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1271:1271:1271) (1298:1298:1298)) - (PORT ena (1011:1011:1011) (1021:1021:1021)) + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1880:1880:1880) (1884:1884:1884)) + (PORT ena (1220:1220:1220) (1214:1214:1214)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -24115,14 +27173,72 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~58) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) (DELAY (ABSOLUTE - (PORT dataa (382:382:382) (461:461:461)) - (PORT datab (691:691:691) (760:760:760)) - (PORT datad (232:232:232) (270:270:270)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (657:657:657) (709:709:709)) + (PORT datab (945:945:945) (994:994:994)) + (PORT datac (888:888:888) (910:910:910)) + (PORT datad (609:609:609) (625:625:625)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1630:1630:1630) (1644:1644:1644)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (823:823:823) (864:864:864)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (473:473:473)) + (PORT datab (583:583:583) (621:621:621)) + (PORT datad (584:584:584) (628:628:628)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24130,13 +27246,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~65) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) (DELAY (ABSOLUTE - (PORT dataa (657:657:657) (711:711:711)) - (PORT datab (633:633:633) (654:654:654)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (329:329:329) (347:347:347)) + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (551:551:551) (556:556:556)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -24146,47 +27262,475 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~66) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (627:627:627)) - (PORT datab (602:602:602) (637:637:637)) - (PORT datac (1952:1952:1952) (2065:2065:2065)) - (PORT datad (568:568:568) (590:590:590)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (1532:1532:1532) (1549:1549:1549)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~11) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT dataa (1034:1034:1034) (1047:1047:1047)) - (PORT datab (1335:1335:1335) (1323:1323:1323)) - (PORT datac (1088:1088:1088) (1082:1082:1082)) - (PORT datad (1019:1019:1019) (1010:1010:1010)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1857:1857:1857) (1863:1863:1863)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~12) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (381:381:381)) - (PORT datab (252:252:252) (310:310:310)) - (PORT datac (1107:1107:1107) (1120:1120:1120)) - (PORT datad (845:845:845) (862:862:862)) + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (962:962:962) (1016:1016:1016)) + (PORT datad (847:847:847) (873:873:873)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (712:712:712) (740:740:740)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (712:712:712) (740:740:740)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (329:329:329)) + (PORT datab (263:263:263) (316:316:316)) + (PORT datad (234:234:234) (273:273:273)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (726:726:726)) + (PORT datab (635:635:635) (674:674:674)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1349:1349:1349) (1373:1373:1373)) + (PORT datab (623:623:623) (653:653:653)) + (PORT datac (643:643:643) (694:694:694)) + (PORT datad (308:308:308) (323:323:323)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1481:1481:1481) (1531:1531:1531)) + (PORT datab (1644:1644:1644) (1715:1715:1715)) + (PORT datac (1522:1522:1522) (1538:1538:1538)) + (PORT datad (1165:1165:1165) (1205:1205:1205)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (996:996:996)) + (PORT datab (878:878:878) (913:913:913)) + (PORT datac (923:923:923) (978:978:978)) + (PORT datad (879:879:879) (914:914:914)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (696:696:696) (721:721:721)) + (PORT datab (1150:1150:1150) (1186:1186:1186)) + (PORT datac (887:887:887) (975:975:975)) + (PORT datad (1184:1184:1184) (1219:1219:1219)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (943:943:943) (996:996:996)) + (PORT datac (648:648:648) (674:674:674)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1352:1352:1352)) + (PORT datab (933:933:933) (975:975:975)) + (PORT datac (1446:1446:1446) (1491:1491:1491)) + (PORT datad (926:926:926) (983:983:983)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (248:248:248)) + (PORT datab (986:986:986) (1033:1033:1033)) + (PORT datac (900:900:900) (933:933:933)) + (PORT datad (222:222:222) (267:267:267)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1695:1695:1695) (1783:1783:1783)) + (PORT datac (897:897:897) (925:925:925)) + (PORT datad (364:364:364) (385:385:385)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (926:926:926) (952:952:952)) + (PORT datad (237:237:237) (274:274:274)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1212:1212:1212)) + (PORT datab (286:286:286) (347:347:347)) + (PORT datac (254:254:254) (311:311:311)) + (PORT datad (254:254:254) (300:300:300)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (432:432:432) (525:525:525)) + (PORT datab (1170:1170:1170) (1217:1217:1217)) + (PORT datac (1156:1156:1156) (1212:1212:1212)) + (PORT datad (661:661:661) (724:724:724)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1535:1535:1535)) + (PORT asdata (672:672:672) (698:698:698)) + (PORT ena (1283:1283:1283) (1287:1287:1287)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (638:638:638)) + (PORT datab (368:368:368) (389:389:389)) + (PORT datad (1139:1139:1139) (1146:1146:1146)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (597:597:597)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (1124:1124:1124) (1146:1146:1146)) + (PORT datad (335:335:335) (355:355:355)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1345:1345:1345)) + (PORT datab (915:915:915) (937:937:937)) + (PORT datac (1123:1123:1123) (1144:1144:1144)) + (PORT datad (945:945:945) (995:995:995)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (964:964:964) (1020:1020:1020)) + (PORT datac (806:806:806) (813:813:813)) + (PORT datad (227:227:227) (273:273:273)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (999:999:999)) + (PORT datac (1663:1663:1663) (1739:1739:1739)) + (PORT datad (1415:1415:1415) (1442:1442:1442)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datac (902:902:902) (931:931:931)) + (PORT datad (239:239:239) (281:281:281)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1211:1211:1211)) + (PORT datab (286:286:286) (349:349:349)) + (PORT datac (255:255:255) (313:313:313)) + (PORT datad (248:248:248) (293:293:293)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (728:728:728)) + (PORT datab (1171:1171:1171) (1217:1217:1217)) + (PORT datac (615:615:615) (673:673:673)) + (PORT datad (661:661:661) (723:723:723)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1535:1535:1535)) + (PORT asdata (1127:1127:1127) (1132:1132:1132)) + (PORT ena (1283:1283:1283) (1287:1287:1287)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (578:578:578)) + (PORT datab (331:331:331) (362:362:362)) + (PORT datad (1138:1138:1138) (1145:1145:1145)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (703:703:703)) + (PORT datab (359:359:359) (389:389:389)) + (PORT datac (797:797:797) (800:800:800)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24194,29 +27738,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~5) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (1230:1230:1230) (1328:1328:1328)) - (PORT datab (899:899:899) (920:920:920)) - (PORT datac (671:671:671) (707:707:707)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (904:904:904)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1497:1497:1497) (1599:1599:1599)) - (PORT datad (1296:1296:1296) (1331:1331:1331)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (588:588:588) (619:619:619)) + (PORT datab (968:968:968) (1015:1015:1015)) + (PORT datac (371:371:371) (403:403:403)) + (PORT datad (863:863:863) (917:917:917)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24224,55 +27754,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~9) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) (DELAY (ABSOLUTE - (PORT dataa (632:632:632) (694:694:694)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (530:530:530) (546:546:546)) - (PORT datad (831:831:831) (855:855:855)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (911:911:911) (951:951:951)) - (PORT datac (601:601:601) (631:631:631)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1171:1171:1171)) - (PORT datab (641:641:641) (685:685:685)) - (PORT datac (796:796:796) (800:800:800)) - (PORT datad (822:822:822) (845:845:845)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (883:883:883) (950:950:950)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (681:681:681) (721:721:721)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24280,10 +27766,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) + (INSTANCE z80_\|alu_\|op1_low\[1\]) (DELAY (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) + (PORT clk (1530:1530:1530) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) (PORT ena (790:790:790) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -24299,40 +27785,65 @@ (INSTANCE z80_\|alu_control_\|out\[6\]\~0) (DELAY (ABSOLUTE - (PORT datab (261:261:261) (341:341:341)) - (PORT datac (243:243:243) (321:321:321)) + (PORT datab (264:264:264) (346:346:346)) + (PORT datac (235:235:235) (311:311:311)) (PORT datad (235:235:235) (303:303:303)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) (DELAY (ABSOLUTE - (PORT dataa (1199:1199:1199) (1324:1324:1324)) - (PORT datab (1140:1140:1140) (1190:1190:1190)) - (PORT datac (1052:1052:1052) (1072:1072:1072)) - (PORT datad (1114:1114:1114) (1181:1181:1181)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT datac (852:852:852) (861:861:861)) + (PORT datad (679:679:679) (700:700:700)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (732:732:732)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datad (621:621:621) (632:632:632)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~19) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (327:327:327)) - (PORT datab (645:645:645) (709:709:709)) - (PORT datac (1310:1310:1310) (1345:1345:1345)) - (PORT datad (556:556:556) (578:578:578)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1231:1231:1231)) + (PORT datab (681:681:681) (697:697:697)) + (PORT datac (1123:1123:1123) (1203:1203:1203)) + (PORT datad (667:667:667) (721:721:721)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -24342,13 +27853,139 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (1694:1694:1694) (1713:1713:1713)) - (PORT datab (869:869:869) (906:906:906)) - (PORT datac (1069:1069:1069) (1103:1103:1103)) - (PORT datad (1032:1032:1032) (1064:1064:1064)) + (PORT dataa (1196:1196:1196) (1252:1252:1252)) + (PORT datab (1640:1640:1640) (1708:1708:1708)) + (PORT datac (1440:1440:1440) (1482:1482:1482)) + (PORT datad (844:844:844) (890:890:890)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (686:686:686)) + (PORT datab (928:928:928) (956:956:956)) + (PORT datac (630:630:630) (688:688:688)) + (PORT datad (848:848:848) (847:847:847)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (856:856:856)) + (PORT datab (904:904:904) (946:946:946)) + (PORT datac (412:412:412) (479:479:479)) + (PORT datad (832:832:832) (862:862:862)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (712:712:712)) + (PORT datab (943:943:943) (996:996:996)) + (PORT datac (576:576:576) (598:598:598)) + (PORT datad (316:316:316) (337:337:337)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1305:1305:1305) (1357:1357:1357)) + (PORT datab (967:967:967) (1024:1024:1024)) + (PORT datac (922:922:922) (952:952:952)) + (PORT datad (1557:1557:1557) (1610:1610:1610)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (642:642:642)) + (PORT datab (987:987:987) (1034:1034:1034)) + (PORT datac (175:175:175) (210:210:210)) + (PORT datad (221:221:221) (266:266:266)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1693:1693:1693) (1778:1778:1778)) + (PORT datab (916:916:916) (942:942:942)) + (PORT datac (904:904:904) (929:929:929)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1446:1446:1446) (1487:1487:1487)) + (PORT datab (1129:1129:1129) (1183:1183:1183)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (234:234:234) (275:275:275)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (274:274:274)) + (PORT datab (246:246:246) (301:301:301)) + (PORT datac (617:617:617) (647:647:647)) + (PORT datad (845:845:845) (875:875:875)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -24358,5215 +27995,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~23) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) (DELAY (ABSOLUTE - (PORT dataa (920:920:920) (977:977:977)) - (PORT datab (825:825:825) (823:823:823)) - (PORT datac (1582:1582:1582) (1644:1644:1644)) - (PORT datad (631:631:631) (666:666:666)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (549:549:549) (580:580:580)) + (PORT datab (714:714:714) (753:753:753)) + (PORT datac (601:601:601) (608:608:608)) + (PORT datad (865:865:865) (915:915:915)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (718:718:718)) + (PORT datab (1128:1128:1128) (1175:1175:1175)) + (PORT datac (587:587:587) (617:617:617)) + (PORT datad (401:401:401) (459:459:459)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~24) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~1) (DELAY (ABSOLUTE - (PORT dataa (842:842:842) (859:859:859)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (1136:1136:1136) (1151:1151:1151)) + (PORT dataa (261:261:261) (336:336:336)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (559:559:559) (578:578:578)) + (PORT datad (903:903:903) (954:954:954)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (550:550:550) (568:568:568)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1255:1255:1255) (1269:1269:1269)) - (PORT datad (670:670:670) (691:691:691)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (208:208:208) (241:241:241)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (628:628:628)) - (PORT datab (261:261:261) (314:314:314)) - (PORT datad (1139:1139:1139) (1169:1169:1169)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (621:621:621) (646:646:646)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1450:1450:1450) (1505:1505:1505)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (937:937:937) (960:960:960)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (274:274:274) (344:344:344)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (585:585:585) (609:609:609)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (977:977:977) (1007:1007:1007)) - (PORT ena (1447:1447:1447) (1426:1426:1426)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (383:383:383)) - (PORT datad (632:632:632) (654:654:654)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1386:1386:1386) (1434:1434:1434)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1384:1384:1384) (1436:1436:1436)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (694:694:694)) - (PORT datab (241:241:241) (324:324:324)) - (PORT datad (850:850:850) (903:903:903)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (986:986:986) (1016:1016:1016)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (986:986:986) (1016:1016:1016)) - (PORT ena (1472:1472:1472) (1481:1481:1481)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (280:280:280) (343:343:343)) - (PORT datab (701:701:701) (738:738:738)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (641:641:641)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (627:627:627) (643:643:643)) - (PORT datad (305:305:305) (321:321:321)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1478:1478:1478) (1511:1511:1511)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1473:1473:1473) (1506:1506:1506)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (427:427:427) (490:490:490)) - (PORT datab (696:696:696) (732:732:732)) - (PORT datad (659:659:659) (676:676:676)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1248:1248:1248) (1264:1264:1264)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1252:1252:1252) (1268:1268:1268)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (774:774:774)) - (PORT datab (709:709:709) (762:762:762)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (874:874:874)) - (PORT datab (634:634:634) (660:660:660)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (866:866:866)) - (PORT datab (866:866:866) (899:899:899)) - (PORT datac (1506:1506:1506) (1607:1607:1607)) - (PORT datad (840:840:840) (838:838:838)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (708:708:708) (742:742:742)) - (PORT ena (983:983:983) (976:976:976)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1248:1248:1248) (1270:1270:1270)) - (PORT datab (1220:1220:1220) (1233:1233:1233)) - (PORT datad (397:397:397) (430:430:430)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datac (449:449:449) (487:487:487)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (906:906:906)) - (PORT datab (1448:1448:1448) (1568:1568:1568)) - (PORT datac (578:578:578) (601:601:601)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (890:890:890)) - (PORT datad (1216:1216:1216) (1314:1314:1314)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (181:181:181) (209:209:209)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1564:1564:1564)) - (PORT ena (2593:2593:2593) (2662:2662:2662)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datac (1019:1019:1019) (1059:1059:1059)) - (PORT datad (813:813:813) (852:852:852)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1291:1291:1291) (1308:1308:1308)) - (PORT datab (1274:1274:1274) (1276:1276:1276)) - (PORT datac (1361:1361:1361) (1410:1410:1410)) - (PORT datad (1277:1277:1277) (1313:1313:1313)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1021:1021:1021) (1037:1037:1037)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1527:1527:1527) (1548:1548:1548)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1527:1527:1527) (1547:1547:1547)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (459:459:459)) - (PORT datab (702:702:702) (734:734:734)) - (PORT datad (662:662:662) (679:679:679)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1226:1226:1226) (1246:1246:1246)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1229:1229:1229) (1249:1249:1249)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (332:332:332)) - (PORT datab (704:704:704) (754:754:754)) - (PORT datad (682:682:682) (728:728:728)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1640:1640:1640) (1677:1677:1677)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1637:1637:1637) (1675:1675:1675)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (697:697:697)) - (PORT datab (872:872:872) (936:936:936)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (537:537:537) (567:567:567)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (626:626:626)) - (PORT datab (642:642:642) (663:663:663)) - (PORT datad (233:233:233) (272:272:272)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (926:926:926) (946:946:946)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (926:926:926) (947:947:947)) - (PORT ena (1472:1472:1472) (1481:1481:1481)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (281:281:281) (346:346:346)) - (PORT datab (701:701:701) (738:738:738)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (943:943:943) (961:961:961)) - (PORT ena (1450:1450:1450) (1505:1505:1505)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (945:945:945) (963:963:963)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (349:349:349)) - (PORT datab (243:243:243) (324:324:324)) - (PORT datad (581:581:581) (608:608:608)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1543:1543:1543)) - (PORT asdata (1615:1615:1615) (1650:1650:1650)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT datab (369:369:369) (407:407:407)) - (PORT datad (217:217:217) (253:253:253)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (777:777:777) (846:846:846)) - (PORT datab (375:375:375) (400:400:400)) - (PORT datac (533:533:533) (549:549:549)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (865:865:865)) - (PORT datac (815:815:815) (815:815:815)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1536:1536:1536) (1645:1645:1645)) - (PORT datab (807:807:807) (836:836:836)) - (PORT datac (813:813:813) (827:827:827)) - (PORT datad (314:314:314) (324:324:324)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (538:538:538) (568:568:568)) - (PORT ena (983:983:983) (976:976:976)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1274:1274:1274)) - (PORT datab (1411:1411:1411) (1449:1449:1449)) - (PORT datad (396:396:396) (430:430:430)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (420:420:420) (500:500:500)) - (PORT datac (448:448:448) (484:484:484)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (268:268:268)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (632:632:632) (698:698:698)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (640:640:640) (681:681:681)) - (PORT datac (582:582:582) (597:597:597)) - (PORT datad (1422:1422:1422) (1523:1523:1523)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT datac (1493:1493:1493) (1574:1574:1574)) - (PORT datad (634:634:634) (649:649:649)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1547:1547:1547)) - (PORT ena (2452:2452:2452) (2480:2480:2480)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1308:1308:1308)) - (PORT datab (1275:1275:1275) (1277:1277:1277)) - (PORT datac (632:632:632) (697:697:697)) - (PORT datad (1277:1277:1277) (1313:1313:1313)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT datac (1492:1492:1492) (1575:1575:1575)) - (PORT datad (597:597:597) (613:613:613)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1547:1547:1547)) - (PORT ena (2452:2452:2452) (2480:2480:2480)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1317:1317:1317) (1359:1359:1359)) - (PORT datab (1272:1272:1272) (1275:1275:1275)) - (PORT datac (1255:1255:1255) (1271:1271:1271)) - (PORT datad (687:687:687) (748:748:748)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (269:269:269)) - (PORT datab (207:207:207) (250:250:250)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (956:956:956)) - (PORT datac (857:857:857) (988:988:988)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1021:1021:1021) (1037:1037:1037)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (537:537:537) (567:567:567)) - (PORT ena (983:983:983) (976:976:976)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1271:1271:1271)) - (PORT datab (1059:1059:1059) (1102:1102:1102)) - (PORT datad (396:396:396) (427:427:427)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (500:500:500)) - (PORT datac (448:448:448) (485:485:485)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (846:846:846)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (577:577:577) (601:601:601)) - (PORT datad (1420:1420:1420) (1528:1528:1528)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (691:691:691) (721:721:721)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (691:691:691) (718:718:718)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (458:458:458)) - (PORT datab (709:709:709) (762:762:762)) - (PORT datad (681:681:681) (733:733:733)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1403:1403:1403) (1428:1428:1428)) - (PORT datab (911:911:911) (951:951:951)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1191:1191:1191) (1214:1214:1214)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1191:1191:1191) (1217:1217:1217)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (464:464:464)) - (PORT datab (696:696:696) (739:739:739)) - (PORT datad (658:658:658) (684:684:684)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1894:1894:1894) (1950:1950:1950)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (1191:1191:1191) (1205:1205:1205)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1896:1896:1896) (1952:1952:1952)) - (PORT ena (1472:1472:1472) (1481:1481:1481)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (687:687:687)) - (PORT datab (701:701:701) (738:738:738)) - (PORT datad (628:628:628) (654:654:654)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (283:283:283) (348:348:348)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (1406:1406:1406) (1420:1420:1420)) - (PORT ena (1450:1450:1450) (1505:1505:1505)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (1408:1408:1408) (1420:1420:1420)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (276:276:276) (349:349:349)) - (PORT datab (242:242:242) (323:323:323)) - (PORT datad (581:581:581) (608:608:608)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1211:1211:1211) (1188:1188:1188)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (944:944:944) (958:958:958)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (946:946:946) (960:960:960)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (698:698:698)) - (PORT datab (875:875:875) (937:937:937)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (632:632:632)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datac (346:346:346) (370:370:370)) - (PORT datad (821:821:821) (828:828:828)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (367:367:367)) - (PORT datab (650:650:650) (666:666:666)) - (PORT datac (598:598:598) (605:605:605)) - (PORT datad (171:171:171) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (411:411:411)) - (PORT datab (926:926:926) (946:946:946)) - (PORT datac (1242:1242:1242) (1334:1334:1334)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (601:601:601)) - (PORT datab (908:908:908) (946:946:946)) - (PORT datac (866:866:866) (891:891:891)) - (PORT datad (622:622:622) (645:645:645)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1608:1608:1608) (1681:1681:1681)) - (PORT datad (335:335:335) (359:359:359)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (742:742:742)) - (PORT datab (631:631:631) (649:649:649)) - (PORT datac (318:318:318) (348:348:348)) - (PORT datad (211:211:211) (245:245:245)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1115:1115:1115) (1153:1153:1153)) - (PORT datab (680:680:680) (703:703:703)) - (PORT datac (887:887:887) (911:911:911)) - (PORT datad (1148:1148:1148) (1170:1170:1170)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (254:254:254) (312:312:312)) - (PORT datac (1316:1316:1316) (1367:1367:1367)) - (PORT datad (844:844:844) (863:863:863)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (957:957:957)) - (PORT datab (701:701:701) (737:737:737)) - (PORT datac (1183:1183:1183) (1279:1279:1279)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (353:353:353) (383:383:383)) - (PORT datac (1397:1397:1397) (1462:1462:1462)) - (PORT datad (570:570:570) (584:584:584)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (615:615:615) (665:665:665)) - (PORT datac (1282:1282:1282) (1326:1326:1326)) - (PORT datad (597:597:597) (614:614:614)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (559:559:559) (584:584:584)) - (PORT datad (833:833:833) (857:857:857)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (889:889:889)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (631:631:631) (656:656:656)) - (PORT datad (878:878:878) (943:943:943)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1337:1337:1337)) - (PORT datab (1262:1262:1262) (1312:1312:1312)) - (PORT datac (247:247:247) (327:327:327)) - (PORT datad (248:248:248) (320:320:320)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (408:408:408)) - (PORT datab (887:887:887) (949:949:949)) - (PORT datac (1117:1117:1117) (1135:1135:1135)) - (PORT datad (1141:1141:1141) (1193:1193:1193)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (802:802:802)) - (PORT datab (706:706:706) (778:778:778)) - (PORT datac (813:813:813) (872:872:872)) - (PORT datad (864:864:864) (895:895:895)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (253:253:253)) - (PORT datab (228:228:228) (268:268:268)) - (PORT datac (316:316:316) (340:340:340)) - (PORT datad (189:189:189) (219:219:219)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (613:613:613)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (169:169:169) (202:202:202)) - (PORT datad (575:575:575) (584:584:584)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2034:2034:2034) (2049:2049:2049)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (983:983:983)) - (PORT datab (726:726:726) (806:806:806)) - (PORT datac (692:692:692) (769:769:769)) - (PORT datad (1067:1067:1067) (1080:1080:1080)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (689:689:689)) - (PORT datab (668:668:668) (729:729:729)) - (PORT datac (541:541:541) (565:565:565)) - (PORT datad (596:596:596) (609:609:609)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (658:658:658)) - (PORT datab (554:554:554) (576:576:576)) - (PORT datad (2091:2091:2091) (2174:2174:2174)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (607:607:607)) - (PORT datac (1366:1366:1366) (1433:1433:1433)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (606:606:606)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (998:998:998) (1028:1028:1028)) - (PORT datad (846:846:846) (862:862:862)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (709:709:709)) - (PORT datab (910:910:910) (948:948:948)) - (PORT datac (599:599:599) (629:629:629)) - (PORT datad (898:898:898) (951:951:951)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (905:905:905)) - (PORT datab (670:670:670) (700:700:700)) - (PORT datac (667:667:667) (722:722:722)) - (PORT datad (606:606:606) (633:633:633)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) - (DELAY - (ABSOLUTE - (PORT datac (669:669:669) (697:697:697)) - (PORT datad (216:216:216) (242:242:242)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (538:538:538) (556:556:556)) - (PORT datad (326:326:326) (349:349:349)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1626:1626:1626) (1670:1670:1670)) - (PORT datab (916:916:916) (984:984:984)) - (PORT datac (1201:1201:1201) (1290:1290:1290)) - (PORT datad (768:768:768) (777:777:777)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (473:473:473)) - (PORT datab (669:669:669) (718:718:718)) - (PORT datac (611:611:611) (625:625:625)) - (PORT datad (816:816:816) (864:864:864)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (607:607:607)) - (PORT datab (1060:1060:1060) (1078:1078:1078)) - (PORT datac (1045:1045:1045) (1063:1063:1063)) - (PORT datad (554:554:554) (572:572:572)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (262:262:262) (348:348:348)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (237:237:237) (313:313:313)) - (PORT datad (241:241:241) (312:312:312)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (718:718:718)) - (PORT datab (871:871:871) (886:886:886)) - (PORT datac (243:243:243) (323:323:323)) - (PORT datad (681:681:681) (774:774:774)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1340:1340:1340) (1402:1402:1402)) - (PORT datab (693:693:693) (788:788:788)) - (PORT datac (629:629:629) (675:675:675)) - (PORT datad (607:607:607) (652:652:652)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (865:865:865) (893:893:893)) - (PORT datad (619:619:619) (667:667:667)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1317:1317:1317)) - (PORT datab (845:845:845) (874:874:874)) - (PORT datac (315:315:315) (336:336:336)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1039:1039:1039)) - (PORT datab (854:854:854) (909:909:909)) - (PORT datac (1493:1493:1493) (1576:1576:1576)) - (PORT datad (2057:2057:2057) (2140:2140:2140)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (413:413:413)) - (PORT datab (683:683:683) (720:720:720)) - (PORT datac (191:191:191) (224:224:224)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (370:370:370)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1005:1005:1005) (1014:1014:1014)) - (PORT datad (182:182:182) (213:213:213)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1044:1044:1044) (1077:1077:1077)) - (PORT datab (1091:1091:1091) (1099:1099:1099)) - (PORT datac (614:614:614) (631:631:631)) - (PORT datad (218:218:218) (253:253:253)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (639:639:639)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (175:175:175) (208:208:208)) - (PORT datad (638:638:638) (663:663:663)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1154:1154:1154)) - (PORT datab (1186:1186:1186) (1208:1208:1208)) - (PORT datac (812:812:812) (859:859:859)) - (PORT datad (839:839:839) (882:882:882)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (919:919:919)) - (PORT datab (876:876:876) (899:899:899)) - (PORT datac (355:355:355) (384:384:384)) - (PORT datad (229:229:229) (274:274:274)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1322:1322:1322)) - (PORT datab (704:704:704) (739:739:739)) - (PORT datac (855:855:855) (907:907:907)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1368:1368:1368)) - (PORT datab (951:951:951) (969:969:969)) - (PORT datac (1419:1419:1419) (1506:1506:1506)) - (PORT datad (334:334:334) (352:352:352)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1119:1119:1119) (1183:1183:1183)) - (PORT datac (599:599:599) (629:629:629)) - (PORT datad (883:883:883) (909:909:909)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1169:1169:1169) (1238:1238:1238)) - (PORT datab (690:690:690) (719:719:719)) - (PORT datac (1120:1120:1120) (1138:1138:1138)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1117:1117:1117)) - (PORT datab (730:730:730) (810:810:810)) - (PORT datac (640:640:640) (708:708:708)) - (PORT datad (881:881:881) (924:924:924)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1219:1219:1219)) - (PORT datab (1097:1097:1097) (1113:1113:1113)) - (PORT datac (1267:1267:1267) (1306:1306:1306)) - (PORT datad (335:335:335) (355:355:355)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (498:498:498) (507:507:507)) - (PORT datad (837:837:837) (862:862:862)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1171:1171:1171)) - (PORT datab (670:670:670) (703:703:703)) - (PORT datac (642:642:642) (676:676:676)) - (PORT datad (877:877:877) (942:942:942)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1401:1401:1401) (1436:1436:1436)) - (PORT datab (734:734:734) (817:817:817)) - (PORT datac (671:671:671) (744:744:744)) - (PORT datad (1015:1015:1015) (1059:1059:1059)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (651:651:651)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (1116:1116:1116) (1131:1131:1131)) - (PORT datad (1142:1142:1142) (1189:1189:1189)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|alu_\|op2_low\[2\]) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) + (PORT clk (1529:1529:1529) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (765:765:765)) - (PORT datab (841:841:841) (900:900:900)) - (PORT datac (637:637:637) (704:704:704)) - (PORT datad (863:863:863) (891:891:891)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (699:699:699) (774:774:774)) - (PORT datac (1370:1370:1370) (1395:1395:1395)) - (PORT datad (706:706:706) (777:777:777)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (401:401:401)) - (PORT datab (220:220:220) (266:266:266)) - (PORT datac (186:186:186) (224:224:224)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (404:404:404)) - (PORT datab (222:222:222) (269:269:269)) - (PORT datac (327:327:327) (352:352:352)) - (PORT datad (208:208:208) (239:239:239)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (827:827:827)) - (PORT datab (379:379:379) (412:412:412)) - (PORT datac (385:385:385) (431:431:431)) - (PORT datad (828:828:828) (829:829:829)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1057:1057:1057)) - (PORT datab (923:923:923) (992:992:992)) - (PORT datac (1097:1097:1097) (1141:1141:1141)) - (PORT datad (1315:1315:1315) (1341:1341:1341)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1059:1059:1059) (1111:1111:1111)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1309:1309:1309) (1382:1382:1382)) - (PORT datad (1071:1071:1071) (1084:1084:1084)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (623:623:623) (647:647:647)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1313:1313:1313)) - (PORT datab (880:880:880) (933:933:933)) - (PORT datac (1111:1111:1111) (1131:1131:1131)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1495:1495:1495)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (802:802:802) (805:805:805)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1498:1498:1498)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (603:603:603) (632:632:632)) - (PORT datad (894:894:894) (957:957:957)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (924:924:924) (998:998:998)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (914:914:914)) - (PORT datab (1140:1140:1140) (1155:1155:1155)) - (PORT datac (242:242:242) (322:322:322)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1082:1082:1082)) - (PORT datab (1004:1004:1004) (1075:1075:1075)) - (PORT datac (2234:2234:2234) (2300:2300:2300)) - (PORT datad (579:579:579) (616:616:616)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1272:1272:1272) (1273:1273:1273)) - (PORT datab (1249:1249:1249) (1339:1339:1339)) - (PORT datac (1511:1511:1511) (1599:1599:1599)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1520:1520:1520) (1576:1576:1576)) - (PORT datab (587:587:587) (613:613:613)) - (PORT datac (1428:1428:1428) (1442:1442:1442)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (380:380:380)) - (PORT datab (238:238:238) (283:283:283)) - (PORT datac (365:365:365) (388:388:388)) - (PORT datad (309:309:309) (325:325:325)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (670:670:670)) - (PORT datab (256:256:256) (308:308:308)) - (PORT datac (785:785:785) (803:803:803)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (675:675:675)) - (PORT datab (870:870:870) (878:878:878)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1092:1092:1092) (1131:1131:1131)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (733:733:733)) - (PORT datab (1205:1205:1205) (1231:1231:1231)) - (PORT datac (1352:1352:1352) (1391:1391:1391)) - (PORT datad (1717:1717:1717) (1758:1758:1758)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1506:1506:1506) (1560:1560:1560)) - (PORT datab (1446:1446:1446) (1461:1461:1461)) - (PORT datac (1144:1144:1144) (1188:1188:1188)) - (PORT datad (1462:1462:1462) (1558:1558:1558)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1422:1422:1422)) - (PORT datab (2164:2164:2164) (2264:2264:2264)) - (PORT datac (1307:1307:1307) (1351:1351:1351)) - (PORT datad (1411:1411:1411) (1421:1421:1421)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (263:263:263) (345:345:345)) - (PORT datac (978:978:978) (982:982:982)) - (PORT datad (590:590:590) (605:605:605)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (936:936:936)) - (PORT datab (1207:1207:1207) (1229:1229:1229)) - (PORT datac (615:615:615) (672:672:672)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1208:1208:1208)) - (PORT datab (1447:1447:1447) (1536:1536:1536)) - (PORT datac (788:788:788) (797:797:797)) - (PORT datad (1166:1166:1166) (1255:1255:1255)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (2422:2422:2422) (2510:2510:2510)) - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1119:1119:1119) (1176:1176:1176)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (935:935:935)) - (PORT datab (653:653:653) (708:708:708)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (808:808:808) (836:836:836)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (565:565:565)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (791:791:791) (829:829:829)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (744:744:744)) - (PORT datab (1407:1407:1407) (1399:1399:1399)) - (PORT datac (1258:1258:1258) (1274:1274:1274)) - (PORT datad (587:587:587) (605:605:605)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (555:555:555) (557:557:557)) - (PORT datad (626:626:626) (649:649:649)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (658:658:658)) - (PORT datab (909:909:909) (947:947:947)) - (PORT datac (866:866:866) (871:871:871)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (921:921:921)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1609:1609:1609) (1684:1684:1684)) - (PORT datad (616:616:616) (639:639:639)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (930:930:930) (949:949:949)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (277:277:277) (352:352:352)) - (PORT datab (1032:1032:1032) (1071:1071:1071)) - (PORT datad (812:812:812) (835:835:835)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (998:998:998) (1014:1014:1014)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (998:998:998) (1014:1014:1014)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (690:690:690)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (854:854:854) (900:900:900)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (972:972:972) (984:984:984)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (930:930:930) (949:949:949)) - (PORT ena (1472:1472:1472) (1481:1481:1481)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (704:704:704)) - (PORT datab (699:699:699) (744:744:744)) - (PORT datad (627:627:627) (656:656:656)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (555:555:555) (568:568:568)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1450:1450:1450) (1505:1505:1505)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (930:930:930) (946:946:946)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (341:341:341)) - (PORT datab (673:673:673) (741:741:741)) - (PORT datad (578:578:578) (595:595:595)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1447:1447:1447) (1426:1426:1426)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (698:698:698)) - (PORT datab (372:372:372) (394:394:394)) - (PORT datac (303:303:303) (325:325:325)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (867:867:867)) - (PORT datab (338:338:338) (372:372:372)) - (PORT datac (597:597:597) (618:618:618)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (1042:1042:1042) (1068:1068:1068)) - (PORT datac (564:564:564) (581:581:581)) - (PORT datad (1831:1831:1831) (1943:1943:1943)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (535:535:535) (566:566:566)) - (PORT ena (983:983:983) (976:976:976)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1268:1268:1268)) - (PORT datab (898:898:898) (922:922:922)) - (PORT datad (401:401:401) (427:427:427)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (421:421:421) (504:504:504)) - (PORT datac (447:447:447) (483:483:483)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (689:689:689)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (579:579:579) (597:597:597)) - (PORT datad (1422:1422:1422) (1524:1524:1524)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1646:1646:1646)) - (PORT datac (624:624:624) (647:647:647)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1547:1547:1547)) - (PORT ena (2484:2484:2484) (2511:2511:2511)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (270:270:270)) - (PORT datab (1120:1120:1120) (1163:1163:1163)) - (PORT datac (701:701:701) (759:759:759)) - (PORT datad (1064:1064:1064) (1090:1090:1090)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (811:811:811)) - (PORT datab (819:819:819) (831:831:831)) - (PORT datac (724:724:724) (731:731:731)) - (PORT datad (190:190:190) (223:223:223)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (187:187:187) (230:230:230)) - (PORT datad (689:689:689) (751:751:751)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (333:333:333) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (640:640:640)) - (PORT datab (1448:1448:1448) (1569:1569:1569)) - (PORT datac (594:594:594) (617:617:617)) - (PORT datad (620:620:620) (655:655:655)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1480:1480:1480) (1490:1490:1490)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1483:1483:1483) (1494:1494:1494)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (689:689:689)) - (PORT datab (882:882:882) (945:945:945)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (1693:1693:1693) (1706:1706:1706)) - (PORT ena (1258:1258:1258) (1246:1246:1246)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1543:1543:1543)) - (PORT asdata (1495:1495:1495) (1523:1523:1523)) - (PORT ena (1455:1455:1455) (1491:1491:1491)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (674:674:674)) - (PORT datab (420:420:420) (486:486:486)) - (PORT datad (584:584:584) (601:601:601)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (1513:1513:1513) (1527:1527:1527)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (276:276:276) (351:351:351)) - (PORT datab (841:841:841) (888:888:888)) - (PORT datad (812:812:812) (835:835:835)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1543:1543:1543)) - (PORT asdata (1495:1495:1495) (1522:1522:1522)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (433:433:433)) - (PORT datad (215:215:215) (248:248:248)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (221:221:221)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1475:1475:1475) (1471:1471:1471)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (1694:1694:1694) (1707:1707:1707)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1170:1170:1170)) - (PORT datab (902:902:902) (919:919:919)) - (PORT datad (234:234:234) (269:269:269)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (857:857:857)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (316:316:316) (335:335:335)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (955:955:955) (984:984:984)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (955:955:955) (984:984:984)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (733:733:733)) - (PORT datab (698:698:698) (738:738:738)) - (PORT datad (659:659:659) (682:682:682)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1253:1253:1253) (1283:1283:1283)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1250:1250:1250) (1280:1280:1280)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (706:706:706) (758:758:758)) - (PORT datad (682:682:682) (733:733:733)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (869:869:869)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datad (624:624:624) (640:640:640)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (454:454:454)) - (PORT datab (556:556:556) (579:579:579)) - (PORT datac (1308:1308:1308) (1322:1322:1322)) - (PORT datad (1285:1285:1285) (1413:1413:1413)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1085:1085:1085) (1161:1161:1161)) - (PORT datab (238:238:238) (283:283:283)) - (PORT datac (1265:1265:1265) (1292:1292:1292)) - (PORT datad (630:630:630) (659:659:659)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (916:916:916) (955:955:955)) - (PORT datac (1654:1654:1654) (1669:1669:1669)) - (PORT datad (641:641:641) (654:654:654)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (683:683:683)) - (PORT datab (201:201:201) (240:240:240)) - (PORT datac (589:589:589) (604:604:604)) - (PORT datad (625:625:625) (649:649:649)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1147:1147:1147)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (550:550:550) (573:573:573)) - (PORT datad (227:227:227) (272:272:272)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (895:895:895)) - (PORT datac (1192:1192:1192) (1289:1289:1289)) - (PORT datad (872:872:872) (902:902:902)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1148:1148:1148)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (1500:1500:1500) (1597:1597:1597)) - (PORT datad (1296:1296:1296) (1328:1328:1328)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (704:704:704)) - (PORT datab (913:913:913) (947:947:947)) - (PORT datad (897:897:897) (951:951:951)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1119:1119:1119) (1186:1186:1186)) - (PORT datab (419:419:419) (499:499:499)) - (PORT datac (410:410:410) (474:474:474)) - (PORT datad (1116:1116:1116) (1154:1154:1154)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (383:383:383)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1116:1116:1116) (1130:1130:1130)) - (PORT datad (1142:1142:1142) (1188:1188:1188)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (705:705:705)) - (PORT datab (911:911:911) (948:948:948)) - (PORT datac (1087:1087:1087) (1143:1143:1143)) - (PORT datad (897:897:897) (950:950:950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (652:652:652) (682:682:682)) - (PORT datac (1121:1121:1121) (1139:1139:1139)) - (PORT datad (1141:1141:1141) (1194:1194:1194)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (778:778:778)) - (PORT datab (842:842:842) (905:905:905)) - (PORT datac (659:659:659) (737:737:737)) - (PORT datad (864:864:864) (895:895:895)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (732:732:732) (835:835:835)) - (PORT datab (207:207:207) (250:250:250)) - (PORT datac (1367:1367:1367) (1393:1393:1393)) - (PORT datad (700:700:700) (780:780:780)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (405:405:405)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (336:336:336) (354:354:354)) - (PORT datad (211:211:211) (243:243:243)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~1) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (323:323:323) (347:347:347)) - (PORT datad (209:209:209) (241:241:241)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (701:701:701) (738:738:738)) - (PORT datac (1182:1182:1182) (1286:1286:1286)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (877:877:877) (930:930:930)) - (PORT datac (1497:1497:1497) (1599:1599:1599)) - (PORT datad (1296:1296:1296) (1332:1332:1332)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (972:972:972)) - (PORT datab (687:687:687) (768:768:768)) - (PORT datac (701:701:701) (797:797:797)) - (PORT datad (1060:1060:1060) (1072:1072:1072)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (1296:1296:1296) (1324:1324:1324)) - (PORT datac (636:636:636) (674:674:674)) - (PORT datad (1295:1295:1295) (1334:1334:1334)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (625:625:625)) - (PORT datab (375:375:375) (401:401:401)) - (PORT datac (1265:1265:1265) (1308:1308:1308)) - (PORT datad (585:585:585) (622:622:622)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (562:562:562) (577:577:577)) - (PORT datab (1159:1159:1159) (1193:1193:1193)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (837:837:837) (863:863:863)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (666:666:666)) - (PORT datab (877:877:877) (899:899:899)) - (PORT datac (660:660:660) (683:683:683)) - (PORT datad (229:229:229) (274:274:274)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (748:748:748)) - (PORT datab (618:618:618) (653:653:653)) - (PORT datac (1588:1588:1588) (1650:1650:1650)) - (PORT datad (637:637:637) (672:672:672)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1038:1038:1038) (1069:1069:1069)) - (PORT datab (1084:1084:1084) (1091:1091:1091)) - (PORT datac (363:363:363) (385:385:385)) - (PORT datad (867:867:867) (885:885:885)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1302:1302:1302) (1309:1309:1309)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (599:599:599) (621:621:621)) - (PORT datad (830:830:830) (843:843:843)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (671:671:671)) - (PORT datab (674:674:674) (704:704:704)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (608:608:608) (656:656:656)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (468:468:468)) - (PORT datab (379:379:379) (409:409:409)) - (PORT datac (626:626:626) (663:663:663)) - (PORT datad (806:806:806) (822:822:822)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1855:1855:1855) (1936:1936:1936)) - (PORT datab (869:869:869) (900:900:900)) - (PORT datac (906:906:906) (997:997:997)) - (PORT datad (1380:1380:1380) (1413:1413:1413)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2662:2662:2662) (2766:2766:2766)) - (PORT datab (1312:1312:1312) (1351:1351:1351)) - (PORT datac (903:903:903) (964:964:964)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (622:622:622)) - (PORT datab (665:665:665) (698:698:698)) - (PORT datac (498:498:498) (506:506:506)) - (PORT datad (520:520:520) (530:530:530)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (889:889:889)) - (PORT datab (600:600:600) (626:626:626)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1212:1212:1212) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1085:1085:1085)) - (PORT datab (1004:1004:1004) (1076:1076:1076)) - (PORT datac (2235:2235:2235) (2300:2300:2300)) - (PORT datad (581:581:581) (617:617:617)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1166:1166:1166)) - (PORT datab (860:860:860) (890:890:890)) - (PORT datac (846:846:846) (887:887:887)) - (PORT datad (822:822:822) (852:852:852)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1972:1972:1972) (2001:2001:2001)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (855:855:855) (926:926:926)) - (PORT datad (345:345:345) (371:371:371)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (598:598:598) (623:623:623)) - (PORT datac (808:808:808) (848:848:848)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (579:579:579)) - (PORT datab (1124:1124:1124) (1210:1210:1210)) - (PORT datac (841:841:841) (877:877:877)) - (PORT datad (1189:1189:1189) (1241:1241:1241)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (927:927:927)) - (PORT datab (1423:1423:1423) (1516:1516:1516)) - (PORT datac (1251:1251:1251) (1370:1370:1370)) - (PORT datad (1095:1095:1095) (1172:1172:1172)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (881:881:881)) - (PORT datab (2176:2176:2176) (2167:2167:2167)) - (PORT datac (846:846:846) (882:882:882)) - (PORT datad (1155:1155:1155) (1203:1203:1203)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (642:642:642) (677:677:677)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (634:634:634)) - (PORT datab (886:886:886) (905:905:905)) - (PORT datac (673:673:673) (708:708:708)) - (PORT datad (861:861:861) (882:882:882)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) - (DELAY - (ABSOLUTE - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (234:234:234) (274:274:274)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (967:967:967)) - (PORT datac (829:829:829) (856:856:856)) - (PORT datad (826:826:826) (854:854:854)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1163:1163:1163)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (846:846:846) (883:883:883)) - (PORT datad (341:341:341) (369:369:369)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (766:766:766)) - (PORT datab (450:450:450) (538:538:538)) - (PORT datac (440:440:440) (518:518:518)) - (PORT datad (1128:1128:1128) (1193:1193:1193)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (801:801:801)) - (PORT datab (910:910:910) (1004:1004:1004)) - (PORT datac (630:630:630) (695:695:695)) - (PORT datad (691:691:691) (752:752:752)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (466:466:466)) - (PORT datab (889:889:889) (1019:1019:1019)) - (PORT datac (652:652:652) (741:741:741)) - (PORT datad (673:673:673) (756:756:756)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1547:1547:1547)) - (PORT ena (2452:2452:2452) (2480:2480:2480)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (726:726:726)) - (PORT datab (261:261:261) (347:347:347)) - (PORT datac (1102:1102:1102) (1161:1161:1161)) - (PORT datad (406:406:406) (462:462:462)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (653:653:653)) - (PORT datab (630:630:630) (649:649:649)) - (PORT datac (1411:1411:1411) (1515:1515:1515)) - (PORT datad (319:319:319) (337:337:337)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1162:1162:1162)) - (PORT datab (915:915:915) (941:941:941)) - (PORT datad (536:536:536) (550:550:550)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1572:1572:1572) (1552:1552:1552)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (913:913:913) (996:996:996)) - (PORT datac (846:846:846) (883:883:883)) - (PORT datad (224:224:224) (297:297:297)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (965:965:965)) - (PORT datab (860:860:860) (892:892:892)) - (PORT datac (828:828:828) (858:858:858)) - (PORT datad (1931:1931:1931) (1953:1953:1953)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (738:738:738)) - (PORT datab (372:372:372) (407:407:407)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (612:612:612) (645:645:645)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (924:924:924)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1091:1091:1091) (1124:1124:1124)) - (PORT datad (1930:1930:1930) (1951:1951:1951)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1290:1290:1290) (1411:1411:1411)) - (PORT datab (1421:1421:1421) (1514:1514:1514)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (400:400:400)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (240:240:240) (317:317:317)) - (PORT datad (818:818:818) (845:845:845)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~13) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (652:652:652)) - (PORT datab (368:368:368) (389:389:389)) - (PORT datac (613:613:613) (633:633:633)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (934:934:934)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (863:863:863) (921:921:921)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (1417:1417:1417) (1449:1449:1449)) - (PORT datad (2061:2061:2061) (2141:2141:2141)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|flags_cond_true) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1066:1066:1066) (1102:1102:1102)) - (PORT datab (879:879:879) (936:936:936)) - (PORT datac (814:814:814) (829:829:829)) - (PORT datad (1555:1555:1555) (1605:1605:1605)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (688:688:688) (721:721:721)) - (PORT datac (1019:1019:1019) (1028:1028:1028)) - (PORT datad (606:606:606) (622:622:622)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (262:262:262)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (546:546:546) (557:557:557)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) - (DELAY - (ABSOLUTE - (PORT dataa (1069:1069:1069) (1101:1101:1101)) - (PORT datac (939:939:939) (962:962:962)) - (PORT datad (1013:1013:1013) (1020:1020:1020)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1166:1166:1166) (1217:1217:1217)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (192:192:192) (224:224:224)) - (PORT datad (584:584:584) (609:609:609)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (262:262:262)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (856:856:856) (854:854:854)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (388:388:388)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (193:193:193) (225:225:225)) - (PORT datad (636:636:636) (687:687:687)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (657:657:657)) - (PORT datab (595:595:595) (612:612:612)) - (PORT datac (1556:1556:1556) (1674:1674:1674)) - (PORT datad (1289:1289:1289) (1314:1314:1314)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1750:1750:1750) (1793:1793:1793)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1746:1746:1746) (1789:1789:1789)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (473:473:473)) - (PORT datab (435:435:435) (462:462:462)) - (PORT datad (357:357:357) (417:417:417)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1448:1448:1448) (1467:1467:1467)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1210:1210:1210) (1281:1281:1281)) - (PORT datab (1383:1383:1383) (1451:1451:1451)) - (PORT datad (1861:1861:1861) (1917:1917:1917)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1773:1773:1773) (1820:1820:1820)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1771:1771:1771) (1826:1826:1826)) - (PORT ena (1525:1525:1525) (1527:1527:1527)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (483:483:483)) - (PORT datab (422:422:422) (469:469:469)) - (PORT datad (362:362:362) (420:420:420)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (931:931:931) (961:961:961)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (934:934:934) (964:964:964)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (510:510:510)) - (PORT datab (242:242:242) (325:325:325)) - (PORT datad (669:669:669) (698:698:698)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1739:1739:1739) (1780:1780:1780)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1740:1740:1740) (1778:1778:1778)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (701:701:701)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (627:627:627) (646:646:646)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1772:1772:1772) (1828:1828:1828)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1336:1336:1336) (1363:1363:1363)) - (PORT datab (1101:1101:1101) (1115:1115:1115)) - (PORT datad (387:387:387) (412:412:412)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (673:673:673)) - (PORT datab (685:685:685) (705:705:705)) - (PORT datac (599:599:599) (618:618:618)) - (PORT datad (580:580:580) (603:603:603)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (883:883:883) (916:916:916)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1445:1445:1445) (1463:1463:1463)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (454:454:454)) - (PORT datab (406:406:406) (433:433:433)) - (PORT datad (655:655:655) (713:713:713)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (711:711:711)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (2006:2006:2006) (2147:2147:2147)) - (PORT datab (588:588:588) (606:606:606)) - (PORT datac (558:558:558) (586:586:586)) - (PORT datad (853:853:853) (863:863:863)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (899:899:899) (925:925:925)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (933:933:933) (1003:1003:1003)) - (PORT datad (233:233:233) (291:291:291)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) @@ -29574,1684 +28075,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~8) + (INSTANCE z80_\|alu_\|db_low\[2\]\~5) (DELAY (ABSOLUTE - (PORT dataa (342:342:342) (372:372:372)) - (PORT datab (454:454:454) (485:485:485)) - (PORT datad (219:219:219) (289:289:289)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (277:277:277)) - (PORT datab (1084:1084:1084) (1121:1121:1121)) - (PORT datac (652:652:652) (743:743:743)) - (PORT datad (391:391:391) (453:453:453)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (651:651:651) (725:725:725)) - (PORT datad (1040:1040:1040) (1058:1058:1058)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (404:404:404) (441:441:441)) - (PORT datac (1657:1657:1657) (1782:1782:1782)) - (PORT datad (621:621:621) (656:656:656)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) - (DELAY - (ABSOLUTE - (PORT datac (1515:1515:1515) (1605:1605:1605)) - (PORT datad (972:972:972) (1033:1033:1033)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1547:1547:1547)) - (PORT ena (2484:2484:2484) (2511:2511:2511)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (1029:1029:1029) (1068:1068:1068)) - (PORT datab (450:450:450) (537:537:537)) - (PORT datac (649:649:649) (725:725:725)) - (PORT datad (1040:1040:1040) (1058:1058:1058)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (669:669:669) (700:700:700)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (616:616:616)) - (PORT datab (932:932:932) (1003:1003:1003)) - (PORT datad (232:232:232) (285:285:285)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (399:399:399)) - (PORT datab (460:460:460) (495:495:495)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (999:999:999) (1080:1080:1080)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (1664:1664:1664) (1792:1792:1792)) - (PORT datad (371:371:371) (397:397:397)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) - (DELAY - (ABSOLUTE - (PORT dataa (1555:1555:1555) (1647:1647:1647)) - (PORT datac (588:588:588) (634:634:634)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1547:1547:1547)) - (PORT ena (2484:2484:2484) (2511:2511:2511)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1028:1028:1028) (1069:1069:1069)) - (PORT datab (446:446:446) (536:536:536)) - (PORT datac (648:648:648) (724:724:724)) - (PORT datad (1040:1040:1040) (1059:1059:1059)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (376:376:376)) - (PORT datab (405:405:405) (475:475:475)) - (PORT datac (620:620:620) (644:644:644)) - (PORT datad (401:401:401) (457:457:457)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT datab (401:401:401) (476:476:476)) - (PORT datad (187:187:187) (220:220:220)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (711:711:711) (733:733:733)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (264:264:264) (336:336:336)) - (PORT datab (929:929:929) (995:995:995)) - (PORT datad (568:568:568) (588:588:588)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (455:455:455) (495:495:495)) - (PORT datac (216:216:216) (292:292:292)) - (PORT datad (306:306:306) (322:322:322)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (690:690:690)) - (PORT datab (404:404:404) (434:434:434)) - (PORT datac (1660:1660:1660) (1785:1785:1785)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) - (DELAY - (ABSOLUTE - (PORT datac (1491:1491:1491) (1572:1572:1572)) - (PORT datad (607:607:607) (645:645:645)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1547:1547:1547)) - (PORT ena (2452:2452:2452) (2480:2480:2480)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) - (DELAY - (ABSOLUTE - (PORT datac (616:616:616) (642:642:642)) - (PORT datad (375:375:375) (438:438:438)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (270:270:270)) - (PORT datab (1119:1119:1119) (1168:1168:1168)) - (PORT datac (655:655:655) (710:710:710)) - (PORT datad (1061:1061:1061) (1090:1090:1090)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (777:777:777)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (232:232:232) (315:315:315)) - (PORT datad (804:804:804) (817:817:817)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (949:949:949) (965:965:965)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (262:262:262) (334:334:334)) - (PORT datab (613:613:613) (631:631:631)) - (PORT datad (894:894:894) (962:962:962)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (459:459:459) (492:492:492)) - (PORT datac (314:314:314) (336:336:336)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (691:691:691)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1664:1664:1664) (1793:1793:1793)) - (PORT datad (370:370:370) (393:393:393)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (715:715:715)) - (PORT datac (1492:1492:1492) (1576:1576:1576)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) - (DELAY - (ABSOLUTE - (PORT datab (1051:1051:1051) (1091:1091:1091)) - (PORT datac (334:334:334) (362:362:362)) - (PORT datad (1332:1332:1332) (1382:1382:1382)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (808:808:808)) - (PORT datab (1553:1553:1553) (1675:1675:1675)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1402:1402:1402) (1495:1495:1495)) - (PORT datab (858:858:858) (927:927:927)) - (PORT datac (1160:1160:1160) (1279:1279:1279)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1822:1822:1822) (1903:1903:1903)) - (PORT datab (1155:1155:1155) (1229:1229:1229)) - (PORT datac (1968:1968:1968) (2075:2075:2075)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (414:414:414)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (884:884:884) (926:926:926)) - (PORT datad (908:908:908) (941:941:941)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (619:619:619)) - (PORT datab (1154:1154:1154) (1227:1227:1227)) - (PORT datac (1964:1964:1964) (2069:2069:2069)) - (PORT datad (556:556:556) (583:583:583)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (957:957:957) (1028:1028:1028)) - (PORT datac (1216:1216:1216) (1233:1233:1233)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1080:1080:1080)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (1172:1172:1172) (1293:1293:1293)) - (PORT datad (1048:1048:1048) (1069:1069:1069)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1396:1396:1396) (1481:1481:1481)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1173:1173:1173) (1294:1294:1294)) - (PORT datad (1115:1115:1115) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (576:576:576) (657:657:657)) - (PORT sload (1915:1915:1915) (1964:1964:1964)) - (PORT ena (1897:1897:1897) (1898:1898:1898)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (1198:1198:1198) (1259:1259:1259)) - (PORT datad (2699:2699:2699) (2899:2899:2899)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT datab (276:276:276) (370:370:370)) - (PORT datac (671:671:671) (730:730:730)) - (PORT datad (328:328:328) (353:353:353)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (700:700:700)) - (PORT datab (317:317:317) (412:412:412)) - (PORT datac (934:934:934) (1001:1001:1001)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (761:761:761)) - (PORT datab (473:473:473) (546:546:546)) - (PORT datac (1085:1085:1085) (1155:1155:1155)) - (PORT datad (1203:1203:1203) (1255:1255:1255)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (786:786:786)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datad (1163:1163:1163) (1228:1228:1228)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (747:747:747) (828:828:828)) - (PORT datab (608:608:608) (625:625:625)) - (PORT datad (828:828:828) (841:841:841)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (747:747:747) (827:827:827)) - (PORT datab (424:424:424) (509:509:509)) - (PORT datac (950:950:950) (1011:1011:1011)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (702:702:702)) - (PORT datab (962:962:962) (1026:1026:1026)) - (PORT datac (896:896:896) (956:956:956)) - (PORT datad (401:401:401) (447:447:447)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1011:1011:1011)) - (PORT datab (980:980:980) (1038:1038:1038)) - (PORT datac (950:950:950) (1010:1010:1010)) - (PORT datad (740:740:740) (812:812:812)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (829:829:829)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (856:856:856) (932:932:932)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (248:248:248)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (580:580:580)) - (PORT datab (1554:1554:1554) (1672:1672:1672)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (956:956:956) (1024:1024:1024)) - (PORT sload (1915:1915:1915) (1964:1964:1964)) - (PORT ena (1897:1897:1897) (1898:1898:1898)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[14\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (3043:3043:3043) (3292:3292:3292)) - (PORT datac (1488:1488:1488) (1594:1594:1594)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (744:744:744)) - (PORT datab (861:861:861) (899:899:899)) - (PORT datac (615:615:615) (664:664:664)) - (PORT datad (909:909:909) (956:956:956)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (813:813:813)) - (PORT datab (276:276:276) (371:371:371)) - (PORT datac (672:672:672) (733:733:733)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT datac (1157:1157:1157) (1229:1229:1229)) - (PORT datad (440:440:440) (516:516:516)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (728:728:728)) - (PORT datab (567:567:567) (594:594:594)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (924:924:924) (976:976:976)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT datab (907:907:907) (922:922:922)) - (PORT datac (645:645:645) (710:710:710)) - (PORT datad (1137:1137:1137) (1178:1178:1178)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (757:757:757)) - (PORT datab (387:387:387) (414:414:414)) - (PORT datad (448:448:448) (529:529:529)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (1579:1579:1579) (1680:1680:1680)) - (PORT datad (353:353:353) (384:384:384)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1794:1794:1794) (1888:1888:1888)) - (PORT sload (1678:1678:1678) (1738:1738:1738)) - (PORT ena (2119:2119:2119) (2120:2120:2120)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (3321:3321:3321) (3558:3558:3558)) - (PORT datad (865:865:865) (930:930:930)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (574:574:574)) - (PORT datac (653:653:653) (707:707:707)) - (PORT datad (881:881:881) (925:925:925)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (622:622:622)) - (PORT datab (1084:1084:1084) (1160:1160:1160)) - (PORT datac (410:410:410) (481:481:481)) - (PORT datad (625:625:625) (645:645:645)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (754:754:754)) - (PORT datab (223:223:223) (261:261:261)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (1538:1538:1538) (1635:1635:1635)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (787:787:787) (862:862:862)) - (PORT sload (1678:1678:1678) (1738:1738:1738)) - (PORT ena (2119:2119:2119) (2120:2120:2120)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[11\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (3322:3322:3322) (3562:3562:3562)) - (PORT datad (1450:1450:1450) (1535:1535:1535)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (328:328:328)) - (PORT datab (908:908:908) (964:964:964)) - (PORT datac (214:214:214) (289:289:289)) - (PORT datad (801:801:801) (824:824:824)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (752:752:752)) - (PORT datac (951:951:951) (1030:1030:1030)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (721:721:721) (790:790:790)) - (PORT datab (961:961:961) (1034:1034:1034)) - (PORT datad (429:429:429) (504:504:504)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (983:983:983)) - (PORT datab (593:593:593) (618:618:618)) - (PORT datac (928:928:928) (986:986:986)) - (PORT datad (536:536:536) (551:551:551)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (269:269:269)) - (PORT datab (208:208:208) (251:251:251)) - (PORT datad (709:709:709) (792:792:792)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1558:1558:1558)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (433:433:433)) - (PORT datab (1576:1576:1576) (1677:1677:1677)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (768:768:768) (840:840:840)) - (PORT sload (1678:1678:1678) (1738:1738:1738)) - (PORT ena (2119:2119:2119) (2120:2120:2120)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (2452:2452:2452) (2613:2613:2613)) - (PORT datad (2501:2501:2501) (2606:2606:2606)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (1557:1557:1557) (1677:1677:1677)) - (PORT datad (315:315:315) (337:337:337)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1447:1447:1447) (1504:1504:1504)) - (PORT sload (1915:1915:1915) (1964:1964:1964)) - (PORT ena (1897:1897:1897) (1898:1898:1898)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~23) - (DELAY - (ABSOLUTE - (PORT datac (3017:3017:3017) (3263:3263:3263)) - (PORT datad (1455:1455:1455) (1525:1525:1525)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (1049:1049:1049)) - (PORT datab (1092:1092:1092) (1157:1157:1157)) - (PORT datad (871:871:871) (933:933:933)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT datab (316:316:316) (409:409:409)) - (PORT datac (627:627:627) (666:666:666)) - (PORT datad (941:941:941) (1006:1006:1006)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1054:1054:1054)) - (PORT datab (1196:1196:1196) (1252:1252:1252)) - (PORT datad (920:920:920) (987:987:987)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (746:746:746) (828:828:828)) - (PORT datab (424:424:424) (510:510:510)) - (PORT datac (909:909:909) (970:970:970)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datad (309:309:309) (323:323:323)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (890:890:890)) - (PORT datab (1427:1427:1427) (1485:1485:1485)) - (PORT datac (845:845:845) (897:897:897)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (219:219:219) (259:259:259)) - (PORT datad (1539:1539:1539) (1640:1640:1640)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (994:994:994) (1068:1068:1068)) - (PORT sload (1678:1678:1678) (1738:1738:1738)) - (PORT ena (2119:2119:2119) (2120:2120:2120)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~19) - (DELAY - (ABSOLUTE - (PORT datac (1651:1651:1651) (1732:1732:1732)) - (PORT datad (2405:2405:2405) (2560:2560:2560)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (240:240:240)) - (PORT datab (807:807:807) (828:828:828)) - (PORT datad (1725:1725:1725) (1791:1791:1791)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1539:1539:1539)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2675:2675:2675) (2768:2768:2768)) - (PORT sload (1762:1762:1762) (1828:1828:1828)) - (PORT ena (1696:1696:1696) (1694:1694:1694)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~20) - (DELAY - (ABSOLUTE - (PORT datac (846:846:846) (912:912:912)) - (PORT datad (2996:2996:2996) (3237:3237:3237)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (424:424:424) (512:512:512)) - (PORT datac (706:706:706) (785:785:785)) - (PORT datad (742:742:742) (817:817:817)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (573:573:573)) - (PORT datab (689:689:689) (742:742:742)) - (PORT datac (934:934:934) (1003:1003:1003)) - (PORT datad (879:879:879) (921:921:921)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1056:1056:1056)) - (PORT datab (926:926:926) (993:993:993)) - (PORT datac (615:615:615) (671:671:671)) - (PORT datad (550:550:550) (553:553:553)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (410:410:410)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (595:595:595) (609:609:609)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (692:692:692)) - (PORT datac (412:412:412) (484:484:484)) - (PORT datad (1058:1058:1058) (1119:1119:1119)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (703:703:703) (784:784:784)) - (PORT datac (942:942:942) (1017:1017:1017)) - (PORT datad (1108:1108:1108) (1175:1175:1175)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (574:574:574)) - (PORT datac (932:932:932) (1003:1003:1003)) - (PORT datad (577:577:577) (583:583:583)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (760:760:760)) - (PORT datab (373:373:373) (394:394:394)) - (PORT datad (314:314:314) (323:323:323)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (2022:2022:2022) (2086:2086:2086)) - (PORT datab (597:597:597) (612:612:612)) - (PORT datac (558:558:558) (607:607:607)) - (PORT datad (361:361:361) (419:419:419)) + (PORT dataa (460:460:460) (538:538:538)) + (PORT datab (638:638:638) (705:705:705)) + (PORT datac (1102:1102:1102) (1133:1133:1133)) + (PORT datad (662:662:662) (719:719:719)) (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -31259,149 +28089,15 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (619:619:619)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (833:833:833) (844:844:844)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (851:851:851) (897:897:897)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|DFF_inst5) + (INSTANCE z80_\|alu_\|result_lo\[2\]) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT clk (1518:1518:1518) (1535:1535:1535)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) + (PORT ena (1283:1283:1283) (1287:1287:1287)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (300:300:300)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) - (DELAY - (ABSOLUTE - (PORT clk (1543:1543:1543) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (567:567:567) (646:646:646)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (734:734:734)) - (PORT datab (1012:1012:1012) (1033:1033:1033)) - (PORT datac (1020:1020:1020) (1033:1033:1033)) - (PORT datad (853:853:853) (868:868:868)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~8) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (624:624:624)) - (PORT datab (1149:1149:1149) (1161:1161:1161)) - (PORT datac (923:923:923) (997:997:997)) - (PORT datad (820:820:820) (841:841:841)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~9) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (563:563:563)) - (PORT datab (379:379:379) (403:403:403)) - (PORT datac (793:793:793) (819:819:819)) - (PORT datad (627:627:627) (659:659:659)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1460:1460:1460) (1461:1461:1461)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK @@ -31411,143 +28107,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) + (INSTANCE z80_\|alu_\|db_low\[2\]\~6) (DELAY (ABSOLUTE - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1460:1460:1460) (1461:1461:1461)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (225:225:225) (296:296:296)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) - (DELAY - (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT asdata (567:567:567) (643:643:643)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|iorq\~0) - (DELAY - (ABSOLUTE - (PORT datab (249:249:249) (333:333:333)) - (PORT datad (223:223:223) (294:294:294)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (341:341:341)) - (PORT datad (795:795:795) (800:800:800)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (710:710:710)) - (PORT datab (841:841:841) (884:884:884)) - (PORT datac (619:619:619) (647:647:647)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1546:1546:1546) (1607:1607:1607)) - (PORT datab (940:940:940) (1007:1007:1007)) - (PORT datac (938:938:938) (970:970:970)) - (PORT datad (859:859:859) (900:900:900)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (554:554:554) (563:563:563)) - (PORT datac (876:876:876) (893:893:893)) - (PORT datad (569:569:569) (579:579:579)) + (PORT dataa (339:339:339) (368:368:368)) + (PORT datab (597:597:597) (636:636:636)) + (PORT datac (965:965:965) (999:999:999)) + (PORT datad (590:590:590) (645:645:645)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -31557,93 +28123,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~36) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) (DELAY (ABSOLUTE - (PORT dataa (1227:1227:1227) (1328:1328:1328)) - (PORT datab (611:611:611) (646:646:646)) - (PORT datac (891:891:891) (977:977:977)) - (PORT datad (785:785:785) (805:805:805)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1147:1147:1147) (1192:1192:1192)) - (PORT datab (429:429:429) (463:463:463)) - (PORT datac (1712:1712:1712) (1761:1761:1761)) - (PORT datad (1211:1211:1211) (1200:1200:1200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (670:670:670)) - (PORT datab (631:631:631) (690:690:690)) - (PORT datad (1881:1881:1881) (1830:1830:1830)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1214:1214:1214)) - (PORT datab (1426:1426:1426) (1516:1516:1516)) - (PORT datac (1076:1076:1076) (1125:1125:1125)) - (PORT datad (1419:1419:1419) (1527:1527:1527)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1757:1757:1757) (1786:1786:1786)) - (PORT datab (894:894:894) (910:910:910)) - (PORT datac (925:925:925) (1021:1021:1021)) - (PORT datad (1185:1185:1185) (1275:1275:1275)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1323:1323:1323)) - (PORT datab (857:857:857) (861:861:861)) - (PORT datac (928:928:928) (1025:1025:1025)) - (PORT datad (615:615:615) (646:646:646)) + (PORT dataa (222:222:222) (276:276:276)) + (PORT datab (653:653:653) (675:675:675)) + (PORT datac (916:916:916) (949:949:949)) + (PORT datad (220:220:220) (264:264:264)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (337:337:337)) + (PORT datab (596:596:596) (614:614:614)) + (PORT datac (585:585:585) (589:589:589)) + (PORT datad (896:896:896) (944:944:944)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (534:534:534)) + (PORT datab (695:695:695) (720:720:720)) + (PORT datac (877:877:877) (900:900:900)) + (PORT datad (417:417:417) (490:490:490)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (411:411:411)) + (PORT datab (395:395:395) (424:424:424)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (345:345:345) (368:368:368)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31651,13 +28203,137 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) (DELAY (ABSOLUTE - (PORT dataa (1056:1056:1056) (1091:1091:1091)) - (PORT datab (866:866:866) (878:878:878)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (176:176:176) (202:202:202)) + (PORT dataa (368:368:368) (407:407:407)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (354:354:354) (383:383:383)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1207:1207:1207)) + (PORT datab (281:281:281) (344:344:344)) + (PORT datac (244:244:244) (303:303:303)) + (PORT datad (255:255:255) (301:301:301)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1695:1695:1695) (1779:1779:1779)) + (PORT datac (887:887:887) (904:904:904)) + (PORT datad (883:883:883) (900:900:900)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (911:911:911) (960:960:960)) + (PORT datad (237:237:237) (277:277:277)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (711:711:711)) + (PORT datab (1166:1166:1166) (1213:1213:1213)) + (PORT datac (421:421:421) (493:493:493)) + (PORT datad (662:662:662) (719:719:719)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1116:1116:1116) (1164:1164:1164)) + (PORT datac (603:603:603) (622:622:622)) + (PORT datad (629:629:629) (654:654:654)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1347:1347:1347)) + (PORT datab (239:239:239) (295:295:295)) + (PORT datac (959:959:959) (993:993:993)) + (PORT datad (329:329:329) (348:348:348)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1295:1295:1295) (1347:1347:1347)) + (PORT datab (963:963:963) (1021:1021:1021)) + (PORT datac (1621:1621:1621) (1653:1653:1653)) + (PORT datad (867:867:867) (886:886:886)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (667:667:667)) + (PORT datab (983:983:983) (1034:1034:1034)) + (PORT datac (313:313:313) (343:343:343)) + (PORT datad (228:228:228) (273:273:273)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -31667,13 +28343,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~4) + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) (DELAY (ABSOLUTE - (PORT datab (644:644:644) (684:684:684)) - (PORT datac (815:815:815) (834:834:834)) - (PORT datad (587:587:587) (605:605:605)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (390:390:390) (465:465:465)) + (PORT datab (263:263:263) (345:345:345)) + (PORT datac (236:236:236) (312:312:312)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1227:1227:1227)) + (PORT datab (658:658:658) (671:671:671)) + (PORT datac (632:632:632) (691:691:691)) + (PORT datad (234:234:234) (310:310:310)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1213:1213:1213)) + (PORT datab (894:894:894) (942:942:942)) + (PORT datac (660:660:660) (687:687:687)) + (PORT datad (883:883:883) (901:901:901)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31681,15 +28391,153 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (INSTANCE z80_\|alu_control_\|db\[6\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1333:1333:1333) (1368:1368:1368)) - (PORT datab (977:977:977) (1007:1007:1007)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (223:223:223) (259:259:259)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (924:924:924) (933:933:933)) + (PORT datac (1121:1121:1121) (1153:1153:1153)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1018:1018:1018)) + (PORT datab (950:950:950) (1001:1001:1001)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (876:876:876) (911:911:911)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (714:714:714)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1597:1597:1597) (1627:1627:1627)) + (PORT datad (861:861:861) (875:875:875)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (655:655:655)) + (PORT datab (1245:1245:1245) (1272:1272:1272)) + (PORT datac (1147:1147:1147) (1195:1195:1195)) + (PORT datad (336:336:336) (365:365:365)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (348:348:348)) + (PORT datad (249:249:249) (295:295:295)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1571:1571:1571) (1550:1550:1550)) + (PORT ena (1258:1258:1258) (1280:1280:1280)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1260:1260:1260)) + (PORT datab (1208:1208:1208) (1291:1291:1291)) + (PORT datac (1222:1222:1222) (1290:1290:1290)) + (PORT datad (272:272:272) (349:349:349)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (485:485:485)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1143:1143:1143) (1174:1174:1174)) + (PORT datad (1174:1174:1174) (1212:1212:1212)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1051:1051:1051)) + (PORT datab (1152:1152:1152) (1212:1212:1212)) + (PORT datac (671:671:671) (716:716:716)) + (PORT datad (621:621:621) (670:670:670)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (864:864:864) (885:885:885)) + (PORT datac (946:946:946) (986:986:986)) + (PORT datad (214:214:214) (249:249:249)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31700,26 +28548,214 @@ (INSTANCE z80_\|execute_\|ctl_mRead\~37) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (647:647:647) (684:684:684)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1300:1300:1300) (1399:1399:1399)) + (PORT datab (2075:2075:2075) (2259:2259:2259)) + (PORT datac (822:822:822) (879:879:879)) + (PORT datad (913:913:913) (964:964:964)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1269:1269:1269) (1304:1304:1304)) + (PORT datac (1404:1404:1404) (1456:1456:1456)) + (PORT datad (913:913:913) (977:977:977)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (241:241:241) (281:281:281)) + (PORT datac (1941:1941:1941) (2072:2072:2072)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (914:914:914)) + (PORT datab (230:230:230) (277:277:277)) + (PORT datac (631:631:631) (653:653:653)) + (PORT datad (955:955:955) (999:999:999)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1051:1051:1051) (1095:1095:1095)) + (PORT datab (1067:1067:1067) (1105:1105:1105)) + (PORT datac (1033:1033:1033) (1064:1064:1064)) + (PORT datad (634:634:634) (644:644:644)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (1056:1056:1056)) + (PORT datab (1130:1130:1130) (1132:1132:1132)) + (PORT datac (939:939:939) (1031:1031:1031)) + (PORT datad (1060:1060:1060) (1062:1062:1062)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~38) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (940:940:940)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (539:539:539) (555:555:555)) + (PORT datad (545:545:545) (556:556:556)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (715:715:715)) + (PORT datab (898:898:898) (929:929:929)) + (PORT datac (1980:1980:1980) (2019:2019:2019)) + (PORT datad (830:830:830) (842:842:842)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~3) + (DELAY + (ABSOLUTE + (PORT datab (833:833:833) (894:894:894)) + (PORT datac (622:622:622) (675:675:675)) + (PORT datad (207:207:207) (239:239:239)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (279:279:279)) + (PORT datab (238:238:238) (284:284:284)) + (PORT datac (356:356:356) (385:385:385)) + (PORT datad (1060:1060:1060) (1062:1062:1062)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (787:787:787)) + (PORT datab (1609:1609:1609) (1627:1627:1627)) + (PORT datac (617:617:617) (649:649:649)) + (PORT datad (544:544:544) (562:562:562)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT datab (553:553:553) (575:575:575)) + (PORT datac (1318:1318:1318) (1317:1317:1317)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1048:1048:1048) (1070:1070:1070)) + (PORT datab (577:577:577) (591:591:591)) + (PORT datac (783:783:783) (785:785:785)) + (PORT datad (770:770:770) (770:770:770)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1554:1554:1554)) + (PORT clk (1535:1535:1535) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1433:1433:1433) (1418:1418:1418)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1291:1291:1291) (1310:1310:1310)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31734,7 +28770,7 @@ (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) (DELAY (ABSOLUTE - (PORT datad (361:361:361) (412:412:412)) + (PORT datad (815:815:815) (866:866:866)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31744,10 +28780,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_mrd) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) + (PORT clk (1540:1540:1540) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) + (PORT clrn (1588:1588:1588) (1565:1565:1565)) + (PORT ena (1172:1172:1172) (1151:1151:1151)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31762,10 +28798,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT asdata (574:574:574) (658:658:658)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) + (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT asdata (1226:1226:1226) (1290:1290:1290)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31780,22 +28816,150 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (350:350:350)) - (PORT datac (215:215:215) (291:291:291)) + (PORT dataa (909:909:909) (983:983:983)) + (PORT datad (215:215:215) (284:284:284)) (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~4) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (281:281:281)) + (PORT datab (702:702:702) (781:781:781)) + (PORT datac (856:856:856) (898:898:898)) + (PORT datad (1074:1074:1074) (1111:1111:1111)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1890:1890:1890) (1960:1960:1960)) + (PORT datab (1472:1472:1472) (1522:1522:1522)) + (PORT datac (1489:1489:1489) (1536:1536:1536)) + (PORT datad (1919:1919:1919) (1985:1985:1985)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1152:1152:1152)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (201:201:201) (236:236:236)) + (PORT datad (679:679:679) (747:747:747)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~9) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (891:891:891)) + (PORT datab (1170:1170:1170) (1227:1227:1227)) + (PORT datac (822:822:822) (840:840:840)) + (PORT datad (805:805:805) (814:814:814)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT asdata (1818:1818:1818) (1849:1849:1849)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) + (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1291:1291:1291) (1310:1310:1310)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (220:220:220) (290:290:290)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1291:1291:1291) (1310:1310:1310)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT asdata (581:581:581) (655:655:655)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT asdata (567:567:567) (645:645:645)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31805,12 +28969,107 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|iorq\~0) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (PORT datad (613:613:613) (663:663:663)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (941:941:941) (1024:1024:1024)) + (PORT datac (374:374:374) (401:401:401)) + (PORT datad (217:217:217) (243:243:243)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (913:913:913)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (1187:1187:1187) (1208:1208:1208)) + (PORT datad (1091:1091:1091) (1137:1137:1137)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1889:1889:1889) (1932:1932:1932)) + (PORT datab (1525:1525:1525) (1597:1597:1597)) + (PORT datac (2202:2202:2202) (2248:2248:2248)) + (PORT datad (210:210:210) (242:242:242)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (263:263:263)) + (PORT datab (336:336:336) (366:366:366)) + (PORT datac (586:586:586) (589:589:589)) + (PORT datad (351:351:351) (382:382:382)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1588:1588:1588) (1563:1563:1563)) + (PORT ena (1810:1810:1810) (1851:1851:1851)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) (DELAY (ABSOLUTE - (PORT datad (220:220:220) (290:290:290)) + (PORT datad (586:586:586) (642:642:642)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31820,10 +29079,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) + (PORT clk (1542:1542:1542) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31838,10 +29097,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT asdata (567:567:567) (646:646:646)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1460:1460:1460) (1461:1461:1461)) + (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT asdata (568:568:568) (646:646:646)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1291:1291:1291) (1310:1310:1310)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31856,11 +29115,11 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (341:341:341)) - (PORT datab (934:934:934) (977:977:977)) - (PORT datad (693:693:693) (763:763:763)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1456:1456:1456) (1520:1520:1520)) + (PORT datab (251:251:251) (336:336:336)) + (PORT datad (1485:1485:1485) (1574:1574:1574)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31871,96 +29130,693 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (586:586:586) (613:613:613)) - (PORT datad (204:204:204) (232:232:232)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (340:340:340) (376:376:376)) + (PORT datab (352:352:352) (391:391:391)) + (PORT datac (1027:1027:1027) (1030:1030:1030)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1747:1747:1747) (1852:1852:1852)) + (PORT datab (1597:1597:1597) (1730:1730:1730)) + (PORT datac (1200:1200:1200) (1265:1265:1265)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2395:2395:2395) (2551:2551:2551)) + (PORT datad (1014:1014:1014) (1128:1128:1128)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~5) + (DELAY + (ABSOLUTE + (PORT datab (1342:1342:1342) (1445:1445:1445)) + (PORT datac (2885:2885:2885) (3060:3060:3060)) + (PORT datad (2470:2470:2470) (2672:2672:2672)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (401:401:401)) + (PORT datab (883:883:883) (892:892:892)) + (PORT datac (957:957:957) (1029:1029:1029)) + (PORT datad (1073:1073:1073) (1058:1058:1058)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1027:1027:1027)) + (PORT datac (1189:1189:1189) (1270:1270:1270)) + (PORT datad (2029:2029:2029) (2154:2154:2154)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1470:1470:1470) (1514:1514:1514)) + (PORT datab (897:897:897) (976:976:976)) + (PORT datac (362:362:362) (383:383:383)) + (PORT datad (193:193:193) (218:218:218)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (736:736:736)) + (PORT datab (837:837:837) (873:873:873)) + (PORT datac (876:876:876) (891:891:891)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1311:1311:1311)) + (PORT datab (870:870:870) (881:881:881)) + (PORT datac (1299:1299:1299) (1298:1298:1298)) + (PORT datad (625:625:625) (681:681:681)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (242:242:242)) + (PORT datab (1100:1100:1100) (1104:1104:1104)) + (PORT datac (369:369:369) (395:395:395)) + (PORT datad (1798:1798:1798) (1887:1887:1887)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~7) + (DELAY + (ABSOLUTE + (PORT datab (916:916:916) (964:964:964)) + (PORT datac (850:850:850) (896:896:896)) + (PORT datad (781:781:781) (791:791:791)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1515:1515:1515) (1583:1583:1583)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1714:1714:1714) (1760:1760:1760)) + (PORT datad (881:881:881) (920:920:920)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1447:1447:1447) (1506:1506:1506)) + (PORT datab (1169:1169:1169) (1174:1174:1174)) + (PORT datac (894:894:894) (923:923:923)) + (PORT datad (781:781:781) (794:794:794)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1513:1513:1513) (1581:1581:1581)) + (PORT datab (1150:1150:1150) (1204:1204:1204)) + (PORT datac (1094:1094:1094) (1111:1111:1111)) + (PORT datad (616:616:616) (634:634:634)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1361:1361:1361)) + (PORT datab (869:869:869) (894:894:894)) + (PORT datac (1706:1706:1706) (1761:1761:1761)) + (PORT datad (263:263:263) (315:315:315)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1146:1146:1146) (1188:1188:1188)) + (PORT datab (214:214:214) (258:258:258)) + (PORT datac (192:192:192) (225:225:225)) + (PORT datad (621:621:621) (651:651:651)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (1051:1051:1051) (1068:1068:1068)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1104:1104:1104)) + (PORT datab (879:879:879) (888:888:888)) + (PORT datac (609:609:609) (624:624:624)) + (PORT datad (1198:1198:1198) (1221:1221:1221)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (927:927:927)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (583:583:583) (601:601:601)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (332:332:332) (351:351:351)) + (PORT datad (813:813:813) (840:840:840)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (906:906:906)) + (PORT datab (1043:1043:1043) (1098:1098:1098)) + (PORT datac (1093:1093:1093) (1111:1111:1111)) + (PORT datad (1130:1130:1130) (1132:1132:1132)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (247:247:247)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (605:605:605)) + (PORT datab (1113:1113:1113) (1136:1136:1136)) + (PORT datac (1714:1714:1714) (1760:1760:1760)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (726:726:726)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (612:612:612) (639:639:639)) + (PORT datad (196:196:196) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (930:930:930) (979:979:979)) + (PORT datac (1054:1054:1054) (1167:1167:1167)) + (PORT datad (1137:1137:1137) (1183:1183:1183)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (296:296:296)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|DFF_inst5) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1587:1587:1587) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (228:228:228) (301:301:301)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1587:1587:1587) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1547:1547:1547)) + (PORT asdata (568:568:568) (647:647:647)) + (PORT clrn (1587:1587:1587) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (342:342:342)) + (PORT datad (605:605:605) (631:631:631)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (2080:2080:2080) (2107:2107:2107)) - (PORT datab (1534:1534:1534) (1595:1595:1595)) - (PORT datac (3025:3025:3025) (3270:3270:3270)) - (PORT datad (2406:2406:2406) (2552:2552:2552)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1750:1750:1750) (1853:1853:1853)) + (PORT datab (1593:1593:1593) (1734:1734:1734)) + (PORT datac (1199:1199:1199) (1264:1264:1264)) + (PORT datad (1222:1222:1222) (1307:1307:1307)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1531:1531:1531)) - (PORT asdata (1663:1663:1663) (1726:1726:1726)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ExtRamWE\~0) (DELAY (ABSOLUTE - (PORT dataa (2564:2564:2564) (2687:2687:2687)) - (PORT datab (3045:3045:3045) (3292:3292:3292)) - (PORT datac (1748:1748:1748) (1787:1787:1787)) - (PORT datad (1758:1758:1758) (1816:1816:1816)) + (PORT dataa (1747:1747:1747) (1852:1852:1852)) + (PORT datab (1597:1597:1597) (1730:1730:1730)) + (PORT datac (1200:1200:1200) (1265:1265:1265)) + (PORT datad (1220:1220:1220) (1307:1307:1307)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1796:1796:1796) (1810:1810:1810)) + (PORT datab (849:849:849) (873:873:873)) + (PORT datad (335:335:335) (353:353:353)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (1028:1028:1028)) + (PORT datab (994:994:994) (1080:1080:1080)) + (PORT datac (1875:1875:1875) (2047:2047:2047)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1686:1686:1686) (1827:1827:1827)) + (PORT datab (974:974:974) (1024:1024:1024)) + (PORT datac (941:941:941) (1003:1003:1003)) + (PORT datad (1201:1201:1201) (1259:1259:1259)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1027:1027:1027)) + (PORT datab (994:994:994) (1080:1080:1080)) + (PORT datac (1875:1875:1875) (2047:2047:2047)) + (PORT datad (622:622:622) (660:660:660)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (603:603:603) (689:689:689)) + (PORT sload (1125:1125:1125) (1169:1169:1169)) + (PORT ena (1155:1155:1155) (1129:1129:1129)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1254:1254:1254)) + (PORT datad (2019:2019:2019) (2140:2140:2140)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1794:1794:1794) (1807:1807:1807)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datad (320:320:320) (334:334:334)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (590:590:590) (668:668:668)) + (PORT sload (1125:1125:1125) (1169:1169:1169)) + (PORT ena (1155:1155:1155) (1129:1129:1129)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (2045:2045:2045) (2178:2178:2178)) + (PORT datad (1147:1147:1147) (1202:1202:1202)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1796:1796:1796) (1810:1810:1810)) + (PORT datab (337:337:337) (371:371:371)) + (PORT datad (554:554:554) (561:561:561)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (577:577:577) (658:658:658)) + (PORT sload (1125:1125:1125) (1169:1169:1169)) + (PORT ena (1155:1155:1155) (1129:1129:1129)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (1641:1641:1641) (1729:1729:1729)) + (PORT datac (1584:1584:1584) (1634:1634:1634)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (330:330:330)) - (PORT datab (239:239:239) (293:293:293)) - (PORT datac (231:231:231) (277:277:277)) - (PORT datad (1159:1159:1159) (1236:1236:1236)) + (PORT dataa (697:697:697) (725:725:725)) + (PORT datab (261:261:261) (314:314:314)) + (PORT datac (366:366:366) (404:404:404)) + (PORT datad (1304:1304:1304) (1296:1296:1296)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -31973,11 +29829,23 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (3043:3043:3043) (3294:3294:3294)) - (PORT datac (1489:1489:1489) (1596:1596:1596)) - (PORT datad (1459:1459:1459) (1527:1527:1527)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (2037:2037:2037) (2174:2174:2174)) + (PORT datac (1153:1153:1153) (1208:1208:1208)) + (PORT datad (1144:1144:1144) (1203:1203:1203)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (971:971:971)) + (PORT datad (1987:1987:1987) (2083:2083:2083)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31987,9 +29855,9 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1767:1767:1767) (1835:1835:1835)) - (PORT datab (930:930:930) (981:981:981)) - (PORT datad (179:179:179) (207:207:207)) + (PORT dataa (854:854:854) (879:879:879)) + (PORT datab (373:373:373) (396:396:396)) + (PORT datad (334:334:334) (343:343:343)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -32001,11 +29869,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1539:1539:1539)) + (PORT clk (1548:1548:1548) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1241:1241:1241) (1302:1302:1302)) - (PORT sload (1762:1762:1762) (1828:1828:1828)) - (PORT ena (1696:1696:1696) (1694:1694:1694)) + (PORT asdata (1128:1128:1128) (1174:1174:1174)) + (PORT sload (1213:1213:1213) (1283:1283:1283)) + (PORT ena (1456:1456:1456) (1440:1440:1440)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32021,9 +29889,9 @@ (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) (DELAY (ABSOLUTE - (PORT datac (1069:1069:1069) (1165:1165:1165)) - (PORT datad (3272:3272:3272) (3493:3493:3493)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1793:1793:1793) (1909:1909:1909)) + (PORT datad (678:678:678) (733:733:733)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32033,11 +29901,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (602:602:602) (623:623:623)) - (PORT datab (1557:1557:1557) (1672:1672:1672)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (855:855:855) (880:880:880)) + (PORT datab (604:604:604) (620:620:620)) + (PORT datad (532:532:532) (544:544:544)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32047,11 +29915,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1532:1532:1532)) + (PORT clk (1548:1548:1548) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1231:1231:1231) (1285:1285:1285)) - (PORT sload (1915:1915:1915) (1964:1964:1964)) - (PORT ena (1897:1897:1897) (1898:1898:1898)) + (PORT asdata (992:992:992) (1045:1045:1045)) + (PORT sload (1213:1213:1213) (1283:1283:1283)) + (PORT ena (1456:1456:1456) (1440:1440:1440)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32067,8 +29935,8 @@ (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) (DELAY (ABSOLUTE - (PORT datac (2987:2987:2987) (3186:3186:3186)) - (PORT datad (1114:1114:1114) (1182:1182:1182)) + (PORT datac (1749:1749:1749) (1862:1862:1862)) + (PORT datad (642:642:642) (699:699:699)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32079,11 +29947,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1551:1551:1551) (1669:1669:1669)) - (PORT datad (808:808:808) (825:825:825)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (858:858:858) (887:887:887)) + (PORT datab (535:535:535) (551:551:551)) + (PORT datad (339:339:339) (355:355:355)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32093,11 +29961,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1532:1532:1532)) + (PORT clk (1548:1548:1548) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (708:708:708) (779:779:779)) - (PORT sload (1915:1915:1915) (1964:1964:1964)) - (PORT ena (1897:1897:1897) (1898:1898:1898)) + (PORT asdata (751:751:751) (807:807:807)) + (PORT sload (1213:1213:1213) (1283:1283:1283)) + (PORT ena (1456:1456:1456) (1440:1440:1440)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32113,9 +29981,9 @@ (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) (DELAY (ABSOLUTE - (PORT datab (2449:2449:2449) (2610:2610:2610)) - (PORT datad (1427:1427:1427) (1510:1510:1510)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datac (1754:1754:1754) (1872:1872:1872)) + (PORT datad (367:367:367) (429:429:429)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32125,11 +29993,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) (DELAY (ABSOLUTE - (PORT dataa (635:635:635) (687:687:687)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datad (1726:1726:1726) (1788:1788:1788)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (853:853:853) (880:880:880)) + (PORT datab (534:534:534) (559:559:559)) + (PORT datad (339:339:339) (357:357:357)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32139,11 +30007,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1539:1539:1539)) + (PORT clk (1548:1548:1548) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1202:1202:1202) (1325:1325:1325)) - (PORT sload (1762:1762:1762) (1828:1828:1828)) - (PORT ena (1696:1696:1696) (1694:1694:1694)) + (PORT asdata (979:979:979) (1031:1031:1031)) + (PORT sload (1213:1213:1213) (1283:1283:1283)) + (PORT ena (1456:1456:1456) (1440:1440:1440)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32159,9 +30027,9 @@ (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) (DELAY (ABSOLUTE - (PORT datac (1523:1523:1523) (1623:1623:1623)) - (PORT datad (2402:2402:2402) (2558:2558:2558)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (1758:1758:1758) (1874:1874:1874)) + (PORT datad (652:652:652) (710:710:710)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32171,11 +30039,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) (DELAY (ABSOLUTE - (PORT dataa (899:899:899) (942:942:942)) - (PORT datab (607:607:607) (637:637:637)) - (PORT datad (1442:1442:1442) (1506:1506:1506)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (1351:1351:1351) (1385:1385:1385)) + (PORT datab (337:337:337) (371:371:371)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32185,11 +30053,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1540:1540:1540)) + (PORT clk (1528:1528:1528) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1016:1016:1016) (1105:1105:1105)) - (PORT sload (1597:1597:1597) (1652:1652:1652)) - (PORT ena (1976:1976:1976) (1959:1959:1959)) + (PORT asdata (1019:1019:1019) (1078:1078:1078)) + (PORT sload (1150:1150:1150) (1218:1218:1218)) + (PORT ena (1176:1176:1176) (1166:1166:1166)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32205,10 +30073,10 @@ (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (351:351:351)) - (PORT datad (3273:3273:3273) (3495:3495:3495)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (2021:2021:2021) (2124:2124:2124)) + (PORT datac (676:676:676) (743:743:743)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -32217,11 +30085,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) (DELAY (ABSOLUTE - (PORT dataa (1767:1767:1767) (1834:1834:1834)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datad (595:595:595) (615:615:615)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datad (1323:1323:1323) (1343:1343:1343)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32231,11 +30099,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1539:1539:1539)) + (PORT clk (1528:1528:1528) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (953:953:953) (1016:1016:1016)) - (PORT sload (1762:1762:1762) (1828:1828:1828)) - (PORT ena (1696:1696:1696) (1694:1694:1694)) + (PORT asdata (1156:1156:1156) (1209:1209:1209)) + (PORT sload (1150:1150:1150) (1218:1218:1218)) + (PORT ena (1176:1176:1176) (1166:1166:1166)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32251,10 +30119,10 @@ (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) (DELAY (ABSOLUTE - (PORT datac (1274:1274:1274) (1343:1343:1343)) - (PORT datad (3270:3270:3270) (3522:3522:3522)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (696:696:696) (759:759:759)) + (PORT datac (1750:1750:1750) (1863:1863:1863)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -32263,11 +30131,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) (DELAY (ABSOLUTE - (PORT dataa (626:626:626) (680:680:680)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datad (1444:1444:1444) (1505:1505:1505)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (1354:1354:1354) (1387:1387:1387)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32277,11 +30145,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1540:1540:1540)) + (PORT clk (1528:1528:1528) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1250:1250:1250) (1311:1311:1311)) - (PORT sload (1597:1597:1597) (1652:1652:1652)) - (PORT ena (1976:1976:1976) (1959:1959:1959)) + (PORT asdata (1639:1639:1639) (1657:1657:1657)) + (PORT sload (1150:1150:1150) (1218:1218:1218)) + (PORT ena (1176:1176:1176) (1166:1166:1166)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32297,20 +30165,250 @@ (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) (DELAY (ABSOLUTE - (PORT datab (3322:3322:3322) (3557:3557:3557)) - (PORT datad (1225:1225:1225) (1301:1301:1301)) + (PORT datac (1748:1748:1748) (1867:1867:1867)) + (PORT datad (927:927:927) (1010:1010:1010)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (380:380:380)) + (PORT datab (1361:1361:1361) (1369:1369:1369)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) (DELAY (ABSOLUTE - (PORT d[0] (2302:2302:2302) (2397:2397:2397)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (597:597:597) (678:678:678)) + (PORT sload (1150:1150:1150) (1218:1218:1218)) + (PORT ena (1176:1176:1176) (1166:1166:1166)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (948:948:948) (1009:1009:1009)) + (PORT datad (2008:2008:2008) (2130:2130:2130)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1422:1422:1422)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datad (552:552:552) (561:561:561)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (591:591:591) (677:677:677)) + (PORT sload (1117:1117:1117) (1168:1168:1168)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) + (DELAY + (ABSOLUTE + (PORT datac (1757:1757:1757) (1868:1868:1868)) + (PORT datad (678:678:678) (737:737:737)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (567:567:567) (585:585:585)) + (PORT datad (1365:1365:1365) (1379:1379:1379)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (580:580:580) (668:668:668)) + (PORT sload (1117:1117:1117) (1168:1168:1168)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) + (DELAY + (ABSOLUTE + (PORT datac (910:910:910) (972:972:972)) + (PORT datad (1442:1442:1442) (1565:1565:1565)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datad (1362:1362:1362) (1374:1374:1374)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (913:913:913) (972:972:972)) + (PORT sload (1117:1117:1117) (1168:1168:1168)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (1010:1010:1010)) + (PORT datad (1442:1442:1442) (1566:1566:1566)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (375:375:375)) + (PORT datab (816:816:816) (834:834:834)) + (PORT datad (1561:1561:1561) (1571:1571:1571)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (583:583:583) (667:667:667)) + (PORT sload (1125:1125:1125) (1169:1169:1169)) + (PORT ena (1155:1155:1155) (1129:1129:1129)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1791:1791:1791) (1903:1903:1903)) + (PORT datad (854:854:854) (913:913:913)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1010:1010:1010) (1062:1062:1062)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -32319,23 +30417,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2750:2750:2750) (2950:2950:2950)) - (PORT d[1] (1649:1649:1649) (1795:1795:1795)) - (PORT d[2] (2825:2825:2825) (3063:3063:3063)) - (PORT d[3] (2361:2361:2361) (2579:2579:2579)) - (PORT d[4] (2246:2246:2246) (2414:2414:2414)) - (PORT d[5] (2774:2774:2774) (2984:2984:2984)) - (PORT d[6] (1739:1739:1739) (1845:1845:1845)) - (PORT d[7] (4071:4071:4071) (4237:4237:4237)) - (PORT d[8] (2438:2438:2438) (2584:2584:2584)) - (PORT d[9] (2822:2822:2822) (2973:2973:2973)) - (PORT d[10] (1896:1896:1896) (2024:2024:2024)) - (PORT d[11] (1897:1897:1897) (2054:2054:2054)) - (PORT d[12] (3374:3374:3374) (3534:3534:3534)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (1009:1009:1009) (1047:1047:1047)) + (PORT d[1] (2076:2076:2076) (2305:2305:2305)) + (PORT d[2] (1463:1463:1463) (1514:1514:1514)) + (PORT d[3] (2867:2867:2867) (3072:3072:3072)) + (PORT d[4] (2625:2625:2625) (2841:2841:2841)) + (PORT d[5] (3152:3152:3152) (3353:3353:3353)) + (PORT d[6] (1368:1368:1368) (1453:1453:1453)) + (PORT d[7] (2906:2906:2906) (3079:3079:3079)) + (PORT d[8] (997:997:997) (1014:1014:1014)) + (PORT d[9] (1597:1597:1597) (1654:1654:1654)) + (PORT d[10] (1607:1607:1607) (1695:1695:1695)) + (PORT d[11] (2235:2235:2235) (2380:2380:2380)) + (PORT d[12] (1610:1610:1610) (1712:1712:1712)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -32344,11 +30442,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2743:2743:2743) (2798:2798:2798)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (958:958:958) (934:934:934)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -32357,60 +30455,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (2884:2884:2884) (2919:2919:2919)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (1472:1472:1472) (1458:1458:1458)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1815:1815:1815) (1842:1842:1842)) + (PORT clk (1816:1816:1816) (1842:1842:1842)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -32421,49 +30519,49 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) + (PORT clk (1001:1001:1001) (1005:1005:1005)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) + (PORT clk (1002:1002:1002) (1006:1006:1006)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) + (PORT clk (1002:1002:1002) (1006:1006:1006)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) + (PORT clk (1002:1002:1002) (1006:1006:1006)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT asdata (1175:1175:1175) (1208:1208:1208)) + (PORT clk (1896:1896:1896) (1918:1918:1918)) + (PORT asdata (2035:2035:2035) (2085:2085:2085)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32473,11 +30571,11 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT asdata (559:559:559) (633:633:633)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT asdata (1451:1451:1451) (1488:1488:1488)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32490,12 +30588,12 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (260:260:260) (326:326:326)) - (PORT datab (243:243:243) (296:296:296)) - (PORT datac (234:234:234) (282:282:282)) - (PORT datad (1156:1156:1156) (1233:1233:1233)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT dataa (697:697:697) (725:725:725)) + (PORT datab (262:262:262) (316:316:316)) + (PORT datac (367:367:367) (405:405:405)) + (PORT datad (1303:1303:1303) (1300:1300:1300)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32506,9 +30604,9 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (3047:3047:3047) (3294:3294:3294)) - (PORT datac (1489:1489:1489) (1599:1599:1599)) - (PORT datad (1458:1458:1458) (1529:1529:1529)) + (PORT datab (2042:2042:2042) (2178:2178:2178)) + (PORT datac (1154:1154:1154) (1211:1211:1211)) + (PORT datad (1145:1145:1145) (1206:1206:1206)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -32517,11 +30615,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1446:1446:1446) (1486:1486:1486)) - (PORT clk (1841:1841:1841) (1870:1870:1870)) + (PORT d[0] (991:991:991) (1045:1045:1045)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) ) ) (TIMINGCHECK @@ -32530,23 +30628,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2224:2224:2224) (2370:2370:2370)) - (PORT d[1] (2380:2380:2380) (2609:2609:2609)) - (PORT d[2] (2064:2064:2064) (2259:2259:2259)) - (PORT d[3] (3907:3907:3907) (4275:4275:4275)) - (PORT d[4] (1889:1889:1889) (2024:2024:2024)) - (PORT d[5] (4270:4270:4270) (4584:4584:4584)) - (PORT d[6] (2296:2296:2296) (2416:2416:2416)) - (PORT d[7] (2481:2481:2481) (2555:2555:2555)) - (PORT d[8] (3366:3366:3366) (3561:3561:3561)) - (PORT d[9] (2497:2497:2497) (2609:2609:2609)) - (PORT d[10] (1595:1595:1595) (1698:1698:1698)) - (PORT d[11] (2735:2735:2735) (2878:2878:2878)) - (PORT d[12] (1892:1892:1892) (1930:1930:1930)) - (PORT clk (1838:1838:1838) (1866:1866:1866)) + (PORT d[0] (1010:1010:1010) (1048:1048:1048)) + (PORT d[1] (2092:2092:2092) (2316:2316:2316)) + (PORT d[2] (3345:3345:3345) (3458:3458:3458)) + (PORT d[3] (2859:2859:2859) (3062:3062:3062)) + (PORT d[4] (2566:2566:2566) (2775:2775:2775)) + (PORT d[5] (3169:3169:3169) (3393:3393:3393)) + (PORT d[6] (1618:1618:1618) (1695:1695:1695)) + (PORT d[7] (2898:2898:2898) (3057:3057:3057)) + (PORT d[8] (1024:1024:1024) (1046:1046:1046)) + (PORT d[9] (3241:3241:3241) (3372:3372:3372)) + (PORT d[10] (1642:1642:1642) (1735:1735:1735)) + (PORT d[11] (1916:1916:1916) (2070:2070:2070)) + (PORT d[12] (1870:1870:1870) (1971:1971:1971)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) ) ) (TIMINGCHECK @@ -32555,11 +30653,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2111:2111:2111) (2135:2135:2135)) - (PORT clk (1838:1838:1838) (1866:1866:1866)) + (PORT d[0] (950:950:950) (925:925:925)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) ) ) (TIMINGCHECK @@ -32568,60 +30666,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1841:1841:1841) (1870:1870:1870)) - (PORT d[0] (2839:2839:2839) (2882:2882:2882)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (1713:1713:1713) (1683:1683:1683)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1842:1842:1842) (1871:1871:1871)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1842:1842:1842) (1871:1871:1871)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1842:1842:1842) (1871:1871:1871)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1842:1842:1842) (1871:1871:1871)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1801:1801:1801) (1829:1829:1829)) + (PORT clk (1814:1814:1814) (1840:1840:1840)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -32632,69 +30730,81 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (986:986:986) (992:992:992)) + (PORT clk (999:999:999) (1003:1003:1003)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (987:987:987) (993:993:993)) + (PORT clk (1000:1000:1000) (1004:1004:1004)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (987:987:987) (993:993:993)) + (PORT clk (1000:1000:1000) (1004:1004:1004)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (987:987:987) (993:993:993)) + (PORT clk (1000:1000:1000) (1004:1004:1004)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) (DELAY (ABSOLUTE - (PORT dataa (334:334:334) (454:454:454)) - (PORT datab (1274:1274:1274) (1334:1334:1334)) - (PORT datac (1165:1165:1165) (1244:1244:1244)) - (PORT datad (886:886:886) (912:912:912)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT asdata (1470:1470:1470) (1518:1518:1518)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT asdata (706:706:706) (770:770:770)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (260:260:260) (324:324:324)) - (PORT datab (243:243:243) (297:297:297)) - (PORT datac (234:234:234) (281:281:281)) - (PORT datad (1156:1156:1156) (1231:1231:1231)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (700:700:700) (726:726:726)) + (PORT datab (266:266:266) (319:319:319)) + (PORT datac (371:371:371) (404:404:404)) + (PORT datad (1304:1304:1304) (1295:1295:1295)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32705,22 +30815,22 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (3051:3051:3051) (3300:3300:3300)) - (PORT datac (1491:1491:1491) (1601:1601:1601)) - (PORT datad (1456:1456:1456) (1526:1526:1526)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (2038:2038:2038) (2171:2171:2171)) + (PORT datac (1153:1153:1153) (1206:1206:1206)) + (PORT datad (1143:1143:1143) (1202:1202:1202)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1690:1690:1690) (1725:1725:1725)) - (PORT clk (1846:1846:1846) (1875:1875:1875)) + (PORT d[0] (1184:1184:1184) (1228:1228:1228)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) ) ) (TIMINGCHECK @@ -32729,23 +30839,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1955:1955:1955) (2104:2104:2104)) - (PORT d[1] (2427:2427:2427) (2639:2639:2639)) - (PORT d[2] (2051:2051:2051) (2252:2252:2252)) - (PORT d[3] (3897:3897:3897) (4247:4247:4247)) - (PORT d[4] (1917:1917:1917) (2062:2062:2062)) - (PORT d[5] (4591:4591:4591) (4927:4927:4927)) - (PORT d[6] (2003:2003:2003) (2104:2104:2104)) - (PORT d[7] (2209:2209:2209) (2271:2271:2271)) - (PORT d[8] (3388:3388:3388) (3585:3585:3585)) - (PORT d[9] (2531:2531:2531) (2653:2653:2653)) - (PORT d[10] (2302:2302:2302) (2480:2480:2480)) - (PORT d[11] (2455:2455:2455) (2599:2599:2599)) - (PORT d[12] (1597:1597:1597) (1628:1628:1628)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (3973:3973:3973) (4187:4187:4187)) + (PORT d[1] (1695:1695:1695) (1858:1858:1858)) + (PORT d[2] (3329:3329:3329) (3462:3462:3462)) + (PORT d[3] (2153:2153:2153) (2276:2276:2276)) + (PORT d[4] (2142:2142:2142) (2252:2252:2252)) + (PORT d[5] (1659:1659:1659) (1777:1777:1777)) + (PORT d[6] (1754:1754:1754) (1804:1804:1804)) + (PORT d[7] (3063:3063:3063) (3210:3210:3210)) + (PORT d[8] (3317:3317:3317) (3546:3546:3546)) + (PORT d[9] (1753:1753:1753) (1814:1814:1814)) + (PORT d[10] (3216:3216:3216) (3426:3426:3426)) + (PORT d[11] (2090:2090:2090) (2212:2212:2212)) + (PORT d[12] (1771:1771:1771) (1834:1834:1834)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) ) ) (TIMINGCHECK @@ -32754,11 +30864,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2315:2315:2315) (2304:2304:2304)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (2235:2235:2235) (2268:2268:2268)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) ) ) (TIMINGCHECK @@ -32767,60 +30877,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (PORT d[0] (2609:2609:2609) (2654:2654:2654)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (2962:2962:2962) (3024:3024:3024)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) + (PORT clk (1846:1846:1846) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) + (PORT clk (1846:1846:1846) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) + (PORT clk (1846:1846:1846) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) + (PORT clk (1846:1846:1846) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1806:1806:1806) (1834:1834:1834)) + (PORT clk (1805:1805:1805) (1832:1832:1832)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -32831,51 +30941,67 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) + (PORT clk (990:990:990) (995:995:995)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) + (PORT clk (991:991:991) (996:996:996)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) + (PORT clk (991:991:991) (996:996:996)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) + (PORT clk (991:991:991) (996:996:996)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (616:616:616)) + (PORT datab (976:976:976) (1039:1039:1039)) + (PORT datac (828:828:828) (832:832:832)) + (PORT datad (1142:1142:1142) (1222:1222:1222)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (330:330:330)) - (PORT datab (237:237:237) (290:290:290)) - (PORT datac (230:230:230) (276:276:276)) - (PORT datad (1159:1159:1159) (1231:1231:1231)) + (PORT dataa (700:700:700) (731:731:731)) + (PORT datab (265:265:265) (319:319:319)) + (PORT datac (371:371:371) (408:408:408)) + (PORT datad (1303:1303:1303) (1299:1299:1299)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -32888,9 +31014,9 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (3049:3049:3049) (3294:3294:3294)) - (PORT datac (1491:1491:1491) (1597:1597:1597)) - (PORT datad (1456:1456:1456) (1526:1526:1526)) + (PORT datab (2046:2046:2046) (2179:2179:2179)) + (PORT datac (1157:1157:1157) (1209:1209:1209)) + (PORT datad (1148:1148:1148) (1203:1203:1203)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -32899,11 +31025,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1723:1723:1723) (1781:1781:1781)) - (PORT clk (1850:1850:1850) (1879:1879:1879)) + (PORT d[0] (1196:1196:1196) (1209:1209:1209)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) ) ) (TIMINGCHECK @@ -32912,23 +31038,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1942:1942:1942) (2071:2071:2071)) - (PORT d[1] (2685:2685:2685) (2897:2897:2897)) - (PORT d[2] (2105:2105:2105) (2287:2287:2287)) - (PORT d[3] (1498:1498:1498) (1596:1596:1596)) - (PORT d[4] (2201:2201:2201) (2359:2359:2359)) - (PORT d[5] (4593:4593:4593) (4932:4932:4932)) - (PORT d[6] (2285:2285:2285) (2384:2384:2384)) - (PORT d[7] (2181:2181:2181) (2235:2235:2235)) - (PORT d[8] (3077:3077:3077) (3253:3253:3253)) - (PORT d[9] (2859:2859:2859) (2985:2985:2985)) - (PORT d[10] (2256:2256:2256) (2432:2432:2432)) - (PORT d[11] (2437:2437:2437) (2584:2584:2584)) - (PORT d[12] (1584:1584:1584) (1596:1596:1596)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (4200:4200:4200) (4456:4456:4456)) + (PORT d[1] (2340:2340:2340) (2537:2537:2537)) + (PORT d[2] (3231:3231:3231) (3326:3326:3326)) + (PORT d[3] (2575:2575:2575) (2761:2761:2761)) + (PORT d[4] (2559:2559:2559) (2766:2766:2766)) + (PORT d[5] (2828:2828:2828) (3008:3008:3008)) + (PORT d[6] (1911:1911:1911) (2053:2053:2053)) + (PORT d[7] (2601:2601:2601) (2739:2739:2739)) + (PORT d[8] (3332:3332:3332) (3618:3618:3618)) + (PORT d[9] (2924:2924:2924) (3075:3075:3075)) + (PORT d[10] (5088:5088:5088) (5359:5359:5359)) + (PORT d[11] (1899:1899:1899) (2034:2034:2034)) + (PORT d[12] (2169:2169:2169) (2292:2292:2292)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) ) ) (TIMINGCHECK @@ -32937,11 +31063,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1709:1709:1709) (1705:1705:1705)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (2009:2009:2009) (1965:1965:1965)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) ) ) (TIMINGCHECK @@ -32950,60 +31076,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1879:1879:1879)) - (PORT d[0] (3209:3209:3209) (3224:3224:3224)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (2224:2224:2224) (2198:2198:2198)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1810:1810:1810) (1838:1838:1838)) + (PORT clk (1814:1814:1814) (1840:1840:1840)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -33014,53 +31140,53 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (1001:1001:1001)) + (PORT clk (999:999:999) (1003:1003:1003)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1002:1002:1002)) + (PORT clk (1000:1000:1000) (1004:1004:1004)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1002:1002:1002)) + (PORT clk (1000:1000:1000) (1004:1004:1004)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1002:1002:1002)) + (PORT clk (1000:1000:1000) (1004:1004:1004)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (INSTANCE D\[6\]\~91) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1262:1262:1262) (1265:1265:1265)) - (PORT datac (1164:1164:1164) (1242:1242:1242)) - (PORT datad (1242:1242:1242) (1287:1287:1287)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (837:837:837) (859:859:859)) + (PORT datab (1432:1432:1432) (1519:1519:1519)) + (PORT datac (318:318:318) (339:339:339)) + (PORT datad (1100:1100:1100) (1101:1101:1101)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33068,15 +31194,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (329:329:329)) - (PORT datab (240:240:240) (293:293:293)) - (PORT datac (230:230:230) (277:277:277)) - (PORT datad (1159:1159:1159) (1236:1236:1236)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (698:698:698) (723:723:723)) + (PORT datab (257:257:257) (310:310:310)) + (PORT datac (364:364:364) (402:402:402)) + (PORT datad (1304:1304:1304) (1295:1295:1295)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33091,17 +31217,27 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1044:1044:1044) (1098:1098:1098)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|vram_address\~0) (DELAY (ABSOLUTE - (PORT dataa (1190:1190:1190) (1270:1270:1270)) - (PORT datab (1481:1481:1481) (1552:1552:1552)) - (PORT datac (1186:1186:1186) (1249:1249:1249)) - (PORT datad (880:880:880) (934:934:934)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1253:1253:1253) (1340:1340:1340)) + (PORT datab (987:987:987) (1065:1065:1065)) + (PORT datac (971:971:971) (1042:1042:1042)) + (PORT datad (277:277:277) (361:361:361)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33112,14 +31248,14 @@ (INSTANCE ula_\|video_\|vram_address\[0\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) - (PORT asdata (1257:1257:1257) (1330:1330:1330)) - (PORT ena (936:936:936) (924:924:924)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -33128,9 +31264,9 @@ (INSTANCE ula_\|video_\|vram_address\[1\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) - (PORT asdata (1262:1262:1262) (1308:1308:1308)) - (PORT ena (936:936:936) (924:924:924)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) + (PORT asdata (1205:1205:1205) (1280:1280:1280)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33144,8 +31280,8 @@ (INSTANCE ula_\|video_\|vram_address\[2\]\~4) (DELAY (ABSOLUTE - (PORT datad (952:952:952) (1009:1009:1009)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (896:896:896) (972:972:972)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -33154,9 +31290,9 @@ (INSTANCE ula_\|video_\|vram_address\[2\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (936:936:936) (924:924:924)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33170,8 +31306,8 @@ (INSTANCE ula_\|video_\|Add3\~0) (DELAY (ABSOLUTE - (PORT datac (986:986:986) (1049:1049:1049)) - (PORT datad (952:952:952) (1009:1009:1009)) + (PORT datac (891:891:891) (968:968:968)) + (PORT datad (1442:1442:1442) (1493:1493:1493)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33182,9 +31318,9 @@ (INSTANCE ula_\|video_\|vram_address\[3\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (936:936:936) (924:924:924)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33198,10 +31334,10 @@ (INSTANCE ula_\|video_\|Add3\~1) (DELAY (ABSOLUTE - (PORT dataa (962:962:962) (1044:1044:1044)) - (PORT datac (983:983:983) (1044:1044:1044)) - (PORT datad (949:949:949) (1005:1005:1005)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (929:929:929) (1008:1008:1008)) + (PORT datac (1383:1383:1383) (1458:1458:1458)) + (PORT datad (1442:1442:1442) (1493:1493:1493)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33212,9 +31348,9 @@ (INSTANCE ula_\|video_\|vram_address\[4\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (936:936:936) (924:924:924)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33228,8 +31364,8 @@ (INSTANCE ula_\|video_\|Add4\~0) (DELAY (ABSOLUTE - (PORT dataa (982:982:982) (1046:1046:1046)) - (PORT datab (686:686:686) (762:762:762)) + (PORT dataa (697:697:697) (779:779:779)) + (PORT datab (721:721:721) (803:803:803)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -33243,7 +31379,7 @@ (INSTANCE ula_\|video_\|Add4\~2) (DELAY (ABSOLUTE - (PORT datab (738:738:738) (799:799:799)) + (PORT datab (644:644:644) (722:722:722)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -33257,7 +31393,7 @@ (INSTANCE ula_\|video_\|Add4\~4) (DELAY (ABSOLUTE - (PORT datab (1164:1164:1164) (1228:1228:1228)) + (PORT datab (706:706:706) (772:772:772)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -33271,9 +31407,9 @@ (INSTANCE ula_\|video_\|Add4\~6) (DELAY (ABSOLUTE - (PORT dataa (946:946:946) (1004:1004:1004)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (682:682:682) (766:766:766)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -33285,9 +31421,9 @@ (INSTANCE ula_\|video_\|vram_address\[5\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (936:936:936) (924:924:924)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33301,9 +31437,9 @@ (INSTANCE ula_\|video_\|Add4\~8) (DELAY (ABSOLUTE - (PORT datab (732:732:732) (799:799:799)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (700:700:700) (788:788:788)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -33315,9 +31451,9 @@ (INSTANCE ula_\|video_\|vram_address\[6\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (936:936:936) (924:924:924)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33331,7 +31467,7 @@ (INSTANCE ula_\|video_\|Add4\~10) (DELAY (ABSOLUTE - (PORT dataa (912:912:912) (974:974:974)) + (PORT dataa (980:980:980) (1052:1052:1052)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -33345,9 +31481,9 @@ (INSTANCE ula_\|video_\|vram_address\[7\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (936:936:936) (924:924:924)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33361,9 +31497,9 @@ (INSTANCE ula_\|video_\|Add4\~12) (DELAY (ABSOLUTE - (PORT dataa (716:716:716) (785:785:785)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (694:694:694) (766:766:766)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -33375,11 +31511,11 @@ (INSTANCE ula_\|video_\|Selector6\~0) (DELAY (ABSOLUTE - (PORT datab (1267:1267:1267) (1344:1344:1344)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (610:610:610) (638:638:638)) + (PORT datac (561:561:561) (582:582:582)) + (PORT datad (957:957:957) (1029:1029:1029)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -33389,12 +31525,12 @@ (INSTANCE ula_\|video_\|vram_address\[9\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1182:1182:1182) (1263:1263:1263)) - (PORT datab (1481:1481:1481) (1553:1553:1553)) - (PORT datac (1190:1190:1190) (1255:1255:1255)) - (PORT datad (876:876:876) (926:926:926)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1254:1254:1254) (1344:1344:1344)) + (PORT datab (987:987:987) (1066:1066:1066)) + (PORT datac (976:976:976) (1049:1049:1049)) + (PORT datad (282:282:282) (366:366:366)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33405,9 +31541,9 @@ (INSTANCE ula_\|video_\|vram_address\[8\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (964:964:964) (963:963:963)) + (PORT ena (820:820:820) (826:826:826)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33421,7 +31557,7 @@ (INSTANCE ula_\|video_\|Add4\~14) (DELAY (ABSOLUTE - (PORT datad (894:894:894) (944:944:944)) + (PORT datad (708:708:708) (780:780:780)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -33432,11 +31568,11 @@ (INSTANCE ula_\|video_\|Selector5\~0) (DELAY (ABSOLUTE - (PORT datab (1267:1267:1267) (1344:1344:1344)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (655:655:655) (677:677:677)) + (PORT datac (792:792:792) (807:807:807)) + (PORT datad (957:957:957) (1033:1033:1033)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -33446,9 +31582,9 @@ (INSTANCE ula_\|video_\|vram_address\[9\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (964:964:964) (963:963:963)) + (PORT ena (820:820:820) (826:826:826)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33462,13 +31598,13 @@ (INSTANCE ula_\|video_\|vram_address\[10\]\~2) (DELAY (ABSOLUTE - (PORT dataa (990:990:990) (1077:1077:1077)) - (PORT datab (707:707:707) (784:784:784)) - (PORT datac (1217:1217:1217) (1309:1309:1309)) - (PORT datad (684:684:684) (763:763:763)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1251:1251:1251) (1338:1338:1338)) + (PORT datab (981:981:981) (1058:1058:1058)) + (PORT datac (980:980:980) (1051:1051:1051)) + (PORT datad (285:285:285) (369:369:369)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -33478,11 +31614,11 @@ (INSTANCE ula_\|video_\|vram_address\[10\]\~3) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (914:914:914)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datad (685:685:685) (767:767:767)) + (PORT dataa (612:612:612) (644:644:644)) + (PORT datab (1014:1014:1014) (1089:1089:1089)) + (PORT datad (173:173:173) (198:198:198)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33493,7 +31629,7 @@ (INSTANCE ula_\|video_\|vram_address\[10\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -33507,9 +31643,9 @@ (INSTANCE ula_\|video_\|Selector3\~0) (DELAY (ABSOLUTE - (PORT datac (1236:1236:1236) (1306:1306:1306)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (613:613:613) (639:639:639)) + (PORT datad (958:958:958) (1031:1031:1031)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -33519,9 +31655,9 @@ (INSTANCE ula_\|video_\|vram_address\[11\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (964:964:964) (963:963:963)) + (PORT ena (820:820:820) (826:826:826)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33535,10 +31671,10 @@ (INSTANCE ula_\|video_\|Selector2\~0) (DELAY (ABSOLUTE - (PORT datab (1265:1265:1265) (1339:1339:1339)) - (PORT datac (180:180:180) (217:217:217)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (618:618:618) (638:638:638)) + (PORT datad (957:957:957) (1029:1029:1029)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -33547,9 +31683,9 @@ (INSTANCE ula_\|video_\|vram_address\[12\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (964:964:964) (963:963:963)) + (PORT ena (820:820:820) (826:826:826)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33558,2335 +31694,13 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1437:1437:1437) (1490:1490:1490)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1070:1070:1070) (1169:1169:1169)) - (PORT d[1] (1681:1681:1681) (1780:1780:1780)) - (PORT d[2] (3943:3943:3943) (4306:4306:4306)) - (PORT d[3] (3370:3370:3370) (3607:3607:3607)) - (PORT d[4] (2195:2195:2195) (2366:2366:2366)) - (PORT d[5] (1291:1291:1291) (1347:1347:1347)) - (PORT d[6] (1159:1159:1159) (1198:1198:1198)) - (PORT d[7] (2411:2411:2411) (2549:2549:2549)) - (PORT d[8] (1300:1300:1300) (1344:1344:1344)) - (PORT d[9] (4657:4657:4657) (4813:4813:4813)) - (PORT d[10] (1346:1346:1346) (1405:1405:1405)) - (PORT d[11] (3870:3870:3870) (4133:4133:4133)) - (PORT d[12] (2405:2405:2405) (2521:2521:2521)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1236:1236:1236) (1201:1201:1201)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (2344:2344:2344) (2351:2351:2351)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1811:1811:1811)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2793:2793:2793) (2865:2865:2865)) - (PORT clk (1824:1824:1824) (1817:1817:1817)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1890:1890:1890) (1975:1975:1975)) - (PORT d[1] (1853:1853:1853) (1980:1980:1980)) - (PORT d[2] (1877:1877:1877) (1979:1979:1979)) - (PORT d[3] (1831:1831:1831) (1958:1958:1958)) - (PORT d[4] (1887:1887:1887) (2020:2020:2020)) - (PORT d[5] (1789:1789:1789) (1891:1891:1891)) - (PORT d[6] (1827:1827:1827) (1976:1976:1976)) - (PORT d[7] (1903:1903:1903) (2052:2052:2052)) - (PORT d[8] (1937:1937:1937) (2078:2078:2078)) - (PORT d[9] (2001:2001:2001) (2080:2080:2080)) - (PORT d[10] (1913:1913:1913) (2004:2004:2004)) - (PORT d[11] (1995:1995:1995) (2079:2079:2079)) - (PORT d[12] (1853:1853:1853) (1938:1938:1938)) - (PORT clk (1820:1820:1820) (1813:1813:1813)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1817:1817:1817)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (1183:1183:1183) (1232:1232:1232)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1539:1539:1539)) - (PORT asdata (1229:1229:1229) (1298:1298:1298)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2734:2734:2734) (2902:2902:2902)) - (PORT d[1] (1554:1554:1554) (1624:1624:1624)) - (PORT d[2] (2906:2906:2906) (3199:3199:3199)) - (PORT d[3] (2577:2577:2577) (2806:2806:2806)) - (PORT d[4] (2301:2301:2301) (2516:2516:2516)) - (PORT d[5] (2281:2281:2281) (2370:2370:2370)) - (PORT d[6] (2395:2395:2395) (2549:2549:2549)) - (PORT d[7] (5032:5032:5032) (5213:5213:5213)) - (PORT d[8] (3015:3015:3015) (3200:3200:3200)) - (PORT d[9] (3266:3266:3266) (3388:3388:3388)) - (PORT d[10] (2595:2595:2595) (2786:2786:2786)) - (PORT d[11] (2498:2498:2498) (2719:2719:2719)) - (PORT d[12] (3618:3618:3618) (3771:3771:3771)) - (PORT clk (1869:1869:1869) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1894:1894:1894)) - (PORT d[0] (1977:1977:1977) (2015:2015:2015)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1857:1857:1857)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1020:1020:1020)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (756:756:756) (807:807:807)) - (PORT d[1] (3091:3091:3091) (3354:3354:3354)) - (PORT d[2] (2216:2216:2216) (2321:2321:2321)) - (PORT d[3] (1007:1007:1007) (1081:1081:1081)) - (PORT d[4] (3106:3106:3106) (3333:3333:3333)) - (PORT d[5] (952:952:952) (1005:1005:1005)) - (PORT d[6] (2909:2909:2909) (3077:3077:3077)) - (PORT d[7] (2643:2643:2643) (2771:2771:2771)) - (PORT d[8] (4036:4036:4036) (4289:4289:4289)) - (PORT d[9] (2994:2994:2994) (3081:3081:3081)) - (PORT d[10] (2883:2883:2883) (3100:3100:3100)) - (PORT d[11] (2224:2224:2224) (2440:2440:2440)) - (PORT d[12] (2093:2093:2093) (2182:2182:2182)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1875:1875:1875)) - (PORT d[0] (2328:2328:2328) (2271:2271:2271)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (262:262:262) (329:329:329)) - (PORT datab (240:240:240) (294:294:294)) - (PORT datac (233:233:233) (280:280:280)) - (PORT datad (1159:1159:1159) (1234:1234:1234)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1825:1825:1825) (1888:1888:1888)) - (PORT clk (1869:1869:1869) (1895:1895:1895)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2488:2488:2488) (2649:2649:2649)) - (PORT d[1] (1342:1342:1342) (1422:1422:1422)) - (PORT d[2] (3064:3064:3064) (3386:3386:3386)) - (PORT d[3] (2682:2682:2682) (2923:2923:2923)) - (PORT d[4] (2589:2589:2589) (2802:2802:2802)) - (PORT d[5] (2084:2084:2084) (2214:2214:2214)) - (PORT d[6] (2079:2079:2079) (2216:2216:2216)) - (PORT d[7] (2688:2688:2688) (2860:2860:2860)) - (PORT d[8] (2089:2089:2089) (2206:2206:2206)) - (PORT d[9] (3755:3755:3755) (3873:3873:3873)) - (PORT d[10] (2252:2252:2252) (2440:2440:2440)) - (PORT d[11] (3088:3088:3088) (3296:3296:3296)) - (PORT d[12] (3369:3369:3369) (3511:3511:3511)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2040:2040:2040) (2036:2036:2036)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (PORT d[0] (3206:3206:3206) (3169:3169:3169)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1820:1820:1820)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3716:3716:3716) (3827:3827:3827)) - (PORT clk (1834:1834:1834) (1826:1826:1826)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1906:1906:1906) (1974:1974:1974)) - (PORT d[1] (1975:1975:1975) (2071:2071:2071)) - (PORT d[2] (1843:1843:1843) (1910:1910:1910)) - (PORT d[3] (1921:1921:1921) (2093:2093:2093)) - (PORT d[4] (1842:1842:1842) (1948:1948:1948)) - (PORT d[5] (2185:2185:2185) (2276:2276:2276)) - (PORT d[6] (2004:2004:2004) (2062:2062:2062)) - (PORT d[7] (1990:1990:1990) (2045:2045:2045)) - (PORT d[8] (2083:2083:2083) (2151:2151:2151)) - (PORT d[9] (1957:1957:1957) (2011:2011:2011)) - (PORT d[10] (2156:2156:2156) (2259:2259:2259)) - (PORT d[11] (2033:2033:2033) (2085:2085:2085)) - (PORT d[12] (1888:1888:1888) (1962:1962:1962)) - (PORT clk (1830:1830:1830) (1822:1822:1822)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1834:1834:1834) (1826:1826:1826)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1822:1822:1822)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1185:1185:1185) (1235:1235:1235)) - (PORT datab (293:293:293) (387:387:387)) - (PORT datac (906:906:906) (923:923:923)) - (PORT datad (1542:1542:1542) (1632:1632:1632)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1213:1213:1213) (1276:1276:1276)) - (PORT datab (296:296:296) (391:391:391)) - (PORT datac (1537:1537:1537) (1619:1619:1619)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (944:944:944) (999:999:999)) - (PORT datab (973:973:973) (1028:1028:1028)) - (PORT datac (1048:1048:1048) (1061:1061:1061)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1836:1836:1836) (1933:1933:1933)) - (PORT datab (2139:2139:2139) (2274:2274:2274)) - (PORT datac (3267:3267:3267) (3490:3490:3490)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (768:768:768)) - (PORT datab (342:342:342) (371:371:371)) - (PORT datac (690:690:690) (731:731:731)) - (PORT datad (871:871:871) (885:885:885)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (748:748:748)) - (PORT datab (1200:1200:1200) (1287:1287:1287)) - (PORT datac (381:381:381) (440:440:440)) - (PORT datad (602:602:602) (624:624:624)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (1340:1340:1340) (1421:1421:1421)) - (PORT datab (1264:1264:1264) (1348:1348:1348)) - (PORT datac (809:809:809) (828:828:828)) - (PORT datad (567:567:567) (581:581:581)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1231:1231:1231)) - (PORT datab (1076:1076:1076) (1145:1145:1145)) - (PORT datac (1175:1175:1175) (1291:1291:1291)) - (PORT datad (1050:1050:1050) (1070:1070:1070)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (820:820:820)) - (PORT datab (1074:1074:1074) (1145:1145:1145)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (1034:1034:1034) (1031:1031:1031)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1249:1249:1249) (1323:1323:1323)) - (PORT datac (1163:1163:1163) (1182:1182:1182)) - (PORT datad (1015:1015:1015) (1049:1049:1049)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1643:1643:1643) (1675:1675:1675)) - (PORT datab (1036:1036:1036) (1059:1059:1059)) - (PORT datac (719:719:719) (796:796:796)) - (PORT datad (682:682:682) (735:735:735)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1181:1181:1181) (1193:1193:1193)) - (PORT datab (762:762:762) (777:777:777)) - (PORT datac (178:178:178) (214:214:214)) - (PORT datad (1218:1218:1218) (1303:1303:1303)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (616:616:616)) - (PORT datac (766:766:766) (785:785:785)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (913:913:913) (996:996:996)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (614:614:614) (662:662:662)) - (PORT datad (645:645:645) (672:672:672)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (742:742:742)) - (PORT datab (1114:1114:1114) (1131:1131:1131)) - (PORT datac (603:603:603) (638:638:638)) - (PORT datad (1017:1017:1017) (1024:1024:1024)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (1444:1444:1444) (1523:1523:1523)) - (PORT datab (1519:1519:1519) (1501:1501:1501)) - (PORT datac (1269:1269:1269) (1301:1301:1301)) - (PORT datad (1376:1376:1376) (1419:1419:1419)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (375:375:375) (412:412:412)) - (PORT datab (1193:1193:1193) (1257:1257:1257)) - (PORT datac (930:930:930) (1008:1008:1008)) - (PORT datad (1537:1537:1537) (1606:1606:1606)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT datac (286:286:286) (385:385:385)) - (PORT datad (290:290:290) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (462:462:462)) - (PORT datab (1365:1365:1365) (1430:1430:1430)) - (PORT datac (1361:1361:1361) (1424:1424:1424)) - (PORT datad (2078:2078:2078) (2122:2122:2122)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1155:1155:1155)) - (PORT datab (944:944:944) (984:984:984)) - (PORT datac (2031:2031:2031) (2073:2073:2073)) - (PORT datad (1173:1173:1173) (1234:1234:1234)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1115:1115:1115)) - (PORT datab (874:874:874) (914:914:914)) - (PORT datac (1269:1269:1269) (1301:1301:1301)) - (PORT datad (350:350:350) (369:369:369)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1410:1410:1410) (1467:1467:1467)) - (PORT datab (1304:1304:1304) (1363:1363:1363)) - (PORT datac (287:287:287) (385:385:385)) - (PORT datad (294:294:294) (384:384:384)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1243:1243:1243) (1347:1347:1347)) - (PORT datac (708:708:708) (786:786:786)) - (PORT datad (819:819:819) (851:851:851)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (571:571:571)) - (PORT datab (939:939:939) (1002:1002:1002)) - (PORT datac (1520:1520:1520) (1563:1563:1563)) - (PORT datad (617:617:617) (630:630:630)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (674:674:674)) - (PORT datab (1172:1172:1172) (1177:1177:1177)) - (PORT datac (559:559:559) (583:583:583)) - (PORT datad (1734:1734:1734) (1803:1803:1803)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1494:1494:1494) (1554:1554:1554)) - (PORT datab (1433:1433:1433) (1472:1472:1472)) - (PORT datac (645:645:645) (691:691:691)) - (PORT datad (1363:1363:1363) (1384:1384:1384)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (1286:1286:1286) (1330:1330:1330)) - (PORT datac (1601:1601:1601) (1583:1583:1583)) - (PORT datad (184:184:184) (213:213:213)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (585:585:585)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (1286:1286:1286) (1300:1300:1300)) - (PORT datad (793:793:793) (804:804:804)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (715:715:715)) - (PORT datab (613:613:613) (671:671:671)) - (PORT datac (1315:1315:1315) (1341:1341:1341)) - (PORT datad (786:786:786) (821:821:821)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1460:1460:1460) (1461:1461:1461)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|mwr_wr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (247:247:247) (331:331:331)) - (PORT datac (1001:1001:1001) (1001:1001:1001)) - (PORT datad (200:200:200) (228:228:228)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (2438:2438:2438) (2603:2603:2603)) - (PORT datab (1532:1532:1532) (1590:1590:1590)) - (PORT datac (3031:3031:3031) (3277:3277:3277)) - (PORT datad (1641:1641:1641) (1714:1714:1714)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1916:1916:1916) (1978:1978:1978)) - (PORT clk (1852:1852:1852) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1873:1873:1873) (1997:1997:1997)) - (PORT d[1] (2418:2418:2418) (2642:2642:2642)) - (PORT d[2] (2358:2358:2358) (2525:2525:2525)) - (PORT d[3] (1766:1766:1766) (1856:1856:1856)) - (PORT d[4] (2228:2228:2228) (2395:2395:2395)) - (PORT d[5] (4867:4867:4867) (5202:5202:5202)) - (PORT d[6] (2286:2286:2286) (2405:2405:2405)) - (PORT d[7] (2145:2145:2145) (2181:2181:2181)) - (PORT d[8] (3063:3063:3063) (3256:3256:3256)) - (PORT d[9] (2860:2860:2860) (2986:2986:2986)) - (PORT d[10] (1957:1957:1957) (2129:2129:2129)) - (PORT d[11] (2115:2115:2115) (2253:2253:2253)) - (PORT d[12] (1326:1326:1326) (1336:1336:1336)) - (PORT clk (1849:1849:1849) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1997:1997:1997) (2001:2001:2001)) - (PORT clk (1849:1849:1849) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1881:1881:1881)) - (PORT d[0] (2598:2598:2598) (2648:2648:2648)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2221:2221:2221) (2290:2290:2290)) - (PORT clk (1848:1848:1848) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2230:2230:2230) (2387:2387:2387)) - (PORT d[1] (2677:2677:2677) (2888:2888:2888)) - (PORT d[2] (2332:2332:2332) (2508:2508:2508)) - (PORT d[3] (3861:3861:3861) (4222:4222:4222)) - (PORT d[4] (2213:2213:2213) (2361:2361:2361)) - (PORT d[5] (4592:4592:4592) (4931:4931:4931)) - (PORT d[6] (2250:2250:2250) (2346:2346:2346)) - (PORT d[7] (2186:2186:2186) (2246:2246:2246)) - (PORT d[8] (3077:3077:3077) (3254:3254:3254)) - (PORT d[9] (2820:2820:2820) (2958:2958:2958)) - (PORT d[10] (2287:2287:2287) (2483:2483:2483)) - (PORT d[11] (2419:2419:2419) (2579:2579:2579)) - (PORT d[12] (1592:1592:1592) (1618:1618:1618)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2142:2142:2142) (2155:2155:2155)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (PORT d[0] (2736:2736:2736) (2801:2801:2801)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1808:1808:1808) (1836:1836:1836)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (449:449:449)) - (PORT datab (1559:1559:1559) (1659:1659:1659)) - (PORT datac (1154:1154:1154) (1232:1232:1232)) - (PORT datad (1236:1236:1236) (1282:1282:1282)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1516:1516:1516) (1557:1557:1557)) - (PORT clk (1862:1862:1862) (1890:1890:1890)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1349:1349:1349) (1426:1426:1426)) - (PORT d[1] (3088:3088:3088) (3380:3380:3380)) - (PORT d[2] (1614:1614:1614) (1742:1742:1742)) - (PORT d[3] (716:716:716) (752:752:752)) - (PORT d[4] (690:690:690) (712:712:712)) - (PORT d[5] (1567:1567:1567) (1646:1646:1646)) - (PORT d[6] (2951:2951:2951) (3127:3127:3127)) - (PORT d[7] (2306:2306:2306) (2405:2405:2405)) - (PORT d[8] (3749:3749:3749) (3997:3997:3997)) - (PORT d[9] (683:683:683) (703:703:703)) - (PORT d[10] (2557:2557:2557) (2734:2734:2734)) - (PORT d[11] (2221:2221:2221) (2437:2437:2437)) - (PORT d[12] (2651:2651:2651) (2759:2759:2759)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2155:2155:2155) (2125:2125:2125)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1862:1862:1862) (1890:1890:1890)) - (PORT d[0] (2528:2528:2528) (2531:2531:2531)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1891:1891:1891)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1891:1891:1891)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1891:1891:1891)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1891:1891:1891)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1849:1849:1849)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1007:1007:1007) (1012:1012:1012)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1013:1013:1013)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1013:1013:1013)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1013:1013:1013)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2782:2782:2782) (2893:2893:2893)) - (PORT clk (1847:1847:1847) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3769:3769:3769) (4062:4062:4062)) - (PORT d[1] (2110:2110:2110) (2313:2313:2313)) - (PORT d[2] (4028:4028:4028) (4262:4262:4262)) - (PORT d[3] (3288:3288:3288) (3576:3576:3576)) - (PORT d[4] (2875:2875:2875) (3086:3086:3086)) - (PORT d[5] (3978:3978:3978) (4258:4258:4258)) - (PORT d[6] (1674:1674:1674) (1737:1737:1737)) - (PORT d[7] (3086:3086:3086) (3210:3210:3210)) - (PORT d[8] (2487:2487:2487) (2660:2660:2660)) - (PORT d[9] (2841:2841:2841) (2939:2939:2939)) - (PORT d[10] (2619:2619:2619) (2772:2772:2772)) - (PORT d[11] (1523:1523:1523) (1634:1634:1634)) - (PORT d[12] (2196:2196:2196) (2275:2275:2275)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1414:1414:1414) (1358:1358:1358)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (PORT d[0] (1912:1912:1912) (1887:1887:1887)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (450:450:450)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1920:1920:1920) (1912:1912:1912)) - (PORT datad (927:927:927) (948:948:948)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (763:763:763) (795:795:795)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (752:752:752) (807:807:807)) - (PORT d[1] (1980:1980:1980) (2100:2100:2100)) - (PORT d[2] (1265:1265:1265) (1350:1350:1350)) - (PORT d[3] (3691:3691:3691) (3938:3938:3938)) - (PORT d[4] (2852:2852:2852) (3055:3055:3055)) - (PORT d[5] (993:993:993) (1050:1050:1050)) - (PORT d[6] (3172:3172:3172) (3392:3392:3392)) - (PORT d[7] (2679:2679:2679) (2847:2847:2847)) - (PORT d[8] (992:992:992) (1031:1031:1031)) - (PORT d[9] (2694:2694:2694) (2778:2778:2778)) - (PORT d[10] (1024:1024:1024) (1049:1049:1049)) - (PORT d[11] (2536:2536:2536) (2760:2760:2760)) - (PORT d[12] (2088:2088:2088) (2176:2176:2176)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (925:925:925) (873:873:873)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1492:1492:1492) (1454:1454:1454)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1812:1812:1812)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2181:2181:2181) (2249:2249:2249)) - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1889:1889:1889) (2010:2010:2010)) - (PORT d[1] (1977:1977:1977) (2066:2066:2066)) - (PORT d[2] (1895:1895:1895) (2016:2016:2016)) - (PORT d[3] (1998:1998:1998) (2161:2161:2161)) - (PORT d[4] (1954:1954:1954) (2048:2048:2048)) - (PORT d[5] (1860:1860:1860) (1976:1976:1976)) - (PORT d[6] (1803:1803:1803) (1917:1917:1917)) - (PORT d[7] (1874:1874:1874) (2004:2004:2004)) - (PORT d[8] (1905:1905:1905) (2030:2030:2030)) - (PORT d[9] (1897:1897:1897) (1993:1993:1993)) - (PORT d[10] (1919:1919:1919) (2028:2028:2028)) - (PORT d[11] (2055:2055:2055) (2124:2124:2124)) - (PORT d[12] (1883:1883:1883) (1964:1964:1964)) - (PORT clk (1821:1821:1821) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3781:3781:3781) (4085:4085:4085)) - (PORT d[1] (2394:2394:2394) (2582:2582:2582)) - (PORT d[2] (4316:4316:4316) (4556:4556:4556)) - (PORT d[3] (3594:3594:3594) (3934:3934:3934)) - (PORT d[4] (3187:3187:3187) (3407:3407:3407)) - (PORT d[5] (3991:3991:3991) (4287:4287:4287)) - (PORT d[6] (2552:2552:2552) (2688:2688:2688)) - (PORT d[7] (2791:2791:2791) (2891:2891:2891)) - (PORT d[8] (3649:3649:3649) (3866:3866:3866)) - (PORT d[9] (2181:2181:2181) (2268:2268:2268)) - (PORT d[10] (1576:1576:1576) (1657:1657:1657)) - (PORT d[11] (1540:1540:1540) (1655:1655:1655)) - (PORT d[12] (2184:2184:2184) (2245:2245:2245)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1874:1874:1874)) - (PORT d[0] (1287:1287:1287) (1295:1295:1295)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (757:757:757) (793:793:793)) - (PORT d[1] (681:681:681) (707:707:707)) - (PORT d[2] (1594:1594:1594) (1676:1676:1676)) - (PORT d[3] (3990:3990:3990) (4271:4271:4271)) - (PORT d[4] (2822:2822:2822) (3033:3033:3033)) - (PORT d[5] (669:669:669) (704:704:704)) - (PORT d[6] (3210:3210:3210) (3376:3376:3376)) - (PORT d[7] (2624:2624:2624) (2763:2763:2763)) - (PORT d[8] (994:994:994) (1014:1014:1014)) - (PORT d[9] (2605:2605:2605) (2661:2661:2661)) - (PORT d[10] (975:975:975) (995:995:995)) - (PORT d[11] (1466:1466:1466) (1525:1525:1525)) - (PORT d[12] (1745:1745:1745) (1803:1803:1803)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1882:1882:1882)) - (PORT d[0] (2643:2643:2643) (2567:2567:2567)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (737:737:737) (777:777:777)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (1548:1548:1548) (1620:1620:1620)) + (PORT clk (1864:1864:1864) (1891:1891:1891)) ) ) (TIMINGCHECK @@ -35898,20 +31712,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1086:1086:1086) (1161:1161:1161)) - (PORT d[1] (1972:1972:1972) (2085:2085:2085)) - (PORT d[2] (1308:1308:1308) (1401:1401:1401)) - (PORT d[3] (3687:3687:3687) (3934:3934:3934)) - (PORT d[4] (2501:2501:2501) (2677:2677:2677)) - (PORT d[5] (975:975:975) (1031:1031:1031)) - (PORT d[6] (899:899:899) (921:921:921)) - (PORT d[7] (2702:2702:2702) (2874:2874:2874)) - (PORT d[8] (1184:1184:1184) (1215:1215:1215)) - (PORT d[9] (2673:2673:2673) (2757:2757:2757)) - (PORT d[10] (1305:1305:1305) (1343:1343:1343)) - (PORT d[11] (2552:2552:2552) (2802:2802:2802)) - (PORT d[12] (2066:2066:2066) (2151:2151:2151)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (2599:2599:2599) (2697:2697:2697)) + (PORT d[1] (2358:2358:2358) (2589:2589:2589)) + (PORT d[2] (2326:2326:2326) (2476:2476:2476)) + (PORT d[3] (1990:1990:1990) (2063:2063:2063)) + (PORT d[4] (2926:2926:2926) (3182:3182:3182)) + (PORT d[5] (2089:2089:2089) (2294:2294:2294)) + (PORT d[6] (1566:1566:1566) (1667:1667:1667)) + (PORT d[7] (1626:1626:1626) (1711:1711:1711)) + (PORT d[8] (2773:2773:2773) (3020:3020:3020)) + (PORT d[9] (2077:2077:2077) (2186:2186:2186)) + (PORT d[10] (2124:2124:2124) (2247:2247:2247)) + (PORT d[11] (3187:3187:3187) (3328:3328:3328)) + (PORT d[12] (2201:2201:2201) (2298:2298:2298)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) ) ) (TIMINGCHECK @@ -35923,8 +31737,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1185:1185:1185) (1137:1137:1137)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (2768:2768:2768) (2740:2740:2740)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) ) ) (TIMINGCHECK @@ -35936,8 +31750,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2364:2364:2364) (2335:2335:2335)) + (PORT clk (1864:1864:1864) (1891:1891:1891)) + (PORT d[0] (2876:2876:2876) (2827:2827:2827)) ) ) ) @@ -35946,7 +31760,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1865:1865:1865) (1892:1892:1892)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -35956,7 +31770,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1865:1865:1865) (1892:1892:1892)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -35966,7 +31780,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1865:1865:1865) (1892:1892:1892)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -35976,7 +31790,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1865:1865:1865) (1892:1892:1892)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -35984,8165 +31798,6 @@ (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2801:2801:2801) (2875:2875:2875)) - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1884:1884:1884) (1984:1984:1984)) - (PORT d[1] (1973:1973:1973) (2056:2056:2056)) - (PORT d[2] (1910:1910:1910) (2035:2035:2035)) - (PORT d[3] (1986:1986:1986) (2169:2169:2169)) - (PORT d[4] (1904:1904:1904) (1986:1986:1986)) - (PORT d[5] (1829:1829:1829) (1940:1940:1940)) - (PORT d[6] (1825:1825:1825) (1963:1963:1963)) - (PORT d[7] (1843:1843:1843) (1968:1968:1968)) - (PORT d[8] (1952:1952:1952) (2098:2098:2098)) - (PORT d[9] (2014:2014:2014) (2111:2111:2111)) - (PORT d[10] (1915:1915:1915) (1994:1994:1994)) - (PORT d[11] (2051:2051:2051) (2121:2121:2121)) - (PORT d[12] (1934:1934:1934) (2039:2039:2039)) - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1815:1815:1815)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1183:1183:1183) (1234:1234:1234)) - (PORT datab (632:632:632) (641:641:641)) - (PORT datad (956:956:956) (963:963:963)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (917:917:917)) - (PORT datab (752:752:752) (824:824:824)) - (PORT datac (1032:1032:1032) (1031:1031:1031)) - (PORT datad (600:600:600) (616:616:616)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (775:775:775) (776:776:776)) - (PORT datab (883:883:883) (931:931:931)) - (PORT datac (1490:1490:1490) (1569:1569:1569)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE ula_\|pll_\|altpll_component\|auto_generated\|wire_pll1_clk\[2\]\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1896:1896:1896) (1878:1878:1878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (1341:1341:1341) (1428:1428:1428)) - (PORT datab (1265:1265:1265) (1351:1351:1351)) - (PORT datac (816:816:816) (842:842:842)) - (PORT datad (819:819:819) (827:827:827)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT datac (942:942:942) (1017:1017:1017)) - (PORT datad (1108:1108:1108) (1175:1175:1175)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (947:947:947) (1017:1017:1017)) - (PORT datab (916:916:916) (981:981:981)) - (PORT datac (804:804:804) (809:809:809)) - (PORT datad (680:680:680) (747:747:747)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (986:986:986) (1071:1071:1071)) - (PORT datab (707:707:707) (788:788:788)) - (PORT datac (190:190:190) (233:233:233)) - (PORT datad (197:197:197) (232:232:232)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (626:626:626)) - (PORT datad (716:716:716) (794:794:794)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT datab (981:981:981) (1050:1050:1050)) - (PORT datac (1154:1154:1154) (1218:1218:1218)) - (PORT datad (688:688:688) (763:763:763)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (1241:1241:1241) (1308:1308:1308)) - (PORT datab (471:471:471) (547:547:547)) - (PORT datac (1125:1125:1125) (1181:1181:1181)) - (PORT datad (936:936:936) (997:997:997)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~135) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1194:1194:1194)) - (PORT datab (1326:1326:1326) (1345:1345:1345)) - (PORT datad (319:319:319) (329:329:329)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (400:400:400)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (963:963:963)) - (PORT datab (240:240:240) (321:321:321)) - (PORT datac (863:863:863) (902:902:902)) - (PORT datad (550:550:550) (589:589:589)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (569:569:569)) - (PORT datac (930:930:930) (1000:1000:1000)) - (PORT datad (578:578:578) (583:583:583)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (829:829:829)) - (PORT datab (950:950:950) (1028:1028:1028)) - (PORT datac (919:919:919) (975:975:975)) - (PORT datad (578:578:578) (594:594:594)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (1031:1031:1031)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (799:799:799)) - (PORT datab (899:899:899) (976:976:976)) - (PORT datac (955:955:955) (1013:1013:1013)) - (PORT datad (920:920:920) (989:989:989)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (948:948:948) (1028:1028:1028)) - (PORT datab (950:950:950) (1028:1028:1028)) - (PORT datad (408:408:408) (475:475:475)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1050:1050:1050)) - (PORT datab (1191:1191:1191) (1247:1247:1247)) - (PORT datac (919:919:919) (978:978:978)) - (PORT datad (923:923:923) (989:989:989)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (224:224:224) (264:264:264)) - (PORT datad (198:198:198) (224:224:224)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (867:867:867)) - (PORT datab (242:242:242) (323:323:323)) - (PORT datac (213:213:213) (289:289:289)) - (PORT datad (2259:2259:2259) (2298:2298:2298)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (935:935:935) (1007:1007:1007)) - (PORT datab (974:974:974) (1034:1034:1034)) - (PORT datac (953:953:953) (1014:1014:1014)) - (PORT datad (853:853:853) (928:928:928)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (722:722:722) (792:792:792)) - (PORT datac (938:938:938) (1013:1013:1013)) - (PORT datad (1106:1106:1106) (1179:1179:1179)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (283:283:283) (376:376:376)) - (PORT datab (967:967:967) (1035:1035:1035)) - (PORT datad (555:555:555) (559:559:559)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~136) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (932:932:932)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datac (937:937:937) (1005:1005:1005)) - (PORT datad (1121:1121:1121) (1176:1176:1176)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (672:672:672)) - (PORT datab (581:581:581) (600:600:600)) - (PORT datac (935:935:935) (1002:1002:1002)) - (PORT datad (1118:1118:1118) (1174:1174:1174)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (541:541:541)) - (PORT datab (568:568:568) (583:583:583)) - (PORT datac (1188:1188:1188) (1247:1247:1247)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~137) - (DELAY - (ABSOLUTE - (PORT dataa (452:452:452) (524:524:524)) - (PORT datab (694:694:694) (763:763:763)) - (PORT datac (912:912:912) (972:972:972)) - (PORT datad (922:922:922) (987:987:987)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (581:581:581)) - (PORT datab (649:649:649) (670:670:670)) - (PORT datad (649:649:649) (674:674:674)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT datab (675:675:675) (743:743:743)) - (PORT datac (660:660:660) (730:730:730)) - (PORT datad (1140:1140:1140) (1181:1181:1181)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (760:760:760)) - (PORT datab (908:908:908) (924:924:924)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (704:704:704)) - (PORT datab (1918:1918:1918) (1961:1961:1961)) - (PORT datac (881:881:881) (922:922:922)) - (PORT datad (689:689:689) (743:743:743)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~115) - (DELAY - (ABSOLUTE - (PORT dataa (1223:1223:1223) (1287:1287:1287)) - (PORT datab (417:417:417) (492:492:492)) - (PORT datac (934:934:934) (1000:1000:1000)) - (PORT datad (1117:1117:1117) (1171:1171:1171)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (681:681:681)) - (PORT datab (351:351:351) (380:380:380)) - (PORT datac (252:252:252) (337:337:337)) - (PORT datad (849:849:849) (909:909:909)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~139) - (DELAY - (ABSOLUTE - (PORT dataa (533:533:533) (560:560:560)) - (PORT datab (686:686:686) (713:713:713)) - (PORT datad (430:430:430) (499:499:499)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (1005:1005:1005)) - (PORT datab (968:968:968) (1035:1035:1035)) - (PORT datac (396:396:396) (475:475:475)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~140) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (753:753:753)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datad (353:353:353) (368:368:368)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) - (DELAY - (ABSOLUTE - (PORT datab (970:970:970) (1042:1042:1042)) - (PORT datac (615:615:615) (685:685:685)) - (PORT datad (662:662:662) (730:730:730)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT datab (641:641:641) (702:702:702)) - (PORT datad (618:618:618) (687:687:687)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (1221:1221:1221) (1287:1287:1287)) - (PORT datab (797:797:797) (812:812:812)) - (PORT datac (605:605:605) (633:633:633)) - (PORT datad (621:621:621) (636:636:636)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (541:541:541)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (251:251:251) (336:336:336)) - (PORT datad (649:649:649) (670:670:670)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (259:259:259)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (454:454:454)) - (PORT datab (378:378:378) (449:449:449)) - (PORT datac (662:662:662) (712:712:712)) - (PORT datad (1308:1308:1308) (1337:1337:1337)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (587:587:587)) - (PORT datab (858:858:858) (870:870:870)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (605:605:605) (619:619:619)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1686:1686:1686) (1771:1771:1771)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3156:3156:3156) (3412:3412:3412)) - (PORT d[1] (2086:2086:2086) (2249:2249:2249)) - (PORT d[2] (2277:2277:2277) (2501:2501:2501)) - (PORT d[3] (2655:2655:2655) (2916:2916:2916)) - (PORT d[4] (2545:2545:2545) (2725:2725:2725)) - (PORT d[5] (3385:3385:3385) (3620:3620:3620)) - (PORT d[6] (2288:2288:2288) (2432:2432:2432)) - (PORT d[7] (3448:3448:3448) (3587:3587:3587)) - (PORT d[8] (2180:2180:2180) (2314:2314:2314)) - (PORT d[9] (2514:2514:2514) (2606:2606:2606)) - (PORT d[10] (1973:1973:1973) (2125:2125:2125)) - (PORT d[11] (1866:1866:1866) (2039:2039:2039)) - (PORT d[12] (2805:2805:2805) (2933:2933:2933)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2536:2536:2536) (2572:2572:2572)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2837:2837:2837) (2858:2858:2858)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2236:2236:2236) (2328:2328:2328)) - (PORT clk (1854:1854:1854) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3478:3478:3478) (3752:3752:3752)) - (PORT d[1] (2338:2338:2338) (2513:2513:2513)) - (PORT d[2] (3442:3442:3442) (3652:3652:3652)) - (PORT d[3] (2974:2974:2974) (3240:3240:3240)) - (PORT d[4] (2559:2559:2559) (2759:2759:2759)) - (PORT d[5] (3332:3332:3332) (3585:3585:3585)) - (PORT d[6] (1653:1653:1653) (1690:1690:1690)) - (PORT d[7] (3392:3392:3392) (3519:3519:3519)) - (PORT d[8] (2214:2214:2214) (2366:2366:2366)) - (PORT d[9] (3087:3087:3087) (3244:3244:3244)) - (PORT d[10] (2304:2304:2304) (2459:2459:2459)) - (PORT d[11] (1888:1888:1888) (2051:2051:2051)) - (PORT d[12] (2510:2510:2510) (2618:2618:2618)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2213:2213:2213) (2169:2169:2169)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (PORT d[0] (2987:2987:2987) (3061:3061:3061)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2325:2325:2325) (2449:2449:2449)) - (PORT clk (1859:1859:1859) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2821:2821:2821) (3028:3028:3028)) - (PORT d[1] (1761:1761:1761) (1901:1901:1901)) - (PORT d[2] (2589:2589:2589) (2822:2822:2822)) - (PORT d[3] (2293:2293:2293) (2500:2500:2500)) - (PORT d[4] (2233:2233:2233) (2385:2385:2385)) - (PORT d[5] (2754:2754:2754) (2940:2940:2940)) - (PORT d[6] (1973:1973:1973) (2089:2089:2089)) - (PORT d[7] (4338:4338:4338) (4519:4519:4519)) - (PORT d[8] (2439:2439:2439) (2603:2603:2603)) - (PORT d[9] (2832:2832:2832) (2960:2960:2960)) - (PORT d[10] (1943:1943:1943) (2072:2072:2072)) - (PORT d[11] (1888:1888:1888) (2044:2044:2044)) - (PORT d[12] (3386:3386:3386) (3561:3561:3561)) - (PORT clk (1856:1856:1856) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2461:2461:2461) (2505:2505:2505)) - (PORT clk (1856:1856:1856) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (PORT d[0] (2862:2862:2862) (2898:2898:2898)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1844:1844:1844)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1008:1008:1008)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1008:1008:1008)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2330:2330:2330) (2428:2428:2428)) - (PORT clk (1847:1847:1847) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3777:3777:3777) (4077:4077:4077)) - (PORT d[1] (2106:2106:2106) (2282:2282:2282)) - (PORT d[2] (4029:4029:4029) (4263:4263:4263)) - (PORT d[3] (3289:3289:3289) (3577:3577:3577)) - (PORT d[4] (3196:3196:3196) (3402:3402:3402)) - (PORT d[5] (4006:4006:4006) (4271:4271:4271)) - (PORT d[6] (1677:1677:1677) (1742:1742:1742)) - (PORT d[7] (2770:2770:2770) (2870:2870:2870)) - (PORT d[8] (2790:2790:2790) (2959:2959:2959)) - (PORT d[9] (1958:1958:1958) (2028:2028:2028)) - (PORT d[10] (1586:1586:1586) (1686:1686:1686)) - (PORT d[11] (1543:1543:1543) (1654:1654:1654)) - (PORT d[12] (2219:2219:2219) (2278:2278:2278)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2684:2684:2684) (2750:2750:2750)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (PORT d[0] (2795:2795:2795) (2869:2869:2869)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (454:454:454)) - (PORT datab (1807:1807:1807) (1871:1871:1871)) - (PORT datac (1164:1164:1164) (1244:1244:1244)) - (PORT datad (897:897:897) (902:902:902)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1644:1644:1644) (1680:1680:1680)) - (PORT datab (958:958:958) (1020:1020:1020)) - (PORT datac (1652:1652:1652) (1666:1666:1666)) - (PORT datad (1036:1036:1036) (1042:1042:1042)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (701:701:701) (747:747:747)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1101:1101:1101) (1196:1196:1196)) - (PORT d[1] (1660:1660:1660) (1757:1757:1757)) - (PORT d[2] (1572:1572:1572) (1662:1662:1662)) - (PORT d[3] (3352:3352:3352) (3609:3609:3609)) - (PORT d[4] (1935:1935:1935) (2121:2121:2121)) - (PORT d[5] (1245:1245:1245) (1290:1290:1290)) - (PORT d[6] (2884:2884:2884) (3078:3078:3078)) - (PORT d[7] (2644:2644:2644) (2789:2789:2789)) - (PORT d[8] (1335:1335:1335) (1404:1404:1404)) - (PORT d[9] (2946:2946:2946) (3033:3033:3033)) - (PORT d[10] (1319:1319:1319) (1372:1372:1372)) - (PORT d[11] (4115:4115:4115) (4370:4370:4370)) - (PORT d[12] (2424:2424:2424) (2536:2536:2536)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1770:1770:1770) (1755:1755:1755)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2353:2353:2353) (2374:2374:2374)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1812:1812:1812)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2801:2801:2801) (2863:2863:2863)) - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1878:1878:1878) (1981:1981:1981)) - (PORT d[1] (1942:1942:1942) (2016:2016:2016)) - (PORT d[2] (1879:1879:1879) (1981:1981:1981)) - (PORT d[3] (1937:1937:1937) (2126:2126:2126)) - (PORT d[4] (1929:1929:1929) (1985:1985:1985)) - (PORT d[5] (1847:1847:1847) (1943:1943:1943)) - (PORT d[6] (1878:1878:1878) (2040:2040:2040)) - (PORT d[7] (1835:1835:1835) (1939:1939:1939)) - (PORT d[8] (1985:1985:1985) (2141:2141:2141)) - (PORT d[9] (2009:2009:2009) (2101:2101:2101)) - (PORT d[10] (1921:1921:1921) (2031:2031:2031)) - (PORT d[11] (2034:2034:2034) (2104:2104:2104)) - (PORT d[12] (1855:1855:1855) (1959:1959:1959)) - (PORT clk (1821:1821:1821) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1076:1076:1076) (1125:1125:1125)) - (PORT d[1] (970:970:970) (1015:1015:1015)) - (PORT d[2] (1606:1606:1606) (1706:1706:1706)) - (PORT d[3] (3970:3970:3970) (4280:4280:4280)) - (PORT d[4] (2834:2834:2834) (3013:3013:3013)) - (PORT d[5] (986:986:986) (1022:1022:1022)) - (PORT d[6] (3210:3210:3210) (3401:3401:3401)) - (PORT d[7] (1156:1156:1156) (1173:1173:1173)) - (PORT d[8] (684:684:684) (705:705:705)) - (PORT d[9] (2371:2371:2371) (2428:2428:2428)) - (PORT d[10] (984:984:984) (1022:1022:1022)) - (PORT d[11] (1160:1160:1160) (1180:1180:1180)) - (PORT d[12] (2330:2330:2330) (2392:2392:2392)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (2568:2568:2568) (2644:2644:2644)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (772:772:772) (832:832:832)) - (PORT d[1] (1981:1981:1981) (2101:2101:2101)) - (PORT d[2] (1595:1595:1595) (1678:1678:1678)) - (PORT d[3] (3662:3662:3662) (3956:3956:3956)) - (PORT d[4] (2837:2837:2837) (3046:3046:3046)) - (PORT d[5] (994:994:994) (1048:1048:1048)) - (PORT d[6] (3173:3173:3173) (3369:3369:3369)) - (PORT d[7] (2355:2355:2355) (2498:2498:2498)) - (PORT d[8] (1008:1008:1008) (1031:1031:1031)) - (PORT d[9] (2661:2661:2661) (2723:2723:2723)) - (PORT d[10] (997:997:997) (1017:1017:1017)) - (PORT d[11] (1180:1180:1180) (1219:1219:1219)) - (PORT d[12] (2107:2107:2107) (2193:2193:2193)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (806:806:806) (831:831:831)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1563:1563:1563) (1673:1673:1673)) - (PORT clk (1870:1870:1870) (1897:1897:1897)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3010:3010:3010) (3153:3153:3153)) - (PORT d[1] (1389:1389:1389) (1482:1482:1482)) - (PORT d[2] (3335:3335:3335) (3662:3662:3662)) - (PORT d[3] (2633:2633:2633) (2845:2845:2845)) - (PORT d[4] (2624:2624:2624) (2835:2835:2835)) - (PORT d[5] (2096:2096:2096) (2244:2244:2244)) - (PORT d[6] (2314:2314:2314) (2459:2459:2459)) - (PORT d[7] (2921:2921:2921) (3086:3086:3086)) - (PORT d[8] (2997:2997:2997) (3182:3182:3182)) - (PORT d[9] (3518:3518:3518) (3626:3626:3626)) - (PORT d[10] (2557:2557:2557) (2764:2764:2764)) - (PORT d[11] (3049:3049:3049) (3278:3278:3278)) - (PORT d[12] (3354:3354:3354) (3501:3501:3501)) - (PORT clk (1867:1867:1867) (1893:1893:1893)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2046:2046:2046) (2047:2047:2047)) - (PORT clk (1867:1867:1867) (1893:1893:1893)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1897:1897:1897)) - (PORT d[0] (3234:3234:3234) (3180:3180:3180)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1822:1822:1822)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4219:4219:4219) (4349:4349:4349)) - (PORT clk (1835:1835:1835) (1828:1828:1828)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1848:1848:1848) (1928:1928:1928)) - (PORT d[1] (1917:1917:1917) (2024:2024:2024)) - (PORT d[2] (1801:1801:1801) (1863:1863:1863)) - (PORT d[3] (1926:1926:1926) (2102:2102:2102)) - (PORT d[4] (1854:1854:1854) (1944:1944:1944)) - (PORT d[5] (2062:2062:2062) (2141:2141:2141)) - (PORT d[6] (1926:1926:1926) (2012:2012:2012)) - (PORT d[7] (1860:1860:1860) (1913:1913:1913)) - (PORT d[8] (2063:2063:2063) (2165:2165:2165)) - (PORT d[9] (1974:1974:1974) (2023:2023:2023)) - (PORT d[10] (2136:2136:2136) (2259:2259:2259)) - (PORT d[11] (2097:2097:2097) (2159:2159:2159)) - (PORT d[12] (2054:2054:2054) (2156:2156:2156)) - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1828:1828:1828)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1827:1827:1827) (1824:1824:1824)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (375:375:375) (410:410:410)) - (PORT datab (670:670:670) (715:715:715)) - (PORT datac (999:999:999) (1090:1090:1090)) - (PORT datad (1438:1438:1438) (1506:1506:1506)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (917:917:917)) - (PORT datab (1031:1031:1031) (1121:1121:1121)) - (PORT datac (656:656:656) (672:672:672)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1502:1502:1502)) - (PORT datab (235:235:235) (279:279:279)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (2434:2434:2434) (2602:2602:2602)) - (PORT datab (1531:1531:1531) (1592:1592:1592)) - (PORT datac (3029:3029:3029) (3276:3276:3276)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (742:742:742) (811:811:811)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (209:209:209) (250:250:250)) - (PORT datad (540:540:540) (552:552:552)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1514:1514:1514) (1591:1591:1591)) - (PORT datab (1677:1677:1677) (1753:1753:1753)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|always0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2081:2081:2081) (2108:2108:2108)) - (PORT datab (3058:3058:3058) (3307:3307:3307)) - (PORT datac (2207:2207:2207) (2319:2319:2319)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|always0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2435:2435:2435) (2597:2597:2597)) - (PORT datab (1535:1535:1535) (1599:1599:1599)) - (PORT datac (3026:3026:3026) (3271:3271:3271)) - (PORT datad (171:171:171) (197:197:197)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|mclk_r\~0) - (DELAY - (ABSOLUTE - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1888:1888:1888) (1912:1912:1912)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (785:785:785)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~2) - (DELAY - (ABSOLUTE - (PORT datab (253:253:253) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) - (DELAY - (ABSOLUTE - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (176:176:176) (203:203:203)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1888:1888:1888) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (438:438:438) (506:506:506)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datac (304:304:304) (327:327:327)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1888:1888:1888) (1910:1910:1910)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~6) - (DELAY - (ABSOLUTE - (PORT datab (398:398:398) (468:468:468)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT datad (591:591:591) (603:603:603)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1887:1887:1887) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~8) - (DELAY - (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (277:277:277)) - (PORT datac (173:173:173) (206:206:206)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1888:1888:1888) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (468:468:468)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) - (DELAY - (ABSOLUTE - (PORT datac (317:317:317) (345:345:345)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1887:1887:1887) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~12) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (469:469:469)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) - (DELAY - (ABSOLUTE - (PORT datac (344:344:344) (371:371:371)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1887:1887:1887) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (487:487:487)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (345:345:345) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1887:1887:1887) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~16) - (DELAY - (ABSOLUTE - (PORT datab (675:675:675) (736:736:736)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) - (DELAY - (ABSOLUTE - (PORT datac (569:569:569) (588:588:588)) - (PORT datad (575:575:575) (582:582:582)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~18) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (300:300:300)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) - (DELAY - (ABSOLUTE - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1888:1888:1888) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (466:466:466)) - (PORT datab (249:249:249) (332:332:332)) - (PORT datac (386:386:386) (448:448:448)) - (PORT datad (636:636:636) (694:694:694)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (509:509:509)) - (PORT datab (392:392:392) (463:463:463)) - (PORT datac (365:365:365) (426:426:426)) - (PORT datad (223:223:223) (294:294:294)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (249:249:249) (333:333:333)) - (PORT datac (667:667:667) (742:742:742)) - (PORT datad (310:310:310) (330:330:330)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (248:248:248) (334:334:334)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (253:253:253) (338:338:338)) - (PORT datac (225:225:225) (305:305:305)) - (PORT datad (227:227:227) (299:299:299)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) - (DELAY - (ABSOLUTE - (PORT datab (277:277:277) (368:368:368)) - (PORT datac (244:244:244) (323:323:323)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~7) - (DELAY - (ABSOLUTE - (PORT datab (277:277:277) (371:371:371)) - (IOPATH datab cout (446:446:446) (318:318:318)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~8) - (DELAY - (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~20) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (371:371:371)) - (PORT datab (276:276:276) (371:371:371)) - (PORT datac (1492:1492:1492) (1577:1577:1577)) - (PORT datad (207:207:207) (243:243:243)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1899:1899:1899) (1922:1922:1922)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (342:342:342)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~17) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (430:430:430)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (210:210:210) (251:251:251)) - (PORT datad (1502:1502:1502) (1581:1581:1581)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1899:1899:1899) (1922:1922:1922)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~19) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (376:376:376)) - (PORT datab (278:278:278) (369:369:369)) - (PORT datac (1492:1492:1492) (1581:1581:1581)) - (PORT datad (207:207:207) (243:243:243)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1899:1899:1899) (1922:1922:1922)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~14) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~16) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (430:430:430)) - (PORT datab (1519:1519:1519) (1611:1611:1611)) - (PORT datac (210:210:210) (251:251:251)) - (PORT datad (314:314:314) (331:331:331)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1899:1899:1899) (1922:1922:1922)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (251:251:251) (339:339:339)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (225:225:225) (306:306:306)) - (PORT datad (224:224:224) (296:296:296)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (479:479:479)) - (PORT datab (275:275:275) (370:370:370)) - (PORT datac (555:555:555) (562:562:562)) - (PORT datad (199:199:199) (234:234:234)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1546:1546:1546) (1630:1630:1630)) - (PORT datab (241:241:241) (286:286:286)) - (PORT datad (207:207:207) (243:243:243)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1899:1899:1899) (1922:1922:1922)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT datab (280:280:280) (375:375:375)) - (PORT datad (202:202:202) (237:237:237)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (396:396:396) (427:427:427)) - (PORT datac (247:247:247) (336:336:336)) - (PORT datad (1254:1254:1254) (1338:1338:1338)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) - (DELAY - (ABSOLUTE - (PORT datad (570:570:570) (576:576:576)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1282:1282:1282) (1381:1381:1381)) - (PORT datac (247:247:247) (338:338:338)) - (PORT datad (368:368:368) (391:391:391)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (720:720:720) (744:744:744)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT sload (1864:1864:1864) (1994:1994:1994)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT datab (248:248:248) (333:333:333)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (719:719:719) (743:743:743)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT sload (1864:1864:1864) (1994:1994:1994)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (719:719:719) (741:741:741)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT sload (1864:1864:1864) (1994:1994:1994)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (718:718:718) (741:741:741)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT sload (1864:1864:1864) (1994:1994:1994)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT datab (273:273:273) (358:358:358)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (716:716:716) (740:740:740)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT sload (1864:1864:1864) (1994:1994:1994)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (492:492:492)) - (PORT datab (278:278:278) (375:375:375)) - (PORT datac (365:365:365) (397:397:397)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE AUD_ADCDAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (414:414:414)) - (PORT datab (1407:1407:1407) (1533:1533:1533)) - (PORT datad (773:773:773) (762:762:762)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1879:1879:1879)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) - (DELAY - (ABSOLUTE - (PORT datac (1369:1369:1369) (1496:1496:1496)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1282:1282:1282) (1382:1382:1382)) - (PORT datac (246:246:246) (338:338:338)) - (PORT datad (370:370:370) (393:393:393)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT datac (1376:1376:1376) (1502:1502:1502)) - (PORT datad (220:220:220) (289:289:289)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) - (DELAY - (ABSOLUTE - (PORT datac (1377:1377:1377) (1500:1500:1500)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) - (DELAY - (ABSOLUTE - (PORT datac (1375:1375:1375) (1499:1499:1499)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datac (1374:1374:1374) (1504:1504:1504)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) - (DELAY - (ABSOLUTE - (PORT datac (1379:1379:1379) (1504:1504:1504)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) - (DELAY - (ABSOLUTE - (PORT datab (245:245:245) (327:327:327)) - (PORT datac (1374:1374:1374) (1505:1505:1505)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) - (DELAY - (ABSOLUTE - (PORT datac (1374:1374:1374) (1499:1499:1499)) - (PORT datad (220:220:220) (289:289:289)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) - (DELAY - (ABSOLUTE - (PORT datac (1365:1365:1365) (1498:1498:1498)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) - (DELAY - (ABSOLUTE - (PORT datab (247:247:247) (330:330:330)) - (PORT datac (1378:1378:1378) (1501:1501:1501)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (336:336:336)) - (PORT datac (1376:1376:1376) (1498:1498:1498)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) - (DELAY - (ABSOLUTE - (PORT datac (1373:1373:1373) (1504:1504:1504)) - (PORT datad (219:219:219) (287:287:287)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) - (DELAY - (ABSOLUTE - (PORT datab (1178:1178:1178) (1223:1223:1223)) - (PORT datad (244:244:244) (314:314:314)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT datad (539:539:539) (550:550:550)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (916:916:916)) - (PORT datab (1184:1184:1184) (1229:1229:1229)) - (PORT datad (374:374:374) (445:445:445)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ula_data\~0) - (DELAY - (ABSOLUTE - (PORT datac (882:882:882) (926:926:926)) - (PORT datad (688:688:688) (782:782:782)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1475:1475:1475) (1461:1461:1461)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datab (1979:1979:1979) (2103:2103:2103)) - (PORT datac (1378:1378:1378) (1504:1504:1504)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (733:733:733) (795:795:795)) - (PORT datab (1186:1186:1186) (1230:1230:1230)) - (PORT datac (2169:2169:2169) (2305:2305:2305)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1866:1866:1866) (1875:1875:1875)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (2767:2767:2767) (2833:2833:2833)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (484:484:484)) - (PORT datab (1187:1187:1187) (1230:1230:1230)) - (PORT datad (245:245:245) (318:318:318)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (869:869:869)) - (PORT datab (1523:1523:1523) (1602:1602:1602)) - (PORT datac (236:236:236) (312:312:312)) - (PORT datad (237:237:237) (306:306:306)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (3264:3264:3264) (3454:3454:3454)) - (PORT datab (834:834:834) (861:861:861)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (2277:2277:2277) (2436:2436:2436)) - (PORT datab (1152:1152:1152) (1241:1241:1241)) - (PORT datac (575:575:575) (625:625:625)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (749:749:749)) - (PORT datab (373:373:373) (397:397:397)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1420:1420:1420)) - (PORT datab (1261:1261:1261) (1344:1344:1344)) - (PORT datac (817:817:817) (836:836:836)) - (PORT datad (216:216:216) (242:242:242)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1326:1326:1326)) - (PORT datac (613:613:613) (660:660:660)) - (PORT datad (1021:1021:1021) (1046:1046:1046)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (723:723:723)) - (PORT datab (911:911:911) (985:985:985)) - (PORT datac (614:614:614) (663:663:663)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1411:1411:1411) (1467:1467:1467)) - (PORT datab (1304:1304:1304) (1367:1367:1367)) - (PORT datad (290:290:290) (379:379:379)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1178:1178:1178)) - (PORT datab (1110:1110:1110) (1162:1162:1162)) - (PORT datac (1334:1334:1334) (1413:1413:1413)) - (PORT datad (1423:1423:1423) (1553:1553:1553)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (278:278:278)) - (PORT datab (260:260:260) (307:307:307)) - (PORT datac (1341:1341:1341) (1384:1384:1384)) - (PORT datad (196:196:196) (229:229:229)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1365:1365:1365)) - (PORT datab (1052:1052:1052) (1078:1078:1078)) - (PORT datac (1010:1010:1010) (1021:1021:1021)) - (PORT datad (1083:1083:1083) (1107:1107:1107)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1073:1073:1073) (1153:1153:1153)) - (PORT datab (235:235:235) (279:279:279)) - (PORT datad (621:621:621) (652:652:652)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (1337:1337:1337) (1379:1379:1379)) - (PORT datac (1582:1582:1582) (1642:1642:1642)) - (PORT datad (554:554:554) (576:576:576)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (742:742:742)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (814:814:814) (825:825:825)) - (PORT datad (630:630:630) (664:664:664)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (874:874:874)) - (PORT datab (718:718:718) (793:793:793)) - (PORT datac (1586:1586:1586) (1641:1641:1641)) - (PORT datad (633:633:633) (664:664:664)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1047:1047:1047) (1081:1081:1081)) - (PORT datab (1091:1091:1091) (1104:1104:1104)) - (PORT datac (872:872:872) (886:886:886)) - (PORT datad (217:217:217) (252:252:252)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (861:861:861)) - (PORT datab (663:663:663) (677:677:677)) - (PORT datac (1259:1259:1259) (1274:1274:1274)) - (PORT datad (674:674:674) (700:700:700)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (286:286:286)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1248:1248:1248) (1322:1322:1322)) - (PORT datac (324:324:324) (358:358:358)) - (PORT datad (1015:1015:1015) (1046:1046:1046)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (749:749:749)) - (PORT datac (954:954:954) (1036:1036:1036)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (209:209:209) (251:251:251)) - (PORT datad (708:708:708) (792:792:792)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1558:1558:1558)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1277:1277:1277)) - (PORT datab (1000:1000:1000) (1059:1059:1059)) - (PORT datac (247:247:247) (330:330:330)) - (PORT datad (628:628:628) (690:690:690)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1256:1256:1256)) - (PORT datab (647:647:647) (714:714:714)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (717:717:717)) - (PORT datab (698:698:698) (764:764:764)) - (PORT datad (328:328:328) (350:350:350)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (377:377:377)) - (PORT datab (979:979:979) (1047:1047:1047)) - (PORT datad (323:323:323) (343:343:343)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (922:922:922)) - (PORT datab (1858:1858:1858) (1898:1898:1898)) - (PORT datac (214:214:214) (289:289:289)) - (PORT datad (540:540:540) (585:585:585)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT datab (669:669:669) (736:736:736)) - (PORT datac (662:662:662) (729:729:729)) - (PORT datad (1143:1143:1143) (1184:1184:1184)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (728:728:728)) - (PORT datab (962:962:962) (1017:1017:1017)) - (PORT datac (539:539:539) (561:561:561)) - (PORT datad (535:535:535) (543:543:543)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT datac (1158:1158:1158) (1230:1230:1230)) - (PORT datad (441:441:441) (517:517:517)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (269:269:269)) - (PORT datab (750:750:750) (833:833:833)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (732:732:732)) - (PORT datac (539:539:539) (565:565:565)) - (PORT datad (922:922:922) (980:980:980)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT datab (477:477:477) (560:560:560)) - (PORT datac (1160:1160:1160) (1233:1233:1233)) - (PORT datad (533:533:533) (544:544:544)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (750:750:750) (832:832:832)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (937:937:937)) - (PORT datab (240:240:240) (321:321:321)) - (PORT datac (214:214:214) (290:290:290)) - (PORT datad (865:865:865) (919:919:919)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (989:989:989) (1073:1073:1073)) - (PORT datab (232:232:232) (275:275:275)) - (PORT datad (197:197:197) (232:232:232)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (634:634:634)) - (PORT datad (704:704:704) (791:791:791)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1558:1558:1558)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT datab (1238:1238:1238) (1305:1305:1305)) - (PORT datac (957:957:957) (1037:1037:1037)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (413:413:413)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (709:709:709) (798:798:798)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1558:1558:1558)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1082:1082:1082) (1109:1109:1109)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datac (1831:1831:1831) (1886:1886:1886)) - (PORT datad (218:218:218) (288:288:288)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (636:636:636)) - (PORT datab (1146:1146:1146) (1216:1216:1216)) - (PORT datac (937:937:937) (1010:1010:1010)) - (PORT datad (958:958:958) (1027:1027:1027)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (266:266:266)) - (PORT datab (834:834:834) (847:847:847)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (684:684:684) (742:742:742)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (705:705:705)) - (PORT datab (370:370:370) (391:391:391)) - (PORT datac (288:288:288) (378:378:378)) - (PORT datad (644:644:644) (711:711:711)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~68) - (DELAY - (ABSOLUTE - (PORT datab (424:424:424) (511:511:511)) - (PORT datac (704:704:704) (785:785:785)) - (PORT datad (744:744:744) (818:818:818)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (770:770:770) (863:863:863)) - (PORT datab (977:977:977) (1041:1041:1041)) - (PORT datac (951:951:951) (1014:1014:1014)) - (PORT datad (856:856:856) (934:934:934)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT datac (906:906:906) (972:972:972)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (827:827:827)) - (PORT datab (209:209:209) (250:250:250)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (739:739:739)) - (PORT datab (856:856:856) (896:896:896)) - (PORT datac (614:614:614) (663:663:663)) - (PORT datad (913:913:913) (960:960:960)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (378:378:378) (402:402:402)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (764:764:764) (789:789:789)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (873:873:873)) - (PORT datab (3323:3323:3323) (3560:3560:3560)) - (PORT datac (1214:1214:1214) (1276:1276:1276)) - (PORT datad (697:697:697) (763:763:763)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2883:2883:2883) (2974:2974:2974)) - (PORT clk (1847:1847:1847) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3758:3758:3758) (4061:4061:4061)) - (PORT d[1] (2384:2384:2384) (2587:2587:2587)) - (PORT d[2] (4330:4330:4330) (4558:4558:4558)) - (PORT d[3] (3269:3269:3269) (3589:3589:3589)) - (PORT d[4] (3205:3205:3205) (3425:3425:3425)) - (PORT d[5] (3995:3995:3995) (4292:4292:4292)) - (PORT d[6] (1989:1989:1989) (2048:2048:2048)) - (PORT d[7] (2791:2791:2791) (2893:2893:2893)) - (PORT d[8] (2796:2796:2796) (2969:2969:2969)) - (PORT d[9] (2195:2195:2195) (2271:2271:2271)) - (PORT d[10] (1561:1561:1561) (1642:1642:1642)) - (PORT d[11] (1535:1535:1535) (1656:1656:1656)) - (PORT d[12] (2218:2218:2218) (2277:2277:2277)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2400:2400:2400) (2441:2441:2441)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (PORT d[0] (2793:2793:2793) (2846:2846:2846)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2603:2603:2603) (2673:2673:2673)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3512:3512:3512) (3767:3767:3767)) - (PORT d[1] (2119:2119:2119) (2309:2309:2309)) - (PORT d[2] (4014:4014:4014) (4236:4236:4236)) - (PORT d[3] (2955:2955:2955) (3243:3243:3243)) - (PORT d[4] (2861:2861:2861) (3093:3093:3093)) - (PORT d[5] (3688:3688:3688) (3954:3954:3954)) - (PORT d[6] (2564:2564:2564) (2723:2723:2723)) - (PORT d[7] (3150:3150:3150) (3265:3265:3265)) - (PORT d[8] (2216:2216:2216) (2371:2371:2371)) - (PORT d[9] (2566:2566:2566) (2692:2692:2692)) - (PORT d[10] (2606:2606:2606) (2782:2782:2782)) - (PORT d[11] (1719:1719:1719) (1828:1828:1828)) - (PORT d[12] (2503:2503:2503) (2607:2607:2607)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1951:1951:1951) (1908:1908:1908)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (2683:2683:2683) (2737:2737:2737)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (458:458:458)) - (PORT datab (909:909:909) (925:925:925)) - (PORT datac (1160:1160:1160) (1239:1239:1239)) - (PORT datad (1162:1162:1162) (1198:1198:1198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2002:2002:2002) (2075:2075:2075)) - (PORT clk (1849:1849:1849) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3172:3172:3172) (3423:3423:3423)) - (PORT d[1] (2108:2108:2108) (2273:2273:2273)) - (PORT d[2] (2307:2307:2307) (2529:2529:2529)) - (PORT d[3] (2676:2676:2676) (2915:2915:2915)) - (PORT d[4] (2225:2225:2225) (2399:2399:2399)) - (PORT d[5] (3373:3373:3373) (3628:3628:3628)) - (PORT d[6] (2284:2284:2284) (2423:2423:2423)) - (PORT d[7] (3683:3683:3683) (3819:3819:3819)) - (PORT d[8] (2176:2176:2176) (2310:2310:2310)) - (PORT d[9] (2801:2801:2801) (2942:2942:2942)) - (PORT d[10] (1977:1977:1977) (2131:2131:2131)) - (PORT d[11] (1870:1870:1870) (2044:2044:2044)) - (PORT d[12] (2810:2810:2810) (2943:2943:2943)) - (PORT clk (1846:1846:1846) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3043:3043:3043) (3118:3118:3118)) - (PORT clk (1846:1846:1846) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1878:1878:1878)) - (PORT d[0] (3443:3443:3443) (3502:3502:3502)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2297:2297:2297) (2367:2367:2367)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3490:3490:3490) (3747:3747:3747)) - (PORT d[1] (2348:2348:2348) (2530:2530:2530)) - (PORT d[2] (3734:3734:3734) (3971:3971:3971)) - (PORT d[3] (2975:2975:2975) (3240:3240:3240)) - (PORT d[4] (2538:2538:2538) (2736:2736:2736)) - (PORT d[5] (3674:3674:3674) (3955:3955:3955)) - (PORT d[6] (1674:1674:1674) (1708:1708:1708)) - (PORT d[7] (3384:3384:3384) (3498:3498:3498)) - (PORT d[8] (2215:2215:2215) (2370:2370:2370)) - (PORT d[9] (2556:2556:2556) (2660:2660:2660)) - (PORT d[10] (2283:2283:2283) (2436:2436:2436)) - (PORT d[11] (1880:1880:1880) (2047:2047:2047)) - (PORT d[12] (2509:2509:2509) (2617:2617:2617)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1745:1745:1745) (1723:1723:1723)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (3117:3117:3117) (3161:3161:3161)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (454:454:454)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (1468:1468:1468) (1509:1509:1509)) - (PORT datad (1175:1175:1175) (1195:1195:1195)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1006:1006:1006) (1049:1049:1049)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1319:1319:1319) (1370:1370:1370)) - (PORT d[1] (1987:1987:1987) (2086:2086:2086)) - (PORT d[2] (1577:1577:1577) (1693:1693:1693)) - (PORT d[3] (3669:3669:3669) (3950:3950:3950)) - (PORT d[4] (2882:2882:2882) (3117:3117:3117)) - (PORT d[5] (1257:1257:1257) (1296:1296:1296)) - (PORT d[6] (1113:1113:1113) (1136:1136:1136)) - (PORT d[7] (2674:2674:2674) (2839:2839:2839)) - (PORT d[8] (1304:1304:1304) (1352:1352:1352)) - (PORT d[9] (4662:4662:4662) (4844:4844:4844)) - (PORT d[10] (1312:1312:1312) (1359:1359:1359)) - (PORT d[11] (4146:4146:4146) (4423:4423:4423)) - (PORT d[12] (2646:2646:2646) (2740:2740:2740)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1748:1748:1748) (1732:1732:1732)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2336:2336:2336) (2359:2359:2359)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2778:2778:2778) (2873:2873:2873)) - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1877:1877:1877) (1980:1980:1980)) - (PORT d[1] (1864:1864:1864) (1967:1967:1967)) - (PORT d[2] (1900:1900:1900) (2034:2034:2034)) - (PORT d[3] (2011:2011:2011) (2198:2198:2198)) - (PORT d[4] (1926:1926:1926) (2025:2025:2025)) - (PORT d[5] (1855:1855:1855) (1968:1968:1968)) - (PORT d[6] (1789:1789:1789) (1915:1915:1915)) - (PORT d[7] (1864:1864:1864) (1990:1990:1990)) - (PORT d[8] (1957:1957:1957) (2108:2108:2108)) - (PORT d[9] (2036:2036:2036) (2135:2135:2135)) - (PORT d[10] (1892:1892:1892) (1976:1976:1976)) - (PORT d[11] (2020:2020:2020) (2088:2088:2088)) - (PORT d[12] (2073:2073:2073) (2152:2152:2152)) - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (740:740:740) (774:774:774)) - (PORT d[1] (3345:3345:3345) (3629:3629:3629)) - (PORT d[2] (1616:1616:1616) (1746:1746:1746)) - (PORT d[3] (3945:3945:3945) (4253:4253:4253)) - (PORT d[4] (3125:3125:3125) (3332:3332:3332)) - (PORT d[5] (1233:1233:1233) (1278:1278:1278)) - (PORT d[6] (3247:3247:3247) (3438:3438:3438)) - (PORT d[7] (2656:2656:2656) (2765:2765:2765)) - (PORT d[8] (1010:1010:1010) (1048:1048:1048)) - (PORT d[9] (2726:2726:2726) (2798:2798:2798)) - (PORT d[10] (1231:1231:1231) (1258:1258:1258)) - (PORT d[11] (1478:1478:1478) (1519:1519:1519)) - (PORT d[12] (2080:2080:2080) (2160:2160:2160)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1879:1879:1879)) - (PORT d[0] (1097:1097:1097) (1106:1106:1106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (997:997:997) (1055:1055:1055)) - (PORT clk (1858:1858:1858) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1395:1395:1395) (1508:1508:1508)) - (PORT d[1] (1654:1654:1654) (1743:1743:1743)) - (PORT d[2] (3652:3652:3652) (4014:4014:4014)) - (PORT d[3] (3377:3377:3377) (3599:3599:3599)) - (PORT d[4] (2253:2253:2253) (2433:2433:2433)) - (PORT d[5] (1303:1303:1303) (1382:1382:1382)) - (PORT d[6] (1184:1184:1184) (1230:1230:1230)) - (PORT d[7] (2668:2668:2668) (2822:2822:2822)) - (PORT d[8] (1474:1474:1474) (1538:1538:1538)) - (PORT d[9] (2957:2957:2957) (3060:3060:3060)) - (PORT d[10] (1955:1955:1955) (2037:2037:2037)) - (PORT d[11] (2657:2657:2657) (2887:2887:2887)) - (PORT d[12] (2384:2384:2384) (2498:2498:2498)) - (PORT clk (1855:1855:1855) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1531:1531:1531) (1523:1523:1523)) - (PORT clk (1855:1855:1855) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (PORT d[0] (2083:2083:2083) (2062:2062:2062)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1811:1811:1811)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3099:3099:3099) (3168:3168:3168)) - (PORT clk (1823:1823:1823) (1817:1817:1817)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1872:1872:1872) (2017:2017:2017)) - (PORT d[1] (1844:1844:1844) (1957:1957:1957)) - (PORT d[2] (1841:1841:1841) (1966:1966:1966)) - (PORT d[3] (1832:1832:1832) (1961:1961:1961)) - (PORT d[4] (1884:1884:1884) (1997:1997:1997)) - (PORT d[5] (1788:1788:1788) (1890:1890:1890)) - (PORT d[6] (1810:1810:1810) (1961:1961:1961)) - (PORT d[7] (1845:1845:1845) (1969:1969:1969)) - (PORT d[8] (1905:1905:1905) (2022:2022:2022)) - (PORT d[9] (1890:1890:1890) (1987:1987:1987)) - (PORT d[10] (1895:1895:1895) (1995:1995:1995)) - (PORT d[11] (1995:1995:1995) (2078:2078:2078)) - (PORT d[12] (1857:1857:1857) (1941:1941:1941)) - (PORT clk (1819:1819:1819) (1813:1813:1813)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (929:929:929)) - (PORT datab (1223:1223:1223) (1263:1263:1263)) - (PORT datac (267:267:267) (356:356:356)) - (PORT datad (1171:1171:1171) (1226:1226:1226)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (734:734:734) (784:784:784)) - (PORT d[1] (3090:3090:3090) (3353:3353:3353)) - (PORT d[2] (2189:2189:2189) (2293:2293:2293)) - (PORT d[3] (1005:1005:1005) (1060:1060:1060)) - (PORT d[4] (3388:3388:3388) (3635:3635:3635)) - (PORT d[5] (1292:1292:1292) (1358:1358:1358)) - (PORT d[6] (2882:2882:2882) (3040:3040:3040)) - (PORT d[7] (2332:2332:2332) (2441:2441:2441)) - (PORT d[8] (4009:4009:4009) (4256:4256:4256)) - (PORT d[9] (3026:3026:3026) (3124:3124:3124)) - (PORT d[10] (2857:2857:2857) (3068:3068:3068)) - (PORT d[11] (2243:2243:2243) (2459:2459:2459)) - (PORT d[12] (2401:2401:2401) (2507:2507:2507)) - (PORT clk (1847:1847:1847) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1873:1873:1873)) - (PORT d[0] (2265:2265:2265) (2316:2316:2316)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1836:1836:1836)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (509:509:509)) - (PORT datab (1216:1216:1216) (1243:1243:1243)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (1147:1147:1147) (1184:1184:1184)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (945:945:945) (1001:1001:1001)) - (PORT datab (974:974:974) (1025:1025:1025)) - (PORT datac (1035:1035:1035) (1021:1021:1021)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1834:1834:1834) (1929:1929:1929)) - (PORT datab (3299:3299:3299) (3522:3522:3522)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (2114:2114:2114) (2240:2240:2240)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1221:1221:1221) (1271:1271:1271)) - (PORT datab (1186:1186:1186) (1278:1278:1278)) - (PORT datac (1163:1163:1163) (1242:1242:1242)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (646:646:646)) - (PORT datac (671:671:671) (706:706:706)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1431:1431:1431)) - (PORT datab (1272:1272:1272) (1358:1358:1358)) - (PORT datac (203:203:203) (240:240:240)) - (PORT datad (815:815:815) (833:833:833)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (650:650:650) (697:697:697)) - (PORT datac (1155:1155:1155) (1213:1213:1213)) - (PORT datad (649:649:649) (676:676:676)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1613:1613:1613) (1667:1667:1667)) - (PORT datad (1599:1599:1599) (1670:1670:1670)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1211:1211:1211)) - (PORT datab (2629:2629:2629) (2707:2707:2707)) - (PORT datac (839:839:839) (855:855:855)) - (PORT datad (1895:1895:1895) (1903:1903:1903)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) - (DELAY - (ABSOLUTE - (PORT dataa (552:552:552) (576:576:576)) - (PORT datab (1794:1794:1794) (1841:1841:1841)) - (PORT datac (908:908:908) (961:961:961)) - (PORT datad (908:908:908) (963:963:963)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) - (PORT ena (1555:1555:1555) (1575:1575:1575)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (508:508:508)) - (PORT datab (1093:1093:1093) (1162:1162:1162)) - (PORT datac (622:622:622) (681:681:681)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1337:1337:1337) (1396:1396:1396)) - (PORT datab (630:630:630) (669:669:669)) - (PORT datac (1459:1459:1459) (1494:1494:1494)) - (PORT datad (930:930:930) (964:964:964)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (946:946:946)) - (PORT datab (1111:1111:1111) (1112:1112:1112)) - (PORT datac (990:990:990) (1004:1004:1004)) - (PORT datad (1053:1053:1053) (1045:1045:1045)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (953:953:953)) - (PORT datab (214:214:214) (258:258:258)) - (PORT datac (1040:1040:1040) (1049:1049:1049)) - (PORT datad (1055:1055:1055) (1058:1058:1058)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) - (DELAY - (ABSOLUTE - (PORT datab (652:652:652) (705:705:705)) - (PORT datad (586:586:586) (626:626:626)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (737:737:737)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (195:195:195) (219:219:219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1111:1111:1111) (1127:1127:1127)) - (PORT datac (727:727:727) (737:737:737)) - (PORT datad (1018:1018:1018) (1023:1023:1023)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (1011:1011:1011) (1018:1018:1018)) - (PORT datac (556:556:556) (578:578:578)) - (PORT datad (790:790:790) (799:799:799)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (773:773:773) (860:860:860)) - (PORT datab (974:974:974) (1036:1036:1036)) - (PORT datac (903:903:903) (968:968:968)) - (PORT datad (853:853:853) (930:930:930)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (985:985:985) (1048:1048:1048)) - (PORT datac (768:768:768) (788:788:788)) - (PORT datad (745:745:745) (820:820:820)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (333:333:333) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT datab (209:209:209) (252:252:252)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (527:527:527)) - (PORT datac (679:679:679) (761:761:761)) - (PORT datad (921:921:921) (988:988:988)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (797:797:797)) - (PORT datab (1091:1091:1091) (1157:1157:1157)) - (PORT datac (956:956:956) (1013:1013:1013)) - (PORT datad (873:873:873) (937:937:937)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (208:208:208) (251:251:251)) - (PORT datad (174:174:174) (201:201:201)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (477:477:477)) - (PORT datab (1426:1426:1426) (1483:1483:1483)) - (PORT datac (842:842:842) (895:895:895)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (754:754:754)) - (PORT datab (384:384:384) (413:413:413)) - (PORT datad (448:448:448) (529:529:529)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (752:752:752)) - (PORT datab (564:564:564) (570:570:570)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (456:456:456)) - (PORT datab (902:902:902) (959:959:959)) - (PORT datac (214:214:214) (290:290:290)) - (PORT datad (799:799:799) (821:821:821)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~134) - (DELAY - (ABSOLUTE - (PORT dataa (1218:1218:1218) (1285:1285:1285)) - (PORT datab (969:969:969) (1037:1037:1037)) - (PORT datad (556:556:556) (560:560:560)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT datac (888:888:888) (945:945:945)) - (PORT datad (677:677:677) (746:746:746)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (789:789:789)) - (PORT datab (346:346:346) (372:372:372)) - (PORT datac (187:187:187) (229:229:229)) - (PORT datad (955:955:955) (1025:1025:1025)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (451:451:451) (525:525:525)) - (PORT datab (335:335:335) (368:368:368)) - (PORT datac (509:509:509) (518:518:518)) - (PORT datad (627:627:627) (648:648:648)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (725:725:725)) - (PORT datad (315:315:315) (335:335:335)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datab (1238:1238:1238) (1305:1305:1305)) - (PORT datac (952:952:952) (1032:1032:1032)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (1208:1208:1208) (1279:1279:1279)) - (PORT datab (666:666:666) (735:735:735)) - (PORT datac (639:639:639) (711:711:711)) - (PORT datad (588:588:588) (642:642:642)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (987:987:987)) - (PORT datab (590:590:590) (617:617:617)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datad (703:703:703) (794:794:794)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1558:1558:1558)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (431:431:431) (500:500:500)) - (PORT datab (856:856:856) (895:895:895)) - (PORT datac (649:649:649) (699:699:699)) - (PORT datad (1107:1107:1107) (1152:1152:1152)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1086:1086:1086) (1158:1158:1158)) - (PORT datab (964:964:964) (1030:1030:1030)) - (PORT datac (613:613:613) (669:669:669)) - (PORT datad (941:941:941) (1011:1011:1011)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~77) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (317:317:317) (410:410:410)) - (PORT datac (613:613:613) (626:626:626)) - (PORT datad (586:586:586) (650:650:650)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1086:1086:1086) (1155:1155:1155)) - (PORT datab (968:968:968) (1034:1034:1034)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (727:727:727) (790:790:790)) - (PORT datab (1146:1146:1146) (1216:1216:1216)) - (PORT datac (942:942:942) (1011:1011:1011)) - (PORT datad (674:674:674) (744:744:744)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~75) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (794:794:794)) - (PORT datab (231:231:231) (274:274:274)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (960:960:960) (1026:1026:1026)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datab (318:318:318) (415:415:415)) - (PORT datac (623:623:623) (663:663:663)) - (PORT datad (331:331:331) (348:348:348)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (430:430:430) (517:517:517)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (768:768:768)) - (PORT datab (1167:1167:1167) (1221:1221:1221)) - (PORT datac (645:645:645) (710:710:710)) - (PORT datad (870:870:870) (885:885:885)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (763:763:763)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (645:645:645)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (2000:2000:2000) (2050:2050:2050)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (907:907:907)) - (PORT datab (331:331:331) (361:361:361)) - (PORT datac (535:535:535) (539:539:539)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2232:2232:2232) (2353:2353:2353)) - (PORT clk (1850:1850:1850) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2861:2861:2861) (3087:3087:3087)) - (PORT d[1] (1799:1799:1799) (1959:1959:1959)) - (PORT d[2] (2607:2607:2607) (2822:2822:2822)) - (PORT d[3] (2355:2355:2355) (2592:2592:2592)) - (PORT d[4] (1954:1954:1954) (2113:2113:2113)) - (PORT d[5] (3082:3082:3082) (3310:3310:3310)) - (PORT d[6] (1979:1979:1979) (2096:2096:2096)) - (PORT d[7] (4035:4035:4035) (4216:4216:4216)) - (PORT d[8] (2475:2475:2475) (2643:2643:2643)) - (PORT d[9] (2803:2803:2803) (2925:2925:2925)) - (PORT d[10] (1891:1891:1891) (2013:2013:2013)) - (PORT d[11] (1908:1908:1908) (2070:2070:2070)) - (PORT d[12] (3099:3099:3099) (3255:3255:3255)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2769:2769:2769) (2830:2830:2830)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1879:1879:1879)) - (PORT d[0] (3160:3160:3160) (3198:3198:3198)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1611:1611:1611) (1719:1719:1719)) - (PORT clk (1854:1854:1854) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1958:1958:1958) (2078:2078:2078)) - (PORT d[1] (2431:2431:2431) (2644:2644:2644)) - (PORT d[2] (2066:2066:2066) (2252:2252:2252)) - (PORT d[3] (1285:1285:1285) (1374:1374:1374)) - (PORT d[4] (2454:2454:2454) (2612:2612:2612)) - (PORT d[5] (4879:4879:4879) (5239:5239:5239)) - (PORT d[6] (1998:1998:1998) (2076:2076:2076)) - (PORT d[7] (1659:1659:1659) (1699:1699:1699)) - (PORT d[8] (2735:2735:2735) (2906:2906:2906)) - (PORT d[9] (3098:3098:3098) (3222:3222:3222)) - (PORT d[10] (1949:1949:1949) (2109:2109:2109)) - (PORT d[11] (2103:2103:2103) (2234:2234:2234)) - (PORT d[12] (1356:1356:1356) (1360:1360:1360)) - (PORT clk (1851:1851:1851) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1707:1707:1707) (1705:1705:1705)) - (PORT clk (1851:1851:1851) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (PORT d[0] (2993:2993:2993) (3013:3013:3013)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1841:1841:1841)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1630:1630:1630) (1719:1719:1719)) - (PORT clk (1853:1853:1853) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1928:1928:1928) (2049:2049:2049)) - (PORT d[1] (2688:2688:2688) (2914:2914:2914)) - (PORT d[2] (2053:2053:2053) (2250:2250:2250)) - (PORT d[3] (1511:1511:1511) (1575:1575:1575)) - (PORT d[4] (2207:2207:2207) (2372:2372:2372)) - (PORT d[5] (4876:4876:4876) (5216:5216:5216)) - (PORT d[6] (2220:2220:2220) (2290:2290:2290)) - (PORT d[7] (1905:1905:1905) (1937:1937:1937)) - (PORT d[8] (3080:3080:3080) (3260:3260:3260)) - (PORT d[9] (3097:3097:3097) (3212:3212:3212)) - (PORT d[10] (1944:1944:1944) (2100:2100:2100)) - (PORT d[11] (2115:2115:2115) (2280:2280:2280)) - (PORT d[12] (1121:1121:1121) (1135:1135:1135)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2198:2198:2198) (2190:2190:2190)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (PORT d[0] (2605:2605:2605) (2653:2653:2653)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1841:1841:1841)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1825:1825:1825) (1934:1934:1934)) - (PORT clk (1843:1843:1843) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2501:2501:2501) (2661:2661:2661)) - (PORT d[1] (2703:2703:2703) (2915:2915:2915)) - (PORT d[2] (2085:2085:2085) (2272:2272:2272)) - (PORT d[3] (3896:3896:3896) (4246:4246:4246)) - (PORT d[4] (1916:1916:1916) (2059:2059:2059)) - (PORT d[5] (4578:4578:4578) (4899:4899:4899)) - (PORT d[6] (2265:2265:2265) (2368:2368:2368)) - (PORT d[7] (2450:2450:2450) (2509:2509:2509)) - (PORT d[8] (3365:3365:3365) (3560:3560:3560)) - (PORT d[9] (2530:2530:2530) (2652:2652:2652)) - (PORT d[10] (2276:2276:2276) (2451:2451:2451)) - (PORT d[11] (2433:2433:2433) (2576:2576:2576)) - (PORT d[12] (1598:1598:1598) (1629:1629:1629)) - (PORT clk (1840:1840:1840) (1868:1868:1868)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2052:2052:2052) (2064:2064:2064)) - (PORT clk (1840:1840:1840) (1868:1868:1868)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1872:1872:1872)) - (PORT d[0] (2833:2833:2833) (2885:2885:2885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1831:1831:1831)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (995:995:995)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (995:995:995)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (458:458:458)) - (PORT datab (1530:1530:1530) (1550:1550:1550)) - (PORT datac (1164:1164:1164) (1242:1242:1242)) - (PORT datad (1166:1166:1166) (1192:1192:1192)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (453:453:453)) - (PORT datab (1744:1744:1744) (1831:1831:1831)) - (PORT datac (1431:1431:1431) (1493:1493:1493)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1057:1057:1057) (1115:1115:1115)) - (PORT d[1] (3332:3332:3332) (3598:3598:3598)) - (PORT d[2] (2180:2180:2180) (2297:2297:2297)) - (PORT d[3] (1004:1004:1004) (1059:1059:1059)) - (PORT d[4] (719:719:719) (767:767:767)) - (PORT d[5] (1251:1251:1251) (1322:1322:1322)) - (PORT d[6] (2900:2900:2900) (3050:3050:3050)) - (PORT d[7] (2353:2353:2353) (2464:2464:2464)) - (PORT d[8] (4005:4005:4005) (4249:4249:4249)) - (PORT d[9] (3027:3027:3027) (3125:3125:3125)) - (PORT d[10] (2849:2849:2849) (3047:3047:3047)) - (PORT d[11] (2235:2235:2235) (2437:2437:2437)) - (PORT d[12] (2418:2418:2418) (2498:2498:2498)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1875:1875:1875)) - (PORT d[0] (1374:1374:1374) (1384:1384:1384)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1828:1828:1828) (1920:1920:1920)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2719:2719:2719) (2866:2866:2866)) - (PORT d[1] (1363:1363:1363) (1442:1442:1442)) - (PORT d[2] (3376:3376:3376) (3692:3692:3692)) - (PORT d[3] (2726:2726:2726) (2952:2952:2952)) - (PORT d[4] (2561:2561:2561) (2773:2773:2773)) - (PORT d[5] (1820:1820:1820) (1944:1944:1944)) - (PORT d[6] (2637:2637:2637) (2778:2778:2778)) - (PORT d[7] (3221:3221:3221) (3388:3388:3388)) - (PORT d[8] (1892:1892:1892) (1953:1953:1953)) - (PORT d[9] (4089:4089:4089) (4235:4235:4235)) - (PORT d[10] (1920:1920:1920) (1999:1999:1999)) - (PORT d[11] (2239:2239:2239) (2469:2469:2469)) - (PORT d[12] (3062:3062:3062) (3188:3188:3188)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1763:1763:1763) (1744:1744:1744)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2924:2924:2924) (2955:2955:2955)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3423:3423:3423) (3527:3527:3527)) - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1877:1877:1877) (1996:1996:1996)) - (PORT d[1] (1804:1804:1804) (1928:1928:1928)) - (PORT d[2] (1809:1809:1809) (1887:1887:1887)) - (PORT d[3] (1978:1978:1978) (2151:2151:2151)) - (PORT d[4] (1882:1882:1882) (2016:2016:2016)) - (PORT d[5] (2114:2114:2114) (2191:2191:2191)) - (PORT d[6] (2030:2030:2030) (2109:2109:2109)) - (PORT d[7] (1862:1862:1862) (1936:1936:1936)) - (PORT d[8] (1896:1896:1896) (2033:2033:2033)) - (PORT d[9] (2025:2025:2025) (2102:2102:2102)) - (PORT d[10] (1898:1898:1898) (2004:2004:2004)) - (PORT d[11] (1937:1937:1937) (2003:2003:2003)) - (PORT d[12] (1900:1900:1900) (2016:2016:2016)) - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (750:750:750) (796:796:796)) - (PORT d[1] (3387:3387:3387) (3654:3654:3654)) - (PORT d[2] (1897:1897:1897) (2000:2000:2000)) - (PORT d[3] (1008:1008:1008) (1082:1082:1082)) - (PORT d[4] (3136:3136:3136) (3348:3348:3348)) - (PORT d[5] (951:951:951) (1004:1004:1004)) - (PORT d[6] (2888:2888:2888) (3054:3054:3054)) - (PORT d[7] (2677:2677:2677) (2789:2789:2789)) - (PORT d[8] (984:984:984) (1018:1018:1018)) - (PORT d[9] (2727:2727:2727) (2799:2799:2799)) - (PORT d[10] (2911:2911:2911) (3132:3132:3132)) - (PORT d[11] (2465:2465:2465) (2695:2695:2695)) - (PORT d[12] (2092:2092:2092) (2181:2181:2181)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1877:1877:1877)) - (PORT d[0] (2329:2329:2329) (2272:2272:2272)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1546:1546:1546) (1644:1644:1644)) - (PORT clk (1864:1864:1864) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1703:1703:1703) (1840:1840:1840)) - (PORT d[1] (1728:1728:1728) (1821:1821:1821)) - (PORT d[2] (3631:3631:3631) (3980:3980:3980)) - (PORT d[3] (2731:2731:2731) (2947:2947:2947)) - (PORT d[4] (2593:2593:2593) (2814:2814:2814)) - (PORT d[5] (1783:1783:1783) (1865:1865:1865)) - (PORT d[6] (2579:2579:2579) (2751:2751:2751)) - (PORT d[7] (2984:2984:2984) (3148:3148:3148)) - (PORT d[8] (2062:2062:2062) (2153:2153:2153)) - (PORT d[9] (4058:4058:4058) (4194:4194:4194)) - (PORT d[10] (2224:2224:2224) (2307:2307:2307)) - (PORT d[11] (3010:3010:3010) (3216:3216:3216)) - (PORT d[12] (3036:3036:3036) (3158:3158:3158)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1779:1779:1779) (1768:1768:1768)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1864:1864:1864) (1891:1891:1891)) - (PORT d[0] (2907:2907:2907) (2889:2889:2889)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1819:1819:1819) (1816:1816:1816)) @@ -44156,10 +31811,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (3428:3428:3428) (3539:3539:3539)) + (PORT d[0] (2147:2147:2147) (2193:2193:2193)) (PORT clk (1829:1829:1829) (1822:1822:1822)) ) ) @@ -44169,22 +31824,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1845:1845:1845) (1955:1955:1955)) - (PORT d[1] (1754:1754:1754) (1823:1823:1823)) - (PORT d[2] (1870:1870:1870) (1937:1937:1937)) - (PORT d[3] (1907:1907:1907) (2071:2071:2071)) - (PORT d[4] (1916:1916:1916) (2037:2037:2037)) - (PORT d[5] (2145:2145:2145) (2251:2251:2251)) - (PORT d[6] (1999:1999:1999) (2062:2062:2062)) - (PORT d[7] (1854:1854:1854) (1924:1924:1924)) - (PORT d[8] (2062:2062:2062) (2122:2122:2122)) - (PORT d[9] (1902:1902:1902) (1949:1949:1949)) - (PORT d[10] (1862:1862:1862) (1970:1970:1970)) - (PORT d[11] (1936:1936:1936) (2003:2003:2003)) - (PORT d[12] (1932:1932:1932) (2009:2009:2009)) + (PORT d[0] (4636:4636:4636) (4688:4688:4688)) + (PORT d[1] (4395:4395:4395) (4383:4383:4383)) + (PORT d[2] (4558:4558:4558) (4624:4624:4624)) + (PORT d[3] (4721:4721:4721) (4720:4720:4720)) + (PORT d[4] (4265:4265:4265) (4262:4262:4262)) + (PORT d[5] (4417:4417:4417) (4355:4355:4355)) + (PORT d[6] (4638:4638:4638) (4708:4708:4708)) + (PORT d[7] (4394:4394:4394) (4343:4343:4343)) + (PORT d[8] (4731:4731:4731) (4705:4705:4705)) + (PORT d[9] (4601:4601:4601) (4791:4791:4791)) + (PORT d[10] (4436:4436:4436) (4445:4445:4445)) + (PORT d[11] (4654:4654:4654) (4682:4682:4682)) + (PORT d[12] (4454:4454:4454) (4466:4466:4466)) (PORT clk (1825:1825:1825) (1818:1818:1818)) ) ) @@ -44194,7 +31849,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1829:1829:1829) (1822:1822:1822)) @@ -44203,7 +31858,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) (DELAY (ABSOLUTE (PORT clk (1830:1830:1830) (1823:1823:1823)) @@ -44213,7 +31868,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1830:1830:1830) (1823:1823:1823)) @@ -44223,7 +31878,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1830:1830:1830) (1823:1823:1823)) @@ -44233,7 +31888,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1830:1830:1830) (1823:1823:1823)) @@ -44243,7 +31898,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) (DELAY (ABSOLUTE (PORT clk (1821:1821:1821) (1818:1818:1818)) @@ -44257,13 +31912,494 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector2\~0) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (1183:1183:1183) (1233:1233:1233)) - (PORT datab (298:298:298) (393:393:393)) - (PORT datac (896:896:896) (920:920:920)) - (PORT datad (1713:1713:1713) (1749:1749:1749)) + (PORT datad (1203:1203:1203) (1298:1298:1298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1947:1947:1947)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT asdata (1724:1724:1724) (1774:1774:1774)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (726:726:726)) + (PORT datab (262:262:262) (315:315:315)) + (PORT datac (366:366:366) (405:405:405)) + (PORT datad (1303:1303:1303) (1300:1300:1300)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1513:1513:1513) (1593:1593:1593)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2905:2905:2905) (3002:3002:3002)) + (PORT d[1] (2381:2381:2381) (2621:2621:2621)) + (PORT d[2] (1221:1221:1221) (1275:1275:1275)) + (PORT d[3] (2017:2017:2017) (2080:2080:2080)) + (PORT d[4] (2910:2910:2910) (3179:3179:3179)) + (PORT d[5] (2405:2405:2405) (2631:2631:2631)) + (PORT d[6] (1533:1533:1533) (1608:1608:1608)) + (PORT d[7] (1282:1282:1282) (1365:1365:1365)) + (PORT d[8] (1697:1697:1697) (1794:1794:1794)) + (PORT d[9] (1564:1564:1564) (1639:1639:1639)) + (PORT d[10] (2164:2164:2164) (2311:2311:2311)) + (PORT d[11] (3205:3205:3205) (3345:3345:3345)) + (PORT d[12] (1922:1922:1922) (2027:2027:2027)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2709:2709:2709) (2650:2650:2650)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (3090:3090:3090) (3120:3120:3120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2167:2167:2167) (2208:2208:2208)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4624:4624:4624) (4660:4660:4660)) + (PORT d[1] (4162:4162:4162) (4152:4152:4152)) + (PORT d[2] (4263:4263:4263) (4325:4325:4325)) + (PORT d[3] (4486:4486:4486) (4524:4524:4524)) + (PORT d[4] (4333:4333:4333) (4346:4346:4346)) + (PORT d[5] (4356:4356:4356) (4399:4399:4399)) + (PORT d[6] (4459:4459:4459) (4542:4542:4542)) + (PORT d[7] (4161:4161:4161) (4129:4129:4129)) + (PORT d[8] (4409:4409:4409) (4389:4389:4389)) + (PORT d[9] (4581:4581:4581) (4772:4772:4772)) + (PORT d[10] (4418:4418:4418) (4409:4409:4409)) + (PORT d[11] (4535:4535:4535) (4594:4594:4594)) + (PORT d[12] (4450:4450:4450) (4459:4459:4459)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2533:2533:2533) (2623:2623:2623)) + (PORT d[1] (2220:2220:2220) (2418:2418:2418)) + (PORT d[2] (2325:2325:2325) (2498:2498:2498)) + (PORT d[3] (2178:2178:2178) (2338:2338:2338)) + (PORT d[4] (2896:2896:2896) (3148:3148:3148)) + (PORT d[5] (2277:2277:2277) (2465:2465:2465)) + (PORT d[6] (1866:1866:1866) (1991:1991:1991)) + (PORT d[7] (2226:2226:2226) (2303:2303:2303)) + (PORT d[8] (2742:2742:2742) (2980:2980:2980)) + (PORT d[9] (1744:1744:1744) (1855:1855:1855)) + (PORT d[10] (1754:1754:1754) (1834:1834:1834)) + (PORT d[11] (3116:3116:3116) (3240:3240:3240)) + (PORT d[12] (1285:1285:1285) (1359:1359:1359)) + (PORT clk (1869:1869:1869) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1894:1894:1894)) + (PORT d[0] (2187:2187:2187) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1021:1021:1021)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1348:1348:1348) (1400:1400:1400)) + (PORT datab (276:276:276) (364:364:364)) + (PORT datac (1381:1381:1381) (1421:1421:1421)) + (PORT datad (1657:1657:1657) (1684:1684:1684)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3643:3643:3643) (3885:3885:3885)) + (PORT d[1] (2602:2602:2602) (2837:2837:2837)) + (PORT d[2] (2449:2449:2449) (2542:2542:2542)) + (PORT d[3] (2141:2141:2141) (2296:2296:2296)) + (PORT d[4] (2227:2227:2227) (2405:2405:2405)) + (PORT d[5] (2065:2065:2065) (2249:2249:2249)) + (PORT d[6] (1926:1926:1926) (2066:2066:2066)) + (PORT d[7] (1993:1993:1993) (2107:2107:2107)) + (PORT d[8] (2992:2992:2992) (3233:3233:3233)) + (PORT d[9] (2617:2617:2617) (2763:2763:2763)) + (PORT d[10] (4742:4742:4742) (4968:4968:4968)) + (PORT d[11] (2083:2083:2083) (2222:2222:2222)) + (PORT d[12] (2446:2446:2446) (2592:2592:2592)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (3176:3176:3176) (3088:3088:3088)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1292:1292:1292)) + (PORT datab (1157:1157:1157) (1165:1165:1165)) + (PORT datac (1614:1614:1614) (1636:1636:1636)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (1434:1434:1434) (1498:1498:1498)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (624:624:624) (685:685:685)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -44273,15 +32409,38 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector2\~1) + (INSTANCE D\[6\]\~111) (DELAY (ABSOLUTE - (PORT dataa (1209:1209:1209) (1254:1254:1254)) - (PORT datab (298:298:298) (392:392:392)) - (PORT datac (1450:1450:1450) (1485:1485:1485)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (642:642:642) (683:683:683)) + (PORT datab (2010:2010:2010) (2117:2117:2117)) + (PORT datac (918:918:918) (1000:1000:1000)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE raw_loader_in\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (967:967:967)) + (PORT datac (1544:1544:1544) (1682:1682:1682)) + (PORT datad (1984:1984:1984) (2079:2079:2079)) + (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44289,15 +32448,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~41) + (INSTANCE D\[6\]\~100) (DELAY (ABSOLUTE - (PORT dataa (947:947:947) (997:997:997)) - (PORT datab (973:973:973) (1025:1025:1025)) - (PORT datac (1220:1220:1220) (1227:1227:1227)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (952:952:952) (1002:1002:1002)) + (PORT datab (1379:1379:1379) (1383:1383:1383)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44305,15 +32464,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~42) + (INSTANCE D\[6\]\~101) (DELAY (ABSOLUTE - (PORT dataa (1832:1832:1832) (1928:1928:1928)) - (PORT datab (2143:2143:2143) (2278:2278:2278)) - (PORT datac (3268:3268:3268) (3487:3487:3487)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (947:947:947) (995:995:995)) + (PORT datab (894:894:894) (965:965:965)) + (PORT datac (1645:1645:1645) (1669:1669:1669)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44321,45 +32480,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~48) + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) (DELAY (ABSOLUTE - (PORT dataa (695:695:695) (718:718:718)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (1323:1323:1323) (1333:1333:1333)) - (PORT datad (700:700:700) (766:766:766)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (749:749:749)) - (PORT datab (1199:1199:1199) (1289:1289:1289)) - (PORT datac (256:256:256) (334:334:334)) - (PORT datad (565:565:565) (577:577:577)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (1341:1341:1341) (1426:1426:1426)) - (PORT datab (227:227:227) (269:269:269)) - (PORT datac (1231:1231:1231) (1319:1319:1319)) - (PORT datad (876:876:876) (907:907:907)) + (PORT dataa (275:275:275) (336:336:336)) + (PORT datab (1389:1389:1389) (1429:1429:1429)) + (PORT datac (938:938:938) (1004:1004:1004)) + (PORT datad (830:830:830) (833:833:833)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -44368,13 +32495,45 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[0\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) (DELAY (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) + (PORT dataa (1684:1684:1684) (1826:1826:1826)) + (PORT datab (754:754:754) (857:857:857)) + (PORT datac (961:961:961) (1023:1023:1023)) + (PORT datad (1204:1204:1204) (1263:1263:1263)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (1041:1041:1041)) + (PORT datab (973:973:973) (1033:1033:1033)) + (PORT datac (961:961:961) (1024:1024:1024)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) + (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -44385,43 +32544,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~14) + (INSTANCE z80_\|bus_control_\|db\[6\]\~9) (DELAY (ABSOLUTE - (PORT dataa (691:691:691) (724:724:724)) - (PORT datac (926:926:926) (968:968:968)) - (PORT datad (1019:1019:1019) (1049:1049:1049)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1317:1317:1317)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (609:609:609) (655:655:655)) - (PORT datad (812:812:812) (820:820:820)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (1178:1178:1178) (1226:1226:1226)) + (PORT datac (224:224:224) (273:273:273)) + (PORT datad (210:210:210) (243:243:243)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[0\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) + (PORT datad (195:195:195) (219:219:219)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1191:1191:1191)) + (PORT datab (909:909:909) (972:972:972)) + (PORT datac (661:661:661) (712:712:712)) + (PORT datad (375:375:375) (392:392:392)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) + (PORT clrn (1577:1577:1577) (1557:1557:1557)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -44433,13 +32604,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) + (INSTANCE z80_\|pla_decode_\|Equal41\~0) (DELAY (ABSOLUTE - (PORT datab (2147:2147:2147) (2201:2201:2201)) - (PORT datac (1401:1401:1401) (1478:1478:1478)) - (PORT datad (1373:1373:1373) (1416:1416:1416)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT datac (1703:1703:1703) (1754:1754:1754)) + (PORT datad (1223:1223:1223) (1322:1322:1322)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44447,15 +32616,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) + (INSTANCE z80_\|pla_decode_\|Equal41\~1) (DELAY (ABSOLUTE - (PORT dataa (1244:1244:1244) (1350:1350:1350)) - (PORT datab (746:746:746) (828:828:828)) - (PORT datac (1316:1316:1316) (1365:1365:1365)) - (PORT datad (820:820:820) (852:852:852)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (1499:1499:1499) (1573:1573:1573)) + (PORT datab (2298:2298:2298) (2366:2366:2366)) + (PORT datac (2132:2132:2132) (2282:2282:2282)) + (PORT datad (1454:1454:1454) (1538:1538:1538)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (502:502:502)) + (PORT datab (1649:1649:1649) (1644:1644:1644)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1095:1095:1095) (1127:1127:1127)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (1962:1962:1962) (2070:2070:2070)) + (PORT datab (1125:1125:1125) (1133:1133:1133)) + (PORT datac (2059:2059:2059) (2181:2181:2181)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44463,61 +32664,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1363:1363:1363) (1373:1373:1373)) - (PORT datab (1624:1624:1624) (1610:1610:1610)) - (PORT datac (844:844:844) (876:876:876)) - (PORT datad (642:642:642) (674:674:674)) + (PORT dataa (1180:1180:1180) (1214:1214:1214)) + (PORT datab (292:292:292) (354:354:354)) + (PORT datac (259:259:259) (316:316:316)) + (PORT datad (245:245:245) (290:290:290)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) - (DELAY - (ABSOLUTE - (PORT datab (620:620:620) (671:671:671)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (560:560:560) (570:570:570)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (915:915:915)) - (PORT datab (649:649:649) (667:667:667)) - (PORT datac (845:845:845) (862:862:862)) - (PORT datad (823:823:823) (824:824:824)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (269:269:269)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (831:831:831) (890:890:890)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1202:1202:1202)) + (PORT datab (1172:1172:1172) (1221:1221:1221)) + (PORT datac (419:419:419) (491:491:491)) + (PORT datad (660:660:660) (723:723:723)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (1002:1002:1002)) + (PORT datac (1667:1667:1667) (1748:1748:1748)) + (PORT datad (900:900:900) (923:923:923)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (201:201:201) (240:240:240)) + (PORT datac (891:891:891) (913:913:913)) + (PORT datad (244:244:244) (286:286:286)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (390:390:390)) + (PORT datab (631:631:631) (659:659:659)) + (PORT datac (1160:1160:1160) (1204:1204:1204)) + (PORT datad (606:606:606) (623:623:623)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44525,13 +32740,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (INSTANCE z80_\|alu_\|db_high\[1\]\~20) (DELAY (ABSOLUTE - (PORT datab (1085:1085:1085) (1092:1092:1092)) - (PORT datac (1008:1008:1008) (1033:1033:1033)) - (PORT datad (215:215:215) (249:249:249)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (999:999:999) (1032:1032:1032)) + (PORT datac (582:582:582) (614:614:614)) + (PORT datad (221:221:221) (263:263:263)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44539,16 +32756,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~1) + (INSTANCE z80_\|alu_\|db\[5\]\~24) (DELAY (ABSOLUTE - (PORT dataa (1246:1246:1246) (1282:1282:1282)) - (PORT datab (668:668:668) (700:700:700)) - (PORT datac (1045:1045:1045) (1120:1120:1120)) - (PORT datad (212:212:212) (245:245:245)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1300:1300:1300) (1351:1351:1351)) + (PORT datab (940:940:940) (958:958:958)) + (PORT datac (1822:1822:1822) (1884:1884:1884)) + (PORT datad (931:931:931) (981:981:981)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (673:673:673)) + (PORT datab (255:255:255) (313:313:313)) + (PORT datac (175:175:175) (209:209:209)) + (PORT datad (945:945:945) (988:988:988)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (501:501:501)) + (PORT datab (1351:1351:1351) (1413:1413:1413)) + (PORT datac (1147:1147:1147) (1181:1181:1181)) + (PORT datad (1196:1196:1196) (1243:1243:1243)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -44558,10 +32807,10 @@ (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) (DELAY (ABSOLUTE - (PORT dataa (424:424:424) (475:475:475)) - (PORT datab (888:888:888) (902:902:902)) - (PORT datac (845:845:845) (884:884:884)) - (PORT datad (232:232:232) (267:267:267)) + (PORT dataa (556:556:556) (578:578:578)) + (PORT datab (623:623:623) (651:651:651)) + (PORT datac (663:663:663) (695:695:695)) + (PORT datad (679:679:679) (697:697:697)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -44574,7 +32823,7 @@ (INSTANCE z80_\|alu_flags_\|flags_yf) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1548:1548:1548)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -44587,47 +32836,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~27) + (INSTANCE z80_\|alu_control_\|db\[5\]\~13) (DELAY (ABSOLUTE - (PORT dataa (1342:1342:1342) (1406:1406:1406)) - (PORT datab (639:639:639) (699:699:699)) - (PORT datac (632:632:632) (679:679:679)) - (PORT datad (679:679:679) (760:760:760)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (644:644:644) (702:702:702)) + (PORT datab (900:900:900) (949:949:949)) + (PORT datac (666:666:666) (693:693:693)) + (PORT datad (888:888:888) (905:905:905)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~28) + (INSTANCE z80_\|alu_control_\|db\[5\]\~14) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (270:270:270)) - (PORT datab (635:635:635) (654:654:654)) - (PORT datac (865:865:865) (874:874:874)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (675:675:675) (703:703:703)) - (PORT datac (812:812:812) (848:848:848)) - (PORT datad (618:618:618) (669:669:669)) + (PORT dataa (969:969:969) (987:987:987)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (948:948:948) (982:982:982)) + (PORT datad (864:864:864) (880:880:880)) (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44635,13 +32868,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~68) + (INSTANCE z80_\|alu_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT dataa (2078:2078:2078) (2105:2105:2105)) - (PORT datab (1531:1531:1531) (1589:1589:1589)) - (PORT datac (3031:3031:3031) (3276:3276:3276)) - (PORT datad (2409:2409:2409) (2559:2559:2559)) + (PORT dataa (685:685:685) (717:717:717)) + (PORT datab (1197:1197:1197) (1212:1212:1212)) + (PORT datac (1119:1119:1119) (1150:1150:1150)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (1749:1749:1749) (1858:1858:1858)) + (PORT datab (1231:1231:1231) (1298:1298:1298)) + (PORT datac (1559:1559:1559) (1700:1700:1700)) + (PORT datad (1126:1126:1126) (1171:1171:1171)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -44649,12 +32898,487 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1190:1190:1190) (1230:1230:1230)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3686:3686:3686) (3900:3900:3900)) + (PORT d[1] (1735:1735:1735) (1904:1904:1904)) + (PORT d[2] (3045:3045:3045) (3164:3164:3164)) + (PORT d[3] (1901:1901:1901) (2003:2003:2003)) + (PORT d[4] (2206:2206:2206) (2342:2342:2342)) + (PORT d[5] (2677:2677:2677) (2865:2865:2865)) + (PORT d[6] (2060:2060:2060) (2133:2133:2133)) + (PORT d[7] (2769:2769:2769) (2894:2894:2894)) + (PORT d[8] (3033:3033:3033) (3241:3241:3241)) + (PORT d[9] (2831:2831:2831) (2926:2926:2926)) + (PORT d[10] (3516:3516:3516) (3751:3751:3751)) + (PORT d[11] (1807:1807:1807) (1907:1907:1907)) + (PORT d[12] (2081:2081:2081) (2168:2168:2168)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1939:1939:1939) (1956:1956:1956)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (2676:2676:2676) (2715:2715:2715)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1180:1180:1180) (1209:1209:1209)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3984:3984:3984) (4216:4216:4216)) + (PORT d[1] (1704:1704:1704) (1855:1855:1855)) + (PORT d[2] (3307:3307:3307) (3443:3443:3443)) + (PORT d[3] (1880:1880:1880) (1997:1997:1997)) + (PORT d[4] (1863:1863:1863) (1963:1963:1963)) + (PORT d[5] (1643:1643:1643) (1769:1769:1769)) + (PORT d[6] (1761:1761:1761) (1817:1817:1817)) + (PORT d[7] (3056:3056:3056) (3189:3189:3189)) + (PORT d[8] (3324:3324:3324) (3551:3551:3551)) + (PORT d[9] (2869:2869:2869) (2985:2985:2985)) + (PORT d[10] (3454:3454:3454) (3652:3652:3652)) + (PORT d[11] (1540:1540:1540) (1618:1618:1618)) + (PORT d[12] (1726:1726:1726) (1787:1787:1787)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1932:1932:1932) (1890:1890:1890)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (2406:2406:2406) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1218:1218:1218) (1268:1268:1268)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3686:3686:3686) (3901:3901:3901)) + (PORT d[1] (1692:1692:1692) (1858:1858:1858)) + (PORT d[2] (2977:2977:2977) (3118:3118:3118)) + (PORT d[3] (2124:2124:2124) (2230:2230:2230)) + (PORT d[4] (2237:2237:2237) (2352:2352:2352)) + (PORT d[5] (2684:2684:2684) (2875:2875:2875)) + (PORT d[6] (1801:1801:1801) (1880:1880:1880)) + (PORT d[7] (2772:2772:2772) (2901:2901:2901)) + (PORT d[8] (3346:3346:3346) (3575:3575:3575)) + (PORT d[9] (2889:2889:2889) (3004:3004:3004)) + (PORT d[10] (3484:3484:3484) (3709:3709:3709)) + (PORT d[11] (1816:1816:1816) (1924:1924:1924)) + (PORT d[12] (2023:2023:2023) (2090:2090:2090)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1889:1889:1889) (1883:1883:1883)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (2482:2482:2482) (2488:2488:2488)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1446:1446:1446) (1499:1499:1499)) + (PORT datab (1431:1431:1431) (1517:1517:1517)) + (PORT datac (1141:1141:1141) (1132:1132:1132)) + (PORT datad (1111:1111:1111) (1136:1136:1136)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1872:1872:1872) (1991:1991:1991)) + (PORT d[0] (1272:1272:1272) (1326:1326:1326)) (PORT clk (1855:1855:1855) (1883:1883:1883)) ) ) @@ -44667,19 +33391,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3467:3467:3467) (3745:3745:3745)) - (PORT d[1] (2402:2402:2402) (2573:2573:2573)) - (PORT d[2] (2265:2265:2265) (2486:2486:2486)) - (PORT d[3] (3297:3297:3297) (3609:3609:3609)) - (PORT d[4] (2871:2871:2871) (3081:3081:3081)) - (PORT d[5] (3662:3662:3662) (3924:3924:3924)) - (PORT d[6] (1692:1692:1692) (1738:1738:1738)) - (PORT d[7] (3122:3122:3122) (3233:3233:3233)) - (PORT d[8] (2503:2503:2503) (2661:2661:2661)) - (PORT d[9] (2575:2575:2575) (2676:2676:2676)) - (PORT d[10] (2638:2638:2638) (2792:2792:2792)) - (PORT d[11] (1527:1527:1527) (1657:1657:1657)) - (PORT d[12] (2496:2496:2496) (2590:2590:2590)) + (PORT d[0] (2887:2887:2887) (3004:3004:3004)) + (PORT d[1] (2662:2662:2662) (2916:2916:2916)) + (PORT d[2] (1218:1218:1218) (1257:1257:1257)) + (PORT d[3] (1701:1701:1701) (1750:1750:1750)) + (PORT d[4] (2885:2885:2885) (3119:3119:3119)) + (PORT d[5] (2382:2382:2382) (2607:2607:2607)) + (PORT d[6] (1263:1263:1263) (1339:1339:1339)) + (PORT d[7] (1323:1323:1323) (1404:1404:1404)) + (PORT d[8] (1739:1739:1739) (1814:1814:1814)) + (PORT d[9] (1262:1262:1262) (1335:1335:1335)) + (PORT d[10] (2409:2409:2409) (2560:2560:2560)) + (PORT d[11] (3166:3166:3166) (3381:3381:3381)) + (PORT d[12] (2205:2205:2205) (2307:2307:2307)) (PORT clk (1852:1852:1852) (1879:1879:1879)) ) ) @@ -44692,7 +33416,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2008:2008:2008) (1989:1989:1989)) + (PORT d[0] (1501:1501:1501) (1496:1496:1496)) (PORT clk (1852:1852:1852) (1879:1879:1879)) ) ) @@ -44706,7 +33430,7 @@ (DELAY (ABSOLUTE (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (3416:3416:3416) (3478:3478:3478)) + (PORT d[0] (2128:2128:2128) (2120:2120:2120)) ) ) ) @@ -44802,601 +33526,29 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2240:2240:2240) (2402:2402:2402)) - (PORT clk (1844:1844:1844) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2233:2233:2233) (2400:2400:2400)) - (PORT d[1] (2732:2732:2732) (2931:2931:2931)) - (PORT d[2] (4344:4344:4344) (4589:4589:4589)) - (PORT d[3] (3583:3583:3583) (3920:3920:3920)) - (PORT d[4] (1582:1582:1582) (1706:1706:1706)) - (PORT d[5] (4291:4291:4291) (4604:4604:4604)) - (PORT d[6] (2306:2306:2306) (2432:2432:2432)) - (PORT d[7] (2514:2514:2514) (2599:2599:2599)) - (PORT d[8] (3671:3671:3671) (3890:3890:3890)) - (PORT d[9] (2215:2215:2215) (2314:2314:2314)) - (PORT d[10] (1588:1588:1588) (1677:1677:1677)) - (PORT d[11] (1555:1555:1555) (1689:1689:1689)) - (PORT d[12] (1907:1907:1907) (1966:1966:1966)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2603:2603:2603) (2611:2611:2611)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (PORT d[0] (2332:2332:2332) (2359:2359:2359)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1804:1804:1804) (1832:1832:1832)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2843:2843:2843) (2980:2980:2980)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3108:3108:3108) (3310:3310:3310)) - (PORT d[1] (1731:1731:1731) (1868:1868:1868)) - (PORT d[2] (2866:2866:2866) (3091:3091:3091)) - (PORT d[3] (2300:2300:2300) (2508:2508:2508)) - (PORT d[4] (2242:2242:2242) (2408:2408:2408)) - (PORT d[5] (2741:2741:2741) (2938:2938:2938)) - (PORT d[6] (1992:1992:1992) (2098:2098:2098)) - (PORT d[7] (4304:4304:4304) (4466:4466:4466)) - (PORT d[8] (2436:2436:2436) (2597:2597:2597)) - (PORT d[9] (2798:2798:2798) (2942:2942:2942)) - (PORT d[10] (1927:1927:1927) (2075:2075:2075)) - (PORT d[11] (1917:1917:1917) (2087:2087:2087)) - (PORT d[12] (3449:3449:3449) (3586:3586:3586)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1980:1980:1980) (2014:2014:2014)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (2673:2673:2673) (2735:2735:2735)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1844:1844:1844)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1008:1008:1008)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1008:1008:1008)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2141:2141:2141) (2269:2269:2269)) - (PORT clk (1868:1868:1868) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2720:2720:2720) (2880:2880:2880)) - (PORT d[1] (1602:1602:1602) (1675:1675:1675)) - (PORT d[2] (3072:3072:3072) (3375:3375:3375)) - (PORT d[3] (2590:2590:2590) (2797:2797:2797)) - (PORT d[4] (2311:2311:2311) (2523:2523:2523)) - (PORT d[5] (2345:2345:2345) (2483:2483:2483)) - (PORT d[6] (2314:2314:2314) (2461:2461:2461)) - (PORT d[7] (2712:2712:2712) (2885:2885:2885)) - (PORT d[8] (3028:3028:3028) (3224:3224:3224)) - (PORT d[9] (3544:3544:3544) (3640:3640:3640)) - (PORT d[10] (2567:2567:2567) (2756:2756:2756)) - (PORT d[11] (2775:2775:2775) (2996:2996:2996)) - (PORT d[12] (3594:3594:3594) (3731:3731:3731)) - (PORT clk (1865:1865:1865) (1890:1890:1890)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2041:2041:2041) (2077:2077:2077)) - (PORT clk (1865:1865:1865) (1890:1890:1890)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1868:1868:1868) (1894:1894:1894)) - (PORT d[0] (2499:2499:2499) (2501:2501:2501)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1828:1828:1828) (1853:1853:1853)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1013:1013:1013) (1016:1016:1016)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1014:1014:1014) (1017:1017:1017)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1014:1014:1014) (1017:1017:1017)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1014:1014:1014) (1017:1017:1017)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) (DELAY (ABSOLUTE - (PORT dataa (2003:2003:2003) (2082:2082:2082)) - (PORT datab (1198:1198:1198) (1282:1282:1282)) - (PORT datac (2200:2200:2200) (2281:2281:2281)) - (PORT datad (305:305:305) (411:411:411)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1130:1130:1130) (1175:1175:1175)) + (PORT datab (1704:1704:1704) (1781:1781:1781)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1426:1426:1426) (1482:1482:1482)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (955:955:955)) - (PORT datab (943:943:943) (970:970:970)) - (PORT datac (1159:1159:1159) (1237:1237:1237)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1357:1357:1357) (1435:1435:1435)) - (PORT d[1] (2822:2822:2822) (3106:3106:3106)) - (PORT d[2] (1988:1988:1988) (2120:2120:2120)) - (PORT d[3] (404:404:404) (434:434:434)) - (PORT d[4] (655:655:655) (679:679:679)) - (PORT d[5] (1546:1546:1546) (1644:1644:1644)) - (PORT d[6] (2947:2947:2947) (3107:3107:3107)) - (PORT d[7] (2315:2315:2315) (2423:2423:2423)) - (PORT d[8] (4005:4005:4005) (4246:4246:4246)) - (PORT d[9] (910:910:910) (914:914:914)) - (PORT d[10] (2299:2299:2299) (2476:2476:2476)) - (PORT d[11] (2222:2222:2222) (2438:2438:2438)) - (PORT d[12] (1107:1107:1107) (1112:1112:1112)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (1700:1700:1700) (1735:1735:1735)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1581:1581:1581) (1671:1671:1671)) - (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (1607:1607:1607) (1720:1720:1720)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) ) ) (TIMINGCHECK @@ -45408,20 +33560,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1377:1377:1377) (1490:1490:1490)) - (PORT d[1] (2047:2047:2047) (2146:2146:2146)) - (PORT d[2] (2140:2140:2140) (2247:2247:2247)) - (PORT d[3] (3064:3064:3064) (3285:3285:3285)) - (PORT d[4] (2586:2586:2586) (2808:2808:2808)) - (PORT d[5] (1550:1550:1550) (1656:1656:1656)) - (PORT d[6] (2560:2560:2560) (2711:2711:2711)) - (PORT d[7] (2705:2705:2705) (2880:2880:2880)) - (PORT d[8] (1784:1784:1784) (1878:1878:1878)) - (PORT d[9] (4368:4368:4368) (4512:4512:4512)) - (PORT d[10] (1908:1908:1908) (1970:1970:1970)) - (PORT d[11] (3582:3582:3582) (3824:3824:3824)) - (PORT d[12] (2698:2698:2698) (2834:2834:2834)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (3186:3186:3186) (3300:3300:3300)) + (PORT d[1] (2007:2007:2007) (2188:2188:2188)) + (PORT d[2] (2193:2193:2193) (2290:2290:2290)) + (PORT d[3] (1861:1861:1861) (1989:1989:1989)) + (PORT d[4] (2485:2485:2485) (2606:2606:2606)) + (PORT d[5] (2236:2236:2236) (2402:2402:2402)) + (PORT d[6] (1711:1711:1711) (1755:1755:1755)) + (PORT d[7] (1687:1687:1687) (1776:1776:1776)) + (PORT d[8] (2608:2608:2608) (2791:2791:2791)) + (PORT d[9] (1955:1955:1955) (2077:2077:2077)) + (PORT d[10] (2011:2011:2011) (2111:2111:2111)) + (PORT d[11] (2425:2425:2425) (2555:2555:2555)) + (PORT d[12] (2552:2552:2552) (2625:2625:2625)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) ) ) (TIMINGCHECK @@ -45433,8 +33585,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1520:1520:1520) (1502:1502:1502)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (2563:2563:2563) (2536:2536:2536)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) ) ) (TIMINGCHECK @@ -45446,8 +33598,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (PORT d[0] (2914:2914:2914) (2928:2928:2928)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (PORT d[0] (3968:3968:3968) (4054:4054:4054)) ) ) ) @@ -45456,7 +33608,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -45466,7 +33618,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -45476,7 +33628,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -45486,7 +33638,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -45496,7 +33648,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1808:1808:1808) (1806:1806:1806)) + (PORT clk (1807:1807:1807) (1805:1805:1805)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -45510,8 +33662,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (3115:3115:3115) (3204:3204:3204)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) + (PORT d[0] (1738:1738:1738) (1727:1727:1727)) + (PORT clk (1817:1817:1817) (1811:1811:1811)) ) ) (TIMINGCHECK @@ -45523,20 +33675,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1862:1862:1862) (1985:1985:1985)) - (PORT d[1] (1922:1922:1922) (2028:2028:2028)) - (PORT d[2] (1880:1880:1880) (1998:1998:1998)) - (PORT d[3] (1835:1835:1835) (1959:1959:1959)) - (PORT d[4] (2160:2160:2160) (2252:2252:2252)) - (PORT d[5] (2115:2115:2115) (2201:2201:2201)) - (PORT d[6] (1788:1788:1788) (1890:1890:1890)) - (PORT d[7] (1904:1904:1904) (2023:2023:2023)) - (PORT d[8] (1919:1919:1919) (2043:2043:2043)) - (PORT d[9] (1950:1950:1950) (1997:1997:1997)) - (PORT d[10] (1889:1889:1889) (1990:1990:1990)) - (PORT d[11] (2026:2026:2026) (2123:2123:2123)) - (PORT d[12] (1894:1894:1894) (2005:2005:2005)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) + (PORT d[0] (4391:4391:4391) (4458:4458:4458)) + (PORT d[1] (4215:4215:4215) (4261:4261:4261)) + (PORT d[2] (4322:4322:4322) (4388:4388:4388)) + (PORT d[3] (4683:4683:4683) (4718:4718:4718)) + (PORT d[4] (4355:4355:4355) (4366:4366:4366)) + (PORT d[5] (4618:4618:4618) (4672:4672:4672)) + (PORT d[6] (4745:4745:4745) (4781:4781:4781)) + (PORT d[7] (4330:4330:4330) (4399:4399:4399)) + (PORT d[8] (4420:4420:4420) (4455:4455:4455)) + (PORT d[9] (4477:4477:4477) (4721:4721:4721)) + (PORT d[10] (4604:4604:4604) (4600:4600:4600)) + (PORT d[11] (4406:4406:4406) (4437:4437:4437)) + (PORT d[12] (4503:4503:4503) (4638:4638:4638)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) ) ) (TIMINGCHECK @@ -45548,7 +33700,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) + (PORT clk (1817:1817:1817) (1811:1811:1811)) ) ) ) @@ -45557,7 +33709,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -45567,7 +33719,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) ) ) ) @@ -45576,7 +33728,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -45586,7 +33738,104 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2857:2857:2857) (2972:2972:2972)) + (PORT d[1] (1730:1730:1730) (1897:1897:1897)) + (PORT d[2] (1950:1950:1950) (2070:2070:2070)) + (PORT d[3] (1897:1897:1897) (2023:2023:2023)) + (PORT d[4] (2739:2739:2739) (2895:2895:2895)) + (PORT d[5] (2232:2232:2232) (2412:2412:2412)) + (PORT d[6] (1964:1964:1964) (2031:2031:2031)) + (PORT d[7] (2136:2136:2136) (2268:2268:2268)) + (PORT d[8] (2383:2383:2383) (2561:2561:2561)) + (PORT d[9] (1973:1973:1973) (2079:2079:2079)) + (PORT d[10] (1681:1681:1681) (1740:1740:1740)) + (PORT d[11] (2036:2036:2036) (2101:2101:2101)) + (PORT d[12] (2509:2509:2509) (2578:2578:2578)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1882:1882:1882)) + (PORT d[0] (2716:2716:2716) (2794:2794:2794)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1009:1009:1009)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -45596,20 +33845,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1067:1067:1067) (1136:1136:1136)) - (PORT d[1] (3088:3088:3088) (3354:3354:3354)) - (PORT d[2] (1617:1617:1617) (1725:1725:1725)) - (PORT d[3] (731:731:731) (787:787:787)) - (PORT d[4] (954:954:954) (1000:1000:1000)) - (PORT d[5] (1258:1258:1258) (1337:1337:1337)) - (PORT d[6] (2620:2620:2620) (2771:2771:2771)) - (PORT d[7] (2318:2318:2318) (2444:2444:2444)) - (PORT d[8] (3182:3182:3182) (3425:3425:3425)) - (PORT d[9] (2995:2995:2995) (3074:3074:3074)) - (PORT d[10] (2620:2620:2620) (2823:2823:2823)) - (PORT d[11] (2195:2195:2195) (2412:2412:2412)) - (PORT d[12] (2418:2418:2418) (2498:2498:2498)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (3922:3922:3922) (4160:4160:4160)) + (PORT d[1] (2875:2875:2875) (3108:3108:3108)) + (PORT d[2] (2719:2719:2719) (2815:2815:2815)) + (PORT d[3] (2274:2274:2274) (2436:2436:2436)) + (PORT d[4] (2511:2511:2511) (2691:2691:2691)) + (PORT d[5] (2520:2520:2520) (2696:2696:2696)) + (PORT d[6] (1898:1898:1898) (2018:2018:2018)) + (PORT d[7] (2284:2284:2284) (2398:2398:2398)) + (PORT d[8] (3090:3090:3090) (3363:3363:3363)) + (PORT d[9] (2691:2691:2691) (2835:2835:2835)) + (PORT d[10] (4531:4531:4531) (4774:4774:4774)) + (PORT d[11] (1925:1925:1925) (2083:2083:2083)) + (PORT d[12] (2422:2422:2422) (2553:2553:2553)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -45621,1802 +33870,14 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1877:1877:1877)) - (PORT d[0] (2000:2000:2000) (1970:1970:1970)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (3644:3644:3644) (3567:3567:3567)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1567:1567:1567) (1645:1645:1645)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1398:1398:1398) (1514:1514:1514)) - (PORT d[1] (1369:1369:1369) (1449:1449:1449)) - (PORT d[2] (1873:1873:1873) (1979:1979:1979)) - (PORT d[3] (3065:3065:3065) (3286:3286:3286)) - (PORT d[4] (2873:2873:2873) (3117:3117:3117)) - (PORT d[5] (1501:1501:1501) (1584:1584:1584)) - (PORT d[6] (2596:2596:2596) (2749:2749:2749)) - (PORT d[7] (2678:2678:2678) (2847:2847:2847)) - (PORT d[8] (1638:1638:1638) (1702:1702:1702)) - (PORT d[9] (4352:4352:4352) (4493:4493:4493)) - (PORT d[10] (1927:1927:1927) (1983:1983:1983)) - (PORT d[11] (3583:3583:3583) (3825:3825:3825)) - (PORT d[12] (2720:2720:2720) (2857:2857:2857)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1498:1498:1498) (1468:1468:1468)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (2122:2122:2122) (2089:2089:2089)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1808:1808:1808)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3114:3114:3114) (3202:3202:3202)) - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1869:1869:1869) (1993:1993:1993)) - (PORT d[1] (1911:1911:1911) (1998:1998:1998)) - (PORT d[2] (1838:1838:1838) (1948:1948:1948)) - (PORT d[3] (1841:1841:1841) (1955:1955:1955)) - (PORT d[4] (1862:1862:1862) (1947:1947:1947)) - (PORT d[5] (1778:1778:1778) (1863:1863:1863)) - (PORT d[6] (1805:1805:1805) (1932:1932:1932)) - (PORT d[7] (1906:1906:1906) (2042:2042:2042)) - (PORT d[8] (1886:1886:1886) (2004:2004:2004)) - (PORT d[9] (2049:2049:2049) (2132:2132:2132)) - (PORT d[10] (1899:1899:1899) (2003:2003:2003)) - (PORT d[11] (2004:2004:2004) (2070:2070:2070)) - (PORT d[12] (1900:1900:1900) (1951:1951:1951)) - (PORT clk (1816:1816:1816) (1810:1810:1810)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (729:729:729)) - (PORT datab (980:980:980) (1046:1046:1046)) - (PORT datac (981:981:981) (1079:1079:1079)) - (PORT datad (1494:1494:1494) (1560:1560:1560)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1008:1008:1008) (1118:1118:1118)) - (PORT datab (990:990:990) (1033:1033:1033)) - (PORT datac (1405:1405:1405) (1485:1485:1485)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1054:1054:1054)) - (PORT datab (1203:1203:1203) (1265:1265:1265)) - (PORT datac (2674:2674:2674) (2864:2864:2864)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (963:963:963)) - (PORT datab (1209:1209:1209) (1309:1309:1309)) - (PORT datac (1393:1393:1393) (1460:1460:1460)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~80) - (DELAY - (ABSOLUTE - (PORT datac (920:920:920) (971:971:971)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (1345:1345:1345) (1423:1423:1423)) - (PORT datab (1270:1270:1270) (1356:1356:1356)) - (PORT datac (856:856:856) (891:891:891)) - (PORT datad (882:882:882) (932:932:932)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1057:1057:1057) (1093:1093:1093)) - (PORT datab (1130:1130:1130) (1180:1180:1180)) - (PORT datad (643:643:643) (672:672:672)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1317:1317:1317)) - (PORT datab (849:849:849) (874:874:874)) - (PORT datac (609:609:609) (655:655:655)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2309:2309:2309) (2384:2384:2384)) - (PORT datab (1876:1876:1876) (1946:1946:1946)) - (PORT datac (2012:2012:2012) (2093:2093:2093)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1470:1470:1470)) - (PORT datab (926:926:926) (979:979:979)) - (PORT datad (1299:1299:1299) (1369:1369:1369)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1042:1042:1042)) - (PORT datab (658:658:658) (709:709:709)) - (PORT datac (1161:1161:1161) (1181:1181:1181)) - (PORT datad (812:812:812) (831:831:831)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (1003:1003:1003)) - (PORT datab (692:692:692) (741:741:741)) - (PORT datac (814:814:814) (883:883:883)) - (PORT datad (595:595:595) (611:611:611)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (829:829:829)) - (PORT datab (654:654:654) (702:702:702)) - (PORT datac (847:847:847) (877:877:877)) - (PORT datad (1016:1016:1016) (1021:1021:1021)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (386:386:386)) - (PORT datab (378:378:378) (403:403:403)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (848:848:848) (859:859:859)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (710:710:710)) - (PORT datab (1037:1037:1037) (1110:1110:1110)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (526:526:526) (544:544:544)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1393:1393:1393)) - (PORT datab (639:639:639) (679:679:679)) - (PORT datac (1458:1458:1458) (1490:1490:1490)) - (PORT datad (931:931:931) (961:961:961)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (871:871:871)) - (PORT datab (701:701:701) (749:749:749)) - (PORT datac (1784:1784:1784) (1776:1776:1776)) - (PORT datad (1065:1065:1065) (1110:1110:1110)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (933:933:933)) - (PORT datab (1110:1110:1110) (1130:1130:1130)) - (PORT datac (394:394:394) (434:434:434)) - (PORT datad (649:649:649) (663:663:663)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1237:1237:1237) (1240:1240:1240)) - (PORT datab (1110:1110:1110) (1127:1127:1127)) - (PORT datac (1570:1570:1570) (1594:1594:1594)) - (PORT datad (1120:1120:1120) (1149:1149:1149)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (184:184:184) (214:214:214)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1036:1036:1036)) - (PORT datab (666:666:666) (723:723:723)) - (PORT datac (1566:1566:1566) (1597:1597:1597)) - (PORT datad (917:917:917) (1021:1021:1021)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (776:776:776)) - (PORT datab (579:579:579) (621:621:621)) - (PORT datac (1566:1566:1566) (1599:1599:1599)) - (PORT datad (633:633:633) (686:686:686)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (644:644:644) (675:675:675)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1244:1244:1244) (1351:1351:1351)) - (PORT datab (610:610:610) (644:644:644)) - (PORT datac (1314:1314:1314) (1364:1364:1364)) - (PORT datad (821:821:821) (854:854:854)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (600:600:600)) - (PORT datab (1147:1147:1147) (1203:1203:1203)) - (PORT datac (814:814:814) (852:852:852)) - (PORT datad (563:563:563) (570:570:570)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1515:1515:1515) (1575:1575:1575)) - (PORT datab (977:977:977) (1008:1008:1008)) - (PORT datac (1197:1197:1197) (1201:1201:1201)) - (PORT datad (224:224:224) (259:259:259)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (610:610:610)) - (PORT datab (1149:1149:1149) (1207:1207:1207)) - (PORT datac (622:622:622) (649:649:649)) - (PORT datad (313:313:313) (333:333:333)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1118:1118:1118)) - (PORT datab (1065:1065:1065) (1111:1111:1111)) - (PORT datac (618:618:618) (640:640:640)) - (PORT datad (1113:1113:1113) (1121:1121:1121)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (614:614:614)) - (PORT datab (552:552:552) (580:580:580)) - (PORT datac (1506:1506:1506) (1510:1510:1510)) - (PORT datad (562:562:562) (571:571:571)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (1772:1772:1772) (1843:1843:1843)) - (PORT datac (1452:1452:1452) (1508:1508:1508)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1189:1189:1189)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (871:871:871)) - (PORT datab (841:841:841) (869:869:869)) - (PORT datac (821:821:821) (836:836:836)) - (PORT datad (611:611:611) (624:624:624)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (730:730:730)) - (PORT datab (401:401:401) (447:447:447)) - (PORT datac (1010:1010:1010) (1010:1010:1010)) - (PORT datad (328:328:328) (350:350:350)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (896:896:896)) - (PORT datab (1519:1519:1519) (1518:1518:1518)) - (PORT datac (990:990:990) (1015:1015:1015)) - (PORT datad (1042:1042:1042) (1044:1044:1044)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~39) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (1360:1360:1360) (1346:1346:1346)) - (PORT datac (848:848:848) (871:871:871)) - (PORT datad (1063:1063:1063) (1077:1077:1077)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (693:693:693)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (585:585:585) (597:597:597)) - (PORT datad (1280:1280:1280) (1302:1302:1302)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (615:615:615) (678:678:678)) - (PORT datac (502:502:502) (513:513:513)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) - (DELAY - (ABSOLUTE - (PORT dataa (1073:1073:1073) (1082:1082:1082)) - (PORT datab (209:209:209) (251:251:251)) - (PORT datad (1048:1048:1048) (1107:1107:1107)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1717:1717:1717) (1872:1872:1872)) - (PORT clk (1845:1845:1845) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2866:2866:2866) (3100:3100:3100)) - (PORT d[1] (1783:1783:1783) (1946:1946:1946)) - (PORT d[2] (2319:2319:2319) (2548:2548:2548)) - (PORT d[3] (2686:2686:2686) (2943:2943:2943)) - (PORT d[4] (2219:2219:2219) (2386:2386:2386)) - (PORT d[5] (3067:3067:3067) (3274:3274:3274)) - (PORT d[6] (1984:1984:1984) (2106:2106:2106)) - (PORT d[7] (3718:3718:3718) (3875:3875:3875)) - (PORT d[8] (2163:2163:2163) (2306:2306:2306)) - (PORT d[9] (2792:2792:2792) (2914:2914:2914)) - (PORT d[10] (1958:1958:1958) (2089:2089:2089)) - (PORT d[11] (1863:1863:1863) (2018:2018:2018)) - (PORT d[12] (3127:3127:3127) (3282:3282:3282)) - (PORT clk (1842:1842:1842) (1870:1870:1870)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2255:2255:2255) (2277:2277:2277)) - (PORT clk (1842:1842:1842) (1870:1870:1870)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (PORT d[0] (2824:2824:2824) (2829:2829:2829)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1833:1833:1833)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1957:1957:1957) (2095:2095:2095)) - (PORT clk (1847:1847:1847) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3163:3163:3163) (3401:3401:3401)) - (PORT d[1] (2074:2074:2074) (2253:2253:2253)) - (PORT d[2] (3143:3143:3143) (3374:3374:3374)) - (PORT d[3] (2675:2675:2675) (2914:2914:2914)) - (PORT d[4] (2247:2247:2247) (2423:2423:2423)) - (PORT d[5] (3044:3044:3044) (3274:3274:3274)) - (PORT d[6] (2298:2298:2298) (2426:2426:2426)) - (PORT d[7] (3691:3691:3691) (3840:3840:3840)) - (PORT d[8] (2159:2159:2159) (2300:2300:2300)) - (PORT d[9] (2799:2799:2799) (2923:2923:2923)) - (PORT d[10] (1971:1971:1971) (2118:2118:2118)) - (PORT d[11] (1870:1870:1870) (2045:2045:2045)) - (PORT d[12] (3145:3145:3145) (3286:3286:3286)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2001:2001:2001) (2020:2020:2020)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (PORT d[0] (3172:3172:3172) (3231:3231:3231)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1702:1702:1702) (1734:1734:1734)) - (PORT clk (1842:1842:1842) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2225:2225:2225) (2392:2392:2392)) - (PORT d[1] (2702:2702:2702) (2914:2914:2914)) - (PORT d[2] (2046:2046:2046) (2229:2229:2229)) - (PORT d[3] (3577:3577:3577) (3925:3925:3925)) - (PORT d[4] (1902:1902:1902) (2026:2026:2026)) - (PORT d[5] (4291:4291:4291) (4608:4608:4608)) - (PORT d[6] (2278:2278:2278) (2399:2399:2399)) - (PORT d[7] (2491:2491:2491) (2574:2574:2574)) - (PORT d[8] (3361:3361:3361) (3559:3559:3559)) - (PORT d[9] (2511:2511:2511) (2611:2611:2611)) - (PORT d[10] (1570:1570:1570) (1669:1669:1669)) - (PORT d[11] (2719:2719:2719) (2859:2859:2859)) - (PORT d[12] (1901:1901:1901) (1951:1951:1951)) - (PORT clk (1839:1839:1839) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2118:2118:2118) (2156:2156:2156)) - (PORT clk (1839:1839:1839) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1871:1871:1871)) - (PORT d[0] (2799:2799:2799) (2874:2874:2874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1802:1802:1802) (1830:1830:1830)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (993:993:993)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (448:448:448)) - (PORT datab (1479:1479:1479) (1543:1543:1543)) - (PORT datac (1157:1157:1157) (1234:1234:1234)) - (PORT datad (924:924:924) (933:933:933)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1388:1388:1388) (1439:1439:1439)) - (PORT clk (1845:1845:1845) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2791:2791:2791) (2923:2923:2923)) - (PORT d[1] (2395:2395:2395) (2583:2583:2583)) - (PORT d[2] (4343:4343:4343) (4588:4588:4588)) - (PORT d[3] (3590:3590:3590) (3895:3895:3895)) - (PORT d[4] (3188:3188:3188) (3408:3408:3408)) - (PORT d[5] (4278:4278:4278) (4576:4576:4576)) - (PORT d[6] (2551:2551:2551) (2687:2687:2687)) - (PORT d[7] (2755:2755:2755) (2837:2837:2837)) - (PORT d[8] (3648:3648:3648) (3866:3866:3866)) - (PORT d[9] (2214:2214:2214) (2313:2313:2313)) - (PORT d[10] (1296:1296:1296) (1384:1384:1384)) - (PORT d[11] (1553:1553:1553) (1685:1685:1685)) - (PORT d[12] (1908:1908:1908) (1968:1968:1968)) - (PORT clk (1842:1842:1842) (1870:1870:1870)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2597:2597:2597) (2614:2614:2614)) - (PORT clk (1842:1842:1842) (1870:1870:1870)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (PORT d[0] (2254:2254:2254) (2277:2277:2277)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1833:1833:1833)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1508:1508:1508) (1581:1581:1581)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1156:1156:1156) (1234:1234:1234)) - (PORT datad (865:865:865) (853:853:853)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1359:1359:1359) (1473:1473:1473)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1428:1428:1428) (1520:1520:1520)) - (PORT d[1] (1667:1667:1667) (1746:1746:1746)) - (PORT d[2] (1866:1866:1866) (1993:1993:1993)) - (PORT d[3] (3031:3031:3031) (3271:3271:3271)) - (PORT d[4] (2605:2605:2605) (2825:2825:2825)) - (PORT d[5] (1481:1481:1481) (1557:1557:1557)) - (PORT d[6] (2624:2624:2624) (2778:2778:2778)) - (PORT d[7] (2650:2650:2650) (2811:2811:2811)) - (PORT d[8] (1630:1630:1630) (1680:1680:1680)) - (PORT d[9] (2982:2982:2982) (3092:3092:3092)) - (PORT d[10] (1818:1818:1818) (1873:1873:1873)) - (PORT d[11] (3866:3866:3866) (4125:4125:4125)) - (PORT d[12] (2746:2746:2746) (2888:2888:2888)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1490:1490:1490) (1464:1464:1464)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (2065:2065:2065) (2075:2075:2075)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1809:1809:1809)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3109:3109:3109) (3190:3190:3190)) - (PORT clk (1822:1822:1822) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1865:1865:1865) (2015:2015:2015)) - (PORT d[1] (1871:1871:1871) (1975:1975:1975)) - (PORT d[2] (1853:1853:1853) (1980:1980:1980)) - (PORT d[3] (1872:1872:1872) (2003:2003:2003)) - (PORT d[4] (1898:1898:1898) (2018:2018:2018)) - (PORT d[5] (1812:1812:1812) (1916:1916:1916)) - (PORT d[6] (1838:1838:1838) (1993:1993:1993)) - (PORT d[7] (1899:1899:1899) (2045:2045:2045)) - (PORT d[8] (2050:2050:2050) (2128:2128:2128)) - (PORT d[9] (2042:2042:2042) (2113:2113:2113)) - (PORT d[10] (1921:1921:1921) (2026:2026:2026)) - (PORT d[11] (1965:1965:1965) (2026:2026:2026)) - (PORT d[12] (1978:1978:1978) (2135:2135:2135)) - (PORT clk (1818:1818:1818) (1811:1811:1811)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1358:1358:1358) (1452:1452:1452)) - (PORT d[1] (2823:2823:2823) (3107:3107:3107)) - (PORT d[2] (1690:1690:1690) (1829:1829:1829)) - (PORT d[3] (645:645:645) (661:661:661)) - (PORT d[4] (656:656:656) (681:681:681)) - (PORT d[5] (1547:1547:1547) (1645:1645:1645)) - (PORT d[6] (2651:2651:2651) (2805:2805:2805)) - (PORT d[7] (2295:2295:2295) (2394:2394:2394)) - (PORT d[8] (3180:3180:3180) (3433:3433:3433)) - (PORT d[9] (912:912:912) (929:929:929)) - (PORT d[10] (2265:2265:2265) (2456:2456:2456)) - (PORT d[11] (2834:2834:2834) (2946:2946:2946)) - (PORT d[12] (1140:1140:1140) (1140:1140:1140)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (1672:1672:1672) (1718:1718:1718)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1858:1858:1858) (1884:1884:1884)) @@ -47426,7 +33887,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1820:1820:1820) (1846:1846:1846)) @@ -47440,7 +33901,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1005:1005:1005) (1009:1009:1009)) @@ -47449,7 +33910,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -47458,7 +33919,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -47468,7 +33929,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -47478,23 +33939,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1051:1051:1051) (1127:1127:1127)) - (PORT d[1] (2772:2772:2772) (3012:3012:3012)) - (PORT d[2] (1986:1986:1986) (2112:2112:2112)) - (PORT d[3] (968:968:968) (1019:1019:1019)) - (PORT d[4] (716:716:716) (762:762:762)) - (PORT d[5] (1259:1259:1259) (1338:1338:1338)) - (PORT d[6] (2992:2992:2992) (3153:3153:3153)) - (PORT d[7] (2336:2336:2336) (2449:2449:2449)) - (PORT d[8] (3743:3743:3743) (3972:3972:3972)) - (PORT d[9] (3302:3302:3302) (3404:3404:3404)) - (PORT d[10] (2592:2592:2592) (2790:2790:2790)) - (PORT d[11] (2210:2210:2210) (2410:2410:2410)) - (PORT d[12] (2380:2380:2380) (2492:2492:2492)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) + (PORT d[0] (1502:1502:1502) (1566:1566:1566)) + (PORT clk (1869:1869:1869) (1895:1895:1895)) ) ) (TIMINGCHECK @@ -47503,30 +33952,98 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1879:1879:1879)) - (PORT d[0] (2000:2000:2000) (1970:1970:1970)) + (PORT d[0] (2818:2818:2818) (2896:2896:2896)) + (PORT d[1] (2077:2077:2077) (2294:2294:2294)) + (PORT d[2] (2223:2223:2223) (2370:2370:2370)) + (PORT d[3] (2274:2274:2274) (2375:2375:2375)) + (PORT d[4] (2928:2928:2928) (3204:3204:3204)) + (PORT d[5] (2379:2379:2379) (2550:2550:2550)) + (PORT d[6] (1572:1572:1572) (1678:1678:1678)) + (PORT d[7] (1564:1564:1564) (1666:1666:1666)) + (PORT d[8] (2761:2761:2761) (2991:2991:2991)) + (PORT d[9] (2092:2092:2092) (2225:2225:2225)) + (PORT d[10] (1872:1872:1872) (1997:1997:1997)) + (PORT d[11] (2890:2890:2890) (3011:3011:3011)) + (PORT d[12] (1605:1605:1605) (1686:1686:1686)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2511:2511:2511) (2509:2509:2509)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (PORT d[0] (2908:2908:2908) (2850:2850:2850)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1880:1880:1880)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1820:1820:1820)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -47537,48 +34054,5896 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) + (PORT d[0] (2487:2487:2487) (2567:2567:2567)) + (PORT clk (1834:1834:1834) (1826:1826:1826)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4515:4515:4515) (4502:4502:4502)) + (PORT d[1] (4098:4098:4098) (4096:4096:4096)) + (PORT d[2] (4387:4387:4387) (4416:4416:4416)) + (PORT d[3] (4466:4466:4466) (4494:4494:4494)) + (PORT d[4] (4550:4550:4550) (4547:4547:4547)) + (PORT d[5] (4395:4395:4395) (4433:4433:4433)) + (PORT d[6] (4601:4601:4601) (4650:4650:4650)) + (PORT d[7] (4160:4160:4160) (4143:4143:4143)) + (PORT d[8] (4661:4661:4661) (4689:4689:4689)) + (PORT d[9] (4502:4502:4502) (4695:4695:4695)) + (PORT d[10] (4622:4622:4622) (4632:4632:4632)) + (PORT d[11] (4398:4398:4398) (4428:4428:4428)) + (PORT d[12] (4464:4464:4464) (4487:4487:4487)) + (PORT clk (1830:1830:1830) (1822:1822:1822)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1834:1834:1834) (1826:1826:1826)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1835:1835:1835) (1827:1827:1827)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1350:1350:1350) (1443:1443:1443)) + (PORT clk (1826:1826:1826) (1822:1822:1822)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1428:1428:1428) (1500:1500:1500)) + (PORT datab (969:969:969) (1047:1047:1047)) + (PORT datac (1170:1170:1170) (1197:1197:1197)) + (PORT datad (1685:1685:1685) (1714:1714:1714)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1516:1516:1516) (1602:1602:1602)) + (PORT datab (970:970:970) (1048:1048:1048)) + (PORT datac (1706:1706:1706) (1767:1767:1767)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (1206:1206:1206) (1299:1299:1299)) + (PORT datac (1658:1658:1658) (1693:1693:1693)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (1382:1382:1382) (1395:1395:1395)) + (PORT datab (1382:1382:1382) (1409:1409:1409)) + (PORT datac (842:842:842) (919:919:919)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~99) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (832:832:832)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1043:1043:1043)) + (PORT datab (1039:1039:1039) (1071:1071:1071)) + (PORT datac (240:240:240) (293:293:293)) + (PORT datad (948:948:948) (984:984:984)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (707:707:707) (729:729:729)) + (PORT datac (235:235:235) (309:309:309)) + (PORT datad (359:359:359) (384:384:384)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1004:1004:1004)) + (PORT datab (917:917:917) (967:967:967)) + (PORT datac (825:825:825) (825:825:825)) + (PORT datad (891:891:891) (919:919:919)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT asdata (598:598:598) (653:653:653)) + (PORT clrn (1571:1571:1571) (1550:1550:1550)) + (PORT ena (1479:1479:1479) (1488:1488:1488)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1333:1333:1333)) + (PORT datab (857:857:857) (877:877:877)) + (PORT datac (862:862:862) (884:884:884)) + (PORT datad (1897:1897:1897) (1952:1952:1952)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1586:1586:1586) (1563:1563:1563)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|use_ixiy) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1072:1072:1072)) + (PORT datac (930:930:930) (1012:1012:1012)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1192:1192:1192) (1230:1230:1230)) + (PORT datab (998:998:998) (1107:1107:1107)) + (PORT datac (657:657:657) (721:721:721)) + (PORT datad (1243:1243:1243) (1329:1329:1329)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (915:915:915)) + (PORT datab (667:667:667) (679:679:679)) + (PORT datac (904:904:904) (934:934:934)) + (PORT datad (360:360:360) (382:382:382)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1168:1168:1168) (1211:1211:1211)) + (PORT datab (1607:1607:1607) (1625:1625:1625)) + (PORT datac (614:614:614) (646:646:646)) + (PORT datad (1081:1081:1081) (1126:1126:1126)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1363:1363:1363)) + (PORT datab (469:469:469) (523:523:523)) + (PORT datac (1707:1707:1707) (1763:1763:1763)) + (PORT datad (264:264:264) (317:317:317)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (441:441:441)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1072:1072:1072) (1108:1108:1108)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1212:1212:1212)) + (PORT datab (568:568:568) (599:599:599)) + (PORT datac (1103:1103:1103) (1115:1115:1115)) + (PORT datad (317:317:317) (336:336:336)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (898:898:898)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (590:590:590) (597:597:597)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (275:275:275)) + (PORT datab (645:645:645) (670:670:670)) + (PORT datac (194:194:194) (238:238:238)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (914:914:914)) + (PORT datab (1115:1115:1115) (1147:1147:1147)) + (PORT datac (1402:1402:1402) (1464:1464:1464)) + (PORT datad (899:899:899) (942:942:942)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (895:895:895)) + (PORT datab (939:939:939) (994:994:994)) + (PORT datac (959:959:959) (1031:1031:1031)) + (PORT datad (1113:1113:1113) (1143:1143:1143)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (916:916:916)) + (PORT datab (876:876:876) (896:896:896)) + (PORT datac (1106:1106:1106) (1134:1134:1134)) + (PORT datad (326:326:326) (350:350:350)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1572:1572:1572) (1664:1664:1664)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (1885:1885:1885) (1936:1936:1936)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1249:1249:1249)) + (PORT datab (997:997:997) (1061:1061:1061)) + (PORT datac (1628:1628:1628) (1678:1678:1678)) + (PORT datad (1161:1161:1161) (1198:1198:1198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1424:1424:1424) (1425:1425:1425)) + (PORT datab (1116:1116:1116) (1146:1146:1146)) + (PORT datac (1040:1040:1040) (1082:1082:1082)) + (PORT datad (337:337:337) (357:357:357)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (594:594:594) (614:614:614)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (644:644:644)) + (PORT datab (1041:1041:1041) (1082:1082:1082)) + (PORT datac (571:571:571) (588:588:588)) + (PORT datad (598:598:598) (647:647:647)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~48) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (933:933:933)) + (PORT datab (1205:1205:1205) (1227:1227:1227)) + (PORT datac (1512:1512:1512) (1585:1585:1585)) + (PORT datad (674:674:674) (712:712:712)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1353:1353:1353) (1383:1383:1383)) + (PORT datab (852:852:852) (880:880:880)) + (PORT datac (1075:1075:1075) (1109:1109:1109)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (942:942:942)) + (PORT datab (941:941:941) (1018:1018:1018)) + (PORT datac (1551:1551:1551) (1591:1591:1591)) + (PORT datad (1215:1215:1215) (1217:1217:1217)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (909:909:909)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (806:806:806) (819:819:819)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (2068:2068:2068) (2159:2159:2159)) + (PORT datab (1202:1202:1202) (1215:1215:1215)) + (PORT datac (1137:1137:1137) (1179:1179:1179)) + (PORT datad (1150:1150:1150) (1187:1187:1187)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (2504:2504:2504) (2616:2616:2616)) + (PORT datab (576:576:576) (586:586:586)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (981:981:981) (1012:1012:1012)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1663:1663:1663) (1697:1697:1697)) + (PORT datab (833:833:833) (893:893:893)) + (PORT datac (1036:1036:1036) (1091:1091:1091)) + (PORT datad (770:770:770) (816:816:816)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1031:1031:1031) (1043:1043:1043)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (819:819:819) (869:869:869)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (888:888:888)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (821:821:821) (872:872:872)) + (PORT datad (195:195:195) (219:219:219)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT datab (974:974:974) (1035:1035:1035)) + (PORT datac (964:964:964) (1026:1026:1026)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1008:1008:1008) (1080:1080:1080)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1191:1191:1191) (1224:1224:1224)) + (PORT d[1] (2415:2415:2415) (2649:2649:2649)) + (PORT d[2] (1758:1758:1758) (1803:1803:1803)) + (PORT d[3] (1013:1013:1013) (1063:1063:1063)) + (PORT d[4] (2608:2608:2608) (2826:2826:2826)) + (PORT d[5] (3496:3496:3496) (3699:3699:3699)) + (PORT d[6] (1026:1026:1026) (1099:1099:1099)) + (PORT d[7] (3197:3197:3197) (3375:3375:3375)) + (PORT d[8] (1246:1246:1246) (1270:1270:1270)) + (PORT d[9] (1026:1026:1026) (1088:1088:1088)) + (PORT d[10] (1315:1315:1315) (1388:1388:1388)) + (PORT d[11] (2503:2503:2503) (2659:2659:2659)) + (PORT d[12] (1307:1307:1307) (1387:1387:1387)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (944:944:944) (900:900:900)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1721:1721:1721) (1677:1677:1677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (708:708:708) (754:754:754)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (966:966:966) (1010:1010:1010)) + (PORT d[1] (2966:2966:2966) (3237:3237:3237)) + (PORT d[2] (1238:1238:1238) (1256:1256:1256)) + (PORT d[3] (1302:1302:1302) (1383:1383:1383)) + (PORT d[4] (2581:2581:2581) (2796:2796:2796)) + (PORT d[5] (2980:2980:2980) (3208:3208:3208)) + (PORT d[6] (692:692:692) (727:727:727)) + (PORT d[7] (705:705:705) (744:744:744)) + (PORT d[8] (1011:1011:1011) (1032:1032:1032)) + (PORT d[9] (717:717:717) (757:757:757)) + (PORT d[10] (1036:1036:1036) (1102:1102:1102)) + (PORT d[11] (2544:2544:2544) (2757:2757:2757)) + (PORT d[12] (1267:1267:1267) (1319:1319:1319)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (967:967:967) (945:945:945)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (2089:2089:2089) (2073:2073:2073)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (752:752:752)) + (PORT datab (688:688:688) (754:754:754)) + (PORT datac (786:786:786) (795:795:795)) + (PORT datad (864:864:864) (896:896:896)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (700:700:700) (744:744:744)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3167:3167:3167) (3303:3303:3303)) + (PORT d[1] (2937:2937:2937) (3208:3208:3208)) + (PORT d[2] (967:967:967) (987:987:987)) + (PORT d[3] (1341:1341:1341) (1401:1401:1401)) + (PORT d[4] (2612:2612:2612) (2843:2843:2843)) + (PORT d[5] (2651:2651:2651) (2894:2894:2894)) + (PORT d[6] (960:960:960) (1001:1001:1001)) + (PORT d[7] (1270:1270:1270) (1343:1343:1343)) + (PORT d[8] (1442:1442:1442) (1513:1513:1513)) + (PORT d[9] (971:971:971) (1019:1019:1019)) + (PORT d[10] (1031:1031:1031) (1057:1057:1057)) + (PORT d[11] (2872:2872:2872) (3095:3095:3095)) + (PORT d[12] (969:969:969) (1020:1020:1020)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1245:1245:1245) (1221:1221:1221)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2049:2049:2049) (2003:2003:2003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (743:743:743) (772:772:772)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3188:3188:3188) (3327:3327:3327)) + (PORT d[1] (2678:2678:2678) (2951:2951:2951)) + (PORT d[2] (1298:1298:1298) (1309:1309:1309)) + (PORT d[3] (1348:1348:1348) (1402:1402:1402)) + (PORT d[4] (2616:2616:2616) (2850:2850:2850)) + (PORT d[5] (2675:2675:2675) (2903:2903:2903)) + (PORT d[6] (1230:1230:1230) (1289:1289:1289)) + (PORT d[7] (1132:1132:1132) (1148:1148:1148)) + (PORT d[8] (1470:1470:1470) (1552:1552:1552)) + (PORT d[9] (1550:1550:1550) (1617:1617:1617)) + (PORT d[10] (724:724:724) (767:767:767)) + (PORT d[11] (2854:2854:2854) (3086:3086:3086)) + (PORT d[12] (971:971:971) (1034:1034:1034)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1229:1229:1229) (1208:1208:1208)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (1822:1822:1822) (1811:1811:1811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1242:1242:1242) (1299:1299:1299)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (968:968:968) (1003:1003:1003)) + (PORT datad (1089:1089:1089) (1119:1119:1119)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (746:746:746) (776:776:776)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2906:2906:2906) (3003:3003:3003)) + (PORT d[1] (2374:2374:2374) (2624:2624:2624)) + (PORT d[2] (1590:1590:1590) (1604:1604:1604)) + (PORT d[3] (1983:1983:1983) (2059:2059:2059)) + (PORT d[4] (2920:2920:2920) (3176:3176:3176)) + (PORT d[5] (2692:2692:2692) (2903:2903:2903)) + (PORT d[6] (1267:1267:1267) (1350:1350:1350)) + (PORT d[7] (1307:1307:1307) (1395:1395:1395)) + (PORT d[8] (1742:1742:1742) (1842:1842:1842)) + (PORT d[9] (1557:1557:1557) (1621:1621:1621)) + (PORT d[10] (2161:2161:2161) (2306:2306:2306)) + (PORT d[11] (3233:3233:3233) (3375:3375:3375)) + (PORT d[12] (1281:1281:1281) (1357:1357:1357)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2941:2941:2941) (2895:2895:2895)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (3092:3092:3092) (3136:3136:3136)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1808:1808:1808) (1806:1806:1806)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2118:2118:2118) (2165:2165:2165)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4374:4374:4374) (4418:4418:4418)) + (PORT d[1] (4140:4140:4140) (4128:4128:4128)) + (PORT d[2] (4277:4277:4277) (4327:4327:4327)) + (PORT d[3] (4389:4389:4389) (4374:4374:4374)) + (PORT d[4] (4369:4369:4369) (4385:4385:4385)) + (PORT d[5] (4402:4402:4402) (4357:4357:4357)) + (PORT d[6] (4635:4635:4635) (4717:4717:4717)) + (PORT d[7] (4444:4444:4444) (4393:4393:4393)) + (PORT d[8] (4445:4445:4445) (4433:4433:4433)) + (PORT d[9] (4508:4508:4508) (4699:4699:4699)) + (PORT d[10] (4409:4409:4409) (4440:4440:4440)) + (PORT d[11] (4509:4509:4509) (4563:4563:4563)) + (PORT d[12] (4429:4429:4429) (4547:4547:4547)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2570:2570:2570) (2648:2648:2648)) + (PORT d[1] (2033:2033:2033) (2232:2232:2232)) + (PORT d[2] (2324:2324:2324) (2498:2498:2498)) + (PORT d[3] (2521:2521:2521) (2687:2687:2687)) + (PORT d[4] (2940:2940:2940) (3191:3191:3191)) + (PORT d[5] (2266:2266:2266) (2447:2447:2447)) + (PORT d[6] (1866:1866:1866) (1990:1990:1990)) + (PORT d[7] (2543:2543:2543) (2628:2628:2628)) + (PORT d[8] (2767:2767:2767) (2988:2988:2988)) + (PORT d[9] (1759:1759:1759) (1863:1863:1863)) + (PORT d[10] (1515:1515:1515) (1609:1609:1609)) + (PORT d[11] (3453:3453:3453) (3586:3586:3586)) + (PORT d[12] (1542:1542:1542) (1649:1649:1649)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (PORT d[0] (2191:2191:2191) (2247:2247:2247)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1511:1511:1511) (1554:1554:1554)) + (PORT d[1] (2684:2684:2684) (2948:2948:2948)) + (PORT d[2] (989:989:989) (1036:1036:1036)) + (PORT d[3] (1684:1684:1684) (1752:1752:1752)) + (PORT d[4] (2594:2594:2594) (2826:2826:2826)) + (PORT d[5] (2711:2711:2711) (2920:2920:2920)) + (PORT d[6] (973:973:973) (1031:1031:1031)) + (PORT d[7] (964:964:964) (1018:1018:1018)) + (PORT d[8] (1426:1426:1426) (1505:1505:1505)) + (PORT d[9] (1567:1567:1567) (1660:1660:1660)) + (PORT d[10] (2478:2478:2478) (2623:2623:2623)) + (PORT d[11] (2885:2885:2885) (3126:3126:3126)) + (PORT d[12] (1271:1271:1271) (1324:1324:1324)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT d[0] (872:872:872) (859:859:859)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (926:926:926) (931:931:931)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3174:3174:3174) (3295:3295:3295)) + (PORT d[1] (2670:2670:2670) (2938:2938:2938)) + (PORT d[2] (1591:1591:1591) (1604:1604:1604)) + (PORT d[3] (1700:1700:1700) (1749:1749:1749)) + (PORT d[4] (2908:2908:2908) (3176:3176:3176)) + (PORT d[5] (2711:2711:2711) (2920:2920:2920)) + (PORT d[6] (974:974:974) (1032:1032:1032)) + (PORT d[7] (1544:1544:1544) (1607:1607:1607)) + (PORT d[8] (3051:3051:3051) (3314:3314:3314)) + (PORT d[9] (996:996:996) (1062:1062:1062)) + (PORT d[10] (2482:2482:2482) (2620:2620:2620)) + (PORT d[11] (2859:2859:2859) (3096:3096:3096)) + (PORT d[12] (2233:2233:2233) (2338:2338:2338)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3083:3083:3083) (3081:3081:3081)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1803:1803:1803) (1787:1787:1787)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1809:1809:1809)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2405:2405:2405) (2433:2433:2433)) + (PORT clk (1822:1822:1822) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4622:4622:4622) (4649:4649:4649)) + (PORT d[1] (4242:4242:4242) (4320:4320:4320)) + (PORT d[2] (4251:4251:4251) (4295:4295:4295)) + (PORT d[3] (4399:4399:4399) (4422:4422:4422)) + (PORT d[4] (4340:4340:4340) (4354:4354:4354)) + (PORT d[5] (4534:4534:4534) (4546:4546:4546)) + (PORT d[6] (4731:4731:4731) (4801:4801:4801)) + (PORT d[7] (4488:4488:4488) (4531:4531:4531)) + (PORT d[8] (4436:4436:4436) (4436:4436:4436)) + (PORT d[9] (4525:4525:4525) (4711:4711:4711)) + (PORT d[10] (4473:4473:4473) (4495:4495:4495)) + (PORT d[11] (4414:4414:4414) (4386:4386:4386)) + (PORT d[12] (4391:4391:4391) (4381:4381:4381)) + (PORT clk (1818:1818:1818) (1811:1811:1811)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1815:1815:1815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1811:1811:1811)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (731:731:731)) + (PORT datab (1192:1192:1192) (1240:1240:1240)) + (PORT datac (825:825:825) (833:833:833)) + (PORT datad (890:890:890) (911:911:911)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1198:1198:1198)) + (PORT datab (1192:1192:1192) (1240:1240:1240)) + (PORT datac (1509:1509:1509) (1586:1586:1586)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~103) + (DELAY + (ABSOLUTE + (PORT dataa (1738:1738:1738) (1846:1846:1846)) + (PORT datab (1412:1412:1412) (1506:1506:1506)) + (PORT datac (648:648:648) (701:701:701)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_DAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (842:842:842) (859:859:859)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (386:386:386)) + (PORT datab (291:291:291) (382:382:382)) + (PORT datad (245:245:245) (325:325:325)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_CLK\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3358:3358:3358) (3700:3700:3700)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (297:297:297)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (302:302:302)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (309:309:309)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (342:342:342)) + (PORT datab (250:250:250) (335:335:335)) + (PORT datac (380:380:380) (441:441:441)) + (PORT datad (225:225:225) (298:298:298)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (299:299:299)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (228:228:228) (301:301:301)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (227:227:227) (299:299:299)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (226:226:226) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) + (DELAY + (ABSOLUTE + (PORT datab (208:208:208) (249:249:249)) + (PORT datad (227:227:227) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) + (DELAY + (ABSOLUTE + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (218:218:218) (295:295:295)) + (PORT datad (224:224:224) (296:296:296)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1562:1562:1562)) + (PORT ena (2016:2016:2016) (2055:2055:2055)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (387:387:387)) + (PORT datab (292:292:292) (383:383:383)) + (PORT datad (240:240:240) (317:317:317)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1562:1562:1562)) + (PORT ena (2016:2016:2016) (2055:2055:2055)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (382:382:382)) + (PORT datab (278:278:278) (373:373:373)) + (PORT datad (242:242:242) (321:321:321)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1562:1562:1562)) + (PORT ena (2016:2016:2016) (2055:2055:2055)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (480:480:480)) + (PORT datab (279:279:279) (374:374:374)) + (PORT datad (243:243:243) (322:322:322)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1562:1562:1562)) + (PORT ena (2016:2016:2016) (2055:2055:2055)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (275:275:275) (377:377:377)) + (PORT datab (288:288:288) (377:377:377)) + (PORT datac (3414:3414:3414) (3775:3775:3775)) + (PORT datad (251:251:251) (331:331:331)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT datab (289:289:289) (380:380:380)) + (PORT datac (247:247:247) (341:341:341)) + (PORT datad (248:248:248) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (264:264:264) (354:354:354)) + (PORT datac (1368:1368:1368) (1427:1427:1427)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT asdata (3957:3957:3957) (4311:4311:4311)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT ena (1226:1226:1226) (1215:1215:1215)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT asdata (560:560:560) (634:634:634)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT ena (1226:1226:1226) (1215:1215:1215)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT asdata (602:602:602) (685:685:685)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT ena (1226:1226:1226) (1215:1215:1215)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT asdata (588:588:588) (665:665:665)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT ena (1226:1226:1226) (1215:1215:1215)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT asdata (958:958:958) (1010:1010:1010)) + (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (PORT ena (1200:1200:1200) (1196:1196:1196)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT asdata (960:960:960) (1018:1018:1018)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT ena (1226:1226:1226) (1215:1215:1215)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT asdata (951:951:951) (1014:1014:1014)) + (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (PORT ena (1200:1200:1200) (1196:1196:1196)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT asdata (761:761:761) (840:840:840)) + (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (PORT ena (1200:1200:1200) (1196:1196:1196)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT asdata (791:791:791) (867:867:867)) + (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (PORT ena (1200:1200:1200) (1196:1196:1196)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1075:1075:1075)) + (PORT datab (675:675:675) (742:742:742)) + (PORT datac (757:757:757) (876:876:876)) + (PORT datad (781:781:781) (888:888:888)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1549:1549:1549)) + (PORT datab (937:937:937) (1037:1037:1037)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (763:763:763) (875:875:875)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT datab (1062:1062:1062) (1155:1155:1155)) + (PORT datad (785:785:785) (795:795:795)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (722:722:722)) + (PORT datab (288:288:288) (378:378:378)) + (PORT datad (833:833:833) (880:880:880)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (827:827:827)) + (PORT datab (669:669:669) (749:749:749)) + (PORT datac (655:655:655) (721:721:721)) + (PORT datad (438:438:438) (511:511:511)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) + (DELAY + (ABSOLUTE + (PORT datab (668:668:668) (736:736:736)) + (PORT datac (345:345:345) (369:369:369)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (255:255:255)) + (PORT datab (3434:3434:3434) (3812:3812:3812)) + (PORT datac (1368:1368:1368) (1428:1428:1428)) + (PORT datad (358:358:358) (390:390:390)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1562:1562:1562)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|extended) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1764:1764:1764) (1796:1796:1796)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (758:758:758)) + (PORT datab (664:664:664) (692:692:692)) + (PORT datac (260:260:260) (346:346:346)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (553:553:553)) + (PORT datac (1367:1367:1367) (1453:1453:1453)) + (PORT datad (841:841:841) (864:864:864)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1265:1265:1265)) + (PORT datac (641:641:641) (670:670:670)) + (PORT datad (910:910:910) (977:977:977)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (426:426:426)) + (PORT datac (615:615:615) (667:667:667)) + (PORT datad (726:726:726) (803:803:803)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (736:736:736)) + (PORT datab (663:663:663) (694:694:694)) + (PORT datad (1337:1337:1337) (1379:1379:1379)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (568:568:568)) + (PORT datab (663:663:663) (740:740:740)) + (PORT datac (606:606:606) (673:673:673)) + (PORT datad (259:259:259) (336:336:336)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datac (416:416:416) (498:498:498)) + (PORT datad (651:651:651) (725:725:725)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (616:616:616)) + (PORT datab (428:428:428) (507:507:507)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (848:848:848)) + (PORT datab (984:984:984) (1072:1072:1072)) + (PORT datad (962:962:962) (1042:1042:1042)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT datab (751:751:751) (858:858:858)) + (PORT datac (739:739:739) (840:840:840)) + (PORT datad (729:729:729) (835:835:835)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (394:394:394)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (963:963:963) (1041:1041:1041)) + (PORT datad (729:729:729) (834:834:834)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (827:827:827)) + (PORT datab (290:290:290) (378:378:378)) + (PORT datac (649:649:649) (725:725:725)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (655:655:655) (729:729:729)) + (PORT datac (395:395:395) (471:471:471)) + (PORT datad (657:657:657) (716:716:716)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (418:418:418)) + (PORT datab (223:223:223) (270:270:270)) + (PORT datac (658:658:658) (723:723:723)) + (PORT datad (433:433:433) (507:507:507)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (269:269:269)) + (PORT datab (622:622:622) (671:671:671)) + (PORT datad (962:962:962) (1038:1038:1038)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1230:1230:1230)) + (PORT datab (241:241:241) (321:321:321)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (548:548:548) (570:570:570)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1044:1044:1044)) + (PORT datac (902:902:902) (995:995:995)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1413:1413:1413) (1549:1549:1549)) + (PORT datab (696:696:696) (729:729:729)) + (PORT datac (959:959:959) (1041:1041:1041)) + (PORT datad (190:190:190) (224:224:224)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (981:981:981) (1070:1070:1070)) + (PORT datac (721:721:721) (830:830:830)) + (PORT datad (729:729:729) (838:838:838)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (908:908:908)) + (PORT datab (667:667:667) (685:685:685)) + (PORT datad (496:496:496) (512:512:512)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1414:1414:1414) (1542:1542:1542)) + (PORT datab (213:213:213) (258:258:258)) + (PORT datac (667:667:667) (692:692:692)) + (PORT datad (766:766:766) (872:872:872)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (818:818:818)) + (PORT datab (363:363:363) (394:394:394)) + (PORT datac (717:717:717) (819:819:819)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1555:1555:1555) (1666:1666:1666)) + (PORT datab (982:982:982) (1037:1037:1037)) + (PORT datad (518:518:518) (530:530:530)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~0) + (DELAY + (ABSOLUTE + (PORT datab (1469:1469:1469) (1606:1606:1606)) + (PORT datac (912:912:912) (975:975:975)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (425:425:425) (503:503:503)) + (PORT datac (1117:1117:1117) (1170:1170:1170)) + (PORT datad (651:651:651) (723:723:723)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (776:776:776)) + (PORT datab (412:412:412) (493:493:493)) + (PORT datac (606:606:606) (674:674:674)) + (PORT datad (261:261:261) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (569:569:569)) + (PORT datab (664:664:664) (741:741:741)) + (PORT datac (497:497:497) (515:515:515)) + (PORT datad (655:655:655) (724:724:724)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (615:615:615)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (768:768:768)) + (PORT datab (1230:1230:1230) (1291:1291:1291)) + (PORT datac (443:443:443) (506:506:506)) + (PORT datad (1066:1066:1066) (1109:1109:1109)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (844:844:844)) + (PORT datab (1400:1400:1400) (1489:1489:1489)) + (PORT datac (917:917:917) (988:988:988)) + (PORT datad (854:854:854) (921:921:921)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (279:279:279)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (739:739:739) (839:839:839)) + (PORT datad (1547:1547:1547) (1637:1637:1637)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (523:523:523) (533:533:533)) + (PORT datad (944:944:944) (998:998:998)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (729:729:729)) + (PORT datab (1120:1120:1120) (1195:1195:1195)) + (PORT datac (633:633:633) (694:694:694)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (745:745:745)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (484:484:484) (550:550:550)) + (PORT datab (1228:1228:1228) (1291:1291:1291)) + (PORT datac (741:741:741) (842:842:842)) + (PORT datad (842:842:842) (867:867:867)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (875:875:875)) + (PORT datab (913:913:913) (986:986:986)) + (PORT datac (1115:1115:1115) (1162:1162:1162)) + (PORT datad (710:710:710) (791:791:791)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (395:395:395)) + (PORT datac (700:700:700) (784:784:784)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (868:868:868)) + (PORT datab (912:912:912) (984:984:984)) + (PORT datac (659:659:659) (735:735:735)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (710:710:710)) + (PORT datab (496:496:496) (580:580:580)) + (PORT datac (396:396:396) (470:470:470)) + (PORT datad (601:601:601) (643:643:643)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (937:937:937)) + (PORT datab (941:941:941) (1038:1038:1038)) + (PORT datac (758:758:758) (878:878:878)) + (PORT datad (764:764:764) (871:871:871)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (932:932:932)) + (PORT datab (788:788:788) (904:904:904)) + (PORT datad (763:763:763) (876:876:876)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (935:935:935)) + (PORT datab (938:938:938) (1037:1037:1037)) + (PORT datac (757:757:757) (875:875:875)) + (PORT datad (764:764:764) (875:875:875)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (279:279:279)) + (PORT datab (941:941:941) (1039:1039:1039)) + (PORT datac (311:311:311) (337:337:337)) + (PORT datad (1387:1387:1387) (1504:1504:1504)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1544:1544:1544)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (932:932:932) (1003:1003:1003)) + (PORT datad (517:517:517) (528:528:528)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (398:398:398)) + (PORT datab (274:274:274) (359:359:359)) + (PORT datad (604:604:604) (617:617:617)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1387:1387:1387) (1447:1447:1447)) + (PORT datab (411:411:411) (471:471:471)) + (PORT datac (1375:1375:1375) (1408:1408:1408)) + (PORT datad (583:583:583) (631:631:631)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (804:804:804)) + (PORT datab (3348:3348:3348) (3488:3488:3488)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1705:1705:1705) (1713:1713:1713)) + (PORT datab (1225:1225:1225) (1301:1301:1301)) + (PORT datac (636:636:636) (675:675:675)) + (PORT datad (1144:1144:1144) (1160:1160:1160)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1628:1628:1628)) + (PORT datab (1226:1226:1226) (1302:1302:1302)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1240:1240:1240) (1368:1368:1368)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1042:1042:1042)) + (PORT datab (636:636:636) (676:676:676)) + (PORT datac (240:240:240) (293:293:293)) + (PORT datad (1667:1667:1667) (1728:1728:1728)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (912:912:912) (931:931:931)) + (PORT datac (945:945:945) (986:986:986)) + (PORT datad (219:219:219) (254:254:254)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (310:310:310)) + (PORT datab (705:705:705) (769:769:769)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (208:208:208) (240:240:240)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (220:220:220)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1557:1557:1557)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (284:284:284) (380:380:380)) + (PORT datac (903:903:903) (966:966:966)) + (PORT datad (928:928:928) (982:982:982)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1410:1410:1410) (1521:1521:1521)) + (PORT datab (897:897:897) (911:911:911)) + (PORT datac (924:924:924) (1011:1011:1011)) + (PORT datad (876:876:876) (894:894:894)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1572:1572:1572) (1710:1710:1710)) + (PORT datab (2337:2337:2337) (2410:2410:2410)) + (PORT datac (671:671:671) (718:718:718)) + (PORT datad (2748:2748:2748) (2873:2873:2873)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (232:232:232) (283:283:283)) + (PORT datac (195:195:195) (238:238:238)) + (PORT datad (371:371:371) (399:399:399)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (658:658:658)) + (PORT datab (427:427:427) (471:471:471)) + (PORT datac (543:543:543) (559:559:559)) + (PORT datad (1164:1164:1164) (1218:1218:1218)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1490:1490:1490) (1592:1592:1592)) + (PORT datab (438:438:438) (474:474:474)) + (PORT datac (943:943:943) (994:994:994)) + (PORT datad (211:211:211) (243:243:243)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1047:1047:1047)) + (PORT datab (1110:1110:1110) (1179:1179:1179)) + (PORT datac (1261:1261:1261) (1313:1313:1313)) + (PORT datad (1359:1359:1359) (1384:1384:1384)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1122:1122:1122)) + (PORT datab (961:961:961) (1050:1050:1050)) + (PORT datac (1264:1264:1264) (1310:1310:1310)) + (PORT datad (1206:1206:1206) (1270:1270:1270)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1505:1505:1505) (1526:1526:1526)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (868:868:868) (865:865:865)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1606:1606:1606) (1627:1627:1627)) + (PORT datab (831:831:831) (859:859:859)) + (PORT datad (1029:1029:1029) (1028:1028:1028)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1568:1568:1568) (1597:1597:1597)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (643:643:643) (684:684:684)) + (PORT datad (555:555:555) (558:558:558)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (650:650:650)) + (PORT datab (552:552:552) (565:565:565)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (372:372:372) (397:397:397)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~21) + (DELAY + (ABSOLUTE + (PORT dataa (2257:2257:2257) (2337:2337:2337)) + (PORT datab (1549:1549:1549) (1673:1673:1673)) + (PORT datac (902:902:902) (922:922:922)) + (PORT datad (1165:1165:1165) (1178:1178:1178)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT datab (230:230:230) (277:277:277)) + (PORT datac (343:343:343) (365:365:365)) + (PORT datad (369:369:369) (394:394:394)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1298:1298:1298) (1395:1395:1395)) + (PORT datab (927:927:927) (974:974:974)) + (PORT datac (1940:1940:1940) (2070:2070:2070)) + (PORT datad (2052:2052:2052) (2214:2214:2214)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (906:906:906)) + (PORT datab (230:230:230) (277:277:277)) + (PORT datac (196:196:196) (240:240:240)) + (PORT datad (370:370:370) (394:394:394)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1167:1167:1167)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (222:222:222) (268:268:268)) + (PORT datac (200:200:200) (236:236:236)) + (PORT datad (223:223:223) (250:250:250)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1938:1938:1938) (2062:2062:2062)) + (PORT datab (2594:2594:2594) (2695:2695:2695)) + (PORT datad (1436:1436:1436) (1528:1528:1528)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (720:720:720)) + (PORT datab (699:699:699) (758:758:758)) + (PORT datac (1095:1095:1095) (1090:1090:1090)) + (PORT datad (644:644:644) (692:692:692)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (611:611:611) (632:632:632)) + (PORT datad (777:777:777) (789:789:789)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (890:890:890)) + (PORT datab (332:332:332) (362:362:362)) + (PORT datac (372:372:372) (397:397:397)) + (PORT datad (604:604:604) (626:626:626)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1811:1811:1811) (1903:1903:1903)) + (PORT datab (921:921:921) (989:989:989)) + (PORT datac (923:923:923) (1008:1008:1008)) + (PORT datad (436:436:436) (468:468:468)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (966:966:966)) + (PORT datac (902:902:902) (921:921:921)) + (PORT datad (1383:1383:1383) (1455:1455:1455)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (444:444:444)) + (PORT datac (192:192:192) (225:225:225)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1242:1242:1242)) + (PORT datab (196:196:196) (236:236:236)) + (PORT datac (593:593:593) (604:604:604)) + (PORT datad (376:376:376) (396:396:396)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1240:1240:1240)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datad (877:877:877) (932:932:932)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2446:2446:2446) (2535:2535:2535)) + (PORT datab (1615:1615:1615) (1728:1728:1728)) + (PORT datac (1769:1769:1769) (1897:1897:1897)) + (PORT datad (1666:1666:1666) (1684:1684:1684)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1432:1432:1432) (1515:1515:1515)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1052:1052:1052) (1100:1100:1100)) + (PORT datad (1335:1335:1335) (1356:1356:1356)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1121:1121:1121) (1241:1241:1241)) + (PORT datac (884:884:884) (939:939:939)) + (PORT datad (957:957:957) (1022:1022:1022)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (935:935:935)) + (PORT datab (944:944:944) (1021:1021:1021)) + (PORT datac (588:588:588) (603:603:603)) + (PORT datad (537:537:537) (536:536:536)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (838:838:838) (860:860:860)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (195:195:195) (228:228:228)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1255:1255:1255)) + (PORT datab (257:257:257) (345:345:345)) + (PORT datac (214:214:214) (290:290:290)) + (PORT datad (580:580:580) (615:615:615)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (607:607:607)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (590:590:590) (613:613:613)) + (PORT datad (600:600:600) (615:615:615)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1706:1706:1706)) + (PORT datab (2568:2568:2568) (2670:2670:2670)) + (PORT datac (1057:1057:1057) (1083:1083:1083)) + (PORT datad (862:862:862) (898:898:898)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1089:1089:1089) (1120:1120:1120)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1186:1186:1186) (1228:1228:1228)) + (PORT datad (564:564:564) (579:579:579)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (920:920:920)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (237:237:237) (278:278:278)) + (PORT datad (594:594:594) (611:611:611)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1036:1036:1036)) + (PORT datab (263:263:263) (310:310:310)) + (PORT datac (1393:1393:1393) (1475:1475:1475)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (950:950:950)) + (PORT datab (1129:1129:1129) (1199:1199:1199)) + (PORT datac (889:889:889) (932:932:932)) + (PORT datad (1015:1015:1015) (1011:1011:1011)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (514:514:514)) + (PORT datab (896:896:896) (914:914:914)) + (PORT datac (922:922:922) (1007:1007:1007)) + (PORT datad (405:405:405) (434:434:434)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT datab (1062:1062:1062) (1088:1088:1088)) + (PORT datac (208:208:208) (250:250:250)) + (PORT datad (209:209:209) (241:241:241)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (524:524:524) (539:539:539)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (594:594:594) (613:613:613)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (567:567:567) (592:592:592)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (746:746:746)) + (PORT datab (661:661:661) (721:721:721)) + (PORT datac (883:883:883) (903:903:903)) + (PORT datad (893:893:893) (916:916:916)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1154:1154:1154) (1188:1188:1188)) + (PORT datad (629:629:629) (643:643:643)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (408:408:408)) + (PORT datab (644:644:644) (678:678:678)) + (PORT datac (871:871:871) (896:896:896)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (721:721:721)) + (PORT datab (956:956:956) (981:981:981)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (217:217:217) (250:250:250)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (772:772:772)) + (PORT datac (1115:1115:1115) (1160:1160:1160)) + (PORT datad (739:739:739) (827:827:827)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (871:871:871)) + (PORT datab (725:725:725) (810:810:810)) + (PORT datac (1118:1118:1118) (1161:1161:1161)) + (PORT datad (711:711:711) (788:788:788)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (915:915:915) (989:989:989)) + (PORT datac (1116:1116:1116) (1162:1162:1162)) + (PORT datad (329:329:329) (349:349:349)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (261:261:261)) + (PORT datab (199:199:199) (239:239:239)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (727:727:727) (814:814:814)) + (PORT datab (981:981:981) (1068:1068:1068)) + (PORT datac (722:722:722) (831:831:831)) + (PORT datad (729:729:729) (835:835:835)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (903:903:903)) + (PORT datab (736:736:736) (834:834:834)) + (PORT datac (710:710:710) (811:811:811)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (390:390:390)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (338:338:338) (357:357:357)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1230:1230:1230)) + (PORT datab (724:724:724) (793:793:793)) + (PORT datac (214:214:214) (291:291:291)) + (PORT datad (550:550:550) (572:572:572)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (1028:1028:1028)) + (PORT datab (779:779:779) (879:879:879)) + (PORT datac (1365:1365:1365) (1458:1458:1458)) + (PORT datad (1189:1189:1189) (1251:1251:1251)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~76) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (382:382:382)) + (PORT datab (281:281:281) (364:364:364)) + (PORT datac (928:928:928) (975:975:975)) + (PORT datad (1494:1494:1494) (1585:1585:1585)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT datac (740:740:740) (842:842:842)) + (PORT datad (1190:1190:1190) (1255:1255:1255)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (872:872:872)) + (PORT datab (728:728:728) (815:815:815)) + (PORT datac (884:884:884) (953:953:953)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (844:844:844)) + (PORT datab (1502:1502:1502) (1605:1605:1605)) + (PORT datac (916:916:916) (991:991:991)) + (PORT datad (852:852:852) (919:919:919)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~74) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (610:610:610)) + (PORT datab (344:344:344) (369:369:369)) + (PORT datac (1366:1366:1366) (1452:1452:1452)) + (PORT datad (1547:1547:1547) (1637:1637:1637)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (448:448:448) (513:513:513)) + (PORT datad (841:841:841) (864:864:864)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (571:571:571)) + (PORT datab (335:335:335) (364:364:364)) + (PORT datad (736:736:736) (824:824:824)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (758:758:758) (862:862:862)) + (PORT datab (729:729:729) (828:828:828)) + (PORT datac (335:335:335) (363:363:363)) + (PORT datad (1132:1132:1132) (1201:1201:1201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) + (DELAY + (ABSOLUTE + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (718:718:718) (814:814:814)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (455:455:455)) + (PORT datab (1124:1124:1124) (1199:1199:1199)) + (PORT datac (636:636:636) (698:698:698)) + (PORT datad (629:629:629) (680:680:680)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1665:1665:1665)) + (PORT datab (981:981:981) (1035:1035:1035)) + (PORT datad (515:515:515) (529:529:529)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (569:569:569)) + (PORT datac (607:607:607) (672:672:672)) + (PORT datad (260:260:260) (335:335:335)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (428:428:428)) + (PORT datab (848:848:848) (850:850:850)) + (PORT datad (734:734:734) (821:821:821)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~1) + (DELAY + (ABSOLUTE + (PORT datab (1472:1472:1472) (1607:1607:1607)) + (PORT datac (347:347:347) (411:411:411)) + (PORT datad (901:901:901) (962:962:962)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (220:220:220) (260:260:260)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~1) + (DELAY + (ABSOLUTE + (PORT datac (1076:1076:1076) (1171:1171:1171)) + (PORT datad (1031:1031:1031) (1115:1115:1115)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (1413:1413:1413) (1543:1543:1543)) + (PORT datab (788:788:788) (903:903:903)) + (PORT datac (960:960:960) (1037:1037:1037)) + (PORT datad (777:777:777) (882:882:882)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (675:675:675) (704:704:704)) + (PORT datac (604:604:604) (622:622:622)) + (PORT datad (901:901:901) (976:976:976)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) + (DELAY + (ABSOLUTE + (PORT datab (968:968:968) (1057:1057:1057)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT datac (654:654:654) (724:724:724)) + (PORT datad (637:637:637) (707:707:707)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT datab (654:654:654) (726:726:726)) + (PORT datac (693:693:693) (782:782:782)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (258:258:258)) + (PORT datab (473:473:473) (549:549:549)) + (PORT datac (637:637:637) (704:704:704)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (277:277:277)) + (PORT datab (665:665:665) (741:741:741)) + (PORT datad (650:650:650) (727:727:727)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (926:926:926)) + (PORT datab (223:223:223) (262:262:262)) + (PORT datac (337:337:337) (360:360:360)) + (PORT datad (543:543:543) (562:562:562)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (820:820:820)) + (PORT datad (946:946:946) (995:995:995)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1387:1387:1387) (1444:1444:1444)) + (PORT datab (598:598:598) (652:652:652)) + (PORT datac (1375:1375:1375) (1406:1406:1406)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (804:804:804)) + (PORT datab (3349:3349:3349) (3490:3490:3490)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (891:891:891) (902:902:902)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1236:1236:1236) (1280:1280:1280)) + (PORT d[1] (983:983:983) (1045:1045:1045)) + (PORT d[2] (962:962:962) (977:977:977)) + (PORT d[3] (1021:1021:1021) (1074:1074:1074)) + (PORT d[4] (2601:2601:2601) (2818:2818:2818)) + (PORT d[5] (1028:1028:1028) (1063:1063:1063)) + (PORT d[6] (994:994:994) (1056:1056:1056)) + (PORT d[7] (954:954:954) (1016:1016:1016)) + (PORT d[8] (1046:1046:1046) (1093:1093:1093)) + (PORT d[9] (998:998:998) (1055:1055:1055)) + (PORT d[10] (1047:1047:1047) (1121:1121:1121)) + (PORT d[11] (2576:2576:2576) (2762:2762:2762)) + (PORT d[12] (1307:1307:1307) (1386:1386:1386)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (951:951:951) (911:911:911)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1484:1484:1484) (1455:1455:1455)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (980:980:980) (991:991:991)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (706:706:706) (727:727:727)) + (PORT d[1] (2392:2392:2392) (2624:2624:2624)) + (PORT d[2] (1503:1503:1503) (1540:1540:1540)) + (PORT d[3] (981:981:981) (1040:1040:1040)) + (PORT d[4] (2591:2591:2591) (2807:2807:2807)) + (PORT d[5] (3468:3468:3468) (3668:3668:3668)) + (PORT d[6] (1271:1271:1271) (1334:1334:1334)) + (PORT d[7] (3191:3191:3191) (3366:3366:3366)) + (PORT d[8] (691:691:691) (713:713:713)) + (PORT d[9] (1603:1603:1603) (1661:1661:1661)) + (PORT d[10] (1346:1346:1346) (1434:1434:1434)) + (PORT d[11] (2230:2230:2230) (2413:2413:2413)) + (PORT d[12] (1570:1570:1570) (1649:1649:1649)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (671:671:671) (627:627:627)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1485:1485:1485) (1441:1441:1441)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1101:1101:1101) (1111:1111:1111)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (986:986:986) (1014:1014:1014)) + (PORT d[1] (3450:3450:3450) (3742:3742:3742)) + (PORT d[2] (1249:1249:1249) (1290:1290:1290)) + (PORT d[3] (1284:1284:1284) (1331:1331:1331)) + (PORT d[4] (2575:2575:2575) (2806:2806:2806)) + (PORT d[5] (3485:3485:3485) (3709:3709:3709)) + (PORT d[6] (1317:1317:1317) (1415:1415:1415)) + (PORT d[7] (1218:1218:1218) (1279:1279:1279)) + (PORT d[8] (1003:1003:1003) (1027:1027:1027)) + (PORT d[9] (1567:1567:1567) (1623:1623:1623)) + (PORT d[10] (1356:1356:1356) (1454:1454:1454)) + (PORT d[11] (2251:2251:2251) (2436:2436:2436)) + (PORT d[12] (1606:1606:1606) (1702:1702:1702)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (963:963:963) (919:919:919)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (1702:1702:1702) (1655:1655:1655)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (409:409:409)) + (PORT datab (686:686:686) (752:752:752)) + (PORT datac (651:651:651) (716:716:716)) + (PORT datad (645:645:645) (655:655:655)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1183:1183:1183) (1208:1208:1208)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3642:3642:3642) (3824:3824:3824)) + (PORT d[1] (1366:1366:1366) (1493:1493:1493)) + (PORT d[2] (2003:2003:2003) (2099:2099:2099)) + (PORT d[3] (2459:2459:2459) (2585:2585:2585)) + (PORT d[4] (2200:2200:2200) (2332:2332:2332)) + (PORT d[5] (1345:1345:1345) (1450:1450:1450)) + (PORT d[6] (1456:1456:1456) (1487:1487:1487)) + (PORT d[7] (3346:3346:3346) (3494:3494:3494)) + (PORT d[8] (3607:3607:3607) (3856:3856:3856)) + (PORT d[9] (3167:3167:3167) (3306:3306:3306)) + (PORT d[10] (3154:3154:3154) (3327:3327:3327)) + (PORT d[11] (1793:1793:1793) (1891:1891:1891)) + (PORT d[12] (1416:1416:1416) (1454:1454:1454)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1620:1620:1620) (1580:1580:1580)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (2766:2766:2766) (2809:2809:2809)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1075:1075:1075)) + (PORT datab (1410:1410:1410) (1504:1504:1504)) + (PORT datac (532:532:532) (545:545:545)) + (PORT datad (1173:1173:1173) (1173:1173:1173)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1641:1641:1641) (1729:1729:1729)) (PORT clk (1857:1857:1857) (1885:1885:1885)) ) ) @@ -47588,22 +39953,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1690:1690:1690) (1807:1807:1807)) - (PORT d[1] (2046:2046:2046) (2145:2145:2145)) - (PORT d[2] (3364:3364:3364) (3706:3706:3706)) - (PORT d[3] (2988:2988:2988) (3217:3217:3217)) - (PORT d[4] (2266:2266:2266) (2486:2486:2486)) - (PORT d[5] (1749:1749:1749) (1820:1820:1820)) - (PORT d[6] (2313:2313:2313) (2470:2470:2470)) - (PORT d[7] (2955:2955:2955) (3126:3126:3126)) - (PORT d[8] (1762:1762:1762) (1854:1854:1854)) - (PORT d[9] (4063:4063:4063) (4204:4204:4204)) - (PORT d[10] (1916:1916:1916) (1991:1991:1991)) - (PORT d[11] (2215:2215:2215) (2437:2437:2437)) - (PORT d[12] (2676:2676:2676) (2810:2810:2810)) + (PORT d[0] (2872:2872:2872) (2966:2966:2966)) + (PORT d[1] (2017:2017:2017) (2182:2182:2182)) + (PORT d[2] (1954:1954:1954) (2061:2061:2061)) + (PORT d[3] (1897:1897:1897) (2022:2022:2022)) + (PORT d[4] (3021:3021:3021) (3172:3172:3172)) + (PORT d[5] (2229:2229:2229) (2391:2391:2391)) + (PORT d[6] (1711:1711:1711) (1774:1774:1774)) + (PORT d[7] (2133:2133:2133) (2250:2250:2250)) + (PORT d[8] (2427:2427:2427) (2610:2610:2610)) + (PORT d[9] (1679:1679:1679) (1785:1785:1785)) + (PORT d[10] (1442:1442:1442) (1508:1508:1508)) + (PORT d[11] (1723:1723:1723) (1780:1780:1780)) + (PORT d[12] (2286:2286:2286) (2347:2347:2347)) (PORT clk (1854:1854:1854) (1881:1881:1881)) ) ) @@ -47613,10 +39978,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1802:1802:1802) (1764:1764:1764)) + (PORT d[0] (2567:2567:2567) (2620:2620:2620)) (PORT clk (1854:1854:1854) (1881:1881:1881)) ) ) @@ -47626,17 +39991,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (2948:2948:2948) (2933:2933:2933)) + (PORT d[0] (3733:3733:3733) (3648:3648:3648)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1858:1858:1858) (1886:1886:1886)) @@ -47646,7 +40011,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1858:1858:1858) (1886:1886:1886)) @@ -47656,7 +40021,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1858:1858:1858) (1886:1886:1886)) @@ -47666,7 +40031,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1858:1858:1858) (1886:1886:1886)) @@ -47676,7 +40041,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1812:1812:1812) (1810:1810:1810)) @@ -47690,10 +40055,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (3414:3414:3414) (3505:3505:3505)) + (PORT d[0] (2034:2034:2034) (2028:2028:2028)) (PORT clk (1822:1822:1822) (1816:1816:1816)) ) ) @@ -47703,22 +40068,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1886:1886:1886) (1997:1997:1997)) - (PORT d[1] (1803:1803:1803) (1927:1927:1927)) - (PORT d[2] (1864:1864:1864) (1977:1977:1977)) - (PORT d[3] (1954:1954:1954) (2123:2123:2123)) - (PORT d[4] (1856:1856:1856) (1953:1953:1953)) - (PORT d[5] (1852:1852:1852) (1945:1945:1945)) - (PORT d[6] (2034:2034:2034) (2116:2116:2116)) - (PORT d[7] (1921:1921:1921) (2042:2042:2042)) - (PORT d[8] (2057:2057:2057) (2134:2134:2134)) - (PORT d[9] (2046:2046:2046) (2126:2126:2126)) - (PORT d[10] (1870:1870:1870) (1972:1972:1972)) - (PORT d[11] (2002:2002:2002) (2092:2092:2092)) - (PORT d[12] (1872:1872:1872) (1984:1984:1984)) + (PORT d[0] (4393:4393:4393) (4461:4461:4461)) + (PORT d[1] (4131:4131:4131) (4181:4181:4181)) + (PORT d[2] (4247:4247:4247) (4323:4323:4323)) + (PORT d[3] (4546:4546:4546) (4614:4614:4614)) + (PORT d[4] (4322:4322:4322) (4309:4309:4309)) + (PORT d[5] (4617:4617:4617) (4651:4651:4651)) + (PORT d[6] (4408:4408:4408) (4485:4485:4485)) + (PORT d[7] (4302:4302:4302) (4274:4274:4274)) + (PORT d[8] (4572:4572:4572) (4637:4637:4637)) + (PORT d[9] (4446:4446:4446) (4691:4691:4691)) + (PORT d[10] (4705:4705:4705) (4743:4743:4743)) + (PORT d[11] (4358:4358:4358) (4390:4390:4390)) + (PORT d[12] (4507:4507:4507) (4645:4645:4645)) (PORT clk (1818:1818:1818) (1812:1812:1812)) ) ) @@ -47728,7 +40093,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1822:1822:1822) (1816:1816:1816)) @@ -47737,7 +40102,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) (DELAY (ABSOLUTE (PORT clk (1823:1823:1823) (1817:1817:1817)) @@ -47747,7 +40112,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1823:1823:1823) (1817:1817:1817)) @@ -47757,7 +40122,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1823:1823:1823) (1817:1817:1817)) @@ -47767,7 +40132,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1823:1823:1823) (1817:1817:1817)) @@ -47777,7 +40142,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) (DELAY (ABSOLUTE (PORT clk (1814:1814:1814) (1812:1812:1812)) @@ -47790,15 +40155,426 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) (DELAY (ABSOLUTE - (PORT dataa (1012:1012:1012) (1121:1121:1121)) - (PORT datab (980:980:980) (1047:1047:1047)) - (PORT datac (900:900:900) (912:912:912)) - (PORT datad (1449:1449:1449) (1539:1539:1539)) - (IOPATH dataa combout (339:339:339) (367:367:367)) + (PORT d[0] (2840:2840:2840) (2949:2949:2949)) + (PORT d[1] (1732:1732:1732) (1897:1897:1897)) + (PORT d[2] (1932:1932:1932) (2053:2053:2053)) + (PORT d[3] (1899:1899:1899) (2019:2019:2019)) + (PORT d[4] (2772:2772:2772) (2916:2916:2916)) + (PORT d[5] (2232:2232:2232) (2415:2415:2415)) + (PORT d[6] (2007:2007:2007) (2069:2069:2069)) + (PORT d[7] (2130:2130:2130) (2260:2260:2260)) + (PORT d[8] (2390:2390:2390) (2571:2571:2571)) + (PORT d[9] (1959:1959:1959) (2082:2082:2082)) + (PORT d[10] (1985:1985:1985) (2067:2067:2067)) + (PORT d[11] (2017:2017:2017) (2091:2091:2091)) + (PORT d[12] (2566:2566:2566) (2656:2656:2656)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1884:1884:1884)) + (PORT d[0] (2730:2730:2730) (2796:2796:2796)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1622:1622:1622) (1706:1706:1706)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2870:2870:2870) (2964:2964:2964)) + (PORT d[1] (2048:2048:2048) (2231:2231:2231)) + (PORT d[2] (1893:1893:1893) (1990:1990:1990)) + (PORT d[3] (1883:1883:1883) (2014:2014:2014)) + (PORT d[4] (3037:3037:3037) (3174:3174:3174)) + (PORT d[5] (1957:1957:1957) (2122:2122:2122)) + (PORT d[6] (1728:1728:1728) (1783:1783:1783)) + (PORT d[7] (1821:1821:1821) (1856:1856:1856)) + (PORT d[8] (2421:2421:2421) (2612:2612:2612)) + (PORT d[9] (1968:1968:1968) (2080:2080:2080)) + (PORT d[10] (2002:2002:2002) (2089:2089:2089)) + (PORT d[11] (2528:2528:2528) (2597:2597:2597)) + (PORT d[12] (2240:2240:2240) (2309:2309:2309)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2519:2519:2519) (2503:2503:2503)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (3674:3674:3674) (3756:3756:3756)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2034:2034:2034) (2023:2023:2023)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4437:4437:4437) (4508:4508:4508)) + (PORT d[1] (4211:4211:4211) (4251:4251:4251)) + (PORT d[2] (4278:4278:4278) (4341:4341:4341)) + (PORT d[3] (4543:4543:4543) (4609:4609:4609)) + (PORT d[4] (4346:4346:4346) (4342:4342:4342)) + (PORT d[5] (4610:4610:4610) (4641:4641:4641)) + (PORT d[6] (4708:4708:4708) (4757:4757:4757)) + (PORT d[7] (4312:4312:4312) (4268:4268:4268)) + (PORT d[8] (4489:4489:4489) (4504:4504:4504)) + (PORT d[9] (4453:4453:4453) (4722:4722:4722)) + (PORT d[10] (4622:4622:4622) (4654:4654:4654)) + (PORT d[11] (4366:4366:4366) (4392:4392:4392)) + (PORT d[12] (4506:4506:4506) (4645:4645:4645)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1206:1206:1206) (1287:1287:1287)) + (PORT datab (1437:1437:1437) (1489:1489:1489)) + (PORT datac (1126:1126:1126) (1177:1177:1177)) + (PORT datad (1429:1429:1429) (1485:1485:1485)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3633:3633:3633) (3814:3814:3814)) + (PORT d[1] (2642:2642:2642) (2867:2867:2867)) + (PORT d[2] (1648:1648:1648) (1726:1726:1726)) + (PORT d[3] (2160:2160:2160) (2263:2263:2263)) + (PORT d[4] (2162:2162:2162) (2254:2254:2254)) + (PORT d[5] (1662:1662:1662) (1786:1786:1786)) + (PORT d[6] (1132:1132:1132) (1171:1171:1171)) + (PORT d[7] (1160:1160:1160) (1190:1190:1190)) + (PORT d[8] (2171:2171:2171) (2353:2353:2353)) + (PORT d[9] (2266:2266:2266) (2413:2413:2413)) + (PORT d[10] (2562:2562:2562) (2693:2693:2693)) + (PORT d[11] (915:915:915) (961:961:961)) + (PORT d[12] (1750:1750:1750) (1775:1775:1775)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (3453:3453:3453) (3330:3330:3330)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1208:1208:1208) (1217:1217:1217)) + (PORT datab (1079:1079:1079) (1088:1088:1088)) + (PORT datac (181:181:181) (219:219:219)) + (PORT datad (1384:1384:1384) (1408:1408:1408)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -47807,14 +40583,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) + (INSTANCE D\[0\]\~54) (DELAY (ABSOLUTE - (PORT dataa (1009:1009:1009) (1117:1117:1117)) - (PORT datab (1493:1493:1493) (1569:1569:1569)) - (PORT datac (1124:1124:1124) (1151:1151:1151)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (1502:1502:1502) (1614:1614:1614)) + (PORT datab (951:951:951) (1007:1007:1007)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (778:778:778)) + (PORT datab (1164:1164:1164) (1255:1255:1255)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1972:1972:1972) (2064:2064:2064)) + (PORT datab (1148:1148:1148) (1200:1200:1200)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (843:843:843) (868:868:868)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -47823,155 +40631,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~89) + (INSTANCE D\[0\]\~58) (DELAY (ABSOLUTE - (PORT dataa (2740:2740:2740) (2944:2944:2944)) - (PORT datab (1198:1198:1198) (1260:1260:1260)) - (PORT datac (979:979:979) (984:984:984)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (985:985:985)) - (PORT datab (1211:1211:1211) (1307:1307:1307)) - (PORT datac (887:887:887) (923:923:923)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1011:1011:1011)) - (PORT datac (193:193:193) (226:226:226)) + (PORT dataa (1975:1975:1975) (2066:2066:2066)) + (PORT datab (647:647:647) (708:708:708)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1634:1634:1634) (1673:1673:1673)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1431:1431:1431)) - (PORT datab (1271:1271:1271) (1357:1357:1357)) - (PORT datac (814:814:814) (834:834:834)) - (PORT datad (632:632:632) (690:690:690)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~8) + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) (DELAY (ABSOLUTE - (PORT dataa (623:623:623) (666:666:666)) - (PORT datac (1211:1211:1211) (1285:1285:1285)) - (PORT datad (1019:1019:1019) (1049:1049:1049)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (970:970:970)) - (PORT datab (645:645:645) (689:689:689)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (643:643:643) (668:668:668)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1412:1412:1412) (1468:1468:1468)) - (PORT datab (1305:1305:1305) (1363:1363:1363)) - (PORT datac (283:283:283) (380:380:380)) - (PORT datad (286:286:286) (376:376:376)) + (PORT dataa (977:977:977) (1044:1044:1044)) + (PORT datab (918:918:918) (964:964:964)) + (PORT datac (244:244:244) (297:297:297)) + (PORT datad (1588:1588:1588) (1606:1606:1606)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (691:691:691)) - (PORT datab (1094:1094:1094) (1129:1129:1129)) - (PORT datac (566:566:566) (581:581:581)) - (PORT datad (2821:2821:2821) (2883:2883:2883)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -47979,13 +40663,59 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) + (INSTANCE z80_\|data_pins_\|dout\[0\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1544:1544:1544)) - (PORT asdata (667:667:667) (689:689:689)) - (PORT clrn (1570:1570:1570) (1550:1550:1550)) - (PORT ena (1954:1954:1954) (1960:1960:1960)) + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (393:393:393) (423:423:423)) + (PORT datac (407:407:407) (468:468:468)) + (PORT datad (674:674:674) (692:692:692)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1004:1004:1004)) + (PORT datab (1377:1377:1377) (1376:1376:1376)) + (PORT datac (889:889:889) (939:939:939)) + (PORT datad (892:892:892) (894:894:894)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT asdata (1523:1523:1523) (1555:1555:1555)) + (PORT clrn (1576:1576:1576) (1555:1555:1555)) + (PORT ena (1506:1506:1506) (1484:1484:1484)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -47997,30 +40727,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (INSTANCE z80_\|pla_decode_\|Equal63\~0) (DELAY (ABSOLUTE - (PORT dataa (589:589:589) (616:616:616)) - (PORT datab (261:261:261) (343:343:343)) - (PORT datad (1208:1208:1208) (1318:1318:1318)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1988:1988:1988) (2128:2128:2128)) + (PORT datab (1534:1534:1534) (1633:1633:1633)) + (PORT datac (227:227:227) (272:272:272)) + (PORT datad (1108:1108:1108) (1149:1149:1149)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) (DELAY (ABSOLUTE - (PORT dataa (591:591:591) (619:619:619)) - (PORT datab (664:664:664) (698:698:698)) - (PORT datac (1041:1041:1041) (1120:1120:1120)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (1494:1494:1494) (1599:1599:1599)) + (PORT datab (1480:1480:1480) (1588:1588:1588)) + (PORT datac (1844:1844:1844) (1910:1910:1910)) + (PORT datad (400:400:400) (434:434:434)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (496:496:496)) + (PORT datab (712:712:712) (746:746:746)) + (PORT datac (1434:1434:1434) (1535:1535:1535)) + (PORT datad (1300:1300:1300) (1393:1393:1393)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (734:734:734)) + (PORT datac (1154:1154:1154) (1186:1186:1186)) + (PORT datad (918:918:918) (942:942:942)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48028,14 +40789,227 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (INSTANCE z80_\|alu_control_\|db\[6\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1181:1181:1181) (1193:1193:1193)) - (PORT datab (763:763:763) (777:777:777)) - (PORT datac (178:178:178) (214:214:214)) - (PORT datad (1218:1218:1218) (1304:1304:1304)) + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (661:661:661) (720:720:720)) + (PORT datac (871:871:871) (900:900:900)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (558:558:558)) + (PORT datab (903:903:903) (932:932:932)) + (PORT datac (591:591:591) (604:604:604)) + (PORT datad (1156:1156:1156) (1185:1185:1185)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (673:673:673)) + (PORT datab (955:955:955) (981:981:981)) + (PORT datac (646:646:646) (694:694:694)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (931:931:931)) + (PORT datab (243:243:243) (291:291:291)) + (PORT datac (626:626:626) (680:680:680)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (757:757:757) (859:859:859)) + (PORT datab (722:722:722) (821:821:821)) + (PORT datac (1142:1142:1142) (1227:1227:1227)) + (PORT datad (912:912:912) (978:978:978)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (707:707:707)) + (PORT datab (345:345:345) (371:371:371)) + (PORT datac (711:711:711) (812:812:812)) + (PORT datad (733:733:733) (834:834:834)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (904:904:904)) + (PORT datac (708:708:708) (801:801:801)) + (PORT datad (1136:1136:1136) (1221:1221:1221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (243:243:243)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (535:535:535)) + (PORT datab (659:659:659) (735:735:735)) + (PORT datad (723:723:723) (804:804:804)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~136) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (585:585:585)) + (PORT datab (451:451:451) (519:519:519)) + (PORT datad (651:651:651) (723:723:723)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (763:763:763)) + (PORT datab (663:663:663) (692:692:692)) + (PORT datad (833:833:833) (881:881:881)) (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (905:905:905)) + (PORT datab (628:628:628) (650:650:650)) + (PORT datad (616:616:616) (634:634:634)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (906:906:906)) + (PORT datab (874:874:874) (902:902:902)) + (PORT datac (610:610:610) (671:671:671)) + (PORT datad (657:657:657) (708:708:708)) + (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -48044,29 +41018,1781 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) (DELAY (ABSOLUTE - (PORT dataa (1058:1058:1058) (1089:1089:1089)) - (PORT datab (885:885:885) (952:952:952)) - (PORT datad (643:643:643) (667:667:667)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (822:822:822) (934:934:934)) + (PORT datab (697:697:697) (727:727:727)) + (PORT datac (960:960:960) (1039:1039:1039)) + (PORT datad (1384:1384:1384) (1501:1501:1501)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~21) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~128) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (649:649:649) (696:696:696)) - (PORT datac (1210:1210:1210) (1284:1284:1284)) - (PORT datad (1058:1058:1058) (1073:1073:1073)) + (PORT dataa (970:970:970) (1046:1046:1046)) + (PORT datab (788:788:788) (902:902:902)) + (PORT datac (903:903:903) (997:997:997)) + (PORT datad (767:767:767) (878:878:878)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (385:385:385)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (904:904:904) (977:977:977)) (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (636:636:636)) + (PORT datab (964:964:964) (1050:1050:1050)) + (PORT datad (568:568:568) (584:584:584)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1590:1590:1590) (1687:1687:1687)) + (PORT datac (744:744:744) (848:848:848)) + (PORT datad (713:713:713) (799:799:799)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (730:730:730)) + (PORT datab (1231:1231:1231) (1291:1291:1291)) + (PORT datac (920:920:920) (989:989:989)) + (PORT datad (331:331:331) (350:350:350)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (260:260:260)) + (PORT datab (965:965:965) (1053:1053:1053)) + (PORT datad (361:361:361) (388:388:388)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (1349:1349:1349) (1392:1392:1392)) + (PORT datab (1223:1223:1223) (1278:1278:1278)) + (PORT datac (216:216:216) (293:293:293)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (536:536:536)) + (PORT datab (659:659:659) (734:734:734)) + (PORT datad (725:725:725) (804:804:804)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (608:608:608)) + (PORT datab (728:728:728) (826:826:826)) + (PORT datac (1546:1546:1546) (1656:1656:1656)) + (PORT datad (580:580:580) (596:596:596)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (689:689:689)) + (PORT datab (745:745:745) (852:852:852)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~3) + (DELAY + (ABSOLUTE + (PORT datab (1510:1510:1510) (1603:1603:1603)) + (PORT datac (869:869:869) (961:961:961)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (453:453:453)) + (PORT datab (632:632:632) (659:659:659)) + (PORT datac (1349:1349:1349) (1408:1408:1408)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (903:903:903)) + (PORT datac (702:702:702) (794:794:794)) + (PORT datad (1130:1130:1130) (1214:1214:1214)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1266:1266:1266)) + (PORT datab (724:724:724) (824:824:824)) + (PORT datac (642:642:642) (670:670:670)) + (PORT datad (909:909:909) (977:977:977)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (411:411:411)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (605:605:605)) + (PORT datab (363:363:363) (394:394:394)) + (PORT datad (717:717:717) (811:811:811)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1168:1168:1168)) + (PORT datab (1142:1142:1142) (1214:1214:1214)) + (PORT datac (639:639:639) (698:698:698)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1616:1616:1616) (1662:1662:1662)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3349:3349:3349) (3565:3565:3565)) + (PORT d[1] (1605:1605:1605) (1743:1743:1743)) + (PORT d[2] (2398:2398:2398) (2522:2522:2522)) + (PORT d[3] (1878:1878:1878) (1993:1993:1993)) + (PORT d[4] (1904:1904:1904) (2011:2011:2011)) + (PORT d[5] (2072:2072:2072) (2262:2262:2262)) + (PORT d[6] (2267:2267:2267) (2352:2352:2352)) + (PORT d[7] (2156:2156:2156) (2268:2268:2268)) + (PORT d[8] (2927:2927:2927) (3117:3117:3117)) + (PORT d[9] (2257:2257:2257) (2323:2323:2323)) + (PORT d[10] (4015:4015:4015) (4256:4256:4256)) + (PORT d[11] (1788:1788:1788) (1883:1883:1883)) + (PORT d[12] (2324:2324:2324) (2423:2423:2423)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (2435:2435:2435) (2530:2530:2530)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1496:1496:1496) (1570:1570:1570)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3471:3471:3471) (3598:3598:3598)) + (PORT d[1] (1681:1681:1681) (1841:1841:1841)) + (PORT d[2] (1803:1803:1803) (1868:1868:1868)) + (PORT d[3] (2137:2137:2137) (2245:2245:2245)) + (PORT d[4] (2206:2206:2206) (2306:2306:2306)) + (PORT d[5] (1648:1648:1648) (1787:1787:1787)) + (PORT d[6] (1447:1447:1447) (1468:1468:1468)) + (PORT d[7] (1455:1455:1455) (1504:1504:1504)) + (PORT d[8] (2907:2907:2907) (3106:3106:3106)) + (PORT d[9] (2261:2261:2261) (2404:2404:2404)) + (PORT d[10] (2303:2303:2303) (2432:2432:2432)) + (PORT d[11] (2139:2139:2139) (2251:2251:2251)) + (PORT d[12] (2022:2022:2022) (2077:2077:2077)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2862:2862:2862) (2854:2854:2854)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT d[0] (4272:4272:4272) (4376:4376:4376)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1801:1801:1801)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1739:1739:1739) (1715:1715:1715)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4403:4403:4403) (4442:4442:4442)) + (PORT d[1] (4232:4232:4232) (4305:4305:4305)) + (PORT d[2] (4291:4291:4291) (4336:4336:4336)) + (PORT d[3] (4528:4528:4528) (4564:4564:4564)) + (PORT d[4] (4637:4637:4637) (4664:4664:4664)) + (PORT d[5] (4315:4315:4315) (4358:4358:4358)) + (PORT d[6] (4706:4706:4706) (4798:4798:4798)) + (PORT d[7] (4277:4277:4277) (4349:4349:4349)) + (PORT d[8] (4511:4511:4511) (4526:4526:4526)) + (PORT d[9] (4469:4469:4469) (4738:4738:4738)) + (PORT d[10] (4368:4368:4368) (4407:4407:4407)) + (PORT d[11] (4392:4392:4392) (4374:4374:4374)) + (PORT d[12] (4337:4337:4337) (4342:4342:4342)) + (PORT clk (1809:1809:1809) (1803:1803:1803)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4186:4186:4186) (4425:4425:4425)) + (PORT d[1] (2884:2884:2884) (3131:3131:3131)) + (PORT d[2] (2708:2708:2708) (2819:2819:2819)) + (PORT d[3] (2283:2283:2283) (2458:2458:2458)) + (PORT d[4] (2517:2517:2517) (2710:2710:2710)) + (PORT d[5] (2529:2529:2529) (2722:2722:2722)) + (PORT d[6] (1890:1890:1890) (2008:2008:2008)) + (PORT d[7] (2314:2314:2314) (2443:2443:2443)) + (PORT d[8] (3115:3115:3115) (3376:3376:3376)) + (PORT d[9] (2627:2627:2627) (2762:2762:2762)) + (PORT d[10] (4822:4822:4822) (5078:5078:5078)) + (PORT d[11] (1897:1897:1897) (2050:2050:2050)) + (PORT d[12] (2209:2209:2209) (2354:2354:2354)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1882:1882:1882)) + (PORT d[0] (3638:3638:3638) (3555:3555:3555)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1555:1555:1555) (1647:1647:1647)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3013:3013:3013) (3193:3193:3193)) + (PORT d[1] (2314:2314:2314) (2501:2501:2501)) + (PORT d[2] (2182:2182:2182) (2293:2293:2293)) + (PORT d[3] (1900:1900:1900) (2029:2029:2029)) + (PORT d[4] (2430:2430:2430) (2538:2538:2538)) + (PORT d[5] (1950:1950:1950) (2108:2108:2108)) + (PORT d[6] (1747:1747:1747) (1762:1762:1762)) + (PORT d[7] (2376:2376:2376) (2506:2506:2506)) + (PORT d[8] (2895:2895:2895) (3077:3077:3077)) + (PORT d[9] (1983:1983:1983) (2113:2113:2113)) + (PORT d[10] (2017:2017:2017) (2125:2125:2125)) + (PORT d[11] (2437:2437:2437) (2546:2546:2546)) + (PORT d[12] (2561:2561:2561) (2626:2626:2626)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2577:2577:2577) (2632:2632:2632)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (4055:4055:4055) (3952:3952:3952)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1804:1804:1804) (1802:1802:1802)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2048:2048:2048) (2021:2021:2021)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4402:4402:4402) (4453:4453:4453)) + (PORT d[1] (4222:4222:4222) (4285:4285:4285)) + (PORT d[2] (4296:4296:4296) (4356:4356:4356)) + (PORT d[3] (4467:4467:4467) (4510:4510:4510)) + (PORT d[4] (4361:4361:4361) (4378:4378:4378)) + (PORT d[5] (4645:4645:4645) (4676:4676:4676)) + (PORT d[6] (4445:4445:4445) (4533:4533:4533)) + (PORT d[7] (4329:4329:4329) (4398:4398:4398)) + (PORT d[8] (4517:4517:4517) (4536:4536:4536)) + (PORT d[9] (4456:4456:4456) (4702:4702:4702)) + (PORT d[10] (4317:4317:4317) (4323:4323:4323)) + (PORT d[11] (4684:4684:4684) (4714:4714:4714)) + (PORT d[12] (4438:4438:4438) (4553:4553:4553)) + (PORT clk (1810:1810:1810) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1806:1806:1806) (1804:1804:1804)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (1219:1219:1219)) + (PORT datab (947:947:947) (1002:1002:1002)) + (PORT datac (1385:1385:1385) (1418:1418:1418)) + (PORT datad (1436:1436:1436) (1475:1475:1475)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1314:1314:1314) (1369:1369:1369)) + (PORT datab (951:951:951) (1008:1008:1008)) + (PORT datac (1440:1440:1440) (1502:1502:1502)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (901:901:901) (939:939:939)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3349:3349:3349) (3527:3527:3527)) + (PORT d[1] (1734:1734:1734) (1904:1904:1904)) + (PORT d[2] (1993:1993:1993) (2068:2068:2068)) + (PORT d[3] (2163:2163:2163) (2257:2257:2257)) + (PORT d[4] (1834:1834:1834) (1918:1918:1918)) + (PORT d[5] (1363:1363:1363) (1460:1460:1460)) + (PORT d[6] (1449:1449:1449) (1474:1474:1474)) + (PORT d[7] (3354:3354:3354) (3503:3503:3503)) + (PORT d[8] (2447:2447:2447) (2653:2653:2653)) + (PORT d[9] (3517:3517:3517) (3682:3682:3682)) + (PORT d[10] (2917:2917:2917) (3102:3102:3102)) + (PORT d[11] (1485:1485:1485) (1553:1553:1553)) + (PORT d[12] (1460:1460:1460) (1502:1502:1502)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3345:3345:3345) (3355:3355:3355)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (1944:1944:1944) (1906:1906:1906)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1470:1470:1470) (1515:1515:1515)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3671:3671:3671) (3886:3886:3886)) + (PORT d[1] (1690:1690:1690) (1854:1854:1854)) + (PORT d[2] (3275:3275:3275) (3430:3430:3430)) + (PORT d[3] (2158:2158:2158) (2262:2262:2262)) + (PORT d[4] (2542:2542:2542) (2676:2676:2676)) + (PORT d[5] (1672:1672:1672) (1804:1804:1804)) + (PORT d[6] (1797:1797:1797) (1871:1871:1871)) + (PORT d[7] (1692:1692:1692) (1762:1762:1762)) + (PORT d[8] (3323:3323:3323) (3550:3550:3550)) + (PORT d[9] (2846:2846:2846) (2959:2959:2959)) + (PORT d[10] (3476:3476:3476) (3688:3688:3688)) + (PORT d[11] (1790:1790:1790) (1894:1894:1894)) + (PORT d[12] (1727:1727:1727) (1788:1788:1788)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1941:1941:1941) (1913:1913:1913)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1869:1869:1869)) + (PORT d[0] (2779:2779:2779) (2775:2775:2775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1828:1828:1828)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (986:986:986) (991:991:991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1247:1247:1247) (1305:1305:1305)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3351:3351:3351) (3542:3542:3542)) + (PORT d[1] (1331:1331:1331) (1442:1442:1442)) + (PORT d[2] (1949:1949:1949) (2052:2052:2052)) + (PORT d[3] (1549:1549:1549) (1617:1617:1617)) + (PORT d[4] (1868:1868:1868) (1957:1957:1957)) + (PORT d[5] (1641:1641:1641) (1721:1721:1721)) + (PORT d[6] (1178:1178:1178) (1228:1228:1228)) + (PORT d[7] (1451:1451:1451) (1507:1507:1507)) + (PORT d[8] (2507:2507:2507) (2697:2697:2697)) + (PORT d[9] (3505:3505:3505) (3649:3649:3649)) + (PORT d[10] (2878:2878:2878) (3044:3044:3044)) + (PORT d[11] (1237:1237:1237) (1307:1307:1307)) + (PORT d[12] (1108:1108:1108) (1125:1125:1125)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2872:2872:2872) (2909:2909:2909)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (3248:3248:3248) (3325:3325:3325)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1750:1750:1750) (1835:1835:1835)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3365:3365:3365) (3581:3581:3581)) + (PORT d[1] (1702:1702:1702) (1864:1864:1864)) + (PORT d[2] (2694:2694:2694) (2816:2816:2816)) + (PORT d[3] (2143:2143:2143) (2257:2257:2257)) + (PORT d[4] (2191:2191:2191) (2314:2314:2314)) + (PORT d[5] (2392:2392:2392) (2607:2607:2607)) + (PORT d[6] (2106:2106:2106) (2209:2209:2209)) + (PORT d[7] (2467:2467:2467) (2597:2597:2597)) + (PORT d[8] (3036:3036:3036) (3248:3248:3248)) + (PORT d[9] (2577:2577:2577) (2669:2669:2669)) + (PORT d[10] (3785:3785:3785) (4034:4034:4034)) + (PORT d[11] (1778:1778:1778) (1856:1856:1856)) + (PORT d[12] (2315:2315:2315) (2396:2396:2396)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2267:2267:2267) (2265:2265:2265)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (2685:2685:2685) (2695:2695:2695)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1829:1829:1829) (1854:1854:1854)) + (PORT datab (1177:1177:1177) (1181:1181:1181)) + (PORT datad (1696:1696:1696) (1748:1748:1748)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1535:1535:1535)) + (PORT datab (1484:1484:1484) (1501:1501:1501)) + (PORT datac (2124:2124:2124) (2189:2189:2189)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (777:777:777)) + (PORT datab (1164:1164:1164) (1255:1255:1255)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (916:916:916)) + (PORT datab (1551:1551:1551) (1605:1605:1605)) + (PORT datac (1462:1462:1462) (1538:1538:1538)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (1168:1168:1168) (1244:1244:1244)) + (PORT datab (1665:1665:1665) (1708:1708:1708)) + (PORT datac (1463:1463:1463) (1538:1538:1538)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1037:1037:1037)) + (PORT datab (1506:1506:1506) (1524:1524:1524)) + (PORT datac (236:236:236) (289:289:289)) + (PORT datad (1153:1153:1153) (1165:1165:1165)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (471:471:471)) + (PORT datab (388:388:388) (422:422:422)) + (PORT datad (671:671:671) (693:693:693)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1007:1007:1007)) + (PORT datab (922:922:922) (965:965:965)) + (PORT datac (888:888:888) (938:938:938)) + (PORT datad (898:898:898) (913:913:913)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48074,13 +42800,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) + (INSTANCE z80_\|ir_\|opcode\[4\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) + (PORT clrn (1571:1571:1571) (1550:1550:1550)) + (PORT ena (1479:1479:1479) (1488:1488:1488)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -48095,8 +42821,8 @@ (INSTANCE z80_\|pla_decode_\|Equal21\~0) (DELAY (ABSOLUTE - (PORT datac (2142:2142:2142) (2218:2218:2218)) - (PORT datad (2370:2370:2370) (2447:2447:2447)) + (PORT datac (1440:1440:1440) (1546:1546:1546)) + (PORT datad (1464:1464:1464) (1552:1552:1552)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48104,202 +42830,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) + (INSTANCE z80_\|execute_\|ctl_mRead\~5) (DELAY (ABSOLUTE - (PORT dataa (1396:1396:1396) (1416:1416:1416)) - (PORT datab (1608:1608:1608) (1686:1686:1686)) - (PORT datac (867:867:867) (892:892:892)) - (PORT datad (610:610:610) (651:651:651)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (457:457:457)) - (PORT datab (310:310:310) (406:406:406)) - (PORT datac (254:254:254) (338:338:338)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (266:266:266)) - (PORT datab (1113:1113:1113) (1135:1135:1135)) - (PORT datad (176:176:176) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1243:1243:1243) (1353:1353:1353)) - (PORT datab (607:607:607) (643:643:643)) - (PORT datac (716:716:716) (794:794:794)) - (PORT datad (822:822:822) (854:854:854)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (621:621:621)) - (PORT datab (555:555:555) (578:578:578)) - (PORT datac (1033:1033:1033) (1081:1081:1081)) - (PORT datad (1301:1301:1301) (1301:1301:1301)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1140:1140:1140) (1189:1189:1189)) - (PORT datab (723:723:723) (781:781:781)) - (PORT datac (1889:1889:1889) (1933:1933:1933)) - (PORT datad (817:817:817) (826:826:826)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (954:954:954) (987:987:987)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (684:684:684)) - (PORT datab (1252:1252:1252) (1353:1353:1353)) - (PORT datac (847:847:847) (869:869:869)) - (PORT datad (1302:1302:1302) (1301:1301:1301)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (908:908:908)) - (PORT datab (1620:1620:1620) (1666:1666:1666)) - (PORT datac (1058:1058:1058) (1088:1088:1088)) - (PORT datad (554:554:554) (558:558:558)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (619:619:619)) - (PORT datab (863:863:863) (908:908:908)) - (PORT datac (1140:1140:1140) (1140:1140:1140)) - (PORT datad (870:870:870) (920:920:920)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (562:562:562) (576:576:576)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (987:987:987) (1072:1072:1072)) - (PORT datab (708:708:708) (790:790:790)) - (PORT datac (937:937:937) (1010:1010:1010)) - (PORT datad (1112:1112:1112) (1181:1181:1181)) + (PORT dataa (1381:1381:1381) (1434:1434:1434)) + (PORT datab (981:981:981) (1038:1038:1038)) + (PORT datac (1636:1636:1636) (1757:1757:1757)) + (PORT datad (1217:1217:1217) (1298:1298:1298)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -48309,107 +42846,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~125) + (INSTANCE z80_\|execute_\|fIOWrite\~2) (DELAY (ABSOLUTE - (PORT dataa (426:426:426) (526:526:526)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datad (196:196:196) (231:231:231)) - (IOPATH dataa combout (325:325:325) (328:328:328)) + (PORT dataa (1286:1286:1286) (1367:1367:1367)) + (PORT datab (1528:1528:1528) (1599:1599:1599)) + (PORT datac (821:821:821) (830:830:830)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT datab (1536:1536:1536) (1647:1647:1647)) + (PORT datac (1349:1349:1349) (1441:1441:1441)) + (PORT datad (2442:2442:2442) (2633:2633:2633)) (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~126) - (DELAY - (ABSOLUTE - (PORT dataa (1197:1197:1197) (1273:1273:1273)) - (PORT datab (967:967:967) (1041:1041:1041)) - (PORT datad (616:616:616) (686:686:686)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (478:478:478) (557:557:557)) - (PORT datac (1064:1064:1064) (1124:1124:1124)) - (PORT datad (531:531:531) (541:541:541)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (385:385:385) (413:413:413)) - (PORT datad (710:710:710) (790:790:790)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (741:741:741)) - (PORT datab (1858:1858:1858) (1900:1900:1900)) - (PORT datac (215:215:215) (291:291:291)) - (PORT datad (861:861:861) (884:884:884)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48417,77 +42876,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~119) + (INSTANCE z80_\|execute_\|fIOWrite\~4) (DELAY (ABSOLUTE - (PORT dataa (730:730:730) (813:813:813)) - (PORT datab (647:647:647) (714:714:714)) - (PORT datac (1150:1150:1150) (1215:1215:1215)) - (PORT datad (627:627:627) (693:693:693)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~138) - (DELAY - (ABSOLUTE - (PORT dataa (1232:1232:1232) (1282:1282:1282)) - (PORT datab (272:272:272) (356:356:356)) + (PORT dataa (863:863:863) (915:915:915)) + (PORT datab (925:925:925) (953:953:953)) + (PORT datac (1717:1717:1717) (1764:1764:1764)) (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~120) + (INSTANCE z80_\|execute_\|fIOWrite\~5) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (389:389:389)) - (PORT datab (341:341:341) (372:372:372)) - (PORT datad (942:942:942) (1006:1006:1006)) + (PORT dataa (426:426:426) (455:455:455)) + (PORT datab (1184:1184:1184) (1238:1238:1238)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (360:360:360) (383:383:383)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1216:1216:1216)) - (PORT datab (470:470:470) (544:544:544)) - (PORT datac (653:653:653) (728:728:728)) - (PORT datad (936:936:936) (994:994:994)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (325:325:325)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48495,246 +42908,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~122) + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) (DELAY (ABSOLUTE - (PORT dataa (1245:1245:1245) (1305:1305:1305)) - (PORT datab (458:458:458) (533:533:533)) - (PORT datac (1297:1297:1297) (1311:1311:1311)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~123) - (DELAY - (ABSOLUTE - (PORT datab (656:656:656) (678:678:678)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (938:938:938)) - (PORT datab (414:414:414) (475:475:475)) - (PORT datac (825:825:825) (847:847:847)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT dataa (931:931:931) (953:953:953)) + (PORT datab (618:618:618) (660:660:660)) + (PORT datac (888:888:888) (936:936:936)) + (PORT datad (892:892:892) (905:905:905)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~129) + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (255:255:255)) - (PORT datab (729:729:729) (830:830:830)) - (PORT datad (349:349:349) (371:371:371)) + (PORT dataa (2004:2004:2004) (2054:2054:2054)) + (PORT datab (1141:1141:1141) (1140:1140:1140)) + (PORT datac (850:850:850) (856:856:856)) + (PORT datad (641:641:641) (681:681:681)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1558:1558:1558)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (990:990:990) (1077:1077:1077)) - (PORT datab (703:703:703) (790:790:790)) - (PORT datac (937:937:937) (1016:1016:1016)) - (PORT datad (1109:1109:1109) (1180:1180:1180)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~131) + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) (DELAY (ABSOLUTE - (PORT dataa (427:427:427) (524:524:524)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (195:195:195) (228:228:228)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (719:719:719)) - (PORT datab (890:890:890) (956:956:956)) - (PORT datac (943:943:943) (986:986:986)) - (PORT datad (825:825:825) (873:873:873)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (212:212:212) (262:262:262)) - (PORT datab (652:652:652) (678:678:678)) - (PORT datad (362:362:362) (380:380:380)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (764:764:764)) - (PORT datab (911:911:911) (925:925:925)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (746:746:746)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (2003:2003:2003) (2052:2052:2052)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (942:942:942)) - (PORT datab (608:608:608) (652:652:652)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (587:587:587) (601:601:601)) + (PORT dataa (201:201:201) (243:243:243)) + (PORT datab (596:596:596) (607:607:607)) + (PORT datac (532:532:532) (546:546:546)) + (PORT datad (180:180:180) (208:208:208)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -48742,643 +42954,15 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2443:2443:2443) (2617:2617:2617)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2845:2845:2845) (3069:3069:3069)) - (PORT d[1] (1764:1764:1764) (1918:1918:1918)) - (PORT d[2] (2808:2808:2808) (3034:3034:3034)) - (PORT d[3] (2278:2278:2278) (2485:2485:2485)) - (PORT d[4] (1916:1916:1916) (2070:2070:2070)) - (PORT d[5] (2492:2492:2492) (2660:2660:2660)) - (PORT d[6] (1998:1998:1998) (2117:2117:2117)) - (PORT d[7] (4337:4337:4337) (4519:4519:4519)) - (PORT d[8] (2440:2440:2440) (2604:2604:2604)) - (PORT d[9] (2745:2745:2745) (2859:2859:2859)) - (PORT d[10] (1916:1916:1916) (2043:2043:2043)) - (PORT d[11] (1893:1893:1893) (2055:2055:2055)) - (PORT d[12] (3387:3387:3387) (3562:3562:3562)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2686:2686:2686) (2720:2720:2720)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (2577:2577:2577) (2609:2609:2609)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2704:2704:2704) (2878:2878:2878)) - (PORT clk (1848:1848:1848) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2844:2844:2844) (3075:3075:3075)) - (PORT d[1] (1782:1782:1782) (1945:1945:1945)) - (PORT d[2] (2893:2893:2893) (3113:3113:3113)) - (PORT d[3] (2356:2356:2356) (2593:2593:2593)) - (PORT d[4] (2231:2231:2231) (2388:2388:2388)) - (PORT d[5] (3094:3094:3094) (3295:3295:3295)) - (PORT d[6] (1983:1983:1983) (2105:2105:2105)) - (PORT d[7] (3746:3746:3746) (3908:3908:3908)) - (PORT d[8] (2163:2163:2163) (2307:2307:2307)) - (PORT d[9] (2811:2811:2811) (2934:2934:2934)) - (PORT d[10] (1692:1692:1692) (1841:1841:1841)) - (PORT d[11] (1922:1922:1922) (2093:2093:2093)) - (PORT d[12] (3138:3138:3138) (3275:3275:3275)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2271:2271:2271) (2251:2251:2251)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (PORT d[0] (2571:2571:2571) (2579:2579:2579)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1808:1808:1808) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2982:2982:2982) (3193:3193:3193)) - (PORT clk (1853:1853:1853) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3490:3490:3490) (3749:3749:3749)) - (PORT d[1] (2107:2107:2107) (2306:2306:2306)) - (PORT d[2] (3412:3412:3412) (3618:3618:3618)) - (PORT d[3] (2985:2985:2985) (3269:3269:3269)) - (PORT d[4] (2532:2532:2532) (2723:2723:2723)) - (PORT d[5] (3358:3358:3358) (3590:3590:3590)) - (PORT d[6] (2289:2289:2289) (2433:2433:2433)) - (PORT d[7] (3420:3420:3420) (3554:3554:3554)) - (PORT d[8] (2178:2178:2178) (2310:2310:2310)) - (PORT d[9] (2507:2507:2507) (2596:2596:2596)) - (PORT d[10] (2318:2318:2318) (2495:2495:2495)) - (PORT d[11] (1859:1859:1859) (2017:2017:2017)) - (PORT d[12] (2797:2797:2797) (2911:2911:2911)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2292:2292:2292) (2242:2242:2242)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (PORT d[0] (2998:2998:2998) (3053:3053:3053)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1841:1841:1841)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2405:2405:2405) (2582:2582:2582)) - (PORT clk (1853:1853:1853) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2852:2852:2852) (3065:3065:3065)) - (PORT d[1] (1745:1745:1745) (1886:1886:1886)) - (PORT d[2] (2620:2620:2620) (2858:2858:2858)) - (PORT d[3] (2326:2326:2326) (2553:2553:2553)) - (PORT d[4] (2246:2246:2246) (2415:2415:2415)) - (PORT d[5] (2748:2748:2748) (2954:2954:2954)) - (PORT d[6] (1970:1970:1970) (2074:2074:2074)) - (PORT d[7] (4043:4043:4043) (4206:4206:4206)) - (PORT d[8] (2473:2473:2473) (2622:2622:2622)) - (PORT d[9] (2794:2794:2794) (2935:2935:2935)) - (PORT d[10] (1902:1902:1902) (2019:2019:2019)) - (PORT d[11] (1876:1876:1876) (2036:2036:2036)) - (PORT d[12] (3099:3099:3099) (3256:3256:3256)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2296:2296:2296) (2325:2325:2325)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (PORT d[0] (2676:2676:2676) (2738:2738:2738)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1841:1841:1841)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) (DELAY (ABSOLUTE - (PORT dataa (1434:1434:1434) (1550:1550:1550)) - (PORT datab (630:630:630) (639:639:639)) - (PORT datac (944:944:944) (1042:1042:1042)) - (PORT datad (1158:1158:1158) (1200:1200:1200)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1458:1458:1458) (1510:1510:1510)) - (PORT datab (971:971:971) (1073:1073:1073)) - (PORT datac (1141:1141:1141) (1162:1162:1162)) - (PORT datad (171:171:171) (196:196:196)) + (PORT dataa (1573:1573:1573) (1667:1667:1667)) + (PORT datab (881:881:881) (895:895:895)) + (PORT datac (1465:1465:1465) (1505:1505:1505)) + (PORT datad (1073:1073:1073) (1063:1063:1063)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -49387,23 +42971,298 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) (DELAY (ABSOLUTE - (PORT d[0] (1074:1074:1074) (1153:1153:1153)) - (PORT d[1] (2831:2831:2831) (3099:3099:3099)) - (PORT d[2] (1986:1986:1986) (2118:2118:2118)) - (PORT d[3] (725:725:725) (773:773:773)) - (PORT d[4] (707:707:707) (738:738:738)) - (PORT d[5] (1585:1585:1585) (1671:1671:1671)) - (PORT d[6] (2942:2942:2942) (3097:3097:3097)) - (PORT d[7] (2027:2027:2027) (2127:2127:2127)) - (PORT d[8] (4009:4009:4009) (4252:4252:4252)) - (PORT d[9] (850:850:850) (860:860:860)) - (PORT d[10] (2565:2565:2565) (2755:2755:2755)) - (PORT d[11] (2245:2245:2245) (2463:2463:2463)) - (PORT d[12] (1365:1365:1365) (1359:1359:1359)) + (PORT dataa (637:637:637) (652:652:652)) + (PORT datab (877:877:877) (906:906:906)) + (PORT datac (864:864:864) (874:874:874)) + (PORT datad (1193:1193:1193) (1249:1249:1249)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1291:1291:1291) (1310:1310:1310)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (219:219:219) (289:289:289)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT asdata (567:567:567) (645:645:645)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (890:890:890)) + (PORT datab (351:351:351) (390:390:390)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (1754:1754:1754) (1854:1854:1854)) + (PORT datab (1594:1594:1594) (1729:1729:1729)) + (PORT datac (1191:1191:1191) (1256:1256:1256)) + (PORT datad (1224:1224:1224) (1308:1308:1308)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1170:1170:1170) (1220:1220:1220)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4199:4199:4199) (4456:4456:4456)) + (PORT d[1] (2869:2869:2869) (3121:3121:3121)) + (PORT d[2] (3253:3253:3253) (3349:3349:3349)) + (PORT d[3] (2536:2536:2536) (2717:2717:2717)) + (PORT d[4] (2232:2232:2232) (2420:2420:2420)) + (PORT d[5] (2568:2568:2568) (2749:2749:2749)) + (PORT d[6] (1862:1862:1862) (1979:1979:1979)) + (PORT d[7] (2324:2324:2324) (2461:2461:2461)) + (PORT d[8] (3106:3106:3106) (3383:3383:3383)) + (PORT d[9] (2915:2915:2915) (3048:3048:3048)) + (PORT d[10] (4807:4807:4807) (5077:5077:5077)) + (PORT d[11] (2186:2186:2186) (2342:2342:2342)) + (PORT d[12] (2200:2200:2200) (2338:2338:2338)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1968:1968:1968) (1944:1944:1944)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (2326:2326:2326) (2304:2304:2304)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1193:1193:1193) (1222:1222:1222)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4194:4194:4194) (4449:4449:4449)) + (PORT d[1] (2891:2891:2891) (3144:3144:3144)) + (PORT d[2] (2764:2764:2764) (2858:2858:2858)) + (PORT d[3] (2536:2536:2536) (2713:2713:2713)) + (PORT d[4] (2253:2253:2253) (2443:2443:2443)) + (PORT d[5] (2541:2541:2541) (2717:2717:2717)) + (PORT d[6] (1898:1898:1898) (2008:2008:2008)) + (PORT d[7] (2297:2297:2297) (2428:2428:2428)) + (PORT d[8] (3124:3124:3124) (3401:3401:3401)) + (PORT d[9] (2609:2609:2609) (2741:2741:2741)) + (PORT d[10] (4803:4803:4803) (5068:5068:5068)) + (PORT d[11] (1891:1891:1891) (2036:2036:2036)) + (PORT d[12] (2208:2208:2208) (2353:2353:2353)) (PORT clk (1855:1855:1855) (1880:1880:1880)) ) ) @@ -49413,27 +43272,70 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) (DELAY (ABSOLUTE + (PORT d[0] (2383:2383:2383) (2365:2365:2365)) (PORT clk (1855:1855:1855) (1880:1880:1880)) - (PORT d[0] (1957:1957:1957) (2005:2005:2005)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT d[0] (2857:2857:2857) (2839:2839:2839)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1881:1881:1881)) + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1818:1818:1818) (1843:1843:1843)) @@ -49447,7 +43349,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1003:1003:1003) (1006:1006:1006)) @@ -49456,7 +43358,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1004:1004:1004) (1007:1007:1007)) @@ -49465,7 +43367,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1004:1004:1004) (1007:1007:1007)) @@ -49475,7 +43377,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1004:1004:1004) (1007:1007:1007)) @@ -49485,11 +43387,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1576:1576:1576) (1686:1686:1686)) - (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT d[0] (880:880:880) (918:918:918)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -49498,23 +43400,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1682:1682:1682) (1816:1816:1816)) - (PORT d[1] (1727:1727:1727) (1820:1820:1820)) - (PORT d[2] (3374:3374:3374) (3700:3700:3700)) - (PORT d[3] (2567:2567:2567) (2757:2757:2757)) - (PORT d[4] (2574:2574:2574) (2781:2781:2781)) - (PORT d[5] (1826:1826:1826) (1959:1959:1959)) - (PORT d[6] (2273:2273:2273) (2406:2406:2406)) - (PORT d[7] (2968:2968:2968) (3135:3135:3135)) - (PORT d[8] (2077:2077:2077) (2192:2192:2192)) - (PORT d[9] (4076:4076:4076) (4203:4203:4203)) - (PORT d[10] (2233:2233:2233) (2334:2334:2334)) - (PORT d[11] (3066:3066:3066) (3278:3278:3278)) - (PORT d[12] (3337:3337:3337) (3464:3464:3464)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) + (PORT d[0] (1334:1334:1334) (1380:1380:1380)) + (PORT d[1] (2044:2044:2044) (2248:2248:2248)) + (PORT d[2] (3016:3016:3016) (3126:3126:3126)) + (PORT d[3] (2584:2584:2584) (2783:2783:2783)) + (PORT d[4] (2569:2569:2569) (2761:2761:2761)) + (PORT d[5] (2836:2836:2836) (3029:3029:3029)) + (PORT d[6] (1949:1949:1949) (2075:2075:2075)) + (PORT d[7] (2609:2609:2609) (2760:2760:2760)) + (PORT d[8] (3388:3388:3388) (3680:3680:3680)) + (PORT d[9] (2935:2935:2935) (3067:3067:3067)) + (PORT d[10] (5109:5109:5109) (5374:5374:5374)) + (PORT d[11] (1927:1927:1927) (2066:2066:2066)) + (PORT d[12] (1910:1910:1910) (2033:2033:2033)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -49523,11 +43425,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1744:1744:1744) (1745:1745:1745)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) + (PORT d[0] (1228:1228:1228) (1223:1223:1223)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -49536,17 +43438,2546 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1866:1866:1866) (1893:1893:1893)) - (PORT d[0] (2622:2622:2622) (2637:2637:2637)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2528:2528:2528) (2496:2496:2496)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1430:1430:1430) (1510:1510:1510)) + (PORT datab (977:977:977) (1037:1037:1037)) + (PORT datac (1084:1084:1084) (1106:1106:1106)) + (PORT datad (833:833:833) (863:863:863)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1183:1183:1183) (1216:1216:1216)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3355:3355:3355) (3572:3572:3572)) + (PORT d[1] (1697:1697:1697) (1865:1865:1865)) + (PORT d[2] (2991:2991:2991) (3133:3133:3133)) + (PORT d[3] (2197:2197:2197) (2290:2290:2290)) + (PORT d[4] (2502:2502:2502) (2653:2653:2653)) + (PORT d[5] (2405:2405:2405) (2601:2601:2601)) + (PORT d[6] (2102:2102:2102) (2200:2200:2200)) + (PORT d[7] (2478:2478:2478) (2588:2588:2588)) + (PORT d[8] (3018:3018:3018) (3244:3244:3244)) + (PORT d[9] (2534:2534:2534) (2624:2624:2624)) + (PORT d[10] (3776:3776:3776) (4011:4011:4011)) + (PORT d[11] (1726:1726:1726) (1804:1804:1804)) + (PORT d[12] (2323:2323:2323) (2409:2409:2409)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2206:2206:2206) (2199:2199:2199)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (2749:2749:2749) (2715:2715:2715)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1449:1449:1449) (1499:1499:1499)) + (PORT datab (1154:1154:1154) (1180:1180:1180)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1425:1425:1425) (1425:1425:1425)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1785:1785:1785) (1834:1834:1834)) + (PORT clk (1844:1844:1844) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3330:3330:3330) (3510:3510:3510)) + (PORT d[1] (2345:2345:2345) (2548:2548:2548)) + (PORT d[2] (2224:2224:2224) (2307:2307:2307)) + (PORT d[3] (1895:1895:1895) (2026:2026:2026)) + (PORT d[4] (2445:2445:2445) (2553:2553:2553)) + (PORT d[5] (1968:1968:1968) (2118:2118:2118)) + (PORT d[6] (1422:1422:1422) (1463:1463:1463)) + (PORT d[7] (1469:1469:1469) (1501:1501:1501)) + (PORT d[8] (2903:2903:2903) (3100:3100:3100)) + (PORT d[9] (1984:1984:1984) (2114:2114:2114)) + (PORT d[10] (1991:1991:1991) (2095:2095:2095)) + (PORT d[11] (1441:1441:1441) (1479:1479:1479)) + (PORT d[12] (2020:2020:2020) (2065:2065:2065)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2835:2835:2835) (2823:2823:2823)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1873:1873:1873)) + (PORT d[0] (3960:3960:3960) (4062:4062:4062)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1799:1799:1799) (1798:1798:1798)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1198:1198:1198) (1181:1181:1181)) + (PORT clk (1809:1809:1809) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4418:4418:4418) (4468:4468:4468)) + (PORT d[1] (4222:4222:4222) (4280:4280:4280)) + (PORT d[2] (4287:4287:4287) (4334:4334:4334)) + (PORT d[3] (4530:4530:4530) (4580:4580:4580)) + (PORT d[4] (4340:4340:4340) (4354:4354:4354)) + (PORT d[5] (4359:4359:4359) (4381:4381:4381)) + (PORT d[6] (4659:4659:4659) (4748:4748:4748)) + (PORT d[7] (4373:4373:4373) (4445:4445:4445)) + (PORT d[8] (4529:4529:4529) (4546:4546:4546)) + (PORT d[9] (4710:4710:4710) (4968:4968:4968)) + (PORT d[10] (4380:4380:4380) (4418:4418:4418)) + (PORT d[11] (4364:4364:4364) (4385:4385:4385)) + (PORT d[12] (4681:4681:4681) (4658:4658:4658)) + (PORT clk (1805:1805:1805) (1800:1800:1800)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1804:1804:1804)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2604:2604:2604) (2682:2682:2682)) + (PORT d[1] (2063:2063:2063) (2283:2283:2283)) + (PORT d[2] (2289:2289:2289) (2441:2441:2441)) + (PORT d[3] (2285:2285:2285) (2377:2377:2377)) + (PORT d[4] (2950:2950:2950) (3220:3220:3220)) + (PORT d[5] (2075:2075:2075) (2260:2260:2260)) + (PORT d[6] (1854:1854:1854) (1963:1963:1963)) + (PORT d[7] (2555:2555:2555) (2658:2658:2658)) + (PORT d[8] (2752:2752:2752) (3006:3006:3006)) + (PORT d[9] (1553:1553:1553) (1673:1673:1673)) + (PORT d[10] (1845:1845:1845) (1962:1962:1962)) + (PORT d[11] (2882:2882:2882) (3002:3002:3002)) + (PORT d[12] (1537:1537:1537) (1640:1640:1640)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1892:1892:1892)) + (PORT d[0] (2184:2184:2184) (2245:2245:2245)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1893:1893:1893)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1855:1855:1855)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1018:1018:1018)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1019:1019:1019)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1019:1019:1019)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1019:1019:1019)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3543:3543:3543) (3733:3733:3733)) + (PORT d[1] (1715:1715:1715) (1880:1880:1880)) + (PORT d[2] (2685:2685:2685) (2807:2807:2807)) + (PORT d[3] (2133:2133:2133) (2228:2228:2228)) + (PORT d[4] (1902:1902:1902) (2026:2026:2026)) + (PORT d[5] (2379:2379:2379) (2573:2573:2573)) + (PORT d[6] (2329:2329:2329) (2418:2418:2418)) + (PORT d[7] (2458:2458:2458) (2570:2570:2570)) + (PORT d[8] (2691:2691:2691) (2888:2888:2888)) + (PORT d[9] (2519:2519:2519) (2590:2590:2590)) + (PORT d[10] (3815:3815:3815) (4071:4071:4071)) + (PORT d[11] (1813:1813:1813) (1894:1894:1894)) + (PORT d[12] (2372:2372:2372) (2459:2459:2459)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (2529:2529:2529) (2434:2434:2434)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1649:1649:1649) (1736:1736:1736)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2915:2915:2915) (3030:3030:3030)) + (PORT d[1] (2366:2366:2366) (2611:2611:2611)) + (PORT d[2] (2597:2597:2597) (2777:2777:2777)) + (PORT d[3] (2017:2017:2017) (2075:2075:2075)) + (PORT d[4] (2919:2919:2919) (3173:3173:3173)) + (PORT d[5] (2370:2370:2370) (2578:2578:2578)) + (PORT d[6] (1866:1866:1866) (1962:1962:1962)) + (PORT d[7] (1642:1642:1642) (1751:1751:1751)) + (PORT d[8] (3027:3027:3027) (3282:3282:3282)) + (PORT d[9] (1219:1219:1219) (1304:1304:1304)) + (PORT d[10] (2155:2155:2155) (2296:2296:2296)) + (PORT d[11] (3694:3694:3694) (3833:3833:3833)) + (PORT d[12] (1894:1894:1894) (1995:1995:1995)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2802:2802:2802) (2787:2787:2787)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (3138:3138:3138) (3102:3102:3102)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1813:1813:1813)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2176:2176:2176) (2231:2231:2231)) + (PORT clk (1825:1825:1825) (1819:1819:1819)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4610:4610:4610) (4658:4658:4658)) + (PORT d[1] (4157:4157:4157) (4160:4160:4160)) + (PORT d[2] (4196:4196:4196) (4284:4284:4284)) + (PORT d[3] (4718:4718:4718) (4716:4716:4716)) + (PORT d[4] (4356:4356:4356) (4386:4386:4386)) + (PORT d[5] (4428:4428:4428) (4381:4381:4381)) + (PORT d[6] (4640:4640:4640) (4703:4703:4703)) + (PORT d[7] (4181:4181:4181) (4140:4140:4140)) + (PORT d[8] (4708:4708:4708) (4720:4720:4720)) + (PORT d[9] (4594:4594:4594) (4806:4806:4806)) + (PORT d[10] (4407:4407:4407) (4422:4422:4422)) + (PORT d[11] (4504:4504:4504) (4555:4555:4555)) + (PORT d[12] (4480:4480:4480) (4497:4497:4497)) + (PORT clk (1821:1821:1821) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1819:1819:1819)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1815:1815:1815)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1424:1424:1424) (1496:1496:1496)) + (PORT datab (973:973:973) (1052:1052:1052)) + (PORT datac (1431:1431:1431) (1467:1467:1467)) + (PORT datad (1389:1389:1389) (1443:1443:1443)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1500:1500:1500) (1615:1615:1615)) + (PORT datab (972:972:972) (1051:1051:1051)) + (PORT datac (1456:1456:1456) (1510:1510:1510)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (1480:1480:1480) (1579:1579:1579)) + (PORT datab (1206:1206:1206) (1296:1296:1296)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (1382:1382:1382) (1396:1396:1396)) + (PORT datab (885:885:885) (963:963:963)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1346:1346:1346) (1371:1371:1371)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~102) + (DELAY + (ABSOLUTE + (PORT datac (191:191:191) (224:224:224)) + (PORT datad (781:781:781) (792:792:792)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (1025:1025:1025)) + (PORT datab (229:229:229) (272:272:272)) + (PORT datac (239:239:239) (287:287:287)) + (PORT datad (858:858:858) (899:899:899)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (1164:1164:1164) (1192:1192:1192)) + (PORT datac (942:942:942) (1003:1003:1003)) + (PORT datad (367:367:367) (390:390:390)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (267:267:267) (355:355:355)) + (PORT datab (711:711:711) (731:731:731)) + (PORT datac (879:879:879) (883:883:883)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (546:546:546) (581:581:581)) + (PORT clrn (1579:1579:1579) (1558:1558:1558)) + (PORT ena (1501:1501:1501) (1488:1488:1488)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (814:814:814)) + (PORT datab (1235:1235:1235) (1355:1355:1355)) + (PORT datac (985:985:985) (1064:1064:1064)) + (PORT datad (1322:1322:1322) (1437:1437:1437)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (756:756:756)) + (PORT datab (994:994:994) (1104:1104:1104)) + (PORT datac (1148:1148:1148) (1191:1191:1191)) + (PORT datad (1194:1194:1194) (1254:1254:1254)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (717:717:717) (780:780:780)) + (PORT datab (376:376:376) (417:417:417)) + (PORT datac (1100:1100:1100) (1123:1123:1123)) + (PORT datad (1740:1740:1740) (1811:1811:1811)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (999:999:999) (1037:1037:1037)) + (PORT datab (1148:1148:1148) (1181:1181:1181)) + (PORT datac (1118:1118:1118) (1156:1156:1156)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1747:1747:1747) (1768:1768:1768)) + (PORT datab (1063:1063:1063) (1181:1181:1181)) + (PORT datac (1205:1205:1205) (1277:1277:1277)) + (PORT datad (1152:1152:1152) (1188:1188:1188)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1745:1745:1745) (1764:1764:1764)) + (PORT datab (372:372:372) (420:420:420)) + (PORT datac (1499:1499:1499) (1632:1632:1632)) + (PORT datad (1111:1111:1111) (1140:1140:1140)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (279:279:279)) + (PORT datab (1037:1037:1037) (1088:1088:1088)) + (PORT datac (1095:1095:1095) (1134:1134:1134)) + (PORT datad (1073:1073:1073) (1110:1110:1110)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (904:904:904)) + (PORT datab (1509:1509:1509) (1569:1569:1569)) + (PORT datac (829:829:829) (848:848:848)) + (PORT datad (860:860:860) (875:875:875)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT datac (1078:1078:1078) (1174:1174:1174)) + (PORT datad (1031:1031:1031) (1116:1116:1116)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (436:436:436)) + (PORT datab (968:968:968) (1056:1056:1056)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (280:280:280)) + (PORT datab (775:775:775) (874:874:874)) + (PORT datac (1366:1366:1366) (1453:1453:1453)) + (PORT datad (1546:1546:1546) (1637:1637:1637)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (379:379:379)) + (PORT datab (222:222:222) (260:260:260)) + (PORT datad (739:739:739) (824:824:824)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (2308:2308:2308) (2488:2488:2488)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datac (574:574:574) (621:621:621)) + (PORT datad (1325:1325:1325) (1345:1345:1345)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (965:965:965) (1048:1048:1048)) + (PORT datad (728:728:728) (839:839:839)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (622:622:622) (672:672:672)) + (PORT datad (961:961:961) (1040:1040:1040)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (568:568:568)) + (PORT datab (664:664:664) (740:740:740)) + (PORT datac (606:606:606) (671:671:671)) + (PORT datad (721:721:721) (799:799:799)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~131) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (538:538:538)) + (PORT datab (342:342:342) (377:377:377)) + (PORT datad (260:260:260) (338:338:338)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (908:908:908)) + (PORT datab (1091:1091:1091) (1095:1095:1095)) + (PORT datad (617:617:617) (636:636:636)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1224:1224:1224)) + (PORT datab (240:240:240) (321:321:321)) + (PORT datac (568:568:568) (626:626:626)) + (PORT datad (553:553:553) (572:572:572)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT datac (1077:1077:1077) (1170:1170:1170)) + (PORT datad (1031:1031:1031) (1112:1112:1112)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (285:285:285)) + (PORT datab (390:390:390) (410:410:410)) + (PORT datac (918:918:918) (988:988:988)) + (PORT datad (328:328:328) (348:348:348)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT datab (969:969:969) (1059:1059:1059)) + (PORT datad (338:338:338) (357:357:357)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (439:439:439)) + (PORT datab (969:969:969) (1059:1059:1059)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datac (559:559:559) (587:587:587)) + (PORT datad (556:556:556) (572:572:572)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1040:1040:1040)) + (PORT datab (793:793:793) (911:911:911)) + (PORT datac (907:907:907) (1000:1000:1000)) + (PORT datad (764:764:764) (871:871:871)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (395:395:395)) + (PORT datab (737:737:737) (825:825:825)) + (PORT datad (589:589:589) (600:600:600)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (262:262:262)) + (PORT datab (201:201:201) (241:241:241)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT datac (244:244:244) (324:324:324)) + (PORT datad (831:831:831) (879:879:879)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (764:764:764)) + (PORT datab (349:349:349) (382:382:382)) + (PORT datac (658:658:658) (727:727:727)) + (PORT datad (638:638:638) (705:705:705)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (471:471:471) (546:546:546)) + (PORT datac (352:352:352) (381:381:381)) + (PORT datad (197:197:197) (232:232:232)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (824:824:824)) + (PORT datab (493:493:493) (577:577:577)) + (PORT datac (572:572:572) (608:608:608)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (849:849:849)) + (PORT datab (773:773:773) (872:872:872)) + (PORT datad (959:959:959) (1036:1036:1036)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (370:370:370)) + (PORT datad (635:635:635) (675:675:675)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1664:1664:1664) (1689:1689:1689)) + (PORT datab (618:618:618) (678:678:678)) + (PORT datac (1058:1058:1058) (1128:1128:1128)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (634:634:634) (655:655:655)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (589:589:589) (603:603:603)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~104) + (DELAY + (ABSOLUTE + (PORT datab (1233:1233:1233) (1299:1299:1299)) + (PORT datac (655:655:655) (738:738:738)) + (PORT datad (1395:1395:1395) (1412:1412:1412)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (947:947:947) (974:974:974)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1333:1333:1333) (1379:1379:1379)) + (PORT d[1] (1965:1965:1965) (2168:2168:2168)) + (PORT d[2] (3064:3064:3064) (3182:3182:3182)) + (PORT d[3] (2837:2837:2837) (3038:3038:3038)) + (PORT d[4] (2548:2548:2548) (2738:2738:2738)) + (PORT d[5] (2841:2841:2841) (3039:3039:3039)) + (PORT d[6] (1923:1923:1923) (2045:2045:2045)) + (PORT d[7] (2590:2590:2590) (2742:2742:2742)) + (PORT d[8] (3415:3415:3415) (3712:3712:3712)) + (PORT d[9] (1607:1607:1607) (1686:1686:1686)) + (PORT d[10] (5088:5088:5088) (5355:5355:5355)) + (PORT d[11] (1909:1909:1909) (2057:2057:2057)) + (PORT d[12] (1909:1909:1909) (2032:2032:2032)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1221:1221:1221) (1217:1217:1217)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (2517:2517:2517) (2474:2474:2474)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1836:1836:1836)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (704:704:704) (727:727:727)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1274:1274:1274) (1301:1301:1301)) + (PORT d[1] (2099:2099:2099) (2330:2330:2330)) + (PORT d[2] (1248:1248:1248) (1286:1286:1286)) + (PORT d[3] (1307:1307:1307) (1357:1357:1357)) + (PORT d[4] (2610:2610:2610) (2833:2833:2833)) + (PORT d[5] (3471:3471:3471) (3676:3676:3676)) + (PORT d[6] (1323:1323:1323) (1420:1420:1420)) + (PORT d[7] (2887:2887:2887) (3061:3061:3061)) + (PORT d[8] (985:985:985) (1023:1023:1023)) + (PORT d[9] (1296:1296:1296) (1359:1359:1359)) + (PORT d[10] (1357:1357:1357) (1455:1455:1455)) + (PORT d[11] (2476:2476:2476) (2609:2609:2609)) + (PORT d[12] (1610:1610:1610) (1711:1711:1711)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (979:979:979) (953:953:953)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT d[0] (1492:1492:1492) (1460:1460:1460)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (947:947:947) (973:973:973)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1343:1343:1343) (1413:1413:1413)) + (PORT d[1] (3163:3163:3163) (3436:3436:3436)) + (PORT d[2] (3532:3532:3532) (3625:3625:3625)) + (PORT d[3] (2837:2837:2837) (3043:3043:3043)) + (PORT d[4] (2558:2558:2558) (2781:2781:2781)) + (PORT d[5] (2869:2869:2869) (3072:3072:3072)) + (PORT d[6] (1676:1676:1676) (1759:1759:1759)) + (PORT d[7] (1505:1505:1505) (1586:1586:1586)) + (PORT d[8] (3442:3442:3442) (3720:3720:3720)) + (PORT d[9] (3231:3231:3231) (3382:3382:3382)) + (PORT d[10] (5089:5089:5089) (5374:5374:5374)) + (PORT d[11] (1942:1942:1942) (2100:2100:2100)) + (PORT d[12] (1901:1901:1901) (2017:2017:2017)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1717:1717:1717) (1648:1648:1648)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2052:2052:2052) (2017:2017:2017)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1152:1152:1152) (1168:1168:1168)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3672:3672:3672) (3852:3852:3852)) + (PORT d[1] (1686:1686:1686) (1851:1851:1851)) + (PORT d[2] (1971:1971:1971) (2046:2046:2046)) + (PORT d[3] (2163:2163:2163) (2263:2263:2263)) + (PORT d[4] (2177:2177:2177) (2306:2306:2306)) + (PORT d[5] (1373:1373:1373) (1485:1485:1485)) + (PORT d[6] (1492:1492:1492) (1541:1541:1541)) + (PORT d[7] (1731:1731:1731) (1802:1802:1802)) + (PORT d[8] (3606:3606:3606) (3855:3855:3855)) + (PORT d[9] (3144:3144:3144) (3281:3281:3281)) + (PORT d[10] (3176:3176:3176) (3363:3363:3363)) + (PORT d[11] (2072:2072:2072) (2195:2195:2195)) + (PORT d[12] (1417:1417:1417) (1455:1455:1455)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1662:1662:1662) (1645:1645:1645)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (2686:2686:2686) (2681:2681:2681)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1035:1035:1035)) + (PORT datab (1190:1190:1190) (1238:1238:1238)) + (PORT datac (820:820:820) (836:836:836)) + (PORT datad (1047:1047:1047) (1047:1047:1047)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1168:1168:1168)) + (PORT datab (1602:1602:1602) (1692:1692:1692)) + (PORT datac (1163:1163:1163) (1158:1158:1158)) + (PORT datad (312:312:312) (328:328:328)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3036:3036:3036) (3209:3209:3209)) + (PORT d[1] (2901:2901:2901) (3127:3127:3127)) + (PORT d[2] (1663:1663:1663) (1761:1761:1761)) + (PORT d[3] (1512:1512:1512) (1583:1583:1583)) + (PORT d[4] (1858:1858:1858) (1967:1967:1967)) + (PORT d[5] (1341:1341:1341) (1451:1451:1451)) + (PORT d[6] (1141:1141:1141) (1162:1162:1162)) + (PORT d[7] (1474:1474:1474) (1532:1532:1532)) + (PORT d[8] (2472:2472:2472) (2678:2678:2678)) + (PORT d[9] (3827:3827:3827) (3998:3998:3998)) + (PORT d[10] (2576:2576:2576) (2725:2725:2725)) + (PORT d[11] (1801:1801:1801) (1882:1882:1882)) + (PORT d[12] (2041:2041:2041) (2064:2064:2064)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT d[0] (1267:1267:1267) (1274:1274:1274)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1634:1634:1634) (1680:1680:1680)) + (PORT clk (1866:1866:1866) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2598:2598:2598) (2696:2696:2696)) + (PORT d[1] (2070:2070:2070) (2298:2298:2298)) + (PORT d[2] (2574:2574:2574) (2730:2730:2730)) + (PORT d[3] (2266:2266:2266) (2351:2351:2351)) + (PORT d[4] (2949:2949:2949) (3214:3214:3214)) + (PORT d[5] (2088:2088:2088) (2293:2293:2293)) + (PORT d[6] (1571:1571:1571) (1677:1677:1677)) + (PORT d[7] (2825:2825:2825) (2918:2918:2918)) + (PORT d[8] (2797:2797:2797) (3045:3045:3045)) + (PORT d[9] (2076:2076:2076) (2185:2185:2185)) + (PORT d[10] (1851:1851:1851) (1973:1973:1973)) + (PORT d[11] (3686:3686:3686) (3803:3803:3803)) + (PORT d[12] (1884:1884:1884) (1967:1967:1967)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3175:3175:3175) (3145:3145:3145)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT d[0] (2870:2870:2870) (2913:2913:2913)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1867:1867:1867) (1894:1894:1894)) @@ -49556,7 +45987,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1867:1867:1867) (1894:1894:1894)) @@ -49566,7 +45997,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1867:1867:1867) (1894:1894:1894)) @@ -49576,7 +46007,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1867:1867:1867) (1894:1894:1894)) @@ -49586,7 +46017,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1821:1821:1821) (1818:1818:1818)) @@ -49600,10 +46031,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (3429:3429:3429) (3540:3540:3540)) + (PORT d[0] (2160:2160:2160) (2219:2219:2219)) (PORT clk (1831:1831:1831) (1824:1824:1824)) ) ) @@ -49613,22 +46044,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1949:1949:1949) (2016:2016:2016)) - (PORT d[1] (1950:1950:1950) (2044:2044:2044)) - (PORT d[2] (1829:1829:1829) (1895:1895:1895)) - (PORT d[3] (1934:1934:1934) (2094:2094:2094)) - (PORT d[4] (1894:1894:1894) (2013:2013:2013)) - (PORT d[5] (2135:2135:2135) (2220:2220:2220)) - (PORT d[6] (1755:1755:1755) (1823:1823:1823)) - (PORT d[7] (2039:2039:2039) (2156:2156:2156)) - (PORT d[8] (2023:2023:2023) (2092:2092:2092)) - (PORT d[9] (2052:2052:2052) (2088:2088:2088)) - (PORT d[10] (2154:2154:2154) (2264:2264:2264)) - (PORT d[11] (1929:1929:1929) (1995:1995:1995)) - (PORT d[12] (1888:1888:1888) (1961:1961:1961)) + (PORT d[0] (4537:4537:4537) (4504:4504:4504)) + (PORT d[1] (4325:4325:4325) (4356:4356:4356)) + (PORT d[2] (4543:4543:4543) (4609:4609:4609)) + (PORT d[3] (4478:4478:4478) (4499:4499:4499)) + (PORT d[4] (4324:4324:4324) (4305:4305:4305)) + (PORT d[5] (4367:4367:4367) (4410:4410:4410)) + (PORT d[6] (4631:4631:4631) (4697:4697:4697)) + (PORT d[7] (4151:4151:4151) (4116:4116:4116)) + (PORT d[8] (4445:4445:4445) (4476:4476:4476)) + (PORT d[9] (4629:4629:4629) (4823:4823:4823)) + (PORT d[10] (4475:4475:4475) (4482:4482:4482)) + (PORT d[11] (4668:4668:4668) (4671:4671:4671)) + (PORT d[12] (4491:4491:4491) (4515:4515:4515)) (PORT clk (1827:1827:1827) (1820:1820:1820)) ) ) @@ -49638,7 +46069,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1831:1831:1831) (1824:1824:1824)) @@ -49647,7 +46078,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) (DELAY (ABSOLUTE (PORT clk (1832:1832:1832) (1825:1825:1825)) @@ -49657,7 +46088,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1832:1832:1832) (1825:1825:1825)) @@ -49666,7 +46097,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1832:1832:1832) (1825:1825:1825)) @@ -49676,7 +46107,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1832:1832:1832) (1825:1825:1825)) @@ -49684,25 +46115,29 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1345:1345:1345) (1398:1398:1398)) + (PORT datab (279:279:279) (367:367:367)) + (PORT datac (1350:1350:1350) (1376:1376:1376)) + (PORT datad (1465:1465:1465) (1526:1526:1526)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (424:424:424) (453:453:453)) - (PORT d[1] (3375:3375:3375) (3656:3656:3656)) - (PORT d[2] (1906:1906:1906) (1993:1993:1993)) - (PORT d[3] (3983:3983:3983) (4280:4280:4280)) - (PORT d[4] (3107:3107:3107) (3335:3335:3335)) - (PORT d[5] (986:986:986) (1025:1025:1025)) - (PORT d[6] (3210:3210:3210) (3376:3376:3376)) - (PORT d[7] (641:641:641) (660:660:660)) - (PORT d[8] (980:980:980) (1013:1013:1013)) - (PORT d[9] (2712:2712:2712) (2800:2800:2800)) - (PORT d[10] (917:917:917) (948:948:948)) - (PORT d[11] (1477:1477:1477) (1518:1518:1518)) - (PORT d[12] (2076:2076:2076) (2144:2144:2144)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT d[0] (1584:1584:1584) (1645:1645:1645)) + (PORT clk (1870:1870:1870) (1897:1897:1897)) ) ) (TIMINGCHECK @@ -49711,30 +46146,98 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1880:1880:1880)) - (PORT d[0] (2635:2635:2635) (2563:2563:2563)) + (PORT d[0] (2320:2320:2320) (2387:2387:2387)) + (PORT d[1] (2054:2054:2054) (2261:2261:2261)) + (PORT d[2] (2320:2320:2320) (2490:2490:2490)) + (PORT d[3] (2275:2275:2275) (2437:2437:2437)) + (PORT d[4] (2932:2932:2932) (3188:3188:3188)) + (PORT d[5] (2382:2382:2382) (2576:2576:2576)) + (PORT d[6] (1862:1862:1862) (1984:1984:1984)) + (PORT d[7] (2524:2524:2524) (2619:2619:2619)) + (PORT d[8] (3132:3132:3132) (3396:3396:3396)) + (PORT d[9] (1782:1782:1782) (1897:1897:1897)) + (PORT d[10] (1810:1810:1810) (1908:1908:1908)) + (PORT d[11] (2927:2927:2927) (3048:3048:3048)) + (PORT d[12] (1876:1876:1876) (1989:1989:1989)) + (PORT clk (1867:1867:1867) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2203:2203:2203) (2195:2195:2195)) + (PORT clk (1867:1867:1867) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1897:1897:1897)) + (PORT d[0] (3171:3171:3171) (3110:3110:3110)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1881:1881:1881)) + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1822:1822:1822)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -49745,49 +46248,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1903:1903:1903) (2034:2034:2034)) - (PORT clk (1870:1870:1870) (1896:1896:1896)) + (PORT d[0] (2476:2476:2476) (2528:2528:2528)) + (PORT clk (1835:1835:1835) (1828:1828:1828)) ) ) (TIMINGCHECK @@ -49796,23 +46261,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2976:2976:2976) (3123:3123:3123)) - (PORT d[1] (1703:1703:1703) (1797:1797:1797)) - (PORT d[2] (3298:3298:3298) (3581:3581:3581)) - (PORT d[3] (2372:2372:2372) (2600:2600:2600)) - (PORT d[4] (2598:2598:2598) (2803:2803:2803)) - (PORT d[5] (2115:2115:2115) (2261:2261:2261)) - (PORT d[6] (2340:2340:2340) (2474:2474:2474)) - (PORT d[7] (2932:2932:2932) (3093:3093:3093)) - (PORT d[8] (2409:2409:2409) (2501:2501:2501)) - (PORT d[9] (3781:3781:3781) (3903:3903:3903)) - (PORT d[10] (2538:2538:2538) (2614:2614:2614)) - (PORT d[11] (2716:2716:2716) (2930:2930:2930)) - (PORT d[12] (3375:3375:3375) (3524:3524:3524)) - (PORT clk (1867:1867:1867) (1892:1892:1892)) + (PORT d[0] (4504:4504:4504) (4508:4508:4508)) + (PORT d[1] (4109:4109:4109) (4118:4118:4118)) + (PORT d[2] (4505:4505:4505) (4547:4547:4547)) + (PORT d[3] (4566:4566:4566) (4624:4624:4624)) + (PORT d[4] (4563:4563:4563) (4541:4541:4541)) + (PORT d[5] (4668:4668:4668) (4705:4705:4705)) + (PORT d[6] (4650:4650:4650) (4703:4703:4703)) + (PORT d[7] (4197:4197:4197) (4161:4161:4161)) + (PORT d[8] (4693:4693:4693) (4743:4743:4743)) + (PORT d[9] (4535:4535:4535) (4748:4748:4748)) + (PORT d[10] (4537:4537:4537) (4522:4522:4522)) + (PORT d[11] (4499:4499:4499) (4551:4551:4551)) + (PORT d[12] (4595:4595:4595) (4623:4623:4623)) + (PORT clk (1831:1831:1831) (1824:1824:1824)) ) ) (TIMINGCHECK @@ -49821,174 +46286,59 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (2067:2067:2067) (2070:2070:2070)) - (PORT clk (1867:1867:1867) (1892:1892:1892)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (PORT d[0] (3206:3206:3206) (3169:3169:3169)) + (PORT clk (1835:1835:1835) (1828:1828:1828)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1897:1897:1897)) + (PORT clk (1836:1836:1836) (1829:1829:1829)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1897:1897:1897)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1897:1897:1897)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1897:1897:1897)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1821:1821:1821)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3725:3725:3725) (3850:3850:3850)) - (PORT clk (1835:1835:1835) (1827:1827:1827)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1839:1839:1839) (1917:1917:1917)) - (PORT d[1] (1961:1961:1961) (2072:2072:2072)) - (PORT d[2] (2074:2074:2074) (2142:2142:2142)) - (PORT d[3] (1947:1947:1947) (2126:2126:2126)) - (PORT d[4] (1875:1875:1875) (1962:1962:1962)) - (PORT d[5] (1775:1775:1775) (1833:1833:1833)) - (PORT d[6] (2014:2014:2014) (2076:2076:2076)) - (PORT d[7] (1854:1854:1854) (1907:1907:1907)) - (PORT d[8] (2056:2056:2056) (2126:2126:2126)) - (PORT d[9] (1989:1989:1989) (2064:2064:2064)) - (PORT d[10] (2172:2172:2172) (2280:2280:2280)) - (PORT d[11] (2069:2069:2069) (2130:2130:2130)) - (PORT d[12] (2178:2178:2178) (2308:2308:2308)) - (PORT clk (1831:1831:1831) (1823:1823:1823)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1828:1828:1828)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1828:1828:1828)) + (PORT clk (1836:1836:1836) (1829:1829:1829)) (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1836:1836:1836) (1828:1828:1828)) + (PORT clk (1836:1836:1836) (1829:1829:1829)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1836:1836:1836) (1828:1828:1828)) + (PORT clk (1836:1836:1836) (1829:1829:1829)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1827:1827:1827) (1823:1823:1823)) + (PORT clk (1827:1827:1827) (1824:1824:1824)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -49998,14 +46348,111 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~0) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) (DELAY (ABSOLUTE - (PORT dataa (972:972:972) (1025:1025:1025)) - (PORT datab (587:587:587) (595:595:595)) - (PORT datac (928:928:928) (995:995:995)) - (PORT datad (1404:1404:1404) (1448:1448:1448)) + (PORT d[0] (987:987:987) (1035:1035:1035)) + (PORT d[1] (989:989:989) (1045:1045:1045)) + (PORT d[2] (1232:1232:1232) (1248:1248:1248)) + (PORT d[3] (1325:1325:1325) (1386:1386:1386)) + (PORT d[4] (2598:2598:2598) (2808:2808:2808)) + (PORT d[5] (2981:2981:2981) (3208:3208:3208)) + (PORT d[6] (983:983:983) (1027:1027:1027)) + (PORT d[7] (1279:1279:1279) (1356:1356:1356)) + (PORT d[8] (1032:1032:1032) (1055:1055:1055)) + (PORT d[9] (975:975:975) (1020:1020:1020)) + (PORT d[10] (1319:1319:1319) (1384:1384:1384)) + (PORT d[11] (2558:2558:2558) (2742:2742:2742)) + (PORT d[12] (1296:1296:1296) (1368:1368:1368)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (574:574:574) (581:581:581)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1284:1284:1284) (1294:1294:1294)) + (PORT datab (865:865:865) (914:914:914)) + (PORT datac (861:861:861) (866:866:866)) + (PORT datad (181:181:181) (211:211:211)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -50015,15 +46462,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~1) + (INSTANCE D\[2\]\~42) (DELAY (ABSOLUTE - (PORT dataa (960:960:960) (1034:1034:1034)) - (PORT datab (960:960:960) (1021:1021:1021)) - (PORT datac (1633:1633:1633) (1673:1673:1673)) + (PORT dataa (209:209:209) (255:255:255)) + (PORT datab (282:282:282) (370:370:370)) + (PORT datac (1627:1627:1627) (1645:1645:1645)) (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa combout (341:341:341) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (928:928:928) (981:981:981)) + (PORT datac (1193:1193:1193) (1255:1255:1255)) + (PORT datad (572:572:572) (583:583:583)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50031,47 +46494,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~60) + (INSTANCE D\[2\]\~45) (DELAY (ABSOLUTE - (PORT dataa (738:738:738) (809:809:809)) - (PORT datab (1620:1620:1620) (1630:1630:1630)) - (PORT datac (630:630:630) (680:680:680)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (1511:1511:1511) (1587:1587:1587)) - (PORT datab (3323:3323:3323) (3556:3556:3556)) - (PORT datac (1800:1800:1800) (1925:1925:1925)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (365:365:365) (410:410:410)) + (PORT datab (234:234:234) (278:278:278)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (338:338:338) (358:358:358)) - (PORT datad (701:701:701) (766:766:766)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50079,15 +46510,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~79) + (INSTANCE D\[2\]\~46) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (654:654:654)) - (PORT datab (262:262:262) (343:343:343)) - (PORT datac (665:665:665) (703:703:703)) - (PORT datad (1174:1174:1174) (1248:1248:1248)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (415:415:415) (501:501:501)) + (PORT datab (234:234:234) (278:278:278)) + (PORT datac (1139:1139:1139) (1183:1183:1183)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50095,12 +46526,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) (DELAY (ABSOLUTE - (PORT dataa (1346:1346:1346) (1423:1423:1423)) - (PORT datab (1270:1270:1270) (1356:1356:1356)) - (PORT datac (874:874:874) (907:907:907)) + (PORT dataa (978:978:978) (1031:1031:1031)) + (PORT datab (648:648:648) (673:673:673)) + (PORT datac (597:597:597) (612:612:612)) (PORT datad (194:194:194) (219:219:219)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (342:342:342) (342:342:342)) @@ -50111,12 +46542,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[4\]) + (INSTANCE z80_\|data_pins_\|dout\[2\]) (DELAY (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) + (PORT clk (1525:1525:1525) (1530:1530:1530)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) + (PORT ena (1245:1245:1245) (1226:1226:1226)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -50127,29 +46558,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (INSTANCE z80_\|bus_control_\|db\[2\]\~12) (DELAY (ABSOLUTE - (PORT dataa (690:690:690) (723:723:723)) - (PORT datac (935:935:935) (1006:1006:1006)) - (PORT datad (1018:1018:1018) (1052:1052:1052)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (920:920:920) (962:962:962)) + (PORT datac (944:944:944) (990:990:990)) + (PORT datad (218:218:218) (253:253:253)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~19) + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) (DELAY (ABSOLUTE - (PORT dataa (1247:1247:1247) (1318:1318:1318)) - (PORT datab (405:405:405) (429:429:429)) - (PORT datac (609:609:609) (655:655:655)) + (PORT dataa (439:439:439) (507:507:507)) + (PORT datab (236:236:236) (280:280:280)) + (PORT datac (225:225:225) (274:274:274)) (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50157,13 +46588,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[4\]) + (INSTANCE z80_\|ir_\|opcode\[2\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) + (PORT clrn (1577:1577:1577) (1557:1557:1557)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50175,13 +46606,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (INSTANCE z80_\|pla_decode_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT datab (997:997:997) (1067:1067:1067)) - (PORT datac (964:964:964) (1046:1046:1046)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (1460:1460:1460) (1533:1533:1533)) + (PORT datad (2264:2264:2264) (2327:2327:2327)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -50190,10 +46621,10 @@ (INSTANCE z80_\|pla_decode_\|Equal43\~0) (DELAY (ABSOLUTE - (PORT dataa (1131:1131:1131) (1155:1155:1155)) - (PORT datab (945:945:945) (984:984:984)) - (PORT datac (2031:2031:2031) (2073:2073:2073)) - (PORT datad (1149:1149:1149) (1168:1168:1168)) + (PORT dataa (944:944:944) (975:975:975)) + (PORT datab (940:940:940) (997:997:997)) + (PORT datac (1637:1637:1637) (1758:1758:1758)) + (PORT datad (1220:1220:1220) (1303:1303:1303)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -50206,9 +46637,9 @@ (INSTANCE z80_\|interrupts_\|test1\~2) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (193:193:193) (226:226:226)) + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (198:198:198) (235:235:235)) (PORT datad (195:195:195) (220:220:220)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) @@ -50222,13 +46653,13 @@ (INSTANCE z80_\|interrupts_\|test1\~3) (DELAY (ABSOLUTE - (PORT dataa (1541:1541:1541) (1599:1599:1599)) - (PORT datab (221:221:221) (259:259:259)) - (PORT datac (929:929:929) (980:980:980)) - (PORT datad (813:813:813) (828:828:828)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (845:845:845) (859:859:859)) + (PORT datab (2054:2054:2054) (2187:2187:2187)) + (PORT datac (1260:1260:1260) (1358:1358:1358)) + (PORT datad (1087:1087:1087) (1084:1084:1084)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50238,10 +46669,10 @@ (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1550:1550:1550)) + (PORT clk (1533:1533:1533) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) - (PORT ena (957:957:957) (955:955:955)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (1669:1669:1669) (1678:1678:1678)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50256,10 +46687,10 @@ (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (462:462:462)) - (PORT datab (927:927:927) (990:990:990)) - (PORT datac (886:886:886) (946:946:946)) - (PORT datad (284:284:284) (370:370:370)) + (PORT dataa (1217:1217:1217) (1308:1308:1308)) + (PORT datab (2052:2052:2052) (2184:2184:2184)) + (PORT datac (1270:1270:1270) (1384:1384:1384)) + (PORT datad (1880:1880:1880) (1934:1934:1934)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -50272,9 +46703,9 @@ (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1550:1550:1550)) + (PORT clk (1528:1528:1528) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) + (PORT clrn (1587:1587:1587) (1563:1563:1563)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50288,8 +46719,8 @@ (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) (DELAY (ABSOLUTE - (PORT datab (876:876:876) (933:933:933)) - (PORT datad (222:222:222) (294:294:294)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datad (226:226:226) (299:299:299)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50300,10 +46731,10 @@ (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1540:1540:1540) (1556:1556:1556)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT ena (1939:1939:1939) (2030:2030:2030)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50318,10 +46749,10 @@ (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT datab (277:277:277) (363:363:363)) - (PORT datac (883:883:883) (919:919:919)) - (PORT datad (861:861:861) (914:914:914)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (267:267:267) (353:353:353)) + (PORT datac (1094:1094:1094) (1135:1135:1135)) + (PORT datad (1105:1105:1105) (1151:1151:1151)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50332,10 +46763,10 @@ (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1540:1540:1540) (1556:1556:1556)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT ena (1939:1939:1939) (2030:2030:2030)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50347,276 +46778,40 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (INSTANCE z80_\|resets_\|x3) (DELAY (ABSOLUTE - (PORT dataa (931:931:931) (976:976:976)) - (PORT datac (238:238:238) (316:316:316)) - (PORT datad (854:854:854) (913:913:913)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (273:273:273) (359:359:359)) - (PORT datac (896:896:896) (930:930:930)) - (PORT datad (857:857:857) (909:909:909)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1409:1409:1409) (1502:1502:1502)) - (PORT datac (1130:1130:1130) (1238:1238:1238)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (2393:2393:2393) (2551:2551:2551)) + (PORT datac (239:239:239) (317:317:317)) + (PORT datad (1364:1364:1364) (1506:1506:1506)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (553:553:553)) - (PORT datad (1353:1353:1353) (1343:1343:1343)) - (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) (DELAY (ABSOLUTE - (PORT dataa (237:237:237) (286:286:286)) - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (1692:1692:1692) (1732:1732:1732)) - (PORT datad (178:178:178) (207:207:207)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1883:1883:1883) (1869:1869:1869)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) (DELAY (ABSOLUTE - (PORT dataa (1187:1187:1187) (1211:1211:1211)) - (PORT datab (870:870:870) (913:913:913)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (804:804:804) (825:825:825)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (615:615:615)) - (PORT datab (1663:1663:1663) (1686:1686:1686)) - (PORT datac (1608:1608:1608) (1632:1632:1632)) - (PORT datad (1862:1862:1862) (1982:1982:1982)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1136:1136:1136)) - (PORT datab (895:895:895) (913:913:913)) - (PORT datac (770:770:770) (789:789:789)) - (PORT datad (1882:1882:1882) (1828:1828:1828)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT datab (1254:1254:1254) (1252:1252:1252)) - (PORT datac (1022:1022:1022) (1023:1023:1023)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (708:708:708)) - (PORT datab (662:662:662) (729:729:729)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (594:594:594) (623:623:623)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (273:273:273)) - (PORT datab (976:976:976) (1004:1004:1004)) - (PORT datac (200:200:200) (235:235:235)) - (PORT datad (225:225:225) (263:263:263)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (707:707:707)) - (PORT datab (1012:1012:1012) (1035:1035:1035)) - (PORT datac (1134:1134:1134) (1176:1176:1176)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1171:1171:1171) (1215:1215:1215)) - (PORT datab (1172:1172:1172) (1200:1200:1200)) - (PORT datac (808:808:808) (841:841:841)) - (PORT datad (1013:1013:1013) (1037:1037:1037)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (615:615:615) (675:675:675)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (628:628:628)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (822:822:822) (850:850:850)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (983:983:983)) - (PORT datad (855:855:855) (904:904:904)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT inclk[0] (1583:1583:1583) (1637:1637:1637)) ) ) ) @@ -50625,9 +46820,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1540:1540:1540) (1556:1556:1556)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50636,600 +46831,14 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT dataa (268:268:268) (355:355:355)) - (PORT datac (882:882:882) (925:925:925)) - (PORT datad (861:861:861) (912:912:912)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1342:1342:1342)) - (PORT datab (1341:1341:1341) (1354:1354:1354)) - (PORT datad (1140:1140:1140) (1170:1170:1170)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1309:1309:1309) (1308:1308:1308)) - (PORT datab (1370:1370:1370) (1434:1434:1434)) - (PORT datac (1021:1021:1021) (1027:1027:1027)) - (PORT datad (863:863:863) (907:907:907)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (883:883:883) (896:896:896)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (908:908:908) (954:954:954)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (669:669:669)) - (PORT datab (228:228:228) (269:269:269)) - (PORT datac (1182:1182:1182) (1214:1214:1214)) - (PORT datad (1533:1533:1533) (1549:1549:1549)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1250:1250:1250) (1287:1287:1287)) - (PORT datab (1336:1336:1336) (1389:1389:1389)) - (PORT datac (623:623:623) (646:646:646)) - (PORT datad (827:827:827) (852:852:852)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) - (DELAY - (ABSOLUTE - (PORT datab (972:972:972) (967:967:967)) - (PORT datac (1002:1002:1002) (1017:1017:1017)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) - (DELAY - (ABSOLUTE - (PORT dataa (772:772:772) (799:799:799)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (719:719:719) (715:715:715)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (864:864:864) (878:878:878)) - (PORT datac (641:641:641) (686:686:686)) - (PORT datad (1029:1029:1029) (1042:1042:1042)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (915:915:915)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1422:1422:1422) (1502:1502:1502)) - (PORT datab (1610:1610:1610) (1646:1646:1646)) - (PORT datac (1843:1843:1843) (1922:1922:1922)) - (PORT datad (1856:1856:1856) (1977:1977:1977)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1402:1402:1402) (1424:1424:1424)) - (PORT datab (910:910:910) (915:915:915)) - (PORT datac (1353:1353:1353) (1395:1395:1395)) - (PORT datad (884:884:884) (921:921:921)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1026:1026:1026) (1045:1045:1045)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (547:547:547) (561:561:561)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (709:709:709)) - (PORT datab (1068:1068:1068) (1131:1131:1131)) - (PORT datac (898:898:898) (964:964:964)) - (PORT datad (894:894:894) (928:928:928)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (270:270:270)) - (PORT datac (554:554:554) (562:562:562)) - (PORT datad (1116:1116:1116) (1165:1165:1165)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (870:870:870)) - (PORT datab (1318:1318:1318) (1363:1363:1363)) - (PORT datac (1109:1109:1109) (1133:1133:1133)) - (PORT datad (773:773:773) (782:782:782)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (212:212:212) (255:255:255)) - (PORT datac (647:647:647) (705:705:705)) - (PORT datad (1344:1344:1344) (1385:1385:1385)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1183:1183:1183) (1208:1208:1208)) - (PORT datab (1054:1054:1054) (1081:1081:1081)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (768:768:768) (780:780:780)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (877:877:877)) - (PORT datab (630:630:630) (686:686:686)) - (PORT datac (1037:1037:1037) (1054:1054:1054)) - (PORT datad (1882:1882:1882) (1827:1827:1827)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1205:1205:1205)) - (PORT datab (1090:1090:1090) (1109:1109:1109)) - (PORT datac (1964:1964:1964) (2005:2005:2005)) - (PORT datad (328:328:328) (351:351:351)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1348:1348:1348)) - (PORT datab (1154:1154:1154) (1232:1232:1232)) - (PORT datac (589:589:589) (640:640:640)) - (PORT datad (221:221:221) (291:291:291)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (1411:1411:1411) (1487:1487:1487)) - (PORT datab (968:968:968) (1045:1045:1045)) - (PORT datac (1266:1266:1266) (1241:1241:1241)) - (PORT datad (963:963:963) (1058:1058:1058)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1611:1611:1611) (1623:1623:1623)) - (PORT datab (922:922:922) (982:982:982)) - (PORT datac (841:841:841) (859:859:859)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (898:898:898)) - (PORT datab (262:262:262) (344:344:344)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (1067:1067:1067) (1075:1075:1075)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (263:263:263)) - (PORT datab (926:926:926) (990:990:990)) - (PORT datac (1335:1335:1335) (1386:1386:1386)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1038:1038:1038) (1038:1038:1038)) - (PORT datab (1021:1021:1021) (1074:1074:1074)) - (PORT datac (1715:1715:1715) (1807:1807:1807)) - (PORT datad (597:597:597) (612:612:612)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (684:684:684)) - (PORT datab (1188:1188:1188) (1238:1238:1238)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (1119:1119:1119) (1190:1190:1190)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1049:1049:1049) (1082:1082:1082)) - (PORT datab (1085:1085:1085) (1123:1123:1123)) - (PORT datac (1021:1021:1021) (1066:1066:1066)) - (PORT datad (824:824:824) (853:853:853)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~29) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (675:675:675)) - (PORT datab (1287:1287:1287) (1297:1297:1297)) - (PORT datac (555:555:555) (561:561:561)) - (PORT datad (541:541:541) (557:557:557)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (576:576:576)) - (PORT datab (977:977:977) (1055:1055:1055)) - (PORT datac (199:199:199) (235:235:235)) - (PORT datad (1036:1036:1036) (1046:1046:1046)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~34) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (834:834:834) (874:874:874)) - (PORT datac (537:537:537) (552:552:552)) - (PORT datad (839:839:839) (849:849:849)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~54) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (931:931:931)) - (PORT datab (1157:1157:1157) (1200:1200:1200)) - (PORT datac (1374:1374:1374) (1450:1450:1450)) - (PORT datad (1324:1324:1324) (1390:1390:1390)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1325:1325:1325)) - (PORT datab (874:874:874) (931:931:931)) - (PORT datac (1018:1018:1018) (1026:1026:1026)) - (PORT datad (846:846:846) (851:851:851)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (925:925:925)) - (PORT datab (555:555:555) (568:568:568)) - (PORT datac (982:982:982) (1004:1004:1004)) - (PORT datad (1050:1050:1050) (1102:1102:1102)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~35) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1353:1353:1353) (1420:1420:1420)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (308:308:308) (335:335:335)) - (PORT datad (783:783:783) (795:795:795)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (929:929:929) (968:968:968)) + (PORT dataa (1130:1130:1130) (1176:1176:1176)) (PORT datab (283:283:283) (372:372:372)) - (PORT datad (861:861:861) (911:911:911)) + (PORT datad (1106:1106:1106) (1160:1160:1160)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -51242,9 +46851,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1540:1540:1540) (1556:1556:1556)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51255,11 +46864,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) + (INSTANCE z80_\|execute_\|ctl_mWrite\~3) (DELAY (ABSOLUTE - (PORT datac (683:683:683) (788:788:788)) - (PORT datad (1012:1012:1012) (1098:1098:1098)) + (PORT datac (1051:1051:1051) (1164:1164:1164)) + (PORT datad (2030:2030:2030) (2123:2123:2123)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51267,15 +46876,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (INSTANCE z80_\|execute_\|nextM\~11) (DELAY (ABSOLUTE - (PORT dataa (681:681:681) (742:742:742)) - (PORT datab (1618:1618:1618) (1623:1623:1623)) - (PORT datac (1777:1777:1777) (1813:1813:1813)) - (PORT datad (1040:1040:1040) (1060:1060:1060)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (1463:1463:1463) (1520:1520:1520)) + (PORT datab (853:853:853) (881:881:881)) + (PORT datac (791:791:791) (801:801:801)) + (PORT datad (672:672:672) (691:691:691)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51283,13 +46892,719 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (INSTANCE z80_\|execute_\|nextM\~8) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (264:264:264)) - (PORT datab (1755:1755:1755) (1766:1766:1766)) - (PORT datac (813:813:813) (831:831:831)) - (PORT datad (209:209:209) (241:241:241)) + (PORT dataa (996:996:996) (1076:1076:1076)) + (PORT datab (661:661:661) (685:685:685)) + (PORT datac (956:956:956) (1008:1008:1008)) + (PORT datad (2243:2243:2243) (2327:2327:2327)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (910:910:910)) + (PORT datab (847:847:847) (857:857:857)) + (PORT datac (945:945:945) (997:997:997)) + (PORT datad (402:402:402) (435:435:435)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (725:725:725)) + (PORT datab (334:334:334) (363:363:363)) + (PORT datac (1475:1475:1475) (1542:1542:1542)) + (PORT datad (2078:2078:2078) (2128:2128:2128)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (429:429:429)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (2002:2002:2002) (2100:2100:2100)) + (PORT datab (880:880:880) (891:891:891)) + (PORT datac (1448:1448:1448) (1504:1504:1504)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (277:277:277)) + (PORT datab (236:236:236) (281:281:281)) + (PORT datac (354:354:354) (382:382:382)) + (PORT datad (1061:1061:1061) (1062:1062:1062)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (279:279:279)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (989:989:989) (1043:1043:1043)) + (PORT datad (780:780:780) (803:803:803)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT datab (1104:1104:1104) (1138:1138:1138)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (316:316:316) (336:336:336)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT datac (766:766:766) (771:771:771)) + (PORT datad (608:608:608) (623:623:623)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~5) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (252:252:252)) + (PORT datab (2053:2053:2053) (2084:2084:2084)) + (PORT datac (618:618:618) (675:675:675)) + (PORT datad (334:334:334) (341:341:341)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (843:843:843)) + (PORT datab (877:877:877) (909:909:909)) + (PORT datac (1022:1022:1022) (1035:1035:1035)) + (PORT datad (538:538:538) (551:551:551)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT datab (273:273:273) (358:358:358)) + (PORT datac (1093:1093:1093) (1130:1130:1130)) + (PORT datad (1107:1107:1107) (1155:1155:1155)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT ena (1939:1939:1939) (2030:2030:2030)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (1123:1123:1123) (1157:1157:1157)) + (PORT datac (246:246:246) (327:327:327)) + (PORT datad (1110:1110:1110) (1159:1159:1159)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT ena (1939:1939:1939) (2030:2030:2030)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT datab (265:265:265) (348:348:348)) + (PORT datac (1077:1077:1077) (1114:1114:1114)) + (PORT datad (1111:1111:1111) (1161:1161:1161)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT ena (1939:1939:1939) (2030:2030:2030)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (637:637:637)) + (PORT datab (872:872:872) (895:895:895)) + (PORT datac (589:589:589) (612:612:612)) + (PORT datad (914:914:914) (960:960:960)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal77\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1115:1115:1115)) + (PORT datab (1187:1187:1187) (1258:1258:1258)) + (PORT datac (655:655:655) (715:715:715)) + (PORT datad (1245:1245:1245) (1328:1328:1328)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (719:719:719)) + (PORT datab (1671:1671:1671) (1704:1704:1704)) + (PORT datac (864:864:864) (890:890:890)) + (PORT datad (857:857:857) (896:896:896)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~14) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (631:631:631) (681:681:681)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~41) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (442:442:442)) + (PORT datac (1069:1069:1069) (1104:1104:1104)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (992:992:992)) + (PORT datab (1106:1106:1106) (1172:1172:1172)) + (PORT datac (411:411:411) (452:452:452)) + (PORT datad (2503:2503:2503) (2629:2629:2629)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT dataa (2006:2006:2006) (2147:2147:2147)) + (PORT datab (771:771:771) (831:831:831)) + (PORT datac (960:960:960) (989:989:989)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (941:941:941)) + (PORT datab (355:355:355) (391:391:391)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (759:759:759) (760:760:760)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (403:403:403)) + (PORT datab (1048:1048:1048) (1080:1080:1080)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (1303:1303:1303) (1325:1325:1325)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1188:1188:1188)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (200:200:200) (237:237:237)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (871:871:871)) + (PORT datab (1589:1589:1589) (1720:1720:1720)) + (PORT datac (636:636:636) (653:653:653)) + (PORT datad (1694:1694:1694) (1790:1790:1790)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~7) + (DELAY + (ABSOLUTE + (PORT datab (867:867:867) (913:913:913)) + (PORT datac (893:893:893) (946:946:946)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1439:1439:1439) (1482:1482:1482)) + (PORT datab (885:885:885) (895:895:895)) + (PORT datac (878:878:878) (926:926:926)) + (PORT datad (632:632:632) (642:642:642)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1493:1493:1493) (1600:1600:1600)) + (PORT datab (1951:1951:1951) (2023:2023:2023)) + (PORT datac (1350:1350:1350) (1424:1424:1424)) + (PORT datad (1111:1111:1111) (1134:1134:1134)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (1125:1125:1125) (1164:1164:1164)) + (PORT datac (514:514:514) (525:525:525)) + (PORT datad (639:639:639) (676:676:676)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~11) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1215:1215:1215) (1255:1255:1255)) + (PORT datac (1013:1013:1013) (1058:1058:1058)) + (PORT datad (342:342:342) (364:364:364)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (655:655:655)) + (PORT datab (1046:1046:1046) (1078:1078:1078)) + (PORT datac (2017:2017:2017) (2052:2052:2052)) + (PORT datad (621:621:621) (635:635:635)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (662:662:662)) + (PORT datab (914:914:914) (975:975:975)) + (PORT datac (1817:1817:1817) (1894:1894:1894)) + (PORT datad (898:898:898) (912:912:912)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (403:403:403)) + (PORT datab (1223:1223:1223) (1259:1259:1259)) + (PORT datac (1402:1402:1402) (1465:1465:1465)) + (PORT datad (856:856:856) (854:854:854)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (886:886:886)) + (PORT datab (916:916:916) (944:944:944)) + (PORT datac (906:906:906) (930:930:930)) + (PORT datad (843:843:843) (882:882:882)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (960:960:960)) + (PORT datab (360:360:360) (395:395:395)) + (PORT datac (859:859:859) (902:902:902)) + (PORT datad (1107:1107:1107) (1120:1120:1120)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (602:602:602)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (896:896:896) (935:935:935)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1215:1215:1215)) + (PORT datac (627:627:627) (650:650:650)) + (PORT datad (1592:1592:1592) (1700:1700:1700)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (906:906:906)) + (PORT datab (1566:1566:1566) (1611:1611:1611)) + (PORT datac (868:868:868) (891:891:891)) + (PORT datad (1122:1122:1122) (1151:1151:1151)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (723:723:723)) + (PORT datab (660:660:660) (684:684:684)) + (PORT datac (2018:2018:2018) (1985:1985:1985)) + (PORT datad (954:954:954) (1028:1028:1028)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (643:643:643) (693:693:693)) + (PORT datad (661:661:661) (727:727:727)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~22) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (949:949:949)) + (PORT datab (904:904:904) (924:924:924)) + (PORT datac (888:888:888) (932:932:932)) + (PORT datad (623:623:623) (628:628:628)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1744:1744:1744) (1869:1869:1869)) + (PORT datab (1550:1550:1550) (1688:1688:1688)) + (PORT datac (1209:1209:1209) (1285:1285:1285)) + (PORT datad (1505:1505:1505) (1539:1539:1539)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~53) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (1045:1045:1045)) + (PORT datab (936:936:936) (1009:1009:1009)) + (PORT datac (649:649:649) (669:669:669)) + (PORT datad (1286:1286:1286) (1339:1339:1339)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -51299,30 +47614,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (INSTANCE z80_\|execute_\|setM1\~23) (DELAY (ABSOLUTE - (PORT dataa (876:876:876) (895:895:895)) - (PORT datab (1364:1364:1364) (1423:1423:1423)) - (PORT datac (809:809:809) (826:826:826)) - (PORT datad (1082:1082:1082) (1100:1100:1100)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~37) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (233:233:233) (277:277:277)) - (PORT datac (843:843:843) (853:853:853)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (363:363:363) (396:396:396)) + (PORT datac (1524:1524:1524) (1571:1571:1571)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51331,15 +47630,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~38) + (INSTANCE z80_\|execute_\|setM1\~18) (DELAY (ABSOLUTE - (PORT dataa (1117:1117:1117) (1159:1159:1159)) - (PORT datab (367:367:367) (389:389:389)) - (PORT datac (1299:1299:1299) (1330:1330:1330)) - (PORT datad (825:825:825) (862:862:862)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (372:372:372) (412:412:412)) + (PORT datab (990:990:990) (1020:1020:1020)) + (PORT datac (1523:1523:1523) (1602:1602:1602)) + (PORT datad (193:193:193) (219:219:219)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (644:644:644)) + (PORT datab (693:693:693) (758:758:758)) + (PORT datac (646:646:646) (704:704:704)) + (PORT datad (1320:1320:1320) (1419:1419:1419)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51347,15 +47662,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (INSTANCE z80_\|execute_\|setM1\~20) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (254:254:254)) - (PORT datab (1399:1399:1399) (1452:1452:1452)) - (PORT datac (552:552:552) (581:581:581)) - (PORT datad (1057:1057:1057) (1107:1107:1107)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (625:625:625) (675:675:675)) + (PORT datab (1180:1180:1180) (1218:1218:1218)) + (PORT datac (868:868:868) (922:922:922)) + (PORT datad (604:604:604) (625:625:625)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51363,45 +47678,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (INSTANCE z80_\|execute_\|setM1\~34) (DELAY (ABSOLUTE - (PORT dataa (582:582:582) (619:619:619)) - (PORT datab (1400:1400:1400) (1453:1453:1453)) - (PORT datac (638:638:638) (660:660:660)) - (PORT datad (1283:1283:1283) (1317:1317:1317)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (816:816:816) (843:843:843)) - (PORT datad (820:820:820) (827:827:827)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (813:813:813)) - (PORT datab (818:818:818) (831:831:831)) - (PORT datac (700:700:700) (760:760:760)) - (PORT datad (745:745:745) (752:752:752)) + (PORT dataa (612:612:612) (649:649:649)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (309:309:309) (334:334:334)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -51409,16 +47692,2289 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~52) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (312:312:312) (330:330:330)) + (PORT datad (970:970:970) (1032:1032:1032)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1167:1167:1167)) + (PORT datac (245:245:245) (326:326:326)) + (PORT datad (1111:1111:1111) (1159:1159:1159)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT ena (1939:1939:1939) (2030:2030:2030)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (DELAY + (ABSOLUTE + (PORT datac (984:984:984) (1073:1073:1073)) + (PORT datad (1348:1348:1348) (1490:1490:1490)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (497:497:497)) + (PORT datac (1177:1177:1177) (1261:1261:1261)) + (PORT datad (272:272:272) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (697:697:697)) + (PORT datab (1593:1593:1593) (1628:1628:1628)) + (PORT datad (638:638:638) (679:679:679)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1575:1575:1575) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1049:1049:1049)) + (PORT datab (1153:1153:1153) (1214:1214:1214)) + (PORT datac (671:671:671) (718:718:718)) + (PORT datad (624:624:624) (674:674:674)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1120:1120:1120) (1227:1227:1227)) + (PORT datab (994:994:994) (1058:1058:1058)) + (PORT datac (1165:1165:1165) (1211:1211:1211)) + (PORT datad (879:879:879) (933:933:933)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (432:432:432)) + (PORT datab (689:689:689) (742:742:742)) + (PORT datac (882:882:882) (943:943:943)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (1080:1080:1080) (1100:1100:1100)) + (PORT datad (647:647:647) (663:663:663)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (954:954:954) (979:979:979)) + (PORT datac (638:638:638) (653:653:653)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (309:309:309)) + (PORT datac (944:944:944) (985:985:985)) + (PORT datad (335:335:335) (356:356:356)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (285:285:285)) + (PORT datab (780:780:780) (881:881:881)) + (PORT datac (1368:1368:1368) (1458:1458:1458)) + (PORT datad (562:562:562) (568:568:568)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (659:659:659)) + (PORT datab (733:733:733) (831:831:831)) + (PORT datad (718:718:718) (812:812:812)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (849:849:849)) + (PORT datab (1176:1176:1176) (1266:1266:1266)) + (PORT datac (727:727:727) (821:821:821)) + (PORT datad (735:735:735) (837:837:837)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (208:208:208) (251:251:251)) + (PORT datad (184:184:184) (213:213:213)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1168:1168:1168)) + (PORT datab (1145:1145:1145) (1215:1215:1215)) + (PORT datac (215:215:215) (292:292:292)) + (PORT datad (361:361:361) (417:417:417)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~99) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (873:873:873)) + (PORT datab (729:729:729) (817:817:817)) + (PORT datac (885:885:885) (954:954:954)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (378:378:378)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (735:735:735) (822:822:822)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (850:850:850)) + (PORT datab (987:987:987) (1082:1082:1082)) + (PORT datad (938:938:938) (1011:1011:1011)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (743:743:743) (852:852:852)) + (PORT datab (723:723:723) (826:826:826)) + (PORT datac (1146:1146:1146) (1231:1231:1231)) + (PORT datad (910:910:910) (977:977:977)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~133) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (704:704:704)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (728:728:728) (824:824:824)) + (PORT datad (731:731:731) (831:831:831)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datad (322:322:322) (345:345:345)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (622:622:622)) + (PORT datab (422:422:422) (485:485:485)) + (PORT datac (556:556:556) (585:585:585)) + (PORT datad (616:616:616) (671:671:671)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (816:816:816)) + (PORT datab (729:729:729) (827:827:827)) + (PORT datac (720:720:720) (822:822:822)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (367:367:367) (395:395:395)) + (PORT datad (718:718:718) (814:814:814)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (1414:1414:1414) (1548:1548:1548)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (959:959:959) (1039:1039:1039)) + (PORT datad (204:204:204) (234:234:234)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (817:817:817)) + (PORT datab (665:665:665) (745:745:745)) + (PORT datac (658:658:658) (727:727:727)) + (PORT datad (433:433:433) (505:505:505)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (279:279:279)) + (PORT datab (412:412:412) (492:492:492)) + (PORT datac (628:628:628) (701:701:701)) + (PORT datad (406:406:406) (471:471:471)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~134) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (399:399:399)) + (PORT datab (380:380:380) (403:403:403)) + (PORT datad (833:833:833) (879:879:879)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (824:824:824)) + (PORT datab (602:602:602) (630:630:630)) + (PORT datac (616:616:616) (675:675:675)) + (PORT datad (531:531:531) (537:537:537)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~135) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (827:827:827)) + (PORT datab (274:274:274) (360:360:360)) + (PORT datad (1094:1094:1094) (1148:1148:1148)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (365:365:365) (407:407:407)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (1198:1198:1198) (1264:1264:1264)) + (PORT datac (618:618:618) (676:676:676)) + (PORT datad (777:777:777) (790:790:790)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (877:877:877)) + (PORT datab (222:222:222) (269:269:269)) + (PORT datac (638:638:638) (702:702:702)) + (PORT datad (324:324:324) (344:344:344)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (817:817:817)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (569:569:569) (605:605:605)) + (PORT datad (464:464:464) (535:535:535)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) + (DELAY + (ABSOLUTE + (PORT datab (562:562:562) (582:582:582)) + (PORT datad (867:867:867) (872:872:872)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1568:1568:1568) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (820:820:820)) + (PORT datab (654:654:654) (726:726:726)) + (PORT datac (638:638:638) (703:703:703)) + (PORT datad (802:802:802) (842:842:842)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (822:822:822)) + (PORT datab (225:225:225) (273:273:273)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (638:638:638) (709:709:709)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~137) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (821:821:821)) + (PORT datab (334:334:334) (362:362:362)) + (PORT datad (340:340:340) (370:370:370)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~138) + (DELAY + (ABSOLUTE + (PORT dataa (1042:1042:1042) (1147:1147:1147)) + (PORT datab (671:671:671) (712:712:712)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (DELAY + (ABSOLUTE + (PORT datab (1402:1402:1402) (1455:1455:1455)) + (PORT datac (1615:1615:1615) (1701:1701:1701)) + (PORT datad (1189:1189:1189) (1294:1294:1294)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (277:277:277)) + (PORT datab (1199:1199:1199) (1232:1232:1232)) + (PORT datac (1173:1173:1173) (1255:1255:1255)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (1123:1123:1123) (1183:1183:1183)) + (PORT datab (3290:3290:3290) (3477:3477:3477)) + (PORT datac (1148:1148:1148) (1200:1200:1200)) + (PORT datad (561:561:561) (572:572:572)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1048:1048:1048) (1087:1087:1087)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3996:3996:3996) (4212:4212:4212)) + (PORT d[1] (1700:1700:1700) (1852:1852:1852)) + (PORT d[2] (1685:1685:1685) (1760:1760:1760)) + (PORT d[3] (1880:1880:1880) (1986:1986:1986)) + (PORT d[4] (2151:2151:2151) (2275:2275:2275)) + (PORT d[5] (1351:1351:1351) (1462:1462:1462)) + (PORT d[6] (1496:1496:1496) (1550:1550:1550)) + (PORT d[7] (3357:3357:3357) (3515:3515:3515)) + (PORT d[8] (3629:3629:3629) (3880:3880:3880)) + (PORT d[9] (1469:1469:1469) (1530:1530:1530)) + (PORT d[10] (3184:3184:3184) (3384:3384:3384)) + (PORT d[11] (2096:2096:2096) (2225:2225:2225)) + (PORT d[12] (1735:1735:1735) (1780:1780:1780)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2569:2569:2569) (2625:2625:2625)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (2985:2985:2985) (3047:3047:3047)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (672:672:672) (698:698:698)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3032:3032:3032) (3215:3215:3215)) + (PORT d[1] (1378:1378:1378) (1491:1491:1491)) + (PORT d[2] (2016:2016:2016) (2093:2093:2093)) + (PORT d[3] (2186:2186:2186) (2283:2283:2283)) + (PORT d[4] (1556:1556:1556) (1641:1641:1641)) + (PORT d[5] (1392:1392:1392) (1479:1479:1479)) + (PORT d[6] (1191:1191:1191) (1221:1221:1221)) + (PORT d[7] (3356:3356:3356) (3523:3523:3523)) + (PORT d[8] (2486:2486:2486) (2673:2673:2673)) + (PORT d[9] (3482:3482:3482) (3624:3624:3624)) + (PORT d[10] (2885:2885:2885) (3060:3060:3060)) + (PORT d[11] (1777:1777:1777) (1854:1854:1854)) + (PORT d[12] (1425:1425:1425) (1448:1448:1448)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1966:1966:1966) (1924:1924:1924)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2989:2989:2989) (2983:2983:2983)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (988:988:988) (1034:1034:1034)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3012:3012:3012) (3174:3174:3174)) + (PORT d[1] (1364:1364:1364) (1477:1477:1477)) + (PORT d[2] (1640:1640:1640) (1735:1735:1735)) + (PORT d[3] (1512:1512:1512) (1577:1577:1577)) + (PORT d[4] (1911:1911:1911) (1988:1988:1988)) + (PORT d[5] (1627:1627:1627) (1743:1743:1743)) + (PORT d[6] (1358:1358:1358) (1370:1370:1370)) + (PORT d[7] (1444:1444:1444) (1493:1493:1493)) + (PORT d[8] (2152:2152:2152) (2337:2337:2337)) + (PORT d[9] (3818:3818:3818) (3964:3964:3964)) + (PORT d[10] (2602:2602:2602) (2756:2756:2756)) + (PORT d[11] (1824:1824:1824) (1907:1907:1907)) + (PORT d[12] (2034:2034:2034) (2077:2077:2077)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1660:1660:1660) (1642:1642:1642)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2201:2201:2201) (2225:2225:2225)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (653:653:653)) + (PORT datab (1345:1345:1345) (1422:1422:1422)) + (PORT datac (885:885:885) (921:921:921)) + (PORT datad (1162:1162:1162) (1219:1219:1219)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1287:1287:1287) (1355:1355:1355)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3658:3658:3658) (3886:3886:3886)) + (PORT d[1] (1696:1696:1696) (1864:1864:1864)) + (PORT d[2] (3022:3022:3022) (3145:3145:3145)) + (PORT d[3] (2178:2178:2178) (2273:2273:2273)) + (PORT d[4] (2261:2261:2261) (2381:2381:2381)) + (PORT d[5] (2406:2406:2406) (2602:2602:2602)) + (PORT d[6] (2067:2067:2067) (2147:2147:2147)) + (PORT d[7] (2761:2761:2761) (2873:2873:2873)) + (PORT d[8] (3032:3032:3032) (3240:3240:3240)) + (PORT d[9] (2561:2561:2561) (2657:2657:2657)) + (PORT d[10] (3754:3754:3754) (3977:3977:3977)) + (PORT d[11] (1812:1812:1812) (1889:1889:1889)) + (PORT d[12] (2036:2036:2036) (2121:2121:2121)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2791:2791:2791) (2784:2784:2784)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (2736:2736:2736) (2702:2702:2702)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1271:1271:1271)) + (PORT datab (935:935:935) (963:963:963)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1431:1431:1431) (1479:1479:1479)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3642:3642:3642) (3806:3806:3806)) + (PORT d[1] (2601:2601:2601) (2824:2824:2824)) + (PORT d[2] (1657:1657:1657) (1747:1747:1747)) + (PORT d[3] (2161:2161:2161) (2264:2264:2264)) + (PORT d[4] (1866:1866:1866) (1940:1940:1940)) + (PORT d[5] (1348:1348:1348) (1465:1465:1465)) + (PORT d[6] (1148:1148:1148) (1176:1176:1176)) + (PORT d[7] (1458:1458:1458) (1492:1492:1492)) + (PORT d[8] (2173:2173:2173) (2360:2360:2360)) + (PORT d[9] (3841:3841:3841) (3989:3989:3989)) + (PORT d[10] (2571:2571:2571) (2714:2714:2714)) + (PORT d[11] (2100:2100:2100) (2188:2188:2188)) + (PORT d[12] (2024:2024:2024) (2056:2056:2056)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (3353:3353:3353) (3478:3478:3478)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1472:1472:1472) (1543:1543:1543)) + (PORT clk (1846:1846:1846) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3349:3349:3349) (3537:3537:3537)) + (PORT d[1] (2304:2304:2304) (2505:2505:2505)) + (PORT d[2] (2195:2195:2195) (2287:2287:2287)) + (PORT d[3] (1835:1835:1835) (1941:1941:1941)) + (PORT d[4] (2157:2157:2157) (2255:2255:2255)) + (PORT d[5] (1649:1649:1649) (1788:1788:1788)) + (PORT d[6] (1483:1483:1483) (1506:1506:1506)) + (PORT d[7] (1491:1491:1491) (1524:1524:1524)) + (PORT d[8] (2907:2907:2907) (3105:3105:3105)) + (PORT d[9] (2279:2279:2279) (2414:2414:2414)) + (PORT d[10] (2285:2285:2285) (2382:2382:2382)) + (PORT d[11] (2475:2475:2475) (2611:2611:2611)) + (PORT d[12] (1976:1976:1976) (2027:2027:2027)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2840:2840:2840) (2830:2830:2830)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1875:1875:1875)) + (PORT d[0] (3982:3982:3982) (4087:4087:4087)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1800:1800:1800)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2301:2301:2301) (2290:2290:2290)) + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4340:4340:4340) (4420:4420:4420)) + (PORT d[1] (4239:4239:4239) (4282:4282:4282)) + (PORT d[2] (4257:4257:4257) (4315:4315:4315)) + (PORT d[3] (4538:4538:4538) (4588:4588:4588)) + (PORT d[4] (4287:4287:4287) (4306:4306:4306)) + (PORT d[5] (4351:4351:4351) (4371:4371:4371)) + (PORT d[6] (4481:4481:4481) (4572:4572:4572)) + (PORT d[7] (4342:4342:4342) (4398:4398:4398)) + (PORT d[8] (4597:4597:4597) (4592:4592:4592)) + (PORT d[9] (4469:4469:4469) (4739:4739:4739)) + (PORT d[10] (4352:4352:4352) (4394:4394:4394)) + (PORT d[11] (4350:4350:4350) (4370:4370:4370)) + (PORT d[12] (4626:4626:4626) (4608:4608:4608)) + (PORT clk (1807:1807:1807) (1802:1802:1802)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (944:944:944)) + (PORT datab (1682:1682:1682) (1751:1751:1751)) + (PORT datac (910:910:910) (950:950:950)) + (PORT datad (1193:1193:1193) (1243:1243:1243)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3603:3603:3603) (3780:3780:3780)) + (PORT d[1] (2612:2612:2612) (2820:2820:2820)) + (PORT d[2] (1542:1542:1542) (1613:1613:1613)) + (PORT d[3] (2126:2126:2126) (2248:2248:2248)) + (PORT d[4] (2158:2158:2158) (2252:2252:2252)) + (PORT d[5] (1643:1643:1643) (1776:1776:1776)) + (PORT d[6] (1395:1395:1395) (1417:1417:1417)) + (PORT d[7] (1473:1473:1473) (1509:1509:1509)) + (PORT d[8] (2157:2157:2157) (2322:2322:2322)) + (PORT d[9] (2292:2292:2292) (2444:2444:2444)) + (PORT d[10] (2276:2276:2276) (2402:2402:2402)) + (PORT d[11] (2115:2115:2115) (2225:2225:2225)) + (PORT d[12] (2288:2288:2288) (2338:2338:2338)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1873:1873:1873)) + (PORT d[0] (3448:3448:3448) (3327:3327:3327)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1836:1836:1836)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (276:276:276)) + (PORT datab (906:906:906) (941:941:941)) + (PORT datac (1129:1129:1129) (1177:1177:1177)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1549:1549:1549) (1631:1631:1631)) + (PORT clk (1862:1862:1862) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2520:2520:2520) (2617:2617:2617)) + (PORT d[1] (1962:1962:1962) (2122:2122:2122)) + (PORT d[2] (1955:1955:1955) (2077:2077:2077)) + (PORT d[3] (1876:1876:1876) (2000:2000:2000)) + (PORT d[4] (2723:2723:2723) (2864:2864:2864)) + (PORT d[5] (2232:2232:2232) (2416:2416:2416)) + (PORT d[6] (2043:2043:2043) (2115:2115:2115)) + (PORT d[7] (2404:2404:2404) (2531:2531:2531)) + (PORT d[8] (2398:2398:2398) (2577:2577:2577)) + (PORT d[9] (1996:1996:1996) (2101:2101:2101)) + (PORT d[10] (1691:1691:1691) (1769:1769:1769)) + (PORT d[11] (2047:2047:2047) (2128:2128:2128)) + (PORT d[12] (2520:2520:2520) (2605:2605:2605)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2655:2655:2655) (2640:2640:2640)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1888:1888:1888)) + (PORT d[0] (3407:3407:3407) (3339:3339:3339)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1813:1813:1813)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2066:2066:2066) (2077:2077:2077)) + (PORT clk (1827:1827:1827) (1819:1819:1819)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4618:4618:4618) (4692:4692:4692)) + (PORT d[1] (4233:4233:4233) (4271:4271:4271)) + (PORT d[2] (4532:4532:4532) (4592:4592:4592)) + (PORT d[3] (4449:4449:4449) (4489:4489:4489)) + (PORT d[4] (4330:4330:4330) (4336:4336:4336)) + (PORT d[5] (4590:4590:4590) (4607:4607:4607)) + (PORT d[6] (4724:4724:4724) (4801:4801:4801)) + (PORT d[7] (4565:4565:4565) (4613:4613:4613)) + (PORT d[8] (4569:4569:4569) (4629:4629:4629)) + (PORT d[9] (4484:4484:4484) (4751:4751:4751)) + (PORT d[10] (4377:4377:4377) (4395:4395:4395)) + (PORT d[11] (4636:4636:4636) (4682:4682:4682)) + (PORT d[12] (4604:4604:4604) (4754:4754:4754)) + (PORT clk (1823:1823:1823) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1827:1827:1827) (1819:1819:1819)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1815:1815:1815)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (946:946:946)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (1482:1482:1482) (1521:1521:1521)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (1613:1613:1613) (1669:1669:1669)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1616:1616:1616) (1701:1701:1701)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (1399:1399:1399) (1458:1458:1458)) + (PORT datac (1325:1325:1325) (1390:1390:1390)) + (PORT datad (341:341:341) (359:359:359)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (1628:1628:1628) (1657:1657:1657)) + (PORT datab (1397:1397:1397) (1455:1455:1455)) + (PORT datac (1102:1102:1102) (1179:1179:1179)) + (PORT datad (313:313:313) (331:331:331)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (975:975:975) (1040:1040:1040)) + (PORT datab (1658:1658:1658) (1724:1724:1724)) + (PORT datac (239:239:239) (291:291:291)) + (PORT datad (875:875:875) (896:896:896)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (310:310:310)) + (PORT datab (660:660:660) (727:727:727)) + (PORT datad (213:213:213) (248:248:248)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1009:1009:1009)) + (PORT datab (906:906:906) (952:952:952)) + (PORT datac (884:884:884) (932:932:932)) + (PORT datad (924:924:924) (947:947:947)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1571:1571:1571) (1550:1550:1550)) + (PORT ena (1479:1479:1479) (1488:1488:1488)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1561:1561:1561)) + (PORT datab (1173:1173:1173) (1201:1201:1201)) + (PORT datac (1193:1193:1193) (1280:1280:1280)) + (PORT datad (1406:1406:1406) (1444:1444:1444)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (970:970:970)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (896:896:896) (900:900:900)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (605:605:605) (641:641:641)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datad (1539:1539:1539) (1638:1638:1638)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (1391:1391:1391) (1424:1424:1424)) + (PORT datab (630:630:630) (671:671:671)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51428,11 +49984,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1531:1531:1531)) + (PORT clk (1528:1528:1528) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (765:765:765) (832:832:832)) - (PORT sload (1678:1678:1678) (1738:1738:1738)) - (PORT ena (2119:2119:2119) (2120:2120:2120)) + (PORT asdata (580:580:580) (654:654:654)) + (PORT sload (1117:1117:1117) (1168:1168:1168)) + (PORT ena (811:811:811) (804:804:804)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -51445,79 +50001,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~84) + (INSTANCE D\[0\]\~59) (DELAY (ABSOLUTE - (PORT dataa (698:698:698) (722:722:722)) - (PORT datab (3327:3327:3327) (3563:3563:3563)) - (PORT datac (1214:1214:1214) (1273:1273:1273)) - (PORT datad (695:695:695) (758:758:758)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (912:912:912)) - (PORT datab (1191:1191:1191) (1280:1280:1280)) - (PORT datac (707:707:707) (759:759:759)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (884:884:884) (914:914:914)) + (PORT datab (1147:1147:1147) (1200:1200:1200)) + (PORT datac (179:179:179) (216:216:216)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~85) + (INSTANCE D\[0\]\~60) (DELAY (ABSOLUTE - (PORT dataa (726:726:726) (766:766:766)) - (PORT datab (2222:2222:2222) (2368:2368:2368)) - (PORT datac (316:316:316) (341:341:341)) - (PORT datad (2998:2998:2998) (3240:3240:3240)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1270:1270:1270)) - (PORT datab (672:672:672) (750:750:750)) - (PORT datac (574:574:574) (611:611:611)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (2231:2231:2231) (2351:2351:2351)) - (PORT datab (236:236:236) (280:280:280)) - (PORT datac (3029:3029:3029) (3275:3275:3275)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (948:948:948) (996:996:996)) + (PORT datab (642:642:642) (701:701:701)) + (PORT datac (1642:1642:1642) (1669:1669:1669)) + (PORT datad (329:329:329) (345:345:345)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51525,15 +50031,73 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~59) + (INSTANCE D\[1\]\~61) (DELAY (ABSOLUTE - (PORT dataa (1511:1511:1511) (1588:1588:1588)) - (PORT datab (1676:1676:1676) (1756:1756:1756)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (1445:1445:1445) (1468:1468:1468)) + (PORT datac (831:831:831) (845:845:845)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (1402:1402:1402) (1476:1476:1476)) + (PORT datab (940:940:940) (1026:1026:1026)) + (PORT datac (962:962:962) (1081:1081:1081)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (413:413:413)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (500:500:500)) + (PORT datab (233:233:233) (277:277:277)) + (PORT datac (1139:1139:1139) (1183:1183:1183)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (260:260:260)) + (PORT datac (1325:1325:1325) (1392:1392:1392)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51541,32 +50105,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~87) + (INSTANCE D\[3\]\~76) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (3324:3324:3324) (3557:3557:3557)) - (PORT datac (1216:1216:1216) (1278:1278:1278)) - (PORT datad (701:701:701) (766:766:766)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1121:1121:1121) (1209:1209:1209)) + (PORT datab (1140:1140:1140) (1196:1196:1196)) + (PORT datac (1527:1527:1527) (1561:1561:1561)) + (PORT datad (328:328:328) (343:343:343)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~67) + (INSTANCE D\[4\]\~82) (DELAY (ABSOLUTE - (PORT dataa (921:921:921) (965:965:965)) - (PORT datab (1471:1471:1471) (1534:1534:1534)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (887:887:887) (917:917:917)) + (PORT datab (1549:1549:1549) (1602:1602:1602)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (1002:1002:1002)) + (PORT datab (1444:1444:1444) (1508:1508:1508)) + (PORT datac (1641:1641:1641) (1667:1667:1667)) + (PORT datad (330:330:330) (348:348:348)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~92) + (DELAY + (ABSOLUTE + (PORT datab (1379:1379:1379) (1383:1383:1383)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1000:1000:1000)) + (PORT datab (894:894:894) (967:967:967)) + (PORT datac (1642:1642:1642) (1672:1672:1672)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51576,12 +50184,12 @@ (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT dataa (935:935:935) (981:981:981)) - (PORT datab (271:271:271) (358:358:358)) - (PORT datac (252:252:252) (334:334:334)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (1365:1365:1365) (1505:1505:1505)) + (PORT datac (2335:2335:2335) (2467:2467:2467)) + (PORT datad (554:554:554) (564:564:564)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -51590,10 +50198,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1535:1535:1535) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1291:1291:1291) (1310:1310:1310)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51608,7 +50216,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (648:648:648) (726:726:726)) + (PORT datad (242:242:242) (312:312:312)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51618,10 +50226,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (1546:1546:1546) (1543:1543:1543)) + (PORT clk (1542:1542:1542) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (1235:1235:1235) (1231:1231:1231)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51636,10 +50244,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT asdata (890:890:890) (938:938:938)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) + (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT asdata (565:565:565) (644:644:644)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51654,9 +50262,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (575:575:575) (633:633:633)) - (PORT datab (251:251:251) (336:336:336)) - (PORT datad (224:224:224) (296:296:296)) + (PORT dataa (251:251:251) (340:340:340)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datad (216:216:216) (283:283:283)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -51669,9 +50277,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (260:260:260) (355:355:355)) - (PORT datab (207:207:207) (250:250:250)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (912:912:912) (985:985:985)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (182:182:182) (211:211:211)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -51679,6 +50287,15 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE ula_\|pll_\|altpll_component\|auto_generated\|wire_pll1_clk\[2\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1896:1896:1896) (1878:1878:1878)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|divider\[0\]\~15) @@ -51693,9 +50310,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51710,7 +50327,7 @@ (DELAY (ABSOLUTE (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (252:252:252) (337:337:337)) + (PORT datab (251:251:251) (337:337:337)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -51724,9 +50341,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51740,9 +50357,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (253:253:253) (343:343:343)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -51754,9 +50371,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51784,9 +50401,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51800,7 +50417,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) (DELAY (ABSOLUTE - (PORT datab (252:252:252) (339:339:339)) + (PORT datab (251:251:251) (337:337:337)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51814,9 +50431,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51830,8 +50447,8 @@ (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) (DELAY (ABSOLUTE - (PORT dataa (255:255:255) (344:344:344)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -51841,9 +50458,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51857,10 +50474,10 @@ (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (342:342:342)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (224:224:224) (302:302:302)) - (PORT datad (226:226:226) (298:298:298)) + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datac (223:223:223) (302:302:302)) + (PORT datad (225:225:225) (297:297:297)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -51873,11 +50490,11 @@ (INSTANCE ula_\|i2c_loader_\|WideAnd0) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (335:335:335)) - (PORT datac (223:223:223) (303:303:303)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (250:250:250) (334:334:334)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (225:225:225) (296:296:296)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51887,10 +50504,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1022:1022:1022) (977:977:977)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT ena (1428:1428:1428) (1403:1403:1403)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51905,7 +50522,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (267:267:267) (348:348:348)) + (PORT datad (245:245:245) (317:317:317)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51916,10 +50533,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1022:1022:1022) (977:977:977)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT ena (1428:1428:1428) (1403:1403:1403)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51934,9 +50551,9 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT dataa (297:297:297) (393:393:393)) - (PORT datad (246:246:246) (319:319:319)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT datab (333:333:333) (440:440:440)) + (PORT datad (247:247:247) (319:319:319)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51947,10 +50564,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1022:1022:1022) (977:977:977)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT ena (1428:1428:1428) (1403:1403:1403)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51960,13 +50577,36 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~5) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (709:709:709)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (307:307:307) (404:404:404)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|Mux42\~0) (DELAY (ABSOLUTE - (PORT datac (1131:1131:1131) (1182:1182:1182)) - (PORT datad (655:655:655) (717:717:717)) + (PORT datac (700:700:700) (774:774:774)) + (PORT datad (677:677:677) (746:746:746)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51974,27 +50614,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (INSTANCE ula_\|i2c_loader_\|nbyte\~4) (DELAY (ABSOLUTE - (PORT dataa (271:271:271) (370:370:370)) - (PORT datab (868:868:868) (936:936:936)) + (PORT dataa (286:286:286) (381:381:381)) + (PORT datab (336:336:336) (443:443:443)) + (PORT datad (634:634:634) (704:704:704)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1223:1223:1223)) - (PORT datab (760:760:760) (826:826:826)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52003,10 +50632,10 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datac (435:435:435) (510:510:510)) - (PORT datad (656:656:656) (720:720:720)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (290:290:290) (381:381:381)) + (PORT datac (578:578:578) (623:623:623)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -52024,13 +50653,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (446:446:446) (519:519:519)) - (PORT datab (1089:1089:1089) (1128:1128:1128)) - (PORT datac (426:426:426) (500:500:500)) - (PORT datad (508:508:508) (502:502:502)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (284:284:284) (379:379:379)) + (PORT datab (272:272:272) (359:359:359)) + (PORT datac (301:301:301) (403:403:403)) + (PORT datad (516:516:516) (513:513:513)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52040,13 +50669,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (239:239:239) (281:281:281)) - (PORT datac (724:724:724) (791:791:791)) - (PORT datad (329:329:329) (343:343:343)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (662:662:662) (747:747:747)) + (PORT datab (653:653:653) (670:670:670)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52056,23 +50685,23 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (691:691:691) (755:755:755)) - (PORT datac (786:786:786) (794:794:794)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (835:835:835) (857:857:857)) + (PORT datac (423:423:423) (492:492:492)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -52085,75 +50714,89 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT dataa (460:460:460) (536:536:536)) - (PORT datab (867:867:867) (935:935:935)) - (PORT datad (406:406:406) (471:471:471)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (677:677:677) (755:755:755)) + (PORT datab (713:713:713) (770:770:770)) + (PORT datac (253:253:253) (337:337:337)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (1125:1125:1125) (1171:1171:1171)) - (PORT datab (867:867:867) (936:936:936)) - (PORT datac (644:644:644) (709:709:709)) - (PORT datad (692:692:692) (746:746:746)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (844:844:844) (895:895:895)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (371:371:371)) - (PORT datab (804:804:804) (839:839:839)) - (PORT datac (211:211:211) (252:252:252)) - (PORT datad (652:652:652) (715:715:715)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (596:596:596) (620:620:620)) + (PORT datab (263:263:263) (314:314:314)) + (PORT datad (341:341:341) (360:360:360)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) + (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (1909:1909:1909) (1926:1926:1926)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) - (PORT ena (1122:1122:1122) (1112:1112:1112)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (389:389:389)) + (PORT datab (261:261:261) (350:350:350)) + (PORT datac (232:232:232) (318:318:318)) + (PORT datad (567:567:567) (616:616:616)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (710:710:710)) + (PORT datab (267:267:267) (356:356:356)) + (PORT datad (234:234:234) (311:311:311)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT ena (1191:1191:1191) (1184:1184:1184)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52168,10 +50811,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) (DELAY (ABSOLUTE - (PORT dataa (271:271:271) (370:370:370)) - (PORT datab (252:252:252) (337:337:337)) - (PORT datac (830:830:830) (890:890:890)) - (PORT datad (233:233:233) (308:308:308)) + (PORT dataa (259:259:259) (351:351:351)) + (PORT datab (249:249:249) (335:335:335)) + (PORT datac (602:602:602) (665:665:665)) + (PORT datad (238:238:238) (316:316:316)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -52184,12 +50827,12 @@ (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (361:361:361)) - (PORT datab (271:271:271) (356:356:356)) - (PORT datac (243:243:243) (322:322:322)) - (PORT datad (255:255:255) (328:328:328)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (361:361:361) (399:399:399)) + (PORT datab (370:370:370) (392:392:392)) + (PORT datac (920:920:920) (977:977:977)) + (PORT datad (327:327:327) (351:351:351)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52200,25 +50843,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (662:662:662)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datac (788:788:788) (805:805:805)) - (PORT datad (267:267:267) (348:348:348)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~2) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (410:410:410)) - (PORT datab (424:424:424) (454:454:454)) - (PORT datad (254:254:254) (328:328:328)) + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (562:562:562) (591:591:591)) + (PORT datad (443:443:443) (515:515:515)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -52242,231 +50869,18 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT dataa (272:272:272) (363:363:363)) - (PORT datac (436:436:436) (512:512:512)) - (PORT datad (770:770:770) (813:813:813)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (268:268:268)) - (PORT datac (1135:1135:1135) (1181:1181:1181)) - (PORT datad (659:659:659) (717:717:717)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT datab (274:274:274) (360:360:360)) - (PORT datac (512:512:512) (523:523:523)) - (PORT datad (385:385:385) (449:449:449)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT datab (609:609:609) (628:628:628)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1134:1134:1134) (1151:1151:1151)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT sload (864:864:864) (978:978:978)) - (PORT ena (1022:1022:1022) (977:977:977)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~5) - (DELAY - (ABSOLUTE - (PORT datab (869:869:869) (937:937:937)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1909:1909:1909) (1926:1926:1926)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) - (PORT ena (1122:1122:1122) (1112:1112:1112)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~0) - (DELAY - (ABSOLUTE - (PORT dataa (269:269:269) (370:370:370)) - (PORT datab (868:868:868) (936:936:936)) - (PORT datad (233:233:233) (308:308:308)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1909:1909:1909) (1926:1926:1926)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) - (PORT ena (1122:1122:1122) (1112:1112:1112)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) - (DELAY - (ABSOLUTE - (PORT datab (252:252:252) (337:337:337)) - (PORT datac (241:241:241) (332:332:332)) - (PORT datad (233:233:233) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) - (DELAY - (ABSOLUTE - (PORT dataa (264:264:264) (361:361:361)) - (PORT datab (343:343:343) (377:377:377)) - (PORT datac (509:509:509) (520:520:520)) - (PORT datad (253:253:253) (326:326:326)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (664:664:664)) - (PORT datab (282:282:282) (369:369:369)) - (PORT datac (174:174:174) (207:207:207)) - (PORT datad (267:267:267) (349:349:349)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (768:768:768)) - (PORT datab (625:625:625) (681:681:681)) - (PORT datac (722:722:722) (792:792:792)) - (PORT datad (1054:1054:1054) (1092:1092:1092)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (439:439:439) (519:519:519)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (595:595:595) (665:665:665)) - (PORT datab (889:889:889) (937:937:937)) - (PORT datac (602:602:602) (649:649:649)) - (PORT datad (732:732:732) (710:710:710)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (285:285:285) (380:380:380)) + (PORT datab (272:272:272) (356:356:356)) + (PORT datac (302:302:302) (404:404:404)) + (PORT datad (517:517:517) (510:510:510)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52476,10 +50890,10 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (862:862:862) (910:910:910)) - (PORT datab (623:623:623) (689:689:689)) - (PORT datac (768:768:768) (775:775:775)) - (PORT datad (176:176:176) (202:202:202)) + (PORT dataa (416:416:416) (489:489:489)) + (PORT datab (587:587:587) (640:640:640)) + (PORT datac (850:850:850) (859:859:859)) + (PORT datad (309:309:309) (325:325:325)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -52492,12 +50906,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2326:2326:2326) (2405:2405:2405)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sload (1723:1723:1723) (1708:1708:1708)) - (PORT ena (820:820:820) (825:825:825)) + (PORT asdata (1124:1124:1124) (1148:1148:1148)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sload (1067:1067:1067) (1036:1036:1036)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52514,9 +50928,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (393:393:393)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (297:297:297) (392:392:392)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52528,12 +50942,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2327:2327:2327) (2405:2405:2405)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sload (1723:1723:1723) (1708:1708:1708)) - (PORT ena (820:820:820) (825:825:825)) + (PORT asdata (1125:1125:1125) (1149:1149:1149)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sload (1067:1067:1067) (1036:1036:1036)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52550,7 +50964,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT datab (298:298:298) (393:393:393)) + (PORT datab (288:288:288) (380:380:380)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52564,11 +50978,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sload (1723:1723:1723) (1708:1708:1708)) - (PORT ena (820:820:820) (825:825:825)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sload (1067:1067:1067) (1036:1036:1036)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52585,7 +50999,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (294:294:294) (387:387:387)) + (PORT datab (306:306:306) (403:403:403)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52599,12 +51013,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2328:2328:2328) (2407:2407:2407)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sload (1723:1723:1723) (1708:1708:1708)) - (PORT ena (820:820:820) (825:825:825)) + (PORT asdata (1125:1125:1125) (1150:1150:1150)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sload (1067:1067:1067) (1036:1036:1036)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52621,10 +51035,10 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (669:669:669) (721:721:721)) - (PORT datab (460:460:460) (532:532:532)) - (PORT datac (402:402:402) (484:484:484)) - (PORT datad (404:404:404) (470:470:470)) + (PORT dataa (426:426:426) (508:508:508)) + (PORT datab (298:298:298) (392:392:392)) + (PORT datac (277:277:277) (365:365:365)) + (PORT datad (279:279:279) (363:363:363)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -52632,13 +51046,29 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (798:798:798)) + (PORT datab (261:261:261) (350:350:350)) + (PORT datac (704:704:704) (778:778:778)) + (PORT datad (260:260:260) (337:337:337)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) (DELAY (ABSOLUTE - (PORT datad (270:270:270) (351:351:351)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (308:308:308) (413:413:413)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -52648,11 +51078,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sload (1723:1723:1723) (1708:1708:1708)) - (PORT ena (820:820:820) (825:825:825)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sload (1067:1067:1067) (1036:1036:1036)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52669,25 +51099,57 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) (DELAY (ABSOLUTE - (PORT datab (201:201:201) (240:240:240)) - (PORT datac (175:175:175) (209:209:209)) - (PORT datad (414:414:414) (479:479:479)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (622:622:622) (640:640:640)) + (PORT datac (335:335:335) (357:357:357)) + (PORT datad (658:658:658) (710:710:710)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (286:286:286) (376:376:376)) + (PORT datac (231:231:231) (314:314:314)) + (PORT datad (487:487:487) (489:489:489)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (374:374:374)) + (PORT datab (266:266:266) (320:320:320)) + (PORT datac (261:261:261) (352:352:352)) + (PORT datad (421:421:421) (491:491:491)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (243:243:243)) - (PORT datab (429:429:429) (456:456:456)) - (PORT datad (596:596:596) (611:611:611)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) + (PORT dataa (343:343:343) (380:380:380)) + (PORT datab (590:590:590) (613:613:613)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52698,9 +51160,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52714,9 +51176,9 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (359:359:359)) - (PORT datab (819:819:819) (842:842:842)) - (PORT datad (268:268:268) (350:350:350)) + (PORT dataa (264:264:264) (356:356:356)) + (PORT datab (267:267:267) (321:321:321)) + (PORT datad (419:419:419) (488:488:488)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -52729,10 +51191,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Start) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1022:1022:1022) (977:977:977)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1192:1192:1192) (1154:1154:1154)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52744,14 +51206,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (INSTANCE ula_\|i2c_loader_\|nbyte\~0) (DELAY (ABSOLUTE - (PORT dataa (1172:1172:1172) (1221:1221:1221)) - (PORT datab (765:765:765) (833:833:833)) - (PORT datad (772:772:772) (817:817:817)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (330:330:330) (437:437:437)) + (PORT datad (630:630:630) (700:700:700)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52759,12 +51219,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -52777,28 +51237,92 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (277:277:277) (369:369:369)) - (PORT datac (433:433:433) (508:508:508)) - (PORT datad (766:766:766) (810:810:810)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (678:678:678) (749:749:749)) + (PORT datac (684:684:684) (733:733:733)) + (PORT datad (441:441:441) (514:514:514)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (632:632:632) (666:666:666)) - (PORT datab (424:424:424) (454:454:454)) - (PORT datad (314:314:314) (333:333:333)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) + (PORT dataa (1033:1033:1033) (1086:1086:1086)) + (PORT datab (486:486:486) (561:561:561)) + (PORT datac (255:255:255) (338:338:338)) + (PORT datad (669:669:669) (726:726:726)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (590:590:590) (648:648:648)) + (PORT datad (326:326:326) (348:348:348)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (387:387:387)) + (PORT datab (262:262:262) (314:314:314)) + (PORT datac (556:556:556) (578:578:578)) + (PORT datad (424:424:424) (491:491:491)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1900:1900:1900) (1919:1919:1919)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT ena (1160:1160:1160) (1135:1135:1135)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (707:707:707)) + (PORT datad (241:241:241) (319:319:319)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52806,18 +51330,111 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Stop) + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) (DELAY (ABSOLUTE (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT ena (1191:1191:1191) (1184:1184:1184)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (355:355:355)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datad (241:241:241) (319:319:319)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~27) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (793:793:793)) + (PORT datac (701:701:701) (775:775:775)) + (PORT datad (486:486:486) (488:488:488)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (753:753:753)) + (PORT datab (714:714:714) (770:770:770)) + (PORT datac (251:251:251) (332:332:332)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~26) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (798:798:798)) + (PORT datac (702:702:702) (777:777:777)) + (PORT datad (347:347:347) (368:368:368)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Data) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (578:578:578) (625:625:625)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT sload (875:875:875) (1003:1003:1003)) + (PORT ena (1192:1192:1192) (1154:1154:1154)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL @@ -52825,9 +51442,9 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~0) (DELAY (ABSOLUTE - (PORT datab (271:271:271) (356:356:356)) - (PORT datac (243:243:243) (323:323:323)) - (PORT datad (252:252:252) (325:325:325)) + (PORT datab (288:288:288) (379:379:379)) + (PORT datac (607:607:607) (657:657:657)) + (PORT datad (233:233:233) (310:310:310)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52839,10 +51456,10 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1938:1938:1938) (1962:1962:1962)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) - (PORT ena (1318:1318:1318) (1294:1294:1294)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT ena (1428:1428:1428) (1403:1403:1403)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52857,12 +51474,12 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (1125:1125:1125) (1171:1171:1171)) - (PORT datab (245:245:245) (328:328:328)) - (PORT datac (847:847:847) (898:898:898)) - (PORT datad (692:692:692) (746:746:746)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (661:661:661) (746:746:746)) + (PORT datab (330:330:330) (435:435:435)) + (PORT datac (260:260:260) (348:348:348)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52873,11 +51490,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (581:581:581) (616:616:616)) - (PORT datac (844:844:844) (893:893:893)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (650:650:650) (670:670:670)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (630:630:630) (699:699:699)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52888,9 +51505,9 @@ (DELAY (ABSOLUTE (PORT clk (1473:1473:1473) (1495:1495:1495)) - (PORT d (960:960:960) (1004:1004:1004)) - (PORT aload (1724:1724:1724) (1790:1790:1790)) - (PORT ena (697:697:697) (696:696:696)) + (PORT d (958:958:958) (1002:1002:1002)) + (PORT aload (1710:1710:1710) (1775:1775:1775)) + (PORT ena (885:885:885) (884:884:884)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -52907,10 +51524,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1938:1938:1938) (1962:1962:1962)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) - (PORT ena (1318:1318:1318) (1294:1294:1294)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT ena (1428:1428:1428) (1403:1403:1403)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52920,18 +51537,74 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) + (DELAY + (ABSOLUTE + (PORT datac (887:887:887) (940:940:940)) + (PORT datad (610:610:610) (673:673:673)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|Mux35\~0) (DELAY (ABSOLUTE - (PORT dataa (667:667:667) (716:716:716)) - (PORT datab (461:461:461) (529:529:529)) - (PORT datac (402:402:402) (479:479:479)) - (PORT datad (403:403:403) (470:470:470)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (442:442:442) (520:520:520)) + (PORT datab (457:457:457) (520:520:520)) + (PORT datac (391:391:391) (449:449:449)) + (PORT datad (395:395:395) (456:456:456)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (409:409:409)) + (PORT datab (298:298:298) (389:389:389)) + (PORT datac (278:278:278) (370:370:370)) + (PORT datad (262:262:262) (338:338:338)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) + (DELAY + (ABSOLUTE + (PORT datac (274:274:274) (369:369:369)) + (PORT datad (260:260:260) (337:337:337)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (307:307:307) (404:404:404)) + (PORT datac (278:278:278) (370:370:370)) + (PORT datad (198:198:198) (224:224:224)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52941,11 +51614,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) (DELAY (ABSOLUTE - (PORT datab (756:756:756) (826:826:826)) - (PORT datac (403:403:403) (482:482:482)) - (PORT datad (404:404:404) (474:474:474)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (456:456:456) (520:520:520)) + (PORT datac (890:890:890) (943:943:943)) + (PORT datad (414:414:414) (478:478:478)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52955,11 +51628,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (665:665:665) (739:739:739)) - (PORT datac (1131:1131:1131) (1178:1178:1178)) - (PORT datad (654:654:654) (713:713:713)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (707:707:707) (795:795:795)) + (PORT datac (702:702:702) (777:777:777)) + (PORT datad (261:261:261) (341:341:341)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52969,13 +51642,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (217:217:217) (266:266:266)) - (PORT datab (764:764:764) (831:831:831)) - (PORT datac (211:211:211) (251:251:251)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (294:294:294) (393:393:393)) + (PORT datab (263:263:263) (313:313:313)) + (PORT datac (173:173:173) (205:205:205)) + (PORT datad (350:350:350) (370:370:370)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52985,11 +51658,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datab (804:804:804) (839:839:839)) - (PORT datad (652:652:652) (716:716:716)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT datab (447:447:447) (530:530:530)) + (PORT datac (557:557:557) (581:581:581)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53001,9 +51674,9 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sclr (1200:1200:1200) (1296:1296:1296)) - (PORT ena (945:945:945) (931:931:931)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sclr (1104:1104:1104) (1198:1198:1198)) + (PORT ena (1397:1397:1397) (1366:1366:1366)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53014,27 +51687,15 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) - (DELAY - (ABSOLUTE - (PORT datac (862:862:862) (909:909:909)) - (PORT datad (846:846:846) (891:891:891)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) (DELAY (ABSOLUTE - (PORT dataa (669:669:669) (718:718:718)) - (PORT datab (448:448:448) (516:516:516)) - (PORT datac (402:402:402) (480:480:480)) - (PORT datad (404:404:404) (469:469:469)) + (PORT dataa (305:305:305) (408:408:408)) + (PORT datab (305:305:305) (398:398:398)) + (PORT datac (278:278:278) (369:369:369)) + (PORT datad (262:262:262) (338:338:338)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -53047,13 +51708,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) (DELAY (ABSOLUTE - (PORT dataa (540:540:540) (561:561:561)) - (PORT datab (462:462:462) (530:530:530)) - (PORT datac (403:403:403) (480:480:480)) - (PORT datad (176:176:176) (202:202:202)) + (PORT dataa (374:374:374) (397:397:397)) + (PORT datab (373:373:373) (401:401:401)) + (PORT datac (390:390:390) (448:448:448)) + (PORT datad (413:413:413) (480:480:480)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53064,8 +51725,8 @@ (DELAY (ABSOLUTE (PORT dataa (247:247:247) (334:334:334)) - (PORT datac (724:724:724) (792:792:792)) - (PORT datad (175:175:175) (201:201:201)) + (PORT datac (893:893:893) (946:946:946)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53077,13 +51738,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) (DELAY (ABSOLUTE - (PORT dataa (662:662:662) (736:736:736)) - (PORT datab (760:760:760) (827:827:827)) - (PORT datac (189:189:189) (233:233:233)) - (PORT datad (656:656:656) (720:720:720)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (712:712:712) (775:775:775)) + (PORT datab (482:482:482) (560:560:560)) + (PORT datac (588:588:588) (650:650:650)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53093,10 +51754,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (804:804:804) (835:835:835)) - (PORT datac (1131:1131:1131) (1179:1179:1179)) - (PORT datad (651:651:651) (712:712:712)) + (PORT dataa (1032:1032:1032) (1083:1083:1083)) + (PORT datab (561:561:561) (587:587:587)) + (PORT datac (921:921:921) (976:976:976)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -53111,8 +51772,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT ena (1003:1003:1003) (1001:1001:1001)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT ena (1207:1207:1207) (1188:1188:1188)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53127,12 +51788,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (391:391:391)) - (PORT datab (296:296:296) (390:390:390)) - (PORT datac (410:410:410) (486:486:486)) - (PORT datad (267:267:267) (348:348:348)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (305:305:305) (410:410:410)) + (PORT datab (303:303:303) (399:399:399)) + (PORT datac (274:274:274) (364:364:364)) + (PORT datad (268:268:268) (349:349:349)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53143,13 +51804,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (382:382:382)) - (PORT datab (297:297:297) (390:390:390)) - (PORT datac (411:411:411) (483:483:483)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (445:445:445) (522:522:522)) + (PORT datab (419:419:419) (491:491:491)) + (PORT datac (308:308:308) (330:330:330)) + (PORT datad (197:197:197) (222:222:222)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53159,9 +51820,9 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datac (721:721:721) (791:791:791)) - (PORT datad (339:339:339) (359:359:359)) + (PORT dataa (248:248:248) (337:337:337)) + (PORT datac (886:886:886) (938:938:938)) + (PORT datad (176:176:176) (202:202:202)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53175,8 +51836,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT ena (1003:1003:1003) (1001:1001:1001)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT ena (1207:1207:1207) (1188:1188:1188)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53186,30 +51847,18 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) - (DELAY - (ABSOLUTE - (PORT datac (269:269:269) (358:358:358)) - (PORT datad (269:269:269) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (388:388:388)) - (PORT datab (297:297:297) (390:390:390)) - (PORT datac (269:269:269) (357:357:357)) - (PORT datad (269:269:269) (350:350:350)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (424:424:424) (505:505:505)) + (PORT datab (298:298:298) (389:389:389)) + (PORT datac (273:273:273) (368:368:368)) + (PORT datad (278:278:278) (358:358:358)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53219,12 +51868,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT dataa (213:213:213) (262:262:262)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (411:411:411) (481:481:481)) - (PORT datad (269:269:269) (350:350:350)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (441:441:441) (526:526:526)) + (PORT datab (454:454:454) (519:519:519)) + (PORT datac (501:501:501) (509:509:509)) + (PORT datad (352:352:352) (369:369:369)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53235,10 +51884,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) (DELAY (ABSOLUTE - (PORT dataa (749:749:749) (809:809:809)) - (PORT datab (245:245:245) (329:329:329)) - (PORT datac (723:723:723) (793:793:793)) - (PORT datad (322:322:322) (342:342:342)) + (PORT dataa (639:639:639) (715:715:715)) + (PORT datab (244:244:244) (327:327:327)) + (PORT datac (888:888:888) (940:940:940)) + (PORT datad (175:175:175) (200:200:200)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -53253,8 +51902,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT ena (1003:1003:1003) (1001:1001:1001)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT ena (1207:1207:1207) (1188:1188:1188)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53264,50 +51913,18 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (289:289:289) (388:388:388)) - (PORT datab (296:296:296) (390:390:390)) - (PORT datac (408:408:408) (482:482:482)) - (PORT datad (267:267:267) (348:348:348)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (259:259:259)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (410:410:410) (482:482:482)) - (PORT datad (267:267:267) (350:350:350)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) (DELAY (ABSOLUTE - (PORT dataa (745:745:745) (805:805:805)) - (PORT datab (245:245:245) (328:328:328)) - (PORT datac (716:716:716) (783:783:783)) - (PORT datad (340:340:340) (361:361:361)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (679:679:679) (734:734:734)) + (PORT datac (620:620:620) (667:667:667)) + (PORT datad (364:364:364) (423:423:423)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53319,8 +51936,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT ena (1003:1003:1003) (1001:1001:1001)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT ena (1410:1410:1410) (1399:1399:1399)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53335,9 +51952,9 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT dataa (366:366:366) (404:404:404)) - (PORT datab (811:811:811) (871:871:871)) - (PORT datad (386:386:386) (446:446:446)) + (PORT dataa (544:544:544) (558:558:558)) + (PORT datab (488:488:488) (559:559:559)) + (PORT datad (364:364:364) (420:420:420)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53349,10 +51966,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) - (PORT sload (1416:1416:1416) (1505:1505:1505)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT sload (1203:1203:1203) (1299:1299:1299)) (PORT ena (812:812:812) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -53370,10 +51987,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT dataa (380:380:380) (456:456:456)) - (PORT datac (719:719:719) (789:789:789)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT datab (642:642:642) (706:706:706)) + (PORT datac (893:893:893) (946:946:946)) + (PORT datad (198:198:198) (224:224:224)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53386,9 +52003,9 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sclr (1200:1200:1200) (1296:1296:1296)) - (PORT ena (1003:1003:1003) (1001:1001:1001)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sclr (1104:1104:1104) (1198:1198:1198)) + (PORT ena (1207:1207:1207) (1188:1188:1188)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53404,8 +52021,8 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) (DELAY (ABSOLUTE - (PORT datac (725:725:725) (794:794:794)) - (PORT datad (220:220:220) (289:289:289)) + (PORT datac (887:887:887) (939:939:939)) + (PORT datad (218:218:218) (287:287:287)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53418,9 +52035,9 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sclr (1200:1200:1200) (1296:1296:1296)) - (PORT ena (945:945:945) (931:931:931)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sclr (1104:1104:1104) (1198:1198:1198)) + (PORT ena (1397:1397:1397) (1366:1366:1366)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53436,12 +52053,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (388:388:388) (459:459:459)) - (PORT datab (759:759:759) (829:829:829)) - (PORT datac (591:591:591) (650:650:650)) - (PORT datad (1052:1052:1052) (1089:1089:1089)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (683:683:683) (742:742:742)) + (PORT datab (416:416:416) (490:490:490)) + (PORT datac (558:558:558) (607:607:607)) + (PORT datad (384:384:384) (444:444:444)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53452,12 +52069,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (521:521:521) (542:542:542)) - (PORT datab (565:565:565) (583:583:583)) - (PORT datac (1097:1097:1097) (1134:1134:1134)) - (PORT datad (508:508:508) (500:500:500)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (537:537:537) (561:561:561)) + (PORT datab (327:327:327) (433:433:433)) + (PORT datac (345:345:345) (368:368:368)) + (PORT datad (517:517:517) (510:510:510)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53468,13 +52085,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~2) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (346:346:346)) - (PORT datab (732:732:732) (788:788:788)) - (PORT datac (1097:1097:1097) (1134:1134:1134)) - (PORT datad (180:180:180) (207:207:207)) + (PORT dataa (254:254:254) (345:345:345)) + (PORT datab (329:329:329) (434:434:434)) + (PORT datac (260:260:260) (345:345:345)) + (PORT datad (181:181:181) (208:208:208)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53485,12 +52102,12 @@ (DELAY (ABSOLUTE (PORT dataa (255:255:255) (348:348:348)) - (PORT datab (730:730:730) (791:791:791)) - (PORT datac (1094:1094:1094) (1137:1137:1137)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (324:324:324) (431:431:431)) + (PORT datac (261:261:261) (346:346:346)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53500,12 +52117,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (586:586:586) (621:621:621)) - (PORT datab (878:878:878) (934:934:934)) - (PORT datac (174:174:174) (208:208:208)) + (PORT dataa (663:663:663) (743:743:743)) + (PORT datab (802:802:802) (828:828:828)) + (PORT datac (173:173:173) (206:206:206)) (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53517,9 +52134,9 @@ (DELAY (ABSOLUTE (PORT clk (1475:1475:1475) (1497:1497:1497)) - (PORT d (692:692:692) (731:731:731)) - (PORT aload (1737:1737:1737) (1805:1805:1805)) - (PORT ena (1070:1070:1070) (1077:1077:1077)) + (PORT d (691:691:691) (730:730:730)) + (PORT aload (1726:1726:1726) (1792:1792:1792)) + (PORT ena (1272:1272:1272) (1294:1294:1294)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -53531,13 +52148,38 @@ (HOLD ena (posedge clk) (101:101:101)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|mclk_r\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|mclk_r) (DELAY (ABSOLUTE (PORT clk (1506:1506:1506) (1528:1528:1528)) - (PORT d (2318:2318:2318) (2289:2289:2289)) + (PORT d (2379:2379:2379) (2282:2282:2282)) (PORT clrn (1763:1763:1763) (1815:1815:1815)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -53548,13 +52190,472 @@ (HOLD d (posedge clk) (97:97:97)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (777:777:777)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (277:277:277)) + (PORT datac (174:174:174) (208:208:208)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (479:479:479)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datad (328:328:328) (343:343:343)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1915:1915:1915)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (391:391:391) (458:458:458)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT datac (345:345:345) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (337:337:337)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (281:281:281)) + (PORT datac (172:172:172) (204:204:204)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (337:337:337)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) + (DELAY + (ABSOLUTE + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (481:481:481)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (365:365:365) (427:427:427)) + (PORT datad (227:227:227) (300:300:300)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (427:427:427) (491:491:491)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT datad (338:338:338) (357:357:357)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (438:438:438) (507:507:507)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT datad (333:333:333) (348:348:348)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1915:1915:1915)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (467:467:467)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) + (DELAY + (ABSOLUTE + (PORT datab (376:376:376) (401:401:401)) + (PORT datac (380:380:380) (411:411:411)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (383:383:383) (442:442:442)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) + (DELAY + (ABSOLUTE + (PORT datad (337:337:337) (357:357:357)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (468:468:468)) + (PORT datab (423:423:423) (484:484:484)) + (PORT datac (392:392:392) (453:453:453)) + (PORT datad (393:393:393) (454:454:454)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (249:249:249) (333:333:333)) + (PORT datac (664:664:664) (736:736:736)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) + (DELAY + (ABSOLUTE + (PORT datad (198:198:198) (224:224:224)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) + (DELAY + (ABSOLUTE + (PORT datab (905:905:905) (938:938:938)) + (PORT datad (233:233:233) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|lrclk_r) (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1526:1526:1526)) - (PORT d (2852:2852:2852) (3007:3007:3007)) + (PORT d (2289:2289:2289) (2450:2450:2450)) (PORT clrn (1761:1761:1761) (1813:1813:1813)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -53571,7 +52672,7 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1527:1527:1527)) - (PORT d (3253:3253:3253) (3391:3391:3391)) + (PORT d (2528:2528:2528) (2663:2663:2663)) (PORT clrn (1762:1762:1762) (1814:1814:1814)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -53582,13 +52683,528 @@ (HOLD d (posedge clk) (97:97:97)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (334:334:334)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (235:235:235) (283:283:283)) + (PORT datac (873:873:873) (896:896:896)) + (PORT datad (241:241:241) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (2714:2714:2714) (2746:2746:2746)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (333:333:333)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (2713:2713:2713) (2746:2746:2746)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (2711:2711:2711) (2744:2744:2744)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (343:343:343)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (2711:2711:2711) (2744:2744:2744)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (343:343:343)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (223:223:223) (303:303:303)) + (PORT datad (227:227:227) (299:299:299)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (269:269:269) (360:360:360)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (2710:2710:2710) (2743:2743:2743)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (538:538:538)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (344:344:344)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~20) + (DELAY + (ABSOLUTE + (PORT dataa (470:470:470) (540:540:540)) + (PORT datab (903:903:903) (940:940:940)) + (PORT datac (205:205:205) (243:243:243)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (472:472:472)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~17) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (284:284:284)) + (PORT datab (234:234:234) (285:285:285)) + (PORT datac (875:875:875) (898:898:898)) + (PORT datad (338:338:338) (359:359:359)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT datab (253:253:253) (339:339:339)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~19) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (539:539:539)) + (PORT datab (906:906:906) (939:939:939)) + (PORT datac (206:206:206) (243:243:243)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT datad (362:362:362) (417:417:417)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (285:285:285)) + (PORT datab (235:235:235) (288:288:288)) + (PORT datac (875:875:875) (900:900:900)) + (PORT datad (339:339:339) (359:359:359)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datac (368:368:368) (430:430:430)) + (PORT datad (361:361:361) (415:415:415)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (353:353:353)) + (PORT datab (217:217:217) (263:263:263)) + (PORT datac (241:241:241) (328:328:328)) + (PORT datad (373:373:373) (399:399:399)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (938:938:938)) + (PORT datab (235:235:235) (286:286:286)) + (PORT datad (375:375:375) (401:401:401)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datac (382:382:382) (450:450:450)) + (PORT datad (371:371:371) (396:396:396)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) + (DELAY + (ABSOLUTE + (PORT datab (216:216:216) (262:262:262)) + (PORT datac (239:239:239) (326:326:326)) + (PORT datad (238:238:238) (316:316:316)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (283:283:283)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (869:869:869) (882:882:882)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|bclk_r) (DELAY (ABSOLUTE (PORT clk (1504:1504:1504) (1526:1526:1526)) - (PORT d (1496:1496:1496) (1579:1579:1579)) + (PORT d (2278:2278:2278) (2430:2430:2430)) (PORT clrn (1761:1761:1761) (1813:1813:1813)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -53599,14 +53215,654 @@ (HOLD d (posedge clk) (97:97:97)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outl\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (861:861:861) (917:917:917)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1754:1754:1754) (1860:1860:1860)) + (PORT datab (1594:1594:1594) (1730:1730:1730)) + (PORT datac (1193:1193:1193) (1255:1255:1255)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|always0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (777:777:777)) + (PORT datab (1248:1248:1248) (1347:1347:1347)) + (PORT datac (1200:1200:1200) (1266:1266:1266)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (2002:2002:2002) (1998:1998:1998)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (279:279:279)) + (PORT datab (216:216:216) (259:259:259)) + (PORT datac (241:241:241) (328:328:328)) + (PORT datad (239:239:239) (317:317:317)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE AUD_ADCDAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1354:1354:1354) (1417:1417:1417)) + (PORT datab (1297:1297:1297) (1385:1385:1385)) + (PORT datad (764:764:764) (757:757:757)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1877:1877:1877) (1887:1887:1887)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT datab (244:244:244) (327:327:327)) + (PORT datad (1250:1250:1250) (1334:1334:1334)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (234:234:234) (283:283:283)) + (PORT datac (872:872:872) (895:895:895)) + (PORT datad (240:240:240) (318:318:318)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) + (DELAY + (ABSOLUTE + (PORT datac (216:216:216) (293:293:293)) + (PORT datad (1250:1250:1250) (1341:1341:1341)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) + (DELAY + (ABSOLUTE + (PORT datab (245:245:245) (328:328:328)) + (PORT datad (1259:1259:1259) (1340:1340:1340)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) + (DELAY + (ABSOLUTE + (PORT datab (246:246:246) (330:330:330)) + (PORT datad (1269:1269:1269) (1352:1352:1352)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) + (DELAY + (ABSOLUTE + (PORT datab (245:245:245) (328:328:328)) + (PORT datad (1270:1270:1270) (1351:1351:1351)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (335:335:335)) + (PORT datad (1261:1261:1261) (1348:1348:1348)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) + (DELAY + (ABSOLUTE + (PORT datab (245:245:245) (328:328:328)) + (PORT datad (1246:1246:1246) (1335:1335:1335)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) + (DELAY + (ABSOLUTE + (PORT datac (216:216:216) (292:292:292)) + (PORT datad (1248:1248:1248) (1334:1334:1334)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) + (DELAY + (ABSOLUTE + (PORT datab (244:244:244) (327:327:327)) + (PORT datad (1249:1249:1249) (1344:1344:1344)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) + (DELAY + (ABSOLUTE + (PORT datac (218:218:218) (296:296:296)) + (PORT datad (1269:1269:1269) (1350:1350:1350)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (334:334:334)) + (PORT datad (1268:1268:1268) (1351:1351:1351)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) + (DELAY + (ABSOLUTE + (PORT datab (244:244:244) (327:327:327)) + (PORT datad (1265:1265:1265) (1355:1355:1355)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1406:1406:1406) (1457:1457:1457)) + (PORT datab (896:896:896) (935:935:935)) + (PORT datad (232:232:232) (306:306:306)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1405:1405:1405) (1456:1456:1456)) + (PORT datab (896:896:896) (934:934:934)) + (PORT datad (232:232:232) (306:306:306)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outr\~0) + (DELAY + (ABSOLUTE + (PORT datac (218:218:218) (296:296:296)) + (PORT datad (219:219:219) (289:289:289)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (2116:2116:2116) (2146:2146:2146)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) + (DELAY + (ABSOLUTE + (PORT datab (1303:1303:1303) (1391:1391:1391)) + (PORT datac (218:218:218) (295:295:295)) + (PORT datad (1337:1337:1337) (1421:1421:1421)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) + (DELAY + (ABSOLUTE + (PORT datab (1222:1222:1222) (1334:1334:1334)) + (PORT datac (217:217:217) (292:292:292)) + (PORT datad (1267:1267:1267) (1356:1356:1356)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|pcm_outl\[14\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1553:1553:1553)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1232:1232:1232) (1224:1224:1224)) + (PORT ena (2262:2262:2262) (2235:2235:2235)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53620,11 +53876,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (405:405:405) (486:486:486)) - (PORT datab (1177:1177:1177) (1229:1229:1229)) - (PORT datad (364:364:364) (429:429:429)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1212:1212:1212) (1296:1296:1296)) + (PORT datac (981:981:981) (1087:1087:1087)) + (PORT datad (656:656:656) (680:680:680)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53634,10 +53890,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1866:1866:1866) (1875:1875:1875)) + (PORT clk (1895:1895:1895) (1927:1927:1927)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (2767:2767:2767) (2833:2833:2833)) + (PORT clrn (1575:1575:1575) (1569:1569:1569)) + (PORT ena (1154:1154:1154) (1136:1136:1136)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53652,10 +53908,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) (DELAY (ABSOLUTE - (PORT datab (1178:1178:1178) (1229:1229:1229)) - (PORT datac (596:596:596) (646:646:646)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (216:216:216) (293:293:293)) + (PORT datad (656:656:656) (683:683:683)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -53664,10 +53920,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1866:1866:1866) (1875:1875:1875)) + (PORT clk (1528:1528:1528) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (2767:2767:2767) (2833:2833:2833)) + (PORT clrn (1575:1575:1575) (1569:1569:1569)) + (PORT ena (1190:1190:1190) (1184:1184:1184)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53682,10 +53938,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (1181:1181:1181) (1224:1224:1224)) - (PORT datac (360:360:360) (423:423:423)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (652:652:652) (681:681:681)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -53695,9 +53951,9 @@ (DELAY (ABSOLUTE (PORT clk (1508:1508:1508) (1530:1530:1530)) - (PORT d (1935:1935:1935) (2050:2050:2050)) + (PORT d (1487:1487:1487) (1588:1588:1588)) (PORT clrn (1765:1765:1765) (1817:1817:1817)) - (PORT ena (869:869:869) (872:872:872)) + (PORT ena (1717:1717:1717) (1806:1806:1806)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -53711,10 +53967,106 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[1\]\~feeder) + (INSTANCE ula_\|video_\|LessThan2\~0) (DELAY (ABSOLUTE - (PORT datad (566:566:566) (583:583:583)) + (PORT dataa (291:291:291) (381:381:381)) + (PORT datab (270:270:270) (353:353:353)) + (PORT datac (262:262:262) (341:341:341)) + (PORT datad (244:244:244) (316:316:316)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (348:348:348)) + (PORT datab (260:260:260) (342:342:342)) + (PORT datac (255:255:255) (332:332:332)) + (PORT datad (237:237:237) (307:307:307)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (540:540:540)) + (PORT datab (270:270:270) (354:354:354)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (356:356:356) (374:374:374)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (383:383:383)) + (PORT datab (241:241:241) (280:280:280)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (361:361:361)) + (PORT datab (261:261:261) (343:343:343)) + (PORT datad (247:247:247) (320:320:320)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~0) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (410:410:410) (484:484:484)) + (PORT datad (659:659:659) (717:717:717)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~1) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (260:260:260)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datad (348:348:348) (371:371:371)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53724,23 +54076,86 @@ (INSTANCE ula_\|border\[1\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1232:1232:1232) (1224:1224:1224)) + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT asdata (537:537:537) (568:568:568)) + (PORT ena (2116:2116:2116) (2146:2146:2146)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (453:453:453) (541:541:541)) + (PORT datab (461:461:461) (551:551:551)) + (PORT datac (424:424:424) (504:504:504)) + (PORT datad (416:416:416) (444:444:444)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (361:361:361)) + (PORT datab (273:273:273) (358:358:358)) + (PORT datad (236:236:236) (304:304:304)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (522:522:522)) + (PORT datab (461:461:461) (542:542:542)) + (PORT datac (543:543:543) (561:561:561)) + (PORT datad (646:646:646) (718:718:718)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (744:744:744)) + (PORT datab (483:483:483) (561:561:561)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (354:354:354) (367:367:367)) + (PORT datad (1472:1472:1472) (1505:1505:1505)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53750,10 +54165,10 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (1188:1188:1188) (1268:1268:1268)) - (PORT datab (1478:1478:1478) (1554:1554:1554)) - (PORT datac (1186:1186:1186) (1250:1250:1250)) - (PORT datad (876:876:876) (932:932:932)) + (PORT dataa (1252:1252:1252) (1343:1343:1343)) + (PORT datab (984:984:984) (1066:1066:1066)) + (PORT datac (973:973:973) (1043:1043:1043)) + (PORT datad (280:280:280) (364:364:364)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -53766,9 +54181,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1933:1933:1933)) + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1459:1459:1459) (1451:1451:1451)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53777,25 +54192,15 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (882:882:882) (914:914:914)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (882:882:882) (938:938:938)) - (PORT datab (1203:1203:1203) (1264:1264:1264)) - (PORT datac (934:934:934) (992:992:992)) - (PORT datad (1154:1154:1154) (1209:1209:1209)) + (PORT dataa (1252:1252:1252) (1342:1342:1342)) + (PORT datab (985:985:985) (1065:1065:1065)) + (PORT datac (974:974:974) (1042:1042:1042)) + (PORT datad (280:280:280) (364:364:364)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -53808,14 +54213,14 @@ (INSTANCE ula_\|video_\|attr\[1\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1187:1187:1187) (1160:1160:1160)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (1788:1788:1788) (1847:1847:1847)) + (PORT ena (1421:1421:1421) (1414:1414:1414)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -53824,7 +54229,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (659:659:659) (671:671:671)) + (PORT datad (1546:1546:1546) (1544:1544:1544)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53834,9 +54239,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1943:1943:1943) (1967:1967:1967)) + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1255:1255:1255) (1237:1237:1237)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53851,8 +54256,8 @@ (DELAY (ABSOLUTE (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1707:1707:1707) (1750:1750:1750)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT asdata (1012:1012:1012) (1085:1085:1085)) + (PORT ena (1421:1421:1421) (1414:1414:1414)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53861,226 +54266,12 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (615:615:615) (625:625:625)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Decoder0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1269:1269:1269)) - (PORT datab (1481:1481:1481) (1551:1551:1551)) - (PORT datac (1184:1184:1184) (1246:1246:1246)) - (PORT datad (879:879:879) (933:933:933)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1905:1905:1905) (1929:1929:1929)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2367:2367:2367) (2409:2409:2409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (2051:2051:2051) (2181:2181:2181)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (658:658:658) (671:671:671)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1913:1913:1913) (1931:1931:1931)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1292:1292:1292) (1300:1300:1300)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1250:1250:1250) (1315:1315:1315)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (633:633:633) (646:646:646)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1900:1900:1900) (1925:1925:1925)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2080:2080:2080) (2091:2091:2091)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1760:1760:1760) (1824:1824:1824)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (350:350:350) (366:366:366)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1899:1899:1899) (1923:1923:1923)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2317:2317:2317) (2356:2356:2356)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1559:1559:1559) (1597:1597:1597)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (505:505:505)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (408:408:408) (473:473:473)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (504:504:504)) - (PORT datab (389:389:389) (454:454:454)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (350:350:350) (366:366:366)) + (PORT datad (1196:1196:1196) (1239:1239:1239)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54090,9 +54281,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1870:1870:1870) (1882:1882:1882)) + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1769:1769:1769) (1807:1807:1807)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54106,9 +54297,9 @@ (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1450:1450:1450) (1514:1514:1514)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (1010:1010:1010) (1078:1078:1078)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54122,9 +54313,9 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT datad (1371:1371:1371) (1372:1372:1372)) + (PORT dataa (620:620:620) (643:643:643)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54133,7 +54324,7 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54147,8 +54338,8 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (670:670:670) (727:727:727)) - (PORT datab (603:603:603) (665:665:665)) + (PORT dataa (613:613:613) (667:667:667)) + (PORT datab (243:243:243) (325:325:325)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -54162,14 +54353,14 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (951:951:951) (969:969:969)) - (PORT ena (1738:1738:1738) (1717:1717:1717)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1236:1236:1236) (1237:1237:1237)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -54178,9 +54369,9 @@ (INSTANCE ula_\|video_\|frame\[2\]\~6) (DELAY (ABSOLUTE - (PORT datab (1070:1070:1070) (1118:1118:1118)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (244:244:244) (331:331:331)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54192,14 +54383,14 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (1933:1933:1933) (1957:1957:1957)) - (PORT asdata (1218:1218:1218) (1220:1220:1220)) - (PORT ena (1428:1428:1428) (1397:1397:1397)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1236:1236:1236) (1237:1237:1237)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -54208,9 +54399,9 @@ (INSTANCE ula_\|video_\|frame\[3\]\~8) (DELAY (ABSOLUTE - (PORT dataa (387:387:387) (466:466:466)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (242:242:242) (324:324:324)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54222,9 +54413,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1291:1291:1291) (1293:1293:1293)) + (PORT ena (1236:1236:1236) (1237:1237:1237)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54238,8 +54429,8 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT datad (226:226:226) (298:298:298)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (266:266:266) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -54249,14 +54440,14 @@ (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (661:661:661) (678:678:678)) - (PORT ena (1291:1291:1291) (1293:1293:1293)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1236:1236:1236) (1237:1237:1237)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -54265,7 +54456,7 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (223:223:223) (293:293:293)) + (PORT datad (372:372:372) (423:423:423)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54273,22 +54464,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) + (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (355:355:355) (369:369:369)) + (PORT datad (1154:1154:1154) (1160:1160:1160)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Decoder0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1340:1340:1340)) + (PORT datab (986:986:986) (1064:1064:1064)) + (PORT datac (973:973:973) (1044:1044:1044)) + (PORT datad (279:279:279) (363:363:363)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[2\]) + (INSTANCE ula_\|video_\|bits_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1900:1900:1900) (1924:1924:1924)) + (PORT clk (1915:1915:1915) (1933:1933:1933)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2302:2302:2302) (2299:2299:2299)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (609:609:609) (678:678:678)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1545:1545:1545) (1541:1541:1541)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54299,12 +54558,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[2\]) + (INSTANCE ula_\|video_\|bits\[4\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1781:1781:1781) (1841:1841:1841)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (997:997:997) (1070:1070:1070)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54313,12 +54572,188 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (937:937:937) (955:955:955)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (651:651:651) (725:725:725)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1201:1201:1201) (1243:1243:1243)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (1216:1216:1216) (1295:1295:1295)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (460:460:460)) + (PORT datab (288:288:288) (377:377:377)) + (PORT datad (636:636:636) (698:698:698)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (287:287:287) (374:374:374)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (883:883:883) (890:890:890)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (640:640:640) (711:711:711)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (354:354:354) (367:367:367)) + (PORT datad (1463:1463:1463) (1429:1429:1429)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54328,9 +54763,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1906:1906:1906) (1930:1930:1930)) + (PORT clk (1915:1915:1915) (1933:1933:1933)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2324:2324:2324) (2364:2364:2364)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54344,9 +54779,9 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1205:1205:1205) (1250:1250:1250)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (978:978:978) (1047:1047:1047)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54360,7 +54795,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (354:354:354) (367:367:367)) + (PORT datad (1470:1470:1470) (1502:1502:1502)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54370,9 +54805,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1882:1882:1882) (1892:1892:1892)) + (PORT clk (1915:1915:1915) (1933:1933:1933)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2649:2649:2649) (2699:2699:2699)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54386,7 +54821,7 @@ (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (830:830:830) (872:872:872)) + (PORT datad (642:642:642) (704:704:704)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54396,9 +54831,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1547:1547:1547)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1187:1187:1187) (1160:1160:1160)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54412,8 +54847,8 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datac (622:622:622) (631:631:631)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datad (1276:1276:1276) (1241:1241:1241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54422,9 +54857,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1915:1915:1915) (1933:1933:1933)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1525:1525:1525) (1521:1521:1521)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54438,9 +54873,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (970:970:970) (1049:1049:1049)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (1448:1448:1448) (1474:1474:1474)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54454,11 +54889,11 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (424:424:424) (506:506:506)) - (PORT datab (421:421:421) (487:487:487)) - (PORT datad (411:411:411) (475:475:475)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (286:286:286) (373:373:373)) + (PORT datad (633:633:633) (694:694:694)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54469,8 +54904,8 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (421:421:421) (505:505:505)) - (PORT datab (242:242:242) (325:325:325)) + (PORT dataa (243:243:243) (329:329:329)) + (PORT datab (287:287:287) (377:377:377)) (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -54484,12 +54919,12 @@ (INSTANCE ula_\|video_\|cindex\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (938:938:938) (1004:1004:1004)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (401:401:401) (477:477:477)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (337:337:337) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54500,195 +54935,25 @@ (INSTANCE ula_\|video_\|cindex\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (430:430:430) (498:498:498)) - (PORT datad (203:203:203) (231:231:231)) + (PORT dataa (245:245:245) (332:332:332)) + (PORT datad (347:347:347) (363:363:363)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (264:264:264) (352:352:352)) - (PORT datab (262:262:262) (344:344:344)) - (PORT datac (234:234:234) (309:309:309)) - (PORT datad (235:235:235) (303:303:303)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (517:517:517)) - (PORT datab (292:292:292) (378:378:378)) - (PORT datac (404:404:404) (473:473:473)) - (PORT datad (364:364:364) (384:384:384)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (518:518:518)) - (PORT datab (272:272:272) (357:357:357)) - (PORT datac (242:242:242) (322:322:322)) - (PORT datad (397:397:397) (464:464:464)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (759:759:759)) - (PORT datab (419:419:419) (499:499:499)) - (PORT datac (656:656:656) (726:726:726)) - (PORT datad (565:565:565) (593:593:593)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~1) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (762:762:762)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (883:883:883) (937:937:937)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (383:383:383)) - (PORT datab (271:271:271) (356:356:356)) - (PORT datac (264:264:264) (345:345:345)) - (PORT datad (264:264:264) (336:336:336)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (530:530:530)) - (PORT datab (290:290:290) (374:374:374)) - (PORT datac (203:203:203) (240:240:240)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (427:427:427) (487:487:487)) - (PORT datad (245:245:245) (317:317:317)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT datab (260:260:260) (342:342:342)) - (PORT datad (242:242:242) (314:314:314)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~0) - (DELAY - (ABSOLUTE - (PORT dataa (272:272:272) (360:360:360)) - (PORT datab (262:262:262) (344:344:344)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datad (632:632:632) (661:661:661)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (2218:2218:2218) (2345:2345:2345)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (1466:1466:1466) (1485:1485:1485)) - (PORT datad (578:578:578) (587:587:587)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (398:398:398) (453:453:453)) + (PORT datab (1490:1490:1490) (1585:1585:1585)) + (PORT datac (235:235:235) (278:278:278)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54699,7 +54964,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (614:614:614) (623:623:623)) + (PORT datad (1157:1157:1157) (1161:1161:1161)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54709,9 +54974,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1876:1876:1876) (1887:1887:1887)) + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2418:2418:2418) (2490:2490:2490)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54725,9 +54990,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (2042:2042:2042) (2159:2159:2159)) - (PORT ena (1470:1470:1470) (1471:1471:1471)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1216:1216:1216) (1269:1269:1269)) + (PORT ena (1638:1638:1638) (1616:1616:1616)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54741,11 +55006,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (659:659:659) (674:674:674)) - (PORT datab (641:641:641) (652:652:652)) - (PORT datad (632:632:632) (661:661:661)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (212:212:212) (261:261:261)) + (PORT datab (208:208:208) (249:249:249)) + (PORT datad (348:348:348) (371:371:371)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54756,11 +55021,11 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1497:1497:1497) (1525:1525:1525)) - (PORT datab (207:207:207) (250:250:250)) - (PORT datad (322:322:322) (343:343:343)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (269:269:269) (322:322:322)) + (PORT datac (391:391:391) (430:430:430)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54770,9 +55035,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1553:1553:1553)) - (PORT asdata (543:543:543) (576:576:576)) - (PORT ena (1232:1232:1232) (1224:1224:1224)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (956:956:956) (977:977:977)) + (PORT ena (812:812:812) (804:804:804)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54786,7 +55051,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (349:349:349) (365:365:365)) + (PORT datad (884:884:884) (889:889:889)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54796,9 +55061,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1882:1882:1882)) + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2092:2092:2092) (2167:2167:2167)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54812,9 +55077,9 @@ (INSTANCE ula_\|video_\|attr\[2\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1737:1737:1737) (1798:1798:1798)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (1208:1208:1208) (1265:1265:1265)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54828,7 +55093,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (634:634:634) (646:646:646)) + (PORT datad (935:935:935) (952:952:952)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54838,9 +55103,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1870:1870:1870) (1883:1883:1883)) + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1883:1883:1883) (1935:1935:1935)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54854,9 +55119,9 @@ (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1552:1552:1552) (1666:1666:1666)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (993:993:993) (1051:1051:1051)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54870,9 +55135,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (330:330:330)) - (PORT datad (205:205:205) (234:234:234)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54883,13 +55148,13 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (2045:2045:2045) (2150:2150:2150)) - (PORT datab (603:603:603) (623:623:623)) - (PORT datac (1467:1467:1467) (1486:1486:1486)) - (PORT datad (184:184:184) (215:215:215)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (2313:2313:2313) (2480:2480:2480)) + (PORT datab (411:411:411) (449:449:449)) + (PORT datac (384:384:384) (420:420:420)) + (PORT datad (547:547:547) (557:557:557)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54899,33 +55164,49 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1498:1498:1498) (1523:1523:1523)) - (PORT datab (209:209:209) (252:252:252)) - (PORT datad (322:322:322) (341:341:341)) + (PORT dataa (636:636:636) (662:662:662)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datad (378:378:378) (398:398:398)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (203:203:203) (231:231:231)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1553:1553:1553)) + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT asdata (1466:1466:1466) (1519:1519:1519)) + (PORT ena (2116:2116:2116) (2146:2146:2146)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1462:1462:1462) (1430:1430:1430)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1232:1232:1232) (1224:1224:1224)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54936,22 +55217,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (INSTANCE ula_\|video_\|attr\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (354:354:354) (367:367:367)) + (PORT datad (839:839:839) (888:888:888)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (INSTANCE ula_\|video_\|attr\[0\]) (DELAY (ABSOLUTE - (PORT clk (1876:1876:1876) (1888:1888:1888)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1535:1535:1535) (1569:1569:1569)) + (PORT ena (1421:1421:1421) (1414:1414:1414)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1276:1276:1276) (1242:1242:1242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54960,46 +55267,14 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1547:1547:1547)) - (PORT asdata (1221:1221:1221) (1279:1279:1279)) - (PORT ena (1187:1187:1187) (1160:1160:1160)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1874:1874:1874) (1882:1882:1882)) - (PORT asdata (1233:1233:1233) (1251:1251:1251)) - (PORT ena (1796:1796:1796) (1819:1819:1819)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1547:1547:1547)) - (PORT asdata (894:894:894) (950:950:950)) - (PORT ena (1187:1187:1187) (1160:1160:1160)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (965:965:965) (1040:1040:1040)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55013,9 +55288,9 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datad (351:351:351) (366:366:366)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datab (384:384:384) (459:459:459)) + (PORT datad (204:204:204) (232:232:232)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55026,13 +55301,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (2201:2201:2201) (2354:2354:2354)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (546:546:546) (551:551:551)) - (PORT datad (529:529:529) (539:539:539)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (399:399:399) (453:453:453)) + (PORT datab (1662:1662:1662) (1745:1745:1745)) + (PORT datac (233:233:233) (279:279:279)) + (PORT datad (334:334:334) (354:354:354)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55042,9 +55317,9 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (858:858:858) (859:859:859)) - (PORT datac (579:579:579) (582:582:582)) - (PORT datad (586:586:586) (589:589:589)) + (PORT dataa (269:269:269) (323:323:323)) + (PORT datac (391:391:391) (429:429:429)) + (PORT datad (340:340:340) (359:359:359)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -55056,11 +55331,11 @@ (INSTANCE ula_\|video_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (1553:1553:1553) (1640:1640:1640)) - (PORT datac (1191:1191:1191) (1249:1249:1249)) - (PORT datad (1156:1156:1156) (1225:1225:1225)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (681:681:681) (753:753:753)) + (PORT datab (282:282:282) (364:364:364)) + (PORT datad (645:645:645) (715:715:715)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55070,7 +55345,7 @@ (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -55084,11 +55359,11 @@ (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (377:377:377)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datad (204:204:204) (232:232:232)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1030:1030:1030) (1035:1035:1035)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datad (571:571:571) (575:575:575)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55100,7 +55375,7 @@ (DELAY (ABSOLUTE (PORT clk (1509:1509:1509) (1531:1531:1531)) - (PORT d (1706:1706:1706) (1786:1786:1786)) + (PORT d (1715:1715:1715) (1721:1721:1721)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -55114,7 +55389,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -55128,11 +55403,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (224:224:224) (268:268:268)) - (PORT datab (724:724:724) (792:792:792)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (620:620:620) (642:642:642)) + (PORT datab (1174:1174:1174) (1179:1179:1179)) + (PORT datad (691:691:691) (762:762:762)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55144,7 +55419,7 @@ (DELAY (ABSOLUTE (PORT clk (1507:1507:1507) (1529:1529:1529)) - (PORT d (1568:1568:1568) (1673:1673:1673)) + (PORT d (1805:1805:1805) (1839:1839:1839)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -55158,7 +55433,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (256:256:256) (332:332:332)) + (PORT datad (620:620:620) (667:667:667)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55168,10 +55443,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1537:1537:1537) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (1483:1483:1483) (1473:1473:1473)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55186,10 +55461,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (561:561:561) (635:635:635)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) + (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT asdata (560:560:560) (634:634:634)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (1483:1483:1483) (1473:1473:1473)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55204,7 +55479,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (249:249:249) (324:324:324)) + (PORT datad (621:621:621) (666:666:666)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55215,9 +55490,9 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT dataa (675:675:675) (793:793:793)) - (PORT datad (252:252:252) (327:327:327)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT datac (1282:1282:1282) (1346:1346:1346)) + (PORT datad (621:621:621) (669:669:669)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55227,12 +55502,10 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT dataa (823:823:823) (851:851:851)) - (PORT datab (910:910:910) (958:958:958)) - (PORT datac (860:860:860) (898:898:898)) - (PORT datad (688:688:688) (779:779:779)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (1714:1714:1714) (1839:1839:1839)) + (PORT datac (3217:3217:3217) (3502:3502:3502)) + (PORT datad (1247:1247:1247) (1342:1342:1342)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55243,9 +55516,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) + (PORT clk (1515:1515:1515) (1529:1529:1529)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1475:1475:1475) (1461:1461:1461)) + (PORT ena (2564:2564:2564) (2572:2572:2572)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo index 1a17ab4..1f3d9fd 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/31/2022 14:04:23" +// DATE "04/01/2022 18:55:51" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -49,14 +49,15 @@ module spectrum ( VGA_VS, SW, GPIO_1, - buzzer_out); + buzzer_out, + raw_loader_in); output [7:0] LED; input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -inout I2C_SCLK; -inout I2C_SDAT; +output I2C_SCLK; +output I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -71,6 +72,7 @@ output VGA_VS; input [3:0] SW; output [33:0] GPIO_1; output buzzer_out; +input raw_loader_in; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -141,10 +143,11 @@ output buzzer_out; // I2C_SDAT => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[1] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: Default // SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// raw_loader_in => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: Default // KEY[0] => Location: PIN_J15, I/O Standard: 3.3-V LVTTL, Current Strength: Default // CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default -// KEY[1] => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_DAT => Location: PIN_B7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// KEY[1] => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_CLK => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default // AUD_ADCDAT => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -175,7 +178,692 @@ wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; +wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; wire \z80_|sequencer_|ena_M~combout ; +wire \KEY[1]~input_o ; +wire \z80_|interrupts_|nmi_armed~feeder_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; +wire \z80_|interrupts_|nmi_armed~q ; +wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~q ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~q ; +wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal1~7_combout ; +wire \z80_|pla_decode_|Equal2~0_combout ; +wire \z80_|pla_decode_|Equal36~0_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|pla_decode_|Equal2~1_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_sw_1d~8_combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~1_combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; +wire \z80_|execute_|ctl_state_iy_set~2_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|pla_decode_|Equal50~0_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|execute_|ixy_d~17_combout ; +wire \z80_|execute_|ixy_d~5_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~15_combout ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|execute_|ctl_ir_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~14_combout ; +wire \z80_|execute_|ctl_mWrite~2_combout ; +wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|ctl_reg_in_hi~5_combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|pla_decode_|Equal9~0_combout ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|pla_decode_|Equal9~1_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|pla_decode_|Equal1~4_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; +wire \z80_|pla_decode_|Equal24~1_combout ; +wire \z80_|pla_decode_|Equal34~0_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|sequencer_|M5~0_combout ; +wire \z80_|sequencer_|M5~q ; +wire \z80_|execute_|ctl_reg_in_hi~2_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; +wire \z80_|execute_|ctl_ir_we~7_combout ; +wire \z80_|pla_decode_|Equal52~1_combout ; +wire \z80_|execute_|ctl_state_alu~14_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|execute_|fMRead~17_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|fMRead~16_combout ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_flags_alu~6_combout ; +wire \z80_|execute_|ctl_ir_we~6_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_reg_in_hi~3_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; +wire \z80_|execute_|ctl_mRead~36_combout ; +wire \z80_|execute_|ctl_alu_op_low~9_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|execute_|ctl_alu_op_low~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|alu_|db_low[2]~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|pla_decode_|Equal1~5_combout ; +wire \z80_|execute_|ctl_alu_op_low~14_combout ; +wire \z80_|execute_|ctl_alu_op_low~12_combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~11_combout ; +wire \z80_|execute_|nextM~2_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_oe~3_combout ; +wire \z80_|execute_|ctl_alu_op_low~15_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~13_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|ctl_flags_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op_low~13_combout ; +wire \z80_|execute_|ctl_flags_bus~15_combout ; +wire \z80_|execute_|ctl_flags_bus~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|execute_|ctl_flags_bus~12_combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_bus_db_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|execute_|ctl_alu_op_low~10_combout ; +wire \z80_|execute_|fMWrite~11_combout ; +wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|execute_|ctl_alu_op_low~22_combout ; +wire \z80_|execute_|ctl_alu_op_low~16_combout ; +wire \z80_|execute_|ctl_alu_op_low~17_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_gp_sel~36_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_alu_op_low~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~19_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_alu_op_low~20_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~14_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|execute_|ctl_flags_alu~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|pla_decode_|Equal11~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; +wire \z80_|execute_|ctl_alu_oe~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_oe~15_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; +wire \z80_|alu_|db_low[2]~24_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_alu_oe~12_combout ; +wire \z80_|execute_|ctl_alu_oe~13_combout ; +wire \z80_|execute_|ctl_alu_oe~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; +wire \z80_|execute_|ctl_reg_out_hi~8_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|execute_|ctl_sw_2u~1_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_inc_cy~35_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_mWrite~6_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_sw_2u~0_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~7_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|execute_|ctl_inc_cy~34_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~92_combout ; +wire \z80_|pla_decode_|Equal19~1_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_inc_cy~38_combout ; +wire \z80_|execute_|ctl_inc_cy~93_combout ; +wire \z80_|execute_|ctl_inc_cy~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; +wire \z80_|execute_|ctl_reg_gp_we~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|fMRead~3_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; +wire \z80_|execute_|ctl_inc_cy~94_combout ; +wire \z80_|execute_|ctl_inc_cy~87_combout ; +wire \z80_|execute_|ctl_inc_cy~42_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|pla_decode_|Equal1~6_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~12_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~13_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|fMWrite~3_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~7_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_sw_1d~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|execute_|setM1~47_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_al_we~13_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_reg_in_hi~13_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_inc_cy~40_combout ; +wire \z80_|execute_|ctl_inc_dec~2_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_inc_cy~43_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_state_alu~13_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_state_alu~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|reg_control_|reg_sel_de2~5_combout ; +wire \z80_|reg_control_|reg_sel_de2~6_combout ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_al_we~14_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|ctl_flags_bus~13_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|pc_inc_hold~49_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|fMRead~5_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; +wire \z80_|execute_|pc_inc_hold~29_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|execute_|ctl_reg_in_hi~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; +wire \z80_|execute_|fMRead~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; +wire \z80_|execute_|fMRead~1_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|ctl_sw_4d~1_combout ; +wire \z80_|execute_|ctl_sw_4d~0_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|execute_|fMRead~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; wire \KEY[0]~input_o ; wire \reset~combout ; @@ -184,801 +872,92 @@ wire \z80_|fpga_reset~feeder_combout ; wire \z80_|fpga_reset~q ; wire \z80_|fpga_reset~clkctrl_outclk ; wire \z80_|resets_|x1~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \KEY[1]~input_o ; -wire \z80_|interrupts_|nmi_armed~feeder_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; -wire \z80_|interrupts_|nmi_armed~q ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|execute_|ctl_ir_we~4_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|pla_decode_|Equal9~0_combout ; -wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|sequencer_|M5~0_combout ; -wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; -wire \z80_|execute_|ctl_mWrite~3_combout ; -wire \z80_|execute_|ctl_mWrite~16_combout ; -wire \z80_|execute_|ixy_d~4_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|pla_decode_|Equal41~1_combout ; -wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ixy_d~8_combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|pla_decode_|Equal19~0_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|execute_|ctl_state_alu~2_combout ; -wire \z80_|execute_|ctl_inc_cy~36_combout ; -wire \z80_|execute_|ctl_inc_dec~0_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|fMWrite~0_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|pla_decode_|Equal19~1_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; -wire \z80_|execute_|ctl_state_alu~3_combout ; -wire \z80_|execute_|ctl_inc_cy~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|execute_|ctl_inc_cy~30_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|fMWrite~1_combout ; -wire \z80_|execute_|fMWrite~2_combout ; -wire \z80_|execute_|fMWrite~3_combout ; -wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|execute_|ctl_inc_cy~34_combout ; -wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|execute_|ctl_inc_cy~35_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|execute_|ctl_mRead~38_combout ; -wire \z80_|execute_|fIOWrite~1_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|execute_|fMRead~2_combout ; -wire \z80_|execute_|ctl_mWrite~2_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|execute_|ctl_inc_cy~32_combout ; -wire \z80_|execute_|ctl_inc_cy~33_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; -wire \z80_|address_pins_|abus[0]~18_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|WideOr16~5_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|WideOr16~7_combout ; -wire \ula_|zx_keyboard_|WideOr16~6_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|pc_inc_hold~19_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|ctl_inc_cy~37_combout ; -wire \z80_|execute_|ctl_inc_dec~1_combout ; -wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; wire \z80_|resets_|clrpc_int~0_combout ; wire \z80_|resets_|clrpc_int~q ; wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|execute_|ctl_inc_cy~47_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|execute_|ctl_inc_cy~38_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|fMRead~12_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~3_combout ; -wire \z80_|execute_|fMRead~13_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~25_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|nextM~11_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~8_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_reg_in_hi~13_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_we~9_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_we~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~8_combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_sel~5_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|pla_decode_|Equal11~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|ctl_iorw~12_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; -wire \z80_|execute_|ctl_bus_db_oe~2_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|pla_decode_|Equal76~0_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~7_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; -wire \z80_|execute_|setM1~56_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~40_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|pc_inc_hold~18_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ; -wire \z80_|execute_|pc_inc_hold~40_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~11_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|ctl_alu_op_low~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_flags_alu~6_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_flags_alu~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~19_combout ; -wire \z80_|execute_|ctl_flags_alu~7_combout ; -wire \z80_|execute_|ctl_flags_alu~9_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|reg_control_|reg_sel_de2~6_combout ; -wire \z80_|reg_control_|reg_sel_de2~5_combout ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~22_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; -wire \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~23_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~24_combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~26_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~25_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~39_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|fMRead~11_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~28_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~29_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~30_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_bus_db_oe~6_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|fMRead~9_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|alu_|db[7]~19_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~52_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~53_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~56_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_file_|db_hi_as[3]~13_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|db_hi_as[3]~14_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; wire \z80_|execute_|ctl_apin_mux~1_combout ; wire \z80_|execute_|ctl_al_we~6_combout ; wire \z80_|execute_|ctl_al_we~7_combout ; wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; wire \z80_|execute_|ctl_al_we~11_combout ; wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|execute_|ctl_inc_cy~78_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|reg_file_|db_hi_as[3]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~57_combout ; -wire \z80_|alu_|db[3]~13_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_sz_we~5_combout ; -wire \z80_|execute_|ctl_flags_sz_we~6_combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_flags_xy_we~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~14_combout ; -wire \z80_|execute_|ctl_flags_xy_we~15_combout ; -wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[3]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|Add0~15 ; wire \ula_|video_|Add0~16_combout ; wire \ula_|video_|vga_hc~2_combout ; wire \ula_|video_|Add0~17 ; wire \ula_|video_|Add0~18_combout ; wire \ula_|video_|vga_hc~1_combout ; -wire \ula_|video_|Equal0~0_combout ; -wire \ula_|video_|Equal0~1_combout ; -wire \ula_|video_|Equal1~0_combout ; +wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; wire \ula_|video_|Add0~1 ; wire \ula_|video_|Add0~2_combout ; +wire \ula_|video_|vga_hc[1]~feeder_combout ; wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; -wire \ula_|video_|vga_hc[2]~feeder_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; +wire \ula_|video_|vga_hc[3]~feeder_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; +wire \ula_|video_|Equal0~0_combout ; +wire \ula_|video_|Equal0~1_combout ; +wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add0~9 ; wire \ula_|video_|Add0~10_combout ; wire \ula_|video_|vga_hc~0_combout ; @@ -987,8 +966,6 @@ wire \ula_|video_|Add0~12_combout ; wire \ula_|video_|Add0~13 ; wire \ula_|video_|Add0~14_combout ; wire \ula_|video_|Add1~0_combout ; -wire \ula_|video_|vga_vc[0]~0_combout ; -wire \ula_|video_|Add1~1 ; wire \ula_|video_|Add1~3 ; wire \ula_|video_|Add1~4_combout ; wire \ula_|video_|vga_vc[2]~2_combout ; @@ -1010,22 +987,24 @@ wire \ula_|video_|vga_vc[7]~6_combout ; wire \ula_|video_|Add1~15 ; wire \ula_|video_|Add1~16_combout ; wire \ula_|video_|vga_vc[8]~7_combout ; -wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Add1~17 ; wire \ula_|video_|Add1~18_combout ; wire \ula_|video_|vga_vc[9]~9_combout ; +wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~0_combout ; wire \ula_|video_|Equal3~1_combout ; +wire \ula_|video_|vga_vc[0]~0_combout ; +wire \ula_|video_|Add1~1 ; wire \ula_|video_|Add1~2_combout ; wire \ula_|video_|vga_vc[1]~1_combout ; wire \SW[1]~input_o ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|iff1~0_combout ; wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; wire \z80_|interrupts_|DFFE_instIFF2~q ; +wire \z80_|interrupts_|iff1~0_combout ; wire \z80_|interrupts_|iff1~1_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; wire \z80_|interrupts_|iff1~q ; @@ -1033,875 +1012,787 @@ wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|interrupts_|int_armed~q ; -wire \z80_|interrupts_|DFFE_inst44~feeder_combout ; wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_cy~49_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~22_combout ; -wire \z80_|execute_|pc_inc_hold~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~23_combout ; -wire \z80_|execute_|pc_inc_hold~25_combout ; -wire \z80_|execute_|pc_inc_hold~20_combout ; -wire \z80_|execute_|pc_inc_hold~41_combout ; -wire \z80_|execute_|pc_inc_hold~21_combout ; -wire \z80_|execute_|pc_inc_hold~26_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|ctl_inc_cy~43_combout ; -wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~42_combout ; -wire \z80_|execute_|pc_inc_hold~27_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|ctl_inc_cy~40_combout ; -wire \z80_|execute_|ctl_inc_cy~41_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~42_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; -wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|pc_inc_hold~38_combout ; +wire \z80_|execute_|ctl_inc_cy~91_combout ; +wire \z80_|execute_|pc_inc_hold~45_combout ; +wire \z80_|execute_|pc_inc_hold~44_combout ; +wire \z80_|execute_|pc_inc_hold~46_combout ; +wire \z80_|execute_|pc_inc_hold~37_combout ; +wire \z80_|execute_|pc_inc_hold~50_combout ; wire \z80_|execute_|pc_inc_hold~33_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~31_combout ; +wire \z80_|execute_|pc_inc_hold~32_combout ; +wire \z80_|execute_|pc_inc_hold~34_combout ; +wire \z80_|execute_|pc_inc_hold~51_combout ; +wire \z80_|execute_|pc_inc_hold~30_combout ; +wire \z80_|execute_|pc_inc_hold~52_combout ; +wire \z80_|execute_|pc_inc_hold~35_combout ; +wire \z80_|execute_|pc_inc_hold~36_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|pc_inc_hold~43_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_inc_cy~46_combout ; +wire \z80_|execute_|pc_inc_hold~53_combout ; +wire \z80_|execute_|pc_inc_hold~39_combout ; +wire \z80_|execute_|pc_inc_hold~47_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|execute_|ctl_inc_cy~78_combout ; +wire \z80_|execute_|ctl_inc_cy~79_combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~82_combout ; +wire \z80_|execute_|ctl_inc_cy~83_combout ; +wire \z80_|execute_|ctl_inc_cy~84_combout ; +wire \z80_|execute_|pc_inc_hold~42_combout ; +wire \z80_|execute_|ctl_inc_cy~90_combout ; +wire \z80_|execute_|pc_inc_hold~41_combout ; wire \z80_|execute_|ctl_inc_cy~66_combout ; wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~31_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op_low~39_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|pla_decode_|Equal72~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~0_combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; -wire \z80_|execute_|ctl_flags_nf_we~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|execute_|ctl_alu_op_low~38_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_alu_core_R~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~35_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|alu_|db_high[3]~0_combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|alu_|db_high[3]~1_combout ; -wire \z80_|alu_|db_low[3]~2_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|alu_|db_low[3]~3_combout ; -wire \z80_|alu_|db_low[3]~4_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|db_high[2]~25_combout ; -wire \z80_|reg_file_|db_hi_as[6]~0_combout ; -wire \z80_|reg_file_|db_hi_as[6]~1_combout ; -wire \z80_|reg_file_|db_hi_as[6]~3_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~14_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~8_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~21_combout ; -wire \z80_|interrupts_|im2~feeder_combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|sw1_|db_down[6]~0_combout ; -wire \z80_|alu_|db_low[1]~10_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|alu_|db_high[1]~3_combout ; -wire \z80_|alu_|db_high[1]~2_combout ; -wire \z80_|alu_|db[7]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~74_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~75_combout ; -wire \z80_|alu_|db[5]~23_combout ; -wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~22_combout ; -wire \z80_|reg_file_|db_hi_as[4]~23_combout ; -wire \z80_|reg_file_|db_hi_as[4]~24_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~77_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~79_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~82_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~84_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_inc_cy~36_combout ; +wire \z80_|execute_|ctl_inc_cy~37_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~41_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~89_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|execute_|ctl_inc_cy~48_combout ; +wire \z80_|execute_|pc_inc_hold~40_combout ; +wire \z80_|execute_|ctl_inc_cy~61_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|ctl_inc_cy~85_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|address_latch_|Q[0]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_|alu_op1[2]~2_combout ; -wire \z80_|alu_|alu_op1[1]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|db[1]~15_combout ; -wire \z80_|alu_|db[1]~16_combout ; -wire \z80_|reg_file_|db_hi_as[0]~10_combout ; -wire \z80_|reg_file_|db_hi_as[0]~11_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; -wire \z80_|reg_file_|db_lo_as[6]~19_combout ; -wire \z80_|reg_file_|db_lo_as[6]~20_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; -wire \z80_|reg_file_|db_lo_as[5]~16_combout ; -wire \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|db_lo_as[5]~17_combout ; -wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|Q[5]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|db_lo_as[6]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|address_latch_|Q[7]~feeder_combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; +wire \z80_|address_latch_|Q[2]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; +wire \z80_|execute_|ctl_inc_cy~86_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; +wire \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|db_hi_as[1]~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|reg_file_|db_hi_as[0]~2_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~41_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~44_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~45_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~43_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~46_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~40_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~47_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~48_combout ; -wire \z80_|alu_|db[0]~17_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_low[0]~16_combout ; -wire \z80_|alu_|db_low[0]~17_combout ; -wire \z80_|alu_|db_low[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|reg_file_|db_hi_as[0]~4_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[1]~3_combout ; +wire \z80_|address_latch_|Q[9]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; +wire \z80_|reg_file_|db_hi_as[2]~7_combout ; +wire \z80_|reg_file_|db_hi_as[2]~8_combout ; +wire \z80_|reg_file_|db_hi_as[2]~9_combout ; +wire \z80_|address_latch_|Q[10]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|db_hi_as[3]~10_combout ; +wire \z80_|reg_file_|db_hi_as[3]~11_combout ; +wire \z80_|reg_file_|db_hi_as[3]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|alu_|alu_op1[3]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~20_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~21_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_flags_sz_we~4_combout ; +wire \z80_|pla_decode_|Equal71~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; +wire \z80_|pla_decode_|Equal72~2_combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|execute_|ctl_flags_nf_we~1_combout ; +wire \z80_|execute_|ctl_flags_nf_we~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; +wire \z80_|execute_|ctl_flags_sz_we~5_combout ; +wire \z80_|execute_|ctl_flags_sz_we~6_combout ; +wire \z80_|execute_|ctl_flags_nf_we~4_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|ctl_flags_xy_we~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~7_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; +wire \z80_|execute_|ctl_flags_alu~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~19_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|alu_|alu_op2[1]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~38_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~43_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|execute_|ctl_alu_core_hf~42_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~41_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~44_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~39_combout ; +wire \z80_|execute_|ctl_alu_core_hf~40_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ; +wire \z80_|alu_|alu_op2[3]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; wire \z80_|execute_|ctl_flags_hf_we~3_combout ; wire \z80_|execute_|ctl_flags_hf_we~4_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_alu_core_hf~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|execute_|ctl_alu_core_hf~16_combout ; -wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; -wire \z80_|execute_|ctl_flags_nf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~9_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|execute_|ctl_alu_core_hf~15_combout ; -wire \z80_|execute_|ctl_alu_core_hf~17_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|execute_|ctl_alu_core_hf~39_combout ; -wire \z80_|execute_|ctl_alu_core_hf~40_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; -wire \z80_|alu_|db_high[0]~8_combout ; -wire \z80_|alu_|db_high[0]~9_combout ; -wire \z80_|alu_|db_high[0]~10_combout ; -wire \z80_|alu_|db_high[0]~11_combout ; -wire \z80_|alu_|db_high[0]~12_combout ; -wire \z80_|alu_|db_high[0]~13_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|alu_|alu_op2[0]~1_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_low[0]~18_combout ; -wire \z80_|alu_|db_low[0]~20_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|address_latch_|Q[12]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[4]~16_combout ; +wire \z80_|reg_file_|db_hi_as[4]~17_combout ; +wire \z80_|reg_file_|db_hi_as[4]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; +wire \z80_|alu_|db[4]~16_combout ; +wire \z80_|alu_|db[7]~26_combout ; +wire \z80_|alu_|db[4]~17_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|db_high[0]~26_combout ; wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|alu_op1[0]~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|alu_|alu_op1[0]~1_combout ; wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|alu_op1[1]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|alu_|alu_op1[2]~2_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|alu_|db_low[2]~7_combout ; -wire \z80_|alu_|db_low[2]~8_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~63_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~61_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~64_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~58_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~65_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~66_combout ; -wire \z80_|alu_|db[2]~11_combout ; -wire \z80_|alu_|db[2]~12_combout ; -wire \z80_|alu_|db_low[2]~5_combout ; -wire \z80_|alu_|db_low[2]~6_combout ; -wire \z80_|alu_|db_low[2]~9_combout ; -wire \z80_|alu_|db_low[2]~22_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|alu_control_|db[2]~19_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; +wire \z80_|reg_file_|db_hi_as[7]~19_combout ; +wire \z80_|reg_file_|db_hi_as[7]~20_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; +wire \z80_|reg_file_|db_hi_as[5]~13_combout ; +wire \z80_|reg_file_|db_hi_as[5]~14_combout ; +wire \z80_|reg_file_|db_hi_as[5]~15_combout ; +wire \z80_|address_latch_|Q[13]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; +wire \z80_|reg_file_|db_hi_as[6]~22_combout ; +wire \z80_|reg_file_|db_hi_as[6]~23_combout ; +wire \z80_|reg_file_|db_hi_as[6]~24_combout ; +wire \z80_|address_latch_|Q[14]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|reg_file_|db_hi_as[7]~21_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; +wire \z80_|alu_|db[7]~20_combout ; +wire \z80_|alu_|db[7]~21_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~4_combout ; +wire \z80_|alu_|db_high[3]~27_combout ; +wire \z80_|alu_|db_high[3]~7_combout ; +wire \z80_|alu_|db_high[3]~8_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ; +wire \z80_|alu_|db_low[3]~9_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|alu_|db_low[3]~10_combout ; +wire \z80_|alu_|db_low[3]~7_combout ; +wire \z80_|alu_|db_low[3]~8_combout ; +wire \z80_|alu_|db_low[3]~11_combout ; +wire \z80_|alu_|db_low[3]~25_combout ; +wire \z80_|alu_|db[3]~10_combout ; +wire \z80_|alu_|db[3]~11_combout ; wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|alu_control_|db[1]~23_combout ; -wire \z80_|alu_control_|db[1]~24_combout ; -wire \z80_|alu_control_|db[1]~25_combout ; -wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|Q[1]~feeder_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; -wire \z80_|alu_control_|db[4]~30_combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \z80_|alu_|db[4]~8_combout ; -wire \z80_|alu_|db[4]~10_combout ; -wire \z80_|alu_|db_high[1]~4_combout ; -wire \z80_|alu_|db_high[1]~5_combout ; -wire \z80_|alu_|db_high[1]~6_combout ; -wire \z80_|alu_|db_high[1]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|alu_op2[1]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; -wire \z80_|alu_|db_low[1]~11_combout ; -wire \z80_|alu_|db_low[1]~12_combout ; -wire \z80_|alu_|db_low[1]~13_combout ; -wire \z80_|alu_|db_low[1]~14_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_control_|db[6]~13_combout ; -wire \z80_|alu_control_|db[6]~14_combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; +wire \z80_|execute_|ctl_flags_xy_we~13_combout ; +wire \z80_|execute_|ctl_flags_xy_we~14_combout ; +wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|alu_flags_|flags_xf~q ; +wire \z80_|alu_control_|db[3]~33_combout ; wire \z80_|execute_|ctl_reg_out_lo~3_combout ; wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; wire \z80_|execute_|ctl_reg_out_lo~4_combout ; wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; -wire \z80_|alu_control_|db[6]~15_combout ; -wire \z80_|alu_|db[6]~21_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db_high[2]~20_combout ; -wire \z80_|alu_|db_high[2]~21_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout ; -wire \z80_|alu_|db_high[2]~22_combout ; -wire \z80_|alu_|db_high[2]~23_combout ; -wire \z80_|alu_|db_high[2]~24_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|alu_op2[2]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~37_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~11_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|alu_control_|db[0]~8_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~9_combout ; -wire \z80_|alu_control_|db[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|sw1_|db_down[3]~1_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; -wire \z80_|sw1_|db_down[3]~2_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|alu_|db[3]~14_combout ; -wire \z80_|alu_|db_low[3]~0_combout ; -wire \z80_|alu_|db_low[3]~1_combout ; -wire \z80_|alu_|db_low[3]~23_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout ; -wire \z80_|alu_|alu_op2[3]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ; -wire \z80_|alu_|db_high[3]~14_combout ; -wire \z80_|alu_|db_high[3]~15_combout ; -wire \z80_|alu_|db_high[3]~16_combout ; -wire \z80_|alu_|db_high[3]~17_combout ; -wire \z80_|alu_|db_high[3]~18_combout ; -wire \z80_|alu_|db_high[3]~19_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_control_|db[7]~16_combout ; -wire \z80_|reg_file_|db_lo_ds[7]~1_combout ; +wire \z80_|reg_file_|db_lo_as[3]~10_combout ; +wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|reg_file_|db_lo_as[3]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; +wire \z80_|reg_file_|db_lo_as[4]~13_combout ; +wire \z80_|reg_file_|db_lo_as[4]~14_combout ; +wire \z80_|reg_file_|db_lo_as[4]~15_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; +wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; +wire \z80_|reg_file_|db_lo_as[5]~16_combout ; +wire \z80_|reg_file_|db_lo_as[5]~17_combout ; +wire \z80_|reg_file_|db_lo_as[5]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|db_lo_as[6]~19_combout ; +wire \z80_|reg_file_|db_lo_as[6]~20_combout ; +wire \z80_|reg_file_|db_lo_as[6]~21_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; +wire \z80_|reg_file_|db_lo_ds[7]~0_combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; wire \z80_|alu_control_|db[7]~17_combout ; +wire \z80_|alu_control_|db[7]~16_combout ; wire \z80_|alu_control_|db[7]~18_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; -wire \z80_|alu_|alu_parity_out~0_combout ; -wire \z80_|alu_|alu_parity_out~combout ; -wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; wire \z80_|execute_|ctl_flags_pf_we~5_combout ; wire \z80_|execute_|ctl_flags_pf_we~6_combout ; wire \z80_|execute_|ctl_flags_pf_we~7_combout ; wire \z80_|execute_|ctl_flags_pf_we~8_combout ; wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~11_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; wire \z80_|decode_state_|DFFE_instNonRep~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; +wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|alu_parity_out~0_combout ; +wire \z80_|alu_|alu_parity_out~combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~14_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~13_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; +wire \z80_|alu_control_|sel[1]~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; +wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; wire \z80_|alu_control_|flags_cond_true~0_combout ; wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~32_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~33_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~36_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~34_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~35_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~37_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~38_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~39_combout ; -wire \z80_|reg_file_|db_hi_as[1]~7_combout ; -wire \z80_|reg_file_|db_hi_as[1]~8_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~9_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[2]~16_combout ; -wire \z80_|reg_file_|db_hi_as[2]~17_combout ; -wire \z80_|reg_file_|db_hi_as[2]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[5]~19_combout ; -wire \z80_|reg_file_|db_hi_as[5]~20_combout ; -wire \z80_|reg_file_|db_hi_as[5]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~4_combout ; -wire \z80_|reg_file_|db_hi_as[7]~5_combout ; -wire \z80_|reg_file_|db_hi_as[7]~6_combout ; -wire \z80_|execute_|ctl_apin_mux~2_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; -wire \z80_|execute_|ctl_apin_mux2~0_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|fIORead~3_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; -wire \z80_|address_pins_|abus[15]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; -wire \z80_|address_pins_|abus[14]~16_combout ; -wire \D[1]~27_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~19_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; -wire \z80_|address_pins_|abus[10]~22_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; -wire \z80_|address_pins_|abus[11]~21_combout ; -wire \D[1]~25_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~24_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; -wire \z80_|address_pins_|abus[13]~23_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \D[1]~26_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~20_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \ula_|zx_keyboard_|keys[1][1]~20_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~21_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \D[1]~24_combout ; -wire \D[1]~28_combout ; -wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; -wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; -wire \z80_|memory_ifc_|wait_iorqinta~q ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|ctl_iorw~8_combout ; -wire \z80_|execute_|ctl_iorw~9_combout ; -wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; -wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; -wire \z80_|memory_ifc_|wait_iorq~q ; -wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; -wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|memory_ifc_|nIORQ_out~0_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|execute_|setM1~57_combout ; -wire \z80_|execute_|setM1~39_combout ; -wire \z80_|execute_|ctl_mRead~36_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|ctl_mRead~35_combout ; -wire \z80_|execute_|ctl_mRead~40_combout ; -wire \z80_|execute_|ctl_mRead~39_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|nextM~4_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; +wire \z80_|reg_file_|db_lo_ds[1]~1_combout ; +wire \z80_|alu_control_|db[1]~25_combout ; +wire \z80_|alu_control_|db[1]~24_combout ; +wire \z80_|alu_control_|db[1]~26_combout ; +wire \z80_|alu_|db[1]~12_combout ; +wire \z80_|alu_|db[1]~13_combout ; +wire \z80_|alu_|db_low[0]~21_combout ; +wire \z80_|alu_|db_low[0]~22_combout ; +wire \z80_|alu_|db_low[0]~18_combout ; +wire \z80_|alu_|db_low[0]~19_combout ; +wire \z80_|alu_|db_low[0]~20_combout ; +wire \z80_|alu_|db_low[0]~23_combout ; +wire \z80_|alu_|db[0]~18_combout ; +wire \z80_|alu_|db[0]~19_combout ; +wire \z80_|alu_|db_low[1]~15_combout ; +wire \z80_|alu_|db_low[1]~16_combout ; +wire \z80_|alu_|db_low[1]~12_combout ; +wire \z80_|alu_|db_low[1]~13_combout ; +wire \z80_|alu_|db_low[1]~14_combout ; +wire \z80_|alu_|db_low[1]~17_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|db[2]~23_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|alu_control_|db[2]~27_combout ; +wire \z80_|alu_control_|db[2]~29_combout ; +wire \z80_|alu_|db[2]~14_combout ; +wire \z80_|alu_|db[2]~15_combout ; +wire \z80_|alu_|db_low[2]~2_combout ; +wire \z80_|alu_|db_low[2]~3_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ; +wire \z80_|alu_|db_low[2]~5_combout ; +wire \z80_|alu_|db_low[2]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ; +wire \z80_|alu_|alu_op2[2]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|alu_|db_high[2]~14_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|alu_|db[6]~23_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_control_|db[6]~19_combout ; +wire \z80_|alu_control_|db[6]~20_combout ; +wire \z80_|alu_control_|db[6]~21_combout ; +wire \z80_|alu_control_|db[6]~22_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|interrupts_|im1~q ; +wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; +wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; +wire \z80_|bus_control_|db[0]~4_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; wire \z80_|execute_|ctl_mRead~37_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|setM1~55_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|nextM~3_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|execute_|ctl_mRead~35_combout ; wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; wire \z80_|memory_ifc_|wait_mrd~q ; wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|execute_|nextM~4_combout ; +wire \z80_|execute_|ctl_iorw~12_combout ; +wire \z80_|execute_|ctl_iorw~8_combout ; +wire \z80_|execute_|ctl_iorw~9_combout ; +wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; +wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; +wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; +wire \z80_|memory_ifc_|wait_iorq~q ; +wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; +wire \z80_|memory_ifc_|iorq~0_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|fIORead~3_combout ; wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; wire \z80_|memory_ifc_|nRD_out~0_combout ; wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \Equal2~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~0_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|execute_|fMWrite~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; +wire \z80_|execute_|fMWrite~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|execute_|fMWrite~8_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; +wire \z80_|execute_|fMWrite~10_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; +wire \z80_|clk_delay_|DFF_inst5~q ; +wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; +wire \z80_|memory_ifc_|wait_iorqinta~q ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; +wire \z80_|memory_ifc_|nIORQ_out~0_combout ; wire \Equal2~0_combout ; -wire \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; wire \ExtRamWE~0_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \z80_|execute_|ctl_apin_mux2~0_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; +wire \z80_|address_pins_|abus[13]~20_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; +wire \z80_|address_pins_|abus[14]~23_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; +wire \z80_|address_pins_|abus[15]~22_combout ; wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \z80_|address_pins_|abus[0]~16_combout ; wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|address_pins_|abus[1]~25_combout ; wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; @@ -1916,18 +1807,29 @@ wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; wire \z80_|address_pins_|abus[6]~30_combout ; wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; wire \z80_|address_pins_|abus[7]~31_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~18_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~17_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; +wire \z80_|address_pins_|abus[10]~24_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|address_pins_|abus[11]~19_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~21_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \D[6]~90_combout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \D[6]~91_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; wire \CLOCK_50~inputclkctrl_outclk ; wire \~GND~combout ; +wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; @@ -1940,9 +1842,9 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; wire \ula_|video_|vram_address[9]~1_combout ; wire \ula_|video_|Add4~13 ; @@ -1954,505 +1856,469 @@ wire \ula_|video_|vram_address[10]~2_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \Selector1~0_combout ; -wire \Selector1~1_combout ; -wire \D[1]~22_combout ; -wire \D[1]~23_combout ; -wire \D[1]~29_combout ; -wire \D[1]~31_combout ; -wire \z80_|pin_control_|bus_db_pin_re~2_combout ; -wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[1]~12_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|bus_control_|db[0]~6_combout ; -wire \z80_|bus_control_|db[1]~13_combout ; -wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; -wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~feeder_combout ; -wire \z80_|memory_ifc_|mwr_wr~q ; -wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \D[0]~30_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \D[6]~87_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \Selector6~0_combout ; -wire \D[6]~70_combout ; -wire \D[6]~71_combout ; -wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; -wire \ula_|zx_keyboard_|keys[5][4]~64_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~135_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \D[3]~55_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~95_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~96_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~97_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~99_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~q ; -wire \D[3]~54_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~136_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~109_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~137_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~110_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \ula_|zx_keyboard_|keys[5][3]~106_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \D[3]~56_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~115_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~116_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~139_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~140_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; -wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \D[3]~57_combout ; -wire \D[3]~58_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \Selector3~0_combout ; -wire \Selector3~1_combout ; -wire \D[3]~52_combout ; -wire \D[3]~53_combout ; -wire \D[3]~76_combout ; -wire \D[3]~77_combout ; -wire \ula_|always0~0_combout ; -wire \ula_|always0~1_combout ; -wire \ula_|i2s_intf_|mclk_r~0_combout ; -wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|Add0~1_cout ; -wire \ula_|i2s_intf_|Add0~2_combout ; -wire \ula_|i2s_intf_|lrdivider~2_combout ; -wire \ula_|i2s_intf_|Add0~3 ; -wire \ula_|i2s_intf_|Add0~4_combout ; -wire \ula_|i2s_intf_|lrdivider[2]~8_combout ; -wire \ula_|i2s_intf_|Add0~5 ; -wire \ula_|i2s_intf_|Add0~6_combout ; -wire \ula_|i2s_intf_|lrdivider[3]~7_combout ; -wire \ula_|i2s_intf_|Add0~7 ; -wire \ula_|i2s_intf_|Add0~8_combout ; -wire \ula_|i2s_intf_|lrdivider~1_combout ; -wire \ula_|i2s_intf_|Add0~9 ; -wire \ula_|i2s_intf_|Add0~10_combout ; -wire \ula_|i2s_intf_|lrdivider[5]~6_combout ; -wire \ula_|i2s_intf_|Add0~11 ; -wire \ula_|i2s_intf_|Add0~12_combout ; -wire \ula_|i2s_intf_|lrdivider[6]~5_combout ; -wire \ula_|i2s_intf_|Add0~13 ; -wire \ula_|i2s_intf_|Add0~14_combout ; -wire \ula_|i2s_intf_|lrdivider[7]~4_combout ; -wire \ula_|i2s_intf_|Add0~15 ; -wire \ula_|i2s_intf_|Add0~16_combout ; -wire \ula_|i2s_intf_|lrdivider~0_combout ; -wire \ula_|i2s_intf_|Add0~17 ; -wire \ula_|i2s_intf_|Add0~18_combout ; -wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; -wire \ula_|i2s_intf_|Equal0~0_combout ; -wire \ula_|i2s_intf_|Equal0~1_combout ; -wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|bitcount[0]~5_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; -wire \ula_|i2s_intf_|bclk_r~0_combout ; -wire \ula_|i2s_intf_|Add2~7_cout ; -wire \ula_|i2s_intf_|Add2~8_combout ; -wire \ula_|i2s_intf_|Add2~20_combout ; -wire \ula_|i2s_intf_|Add2~9 ; -wire \ula_|i2s_intf_|Add2~10_combout ; -wire \ula_|i2s_intf_|Add2~17_combout ; -wire \ula_|i2s_intf_|Add2~11 ; -wire \ula_|i2s_intf_|Add2~12_combout ; -wire \ula_|i2s_intf_|Add2~19_combout ; -wire \ula_|i2s_intf_|Add2~13 ; -wire \ula_|i2s_intf_|Add2~14_combout ; -wire \ula_|i2s_intf_|Add2~16_combout ; -wire \ula_|i2s_intf_|Equal1~0_combout ; -wire \ula_|i2s_intf_|shiftreg[8]~1_combout ; -wire \ula_|i2s_intf_|Add2~18_combout ; -wire \ula_|i2s_intf_|Equal1~1_combout ; -wire \ula_|i2s_intf_|bclk_r~1_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|bitcount[4]~15_combout ; -wire \ula_|i2s_intf_|bitcount[0]~6 ; -wire \ula_|i2s_intf_|bitcount[1]~7_combout ; -wire \ula_|i2s_intf_|bitcount[1]~8 ; -wire \ula_|i2s_intf_|bitcount[2]~9_combout ; -wire \ula_|i2s_intf_|bitcount[2]~10 ; -wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|bitcount[3]~12 ; -wire \ula_|i2s_intf_|bitcount[4]~13_combout ; -wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; -wire \AUD_ADCDAT~input_o ; -wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; -wire \ula_|i2s_intf_|shiftreg~18_combout ; -wire \ula_|i2s_intf_|shiftreg[8]~2_combout ; -wire \ula_|i2s_intf_|shiftreg~17_combout ; -wire \ula_|i2s_intf_|shiftreg~16_combout ; -wire \ula_|i2s_intf_|shiftreg~15_combout ; -wire \ula_|i2s_intf_|shiftreg~14_combout ; -wire \ula_|i2s_intf_|shiftreg~13_combout ; -wire \ula_|i2s_intf_|shiftreg~12_combout ; -wire \ula_|i2s_intf_|shiftreg~11_combout ; -wire \ula_|i2s_intf_|shiftreg~10_combout ; -wire \ula_|i2s_intf_|shiftreg~9_combout ; -wire \ula_|i2s_intf_|shiftreg~8_combout ; -wire \ula_|i2s_intf_|shiftreg~7_combout ; -wire \ula_|i2s_intf_|lrclk_r~0_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; -wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; -wire \ula_|ula_data~0_combout ; -wire \ula_|i2s_intf_|shiftreg~6_combout ; -wire \ula_|i2s_intf_|shiftreg~5_combout ; -wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; -wire \D[6]~72_combout ; -wire \D[6]~73_combout ; -wire \D[6]~74_combout ; -wire \D[6]~81_combout ; -wire \z80_|bus_control_|db[6]~5_combout ; -wire \z80_|bus_control_|db[6]~7_combout ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|alu_control_|db[6]~10_combout ; -wire \z80_|alu_control_|db[6]~11_combout ; -wire \z80_|alu_control_|db[2]~20_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; -wire \z80_|alu_control_|db[2]~21_combout ; -wire \z80_|alu_control_|db[2]~22_combout ; -wire \z80_|bus_control_|db[2]~10_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~59_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~133_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~132_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~34_combout ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~55_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \D[2]~33_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~48_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \D[2]~32_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~63_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~67_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \ula_|zx_keyboard_|keys[5][0]~68_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~71_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; -wire \D[2]~35_combout ; -wire \D[2]~36_combout ; -wire \D[2]~83_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \Selector0~0_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \Selector0~1_combout ; -wire \D[2]~37_combout ; -wire \D[2]~38_combout ; -wire \D[2]~39_combout ; -wire \D[2]~40_combout ; -wire \z80_|bus_control_|db[2]~11_combout ; -wire \z80_|pla_decode_|Equal3~1_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|execute_|ctl_bus_db_oe~4_combout ; -wire \z80_|execute_|ctl_bus_db_oe~5_combout ; -wire \z80_|execute_|ctl_bus_db_oe~combout ; -wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \D[0]~45_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \D[0]~44_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~134_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~93_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \D[0]~46_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~77_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~74_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~75_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~76_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~73_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \D[0]~43_combout ; -wire \D[0]~47_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \Selector2~0_combout ; -wire \Selector2~1_combout ; -wire \D[0]~41_combout ; -wire \D[0]~42_combout ; -wire \D[0]~48_combout ; -wire \D[0]~49_combout ; -wire \z80_|bus_control_|db[0]~14_combout ; -wire \z80_|bus_control_|db[0]~15_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|sw1_|db_down[5]~1_combout ; +wire \D[6]~88_combout ; +wire \D[6]~89_combout ; +wire \D[6]~111_combout ; +wire \raw_loader_in~input_o ; +wire \D[6]~86_combout ; +wire \D[6]~100_combout ; +wire \D[6]~101_combout ; +wire \z80_|pin_control_|bus_db_pin_re~2_combout ; +wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; +wire \z80_|bus_control_|db[6]~9_combout ; +wire \z80_|ir_|opcode[6]~feeder_combout ; +wire \z80_|execute_|ctl_ir_we~13_combout ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal41~1_combout ; +wire \z80_|pla_decode_|Equal41~2_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|db_high[1]~20_combout ; +wire \z80_|alu_|db[5]~24_combout ; +wire \z80_|alu_|db[5]~25_combout ; +wire \z80_|sw1_|db_down[5]~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; wire \z80_|alu_flags_|flags_yf~q ; -wire \z80_|alu_control_|db[5]~27_combout ; -wire \z80_|alu_control_|db[5]~28_combout ; -wire \z80_|alu_control_|db[5]~29_combout ; -wire \D[5]~68_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \z80_|alu_control_|db[5]~13_combout ; +wire \z80_|alu_control_|db[5]~14_combout ; +wire \z80_|alu_control_|db[5]~15_combout ; +wire \D[0]~107_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \Mux2~0_combout ; wire \Mux2~1_combout ; -wire \D[5]~88_combout ; -wire \D[5]~69_combout ; -wire \D[5]~80_combout ; -wire \z80_|bus_control_|db[5]~16_combout ; -wire \z80_|bus_control_|db[5]~17_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; -wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|fMRead~28_combout ; -wire \z80_|execute_|fMRead~30_combout ; +wire \D[5]~110_combout ; +wire \D[5]~85_combout ; +wire \D[5]~99_combout ; +wire \z80_|bus_control_|db[5]~14_combout ; +wire \z80_|bus_control_|db[5]~15_combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|fMRead~34_combout ; wire \z80_|execute_|fMRead~31_combout ; wire \z80_|execute_|fMRead~29_combout ; +wire \z80_|execute_|fMRead~30_combout ; +wire \z80_|execute_|fMRead~28_combout ; wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~37_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~35_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; +wire \z80_|execute_|fMRead~14_combout ; wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~11_combout ; +wire \z80_|execute_|fMRead~12_combout ; +wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|fMRead~15_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|pc_inc_hold~48_combout ; wire \z80_|execute_|fMRead~22_combout ; +wire \z80_|execute_|fMRead~21_combout ; wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|pc_inc_hold~39_combout ; wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|fMRead~36_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|fMRead~35_combout ; wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \Mux0~0_combout ; -wire \Mux0~1_combout ; -wire \D[7]~89_combout ; -wire \D[7]~75_combout ; -wire \D[7]~82_combout ; -wire \z80_|bus_control_|db[7]~8_combout ; -wire \z80_|bus_control_|db[7]~9_combout ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; -wire \z80_|interrupts_|im1~q ; -wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; -wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|pla_decode_|Equal21~0_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; -wire \z80_|execute_|ctl_bus_db_we~4_combout ; -wire \z80_|execute_|ctl_bus_db_we~6_combout ; -wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; -wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[4][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~128_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \D[4]~64_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~138_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \Selector1~0_combout ; +wire \Selector1~1_combout ; +wire \D[1]~103_combout ; +wire \PS2_DAT~input_o ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; +wire \ula_|zx_keyboard_|shifted~0_combout ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~23_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \D[1]~30_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \ula_|zx_keyboard_|key_row~0_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~19_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~21_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \D[1]~28_combout ; +wire \D[1]~29_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; +wire \ula_|zx_keyboard_|WideOr16~5_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|WideOr16~7_combout ; +wire \ula_|zx_keyboard_|WideOr16~6_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; +wire \D[1]~31_combout ; +wire \D[1]~32_combout ; +wire \D[1]~33_combout ; +wire \D[1]~34_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; +wire \z80_|bus_control_|db[1]~11_combout ; +wire \z80_|ir_|opcode[1]~feeder_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|execute_|ctl_flags_cf_set~0_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|alu_control_|db[0]~8_combout ; +wire \z80_|sw2_|db_up[0]~0_combout ; +wire \z80_|alu_control_|db[0]~9_combout ; +wire \z80_|alu_control_|db[0]~12_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~67_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \D[0]~49_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys~76_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~73_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~74_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; +wire \ula_|zx_keyboard_|keys[1][0]~71_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \D[0]~47_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \ula_|zx_keyboard_|keys[3][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \ula_|zx_keyboard_|key_row~1_combout ; +wire \D[0]~48_combout ; +wire \ula_|zx_keyboard_|shifted~1_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|keys[5][4]~63_combout ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~132_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \D[0]~50_combout ; +wire \D[0]~51_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~55_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \D[0]~56_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \D[0]~52_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~53_combout ; +wire \D[0]~54_combout ; +wire \D[0]~106_combout ; +wire \D[0]~57_combout ; +wire \D[0]~58_combout ; +wire \z80_|bus_control_|db[0]~16_combout ; +wire \z80_|bus_control_|db[0]~17_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|alu_control_|db[6]~10_combout ; +wire \z80_|alu_control_|db[6]~11_combout ; +wire \z80_|alu_control_|db[4]~30_combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \z80_|alu_control_|db[4]~32_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~95_combout ; wire \ula_|zx_keyboard_|keys[2][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~123_combout ; wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \D[4]~63_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~129_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \ula_|zx_keyboard_|keys[6][4]~130_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~131_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~136_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~130_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \D[4]~78_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~128_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~129_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \ula_|zx_keyboard_|keys[6][4]~127_combout ; wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \D[4]~65_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~118_combout ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \D[4]~79_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \ula_|zx_keyboard_|key_row~3_combout ; +wire \D[4]~80_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~97_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~116_combout ; wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~115_combout ; wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~62_combout ; -wire \D[4]~66_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \D[4]~77_combout ; +wire \D[4]~81_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; wire \Selector4~0_combout ; wire \Selector4~1_combout ; -wire \D[4]~60_combout ; -wire \D[4]~61_combout ; -wire \D[4]~78_combout ; -wire \D[4]~79_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ; +wire \D[4]~109_combout ; +wire \D[4]~97_combout ; +wire \D[4]~98_combout ; wire \z80_|bus_control_|db[4]~18_combout ; wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|pla_decode_|Equal21~0_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_mWrite~13_combout ; +wire \z80_|execute_|ctl_mWrite~14_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; +wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; +wire \z80_|memory_ifc_|wait_mwr~q ; +wire \z80_|memory_ifc_|mwr_wr~q ; +wire \z80_|memory_ifc_|nWR_out~0_combout ; +wire \D[5]~84_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Mux0~0_combout ; +wire \Mux0~1_combout ; +wire \D[7]~112_combout ; +wire \D[7]~94_combout ; +wire \D[7]~102_combout ; +wire \z80_|bus_control_|db[7]~5_combout ; +wire \z80_|bus_control_|db[7]~7_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|execute_|ctl_mWrite~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_bus_db_we~8_combout ; +wire \z80_|execute_|ctl_bus_db_we~2_combout ; +wire \z80_|execute_|ctl_bus_db_we~4_combout ; +wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_bus_db_we~7_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \ula_|zx_keyboard_|keys[3][3]~48_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \D[2]~35_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~131_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \D[2]~37_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \D[2]~36_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \D[2]~38_combout ; +wire \D[2]~39_combout ; +wire \D[2]~104_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \D[2]~43_combout ; +wire \D[2]~44_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \D[2]~40_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \D[2]~41_combout ; +wire \D[2]~42_combout ; +wire \D[2]~105_combout ; +wire \D[2]~45_combout ; +wire \D[2]~46_combout ; +wire \z80_|bus_control_|db[2]~12_combout ; +wire \z80_|bus_control_|db[2]~13_combout ; +wire \z80_|pla_decode_|Equal3~1_combout ; wire \z80_|pla_decode_|Equal43~0_combout ; wire \z80_|interrupts_|test1~2_combout ; wire \z80_|interrupts_|test1~3_combout ; @@ -2463,83 +2329,151 @@ wire \z80_|clk_delay_|hold_clk_iorq~combout ; wire \z80_|sequencer_|DFFE_T1_ff~q ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; -wire \z80_|sequencer_|DFFE_T3_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|setM1~53_combout ; -wire \z80_|execute_|nextM~3_combout ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; +wire \z80_|execute_|ctl_mWrite~3_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|execute_|nextM~8_combout ; wire \z80_|execute_|nextM~9_combout ; wire \z80_|execute_|nextM~10_combout ; wire \z80_|execute_|nextM~12_combout ; wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~5_combout ; +wire \z80_|execute_|nextM~6_combout ; wire \z80_|execute_|nextM~7_combout ; -wire \z80_|execute_|nextM~8_combout ; wire \z80_|execute_|nextM~13_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|nextM~5_combout ; wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; wire \z80_|sequencer_|T6~q ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~41_combout ; wire \z80_|execute_|setM1~42_combout ; wire \z80_|execute_|setM1~43_combout ; wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~16_combout ; wire \z80_|execute_|setM1~50_combout ; wire \z80_|execute_|setM1~51_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~6_combout ; +wire \z80_|execute_|setM1~7_combout ; wire \z80_|execute_|setM1~8_combout ; wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~53_combout ; +wire \z80_|execute_|setM1~23_combout ; wire \z80_|execute_|setM1~18_combout ; wire \z80_|execute_|setM1~19_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~54_combout ; wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~34_combout ; wire \z80_|execute_|setM1~52_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_inc_cy~39_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~37_combout ; -wire \z80_|execute_|pc_inc_hold~38_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; +wire \z80_|sequencer_|DFFE_T3_ff~q ; +wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|execute_|ctl_bus_db_oe~2_combout ; +wire \z80_|execute_|ctl_bus_db_oe~5_combout ; +wire \z80_|execute_|ctl_bus_db_oe~6_combout ; +wire \z80_|execute_|ctl_bus_db_oe~4_combout ; +wire \z80_|execute_|ctl_bus_db_oe~combout ; +wire \z80_|bus_control_|db[0]~6_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~q ; +wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~q ; +wire \D[3]~65_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~133_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \D[3]~66_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~134_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~135_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \D[3]~67_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~q ; +wire \ula_|zx_keyboard_|keys[6][3]~109_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~110_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~137_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~138_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \ula_|zx_keyboard_|key_row~2_combout ; +wire \D[3]~68_combout ; +wire \D[3]~69_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \D[3]~73_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \D[3]~74_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \D[3]~70_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~71_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~72_combout ; +wire \D[3]~108_combout ; +wire \D[3]~95_combout ; +wire \D[3]~96_combout ; +wire \z80_|bus_control_|db[3]~20_combout ; +wire \z80_|bus_control_|db[3]~21_combout ; +wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \z80_|execute_|ctl_apin_mux~2_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~84_combout ; -wire \D[0]~50_combout ; -wire \D[1]~85_combout ; -wire \D[1]~51_combout ; -wire \D[3]~86_combout ; -wire \D[3]~59_combout ; -wire \D[4]~87_combout ; -wire \D[4]~67_combout ; +wire \D[0]~59_combout ; +wire \D[0]~60_combout ; +wire \D[1]~61_combout ; +wire \D[1]~62_combout ; +wire \D[2]~63_combout ; +wire \D[2]~64_combout ; +wire \D[3]~75_combout ; +wire \D[3]~76_combout ; +wire \D[4]~82_combout ; +wire \D[4]~83_combout ; +wire \D[6]~92_combout ; +wire \D[6]~93_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2547,6 +2481,7 @@ wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ; wire \z80_|memory_ifc_|DFFE_mreq_ff2~q ; wire \z80_|memory_ifc_|nMREQ_out~0_combout ; wire \z80_|memory_ifc_|nMREQ_out~1_combout ; +wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|divider[0]~15_combout ; wire \ula_|i2c_loader_|divider[1]~5_combout ; @@ -2563,35 +2498,24 @@ wire \ula_|i2c_loader_|WideAnd0~combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; +wire \ula_|i2c_loader_|nbit~5_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|Mux42~0_combout ; -wire \ula_|i2c_loader_|nbit~6_combout ; -wire \ula_|i2c_loader_|nbyte~0_combout ; +wire \ula_|i2c_loader_|nbyte~4_combout ; wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; wire \I2C_SDAT~input_o ; wire \ula_|i2c_loader_|nbyte[0]~1_combout ; wire \ula_|i2c_loader_|nbyte[0]~2_combout ; wire \ula_|i2c_loader_|nbyte[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~4_combout ; +wire \ula_|i2c_loader_|state.Stop~0_combout ; +wire \ula_|i2c_loader_|state.Stop~1_combout ; +wire \ula_|i2c_loader_|state.Stop~q ; +wire \ula_|i2c_loader_|state.Idle~0_combout ; +wire \ula_|i2c_loader_|nbit~0_combout ; wire \ula_|i2c_loader_|state.Done~0_combout ; wire \ula_|i2c_loader_|state.Ack~0_combout ; wire \ula_|i2c_loader_|state.Ack~1_combout ; -wire \ula_|i2c_loader_|state.Ack~2_combout ; wire \ula_|i2c_loader_|state.Ack~q ; -wire \ula_|i2c_loader_|state~24_combout ; -wire \ula_|i2c_loader_|state~26_combout ; -wire \ula_|i2c_loader_|state~27_combout ; -wire \ula_|i2c_loader_|state.Data~0_combout ; -wire \ula_|i2c_loader_|state.Data~q ; -wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|nbit~0_combout ; -wire \ula_|i2c_loader_|state.Done~1_combout ; -wire \ula_|i2c_loader_|state.Done~2_combout ; -wire \ula_|i2c_loader_|state.Pause~2_combout ; -wire \ula_|i2c_loader_|state.Pause~0_combout ; -wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|nbyte[1]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; @@ -2601,29 +2525,43 @@ wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; wire \ula_|i2c_loader_|Equal2~0_combout ; +wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|state.Done~2_combout ; +wire \ula_|i2c_loader_|state.Pause~2_combout ; wire \ula_|i2c_loader_|state.Pause~3_combout ; wire \ula_|i2c_loader_|state.Pause~q ; wire \ula_|i2c_loader_|state~25_combout ; wire \ula_|i2c_loader_|state.Start~q ; -wire \ula_|i2c_loader_|nbyte~4_combout ; -wire \ula_|i2c_loader_|state.Stop~0_combout ; -wire \ula_|i2c_loader_|state.Stop~1_combout ; -wire \ula_|i2c_loader_|state.Stop~q ; +wire \ula_|i2c_loader_|nbyte~0_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit[0]~4_combout ; +wire \ula_|i2c_loader_|nbit~6_combout ; +wire \ula_|i2c_loader_|state.Done~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; +wire \ula_|i2c_loader_|state~24_combout ; +wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|state.Data~0_combout ; +wire \ula_|i2c_loader_|state.Data~q ; wire \ula_|i2c_loader_|scl_out~0_combout ; wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|scl_out~1_combout ; wire \ula_|i2c_loader_|scl_out~2_combout ; wire \ula_|i2c_loader_|scl_out~q ; wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; +wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|Mux35~0_combout ; +wire \ula_|i2c_loader_|shiftreg~13_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~15_combout ; wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|shiftreg~21_combout ; wire \ula_|i2c_loader_|shiftreg~22_combout ; wire \ula_|i2c_loader_|shiftreg~23_combout ; @@ -2632,12 +2570,9 @@ wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; wire \ula_|i2c_loader_|shiftreg~18_combout ; wire \ula_|i2c_loader_|shiftreg~19_combout ; wire \ula_|i2c_loader_|shiftreg~20_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; wire \ula_|i2c_loader_|shiftreg~16_combout ; wire \ula_|i2c_loader_|shiftreg~17_combout ; wire \ula_|i2c_loader_|shiftreg~26_combout ; -wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~15_combout ; wire \ula_|i2c_loader_|shiftreg~25_combout ; wire \ula_|i2c_loader_|shiftreg~12_combout ; wire \ula_|i2c_loader_|shiftreg~9_combout ; @@ -2648,31 +2583,120 @@ wire \ula_|i2c_loader_|sda_out~2_combout ; wire \ula_|i2c_loader_|sda_out~3_combout ; wire \ula_|i2c_loader_|sda_out~4_combout ; wire \ula_|i2c_loader_|sda_out~q ; +wire \ula_|i2s_intf_|mclk_r~0_combout ; +wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|mclk_r~q ; +wire \ula_|i2s_intf_|Add0~1_cout ; +wire \ula_|i2s_intf_|Add0~2_combout ; +wire \ula_|i2s_intf_|lrdivider~2_combout ; +wire \ula_|i2s_intf_|Add0~3 ; +wire \ula_|i2s_intf_|Add0~4_combout ; +wire \ula_|i2s_intf_|lrdivider[2]~8_combout ; +wire \ula_|i2s_intf_|Add0~5 ; +wire \ula_|i2s_intf_|Add0~6_combout ; +wire \ula_|i2s_intf_|lrdivider[3]~7_combout ; +wire \ula_|i2s_intf_|Add0~7 ; +wire \ula_|i2s_intf_|Add0~8_combout ; +wire \ula_|i2s_intf_|lrdivider~1_combout ; +wire \ula_|i2s_intf_|Add0~9 ; +wire \ula_|i2s_intf_|Add0~10_combout ; +wire \ula_|i2s_intf_|lrdivider[5]~6_combout ; +wire \ula_|i2s_intf_|Equal0~1_combout ; +wire \ula_|i2s_intf_|Add0~11 ; +wire \ula_|i2s_intf_|Add0~12_combout ; +wire \ula_|i2s_intf_|lrdivider[6]~5_combout ; +wire \ula_|i2s_intf_|Add0~13 ; +wire \ula_|i2s_intf_|Add0~14_combout ; +wire \ula_|i2s_intf_|lrdivider[7]~4_combout ; +wire \ula_|i2s_intf_|Add0~15 ; +wire \ula_|i2s_intf_|Add0~16_combout ; +wire \ula_|i2s_intf_|lrdivider~0_combout ; +wire \ula_|i2s_intf_|Add0~17 ; +wire \ula_|i2s_intf_|Add0~18_combout ; +wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; +wire \ula_|i2s_intf_|Equal0~0_combout ; +wire \ula_|i2s_intf_|Equal0~2_combout ; +wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; +wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; +wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|bitcount[0]~5_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|bitcount[4]~15_combout ; +wire \ula_|i2s_intf_|bitcount[0]~6 ; +wire \ula_|i2s_intf_|bitcount[1]~7_combout ; +wire \ula_|i2s_intf_|bitcount[1]~8 ; +wire \ula_|i2s_intf_|bitcount[2]~9_combout ; +wire \ula_|i2s_intf_|bitcount[2]~10 ; +wire \ula_|i2s_intf_|bitcount[3]~11_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|bitcount[3]~12 ; +wire \ula_|i2s_intf_|bitcount[4]~13_combout ; +wire \ula_|i2s_intf_|Add2~7_cout ; +wire \ula_|i2s_intf_|Add2~8_combout ; +wire \ula_|i2s_intf_|Add2~20_combout ; +wire \ula_|i2s_intf_|Add2~9 ; +wire \ula_|i2s_intf_|Add2~10_combout ; +wire \ula_|i2s_intf_|Add2~17_combout ; +wire \ula_|i2s_intf_|Add2~11 ; +wire \ula_|i2s_intf_|Add2~12_combout ; +wire \ula_|i2s_intf_|Add2~19_combout ; +wire \ula_|i2s_intf_|Add2~13 ; +wire \ula_|i2s_intf_|Add2~14_combout ; +wire \ula_|i2s_intf_|Add2~16_combout ; +wire \ula_|i2s_intf_|Equal1~0_combout ; +wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; +wire \ula_|i2s_intf_|Add2~18_combout ; +wire \ula_|i2s_intf_|Equal1~1_combout ; +wire \ula_|i2s_intf_|bclk_r~0_combout ; +wire \ula_|i2s_intf_|bclk_r~1_combout ; wire \ula_|i2s_intf_|bclk_r~q ; +wire \ula_|pcm_outl[13]~feeder_combout ; +wire \ula_|always0~2_combout ; +wire \ula_|always0~3_combout ; +wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; +wire \AUD_ADCDAT~input_o ; +wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; +wire \ula_|i2s_intf_|shiftreg~18_combout ; +wire \ula_|i2s_intf_|shiftreg[4]~2_combout ; +wire \ula_|i2s_intf_|shiftreg~17_combout ; +wire \ula_|i2s_intf_|shiftreg~16_combout ; +wire \ula_|i2s_intf_|shiftreg~15_combout ; +wire \ula_|i2s_intf_|shiftreg~14_combout ; +wire \ula_|i2s_intf_|shiftreg~13_combout ; +wire \ula_|i2s_intf_|shiftreg~12_combout ; +wire \ula_|i2s_intf_|shiftreg~11_combout ; +wire \ula_|i2s_intf_|shiftreg~10_combout ; +wire \ula_|i2s_intf_|shiftreg~9_combout ; +wire \ula_|i2s_intf_|shiftreg~8_combout ; +wire \ula_|i2s_intf_|shiftreg~7_combout ; +wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; +wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; +wire \ula_|pcm_outr~0_combout ; +wire \ula_|i2s_intf_|shiftreg~6_combout ; +wire \ula_|i2s_intf_|shiftreg~5_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|border[1]~feeder_combout ; +wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|video_|LessThan6~0_combout ; +wire \ula_|video_|LessThan2~1_combout ; +wire \ula_|video_|LessThan3~0_combout ; +wire \ula_|video_|LessThan0~0_combout ; +wire \ula_|video_|disp_enable~0_combout ; +wire \ula_|video_|disp_enable~1_combout ; +wire \ula_|video_|LessThan6~1_combout ; +wire \ula_|video_|LessThan4~0_combout ; +wire \ula_|video_|screen_en~0_combout ; +wire \ula_|video_|screen_en~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|Decoder0~1_combout ; -wire \ula_|video_|attr[1]~feeder_combout ; wire \ula_|video_|Decoder0~0_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[4]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[6]~feeder_combout ; -wire \ula_|video_|Decoder0~2_combout ; -wire \ula_|video_|bits_prefetch[4]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[5]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[7]~feeder_combout ; -wire \ula_|video_|Mux0~0_combout ; -wire \ula_|video_|Mux0~1_combout ; wire \ula_|video_|attr_prefetch[7]~feeder_combout ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; @@ -2683,8 +2707,20 @@ wire \ula_|video_|frame[3]~8_combout ; wire \ula_|video_|frame[3]~9 ; wire \ula_|video_|frame[4]~10_combout ; wire \ula_|video_|inverted~combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[6]~feeder_combout ; +wire \ula_|video_|Decoder0~2_combout ; +wire \ula_|video_|bits[6]~feeder_combout ; +wire \ula_|video_|bits_prefetch[4]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[5]~feeder_combout ; +wire \ula_|video_|bits[5]~feeder_combout ; +wire \ula_|video_|bits_prefetch[7]~feeder_combout ; +wire \ula_|video_|Mux0~0_combout ; +wire \ula_|video_|Mux0~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[2]~feeder_combout ; +wire \ula_|video_|bits[2]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[0]~feeder_combout ; wire \ula_|video_|bits_prefetch[1]~feeder_combout ; @@ -2695,17 +2731,6 @@ wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; wire \ula_|video_|cindex[1]~0_combout ; wire \ula_|video_|cindex[1]~1_combout ; -wire \ula_|video_|LessThan6~0_combout ; -wire \ula_|video_|LessThan6~1_combout ; -wire \ula_|video_|LessThan4~0_combout ; -wire \ula_|video_|screen_en~0_combout ; -wire \ula_|video_|screen_en~1_combout ; -wire \ula_|video_|LessThan2~0_combout ; -wire \ula_|video_|LessThan2~1_combout ; -wire \ula_|video_|LessThan3~0_combout ; -wire \ula_|video_|LessThan0~0_combout ; -wire \ula_|video_|disp_enable~0_combout ; -wire \ula_|video_|disp_enable~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; @@ -2715,8 +2740,9 @@ wire \ula_|video_|attr_prefetch[5]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; -wire \ula_|border[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[0]~feeder_combout ; +wire \ula_|video_|attr[0]~feeder_combout ; +wire \ula_|video_|attr_prefetch[3]~feeder_combout ; wire \ula_|video_|cindex[0]~3_combout ; wire \ula_|video_|VGA_B[0]~1_combout ; wire \ula_|video_|VGA_B[1]~2_combout ; @@ -2751,13 +2777,11 @@ wire [4:0] \ula_|video_|frame ; wire [7:0] \ula_|video_|bits_prefetch ; wire [7:0] \ula_|video_|attr_prefetch ; wire [7:0] \ula_|ps2_keyboard_|clk_filter ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; @@ -2768,9 +2792,10 @@ wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; wire [3:0] \z80_|alu_|op2_low ; wire [3:0] \z80_|alu_|op1_low ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; -wire [15:0] \z80_|address_latch_|abusz ; -wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [15:0] \z80_|address_latch_|Q ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; +wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [7:0] \z80_|data_pins_|dout ; wire [7:0] \z80_|ir_|opcode ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; @@ -2790,11 +2815,13 @@ wire [7:0] \ula_|video_|bits ; wire [7:0] \ula_|video_|attr ; wire [8:0] \ula_|ps2_keyboard_|shiftreg ; wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; @@ -2806,10 +2833,9 @@ wire [3:0] \z80_|alu_|result_lo ; wire [3:0] \z80_|alu_|op2_high ; wire [3:0] \z80_|alu_|op1_high ; wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; -wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; -wire [7:0] \z80_|data_pins_|dout ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; +wire [15:0] \z80_|address_latch_|abusz ; +wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; @@ -2821,33 +2847,33 @@ wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_b wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; @@ -2866,15 +2892,15 @@ wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_b wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; @@ -2909,60 +2935,60 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; @@ -2999,24 +3025,24 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; @@ -3245,8 +3271,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~50_combout ), - .oe(\D[0]~30_combout ), + .i(\D[0]~60_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3258,8 +3284,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~51_combout ), - .oe(\D[0]~30_combout ), + .i(\D[1]~62_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3271,8 +3297,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~39_combout ), - .oe(\D[0]~30_combout ), + .i(\D[2]~64_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3284,8 +3310,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~59_combout ), - .oe(\D[0]~30_combout ), + .i(\D[3]~76_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3297,8 +3323,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~67_combout ), - .oe(\D[0]~30_combout ), + .i(\D[4]~83_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3310,8 +3336,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~69_combout ), - .oe(\D[0]~30_combout ), + .i(\D[5]~85_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3323,8 +3349,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~74_combout ), - .oe(\D[0]~30_combout ), + .i(\D[6]~93_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3336,8 +3362,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~75_combout ), - .oe(\D[0]~30_combout ), + .i(\D[7]~94_combout ), + .oe(\D[0]~107_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -3440,7 +3466,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(gnd), + .i(\raw_loader_in~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -4080,7 +4106,7 @@ defparam \ula_|clocks_|clk_cpu .is_wysiwyg = "true"; defparam \ula_|clocks_|clk_cpu .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G10 +// Location: CLKCTRL_G14 cycloneive_clkctrl \ula_|clocks_|clk_cpu~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\ula_|clocks_|clk_cpu~q }), @@ -4093,7 +4119,24 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N0 +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N12 cycloneive_lcell_comb \z80_|sequencer_|ena_M ( // Equation(s): // \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout ) @@ -4110,6 +4153,11802 @@ defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; // synopsys translate_on +// Location: IOIBUF_X0_Y16_N8 +cycloneive_io_ibuf \KEY[1]~input ( + .i(KEY[1]), + .ibar(gnd), + .o(\KEY[1]~input_o )); +// synopsys translate_off +defparam \KEY[1]~input .bus_hold = "false"; +defparam \KEY[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( +// Equation(s): +// \z80_|interrupts_|nmi_armed~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; +defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N2 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hAAFF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y15_N7 +dffeas \z80_|interrupts_|nmi_armed ( + .clk(!\KEY[1]~input_o ), + .d(\z80_|interrupts_|nmi_armed~feeder_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|nmi_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|nmi_armed .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N12 +cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( +// Equation(s): +// \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|interrupts_|nmi_armed~q ), + .cin(gnd), + .combout(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( +// Equation(s): +// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h1100; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N31 +dffeas \z80_|sequencer_|DFFE_M3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( +// Equation(s): +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hD0D0; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N2 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N3 +dffeas \z80_|sequencer_|DFFE_M4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h00CC; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( +// Equation(s): +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|decode_state_|table_xx~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal36~0_combout )))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|pla_decode_|Equal36~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal36~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hB3A0; +defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EA; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X41_Y17_N29 +dffeas \z80_|decode_state_|DFFE_instCB ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instCB~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X41_Y17_N17 +dffeas \z80_|decode_state_|DFFE_instED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) + + .dataa(\z80_|ir_|opcode [7]), + .datab(gnd), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout )) + + .dataa(gnd), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal49~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [3])) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~8_combout = (((!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h4FFF; +defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N12 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h0055; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hEF00; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( +// Equation(s): +// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal3~2_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( +// Equation(s): +// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( +// Equation(s): +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( +// Equation(s): +// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( +// Equation(s): +// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~8_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( +// Equation(s): +// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal44~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( +// Equation(s): +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( +// Equation(s): +// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|execute_|ixy_d~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(gnd), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal50~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( +// Equation(s): +// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|pla_decode_|Equal50~0_combout & ((!\z80_|pla_decode_|Equal33~2_combout )))) # (!\z80_|decode_state_|DFFE_inst4~q & (((!\z80_|pla_decode_|Equal50~0_combout & +// !\z80_|pla_decode_|Equal33~2_combout )) # (!\z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0537; +defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( +// Equation(s): +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & +// (!\z80_|execute_|ixy_d~13_combout & (\z80_|execute_|ixy_d~17_combout ))) + + .dataa(\z80_|execute_|ixy_d~12_combout ), + .datab(\z80_|execute_|ixy_d~13_combout ), + .datac(\z80_|execute_|ixy_d~17_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h30BA; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( +// Equation(s): +// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( +// Equation(s): +// \z80_|execute_|ixy_d~15_combout = ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|execute_|ixy_d~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & +// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N23 +dffeas \z80_|decode_state_|DFFE_instIY1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_iy_set~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instIY1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0500; +defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_mRead~26_combout & !\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ctl_mRead~27_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h5D00; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal12~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0500; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( +// Equation(s): +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|comb~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|comb~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~17_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~18_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal32~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|reg_control_|reg_sys_we_lo~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|pla_decode_|Equal24~1_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~3_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|reg_control_|reg_sys_we_lo~3_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h153F; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~20_combout ), + .datab(\z80_|execute_|ctl_mRead~21_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~18_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~18_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( +// Equation(s): +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|M5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N17 +dffeas \z80_|sequencer_|M5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|M5~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|M5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|M5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & +// (((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'h0777; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout +// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~29_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~7_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~14_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_state_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~14_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & +// (((!\z80_|execute_|ctl_state_alu~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'h115F; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F3F; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|pla_decode_|Equal29~0_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Equation(s): +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_state_alu~8_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~8_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'h7000; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & +// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mRead~18_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal41~0_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal46~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_flags_alu~17_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0505; +defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~6_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_alu~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~17_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_mWrite~8_combout ))) + + .dataa(\z80_|execute_|fMRead~17_combout ), + .datab(\z80_|execute_|ctl_sw_2d~4_combout ), + .datac(\z80_|execute_|fMRead~16_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_mRead~24_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~18_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~24_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|fMRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~36_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~9_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~3_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h007F; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ixy_d~6_combout & +// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~4_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal46~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & (((!\z80_|execute_|ctl_ir_we~12_combout ) # +// (!\z80_|execute_|ctl_mWrite~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0577; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datab(\z80_|execute_|ctl_sw_2d~7_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|fMRead~19_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|ctl_sw_2d~8_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), + .datab(\z80_|execute_|fMRead~19_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datad(\z80_|execute_|ctl_sw_2d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_sw_2d~9_combout ))) + + .dataa(\z80_|execute_|ctl_im_we~combout ), + .datab(\z80_|execute_|ctl_sw_1d~5_combout ), + .datac(\z80_|execute_|ctl_sw_1d~4_combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout ))) # (!\z80_|execute_|ctl_sw_1d~6_combout ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7333; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0111; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~4 ( +// Equation(s): +// \z80_|alu_|db_low[2]~4_combout = ((\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~4 .lut_mask = 16'h555D; +defparam \z80_|alu_|db_low[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_sw_4u~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # +// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~29_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) + + .dataa(\z80_|ir_|opcode [4]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00AA; +defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~2 ( +// Equation(s): +// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0011; +defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0103; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0D0; +defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~15_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0F3F; +defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_ir_we~7_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~15_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & !\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_mWrite~16_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~13 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_alu_bs_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_alu_bs_oe~13_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~13_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|pla_decode_|Equal68~2_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_flags_bus~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'hAFBF; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~10_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_flags_bus~8_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_flags_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~11_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~14_combout ), + .datab(\z80_|execute_|ctl_flags_bus~11_combout ), + .datac(\z80_|execute_|ctl_flags_bus~10_combout ), + .datad(\z80_|execute_|ctl_flags_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_state_alu~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) # +// (!\z80_|execute_|ctl_mWrite~3_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h3030; +defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|pla_decode_|Equal41~2_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1100; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[2]~14_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N17 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88C8; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~11 ( +// Equation(s): +// \z80_|execute_|fMWrite~11_combout = ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~11 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~21_combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_alu_op_low~9_combout ))) # (!\z80_|execute_|fMWrite~11_combout ) + + .dataa(\z80_|execute_|fMWrite~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~22_combout = ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h7737; +defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~16_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~36 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (\z80_|execute_|ctl_state_alu~8_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datab(\z80_|execute_|ctl_state_alu~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_mWrite~3_combout & +// (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~19_combout = ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'h77F7; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_mRead~36_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op_low~22_combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|execute_|ixy_d~5_combout & +// (\z80_|pla_decode_|Equal40~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hEAE0; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFF08; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = ((\z80_|execute_|ctl_alu_op_low~24_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~26_combout ) # (\z80_|execute_|ctl_mRead~27_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) + + .dataa(\z80_|execute_|ctl_mRead~26_combout ), + .datab(\z80_|execute_|ctl_mRead~27_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hEF0F; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = (\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (((\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = (\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hF200; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3F20; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~22_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0CEC; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h32F0; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h22EA; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~14_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~14 .lut_mask = 16'hC0C8; +defparam \z80_|execute_|ctl_alu_bs_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~14_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00EA; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & +// (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~4_combout +// & (\z80_|execute_|ctl_ir_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEAC8; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|execute_|ctl_alu_bs_oe~10_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (!\z80_|execute_|ctl_alu_bs_oe~11_combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h00CF; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~32_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_alu_shift_oe~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF51; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~7_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # +// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h3F20; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~12_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~26_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|pla_decode_|Equal48~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h1300; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0C00; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & +// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal11~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_alu~9_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~9_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~10_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_ir_we~14_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout ) # +// (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'h0377; +defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~25_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~13_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'h3331; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h5557; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h7000; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|ctl_state_alu~7_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~3_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & +// (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~3_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'h8C88; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~2_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(gnd), + .datac(\z80_|alu_|db_high[3]~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hFAFA; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~24 ( +// Equation(s): +// \z80_|alu_|db_low[2]~24_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~3_combout & (\z80_|alu_|db_low[2]~6_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~3_combout & +// \z80_|alu_|db_low[2]~6_combout )) # (!\z80_|alu_|db_high[3]~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[2]~3_combout ), + .datac(\z80_|alu_|db_low[2]~6_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~24 .lut_mask = 16'hC0D5; +defparam \z80_|alu_|db_low[2]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h0AAA; +defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|reg_control_|reg_sys_we_lo~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~43_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & \z80_|execute_|ctl_bus_inc_oe~25_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|execute_|ctl_alu_oe~8_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~8_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mWrite~16_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & +// (((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (((!\z80_|execute_|ctl_mRead~27_combout & !\z80_|execute_|ctl_mRead~26_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~27_combout ), + .datac(\z80_|execute_|ctl_mRead~26_combout ), + .datad(\z80_|execute_|ctl_alu_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|execute_|ctl_alu_oe~11_combout ) # (((!\z80_|execute_|ctl_alu_oe~7_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|execute_|ctl_alu_oe~5_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_alu_oe~12_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~12_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_oe~13_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hF5F5; +defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & +// (((!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mRead~26_combout ))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|nextM~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'h8C00; +defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( +// Equation(s): +// \z80_|execute_|setM1~54_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'hABFF; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~7_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_alu_oe~3_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout )) # +// (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_alu_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_sw_2u~4_combout )) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~1_combout ), + .datad(\z80_|execute_|ctl_sw_2u~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~36_combout & (\z80_|execute_|comb~0_combout $ ((!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_reg_gp_sel~36_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & +// (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~35_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_inc_cy~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(\z80_|execute_|ctl_sw_2u~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h7878; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & +// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (!\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h5AAA; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h0444; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~14_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~10_combout ), + .datab(\z80_|execute_|ctl_sw_2d~14_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEAA; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~11_combout ), + .datac(\z80_|execute_|ctl_sw_2d~12_combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_alu_oe~2_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|pla_decode_|Equal38~2_combout & ((!\z80_|pla_decode_|Equal37~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|pla_decode_|Equal38~2_combout +// & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~75_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal29~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~48_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|execute_|ctl_bus_inc_oe~48_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & +// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~92_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~38_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal3~1_combout )) # (!\z80_|pla_decode_|Equal19~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal19~1_combout ), + .datac(\z80_|execute_|ctl_sw_4u~0_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~93_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~93_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~93_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~24_combout = (\z80_|execute_|ctl_inc_cy~92_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~39_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~92_combout ), + .datac(\z80_|execute_|ctl_inc_cy~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~1_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (\z80_|execute_|ctl_bus_inc_oe~46_combout & (\z80_|execute_|ctl_inc_cy~53_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~53_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~44_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_sw_4u~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .datad(\z80_|execute_|ctl_sw_4u~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( +// Equation(s): +// \z80_|execute_|fMRead~3_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ctl_state_alu~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # +// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~15_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_state_alu~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_sw_4u~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~94_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~94_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~87_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~94_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ctl_inc_cy~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (\z80_|execute_|fMRead~3_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) + + .dataa(\z80_|execute_|fMRead~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout ))) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~5_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~6_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal1~5_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~6_combout & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal1~6_combout ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N23 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N27 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal2~1_combout ), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hC888; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~12_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal50~0_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( +// Equation(s): +// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFAF; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( +// Equation(s): +// \z80_|execute_|fMRead~2_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_flags_bus~5_combout )) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~14_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h1010; +defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|fMWrite~3_combout & (\z80_|execute_|fMRead~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|fMWrite~3_combout ), + .datac(\z80_|execute_|fMRead~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h00C0; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h50F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hC5CD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout & ((\z80_|execute_|ctl_ir_we~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hCAC0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [4]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~47_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~8_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~47_combout & \z80_|execute_|nextM~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~21_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~5_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_sw_1d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & +// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hAB00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~20_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|pla_decode_|Equal49~0_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .lut_mask = 16'h0101; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~22_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'h0032; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout & \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~36_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00CC; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h20AA; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0505; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|pla_decode_|Equal68~2_combout & (!\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_flags_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~48_combout )))) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|ctl_flags_oe~1_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0070; +defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~40_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (\z80_|execute_|ctl_inc_cy~43_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_inc_cy~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal29~0_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & +// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0357; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & +// !\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h111F; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|fMRead~7_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h10F0; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .datac(\z80_|execute_|fMRead~6_combout ), + .datad(\z80_|execute_|fMRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|execute_|ctl_state_alu~8_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~8_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'h3331; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) # +// (!\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|pla_decode_|Equal52~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (\z80_|execute_|ctl_state_alu~14_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|execute_|ctl_state_alu~14_combout & (\z80_|pla_decode_|Equal52~1_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'hF3A2; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~9_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hFD00; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~4_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h373F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~9_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00FD; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal64~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hEEFF; +defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .datac(\z80_|execute_|ctl_alu_oe~7_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_state_alu~14_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|pla_decode_|Equal52~1_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~15 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|ctl_state_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (\z80_|execute_|ctl_state_alu~15_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )) + + .dataa(\z80_|execute_|ctl_state_alu~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ) # (((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout & \z80_|ir_|opcode [5])) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & +// ((\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hFF70; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hF7F7; +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h22A2; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; +defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h0F0B; +defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N15 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) + + .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hAC00; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_state_alu~15_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_state_alu~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h1100; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout & ((!\z80_|execute_|ctl_iorw~10_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout +// )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|pla_decode_|Equal25~0_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout & !\z80_|execute_|ctl_sw_1d~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), + .datad(\z80_|execute_|ctl_sw_1d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_reg_gp_we~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~5_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .datab(\z80_|execute_|ctl_sw_4u~3_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~7_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; +defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_flags_oe~1_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h1033; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ctl_al_we~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFBF0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h40CC; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (((\z80_|execute_|ctl_ir_we~7_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_iorw~11_combout ) # ((\z80_|execute_|ctl_state_alu~14_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~14_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~25_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & +// (((\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )) # (!\z80_|execute_|setM1~48_combout ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hCD05; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~9_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout )) # +// (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h1357; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h1155; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~40_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h1101; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout +// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_gp_we~5_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_mRead~22_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00B0; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) + + .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N21 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (!\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_control_|bank_af~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h1000; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_control_|bank_af~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout ) # +// (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'h035F; +defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hF8F8; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_bus~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h0777; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~7_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~24_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), + .datab(\z80_|execute_|fMRead~24_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3777; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|fMRead~3_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7757; +defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ixy_d~16_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ixy_d~16_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h557F; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & +// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|execute_|ctl_mRead~17_combout )))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h0222; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sel_pc~10_combout & (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datab(\z80_|execute_|ctl_inc_cy~94_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ctl_inc_cy~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & +// !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|ir_|opcode [5]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h5455; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~49 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~49_combout = (!\z80_|pla_decode_|Equal35~0_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~49 .lut_mask = 16'h00FD; +defparam \z80_|execute_|pc_inc_hold~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) + + .dataa(\z80_|execute_|pc_inc_hold~49_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0A00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|pla_decode_|Equal33~2_combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0515; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'h0003; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( +// Equation(s): +// \z80_|execute_|setM1~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_mRead~9_combout & (\z80_|execute_|pc_inc_hold~28_combout & \z80_|execute_|setM1~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|setM1~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~36 .lut_mask = 16'h2000; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( +// Equation(s): +// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|setM1~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0100; +defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA222; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hC8C8; +defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(gnd), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEE00; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~49_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|pc_inc_hold~49_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hF0B0; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~3_combout = (((\z80_|execute_|ctl_reg_sys_we~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout )) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|execute_|ctl_reg_sys_we~3_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEFFF; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF5D; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~34_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~34_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'h8CCC; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal3~1_combout ) # (!\z80_|pla_decode_|Equal19~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal19~1_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h5777; +defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; +defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h80C0; +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|execute_|ctl_mRead~36_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_al_we~13_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (\z80_|execute_|setM1~52_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datac(\z80_|execute_|setM1~52_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ctl_mRead~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h2022; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~0 ( +// Equation(s): +// \z80_|execute_|fMRead~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~0 .lut_mask = 16'h5D5D; +defparam \z80_|execute_|fMRead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal52~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0030; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h050F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h0FAF; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_reg_sys_hilo~20_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # +// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datac(\z80_|execute_|ctl_inc_dec~4_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hD0DD; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_ir_we~14_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout +// )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00C4; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~49_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~49_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h08CC; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h4455; +defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~0_combout ) # ((!\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|pc_inc_hold~28_combout )))) + + .dataa(\z80_|execute_|fMRead~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00BA; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_al_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4404; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_state_alu~14_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~49_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h0222; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~45_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~1 ( +// Equation(s): +// \z80_|execute_|fMRead~1_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~1 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMRead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMRead~1_combout ))) + + .dataa(\z80_|execute_|fMRead~1_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~46_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~45_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~39_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout ) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_inc_cy~76_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # +// (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~2_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~53_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), + .datab(\z80_|execute_|ctl_inc_cy~77_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & +// (((!\z80_|execute_|ctl_alu_oe~2_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'hA0F3; +defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_sel_wz~10_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & +// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~6_combout ), + .datad(\z80_|execute_|fMRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_reg_sel_wz~11_combout & (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~4_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .datab(\z80_|execute_|ctl_sw_4d~3_combout ), + .datac(\z80_|execute_|ctl_sw_4d~4_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~19_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~19_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~45_combout & !\z80_|execute_|ctl_mWrite~6_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_al_we~13_combout ), + .datac(\z80_|execute_|setM1~45_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h00C0; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~1_combout = ((!\z80_|decode_state_|use_ixiy~combout & ((\z80_|pla_decode_|Equal50~0_combout ) # (\z80_|pla_decode_|Equal49~0_combout )))) # (!\z80_|execute_|setM1~46_combout ) + + .dataa(\z80_|pla_decode_|Equal50~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|setM1~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'h32FF; +defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_al_we~14_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = ((\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout & \z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~5_combout ), + .datab(\z80_|execute_|ctl_sw_4d~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_sw_4d~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( +// Equation(s): +// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; +defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|fMRead~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h5DFF; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & (((\z80_|decode_state_|table_xx~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h00DF; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5010; +defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|setM1~36_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .datad(\z80_|execute_|fMRead~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hF0F7; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((!\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h4FFF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (\z80_|execute_|ctl_reg_sel_pc~18_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0800; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|execute_|ctl_sw_4d~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hF030; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N26 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N27 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N9 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N29 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + // Location: IOIBUF_X53_Y14_N1 cycloneive_io_ibuf \KEY[0]~input ( .i(KEY[0]), @@ -4120,7 +15959,7 @@ defparam \KEY[0]~input .bus_hold = "false"; defparam \KEY[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N6 +// Location: LCCOMB_X52_Y14_N4 cycloneive_lcell_comb reset( // Equation(s): // \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) @@ -4137,7 +15976,7 @@ defparam reset.lut_mask = 16'h0FFF; defparam reset.sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N22 +// Location: LCCOMB_X35_Y13_N26 cycloneive_lcell_comb \z80_|resets_|x1~0 ( // Equation(s): // \z80_|resets_|x1~0_combout = !\reset~combout @@ -4203,7 +16042,7 @@ defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X52_Y17_N23 +// Location: FF_X35_Y13_N27 dffeas \z80_|resets_|x1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|x1~0_combout ), @@ -4222,4021 +16061,25 @@ defparam \z80_|resets_|x1 .is_wysiwyg = "true"; defparam \z80_|resets_|x1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N8 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|x3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hFF44; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y17_N9 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G7 -cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y16_N8 -cycloneive_io_ibuf \KEY[1]~input ( - .i(KEY[1]), - .ibar(gnd), - .o(\KEY[1]~input_o )); -// synopsys translate_off -defparam \KEY[1]~input .bus_hold = "false"; -defparam \KEY[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N12 -cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( -// Equation(s): -// \z80_|interrupts_|nmi_armed~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; -defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N14 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y15_N13 -dffeas \z80_|interrupts_|nmi_armed ( - .clk(!\KEY[1]~input_o ), - .d(\z80_|interrupts_|nmi_armed~feeder_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|nmi_armed~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|nmi_armed .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N26 -cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( -// Equation(s): -// \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|interrupts_|nmi_armed~q ), - .cin(gnd), - .combout(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N24 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h5500; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N20 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N21 -dffeas \z80_|sequencer_|DFFE_M3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N6 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N7 -dffeas \z80_|sequencer_|DFFE_M4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h0303; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0030; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N28 -cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( -// Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|M5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N29 -dffeas \z80_|sequencer_|M5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|M5~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|M5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|M5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~12_combout & -// ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|decode_state_|DFFE_instCB~q & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal46~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [6] & \z80_|ir_|opcode [7]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hC0C0; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0303; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (((!\z80_|execute_|ixy_d~7_combout )) # -// (!\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_alu_core_S~10_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~49_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout )) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|ir_|opcode [7] & (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [6] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ixy_d~4_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ctl_mWrite~16_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_bus_inc_oe~49_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N10 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N11 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|pla_decode_|Equal41~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal33~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC080; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~13_combout & (!\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ixy_d~12_combout ))) # (!\z80_|execute_|ixy_d~13_combout & ((\z80_|execute_|ixy_d~17_combout ) # ((!\z80_|execute_|ixy_d~4_combout -// & \z80_|execute_|ixy_d~12_combout )))) - - .dataa(\z80_|execute_|ixy_d~13_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ixy_d~12_combout ), - .datad(\z80_|execute_|ixy_d~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h7530; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (!\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'h0300; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hC8CC; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h0A00; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|execute_|ixy_d~11_combout & (\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|execute_|ixy_d~14_combout ), - .datab(\z80_|execute_|ixy_d~11_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'hD555; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N4 -cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|ir_|opcode [5] & -// \z80_|pla_decode_|Equal3~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h5530; -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N5 -dffeas \z80_|decode_state_|DFFE_inst4 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_inst4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N20 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( -// Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) - - .dataa(gnd), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFCC; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~9_combout & !\z80_|execute_|ctl_mWrite~4_combout )) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h0011; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hF000; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~36_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~0 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~0_combout = (\z80_|execute_|ctl_inc_cy~36_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_inc_cy~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~0 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_inc_dec~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ctl_inc_dec~0_combout & ((\z80_|execute_|fMWrite~5_combout ) # ((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|fMWrite~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~0_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hFE00; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~12_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout & -// (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~12_combout )) # (!\z80_|execute_|ctl_sw_4u~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|ctl_mRead~12_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hC000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'h007F; -defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( -// Equation(s): -// \z80_|execute_|fIOWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'h5755; -defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( -// Equation(s): -// \z80_|execute_|fMWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h1F1F; -defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal46~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hFF2F; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N8 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|fIOWrite~5_combout & (((\z80_|execute_|fMWrite~0_combout ) # (\z80_|execute_|fMWrite~6_combout )))) # (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|ctl_mWrite~6_combout & -// ((\z80_|execute_|fMWrite~0_combout ) # (\z80_|execute_|fMWrite~6_combout )))) - - .dataa(\z80_|execute_|fIOWrite~5_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|fMWrite~0_combout ), - .datad(\z80_|execute_|fMWrite~6_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'hBBB0; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = ((!\z80_|ir_|opcode [7]) # (!\z80_|execute_|ctl_ir_we~5_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|ir_|opcode [7]), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h3FFF; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal33~1_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N16 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|fMRead~3_combout & ((!\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~8_combout ) # -// (!\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h03AF; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~7_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~1_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal19~1_combout ) # (!\z80_|pla_decode_|Equal3~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h1F3F; -defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N18 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (!\z80_|execute_|fMWrite~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) - - .dataa(\z80_|execute_|fMWrite~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h4000; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (!\z80_|execute_|fMWrite~8_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & \z80_|pin_control_|bus_db_pin_oe~11_combout ))) - - .dataa(\z80_|execute_|fMWrite~8_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h4000; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N12 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h135F; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'hAA2A; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h2A00; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~3_combout = (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~31 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~31_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~31 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|execute_|ctl_inc_cy~31_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|execute_|ctl_inc_cy~31_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h8AAA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~30 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~30_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & -// (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_inc_cy~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_inc_cy~30_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( -// Equation(s): -// \z80_|execute_|fMWrite~1_combout = (!\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = (!\z80_|execute_|fMWrite~1_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|fMWrite~0_combout )))) - - .dataa(\z80_|execute_|fMWrite~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|fMWrite~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h5545; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h3F33; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h3332; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~34_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal19~1_combout )) # (!\z80_|pla_decode_|Equal3~1_combout ) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (((!\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_inc_cy~86_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_inc_cy~85_combout & (\z80_|execute_|ctl_inc_cy~34_combout & \z80_|execute_|ctl_inc_cy~35_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|execute_|ctl_inc_cy~34_combout ), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( -// Equation(s): -// \z80_|execute_|fIOWrite~3_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'hB0B0; -defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal21~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~38 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~38_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~38 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'h7575; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( -// Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|fIOWrite~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|execute_|fIOWrite~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h5F0F; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = (\z80_|execute_|ctl_iorw~10_combout & (((\z80_|execute_|ctl_mWrite~2_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|fMRead~2_combout ))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'hFD00; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( -// Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~0_combout ) # ((\z80_|execute_|fIOWrite~3_combout & \z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|fIOWrite~3_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|fIOWrite~2_combout ), - .datad(\z80_|execute_|fIOWrite~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (!\z80_|execute_|fMWrite~2_combout & (!\z80_|execute_|fMWrite~4_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & !\z80_|execute_|fIOWrite~4_combout ))) - - .dataa(\z80_|execute_|fMWrite~2_combout ), - .datab(\z80_|execute_|fMWrite~4_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h0010; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~32 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~32_combout = ((!\z80_|execute_|ixy_d~4_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~32 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_inc_cy~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~33 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~33_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~32_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_sw_2u~0_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~33 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_inc_cy~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~13_combout & (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~3_combout & \z80_|execute_|ctl_inc_cy~33_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datab(\z80_|execute_|ctl_apin_mux~0_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .datad(\z80_|execute_|ctl_inc_cy~33_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFFAA; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~15_combout = (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|execute_|fIOWrite~4_combout ) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout & \z80_|pin_control_|bus_db_pin_oe~2_combout )))) # (!\z80_|sequencer_|DFFE_T4_ff~q & -// (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|pin_control_|bus_db_pin_oe~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'hBA30; -defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G5 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [2] & !\ula_|ps2_keyboard_|bit_count [1])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0507; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: FF_X25_Y23_N21 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_CLK~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y23_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|clk_filter [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N25 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N7 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [5]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [6]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [4]), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [1] & (!\ula_|ps2_keyboard_|clk_filter [2] & (\ula_|ps2_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|clk_filter [3]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [1]), - .datab(\ula_|ps2_keyboard_|clk_filter [2]), - .datac(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0010; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h00FF; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFA50; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N27 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y23_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) - - .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0A00; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y23_N29 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y15_N3 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [0]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1450; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N5 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & -// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N7 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N13 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [2]) # (\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hAAA0; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|always1~0_combout ), - .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h3010; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N27 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N21 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N19 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N15 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N23 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N31 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y15_N3 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~0_combout $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hA55A; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & \ula_|ps2_keyboard_|WideXor0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|clk_edge~q ), - .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N9 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|Equal0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF500; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N15 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~45_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0010; -defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hF830; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [1]) # (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; -defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h1004; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & ((!\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hC0E2; -defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|WideOr16~5_combout & (\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~5_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|WideOr16~7_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF088; -defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N7 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h00C0; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hAA88; -defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|pc_inc_hold~19_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|pc_inc_hold~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hEA00; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~9_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~9_combout )) # -// (!\z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h131F; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & (!\z80_|execute_|ctl_reg_sys_we~0_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~34_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4040; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~13_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~1 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~1_combout = (\z80_|execute_|ctl_inc_cy~37_combout & (((!\z80_|pla_decode_|Equal19~1_combout ) # (!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_inc_cy~37_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~1 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_inc_dec~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_dec~1_combout & (\z80_|execute_|ctl_inc_dec~0_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3F0F; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|fIOWrite~5_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|fIOWrite~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~38_combout ))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|execute_|ctl_mWrite~3_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h1F5F; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_inc_dec~4_combout ) # (((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_inc_dec~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .datad(\z80_|execute_|ctl_inc_dec~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'hCEFF; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (((\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )) # (!\z80_|execute_|ctl_inc_dec~7_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|execute_|ctl_inc_dec~2_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N28 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h00FF; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N29 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N22 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N23 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X51_Y12_N27 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N0 +// Location: LCCOMB_X29_Y17_N18 cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( // Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|resets_|clrpc_int~q & ((!\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|resets_|clrpc_int~q & -// (!\z80_|resets_|x1~q & \z80_|sequencer_|DFFE_T2_ff~q )))) +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # +// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|resets_|x1~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), .datac(\z80_|resets_|clrpc_int~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|resets_|x1~q ), .cin(gnd), .combout(\z80_|resets_|clrpc_int~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hA1F0; +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X51_Y12_N1 +// Location: FF_X29_Y17_N19 dffeas \z80_|resets_|clrpc_int ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|clrpc_int~0_combout ), @@ -8255,13 +16098,13 @@ defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; defparam \z80_|resets_|clrpc_int .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y12_N26 +// Location: LCCOMB_X29_Y17_N28 cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( // Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), .datac(\z80_|resets_|DFFE_intr_ff3~q ), .datad(\z80_|resets_|clrpc_int~q ), .cin(gnd), @@ -8272,9478 +16115,181 @@ defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .lut_mask = 16'h1300; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|pla_decode_|Equal38~2_combout & (!\z80_|execute_|ixy_d~4_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~4_combout & -// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_inc_cy~76_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ixy_d~4_combout ))) # (!\z80_|execute_|ctl_mRead~18_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & -// !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0357; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~50_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hF000; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|ir_|opcode [3]))) - - .dataa(\z80_|execute_|comb~1_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .datab(\z80_|pla_decode_|Equal4~0_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (\z80_|execute_|ctl_inc_cy~47_combout & (\z80_|execute_|ctl_bus_inc_oe~48_combout & \z80_|execute_|ctl_bus_inc_oe~26_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~77_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3])) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|pla_decode_|Equal56~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0101; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~4_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_sw_4u~2_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_sw_4u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (((\z80_|ir_|opcode [5]) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0F07; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~38_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'hAFBF; -defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout = (\z80_|execute_|ctl_inc_cy~82_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~87_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~82_combout ), - .datab(\z80_|execute_|ctl_inc_cy~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~87_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout = (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout -// )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'h040C; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0003; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hC0C0; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~34_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~34 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout & \z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal1~5_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal1~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'hFDDD; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (((\z80_|execute_|ctl_sw_4u~4_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~16_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .datac(\z80_|execute_|ctl_sw_4u~4_combout ), - .datad(\z80_|execute_|ctl_apin_mux~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~19_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( -// Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal29~0_combout & (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|pla_decode_|Equal29~0_combout & -// !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~3_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~13_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~3 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( -// Equation(s): -// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|execute_|ctl_mRead~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( -// Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|fMRead~13_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'h3070; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~25_combout = (\z80_|execute_|fMRead~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~3_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|fMRead~14_combout ))) - - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datad(\z80_|execute_|fMRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_mRead~13_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( -// Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h01FF; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~25_combout )) - - .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hBBFF; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N22 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h0303; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5515; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal12~0_combout ) - - .dataa(\z80_|pla_decode_|Equal12~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h2020; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~16_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0011; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_sw_1d~8_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|decode_state_|DFFE_instCB~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~3_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFBB; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|ir_|opcode [1])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|execute_|ctl_flags_oe~0_combout & \z80_|execute_|ctl_al_we~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_flags_oe~0_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hAFAF; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & !\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~8_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & (!\z80_|pla_decode_|Equal68~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|pla_decode_|Equal68~2_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal46~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|pla_decode_|Equal20~0_combout & !\z80_|execute_|ctl_ir_we~8_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h000F; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_hf_cpl~8_combout & (\z80_|execute_|setM1~47_combout & (\z80_|execute_|nextM~2_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datab(\z80_|execute_|setM1~47_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|setM1~48_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~1_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h004C; -defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_in_hi~8_combout & (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_mRead~19_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout -// & (((!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_mRead~19_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~18_combout & -// (((!\z80_|execute_|ctl_mRead~19_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~2_combout = (\z80_|execute_|ctl_mRead~27_combout & (\z80_|execute_|setM1~30_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|setM1~30_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~2 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & ((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|pla_decode_|Equal21~1_combout -// )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0007; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h035F; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h3233; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & \z80_|execute_|ctl_state_alu~9_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout -// & (\z80_|execute_|ctl_state_alu~5_combout & (\z80_|execute_|ctl_state_alu~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|pla_decode_|Equal52~1_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hF5C4; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal3~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout = ((!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .lut_mask = 16'h337F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h5551; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal64~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hFAFF; -defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal3~1_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_alu_oe~9_combout & (((!\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_mRead~28_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mRead~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & \z80_|execute_|ctl_alu_oe~10_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|execute_|ctl_alu_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_mRead~20_combout ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout & \z80_|execute_|ctl_reg_gp_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_we~5_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~2_combout & \z80_|execute_|ctl_reg_gp_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~8_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~9_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|execute_|setM1~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .lut_mask = 16'h8AFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_alu_op_low~19_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'h3233; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hCC04; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~51_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~51 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ctl_mRead~7_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~4_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .lut_mask = 16'h4C44; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h6A6A; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .lut_mask = 16'hFAFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h3FC0; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~10_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_sw_2u~0_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~50_combout = (\z80_|execute_|ctl_sw_2u~3_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|sequencer_|M5~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_sw_2u~3_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~50 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~5_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_gp_sel~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_2u~5_combout ) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ) # (((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .lut_mask = 16'hBFAF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout ) # -// (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h0757; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|pla_decode_|Equal4~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h030F; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|pla_decode_|Equal2~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|setM1~41_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h0023; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~25_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_state_alu~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h000C; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (!\z80_|execute_|ctl_mRead~15_combout & (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_ir_we~12_combout & \z80_|execute_|fMRead~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|fMWrite~1_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (((\z80_|ir_|opcode [7]) # (!\z80_|decode_state_|DFFE_instED~q )) # (!\z80_|ir_|opcode [6])) # (!\z80_|pla_decode_|Equal1~4_combout ) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_mRead~21_combout & (\z80_|execute_|ctl_iorw~12_combout & (!\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ctl_al_we~13_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~21_combout ), - .datab(\z80_|execute_|ctl_iorw~12_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h0800; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h3BBB; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal44~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~38_combout & !\z80_|execute_|ctl_iorw~11_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (\z80_|execute_|ctl_alu_shift_oe~26_combout & ((!\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal32~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|execute_|ixy_d~10_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_flags_bus~6_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_flags_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal76~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal76~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4])) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal76~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = ((!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|pla_decode_|Equal76~0_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|pla_decode_|Equal76~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|execute_|ctl_alu_op_low~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_flags_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~7_combout & (\z80_|execute_|ctl_flags_bus~8_combout & (\z80_|execute_|ctl_flags_bus~14_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), - .datab(\z80_|execute_|ctl_flags_bus~8_combout ), - .datac(\z80_|execute_|ctl_flags_bus~14_combout ), - .datad(\z80_|execute_|ctl_flags_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout & \z80_|execute_|ctl_flags_bus~10_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_flags_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h1115; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h0111; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~7_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~22_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|execute_|ctl_mRead~22_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~7 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & \z80_|execute_|ctl_reg_gp_sel[0]~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datab(\z80_|execute_|nextM~11_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal21~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # (\z80_|sequencer_|M5~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h0302; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~34_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~34 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((!\z80_|pla_decode_|Equal12~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hB0F5; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & (\z80_|execute_|ctl_ir_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~6_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hF808; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~2_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~51_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~34_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h80F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # (\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ))) # -// (!\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal2~1_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal4~0_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'hA8A0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'h0F0E; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # ((\z80_|execute_|ctl_mRead~38_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~56 ( -// Equation(s): -// \z80_|execute_|setM1~56_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~56 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout = (\z80_|execute_|setM1~56_combout & (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|setM1~56_combout ), - .datab(\z80_|execute_|ctl_sw_2u~1_combout ), - .datac(\z80_|execute_|ctl_sw_2u~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|ir_|opcode [2] & !\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~26_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~5_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~26 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~7_combout & (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout & \z80_|execute_|ctl_reg_gp_sel[0]~26_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~25_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_mRead~38_combout ) # ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'h3377; -defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_ir_we~12_combout & \z80_|execute_|fMRead~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|fMWrite~1_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # (!\z80_|execute_|ctl_mRead~29_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_mRead~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hB3F3; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~29 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~24_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~24 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_reg_sys_hilo~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ctl_reg_sys_hilo~24_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h22A2; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~31_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & -// ((\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~31 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~31_combout ) # ((\z80_|ir_|opcode [1] & !\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~31_combout ), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'hAAEE; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~28_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal1~5_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N18 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|pla_decode_|Equal1~6_combout & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|pla_decode_|Equal1~6_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hF078; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N19 -dffeas \z80_|reg_control_|bank_exx ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0200; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0200; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFFEE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N0 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((\z80_|pla_decode_|Equal32~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal21~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N1 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|reg_control_|bank_af~q & (!\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0200; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_control_|bank_af~q & (!\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h0800; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h4400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|pla_decode_|Equal19~0_combout )) # -// (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h07FF; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal29~0_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal38~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~11_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_sel_wz~6_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & \z80_|execute_|ctl_reg_in_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|execute_|ctl_mRead~11_combout & -// ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h45CF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # ((\z80_|execute_|ctl_mRead~19_combout ) # (\z80_|pla_decode_|Equal34~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_mRead~19_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~4_combout ) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal25~0_combout ), - .datac(\z80_|pla_decode_|Equal12~1_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h55F7; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ixy_d~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ixy_d~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|execute_|ixy_d~4_combout & -// (((!\z80_|execute_|ixy_d~16_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (!\z80_|execute_|ctl_reg_sel_pc~9_combout & (\z80_|execute_|ctl_reg_sel_pc~7_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h1050; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout = (\z80_|execute_|ctl_inc_cy~82_combout & (\z80_|execute_|ctl_inc_cy~38_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~87_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~82_combout ), - .datab(\z80_|execute_|ctl_inc_cy~38_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datad(\z80_|execute_|ctl_inc_cy~87_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_mWrite~16_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_sel_pc~11_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ixy_d~16_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ixy_d~16_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~40_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~40 .lut_mask = 16'h4050; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y15_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_ir_we~6_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~18_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'h001F; -defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (!\z80_|execute_|ctl_mRead~19_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h00AF; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (!\z80_|execute_|ctl_reg_sel_wz~7_combout & ((\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00FE; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & ((\z80_|execute_|fMRead~2_combout ) # ((!\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|pc_inc_hold~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|fMRead~2_combout ), - .datac(\z80_|execute_|pc_inc_hold~18_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h00DC; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal40~0_combout ) - - .dataa(\z80_|pla_decode_|Equal40~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h57FF; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout = (!\z80_|pla_decode_|Equal24~1_combout & (!\z80_|pla_decode_|Equal19~0_combout & (!\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~1_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .lut_mask = 16'h050F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~40_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h3323; -defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0101; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (\z80_|pla_decode_|Equal33~3_combout & (\z80_|execute_|ctl_inc_dec~3_combout & ((\z80_|execute_|ctl_reg_sys_hilo~24_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )))) # -// (!\z80_|pla_decode_|Equal33~3_combout & (((\z80_|execute_|ctl_reg_sys_hilo~24_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_inc_dec~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'hF531; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4500; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & (((\z80_|execute_|pc_inc_hold~40_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~40_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h3B00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h4500; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~16_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (!\z80_|execute_|ctl_reg_sys_hilo~20_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hA8AA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h8C0C; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (\z80_|execute_|setM1~52_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout & \z80_|execute_|ctl_reg_sel_pc~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~20_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~19_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h5444; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # (((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~10_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_ir_we~4_combout & (((\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~7_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((\z80_|execute_|ctl_reg_sel_wz~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hCF05; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & \z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~19_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'hFFDC; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal38~2_combout ) # (\z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N4 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .datac(\z80_|pla_decode_|Equal24~1_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N4 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|reg_control_|reg_sys_we_lo~1_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h0777; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # (\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~24_combout & !\z80_|execute_|ctl_mRead~23_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~24_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datad(\z80_|execute_|ctl_mRead~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h01FF; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~3_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h2A00; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~25_combout & (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal13~1_combout )) # (!\z80_|pla_decode_|Equal13~0_combout ) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'hEAEA; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~11_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_bus~4_combout ), - .datad(\z80_|execute_|ctl_flags_bus~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'hCC4C; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( -// Equation(s): -// \z80_|execute_|fMRead~27_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_alu_shift_oe~28_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_flags_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~12_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~27_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~12_combout ), - .datab(\z80_|execute_|fMRead~27_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~7_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .lut_mask = 16'hBABB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~36_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & \z80_|execute_|ctl_alu_op_low~36_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_state_alu~7_combout & !\z80_|execute_|ctl_alu_shift_oe~15_combout )) - - .dataa(\z80_|execute_|ctl_sw_2u~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'h0088; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (\z80_|execute_|ctl_alu_op_low~21_combout & (!\z80_|execute_|ctl_reg_gp_sel~5_combout & (\z80_|execute_|setM1~17_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datac(\z80_|execute_|setM1~17_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_mRead~38_combout & (!\z80_|execute_|ctl_mRead~13_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_mRead~38_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~27_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hC8CC; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~2_combout = (\z80_|execute_|ctl_flags_cf_we~7_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_flags_use_cf2~13_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_pf_sel[0]~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & (\z80_|execute_|ctl_alu_oe~6_combout & \z80_|execute_|ctl_flags_pf_we~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~6_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~11_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|ir_|opcode [5] & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mRead~38_combout )))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mWrite~7_combout & ((!\z80_|execute_|ctl_mWrite~2_combout )))) # (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_ir_we~11_combout )) -// # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datad(\z80_|pla_decode_|Equal20~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_xy_we~16_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~13_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ctl_reg_use_sp~1_combout & \z80_|execute_|ctl_flags_alu~14_combout ))) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1010; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T5_ff~q )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal10~0_combout & ((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (((!\z80_|execute_|ixy_d~5_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & \z80_|execute_|ctl_flags_alu~10_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~11_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datab(\z80_|execute_|ctl_flags_alu~11_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~6_combout = (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~8_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|execute_|ctl_flags_alu~6_combout & \z80_|execute_|ctl_flags_alu~17_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_alu~6_combout ), - .datad(\z80_|execute_|ctl_flags_alu~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal56~0_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal1~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal1~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hEFCC; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~19_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~19_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~9_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_flags_alu~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout ))) # (!\z80_|execute_|ctl_flags_alu~8_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .datac(\z80_|execute_|ctl_flags_alu~7_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (((\z80_|execute_|ctl_flags_alu~9_combout ) # (!\z80_|execute_|ctl_flags_alu~12_combout )) # (!\z80_|execute_|ctl_flags_alu~15_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_alu~15_combout ), - .datac(\z80_|execute_|ctl_flags_alu~12_combout ), - .datad(\z80_|execute_|ctl_flags_alu~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFFE0; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~6_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|execute_|ctl_reg_gp_sel~5_combout & (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|execute_|comb~0_combout -// $ (!\z80_|ir_|opcode [0])))) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'hD00D; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout & !\z80_|execute_|ctl_sw_2u~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~50_combout ), - .datad(\z80_|execute_|ctl_sw_2u~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|execute_|nextM~2_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hC040; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = (((\z80_|execute_|ctl_reg_out_hi~8_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N20 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N21 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y16_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~28_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h3323; -defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & !\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; -defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h3120; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h3210; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N12 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y12_N13 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de2~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hC840; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~22_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~22 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de2~q ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hC480; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_hl2~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~23_combout = (\z80_|reg_file_|gdfx_temp1[7]~22_combout & (\z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~23 .lut_mask = 16'hC400; -defparam \z80_|reg_file_|gdfx_temp1[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_af~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_control_|bank_exx~q & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|reg_control_|bank_exx~q & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~24 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h1115; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_mRead~7_combout -// & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h2020; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (\z80_|execute_|ctl_reg_in_hi~10_combout & (\z80_|execute_|ctl_reg_in_hi~7_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = ((\z80_|execute_|ctl_reg_in_hi~9_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~11_combout ) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~26_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[7]~20_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~26 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|decode_state_|DFFE_inst4~q & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~25_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~25 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (!\z80_|pla_decode_|Equal33~3_combout & (!\z80_|pla_decode_|Equal24~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal6~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|pla_decode_|Equal24~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|execute_|ctl_mWrite~16_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~32_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hBFAF; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~1_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hDDD5; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (!\z80_|execute_|ctl_mRead~16_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~0_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~39_combout = (\z80_|execute_|pc_inc_hold~18_combout & (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|pc_inc_hold~18_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~39 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_reg_sys_hilo~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (\z80_|execute_|setM1~36_combout & (\z80_|execute_|ctl_reg_sys_hilo~39_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ))) - - .dataa(\z80_|execute_|setM1~36_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~39_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h0800; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( -// Equation(s): -// \z80_|execute_|fMRead~11_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~37_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'h0004; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (((\z80_|execute_|ctl_bus_inc_oe~31_combout & \z80_|execute_|fMRead~11_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datac(\z80_|execute_|fMRead~11_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h80AA; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFDFF; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~17_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~27 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[7]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~28_combout = (\z80_|reg_file_|gdfx_temp1[7]~24_combout & (\z80_|reg_file_|gdfx_temp1[7]~26_combout & (\z80_|reg_file_|gdfx_temp1[7]~25_combout & \z80_|reg_file_|gdfx_temp1[7]~27_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~27_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_32 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~29_combout = (\z80_|reg_file_|gdfx_temp1[7]~23_combout & (\z80_|reg_file_|gdfx_temp1[7]~28_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~23_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datac(\z80_|reg_file_|gdfx_temp1[7]~28_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~29 .lut_mask = 16'h80A0; -defparam \z80_|reg_file_|gdfx_temp1[7]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~30_combout = ((\z80_|reg_file_|gdfx_temp1[7]~29_combout & ((\z80_|reg_file_|db_hi_as[7]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~29_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~30 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp1[7]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_shift_oe~15_combout ) # (\z80_|execute_|ctl_alu_op_low~20_combout )))) - - .dataa(\z80_|execute_|rsel3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~16_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h3133; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_iorw~10_combout & \z80_|execute_|rsel3~combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hB030; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_sw_2d~14_combout ), - .datad(\z80_|execute_|ctl_sw_2d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hFF2A; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = (\z80_|execute_|ctl_flags_alu~19_combout & (((!\z80_|execute_|ctl_mRead~28_combout & !\z80_|execute_|ctl_mRead~22_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_mRead~28_combout ), - .datac(\z80_|execute_|ctl_flags_alu~19_combout ), - .datad(\z80_|execute_|ctl_mRead~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~6_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~7_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h7030; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (\z80_|execute_|ixy_d~15_combout & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h070F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~13_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~7_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~7_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_sw_2d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & \z80_|execute_|ctl_sw_2d~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|ctl_sw_2d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~25_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~20_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~25_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h40C0; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_flags_alu~6_combout & \z80_|execute_|ctl_flags_alu~17_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_flags_alu~6_combout ), - .datad(\z80_|execute_|ctl_flags_alu~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|execute_|ctl_mRead~20_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (((!\z80_|execute_|ctl_mRead~20_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|ctl_sw_2d~4_combout ))) - - .dataa(\z80_|execute_|fMRead~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~9_combout ), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|ctl_sw_2d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( -// Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_mRead~26_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~2_combout & \z80_|execute_|fMRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~2_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & (\z80_|execute_|ctl_sw_2d~8_combout & \z80_|execute_|fMRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datac(\z80_|execute_|ctl_sw_2d~8_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~12_combout ) # ((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~12_combout ), - .datac(\z80_|execute_|ctl_sw_2d~11_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N0 -cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( -// Equation(s): -// \z80_|alu_|db[7]~19_combout = (\z80_|alu_control_|db[7]~18_combout & (((\z80_|reg_file_|gdfx_temp1[7]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_control_|db[7]~18_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[7]~30_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[7]~18_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_alu_oe~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hCF8F; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_alu_oe~12_combout ) # ((\z80_|execute_|ctl_alu_oe~11_combout ) # (!\z80_|execute_|ctl_alu_oe~10_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_oe~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h3F00; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_reg_in_hi~7_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_mWrite~8_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mRead~22_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_alu_oe~7_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|ctl_bus_db_we~5_combout & \z80_|execute_|ctl_alu_oe~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_alu_oe~8_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~13_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_alu_oe~8_combout ), - .datad(\z80_|execute_|ctl_flags_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout -// & (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_ir_we~7_combout & (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & \z80_|execute_|ctl_flags_sz_we~0_combout -// ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~1_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal1~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal13~1_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal1~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op_low~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_mRead~38_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # -// (!\z80_|execute_|ctl_mRead~38_combout & (((!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~31_combout & (\z80_|execute_|ctl_alu_shift_oe~30_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h0507; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|execute_|ctl_mWrite~2_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout -// & (((!\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~5_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout & \z80_|execute_|ctl_alu_op1_sel_bus~6_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~12_combout & (\z80_|execute_|ctl_flags_xy_we~12_combout & ((!\z80_|pla_decode_|Equal48~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) # (((!\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~4_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_66_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[3]~19_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~19_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00A0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFAA; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N13 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_hl2~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~49_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~49 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~50_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout & (\z80_|reg_file_|gdfx_temp1[3]~49_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datad(\z80_|reg_file_|gdfx_temp1[3]~49_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~50 .lut_mask = 16'hC400; -defparam \z80_|reg_file_|gdfx_temp1[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~52 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~51 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~54 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[3]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~53_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[3]~14_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[3]~14_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~53 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~55_combout = (\z80_|reg_file_|gdfx_temp1[3]~52_combout & (\z80_|reg_file_|gdfx_temp1[3]~51_combout & (\z80_|reg_file_|gdfx_temp1[3]~54_combout & \z80_|reg_file_|gdfx_temp1[3]~53_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~52_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~54_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~56_combout = (\z80_|reg_file_|gdfx_temp1[3]~50_combout & (\z80_|reg_file_|gdfx_temp1[3]~55_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datab(\z80_|reg_file_|gdfx_temp1[3]~50_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~55_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~56 .lut_mask = 16'h80C0; -defparam \z80_|reg_file_|gdfx_temp1[3]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_bus_inc_oe~32_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~11_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal21~1_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'h000F; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|setM1~37_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~15_combout )))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datac(\z80_|execute_|setM1~37_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'hFF15; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_al_we~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sel_wz~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~4_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0C00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h2FFF; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~18_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # (\z80_|execute_|ctl_reg_sel_pc~17_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (\z80_|reg_control_|reg_sel_pc~2_combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h2000; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0200; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|reg_control_|reg_sel_pc~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h0F0A; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = (\z80_|execute_|ctl_reg_sel_ir~0_combout ) # (((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hCFEF; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hF777; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEEFF; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|setM1~46_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|setM1~46_combout ), - .datac(\z80_|execute_|ctl_alu_oe~5_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_flags_bus~5_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h0DDD; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~3_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|fMRead~14_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|fMRead~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|fMRead~14_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|fMRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~4_combout & (\z80_|execute_|ctl_reg_sel_wz~13_combout & (\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datac(\z80_|execute_|ctl_sw_4d~3_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_4d~0_combout ), - .datac(\z80_|execute_|ctl_sw_4d~1_combout ), - .datad(\z80_|execute_|ctl_sw_4d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hF700; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [3] & ((\z80_|reg_file_|gdfx_temp1[3]~57_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[3]~57_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|reg_control_|reg_sel_pc~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~14_combout = (\z80_|reg_file_|db_hi_as[3]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~13_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~14 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~15_combout ) +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) .dataa(gnd), .datab(gnd), .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~15_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), + .combout(\z80_|address_latch_|abusz [7]), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_ir_we~4_combout & (((!\z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_state_alu~4_combout & -// ((!\z80_|execute_|ctl_al_we~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_al_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h32FA; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~9_combout ) # (((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) - - .dataa(\z80_|execute_|ctl_al_we~9_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y17_N20 +// Location: LCCOMB_X37_Y17_N14 cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), .combout(\z80_|execute_|ctl_apin_mux~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h3322; +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N2 +// Location: LCCOMB_X37_Y17_N26 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( // Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((!\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )) # (!\z80_|execute_|ctl_al_we~5_combout ))) - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_al_we~5_combout ), - .datad(\z80_|execute_|ctl_apin_mux~1_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|execute_|ctl_al_we~14_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hAA2A; defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y18_N4 +// Location: LCCOMB_X40_Y17_N8 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( // Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = (((!\z80_|execute_|ctl_al_we~4_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) +// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & (\z80_|execute_|ctl_ir_we~4_combout & +// ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datab(\z80_|execute_|ctl_alu_oe~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_al_we~13_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h0EEE; defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y17_N18 +// Location: LCCOMB_X40_Y17_N30 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( // Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_al_we~7_combout ) # (!\z80_|execute_|ctl_iorw~12_combout )) # (!\z80_|execute_|ctl_mRead~21_combout ))) +// \z80_|execute_|ctl_al_we~8_combout = ((\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - .dataa(\z80_|execute_|ctl_mRead~21_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ctl_iorw~12_combout ), - .datad(\z80_|execute_|ctl_al_we~7_combout ), + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_al_we~7_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBF3; defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N16 +// Location: LCCOMB_X34_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = (((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout )) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), + .datab(\z80_|execute_|ctl_al_we~4_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_al_we~9_combout ) # (!\z80_|execute_|setM1~45_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|setM1~45_combout ), + .datad(\z80_|execute_|ctl_al_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEEAE; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N0 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( // Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~10_combout ) # ((\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) +// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - .dataa(\z80_|execute_|ctl_al_we~10_combout ), - .datab(\z80_|execute_|ctl_al_we~6_combout ), + .dataa(\z80_|execute_|ctl_al_we~6_combout ), + .datab(gnd), .datac(\z80_|execute_|ctl_sw_4d~5_combout ), - .datad(\z80_|execute_|ctl_al_we~8_combout ), + .datad(\z80_|execute_|ctl_al_we~10_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFAF; defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N18 +// Location: LCCOMB_X41_Y18_N4 cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( // Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = ((\z80_|execute_|ctl_al_we~11_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|setM1~52_combout ) +// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|setM1~52_combout )) - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_al_we~11_combout ), .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_al_we~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hEFCF; defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N5 -dffeas \z80_|address_latch_|Q[11] ( +// Location: FF_X30_Y16_N5 +dffeas \z80_|address_latch_|Q[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), + .d(\z80_|address_latch_|abusz [7]), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -17752,724 +16298,119 @@ dffeas \z80_|address_latch_|Q[11] ( .ena(\z80_|execute_|ctl_al_we~12_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), + .q(\z80_|address_latch_|Q [7]), .prn(vcc)); // synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Location: LCCOMB_X35_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) +// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - .dataa(gnd), - .datab(\z80_|address_latch_|Q [11]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h33CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Location: LCCOMB_X36_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) +// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|execute_|ctl_inc_cy~77_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_inc_cy~47_combout & \z80_|execute_|ctl_inc_cy~78_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_inc_cy~78_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|fMRead~3_combout ))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (\z80_|execute_|ctl_bus_inc_oe~39_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~48_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # (\z80_|execute_|ctl_bus_inc_oe~37_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~45_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFD55; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~46_combout ) # (\z80_|execute_|ctl_bus_inc_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = (((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~15_combout = ((\z80_|reg_file_|db_hi_as[3]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[3]~14_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~15 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_hi_as[3]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~57_combout = ((\z80_|reg_file_|gdfx_temp1[3]~56_combout & ((\z80_|reg_file_|db_hi_as[3]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~56_combout ), - .datab(\z80_|reg_file_|db_hi_as[3]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~57 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|gdfx_temp1[3]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N28 -cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( -// Equation(s): -// \z80_|alu_|db[3]~13_combout = (\z80_|alu_|db_low[3]~23_combout & (((\z80_|reg_file_|gdfx_temp1[3]~57_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_|db_low[3]~23_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & -// ((\z80_|reg_file_|gdfx_temp1[3]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_|db_low[3]~23_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~57_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|setM1~48_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h040C; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_flags_alu~16_combout & ((\z80_|alu_|db_low[3]~23_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[3]~35_combout )))) # -// (!\z80_|execute_|ctl_flags_alu~16_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[3]~35_combout )))) - - .dataa(\z80_|execute_|ctl_flags_alu~16_combout ), - .datab(\z80_|alu_|db_low[3]~23_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .combout(\z80_|execute_|fIOWrite~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFFCF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3373; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Location: LCCOMB_X36_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( // Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & \z80_|execute_|ctl_flags_sz_we~5_combout )))) # -// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_alu_core_R~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout ))) +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_inc_dec~4_combout ))) - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|execute_|ctl_inc_dec~4_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Location: LCCOMB_X36_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( // Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) +// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~0_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_inc_dec~3_combout ), + .datad(\z80_|execute_|ctl_inc_dec~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hFF4F; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF3F3; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( // Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) +// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # (((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout )) # -// (!\z80_|execute_|ctl_flags_xy_we~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_flags_xy_we~13_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~7_combout ) # (!\z80_|execute_|ctl_flags_xy_we~16_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = ((\z80_|execute_|ctl_flags_xy_we~14_combout ) # ((!\z80_|execute_|ctl_flags_pf_we~4_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y15_N19 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N28 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( -// Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( -// Equation(s): -// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_flags_|flags_xf~q ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF300; -defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~30_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|M5~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_inc_cy~30_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal48~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .lut_mask = 16'hBAAA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~35_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout & \z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~35 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~42_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~42 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~42_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h55FF; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( +// Location: FF_X31_Y17_N17 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|execute_|ctl_reg_sel_ir~1_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -18478,28 +16419,1319 @@ dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Location: LCCOMB_X26_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N1 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hCA00; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h1000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2A2; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[2]~29_combout & +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|alu_control_|db[2]~29_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datac(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8CAF; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0020; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[2]~42_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N31 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[0]~12_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .datad(\z80_|alu_control_|db[0]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~16_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & \z80_|reg_file_|gdfx_temp0[0]~13_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|reg_file_|gdfx_temp0[0]~22_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; // synopsys translate_on // Location: CLKCTRL_G18 @@ -18515,25 +17747,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N6 -cycloneive_lcell_comb \ula_|video_|Add0~0 ( -// Equation(s): -// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) -// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add0~0_combout ), - .cout(\ula_|video_|Add0~1 )); -// synopsys translate_off -defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; -defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N20 +// Location: LCCOMB_X39_Y33_N16 cycloneive_lcell_comb \ula_|video_|Add0~14 ( // Equation(s): // \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) @@ -18551,50 +17765,50 @@ defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N22 +// Location: LCCOMB_X39_Y33_N18 cycloneive_lcell_comb \ula_|video_|Add0~16 ( // Equation(s): // \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) // \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [8]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~15 ), .combout(\ula_|video_|Add0~16_combout ), .cout(\ula_|video_|Add0~17 )); // synopsys translate_off -defparam \ula_|video_|Add0~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N0 +// Location: LCCOMB_X39_Y33_N26 cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( // Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) - .dataa(\ula_|video_|Add0~16_combout ), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~16_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hAA00; +defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y31_N15 +// Location: FF_X39_Y33_N27 dffeas \ula_|video_|vga_hc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~2_combout ), + .d(\ula_|video_|vga_hc~2_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18605,32 +17819,32 @@ defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N24 +// Location: LCCOMB_X39_Y33_N20 cycloneive_lcell_comb \ula_|video_|Add0~18 ( // Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|vga_hc [9] $ (\ula_|video_|Add0~17 ) +// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) .dataa(gnd), - .datab(\ula_|video_|vga_hc [9]), + .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|vga_hc [9]), .cin(\ula_|video_|Add0~17 ), .combout(\ula_|video_|Add0~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h3C3C; +defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N4 +// Location: LCCOMB_X37_Y33_N20 cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( // Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) .dataa(gnd), - .datab(\ula_|video_|Add0~18_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~18_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~1_combout ), .cout()); @@ -18639,15 +17853,15 @@ defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y31_N29 +// Location: FF_X37_Y33_N21 dffeas \ula_|video_|vga_hc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~1_combout ), + .d(\ula_|video_|vga_hc~1_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18658,58 +17872,25 @@ defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N20 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Location: LCCOMB_X39_Y33_N2 +cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [0] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) +// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) +// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - .dataa(\ula_|video_|vga_hc [2]), + .dataa(gnd), .datab(\ula_|video_|vga_hc [0]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), + .datac(gnd), + .datad(vcc), .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); + .combout(\ula_|video_|Add0~0_combout ), + .cout(\ula_|video_|Add0~1 )); // synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N14 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & (\ula_|video_|vga_hc [5] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [4]), - .datac(\ula_|video_|vga_hc [5]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h1000; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N24 -cycloneive_lcell_comb \ula_|video_|Equal1~0 ( -// Equation(s): -// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|Equal0~1_combout ), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hFF7F; -defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N6 +// Location: LCCOMB_X34_Y31_N0 cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( // Equation(s): // \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) @@ -18726,15 +17907,15 @@ defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N11 +// Location: FF_X34_Y31_N1 dffeas \ula_|video_|vga_hc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~3_combout ), + .d(\ula_|video_|vga_hc~3_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18745,7 +17926,7 @@ defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N8 +// Location: LCCOMB_X39_Y33_N4 cycloneive_lcell_comb \ula_|video_|Add0~2 ( // Equation(s): // \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) @@ -18763,15 +17944,32 @@ defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y31_N17 +// Location: LCCOMB_X36_Y33_N16 +cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( +// Equation(s): +// \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Add0~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N17 dffeas \ula_|video_|vga_hc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~2_combout ), + .d(\ula_|video_|vga_hc[1]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18782,50 +17980,33 @@ defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N10 +// Location: LCCOMB_X39_Y33_N6 cycloneive_lcell_comb \ula_|video_|Add0~4 ( // Equation(s): // \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) // \ula_|video_|Add0~5 = CARRY((\ula_|video_|vga_hc [2] & !\ula_|video_|Add0~3 )) - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~3 ), .combout(\ula_|video_|Add0~4_combout ), .cout(\ula_|video_|Add0~5 )); // synopsys translate_off -defparam \ula_|video_|Add0~4 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N22 -cycloneive_lcell_comb \ula_|video_|vga_hc[2]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[2]~feeder_combout = \ula_|video_|Add0~4_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~4_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y31_N23 +// Location: FF_X39_Y33_N23 dffeas \ula_|video_|vga_hc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[2]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|Add0~4_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18836,7 +18017,7 @@ defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N12 +// Location: LCCOMB_X39_Y33_N8 cycloneive_lcell_comb \ula_|video_|Add0~6 ( // Equation(s): // \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) @@ -18854,10 +18035,27 @@ defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N13 +// Location: LCCOMB_X36_Y33_N8 +cycloneive_lcell_comb \ula_|video_|vga_hc[3]~feeder ( +// Equation(s): +// \ula_|video_|vga_hc[3]~feeder_combout = \ula_|video_|Add0~6_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Add0~6_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vga_hc[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N9 dffeas \ula_|video_|vga_hc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add0~6_combout ), + .d(\ula_|video_|vga_hc[3]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -18873,25 +18071,25 @@ defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N14 +// Location: LCCOMB_X39_Y33_N10 cycloneive_lcell_comb \ula_|video_|Add0~8 ( // Equation(s): // \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) // \ula_|video_|Add0~9 = CARRY((\ula_|video_|vga_hc [4] & !\ula_|video_|Add0~7 )) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [4]), + .dataa(\ula_|video_|vga_hc [4]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~7 ), .combout(\ula_|video_|Add0~8_combout ), .cout(\ula_|video_|Add0~9 )); // synopsys translate_off -defparam \ula_|video_|Add0~8 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N3 +// Location: FF_X39_Y33_N31 dffeas \ula_|video_|vga_hc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18910,7 +18108,58 @@ defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N16 +// Location: LCCOMB_X34_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N30 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( +// Equation(s): +// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) + + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|vga_hc [4]), + .datad(\ula_|video_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0200; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y33_N16 +cycloneive_lcell_comb \ula_|video_|Equal1~0 ( +// Equation(s): +// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; +defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N12 cycloneive_lcell_comb \ula_|video_|Add0~10 ( // Equation(s): // \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) @@ -18928,32 +18177,32 @@ defparam \ula_|video_|Add0~10 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N26 +// Location: LCCOMB_X39_Y33_N0 cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( // Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) - .dataa(\ula_|video_|Add0~10_combout ), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~10_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hAA00; +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y31_N1 +// Location: FF_X39_Y33_N1 dffeas \ula_|video_|vga_hc[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~0_combout ), + .d(\ula_|video_|vga_hc~0_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18964,7 +18213,7 @@ defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y31_N18 +// Location: LCCOMB_X39_Y33_N14 cycloneive_lcell_comb \ula_|video_|Add0~12 ( // Equation(s): // \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) @@ -18982,7 +18231,7 @@ defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N5 +// Location: FF_X39_Y33_N29 dffeas \ula_|video_|vga_hc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -19001,7 +18250,7 @@ defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X31_Y31_N27 +// Location: FF_X39_Y33_N25 dffeas \ula_|video_|vga_hc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -19020,61 +18269,25 @@ defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N2 +// Location: LCCOMB_X35_Y33_N0 cycloneive_lcell_comb \ula_|video_|Add1~0 ( // Equation(s): // \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) // \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) - .dataa(\ula_|video_|vga_vc [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [0]), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\ula_|video_|Add1~0_combout ), .cout(\ula_|video_|Add1~1 )); // synopsys translate_off -defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; +defparam \ula_|video_|Add1~0 .lut_mask = 16'h33CC; defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N8 -cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( -// Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [0])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~0_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Add1~0_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y31_N9 -dffeas \ula_|video_|vga_vc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[0]~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N4 +// Location: LCCOMB_X35_Y33_N2 cycloneive_lcell_comb \ula_|video_|Add1~2 ( // Equation(s): // \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) @@ -19092,42 +18305,42 @@ defparam \ula_|video_|Add1~2 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N6 +// Location: LCCOMB_X35_Y33_N4 cycloneive_lcell_comb \ula_|video_|Add1~4 ( // Equation(s): // \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) // \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), + .dataa(\ula_|video_|vga_vc [2]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~3 ), .combout(\ula_|video_|Add1~4_combout ), .cout(\ula_|video_|Add1~5 )); // synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N24 +// Location: LCCOMB_X38_Y33_N12 cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( // Equation(s): // \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), .datab(\ula_|video_|Add1~4_combout ), .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N25 +// Location: FF_X38_Y33_N13 dffeas \ula_|video_|vga_vc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[2]~2_combout ), @@ -19146,7 +18359,7 @@ defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N8 +// Location: LCCOMB_X35_Y33_N6 cycloneive_lcell_comb \ula_|video_|Add1~6 ( // Equation(s): // \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) @@ -19164,7 +18377,7 @@ defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N2 +// Location: LCCOMB_X35_Y33_N20 cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( // Equation(s): // \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) @@ -19181,15 +18394,15 @@ defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h5140; defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N3 +// Location: FF_X38_Y33_N3 dffeas \ula_|video_|vga_vc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[3]~3_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|vga_vc[3]~3_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -19200,42 +18413,42 @@ defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N10 +// Location: LCCOMB_X35_Y33_N8 cycloneive_lcell_comb \ula_|video_|Add1~8 ( // Equation(s): // \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) // \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - .dataa(\ula_|video_|vga_vc [4]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~7 ), .combout(\ula_|video_|Add1~8_combout ), .cout(\ula_|video_|Add1~9 )); // synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N20 +// Location: LCCOMB_X38_Y33_N20 cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( // Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [4])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~8_combout ))))) +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~8_combout ), .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Add1~8_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[4]~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N21 +// Location: FF_X38_Y33_N21 dffeas \ula_|video_|vga_vc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[4]~5_combout ), @@ -19254,50 +18467,50 @@ defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N12 +// Location: LCCOMB_X35_Y33_N10 cycloneive_lcell_comb \ula_|video_|Add1~10 ( // Equation(s): // \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) // \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~9 ), .combout(\ula_|video_|Add1~10_combout ), .cout(\ula_|video_|Add1~11 )); // synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N0 +// Location: LCCOMB_X35_Y33_N22 cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( // Equation(s): // \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|vga_vc [5]), .datad(\ula_|video_|Add1~10_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[5]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5140; defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N1 +// Location: FF_X38_Y33_N17 dffeas \ula_|video_|vga_vc[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[5]~8_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|vga_vc[5]~8_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -19308,42 +18521,42 @@ defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N14 +// Location: LCCOMB_X35_Y33_N12 cycloneive_lcell_comb \ula_|video_|Add1~12 ( // Equation(s): // \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) // \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~11 ), .combout(\ula_|video_|Add1~12_combout ), .cout(\ula_|video_|Add1~13 )); // synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N6 +// Location: LCCOMB_X38_Y33_N6 cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( // Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [6])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~12_combout ))))) +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~12_combout ), .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Add1~12_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[6]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N7 +// Location: FF_X38_Y33_N7 dffeas \ula_|video_|vga_vc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[6]~4_combout ), @@ -19362,42 +18575,42 @@ defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N16 +// Location: LCCOMB_X35_Y33_N14 cycloneive_lcell_comb \ula_|video_|Add1~14 ( // Equation(s): // \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) // \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) - .dataa(\ula_|video_|vga_vc [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~13 ), .combout(\ula_|video_|Add1~14_combout ), .cout(\ula_|video_|Add1~15 )); // synopsys translate_off -defparam \ula_|video_|Add1~14 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N22 +// Location: LCCOMB_X38_Y33_N14 cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( // Equation(s): // \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), .datab(\ula_|video_|Add1~14_combout ), .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[7]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N23 +// Location: FF_X38_Y33_N15 dffeas \ula_|video_|vga_vc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[7]~6_combout ), @@ -19416,7 +18629,7 @@ defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N18 +// Location: LCCOMB_X35_Y33_N16 cycloneive_lcell_comb \ula_|video_|Add1~16 ( // Equation(s): // \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) @@ -19434,24 +18647,24 @@ defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N0 +// Location: LCCOMB_X38_Y33_N24 cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( // Equation(s): -// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [8])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~16_combout ))))) +// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~16_combout ), .datac(\ula_|video_|vga_vc [8]), - .datad(\ula_|video_|Add1~16_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[8]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N1 +// Location: FF_X38_Y33_N25 dffeas \ula_|video_|vga_vc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[8]~7_combout ), @@ -19470,24 +18683,7 @@ defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N10 -cycloneive_lcell_comb \ula_|video_|Equal2~0 ( -// Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N20 +// Location: LCCOMB_X35_Y33_N18 cycloneive_lcell_comb \ula_|video_|Add1~18 ( // Equation(s): // \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) @@ -19504,24 +18700,24 @@ defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N28 +// Location: LCCOMB_X38_Y33_N10 cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( // Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [9])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~18_combout ))))) +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~18_combout ), .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Add1~18_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[9]~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h5140; +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N29 +// Location: FF_X38_Y33_N11 dffeas \ula_|video_|vga_vc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[9]~9_combout ), @@ -19540,58 +18736,111 @@ defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N26 +// Location: LCCOMB_X38_Y33_N18 +cycloneive_lcell_comb \ula_|video_|Equal2~0 ( +// Equation(s): +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(\ula_|video_|vga_vc [4]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [8]), + .cin(gnd), + .combout(\ula_|video_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N30 cycloneive_lcell_comb \ula_|video_|Equal3~0 ( // Equation(s): -// \ula_|video_|Equal3~0_combout = (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [2] & \ula_|video_|vga_vc [3]))) +// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0]))) - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [0]), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|vga_vc [3]), + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|vga_vc [0]), .cin(gnd), .combout(\ula_|video_|Equal3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h4000; +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0800; defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N16 +// Location: LCCOMB_X37_Y33_N18 cycloneive_lcell_comb \ula_|video_|Equal3~1 ( // Equation(s): -// \ula_|video_|Equal3~1_combout = (\ula_|video_|Equal2~0_combout & (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & \ula_|video_|Equal3~0_combout ))) +// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal2~0_combout & \ula_|video_|Equal3~0_combout ))) - .dataa(\ula_|video_|Equal2~0_combout ), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [9]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|Equal2~0_combout ), .datad(\ula_|video_|Equal3~0_combout ), .cin(gnd), .combout(\ula_|video_|Equal3~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal3~1 .lut_mask = 16'h2000; +defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N30 +// Location: LCCOMB_X38_Y33_N28 +cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( +// Equation(s): +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~0_combout ), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y33_N29 +dffeas \ula_|video_|vga_vc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N22 cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( // Equation(s): // \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|Equal1~0_combout ), .datab(\ula_|video_|Add1~2_combout ), .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N31 +// Location: FF_X38_Y33_N23 dffeas \ula_|video_|vga_vc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[1]~1_combout ), @@ -19620,14 +18869,14 @@ defparam \SW[1]~input .bus_hold = "false"; defparam \SW[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N16 +// Location: LCCOMB_X34_Y33_N30 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & (!\ula_|video_|vga_hc [8] & !\ula_|video_|vga_hc [9]))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & !\ula_|video_|vga_hc [9]))) - .dataa(\ula_|video_|vga_vc [1]), - .datab(\SW[1]~input_o ), - .datac(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [8]), + .datab(\ula_|video_|vga_vc [1]), + .datac(\SW[1]~input_o ), .datad(\ula_|video_|vga_hc [9]), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), @@ -19637,15 +18886,15 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N0 +// Location: LCCOMB_X35_Y17_N30 cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( // Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [5]), + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), .combout(\z80_|pla_decode_|Equal79~0_combout ), .cout()); @@ -19654,34 +18903,16 @@ defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N26 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( -// Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )) - - .dataa(\z80_|interrupts_|iff1~q ), - .datab(\z80_|pla_decode_|Equal79~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hE2AA; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N16 +// Location: LCCOMB_X35_Y17_N16 cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( // Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|DFFE_instIFF2~q +// ))))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal79~0_combout ), .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .cin(gnd), .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), .cout()); @@ -19690,24 +18921,24 @@ defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N24 +// Location: LCCOMB_X32_Y15_N28 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( // Equation(s): // \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h5F0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h7733; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: CLKCTRL_G8 +// Location: CLKCTRL_G16 cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), @@ -19720,7 +18951,7 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clo defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X46_Y10_N17 +// Location: FF_X35_Y17_N17 dffeas \z80_|interrupts_|DFFE_instIFF2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), @@ -19739,42 +18970,60 @@ defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N10 +// Location: LCCOMB_X35_Y17_N2 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|interrupts_|iff1~q ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hEC4C; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N18 cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( // Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )) +// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|iff1~0_combout ))))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|interrupts_|iff1~0_combout )))) - .dataa(\z80_|interrupts_|iff1~0_combout ), + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|interrupts_|iff1~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|iff1~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hCAAA; +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hDF80; defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N6 +// Location: LCCOMB_X38_Y18_N12 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFAF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X46_Y10_N11 +// Location: FF_X35_Y17_N19 dffeas \z80_|interrupts_|iff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|iff1~1_combout ), @@ -19793,15 +19042,15 @@ defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; defparam \z80_|interrupts_|iff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N22 +// Location: LCCOMB_X37_Y33_N4 cycloneive_lcell_comb \ula_|video_|Equal2~1 ( // Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [3]))) +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [0]))) - .dataa(\ula_|video_|vga_vc [2]), - .datab(\ula_|video_|vga_vc [0]), + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|vga_vc [2]), .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [0]), .cin(gnd), .combout(\ula_|video_|Equal2~1_combout ), .cout()); @@ -19810,24 +19059,24 @@ defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N12 +// Location: LCCOMB_X37_Y33_N14 cycloneive_lcell_comb \ula_|video_|Equal2~2 ( // Equation(s): -// \ula_|video_|Equal2~2_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~1_combout & \ula_|video_|Equal2~0_combout )) +// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (\ula_|video_|Equal2~0_combout & !\ula_|video_|vga_vc [5])) .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|Equal2~1_combout ), - .datad(\ula_|video_|Equal2~0_combout ), + .datab(\ula_|video_|Equal2~1_combout ), + .datac(\ula_|video_|Equal2~0_combout ), + .datad(\ula_|video_|vga_vc [5]), .cin(gnd), .combout(\ula_|video_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h3000; +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h00C0; defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y20_N20 +// Location: LCCOMB_X35_Y31_N28 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( // Equation(s): // \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (\z80_|interrupts_|iff1~q & \ula_|video_|Equal2~2_combout ))) @@ -19844,7 +19093,7 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y20_N21 +// Location: FF_X35_Y31_N29 dffeas \z80_|interrupts_|int_armed ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), @@ -19863,32 +19112,15 @@ defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; defparam \z80_|interrupts_|int_armed .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N28 -cycloneive_lcell_comb \z80_|interrupts_|DFFE_inst44~feeder ( -// Equation(s): -// \z80_|interrupts_|DFFE_inst44~feeder_combout = \z80_|interrupts_|int_armed~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|interrupts_|int_armed~q ), - .cin(gnd), - .combout(\z80_|interrupts_|DFFE_inst44~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_inst44~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|DFFE_inst44~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X50_Y12_N29 +// Location: FF_X32_Y15_N11 dffeas \z80_|interrupts_|DFFE_inst44 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|DFFE_inst44~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|interrupts_|int_armed~q ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|interrupts_|test1~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -19899,127 +19131,163 @@ defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Location: LCCOMB_X32_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) +// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datab(gnd), .datac(\z80_|decode_state_|in_halt~q ), - .datad(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .combout(\z80_|execute_|pc_inc_hold~38_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Location: LCCOMB_X35_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~6_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~7_combout ) +// \z80_|execute_|ctl_inc_cy~91_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .combout(\z80_|execute_|ctl_inc_cy~91_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Location: LCCOMB_X35_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~45 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|pc_inc_hold~40_combout ))) +// \z80_|execute_|pc_inc_hold~45_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & +// (((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|pc_inc_hold~40_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .combout(\z80_|execute_|pc_inc_hold~45_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~45 .lut_mask = 16'hF888; +defparam \z80_|execute_|pc_inc_hold~45 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Location: LCCOMB_X35_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~44 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (((\z80_|execute_|ctl_alu_op_low~14_combout & -// \z80_|execute_|ctl_mRead~38_combout )))) +// \z80_|execute_|pc_inc_hold~44_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~49_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~44 .lut_mask = 16'h8CCC; +defparam \z80_|execute_|pc_inc_hold~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~46 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~46_combout = (\z80_|execute_|pc_inc_hold~45_combout ) # ((\z80_|execute_|pc_inc_hold~44_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~49_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~45_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|pc_inc_hold~44_combout ), + .datad(\z80_|execute_|pc_inc_hold~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~46 .lut_mask = 16'hFAFE; +defparam \z80_|execute_|pc_inc_hold~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & +// (\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), + .datab(\z80_|pla_decode_|Equal52~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), + .combout(\z80_|execute_|pc_inc_hold~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hF8A8; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Location: LCCOMB_X35_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~50 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = (((\z80_|execute_|ctl_inc_cy~49_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~11_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ) +// \z80_|execute_|pc_inc_hold~50_combout = (\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datad(\z80_|execute_|ctl_inc_cy~49_combout ), + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|pc_inc_hold~37_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .combout(\z80_|execute_|pc_inc_hold~50_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~50 .lut_mask = 16'hECCC; +defparam \z80_|execute_|pc_inc_hold~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Location: LCCOMB_X36_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_inc_cy~51_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout )) +// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_mRead~10_combout & (((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal6~1_combout & +// ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) - .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), - .datab(\z80_|execute_|ctl_inc_cy~50_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .combout(\z80_|execute_|pc_inc_hold~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Location: LCCOMB_X36_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = (\z80_|execute_|ctl_inc_cy~52_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # (!\z80_|execute_|fMRead~11_combout )))) +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~52_combout ), - .datac(\z80_|execute_|fMRead~11_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hEFCC; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N8 +// Location: LCCOMB_X34_Y17_N26 cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( // Equation(s): // \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~2_combout ))) @@ -20036,4853 +19304,1086 @@ defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|pc_inc_hold~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datad(\z80_|execute_|pc_inc_hold~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hF8FC; -defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~24_combout = (\z80_|execute_|ixy_d~4_combout & (((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) # (!\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & -// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ixy_d~4_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (((\z80_|execute_|ctl_mRead~17_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ixy_d~4_combout & -// (\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hECE0; -defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~25_combout = (\z80_|execute_|pc_inc_hold~22_combout ) # ((\z80_|execute_|pc_inc_hold~24_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # (\z80_|execute_|pc_inc_hold~23_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~22_combout ), - .datab(\z80_|execute_|pc_inc_hold~24_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datad(\z80_|execute_|pc_inc_hold~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~20_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal25~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFF37; -defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~10_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hA080; -defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~21_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~19_combout ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'h37FF; -defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~26_combout = (!\z80_|execute_|pc_inc_hold~25_combout & (\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|pc_inc_hold~21_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(\z80_|execute_|pc_inc_hold~20_combout ), - .datac(\z80_|execute_|pc_inc_hold~41_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'h0400; -defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & -// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|execute_|ctl_inc_cy~44_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~13_combout )) # (!\z80_|execute_|ctl_inc_cy~87_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ctl_inc_cy~45_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~43_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~85_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'hBBB3; -defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~43_combout ) # (!\z80_|execute_|ctl_inc_cy~47_combout ))) # (!\z80_|execute_|ctl_inc_cy~33_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~33_combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~47_combout ), - .datad(\z80_|execute_|ctl_inc_cy~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|execute_|pc_inc_hold~30_combout & (((\z80_|execute_|pc_inc_hold~26_combout & \z80_|execute_|ctl_inc_cy~48_combout )))) # (!\z80_|execute_|pc_inc_hold~30_combout & ((\z80_|execute_|ctl_inc_cy~54_combout ) # -// ((\z80_|execute_|ctl_inc_cy~48_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~30_combout ), - .datab(\z80_|execute_|ctl_inc_cy~54_combout ), - .datac(\z80_|execute_|pc_inc_hold~26_combout ), - .datad(\z80_|execute_|ctl_inc_cy~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hF544; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ixy_d~10_combout & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~42_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hA800; -defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|pc_inc_hold~19_combout & \z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout & -// (\z80_|execute_|pc_inc_hold~19_combout & (\z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|pc_inc_hold~19_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|execute_|pc_inc_hold~27_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|pc_inc_hold~27_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|pc_inc_hold~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .datab(\z80_|execute_|pc_inc_hold~26_combout ), - .datac(\z80_|execute_|pc_inc_hold~42_combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'h0004; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout & (((\z80_|execute_|ctl_inc_cy~39_combout & \z80_|execute_|pc_inc_hold~29_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'hB030; -defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|pc_inc_hold~42_combout & (\z80_|execute_|pc_inc_hold~26_combout & (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout & !\z80_|execute_|pc_inc_hold~28_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~42_combout ), - .datab(\z80_|execute_|pc_inc_hold~26_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|execute_|ctl_inc_cy~41_combout ) # ((\z80_|execute_|ctl_inc_cy~83_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # (!\z80_|execute_|pc_inc_hold~30_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~41_combout ), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|ctl_inc_cy~83_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hFABA; -defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (!\z80_|decode_state_|in_halt~q & \z80_|execute_|ctl_mRead~16_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~62_combout ) # ((!\z80_|execute_|pc_inc_hold~22_combout & !\z80_|execute_|ctl_reg_sys_hilo~24_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~22_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~62_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'hC0C4; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N20 +// Location: LCCOMB_X36_Y19_N26 cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~23_combout ) # ((\z80_|execute_|pc_inc_hold~22_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ixy_d~4_combout ))) +// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout )))) - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|pc_inc_hold~23_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|pc_inc_hold~22_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|pc_inc_hold~28_combout ), .cin(gnd), .combout(\z80_|execute_|pc_inc_hold~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hECEE; defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|pc_inc_hold~31_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~63_combout ), - .datad(\z80_|execute_|pc_inc_hold~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'hF0F8; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal33~1_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = ((!\z80_|execute_|pc_inc_hold~22_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout & \z80_|execute_|ctl_inc_cy~58_combout ))) # (!\z80_|execute_|pc_inc_hold~30_combout ) - - .dataa(\z80_|execute_|pc_inc_hold~22_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_inc_cy~58_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'h1F0F; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~12_combout ) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|execute_|pc_inc_hold~25_combout & (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_inc_cy~59_combout ))) # (!\z80_|execute_|pc_inc_hold~25_combout & -// (((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & \z80_|execute_|ctl_inc_cy~59_combout )) # (!\z80_|execute_|ctl_inc_cy~60_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_inc_cy~59_combout ), - .datad(\z80_|execute_|ctl_inc_cy~60_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'hC0D5; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N8 +// Location: LCCOMB_X36_Y19_N12 cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|pc_inc_hold~25_combout ) # ((\z80_|execute_|pc_inc_hold~41_combout ) # (!\z80_|execute_|pc_inc_hold~20_combout )) +// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|execute_|ctl_mRead~15_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(gnd), - .datac(\z80_|execute_|pc_inc_hold~41_combout ), - .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), .cin(gnd), .combout(\z80_|execute_|pc_inc_hold~32_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hFAFF; +defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hEEA0; defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N2 +// Location: LCCOMB_X36_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~31_combout ) # (\z80_|execute_|pc_inc_hold~32_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~33_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~31_combout ), + .datad(\z80_|execute_|pc_inc_hold~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~51 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~51_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~51 .lut_mask = 16'h57FF; +defparam \z80_|execute_|pc_inc_hold~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~52 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~52_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~52 .lut_mask = 16'hA800; +defparam \z80_|execute_|pc_inc_hold~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~35_combout = (!\z80_|execute_|pc_inc_hold~34_combout & (\z80_|execute_|pc_inc_hold~51_combout & (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~52_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~34_combout ), + .datab(\z80_|execute_|pc_inc_hold~51_combout ), + .datac(\z80_|execute_|pc_inc_hold~30_combout ), + .datad(\z80_|execute_|pc_inc_hold~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'h0040; +defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|pc_inc_hold~35_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hCF8F; +defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~10_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_inc_cy~44_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~50_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|ctl_inc_cy~44_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~43 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~43_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~2_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~43 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~91_combout & (!\z80_|execute_|pc_inc_hold~46_combout & (\z80_|execute_|ctl_inc_cy~45_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), + .datab(\z80_|execute_|pc_inc_hold~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~45_combout ), + .datad(\z80_|execute_|pc_inc_hold~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~72_combout & \z80_|execute_|ctl_inc_cy~71_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_inc_cy~72_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~71_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_mWrite~16_combout & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h8C00; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~53 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~53_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~53 .lut_mask = 16'hE000; +defparam \z80_|execute_|pc_inc_hold~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~39_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~53_combout & (\z80_|execute_|pc_inc_hold~35_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~50_combout ), + .datab(\z80_|execute_|pc_inc_hold~53_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'h0010; +defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~47 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~47_combout = (\z80_|execute_|pc_inc_hold~46_combout ) # ((\z80_|execute_|pc_inc_hold~43_combout ) # ((!\z80_|execute_|ctl_inc_cy~44_combout ) # (!\z80_|execute_|pc_inc_hold~39_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~46_combout ), + .datab(\z80_|execute_|pc_inc_hold~43_combout ), + .datac(\z80_|execute_|pc_inc_hold~39_combout ), + .datad(\z80_|execute_|ctl_inc_cy~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~47 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|pc_inc_hold~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~34_combout )) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~43_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~43_combout ), + .datab(\z80_|execute_|ctl_inc_cy~35_combout ), + .datac(\z80_|execute_|ctl_inc_cy~34_combout ), + .datad(\z80_|execute_|ctl_inc_cy~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = ((\z80_|execute_|ctl_inc_cy~74_combout ) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~39_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~39_combout ), + .datac(\z80_|execute_|ctl_inc_cy~77_combout ), + .datad(\z80_|execute_|ctl_inc_cy~74_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|pc_inc_hold~47_combout & \z80_|execute_|ctl_inc_cy~91_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~47_combout ), + .datab(\z80_|execute_|ctl_inc_cy~78_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~91_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h4C0C; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|pc_inc_hold~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal19~1_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|pla_decode_|Equal19~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hA800; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|ctl_inc_cy~81_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|pc_inc_hold~47_combout & (!\z80_|execute_|pc_inc_hold~38_combout & ((\z80_|execute_|ctl_inc_cy~82_combout ) # (!\z80_|execute_|ctl_inc_cy~38_combout )))) # (!\z80_|execute_|pc_inc_hold~47_combout +// & ((\z80_|execute_|ctl_inc_cy~82_combout ) # ((!\z80_|execute_|ctl_inc_cy~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~47_combout ), + .datab(\z80_|execute_|ctl_inc_cy~82_combout ), + .datac(\z80_|execute_|pc_inc_hold~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h4C5F; +defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N26 cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout )) - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ctl_inc_cy~80_combout ), + .datad(\z80_|execute_|ctl_inc_cy~83_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_inc_cy~84_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hFFFC; defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Location: LCCOMB_X37_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~64_combout ) # ((\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|pc_inc_hold~32_combout & !\z80_|execute_|ctl_inc_cy~84_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), - .datab(\z80_|execute_|ctl_inc_cy~61_combout ), - .datac(\z80_|execute_|pc_inc_hold~32_combout ), - .datad(\z80_|execute_|ctl_inc_cy~84_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = ((!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h575F; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = (!\z80_|execute_|ctl_inc_cy~56_combout & (!\z80_|execute_|pc_inc_hold~42_combout & \z80_|execute_|pc_inc_hold~26_combout )) +// \z80_|execute_|pc_inc_hold~42_combout = ((\z80_|execute_|pc_inc_hold~34_combout ) # (\z80_|execute_|pc_inc_hold~52_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ) .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~56_combout ), - .datac(\z80_|execute_|pc_inc_hold~42_combout ), - .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .datab(\z80_|execute_|pc_inc_hold~30_combout ), + .datac(\z80_|execute_|pc_inc_hold~34_combout ), + .datad(\z80_|execute_|pc_inc_hold~52_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .combout(\z80_|execute_|pc_inc_hold~42_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'h0300; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( +// Location: LCCOMB_X37_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|pc_inc_hold~30_combout & ((\z80_|execute_|pc_inc_hold~25_combout ) # (!\z80_|execute_|pc_inc_hold~20_combout ))) +// \z80_|execute_|ctl_inc_cy~90_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(gnd), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), + .combout(\z80_|execute_|ctl_inc_cy~90_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hA0F0; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y13_N2 +// Location: LCCOMB_X36_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~31_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|pc_inc_hold~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N18 cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = (\z80_|execute_|ctl_inc_cy~65_combout ) # ((\z80_|execute_|ctl_inc_cy~57_combout ) # ((!\z80_|execute_|pc_inc_hold~33_combout & !\z80_|execute_|ctl_inc_cy~38_combout ))) +// \z80_|execute_|ctl_inc_cy~66_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q ))) - .dataa(\z80_|execute_|ctl_inc_cy~65_combout ), - .datab(\z80_|execute_|ctl_inc_cy~57_combout ), - .datac(\z80_|execute_|pc_inc_hold~33_combout ), - .datad(\z80_|execute_|ctl_inc_cy~38_combout ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), .combout(\z80_|execute_|ctl_inc_cy~66_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hEEEF; +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h0004; defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N20 +// Location: LCCOMB_X36_Y19_N4 cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~40_combout ) # ((\z80_|execute_|ctl_inc_cy~42_combout ) # (\z80_|execute_|ctl_inc_cy~66_combout ))) +// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & !\z80_|execute_|pc_inc_hold~31_combout )))) - .dataa(\z80_|execute_|ctl_inc_cy~55_combout ), - .datab(\z80_|execute_|ctl_inc_cy~40_combout ), - .datac(\z80_|execute_|ctl_inc_cy~42_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datac(\z80_|execute_|pc_inc_hold~31_combout ), .datad(\z80_|execute_|ctl_inc_cy~66_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_inc_cy~67_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hAA02; defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Location: LCCOMB_X36_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = (((!\z80_|execute_|ctl_inc_cy~37_combout ) # (!\z80_|execute_|ctl_inc_cy~31_combout )) # (!\z80_|execute_|ctl_inc_cy~36_combout )) # (!\z80_|execute_|ctl_inc_cy~30_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~30_combout ), - .datab(\z80_|execute_|ctl_inc_cy~36_combout ), - .datac(\z80_|execute_|ctl_inc_cy~31_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~75_combout ) # ((!\z80_|execute_|ctl_inc_cy~35_combout ) # (!\z80_|execute_|ctl_inc_cy~78_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_inc_cy~78_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'hBBFF; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = ((\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_inc_cy~72_combout & \z80_|pla_decode_|Equal19~1_combout ))) # (!\z80_|execute_|ctl_inc_cy~34_combout ) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_inc_cy~34_combout ), - .datac(\z80_|execute_|ctl_inc_cy~72_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'hB333; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|ctl_mRead~15_combout ))) .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|pc_inc_hold~41_combout ), + .datac(\z80_|execute_|ctl_inc_cy~67_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Location: LCCOMB_X36_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & (!\z80_|execute_|pc_inc_hold~34_combout & \z80_|execute_|pc_inc_hold~29_combout ))) +// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~31_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~73_combout & ((!\z80_|execute_|pc_inc_hold~30_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_inc_cy~73_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'hFF4C; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~74_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout & ((\z80_|execute_|ctl_inc_cy~68_combout ) # (!\z80_|execute_|pc_inc_hold~30_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~68_combout ), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_inc_cy~74_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hFF8C; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = (!\z80_|execute_|ctl_inc_dec~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'h5F5F; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .lut_mask = 16'h2F00; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~53_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_flags_oe~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~53 .lut_mask = 16'h050D; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~53_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .lut_mask = 16'hECFC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal25~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~54 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~54_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~54 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~27_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~54_combout ), - .datac(\z80_|execute_|ctl_mRead~27_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~20_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~20 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # (((\z80_|execute_|ctl_ir_we~15_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo~24_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo~24_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout = (\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & ((\z80_|execute_|rsel0~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// (((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|rsel0~combout )) # (!\z80_|execute_|setM1~48_combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|execute_|rsel0~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .lut_mask = 16'hCD05; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~47 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) # (!\z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_de~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de2_lo|db[0]~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .datac(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = (\z80_|pla_decode_|Equal40~1_combout & (((\z80_|execute_|ixy_d~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal40~1_combout & (\z80_|pla_decode_|Equal39~0_combout & -// ((\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFAC0; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0A00; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hA8A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout )) # (!\z80_|execute_|ctl_alu_op_low~21_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ixy_d~4_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|execute_|ctl_mRead~38_combout )))) # (!\z80_|execute_|ixy_d~4_combout & (((\z80_|execute_|ctl_eval_cond~0_combout & -// \z80_|execute_|ctl_mRead~38_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFC88; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h55F7; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~23_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal44~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_state_alu~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel~5_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hFF0F; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~17_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~17_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~39_combout = (((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~18_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'h7F77; -defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op_low~39_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout & ((\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'hF0E0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal56~0_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~38_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~38_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h0777; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y18_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~10_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h0155; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hEEEC; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_flags_cf_cpl~2_combout & ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hEF00; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mWrite~2_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout & -// (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (!\z80_|execute_|ctl_flags_cf_cpl~3_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h0200; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_alu_op_low~30_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC800; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = ((\z80_|execute_|ctl_reg_gp_sel~5_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal72~2_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~11_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal72~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|pla_decode_|Equal61~2_combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_mRead~38_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|pla_decode_|Equal61~2_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~11_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal21~0_combout ) # ((\z80_|pla_decode_|Equal3~0_combout )))) # (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_eval_cond~0_combout & -// ((\z80_|pla_decode_|Equal21~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .lut_mask = 16'hFAC8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout -// ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .lut_mask = 16'hFFF8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (\z80_|execute_|ctl_alu_op_low~36_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~36_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'h4000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (!\z80_|pla_decode_|Equal72~2_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal72~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & \z80_|execute_|ctl_flags_nf_we~1_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~38_combout = (\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'h8880; -defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|execute_|ctl_alu_op_low~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~38_combout ) # (\z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_alu_op_low~32_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|pla_decode_|Equal64~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h00C4; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|pla_decode_|Equal20~0_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (\z80_|execute_|ctl_flags_use_cf2~9_combout ))) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|execute_|ctl_flags_bus~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hBAFA; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_mRead~38_combout & \z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_mRead~38_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|pc_inc_hold~31_combout ), .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Location: LCCOMB_X37_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = (((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (\z80_|execute_|ctl_flags_cf_we~5_combout )) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_mWrite~3_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (((\z80_|ir_|opcode [3]) # (!\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'hF700; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|execute_|ctl_alu_core_R~2_combout ) # ((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|execute_|ctl_alu_op_low~25_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # (((\z80_|execute_|ctl_alu_op_low~33_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout )) # (!\z80_|execute_|ctl_alu_op_low~39_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~34_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hCC40; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hA0A8; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h54F0; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~18_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h5C4C; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~19_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h5F08; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_mWrite~2_combout ) # (\z80_|execute_|ctl_alu_shift_oe~20_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~20_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h5F40; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~21_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout -// & ((\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hEEC0; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_ir_we~7_combout )))) # (!\z80_|execute_|ctl_bus_db_oe~7_combout & ((\z80_|execute_|ixy_d~7_combout ) -// # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'hDC50; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_alu_shift_oe~24_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~44_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ) # (\z80_|execute_|ctl_alu_shift_oe~16_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0F0E; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~23_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF45; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hC4C0; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) +// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|pc_inc_hold~34_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_sw_4u~0_combout )))) .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|pc_inc_hold~34_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0C08; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Location: LCCOMB_X37_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( // Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~22_combout ) # (\z80_|execute_|ctl_mRead~28_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) +// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_inc_cy~64_combout ), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hFFC4; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_inc_cy~68_combout ) # ((\z80_|execute_|ctl_inc_cy~65_combout ) # ((!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|ctl_inc_cy~90_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~42_combout ), + .datab(\z80_|execute_|ctl_inc_cy~90_combout ), + .datac(\z80_|execute_|ctl_inc_cy~68_combout ), + .datad(\z80_|execute_|ctl_inc_cy~65_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~49_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_inc_cy~92_combout ) .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|execute_|ctl_mRead~28_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_inc_cy~92_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Location: LCCOMB_X35_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( // Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (!\z80_|execute_|ctl_alu_op_low~24_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) +// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ixy_d~9_combout & +// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h5F40; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_flags_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~22_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~42_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hB0A0; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( -// Equation(s): -// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .dataa(\z80_|execute_|ixy_d~9_combout ), .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Location: LCCOMB_X36_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~2_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~10_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_ir_we~10_combout ))) +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_inc_cy~94_combout )) - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|execute_|ctl_inc_cy~94_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Location: LCCOMB_X35_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) +// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|pla_decode_|Equal11~0_combout ))) - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~51_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Location: LCCOMB_X36_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( // Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_mWrite~3_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) +// \z80_|execute_|ctl_inc_cy~36_combout = ((!\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .combout(\z80_|execute_|ctl_inc_cy~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_alu_res_oe~1_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( -// Equation(s): -// \z80_|alu_|db_high[3]~1_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # ((\z80_|alu_|db_high[3]~0_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~0_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFEFF; -defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~2 ( -// Equation(s): -// \z80_|alu_|db_low[3]~2_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [3]), - .datac(\z80_|alu_|op2_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~2 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db_low[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hC0C0; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N26 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~3 ( -// Equation(s): -// \z80_|alu_|db_low[3]~3_combout = (\z80_|alu_|db_low[3]~2_combout & (((!\z80_|bus_control_|db[5]~17_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|alu_|db_low[3]~2_combout ), - .datab(\z80_|bus_control_|db[5]~17_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~3 .lut_mask = 16'h2A0A; -defparam \z80_|alu_|db_low[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y16_N13 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( -// Equation(s): -// \z80_|alu_|db_low[3]~4_combout = (\z80_|alu_|db_low[3]~3_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|alu_|db_low[3]~3_combout ), - .datab(\z80_|alu_|result_lo [3]), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hAA88; -defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (((\z80_|alu_|db_low[3]~1_combout & \z80_|alu_|db_low[3]~4_combout )) # (!\z80_|alu_|db_high[3]~1_combout ))) - - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .lut_mask = 16'hB030; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|alu_|db_high[3]~19_combout ), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .lut_mask = 16'h00F8; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_low~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N29 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[3]~3_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|alu_|alu_op2[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFCD; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = ((!\z80_|execute_|ctl_alu_core_S~11_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h3FFF; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|pla_decode_|Equal62~2_combout & \z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFBBB; -defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ) # (\z80_|execute_|ctl_alu_core_S~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~25 ( -// Equation(s): -// \z80_|alu_|db_high[2]~25_combout = (\z80_|alu_|db_high[2]~24_combout ) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_high[3]~1_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|alu_|db_high[2]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~25 .lut_mask = 16'hFF55; -defparam \z80_|alu_|db_high[2]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [6] & ((\z80_|reg_file_|gdfx_temp1[6]~21_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[6]~21_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~0 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|db_hi_as[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~1_combout = (\z80_|reg_file_|db_hi_as[6]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[6]~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~1 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|db_hi_as[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N29 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [14]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [13]))))) - - .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~3_combout = ((\z80_|reg_file_|db_hi_as[6]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[6]~1_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~3 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_hi_as[6]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X36_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 ( +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( // Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) +// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~36_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_sw_2u~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~36_combout ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), + .combout(\z80_|execute_|ctl_inc_cy~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Location: LCCOMB_X35_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout )) +// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout ))) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_inc_cy~52_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~9 ( +// Location: LCCOMB_X39_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) +// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|ctl_mRead~17_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~9_combout ), + .combout(\z80_|execute_|ctl_inc_cy~41_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~9 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~9 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0045; +defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~10 ( +// Location: LCCOMB_X39_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) +// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout )) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~10 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~11_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~11 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~12_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[6]~22_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~12 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~14_combout = (\z80_|reg_file_|gdfx_temp1[6]~10_combout & (\z80_|reg_file_|gdfx_temp1[6]~11_combout & (\z80_|reg_file_|gdfx_temp1[6]~13_combout & \z80_|reg_file_|gdfx_temp1[6]~12_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~10_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~11_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~13_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~21_combout - - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), + .datad(\z80_|execute_|ctl_inc_cy~41_combout ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hEEFF; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~8 ( +// Location: LCCOMB_X35_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~8_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) +// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & +// ((\z80_|execute_|ctl_mRead~36_combout )))) - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~8_combout ), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~8 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[6]~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~15 ( +// Location: LCCOMB_X38_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~15_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout & (\z80_|reg_file_|gdfx_temp1[6]~9_combout & (\z80_|reg_file_|gdfx_temp1[6]~14_combout & \z80_|reg_file_|gdfx_temp1[6]~8_combout ))) +// \z80_|execute_|ctl_inc_cy~56_combout = (((!\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|fMRead~3_combout ) - .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~8_combout ), + .dataa(\z80_|execute_|fMRead~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~15_combout ), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~21 ( +// Location: LCCOMB_X39_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~21_combout = ((\z80_|reg_file_|gdfx_temp1[6]~15_combout & ((\z80_|reg_file_|db_hi_as[6]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) +// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - .dataa(\z80_|reg_file_|db_hi_as[6]~3_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), + .combout(\z80_|execute_|ctl_inc_cy~89_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~21 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp1[6]~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hA020; +defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N24 -cycloneive_lcell_comb \z80_|interrupts_|im2~feeder ( +// Location: LCCOMB_X39_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( // Equation(s): -// \z80_|interrupts_|im2~feeder_combout = \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout +// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~56_combout ) # (\z80_|execute_|ctl_inc_cy~89_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ctl_inc_cy~55_combout ), + .datac(\z80_|execute_|ctl_inc_cy~56_combout ), + .datad(\z80_|execute_|ctl_inc_cy~89_combout ), .cin(gnd), - .combout(\z80_|interrupts_|im2~feeder_combout ), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|im2~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|im2~feeder .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y12_N25 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|im2~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Location: LCCOMB_X39_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( // Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) +// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~57_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~58_combout ) # (!\z80_|execute_|fMRead~5_combout )))) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_inc_cy~58_combout ), + .datac(\z80_|execute_|fMRead~5_combout ), + .datad(\z80_|execute_|ctl_inc_cy~57_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hFF8A; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Location: LCCOMB_X37_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( // Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|execute_|ctl_mRead~14_combout & (\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|pc_inc_hold~38_combout & (\z80_|execute_|pc_inc_hold~35_combout & (\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|pc_inc_hold~38_combout & (((\z80_|execute_|ctl_inc_cy~54_combout ) # +// (\z80_|execute_|ctl_inc_cy~59_combout )))) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|pc_inc_hold~35_combout ), + .datac(\z80_|execute_|ctl_inc_cy~54_combout ), + .datad(\z80_|execute_|ctl_inc_cy~59_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hD5D0; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N0 -cycloneive_lcell_comb \z80_|sw1_|db_down[6]~0 ( +// Location: LCCOMB_X35_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( // Equation(s): -// \z80_|sw1_|db_down[6]~0_combout = ((\z80_|bus_control_|db[6]~7_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) +// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|pc_inc_hold~50_combout ))) - .dataa(gnd), - .datab(\z80_|bus_control_|db[6]~7_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~50_combout ), .cin(gnd), - .combout(\z80_|sw1_|db_down[6]~0_combout ), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), .cout()); // synopsys translate_off -defparam \z80_|sw1_|db_down[6]~0 .lut_mask = 16'h0CFF; -defparam \z80_|sw1_|db_down[6]~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~10 ( +// Location: LCCOMB_X37_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( // Equation(s): -// \z80_|alu_|db_low[1]~10_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & !\z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~10 .lut_mask = 16'h3373; -defparam \z80_|alu_|db_low[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) +// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .combout(\z80_|execute_|ctl_inc_cy~88_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hAA08; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y17_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 ( +// Location: LCCOMB_X37_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( // Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout = (\z80_|alu_|db_low[1]~15_combout & \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) +// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_inc_cy~88_combout & ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~39_combout ), + .datab(\z80_|execute_|ctl_inc_cy~47_combout ), + .datac(\z80_|execute_|ctl_inc_cy~88_combout ), + .datad(\z80_|execute_|pc_inc_hold~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hECFC; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~40_combout = (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~34_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|pc_inc_hold~30_combout ), + .datac(\z80_|execute_|pc_inc_hold~34_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h3200; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|ctl_inc_cy~42_combout & ((\z80_|execute_|pc_inc_hold~40_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|pc_inc_hold~40_combout ), + .datac(\z80_|execute_|ctl_inc_cy~61_combout ), + .datad(\z80_|execute_|ctl_inc_cy~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hF0FD; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~48_combout ) # (\z80_|execute_|ctl_inc_cy~62_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), + .datab(\z80_|execute_|ctl_inc_cy~60_combout ), + .datac(\z80_|execute_|ctl_inc_cy~48_combout ), + .datad(\z80_|execute_|ctl_inc_cy~62_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~85_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~70_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), + .datab(\z80_|execute_|ctl_inc_cy~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~84_combout ), + .datad(\z80_|execute_|ctl_inc_cy~70_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (\z80_|execute_|ctl_inc_cy~85_combout ) .dataa(gnd), .datab(gnd), - .datac(\z80_|alu_|db_low[1]~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_cy~85_combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .lut_mask = 16'hF000; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( // Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .dataa(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFCF8; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hAF2F; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~12 ( +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( // Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~12_combout = (((!\z80_|execute_|nextM~11_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout )) # (!\z80_|execute_|ctl_reg_use_sp~0_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|ctl_mRead~38_combout -// & (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~13_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[1]~15_combout ) # ((\z80_|alu_|db_high[1]~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_high[1]~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(\z80_|alu_|db_high[1]~7_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|db_low[1]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) +// \z80_|address_latch_|abusz [0] = (\z80_|reg_file_|db_lo_as[0]~3_combout & !\z80_|resets_|clrpc~0_combout ) .dataa(gnd), - .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] + + .dataa(gnd), + .datab(gnd), .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|address_latch_|abusz [0]), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout ), + .combout(\z80_|address_latch_|Q[0]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1 .lut_mask = 16'h00CC; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # (\z80_|execute_|ctl_alu_op2_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N13 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[1]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[1]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00A0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N1 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~3 ( -// Equation(s): -// \z80_|alu_|db_high[1]~3_combout = (\z80_|alu_|op2_high [1] & (((\z80_|alu_|op1_high [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_high [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [1]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [1]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~3 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~2 ( -// Equation(s): -// \z80_|alu_|db_high[1]~2_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~2 .lut_mask = 16'h7333; -defparam \z80_|alu_|db_high[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N2 -cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( -// Equation(s): -// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_sw_2d~13_combout ) # ((\z80_|execute_|ctl_alu_oe~14_combout ) # (\z80_|execute_|ctl_reg_out_hi~7_combout )) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFEE; -defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( +// Location: FF_X31_Y16_N23 +dffeas \z80_|address_latch_|Q[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~70 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~72 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~71_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[5]~24_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~71 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~69 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~73_combout = (\z80_|reg_file_|gdfx_temp1[5]~70_combout & (\z80_|reg_file_|gdfx_temp1[5]~72_combout & (\z80_|reg_file_|gdfx_temp1[5]~71_combout & \z80_|reg_file_|gdfx_temp1[5]~69_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~70_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~72_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~71_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~69_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~67_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~67 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N27 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~16 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~68 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~74_combout = (\z80_|reg_file_|gdfx_temp1[5]~73_combout & (\z80_|reg_file_|gdfx_temp1[5]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout & \z80_|reg_file_|gdfx_temp1[5]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[5]~16_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~75_combout = ((\z80_|reg_file_|gdfx_temp1[5]~74_combout & ((\z80_|reg_file_|db_hi_as[5]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~74_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~75 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp1[5]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N4 -cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( -// Equation(s): -// \z80_|alu_|db[5]~23_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[5]~29_combout & ((\z80_|reg_file_|gdfx_temp1[5]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// (((\z80_|reg_file_|gdfx_temp1[5]~75_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|alu_control_|db[5]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N6 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_high[1]~7_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db[5]~23_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_mWrite~2_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~24_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y11_N25 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [12]), + .d(\z80_|address_latch_|Q[0]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -24891,815 +20392,31 @@ dffeas \z80_|address_latch_|Q[12] ( .ena(\z80_|execute_|ctl_al_we~12_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), + .q(\z80_|address_latch_|Q [0]), .prn(vcc)); // synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [11] $ -// (\z80_|execute_|ctl_inc_dec~8_combout ))))) +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - .dataa(\z80_|address_latch_|Q [12]), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [4] & ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~22 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|db_hi_as[4]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~23_combout = (\z80_|reg_file_|db_hi_as[4]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~22_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~23 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[4]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~24_combout = ((\z80_|reg_file_|db_hi_as[4]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~24 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~17 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~77 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~76 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~79 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~78 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~80_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[4]~10_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[4]~10_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~80 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~81 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~82_combout = (\z80_|reg_file_|gdfx_temp1[4]~79_combout & (\z80_|reg_file_|gdfx_temp1[4]~78_combout & (\z80_|reg_file_|gdfx_temp1[4]~80_combout & \z80_|reg_file_|gdfx_temp1[4]~81_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~79_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~78_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~80_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~81_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~83_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout & (\z80_|reg_file_|gdfx_temp1[4]~77_combout & (\z80_|reg_file_|gdfx_temp1[4]~76_combout & \z80_|reg_file_|gdfx_temp1[4]~82_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[4]~17_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~76_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~84_combout = ((\z80_|reg_file_|gdfx_temp1[4]~83_combout & ((\z80_|reg_file_|db_hi_as[4]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~83_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~84 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp1[4]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~2_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~19_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # (\z80_|execute_|ctl_sw_4u~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & \z80_|decode_state_|DFFE_inst4~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # (\z80_|execute_|ctl_inc_cy~80_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~70_combout ), - .datab(\z80_|execute_|ctl_inc_cy~67_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~81_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), - .datab(\z80_|address_latch_|Q [1]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h66CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N11 +// Location: FF_X31_Y17_N5 dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), @@ -25718,5802 +20435,7 @@ defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|execute_|ctl_reg_gp_sel[1]~29_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hFAD8; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N13 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_alu_op_low~32_combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~32_combout & (\z80_|alu_|op1_high [2])))) # -// (!\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|alu_|op1_low [2])))) - - .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hF0D8; -defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[1]~1_combout = (\z80_|execute_|ctl_alu_op_low~32_combout & (((\z80_|alu_|op1_low [1])))) # (!\z80_|execute_|ctl_alu_op_low~32_combout & ((\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|alu_|op1_high [1])) # -// (!\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|alu_|op1_low [1]))))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[1]~1 .lut_mask = 16'hE2F0; -defparam \z80_|alu_|alu_op1[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op2[1]~0_combout & \z80_|alu_|alu_op1[1]~1_combout )) - - .dataa(\z80_|alu_|alu_op2[1]~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~combout ), - .datac(gnd), - .datad(\z80_|alu_|alu_op1[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hEECC; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[1]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [1]))))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|alu_|alu_op2[1]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0027; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N8 -cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( -// Equation(s): -// \z80_|alu_|db[1]~15_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[1]~26_combout & ((\z80_|reg_file_|gdfx_temp1[1]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// (((\z80_|reg_file_|gdfx_temp1[1]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N10 -cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( -// Equation(s): -// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~15_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db[1]~15_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~48_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[0]~48_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~10 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~11_combout = (\z80_|reg_file_|db_hi_as[0]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~11 .lut_mask = 16'hB0B0; -defparam \z80_|reg_file_|db_hi_as[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0020; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[6]~15_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datad(\z80_|alu_control_|db[6]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~29_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|decode_state_|DFFE_inst4~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~47_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~75_combout & (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~78_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout & (\z80_|reg_file_|gdfx_temp0[6]~74_combout & \z80_|reg_file_|gdfx_temp0[6]~73_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (\z80_|reg_file_|db_lo_as[4]~15_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N11 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [4]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [4]) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h3C3C; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ -// (\z80_|execute_|ctl_inc_dec~8_combout ))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|Q [4]), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|Q [5]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'hD728; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X39_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~29_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[5]~29_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|alu_control_|db[5]~29_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~67_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~63_combout & (\z80_|reg_file_|gdfx_temp0[5]~64_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datac(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout = \z80_|reg_file_|db_lo_as[5]~18_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (\z80_|reg_file_|db_lo_as[5]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|address_latch_|Q[5]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[5]~feeder_combout = \z80_|address_latch_|abusz [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [5]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N9 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[5]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (\z80_|execute_|ctl_inc_dec~6_combout )) # (!\z80_|execute_|ctl_inc_dec~7_combout ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h5559; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N15 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~8_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & -// (\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_inc_dec~8_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2 .lut_mask = 16'h0BB0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[7]~18_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (\z80_|reg_file_|db_lo_as[7]~24_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[7]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[7]~feeder_combout = \z80_|address_latch_|abusz [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [7]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N5 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[7]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~12_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N31 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [7]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hD728; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~12_combout = ((\z80_|reg_file_|db_hi_as[0]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~11_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~12 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_hi_as[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~41 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~14 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~42 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~44_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[0]~18_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[0]~18_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~44 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[0]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~45 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[0]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~43_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~46_combout = (\z80_|reg_file_|gdfx_temp1[0]~42_combout & (\z80_|reg_file_|gdfx_temp1[0]~44_combout & (\z80_|reg_file_|gdfx_temp1[0]~45_combout & \z80_|reg_file_|gdfx_temp1[0]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~42_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~44_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~45_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~40 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[0]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~47_combout = (\z80_|reg_file_|gdfx_temp1[0]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout & (\z80_|reg_file_|gdfx_temp1[0]~46_combout & \z80_|reg_file_|gdfx_temp1[0]~40_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~41_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[0]~14_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~46_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~48_combout = ((\z80_|reg_file_|gdfx_temp1[0]~47_combout & ((\z80_|reg_file_|db_hi_as[0]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~12_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~47_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~48 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp1[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N24 -cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( -// Equation(s): -// \z80_|alu_|db[0]~17_combout = (\z80_|alu_|db_low[0]~21_combout & (((\z80_|reg_file_|gdfx_temp1[0]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_|db_low[0]~21_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & -// ((\z80_|reg_file_|gdfx_temp1[0]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_|db_low[0]~21_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~48_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N22 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|alu_|db[0]~17_combout ), - .datac(\z80_|alu_control_|db[0]~12_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4FF; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N2 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [3] & ((\z80_|ir_|opcode [5] & ((\z80_|alu_|db[7]~20_combout ))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_|db[0]~18_combout )))) # (!\z80_|ir_|opcode [3] & -// (((\z80_|alu_|db[7]~20_combout & !\z80_|ir_|opcode [5])))) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hC0AC; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N4 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N20 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((!\z80_|ir_|opcode [4] & \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout )) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datac(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hF4F4; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~16 ( -// Equation(s): -// \z80_|alu_|db_low[0]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[1]~16_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~16 .lut_mask = 16'hF5A0; -defparam \z80_|alu_|db_low[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~17 ( -// Equation(s): -// \z80_|alu_|db_low[0]~17_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~16_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~18_combout )))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db_low[0]~16_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(\z80_|alu_|db[0]~18_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~17 .lut_mask = 16'hB8FF; -defparam \z80_|alu_|db_low[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( -// Equation(s): -// \z80_|alu_|db_low[0]~19_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [0] & ((\z80_|alu_|op1_low [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [0])) -// # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|alu_|op2_low [0]), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hF351; -defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # -// (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h57FF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~16_combout )))) # -// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~16_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & -// (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hEEC0; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # ((!\z80_|execute_|ctl_flags_alu~15_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & ((\z80_|execute_|ctl_flags_hf_we~2_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hB8AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y14_N23 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~14_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~11_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~11_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'h55F7; -defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & !\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal61~2_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFFA8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_control_|db[1]~26_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFFEC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|alu_|db_high[3]~19_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) - - .dataa(\z80_|alu_|db_high[3]~19_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFBF3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hB0F0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'h40C0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~16_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout )) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout & (\z80_|execute_|ctl_alu_core_hf~16_combout & \z80_|execute_|ctl_flags_nf_we~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal61~2_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~4_combout = ((\z80_|execute_|ctl_flags_nf_we~3_combout ) # ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_alu_core_hf~16_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hF000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N8 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (((!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0133; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout & (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'hB830; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X44_Y15_N29 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~9_combout = (\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_flags_hf_cpl~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (\z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'hFEFE; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_hf_cpl~10_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~8_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'h4404; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N0 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h0FB4; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_core_hf~16_combout & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~14_combout )) # (!\z80_|execute_|ctl_alu_core_hf~17_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (!\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|execute_|ctl_alu_core_hf~15_combout ) # ((!\z80_|execute_|ctl_alu_op_low~38_combout & \z80_|execute_|ctl_alu_core_hf~18_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'h3130; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_mRead~38_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hF400; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout & ((!\z80_|execute_|ctl_mRead~38_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'hDCFC; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~20_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hFFF4; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout & (((!\z80_|execute_|ctl_alu_op_low~27_combout & \z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_op_low~34_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~23_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (\z80_|execute_|ctl_alu_core_hf~21_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h30BA; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_op_low~18_combout & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_alu_op_low~33_combout & ((\z80_|execute_|ctl_alu_core_hf~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~17_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_mWrite~2_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h8A88; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) # (!\z80_|execute_|ctl_mRead~8_combout & -// (\z80_|sequencer_|DFFE_M2_ff~q & ((!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (((\z80_|execute_|ctl_alu_op_low~17_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ixy_d~7_combout & -// (!\z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hF022; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (!\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout ))) # -// (!\z80_|pla_decode_|Equal56~0_combout & (\z80_|execute_|ctl_alu_core_hf~29_combout & \z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'h5440; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout & ((\z80_|execute_|ctl_alu_core_hf~31_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal10~0_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (!\z80_|execute_|ctl_alu_op_low~20_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~26_combout ) # (\z80_|execute_|ctl_alu_core_hf~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h0054; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout & !\z80_|execute_|ctl_alu_op_low~26_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ixy_d~5_combout ) # ((!\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ixy_d~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hF3F0; -defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~39_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~4_combout & \z80_|pla_decode_|Equal40~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hD0C0; -defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_alu_core_hf~24_combout ) # ((\z80_|execute_|ctl_alu_core_hf~33_combout ) # ((\z80_|execute_|ctl_alu_core_hf~40_combout & !\z80_|execute_|ctl_alu_op_low~30_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_core_hf~19_combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N30 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~35_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~35_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_flags_|flags_hf~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hCCAA; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~8 ( -// Equation(s): -// \z80_|alu_|db_high[0]~8_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~8 .lut_mask = 16'h3733; -defparam \z80_|alu_|db_high[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[0]~13_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00A0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N27 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~9 ( -// Equation(s): -// \z80_|alu_|db_high[0]~9_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [0] & ((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_high -// [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datab(\z80_|alu_|op2_high [0]), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op1_high [0]), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~9 .lut_mask = 16'hDD0D; -defparam \z80_|alu_|db_high[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~10 ( -// Equation(s): -// \z80_|alu_|db_high[0]~10_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~10 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_high[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~11 ( -// Equation(s): -// \z80_|alu_|db_high[0]~11_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~10_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~10_combout )) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~11 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_high[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~12 ( -// Equation(s): -// \z80_|alu_|db_high[0]~12_combout = (\z80_|alu_|db_high[0]~8_combout & (\z80_|alu_|db_high[0]~9_combout & ((\z80_|alu_|db_high[0]~11_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~8_combout ), - .datab(\z80_|alu_|db_high[0]~9_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[0]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~12 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~13 ( -// Equation(s): -// \z80_|alu_|db_high[0]~13_combout = ((\z80_|alu_|db_high[0]~12_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datab(\z80_|alu_|db_high[0]~12_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~13 .lut_mask = 16'hC8FF; -defparam \z80_|alu_|db_high[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[0]~13_combout ) # ((\z80_|alu_|db_low[0]~21_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((\z80_|alu_|db_low[0]~21_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_high[0]~13_combout ), - .datac(\z80_|alu_|db_low[0]~21_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N15 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_bus_inc_oe~44_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|pla_decode_|Equal61~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ) # (!\z80_|execute_|ctl_alu_op_low~39_combout -// ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # (((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # (((\z80_|execute_|ctl_alu_sel_op2_neg~12_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N20 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datab(\z80_|alu_|op2_low [0]), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~1 .lut_mask = 16'h1BE4; -defparam \z80_|alu_|alu_op2[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~0_combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op2[0]~1_combout -// )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & (\z80_|alu_|alu_op1[0]~0_combout & (\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op2[0]~1_combout ))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datab(\z80_|alu_|alu_op1[0]~0_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op2[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hEAA8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N17 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( -// Equation(s): -// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & !\z80_|bus_control_|db[5]~17_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h3337; -defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( -// Equation(s): -// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~19_combout & (\z80_|alu_|db_low[0]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|db_low[0]~19_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|alu_|db_low[0]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'hC800; -defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = ((\z80_|alu_|db_low[0]~17_combout & \z80_|alu_|db_low[0]~20_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(gnd), - .datab(\z80_|alu_|db_low[0]~17_combout ), - .datac(\z80_|alu_|db_low[0]~20_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hC0FF; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[0]~13_combout ) # ((\z80_|alu_|db_low[0]~21_combout & \z80_|execute_|ctl_alu_op1_sel_bus~14_combout )))) # -// (!\z80_|execute_|ctl_alu_op1_sel_low~combout & (\z80_|alu_|db_low[0]~21_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|alu_|db_low[0]~21_combout ), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N11 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|alu_|op1_high [0]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~0 .lut_mask = 16'hF3C0; -defparam \z80_|alu_|alu_op1[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_low[0]~21_combout ) # ((\z80_|alu_|alu_op1[0]~0_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|alu_|alu_op1[0]~0_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|alu_op1[0]~0_combout ), - .datac(\z80_|alu_|db_low[0]~21_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(gnd), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0C0C; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N29 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(gnd), - .datab(\z80_|alu_|op2_low [0]), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~0_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & !\z80_|execute_|ctl_alu_core_S~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hCCCF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # -// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h2223; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & \z80_|alu_|alu_op2[2]~2_combout )) - - .dataa(\z80_|alu_|alu_op1[2]~2_combout ), - .datab(gnd), - .datac(\z80_|alu_|alu_op2[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFA0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h33BF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op1[2]~2_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op2[2]~2_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op1[2]~2_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[2]~2_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[2]~2_combout ), - .datab(\z80_|alu_|alu_op2[2]~2_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hFE80; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y16_N11 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h3030; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N26 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~7 ( -// Equation(s): -// \z80_|alu_|db_low[2]~7_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|op2_low [2]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~7 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db_low[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~8 ( -// Equation(s): -// \z80_|alu_|db_low[2]~8_combout = (\z80_|alu_|db_low[2]~7_combout & (((!\z80_|bus_control_|db[5]~17_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~17_combout ), - .datab(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_low[2]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~8 .lut_mask = 16'h4F00; -defparam \z80_|alu_|db_low[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~59 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~62_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[2]~12_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[2]~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~62 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~63 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~61_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~61 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~60 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~64_combout = (\z80_|reg_file_|gdfx_temp1[2]~62_combout & (\z80_|reg_file_|gdfx_temp1[2]~63_combout & (\z80_|reg_file_|gdfx_temp1[2]~61_combout & \z80_|reg_file_|gdfx_temp1[2]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~62_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~63_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~61_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~15 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~58_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~58 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~65_combout = (\z80_|reg_file_|gdfx_temp1[2]~59_combout & (\z80_|reg_file_|gdfx_temp1[2]~64_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout & \z80_|reg_file_|gdfx_temp1[2]~58_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~59_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~64_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~58_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~66_combout = ((\z80_|reg_file_|gdfx_temp1[2]~65_combout & ((\z80_|reg_file_|db_hi_as[2]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~65_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~66 .lut_mask = 16'hDD5D; -defparam \z80_|reg_file_|gdfx_temp1[2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( -// Equation(s): -// \z80_|alu_|db[2]~11_combout = (\z80_|alu_control_|db[2]~22_combout & ((\z80_|reg_file_|gdfx_temp1[2]~66_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[2]~22_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[2]~66_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[2]~22_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~11 .lut_mask = 16'h8ACF; -defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N14 -cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( -// Equation(s): -// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~22_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[2]~11_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db_low[2]~22_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( -// Equation(s): -// \z80_|alu_|db_low[2]~5_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( -// Equation(s): -// \z80_|alu_|db_low[2]~6_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~5_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~12_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_|db_low[2]~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'hCAFF; -defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N2 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( -// Equation(s): -// \z80_|alu_|db_low[2]~9_combout = (\z80_|alu_|db_low[2]~8_combout & (\z80_|alu_|db_low[2]~6_combout & ((\z80_|alu_|result_lo [2]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|result_lo [2]), - .datab(\z80_|alu_|db_low[2]~8_combout ), - .datac(\z80_|alu_|db_low[2]~6_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hC080; -defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~22 ( -// Equation(s): -// \z80_|alu_|db_low[2]~22_combout = (\z80_|alu_|db_low[2]~9_combout ) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_low[2]~9_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~22 .lut_mask = 16'hF3F3; -defparam \z80_|alu_|db_low[2]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & ((\z80_|alu_|db_low[2]~22_combout ) # ((\z80_|alu_|db_high[2]~25_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (\z80_|alu_|db_high[2]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(\z80_|alu_|db_high[2]~25_combout ), - .datac(\z80_|alu_|db_low[2]~22_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N19 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N24 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hFC00; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~19 ( -// Equation(s): -// \z80_|alu_control_|db[2]~19_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|alu_flags_|flags_hf2~q ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_66_oe~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~19 .lut_mask = 16'hFFEF; -defparam \z80_|alu_control_|db[2]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~8_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~23 ( -// Equation(s): -// \z80_|alu_control_|db[1]~23_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|alu_|db[1]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_oe~2_combout ) # -// ((!\z80_|alu_|db[1]~16_combout & \z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~23 .lut_mask = 16'h7350; -defparam \z80_|alu_control_|db[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( -// Equation(s): -// \z80_|alu_control_|db[1]~24_combout = (\z80_|alu_control_|db[2]~19_combout & (!\z80_|alu_control_|db[1]~23_combout & ((\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|db[2]~19_combout ), - .datac(\z80_|alu_control_|db[1]~23_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0C04; -defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|alu_control_|db[1]~24_combout & (((\z80_|bus_control_|db[1]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[1]~13_combout ), - .datab(\z80_|alu_control_|db[1]~24_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h08CC; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = (\z80_|alu_control_|db[1]~25_combout ) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_control_|db[1]~25_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'hF0FF; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[1]~26_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .datad(\z80_|alu_control_|db[1]~26_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~29_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~25_combout & \z80_|reg_file_|gdfx_temp0[1]~28_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N3 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N29 +// Location: FF_X31_Y13_N23 dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -31532,101 +20454,101 @@ defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N28 +// Location: LCCOMB_X31_Y13_N22 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[1]~32_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hA2F3; defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N12 +// Location: LCCOMB_X31_Y17_N26 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( // Equation(s): // \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hAF00; +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF300; defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N10 +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~85_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_cy~85_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h6A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N4 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .dataa(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hAF2F; defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N2 +// Location: LCCOMB_X30_Y17_N14 cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( // Equation(s): -// \z80_|address_latch_|abusz [1] = (\z80_|reg_file_|db_lo_as[1]~6_combout & !\z80_|resets_|clrpc~0_combout ) +// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - .dataa(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), .cin(gnd), .combout(\z80_|address_latch_|abusz [1]), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h00AA; +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h3300; defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[1]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[1]~feeder_combout = \z80_|address_latch_|abusz [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N23 +// Location: FF_X30_Y17_N19 dffeas \z80_|address_latch_|Q[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[1]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [1]), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|execute_|ctl_al_we~12_combout ), .devclrn(devclrn), .devpor(devpor), @@ -31637,30 +20559,13 @@ defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; defparam \z80_|address_latch_|Q[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hFF0F; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 +// Location: LCCOMB_X30_Y17_N6 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ))) +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), .datac(\z80_|address_latch_|Q [1]), .datad(\z80_|execute_|ctl_inc_dec~10_combout ), .cin(gnd), @@ -31671,493 +20576,16 @@ defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .lut_mask = defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[2]~22_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|alu_control_|db[2]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~35_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~37_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[2]~42_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 +// Location: LCCOMB_X29_Y17_N22 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & -// \z80_|execute_|ctl_inc_cy~81_combout )))) +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|execute_|ctl_inc_cy~85_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datab(\z80_|execute_|ctl_inc_cy~85_combout ), .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|execute_|ctl_inc_cy~81_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), .cout()); @@ -32166,44 +20594,61 @@ defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N4 +// Location: LCCOMB_X31_Y17_N16 cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - .dataa(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), .cin(gnd), .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'h8FAF; +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hF575; defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N16 +// Location: LCCOMB_X29_Y17_N12 cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( // Equation(s): -// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) +// \z80_|address_latch_|abusz [2] = (\z80_|reg_file_|db_lo_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - .dataa(gnd), + .dataa(\z80_|reg_file_|db_lo_as[2]~9_combout ), .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), .cin(gnd), .combout(\z80_|address_latch_|abusz [2]), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h00AA; defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N17 +// Location: LCCOMB_X29_Y17_N14 +cycloneive_lcell_comb \z80_|address_latch_|Q[2]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[2]~feeder_combout = \z80_|address_latch_|abusz [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [2]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N15 dffeas \z80_|address_latch_|Q[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [2]), + .d(\z80_|address_latch_|Q[2]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -32219,2641 +20664,112 @@ defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; defparam \z80_|address_latch_|Q[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y10_N28 +// Location: LCCOMB_X30_Y17_N2 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ))) +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|address_latch_|Q [2]), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h0F87; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h40BF; defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Location: LCCOMB_X35_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( // Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) +// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ctl_inc_cy~80_combout ), + .datad(\z80_|execute_|ctl_inc_cy~83_combout ), .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), + .combout(\z80_|execute_|ctl_inc_cy~86_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N13 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [3]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (!\z80_|execute_|ctl_inc_dec~2_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [4]) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(gnd), - .datac(\z80_|address_latch_|Q [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hAF00; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hDD00; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X39_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N15 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~59_combout & (\z80_|reg_file_|gdfx_temp0[4]~58_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .datab(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .datac(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h80A0; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & (\z80_|reg_file_|gdfx_temp0[4]~56_combout & \z80_|reg_file_|gdfx_temp0[4]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( -// Equation(s): -// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~10_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~10_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; -defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (!\z80_|alu_control_|db[4]~30_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_control_|db[4]~30_combout ), - .datab(\z80_|alu_flags_|flags_hf~combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h4500; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|alu_control_|db[4]~31_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hC4FF; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( -// Equation(s): -// \z80_|alu_|db[4]~8_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[4]~32_combout & ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[4]~84_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~84_combout ), - .datac(\z80_|alu_control_|db[4]~32_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~8 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N16 -cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( -// Equation(s): -// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[4]~8_combout ), - .datab(\z80_|alu_|db[7]~9_combout ), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~4 ( -// Equation(s): -// \z80_|alu_|db_high[1]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~22_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~10_combout )) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~4 .lut_mask = 16'hCACA; -defparam \z80_|alu_|db_high[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~5 ( -// Equation(s): -// \z80_|alu_|db_high[1]~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[1]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~5 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_high[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~6 ( -// Equation(s): -// \z80_|alu_|db_high[1]~6_combout = (\z80_|alu_|db_high[1]~3_combout & (\z80_|alu_|db_high[1]~2_combout & ((\z80_|alu_|db_high[1]~5_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~3_combout ), - .datab(\z80_|alu_|db_high[1]~2_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[1]~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~6 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~7 ( -// Equation(s): -// \z80_|alu_|db_high[1]~7_combout = ((\z80_|alu_|db_high[1]~6_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_high[3]~1_combout ), - .datab(\z80_|alu_|db_high[1]~6_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~7 .lut_mask = 16'hDDD5; -defparam \z80_|alu_|db_high[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), - .datac(\z80_|alu_|db_high[1]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'h00EC; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N9 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hC480; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~15_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) - - .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datab(\z80_|alu_|db_low[1]~15_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N11 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|alu_|op2_high [1]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~0 .lut_mask = 16'h3C5A; -defparam \z80_|alu_|alu_op2[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h7773; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & -// \z80_|alu_|alu_op1[1]~1_combout )))) # (!\z80_|alu_|alu_op2[1]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~1_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[1]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .datad(\z80_|alu_|alu_op1[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hF2B0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y16_N29 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~11 ( -// Equation(s): -// \z80_|alu_|db_low[1]~11_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [1] & ((\z80_|alu_|op2_low [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op2_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~11 .lut_mask = 16'hD0DD; -defparam \z80_|alu_|db_low[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( -// Equation(s): -// \z80_|alu_|db_low[1]~12_combout = (\z80_|alu_|db_low[1]~10_combout & (\z80_|alu_|db_low[1]~11_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~10_combout ), - .datab(\z80_|alu_|result_lo [1]), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_low[1]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( -// Equation(s): -// \z80_|alu_|db_low[1]~13_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_|db[0]~18_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hAACC; -defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( -// Equation(s): -// \z80_|alu_|db_low[1]~14_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~13_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~16_combout )) - - .dataa(\z80_|alu_|db[1]~16_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_low[1]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = ((\z80_|alu_|db_low[1]~12_combout & ((\z80_|alu_|db_low[1]~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_low[1]~12_combout ), - .datab(\z80_|alu_|db_low[1]~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'h8AFF; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (\z80_|alu_|db_high[3]~1_combout & (!\z80_|alu_|db_low[2]~9_combout & ((!\z80_|alu_|db_low[3]~4_combout ) # (!\z80_|alu_|db_low[3]~1_combout )))) - - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_low[2]~9_combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~15_combout & (\z80_|execute_|ctl_flags_alu~16_combout & (!\z80_|alu_|db_low[0]~21_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(\z80_|execute_|ctl_flags_alu~16_combout ), - .datac(\z80_|alu_|db_low[0]~21_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[0]~13_combout & !\z80_|alu_|db_high[1]~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|db_high[0]~13_combout ), - .datad(\z80_|alu_|db_high[1]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h000F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & (!\z80_|alu_|db_high[2]~25_combout & !\z80_|alu_|db_high[3]~19_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .datac(\z80_|alu_|db_high[2]~25_combout ), - .datad(\z80_|alu_|db_high[3]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .lut_mask = 16'h0008; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y18_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal13~0_combout ) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hDFFF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[6]~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[6]~15_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hF800; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y15_N13 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N2 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_control_|out[6]~0_combout & \z80_|alu_|op1_high [0]))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|alu_|op1_high [0]), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFFEA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N14 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) - - .dataa(\z80_|alu_control_|out[6]~1_combout ), - .datab(\z80_|execute_|ctl_66_oe~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|alu_|op1_high [3]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~13 ( -// Equation(s): -// \z80_|alu_control_|db[6]~13_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|out[6]~2_combout ) # (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) # -// (!\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|alu_control_|out[6]~2_combout ) # (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~13 .lut_mask = 16'hDDD0; -defparam \z80_|alu_control_|db[6]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~14 ( -// Equation(s): -// \z80_|alu_control_|db[6]~14_combout = (\z80_|alu_control_|db[6]~13_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(\z80_|alu_control_|db[6]~13_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~14 .lut_mask = 16'h88AA; -defparam \z80_|alu_control_|db[6]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_reg_out_lo~2_combout ))) - - .dataa(\z80_|execute_|rsel3~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFFC8; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~20_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hF4F0; -defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~15 ( -// Equation(s): -// \z80_|alu_control_|db[6]~15_combout = ((\z80_|sw1_|db_down[6]~0_combout & (\z80_|alu_control_|db[6]~14_combout & \z80_|reg_file_|db_lo_ds[6]~0_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|sw1_|db_down[6]~0_combout ), - .datab(\z80_|alu_control_|db[6]~14_combout ), - .datac(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~15 .lut_mask = 16'h80FF; -defparam \z80_|alu_control_|db[6]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N20 -cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( -// Equation(s): -// \z80_|alu_|db[6]~21_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[6]~15_combout & ((\z80_|reg_file_|gdfx_temp1[6]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & -// (((\z80_|reg_file_|gdfx_temp1[6]~21_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~21_combout ), - .datad(\z80_|alu_control_|db[6]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N26 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_high[2]~25_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[6]~21_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~20 ( -// Equation(s): -// \z80_|alu_|db_high[2]~20_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~20_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|alu_|db[7]~20_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~20 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_high[2]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~21 ( -// Equation(s): -// \z80_|alu_|db_high[2]~21_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~20_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[2]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~21 .lut_mask = 16'hFD5D; -defparam \z80_|alu_|db_high[2]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[2]~9_combout ) # (!\z80_|alu_|db_high[3]~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(gnd), - .datac(\z80_|alu_|db_low[2]~9_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6 .lut_mask = 16'hA0AA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ) # ((\z80_|alu_|db_high[2]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|db_high[2]~25_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7 .lut_mask = 16'h5540; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N21 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~22 ( -// Equation(s): -// \z80_|alu_|db_high[2]~22_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [2] & ((\z80_|alu_|op1_high [2]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high -// [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~22 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db_high[2]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~23 ( -// Equation(s): -// \z80_|alu_|db_high[2]~23_combout = (\z80_|alu_|db_high[2]~22_combout & (((\z80_|bus_control_|db[5]~17_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~17_combout ), - .datab(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_high[2]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~23 .lut_mask = 16'h8F00; -defparam \z80_|alu_|db_high[2]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~24 ( -// Equation(s): -// \z80_|alu_|db_high[2]~24_combout = (\z80_|alu_|db_high[2]~21_combout & (\z80_|alu_|db_high[2]~23_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_high[2]~21_combout ), - .datab(\z80_|alu_|db_high[2]~23_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~24 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_high[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|db_high[2]~24_combout ) # (!\z80_|alu_|db_high[3]~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datab(\z80_|alu_|db_high[2]~24_combout ), - .datac(\z80_|alu_|db_high[3]~1_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h008A; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y17_N7 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'hE400; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_low[2]~22_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) - - .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .datab(\z80_|alu_|db_low[2]~22_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y17_N7 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N6 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [2]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [2])))) - - .dataa(\z80_|alu_|op2_low [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~2 .lut_mask = 16'h3C66; -defparam \z80_|alu_|alu_op2[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [2]))))) - - .dataa(\z80_|alu_|alu_op2[2]~2_combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [2]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1015; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hCCEF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hCFCE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~12_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout -// & ((\z80_|execute_|ctl_flags_alu~16_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~12_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_flags_alu~16_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hF444; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~0_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~0 .lut_mask = 16'h2202; -defparam \z80_|execute_|ctl_flags_cf2_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~1_combout = (((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_we~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_we~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~1 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_flags_cf2_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~1_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0D8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y14_N23 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|alu_|db[0]~18_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hE4E4; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # -// (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & -// ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h4472; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout $ ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout & \z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y14_N1 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hFE10; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = (\z80_|execute_|ctl_state_alu~11_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'h8500; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|pla_decode_|Equal10~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'hCECC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_alu_op_low~37_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~27_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'hFFD5; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) # ((\z80_|execute_|ctl_alu_op_low~32_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'hFFEA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~18_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'h7775; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|pla_decode_|Equal9~0_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & -// (((\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFCB8; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hFF20; -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~11_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~11 .lut_mask = 16'hF0F8; -defparam \z80_|execute_|ctl_flags_cf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~11_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_alu_op_low~33_combout & \z80_|execute_|ctl_alu_op_low~18_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~11_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout & \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N14 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~10_combout ))))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0A28; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( -// Equation(s): -// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~15_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|bus_control_|db[0]~15_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h5D00; -defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N28 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|db[0]~18_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hF0FF; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( -// Equation(s): -// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~8_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'hA200; -defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( -// Equation(s): -// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_control_|db[0]~9_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'h8CFF; -defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[0]~12_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .datad(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hC040; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~13_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .datab(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y11_N29 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [0]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~7_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 +// Location: LCCOMB_X29_Y17_N0 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # -// (\z80_|execute_|ctl_inc_cy~80_combout )))) +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~86_combout ) # +// (\z80_|execute_|ctl_inc_cy~70_combout )))) - .dataa(\z80_|execute_|ctl_inc_cy~70_combout ), - .datab(\z80_|execute_|ctl_inc_cy~67_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datab(\z80_|execute_|ctl_inc_cy~46_combout ), + .datac(\z80_|execute_|ctl_inc_cy~86_combout ), + .datad(\z80_|execute_|ctl_inc_cy~70_combout ), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hFE00; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hAAA8; defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y10_N16 +// Location: LCCOMB_X30_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|execute_|ctl_inc_cy~85_combout & ((\z80_|address_latch_|Q [1] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q [0])) # (!\z80_|address_latch_|Q +// [1] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [0])))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_cy~85_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'h2400; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N10 cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout +// ))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), + .dataa(gnd), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), .datad(\z80_|address_latch_|Q [3]), .cin(gnd), .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h7F80; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h3FC0; defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N3 +// Location: FF_X28_Y10_N15 dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -34872,7 +20788,7 @@ defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y11_N21 +// Location: FF_X28_Y10_N21 dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -34891,7 +20807,7 @@ defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y11_N2 +// Location: LCCOMB_X28_Y10_N14 cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( // Equation(s): // \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # @@ -34909,15 +20825,32 @@ defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y12_N19 +// Location: LCCOMB_X29_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N27 dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -34928,7 +20861,7 @@ defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X38_Y12_N3 +// Location: FF_X30_Y11_N11 dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -34947,123 +20880,33 @@ defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N2 +// Location: LCCOMB_X30_Y11_N10 cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) +// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), .cin(gnd), .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hB0BB; defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[3]~35_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|alu_control_|db[3]~35_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y13_N13 +// Location: FF_X30_Y10_N5 dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), .devclrn(devclrn), .devpor(devpor), @@ -35074,7 +20917,7 @@ defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X39_Y12_N29 +// Location: FF_X30_Y10_N11 dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -35093,345 +20936,3536 @@ defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y12_N28 +// Location: LCCOMB_X30_Y10_N10 cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) +// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), .cin(gnd), .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~47_combout & \z80_|reg_file_|gdfx_temp0[3]~49_combout ))) +// \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X35_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N6 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~2 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~2_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~2 .lut_mask = 16'hF8FC; -defparam \z80_|sw1_|db_down[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~2_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[3]~33_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datad(\z80_|sw1_|db_down[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hA200; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[3]~34_combout ), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hD5DD; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N18 -cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( -// Equation(s): -// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), - .datab(\z80_|alu_|db[3]~13_combout ), - .datac(\z80_|alu_control_|db[3]~35_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hC4FF; -defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~0 ( -// Equation(s): -// \z80_|alu_|db_low[3]~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) - - .dataa(\z80_|alu_|db[2]~12_combout ), + .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~0 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~1 ( -// Equation(s): -// \z80_|alu_|db_low[3]~1_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~14_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[3]~14_combout ), - .datab(\z80_|alu_|db_low[3]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~1 .lut_mask = 16'hCAFF; -defparam \z80_|alu_|db_low[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~23 ( -// Equation(s): -// \z80_|alu_|db_low[3]~23_combout = ((\z80_|alu_|db_low[3]~1_combout & \z80_|alu_|db_low[3]~4_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), .datac(gnd), - .datad(\z80_|alu_|db_low[3]~4_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .cin(gnd), - .combout(\z80_|alu_|db_low[3]~23_combout ), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|db_low[3]~23 .lut_mask = 16'hBB33; -defparam \z80_|alu_|db_low[3]~23 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))))) +// Location: FF_X29_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(\z80_|alu_|op1_low [3]), - .datac(\z80_|alu_|op1_high [3]), +// Location: FF_X30_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h3F3B; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~29_combout ) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|setM1~29_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_al_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hB3F3; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|execute_|setM1~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h5DDD; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # (!\z80_|execute_|ctl_reg_gp_we~2_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB3FF; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (\z80_|execute_|ctl_reg_in_hi~11_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~4_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) + + .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|alu_|db[3]~11_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[3]~11_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[3]~11_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h4444; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|execute_|ctl_reg_gp_we~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5450; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~3_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hFB33; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (\z80_|execute_|ctl_reg_sys_we~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF3; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0002; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0008; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & (\z80_|reg_file_|gdfx_temp1[3]~45_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~40_combout & (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout & \z80_|reg_file_|gdfx_temp1[3]~46_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~13_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~13_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[1]~13_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout & (\z80_|reg_file_|gdfx_temp1[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'h8AAA; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h96CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~19_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~19_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[0]~19_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~24_combout & (\z80_|reg_file_|gdfx_temp1[0]~26_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & \z80_|reg_file_|gdfx_temp1[0]~27_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~6_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N9 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [7] & (\z80_|address_latch_|Q [8] & !\z80_|execute_|ctl_inc_dec~11_combout +// )) # (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [8] & \z80_|execute_|ctl_inc_dec~11_combout )))) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1800; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0C0C; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N5 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[9]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [9]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|alu_|db[2]~15_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[2]~15_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[2]~15_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N15 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~35_combout & (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~33_combout & \z80_|reg_file_|gdfx_temp1[2]~36_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~32_combout & (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .datab(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'h8FAF; +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hCC44; +defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (\z80_|reg_file_|db_hi_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|Q[10]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[10]~feeder_combout = \z80_|address_latch_|abusz [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [10]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N27 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[10]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [10] & (\z80_|address_latch_|Q [9] & +// !\z80_|execute_|ctl_inc_dec~11_combout )) # (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [9] & \z80_|execute_|ctl_inc_dec~11_combout )))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [9]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h1800; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N15 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [11]) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(gnd), + .datac(\z80_|address_latch_|Q [11]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|alu_|db_low[3]~11_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'h888A; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~8_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N7 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~3 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~3_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])) + + .dataa(gnd), + .datab(\z80_|alu_|op1_high [3]), + .datac(\z80_|alu_|op1_low [3]), .datad(\z80_|execute_|ctl_alu_op_low~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .combout(\z80_|alu_|alu_op1[3]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'h88A0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_|alu_op1[3]~3 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|alu_op1[3]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( +// Location: LCCOMB_X38_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( // Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|alu_|db_low[3]~23_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high +// [2])))) - .dataa(\z80_|alu_|db_low[3]~23_combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|alu_op2[2]~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h00EC; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0305; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y17_N5 -dffeas \z80_|alu_|op2_low[3] ( +// Location: LCCOMB_X39_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = ((\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mWrite~2_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAAFB; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # +// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[1]~17_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_high[1]~20_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'h5050; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N1 +dffeas \z80_|alu_|op2_high[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -35440,51 +24474,1928 @@ dffeas \z80_|alu_|op2_low[3] ( .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), + .q(\z80_|alu_|op2_high [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4 ( +// Location: LCCOMB_X36_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( // Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[3]~1_combout & \z80_|alu_|db_low[3]~4_combout )) # (!\z80_|alu_|db_high[3]~1_combout ))) +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~20_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - .dataa(\z80_|alu_|db_low[3]~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[1]~20_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4 .lut_mask = 16'hB030; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ) # ((\z80_|alu_|db_high[3]~19_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout )))) +// Location: FF_X36_Y10_N23 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4_combout ), - .datab(\z80_|alu_|db_high[3]~19_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), +// Location: LCCOMB_X37_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'h8C80; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N21 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~20_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal68~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # ((\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|execute_|ctl_state_alu~8_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~9_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~12_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h7577; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal61~2_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hFC00; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~20_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~21_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout & (((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout +// ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .lut_mask = 16'hC4CC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~12_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_alu_core_hf~20_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & !\z80_|pla_decode_|Equal71~2_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|pla_decode_|Equal71~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|pla_decode_|Equal21~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal3~0_combout & +// ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'hFCA8; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal13~1_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & \z80_|pla_decode_|Equal63~0_combout +// ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hFFEC; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y15_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|execute_|ctl_alu_op_low~31_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal72~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (!\z80_|pla_decode_|Equal72~2_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datab(\z80_|pla_decode_|Equal72~2_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout )) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFAFF; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_flags_sz_we~5_combout & \z80_|execute_|ctl_alu_core_R~0_combout )))) # +// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~4_combout = (((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (\z80_|execute_|ctl_flags_sz_we~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'h5000; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( +// Equation(s): +// \z80_|execute_|setM1~16_combout = (\z80_|execute_|setM1~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~31_combout ))) + + .dataa(\z80_|execute_|setM1~15_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0200; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|setM1~16_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|execute_|setM1~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_alu_oe~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (\z80_|execute_|ctl_flags_xy_we~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal11~1_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal11~1_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBAA; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; +defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~8_combout = ((\z80_|execute_|ctl_flags_alu~7_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~8_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_flags_alu~6_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_alu~7_combout ), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0070; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_xy_we~16_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datac(\z80_|execute_|ctl_sw_2d~4_combout ), + .datad(\z80_|execute_|ctl_flags_alu~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_flags_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|execute_|ctl_flags_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = ((\z80_|execute_|ctl_flags_alu~8_combout ) # ((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_alu~8_combout ), + .datac(\z80_|execute_|ctl_flags_alu~14_combout ), + .datad(\z80_|execute_|ctl_flags_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), + .datac(\z80_|alu_control_|db[1]~26_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEEE; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_high[3]~8_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFFB3; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h3070; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'h0800; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'hD850; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y9_N27 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|sequencer_|DFFE_M2_ff~q & +// (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'h7707; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = ((\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'hB3BB; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~15_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal13~2_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) + + .dataa(\z80_|alu_|op2_high [1]), + .datab(\z80_|alu_|op2_low [1]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h5A3C; +defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [1]))))) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(\z80_|alu_|op1_low [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = (((\z80_|pla_decode_|Equal71~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datad(\z80_|pla_decode_|Equal71~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|db_high[0]~26_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|alu_|db_high[0]~26_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) + + .dataa(\z80_|alu_|db_high[0]~26_combout ), + .datab(\z80_|alu_|db_low[0]~23_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout ), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .lut_mask = 16'h00F0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y17_N31 +// Location: FF_X37_Y10_N7 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|alu_|op2_high [0]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h3C5A; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & ((\z80_|ir_|opcode [3]) # ((!\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal62~2_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'hB0F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & \z80_|execute_|ctl_alu_core_S~7_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~9_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # +// (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h37FF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_alu_core_hf~20_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_core_hf~18_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hA0E0; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout & (((\z80_|execute_|ctl_alu_core_hf~19_combout & !\z80_|execute_|ctl_alu_op_low~29_combout )) # (!\z80_|execute_|ctl_alu_op_low~28_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~22_combout & (\z80_|execute_|ctl_alu_core_hf~19_combout & (!\z80_|execute_|ctl_alu_op_low~29_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0CAE; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hFF30; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hDFCC; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~20_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h22F2; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datab(\z80_|execute_|ctl_state_alu~13_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & !\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~7_combout & +// ((!\z80_|execute_|ctl_mWrite~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hC0CA; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~43_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~6_combout & (\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # +// ((\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~43 .lut_mask = 16'hD5C0; +defparam \z80_|execute_|ctl_alu_core_hf~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (!\z80_|execute_|ctl_alu_core_hf~43_combout & ((\z80_|execute_|ctl_alu_core_hf~32_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~32_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'h00E8; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~42_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~42 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_core_hf~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~42_combout & ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # (\z80_|execute_|ctl_alu_core_hf~33_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~41_combout = (!\z80_|execute_|ctl_state_alu~4_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal10~0_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~41 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_core_hf~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & +// (\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal11~1_combout & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal11~1_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~41_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~41_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .datad(\z80_|execute_|ctl_mWrite~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h0054; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~44_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~44 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & ((\z80_|execute_|ctl_alu_core_hf~44_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~44_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'h0E0A; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # ((!\z80_|execute_|ctl_alu_op_low~30_combout & \z80_|execute_|ctl_alu_core_hf~35_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~24_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFCFE; +defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~39_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~2_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = (\z80_|execute_|ctl_alu_core_R~2_combout ) # (((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[3]~11_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .lut_mask = 16'hC0D0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[3]~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), + .datad(\z80_|alu_|db_high[3]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .lut_mask = 16'h5450; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N9 dffeas \z80_|alu_|op2_high[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5_combout ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -35500,649 +26411,2610 @@ defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; defparam \z80_|alu_|op2_high[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y16_N20 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~3 ( +// Location: LCCOMB_X37_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 ( // Equation(s): -// \z80_|alu_|alu_op2[3]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) - - .dataa(\z80_|alu_|op2_low [3]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|op2_high [3]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~3 .lut_mask = 16'h3C66; -defparam \z80_|alu_|alu_op2[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~3_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [3])))) +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|alu_|alu_op2[3]~3_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), .datac(\z80_|execute_|ctl_alu_op_low~combout ), .datad(\z80_|alu_|op1_low [3]), .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), + .datac(\z80_|alu_|db_low[3]~25_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N19 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) + + .dataa(\z80_|alu_|op2_high [3]), + .datab(\z80_|alu_|op2_low [3]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h5A3C; +defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[3]~3_combout & \z80_|alu_|alu_op2[3]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) + + .dataa(\z80_|alu_|alu_op1[3]~3_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|alu_|alu_op2[3]~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high +// [3])))) + + .dataa(\z80_|alu_|alu_op2[3]~2_combout ), + .datab(\z80_|alu_|op1_high [3]), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0131; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0511; defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N24 +// Location: LCCOMB_X39_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hAFAE; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # +// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[4]~32_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|pla_decode_|Equal10~0_combout & +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hFC88; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~14_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~14_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N7 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ctl_state_alu~14_combout )) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|alu_flags_|DFFE_inst_latch_nf~q ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N8 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( +// Equation(s): +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h559A; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N30 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~40_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~40_combout & (\z80_|alu_flags_|flags_cf~combout )) + + .dataa(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(gnd), + .datad(\z80_|alu_flags_|flags_hf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hEE44; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~1_combout )))) +// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~1_combout )))) + + .dataa(\z80_|alu_|alu_op2[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~25_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|alu_|db[3]~11_combout ), + .datac(\z80_|alu_|db[5]~25_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hE4E4; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0C0C; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|Q[12]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[12]~feeder_combout = \z80_|address_latch_|abusz [12] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [12]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[12]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[12]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N15 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[12]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ +// (\z80_|address_latch_|Q [11]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .datad(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~12_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~17_combout )) # (!\z80_|execute_|ctl_reg_in_hi~12_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|alu_|db[4]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y11_N29 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & (\z80_|reg_file_|gdfx_temp1[4]~61_combout & \z80_|reg_file_|gdfx_temp1[4]~60_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|db[4]~16 ( +// Equation(s): +// \z80_|alu_|db[4]~16_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[4]~32_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[4]~32_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~16 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|db[7]~26 ( +// Equation(s): +// \z80_|alu_|db[7]~26_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_alu_oe~13_combout ), + .datac(\z80_|execute_|ctl_alu_oe~9_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~26 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|db[7]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( +// Equation(s): +// \z80_|alu_|db[4]~17_combout = ((\z80_|alu_|db[4]~16_combout & ((\z80_|alu_|db_high[0]~26_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[4]~16_combout ), + .datab(\z80_|alu_|db[7]~26_combout ), + .datac(\z80_|alu_|db_high[0]~26_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h00C8; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~6_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[0]~23_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[4]~17_combout ))) + + .dataa(\z80_|alu_|db_high[0]~23_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[4]~17_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hAAF0; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'h5575; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~26_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[0]~26_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N21 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op1_high [0] & (((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [0] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [0]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [0]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~22_combout & ((\z80_|alu_|db_high[0]~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[0]~24_combout ), + .datab(\z80_|alu_|db_high[0]~21_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'h8C00; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~26 ( +// Equation(s): +// \z80_|alu_|db_high[0]~26_combout = ((\z80_|alu_|db_high[0]~25_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~26 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) # +// (!\z80_|alu_|db_low[0]~23_combout & (((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) + + .dataa(\z80_|alu_|db_low[0]~23_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datad(\z80_|alu_|db_high[0]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h00F0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFEFE; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N31 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|alu_|op1_high [0]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) # +// (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_low[0]~23_combout )))) + + .dataa(\z80_|alu_|alu_op1[0]~1_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h5050; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N15 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(gnd), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0AA; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~9_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & +// \z80_|execute_|ctl_alu_core_S~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_low [1]), + .datac(gnd), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hDD88; +defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[1]~0_combout & \z80_|alu_|alu_op2[1]~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datac(\z80_|alu_|alu_op1[1]~0_combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFBBB; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # +// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F01; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( +// Equation(s): +// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(gnd), + .datad(\z80_|alu_|op1_low [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hEE22; +defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op2[2]~0_combout & \z80_|alu_|alu_op1[2]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|alu_|alu_op1[2]~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hFF0B; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N14 cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( // Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|execute_|ctl_alu_core_R~5_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ))) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op1[3]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & +// \z80_|alu_|alu_op2[3]~2_combout )))) # (!\z80_|alu_|alu_op1[3]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .dataa(\z80_|alu_|alu_op1[3]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|alu_|alu_op2[3]~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), .cin(gnd), .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'h152F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFB20; defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 ( +// Location: LCCOMB_X28_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder ( // Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout -// )) +// \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout .dataa(gnd), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .lut_mask = 16'hCCFC; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~14 ( -// Equation(s): -// \z80_|alu_|db_high[3]~14_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[6]~22_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~14 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_high[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~15 ( -// Equation(s): -// \z80_|alu_|db_high[3]~15_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~14_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~20_combout )))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db_high[3]~14_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~15 .lut_mask = 16'hACFF; -defparam \z80_|alu_|db_high[3]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~16 ( -// Equation(s): -// \z80_|alu_|db_high[3]~16_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_high [3] & ((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high -// [3]) # ((!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op2_high [3]), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~16 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db_high[3]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~17 ( -// Equation(s): -// \z80_|alu_|db_high[3]~17_combout = (\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[5]~17_combout )) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|bus_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~17 .lut_mask = 16'hC000; -defparam \z80_|alu_|db_high[3]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~18 ( -// Equation(s): -// \z80_|alu_|db_high[3]~18_combout = (\z80_|alu_|db_high[3]~15_combout & (\z80_|alu_|db_high[3]~16_combout & ((\z80_|alu_|db_high[3]~17_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) - - .dataa(\z80_|alu_|db_high[3]~15_combout ), - .datab(\z80_|alu_|db_high[3]~16_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_high[3]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~18 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[3]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~19 ( -// Equation(s): -// \z80_|alu_|db_high[3]~19_combout = ((\z80_|alu_|db_high[3]~18_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_high[3]~18_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~19 .lut_mask = 16'hF3B3; -defparam \z80_|alu_|db_high[3]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N30 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~19_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_high[3]~19_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( -// Equation(s): -// \z80_|alu_control_|db[7]~16_combout = (\z80_|alu_flags_|DFFE_inst_latch_sf~q & (!\z80_|alu_|db[7]~20_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q & ((\z80_|execute_|ctl_flags_oe~2_combout ) # -// ((!\z80_|alu_|db[7]~20_combout & \z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h7350; -defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[7]~1_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[7]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[7]~1 .lut_mask = 16'hFF40; -defparam \z80_|reg_file_|db_lo_ds[7]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( -// Equation(s): -// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~1_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~9_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datab(\z80_|reg_file_|db_lo_ds[7]~1_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h4C0C; -defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = ((!\z80_|alu_control_|db[7]~16_combout & (\z80_|alu_control_|db[7]~17_combout & \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[7]~16_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_control_|db[7]~17_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h7333; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|execute_|ctl_flags_alu~16_combout & \z80_|alu_|db_high[3]~19_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (\z80_|execute_|ctl_flags_alu~16_combout & ((\z80_|alu_|db_high[3]~19_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|execute_|ctl_flags_alu~16_combout ), - .datac(\z80_|alu_control_|db[7]~18_combout ), - .datad(\z80_|alu_|db_high[3]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hECA0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y15_N5 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( +// Location: FF_X28_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N18 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal40~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) +// Location: FF_X28_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), +// Location: LCCOMB_X28_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N28 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ) # ((\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|ir_|opcode [4] & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// !\z80_|alu_control_|sel[1]~0_combout )))) +// Location: FF_X27_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|alu_control_|sel[1]~0_combout ), +// Location: FF_X27_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hAAD8; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y16_N18 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ))) +// Location: FF_X27_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), +// Location: FF_X28_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N10 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q ))) +// Location: FF_X28_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|alu_|alu_parity_out~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), +// Location: LCCOMB_X28_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|alu_|db[7]~21_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[7]~21_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[7]~21_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~69_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & (\z80_|reg_file_|gdfx_temp1[7]~72_combout & \z80_|reg_file_|gdfx_temp1[7]~71_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout & \z80_|reg_file_|gdfx_temp1[7]~68_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~75_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & +// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [13]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|alu_|db[5]~25_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[5]~25_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[5]~25_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~52_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N9 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~50_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), .datad(gnd), .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), + .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h5656; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X41_Y13_N11 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( // Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~11_combout ))) +// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), + .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout ) +// \z80_|address_latch_|abusz [13] = (\z80_|reg_file_|db_hi_as[5]~15_combout & !\z80_|resets_|clrpc~0_combout ) - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal62~3_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .combout(\z80_|address_latch_|abusz [13]), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'hFFFD; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0C0C; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|Q[13]~feeder ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h7000; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|alu_control_|DFFE_latch_pf_tmp~q ) # (\z80_|execute_|ctl_alu_op_low~combout ))))) - - .dataa(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|alu_parity_out~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h1E00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~38_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = ((\z80_|execute_|ctl_flags_pf_we~5_combout ) # ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_flags_xy_we~11_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & \z80_|execute_|ctl_flags_alu~16_combout ) +// \z80_|address_latch_|Q[13]~feeder_combout = \z80_|address_latch_|abusz [13] .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [13]), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .combout(\z80_|address_latch_|Q[13]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'hF000; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|Q[13]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[13]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~19_combout )) +// Location: FF_X28_Y16_N23 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[13]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ) + + .dataa(gnd), .datab(gnd), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|address_latch_|Q [13]), + .datad(\z80_|execute_|ctl_inc_dec~11_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'h000A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~11 ( +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~11_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout )) # (!\z80_|pla_decode_|Equal69~0_combout ))) +// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~21_combout & !\z80_|resets_|clrpc~0_combout ) - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout ), + .combout(\z80_|address_latch_|abusz [15]), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~11 .lut_mask = 16'h8A0A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~11 .sum_lutc_input = "datac"; +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [9] & (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & !\z80_|address_latch_|Q [8]))) - - .dataa(\z80_|address_latch_|Q [9]), - .datab(\z80_|address_latch_|Q [10]), - .datac(\z80_|address_latch_|Q [11]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [1] & (!\z80_|address_latch_|Q [2] & !\z80_|address_latch_|Q [3]))) - - .dataa(\z80_|address_latch_|Q [0]), - .datab(\z80_|address_latch_|Q [1]), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [7] & !\z80_|address_latch_|Q [5]))) - - .dataa(\z80_|address_latch_|Q [6]), - .datab(\z80_|address_latch_|Q [4]), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|Q [5]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N15 +// Location: FF_X28_Y16_N27 dffeas \z80_|address_latch_|Q[15] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_latch_|abusz [15]), @@ -36161,15 +29033,4509 @@ defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; defparam \z80_|address_latch_|Q[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N0 +// Location: LCCOMB_X28_Y16_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|execute_|ctl_inc_dec~11_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|alu_|db[6]~23_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[6]~23_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[6]~23_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & (\z80_|reg_file_|gdfx_temp1[6]~78_combout & \z80_|reg_file_|gdfx_temp1[6]~81_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~76_combout & (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .datab(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|Q[14]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[14]~feeder_combout = \z80_|address_latch_|abusz [14] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [14]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N5 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[14]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [14]), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3363; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( +// Equation(s): +// \z80_|alu_|db[7]~20_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .datad(\z80_|alu_control_|db[7]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db[7]~21 ( +// Equation(s): +// \z80_|alu_|db[7]~21_combout = ((\z80_|alu_|db[7]~20_combout & ((\z80_|alu_|db_high[3]~8_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|alu_|db[7]~26_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~21 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[7]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N22 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~21_combout & ((\z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & +// (\z80_|alu_|db[7]~21_combout )))) + + .dataa(\z80_|alu_|db[7]~21_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_|db[0]~19_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB822; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|alu_control_|db[0]~12_combout & (\z80_|execute_|ctl_flags_bus~combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & +// ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[0]~12_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hD5C0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hE000; +defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y9_N3 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N0 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N4 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) + + .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCCEE; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~23_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(\z80_|alu_|db[6]~23_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~5_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~21_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(\z80_|alu_|db_high[3]~5_combout ), + .datac(\z80_|alu_|db[7]~21_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op2_high [3] & (((\z80_|alu_|op1_high [3])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_high [3] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [3]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_high [3]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~27 ( +// Equation(s): +// \z80_|alu_|db_high[3]~27_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~27 .lut_mask = 16'hD555; +defparam \z80_|alu_|db_high[3]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~27_combout & ((\z80_|alu_|db_high[3]~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[3]~6_combout ), + .datab(\z80_|alu_|db_high[3]~4_combout ), + .datac(\z80_|alu_|db_high[3]~27_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'h80C0; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~8 ( +// Equation(s): +// \z80_|alu_|db_high[3]~8_combout = ((\z80_|alu_|db_high[3]~7_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~8 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~8_combout )))) + + .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .lut_mask = 16'h00EA; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N15 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~9 ( +// Equation(s): +// \z80_|alu_|db_low[3]~9_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~9 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_low[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~10 ( +// Equation(s): +// \z80_|alu_|db_low[3]~10_combout = (\z80_|alu_|db_low[3]~9_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~15_combout ), + .datab(\z80_|alu_|db_low[3]~9_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~10 .lut_mask = 16'h4C0C; +defparam \z80_|alu_|db_low[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N15 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( +// Equation(s): +// \z80_|alu_|db_low[3]~7_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~17_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) + + .dataa(\z80_|alu_|db[4]~17_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( +// Equation(s): +// \z80_|alu_|db_low[3]~8_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~7_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~11_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|alu_|db[3]~11_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_low[3]~7_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~11 ( +// Equation(s): +// \z80_|alu_|db_low[3]~11_combout = (\z80_|alu_|db_low[3]~10_combout & (\z80_|alu_|db_low[3]~8_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[3]~10_combout ), + .datab(\z80_|alu_|result_lo [3]), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|db_low[3]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~11 .lut_mask = 16'hA800; +defparam \z80_|alu_|db_low[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( +// Equation(s): +// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_high[3]~2_combout ), + .datac(\z80_|alu_|db_low[3]~11_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hF1F1; +defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N12 +cycloneive_lcell_comb \z80_|alu_|db[3]~10 ( +// Equation(s): +// \z80_|alu_|db[3]~10_combout = (\z80_|execute_|ctl_alu_oe~14_combout & (\z80_|alu_|db_low[3]~25_combout & ((\z80_|reg_file_|gdfx_temp1[3]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~14_combout & +// (((\z80_|reg_file_|gdfx_temp1[3]~48_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datad(\z80_|alu_|db_low[3]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~10 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|db[3]~11 ( +// Equation(s): +// \z80_|alu_|db[3]~11_combout = ((\z80_|alu_|db[3]~10_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[3]~10_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[3]~35_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~11 .lut_mask = 16'hA2FF; +defparam \z80_|alu_|db[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~9_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~3_combout ), + .datac(\z80_|execute_|ctl_alu_oe~9_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0070; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~14_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~14_combout ), + .datab(\z80_|execute_|setM1~49_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_|db_low[3]~25_combout & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[3]~35_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_low[3]~25_combout & +// (\z80_|alu_control_|db[3]~35_combout & (\z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_|db_low[3]~25_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hEAC0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00CC; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|pla_decode_|Equal56~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # +// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N31 +dffeas \z80_|alu_flags_|flags_xf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_xf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( +// Equation(s): +// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|alu_flags_|flags_xf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF030; +defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N16 +cycloneive_lcell_comb \z80_|sw1_|db_down[3]~1 ( +// Equation(s): +// \z80_|sw1_|db_down[3]~1_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[3]~1 .lut_mask = 16'hFF8C; +defparam \z80_|sw1_|db_down[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( +// Equation(s): +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~1_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datab(\z80_|alu_control_|db[3]~33_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|sw1_|db_down[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8C00; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~11_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_|db[3]~11_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[3]~34_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N3 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N17 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [3]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h40BF; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout )))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h6AAA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N27 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N9 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|alu_control_|db[4]~32_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~59_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & \z80_|reg_file_|gdfx_temp0[4]~56_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp0[4]~62_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hCC0C; +defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N23 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [4]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|address_latch_|Q [4]), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0F4B; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout +// ))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h6A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N5 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|alu_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N3 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~68_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hF050; +defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N27 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5595; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|alu_control_|db[6]~22_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N5 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & \z80_|reg_file_|gdfx_temp0[6]~75_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N23 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout ))))) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h001E; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hF575; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|alu_control_|db[7]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[7]~0_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[7]~0 .lut_mask = 16'hF0F8; +defparam \z80_|reg_file_|db_lo_ds[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N11 +dffeas \z80_|interrupts_|im2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|interrupts_|im2~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( +// Equation(s): +// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|reg_file_|db_lo_ds[7]~0_combout ), + .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|bus_control_|db[7]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2A0A; +defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( +// Equation(s): +// \z80_|alu_control_|db[7]~16_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[7]~21_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (\z80_|execute_|ctl_sw_2u~7_combout & (!\z80_|alu_|db[7]~21_combout ))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_|db[7]~21_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h0CAE; +defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( +// Equation(s): +// \z80_|alu_control_|db[7]~18_combout = ((\z80_|alu_control_|db[7]~17_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & !\z80_|alu_control_|db[7]~16_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[7]~17_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|alu_control_|db[7]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h33B3; +defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[7]~18_combout ), + .datac(\z80_|alu_|db_high[3]~8_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y9_N9 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal62~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h008C; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (\z80_|execute_|ctl_flags_pf_we~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_pf_sel[0]~3_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~11_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & (\z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[2]~29_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datad(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'h88F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal62~3_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3070; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h152A; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h3B00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N24 cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( // Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [15] & (!\z80_|address_latch_|Q [13] & !\z80_|address_latch_|Q [12]))) +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [13]))) .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|address_latch_|Q [15]), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|Q [12]), + .datab(\z80_|address_latch_|Q [12]), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|Q [13]), .cin(gnd), .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), .cout()); @@ -36178,15 +33544,66 @@ defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y12_N0 +// Location: LCCOMB_X30_Y17_N16 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [2]))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|address_latch_|Q [3]), + .datad(\z80_|address_latch_|Q [2]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0004; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & !\z80_|address_latch_|Q [4]))) + + .dataa(\z80_|address_latch_|Q [7]), + .datab(\z80_|address_latch_|Q [6]), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|address_latch_|Q [4]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [8]))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [11]), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [8]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N18 cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( // Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~0_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~1_combout ))) - .dataa(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .dataa(\z80_|decode_state_|DFFE_instNonRep~0_combout ), .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), .datac(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~1_combout ), .cin(gnd), .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), .cout()); @@ -36195,7 +33612,7 @@ defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N28 +// Location: LCCOMB_X32_Y16_N16 cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( // Equation(s): // \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & @@ -36213,7 +33630,7 @@ defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X41_Y13_N29 +// Location: FF_X32_Y16_N17 dffeas \z80_|decode_state_|DFFE_instNonRep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), @@ -36232,133 +33649,220 @@ defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~12 ( +// Location: LCCOMB_X32_Y16_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout & (((!\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout & -// (((\z80_|decode_state_|DFFE_instNonRep~q )))) +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~11_combout ), - .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~12 .lut_mask = 16'h7F2A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'h02AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N8 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .dataa(\z80_|pla_decode_|Equal62~3_combout ), .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h152A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0040; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'h40CC; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~14 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~14_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~12_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~14 .lut_mask = 16'hFF01; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N0 +// Location: LCCOMB_X32_Y16_N10 cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[2]~22_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datab(\z80_|execute_|ctl_flags_bus~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|alu_control_|db[2]~22_combout ), + .dataa(\z80_|interrupts_|DFFE_instIFF2~q ), + .datab(\z80_|decode_state_|DFFE_instNonRep~q ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), .cin(gnd), .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hD850; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hA030; defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~13 ( +// Location: LCCOMB_X32_Y16_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~13_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # (\z80_|alu_flags_|DFFE_inst_latch_pf~14_combout -// )))) +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h808C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N23 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & +// \z80_|alu_|alu_op1[1]~0_combout )))) # (!\z80_|alu_|alu_op2[1]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|alu_op1[1]~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hFB20; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hA55A; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( +// Equation(s): +// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datad(\z80_|alu_|alu_parity_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out .lut_mask = 16'hA956; +defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal62~3_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFEF; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h20A0; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datac(\z80_|alu_|alu_parity_out~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~13_combout ), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~13 .lut_mask = 16'hFFC8; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~13 .sum_lutc_input = "datac"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X41_Y15_N27 +// Location: LCCOMB_X36_Y11_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hECCC; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N15 dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~13_combout ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -36374,34 +33878,190 @@ defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N26 +// Location: LCCOMB_X37_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[1]~20_combout & (!\z80_|alu_|db_high[3]~8_combout & (!\z80_|alu_|db_high[2]~14_combout & !\z80_|alu_|db_high[0]~26_combout ))) + + .dataa(\z80_|alu_|db_high[1]~20_combout ), + .datab(\z80_|alu_|db_high[3]~8_combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|alu_|db_high[0]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) + + .dataa(\z80_|alu_control_|db[6]~22_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hAA00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~11_combout & (\z80_|alu_|db_high[3]~3_combout & ((!\z80_|alu_|db_low[2]~3_combout ) # (!\z80_|alu_|db_low[2]~6_combout )))) + + .dataa(\z80_|alu_|db_low[2]~6_combout ), + .datab(\z80_|alu_|db_low[3]~11_combout ), + .datac(\z80_|alu_|db_low[2]~3_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h1300; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~17_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[0]~23_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) + + .dataa(\z80_|alu_|db_low[1]~17_combout ), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|alu_|db_low[0]~23_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hEC00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N27 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] +// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N18 cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( // Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ) # ((!\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|alu_control_|sel[1]~0_combout )))) +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|alu_control_|sel[1]~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), .cin(gnd), .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hB8CC; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y16_N24 +// Location: LCCOMB_X37_Y11_N20 cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( // Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout $ (((!\z80_|ir_|opcode [3]))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & // (((\z80_|alu_control_|flags_cond_true~q )))) - .dataa(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .dataa(\z80_|ir_|opcode [3]), .datab(\z80_|execute_|ctl_eval_cond~0_combout ), .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), .cin(gnd), .combout(\z80_|alu_control_|flags_cond_true~0_combout ), .cout()); @@ -36410,7 +34070,7 @@ defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y16_N25 +// Location: FF_X37_Y11_N21 dffeas \z80_|alu_control_|flags_cond_true ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|alu_control_|flags_cond_true~0_combout ), @@ -36429,32 +34089,32 @@ defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Location: LCCOMB_X35_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( // Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ixy_d~5_combout ) +// \z80_|execute_|ctl_reg_sel_wz~13_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - .dataa(\z80_|execute_|ixy_d~5_combout ), + .dataa(\z80_|pla_decode_|Equal35~0_combout ), .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), .datad(\z80_|pla_decode_|Equal34~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y15_N16 +// Location: LCCOMB_X35_Y16_N18 cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( // Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~10_combout ) +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - .dataa(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~13_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), .cout()); @@ -36463,3091 +34123,2050 @@ defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'hF7FF; defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y15_N4 +// Location: LCCOMB_X34_Y14_N0 cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( // Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (((\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~16_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) - .dataa(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~11_combout ), .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hBFFF; defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~17_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Location: LCCOMB_X30_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Location: LCCOMB_X29_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Location: LCCOMB_X30_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~16_combout ) # ((\z80_|execute_|ctl_sw_4u~5_combout ) # (\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .datac(\z80_|execute_|ctl_sw_4u~5_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( +// Location: FF_X30_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( +// Location: FF_X31_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~32 ( +// Location: LCCOMB_X31_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~32_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~32 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~32 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( +// Location: FF_X31_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~13 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ))) # (!\z80_|reg_control_|reg_sel_af~0_combout ) +// Location: FF_X30_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), +// Location: FF_X30_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~13 .lut_mask = 16'hFDFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~13 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~33 ( +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~33_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~33 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~33 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( +// Location: FF_X30_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y15_N3 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~36 ( +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|alu_control_|db[1]~26_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~36_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~36 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~36 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( +// Location: FF_X28_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X35_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~34 ( +// Location: LCCOMB_X28_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~34 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~35_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[1]~16_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # -// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~35 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~37_combout = (\z80_|reg_file_|gdfx_temp1[1]~33_combout & (\z80_|reg_file_|gdfx_temp1[1]~36_combout & (\z80_|reg_file_|gdfx_temp1[1]~34_combout & \z80_|reg_file_|gdfx_temp1[1]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~33_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~36_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~34_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~39_combout +// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( +// Location: FF_X28_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~31 ( +// Location: LCCOMB_X28_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~31_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~31_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~31 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[1]~31 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~38 ( +// Location: LCCOMB_X31_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~38_combout = (\z80_|reg_file_|gdfx_temp1[1]~32_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~37_combout & \z80_|reg_file_|gdfx_temp1[1]~31_combout ))) +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~29_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - .dataa(\z80_|reg_file_|gdfx_temp1[1]~32_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~37_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~31_combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~38_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~38 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~39 ( +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( // Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~39_combout = ((\z80_|reg_file_|gdfx_temp1[1]~38_combout & ((\z80_|reg_file_|db_hi_as[1]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~5_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~5_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~39 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp1[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~7_combout = (\z80_|reg_file_|gdfx_temp1[1]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[1]~39_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~39_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~7 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~8_combout = (\z80_|reg_file_|db_hi_as[1]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[1]~7_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~8 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|execute_|ctl_inc_dec~8_combout & (!\z80_|address_latch_|Q [7] & !\z80_|address_latch_|Q -// [8])) # (!\z80_|execute_|ctl_inc_dec~8_combout & (\z80_|address_latch_|Q [7] & \z80_|address_latch_|Q [8])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~8_combout ), - .datac(\z80_|address_latch_|Q [7]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) +// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout .dataa(gnd), .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~9_combout = ((\z80_|reg_file_|db_hi_as[1]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[1]~8_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~9 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~9_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[1]~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y11_N27 -dffeas \z80_|address_latch_|Q[9] ( +// Location: FF_X29_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [9]), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q -// [9]))))) - - .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), - .datab(\z80_|address_latch_|Q [10]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( +// Location: FF_X29_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~18_combout ), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~16 ( +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( // Equation(s): -// \z80_|reg_file_|db_hi_as[2]~16_combout = (\z80_|reg_file_|gdfx_temp1[2]~66_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[2]~66_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - .dataa(\z80_|reg_file_|gdfx_temp1[2]~66_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~16_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~16 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[2]~16 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( +// Location: FF_X30_Y13_N23 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~18_combout ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hF733; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hF0F8; +defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( +// Equation(s): +// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|bus_control_|db[1]~11_combout ), + .datab(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0C8C; +defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( +// Equation(s): +// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[1]~13_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[1]~13_combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_|db[1]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0ACE; +defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( +// Equation(s): +// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~23_combout & !\z80_|alu_control_|db[1]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[1]~25_combout ), + .datab(\z80_|alu_control_|db[2]~23_combout ), + .datac(\z80_|alu_control_|db[6]~11_combout ), + .datad(\z80_|alu_control_|db[1]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h0F8F; +defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|db[1]~12 ( +// Equation(s): +// \z80_|alu_|db[1]~12_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[1]~26_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[1]~26_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~12 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db[1]~13 ( +// Equation(s): +// \z80_|alu_|db[1]~13_combout = ((\z80_|alu_|db[1]~12_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[1]~12_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~13 .lut_mask = 16'hA2FF; +defparam \z80_|alu_|db[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( +// Equation(s): +// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~13_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|alu_|db[1]~13_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF5A0; +defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( +// Equation(s): +// \z80_|alu_|db_low[0]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~19_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[0]~21_combout ), + .datac(\z80_|alu_|db[0]~19_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( +// Equation(s): +// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h5557; +defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( +// Equation(s): +// \z80_|alu_|db_low[0]~19_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op1_low [0]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N25 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( +// Equation(s): +// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~18_combout & (\z80_|alu_|db_low[0]~19_combout & ((\z80_|alu_|result_lo [0]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[0]~18_combout ), + .datab(\z80_|alu_|db_low[0]~19_combout ), + .datac(\z80_|alu_|result_lo [0]), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( +// Equation(s): +// \z80_|alu_|db_low[0]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & ((\z80_|alu_|db_low[0]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~20_combout ) # +// (!\z80_|alu_|db_high[3]~2_combout )))) + + .dataa(\z80_|alu_|db_low[0]~22_combout ), + .datab(\z80_|alu_|db_high[3]~2_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[0]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hAF03; +defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( +// Equation(s): +// \z80_|alu_|db[0]~18_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_|db_low[0]~23_combout ) # ((!\z80_|execute_|ctl_alu_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_|db_low[0]~23_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db[0]~19 ( +// Equation(s): +// \z80_|alu_|db[0]~19_combout = ((\z80_|alu_|db[0]~18_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[0]~12_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~19 .lut_mask = 16'hA2FF; +defparam \z80_|alu_|db[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( +// Equation(s): +// \z80_|alu_|db_low[1]~15_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~19_combout )) + + .dataa(\z80_|alu_|db[0]~19_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( +// Equation(s): +// \z80_|alu_|db_low[1]~16_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[1]~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[1]~13_combout ))) + + .dataa(\z80_|alu_|db_low[1]~15_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[1]~13_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAAF0; +defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( +// Equation(s): +// \z80_|alu_|db_low[1]~12_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'h5755; +defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( +// Equation(s): +// \z80_|alu_|db_low[1]~13_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op1_low [1]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y10_N21 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( +// Equation(s): +// \z80_|alu_|db_low[1]~14_combout = (\z80_|alu_|db_low[1]~12_combout & (\z80_|alu_|db_low[1]~13_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[1]~12_combout ), + .datab(\z80_|alu_|db_low[1]~13_combout ), + .datac(\z80_|alu_|result_lo [1]), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( +// Equation(s): +// \z80_|alu_|db_low[1]~17_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~16_combout & \z80_|alu_|db_low[1]~14_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~14_combout )) # +// (!\z80_|alu_|db_high[3]~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_high[3]~2_combout ), + .datac(\z80_|alu_|db_low[1]~16_combout ), + .datad(\z80_|alu_|db_low[1]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hF511; +defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_low[1]~17_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[1]~20_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00F0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y10_N1 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .q(\z80_|alu_|op1_low [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~17 ( +// Location: LCCOMB_X36_Y10_N28 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( // Equation(s): -// \z80_|reg_file_|db_hi_as[2]~17_combout = (\z80_|reg_file_|db_hi_as[2]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) - .dataa(\z80_|reg_file_|db_hi_as[2]~16_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .dataa(gnd), + .datab(\z80_|alu_|op1_low [1]), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|alu_|op1_low [2]), .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~17_combout ), + .combout(\z80_|alu_control_|out[6]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~17 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[2]~17 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0C0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~18 ( +// Location: LCCOMB_X36_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( // Equation(s): -// \z80_|reg_file_|db_hi_as[2]~18_combout = ((\z80_|reg_file_|db_hi_as[2]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout ) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~17_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~18 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_hi_as[2]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~18_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), + .dataa(gnd), .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[2]~18_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N8 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|alu_control_|db[4]~32_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N9 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( +// Equation(s): +// \z80_|alu_control_|db[2]~23_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|alu_flags_|flags_hf2~q ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~combout ), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|alu_flags_|flags_hf2~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFEF; +defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|bus_control_|db[2]~13_combout ), + .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h2F00; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( +// Equation(s): +// \z80_|alu_control_|db[2]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[2]~15_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (!\z80_|alu_|db[2]~15_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|alu_|db[2]~15_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h3B0A; +defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( +// Equation(s): +// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~23_combout & (\z80_|alu_control_|db[2]~28_combout & !\z80_|alu_control_|db[2]~27_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[6]~11_combout ), + .datab(\z80_|alu_control_|db[2]~23_combout ), + .datac(\z80_|alu_control_|db[2]~28_combout ), + .datad(\z80_|alu_control_|db[2]~27_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h55D5; +defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db[2]~14 ( +// Equation(s): +// \z80_|alu_|db[2]~14_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~39_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[2]~29_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[2]~29_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~14 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[2]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( +// Equation(s): +// \z80_|alu_|db[2]~15_combout = ((\z80_|alu_|db[2]~14_combout & ((\z80_|alu_|db_low[2]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db_low[2]~24_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[2]~14_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~2 ( +// Equation(s): +// \z80_|alu_|db_low[2]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~13_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|alu_|db[3]~11_combout ), + .datac(\z80_|alu_|db[1]~13_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), + .combout(\z80_|alu_|db_low[2]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~2 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|db_low[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N31 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [10]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Location: LCCOMB_X35_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~3 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~8_combout & (!\z80_|address_latch_|Q [10] & -// !\z80_|address_latch_|Q [9])) # (!\z80_|execute_|ctl_inc_dec~8_combout & (\z80_|address_latch_|Q [10] & \z80_|address_latch_|Q [9])))) +// \z80_|alu_|db_low[2]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~15_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), - .datab(\z80_|address_latch_|Q [10]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .dataa(\z80_|alu_|db[2]~15_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_low[2]~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .combout(\z80_|alu_|db_low[2]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h4200; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~3 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_low[2]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Location: LCCOMB_X35_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [11] & (!\z80_|execute_|ctl_inc_dec~8_combout & -// \z80_|address_latch_|Q [12])) # (!\z80_|address_latch_|Q [11] & (\z80_|execute_|ctl_inc_dec~8_combout & !\z80_|address_latch_|Q [12])))) +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|Q [12]), + .dataa(\z80_|alu_|db_low[2]~6_combout ), + .datab(\z80_|alu_|db_high[3]~3_combout ), + .datac(\z80_|alu_|db_low[2]~3_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0820; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hB300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Location: LCCOMB_X36_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - .dataa(gnd), - .datab(\z80_|address_latch_|Q [13]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h33CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3222; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [5] & ((\z80_|reg_file_|gdfx_temp1[5]~75_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[5]~75_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp1[5]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~19 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[5]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~20_combout = (\z80_|reg_file_|db_hi_as[5]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datad(\z80_|reg_file_|db_hi_as[5]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~20 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_hi_as[5]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~21_combout = ((\z80_|reg_file_|db_hi_as[5]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~21 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[5]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~21_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N27 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [13]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|execute_|ctl_inc_dec~8_combout $ (\z80_|address_latch_|Q [13]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|address_latch_|Q [13]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~6_combout ) # (!\z80_|execute_|ctl_inc_dec~7_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~4_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [7] & ((\z80_|reg_file_|gdfx_temp1[7]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[7]~30_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~30_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~4 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|db_hi_as[7]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~5_combout = (\z80_|reg_file_|db_hi_as[7]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[7]~4_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~5 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[7]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~6_combout = ((\z80_|reg_file_|db_hi_as[7]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .datab(\z80_|reg_file_|db_hi_as[7]~5_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~6 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_hi_as[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~6_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~6_combout ), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h0A0A; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|execute_|ctl_inc_dec~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|execute_|ctl_apin_mux~1_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'hF333; -defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|address_latch_|abusz [15]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0D0D; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ctl_mWrite~2_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~15_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & !\z80_|execute_|fIOWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|fIORead~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( -// Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|ctl_mRead~7_combout & \z80_|execute_|fIOWrite~3_combout ))) - - .dataa(\z80_|execute_|fIORead~2_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|fIOWrite~3_combout ), - .datad(\z80_|execute_|fIORead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N14 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fMRead~36_combout ) # (((\z80_|execute_|fIORead~3_combout ) # (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )) - - .dataa(\z80_|execute_|fMRead~36_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFBF; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout ) # -// ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h4F44; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( +// Location: FF_X36_Y10_N25 +dffeas \z80_|alu_|op1_low[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~17 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[15]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~15_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0030; -defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h0202; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg -// [6] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|WideOr17~0_combout & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|WideOr17~0_combout ), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0088; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~0_combout ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N13 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), + .q(\z80_|alu_|op1_low [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Location: LCCOMB_X37_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [2])) +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [2]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Location: LCCOMB_X37_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~41_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q ))) +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ) # ((\z80_|alu_|db_low[2]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|extended~q ), + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), + .datac(\z80_|alu_|db_low[2]~24_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|zx_keyboard_|keys[6][1]~42_combout & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & (!\ula_|zx_keyboard_|keys[6][1]~40_combout )) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & ((\ula_|zx_keyboard_|keys[6][1]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N31 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( +// Location: FF_X37_Y10_N13 +dffeas \z80_|alu_|op2_low[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~16 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[14]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \D[1]~27 ( -// Equation(s): -// \D[1]~27_combout = (\ula_|zx_keyboard_|keys[7][1]~q & (\z80_|address_pins_|abus[15]~17_combout & ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[7][1]~q & -// (((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~q ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\z80_|address_pins_|abus[14]~16_combout ), - .cin(gnd), - .combout(\D[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~27 .lut_mask = 16'hDD0D; -defparam \D[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~19_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~19 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|keys[7][1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hF000; -defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|keys[5][4]~24_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~26_combout = (\ula_|zx_keyboard_|keys[1][4]~25_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h0C00; -defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N11 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .q(\z80_|alu_|op2_low [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Location: LCCOMB_X38_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) +// \z80_|alu_|db_low[2]~5_combout = (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - .dataa(\z80_|address_latch_|abusz [10]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .dataa(\z80_|alu_|op2_low [2]), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .combout(\z80_|alu_|db_low[2]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'h8ACF; +defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), +// Location: FF_X39_Y10_N13 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [10]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~22 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[10]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00A0; -defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~28_combout = (\ula_|zx_keyboard_|keys[5][4]~24_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[7][1]~19_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N9 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .q(\z80_|alu_|result_lo [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Location: LCCOMB_X35_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) +// \z80_|alu_|db_low[2]~6_combout = (\z80_|alu_|db_low[2]~4_combout & (\z80_|alu_|db_low[2]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2])))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|address_latch_|abusz [11]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|alu_|db_low[2]~4_combout ), + .datab(\z80_|alu_|db_low[2]~5_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|result_lo [2]), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .combout(\z80_|alu_|db_low[2]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N23 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( +// Location: LCCOMB_X35_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) + + .dataa(\z80_|alu_|db_low[2]~6_combout ), + .datab(\z80_|alu_|db_low[2]~3_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h80F0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .datac(\z80_|alu_|db_high[2]~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .lut_mask = 16'h5444; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y10_N27 +dffeas \z80_|alu_|op2_high[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [11]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~21 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[11]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N2 -cycloneive_lcell_comb \D[1]~25 ( -// Equation(s): -// \D[1]~25_combout = (\ula_|zx_keyboard_|keys[2][1]~q & (\z80_|address_pins_|abus[10]~22_combout & ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) # (!\ula_|zx_keyboard_|keys[2][1]~q & -// (((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[2][1]~q ), - .datab(\z80_|address_pins_|abus[10]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\z80_|address_pins_|abus[11]~21_combout ), - .cin(gnd), - .combout(\D[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~25 .lut_mask = 16'hDD0D; -defparam \D[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~31_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h5050; -defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~32_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h1100; -defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][2]~32_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N5 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .q(\z80_|alu_|op2_high [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Location: LCCOMB_X38_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [12]))) +// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [12]), + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datad(\z80_|alu_|op2_low [2]), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .combout(\z80_|alu_|alu_op2[2]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h4B78; +defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y2_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~24 ( +// Location: LCCOMB_X39_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( // Equation(s): -// \z80_|address_pins_|abus[12]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [12]), + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~24_combout ), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[12]~24 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[12]~24 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0BFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Location: LCCOMB_X39_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [13])) +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~2_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - .dataa(\z80_|address_latch_|abusz [13]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|alu_op1[2]~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N3 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~23 ( +// Location: LCCOMB_X34_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( // Equation(s): -// \z80_|address_pins_|abus[13]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_|db_high[2]~9_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - .dataa(gnd), + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'h55D5; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~21_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~25_combout )) + + .dataa(\z80_|ir_|opcode [3]), .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|alu_|db[5]~25_combout ), + .datad(\z80_|alu_|db[7]~21_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~23_combout ), + .combout(\z80_|alu_|db_high[2]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[13]~23 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[13]~23 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hFA50; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( +// Location: LCCOMB_X35_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0011; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|ps2_keyboard_|shiftreg [4])) +// \z80_|alu_|db_high[2]~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[2]~11_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[6]~23_combout ))) .dataa(gnd), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\z80_|alu_|db_high[2]~11_combout ), + .datac(\z80_|alu_|db[6]~23_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .combout(\z80_|alu_|db_high[2]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0030; -defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Location: LCCOMB_X38_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [6])) +// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_high [2]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .combout(\z80_|alu_|db_high[2]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'h8800; -defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Location: LCCOMB_X34_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) +// \z80_|alu_|db_high[2]~13_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~12_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(gnd), + .dataa(\z80_|alu_|db_high[2]~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[2]~12_combout ), + .datad(\z80_|alu_|db_high[2]~10_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .combout(\z80_|alu_|db_high[2]~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( +// Location: LCCOMB_X35_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~14 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~38_combout & ((\ula_|zx_keyboard_|keys[5][1]~37_combout & ((!\ula_|zx_keyboard_|keys[5][1]~35_combout ))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & -// (\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) +// \z80_|alu_|db_high[2]~14_combout = ((\z80_|alu_|db_high[2]~13_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - .dataa(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .datab(\z80_|alu_|db_high[3]~3_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|db_high[2]~13_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .combout(\z80_|alu_|db_high[2]~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db_high[2]~14 .lut_mask = 16'hFB33; +defparam \z80_|alu_|db_high[2]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y13_N29 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \D[1]~26 ( +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( // Equation(s): -// \D[1]~26_combout = (\ula_|zx_keyboard_|keys[4][1]~q & (\z80_|address_pins_|abus[12]~24_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\ula_|zx_keyboard_|keys[4][1]~q & -// (((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) +// \z80_|alu_|db[6]~22_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - .dataa(\ula_|zx_keyboard_|keys[4][1]~q ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[5][1]~q ), + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .datad(\z80_|alu_control_|db[6]~22_combout ), .cin(gnd), - .combout(\D[1]~26_combout ), + .combout(\z80_|alu_|db[6]~22_combout ), .cout()); // synopsys translate_off -defparam \D[1]~26 .lut_mask = 16'hD0DD; -defparam \D[1]~26 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db[6]~23 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [9])) +// \z80_|alu_|db[6]~23_combout = ((\z80_|alu_|db[6]~22_combout & ((\z80_|alu_|db_high[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - .dataa(\z80_|address_latch_|abusz [9]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|alu_|db_high[2]~14_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_|db[7]~26_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .combout(\z80_|alu_|db[6]~23_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +defparam \z80_|alu_|db[6]~23 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[6]~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y3_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~19 ( +// Location: LCCOMB_X36_Y10_N10 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( // Equation(s): -// \z80_|address_pins_|abus[9]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|alu_|op1_high [1]), + .datad(\z80_|alu_control_|out[6]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N26 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) + + .dataa(\z80_|execute_|ctl_66_oe~combout ), + .datab(\z80_|alu_control_|out[6]~1_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEA; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~19 ( +// Equation(s): +// \z80_|alu_control_|db[6]~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & +// (!\z80_|execute_|ctl_flags_oe~2_combout & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|out[6]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~19 .lut_mask = 16'hAF8C; +defparam \z80_|alu_control_|db[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( +// Equation(s): +// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_control_|db[6]~19_combout & ((\z80_|alu_|db[6]~23_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [9]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|alu_|db[6]~23_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[6]~19_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~19_combout ), + .combout(\z80_|alu_control_|db[6]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[9]~19 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[9]~19 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'hCF00; +defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Location: LCCOMB_X34_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) +// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|db[6]~20_combout & (((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - .dataa(\z80_|address_latch_|abusz [8]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|bus_control_|db[6]~9_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|alu_control_|db[6]~20_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .combout(\z80_|alu_control_|db[6]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h30B0; +defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N27 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~20 ( +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( // Equation(s): -// \z80_|address_pins_|abus[8]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|alu_control_|db[6]~22_combout = ((\z80_|alu_control_|db[6]~21_combout & ((\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [8]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|alu_control_|db[6]~11_combout ), + .datab(\z80_|alu_control_|db[6]~21_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~20_combout ), + .combout(\z80_|alu_control_|db[6]~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[8]~20 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[8]~20 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hD5DD; +defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Location: LCCOMB_X39_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) +// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - .dataa(gnd), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hF0F3; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0028; -defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2400; -defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & -// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N1 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~20_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~20 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|keys[1][1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~21 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~21_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~21 .lut_mask = 16'h3000; -defparam \ula_|zx_keyboard_|keys[6][4]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~21_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~23_combout = (\ula_|zx_keyboard_|keys[1][1]~20_combout & ((\ula_|zx_keyboard_|keys[1][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~22_combout & ((\ula_|zx_keyboard_|keys[1][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[1][1]~20_combout & (((\ula_|zx_keyboard_|keys[1][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[1][1]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~23 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[1][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y14_N7 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~23_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N0 -cycloneive_lcell_comb \D[1]~24 ( -// Equation(s): -// \D[1]~24_combout = (\z80_|address_pins_|abus[9]~19_combout & ((\z80_|address_pins_|abus[8]~20_combout ) # ((!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\z80_|address_pins_|abus[9]~19_combout & (!\ula_|zx_keyboard_|keys[1][1]~q & -// ((\z80_|address_pins_|abus[8]~20_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~19_combout ), - .datab(\z80_|address_pins_|abus[8]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[1][1]~q ), - .cin(gnd), - .combout(\D[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~24 .lut_mask = 16'h8ACF; -defparam \D[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N4 -cycloneive_lcell_comb \D[1]~28 ( -// Equation(s): -// \D[1]~28_combout = (\D[1]~27_combout & (\D[1]~25_combout & (\D[1]~26_combout & \D[1]~24_combout ))) - - .dataa(\D[1]~27_combout ), - .datab(\D[1]~25_combout ), - .datac(\D[1]~26_combout ), - .datad(\D[1]~24_combout ), - .cin(gnd), - .combout(\D[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~28 .lut_mask = 16'h8000; -defparam \D[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y14_N0 -cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( -// Equation(s): -// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; -defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y14_N1 -dffeas \z80_|clk_delay_|DFF_inst5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|DFF_inst5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y14_N26 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y14_N27 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; -// synopsys translate_on - -// Location: FF_X52_Y14_N5 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = ((!\z80_|execute_|ctl_mRead~38_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|execute_|ctl_mRead~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'h337F; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_iorw~12_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_iorw~12_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), + .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hC800; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Location: LCCOMB_X34_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( // Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~13_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~6_combout ) +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) - .dataa(\z80_|execute_|nextM~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[3]~21_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h00CC; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N25 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( +// Location: FF_X34_Y10_N9 +dffeas \z80_|interrupts_|im1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(\z80_|execute_|ctl_im_we~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .q(\z80_|interrupts_|im1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( +// Location: LCCOMB_X32_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( // Equation(s): -// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|interrupts_|im1~q ), + .datac(\z80_|interrupts_|im2~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hDC00; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h40EE; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( +// Equation(s): +// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hFF31; +defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), + .combout(\z80_|bus_control_|db[6]~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N13 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N8 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Location: LCCOMB_X37_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( // Equation(s): -// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q +// \z80_|execute_|ctl_mRead~37_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|execute_|ctl_mRead~36_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .combout(\z80_|execute_|ctl_mRead~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N9 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X50_Y16_N3 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N2 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Location: LCCOMB_X37_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( // Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) +// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~37_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .dataa(\z80_|execute_|ctl_mRead~37_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), + .combout(\z80_|execute_|ctl_mRead~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N4 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Location: LCCOMB_X37_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( // Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ctl_mRead~28_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) - .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), - .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), + .dataa(\z80_|execute_|ctl_mRead~28_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .combout(\z80_|execute_|ctl_mRead~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( -// Equation(s): -// \z80_|execute_|setM1~38_combout = (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|fMRead~4_combout & !\z80_|pla_decode_|Equal9~1_combout )) - - .dataa(\z80_|pla_decode_|Equal29~0_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0404; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~57 ( -// Equation(s): -// \z80_|execute_|setM1~57_combout = (!\z80_|execute_|ctl_mRead~16_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~57 .lut_mask = 16'h00EF; -defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~57_combout & (\z80_|execute_|setM1~37_combout & !\z80_|execute_|ctl_mRead~18_combout ))) - - .dataa(\z80_|execute_|setM1~38_combout ), - .datab(\z80_|execute_|setM1~57_combout ), - .datac(\z80_|execute_|setM1~37_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & ((!\z80_|execute_|setM1~39_combout ) # (!\z80_|execute_|ctl_mRead~21_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_mRead~21_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h1050; -defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~35_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~14_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hEEAA; -defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~40 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~40_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal38~2_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~40 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_mRead~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~39 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~39_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~38_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~39 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_mRead~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N0 +// Location: LCCOMB_X35_Y16_N28 cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( // Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~27_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )))) +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~29_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_mRead~27_combout ), + .dataa(\z80_|execute_|ctl_mRead~29_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'h0080; defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Location: LCCOMB_X38_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( // Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~40_combout & (\z80_|execute_|ctl_mRead~26_combout & (\z80_|execute_|ctl_mRead~39_combout & \z80_|execute_|ctl_mRead~30_combout ))) +// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|ctl_al_we~4_combout & \z80_|execute_|ctl_inc_cy~41_combout ))) - .dataa(\z80_|execute_|ctl_mRead~40_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_mRead~39_combout ), - .datad(\z80_|execute_|ctl_mRead~30_combout ), + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|execute_|ctl_inc_cy~41_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), + .combout(\z80_|execute_|setM1~37_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~37 .lut_mask = 16'h1000; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Location: LCCOMB_X40_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( // Equation(s): -// \z80_|execute_|nextM~4_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) +// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'h3233; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (!\z80_|execute_|ctl_mRead~16_combout & (\z80_|execute_|setM1~37_combout & (\z80_|execute_|setM1~55_combout & \z80_|execute_|setM1~36_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|setM1~37_combout ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|execute_|setM1~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'h4000; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|setM1~38_combout ))) + + .dataa(\z80_|execute_|setM1~38_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|nextM~3 ( +// Equation(s): +// \z80_|execute_|nextM~3_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) .dataa(gnd), .datab(\z80_|pla_decode_|Equal41~2_combout ), .datac(\z80_|execute_|ixy_d~10_combout ), .datad(\z80_|execute_|ixy_d~16_combout ), .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), + .combout(\z80_|execute_|nextM~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0003; +defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Location: LCCOMB_X40_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( // Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|nextM~4_combout ))) +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|nextM~4_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|ctl_mRead~32_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'h8A0A; +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFC0; defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( +// Location: LCCOMB_X43_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( // Equation(s): -// \z80_|execute_|ctl_mRead~37_combout = (\z80_|execute_|ctl_mRead~36_combout ) # ((\z80_|execute_|ctl_mRead~35_combout ) # ((\z80_|execute_|ctl_mRead~33_combout ) # (!\z80_|execute_|ctl_mRead~31_combout ))) +// \z80_|execute_|ctl_mRead~35_combout = ((\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (\z80_|execute_|ctl_mRead~33_combout ))) # (!\z80_|execute_|ctl_mRead~30_combout ) - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ctl_mRead~35_combout ), + .dataa(\z80_|execute_|ctl_mRead~30_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), .datac(\z80_|execute_|ctl_mRead~31_combout ), .datad(\z80_|execute_|ctl_mRead~33_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~37_combout ), + .combout(\z80_|execute_|ctl_mRead~35_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X49_Y16_N15 +// Location: FF_X43_Y17_N23 dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~37_combout ), + .d(\z80_|execute_|ctl_mRead~35_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -39563,7 +36182,7 @@ defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N22 +// Location: LCCOMB_X46_Y15_N24 cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( // Equation(s): // \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q @@ -39580,7 +36199,7 @@ defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N23 +// Location: FF_X46_Y15_N25 dffeas \z80_|memory_ifc_|wait_mrd ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), @@ -39599,7 +36218,7 @@ defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; // synopsys translate_on -// Location: FF_X50_Y16_N15 +// Location: FF_X43_Y17_N3 dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -39618,28 +36237,151 @@ defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N26 +// Location: LCCOMB_X43_Y17_N8 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( // Equation(s): // \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) .dataa(\z80_|memory_ifc_|wait_mrd~q ), .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datad(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nRD_out~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0505; +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N7 -dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( +// Location: LCCOMB_X40_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout ) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|nextM~4_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~16_combout ), + .datad(\z80_|execute_|ctl_iorw~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N7 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_iorw~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( +// Equation(s): +// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N27 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y17_N9 +dffeas \z80_|memory_ifc_|wait_iorq ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|execute_|setM1~52_combout ), + .asdata(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), @@ -39647,6 +36389,129 @@ dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y17_N13 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|wait_iorq~q ), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~3_combout ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hA800; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|fIORead~1_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFF2; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Equation(s): +// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hA080; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|fIOWrite~1_combout ), + .datab(\z80_|execute_|fIORead~2_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|fIORead~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X41_Y17_N25 +dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|setM1~52_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), .prn(vcc)); // synopsys translate_off @@ -39654,7 +36519,7 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N30 +// Location: LCCOMB_X43_Y17_N14 cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( // Equation(s): // \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q @@ -39671,7 +36536,7 @@ defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N31 +// Location: FF_X43_Y17_N15 dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), @@ -39690,7 +36555,7 @@ defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; // synopsys translate_on -// Location: FF_X50_Y16_N17 +// Location: FF_X43_Y17_N21 dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -39709,139 +36574,817 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N16 +// Location: LCCOMB_X43_Y17_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( // Equation(s): -// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & (((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|interrupts_|DFFE_inst44~q ))) # (!\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & -// (\z80_|memory_ifc_|DFFE_m1_ff3~q & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|interrupts_|DFFE_inst44~q )))) +// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|DFFE_inst44~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|DFFE_inst44~q & +// ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - .dataa(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), + .dataa(\z80_|interrupts_|DFFE_inst44~q ), + .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nRD_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFA32; +defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFC54; defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N20 +// Location: LCCOMB_X43_Y17_N18 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( // Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) +// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) .dataa(\z80_|memory_ifc_|nRD_out~1_combout ), - .datab(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|memory_ifc_|iorq~0_combout ), .datac(\z80_|execute_|fIORead~3_combout ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nRD_out~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFDDD; +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFFD5; defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N4 -cycloneive_lcell_comb \Equal2~0 ( +// Location: LCCOMB_X31_Y12_N24 +cycloneive_lcell_comb \Equal2~1 ( // Equation(s): -// \Equal2~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) +// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) - .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), .datab(\z80_|memory_ifc_|nRD_out~2_combout ), .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .datad(gnd), .cin(gnd), - .combout(\Equal2~0_combout ), + .combout(\Equal2~1_combout ), .cout()); // synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h0080; -defparam \Equal2~0 .sum_lutc_input = "datac"; +defparam \Equal2~1 .lut_mask = 16'h4040; +defparam \Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y13_N21 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N12 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~0 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram1|altsyncram_component|auto_generated|address_reg_a [0] +// \z80_|pin_control_|bus_db_pin_oe~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~0 .lut_mask = 16'hFFAA; +defparam \z80_|pin_control_|bus_db_pin_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3F33; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) + + .dataa(\z80_|execute_|fMWrite~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'h5554; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( +// Equation(s): +// \z80_|execute_|fMWrite~2_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h555F; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fMWrite~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h00EF; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~1 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~1_combout = (\z80_|execute_|ctl_bus_inc_oe~24_combout & (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|fMWrite~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .datab(\z80_|execute_|fIOWrite~5_combout ), + .datac(\z80_|execute_|fMWrite~6_combout ), + .datad(\z80_|execute_|fMWrite~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~1 .lut_mask = 16'h0002; +defparam \z80_|pin_control_|bus_db_pin_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'h135F; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y18_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|pin_control_|bus_db_pin_oe~2_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'hA2AA; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_mRead~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'h0003; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~7_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|fMWrite~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hCD00; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h0777; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|fMRead~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout )) # +// (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|fMRead~1_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h3715; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~9 ( +// Equation(s): +// \z80_|execute_|fMWrite~9_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout )) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal46~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~9 .lut_mask = 16'hCEFF; +defparam \z80_|execute_|fMWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & +// (((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fMWrite~9_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hDDD0; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|execute_|fMWrite~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout )) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datab(\z80_|execute_|fMWrite~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0808; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_state_alu~6_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & (\z80_|execute_|ctl_reg_sel_wz~5_combout & (!\z80_|execute_|fMWrite~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~5_combout ), + .datac(\z80_|execute_|fMWrite~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h0800; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~7_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~5_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|fMWrite~10 ( +// Equation(s): +// \z80_|execute_|fMWrite~10_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & +// ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~10 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & (!\z80_|execute_|fMWrite~10_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .datac(\z80_|execute_|fMWrite~10_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h0800; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2A00; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~1_combout & (\z80_|pin_control_|bus_db_pin_oe~12_combout & \z80_|execute_|ctl_inc_cy~37_combout ))) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout ))) # +// (!\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|fIOWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'hF222; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y15_N0 +cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( +// Equation(s): +// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; +defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y13_N13 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( +// Location: FF_X43_Y15_N1 +dffeas \z80_|clk_delay_|DFF_inst5 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .q(\z80_|clk_delay_|DFF_inst5~q ), .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \ExtRamWE~0 ( +// Location: LCCOMB_X43_Y15_N22 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( // Equation(s): -// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|memory_ifc_|nIORQ_out~0_combout & !\z80_|memory_ifc_|nRD_out~2_combout ))) +// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|clk_delay_|DFF_inst5~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y15_N23 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y15_N13 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y15_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datad(\z80_|memory_ifc_|iorq~0_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nIORQ_out~0_combout ))) .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datad(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h4000; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), .cin(gnd), .combout(\ExtRamWE~0_combout ), .cout()); // synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h0008; +defparam \ExtRamWE~0 .lut_mask = 16'h0020; defparam \ExtRamWE~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N10 +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [13]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0B0B; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~2_combout = (((\z80_|execute_|fMRead~35_combout ) # (\z80_|execute_|fIORead~3_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .datac(\z80_|execute_|fMRead~35_combout ), + .datad(\z80_|execute_|fIORead~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFF7; +defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pin_control_|bus_ab_pin_we~2_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T3_ff~q & +// (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h3B0A; +defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [14]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N4 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [15]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[15]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hF3F3; +defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N8 cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), .cin(gnd), .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .cout()); @@ -39850,24 +37393,41 @@ defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_m defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N8 +// Location: LCCOMB_X32_Y14_N22 cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) .dataa(gnd), .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), .cin(gnd), .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h0C00; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00C0; defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N8 +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) @@ -39884,7 +37444,7 @@ defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hDD88; defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N9 +// Location: FF_X31_Y17_N29 dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), @@ -39903,41 +37463,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N4 +// Location: LCCOMB_X31_Y18_N20 cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( // Equation(s): // \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(gnd), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [1]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [1]), .cin(gnd), .combout(\z80_|address_pins_|abus[1]~25_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hFF55; defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N8 +// Location: LCCOMB_X31_Y17_N18 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [2]))) +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [2]), .datac(gnd), - .datad(\z80_|address_latch_|abusz [2]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N9 +// Location: FF_X31_Y17_N19 dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), @@ -39956,7 +37516,7 @@ defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N16 +// Location: LCCOMB_X31_Y18_N26 cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( // Equation(s): // \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) @@ -39973,24 +37533,24 @@ defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N30 +// Location: LCCOMB_X31_Y17_N0 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) - .dataa(\z80_|address_latch_|abusz [3]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [3]), .datac(gnd), .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y11_N31 +// Location: FF_X31_Y17_N1 dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), @@ -40009,41 +37569,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y2_N22 +// Location: LCCOMB_X31_Y18_N12 cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( // Equation(s): // \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\z80_|address_pins_|DFFE_apin_latch [3]), .cin(gnd), .combout(\z80_|address_pins_|abus[3]~27_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N4 +// Location: LCCOMB_X31_Y17_N30 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) - .dataa(\z80_|address_latch_|abusz [4]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [4]), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N5 +// Location: FF_X31_Y17_N31 dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), @@ -40062,41 +37622,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y3_N22 +// Location: LCCOMB_X31_Y18_N2 cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( // Equation(s): // \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [4]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [4]), .cin(gnd), .combout(\z80_|address_pins_|abus[4]~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N12 +// Location: LCCOMB_X30_Y16_N12 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - .dataa(\z80_|address_latch_|abusz [5]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [5]), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y13_N13 +// Location: FF_X30_Y16_N13 dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), @@ -40115,41 +37675,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N10 +// Location: LCCOMB_X29_Y17_N20 cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( // Equation(s): // \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|address_pins_|DFFE_apin_latch [5]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(gnd), .cin(gnd), .combout(\z80_|address_pins_|abus[5]~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF3F3; defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y14_N6 +// Location: LCCOMB_X30_Y16_N10 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [6]), + .dataa(\z80_|address_latch_|abusz [6]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hCCAA; defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y14_N7 +// Location: FF_X30_Y16_N11 dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), @@ -40168,41 +37728,41 @@ defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N8 +// Location: LCCOMB_X31_Y18_N28 cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( // Equation(s): // \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [6]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [6]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|address_pins_|abus[6]~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N22 +// Location: LCCOMB_X30_Y16_N30 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - .dataa(\z80_|address_latch_|abusz [7]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [7]), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y13_N23 +// Location: FF_X30_Y16_N31 dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), @@ -40221,2261 +37781,289 @@ defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N24 +// Location: LCCOMB_X31_Y18_N22 cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( // Equation(s): // \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\z80_|address_pins_|DFFE_apin_latch [7]), .cin(gnd), .combout(\z80_|address_pins_|abus[7]~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF0F; defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y29_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X29_Y14_N27 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~16_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N23 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (!\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), + .dataa(\z80_|address_latch_|abusz [8]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0400; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N21 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [8]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [14] & !\z80_|address_pins_|DFFE_apin_latch [13])) +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: FF_X31_Y16_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N30 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (!\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h4000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [14] & !\z80_|address_pins_|DFFE_apin_latch [13])) +// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .combout(\z80_|address_pins_|abus[9]~17_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h00C0; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & \z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [14]), - .datad(\z80_|address_pins_|DFFE_apin_latch [13]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N16 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout & -// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEA4A; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & !\z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N20 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datab(\z80_|address_latch_|abusz [10]), .datac(gnd), - .datad(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), - .combout(\~GND~combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), .cout()); // synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y30_N2 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) - - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0028; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N21 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y30_N25 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N2 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h00FF; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N3 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N0 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [7] $ (\ula_|video_|vga_hc [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N1 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N30 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [7]))) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'hA555; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N31 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N8 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N10 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N12 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N14 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N15 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N16 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N17 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N18 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N19 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N20 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N28 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFC30; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y30_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( -// Equation(s): -// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) - - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[9]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0028; -defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N29 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N22 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [8]), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N26 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|Add4~2_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hF3C0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N27 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N2 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [0]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h1020; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y31_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|Add4~4_combout ), - .datab(\ula_|video_|vram_address[10]~2_combout ), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hB830; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y31_N29 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N4 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N5 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N6 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|Add4~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFCFC; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N7 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y20_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X30_Y13_N27 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y13_N9 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: M9K_X33_Y9_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (!\z80_|address_pins_|abus[13]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[14]~16_combout & !\z80_|address_pins_|abus[15]~17_combout ))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ExtRamWE~0_combout ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0040; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y29_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~31_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \Selector1~0 ( -// Equation(s): -// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~16_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\Selector1~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~0 .lut_mask = 16'hBA98; -defparam \Selector1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \Selector1~1 ( -// Equation(s): -// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\Selector1~0_combout ), - .cin(gnd), - .combout(\Selector1~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~1 .lut_mask = 16'hBBC0; -defparam \Selector1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \D[1]~22 ( -// Equation(s): -// \D[1]~22_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector1~1_combout ))))) - - .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .datad(\Selector1~1_combout ), - .cin(gnd), - .combout(\D[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~22 .lut_mask = 16'h5140; -defparam \D[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \D[1]~23 ( -// Equation(s): -// \D[1]~23_combout = ((\z80_|memory_ifc_|nWR_out~0_combout ) # ((\D[1]~22_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[1]~22_combout ), - .cin(gnd), - .combout(\D[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~23 .lut_mask = 16'hFFDF; -defparam \D[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \D[1]~29 ( -// Equation(s): -// \D[1]~29_combout = (\D[1]~23_combout ) # ((\Equal2~0_combout & ((\z80_|address_pins_|abus[0]~18_combout ) # (\D[1]~28_combout )))) - - .dataa(\z80_|address_pins_|abus[0]~18_combout ), - .datab(\D[1]~28_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[1]~23_combout ), - .cin(gnd), - .combout(\D[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~29 .lut_mask = 16'hFFE0; -defparam \D[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \D[1]~31 ( -// Equation(s): -// \D[1]~31_combout = ((\D[1]~29_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\D[0]~30_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\D[1]~29_combout ), - .cin(gnd), - .combout(\D[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'hF755; -defparam \D[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N6 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[1]~31_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[1]~13_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[1]~13_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[1]~13_combout ), - .datad(\D[1]~31_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N8 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T3_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hAE0C; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N22 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .datad(\z80_|execute_|fMRead~36_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFEFA; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N7 -dffeas \z80_|data_pins_|dout[1] ( +// Location: FF_X31_Y16_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .asdata(vcc), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [1]), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[1] .power_up = "low"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~12 ( +// Location: LCCOMB_X30_Y20_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( // Equation(s): -// \z80_|bus_control_|db[1]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~12 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h0203; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( -// Equation(s): -// \z80_|bus_control_|db[0]~6_combout = ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (\z80_|execute_|ctl_bus_db_oe~combout )) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFFF5; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~13 ( -// Equation(s): -// \z80_|bus_control_|db[1]~13_combout = ((\z80_|bus_control_|db[1]~12_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [1]), - .datab(\z80_|bus_control_|db[1]~12_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~13 .lut_mask = 16'h8FCF; -defparam \z80_|bus_control_|db[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~5_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hFB33; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N17 -dffeas \z80_|ir_|opcode[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[1]~13_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y15_N29 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N20 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) +// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), + .combout(\z80_|address_pins_|abus[10]~24_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFF0; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y15_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( // Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [0]))) +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [0]), + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datab(\z80_|address_latch_|abusz [11]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal36~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal36~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal36~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hAE0C; -defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y15_N27 -dffeas \z80_|decode_state_|DFFE_instCB ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), +// Location: FF_X31_Y16_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instCB~q ), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), .prn(vcc)); // synopsys translate_off -defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y15_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Location: LCCOMB_X30_Y20_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( // Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0004; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|pla_decode_|Equal50~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q ))) # (!\z80_|pla_decode_|Equal50~0_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & -// !\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal33~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0357; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mRead~9_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_mRead~9_combout & -// (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~11_combout & (\z80_|execute_|ctl_mWrite~9_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mWrite~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~11_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~3_combout & (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_bus_db_oe~6_combout & \z80_|execute_|ctl_mWrite~12_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_mWrite~14_combout ) # (((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~14_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hDCFF; -defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X50_Y16_N29 -dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~15_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N18 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q - - .dataa(gnd), + .dataa(\z80_|address_pins_|DFFE_apin_latch [11]), .datab(gnd), .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .combout(\z80_|address_pins_|abus[11]~19_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N19 -dffeas \z80_|memory_ifc_|wait_mwr ( +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) + + .dataa(\z80_|address_latch_|abusz [12]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mwr~q ), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N0 -cycloneive_lcell_comb \z80_|memory_ifc_|mwr_wr~feeder ( +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( // Equation(s): -// \z80_|memory_ifc_|mwr_wr~feeder_combout = \z80_|memory_ifc_|wait_mwr~q +// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(gnd), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mwr~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [12]), .cin(gnd), - .combout(\z80_|memory_ifc_|mwr_wr~feeder_combout ), + .combout(\z80_|address_pins_|abus[12]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|mwr_wr~feeder .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y16_N1 -dffeas \z80_|memory_ifc_|mwr_wr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|mwr_wr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|mwr_wr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y16_N4 -cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~4_combout & \z80_|memory_ifc_|iorq~0_combout )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|mwr_wr~q ), - .datac(\z80_|execute_|fIOWrite~4_combout ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nWR_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hFCCC; -defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N30 -cycloneive_lcell_comb \D[0]~30 ( -// Equation(s): -// \D[0]~30_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cin(gnd), - .combout(\D[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~30 .lut_mask = 16'hFF40; -defparam \D[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 +// Location: M9K_X33_Y11_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -42483,7 +38071,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .ena1(vcc), @@ -42491,10 +38079,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -42532,26 +38120,1177 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), - .cout()); +// Location: FF_X32_Y14_N31 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[13]~20_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hE6C4; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y16_N0 +// Location: FF_X32_Y14_N1 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0200; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: FF_X29_Y14_N5 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0C00; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \D[6]~90 ( +// Equation(s): +// \D[6]~90_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\D[6]~90_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~90 .lut_mask = 16'hCCE2; +defparam \D[6]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N16 +cycloneive_lcell_comb \D[6]~91 ( +// Equation(s): +// \D[6]~91_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~90_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~90_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~90_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[6]~90_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\D[6]~91_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~91 .lut_mask = 16'hF838; +defparam \D[6]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0020; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y24_N16 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N20 +cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [4]), + .cin(gnd), + .combout(\ula_|video_|vram_address[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N4 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N21 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y33_N19 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N0 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N1 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N26 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N27 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N28 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'hA50F; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y33_N29 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N2 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N4 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N6 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N8 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y33_N9 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N10 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y33_N11 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N12 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y33_N13 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N14 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N22 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) + + .dataa(gnd), + .datab(\ula_|video_|Add4~12_combout ), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hCCF0; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N14 +cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( +// Equation(s): +// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N23 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y33_N16 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [8]), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) + + .dataa(\ula_|video_|Add4~14_combout ), + .datab(gnd), + .datac(\ula_|video_|Add4~2_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hAAF0; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N21 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N30 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & (\ula_|video_|vga_hc [1]))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|Add4~4_combout ), + .datab(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|vram_address[10]~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N31 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) + + .dataa(gnd), + .datab(\ula_|video_|Add4~12_combout ), + .datac(gnd), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFCC; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N17 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N26 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|Add4~14_combout ) # (\ula_|video_|vga_hc [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|Add4~14_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y31_N27 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N23 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y14_N1 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) + + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -42561,16 +39300,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[6]~101_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -42624,7 +39363,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y13_N0 +// Location: M9K_X33_Y33_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(vcc), .portare(vcc), @@ -42634,16 +39373,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -42682,7 +39421,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; // synopsys translate_on -// Location: M9K_X33_Y13_N0 +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \D[6]~87 ( +// Equation(s): +// \D[6]~87_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\D[6]~87_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~87 .lut_mask = 16'hE6A2; +defparam \D[6]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y1_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portawe(vcc), .portare(vcc), @@ -42692,16 +39449,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -42740,3739 +39497,175 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; // synopsys translate_on -// Location: M9K_X33_Y17_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~81_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \Selector6~0 ( -// Equation(s): -// \Selector6~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector6~0 .lut_mask = 16'hAEA4; -defparam \Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N0 -cycloneive_lcell_comb \D[6]~70 ( -// Equation(s): -// \D[6]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector6~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\Selector6~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector6~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datad(\Selector6~0_combout ), - .cin(gnd), - .combout(\D[6]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~70 .lut_mask = 16'hBBC0; -defparam \D[6]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \D[6]~71 ( -// Equation(s): -// \D[6]~71_combout = ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\D[6]~70_combout )))) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\z80_|memory_ifc_|nRD_out~2_combout ), - .datad(\D[6]~70_combout ), - .cin(gnd), - .combout(\D[6]~71_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~71 .lut_mask = 16'hBF8F; -defparam \D[6]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G19 -cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2]}), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk )); -// synopsys translate_off -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock"; -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~77_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[3]~21_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[3]~21_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\D[3]~77_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N11 -dffeas \z80_|data_pins_|dout[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~64 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~64_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~64 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[5][4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~101_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[5][4]~64_combout & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~101_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~101 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[3][3]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~102 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~102_combout = (\ula_|zx_keyboard_|keys[3][3]~101_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~101_combout & (\ula_|zx_keyboard_|keys[3][3]~q )) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~101_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~102_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~102 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[3][3]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N3 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~102_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'hCCCF; -defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~104 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~104_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~104 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[2][3]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~135 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~135_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[2][3]~104_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[2][3]~104_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~135_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~135 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[2][3]~135 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~105_combout = (\ula_|zx_keyboard_|keys[2][3]~135_combout & (!\ula_|zx_keyboard_|keys[2][3]~103_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~135_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~135_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~105 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N17 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~105_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \D[3]~55 ( -// Equation(s): -// \D[3]~55_combout = (\z80_|address_pins_|abus[11]~21_combout & (((\z80_|address_pins_|abus[10]~22_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~21_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~22_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~21_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~q ), - .datac(\z80_|address_pins_|abus[10]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[2][3]~q ), - .cin(gnd), - .combout(\D[3]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~55 .lut_mask = 16'hB0BB; -defparam \D[3]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~21_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~95_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][3]~94_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~95 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[1][3]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~96_combout = (\ula_|zx_keyboard_|keys[1][3]~95_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][3]~95_combout & ((\ula_|zx_keyboard_|keys[1][3]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|keys[1][3]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~96_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~96 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[1][3]~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N9 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~96_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~97 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~97_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~97 .lut_mask = 16'hAAEE; -defparam \ula_|zx_keyboard_|keys[2][4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~99_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [6])))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~99_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~99 .lut_mask = 16'h0220; -defparam \ula_|zx_keyboard_|keys[0][4]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~100 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~100_combout = (\ula_|zx_keyboard_|keys[0][3]~98_combout & ((\ula_|zx_keyboard_|keys[0][4]~99_combout & (!\ula_|zx_keyboard_|keys[2][4]~97_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~99_combout & -// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][3]~98_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~99_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~100 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N31 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~100_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \D[3]~54 ( -// Equation(s): -// \D[3]~54_combout = (\z80_|address_pins_|abus[8]~20_combout & (((\z80_|address_pins_|abus[9]~19_combout )) # (!\ula_|zx_keyboard_|keys[1][3]~q ))) # (!\z80_|address_pins_|abus[8]~20_combout & (!\ula_|zx_keyboard_|keys[0][3]~q & -// ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[1][3]~q ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\z80_|address_pins_|abus[9]~19_combout ), - .cin(gnd), - .combout(\D[3]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~54 .lut_mask = 16'hAF23; -defparam \D[3]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~79_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[3][0]~79_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~136 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~136_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), - .datab(\ula_|zx_keyboard_|Selector5~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~136_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~136 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~136 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~109 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~109_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~108_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~136_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[4][3]~136_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~108_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~109_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~109 .lut_mask = 16'hEA40; -defparam \ula_|zx_keyboard_|keys[4][3]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~137 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~137_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~137_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~137 .lut_mask = 16'hFF02; -defparam \ula_|zx_keyboard_|keys[4][3]~137 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~110 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~110_combout = (\ula_|zx_keyboard_|keys[4][3]~109_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|zx_keyboard_|keys[4][3]~137_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & -// ((\ula_|zx_keyboard_|keys[4][3]~q ))))) # (!\ula_|zx_keyboard_|keys[4][3]~109_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~109_combout ), - .datab(\ula_|zx_keyboard_|keys[4][3]~137_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~110_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~110 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][3]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N19 -dffeas \ula_|zx_keyboard_|keys[4][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][3]~110_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~106 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~106_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~106 .lut_mask = 16'h00C0; -defparam \ula_|zx_keyboard_|keys[5][3]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~107 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~107_combout = (\ula_|zx_keyboard_|keys[1][4]~25_combout & ((\ula_|zx_keyboard_|keys[5][3]~106_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][3]~106_combout & ((\ula_|zx_keyboard_|keys[5][3]~q -// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|keys[5][3]~106_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~107_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~107 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][3]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y14_N17 -dffeas \ula_|zx_keyboard_|keys[5][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~107_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N26 -cycloneive_lcell_comb \D[3]~56 ( -// Equation(s): -// \D[3]~56_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][3]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[5][3]~q ), - .cin(gnd), - .combout(\D[3]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~56 .lut_mask = 16'h8ACF; -defparam \D[3]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~115 ( +cycloneive_lcell_comb \D[6]~88 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~115_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) +// \D[6]~88_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~87_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~87_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~87_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~115_combout ), + .combout(\D[6]~88_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~115 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][3]~115 .sum_lutc_input = "datac"; +defparam \D[6]~88 .lut_mask = 16'h22D8; +defparam \D[6]~88 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~116 ( +cycloneive_lcell_comb \D[6]~89 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~116_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~115_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[7][2]~32_combout & ((\ula_|ps2_keyboard_|shiftreg [2])))) +// \D[6]~89_combout = (\D[6]~87_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~88_combout )))) # (!\D[6]~87_combout & +// (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \D[6]~88_combout )))) - .dataa(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datab(\ula_|zx_keyboard_|keys[6][3]~115_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\D[6]~87_combout ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\D[6]~88_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~116_combout ), + .combout(\D[6]~89_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~116 .lut_mask = 16'hCCA0; -defparam \ula_|zx_keyboard_|keys[6][3]~116 .sum_lutc_input = "datac"; +defparam \D[6]~89 .lut_mask = 16'hC3C8; +defparam \D[6]~89 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~139 ( +cycloneive_lcell_comb \D[6]~111 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~139_combout = (((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout )) # (!\ula_|zx_keyboard_|keys[6][3]~116_combout ) +// \D[6]~111_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[6]~91_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[6]~89_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[6]~91_combout )) - .dataa(\ula_|zx_keyboard_|keys[6][3]~116_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), + .dataa(\D[6]~91_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\D[6]~89_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~139_combout ), + .combout(\D[6]~111_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~139 .lut_mask = 16'hFF7F; -defparam \ula_|zx_keyboard_|keys[6][3]~139 .sum_lutc_input = "datac"; +defparam \D[6]~111 .lut_mask = 16'hAEA2; +defparam \D[6]~111 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(gnd), +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \D[6]~86 ( +// Equation(s): +// \D[6]~86_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(gnd), + .datac(\raw_loader_in~input_o ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector13~0_combout ), + .combout(\D[6]~86_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hF2F2; -defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; +defparam \D[6]~86 .lut_mask = 16'hFAFF; +defparam \D[6]~86 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~140 ( +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \D[6]~100 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~140_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~139_combout & (\ula_|zx_keyboard_|keys[6][3]~q )) # (!\ula_|zx_keyboard_|keys[6][3]~139_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout -// ))))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) +// \D[6]~100_combout = ((\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout ))) # (!\Equal2~1_combout ) - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[6][3]~139_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), + .dataa(\Equal2~1_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[6]~111_combout ), + .datad(\D[6]~86_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~140_combout ), + .combout(\D[6]~100_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~140 .lut_mask = 16'hD0F2; -defparam \ula_|zx_keyboard_|keys[6][3]~140 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N9 -dffeas \ula_|zx_keyboard_|keys[6][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~140_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFCF0; -defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h00CC; -defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~62_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hF080; -defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; +defparam \D[6]~100 .lut_mask = 16'hFD75; +defparam \D[6]~100 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( +cycloneive_lcell_comb \D[6]~101 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & ((\ula_|zx_keyboard_|keys[7][3]~q ))) +// \D[6]~101_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [6] & \D[6]~100_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[6]~100_combout )) # (!\Equal2~1_combout ))) - .dataa(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [6]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[6]~100_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .combout(\D[6]~101_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; +defparam \D[6]~101 .lut_mask = 16'hCF05; +defparam \D[6]~101 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N5 -dffeas \ula_|zx_keyboard_|keys[7][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N16 -cycloneive_lcell_comb \D[3]~57 ( -// Equation(s): -// \D[3]~57_combout = (\ula_|zx_keyboard_|keys[6][3]~q & (\z80_|address_pins_|abus[14]~16_combout & ((\z80_|address_pins_|abus[15]~17_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~q & -// (((\z80_|address_pins_|abus[15]~17_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[6][3]~q ), - .datab(\ula_|zx_keyboard_|keys[7][3]~q ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\D[3]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~57 .lut_mask = 16'hF531; -defparam \D[3]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N16 -cycloneive_lcell_comb \D[3]~58 ( -// Equation(s): -// \D[3]~58_combout = (\D[3]~55_combout & (\D[3]~54_combout & (\D[3]~56_combout & \D[3]~57_combout ))) - - .dataa(\D[3]~55_combout ), - .datab(\D[3]~54_combout ), - .datac(\D[3]~56_combout ), - .datad(\D[3]~57_combout ), - .cin(gnd), - .combout(\D[3]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~58 .lut_mask = 16'h8000; -defparam \D[3]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y31_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hBBC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; -// synopsys translate_on - -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; -// synopsys translate_on - -// Location: M9K_X33_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~77_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N18 -cycloneive_lcell_comb \Selector3~0 ( -// Equation(s): -// \Selector3~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector3~0 .lut_mask = 16'hCEC2; -defparam \Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N12 -cycloneive_lcell_comb \Selector3~1 ( -// Equation(s): -// \Selector3~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\Selector3~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector3~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\Selector3~0_combout ), - .cin(gnd), - .combout(\Selector3~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector3~1 .lut_mask = 16'hBBC0; -defparam \Selector3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N6 -cycloneive_lcell_comb \D[3]~52 ( -// Equation(s): -// \D[3]~52_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector3~1_combout ))))) - - .dataa(\z80_|address_pins_|abus[15]~17_combout ), - .datab(\Equal2~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), - .datad(\Selector3~1_combout ), - .cin(gnd), - .combout(\D[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~52 .lut_mask = 16'h3120; -defparam \D[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N20 -cycloneive_lcell_comb \D[3]~53 ( -// Equation(s): -// \D[3]~53_combout = (\z80_|memory_ifc_|nWR_out~0_combout ) # (((\D[3]~52_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|memory_ifc_|nRD_out~2_combout )) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~52_combout ), - .cin(gnd), - .combout(\D[3]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~53 .lut_mask = 16'hFFBF; -defparam \D[3]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N10 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\D[3]~53_combout ) # ((\Equal2~0_combout & ((\z80_|address_pins_|abus[0]~18_combout ) # (\D[3]~58_combout )))) - - .dataa(\z80_|address_pins_|abus[0]~18_combout ), - .datab(\D[3]~58_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[3]~53_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'hFFE0; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N24 -cycloneive_lcell_comb \D[3]~77 ( -// Equation(s): -// \D[3]~77_combout = ((\D[3]~76_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\z80_|data_pins_|dout [3]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[0]~30_combout ), - .datad(\D[3]~76_combout ), - .cin(gnd), - .combout(\D[3]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~77 .lut_mask = 16'hBF0F; -defparam \D[3]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N0 -cycloneive_lcell_comb \ula_|always0~0 ( -// Equation(s): -// \ula_|always0~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [0])) - - .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|always0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|always0~0 .lut_mask = 16'h0808; -defparam \ula_|always0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N2 -cycloneive_lcell_comb \ula_|always0~1 ( -// Equation(s): -// \ula_|always0~1_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|always0~0_combout ), - .cin(gnd), - .combout(\ula_|always0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|always0~1 .lut_mask = 16'h2000; -defparam \ula_|always0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y15_N25 -dffeas \ula_|pcm_outl[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[3]~77_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|pcm_outl [13]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y17_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|mclk_r~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y17_N5 -dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|mclk_r~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) - - .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add0~1_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; -defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) -// \ula_|i2s_intf_|Add0~3 = CARRY((!\ula_|i2s_intf_|lrdivider [1] & !\ula_|i2s_intf_|Add0~1_cout )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~1_cout ), - .combout(\ula_|i2s_intf_|Add0~2_combout ), - .cout(\ula_|i2s_intf_|Add0~3 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add0~2_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N29 -dffeas \ula_|i2s_intf_|lrdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) -// \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) - - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~3 ), - .combout(\ula_|i2s_intf_|Add0~4_combout ), - .cout(\ula_|i2s_intf_|Add0~5 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~4_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N5 -dffeas \ula_|i2s_intf_|lrdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) -// \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~5 ), - .combout(\ula_|i2s_intf_|Add0~6_combout ), - .cout(\ula_|i2s_intf_|Add0~7 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; -defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~6_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; -defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y15_N1 -dffeas \ula_|i2s_intf_|lrdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) -// \ula_|i2s_intf_|Add0~9 = CARRY((\ula_|i2s_intf_|lrdivider [4]) # (!\ula_|i2s_intf_|Add0~7 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~7 ), - .combout(\ula_|i2s_intf_|Add0~8_combout ), - .cout(\ula_|i2s_intf_|Add0~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; -defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N25 -dffeas \ula_|i2s_intf_|lrdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) -// \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) - - .dataa(\ula_|i2s_intf_|lrdivider [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~9 ), - .combout(\ula_|i2s_intf_|Add0~10_combout ), - .cout(\ula_|i2s_intf_|Add0~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; -defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[5]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y16_N17 -dffeas \ula_|i2s_intf_|lrdivider[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) -// \ula_|i2s_intf_|Add0~13 = CARRY((!\ula_|i2s_intf_|Add0~11 ) # (!\ula_|i2s_intf_|lrdivider [6])) - - .dataa(\ula_|i2s_intf_|lrdivider [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~11 ), - .combout(\ula_|i2s_intf_|Add0~12_combout ), - .cout(\ula_|i2s_intf_|Add0~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~12_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[6]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y16_N15 -dffeas \ula_|i2s_intf_|lrdivider[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) -// \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) - - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~13 ), - .combout(\ula_|i2s_intf_|Add0~14_combout ), - .cout(\ula_|i2s_intf_|Add0~15 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; -defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; -defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y16_N1 -dffeas \ula_|i2s_intf_|lrdivider[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) -// \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [8]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add0~15 ), - .combout(\ula_|i2s_intf_|Add0~16_combout ), - .cout(\ula_|i2s_intf_|Add0~17 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add0~16_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N25 -dffeas \ula_|i2s_intf_|lrdivider[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( -// Equation(s): -// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrdivider [9]), - .cin(\ula_|i2s_intf_|Add0~17 ), - .combout(\ula_|i2s_intf_|Add0~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; -defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( -// Equation(s): -// \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~18_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; -defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N21 -dffeas \ula_|i2s_intf_|lrdivider[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrdivider [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|lrdivider [8]))) - - .dataa(\ula_|i2s_intf_|lrdivider [6]), - .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [7]), - .datad(\ula_|i2s_intf_|lrdivider [8]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0080; -defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( -// Equation(s): -// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|lrdivider [4]))) - - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(\ula_|i2s_intf_|lrdivider [3]), - .datac(\ula_|i2s_intf_|lrdivider [5]), - .datad(\ula_|i2s_intf_|lrdivider [4]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h0080; -defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( -// Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~0_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~1_combout ))) - - .dataa(\ula_|i2s_intf_|Equal0~0_combout ), - .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; -defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] -// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .cout(\ula_|i2s_intf_|bitcount[0]~6 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; -defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(\ula_|i2s_intf_|bitcount [2]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h33C3; -defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add2~7_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0033; -defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) -// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~7_cout ), - .combout(\ula_|i2s_intf_|Add2~8_combout ), - .cout(\ula_|i2s_intf_|Add2~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (\ula_|i2s_intf_|Add2~8_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|Add2~8_combout ), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h020A; -defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N25 -dffeas \ula_|i2s_intf_|bdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) -// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) - - .dataa(\ula_|i2s_intf_|bdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~9 ), - .combout(\ula_|i2s_intf_|Add2~10_combout ), - .cout(\ula_|i2s_intf_|Add2~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[8]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|Add2~10_combout ), - .datac(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h000B; -defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N13 -dffeas \ula_|i2s_intf_|bdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) -// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - - .dataa(\ula_|i2s_intf_|bdivider [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~11 ), - .combout(\ula_|i2s_intf_|Add2~12_combout ), - .cout(\ula_|i2s_intf_|Add2~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|Add2~12_combout ), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h020A; -defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N27 -dffeas \ula_|i2s_intf_|bdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~19_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(\ula_|i2s_intf_|Add2~13 ), - .combout(\ula_|i2s_intf_|Add2~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; -defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[8]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .datad(\ula_|i2s_intf_|Add2~14_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N11 -dffeas \ula_|i2s_intf_|bdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (\ula_|i2s_intf_|bdivider [4] & (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & \ula_|i2s_intf_|bdivider [2]))) - - .dataa(\ula_|i2s_intf_|bdivider [4]), - .datab(\ula_|i2s_intf_|bdivider [1]), - .datac(\ula_|i2s_intf_|bdivider [3]), - .datad(\ula_|i2s_intf_|bdivider [2]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0200; -defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[8]~1 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[8]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bitcount [4]), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(\ula_|i2s_intf_|LessThan0~0_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8]~1 .lut_mask = 16'hC400; -defparam \ula_|i2s_intf_|shiftreg[8]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[8]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .datac(\ula_|i2s_intf_|bdivider [0]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; -defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y32_N29 -dffeas \ula_|i2s_intf_|bdivider[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [0]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; -defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) - - .dataa(\ula_|i2s_intf_|bclk_r~0_combout ), - .datab(\ula_|i2s_intf_|Equal1~1_combout ), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00B8; -defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bclk_r~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N15 -dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[8]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hAFAA; -defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N1 -dffeas \ula_|i2s_intf_|bitcount[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) -// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[0]~6 ), - .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .cout(\ula_|i2s_intf_|bitcount[1]~8 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N3 -dffeas \ula_|i2s_intf_|bitcount[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) -// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[1]~8 ), - .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .cout(\ula_|i2s_intf_|bitcount[2]~10 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N5 -dffeas \ula_|i2s_intf_|bitcount[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) -// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[2]~10 ), - .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .cout(\ula_|i2s_intf_|bitcount[3]~12 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N7 -dffeas \ula_|i2s_intf_|bitcount[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [4]), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2s_intf_|bitcount[3]~12 ), - .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; -defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N9 -dffeas \ula_|i2s_intf_|bitcount[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~19_combout = (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & (\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bitcount [4]), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|Equal1~1_combout ), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h3010; -defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X23_Y34_N22 -cycloneive_io_ibuf \AUD_ADCDAT~input ( - .i(AUD_ADCDAT), - .ibar(gnd), - .o(\AUD_ADCDAT~input_o )); -// synopsys translate_off -defparam \AUD_ADCDAT~input .bus_hold = "false"; -defparam \AUD_ADCDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) - - .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [0]), - .datad(\AUD_ADCDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; -defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N3 -dffeas \ula_|i2s_intf_|shiftreg[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[8]~2 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[8]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[8]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|shiftreg[8]~1_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8]~2 .lut_mask = 16'hFAAA; -defparam \ula_|i2s_intf_|shiftreg[8]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N1 -dffeas \ula_|i2s_intf_|shiftreg[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N19 -dffeas \ula_|i2s_intf_|shiftreg[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N29 -dffeas \ula_|i2s_intf_|shiftreg[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N27 -dffeas \ula_|i2s_intf_|shiftreg[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~15_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(\ula_|i2s_intf_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0A0A; -defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N21 -dffeas \ula_|i2s_intf_|shiftreg[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~14_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N15 -dffeas \ula_|i2s_intf_|shiftreg[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~13_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [6]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N25 -dffeas \ula_|i2s_intf_|shiftreg[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~11_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [7]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N11 -dffeas \ula_|i2s_intf_|shiftreg[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~11_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [8]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N9 -dffeas \ula_|i2s_intf_|shiftreg[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~10_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [9]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N31 -dffeas \ula_|i2s_intf_|shiftreg[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~9_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(\ula_|i2s_intf_|shiftreg [10]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0A0A; -defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N13 -dffeas \ula_|i2s_intf_|shiftreg[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~8_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~7_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [11]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [11]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N23 -dffeas \ula_|i2s_intf_|shiftreg[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~7_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; -defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N21 -dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( -// Equation(s): -// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|PCM_INR [14])))) # -// (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (((\ula_|i2s_intf_|PCM_INR [14])))) - - .dataa(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|shiftreg [14]), - .cin(gnd), - .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hF870; -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N19 -dffeas \ula_|i2s_intf_|PCM_INR[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|PCM_INR [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \ula_|ula_data~0 ( -// Equation(s): -// \ula_|ula_data~0_combout = (\ula_|i2s_intf_|PCM_INL [14]) # (\ula_|i2s_intf_|PCM_INR [14]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|PCM_INR [14]), - .cin(gnd), - .combout(\ula_|ula_data~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ula_data~0 .lut_mask = 16'hFFF0; -defparam \ula_|ula_data~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N3 -dffeas \ula_|pcm_outl[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ula_data~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|pcm_outl [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) - - .dataa(\ula_|i2s_intf_|shiftreg [12]), - .datab(\ula_|pcm_outl [12]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hCACA; -defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N17 -dffeas \ula_|i2s_intf_|shiftreg[13] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [13]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) - - .dataa(\ula_|pcm_outl [13]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [13]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hB8B8; -defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N9 -dffeas \ula_|i2s_intf_|shiftreg[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( -// Equation(s): -// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) - - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N5 -dffeas \ula_|i2s_intf_|PCM_INL[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|PCM_INL [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \D[6]~72 ( -// Equation(s): -// \D[6]~72_combout = (!\z80_|address_pins_|abus[0]~18_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (!\ula_|i2s_intf_|PCM_INL [14] & !\ula_|i2s_intf_|PCM_INR [14]))) - - .dataa(\z80_|address_pins_|abus[0]~18_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|PCM_INR [14]), - .cin(gnd), - .combout(\D[6]~72_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~72 .lut_mask = 16'h0004; -defparam \D[6]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \D[6]~73 ( -// Equation(s): -// \D[6]~73_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Equal2~0_combout & ((\D[6]~72_combout ))) # (!\Equal2~0_combout & (!\D[6]~71_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\Equal2~0_combout ), - .datac(\D[6]~71_combout ), - .datad(\D[6]~72_combout ), - .cin(gnd), - .combout(\D[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~73 .lut_mask = 16'h8A02; -defparam \D[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \D[6]~74 ( -// Equation(s): -// \D[6]~74_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (((\z80_|data_pins_|dout [6])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) # (!\z80_|memory_ifc_|nWR_out~0_combout & (!\D[6]~73_combout & ((\z80_|data_pins_|dout [6]) # -// (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\D[6]~73_combout ), - .cin(gnd), - .combout(\D[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~74 .lut_mask = 16'hA2F3; -defparam \D[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 -cycloneive_lcell_comb \D[6]~81 ( -// Equation(s): -// \D[6]~81_combout = (\D[6]~74_combout ) # (!\D[0]~30_combout ) - - .dataa(\D[0]~30_combout ), - .datab(\D[6]~74_combout ), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\D[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~81 .lut_mask = 16'hDDDD; -defparam \D[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 +// Location: LCCOMB_X32_Y13_N12 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~81_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~7_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[6]~7_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~101_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & +// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[6]~7_combout ), - .datad(\D[6]~81_combout ), + .datab(\D[6]~101_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[6]~9_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N1 +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # +// ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|fIORead~3_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|fIORead~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hDC50; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|execute_|fMRead~35_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N13 dffeas \z80_|data_pins_|dout[6] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), @@ -46491,44 +39684,61 @@ defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~5 ( +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( // Equation(s): -// \z80_|bus_control_|db[6]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|db[6]~15_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~5 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[6]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~7 ( -// Equation(s): -// \z80_|bus_control_|db[6]~7_combout = ((\z80_|bus_control_|db[6]~5_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(\z80_|bus_control_|db[6]~8_combout ), .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[6]~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[6]~7_combout ), + .combout(\z80_|bus_control_|db[6]~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[6]~7 .lut_mask = 16'hDF0F; -defparam \z80_|bus_control_|db[6]~7 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'h8AFF; +defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N19 +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~9_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[6]~9_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N9 dffeas \z80_|ir_|opcode[6] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[6]~7_combout ), + .d(\z80_|ir_|opcode[6]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -46544,3371 +39754,239 @@ defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y15_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( +// Location: LCCOMB_X37_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( // Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), + .combout(\z80_|pla_decode_|Equal41~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h4400; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Location: LCCOMB_X38_Y16_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( // Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) +// \z80_|pla_decode_|Equal41~1_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [5]))) - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), + .combout(\z80_|pla_decode_|Equal41~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Location: LCCOMB_X38_Y16_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( // Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) +// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_sw_1d~8_combout ), + .dataa(\z80_|pla_decode_|Equal41~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal41~1_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .combout(\z80_|pla_decode_|Equal41~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X40_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( // Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_2d~9_combout & \z80_|execute_|ctl_sw_1d~4_combout ))) +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal41~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_1d~5_combout ), - .datac(\z80_|execute_|ctl_sw_2d~9_combout ), - .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFF08; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Location: LCCOMB_X34_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( // Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|execute_|ctl_66_oe~2_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) +// \z80_|alu_|db_high[1]~15_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'h7555; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_high [1]), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~23_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~17_combout ))) + + .dataa(\z80_|alu_|db[6]~23_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[4]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[1]~17_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[5]~25_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[1]~17_combout ), + .datac(\z80_|alu_|db[5]~25_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = (\z80_|alu_|db_high[1]~15_combout & (\z80_|alu_|db_high[1]~16_combout & ((\z80_|alu_|db_high[1]~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[1]~15_combout ), + .datab(\z80_|alu_|db_high[1]~16_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[1]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~20 ( +// Equation(s): +// \z80_|alu_|db_high[1]~20_combout = ((\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~20 .lut_mask = 16'hA8FF; +defparam \z80_|alu_|db_high[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[5]~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db[5]~25 ( +// Equation(s): +// \z80_|alu_|db[5]~25_combout = ((\z80_|alu_|db[5]~24_combout & ((\z80_|alu_|db_high[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) + + .dataa(\z80_|alu_|db_high[1]~20_combout ), + .datab(\z80_|alu_|db[7]~26_combout ), + .datac(\z80_|alu_|db[5]~24_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~25 .lut_mask = 16'hB3F3; +defparam \z80_|alu_|db[5]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N14 +cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Equation(s): +// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7733; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( -// Equation(s): -// \z80_|alu_control_|db[6]~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_flags_oe~2_combout ) # (\z80_|execute_|ctl_66_oe~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_66_oe~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFFC; -defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( -// Equation(s): -// \z80_|alu_control_|db[6]~11_combout = (\z80_|execute_|ctl_sw_1d~7_combout ) # ((\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_reg_out_lo~8_combout ) # (\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|alu_control_|db[6]~10_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFFFE; -defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~20 ( -// Equation(s): -// \z80_|alu_control_|db[2]~20_combout = (\z80_|alu_|db[2]~12_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & (\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_|db[2]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~20 .lut_mask = 16'h7530; -defparam \z80_|alu_control_|db[2]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hF4F0; -defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~21 ( -// Equation(s): -// \z80_|alu_control_|db[2]~21_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[2]~11_combout ), - .datab(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~21 .lut_mask = 16'h08CC; -defparam \z80_|alu_control_|db[2]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~22 ( -// Equation(s): -// \z80_|alu_control_|db[2]~22_combout = ((!\z80_|alu_control_|db[2]~20_combout & (\z80_|alu_control_|db[2]~21_combout & \z80_|alu_control_|db[2]~19_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[2]~20_combout ), - .datac(\z80_|alu_control_|db[2]~21_combout ), - .datad(\z80_|alu_control_|db[2]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~22 .lut_mask = 16'h7555; -defparam \z80_|alu_control_|db[2]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~10 ( -// Equation(s): -// \z80_|bus_control_|db[2]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|db[2]~22_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~10 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h0A0A; -defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~59 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~59_combout = (\ula_|zx_keyboard_|keys[5][2]~58_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][2]~58_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~59_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~59 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][2]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \ula_|zx_keyboard_|keys[5][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~59_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~133_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][2]~60_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~133 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[4][2]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~132_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~132 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][4]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~61 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~61_combout = (\ula_|zx_keyboard_|keys[4][2]~133_combout & ((\ula_|zx_keyboard_|keys[3][4]~132_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~132_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~133_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][2]~133_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~132_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~61 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N23 -dffeas \ula_|zx_keyboard_|keys[4][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~61_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N6 -cycloneive_lcell_comb \D[2]~34 ( -// Equation(s): -// \D[2]~34_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|keys[4][2]~q ), - .cin(gnd), - .combout(\D[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~34 .lut_mask = 16'h8CAF; -defparam \D[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h000C; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~51_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N21 -dffeas \ula_|zx_keyboard_|keys[3][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~55_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~55 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[1][4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~56_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|Equal0~2_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h3000; -defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~57_combout = (\ula_|zx_keyboard_|keys[1][4]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~56_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~56_combout & ((\ula_|zx_keyboard_|keys[2][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~55_combout & (((\ula_|zx_keyboard_|keys[2][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][4]~55_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~57_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~57 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[2][2]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \ula_|zx_keyboard_|keys[2][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~57_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \D[2]~33 ( -// Equation(s): -// \D[2]~33_combout = (\z80_|address_pins_|abus[10]~22_combout & (((\z80_|address_pins_|abus[11]~21_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) # (!\z80_|address_pins_|abus[10]~22_combout & (!\ula_|zx_keyboard_|keys[2][2]~q & -// ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\z80_|address_pins_|abus[10]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[3][2]~q ), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\z80_|address_pins_|abus[11]~21_combout ), - .cin(gnd), - .combout(\D[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~33 .lut_mask = 16'hAF23; -defparam \D[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~48 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~48_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[6][4]~21_combout & \ula_|zx_keyboard_|keys[6][4]~47_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~48 .lut_mask = 16'h4400; -defparam \ula_|zx_keyboard_|keys[1][2]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[1][2]~48_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][2]~48_combout & (\ula_|zx_keyboard_|keys[1][2]~q )) - - .dataa(\ula_|zx_keyboard_|keys[1][2]~48_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h0303; -defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & (\ula_|zx_keyboard_|keys[0][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N1 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N26 -cycloneive_lcell_comb \D[2]~32 ( -// Equation(s): -// \D[2]~32_combout = (\z80_|address_pins_|abus[8]~20_combout & (((\z80_|address_pins_|abus[9]~19_combout )) # (!\ula_|zx_keyboard_|keys[1][2]~q ))) # (!\z80_|address_pins_|abus[8]~20_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & -// ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[1][2]~q ), - .datac(\z80_|address_pins_|abus[9]~19_combout ), - .datad(\ula_|zx_keyboard_|keys[0][2]~q ), - .cin(gnd), - .combout(\D[2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~32 .lut_mask = 16'hA2F3; -defparam \D[2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~63_combout = (\ula_|zx_keyboard_|keys[7][2]~62_combout & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~63 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~65_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~63_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~64_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[7][2]~63_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'hF800; -defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (\ula_|zx_keyboard_|keys[7][2]~65_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~67_combout = (\ula_|zx_keyboard_|keys[7][2]~66_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~66_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][2]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~67 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][2]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N29 -dffeas \ula_|zx_keyboard_|keys[7][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~67_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~68 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~68_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~68_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~68 .lut_mask = 16'hF3F0; -defparam \ula_|zx_keyboard_|keys[5][0]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~70_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~69_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~71_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & ((\ula_|zx_keyboard_|keys[6][2]~70_combout & (!\ula_|zx_keyboard_|keys[5][0]~68_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~70_combout & -// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~41_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~68_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~71 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][2]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N29 -dffeas \ula_|zx_keyboard_|keys[6][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~71_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N30 -cycloneive_lcell_comb \D[2]~35 ( -// Equation(s): -// \D[2]~35_combout = (\ula_|zx_keyboard_|keys[7][2]~q & (\z80_|address_pins_|abus[15]~17_combout & ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~q & -// (((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~q ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(\z80_|address_pins_|abus[14]~16_combout ), - .cin(gnd), - .combout(\D[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~35 .lut_mask = 16'hDD0D; -defparam \D[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \D[2]~36 ( -// Equation(s): -// \D[2]~36_combout = (\D[2]~34_combout & (\D[2]~33_combout & (\D[2]~32_combout & \D[2]~35_combout ))) - - .dataa(\D[2]~34_combout ), - .datab(\D[2]~33_combout ), - .datac(\D[2]~32_combout ), - .datad(\D[2]~35_combout ), - .cin(gnd), - .combout(\D[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~36 .lut_mask = 16'h8000; -defparam \D[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \D[2]~83 ( -// Equation(s): -// \D[2]~83_combout = (\Equal2~0_combout & ((\D[2]~36_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) - - .dataa(\D[2]~36_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[2]~83_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~83 .lut_mask = 16'hFB00; -defparam \D[2]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hF4A4; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y23_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .lut_mask = 16'hEC64; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; -// synopsys translate_on - -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~40_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \Selector0~0 ( -// Equation(s): -// \Selector0~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .cin(gnd), - .combout(\Selector0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector0~0 .lut_mask = 16'hCEC2; -defparam \Selector0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \Selector0~1 ( -// Equation(s): -// \Selector0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\Selector0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector0~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datac(\Selector0~0_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\Selector0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector0~1 .lut_mask = 16'hDAD0; -defparam \Selector0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N30 -cycloneive_lcell_comb \D[2]~37 ( -// Equation(s): -// \D[2]~37_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector0~1_combout ))))) - - .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), - .datad(\Selector0~1_combout ), - .cin(gnd), - .combout(\D[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~37 .lut_mask = 16'h5140; -defparam \D[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \D[2]~38 ( -// Equation(s): -// \D[2]~38_combout = (((\D[2]~37_combout ) # (\z80_|memory_ifc_|nWR_out~0_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[2]~37_combout ), - .datad(\z80_|memory_ifc_|nWR_out~0_combout ), - .cin(gnd), - .combout(\D[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~38 .lut_mask = 16'hFFF7; -defparam \D[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \D[2]~39 ( -// Equation(s): -// \D[2]~39_combout = (\D[2]~83_combout & (((\z80_|data_pins_|dout [2])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) # (!\D[2]~83_combout & (\D[2]~38_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) - - .dataa(\D[2]~83_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\D[2]~38_combout ), - .cin(gnd), - .combout(\D[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~39 .lut_mask = 16'hF3A2; -defparam \D[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \D[2]~40 ( -// Equation(s): -// \D[2]~40_combout = (\D[2]~39_combout ) # (!\D[0]~30_combout ) - - .dataa(\D[2]~39_combout ), - .datab(gnd), - .datac(\D[0]~30_combout ), - .datad(gnd), - .cin(gnd), - .combout(\D[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~40 .lut_mask = 16'hAFAF; -defparam \D[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[2]~40_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[2]~11_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~11_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\D[2]~40_combout ), - .datad(\z80_|bus_control_|db[2]~11_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N31 -dffeas \z80_|data_pins_|dout[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~11 ( -// Equation(s): -// \z80_|bus_control_|db[2]~11_combout = ((\z80_|bus_control_|db[2]~10_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[2]~10_combout ), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~11 .lut_mask = 16'hB3BB; -defparam \z80_|bus_control_|db[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N31 -dffeas \z80_|ir_|opcode[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[2]~11_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00AA; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|pla_decode_|Equal3~2_combout & (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal3~2_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X51_Y12_N3 -dffeas \z80_|decode_state_|DFFE_instIY1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_inst4~q )) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0404; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [6] & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (!\z80_|execute_|ctl_bus_db_oe~2_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h33FF; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_bus_db_oe~4_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X44_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & ((\z80_|execute_|ctl_bus_db_oe~3_combout ) # ((\z80_|execute_|ctl_bus_db_oe~5_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), .datad(\z80_|execute_|ctl_sw_1d~6_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .combout(\z80_|sw1_|db_down[5]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hEFCC; +defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y13_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h2080; -defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~84 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~84_combout = (\ula_|zx_keyboard_|keys[5][0]~83_combout & (!\ula_|zx_keyboard_|keys[5][0]~68_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~83_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[5][0]~68_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~84 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[5][0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N3 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~84_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'hFF50; -defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'h0160; -defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~87_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~85_combout & (!\ula_|zx_keyboard_|keys[4][0]~86_combout )) # (!\ula_|zx_keyboard_|keys[4][0]~85_combout & -// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~87 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N21 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~87_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N14 -cycloneive_lcell_comb \D[0]~45 ( -// Equation(s): -// \D[0]~45_combout = (\ula_|zx_keyboard_|keys[5][0]~q & (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~q ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[4][0]~q ), - .cin(gnd), - .combout(\D[0]~45_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~45 .lut_mask = 16'hC4F5; -defparam \D[0]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~81_combout = (\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][0]~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|zx_keyboard_|released~q )))) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & (((\ula_|zx_keyboard_|keys[2][0]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~81 .lut_mask = 16'hF074; -defparam \ula_|zx_keyboard_|keys[2][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N21 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~81_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~80_combout = (\ula_|zx_keyboard_|keys[3][0]~79_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][0]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][0]~79_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~80 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N31 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N22 -cycloneive_lcell_comb \D[0]~44 ( -// Equation(s): -// \D[0]~44_combout = (\ula_|zx_keyboard_|keys[2][0]~q & (\z80_|address_pins_|abus[10]~22_combout & ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\ula_|zx_keyboard_|keys[2][0]~q & -// (((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[2][0]~q ), - .datab(\z80_|address_pins_|abus[10]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\z80_|address_pins_|abus[11]~21_combout ), - .cin(gnd), - .combout(\D[0]~44_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~44 .lut_mask = 16'hDD0D; -defparam \D[0]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~134 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~134_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[3][0]~79_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~134_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~134 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[7][0]~134 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h000F; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|WideOr16~3_combout & (\ula_|zx_keyboard_|keys[5][4]~64_combout & !\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|WideOr16~3_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~64_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & ((\ula_|zx_keyboard_|keys[7][0]~134_combout ) # (\ula_|zx_keyboard_|keys[7][0]~88_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[7][0]~134_combout ), - .datac(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'hA800; -defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~90 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~90_combout = (\ula_|zx_keyboard_|keys[7][0]~89_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~89_combout & ((\ula_|zx_keyboard_|keys[7][0]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~90_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~90 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[7][0]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N31 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~90_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0C0C; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|shifted~1_combout & \ula_|zx_keyboard_|keys[6][0]~91_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datac(\ula_|zx_keyboard_|shifted~1_combout ), - .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~93_combout = (\ula_|zx_keyboard_|keys[6][0]~92_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][0]~92_combout & (\ula_|zx_keyboard_|keys[6][0]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~93 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N15 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~93_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \D[0]~46 ( -// Equation(s): -// \D[0]~46_combout = (\ula_|zx_keyboard_|keys[7][0]~q & (\z80_|address_pins_|abus[15]~17_combout & ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][0]~q )))) # (!\ula_|zx_keyboard_|keys[7][0]~q & -// ((\z80_|address_pins_|abus[14]~16_combout ) # ((!\ula_|zx_keyboard_|keys[6][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~q ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\z80_|address_pins_|abus[15]~17_combout ), - .cin(gnd), - .combout(\D[0]~46_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~46 .lut_mask = 16'hCF45; -defparam \D[0]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg -// [1] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8180; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~77_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~77 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~74_combout = (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~74 .lut_mask = 16'h8888; -defparam \ula_|zx_keyboard_|keys[4][3]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// ((\ula_|ps2_keyboard_|shiftreg [2]))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0510; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~75_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~21_combout )) # (!\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|keys[6][4]~21_combout ), - .datac(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~75 .lut_mask = 16'h0F77; -defparam \ula_|zx_keyboard_|keys~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~76_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~74_combout & !\ula_|zx_keyboard_|keys~75_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~74_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|keys~75_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~76 .lut_mask = 16'h30B0; -defparam \ula_|zx_keyboard_|keys[0][0]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~78 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~78_combout = (\ula_|zx_keyboard_|keys~77_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~77_combout & ((\ula_|zx_keyboard_|keys[0][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[0][0]~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys~77_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~76_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~78_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~78 .lut_mask = 16'hD1F0; -defparam \ula_|zx_keyboard_|keys[0][0]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N7 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~78_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~25_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~73 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~73_combout = (\ula_|zx_keyboard_|keys[1][0]~72_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~72_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~73_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~73 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[1][0]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y14_N11 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~73_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N24 -cycloneive_lcell_comb \D[0]~43 ( -// Equation(s): -// \D[0]~43_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~20_combout & ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & -// (((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), - .datab(\z80_|address_pins_|abus[8]~20_combout ), - .datac(\z80_|address_pins_|abus[9]~19_combout ), - .datad(\ula_|zx_keyboard_|keys[1][0]~q ), - .cin(gnd), - .combout(\D[0]~43_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~43 .lut_mask = 16'hD0DD; -defparam \D[0]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \D[0]~47 ( -// Equation(s): -// \D[0]~47_combout = (\D[0]~45_combout & (\D[0]~44_combout & (\D[0]~46_combout & \D[0]~43_combout ))) - - .dataa(\D[0]~45_combout ), - .datab(\D[0]~44_combout ), - .datac(\D[0]~46_combout ), - .datad(\D[0]~43_combout ), - .cin(gnd), - .combout(\D[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~47 .lut_mask = 16'h8000; -defparam \D[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y13_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .lut_mask = 16'hF588; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~49_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \Selector2~0 ( -// Equation(s): -// \Selector2~0_combout = (\z80_|address_pins_|abus[14]~16_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector2~0 .lut_mask = 16'hBA98; -defparam \Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \Selector2~1 ( -// Equation(s): -// \Selector2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector2~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\Selector2~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector2~0_combout )))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datad(\Selector2~0_combout ), - .cin(gnd), - .combout(\Selector2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector2~1 .lut_mask = 16'hF388; -defparam \Selector2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \D[0]~41 ( -// Equation(s): -// \D[0]~41_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector2~1_combout ))))) - - .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|abus[15]~17_combout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), - .datad(\Selector2~1_combout ), - .cin(gnd), - .combout(\D[0]~41_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~41 .lut_mask = 16'h5140; -defparam \D[0]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \D[0]~42 ( -// Equation(s): -// \D[0]~42_combout = ((\z80_|memory_ifc_|nWR_out~0_combout ) # ((\D[0]~41_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) # (!\z80_|memory_ifc_|nRD_out~2_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[0]~41_combout ), - .cin(gnd), - .combout(\D[0]~42_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~42 .lut_mask = 16'hFFDF; -defparam \D[0]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N18 -cycloneive_lcell_comb \D[0]~48 ( -// Equation(s): -// \D[0]~48_combout = (\D[0]~42_combout ) # ((\Equal2~0_combout & ((\D[0]~47_combout ) # (\z80_|address_pins_|abus[0]~18_combout )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|address_pins_|abus[0]~18_combout ), - .datac(\D[0]~42_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~48 .lut_mask = 16'hFEF0; -defparam \D[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \D[0]~49 ( -// Equation(s): -// \D[0]~49_combout = ((\D[0]~48_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\D[0]~30_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\D[0]~48_combout ), - .cin(gnd), - .combout(\D[0]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~49 .lut_mask = 16'hF755; -defparam \D[0]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[0]~49_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[0]~15_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[0]~15_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[0]~49_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~15_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N15 -dffeas \z80_|data_pins_|dout[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~14 ( -// Equation(s): -// \z80_|bus_control_|db[0]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(gnd), - .datac(\z80_|data_pins_|dout [0]), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~14 .lut_mask = 16'hF500; -defparam \z80_|bus_control_|db[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~15 ( -// Equation(s): -// \z80_|bus_control_|db[0]~15_combout = ((\z80_|bus_control_|db[0]~14_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~14_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~15 .lut_mask = 16'hCF4F; -defparam \z80_|bus_control_|db[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N1 -dffeas \z80_|ir_|opcode[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[0]~15_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y15_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hAB00; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mWrite~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # -// (!\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~4_combout & (\z80_|execute_|setM1~56_combout & \z80_|execute_|ctl_sw_2u~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~4_combout ), - .datac(\z80_|execute_|setM1~56_combout ), - .datad(\z80_|execute_|ctl_sw_2u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((\z80_|execute_|ctl_sw_2u~5_combout & !\z80_|execute_|ctl_reg_gp_sel~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~5_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h3B00; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N8 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[5]~1_combout = (\z80_|bus_control_|db[5]~17_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|bus_control_|db[5]~17_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|execute_|ctl_sw_1d~6_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[5]~1 .lut_mask = 16'hFBAA; -defparam \z80_|sw1_|db_down[5]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N0 +// Location: LCCOMB_X36_Y11_N22 cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( // Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[5]~29_combout ) # ((\z80_|alu_|db_high[1]~7_combout & \z80_|execute_|ctl_flags_alu~16_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (\z80_|alu_|db_high[1]~7_combout & ((\z80_|execute_|ctl_flags_alu~16_combout )))) +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|alu_control_|db[5]~15_combout +// & (\z80_|alu_|db_high[1]~20_combout & ((\z80_|execute_|ctl_flags_alu~15_combout )))) - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_|db_high[1]~7_combout ), - .datac(\z80_|alu_control_|db[5]~29_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .dataa(\z80_|alu_control_|db[5]~15_combout ), + .datab(\z80_|alu_|db_high[1]~20_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), .cin(gnd), .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), .cout()); @@ -49917,7 +39995,7 @@ defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y15_N1 +// Location: FF_X36_Y11_N23 dffeas \z80_|alu_flags_|flags_yf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), @@ -49936,133 +40014,76 @@ defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; defparam \z80_|alu_flags_|flags_yf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~27 ( +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( // Equation(s): -// \z80_|alu_control_|db[5]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) +// \z80_|alu_control_|db[5]~13_combout = (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|flags_yf~q & (!\z80_|execute_|ctl_flags_oe~2_combout & +// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .dataa(\z80_|alu_flags_|flags_yf~q ), .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|flags_yf~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|out[6]~2_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~27_combout ), + .combout(\z80_|alu_control_|db[5]~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~27 .lut_mask = 16'hFC54; -defparam \z80_|alu_control_|db[5]~27 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hAF8C; +defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~28 ( +// Location: LCCOMB_X34_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( // Equation(s): -// \z80_|alu_control_|db[5]~28_combout = (\z80_|sw1_|db_down[5]~1_combout & (\z80_|alu_control_|db[5]~27_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) +// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|sw1_|db_down[5]~1_combout ), + .dataa(\z80_|sw1_|db_down[5]~0_combout ), + .datab(\z80_|alu_control_|db[5]~13_combout ), .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datad(\z80_|alu_control_|db[5]~27_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~28_combout ), + .combout(\z80_|alu_control_|db[5]~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~28 .lut_mask = 16'hC400; -defparam \z80_|alu_control_|db[5]~28 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; +defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~29 ( +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( // Equation(s): -// \z80_|alu_control_|db[5]~29_combout = ((\z80_|alu_control_|db[5]~28_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) +// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~25_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(\z80_|alu_control_|db[5]~28_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_|db[5]~24_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .dataa(\z80_|alu_control_|db[6]~11_combout ), + .datab(\z80_|alu_|db[5]~25_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[5]~14_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~29_combout ), + .combout(\z80_|alu_control_|db[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~29 .lut_mask = 16'hB3BB; -defparam \z80_|alu_control_|db[5]~29 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hDF55; +defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N28 -cycloneive_lcell_comb \D[5]~68 ( +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \D[0]~107 ( // Equation(s): -// \D[5]~68_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) +// \D[0]~107_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout ))) - .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), .cin(gnd), - .combout(\D[5]~68_combout ), + .combout(\D[0]~107_combout ), .cout()); // synopsys translate_off -defparam \D[5]~68 .lut_mask = 16'h0040; -defparam \D[5]~68 .sum_lutc_input = "datac"; +defparam \D[0]~107 .lut_mask = 16'hFF40; +defparam \D[0]~107 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y11_N0 +// Location: M9K_X22_Y6_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -50070,7 +40091,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), .ena1(vcc), @@ -50078,10 +40099,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50119,7 +40140,7 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y30_N0 +// Location: M9K_X22_Y9_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -50127,7 +40148,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), .ena1(vcc), @@ -50135,10 +40156,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50176,7 +40197,7 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; // synopsys translate_on -// Location: M9K_X33_Y32_N0 +// Location: M9K_X22_Y7_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -50184,7 +40205,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .ena1(vcc), @@ -50192,10 +40213,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50233,103 +40254,102 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Location: LCCOMB_X29_Y10_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hFC22; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hAFC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(vcc), +// Location: M9K_X33_Y23_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y24_N0 +// Location: LCCOMB_X29_Y10_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -50339,16 +40359,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -50402,7 +40422,65 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y6_N0 +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -50412,16 +40490,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -50460,7 +40538,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: M9K_X33_Y23_N0 +// Location: M9K_X33_Y29_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), .portare(vcc), @@ -50470,16 +40548,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~80_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[5]~99_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -50532,104 +40610,104 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N6 +// Location: LCCOMB_X29_Y10_N0 cycloneive_lcell_comb \Mux2~0 ( // Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) +// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .cin(gnd), .combout(\Mux2~0_combout ), .cout()); // synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hCEC2; +defparam \Mux2~0 .lut_mask = 16'hBA98; defparam \Mux2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N12 +// Location: LCCOMB_X29_Y10_N2 cycloneive_lcell_comb \Mux2~1 ( // Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # (!\Mux2~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) +// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), .datad(\Mux2~0_combout ), .cin(gnd), .combout(\Mux2~1_combout ), .cout()); // synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hF588; +defparam \Mux2~1 .lut_mask = 16'hBBC0; defparam \Mux2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N2 -cycloneive_lcell_comb \D[5]~88 ( +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \D[5]~110 ( // Equation(s): -// \D[5]~88_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux2~1_combout ))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )))) +// \D[5]~110_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), .datad(\Mux2~1_combout ), .cin(gnd), - .combout(\D[5]~88_combout ), + .combout(\D[5]~110_combout ), .cout()); // synopsys translate_off -defparam \D[5]~88 .lut_mask = 16'hBA8A; -defparam \D[5]~88 .sum_lutc_input = "datac"; +defparam \D[5]~110 .lut_mask = 16'hAEA2; +defparam \D[5]~110 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N10 -cycloneive_lcell_comb \D[5]~69 ( +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \D[5]~85 ( // Equation(s): -// \D[5]~69_combout = (\D[5]~68_combout & (\D[5]~88_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~68_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) +// \D[5]~85_combout = (\D[5]~84_combout & (\D[5]~110_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout ))) - .dataa(\D[5]~68_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .dataa(\D[5]~84_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), .datac(\z80_|data_pins_|dout [5]), - .datad(\D[5]~88_combout ), + .datad(\D[5]~110_combout ), .cin(gnd), - .combout(\D[5]~69_combout ), + .combout(\D[5]~85_combout ), .cout()); // synopsys translate_off -defparam \D[5]~69 .lut_mask = 16'hF351; -defparam \D[5]~69 .sum_lutc_input = "datac"; +defparam \D[5]~85 .lut_mask = 16'hF351; +defparam \D[5]~85 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N14 -cycloneive_lcell_comb \D[5]~80 ( +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \D[5]~99 ( // Equation(s): -// \D[5]~80_combout = (\D[5]~69_combout ) # (!\D[0]~30_combout ) +// \D[5]~99_combout = (\D[5]~85_combout ) # (!\D[0]~107_combout ) - .dataa(gnd), + .dataa(\D[0]~107_combout ), .datab(gnd), - .datac(\D[0]~30_combout ), - .datad(\D[5]~69_combout ), + .datac(gnd), + .datad(\D[5]~85_combout ), .cin(gnd), - .combout(\D[5]~80_combout ), + .combout(\D[5]~99_combout ), .cout()); // synopsys translate_off -defparam \D[5]~80 .lut_mask = 16'hFF0F; -defparam \D[5]~80 .sum_lutc_input = "datac"; +defparam \D[5]~99 .lut_mask = 16'hFF55; +defparam \D[5]~99 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N22 +// Location: LCCOMB_X32_Y13_N14 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[5]~80_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~17_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[5]~17_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[5]~15_combout ) # ((\D[5]~99_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[5]~99_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[5]~17_combout ), - .datad(\D[5]~80_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[5]~99_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), .cout()); @@ -50638,7 +40716,7 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N23 +// Location: FF_X32_Y13_N15 dffeas \z80_|data_pins_|dout[5] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), @@ -50657,49 +40735,49 @@ defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~16 ( +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( // Equation(s): -// \z80_|bus_control_|db[5]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|bus_control_|db[0]~4_combout ), - .datab(\z80_|data_pins_|dout [5]), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [5]), + .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~16_combout ), + .combout(\z80_|bus_control_|db[5]~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~16 .lut_mask = 16'h88AA; -defparam \z80_|bus_control_|db[5]~16 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF300; +defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~17 ( +// Location: LCCOMB_X34_Y10_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( // Equation(s): -// \z80_|bus_control_|db[5]~17_combout = ((\z80_|bus_control_|db[5]~16_combout & ((\z80_|alu_control_|db[5]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|alu_control_|db[5]~29_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[5]~16_combout ), + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|alu_control_|db[5]~15_combout ), + .datad(\z80_|bus_control_|db[5]~14_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~17_combout ), + .combout(\z80_|bus_control_|db[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~17 .lut_mask = 16'hDF0F; -defparam \z80_|bus_control_|db[5]~17 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hF755; +defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N3 +// Location: FF_X34_Y10_N13 dffeas \z80_|ir_|opcode[5] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[5]~17_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|bus_control_|db[5]~15_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), @@ -50710,642 +40788,513 @@ defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X46_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( +// Location: LCCOMB_X37_Y15_N20 +cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( // Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [5])) +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|ir_|opcode [5] & +// ((\z80_|pla_decode_|Equal3~2_combout )))) - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3350; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N21 +dffeas \z80_|decode_state_|DFFE_inst4 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_inst4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N4 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Equation(s): +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), + .combout(\z80_|decode_state_|use_ixiy~combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h2020; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X45_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Location: LCCOMB_X34_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( // Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) +// \z80_|execute_|ctl_mRead~23_combout = (!\z80_|decode_state_|use_ixiy~combout & (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sel_wz~7_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~20_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( -// Equation(s): -// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|ctl_ir_we~12_combout ) # (((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|fMWrite~1_combout )) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|fMWrite~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hCFEF; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|fMRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .datab(\z80_|execute_|fMRead~15_combout ), - .datac(\z80_|execute_|fMRead~11_combout ), - .datad(\z80_|execute_|fMRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hAAEF; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( -// Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ctl_mRead~16_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|fMRead~27_combout ) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|fMRead~27_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'h0F8F; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X51_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( -// Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|execute_|ctl_ir_we~5_combout ), - .datac(\z80_|ir_|opcode [6]), + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), .datad(\z80_|pla_decode_|Equal33~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), + .combout(\z80_|execute_|ctl_mRead~23_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hC800; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( -// Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|fMRead~30_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout ) # (\z80_|execute_|ctl_ir_we~9_combout )))) - - .dataa(\z80_|execute_|fMRead~30_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( -// Equation(s): -// \z80_|execute_|fMRead~29_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|execute_|nextM~6_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|nextM~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( -// Equation(s): -// \z80_|execute_|fMRead~32_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( -// Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~29_combout ) # ((\z80_|execute_|fMRead~32_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ))) - - .dataa(\z80_|execute_|fMRead~31_combout ), - .datab(\z80_|execute_|fMRead~29_combout ), - .datac(\z80_|execute_|fMRead~32_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( -// Equation(s): -// \z80_|execute_|fMRead~37_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~17_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h00A8; -defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y17_N12 +// Location: LCCOMB_X39_Y18_N16 cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( // Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|ctl_mRead~17_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )))) # -// (!\z80_|execute_|ctl_alu_shift_oe~14_combout & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) +// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMWrite~3_combout )) - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|execute_|fMWrite~3_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~34_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFBFF; defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Location: LCCOMB_X41_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( // Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|fMRead~37_combout ) # (!\z80_|execute_|fMRead~34_combout ))) +// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) - .dataa(\z80_|execute_|fMRead~28_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~37_combout ), - .datad(\z80_|execute_|fMRead~34_combout ), + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), + .combout(\z80_|execute_|fMRead~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Location: LCCOMB_X37_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( // Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) +// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), + .combout(\z80_|execute_|fMRead~29_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC800; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Location: LCCOMB_X37_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( // Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~17_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_mRead~32_combout ))) +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) - .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|fMRead~29_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .datab(\z80_|execute_|fMRead~31_combout ), + .datac(\z80_|execute_|fMRead~30_combout ), + .datad(\z80_|execute_|fMRead~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~53_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datab(\z80_|execute_|ctl_inc_cy~77_combout ), + .datac(\z80_|execute_|ctl_inc_cy~53_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_mRead~23_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~23_combout ), .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), + .combout(\z80_|execute_|fMRead~14_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( -// Equation(s): -// \z80_|execute_|fMRead~20_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|fMRead~19_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|fMWrite~3_combout ), - .datad(\z80_|execute_|fMRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h0F0E; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N22 +// Location: LCCOMB_X39_Y18_N18 cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( // Equation(s): -// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~7_combout & !\z80_|pla_decode_|Equal6~1_combout ))) +// \z80_|execute_|fMRead~10_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0002; +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0100; defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Location: LCCOMB_X39_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( // Equation(s): -// \z80_|execute_|fMRead~17_combout = (((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~32_combout )) # (!\z80_|execute_|pc_inc_hold~18_combout )) # (!\z80_|execute_|nextM~4_combout ) +// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|pc_inc_hold~28_combout )) - .dataa(\z80_|execute_|nextM~4_combout ), - .datab(\z80_|execute_|pc_inc_hold~18_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|nextM~3_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), + .combout(\z80_|execute_|fMRead~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Location: LCCOMB_X39_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( // Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~17_combout )) # (!\z80_|execute_|fMRead~10_combout ))) - - .dataa(\z80_|execute_|fMRead~10_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( -// Equation(s): -// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~18_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|fMRead~21_combout ))) +// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|fMRead~10_combout ))) .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~21_combout ), - .datac(\z80_|execute_|fMRead~20_combout ), - .datad(\z80_|execute_|fMRead~18_combout ), + .datab(\z80_|execute_|fMRead~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|fMRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hAAA2; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fMRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_mRead~6_combout )))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|fMWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h00FE; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|fMRead~14_combout ), + .datab(\z80_|execute_|fMRead~11_combout ), + .datac(\z80_|execute_|fMRead~13_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Equation(s): +// \z80_|execute_|fMRead~20_combout = (((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~19_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datab(\z80_|execute_|fMRead~19_combout ), + .datac(\z80_|execute_|fMRead~15_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~48 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~48_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~48 .lut_mask = 16'hE0C0; +defparam \z80_|execute_|pc_inc_hold~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( +// Equation(s): +// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_mRead~18_combout & +// ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_mRead~18_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFAC8; defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y14_N8 +// Location: LCCOMB_X38_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|fMRead~2_combout ))) + + .dataa(\z80_|execute_|fMRead~2_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|fMRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N10 cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( // Equation(s): -// \z80_|execute_|fMRead~23_combout = (((\z80_|execute_|fMRead~22_combout ) # (!\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) +// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|pc_inc_hold~48_combout ) # ((\z80_|execute_|fMRead~22_combout ) # (\z80_|execute_|fMRead~21_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|pc_inc_hold~48_combout ), .datac(\z80_|execute_|fMRead~22_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), + .datad(\z80_|execute_|fMRead~21_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~23_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hFFFD; defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X48_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_mRead~38_combout ) # ((!\z80_|execute_|fMRead~5_combout ) # (!\z80_|execute_|fMRead~4_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|fMRead~4_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( -// Equation(s): -// \z80_|execute_|fMRead~25_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (((\z80_|execute_|ctl_mRead~20_combout ) # (\z80_|execute_|ctl_mRead~19_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (\z80_|execute_|ctl_ir_we~4_combout & -// ((\z80_|execute_|ctl_mRead~20_combout ) # (\z80_|execute_|ctl_mRead~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~39_combout = (\z80_|execute_|ixy_d~4_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'hF800; -defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y14_N2 +// Location: LCCOMB_X36_Y12_N8 cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( // Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout ))) +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - .dataa(\z80_|execute_|fMRead~24_combout ), - .datab(\z80_|execute_|fMRead~25_combout ), - .datac(\z80_|execute_|pc_inc_hold~39_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hCCEC; defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( +// Location: LCCOMB_X38_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( // Equation(s): -// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~16_combout ) # ((\z80_|execute_|fMRead~35_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~26_combout ))) +// \z80_|execute_|fMRead~25_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|fMRead~24_combout ) - .dataa(\z80_|execute_|fMRead~16_combout ), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|execute_|fMRead~23_combout ), - .datad(\z80_|execute_|fMRead~26_combout ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|fMRead~24_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~36_combout ), + .combout(\z80_|execute_|fMRead~25_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'h2F0F; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X44_Y13_N28 +// Location: LCCOMB_X37_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~26_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|execute_|fMRead~3_combout ) + + .dataa(\z80_|execute_|fMRead~26_combout ), + .datab(\z80_|execute_|fMRead~3_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|fMRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~27_combout ))) + + .dataa(\z80_|execute_|fMRead~32_combout ), + .datab(\z80_|execute_|fMRead~20_combout ), + .datac(\z80_|execute_|fMRead~23_combout ), + .datad(\z80_|execute_|fMRead~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Equation(s): +// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|fMRead~0_combout ))) + + .dataa(\z80_|execute_|fMRead~34_combout ), + .datab(\z80_|execute_|fMRead~33_combout ), + .datac(\z80_|execute_|fMRead~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N30 cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( // Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~36_combout & \z80_|sequencer_|DFFE_T2_ff~q )) +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q )) - .dataa(\z80_|execute_|fMRead~36_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .dataa(gnd), + .datab(\z80_|execute_|fMRead~35_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), .cin(gnd), .combout(\z80_|pin_control_|bus_db_pin_re~combout ), .cout()); // synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hEECC; +defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y24_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), .ena1(vcc), @@ -51353,75 +41302,132 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), +// Location: LCCOMB_X32_Y14_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), .ena1(vcc), @@ -51429,68 +41435,125 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y13_N2 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ) # -// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout )) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hBC8C; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC64; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), .portaaddrstall(gnd), @@ -51499,16 +41562,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51516,54 +41579,54 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -51572,56 +41635,56 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; // synopsys translate_on -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -51630,56 +41693,56 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; // synopsys translate_on -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), .portare(vcc), .portaaddrstall(gnd), @@ -51688,16 +41751,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~82_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[1]~34_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51705,161 +41768,2152 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N0 -cycloneive_lcell_comb \Mux0~0 ( +// Location: LCCOMB_X32_Y18_N0 +cycloneive_lcell_comb \Selector1~0 ( // Equation(s): -// \Mux0~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~16_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~16_combout & -// ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) # (!\z80_|address_pins_|abus[14]~16_combout & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) +// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\z80_|address_pins_|abus[14]~16_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .cin(gnd), - .combout(\Mux0~0_combout ), + .combout(\Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hDC98; -defparam \Mux0~0 .sum_lutc_input = "datac"; +defparam \Selector1~0 .lut_mask = 16'hBA98; +defparam \Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N18 -cycloneive_lcell_comb \Mux0~1 ( +// Location: LCCOMB_X32_Y18_N2 +cycloneive_lcell_comb \Selector1~1 ( // Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) +// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\Selector1~0_combout ), .cin(gnd), - .combout(\Mux0~1_combout ), + .combout(\Selector1~1_combout ), .cout()); // synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hDDA0; -defparam \Mux0~1 .sum_lutc_input = "datac"; +defparam \Selector1~1 .lut_mask = 16'hBBC0; +defparam \Selector1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N24 -cycloneive_lcell_comb \D[7]~89 ( +// Location: LCCOMB_X32_Y18_N12 +cycloneive_lcell_comb \D[1]~103 ( // Equation(s): -// \D[7]~89_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )))) +// \D[1]~103_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector1~1_combout +// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), - .datad(\Mux0~1_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .datad(\Selector1~1_combout ), .cin(gnd), - .combout(\D[7]~89_combout ), + .combout(\D[1]~103_combout ), .cout()); // synopsys translate_off -defparam \D[7]~89 .lut_mask = 16'hF2D0; -defparam \D[7]~89 .sum_lutc_input = "datac"; +defparam \D[1]~103 .lut_mask = 16'hF2D0; +defparam \D[1]~103 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N8 -cycloneive_lcell_comb \D[7]~75 ( -// Equation(s): -// \D[7]~75_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~89_combout ) # (!\D[5]~68_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[7]~89_combout ) # (!\D[5]~68_combout )))) +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[5]~68_combout ), - .datad(\D[7]~89_combout ), +// Location: CLKCTRL_G5 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), .cin(gnd), - .combout(\D[7]~75_combout ), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), .cout()); // synopsys translate_off -defparam \D[7]~75 .lut_mask = 16'hBB0B; -defparam \D[7]~75 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y9_N16 -cycloneive_lcell_comb \D[7]~82 ( -// Equation(s): -// \D[7]~82_combout = (\D[7]~75_combout ) # (!\D[0]~30_combout ) +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on - .dataa(\D[0]~30_combout ), +// Location: LCCOMB_X20_Y26_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), .datab(gnd), - .datac(\D[7]~75_combout ), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N1 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N7 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N21 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [5] & !\ula_|ps2_keyboard_|clk_filter [4]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [6]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [5]), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N29 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N23 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [3]))) + + .dataa(\ula_|ps2_keyboard_|Equal0~0_combout ), + .datab(\ula_|ps2_keyboard_|clk_filter [2]), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0002; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), .datad(gnd), .cin(gnd), - .combout(\D[7]~82_combout ), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), .cout()); // synopsys translate_off -defparam \D[7]~82 .lut_mask = 16'hF5F5; -defparam \D[7]~82 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Location: FF_X20_Y26_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[7]~82_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[7]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[7]~9_combout ))) +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[7]~9_combout ), - .datad(\D[7]~82_combout ), + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFC30; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N27 -dffeas \z80_|data_pins_|dout[7] ( +// Location: FF_X20_Y26_N27 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y26_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0C00; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y26_N5 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N3 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N1 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & +// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N17 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & +// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [3]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N27 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\PS2_DAT~input_o ), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCCC0; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|always1~0_combout ), + .datab(\ula_|ps2_keyboard_|bit_count [0]), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00D0; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N9 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N15 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [8]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N11 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N11 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N25 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N29 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N1 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y21_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [1]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|Equal0~0_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF300; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) + + .dataa(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datab(\PS2_DAT~input_o ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N9 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y20_N1 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~15_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & !\ula_|ps2_keyboard_|shiftreg [7])) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0202; +defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[0][0]~15_combout )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q )) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( +// Equation(s): +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|released~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hC8F0; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N19 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y21_N3 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hFF88; +defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0003; +defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[5][1]~38_combout & (!\ula_|zx_keyboard_|keys[5][1]~35_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & +// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N19 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~31_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h00CC; +defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~23_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~23 .lut_mask = 16'h1010; +defparam \ula_|zx_keyboard_|keys[7][1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[7][2]~32_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q +// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), + .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N9 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \D[1]~30 ( +// Equation(s): +// \D[1]~30_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][1]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~30 .lut_mask = 16'hBB0B; +defparam \D[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hA0A0; +defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~24_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00C0; +defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N17 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & \ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h4040; +defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N17 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; +defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0060; +defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2040; +defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & +// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y21_N7 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|scan_code_ready~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~19 .lut_mask = 16'h0100; +defparam \ula_|zx_keyboard_|keys[7][4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~20 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~20 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[6][4]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~21 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~21_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[6][4]~20_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~21 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[1][1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|zx_keyboard_|keys[1][1]~21_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][1]~21_combout & (\ula_|zx_keyboard_|keys[1][1]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[1][1]~21_combout ), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N13 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~22_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N2 +cycloneive_lcell_comb \D[1]~28 ( +// Equation(s): +// \D[1]~28_combout = (\ula_|zx_keyboard_|keys[0][1]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) # (!\ula_|zx_keyboard_|keys[0][1]~q & +// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][1]~q ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\ula_|zx_keyboard_|keys[1][1]~q ), + .cin(gnd), + .combout(\D[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~28 .lut_mask = 16'hD0DD; +defparam \D[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N26 +cycloneive_lcell_comb \D[1]~29 ( +// Equation(s): +// \D[1]~29_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~28_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~q ), + .datab(\ula_|zx_keyboard_|key_row~0_combout ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\D[1]~28_combout ), + .cin(gnd), + .combout(\D[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~29 .lut_mask = 16'hC400; +defparam \D[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~41_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~42_combout )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; +defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & ((!\ula_|zx_keyboard_|keys[6][1]~40_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N25 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~45_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [7]))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [7]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0002; +defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; +defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0044; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0140; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hF022; +defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~5_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|WideOr16~5_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF808; +defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N31 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N20 +cycloneive_lcell_comb \D[1]~31 ( +// Equation(s): +// \D[1]~31_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~q ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\ula_|zx_keyboard_|keys[7][1]~q ), + .cin(gnd), + .combout(\D[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~31 .lut_mask = 16'hB0BB; +defparam \D[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N18 +cycloneive_lcell_comb \D[1]~32 ( +// Equation(s): +// \D[1]~32_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~30_combout & (\D[1]~29_combout & \D[1]~31_combout ))) + + .dataa(\D[1]~30_combout ), + .datab(\z80_|address_pins_|abus[0]~16_combout ), + .datac(\D[1]~29_combout ), + .datad(\D[1]~31_combout ), + .cin(gnd), + .combout(\D[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~32 .lut_mask = 16'hECCC; +defparam \D[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N4 +cycloneive_lcell_comb \D[1]~33 ( +// Equation(s): +// \D[1]~33_combout = ((\Equal2~0_combout & ((\D[1]~32_combout ))) # (!\Equal2~0_combout & (\D[1]~103_combout ))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[1]~103_combout ), + .datad(\D[1]~32_combout ), + .cin(gnd), + .combout(\D[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~33 .lut_mask = 16'hFB73; +defparam \D[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N8 +cycloneive_lcell_comb \D[1]~34 ( +// Equation(s): +// \D[1]~34_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout & \z80_|data_pins_|dout [1])))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[1]~33_combout ), + .datad(\z80_|data_pins_|dout [1]), + .cin(gnd), + .combout(\D[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~34 .lut_mask = 16'hF151; +defparam \D[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[1]~11_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\D[1]~34_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N19 +dffeas \z80_|data_pins_|dout[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -51868,51 +43922,68 @@ dffeas \z80_|data_pins_|dout[7] ( .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [7]), + .q(\z80_|data_pins_|dout [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[7] .power_up = "low"; +defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~8 ( +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( // Equation(s): -// \z80_|bus_control_|db[7]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - .dataa(\z80_|alu_control_|db[7]~18_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\z80_|alu_control_|db[1]~26_combout ), .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~8_combout ), + .combout(\z80_|bus_control_|db[1]~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~8 .lut_mask = 16'hAF00; -defparam \z80_|bus_control_|db[7]~8 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~9 ( +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( // Equation(s): -// \z80_|bus_control_|db[7]~9_combout = ((\z80_|bus_control_|db[7]~8_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|bus_control_|db[7]~8_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|bus_control_|db[1]~10_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~9_combout ), + .combout(\z80_|bus_control_|db[1]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~9 .lut_mask = 16'hB3F3; -defparam \z80_|bus_control_|db[7]~9 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD0FF; +defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N9 -dffeas \z80_|ir_|opcode[7] ( +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|ir_|opcode[1]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[1]~feeder_combout = \z80_|bus_control_|db[1]~11_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[1]~11_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N15 +dffeas \z80_|ir_|opcode[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[7]~9_combout ), + .d(\z80_|ir_|opcode[1]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -51921,666 +43992,2542 @@ dffeas \z80_|ir_|opcode[7] ( .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [7]), + .q(\z80_|ir_|opcode [1]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[7] .power_up = "low"; +defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X51_Y15_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( // Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instCB~q & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|decode_state_|DFFE_instCB~q ), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), + .combout(\z80_|pla_decode_|Equal40~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Location: LCCOMB_X37_Y11_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( // Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0]))) +// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|ir_|opcode [0]), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .combout(\z80_|pla_decode_|Equal21~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y12_N19 -dffeas \z80_|interrupts_|im1 ( +// Location: LCCOMB_X39_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hC080; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~28_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|pla_decode_|Equal64~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~16_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h001F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_mRead~36_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h153F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0088; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h4000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_flags_cf_cpl~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h040C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout = (((!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .lut_mask = 16'h777F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h0F0C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC0E0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAA8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_nf_we~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & !\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ))) + + .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h0008; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h20A0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal10~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hCECC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~20_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFB3; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'h8500; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~21_combout )) + + .dataa(\z80_|alu_|db[7]~21_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[0]~19_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hF0AA; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout +// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h11D8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y9_N31 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0B00; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~14_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout )) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout )) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hF0E4; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout & \z80_|execute_|ctl_alu_op_low~28_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~12_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFF40; +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~19_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (\z80_|execute_|ctl_state_alu~7_combout )))) # (!\z80_|execute_|ctl_state_alu~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_state_alu~15_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h3F3B; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal68~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF32; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~12_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC0CC; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N4 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~9_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( +// Equation(s): +// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~17_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|bus_control_|db[0]~17_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h22A2; +defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N20 +cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( +// Equation(s): +// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~19_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_|db[0]~19_combout ), + .cin(gnd), + .combout(\z80_|sw2_|db_up[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hFF0F; +defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( +// Equation(s): +// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[0]~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|sw2_|db_up[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8A00; +defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( +// Equation(s): +// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[0]~9_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; +defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~67_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~67 .lut_mask = 16'hFF50; +defparam \ula_|zx_keyboard_|keys[5][0]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0420; +defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[5][0]~81_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h2800; +defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), + .datab(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h7474; +defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N11 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~83_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h0160; +defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'hBABA; +defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~84_combout & ((!\ula_|zx_keyboard_|keys[4][0]~85_combout ))) # (!\ula_|zx_keyboard_|keys[4][0]~84_combout & +// (\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N27 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~86_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \D[0]~49 ( +// Equation(s): +// \D[0]~49_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[5][0]~q ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[0]~49_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~49 .lut_mask = 16'hBB0B; +defparam \D[0]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|ps2_keyboard_|shiftreg [6])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & +// (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8810; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~76_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) + + .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~76 .lut_mask = 16'h3313; +defparam \ula_|zx_keyboard_|keys~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~73 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~73_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~73_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~73 .lut_mask = 16'hF000; +defparam \ula_|zx_keyboard_|keys[4][3]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// ((\ula_|ps2_keyboard_|shiftreg [2]))))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0310; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~74_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h353F; +defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~73_combout & !\ula_|zx_keyboard_|keys~74_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~73_combout ), + .datab(\ula_|zx_keyboard_|keys~74_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'h2F00; +defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~77_combout = (\ula_|zx_keyboard_|keys~76_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~75_combout & ((!\ula_|zx_keyboard_|released~q ))) # +// (!\ula_|zx_keyboard_|keys[0][0]~75_combout & (\ula_|zx_keyboard_|keys[0][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys~76_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~77 .lut_mask = 16'hB0F4; +defparam \ula_|zx_keyboard_|keys[0][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N15 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~71_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~71 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[1][0]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|zx_keyboard_|keys[1][0]~71_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][0]~71_combout & (\ula_|zx_keyboard_|keys[1][0]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[1][0]~71_combout ), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N17 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~72_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N30 +cycloneive_lcell_comb \D[0]~47 ( +// Equation(s): +// \D[0]~47_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & +// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\ula_|zx_keyboard_|keys[1][0]~q ), + .cin(gnd), + .combout(\D[0]~47_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~47 .lut_mask = 16'hD0DD; +defparam \D[0]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~80 .lut_mask = 16'hB1F0; +defparam \ula_|zx_keyboard_|keys[2][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N23 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~80_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~78 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|keys[3][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~79_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (\ula_|zx_keyboard_|keys[3][0]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][0]~78_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N5 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~79_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~1_combout = ((\z80_|address_pins_|DFFE_apin_latch [11]) # (!\ula_|zx_keyboard_|keys[3][0]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [11]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hFF3F; +defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N4 +cycloneive_lcell_comb \D[0]~48 ( +// Equation(s): +// \D[0]~48_combout = (\D[0]~47_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) + + .dataa(\D[0]~47_combout ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|key_row~1_combout ), + .cin(gnd), + .combout(\D[0]~48_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~48 .lut_mask = 16'h8A00; +defparam \D[0]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|shifted~1_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[6][0]~90_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|shifted~1_combout ), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|zx_keyboard_|keys[6][0]~91_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~91_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N21 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~92_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~63_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~63 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[5][4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0303; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[5][4]~63_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|WideOr16~3_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~132 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~132_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~132_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~132 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[7][0]~132 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & ((\ula_|zx_keyboard_|keys[7][0]~87_combout ) # (\ula_|zx_keyboard_|keys[7][0]~132_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~132_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h8880; +defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|zx_keyboard_|keys[7][0]~88_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~88_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) + + .dataa(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y20_N7 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~89_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N28 +cycloneive_lcell_comb \D[0]~50 ( +// Equation(s): +// \D[0]~50_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~q ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~q ), + .cin(gnd), + .combout(\D[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~50 .lut_mask = 16'hB0BB; +defparam \D[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y20_N10 +cycloneive_lcell_comb \D[0]~51 ( +// Equation(s): +// \D[0]~51_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~49_combout & (\D[0]~48_combout & \D[0]~50_combout ))) + + .dataa(\D[0]~49_combout ), + .datab(\z80_|address_pins_|abus[0]~16_combout ), + .datac(\D[0]~48_combout ), + .datad(\D[0]~50_combout ), + .cin(gnd), + .combout(\D[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~51 .lut_mask = 16'hECCC; +defparam \D[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N14 +cycloneive_lcell_comb \D[0]~55 ( +// Equation(s): +// \D[0]~55_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\D[0]~55_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~55 .lut_mask = 16'hE3E0; +defparam \D[0]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \D[0]~56 ( +// Equation(s): +// \D[0]~56_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~55_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\D[0]~55_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~55_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[0]~55_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\D[0]~56_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~56 .lut_mask = 16'hBCB0; +defparam \D[0]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~58_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \D[0]~52 ( +// Equation(s): +// \D[0]~52_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~23_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\D[0]~52_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~52 .lut_mask = 16'hF858; +defparam \D[0]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \D[0]~53 ( +// Equation(s): +// \D[0]~53_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ ((\D[0]~52_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & (((!\D[0]~52_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\z80_|address_pins_|abus[15]~22_combout ), + .datac(\D[0]~52_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\D[0]~53_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~53 .lut_mask = 16'h4B48; +defparam \D[0]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \D[0]~54 ( +// Equation(s): +// \D[0]~54_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~52_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~52_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~53_combout )) # (!\D[0]~52_combout & ((\D[0]~53_combout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[0]~52_combout ), + .datad(\D[0]~53_combout ), + .cin(gnd), + .combout(\D[0]~54_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~54 .lut_mask = 16'hC3E0; +defparam \D[0]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \D[0]~106 ( +// Equation(s): +// \D[0]~106_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~56_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~54_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[0]~56_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[0]~56_combout ), + .datad(\D[0]~54_combout ), + .cin(gnd), + .combout(\D[0]~106_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~106 .lut_mask = 16'hF4B0; +defparam \D[0]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \D[0]~57 ( +// Equation(s): +// \D[0]~57_combout = ((\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~1_combout ), + .datab(\D[0]~51_combout ), + .datac(\D[0]~106_combout ), + .datad(\Equal2~0_combout ), + .cin(gnd), + .combout(\D[0]~57_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~57 .lut_mask = 16'hDDF5; +defparam \D[0]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \D[0]~58 ( +// Equation(s): +// \D[0]~58_combout = (\D[0]~57_combout & (((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[0]~57_combout & (!\Equal2~1_combout & ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\D[0]~57_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\D[0]~58_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~58 .lut_mask = 16'hC0F5; +defparam \D[0]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~17_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\D[0]~58_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N1 +dffeas \z80_|data_pins_|dout[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Equation(s): +// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|data_pins_|dout [0]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hC0CC; +defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N28 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Equation(s): +// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~16_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF55; +defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y13_N27 +dffeas \z80_|ir_|opcode[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .asdata(\z80_|bus_control_|db[0]~17_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|im2~q ), - .datac(\z80_|interrupts_|im1~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hF400; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h5D50; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hCECF; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( -// Equation(s): -// \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|bus_control_|db[0]~4_combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'h88AA; -defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( -// Equation(s): -// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[3]~20_combout ), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hBB3B; -defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y13_N23 -dffeas \z80_|ir_|opcode[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[3]~21_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [3]), + .q(\z80_|ir_|opcode [0]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[3] .power_up = "low"; +defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( +// Location: LCCOMB_X39_Y16_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( // Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y12_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .dataa(\z80_|ir_|opcode [0]), .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~1_combout ), + .combout(\z80_|pla_decode_|Equal63~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N20 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Location: LCCOMB_X40_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( // Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N20 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h070F; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( +// Equation(s): +// \z80_|alu_control_|db[6]~10_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) + + .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFF5; +defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( +// Equation(s): +// \z80_|alu_control_|db[6]~11_combout = (\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_sw_1d~7_combout ) # (\z80_|execute_|ctl_reg_out_lo~8_combout )) + + .dataa(\z80_|alu_control_|db[6]~10_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), + .combout(\z80_|alu_control_|db[6]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h1010; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFEFE; +defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N8 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( // Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|decode_state_|in_halt~q ))) +// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~17_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~17_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - .dataa(\z80_|pla_decode_|Equal77~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|decode_state_|in_halt~0_combout ), + .dataa(\z80_|alu_|db[4]~17_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), .cin(gnd), - .combout(\z80_|decode_state_|in_halt~1_combout ), + .combout(\z80_|alu_control_|db[4]~30_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hFF08; -defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; +defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y12_N9 -dffeas \z80_|decode_state_|in_halt ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|in_halt~1_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|in_halt~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; -defparam \z80_|decode_state_|in_halt .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal77~0_combout ))) +// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|alu_control_|db[4]~30_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .combout(\z80_|alu_control_|db[4]~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h00B0; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Location: LCCOMB_X32_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) +// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[4]~31_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .combout(\z80_|alu_control_|db[4]~32_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) +// \ula_|zx_keyboard_|keys[2][4]~119_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h0420; +defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Location: LCCOMB_X29_Y18_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = ((\z80_|execute_|ctl_bus_db_we~4_combout ) # ((!\z80_|execute_|ctl_apin_mux~0_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout ))) # (!\z80_|execute_|ctl_bus_db_we~5_combout ) +// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - .dataa(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datac(\z80_|execute_|ctl_sw_2u~3_combout ), - .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datab(\ula_|zx_keyboard_|keys[2][4]~119_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Location: LCCOMB_X29_Y18_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~95 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h2220; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_ir_we~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFE0; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~6_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_db_we~3_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~124_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~124 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[5][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~125 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~125_combout = (\ula_|zx_keyboard_|keys[5][4]~124_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & ((\ula_|zx_keyboard_|keys[5][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][4]~124_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) +// \ula_|zx_keyboard_|keys[2][4]~95_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[5][4]~124_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~125_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~125 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][4]~125 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N17 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~126_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [6])) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|shiftreg -// [6])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(gnd), + .datab(gnd), + .datac(\ula_|zx_keyboard_|shifted~q ), .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~126_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~95_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~126 .lut_mask = 16'h4422; -defparam \ula_|zx_keyboard_|keys[4][4]~126 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~95 .lut_mask = 16'hAFAA; +defparam \ula_|zx_keyboard_|keys[2][4]~95 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~127_combout = (\ula_|zx_keyboard_|keys[4][4]~126_combout & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[4][4]~126_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~127 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~128_combout = (\ula_|zx_keyboard_|keys[4][4]~127_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (\ula_|zx_keyboard_|keys[4][4]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][4]~127_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][4]~127_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~128 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][4]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N23 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~128_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \D[4]~64 ( -// Equation(s): -// \D[4]~64_combout = (\ula_|zx_keyboard_|keys[5][4]~q & (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][4]~q )))) # (!\ula_|zx_keyboard_|keys[5][4]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\D[4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~64 .lut_mask = 16'hCF45; -defparam \D[4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~119_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg -// [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~119 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[3][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~138 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~138_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|keys[3][4]~119_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~138_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~138 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[3][4]~138 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~120 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~120_combout = (\ula_|zx_keyboard_|keys[3][4]~132_combout & ((\ula_|zx_keyboard_|keys[3][4]~138_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][4]~138_combout & -// (\ula_|zx_keyboard_|keys[3][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][4]~132_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][4]~132_combout ), - .datab(\ula_|zx_keyboard_|keys[3][4]~138_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~120_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~120 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][4]~120 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N29 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~120_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 +// Location: LCCOMB_X29_Y18_N22 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~121 ( // Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|zx_keyboard_|keys[2][4]~120_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~120_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\ula_|zx_keyboard_|keys[2][4]~120_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[2][4]~121_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h50FA; defparam \ula_|zx_keyboard_|keys[2][4]~121 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y15_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|zx_keyboard_|keys[2][4]~121_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~122 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[2][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~123_combout = (\ula_|zx_keyboard_|keys[2][4]~122_combout & (!\ula_|zx_keyboard_|keys[2][4]~97_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~122_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[2][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~122_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~123 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N19 +// Location: FF_X29_Y18_N23 dffeas \ula_|zx_keyboard_|keys[2][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~123_combout ), + .d(\ula_|zx_keyboard_|keys[2][4]~121_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52596,46 +46543,80 @@ defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \D[4]~63 ( +// Location: LCCOMB_X29_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( // Equation(s): -// \D[4]~63_combout = (\z80_|address_pins_|abus[10]~22_combout & (((\z80_|address_pins_|abus[11]~21_combout )) # (!\ula_|zx_keyboard_|keys[3][4]~q ))) # (!\z80_|address_pins_|abus[10]~22_combout & (!\ula_|zx_keyboard_|keys[2][4]~q & -// ((\z80_|address_pins_|abus[11]~21_combout ) # (!\ula_|zx_keyboard_|keys[3][4]~q )))) +// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|extended~q ))) - .dataa(\z80_|address_pins_|abus[10]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[3][4]~q ), - .datac(\z80_|address_pins_|abus[11]~21_combout ), - .datad(\ula_|zx_keyboard_|keys[2][4]~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\D[4]~63_combout ), + .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), .cout()); // synopsys translate_off -defparam \D[4]~63 .lut_mask = 16'hA2F3; -defparam \D[4]~63 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~129 ( +// Location: LCCOMB_X29_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~136 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~129_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) +// \ula_|zx_keyboard_|keys[3][4]~136_combout = (\ula_|zx_keyboard_|keys[3][4]~117_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [4]))) - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .dataa(\ula_|zx_keyboard_|keys[3][4]~117_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~129_combout ), + .combout(\ula_|zx_keyboard_|keys[3][4]~136_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~129 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][4]~129 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][4]~136 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[3][4]~136 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y15_N25 -dffeas \ula_|zx_keyboard_|keys[7][4] ( +// Location: LCCOMB_X28_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~130_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~130 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[3][4]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|zx_keyboard_|keys[3][4]~136_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[3][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~136_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~136_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N9 +dffeas \ula_|zx_keyboard_|keys[3][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~129_combout ), + .d(\ula_|zx_keyboard_|keys[3][4]~118_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52644,52 +46625,124 @@ dffeas \ula_|zx_keyboard_|keys[7][4] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~130 ( +// Location: LCCOMB_X29_Y19_N18 +cycloneive_lcell_comb \D[4]~78 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~130_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) +// \D[4]~78_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~q ), + .cin(gnd), + .combout(\D[4]~78_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~78 .lut_mask = 16'h8ACF; +defparam \D[4]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~126_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~130_combout ), + .combout(\ula_|zx_keyboard_|keys[5][4]~128_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~130 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[6][4]~130 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][4]~128 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[5][4]~128 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~131 ( +// Location: LCCOMB_X28_Y19_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~129 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~131_combout = (\ula_|zx_keyboard_|keys[6][4]~130_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~130_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) +// \ula_|zx_keyboard_|keys[5][4]~129_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[5][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~128_combout & +// (\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[6][4]~130_combout ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~128_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~131_combout ), + .combout(\ula_|zx_keyboard_|keys[5][4]~129_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~131 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[6][4]~131 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][4]~129 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][4]~129 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y14_N31 +// Location: FF_X28_Y19_N9 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~129_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~127_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~20_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~20_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~127 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[6][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N5 dffeas \ula_|zx_keyboard_|keys[6][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~131_combout ), + .d(\ula_|zx_keyboard_|keys[6][4]~127_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52705,46 +46758,257 @@ defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \D[4]~65 ( +// Location: LCCOMB_X28_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( // Equation(s): -// \D[4]~65_combout = (\z80_|address_pins_|abus[15]~17_combout & (((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~17_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & -// ((\z80_|address_pins_|abus[14]~16_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) +// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - .dataa(\z80_|address_pins_|abus[15]~17_combout ), - .datab(\ula_|zx_keyboard_|keys[7][4]~q ), - .datac(\z80_|address_pins_|abus[14]~16_combout ), - .datad(\ula_|zx_keyboard_|keys[6][4]~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), .cin(gnd), - .combout(\D[4]~65_combout ), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \D[4]~65 .lut_mask = 16'hB0BB; -defparam \D[4]~65 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~118 ( +// Location: LCCOMB_X28_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~118_combout = (\ula_|zx_keyboard_|keys[0][4]~99_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~99_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) +// \ula_|zx_keyboard_|keys[7][4]~51_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - .dataa(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~99_combout ), + .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) +// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~1_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N11 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N30 +cycloneive_lcell_comb \D[4]~79 ( +// Equation(s): +// \D[4]~79_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & +// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .cin(gnd), + .combout(\D[4]~79_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~79 .lut_mask = 16'h8ACF; +defparam \D[4]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & +// \ula_|zx_keyboard_|extended~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h4422; +defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][4]~122_combout ))) + + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N25 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\ula_|zx_keyboard_|keys[4][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [12]), + .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hF3FF; +defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N8 +cycloneive_lcell_comb \D[4]~80 ( +// Equation(s): +// \D[4]~80_combout = (\D[4]~79_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), + .datab(\D[4]~79_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|key_row~3_combout ), + .cin(gnd), + .combout(\D[4]~80_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~80 .lut_mask = 16'hC400; +defparam \D[4]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFAAA; +defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~97_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~97 .lut_mask = 16'h0060; +defparam \ula_|zx_keyboard_|keys[0][4]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~116_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & +// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~111_combout ), .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), + .datad(\ula_|zx_keyboard_|keys[0][4]~97_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~118_combout ), + .combout(\ula_|zx_keyboard_|keys[0][4]~116_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~118 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[0][4]~118 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[0][4]~116 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][4]~116 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y14_N3 +// Location: FF_X29_Y18_N11 dffeas \ula_|zx_keyboard_|keys[0][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~118_combout ), + .d(\ula_|zx_keyboard_|keys[0][4]~116_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52760,28 +47024,28 @@ defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~117 ( +// Location: LCCOMB_X29_Y19_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~115 ( // Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~117_combout = (\ula_|zx_keyboard_|keys[1][4]~25_combout & ((\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # -// (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) +// \ula_|zx_keyboard_|keys[1][4]~115_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # +// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - .dataa(\ula_|zx_keyboard_|released~q ), + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~117_combout ), + .combout(\ula_|zx_keyboard_|keys[1][4]~115_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~117 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[1][4]~117 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[1][4]~115 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][4]~115 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y14_N3 +// Location: FF_X29_Y19_N7 dffeas \ula_|zx_keyboard_|keys[1][4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~117_combout ), + .d(\ula_|zx_keyboard_|keys[1][4]~115_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52797,308 +47061,42 @@ defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N4 -cycloneive_lcell_comb \D[4]~62 ( +// Location: LCCOMB_X29_Y19_N28 +cycloneive_lcell_comb \D[4]~77 ( // Equation(s): -// \D[4]~62_combout = (\ula_|zx_keyboard_|keys[0][4]~q & (\z80_|address_pins_|abus[8]~20_combout & ((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][4]~q )))) # (!\ula_|zx_keyboard_|keys[0][4]~q & -// (((\z80_|address_pins_|abus[9]~19_combout ) # (!\ula_|zx_keyboard_|keys[1][4]~q )))) +// \D[4]~77_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - .dataa(\ula_|zx_keyboard_|keys[0][4]~q ), - .datab(\z80_|address_pins_|abus[8]~20_combout ), - .datac(\z80_|address_pins_|abus[9]~19_combout ), + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), .datad(\ula_|zx_keyboard_|keys[1][4]~q ), .cin(gnd), - .combout(\D[4]~62_combout ), + .combout(\D[4]~77_combout ), .cout()); // synopsys translate_off -defparam \D[4]~62 .lut_mask = 16'hD0DD; -defparam \D[4]~62 .sum_lutc_input = "datac"; +defparam \D[4]~77 .lut_mask = 16'h8ACF; +defparam \D[4]~77 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \D[4]~66 ( +// Location: LCCOMB_X29_Y19_N26 +cycloneive_lcell_comb \D[4]~81 ( // Equation(s): -// \D[4]~66_combout = (\D[4]~64_combout & (\D[4]~63_combout & (\D[4]~65_combout & \D[4]~62_combout ))) +// \D[4]~81_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~78_combout & (\D[4]~80_combout & \D[4]~77_combout ))) - .dataa(\D[4]~64_combout ), - .datab(\D[4]~63_combout ), - .datac(\D[4]~65_combout ), - .datad(\D[4]~62_combout ), + .dataa(\z80_|address_pins_|abus[0]~16_combout ), + .datab(\D[4]~78_combout ), + .datac(\D[4]~80_combout ), + .datad(\D[4]~77_combout ), .cin(gnd), - .combout(\D[4]~66_combout ), + .combout(\D[4]~81_combout ), .cout()); // synopsys translate_off -defparam \D[4]~66 .lut_mask = 16'h8000; -defparam \D[4]~66 .sum_lutc_input = "datac"; +defparam \D[4]~81 .lut_mask = 16'hEAAA; +defparam \D[4]~81 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y32_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y21_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X23_Y21_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ) # -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hADA8; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y21_N2 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hF388; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y4_N0 +// Location: M9K_X22_Y1_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portawe(vcc), .portare(vcc), @@ -53108,16 +47106,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -53156,7 +47154,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: M9K_X33_Y28_N0 +// Location: M9K_X22_Y22_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -53166,16 +47164,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -53229,7 +47227,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y12_N0 +// Location: M9K_X33_Y3_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(vcc), .portare(vcc), @@ -53239,16 +47237,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -53287,7 +47285,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: M9K_X33_Y30_N0 +// Location: M9K_X22_Y25_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), .portare(vcc), @@ -53297,16 +47295,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~79_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~21_combout ,\z80_|address_pins_|abus[10]~22_combout ,\z80_|address_pins_|abus[9]~19_combout ,\z80_|address_pins_|abus[8]~20_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~18_combout }), +\z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -53359,120 +47357,370 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N12 +// Location: LCCOMB_X29_Y14_N2 cycloneive_lcell_comb \Selector4~0 ( // Equation(s): -// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~16_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~16_combout -// & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) +// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - .dataa(\z80_|address_pins_|abus[14]~16_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), .cin(gnd), .combout(\Selector4~0_combout ), .cout()); // synopsys translate_off -defparam \Selector4~0 .lut_mask = 16'hAEA4; +defparam \Selector4~0 .lut_mask = 16'hBA98; defparam \Selector4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N2 +// Location: LCCOMB_X29_Y14_N26 cycloneive_lcell_comb \Selector4~1 ( // Equation(s): // \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & // (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), .datad(\Selector4~0_combout ), .cin(gnd), .combout(\Selector4~1_combout ), .cout()); // synopsys translate_off -defparam \Selector4~1 .lut_mask = 16'hF588; +defparam \Selector4~1 .lut_mask = 16'hF388; defparam \Selector4~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \D[4]~60 ( +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~98_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 ( // Equation(s): -// \D[4]~60_combout = (!\Equal2~0_combout & ((\z80_|address_pins_|abus[15]~17_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout )) # (!\z80_|address_pins_|abus[15]~17_combout & ((\Selector4~1_combout ))))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .lut_mask = 16'hE5E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .lut_mask = 16'hAFC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \D[4]~109 ( +// Equation(s): +// \D[4]~109_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Selector4~1_combout +// )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ))))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Selector4~1_combout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), + .cin(gnd), + .combout(\D[4]~109_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~109 .lut_mask = 16'hFB40; +defparam \D[4]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \D[4]~97 ( +// Equation(s): +// \D[4]~97_combout = ((\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout )))) # (!\Equal2~1_combout ) .dataa(\Equal2~0_combout ), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), - .datac(\z80_|address_pins_|abus[15]~17_combout ), - .datad(\Selector4~1_combout ), + .datab(\D[4]~81_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[4]~109_combout ), .cin(gnd), - .combout(\D[4]~60_combout ), + .combout(\D[4]~97_combout ), .cout()); // synopsys translate_off -defparam \D[4]~60 .lut_mask = 16'h4540; -defparam \D[4]~60 .sum_lutc_input = "datac"; +defparam \D[4]~97 .lut_mask = 16'hDF8F; +defparam \D[4]~97 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \D[4]~61 ( +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \D[4]~98 ( // Equation(s): -// \D[4]~61_combout = (((\z80_|memory_ifc_|nWR_out~0_combout ) # (\D[4]~60_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|memory_ifc_|nRD_out~2_combout ) +// \D[4]~98_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~97_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[4]~97_combout ) # (!\Equal2~1_combout )))) - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nWR_out~0_combout ), - .datad(\D[4]~60_combout ), + .dataa(\z80_|data_pins_|dout [4]), + .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[4]~97_combout ), .cin(gnd), - .combout(\D[4]~61_combout ), + .combout(\D[4]~98_combout ), .cout()); // synopsys translate_off -defparam \D[4]~61 .lut_mask = 16'hFFF7; -defparam \D[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \D[4]~78 ( -// Equation(s): -// \D[4]~78_combout = (\D[4]~61_combout ) # ((\Equal2~0_combout & ((\D[4]~66_combout ) # (\z80_|address_pins_|abus[0]~18_combout )))) - - .dataa(\D[4]~66_combout ), - .datab(\z80_|address_pins_|abus[0]~18_combout ), - .datac(\D[4]~61_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~78 .lut_mask = 16'hFEF0; -defparam \D[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \D[4]~79 ( -// Equation(s): -// \D[4]~79_combout = ((\D[4]~78_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[0]~30_combout ) - - .dataa(\D[4]~78_combout ), - .datab(\z80_|data_pins_|dout [4]), - .datac(\D[0]~30_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cin(gnd), - .combout(\D[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~79 .lut_mask = 16'h8FAF; -defparam \D[4]~79 .sum_lutc_input = "datac"; +defparam \D[4]~98 .lut_mask = 16'hBB03; +defparam \D[4]~98 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X32_Y13_N24 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[4]~79_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[4]~19_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (\z80_|execute_|ctl_bus_db_we~7_combout & (\z80_|bus_control_|db[4]~19_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[4]~19_combout ) # ((\D[4]~98_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[4]~98_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\D[4]~79_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[4]~98_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), .cout()); @@ -53500,41 +47748,41 @@ defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N20 +// Location: LCCOMB_X32_Y13_N20 cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( // Equation(s): // \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(gnd), - .datac(\z80_|data_pins_|dout [4]), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|data_pins_|dout [4]), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), .combout(\z80_|bus_control_|db[4]~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hF500; +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88CC; defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N4 +// Location: LCCOMB_X34_Y10_N18 cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( // Equation(s): // \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .dataa(\z80_|bus_control_|db[0]~6_combout ), .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[4]~19_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF0F; +defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF55; defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y13_N5 +// Location: FF_X34_Y10_N19 dffeas \z80_|ir_|opcode[4] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|bus_control_|db[4]~19_combout ), @@ -53553,32 +47801,2546 @@ defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X41_Y11_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Location: LCCOMB_X40_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( // Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) +// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), + .datab(gnd), .datac(\z80_|ir_|opcode [3]), - .datad(gnd), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), + .combout(\z80_|pla_decode_|Equal21~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h3030; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N12 +// Location: LCCOMB_X35_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( +// Equation(s): +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|fMRead~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|fMRead~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Equation(s): +// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F0F; +defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( +// Equation(s): +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~36_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|fIOWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( +// Equation(s): +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~5_combout ))) + + .dataa(\z80_|execute_|fIOWrite~1_combout ), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|fIOWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & +// (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~15_combout = ((\z80_|execute_|ctl_mWrite~14_combout ) # ((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout ))) # (!\z80_|execute_|ctl_mWrite~13_combout ) + + .dataa(\z80_|execute_|ixy_d~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~13_combout ), + .datac(\z80_|execute_|ctl_mWrite~14_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF7F3; +defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N29 +dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mWrite~15_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N4 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X43_Y17_N5 +dffeas \z80_|memory_ifc_|wait_mwr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mwr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +// synopsys translate_on + +// Location: FF_X43_Y17_N17 +dffeas \z80_|memory_ifc_|mwr_wr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|mwr_wr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N16 +cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(\z80_|memory_ifc_|iorq~0_combout ), + .datac(\z80_|memory_ifc_|mwr_wr~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|memory_ifc_|nWR_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; +defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \D[5]~84 ( +// Equation(s): +// \D[5]~84_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cin(gnd), + .combout(\D[5]~84_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~84 .lut_mask = 16'h0040; +defparam \D[5]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF858; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~102_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~0 .lut_mask = 16'hBA98; +defparam \Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \Mux0~1 ( +// Equation(s): +// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datad(\Mux0~0_combout ), + .cin(gnd), + .combout(\Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~1 .lut_mask = 16'hBBC0; +defparam \Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N22 +cycloneive_lcell_comb \D[7]~112 ( +// Equation(s): +// \D[7]~112_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux0~1_combout ))) +// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~112_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~112 .lut_mask = 16'hF4B0; +defparam \D[7]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N30 +cycloneive_lcell_comb \D[7]~94 ( +// Equation(s): +// \D[7]~94_combout = (\D[5]~84_combout & (\D[7]~112_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) + + .dataa(\D[5]~84_combout ), + .datab(\z80_|data_pins_|dout [7]), + .datac(\D[7]~112_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\D[7]~94_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~94 .lut_mask = 16'hC4F5; +defparam \D[7]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \D[7]~102 ( +// Equation(s): +// \D[7]~102_combout = (\D[7]~94_combout ) # (!\D[0]~107_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\D[7]~94_combout ), + .datad(\D[0]~107_combout ), + .cin(gnd), + .combout(\D[7]~102_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~102 .lut_mask = 16'hF0FF; +defparam \D[7]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\D[7]~102_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[7]~7_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[7]~102_combout & (\z80_|bus_control_|db[7]~7_combout +// & ((\z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[7]~102_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N27 +dffeas \z80_|data_pins_|dout[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Equation(s): +// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[7]~18_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N8 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Equation(s): +// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|data_pins_|dout [7]), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|bus_control_|db[7]~5_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hBF0F; +defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N21 +dffeas \z80_|ir_|opcode[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[7]~7_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_ir_we~4_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h3020; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC8C0; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~6_combout = (((\z80_|execute_|ctl_bus_db_we~4_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~2_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~3_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h000F; +defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & ((\ula_|zx_keyboard_|keys[0][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N17 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~48_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~48 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[3][3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), + .datab(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N23 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N22 +cycloneive_lcell_comb \D[2]~35 ( +// Equation(s): +// \D[2]~35_combout = (\z80_|address_pins_|abus[8]~18_combout & (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\z80_|address_pins_|abus[8]~18_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & +// ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) + + .dataa(\z80_|address_pins_|abus[8]~18_combout ), + .datab(\ula_|zx_keyboard_|keys[0][2]~q ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\z80_|address_pins_|abus[9]~17_combout ), + .cin(gnd), + .combout(\D[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~35 .lut_mask = 16'hBB0B; +defparam \D[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h3300; +defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|zx_keyboard_|keys[5][2]~57_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[5][2]~57_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N15 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h0420; +defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[4][2]~59_combout & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~131 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[4][2]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|zx_keyboard_|keys[4][2]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~131_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[4][2]~131_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N15 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \D[2]~37 ( +// Equation(s): +// \D[2]~37_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[5][2]~q ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~37 .lut_mask = 16'hBB0B; +defparam \D[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~55 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[2][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~56_combout = (\ula_|zx_keyboard_|keys[2][2]~55_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][2]~q ), + .datad(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N27 +dffeas \ula_|zx_keyboard_|keys[2][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y20_N29 +dffeas \ula_|zx_keyboard_|keys[3][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N8 +cycloneive_lcell_comb \D[2]~36 ( +// Equation(s): +// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~24_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & +// (((\z80_|address_pins_|abus[11]~19_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), + .datab(\ula_|zx_keyboard_|keys[3][2]~q ), + .datac(\z80_|address_pins_|abus[10]~24_combout ), + .datad(\z80_|address_pins_|abus[11]~19_combout ), + .cin(gnd), + .combout(\D[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~36 .lut_mask = 16'hF531; +defparam \D[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h0180; +defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~68_combout )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~70_combout = (\ula_|zx_keyboard_|keys[6][2]~69_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~69_combout & ((\ula_|zx_keyboard_|keys[6][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), + .datab(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .datac(\ula_|zx_keyboard_|keys[6][2]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h7474; +defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N1 +dffeas \ula_|zx_keyboard_|keys[6][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[7][2]~61_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~62_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~63_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[7][2]~62_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'hC8C0; +defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~65_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & \ula_|zx_keyboard_|keys[7][2]~64_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector13~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF22; +defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[7][2]~65_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~65_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][2]~q ), + .datad(\ula_|zx_keyboard_|Selector13~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N13 +dffeas \ula_|zx_keyboard_|keys[7][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N0 +cycloneive_lcell_comb \D[2]~38 ( +// Equation(s): +// \D[2]~38_combout = (\z80_|address_pins_|abus[15]~22_combout & (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][2]~q & +// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\ula_|zx_keyboard_|keys[6][2]~q ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~q ), + .cin(gnd), + .combout(\D[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~38 .lut_mask = 16'hA2F3; +defparam \D[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N14 +cycloneive_lcell_comb \D[2]~39 ( +// Equation(s): +// \D[2]~39_combout = (\D[2]~35_combout & (\D[2]~37_combout & (\D[2]~36_combout & \D[2]~38_combout ))) + + .dataa(\D[2]~35_combout ), + .datab(\D[2]~37_combout ), + .datac(\D[2]~36_combout ), + .datad(\D[2]~38_combout ), + .cin(gnd), + .combout(\D[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~39 .lut_mask = 16'h8000; +defparam \D[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \D[2]~104 ( +// Equation(s): +// \D[2]~104_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\D[2]~39_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [0]), + .datad(\D[2]~39_combout ), + .cin(gnd), + .combout(\D[2]~104_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~104 .lut_mask = 16'hFFF3; +defparam \D[2]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \D[2]~43 ( +// Equation(s): +// \D[2]~43_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\D[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~43 .lut_mask = 16'hB9A8; +defparam \D[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \D[2]~44 ( +// Equation(s): +// \D[2]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~43_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout )) # (!\D[2]~43_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~43_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\D[2]~43_combout ), + .cin(gnd), + .combout(\D[2]~44_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~44 .lut_mask = 16'hBBC0; +defparam \D[2]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \D[2]~40 ( +// Equation(s): +// \D[2]~40_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\D[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~40 .lut_mask = 16'hEA62; +defparam \D[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \D[2]~41 ( +// Equation(s): +// \D[2]~41_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ (\D[2]~40_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & ((!\D[2]~40_combout )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\D[2]~40_combout ), + .cin(gnd), + .combout(\D[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~41 .lut_mask = 16'h0AE4; +defparam \D[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \D[2]~42 ( +// Equation(s): +// \D[2]~42_combout = (\D[2]~40_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~41_combout )))) # (!\D[2]~40_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~41_combout )))) + + .dataa(\D[2]~40_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\D[2]~41_combout ), + .cin(gnd), + .combout(\D[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~42 .lut_mask = 16'h99A8; +defparam \D[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \D[2]~105 ( +// Equation(s): +// \D[2]~105_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[2]~44_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~42_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[2]~44_combout )))) + + .dataa(\D[2]~44_combout ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\D[2]~42_combout ), + .cin(gnd), + .combout(\D[2]~105_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~105 .lut_mask = 16'hBA8A; +defparam \D[2]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N28 +cycloneive_lcell_comb \D[2]~45 ( +// Equation(s): +// \D[2]~45_combout = ((\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[2]~104_combout ), + .datad(\D[2]~105_combout ), + .cin(gnd), + .combout(\D[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~45 .lut_mask = 16'hF7B3; +defparam \D[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N30 +cycloneive_lcell_comb \D[2]~46 ( +// Equation(s): +// \D[2]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~45_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[2]~45_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[2]~45_combout ), + .cin(gnd), + .combout(\D[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~46 .lut_mask = 16'hAF03; +defparam \D[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N2 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[2]~46_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[2]~46_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\D[2]~46_combout ), + .datad(\z80_|bus_control_|db[2]~13_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N3 +dffeas \z80_|data_pins_|dout[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( +// Equation(s): +// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[2]~29_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( +// Equation(s): +// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|bus_control_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hBF33; +defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N13 +dffeas \z80_|ir_|opcode[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[2]~13_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N26 cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( // Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) +// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal43~0_combout ), .cout()); @@ -53587,14 +50349,14 @@ defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N14 +// Location: LCCOMB_X35_Y17_N24 cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( // Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal79~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & !\z80_|pla_decode_|Equal36~0_combout ))) +// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) .dataa(\z80_|pla_decode_|Equal43~0_combout ), - .datab(\z80_|pla_decode_|Equal79~0_combout ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datab(\z80_|pla_decode_|Equal3~2_combout ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), .datad(\z80_|pla_decode_|Equal36~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|test1~2_combout ), @@ -53604,24 +50366,24 @@ defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X49_Y12_N22 +// Location: LCCOMB_X43_Y15_N26 cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( // Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & (((\z80_|interrupts_|test1~2_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) +// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|interrupts_|test1~2_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|interrupts_|test1~2_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|interrupts_|test1~2_combout ), .cin(gnd), .combout(\z80_|interrupts_|test1~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h00FD; +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h5545; defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y12_N27 +// Location: FF_X32_Y15_N13 dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), @@ -53640,7 +50402,7 @@ defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y12_N16 +// Location: LCCOMB_X43_Y15_N2 cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( // Equation(s): // \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) @@ -53657,7 +50419,7 @@ defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X50_Y12_N17 +// Location: FF_X43_Y15_N3 dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), @@ -53676,7 +50438,7 @@ defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N2 +// Location: LCCOMB_X43_Y15_N20 cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( // Equation(s): // \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) @@ -53693,7 +50455,7 @@ defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0033; defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N1 +// Location: FF_X32_Y17_N13 dffeas \z80_|sequencer_|DFFE_T1_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|ena_M~combout ), @@ -53712,24 +50474,24 @@ defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N26 +// Location: LCCOMB_X32_Y17_N4 cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( // Equation(s): // \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), .datac(\z80_|execute_|setM1~52_combout ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0030; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N27 +// Location: FF_X32_Y17_N5 dffeas \z80_|sequencer_|DFFE_T2_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), @@ -53748,318 +50510,56 @@ defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N16 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|resets_|x3 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - .dataa(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datac(\z80_|resets_|x1~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .combout(\z80_|resets_|x3~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +defparam \z80_|resets_|x3 .lut_mask = 16'hF0FA; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N17 -dffeas \z80_|sequencer_|DFFE_T3_ff ( +// Location: FF_X35_Y13_N11 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .d(\z80_|resets_|x3~combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N14 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N15 -dffeas \z80_|sequencer_|DFFE_T4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), +// Location: CLKCTRL_G7 +cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), + .clkselect(2'b00), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), - .prn(vcc)); + .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X44_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( -// Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (\z80_|execute_|setM1~39_combout & !\z80_|execute_|ctl_mWrite~5_combout ) - - .dataa(\z80_|execute_|setM1~39_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h00AA; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~53 ( -// Equation(s): -// \z80_|execute_|setM1~53_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & \z80_|execute_|ctl_mRead~29_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~53_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h2AAA; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'hA800; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ctl_mRead~38_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|execute_|nextM~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|ctl_alu_op_low~37_combout ) # (\z80_|execute_|nextM~10_combout )) # (!\z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|nextM~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~37_combout ), - .datad(\z80_|execute_|nextM~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|fMRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'h8808; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (((\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|nextM~4_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|nextM~4_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~5_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~6_combout ) - - .dataa(\z80_|execute_|nextM~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|nextM~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( -// Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ixy_d~8_combout & (((!\z80_|alu_control_|flags_cond_true~q & \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|ixy_d~8_combout & -// (((!\z80_|alu_control_|flags_cond_true~q & \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout )))) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h2F22; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # ((\z80_|execute_|nextM~7_combout ) # (\z80_|execute_|nextM~8_combout ))) - - .dataa(\z80_|execute_|nextM~12_combout ), - .datab(\z80_|execute_|nextM~15_combout ), - .datac(\z80_|execute_|nextM~7_combout ), - .datad(\z80_|execute_|nextM~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~3_combout ) # ((\z80_|execute_|nextM~13_combout ) # ((!\z80_|execute_|ctl_mWrite~13_combout ) # (!\z80_|execute_|ctl_mRead~31_combout ))) - - .dataa(\z80_|execute_|nextM~3_combout ), - .datab(\z80_|execute_|nextM~13_combout ), - .datac(\z80_|execute_|ctl_mRead~31_combout ), - .datad(\z80_|execute_|ctl_mWrite~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N4 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; -defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N5 +// Location: FF_X32_Y17_N21 dffeas \z80_|sequencer_|DFFE_M1_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), @@ -54078,644 +50578,7 @@ defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N24 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X52_Y13_N25 -dffeas \z80_|sequencer_|T6 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|T6~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|T6 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~9_combout )) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0011; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~43 ( -// Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0004; -defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~42_combout & (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|setM1~43_combout & !\z80_|pla_decode_|Equal21~1_combout ))) - - .dataa(\z80_|execute_|setM1~42_combout ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|setM1~43_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0020; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (\z80_|execute_|setM1~44_combout & (\z80_|execute_|setM1~41_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|execute_|setM1~44_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0888; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & -// (((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal21~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & !\z80_|pla_decode_|Equal1~6_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal77~1_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|pla_decode_|Equal1~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (!\z80_|pla_decode_|Equal2~2_combout & (\z80_|execute_|setM1~15_combout & (\z80_|execute_|setM1~14_combout & \z80_|interrupts_|test1~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|execute_|setM1~15_combout ), - .datac(\z80_|execute_|setM1~14_combout ), - .datad(\z80_|interrupts_|test1~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~49_combout & (\z80_|execute_|setM1~46_combout & \z80_|execute_|setM1~16_combout ))) - - .dataa(\z80_|execute_|setM1~45_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|execute_|setM1~46_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|setM1~41_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & -// (\z80_|execute_|setM1~40_combout ))) - - .dataa(\z80_|sequencer_|T6~q ), - .datab(\z80_|execute_|setM1~50_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'hC0EA; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hCDCC; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal6~1_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout ) # (\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|fMWrite~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|fMWrite~1_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~11_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|setM1~11_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|setM1~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & ((\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hDC50; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = ((\z80_|execute_|setM1~8_combout & \z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|execute_|setM1~8_combout ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF333; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( -// Equation(s): -// \z80_|execute_|setM1~13_combout = (\z80_|execute_|setM1~9_combout ) # (((\z80_|execute_|setM1~12_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) - - .dataa(\z80_|execute_|setM1~12_combout ), - .datab(\z80_|execute_|setM1~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'hECFF; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X45_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (\z80_|execute_|setM1~17_combout & (\z80_|execute_|ctl_alu_op_low~36_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|setM1~17_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~36_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0008; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~13_combout ) # (((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|setM1~16_combout )) # (!\z80_|execute_|setM1~18_combout )) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|setM1~16_combout ), - .datac(\z80_|execute_|setM1~13_combout ), - .datad(\z80_|execute_|setM1~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hF2FF; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = (\z80_|alu_control_|flags_cond_true~q & (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) # (!\z80_|alu_control_|flags_cond_true~q & -// ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((!\z80_|execute_|ctl_mRead~14_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'h7350; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|execute_|fMWrite~6_combout ))) - - .dataa(\z80_|execute_|fMWrite~1_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|fMWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0200; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'hFF02; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( -// Equation(s): -// \z80_|execute_|setM1~55_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~22_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~22_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'hC888; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X50_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~55_combout )) # (!\z80_|execute_|setM1~23_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~55_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|setM1~23_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~55_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h2F22; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hBAFF; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = ((\z80_|execute_|setM1~26_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datad(\z80_|execute_|setM1~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|setM1~27_combout ))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~24_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|setM1~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_mRead~38_combout & \z80_|execute_|setM1~11_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~38_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|setM1~11_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~20_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ctl_mRead~20_combout & -// (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X49_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|setM1~29_combout & \z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|setM1~30_combout )) # (!\z80_|execute_|setM1~56_combout ) - - .dataa(\z80_|execute_|setM1~29_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|setM1~56_combout ), - .datad(\z80_|execute_|setM1~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~33_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|setM1~33_combout ), - .datac(\z80_|execute_|setM1~32_combout ), - .datad(\z80_|execute_|setM1~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = ((\z80_|execute_|ctl_iorw~10_combout & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hD555; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X47_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~13_combout & (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~13_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20AA; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|execute_|setM1~20_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hECCC; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~34_combout ) # ((\z80_|execute_|setM1~54_combout ) # (\z80_|execute_|setM1~21_combout ))) - - .dataa(\z80_|execute_|setM1~28_combout ), - .datab(\z80_|execute_|setM1~34_combout ), - .datac(\z80_|execute_|setM1~54_combout ), - .datad(\z80_|execute_|setM1~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X48_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( -// Equation(s): -// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~19_combout & (!\z80_|execute_|setM1~35_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|setM1~51_combout ), - .datac(\z80_|execute_|setM1~19_combout ), - .datad(\z80_|execute_|setM1~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'h000B; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y13_N18 +// Location: LCCOMB_X32_Y17_N10 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( // Equation(s): // \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) @@ -54732,7 +50595,7 @@ defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N19 +// Location: FF_X32_Y17_N11 dffeas \z80_|sequencer_|DFFE_M2_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), @@ -54751,195 +50614,2625 @@ defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( // Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .combout(\z80_|execute_|ctl_mWrite~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X51_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Location: LCCOMB_X41_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~39_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) +// \z80_|execute_|nextM~11_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ctl_mWrite~3_combout ) - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), + .dataa(\z80_|execute_|ctl_mWrite~3_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .combout(\z80_|execute_|nextM~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Location: LCCOMB_X40_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = (\z80_|execute_|pc_inc_hold~19_combout & ((\z80_|execute_|ctl_mRead~38_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ixy_d~4_combout )))) # (!\z80_|execute_|pc_inc_hold~19_combout & -// (((\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ixy_d~4_combout )))) +// \z80_|execute_|nextM~8_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout +// ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~19_combout ), - .datab(\z80_|execute_|ctl_mRead~38_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ixy_d~4_combout ), + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ixy_d~8_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .combout(\z80_|execute_|nextM~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~8 .lut_mask = 16'h44F4; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Location: LCCOMB_X39_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (((\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_bus_db_oe~7_combout )) # (!\z80_|execute_|pc_inc_hold~40_combout ))) +// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ixy_d~6_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~40_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .dataa(\z80_|execute_|ctl_mWrite~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .combout(\z80_|execute_|nextM~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~9 .lut_mask = 16'h8880; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X46_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( +// Location: LCCOMB_X40_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|execute_|pc_inc_hold~36_combout ) # ((\z80_|execute_|pc_inc_hold~35_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|pc_inc_hold~40_combout ))) +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|ixy_d~9_combout ))) - .dataa(\z80_|execute_|pc_inc_hold~36_combout ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|pc_inc_hold~40_combout ), - .datad(\z80_|execute_|pc_inc_hold~35_combout ), + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datab(\z80_|execute_|nextM~9_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~37_combout ), + .combout(\z80_|execute_|nextM~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( +// Location: LCCOMB_X40_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~38_combout = ((\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|pc_inc_hold~34_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout ))) # (!\z80_|execute_|ctl_inc_cy~39_combout ) +// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|ctl_alu_op_low~32_combout ))) # (!\z80_|execute_|nextM~11_combout ) - .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), - .datab(\z80_|execute_|pc_inc_hold~37_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .dataa(\z80_|execute_|nextM~11_combout ), + .datab(\z80_|execute_|nextM~8_combout ), + .datac(\z80_|execute_|nextM~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~38_combout ), + .combout(\z80_|execute_|nextM~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Location: LCCOMB_X39_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (!\z80_|execute_|pc_inc_hold~38_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) +// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|fMRead~10_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .combout(\z80_|execute_|nextM~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +defparam \z80_|execute_|nextM~15 .lut_mask = 16'h80A0; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Location: LCCOMB_X40_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) +// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|nM1_int~2_combout ), + .dataa(\z80_|execute_|ixy_d~17_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'hDF5F; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ixy_d~8_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|execute_|nextM~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # (\z80_|execute_|nextM~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(\z80_|execute_|nextM~15_combout ), + .datad(\z80_|execute_|nextM~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (!\z80_|execute_|ctl_mWrite~5_combout & \z80_|execute_|setM1~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|setM1~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0F00; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~45_combout ) # (!\z80_|execute_|nextM~2_combout )) # (!\z80_|execute_|setM1~39_combout ))) + + .dataa(\z80_|execute_|setM1~39_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|setM1~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~13_combout ) # (((\z80_|execute_|nextM~5_combout ) # (!\z80_|execute_|ctl_mRead~30_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) + + .dataa(\z80_|execute_|nextM~13_combout ), + .datab(\z80_|execute_|ctl_mWrite~13_combout ), + .datac(\z80_|execute_|ctl_mRead~30_combout ), + .datad(\z80_|execute_|nextM~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N14 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|setM1~52_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N15 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N18 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N19 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N26 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|setM1~52_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N27 +dffeas \z80_|sequencer_|T6 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|T6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|T6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal21~2_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & +// (((!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal21~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'h153F; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal77~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~1_combout ), + .datab(\z80_|execute_|ctl_alu_oe~3_combout ), + .datac(\z80_|pla_decode_|Equal1~6_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~13_combout & (\z80_|interrupts_|test1~2_combout & \z80_|execute_|setM1~12_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~13_combout ), + .datac(\z80_|interrupts_|test1~2_combout ), + .datad(\z80_|execute_|setM1~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'hC000; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0005; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0100; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~43 ( +// Equation(s): +// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~41_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~42_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|setM1~41_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|setM1~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0400; +defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (\z80_|execute_|setM1~40_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|execute_|setM1~40_combout ), + .datad(\z80_|pla_decode_|Equal2~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h20A0; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~14_combout & (\z80_|execute_|setM1~44_combout & \z80_|execute_|setM1~49_combout ))) + + .dataa(\z80_|execute_|setM1~46_combout ), + .datab(\z80_|execute_|setM1~14_combout ), + .datac(\z80_|execute_|setM1~44_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~39_combout )) # (!\z80_|execute_|setM1~40_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & +// ((\z80_|execute_|setM1~39_combout )))) + + .dataa(\z80_|sequencer_|T6~q ), + .datab(\z80_|execute_|setM1~50_combout ), + .datac(\z80_|execute_|setM1~40_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'hCE0A; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~6 ( +// Equation(s): +// \z80_|execute_|setM1~6_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & (\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & +// \z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~6 .lut_mask = 16'hD5C0; +defparam \z80_|execute_|setM1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~7 ( +// Equation(s): +// \z80_|execute_|setM1~7_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|setM1~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~7 .lut_mask = 16'hF333; +defparam \z80_|execute_|setM1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~8 ( +// Equation(s): +// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|fMWrite~3_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~8 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~9 ( +// Equation(s): +// \z80_|execute_|setM1~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF1F0; +defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = ((\z80_|execute_|setM1~8_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~9_combout ))) # (!\z80_|execute_|nextM~2_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~16_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|setM1~8_combout ), + .datad(\z80_|execute_|setM1~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = (\z80_|execute_|setM1~7_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~10_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) + + .dataa(\z80_|execute_|setM1~7_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|setM1~10_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = ((\z80_|execute_|setM1~11_combout ) # ((!\z80_|execute_|setM1~14_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~16_combout ) + + .dataa(\z80_|execute_|setM1~16_combout ), + .datab(\z80_|execute_|setM1~14_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'hFF75; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~18_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & +// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~18_combout )))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hECA0; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|setM1~28_combout )) # (!\z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~54_combout ) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|execute_|setM1~29_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|setM1~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'hF777; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|setM1~9_combout & \z80_|execute_|ctl_mRead~36_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|setM1~9_combout ), + .datac(\z80_|execute_|ctl_mRead~36_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~32_combout ))) + + .dataa(\z80_|execute_|setM1~31_combout ), + .datab(\z80_|execute_|setM1~30_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|setM1~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'hAF0F; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_mRead~12_combout ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & ((!\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|alu_control_|flags_cond_true~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|setM1~25_combout ) # (\z80_|execute_|setM1~26_combout )))) + + .dataa(\z80_|execute_|setM1~25_combout ), + .datab(\z80_|execute_|setM1~26_combout ), + .datac(\z80_|execute_|setM1~24_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|execute_|fMWrite~9_combout & (!\z80_|execute_|ctl_mRead~8_combout & \z80_|execute_|fMWrite~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|execute_|fMWrite~9_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'h0400; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~2_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF1F0; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~53 ( +// Equation(s): +// \z80_|execute_|setM1~53_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~21_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|setM1~21_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~53 .lut_mask = 16'hC888; +defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~22_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # +// ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) + + .dataa(\z80_|execute_|setM1~22_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'h4F44; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|execute_|ctl_flags_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'h08CC; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~18_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) + + .dataa(\z80_|execute_|setM1~18_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'hEAAA; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = ((\z80_|execute_|setM1~19_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|ctl_mWrite~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~3_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datad(\z80_|execute_|setM1~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|setM1~23_combout ) # (\z80_|execute_|setM1~20_combout ))) + + .dataa(\z80_|execute_|setM1~33_combout ), + .datab(\z80_|execute_|setM1~27_combout ), + .datac(\z80_|execute_|setM1~23_combout ), + .datad(\z80_|execute_|setM1~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X41_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~17_combout & (!\z80_|execute_|setM1~34_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|setM1~34_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'h0301; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N24 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N25 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N24 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Equation(s): +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|decode_state_|in_halt~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0050; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( +// Equation(s): +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|decode_state_|in_halt~0_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|pla_decode_|Equal77~1_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|in_halt~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hCECC; +defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N25 +dffeas \z80_|decode_state_|in_halt ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|in_halt~1_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|in_halt~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; +defparam \z80_|decode_state_|in_halt .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_zero_oe~0_combout & (!\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0031; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), .datad(\z80_|pla_decode_|Equal41~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'h010F; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( // Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~68_combout & \z80_|execute_|ctl_inc_cy~69_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ))) +// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - .dataa(\z80_|execute_|ctl_inc_cy~68_combout ), - .datab(\z80_|execute_|ctl_inc_cy~69_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'h8F00; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( // Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # (\z80_|execute_|ctl_inc_cy~80_combout )))) +// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - .dataa(\z80_|execute_|ctl_inc_cy~70_combout ), - .datab(\z80_|execute_|ctl_inc_cy~67_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~80_combout ), + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0F1E; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N20 +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Equation(s): +// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; +defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|zx_keyboard_|keys[1][3]~93_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][3]~93_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N31 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~94_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|zx_keyboard_|keys[0][3]~96_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & +// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~97_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N1 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~98_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N4 +cycloneive_lcell_comb \D[3]~65 ( +// Equation(s): +// \D[3]~65_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][3]~q ), + .cin(gnd), + .combout(\D[3]~65_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~65 .lut_mask = 16'h8CAF; +defparam \D[3]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~99_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~99 .lut_mask = 16'h4040; +defparam \ula_|zx_keyboard_|keys[3][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~100 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~100_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[3][3]~99_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~99_combout & (\ula_|zx_keyboard_|keys[3][3]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), + .datab(\ula_|zx_keyboard_|keys[3][3]~99_combout ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~100_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~100 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][3]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y20_N9 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~100_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'hCCDD; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~133 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~133_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][3]~102_combout & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~133_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~133 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[2][3]~133 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|keys[2][3]~133_combout & (!\ula_|zx_keyboard_|keys[2][3]~101_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~133_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][3]~133_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N3 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~103_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N28 +cycloneive_lcell_comb \D[3]~66 ( +// Equation(s): +// \D[3]~66_combout = (\z80_|address_pins_|abus[11]~19_combout & (((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[3][3]~q ), + .datac(\z80_|address_pins_|abus[10]~24_combout ), + .datad(\ula_|zx_keyboard_|keys[2][3]~q ), + .cin(gnd), + .combout(\D[3]~66_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~66 .lut_mask = 16'hB0BB; +defparam \D[3]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[5][3]~q +// )))) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y19_N23 +dffeas \ula_|zx_keyboard_|keys[5][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|WideOr16~2_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~134 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~134_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), + .datab(\ula_|zx_keyboard_|Selector5~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~134 .lut_mask = 16'hCECC; +defparam \ula_|zx_keyboard_|keys[4][3]~134 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~106_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][3]~134_combout )))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~135 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~135_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~135 .lut_mask = 16'hCDCC; +defparam \ula_|zx_keyboard_|keys[4][3]~135 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|keys[4][3]~135_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & +// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N23 +dffeas \ula_|zx_keyboard_|keys[4][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][3]~108_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N20 +cycloneive_lcell_comb \D[3]~67 ( +// Equation(s): +// \D[3]~67_combout = (\ula_|zx_keyboard_|keys[5][3]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][3]~q & +// (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][3]~q ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), + .cin(gnd), + .combout(\D[3]~67_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~67 .lut_mask = 16'hDD0D; +defparam \D[3]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~61_combout )))) + + .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hA888; +defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & ((!\ula_|zx_keyboard_|keys[0][4]~111_combout ))) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & (\ula_|zx_keyboard_|keys[7][3]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y20_N9 +dffeas \ula_|zx_keyboard_|keys[7][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~109_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~109 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[6][3]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~110_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~109_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~32_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~110 .lut_mask = 16'hF088; +defparam \ula_|zx_keyboard_|keys[6][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~137 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~137_combout = (\ula_|zx_keyboard_|extended~q ) # (((!\ula_|zx_keyboard_|keys[0][0]~15_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~110_combout )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~137 .lut_mask = 16'hBFFF; +defparam \ula_|zx_keyboard_|keys[6][3]~137 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~138 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~138_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~137_combout & ((\ula_|zx_keyboard_|keys[6][3]~q ))) # (!\ula_|zx_keyboard_|keys[6][3]~137_combout & +// (!\ula_|zx_keyboard_|Selector13~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~138 .lut_mask = 16'hF072; +defparam \ula_|zx_keyboard_|keys[6][3]~138 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N29 +dffeas \ula_|zx_keyboard_|keys[6][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # ((!\ula_|zx_keyboard_|keys[6][3]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[6][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \D[3]~68 ( +// Equation(s): +// \D[3]~68_combout = (\D[3]~67_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\D[3]~67_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|key_row~2_combout ), + .cin(gnd), + .combout(\D[3]~68_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~68 .lut_mask = 16'h8C00; +defparam \D[3]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \D[3]~69 ( +// Equation(s): +// \D[3]~69_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~65_combout & (\D[3]~66_combout & \D[3]~68_combout ))) + + .dataa(\D[3]~65_combout ), + .datab(\z80_|address_pins_|abus[0]~16_combout ), + .datac(\D[3]~66_combout ), + .datad(\D[3]~68_combout ), + .cin(gnd), + .combout(\D[3]~69_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~69 .lut_mask = 16'hECCC; +defparam \D[3]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \D[3]~73 ( +// Equation(s): +// \D[3]~73_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\D[3]~73_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~73 .lut_mask = 16'hCCE2; +defparam \D[3]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \D[3]~74 ( +// Equation(s): +// \D[3]~74_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[3]~73_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ))) # (!\D[3]~73_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~73_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datac(\D[3]~73_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .cin(gnd), + .combout(\D[3]~74_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~74 .lut_mask = 16'hF858; +defparam \D[3]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \D[3]~70 ( +// Equation(s): +// \D[3]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~23_combout )) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\D[3]~70_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~70 .lut_mask = 16'hEC64; +defparam \D[3]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \D[3]~71 ( +// Equation(s): +// \D[3]~71_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout $ (((\D[3]~70_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & !\D[3]~70_combout )))) + + .dataa(\z80_|address_pins_|abus[15]~22_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\D[3]~70_combout ), + .cin(gnd), + .combout(\D[3]~71_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~71 .lut_mask = 16'h22D8; +defparam \D[3]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~96_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \D[3]~72 ( +// Equation(s): +// \D[3]~72_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~70_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~70_combout & (!\D[3]~71_combout & +// \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )) # (!\D[3]~70_combout & (\D[3]~71_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\D[3]~70_combout ), + .datac(\D[3]~71_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\D[3]~72_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~72 .lut_mask = 16'h9C98; +defparam \D[3]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \D[3]~108 ( +// Equation(s): +// \D[3]~108_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[3]~74_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[3]~72_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[3]~74_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\D[3]~74_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\D[3]~72_combout ), + .cin(gnd), + .combout(\D[3]~108_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~108 .lut_mask = 16'hDC8C; +defparam \D[3]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \D[3]~95 ( +// Equation(s): +// \D[3]~95_combout = ((\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[3]~69_combout ), + .datab(\Equal2~1_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[3]~108_combout ), + .cin(gnd), + .combout(\D[3]~95_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~95 .lut_mask = 16'hBFB3; +defparam \D[3]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \D[3]~96 ( +// Equation(s): +// \D[3]~96_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [3] & \D[3]~95_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[3]~95_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [3]), + .datad(\D[3]~95_combout ), + .cin(gnd), + .combout(\D[3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~96 .lut_mask = 16'hF511; +defparam \D[3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\D[3]~96_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[3]~96_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[3]~96_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\z80_|bus_control_|db[3]~21_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N7 +dffeas \z80_|data_pins_|dout[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( +// Equation(s): +// \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(\z80_|data_pins_|dout [3]), + .datac(gnd), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hDD00; +defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( +// Equation(s): +// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N1 +dffeas \z80_|ir_|opcode[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[3]~21_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_apin_mux~1_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|execute_|ctl_apin_mux~1_combout ), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h8F8F; +defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N18 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .datab(\z80_|address_latch_|abusz [0]), + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .datad(\z80_|address_latch_|abusz [0]), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y11_N21 +// Location: FF_X31_Y16_N19 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -54958,160 +53251,228 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \D[0]~84 ( +// Location: LCCOMB_X29_Y14_N12 +cycloneive_lcell_comb \D[0]~59 ( // Equation(s): -// \D[0]~84_combout = (\Equal2~0_combout & ((\D[0]~47_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~84 .lut_mask = 16'hFB00; -defparam \D[0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \D[0]~50 ( -// Equation(s): -// \D[0]~50_combout = (\D[0]~84_combout & (((\z80_|data_pins_|dout [0])) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout ))) # (!\D[0]~84_combout & (\D[0]~42_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) - - .dataa(\D[0]~84_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\D[0]~42_combout ), - .cin(gnd), - .combout(\D[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~50 .lut_mask = 16'hF3A2; -defparam \D[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N30 -cycloneive_lcell_comb \D[1]~85 ( -// Equation(s): -// \D[1]~85_combout = (\Equal2~0_combout & ((\z80_|address_pins_|DFFE_apin_latch [0]) # ((\D[1]~28_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \D[0]~59_combout = (\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout ))) .dataa(\Equal2~0_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\D[1]~28_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\D[0]~51_combout ), + .datac(\D[0]~106_combout ), + .datad(gnd), .cin(gnd), - .combout(\D[1]~85_combout ), + .combout(\D[0]~59_combout ), .cout()); // synopsys translate_off -defparam \D[1]~85 .lut_mask = 16'hA8AA; -defparam \D[1]~85 .sum_lutc_input = "datac"; +defparam \D[0]~59 .lut_mask = 16'hD8D8; +defparam \D[0]~59 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \D[1]~51 ( +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \D[0]~60 ( // Equation(s): -// \D[1]~51_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~85_combout ) # (\D[1]~23_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[1]~85_combout ) # (\D[1]~23_combout )))) +// \D[0]~60_combout = (\Equal2~1_combout & (\D[0]~59_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [0]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\D[1]~85_combout ), - .datad(\D[1]~23_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[0]~59_combout ), .cin(gnd), - .combout(\D[1]~51_combout ), + .combout(\D[0]~60_combout ), .cout()); // synopsys translate_off -defparam \D[1]~51 .lut_mask = 16'hDDD0; -defparam \D[1]~51 .sum_lutc_input = "datac"; +defparam \D[0]~60 .lut_mask = 16'hCF45; +defparam \D[0]~60 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N22 -cycloneive_lcell_comb \D[3]~86 ( +// Location: LCCOMB_X32_Y18_N20 +cycloneive_lcell_comb \D[1]~61 ( // Equation(s): -// \D[3]~86_combout = (\Equal2~0_combout & ((\z80_|address_pins_|DFFE_apin_latch [0]) # ((\D[3]~58_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \D[1]~61_combout = (\Equal2~0_combout & (\D[1]~32_combout )) # (!\Equal2~0_combout & ((\D[1]~103_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(\Equal2~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~58_combout ), + .dataa(\Equal2~0_combout ), + .datab(gnd), + .datac(\D[1]~32_combout ), + .datad(\D[1]~103_combout ), .cin(gnd), - .combout(\D[3]~86_combout ), + .combout(\D[1]~61_combout ), .cout()); // synopsys translate_off -defparam \D[3]~86 .lut_mask = 16'hCC8C; -defparam \D[3]~86 .sum_lutc_input = "datac"; +defparam \D[1]~61 .lut_mask = 16'hF5A0; +defparam \D[1]~61 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N14 -cycloneive_lcell_comb \D[3]~59 ( +// Location: LCCOMB_X32_Y18_N22 +cycloneive_lcell_comb \D[1]~62 ( // Equation(s): -// \D[3]~59_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~86_combout ) # (\D[3]~53_combout )))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[3]~86_combout ) # (\D[3]~53_combout )))) +// \D[1]~62_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~61_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~61_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [1]), + .datad(\D[1]~61_combout ), + .cin(gnd), + .combout(\D[1]~62_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~62 .lut_mask = 16'hF531; +defparam \D[1]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \D[2]~63 ( +// Equation(s): +// \D[2]~63_combout = (\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout ))) + + .dataa(\Equal2~0_combout ), + .datab(gnd), + .datac(\D[2]~104_combout ), + .datad(\D[2]~105_combout ), + .cin(gnd), + .combout(\D[2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~63 .lut_mask = 16'hF5A0; +defparam \D[2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \D[2]~64 ( +// Equation(s): +// \D[2]~64_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~63_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[2]~63_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[2]~63_combout ), + .cin(gnd), + .combout(\D[2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~64 .lut_mask = 16'hAF23; +defparam \D[2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \D[3]~75 ( +// Equation(s): +// \D[3]~75_combout = (\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout ))) + + .dataa(\D[3]~69_combout ), + .datab(gnd), + .datac(\Equal2~0_combout ), + .datad(\D[3]~108_combout ), + .cin(gnd), + .combout(\D[3]~75_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~75 .lut_mask = 16'hAFA0; +defparam \D[3]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \D[3]~76 ( +// Equation(s): +// \D[3]~76_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~75_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[3]~75_combout ) # (!\Equal2~1_combout )))) .dataa(\z80_|data_pins_|dout [3]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[3]~86_combout ), - .datad(\D[3]~53_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[3]~75_combout ), .cin(gnd), - .combout(\D[3]~59_combout ), + .combout(\D[3]~76_combout ), .cout()); // synopsys translate_off -defparam \D[3]~59 .lut_mask = 16'hBBB0; -defparam \D[3]~59 .sum_lutc_input = "datac"; +defparam \D[3]~76 .lut_mask = 16'hAF23; +defparam \D[3]~76 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \D[4]~87 ( +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \D[4]~82 ( // Equation(s): -// \D[4]~87_combout = (\Equal2~0_combout & ((\D[4]~66_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \D[4]~82_combout = (\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout ))) - .dataa(\D[4]~66_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\Equal2~0_combout ), + .dataa(\Equal2~0_combout ), + .datab(\D[4]~81_combout ), + .datac(gnd), + .datad(\D[4]~109_combout ), .cin(gnd), - .combout(\D[4]~87_combout ), + .combout(\D[4]~82_combout ), .cout()); // synopsys translate_off -defparam \D[4]~87 .lut_mask = 16'hFB00; -defparam \D[4]~87 .sum_lutc_input = "datac"; +defparam \D[4]~82 .lut_mask = 16'hDD88; +defparam \D[4]~82 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N4 -cycloneive_lcell_comb \D[4]~67 ( +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \D[4]~83 ( // Equation(s): -// \D[4]~67_combout = (\z80_|data_pins_|dout [4] & (((\D[4]~87_combout ) # (\D[4]~61_combout )))) # (!\z80_|data_pins_|dout [4] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[4]~87_combout ) # (\D[4]~61_combout )))) +// \D[4]~83_combout = (\Equal2~1_combout & (\D[4]~82_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\D[4]~87_combout ), - .datad(\D[4]~61_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[4]~82_combout ), .cin(gnd), - .combout(\D[4]~67_combout ), + .combout(\D[4]~83_combout ), .cout()); // synopsys translate_off -defparam \D[4]~67 .lut_mask = 16'hBBB0; -defparam \D[4]~67 .sum_lutc_input = "datac"; +defparam \D[4]~83 .lut_mask = 16'hCF45; +defparam \D[4]~83 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N2 +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \D[6]~92 ( +// Equation(s): +// \D[6]~92_combout = (\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout )) + + .dataa(gnd), + .datab(\Equal2~0_combout ), + .datac(\D[6]~111_combout ), + .datad(\D[6]~86_combout ), + .cin(gnd), + .combout(\D[6]~92_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~92 .lut_mask = 16'hFC30; +defparam \D[6]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \D[6]~93 ( +// Equation(s): +// \D[6]~93_combout = (\Equal2~1_combout & (\D[6]~92_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [6]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [6]), + .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datad(\D[6]~92_combout ), + .cin(gnd), + .combout(\D[6]~93_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~93 .lut_mask = 16'hCF45; +defparam \D[6]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y17_N0 cycloneive_lcell_comb \z80_|nM1_int~3 ( // Equation(s): // \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) - .dataa(\z80_|execute_|setM1~52_combout ), + .dataa(gnd), .datab(\z80_|sequencer_|DFFE_T1_ff~q ), .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), + .datad(\z80_|execute_|setM1~52_combout ), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hA8A8; +defparam \z80_|nM1_int~3 .lut_mask = 16'hFC00; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N3 +// Location: FF_X43_Y17_N1 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -55130,7 +53491,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y16_N24 +// Location: LCCOMB_X43_Y17_N30 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -55147,7 +53508,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y16_N25 +// Location: FF_X43_Y17_N31 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -55166,7 +53527,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X50_Y16_N11 +// Location: FF_X43_Y17_N25 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -55185,7 +53546,7 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N10 +// Location: LCCOMB_X43_Y17_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) @@ -55202,15 +53563,15 @@ defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X50_Y16_N14 +// Location: LCCOMB_X43_Y17_N2 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nRD_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nMREQ_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nRD_out~0_combout ))) .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datad(\z80_|memory_ifc_|nMREQ_out~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), .cout()); @@ -55219,7 +53580,20 @@ defparam \z80_|memory_ifc_|nMREQ_out~1 .lut_mask = 16'h0001; defparam \z80_|memory_ifc_|nMREQ_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N10 +// Location: CLKCTRL_G19 +cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk )); +// synopsys translate_off +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock"; +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( // Equation(s): // \ula_|i2c_loader_|state.Idle~feeder_combout = VCC @@ -55236,7 +53610,7 @@ defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N12 +// Location: LCCOMB_X4_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -55253,7 +53627,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N13 +// Location: FF_X4_Y24_N1 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -55272,14 +53646,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X4_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) - .dataa(\ula_|i2c_loader_|divider [0]), - .datab(\ula_|i2c_loader_|divider [1]), + .dataa(\ula_|i2c_loader_|divider [1]), + .datab(\ula_|i2c_loader_|divider [0]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -55290,7 +53664,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N15 +// Location: FF_X4_Y24_N11 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -55309,25 +53683,25 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N16 +// Location: LCCOMB_X4_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) // \ula_|i2c_loader_|divider[2]~8 = CARRY((!\ula_|i2c_loader_|divider[1]~6 ) # (!\ula_|i2c_loader_|divider [2])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [2]), + .dataa(\ula_|i2c_loader_|divider [2]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[1]~6 ), .combout(\ula_|i2c_loader_|divider[2]~7_combout ), .cout(\ula_|i2c_loader_|divider[2]~8 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N17 +// Location: FF_X4_Y24_N13 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -55346,7 +53720,7 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N18 +// Location: LCCOMB_X4_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) @@ -55364,7 +53738,7 @@ defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hC30C; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N19 +// Location: FF_X4_Y24_N15 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -55383,7 +53757,7 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N20 +// Location: LCCOMB_X4_Y24_N16 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) @@ -55401,7 +53775,7 @@ defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N21 +// Location: FF_X4_Y24_N17 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -55420,24 +53794,24 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N22 +// Location: LCCOMB_X4_Y24_N18 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): -// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider [5] $ (!\ula_|i2c_loader_|divider[4]~12 ) +// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) - .dataa(\ula_|i2c_loader_|divider [5]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|i2c_loader_|divider [5]), .cin(\ula_|i2c_loader_|divider[4]~12 ), .combout(\ula_|i2c_loader_|divider[5]~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N23 +// Location: FF_X4_Y24_N19 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -55456,14 +53830,14 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N2 +// Location: LCCOMB_X4_Y24_N22 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0]) +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [1]) - .dataa(\ula_|i2c_loader_|divider [0]), - .datab(\ula_|i2c_loader_|divider [3]), - .datac(\ula_|i2c_loader_|divider [1]), + .dataa(\ula_|i2c_loader_|divider [1]), + .datab(\ula_|i2c_loader_|divider [0]), + .datac(\ula_|i2c_loader_|divider [3]), .datad(\ula_|i2c_loader_|divider [2]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), @@ -55473,24 +53847,24 @@ defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N28 +// Location: LCCOMB_X4_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [5])) # (!\ula_|i2c_loader_|divider [4]) +// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [4]), - .datac(\ula_|i2c_loader_|divider [5]), - .datad(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datab(\ula_|i2c_loader_|divider [5]), + .datac(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datad(\ula_|i2c_loader_|divider [4]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hFF3F; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hF3FF; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N11 +// Location: FF_X1_Y23_N1 dffeas \ula_|i2c_loader_|state.Idle ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), @@ -55509,7 +53883,7 @@ defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N2 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( // Equation(s): // \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) @@ -55526,7 +53900,7 @@ defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N3 +// Location: FF_X1_Y23_N5 dffeas \ula_|i2c_loader_|phase[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~0_combout ), @@ -55545,24 +53919,24 @@ defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N8 +// Location: LCCOMB_X1_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( // Equation(s): -// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [1] $ (\ula_|i2c_loader_|phase [0]))) +// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) - .dataa(\ula_|i2c_loader_|state.Idle~q ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|phase~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h0AA0; +defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N9 +// Location: FF_X1_Y23_N15 dffeas \ula_|i2c_loader_|phase[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~1_combout ), @@ -55581,558 +53955,24 @@ defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( -// Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux42~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [0] $ (!\ula_|i2c_loader_|nbit [1])) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|nbit [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hB7B7; -defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|nbyte [0])) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|nbyte [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h0202; -defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|phase [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y23_N1 -cycloneive_io_ibuf \I2C_SDAT~input ( - .i(I2C_SDAT), - .ibar(gnd), - .o(\I2C_SDAT~input_o )); -// synopsys translate_off -defparam \I2C_SDAT~input .bus_hold = "false"; -defparam \I2C_SDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|thisbyte[0]~7_combout & ((\ula_|i2c_loader_|nbyte[0]~1_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hCAC0; -defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h0C00; -defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y23_N5 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [1] & (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbyte [0])) - - .dataa(\ula_|i2c_loader_|nbyte [1]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(gnd), - .datad(\ula_|i2c_loader_|nbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0011; -defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; -defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|state.Done~0_combout ) # (\ula_|i2c_loader_|nbit[0]~2_combout )))) - - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|state.Done~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; -defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|Mux42~0_combout & \ula_|i2c_loader_|state.Idle~q ))) - - .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|Mux42~0_combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h1000; -defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N17 -dffeas \ula_|i2c_loader_|nbit[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [0] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) - - .dataa(\ula_|i2c_loader_|nbit [0]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~0_combout = (!\ula_|i2c_loader_|state.Pause~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Start~q ))) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'h0001; -defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Ack~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Done~0_combout ), - .datab(\ula_|i2c_loader_|state.Ack~0_combout ), - .datac(\ula_|i2c_loader_|Mux42~0_combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hB0FF; -defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~2_combout = (\ula_|i2c_loader_|state.Ack~1_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # -// (!\ula_|i2c_loader_|state.Ack~1_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|state.Ack~1_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~2 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Ack~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N31 -dffeas \ula_|i2c_loader_|state.Ack ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Ack~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Ack~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( -// Equation(s): -// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [1]) # (\ula_|i2c_loader_|nbyte [0]))) - - .dataa(\ula_|i2c_loader_|nbyte [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|nbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hF0A0; -defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( -// Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|state~24_combout & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1])) - - .dataa(\ula_|i2c_loader_|state~24_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; -defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( -// Equation(s): -// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|phase [1]) # (!\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|phase [0]) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|state.Done~1_combout ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h3FFF; -defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~27_combout ))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~26_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state~26_combout ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state~27_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Data~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hFC0C; -defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N21 -dffeas \ula_|i2c_loader_|state.Data ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Data~0_combout ), - .asdata(\ula_|i2c_loader_|Mux42~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Data~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Data .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N26 +// Location: LCCOMB_X3_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( // Equation(s): // \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|nbit [0]) # (!\ula_|i2c_loader_|state.Data~q ) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(gnd), .datac(\ula_|i2c_loader_|nbit [0]), .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|nbit~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h3F3F; +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h5F5F; defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N27 -dffeas \ula_|i2c_loader_|nbit[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|nbit [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|nbit [2]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF3B7; -defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N21 -dffeas \ula_|i2c_loader_|nbit[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|nbit [0]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0003; -defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|state.Pause~q & (((!\ula_|i2c_loader_|state.Done~1_combout & \ula_|i2c_loader_|state.Data~q )))) # (!\ula_|i2c_loader_|state.Pause~q & ((\ula_|i2c_loader_|scl_out~0_combout ) # -// ((!\ula_|i2c_loader_|state.Done~1_combout & \ula_|i2c_loader_|state.Data~q )))) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|scl_out~0_combout ), - .datac(\ula_|i2c_loader_|state.Done~1_combout ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h4F44; -defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Done~2_combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h8AFF; -defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|phase [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5CFC; -defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N10 +// Location: LCCOMB_X2_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) @@ -56150,332 +53990,119 @@ defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Location: LCCOMB_X1_Y24_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|phase [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Mux42~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) .dataa(\ula_|i2c_loader_|nbyte [0]), .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; -defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y23_N11 -dffeas \ula_|i2c_loader_|thisbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), - .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h5A5F; -defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N13 -dffeas \ula_|i2c_loader_|thisbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) -// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), - .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; -defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N15 -dffeas \ula_|i2c_loader_|thisbyte[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), - .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N17 -dffeas \ula_|i2c_loader_|thisbyte[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte[3]~15 $ (!\ula_|i2c_loader_|thisbyte [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), - .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hF00F; -defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y23_N19 -dffeas \ula_|i2c_loader_|thisbyte[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Pause~0_combout ), - .datac(\ula_|i2c_loader_|Equal2~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h0CCC; -defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Pause~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~1_combout ))))) # -// (!\ula_|i2c_loader_|state.Pause~2_combout & (((\ula_|i2c_loader_|state.Pause~q )))) - - .dataa(\ula_|i2c_loader_|state.Pause~2_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Pause~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N7 -dffeas \ula_|i2c_loader_|state.Pause ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Pause~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Pause~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( -// Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # -// (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; -defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N17 -dffeas \ula_|i2c_loader_|state.Start ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state~25_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Start~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Start .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [1] $ (!\ula_|i2c_loader_|nbyte [0])))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hECCE; +defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hFF84; defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N31 +// Location: LCCOMB_X1_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N1 +cycloneive_io_ibuf \I2C_SDAT~input ( + .i(I2C_SDAT), + .ibar(gnd), + .o(\I2C_SDAT~input_o )); +// synopsys translate_off +defparam \I2C_SDAT~input .bus_hold = "false"; +defparam \I2C_SDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hEFE0; +defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; +defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~3_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbyte[0]~2_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h3000; +defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N29 dffeas \ula_|i2c_loader_|nbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbyte~4_combout ), @@ -56494,42 +54121,42 @@ defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 +// Location: LCCOMB_X2_Y24_N18 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [1] & (\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|nbyte [0])) +// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) - .dataa(\ula_|i2c_loader_|nbyte [1]), - .datab(gnd), + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|nbyte [0]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|state.Stop~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0050; +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h1010; defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N24 +// Location: LCCOMB_X1_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( // Equation(s): -// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Stop~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))))) # -// (!\ula_|i2c_loader_|Mux42~0_combout & (((\ula_|i2c_loader_|state.Stop~q )))) +// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))) # +// (!\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~q )))) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), .datac(\ula_|i2c_loader_|state.Stop~q ), .datad(\ula_|i2c_loader_|state.Stop~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Stop~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF4B0; defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N25 +// Location: FF_X1_Y24_N3 dffeas \ula_|i2c_loader_|state.Stop ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Stop~1_combout ), @@ -56548,16 +54175,763 @@ defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Location: LCCOMB_X1_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Ack~q ))) - .dataa(gnd), + .dataa(\ula_|i2c_loader_|state.Start~q ), .datab(\ula_|i2c_loader_|state.Stop~q ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; +defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|nbit [2]), + .datad(\ula_|i2c_loader_|nbit [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N1 +dffeas \ula_|i2c_loader_|nbit[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [0]))) + + .dataa(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|nbit [2]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Idle~0_combout ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|state.Done~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hAF2F; +defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), .datac(\ula_|i2c_loader_|state.Ack~q ), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N31 +dffeas \ula_|i2c_loader_|state.Ack ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Ack~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Ack~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hEFE0; +defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N15 +dffeas \ula_|i2c_loader_|thisbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), + .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N17 +dffeas \ula_|i2c_loader_|thisbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) +// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), + .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N19 +dffeas \ula_|i2c_loader_|thisbyte[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), + .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N21 +dffeas \ula_|i2c_loader_|thisbyte[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Stop~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5FCC; +defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), + .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X2_Y23_N23 +dffeas \ula_|i2c_loader_|thisbyte[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|Equal2~0_combout ), + .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h30F0; +defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & +// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Done~1_combout )))) + + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Done~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0ACE; +defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Done~2_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hC4FF; +defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~2_combout & (\ula_|i2c_loader_|state.Pause~1_combout )) # +// (!\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) + + .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Pause~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hE2F0; +defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N23 +dffeas \ula_|i2c_loader_|state.Pause ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Pause~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Pause~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( +// Equation(s): +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; +defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N31 +dffeas \ula_|i2c_loader_|state.Start ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Start~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Start .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; +defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N11 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0005; +defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|phase [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; +defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) + + .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Done~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; +defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) + + .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0400; +defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N3 +dffeas \ula_|i2c_loader_|nbit[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF55F; +defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N13 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & !\ula_|i2c_loader_|nbit [0])) + + .dataa(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|nbit [2]), + .datac(gnd), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( +// Equation(s): +// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Done~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Done~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; +defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( +// Equation(s): +// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|nbyte [1]), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hE0E0; +defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( +// Equation(s): +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; +defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) + + .dataa(\ula_|i2c_loader_|state~27_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state~26_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Data~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hAFA0; +defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N29 +dffeas \ula_|i2c_loader_|state.Data ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Data~0_combout ), + .asdata(\ula_|i2c_loader_|Mux42~0_combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2c_loader_|state.Start~q ), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Data~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Data .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Stop~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|state.Stop~q ), + .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~0_combout ), .cout()); // synopsys translate_off @@ -56565,7 +54939,7 @@ defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N9 +// Location: FF_X1_Y23_N13 dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|scl_out~2_combout ), @@ -56584,38 +54958,38 @@ defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N28 +// Location: LCCOMB_X1_Y23_N16 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ ((!\ula_|i2c_loader_|state.Start~q )))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # -// ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q & \ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # +// ((\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|scl_out~_Duplicate_1_q )))) - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hD7C2; +defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hBA74; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N8 +// Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|scl_out~1_combout ))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|scl_out~1_combout )) +// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & ((\ula_|i2c_loader_|state.Start~q ))) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|state.Start~q )) .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|scl_out~1_combout ), + .datab(\ula_|i2c_loader_|scl_out~1_combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hF005; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hCC11; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56638,7 +55012,7 @@ defparam \ula_|i2c_loader_|scl_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out .power_up = "high"; // synopsys translate_on -// Location: FF_X1_Y23_N31 +// Location: FF_X1_Y23_N23 dffeas \ula_|i2c_loader_|sda_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|sda_out~4_combout ), @@ -56657,88 +55031,156 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N6 +// Location: LCCOMB_X3_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state.Start~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; +defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte [0] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [2]), .cin(gnd), .combout(\ula_|i2c_loader_|Mux35~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h20A0; +defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h2A00; defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X2_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h001A; +defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h00F0; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|shiftreg~14_combout ))) + + .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~14_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hAABA; +defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: LCCOMB_X3_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3])) +// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0030; +defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0300; defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 +// Location: LCCOMB_X1_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [0] & !\ula_|i2c_loader_|phase [1])) +// \ula_|i2c_loader_|shiftreg[0]~6_combout = (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Data~q )) - .dataa(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|phase [1]), .datab(gnd), .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h00A0; +defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h5000; defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N26 +// Location: LCCOMB_X1_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state~24_combout ) # (\ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) - .dataa(\ula_|i2c_loader_|state~24_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|Mux42~0_combout ), - .datad(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .datad(\ula_|i2c_loader_|state~24_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFFE0; +defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFCF8; defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N20 +// Location: LCCOMB_X1_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|shiftreg[0]~7_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q )) +// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|shiftreg[0]~7_combout )) - .dataa(\ula_|i2c_loader_|shiftreg[0]~7_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h2200; +defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h0C00; defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56761,54 +55203,37 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; -defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N24 +// Location: LCCOMB_X2_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [3]))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte [2]))) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2])))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [4]), + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [2]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hA010; +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hC010; defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N2 +// Location: LCCOMB_X3_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~21_combout ), + .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), + .datab(\ula_|i2c_loader_|shiftreg~4_combout ), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~22_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'hAA08; +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h88C8; defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56829,33 +55254,33 @@ defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N10 +// Location: LCCOMB_X2_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|phase [1]))))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q -// ) # (\ula_|i2c_loader_|state~24_combout )))) +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q +// & (!\ula_|i2c_loader_|state.Start~q ))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state~24_combout ), - .datad(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state~24_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hDC22; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hA6A4; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N24 +// Location: LCCOMB_X2_Y24_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|shiftreg[6]~10_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ))) +// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|shiftreg[6]~10_combout ))) - .dataa(\ula_|i2c_loader_|shiftreg[6]~10_combout ), + .dataa(\ula_|i2c_loader_|phase [0]), .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .cout()); @@ -56883,41 +55308,41 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N20 +// Location: LCCOMB_X2_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) +// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [1]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [3])))) - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(\ula_|i2c_loader_|thisbyte [4]), + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h4070; +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h10B0; defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N22 +// Location: LCCOMB_X3_Y23_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0])) # (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|shiftreg~18_combout )))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .dataa(\ula_|i2c_loader_|thisbyte [0]), .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~18_combout ), + .datac(\ula_|i2c_loader_|shiftreg~18_combout ), + .datad(\ula_|i2c_loader_|shiftreg~4_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h7F5D; +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h74FF; defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N16 +// Location: LCCOMB_X3_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) @@ -56934,7 +55359,7 @@ defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hAF00; defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N17 +// Location: FF_X3_Y23_N3 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~20_combout ), @@ -56953,58 +55378,41 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|thisbyte [2]), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0F00; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N0 +// Location: LCCOMB_X2_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(\ula_|i2c_loader_|thisbyte [4]), - .datac(\ula_|i2c_loader_|thisbyte [2]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h04F4; +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h10BA; defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N2 +// Location: LCCOMB_X3_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|shiftreg~14_combout & ((\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [3] & ((!\ula_|i2c_loader_|shiftreg~14_combout )))) - .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), - .datab(\ula_|i2c_loader_|shiftreg~16_combout ), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|shiftreg~16_combout ), + .datad(\ula_|i2c_loader_|shiftreg~14_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hC5C0; +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hA0E4; defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 +// Location: LCCOMB_X3_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg~17_combout )))) @@ -57021,7 +55429,7 @@ defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hC5C0; defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X3_Y23_N7 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~26_combout ), @@ -57040,58 +55448,24 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [4])) # (!\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4]))))) - - .dataa(\ula_|i2c_loader_|thisbyte [1]), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h0310; -defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|shiftreg~14_combout & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), - .datab(\ula_|i2c_loader_|shiftreg~13_combout ), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hCCDC; -defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N4 +// Location: LCCOMB_X2_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|shiftreg~15_combout )))) +// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|shiftreg [3]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~15_combout ), + .dataa(\ula_|i2c_loader_|shiftreg~15_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|shiftreg [3]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hCFCA; +defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE32; defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N5 +// Location: FF_X2_Y23_N1 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~25_combout ), @@ -57110,7 +55484,7 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N8 +// Location: LCCOMB_X2_Y24_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) @@ -57127,7 +55501,7 @@ defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hEE22; defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N9 +// Location: FF_X2_Y24_N5 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~12_combout ), @@ -57146,24 +55520,24 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 +// Location: LCCOMB_X3_Y23_N18 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( // Equation(s): // \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) - .dataa(\ula_|i2c_loader_|shiftreg [5]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg [5]), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|Mux35~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hAFA0; +defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hCFC0; defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N11 +// Location: FF_X3_Y23_N19 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~9_combout ), @@ -57182,7 +55556,7 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N28 +// Location: LCCOMB_X3_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( // Equation(s): // \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) @@ -57199,7 +55573,7 @@ defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N29 +// Location: FF_X3_Y23_N5 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), @@ -57218,21 +55592,21 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N26 +// Location: LCCOMB_X2_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|shiftreg [7]))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|state.Data~q & // (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|shiftreg [7]), - .datab(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|shiftreg [7]), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hB8F0; +defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hF870; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57241,67 +55615,67 @@ cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): // \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|sda_out~0_combout ), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|sda_out~0_combout ), .datad(\I2C_SDAT~input_o ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hA0A8; +defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hC0E0; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N4 +// Location: LCCOMB_X1_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h5054; +defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N10 +// Location: LCCOMB_X1_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|sda_out~1_combout )))) # (!\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|phase [0] -// & ((!\ula_|i2c_loader_|sda_out~1_combout ))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )))) +// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase +// [0] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|sda_out~1_combout )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'h8EBA; +defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2AE; defparam \ula_|i2c_loader_|sda_out~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N30 +// Location: LCCOMB_X1_Y23_N22 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~4 ( // Equation(s): // \ula_|i2c_loader_|sda_out~4_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|sda_out~2_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & ((\ula_|i2c_loader_|sda_out~3_combout )))) - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|scl_out~0_combout ), .datac(\ula_|i2c_loader_|sda_out~2_combout ), .datad(\ula_|i2c_loader_|sda_out~3_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1D0C; +defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1B0A; defparam \ula_|i2c_loader_|sda_out~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57324,6 +55698,42 @@ defparam \ula_|i2c_loader_|sda_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out .power_up = "high"; // synopsys translate_on +// Location: LCCOMB_X27_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|mclk_r~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N17 +dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|mclk_r~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + // Location: DDIOOUTCELL_X20_Y34_N25 dffeas \ula_|i2s_intf_|mclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -57343,6 +55753,612 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X29_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) + + .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add0~1_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) +// \ula_|i2s_intf_|Add0~3 = CARRY((!\ula_|i2s_intf_|lrdivider [1] & !\ula_|i2s_intf_|Add0~1_cout )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~1_cout ), + .combout(\ula_|i2s_intf_|Add0~2_combout ), + .cout(\ula_|i2s_intf_|Add0~3 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y23_N29 +dffeas \ula_|i2s_intf_|lrdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) +// \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) + + .dataa(\ula_|i2s_intf_|lrdivider [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~3 ), + .combout(\ula_|i2s_intf_|Add0~4_combout ), + .cout(\ula_|i2s_intf_|Add0~5 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~4_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y23_N7 +dffeas \ula_|i2s_intf_|lrdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) +// \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~5 ), + .combout(\ula_|i2s_intf_|Add0~6_combout ), + .cout(\ula_|i2s_intf_|Add0~7 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N7 +dffeas \ula_|i2s_intf_|lrdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) +// \ula_|i2s_intf_|Add0~9 = CARRY((\ula_|i2s_intf_|lrdivider [4]) # (!\ula_|i2s_intf_|Add0~7 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~7 ), + .combout(\ula_|i2s_intf_|Add0~8_combout ), + .cout(\ula_|i2s_intf_|Add0~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y23_N5 +dffeas \ula_|i2s_intf_|lrdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) +// \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~9 ), + .combout(\ula_|i2s_intf_|Add0~10_combout ), + .cout(\ula_|i2s_intf_|Add0~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~10_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[5]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y23_N3 +dffeas \ula_|i2s_intf_|lrdivider[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) + + .dataa(\ula_|i2s_intf_|lrdivider [2]), + .datab(\ula_|i2s_intf_|lrdivider [4]), + .datac(\ula_|i2s_intf_|lrdivider [3]), + .datad(\ula_|i2s_intf_|lrdivider [5]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) +// \ula_|i2s_intf_|Add0~13 = CARRY((!\ula_|i2s_intf_|Add0~11 ) # (!\ula_|i2s_intf_|lrdivider [6])) + + .dataa(\ula_|i2s_intf_|lrdivider [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~11 ), + .combout(\ula_|i2s_intf_|Add0~12_combout ), + .cout(\ula_|i2s_intf_|Add0~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~12_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N27 +dffeas \ula_|i2s_intf_|lrdivider[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) +// \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) + + .dataa(\ula_|i2s_intf_|lrdivider [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~13 ), + .combout(\ula_|i2s_intf_|Add0~14_combout ), + .cout(\ula_|i2s_intf_|Add0~15 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y23_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~14_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y23_N5 +dffeas \ula_|i2s_intf_|lrdivider[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) +// \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) + + .dataa(\ula_|i2s_intf_|lrdivider [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add0~15 ), + .combout(\ula_|i2s_intf_|Add0~16_combout ), + .cout(\ula_|i2s_intf_|Add0~17 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h5AAF; +defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Add0~16_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0C0C; +defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N17 +dffeas \ula_|i2s_intf_|lrdivider[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( +// Equation(s): +// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|lrdivider [9]), + .cin(\ula_|i2s_intf_|Add0~17 ), + .combout(\ula_|i2s_intf_|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; +defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y23_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( +// Equation(s): +// \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~18_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y23_N25 +dffeas \ula_|i2s_intf_|lrdivider[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrdivider [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal0~0_combout = (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [6] & \ula_|i2s_intf_|lrdivider [7]))) + + .dataa(\ula_|i2s_intf_|lrdivider [8]), + .datab(\ula_|i2s_intf_|lrdivider [9]), + .datac(\ula_|i2s_intf_|lrdivider [6]), + .datad(\ula_|i2s_intf_|lrdivider [7]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h4000; +defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y23_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( +// Equation(s): +// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) + + .dataa(\ula_|i2s_intf_|Equal0~1_combout ), + .datab(\ula_|i2s_intf_|lrdivider [1]), + .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( +// Equation(s): +// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N25 +dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; +defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X16_Y34_N18 dffeas \ula_|i2s_intf_|lrclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -57381,6 +56397,596 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X31_Y22_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] +// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .cout(\ula_|i2s_intf_|bitcount[0]~6 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; +defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N11 +dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bclk_r~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF0FC; +defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N1 +dffeas \ula_|i2s_intf_|bitcount[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) +// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[0]~6 ), + .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .cout(\ula_|i2s_intf_|bitcount[1]~8 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N3 +dffeas \ula_|i2s_intf_|bitcount[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) +// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[1]~8 ), + .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .cout(\ula_|i2s_intf_|bitcount[2]~10 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N5 +dffeas \ula_|i2s_intf_|bitcount[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) +// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) + + .dataa(\ula_|i2s_intf_|bitcount [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[2]~10 ), + .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .cout(\ula_|i2s_intf_|bitcount[3]~12 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; +defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N7 +dffeas \ula_|i2s_intf_|bitcount[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) + + .dataa(\ula_|i2s_intf_|bitcount [3]), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(\ula_|i2s_intf_|bitcount [2]), + .datad(\ula_|i2s_intf_|bitcount [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [4]), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2s_intf_|bitcount[3]~12 ), + .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; +defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y22_N9 +dffeas \ula_|i2s_intf_|bitcount[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add2~7_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) +// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~7_cout ), + .combout(\ula_|i2s_intf_|Add2~8_combout ), + .cout(\ula_|i2s_intf_|Add2~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; +defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|Add2~8_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1300; +defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N13 +dffeas \ula_|i2s_intf_|bdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) +// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) + + .dataa(\ula_|i2s_intf_|bdivider [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~9 ), + .combout(\ula_|i2s_intf_|Add2~10_combout ), + .cout(\ula_|i2s_intf_|Add2~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Add2~10_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0203; +defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N17 +dffeas \ula_|i2s_intf_|bdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) +// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~11 ), + .combout(\ula_|i2s_intf_|Add2~12_combout ), + .cout(\ula_|i2s_intf_|Add2~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~19_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~12_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|Add2~12_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h1300; +defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N3 +dffeas \ula_|i2s_intf_|bdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(\ula_|i2s_intf_|Add2~13 ), + .combout(\ula_|i2s_intf_|Add2~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; +defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Add2~14_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; +defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N19 +dffeas \ula_|i2s_intf_|bdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & \ula_|i2s_intf_|bdivider [4]))) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(\ula_|i2s_intf_|bdivider [2]), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h1000; +defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~1 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[4]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8A00; +defparam \ula_|i2s_intf_|shiftreg[4]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y22_N13 +dffeas \ula_|i2s_intf_|bdivider[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hF000; +defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h30CF; +defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|bclk_r~0_combout ), + .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00D8; +defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X14_Y34_N18 dffeas \ula_|i2s_intf_|bclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -57400,16 +57006,781 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y13_N29 -dffeas \ula_|pcm_outl[14] ( +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( +// Equation(s): +// \ula_|pcm_outl[13]~feeder_combout = \D[3]~96_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[3]~96_combout ), + .cin(gnd), + .combout(\ula_|pcm_outl[13]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; +defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N2 +cycloneive_lcell_comb \ula_|always0~2 ( +// Equation(s): +// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|always0~2 .lut_mask = 16'h2020; +defparam \ula_|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \ula_|always0~3 ( +// Equation(s): +// \ula_|always0~3_combout = (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|always0~2_combout ), + .cin(gnd), + .combout(\ula_|always0~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|always0~3 .lut_mask = 16'h4000; +defparam \ula_|always0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N25 +dffeas \ula_|pcm_outl[13] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[4]~79_combout ), + .d(\ula_|pcm_outl[13]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|always0~1_combout ), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|pcm_outl [13]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|Equal1~1_combout ), + .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h008A; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y34_N22 +cycloneive_io_ibuf \AUD_ADCDAT~input ( + .i(AUD_ADCDAT), + .ibar(gnd), + .o(\AUD_ADCDAT~input_o )); +// synopsys translate_off +defparam \AUD_ADCDAT~input .bus_hold = "false"; +defparam \AUD_ADCDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # +// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) + + .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [0]), + .datad(\AUD_ADCDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N21 +dffeas \ula_|i2s_intf_|shiftreg[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~18_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~2 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFCF0; +defparam \ula_|i2s_intf_|shiftreg[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N27 +dffeas \ula_|i2s_intf_|shiftreg[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [1] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [1]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N25 +dffeas \ula_|i2s_intf_|shiftreg[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N19 +dffeas \ula_|i2s_intf_|shiftreg[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~15_combout = (\ula_|i2s_intf_|shiftreg [3] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [3]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N1 +dffeas \ula_|i2s_intf_|shiftreg[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~15_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [4]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N11 +dffeas \ula_|i2s_intf_|shiftreg[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~14_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~13_combout = (\ula_|i2s_intf_|shiftreg [5] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(\ula_|i2s_intf_|shiftreg [5]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N17 +dffeas \ula_|i2s_intf_|shiftreg[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~13_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [6]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N31 +dffeas \ula_|i2s_intf_|shiftreg[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [7]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N29 +dffeas \ula_|i2s_intf_|shiftreg[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~11_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~10_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [8]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N23 +dffeas \ula_|i2s_intf_|shiftreg[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~10_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [9]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N13 +dffeas \ula_|i2s_intf_|shiftreg[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~9_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(\ula_|i2s_intf_|shiftreg [10]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N3 +dffeas \ula_|i2s_intf_|shiftreg[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~8_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|shiftreg [11]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N9 +dffeas \ula_|i2s_intf_|shiftreg[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~7_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( +// Equation(s): +// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # +// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) + + .dataa(\ula_|i2s_intf_|shiftreg [14]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N31 +dffeas \ula_|i2s_intf_|PCM_INR[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|PCM_INR [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( +// Equation(s): +// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # +// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) + + .dataa(\ula_|i2s_intf_|shiftreg [14]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|PCM_INL [14]), + .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N29 +dffeas \ula_|i2s_intf_|PCM_INL[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|PCM_INL [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y22_N6 +cycloneive_lcell_comb \ula_|pcm_outr~0 ( +// Equation(s): +// \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datad(\ula_|i2s_intf_|PCM_INL [14]), + .cin(gnd), + .combout(\ula_|pcm_outr~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; +defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N7 +dffeas \ula_|pcm_outl[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|pcm_outr~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|pcm_outl [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [12]), + .datad(\ula_|pcm_outl [12]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N15 +dffeas \ula_|i2s_intf_|shiftreg[13] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [13]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) + + .dataa(gnd), + .datab(\ula_|pcm_outl [13]), + .datac(\ula_|i2s_intf_|shiftreg [13]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCCF0; +defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N5 +dffeas \ula_|i2s_intf_|shiftreg[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N31 +dffeas \ula_|pcm_outl[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\D[4]~98_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|pcm_outl [14]), @@ -57419,24 +57790,24 @@ defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y13_N22 +// Location: LCCOMB_X28_Y22_N4 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|pcm_outl [14]), + .datab(gnd), + .datac(\ula_|pcm_outl [14]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hEE22; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF0AA; defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y13_N23 +// Location: FF_X28_Y22_N5 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~4_combout ), @@ -57445,7 +57816,7 @@ dffeas \ula_|i2s_intf_|shiftreg[15] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [15]), @@ -57455,24 +57826,24 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y13_N24 +// Location: LCCOMB_X28_Y22_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) +// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|shiftreg [15] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), .datac(\ula_|i2s_intf_|shiftreg [15]), - .datad(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h3030; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h00F0; defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y13_N25 +// Location: FF_X28_Y22_N1 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~3_combout ), @@ -57481,7 +57852,7 @@ dffeas \ula_|i2s_intf_|shiftreg[16] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [16]), @@ -57491,20 +57862,20 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y13_N30 +// Location: LCCOMB_X28_Y22_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [16]) +// \ula_|i2s_intf_|shiftreg~0_combout = (\ula_|i2s_intf_|shiftreg [16] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [16]), - .datad(gnd), + .datab(\ula_|i2s_intf_|shiftreg [16]), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h3030; +defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h00CC; defparam \ula_|i2s_intf_|shiftreg~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57517,7 +57888,7 @@ dffeas \ula_|i2s_intf_|shiftreg[17] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[8]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [17]), @@ -57527,33 +57898,136 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \ula_|border[1]~feeder ( +// Location: LCCOMB_X38_Y33_N8 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( // Equation(s): -// \ula_|border[1]~feeder_combout = \D[1]~31_combout +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [6]))) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[1]~31_combout ), + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [6]), .cin(gnd), - .combout(\ula_|border[1]~feeder_combout ), + .combout(\ula_|video_|LessThan2~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N13 +// Location: LCCOMB_X38_Y33_N4 +cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( +// Equation(s): +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(\ula_|video_|vga_vc [3]), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0111; +defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N30 +cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( +// Equation(s): +// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|vga_vc [4]), + .datac(\ula_|video_|LessThan2~0_combout ), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7050; +defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N16 +cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( +// Equation(s): +// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|LessThan6~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|LessThan6~0_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h5D55; +defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N22 +cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( +// Equation(s): +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [5])) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [6]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0011; +defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N24 +cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( +// Equation(s): +// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((\ula_|video_|LessThan0~0_combout & !\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # +// ((!\ula_|video_|LessThan0~0_combout & \ula_|video_|vga_hc [7])))) + + .dataa(\ula_|video_|LessThan0~0_combout ), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [7]), + .datad(\ula_|video_|vga_hc [9]), + .cin(gnd), + .combout(\ula_|video_|disp_enable~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h3BDC; +defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y33_N2 +cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( +// Equation(s): +// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) + + .dataa(\ula_|video_|LessThan2~1_combout ), + .datab(\ula_|video_|LessThan3~0_combout ), + .datac(gnd), + .datad(\ula_|video_|disp_enable~0_combout ), + .cin(gnd), + .combout(\ula_|video_|disp_enable~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; +defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y22_N11 dffeas \ula_|border[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[1]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[1]~34_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), + .sload(vcc), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|border [1]), @@ -57563,7 +58037,76 @@ defparam \ula_|border[1] .is_wysiwyg = "true"; defparam \ula_|border[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y29_N4 +// Location: LCCOMB_X37_Y33_N8 +cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( +// Equation(s): +// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; +defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y33_N28 +cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( +// Equation(s): +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [5]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; +defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y33_N10 +cycloneive_lcell_comb \ula_|video_|screen_en~0 ( +// Equation(s): +// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|LessThan4~0_combout ), + .datad(\ula_|video_|vga_hc [8]), + .cin(gnd), + .combout(\ula_|video_|screen_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1121; +defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y33_N22 +cycloneive_lcell_comb \ula_|video_|screen_en~1 ( +// Equation(s): +// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # +// (!\ula_|video_|LessThan6~1_combout ))))) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|LessThan6~1_combout ), + .datad(\ula_|video_|screen_en~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; +defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N28 cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -57580,14 +58123,14 @@ defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y30_N10 +// Location: LCCOMB_X34_Y31_N10 cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( // Equation(s): -// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) +// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), .datad(\ula_|video_|vga_hc [0]), .cin(gnd), .combout(\ula_|video_|Decoder0~1_combout ), @@ -57597,7 +58140,7 @@ defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y29_N5 +// Location: FF_X32_Y33_N29 dffeas \ula_|video_|attr_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), @@ -57616,32 +58159,15 @@ defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N4 -cycloneive_lcell_comb \ula_|video_|attr[1]~feeder ( -// Equation(s): -// \ula_|video_|attr[1]~feeder_combout = \ula_|video_|attr_prefetch [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|attr_prefetch [1]), - .cin(gnd), - .combout(\ula_|video_|attr[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y30_N0 +// Location: LCCOMB_X34_Y31_N12 cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( // Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & \ula_|video_|vga_hc [3]))) +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & \ula_|video_|vga_hc [0]))) - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [3]), + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), .cin(gnd), .combout(\ula_|video_|Decoder0~0_combout ), .cout()); @@ -57650,15 +58176,15 @@ defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y31_N5 +// Location: FF_X37_Y33_N27 dffeas \ula_|video_|attr[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr[1]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [1]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -57669,7 +58195,7 @@ defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N0 +// Location: LCCOMB_X32_Y33_N10 cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 @@ -57686,7 +58212,7 @@ defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y30_N1 +// Location: FF_X32_Y33_N11 dffeas \ula_|video_|attr_prefetch[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), @@ -57705,7 +58231,7 @@ defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N15 +// Location: FF_X37_Y33_N13 dffeas \ula_|video_|attr[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -57724,278 +58250,7 @@ defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; defparam \ula_|video_|attr[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N0 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y30_N0 -cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( -// Equation(s): -// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0020; -defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N1 -dffeas \ula_|video_|bits_prefetch[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N7 -dffeas \ula_|video_|bits[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N2 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N3 -dffeas \ula_|video_|bits_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N13 -dffeas \ula_|video_|bits[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y23_N16 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y23_N17 -dffeas \ula_|video_|bits_prefetch[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N25 -dffeas \ula_|video_|bits[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y25_N28 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y25_N29 -dffeas \ula_|video_|bits_prefetch[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y31_N19 -dffeas \ula_|video_|bits[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y31_N18 -cycloneive_lcell_comb \ula_|video_|Mux0~0 ( -// Equation(s): -// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [5]), - .datac(\ula_|video_|bits [7]), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE50; -defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y31_N12 -cycloneive_lcell_comb \ula_|video_|Mux0~1 ( -// Equation(s): -// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [6]), - .datac(\ula_|video_|bits [4]), - .datad(\ula_|video_|Mux0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; -defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y25_N26 +// Location: LCCOMB_X32_Y33_N24 cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58012,7 +58267,7 @@ defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y25_N27 +// Location: FF_X32_Y33_N25 dffeas \ula_|video_|attr_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), @@ -58031,7 +58286,7 @@ defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N27 +// Location: FF_X36_Y33_N5 dffeas \ula_|video_|attr[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58050,24 +58305,24 @@ defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N28 +// Location: LCCOMB_X34_Y33_N22 cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( // Equation(s): -// \ula_|video_|frame[0]~12_combout = \ula_|video_|frame [0] $ (\ula_|video_|Equal3~1_combout ) +// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) - .dataa(gnd), + .dataa(\ula_|video_|Equal3~1_combout ), .datab(gnd), .datac(\ula_|video_|frame [0]), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|frame[0]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h0FF0; +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h5A5A; defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N29 +// Location: FF_X34_Y33_N23 dffeas \ula_|video_|frame[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[0]~12_combout ), @@ -58086,14 +58341,14 @@ defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; defparam \ula_|video_|frame[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N4 +// Location: LCCOMB_X35_Y33_N24 cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( // Equation(s): -// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [1] & (\ula_|video_|frame [0] $ (VCC))) # (!\ula_|video_|frame [1] & (\ula_|video_|frame [0] & VCC)) -// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [1] & \ula_|video_|frame [0])) +// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) +// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [0] & \ula_|video_|frame [1])) - .dataa(\ula_|video_|frame [1]), - .datab(\ula_|video_|frame [0]), + .dataa(\ula_|video_|frame [0]), + .datab(\ula_|video_|frame [1]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -58104,15 +58359,15 @@ defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y30_N13 +// Location: FF_X35_Y33_N25 dffeas \ula_|video_|frame[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[1]~4_combout ), + .d(\ula_|video_|frame[1]~4_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58123,33 +58378,33 @@ defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; defparam \ula_|video_|frame[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N6 +// Location: LCCOMB_X35_Y33_N26 cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( // Equation(s): // \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) // \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - .dataa(gnd), - .datab(\ula_|video_|frame [2]), + .dataa(\ula_|video_|frame [2]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[1]~5 ), .combout(\ula_|video_|frame[2]~6_combout ), .cout(\ula_|video_|frame[2]~7 )); // synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h5A5F; defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y31_N21 +// Location: FF_X35_Y33_N27 dffeas \ula_|video_|frame[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[2]~6_combout ), + .d(\ula_|video_|frame[2]~6_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58160,25 +58415,25 @@ defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; defparam \ula_|video_|frame[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N8 +// Location: LCCOMB_X35_Y33_N28 cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( // Equation(s): // \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) // \ula_|video_|frame[3]~9 = CARRY((\ula_|video_|frame [3] & !\ula_|video_|frame[2]~7 )) - .dataa(\ula_|video_|frame [3]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|frame [3]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[2]~7 ), .combout(\ula_|video_|frame[3]~8_combout ), .cout(\ula_|video_|frame[3]~9 )); // synopsys translate_off -defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X36_Y31_N9 +// Location: FF_X35_Y33_N29 dffeas \ula_|video_|frame[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[3]~8_combout ), @@ -58197,32 +58452,32 @@ defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; defparam \ula_|video_|frame[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N10 +// Location: LCCOMB_X35_Y33_N30 cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( // Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame [4] $ (\ula_|video_|frame[3]~9 ) - .dataa(gnd), + .dataa(\ula_|video_|frame [4]), .datab(gnd), .datac(gnd), - .datad(\ula_|video_|frame [4]), + .datad(gnd), .cin(\ula_|video_|frame[3]~9 ), .combout(\ula_|video_|frame[4]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h5A5A; defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X36_Y31_N17 +// Location: FF_X35_Y33_N31 dffeas \ula_|video_|frame[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[4]~10_combout ), + .d(\ula_|video_|frame[4]~10_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58233,7 +58488,7 @@ defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; defparam \ula_|video_|frame[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N26 +// Location: LCCOMB_X36_Y33_N4 cycloneive_lcell_comb \ula_|video_|inverted ( // Equation(s): // \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) @@ -58250,7 +58505,312 @@ defparam \ula_|video_|inverted .lut_mask = 16'hF000; defparam \ula_|video_|inverted .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y21_N0 +// Location: LCCOMB_X32_Y33_N12 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( +// Equation(s): +// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [1]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0008; +defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N13 +dffeas \ula_|video_|bits_prefetch[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N6 +cycloneive_lcell_comb \ula_|video_|bits[6]~feeder ( +// Equation(s): +// \ula_|video_|bits[6]~feeder_combout = \ula_|video_|bits_prefetch [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [6]), + .cin(gnd), + .combout(\ula_|video_|bits[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N7 +dffeas \ula_|video_|bits[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N22 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N23 +dffeas \ula_|video_|bits_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y33_N23 +dffeas \ula_|video_|bits[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N18 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N19 +dffeas \ula_|video_|bits_prefetch[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N18 +cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( +// Equation(s): +// \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [5]), + .cin(gnd), + .combout(\ula_|video_|bits[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N19 +dffeas \ula_|video_|bits[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N0 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N1 +dffeas \ula_|video_|bits_prefetch[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y33_N1 +dffeas \ula_|video_|bits[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N0 +cycloneive_lcell_comb \ula_|video_|Mux0~0 ( +// Equation(s): +// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) + + .dataa(\ula_|video_|bits [5]), + .datab(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|bits [7]), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y33_N22 +cycloneive_lcell_comb \ula_|video_|Mux0~1 ( +// Equation(s): +// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) + + .dataa(\ula_|video_|bits [6]), + .datab(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|bits [4]), + .datad(\ula_|video_|Mux0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y33_N16 cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58267,7 +58827,7 @@ defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y21_N1 +// Location: FF_X32_Y33_N17 dffeas \ula_|video_|bits_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), @@ -58286,15 +58846,32 @@ defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N5 +// Location: LCCOMB_X36_Y33_N12 +cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( +// Equation(s): +// \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [2]), + .cin(gnd), + .combout(\ula_|video_|bits[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y33_N13 dffeas \ula_|video_|bits[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [2]), + .d(\ula_|video_|bits[2]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58305,7 +58882,7 @@ defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y27_N4 +// Location: LCCOMB_X32_Y33_N14 cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -58322,7 +58899,7 @@ defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y27_N5 +// Location: FF_X32_Y33_N15 dffeas \ula_|video_|bits_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), @@ -58341,7 +58918,7 @@ defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N21 +// Location: FF_X36_Y33_N3 dffeas \ula_|video_|bits[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58360,7 +58937,7 @@ defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y29_N6 +// Location: LCCOMB_X32_Y33_N6 cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -58377,7 +58954,7 @@ defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y29_N7 +// Location: FF_X32_Y33_N7 dffeas \ula_|video_|bits_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), @@ -58396,7 +58973,7 @@ defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N24 +// Location: LCCOMB_X36_Y33_N26 cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( // Equation(s): // \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] @@ -58413,7 +58990,7 @@ defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y31_N25 +// Location: FF_X36_Y33_N27 dffeas \ula_|video_|bits[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[1]~feeder_combout ), @@ -58432,24 +59009,24 @@ defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N18 +// Location: LCCOMB_X32_Y33_N4 cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), - .datad(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), .cin(gnd), .combout(\ula_|video_|bits_prefetch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hF0F0; +defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y31_N19 +// Location: FF_X32_Y33_N5 dffeas \ula_|video_|bits_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), @@ -58468,7 +59045,7 @@ defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N3 +// Location: FF_X36_Y33_N25 dffeas \ula_|video_|bits[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58487,58 +59064,58 @@ defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N2 +// Location: LCCOMB_X36_Y33_N24 cycloneive_lcell_comb \ula_|video_|Mux0~2 ( // Equation(s): // \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [1]), + .dataa(\ula_|video_|bits [1]), + .datab(\ula_|video_|vga_hc [1]), .datac(\ula_|video_|bits [3]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE30; defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N20 +// Location: LCCOMB_X36_Y33_N2 cycloneive_lcell_comb \ula_|video_|Mux0~3 ( // Equation(s): // \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [2]), + .dataa(\ula_|video_|bits [2]), + .datab(\ula_|video_|vga_hc [1]), .datac(\ula_|video_|bits [0]), .datad(\ula_|video_|Mux0~2_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF388; defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N28 +// Location: LCCOMB_X36_Y33_N10 cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( // Equation(s): // \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - .dataa(\ula_|video_|Mux0~1_combout ), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|inverted~combout ), + .dataa(\ula_|video_|vga_hc [3]), + .datab(\ula_|video_|inverted~combout ), + .datac(\ula_|video_|Mux0~1_combout ), .datad(\ula_|video_|Mux0~3_combout ), .cin(gnd), .combout(\ula_|video_|cindex[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h1ED2; +defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h369C; defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N14 +// Location: LCCOMB_X37_Y33_N12 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): // \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) @@ -58555,213 +59132,24 @@ defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N4 -cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( -// Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|vga_vc [3]), - .cin(gnd), - .combout(\ula_|video_|LessThan6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0013; -defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N24 -cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( -// Equation(s): -// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan6~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; -defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N30 -cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( -// Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [6])) # (!\ula_|video_|vga_hc [7]) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|LessThan4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; -defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N22 -cycloneive_lcell_comb \ula_|video_|screen_en~0 ( -// Equation(s): -// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|vga_hc [9]), - .datad(\ula_|video_|LessThan4~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1203; -defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N26 -cycloneive_lcell_comb \ula_|video_|screen_en~1 ( -// Equation(s): -// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # -// (!\ula_|video_|LessThan6~1_combout ))))) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(\ula_|video_|LessThan6~1_combout ), - .datac(\ula_|video_|screen_en~0_combout ), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|screen_en~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~1 .lut_mask = 16'hD0B0; -defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N12 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( -// Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N26 -cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( -// Equation(s): -// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|LessThan6~0_combout ), - .datad(\ula_|video_|LessThan2~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7500; -defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N14 -cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( -// Equation(s): -// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|Equal2~0_combout & (\ula_|video_|LessThan6~0_combout & !\ula_|video_|vga_vc [5]))) # (!\ula_|video_|vga_vc [9]) - - .dataa(\ula_|video_|Equal2~0_combout ), - .datab(\ula_|video_|LessThan6~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|vga_vc [9]), - .cin(gnd), - .combout(\ula_|video_|LessThan3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h08FF; -defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N2 -cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( -// Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [6]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|vga_hc [5]), - .cin(gnd), - .combout(\ula_|video_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0003; -defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y31_N28 -cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( -// Equation(s): -// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & -// !\ula_|video_|LessThan0~0_combout )))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [9]), - .datad(\ula_|video_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|disp_enable~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; -defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N16 -cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( -// Equation(s): -// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) - - .dataa(\ula_|video_|LessThan2~1_combout ), - .datab(\ula_|video_|LessThan3~0_combout ), - .datac(gnd), - .datad(\ula_|video_|disp_enable~0_combout ), - .cin(gnd), - .combout(\ula_|video_|disp_enable~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; -defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y31_N22 +// Location: LCCOMB_X37_Y33_N24 cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( // Equation(s): // \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - .dataa(\ula_|border [1]), - .datab(\ula_|video_|cindex[1]~1_combout ), + .dataa(\ula_|video_|disp_enable~1_combout ), + .datab(\ula_|border [1]), .datac(\ula_|video_|screen_en~1_combout ), - .datad(\ula_|video_|disp_enable~1_combout ), + .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hCA00; +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hA808; defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N14 +// Location: LCCOMB_X32_Y33_N26 cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 @@ -58778,7 +59166,7 @@ defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N15 +// Location: FF_X32_Y33_N27 dffeas \ula_|video_|attr_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), @@ -58797,7 +59185,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X35_Y31_N19 +// Location: FF_X38_Y33_N1 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58816,50 +59204,50 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N18 +// Location: LCCOMB_X38_Y33_N0 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): -// \ula_|video_|VGA_B[1]~0_combout = (\ula_|video_|LessThan3~0_combout & (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) +// \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) - .dataa(\ula_|video_|LessThan3~0_combout ), - .datab(\ula_|video_|LessThan2~1_combout ), + .dataa(\ula_|video_|LessThan2~1_combout ), + .datab(\ula_|video_|LessThan3~0_combout ), .datac(\ula_|video_|attr [6]), .datad(\ula_|video_|disp_enable~0_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h2000; +defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N16 +// Location: LCCOMB_X37_Y33_N2 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): -// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[1]~1_combout & \ula_|video_|VGA_B[1]~0_combout )) +// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[1]~1_combout )) .dataa(\ula_|video_|screen_en~1_combout ), - .datab(\ula_|video_|cindex[1]~1_combout ), - .datac(gnd), - .datad(\ula_|video_|VGA_B[1]~0_combout ), + .datab(gnd), + .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8800; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N3 +// Location: FF_X31_Y12_N17 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\D[2]~40_combout ), + .asdata(\D[2]~46_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\ula_|always0~1_combout ), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|border [2]), @@ -58869,7 +59257,7 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y21_N30 +// Location: LCCOMB_X32_Y33_N8 cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58886,7 +59274,7 @@ defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y21_N31 +// Location: FF_X32_Y33_N9 dffeas \ula_|video_|attr_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), @@ -58905,7 +59293,7 @@ defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N11 +// Location: FF_X36_Y33_N21 dffeas \ula_|video_|attr[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58924,7 +59312,7 @@ defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y23_N14 +// Location: LCCOMB_X32_Y33_N30 cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -58941,7 +59329,7 @@ defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y23_N15 +// Location: FF_X32_Y33_N31 dffeas \ula_|video_|attr_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), @@ -58960,7 +59348,7 @@ defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y31_N1 +// Location: FF_X36_Y33_N15 dffeas \ula_|video_|attr[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58979,49 +59367,49 @@ defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N0 +// Location: LCCOMB_X36_Y33_N14 cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( // Equation(s): // \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) - .dataa(\ula_|video_|attr [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|attr [2]), .datac(\ula_|video_|attr [5]), .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N30 +// Location: LCCOMB_X38_Y33_N26 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) .dataa(\ula_|border [2]), - .datab(\ula_|video_|disp_enable~1_combout ), - .datac(\ula_|video_|screen_en~1_combout ), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hC808; +defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hE020; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y31_N24 +// Location: LCCOMB_X36_Y33_N20 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|VGA_B[1]~0_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|screen_en~1_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), .datab(\ula_|video_|cindex[2]~2_combout ), .datac(gnd), - .datad(\ula_|video_|VGA_B[1]~0_combout ), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), .cout()); @@ -59030,33 +59418,16 @@ defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \ula_|border[0]~feeder ( -// Equation(s): -// \ula_|border[0]~feeder_combout = \D[0]~49_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[0]~49_combout ), - .cin(gnd), - .combout(\ula_|border[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N9 +// Location: FF_X32_Y22_N1 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[0]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[0]~58_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~1_combout ), + .sload(vcc), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|border [0]), @@ -59066,7 +59437,7 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y27_N6 +// Location: LCCOMB_X32_Y33_N20 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -59083,7 +59454,7 @@ defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y27_N7 +// Location: FF_X32_Y33_N21 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -59102,15 +59473,32 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y31_N7 +// Location: LCCOMB_X37_Y33_N28 +cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( +// Equation(s): +// \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|attr_prefetch [0]), + .cin(gnd), + .combout(\ula_|video_|attr[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y33_N29 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [0]), + .d(\ula_|video_|attr[0]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59121,15 +59509,32 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X34_Y31_N13 +// Location: LCCOMB_X32_Y33_N2 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y33_N3 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59140,7 +59545,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X37_Y31_N9 +// Location: FF_X36_Y33_N29 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59159,49 +59564,49 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N8 +// Location: LCCOMB_X36_Y33_N28 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): // \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) - .dataa(\ula_|video_|attr [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|attr [0]), .datac(\ula_|video_|attr [3]), .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y31_N2 +// Location: LCCOMB_X37_Y33_N30 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) - .dataa(\ula_|border [0]), - .datab(\ula_|video_|cindex[0]~3_combout ), - .datac(\ula_|video_|disp_enable~1_combout ), - .datad(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|video_|disp_enable~1_combout ), + .datab(\ula_|border [0]), + .datac(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hC0A0; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hA808; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y31_N0 +// Location: LCCOMB_X37_Y33_N0 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[0]~3_combout & \ula_|video_|VGA_B[1]~0_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[0]~3_combout )) .dataa(\ula_|video_|screen_en~1_combout ), .datab(gnd), - .datac(\ula_|video_|cindex[0]~3_combout ), - .datad(\ula_|video_|VGA_B[1]~0_combout ), + .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~2_combout ), .cout()); @@ -59210,24 +59615,24 @@ defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N4 +// Location: LCCOMB_X37_Y33_N26 cycloneive_lcell_comb \ula_|video_|Equal0~2 ( // Equation(s): -// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_hc [8] & \ula_|video_|vga_hc [6])) +// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [9] & !\ula_|video_|vga_hc [8])) - .dataa(\ula_|video_|vga_hc [9]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [6]), + .dataa(\ula_|video_|vga_hc [6]), + .datab(\ula_|video_|vga_hc [9]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [8]), .cin(gnd), .combout(\ula_|video_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0500; +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0022; defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y31_N9 +// Location: FF_X37_Y33_N7 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -59246,21 +59651,21 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N8 +// Location: LCCOMB_X37_Y33_N6 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): -// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|VGA_HS~_Duplicate_1_q & \ula_|video_|Equal1~0_combout )))) # (!\ula_|video_|Equal0~2_combout & (((\ula_|video_|VGA_HS~_Duplicate_1_q -// & \ula_|video_|Equal1~0_combout )))) +// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & +// (\ula_|video_|VGA_HS~_Duplicate_1_q ))) .dataa(\ula_|video_|Equal0~2_combout ), - .datab(\ula_|video_|Equal0~1_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|VGA_HS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Equal0~1_combout ), .cin(gnd), .combout(\ula_|video_|Selector0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector0~0 .lut_mask = 16'hF888; +defparam \ula_|video_|Selector0~0 .lut_mask = 16'hEAC0; defparam \ula_|video_|Selector0~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59283,7 +59688,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y31_N31 +// Location: FF_X34_Y33_N25 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -59302,21 +59707,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y31_N30 +// Location: LCCOMB_X34_Y33_N24 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1]) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|Equal2~2_combout & (((\ula_|video_|VGA_VS~_Duplicate_1_q & -// !\ula_|video_|Equal3~1_combout )))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal3~1_combout & (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1])))) # (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|VGA_VS~_Duplicate_1_q ) # ((\ula_|video_|Equal2~2_combout & +// \ula_|video_|vga_vc [1])))) - .dataa(\ula_|video_|Equal2~2_combout ), - .datab(\ula_|video_|vga_vc [1]), + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Equal2~2_combout ), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'hDC50; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59339,7 +59744,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N30 +// Location: LCCOMB_X47_Y17_N4 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -59356,7 +59761,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X52_Y13_N31 +// Location: FF_X47_Y17_N5 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -59375,7 +59780,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X52_Y13_N9 +// Location: FF_X47_Y17_N25 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -59394,7 +59799,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N8 +// Location: LCCOMB_X47_Y17_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -59411,41 +59816,41 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y13_N22 +// Location: LCCOMB_X47_Y17_N26 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(gnd), .datab(gnd), - .datac(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nM1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF55; +defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y16_N4 +// Location: LCCOMB_X23_Y26_N0 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[3]~77_combout $ (\D[4]~79_combout $ (((\ula_|i2s_intf_|PCM_INL [14]) # (\ula_|i2s_intf_|PCM_INR [14])))) +// \ula_|beep~0_combout = \D[4]~98_combout $ (\raw_loader_in~input_o $ (\D[3]~96_combout )) - .dataa(\D[3]~77_combout ), - .datab(\ula_|i2s_intf_|PCM_INL [14]), - .datac(\D[4]~79_combout ), - .datad(\ula_|i2s_intf_|PCM_INR [14]), + .dataa(gnd), + .datab(\D[4]~98_combout ), + .datac(\raw_loader_in~input_o ), + .datad(\D[3]~96_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hA596; +defparam \ula_|beep~0 .lut_mask = 16'hC33C; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y16_N5 +// Location: FF_X23_Y26_N1 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), @@ -59454,7 +59859,7 @@ dffeas \ula_|beep ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|always0~1_combout ), + .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|beep~q ), diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo index 2e02e98..ef4ecfb 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/31/2022 14:04:24") + (DATE "04/01/2022 18:55:52") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1032:1032:1032) (1172:1172:1172)) - (PORT oe (356:356:356) (412:412:412)) + (PORT i (1174:1174:1174) (1317:1317:1317)) + (PORT oe (934:934:934) (1057:1057:1057)) (IOPATH i o (1586:1586:1586) (1541:1541:1541)) (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (871:871:871) (1017:1017:1017)) - (PORT oe (1243:1243:1243) (1432:1432:1432)) + (PORT i (1180:1180:1180) (1340:1340:1340)) + (PORT oe (1037:1037:1037) (1174:1174:1174)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (711:711:711) (808:808:808)) - (PORT oe (1243:1243:1243) (1432:1432:1432)) + (PORT i (1119:1119:1119) (1291:1291:1291)) + (PORT oe (1037:1037:1037) (1174:1174:1174)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (893:893:893) (1021:1021:1021)) - (PORT oe (1355:1355:1355) (1582:1582:1582)) + (PORT i (1254:1254:1254) (1427:1427:1427)) + (PORT oe (1198:1198:1198) (1376:1376:1376)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (730:730:730) (838:838:838)) - (PORT oe (1355:1355:1355) (1582:1582:1582)) + (PORT i (1312:1312:1312) (1495:1495:1495)) + (PORT oe (1198:1198:1198) (1376:1376:1376)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (645:645:645) (736:736:736)) - (PORT oe (1347:1347:1347) (1567:1567:1567)) + (PORT i (1099:1099:1099) (1242:1242:1242)) + (PORT oe (1064:1064:1064) (1222:1222:1222)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (767:767:767) (871:871:871)) - (PORT oe (1347:1347:1347) (1567:1567:1567)) + (PORT i (918:918:918) (1050:1050:1050)) + (PORT oe (1064:1064:1064) (1222:1222:1222)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (512:512:512) (599:599:599)) - (PORT oe (1347:1347:1347) (1567:1567:1567)) + (PORT i (1143:1143:1143) (1334:1334:1334)) + (PORT oe (1064:1064:1064) (1222:1222:1222)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (525:525:525) (612:612:612)) - (PORT oe (1351:1351:1351) (1570:1570:1570)) + (PORT i (543:543:543) (634:634:634)) + (PORT oe (1215:1215:1215) (1393:1393:1393)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (605:605:605) (698:698:698)) - (PORT oe (1351:1351:1351) (1570:1570:1570)) + (PORT i (970:970:970) (1109:1109:1109)) + (PORT oe (1215:1215:1215) (1393:1393:1393)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (637:637:637) (730:730:730)) - (PORT oe (1479:1479:1479) (1736:1736:1736)) + (PORT i (1061:1061:1061) (1219:1219:1219)) + (PORT oe (1375:1375:1375) (1593:1593:1593)) (IOPATH i o (3177:3177:3177) (2883:2883:2883)) (IOPATH oe o (3164:3164:3164) (2848:2848:2848)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (614:614:614) (707:707:707)) - (PORT oe (1351:1351:1351) (1570:1570:1570)) + (PORT i (775:775:775) (876:876:876)) + (PORT oe (1215:1215:1215) (1393:1393:1393)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (869:869:869) (989:989:989)) - (PORT oe (1236:1236:1236) (1424:1424:1424)) + (PORT i (1194:1194:1194) (1336:1336:1336)) + (PORT oe (933:933:933) (1055:1055:1055)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (624:624:624) (714:714:714)) - (PORT oe (1479:1479:1479) (1736:1736:1736)) + (PORT i (1275:1275:1275) (1459:1459:1459)) + (PORT oe (1375:1375:1375) (1593:1593:1593)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (790:790:790) (908:908:908)) - (PORT oe (1357:1357:1357) (1578:1578:1578)) + (PORT i (934:934:934) (1057:1057:1057)) + (PORT oe (1212:1212:1212) (1388:1388:1388)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (606:606:606) (694:694:694)) - (PORT oe (1345:1345:1345) (1575:1575:1575)) + (PORT i (987:987:987) (1146:1146:1146)) + (PORT oe (1050:1050:1050) (1190:1190:1190)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (610:610:610) (692:692:692)) - (PORT oe (1597:1597:1597) (1807:1807:1807)) + (PORT i (673:673:673) (772:772:772)) + (PORT oe (1396:1396:1396) (1566:1566:1566)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (618:618:618) (690:690:690)) - (PORT oe (1567:1567:1567) (1760:1760:1760)) + (PORT i (694:694:694) (791:791:791)) + (PORT oe (1396:1396:1396) (1567:1567:1567)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (680:680:680) (764:764:764)) - (PORT oe (1401:1401:1401) (1573:1573:1573)) + (PORT i (620:620:620) (700:700:700)) + (PORT oe (1211:1211:1211) (1355:1355:1355)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (651:651:651) (736:736:736)) - (PORT oe (1597:1597:1597) (1807:1807:1807)) + (PORT i (663:663:663) (769:769:769)) + (PORT oe (1396:1396:1396) (1566:1566:1566)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (825:825:825) (940:940:940)) - (PORT oe (1390:1390:1390) (1561:1561:1561)) + (PORT i (826:826:826) (944:944:944)) + (PORT oe (1184:1184:1184) (1331:1331:1331)) (IOPATH i o (1586:1586:1586) (1541:1541:1541)) (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (535:535:535) (612:612:612)) - (PORT oe (1400:1400:1400) (1572:1572:1572)) + (PORT i (736:736:736) (825:825:825)) + (PORT oe (1210:1210:1210) (1354:1354:1354)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (742:742:742) (846:846:846)) - (PORT oe (1358:1358:1358) (1523:1523:1523)) + (PORT i (678:678:678) (773:773:773)) + (PORT oe (1148:1148:1148) (1280:1280:1280)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (476:476:476) (542:542:542)) - (PORT oe (1575:1575:1575) (1774:1774:1774)) + (PORT i (622:622:622) (691:691:691)) + (PORT oe (1364:1364:1364) (1526:1526:1526)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (815:815:815) (731:731:731)) - (PORT oe (691:691:691) (807:807:807)) + (PORT i (846:846:846) (761:761:761)) + (PORT oe (926:926:926) (1046:1046:1046)) (IOPATH i o (1541:1541:1541) (1586:1586:1586)) (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (894:894:894) (794:794:794)) - (PORT oe (1345:1345:1345) (1575:1575:1575)) + (PORT i (1098:1098:1098) (954:954:954)) + (PORT oe (1050:1050:1050) (1190:1190:1190)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -353,8 +353,8 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (371:371:371) (338:338:338)) - (PORT oe (525:525:525) (617:617:617)) + (PORT i (934:934:934) (837:837:837)) + (PORT oe (757:757:757) (859:859:859)) (IOPATH i o (1600:1600:1600) (1666:1666:1666)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (410:410:410) (449:449:449)) - (PORT oe (378:378:378) (446:446:446)) + (PORT i (571:571:571) (628:628:628)) + (PORT oe (731:731:731) (836:836:836)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -377,7 +377,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1018:1018:1018) (884:884:884)) + (PORT i (1022:1022:1022) (889:889:889)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -392,6 +392,16 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (741:741:741) (831:831:831)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_obuf") (INSTANCE AUD_XCK\~output) @@ -442,7 +452,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (685:685:685) (788:788:788)) + (PORT i (638:638:638) (733:733:733)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -452,7 +462,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (687:687:687) (795:795:795)) + (PORT i (601:601:601) (687:687:687)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -462,7 +472,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (285:285:285) (316:316:316)) + (PORT i (397:397:397) (437:437:437)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -472,7 +482,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (662:662:662) (763:763:763)) + (PORT i (527:527:527) (586:586:586)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -482,7 +492,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (470:470:470) (525:525:525)) + (PORT i (524:524:524) (579:579:579)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -492,7 +502,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (443:443:443) (495:495:495)) + (PORT i (382:382:382) (418:418:418)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -502,7 +512,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (591:591:591) (661:661:661)) + (PORT i (444:444:444) (480:480:480)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -512,7 +522,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (591:591:591) (661:661:661)) + (PORT i (444:444:444) (480:480:480)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -522,7 +532,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (400:400:400) (440:440:440)) + (PORT i (384:384:384) (417:417:417)) (IOPATH i o (3177:3177:3177) (2883:2883:2883)) ) ) @@ -532,7 +542,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (268:268:268) (298:298:298)) + (PORT i (373:373:373) (405:405:405)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -542,7 +552,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (563:563:563) (625:625:625)) + (PORT i (511:511:511) (561:561:561)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -552,7 +562,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (773:773:773) (852:852:852)) + (PORT i (738:738:738) (808:808:808)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -580,7 +590,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (776:776:776) (676:676:676)) + (PORT i (1282:1282:1282) (1120:1120:1120)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) ) ) @@ -590,7 +600,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (374:374:374) (329:329:329)) + (PORT i (792:792:792) (715:715:715)) (IOPATH i o (2841:2841:2841) (3106:3106:3106)) ) ) @@ -600,7 +610,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (156:156:156) (176:176:176)) + (PORT i (506:506:506) (553:553:553)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) ) ) @@ -610,7 +620,7 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (1018:1018:1018) (1183:1183:1183)) + (PORT i (749:749:749) (860:860:860)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -724,7 +734,20 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (405:405:405) (440:440:440)) + (PORT inclk[0] (388:388:388) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (714:714:714)) + (PORT datad (612:612:612) (707:707:707)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -733,122 +756,13 @@ (INSTANCE z80_\|sequencer_\|ena_M) (DELAY (ABSOLUTE - (PORT datac (496:496:496) (575:575:575)) - (PORT datad (472:472:472) (548:548:548)) + (PORT datac (596:596:596) (692:692:692)) + (PORT datad (608:608:608) (702:702:702)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE KEY\[0\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (153:153:153) (705:705:705)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE reset) - (DELAY - (ABSOLUTE - (PORT datac (1233:1233:1233) (1038:1038:1038)) - (PORT datad (464:464:464) (514:514:514)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x1\~0) - (DELAY - (ABSOLUTE - (PORT datad (105:105:105) (123:123:123)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|fpga_reset) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|fpga_reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (392:392:392) (424:424:424)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|x1) - (DELAY - (ABSOLUTE - (PORT clk (933:933:933) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (894:894:894)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (744:744:744)) - (PORT datab (579:579:579) (698:698:698)) - (PORT datad (195:195:195) (244:244:244)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT clk (922:922:922) (929:929:929)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (894:894:894)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (329:329:329) (364:364:364)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE KEY\[1\]\~input) @@ -863,9 +777,9 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) (DELAY (ABSOLUTE - (PORT datac (2160:2160:2160) (2499:2499:2499)) - (PORT datad (619:619:619) (719:719:719)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (203:203:203) (280:280:280)) + (PORT datad (1132:1132:1132) (1310:1310:1310)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -875,9 +789,9 @@ (INSTANCE z80_\|interrupts_\|nmi_armed) (DELAY (ABSOLUTE - (PORT clk (1048:1048:1048) (1152:1152:1152)) + (PORT clk (830:830:830) (891:891:891)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (389:389:389) (407:407:407)) + (PORT clrn (694:694:694) (742:742:742)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -891,31 +805,33 @@ (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) (DELAY (ABSOLUTE - (PORT datad (584:584:584) (679:679:679)) + (PORT datad (425:425:425) (491:491:491)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) (DELAY (ABSOLUTE - (PORT datac (694:694:694) (806:806:806)) - (PORT datad (667:667:667) (786:786:786)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT datac (133:133:133) (175:175:175)) + (PORT datad (136:136:136) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (INSTANCE z80_\|execute_\|ixy_d\~4) (DELAY (ABSOLUTE - (PORT dataa (715:715:715) (858:858:858)) - (PORT datad (746:746:746) (878:878:878)) + (PORT dataa (1371:1371:1371) (1593:1593:1593)) + (PORT datab (1375:1375:1375) (1595:1595:1595)) + (PORT datad (904:904:904) (1067:1067:1067)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -925,9 +841,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (506:506:506) (593:593:593)) - (PORT datab (147:147:147) (197:197:197)) - (PORT datad (479:479:479) (557:557:557)) + (PORT dataa (606:606:606) (709:709:709)) + (PORT datab (214:214:214) (274:274:274)) + (PORT datad (615:615:615) (711:711:711)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -940,9 +856,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) + (PORT clk (920:920:920) (927:927:927)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (903:903:903)) + (PORT clrn (927:927:927) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -951,14 +867,28 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (743:743:743) (846:846:846)) + (PORT datab (854:854:854) (1004:1004:1004)) + (PORT datac (752:752:752) (882:882:882)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (512:512:512) (600:600:600)) - (PORT datab (144:144:144) (193:193:193)) - (PORT datad (474:474:474) (550:550:550)) + (PORT dataa (619:619:619) (724:724:724)) + (PORT datab (218:218:218) (276:276:276)) + (PORT datad (605:605:605) (699:699:699)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -971,9 +901,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) + (PORT clk (920:920:920) (927:927:927)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (903:903:903)) + (PORT clrn (927:927:927) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -984,13 +914,53 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) + (INSTANCE z80_\|pla_decode_\|Equal32\~0) (DELAY (ABSOLUTE - (PORT dataa (750:750:750) (888:888:888)) - (PORT datac (454:454:454) (555:555:555)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datab (206:206:206) (265:265:265)) + (PORT datad (363:363:363) (441:441:441)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) + (DELAY + (ABSOLUTE + (PORT datab (1456:1456:1456) (1687:1687:1687)) + (PORT datad (880:880:880) (1039:1039:1039)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (781:781:781) (936:936:936)) + (PORT datad (666:666:666) (794:794:794)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (1066:1066:1066)) + (PORT datab (519:519:519) (601:601:601)) + (PORT datac (1240:1240:1240) (1447:1447:1447)) + (PORT datad (652:652:652) (756:756:756)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -999,8 +969,8 @@ (INSTANCE z80_\|pla_decode_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT datac (779:779:779) (906:906:906)) - (PORT datad (763:763:763) (884:884:884)) + (PORT datac (811:811:811) (946:946:946)) + (PORT datad (1277:1277:1277) (1473:1473:1473)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -1008,25 +978,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (INSTANCE z80_\|pla_decode_\|Equal36\~0) (DELAY (ABSOLUTE - (PORT datab (536:536:536) (641:641:641)) - (PORT datac (528:528:528) (630:630:630)) + (PORT dataa (704:704:704) (826:826:826)) + (PORT datab (932:932:932) (1116:1116:1116)) + (PORT datac (516:516:516) (599:599:599)) + (PORT datad (519:519:519) (609:609:609)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) (DELAY (ABSOLUTE - (PORT dataa (680:680:680) (789:789:789)) - (PORT datab (721:721:721) (819:819:819)) - (PORT datac (1122:1122:1122) (1292:1292:1292)) - (PORT datad (492:492:492) (573:573:573)) + (PORT dataa (975:975:975) (1124:1124:1124)) + (PORT datab (801:801:801) (910:910:910)) + (PORT datac (461:461:461) (539:539:539)) + (PORT datad (425:425:425) (474:474:474)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (795:795:795)) + (PORT datab (1485:1485:1485) (1716:1716:1716)) + (PORT datac (459:459:459) (536:536:536)) + (PORT datad (543:543:543) (638:638:638)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (920:920:920)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (920:920:920) (902:902:902)) + (PORT ena (407:407:407) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (481:481:481)) + (PORT datab (680:680:680) (814:814:814)) + (PORT datac (543:543:543) (642:642:642)) + (PORT datad (760:760:760) (909:909:909)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1347:1347:1347) (1572:1572:1572)) + (PORT datab (931:931:931) (1114:1114:1114)) + (PORT datac (515:515:515) (597:597:597)) + (PORT datad (376:376:376) (440:440:440)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -1034,15 +1074,121 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (DELAY + (ABSOLUTE + (PORT dataa (987:987:987) (1141:1141:1141)) + (PORT datab (447:447:447) (515:515:515)) + (PORT datac (784:784:784) (887:887:887)) + (PORT datad (1145:1145:1145) (1327:1327:1327)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instED) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (920:920:920)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (920:920:920) (902:902:902)) + (PORT ena (407:407:407) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (485:485:485)) + (PORT datac (535:535:535) (633:633:633)) + (PORT datad (756:756:756) (905:905:905)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1256:1256:1256) (1471:1471:1471)) + (PORT datac (811:811:811) (946:946:946)) + (PORT datad (1277:1277:1277) (1474:1474:1474)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (366:366:366)) + (PORT datab (591:591:591) (702:702:702)) + (PORT datac (752:752:752) (890:890:890)) + (PORT datad (510:510:510) (595:595:595)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT datab (553:553:553) (662:662:662)) + (PORT datac (372:372:372) (439:439:439)) + (PORT datad (715:715:715) (832:832:832)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~1) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (929:929:929)) + (PORT datab (843:843:843) (988:988:988)) + (PORT datac (813:813:813) (946:946:946)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pla_decode_\|Equal6\~0) (DELAY (ABSOLUTE - (PORT dataa (759:759:759) (898:898:898)) - (PORT datab (723:723:723) (830:830:830)) - (PORT datac (157:157:157) (214:214:214)) - (PORT datad (159:159:159) (211:211:211)) + (PORT dataa (392:392:392) (481:481:481)) + (PORT datab (680:680:680) (814:814:814)) + (PORT datac (544:544:544) (643:643:643)) + (PORT datad (760:760:760) (910:910:910)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -1052,12 +1198,100 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (INSTANCE z80_\|execute_\|ctl_mRead\~14) (DELAY (ABSOLUTE - (PORT datab (783:783:783) (912:912:912)) - (PORT datac (954:954:954) (1121:1121:1121)) - (PORT datad (946:946:946) (1102:1102:1102)) + (PORT dataa (670:670:670) (794:794:794)) + (PORT datab (731:731:731) (859:859:859)) + (PORT datad (401:401:401) (483:483:483)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1529:1529:1529) (1775:1775:1775)) + (PORT datab (476:476:476) (565:565:565)) + (PORT datac (615:615:615) (717:717:717)) + (PORT datad (630:630:630) (728:728:728)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (627:627:627)) + (PORT datab (882:882:882) (1046:1046:1046)) + (PORT datac (771:771:771) (895:895:895)) + (PORT datad (107:107:107) (132:132:132)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (758:758:758)) + (PORT datad (1171:1171:1171) (1359:1359:1359)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (731:731:731)) + (PORT datab (606:606:606) (688:688:688)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (387:387:387) (458:458:458)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datac (814:814:814) (955:955:955)) + (PORT datad (835:835:835) (972:972:972)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (821:821:821)) + (PORT datab (929:929:929) (1113:1113:1113)) + (PORT datac (957:957:957) (1095:1095:1095)) + (PORT datad (521:521:521) (611:611:611)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1066,13 +1300,127 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (INSTANCE z80_\|execute_\|ixy_d\~7) (DELAY (ABSOLUTE - (PORT dataa (732:732:732) (860:860:860)) - (PORT datab (478:478:478) (550:550:550)) - (PORT datac (586:586:586) (680:680:680)) - (PORT datad (637:637:637) (739:739:739)) + (PORT datac (1149:1149:1149) (1365:1365:1365)) + (PORT datad (685:685:685) (796:796:796)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1088:1088:1088) (1274:1274:1274)) + (PORT datac (1441:1441:1441) (1671:1671:1671)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (571:571:571)) + (PORT datab (589:589:589) (696:696:696)) + (PORT datac (481:481:481) (579:579:579)) + (PORT datad (501:501:501) (587:587:587)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~1) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (571:571:571)) + (PORT datab (485:485:485) (562:562:562)) + (PORT datac (500:500:500) (609:609:609)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (571:571:571)) + (PORT datab (485:485:485) (562:562:562)) + (PORT datac (499:499:499) (609:609:609)) + (PORT datad (652:652:652) (747:747:747)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (472:472:472) (546:546:546)) + (PORT datac (544:544:544) (643:643:643)) + (PORT datad (626:626:626) (718:718:718)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1470:1470:1470)) + (PORT datac (811:811:811) (947:947:947)) + (PORT datad (1276:1276:1276) (1472:1472:1472)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (579:579:579)) + (PORT datab (961:961:961) (1119:1119:1119)) + (PORT datac (623:623:623) (709:709:709)) + (PORT datad (350:350:350) (413:413:413)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (595:595:595)) + (PORT datab (1337:1337:1337) (1560:1560:1560)) + (PORT datac (959:959:959) (1097:1097:1097)) + (PORT datad (370:370:370) (434:434:434)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -1080,14 +1428,950 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (814:814:814)) + (PORT datab (1179:1179:1179) (1400:1400:1400)) + (PORT datac (470:470:470) (534:534:534)) + (PORT datad (824:824:824) (972:972:972)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT datab (780:780:780) (902:902:902)) + (PORT datac (872:872:872) (1009:1009:1009)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~6) + (DELAY + (ABSOLUTE + (PORT datac (897:897:897) (1030:1030:1030)) + (PORT datad (1066:1066:1066) (1247:1247:1247)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~9) + (DELAY + (ABSOLUTE + (PORT datac (572:572:572) (683:683:683)) + (PORT datad (542:542:542) (632:632:632)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (651:651:651)) + (PORT datab (547:547:547) (647:647:647)) + (PORT datac (486:486:486) (568:568:568)) + (PORT datad (1183:1183:1183) (1350:1350:1350)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (265:265:265)) + (PORT datab (642:642:642) (740:740:740)) + (PORT datac (352:352:352) (411:411:411)) + (PORT datad (619:619:619) (708:708:708)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal44\~0) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (484:484:484)) + (PORT datab (686:686:686) (821:821:821)) + (PORT datac (535:535:535) (634:634:634)) + (PORT datad (756:756:756) (905:905:905)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~16) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (660:660:660)) + (PORT datab (737:737:737) (838:838:838)) + (PORT datac (528:528:528) (622:622:622)) + (PORT datad (598:598:598) (682:682:682)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT datab (461:461:461) (539:539:539)) + (PORT datac (346:346:346) (409:409:409)) + (PORT datad (114:114:114) (136:136:136)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal50\~0) + (DELAY + (ABSOLUTE + (PORT datab (554:554:554) (662:662:662)) + (PORT datac (372:372:372) (439:439:439)) + (PORT datad (648:648:648) (765:765:765)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~2) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (794:794:794)) + (PORT datab (731:731:731) (860:860:860)) + (PORT datad (402:402:402) (483:483:483)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~17) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (648:648:648)) + (PORT datab (601:601:601) (680:680:680)) + (PORT datac (526:526:526) (619:619:619)) + (PORT datad (581:581:581) (663:663:663)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datac (894:894:894) (1057:1057:1057)) + (PORT datad (540:540:540) (631:631:631)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (409:409:409)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (105:105:105) (129:129:129)) + (PORT datad (589:589:589) (682:682:682)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (1033:1033:1033)) + (PORT datab (781:781:781) (903:903:903)) + (PORT datac (191:191:191) (228:228:228)) + (PORT datad (1020:1020:1020) (1182:1182:1182)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (674:674:674)) + (PORT datab (124:124:124) (156:156:156)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (832:832:832)) + (PORT datab (845:845:845) (1000:1000:1000)) + (PORT datac (837:837:837) (976:976:976)) + (PORT datad (1172:1172:1172) (1384:1384:1384)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (571:571:571)) + (PORT datac (350:350:350) (421:421:421)) + (PORT datad (781:781:781) (925:925:925)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (832:832:832)) + (PORT datab (253:253:253) (308:308:308)) + (PORT datac (938:938:938) (1081:1081:1081)) + (PORT datad (145:145:145) (182:182:182)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (481:481:481)) + (PORT datab (559:559:559) (663:663:663)) + (PORT datac (375:375:375) (457:457:457)) + (PORT datad (759:759:759) (909:909:909)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (1090:1090:1090)) + (PORT datab (862:862:862) (993:993:993)) + (PORT datac (979:979:979) (1128:1128:1128)) + (PORT datad (857:857:857) (1004:1004:1004)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (859:859:859)) + (PORT datab (696:696:696) (819:819:819)) + (PORT datac (580:580:580) (688:688:688)) + (PORT datad (936:936:936) (1067:1067:1067)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT datac (375:375:375) (436:436:436)) + (PORT datad (979:979:979) (1143:1143:1143)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (387:387:387)) + (PORT datac (606:606:606) (703:703:703)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (141:141:141)) + (PORT datab (132:132:132) (167:167:167)) + (PORT datac (358:358:358) (422:422:422)) + (PORT datad (1181:1181:1181) (1348:1348:1348)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (651:651:651)) + (PORT datab (682:682:682) (795:795:795)) + (PORT datac (379:379:379) (441:441:441)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (520:520:520) (625:625:625)) + (PORT datab (880:880:880) (1044:1044:1044)) + (PORT datac (766:766:766) (890:890:890)) + (PORT datad (106:106:106) (130:130:130)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (DELAY + (ABSOLUTE + (PORT dataa (159:159:159) (217:217:217)) + (PORT datac (500:500:500) (585:585:585)) + (PORT datad (507:507:507) (594:594:594)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1160:1160:1160)) + (PORT datac (638:638:638) (752:752:752)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (388:388:388)) + (PORT datab (637:637:637) (747:747:747)) + (PORT datac (521:521:521) (627:627:627)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (414:414:414)) + (PORT datab (347:347:347) (398:398:398)) + (PORT datac (523:523:523) (630:630:630)) + (PORT datad (494:494:494) (570:570:570)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (584:584:584)) + (PORT datab (638:638:638) (743:743:743)) + (PORT datac (1023:1023:1023) (1194:1194:1194)) + (PORT datad (484:484:484) (556:556:556)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (1085:1085:1085)) + (PORT datac (898:898:898) (1044:1044:1044)) + (PORT datad (656:656:656) (761:761:761)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datac (448:448:448) (528:528:528)) + (PORT datad (490:490:490) (584:584:584)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (1085:1085:1085)) + (PORT datab (915:915:915) (1066:1066:1066)) + (PORT datac (835:835:835) (984:984:984)) + (PORT datad (668:668:668) (776:776:776)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (968:968:968)) + (PORT datab (691:691:691) (816:816:816)) + (PORT datac (804:804:804) (935:935:935)) + (PORT datad (446:446:446) (503:503:503)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (551:551:551)) + (PORT datab (694:694:694) (803:803:803)) + (PORT datac (752:752:752) (855:855:855)) + (PORT datad (715:715:715) (832:832:832)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (384:384:384)) + (PORT datab (534:534:534) (640:640:640)) + (PORT datad (627:627:627) (727:727:727)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (1011:1011:1011)) + (PORT datab (539:539:539) (636:636:636)) + (PORT datac (912:912:912) (1095:1095:1095)) + (PORT datad (688:688:688) (798:798:798)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (976:976:976)) + (PORT datab (865:865:865) (1032:1032:1032)) + (PORT datac (748:748:748) (868:868:868)) + (PORT datad (877:877:877) (994:994:994)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (548:548:548)) + (PORT datab (1013:1013:1013) (1170:1170:1170)) + (PORT datac (462:462:462) (531:531:531)) + (PORT datad (841:841:841) (969:969:969)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (782:782:782)) + (PORT datac (526:526:526) (615:615:615)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (588:588:588)) + (PORT datab (532:532:532) (619:619:619)) + (PORT datac (912:912:912) (1095:1095:1095)) + (PORT datad (688:688:688) (798:798:798)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT datac (963:963:963) (1115:1115:1115)) + (PORT datad (1142:1142:1142) (1323:1323:1323)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (145:145:145)) + (PORT datab (632:632:632) (729:729:729)) + (PORT datac (877:877:877) (995:995:995)) + (PORT datad (817:817:817) (953:953:953)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~1) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (1009:1009:1009)) + (PORT datab (537:537:537) (633:633:633)) + (PORT datac (915:915:915) (1098:1098:1098)) + (PORT datad (693:693:693) (804:804:804)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1256:1256:1256) (1471:1471:1471)) + (PORT datab (521:521:521) (603:603:603)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (232:232:232) (271:271:271)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (292:292:292)) + (PORT datab (518:518:518) (600:600:600)) + (PORT datac (1240:1240:1240) (1447:1447:1447)) + (PORT datad (622:622:622) (714:714:714)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (294:294:294)) + (PORT datab (520:520:520) (602:602:602)) + (PORT datac (1240:1240:1240) (1447:1447:1447)) + (PORT datad (102:102:102) (120:120:120)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal38\~2) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (1089:1089:1089)) + (PORT datab (876:876:876) (1032:1032:1032)) + (PORT datac (978:978:978) (1128:1128:1128)) + (PORT datad (815:815:815) (930:930:930)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (708:708:708)) + (PORT datab (616:616:616) (736:736:736)) + (PORT datac (315:315:315) (370:370:370)) + (PORT datad (487:487:487) (571:571:571)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (551:551:551)) + (PORT datab (784:784:784) (923:923:923)) + (PORT datac (325:325:325) (381:381:381)) + (PORT datad (316:316:316) (360:360:360)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datab (1101:1101:1101) (1266:1266:1266)) + (PORT datac (656:656:656) (766:766:766)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (299:299:299)) + (PORT datab (524:524:524) (606:606:606)) + (PORT datac (1238:1238:1238) (1444:1444:1444)) + (PORT datad (188:188:188) (219:219:219)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (850:850:850)) + (PORT datab (657:657:657) (761:761:761)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (717:717:717) (845:845:845)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (430:430:430)) + (PORT datab (336:336:336) (396:396:396)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (638:638:638) (735:735:735)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (581:581:581)) + (PORT datab (122:122:122) (157:157:157)) + (PORT datac (335:335:335) (390:390:390)) + (PORT datad (361:361:361) (420:420:420)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (920:920:920)) + (PORT datab (687:687:687) (811:811:811)) + (PORT datac (373:373:373) (443:443:443)) + (PORT datad (633:633:633) (722:722:722)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (454:454:454)) + (PORT datab (621:621:621) (717:717:717)) + (PORT datac (1030:1030:1030) (1202:1202:1202)) + (PORT datad (307:307:307) (363:363:363)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (963:963:963)) + (PORT datab (633:633:633) (730:730:730)) + (PORT datac (670:670:670) (792:792:792)) + (PORT datad (359:359:359) (425:425:425)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (971:971:971)) + (PORT datab (377:377:377) (452:452:452)) + (PORT datac (666:666:666) (788:788:788)) + (PORT datad (778:778:778) (892:892:892)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|M5\~0) (DELAY (ABSOLUTE - (PORT dataa (503:503:503) (590:590:590)) - (PORT datab (213:213:213) (271:271:271)) - (PORT datad (482:482:482) (560:560:560)) + (PORT dataa (612:612:612) (716:716:716)) + (PORT datab (144:144:144) (193:193:193)) + (PORT datad (611:611:611) (705:705:705)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -1100,9 +2384,9 @@ (INSTANCE z80_\|sequencer_\|M5) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) + (PORT clk (920:920:920) (927:927:927)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (903:903:903)) + (PORT clrn (927:927:927) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -1116,36 +2400,56 @@ (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) (DELAY (ABSOLUTE - (PORT dataa (766:766:766) (908:908:908)) - (PORT datac (704:704:704) (825:825:825)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (908:908:908) (1071:1071:1071)) + (PORT datac (1462:1462:1462) (1689:1689:1689)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) + (INSTANCE z80_\|execute_\|setM1\~29) (DELAY (ABSOLUTE - (PORT datac (644:644:644) (759:759:759)) - (PORT datad (965:965:965) (1119:1119:1119)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (333:333:333) (389:389:389)) + (PORT datab (516:516:516) (605:605:605)) + (PORT datac (563:563:563) (665:665:665)) + (PORT datad (364:364:364) (430:430:430)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) + (INSTANCE z80_\|execute_\|ctl_mRead\~25) (DELAY (ABSOLUTE - (PORT dataa (475:475:475) (556:556:556)) - (PORT datab (923:923:923) (1057:1057:1057)) - (PORT datac (554:554:554) (638:638:638)) - (PORT datad (481:481:481) (562:562:562)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (1104:1104:1104) (1300:1300:1300)) + (PORT datab (377:377:377) (453:453:453)) + (PORT datac (376:376:376) (440:440:440)) + (PORT datad (309:309:309) (358:358:358)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1059:1059:1059) (1216:1216:1216)) + (PORT datab (516:516:516) (618:618:618)) + (PORT datac (102:102:102) (124:124:124)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -1156,204 +2460,10 @@ (INSTANCE z80_\|execute_\|ctl_ir_we\~7) (DELAY (ABSOLUTE - (PORT dataa (733:733:733) (849:849:849)) - (PORT datab (328:328:328) (389:389:389)) - (PORT datac (790:790:790) (910:910:910)) - (PORT datad (513:513:513) (589:589:589)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (774:774:774) (913:913:913)) - (PORT datab (1190:1190:1190) (1372:1372:1372)) - (PORT datac (163:163:163) (221:221:221)) - (PORT datad (750:750:750) (877:877:877)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (931:931:931)) - (PORT datab (711:711:711) (822:822:822)) - (PORT datac (321:321:321) (376:376:376)) - (PORT datad (331:331:331) (384:384:384)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (942:942:942)) - (PORT datab (644:644:644) (771:771:771)) - (PORT datac (869:869:869) (1018:1018:1018)) - (PORT datad (924:924:924) (1070:1070:1070)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) - (DELAY - (ABSOLUTE - (PORT datab (746:746:746) (866:866:866)) - (PORT datac (744:744:744) (871:871:871)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (401:401:401)) - (PORT datab (324:324:324) (385:385:385)) - (PORT datac (388:388:388) (467:467:467)) - (PORT datad (514:514:514) (590:590:590)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (768:768:768) (882:882:882)) - (PORT datab (641:641:641) (768:768:768)) - (PORT datac (865:865:865) (1014:1014:1014)) - (PORT datad (737:737:737) (844:844:844)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (732:732:732) (848:848:848)) - (PORT datab (334:334:334) (395:395:395)) - (PORT datac (788:788:788) (908:908:908)) - (PORT datad (511:511:511) (587:587:587)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT datab (750:750:750) (871:871:871)) - (PORT datac (753:753:753) (881:881:881)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (420:420:420)) - (PORT datab (340:340:340) (403:403:403)) - (PORT datac (383:383:383) (461:461:461)) - (PORT datad (509:509:509) (585:585:585)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT datac (614:614:614) (724:724:724)) - (PORT datad (658:658:658) (786:786:786)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (727:727:727)) - (PORT datab (339:339:339) (398:398:398)) - (PORT datac (846:846:846) (965:965:965)) - (PORT datad (629:629:629) (719:719:719)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT datab (107:107:107) (138:138:138)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (613:613:613) (698:698:698)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1741:1741:1741) (1988:1988:1988)) - (PORT datab (1216:1216:1216) (1398:1398:1398)) - (PORT datac (541:541:541) (633:633:633)) - (PORT datad (566:566:566) (645:645:645)) + (PORT dataa (702:702:702) (833:833:833)) + (PORT datab (252:252:252) (307:307:307)) + (PORT datac (936:936:936) (1080:1080:1080)) + (PORT datad (146:146:146) (182:182:182)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -1361,4033 +2471,15 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (770:770:770)) - (PORT datab (625:625:625) (742:742:742)) - (PORT datac (642:642:642) (774:774:774)) - (PORT datad (107:107:107) (126:126:126)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (754:754:754) (890:890:890)) - (PORT datab (180:180:180) (243:243:243)) - (PORT datac (703:703:703) (806:806:806)) - (PORT datad (729:729:729) (842:842:842)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1232:1232:1232)) - (PORT datab (962:962:962) (1130:1130:1130)) - (PORT datac (950:950:950) (1117:1117:1117)) - (PORT datad (772:772:772) (889:889:889)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) - (DELAY - (ABSOLUTE - (PORT datac (625:625:625) (742:742:742)) - (PORT datad (745:745:745) (867:867:867)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (721:721:721) (830:830:830)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (358:358:358) (429:429:429)) - (PORT datad (1044:1044:1044) (1192:1192:1192)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (397:397:397)) - (PORT datab (357:357:357) (421:421:421)) - (PORT datac (89:89:89) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datab (732:732:732) (859:859:859)) - (PORT datad (739:739:739) (867:867:867)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (511:511:511) (599:599:599)) - (PORT datac (128:128:128) (169:169:169)) - (PORT datad (475:475:475) (552:552:552)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (903:903:903)) - (PORT ena (639:639:639) (693:693:693)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1172:1172:1172) (1353:1353:1353)) - (PORT datab (745:745:745) (864:864:864)) - (PORT datac (753:753:753) (892:892:892)) - (PORT datad (749:749:749) (876:876:876)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) - (DELAY - (ABSOLUTE - (PORT dataa (843:843:843) (954:954:954)) - (PORT datab (138:138:138) (177:177:177)) - (PORT datac (174:174:174) (210:210:210)) - (PORT datad (594:594:594) (678:678:678)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (1011:1011:1011)) - (PORT datab (122:122:122) (154:154:154)) - (PORT datac (403:403:403) (485:485:485)) - (PORT datad (313:313:313) (360:360:360)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (755:755:755) (892:892:892)) - (PORT datab (720:720:720) (828:828:828)) - (PORT datac (162:162:162) (221:221:221)) - (PORT datad (165:165:165) (218:218:218)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (411:411:411)) - (PORT datab (445:445:445) (514:514:514)) - (PORT datac (473:473:473) (543:543:543)) - (PORT datad (207:207:207) (256:256:256)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT datab (356:356:356) (421:421:421)) - (PORT datac (438:438:438) (507:507:507)) - (PORT datad (318:318:318) (371:371:371)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datac (736:736:736) (871:871:871)) - (PORT datad (876:876:876) (1016:1016:1016)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) - (DELAY - (ABSOLUTE - (PORT datac (521:521:521) (625:625:625)) - (PORT datad (506:506:506) (597:597:597)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (463:463:463) (532:532:532)) - (PORT datab (705:705:705) (808:808:808)) - (PORT datac (455:455:455) (527:527:527)) - (PORT datad (380:380:380) (445:445:445)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (584:584:584) (666:666:666)) - (PORT datac (276:276:276) (311:311:311)) - (PORT datad (107:107:107) (126:126:126)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT datab (847:847:847) (986:986:986)) - (PORT datac (533:533:533) (651:651:651)) - (PORT datad (967:967:967) (1120:1120:1120)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (399:399:399)) - (PORT datab (349:349:349) (424:424:424)) - (PORT datac (313:313:313) (371:371:371)) - (PORT datad (379:379:379) (445:445:445)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT dataa (727:727:727) (836:836:836)) - (PORT datac (481:481:481) (570:570:570)) - (PORT datad (428:428:428) (489:489:489)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (509:509:509) (596:596:596)) - (PORT datad (118:118:118) (141:141:141)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datac (609:609:609) (716:716:716)) - (PORT datad (555:555:555) (636:636:636)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (647:647:647)) - (PORT datab (991:991:991) (1146:1146:1146)) - (PORT datac (275:275:275) (310:310:310)) - (PORT datad (534:534:534) (603:603:603)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (590:590:590)) - (PORT datab (581:581:581) (701:701:701)) - (PORT datac (616:616:616) (703:703:703)) - (PORT datad (613:613:613) (716:716:716)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (834:834:834) (922:922:922)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) - (DELAY - (ABSOLUTE - (PORT datab (503:503:503) (601:601:601)) - (PORT datad (829:829:829) (954:954:954)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (1013:1013:1013)) - (PORT datab (425:425:425) (514:514:514)) - (PORT datac (718:718:718) (825:825:825)) - (PORT datad (312:312:312) (359:359:359)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1350:1350:1350) (1555:1555:1555)) - (PORT datab (1579:1579:1579) (1811:1811:1811)) - (PORT datac (634:634:634) (733:733:733)) - (PORT datad (574:574:574) (661:661:661)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1031:1031:1031) (1175:1175:1175)) - (PORT datab (461:461:461) (540:540:540)) - (PORT datad (706:706:706) (808:808:808)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT datab (848:848:848) (986:986:986)) - (PORT datac (653:653:653) (796:796:796)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (707:707:707)) - (PORT datab (507:507:507) (598:598:598)) - (PORT datac (1121:1121:1121) (1291:1291:1291)) - (PORT datad (635:635:635) (729:729:729)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datac (993:993:993) (1146:1146:1146)) - (PORT datad (903:903:903) (1053:1053:1053)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1376:1376:1376)) - (PORT datab (139:139:139) (177:177:177)) - (PORT datac (198:198:198) (244:244:244)) - (PORT datad (561:561:561) (633:633:633)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (267:267:267)) - (PORT datab (141:141:141) (179:179:179)) - (PORT datac (1171:1171:1171) (1348:1348:1348)) - (PORT datad (843:843:843) (956:956:956)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~2) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (801:801:801)) - (PORT datac (827:827:827) (959:959:959)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (699:699:699)) - (PORT datab (383:383:383) (454:454:454)) - (PORT datac (664:664:664) (778:778:778)) - (PORT datad (773:773:773) (895:895:895)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~0) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (799:799:799)) - (PORT datab (347:347:347) (416:416:416)) - (PORT datac (501:501:501) (584:584:584)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (419:419:419) (474:474:474)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (324:324:324) (368:368:368)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (469:469:469) (544:544:544)) - (PORT datab (633:633:633) (724:724:724)) - (PORT datac (574:574:574) (657:657:657)) - (PORT datad (779:779:779) (909:909:909)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (759:759:759) (901:901:901)) - (PORT datad (510:510:510) (614:614:614)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT datac (588:588:588) (700:700:700)) - (PORT datad (510:510:510) (613:613:613)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (793:793:793)) - (PORT datab (895:895:895) (1023:1023:1023)) - (PORT datac (284:284:284) (317:317:317)) - (PORT datad (939:939:939) (1078:1078:1078)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1294:1294:1294)) - (PORT datab (662:662:662) (756:756:756)) - (PORT datac (451:451:451) (515:515:515)) - (PORT datad (455:455:455) (524:524:524)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT datab (785:785:785) (914:914:914)) - (PORT datac (952:952:952) (1119:1119:1119)) - (PORT datad (947:947:947) (1103:1103:1103)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (801:801:801)) - (PORT datab (784:784:784) (911:911:911)) - (PORT datac (1367:1367:1367) (1564:1564:1564)) - (PORT datad (1314:1314:1314) (1515:1515:1515)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (1016:1016:1016)) - (PORT datab (432:432:432) (522:522:522)) - (PORT datac (441:441:441) (501:501:501)) - (PORT datad (747:747:747) (861:861:861)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (979:979:979)) - (PORT datab (506:506:506) (605:605:605)) - (PORT datac (726:726:726) (818:818:818)) - (PORT datad (447:447:447) (512:512:512)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (496:496:496) (586:586:586)) - (PORT datab (652:652:652) (765:765:765)) - (PORT datac (831:831:831) (959:959:959)) - (PORT datad (485:485:485) (575:575:575)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1137:1137:1137) (1305:1305:1305)) - (PORT datab (476:476:476) (559:559:559)) - (PORT datac (709:709:709) (818:818:818)) - (PORT datad (635:635:635) (736:736:736)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (977:977:977)) - (PORT datab (654:654:654) (767:767:767)) - (PORT datac (469:469:469) (555:555:555)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (935:935:935)) - (PORT datab (713:713:713) (824:824:824)) - (PORT datac (308:308:308) (361:361:361)) - (PORT datad (327:327:327) (379:379:379)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (235:235:235)) - (PORT datab (742:742:742) (844:844:844)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (165:165:165) (196:196:196)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT datab (533:533:533) (617:617:617)) - (PORT datac (309:309:309) (362:362:362)) - (PORT datad (699:699:699) (801:801:801)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (1016:1016:1016)) - (PORT datab (127:127:127) (160:160:160)) - (PORT datac (413:413:413) (496:496:496)) - (PORT datad (310:310:310) (357:357:357)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (242:242:242)) - (PORT datab (638:638:638) (736:736:736)) - (PORT datac (325:325:325) (373:373:373)) - (PORT datad (458:458:458) (529:529:529)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (708:708:708)) - (PORT datab (1462:1462:1462) (1678:1678:1678)) - (PORT datac (446:446:446) (521:521:521)) - (PORT datad (902:902:902) (1046:1046:1046)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (767:767:767)) - (PORT datab (382:382:382) (453:453:453)) - (PORT datac (510:510:510) (572:572:572)) - (PORT datad (333:333:333) (391:391:391)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1313:1313:1313) (1504:1504:1504)) - (PORT datab (475:475:475) (552:552:552)) - (PORT datac (291:291:291) (338:338:338)) - (PORT datad (578:578:578) (665:665:665)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) - (DELAY - (ABSOLUTE - (PORT dataa (953:953:953) (1106:1106:1106)) - (PORT datab (893:893:893) (1020:1020:1020)) - (PORT datac (881:881:881) (1017:1017:1017)) - (PORT datad (627:627:627) (700:700:700)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT datac (440:440:440) (511:511:511)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (171:171:171) (209:209:209)) - (PORT datab (109:109:109) (141:141:141)) - (PORT datac (425:425:425) (487:487:487)) - (PORT datad (103:103:103) (121:121:121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (543:543:543)) - (PORT datab (472:472:472) (549:549:549)) - (PORT datac (492:492:492) (562:562:562)) - (PORT datad (343:343:343) (400:400:400)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1044:1044:1044) (1235:1235:1235)) - (PORT datab (959:959:959) (1127:1127:1127)) - (PORT datac (960:960:960) (1128:1128:1128)) - (PORT datad (763:763:763) (879:879:879)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (810:810:810)) - (PORT datab (464:464:464) (540:540:540)) - (PORT datac (852:852:852) (975:975:975)) - (PORT datad (761:761:761) (861:861:861)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (551:551:551) (663:663:663)) - (PORT datac (467:467:467) (536:536:536)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (467:467:467) (543:543:543)) - (PORT datac (886:886:886) (1008:1008:1008)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~3) - (DELAY - (ABSOLUTE - (PORT datab (566:566:566) (683:683:683)) - (PORT datad (519:519:519) (622:622:622)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~31) - (DELAY - (ABSOLUTE - (PORT dataa (579:579:579) (681:681:681)) - (PORT datab (377:377:377) (448:448:448)) - (PORT datac (582:582:582) (660:660:660)) - (PORT datad (543:543:543) (616:616:616)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (111:111:111) (146:146:146)) - (PORT datab (510:510:510) (606:606:606)) - (PORT datac (739:739:739) (880:880:880)) - (PORT datad (337:337:337) (396:396:396)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~30) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (732:732:732)) - (PORT datab (377:377:377) (447:447:447)) - (PORT datac (329:329:329) (373:373:373)) - (PORT datad (589:589:589) (675:675:675)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (550:550:550)) - (PORT datab (807:807:807) (928:928:928)) - (PORT datac (460:460:460) (537:537:537)) - (PORT datad (448:448:448) (520:520:520)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (994:994:994)) - (PORT datab (1111:1111:1111) (1257:1257:1257)) - (PORT datac (460:460:460) (536:536:536)) - (PORT datad (648:648:648) (744:744:744)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (744:744:744)) - (PORT datab (465:465:465) (536:536:536)) - (PORT datac (91:91:91) (115:115:115)) - (PORT datad (404:404:404) (452:452:452)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT datab (508:508:508) (606:606:606)) - (PORT datac (635:635:635) (747:747:747)) - (PORT datad (483:483:483) (573:573:573)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (313:313:313) (368:368:368)) - (PORT datab (353:353:353) (415:415:415)) - (PORT datac (571:571:571) (652:652:652)) - (PORT datad (308:308:308) (366:366:366)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (408:408:408)) - (PORT datab (528:528:528) (636:636:636)) - (PORT datac (589:589:589) (701:701:701)) - (PORT datad (737:737:737) (874:874:874)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (768:768:768)) - (PORT datab (377:377:377) (441:441:441)) - (PORT datac (455:455:455) (517:517:517)) - (PORT datad (332:332:332) (389:389:389)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (758:758:758) (900:900:900)) - (PORT datab (900:900:900) (1041:1041:1041)) - (PORT datac (584:584:584) (695:695:695)) - (PORT datad (512:512:512) (615:615:615)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (679:679:679)) - (PORT datab (598:598:598) (694:694:694)) - (PORT datac (811:811:811) (933:933:933)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) - (DELAY - (ABSOLUTE - (PORT datab (105:105:105) (135:135:135)) - (PORT datac (344:344:344) (399:399:399)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (501:501:501) (604:604:604)) - (PORT datab (366:366:366) (434:434:434)) - (PORT datac (499:499:499) (592:592:592)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (790:790:790)) - (PORT datab (756:756:756) (857:857:857)) - (PORT datac (1115:1115:1115) (1284:1284:1284)) - (PORT datad (490:490:490) (570:570:570)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1232:1232:1232)) - (PORT datab (963:963:963) (1131:1131:1131)) - (PORT datac (947:947:947) (1114:1114:1114)) - (PORT datad (775:775:775) (892:892:892)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (765:765:765)) - (PORT datab (641:641:641) (757:757:757)) - (PORT datac (637:637:637) (761:761:761)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (748:748:748) (859:859:859)) - (PORT datab (127:127:127) (159:159:159)) - (PORT datac (948:948:948) (1090:1090:1090)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (925:925:925)) - (PORT datac (810:810:810) (962:962:962)) - (PORT datad (736:736:736) (859:859:859)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~2) - (DELAY - (ABSOLUTE - (PORT datac (740:740:740) (875:875:875)) - (PORT datad (712:712:712) (830:830:830)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (917:917:917) (1072:1072:1072)) - (PORT datab (920:920:920) (1077:1077:1077)) - (PORT datac (581:581:581) (667:667:667)) - (PORT datad (1015:1015:1015) (1167:1167:1167)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (978:978:978)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (959:959:959) (1115:1115:1115)) - (PORT datad (610:610:610) (701:701:701)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (467:467:467)) - (PORT datab (1082:1082:1082) (1245:1245:1245)) - (PORT datac (428:428:428) (488:488:488)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (816:816:816)) - (PORT datab (391:391:391) (446:446:446)) - (PORT datac (392:392:392) (447:447:447)) - (PORT datad (426:426:426) (488:488:488)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (645:645:645)) - (PORT datab (299:299:299) (348:348:348)) - (PORT datac (385:385:385) (458:458:458)) - (PORT datad (456:456:456) (527:527:527)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~32) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (792:792:792)) - (PORT datab (978:978:978) (1138:1138:1138)) - (PORT datac (927:927:927) (1064:1064:1064)) - (PORT datad (456:456:456) (527:527:527)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~33) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (656:656:656)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (679:679:679) (768:768:768)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (678:678:678)) - (PORT datab (474:474:474) (545:545:545)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (287:287:287) (327:327:327)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (724:724:724)) - (PORT datad (558:558:558) (653:653:653)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (570:570:570) (671:671:671)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (430:430:430) (492:492:492)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (677:677:677) (806:806:806)) - (PORT datad (1881:1881:1881) (2196:2196:2196)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_DAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (153:153:153) (704:704:704)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (314:314:314) (320:320:320)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) - (DELAY - (ABSOLUTE - (PORT dataa (154:154:154) (213:213:213)) - (PORT datab (149:149:149) (204:204:204)) - (PORT datad (133:133:133) (178:178:178)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_CLK\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (153:153:153) (704:704:704)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (2168:2168:2168) (2437:2437:2437)) - (PORT clrn (905:905:905) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (122:122:122) (160:160:160)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (131:131:131) (168:168:168)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (124:124:124) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (301:301:301) (343:343:343)) - (PORT clrn (905:905:905) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (124:124:124) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (124:124:124) (164:164:164)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (273:273:273)) - (PORT datab (136:136:136) (186:186:186)) - (PORT datac (123:123:123) (167:167:167)) - (PORT datad (121:121:121) (160:160:160)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (188:188:188)) - (PORT datab (136:136:136) (187:187:187)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (122:122:122) (161:161:161)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datad (123:123:123) (162:162:162)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (146:146:146)) - (PORT datad (124:124:124) (163:163:163)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (146:146:146)) - (PORT datac (116:116:116) (157:157:157)) - (PORT datad (124:124:124) (163:163:163)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (911:911:911)) - (PORT ena (869:869:869) (974:974:974)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) - (DELAY - (ABSOLUTE - (PORT dataa (153:153:153) (212:212:212)) - (PORT datab (142:142:142) (195:195:195)) - (PORT datad (134:134:134) (178:178:178)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (911:911:911)) - (PORT ena (869:869:869) (974:974:974)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) - (DELAY - (ABSOLUTE - (PORT dataa (153:153:153) (212:212:212)) - (PORT datab (150:150:150) (205:205:205)) - (PORT datad (129:129:129) (172:172:172)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (911:911:911)) - (PORT ena (869:869:869) (974:974:974)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (149:149:149) (206:206:206)) - (PORT datab (151:151:151) (207:207:207)) - (PORT datad (130:130:130) (174:174:174)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (911:911:911)) - (PORT ena (869:869:869) (974:974:974)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (152:152:152) (210:210:210)) - (PORT datab (150:150:150) (205:205:205)) - (PORT datac (2071:2071:2071) (2353:2353:2353)) - (PORT datad (134:134:134) (179:179:179)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (154:154:154) (212:212:212)) - (PORT datac (138:138:138) (186:186:186)) - (PORT datad (137:137:137) (182:182:182)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (106:106:106) (137:137:137)) - (PORT datac (532:532:532) (628:628:628)) - (PORT datad (133:133:133) (176:176:176)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT asdata (2269:2269:2269) (2557:2557:2557)) - (PORT clrn (911:911:911) (917:917:917)) - (PORT ena (663:663:663) (729:729:729)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT asdata (296:296:296) (336:336:336)) - (PORT clrn (911:911:911) (917:917:917)) - (PORT ena (663:663:663) (729:729:729)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT asdata (314:314:314) (361:361:361)) - (PORT clrn (911:911:911) (917:917:917)) - (PORT ena (663:663:663) (729:729:729)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT asdata (681:681:681) (780:780:780)) - (PORT clrn (911:911:911) (916:916:916)) - (PORT ena (920:920:920) (1042:1042:1042)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT asdata (498:498:498) (568:568:568)) - (PORT clrn (911:911:911) (917:917:917)) - (PORT ena (663:663:663) (729:729:729)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT asdata (814:814:814) (921:921:921)) - (PORT clrn (911:911:911) (916:916:916)) - (PORT ena (920:920:920) (1042:1042:1042)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT asdata (492:492:492) (551:551:551)) - (PORT clrn (911:911:911) (916:916:916)) - (PORT ena (920:920:920) (1042:1042:1042)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT asdata (800:800:800) (902:902:902)) - (PORT clrn (911:911:911) (917:917:917)) - (PORT ena (663:663:663) (729:729:729)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT asdata (772:772:772) (872:872:872)) - (PORT clrn (911:911:911) (917:917:917)) - (PORT ena (663:663:663) (730:730:730)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (780:780:780)) - (PORT datab (244:244:244) (307:307:307)) - (PORT datac (337:337:337) (418:418:418)) - (PORT datad (639:639:639) (750:750:750)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (414:414:414)) - (PORT datab (154:154:154) (209:209:209)) - (PORT datad (327:327:327) (396:396:396)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (193:193:193)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (236:236:236)) - (PORT datac (280:280:280) (315:315:315)) - (PORT datad (134:134:134) (173:173:173)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) - (DELAY - (ABSOLUTE - (PORT dataa (552:552:552) (658:658:658)) - (PORT datab (111:111:111) (142:142:142)) - (PORT datac (2071:2071:2071) (2353:2353:2353)) - (PORT datad (274:274:274) (317:317:317)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (911:911:911)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (759:759:759)) - (PORT datab (338:338:338) (416:416:416)) - (PORT datac (136:136:136) (184:184:184)) - (PORT datad (486:486:486) (573:573:573)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (150:150:150) (205:205:205)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (628:628:628) (735:735:735)) - (PORT datad (326:326:326) (395:395:395)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT dataa (519:519:519) (623:623:623)) - (PORT datad (339:339:339) (400:400:400)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|extended) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (PORT ena (945:945:945) (1082:1082:1082)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (419:419:419)) - (PORT datab (150:150:150) (206:206:206)) - (PORT datac (367:367:367) (443:443:443)) - (PORT datad (387:387:387) (458:458:458)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (520:520:520) (624:624:624)) - (PORT datab (630:630:630) (764:764:764)) - (PORT datad (338:338:338) (399:399:399)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (782:782:782)) - (PORT datab (236:236:236) (298:298:298)) - (PORT datac (344:344:344) (426:426:426)) - (PORT datad (635:635:635) (745:745:745)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (781:781:781)) - (PORT datac (338:338:338) (419:419:419)) - (PORT datad (228:228:228) (282:282:282)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (781:781:781)) - (PORT datab (243:243:243) (306:306:306)) - (PORT datac (338:338:338) (419:419:419)) - (PORT datad (639:639:639) (749:749:749)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) - (DELAY - (ABSOLUTE - (PORT dataa (118:118:118) (150:150:150)) - (PORT datab (249:249:249) (314:314:314)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (634:634:634) (745:745:745)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (249:249:249) (314:314:314)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (358:358:358) (431:431:431)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (525:525:525) (631:631:631)) - (PORT datad (166:166:166) (195:195:195)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (900:900:900)) - (PORT datab (656:656:656) (766:766:766)) - (PORT datac (427:427:427) (495:495:495)) - (PORT datad (512:512:512) (616:616:616)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1044:1044:1044) (1236:1236:1236)) - (PORT datab (958:958:958) (1126:1126:1126)) - (PORT datac (963:963:963) (1130:1130:1130)) - (PORT datad (760:760:760) (875:875:875)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT datab (781:781:781) (909:909:909)) - (PORT datac (956:956:956) (1124:1124:1124)) - (PORT datad (946:946:946) (1101:1101:1101)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~19) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (789:789:789)) - (PORT datab (640:640:640) (755:755:755)) - (PORT datad (750:750:750) (873:873:873)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (472:472:472) (549:549:549)) - (PORT datab (497:497:497) (577:577:577)) - (PORT datac (424:424:424) (492:492:492)) - (PORT datad (431:431:431) (485:485:485)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (552:552:552)) - (PORT datab (640:640:640) (745:745:745)) - (PORT datac (423:423:423) (489:489:489)) - (PORT datad (111:111:111) (132:132:132)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datac (101:101:101) (122:122:122)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (796:796:796)) - (PORT datab (624:624:624) (742:742:742)) - (PORT datac (285:285:285) (335:335:335)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (456:456:456) (531:531:531)) - (PORT datab (460:460:460) (533:533:533)) - (PORT datac (286:286:286) (329:329:329)) - (PORT datad (457:457:457) (532:532:532)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (641:641:641)) - (PORT datad (643:643:643) (767:767:767)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (702:702:702)) - (PORT datab (377:377:377) (448:448:448)) - (PORT datac (617:617:617) (716:716:716)) - (PORT datad (574:574:574) (655:655:655)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~1) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (769:769:769)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (616:616:616) (716:716:716)) - (PORT datad (331:331:331) (388:388:388)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (516:516:516) (606:606:606)) - (PORT datac (616:616:616) (716:716:716)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT datab (637:637:637) (752:752:752)) - (PORT datac (713:713:713) (826:826:826)) - (PORT datad (623:623:623) (738:738:738)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (407:407:407)) - (PORT datab (450:450:450) (530:530:530)) - (PORT datac (661:661:661) (750:750:750)) - (PORT datad (454:454:454) (524:524:524)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (956:956:956) (1112:1112:1112)) - (PORT datab (549:549:549) (647:647:647)) - (PORT datac (660:660:660) (763:763:763)) - (PORT datad (947:947:947) (1091:1091:1091)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (1274:1274:1274) (1448:1448:1448)) - (PORT datab (483:483:483) (562:562:562)) - (PORT datac (513:513:513) (617:617:617)) - (PORT datad (515:515:515) (612:612:612)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (463:463:463) (538:538:538)) - (PORT datac (537:537:537) (655:655:655)) - (PORT datad (531:531:531) (637:637:637)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (147:147:147)) - (PORT datab (698:698:698) (794:794:794)) - (PORT datac (1023:1023:1023) (1168:1168:1168)) - (PORT datad (474:474:474) (548:548:548)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (818:818:818)) - (PORT datac (728:728:728) (853:853:853)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (658:658:658)) - (PORT datab (596:596:596) (693:693:693)) - (PORT datac (756:756:756) (868:868:868)) - (PORT datad (515:515:515) (600:600:600)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1315:1315:1315) (1516:1516:1516)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (352:352:352) (413:413:413)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (804:804:804)) - (PORT datab (604:604:604) (703:703:703)) - (PORT datac (663:663:663) (751:751:751)) - (PORT datad (578:578:578) (664:664:664)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datad (643:643:643) (760:760:760)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (925:925:925) (909:909:909)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (122:122:122) (161:161:161)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (925:925:925) (909:909:909)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (925:925:925) (909:909:909)) - (PORT asdata (299:299:299) (340:340:340)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc_int\~0) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (605:605:605)) - (PORT datab (534:534:534) (637:637:637)) - (PORT datad (484:484:484) (573:573:573)) - (IOPATH dataa combout (166:166:166) (165:165:165)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|clrpc_int) - (DELAY - (ABSOLUTE - (PORT clk (925:925:925) (909:909:909)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (902:902:902)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (187:187:187)) - (PORT datab (133:133:133) (183:183:183)) - (PORT datad (120:120:120) (157:157:157)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) - (DELAY - (ABSOLUTE - (PORT datab (304:304:304) (361:361:361)) - (PORT datac (610:610:610) (726:726:726)) - (PORT datad (703:703:703) (820:820:820)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (951:951:951) (1105:1105:1105)) - (PORT datab (432:432:432) (503:503:503)) - (PORT datac (703:703:703) (805:805:805)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal38\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1193:1193:1193) (1382:1382:1382)) - (PORT datab (1042:1042:1042) (1200:1200:1200)) - (PORT datac (772:772:772) (874:874:874)) - (PORT datad (889:889:889) (1043:1043:1043)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) - (DELAY - (ABSOLUTE - (PORT datac (978:978:978) (1130:1130:1130)) - (PORT datad (875:875:875) (1013:1013:1013)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (272:272:272)) - (PORT datab (137:137:137) (174:174:174)) - (PORT datac (1177:1177:1177) (1354:1354:1354)) - (PORT datad (742:742:742) (857:857:857)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (563:563:563)) - (PORT datab (384:384:384) (451:451:451)) - (PORT datac (543:543:543) (621:621:621)) - (PORT datad (931:931:931) (1068:1068:1068)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (708:708:708)) - (PORT datab (504:504:504) (593:593:593)) - (PORT datac (331:331:331) (389:389:389)) - (PORT datad (902:902:902) (1045:1045:1045)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1094:1094:1094)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (449:449:449) (518:518:518)) - (PORT datad (369:369:369) (430:430:430)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1067:1067:1067) (1232:1232:1232)) - (PORT datab (291:291:291) (340:340:340)) - (PORT datac (649:649:649) (760:760:760)) - (PORT datad (1288:1288:1288) (1474:1474:1474)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (528:528:528)) - (PORT datab (947:947:947) (1091:1091:1091)) - (PORT datac (678:678:678) (767:767:767)) - (PORT datad (456:456:456) (532:532:532)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (959:959:959)) - (PORT datab (695:695:695) (797:797:797)) - (PORT datac (1187:1187:1187) (1374:1374:1374)) - (PORT datad (506:506:506) (597:597:597)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT datac (1363:1363:1363) (1560:1560:1560)) - (PORT datad (1312:1312:1312) (1513:1513:1513)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (498:498:498)) - (PORT datab (665:665:665) (778:778:778)) - (PORT datac (275:275:275) (317:317:317)) - (PORT datad (1291:1291:1291) (1477:1477:1477)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (112:112:112) (144:144:144)) - (PORT datac (520:520:520) (624:624:624)) - (PORT datad (714:714:714) (828:828:828)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (393:393:393)) - (PORT datab (348:348:348) (403:403:403)) - (PORT datac (440:440:440) (508:508:508)) - (PORT datad (553:553:553) (625:625:625)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (580:580:580)) - (PORT datac (590:590:590) (680:680:680)) - (PORT datad (1028:1028:1028) (1180:1180:1180)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (766:766:766)) - (PORT datab (570:570:570) (659:659:659)) - (PORT datac (695:695:695) (794:794:794)) - (PORT datad (1638:1638:1638) (1870:1870:1870)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (470:470:470) (548:548:548)) - (PORT datab (1375:1375:1375) (1580:1580:1580)) - (PORT datac (464:464:464) (546:546:546)) - (PORT datad (1632:1632:1632) (1864:1864:1864)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT dataa (485:485:485) (568:568:568)) - (PORT datab (612:612:612) (726:726:726)) - (PORT datac (930:930:930) (1072:1072:1072)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (496:496:496) (574:574:574)) - (PORT datab (550:550:550) (648:648:648)) - (PORT datac (704:704:704) (806:806:806)) - (PORT datad (655:655:655) (758:758:758)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (658:658:658)) - (PORT datab (786:786:786) (915:915:915)) - (PORT datac (951:951:951) (1118:1118:1118)) - (PORT datad (947:947:947) (1103:1103:1103)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (732:732:732) (848:848:848)) - (PORT datab (335:335:335) (396:396:396)) - (PORT datac (788:788:788) (908:908:908)) - (PORT datad (511:511:511) (587:587:587)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (733:733:733)) - (PORT datac (302:302:302) (356:356:356)) - (PORT datad (728:728:728) (850:850:850)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (226:226:226)) - (PORT datab (473:473:473) (553:553:553)) - (PORT datac (634:634:634) (721:721:721)) - (PORT datad (871:871:871) (1003:1003:1003)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (679:679:679)) - (PORT datac (557:557:557) (627:627:627)) - (PORT datad (532:532:532) (638:638:638)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1892:1892:1892)) - (PORT datab (1375:1375:1375) (1579:1579:1579)) - (PORT datac (454:454:454) (524:524:524)) - (PORT datad (644:644:644) (741:741:741)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (639:639:639)) - (PORT datab (706:706:706) (814:814:814)) - (PORT datac (454:454:454) (524:524:524)) - (PORT datad (903:903:903) (1055:1055:1055)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (535:535:535)) - (PORT datab (482:482:482) (563:563:563)) - (PORT datac (458:458:458) (530:530:530)) - (PORT datad (340:340:340) (387:387:387)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (766:766:766)) - (PORT datab (577:577:577) (666:666:666)) - (PORT datac (690:690:690) (789:789:789)) - (PORT datad (1631:1631:1631) (1863:1863:1863)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (427:427:427) (526:526:526)) - (PORT datab (578:578:578) (696:696:696)) - (PORT datac (370:370:370) (449:449:449)) - (PORT datad (547:547:547) (620:620:620)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (421:421:421)) - (PORT datab (457:457:457) (531:531:531)) - (PORT datad (450:450:450) (518:518:518)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (648:648:648)) - (PORT datab (341:341:341) (401:401:401)) - (PORT datac (535:535:535) (598:598:598)) - (PORT datad (479:479:479) (551:551:551)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1314:1314:1314) (1515:1515:1515)) - (PORT datab (530:530:530) (621:621:621)) - (PORT datac (825:825:825) (943:943:943)) - (PORT datad (437:437:437) (495:495:495)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (800:800:800)) - (PORT datab (111:111:111) (142:142:142)) - (PORT datac (97:97:97) (121:121:121)) - (PORT datad (451:451:451) (527:527:527)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (562:562:562)) - (PORT datab (460:460:460) (533:533:533)) - (PORT datac (270:270:270) (314:314:314)) - (PORT datad (431:431:431) (495:495:495)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT datab (788:788:788) (917:917:917)) - (PORT datac (949:949:949) (1116:1116:1116)) - (PORT datad (948:948:948) (1104:1104:1104)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (430:430:430)) - (PORT datab (474:474:474) (559:559:559)) - (PORT datac (501:501:501) (598:598:598)) - (PORT datad (1013:1013:1013) (1159:1159:1159)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datab (544:544:544) (650:650:650)) - (PORT datac (524:524:524) (626:626:626)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (521:521:521) (618:618:618)) - (PORT datab (476:476:476) (561:561:561)) - (PORT datac (640:640:640) (724:724:724)) - (PORT datad (1011:1011:1011) (1155:1155:1155)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1026:1026:1026) (1184:1184:1184)) - (PORT datab (473:473:473) (558:558:558)) - (PORT datac (501:501:501) (599:599:599)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (765:765:765) (888:888:888)) - (PORT datab (470:470:470) (545:545:545)) - (PORT datac (540:540:540) (638:638:638)) - (PORT datad (686:686:686) (787:787:787)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (767:767:767) (889:889:889)) - (PORT datab (703:703:703) (814:814:814)) - (PORT datac (549:549:549) (649:649:649)) - (PORT datad (622:622:622) (714:714:714)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (113:113:113) (141:141:141)) - (PORT datac (108:108:108) (132:132:132)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT datac (1370:1370:1370) (1568:1568:1568)) - (PORT datad (1316:1316:1316) (1518:1518:1518)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (153:153:153)) - (PORT datab (782:782:782) (909:909:909)) - (PORT datac (682:682:682) (780:780:780)) - (PORT datad (114:114:114) (136:136:136)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (552:552:552)) - (PORT datab (574:574:574) (655:655:655)) - (PORT datac (384:384:384) (435:435:435)) - (PORT datad (574:574:574) (649:649:649)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (419:419:419)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (276:276:276) (314:314:314)) - (PORT datad (103:103:103) (121:121:121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1741:1741:1741) (1988:1988:1988)) - (PORT datab (1216:1216:1216) (1398:1398:1398)) - (PORT datac (458:458:458) (532:532:532)) - (PORT datad (557:557:557) (631:631:631)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (554:554:554)) - (PORT datab (892:892:892) (1028:1028:1028)) - (PORT datac (433:433:433) (516:516:516)) - (PORT datad (487:487:487) (577:577:577)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (678:678:678) (776:776:776)) - (PORT datac (553:553:553) (636:636:636)) - (PORT datad (385:385:385) (457:457:457)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (829:829:829)) - (PORT datab (488:488:488) (569:569:569)) - (PORT datac (475:475:475) (563:563:563)) - (PORT datad (959:959:959) (1089:1089:1089)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (713:713:713) (813:813:813)) - (PORT datab (975:975:975) (1135:1135:1135)) - (PORT datac (544:544:544) (620:620:620)) - (PORT datad (439:439:439) (510:510:510)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (829:829:829)) - (PORT datab (689:689:689) (793:793:793)) - (PORT datac (445:445:445) (511:511:511)) - (PORT datad (959:959:959) (1089:1089:1089)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (830:830:830)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (958:958:958) (1089:1089:1089)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (463:463:463) (536:536:536)) - (PORT datac (584:584:584) (659:659:659)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (536:536:536)) - (PORT datab (305:305:305) (349:349:349)) - (PORT datac (387:387:387) (445:445:445)) - (PORT datad (734:734:734) (840:840:840)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (572:572:572)) - (PORT datab (949:949:949) (1092:1092:1092)) - (PORT datac (686:686:686) (817:817:817)) - (PORT datad (600:600:600) (705:705:705)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (482:482:482) (564:564:564)) - (PORT datab (611:611:611) (725:725:725)) - (PORT datac (930:930:930) (1072:1072:1072)) - (PORT datad (486:486:486) (558:558:558)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (356:356:356) (420:420:420)) - (PORT datac (355:355:355) (424:424:424)) - (PORT datad (574:574:574) (658:658:658)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (451:451:451) (532:532:532)) - (PORT datab (318:318:318) (369:369:369)) - (PORT datad (93:93:93) (113:113:113)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT datab (694:694:694) (836:836:836)) - (PORT datac (645:645:645) (777:777:777)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (864:864:864)) - (PORT datab (191:191:191) (229:229:229)) - (PORT datac (659:659:659) (747:747:747)) - (PORT datad (428:428:428) (493:493:493)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (747:747:747)) - (PORT datab (619:619:619) (715:715:715)) - (PORT datac (625:625:625) (720:720:720)) - (PORT datad (559:559:559) (633:633:633)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (1213:1213:1213) (1394:1394:1394)) - (PORT datac (459:459:459) (533:533:533)) - (PORT datad (561:561:561) (640:640:640)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (527:527:527)) - (PORT datab (396:396:396) (477:477:477)) - (PORT datac (347:347:347) (409:409:409)) - (PORT datad (559:559:559) (624:624:624)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (642:642:642)) - (PORT datab (1193:1193:1193) (1375:1375:1375)) - (PORT datac (1227:1227:1227) (1398:1398:1398)) - (PORT datad (812:812:812) (956:956:956)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal69\~0) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (800:800:800)) - (PORT datab (784:784:784) (911:911:911)) - (PORT datac (1368:1368:1368) (1565:1565:1565)) - (PORT datad (1314:1314:1314) (1516:1516:1516)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (728:728:728) (838:838:838)) - (PORT datab (649:649:649) (765:765:765)) - (PORT datac (453:453:453) (531:531:531)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (420:420:420)) - (PORT datab (142:142:142) (176:176:176)) - (PORT datad (110:110:110) (130:130:130)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1043:1043:1043) (1205:1205:1205)) - (PORT datab (115:115:115) (149:149:149)) - (PORT datac (294:294:294) (333:333:333)) - (PORT datad (100:100:100) (122:122:122)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pla_decode_\|Equal52\~1) (DELAY (ABSOLUTE - (PORT dataa (180:180:180) (246:246:246)) - (PORT datab (128:128:128) (157:157:157)) - (PORT datac (267:267:267) (300:300:300)) - (PORT datad (165:165:165) (218:218:218)) + (PORT dataa (780:780:780) (935:935:935)) + (PORT datab (522:522:522) (616:616:616)) + (PORT datac (526:526:526) (613:613:613)) + (PORT datad (668:668:668) (796:796:796)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -5397,13 +2489,93 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (INSTANCE z80_\|execute_\|ctl_state_alu\~14) (DELAY (ABSOLUTE - (PORT dataa (338:338:338) (413:413:413)) - (PORT datab (446:446:446) (515:515:515)) - (PORT datac (472:472:472) (542:542:542)) - (PORT datad (209:209:209) (258:258:258)) + (PORT dataa (552:552:552) (655:655:655)) + (PORT datab (738:738:738) (839:839:839)) + (PORT datac (527:527:527) (621:621:621)) + (PORT datad (596:596:596) (679:679:679)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (396:396:396)) + (PORT datab (703:703:703) (820:820:820)) + (PORT datac (306:306:306) (350:350:350)) + (PORT datad (911:911:911) (1051:1051:1051)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (481:481:481)) + (PORT datab (114:114:114) (143:143:143)) + (PORT datac (142:142:142) (190:190:190)) + (PORT datad (494:494:494) (571:571:571)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (582:582:582)) + (PORT datab (619:619:619) (740:740:740)) + (PORT datac (607:607:607) (691:691:691)) + (PORT datad (370:370:370) (429:429:429)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (291:291:291)) + (PORT datab (1132:1132:1132) (1336:1336:1336)) + (PORT datac (579:579:579) (676:676:676)) + (PORT datad (891:891:891) (1034:1034:1034)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (599:599:599)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (487:487:487) (571:571:571)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -5413,13 +2585,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (INSTANCE z80_\|execute_\|fMRead\~17) (DELAY (ABSOLUTE - (PORT dataa (640:640:640) (758:758:758)) - (PORT datab (584:584:584) (670:670:670)) - (PORT datac (687:687:687) (822:822:822)) - (PORT datad (749:749:749) (870:870:870)) + (PORT dataa (334:334:334) (396:396:396)) + (PORT datab (661:661:661) (762:762:762)) + (PORT datac (109:109:109) (134:134:134)) + (PORT datad (338:338:338) (397:397:397)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -5429,13 +2601,93 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (INSTANCE z80_\|execute_\|ctl_mRead\~6) (DELAY (ABSOLUTE - (PORT dataa (734:734:734) (861:861:861)) - (PORT datab (311:311:311) (365:365:365)) - (PORT datac (586:586:586) (681:681:681)) - (PORT datad (1566:1566:1566) (1789:1789:1789)) + (PORT dataa (212:212:212) (261:261:261)) + (PORT datab (647:647:647) (745:745:745)) + (PORT datac (350:350:350) (409:409:409)) + (PORT datad (620:620:620) (709:709:709)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (1088:1088:1088)) + (PORT datab (861:861:861) (993:993:993)) + (PORT datac (978:978:978) (1128:1128:1128)) + (PORT datad (855:855:855) (1002:1002:1002)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (1090:1090:1090)) + (PORT datab (862:862:862) (994:994:994)) + (PORT datac (979:979:979) (1129:1129:1129)) + (PORT datad (858:858:858) (1005:1005:1005)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (1095:1095:1095)) + (PORT datab (826:826:826) (967:967:967)) + (PORT datac (1442:1442:1442) (1672:1672:1672)) + (PORT datad (1066:1066:1066) (1247:1247:1247)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (397:397:397)) + (PORT datab (702:702:702) (819:819:819)) + (PORT datac (608:608:608) (702:702:702)) + (PORT datad (290:290:290) (330:330:330)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (833:833:833)) + (PORT datab (252:252:252) (307:307:307)) + (PORT datac (937:937:937) (1081:1081:1081)) + (PORT datad (146:146:146) (182:182:182)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -5445,13 +2697,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (INSTANCE z80_\|execute_\|fMRead\~16) (DELAY (ABSOLUTE - (PORT dataa (800:800:800) (913:913:913)) - (PORT datab (1334:1334:1334) (1536:1536:1536)) - (PORT datac (803:803:803) (943:943:943)) - (PORT datad (1313:1313:1313) (1522:1522:1522)) + (PORT dataa (612:612:612) (729:729:729)) + (PORT datab (639:639:639) (740:740:740)) + (PORT datac (294:294:294) (332:332:332)) + (PORT datad (319:319:319) (370:370:370)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (205:205:205)) + (PORT datab (253:253:253) (308:308:308)) + (PORT datac (101:101:101) (121:121:121)) + (PORT datad (782:782:782) (926:926:926)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal46\~0) + (DELAY + (ABSOLUTE + (PORT dataa (156:156:156) (213:213:213)) + (PORT datab (517:517:517) (613:613:613)) + (PORT datac (501:501:501) (586:586:586)) + (PORT datad (662:662:662) (789:789:789)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -5461,27 +2745,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) (DELAY (ABSOLUTE - (PORT dataa (902:902:902) (1068:1068:1068)) - (PORT datab (1038:1038:1038) (1221:1221:1221)) - (PORT datad (1171:1171:1171) (1355:1355:1355)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (1072:1072:1072)) - (PORT datab (918:918:918) (1075:1075:1075)) - (PORT datac (578:578:578) (664:664:664)) - (PORT datad (1013:1013:1013) (1164:1164:1164)) + (PORT dataa (697:697:697) (829:829:829)) + (PORT datab (475:475:475) (551:551:551)) + (PORT datac (942:942:942) (1086:1086:1086)) + (PORT datad (144:144:144) (178:178:178)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -5491,13 +2761,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) (DELAY (ABSOLUTE - (PORT dataa (124:124:124) (158:158:158)) - (PORT datab (668:668:668) (780:780:780)) - (PORT datac (464:464:464) (540:540:540)) - (PORT datad (644:644:644) (740:740:740)) + (PORT dataa (1196:1196:1196) (1388:1388:1388)) + (PORT datab (1137:1137:1137) (1323:1323:1323)) + (PORT datac (552:552:552) (649:649:649)) + (PORT datad (663:663:663) (762:762:762)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -5507,29 +2777,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) (DELAY (ABSOLUTE - (PORT datab (959:959:959) (1127:1127:1127)) - (PORT datac (958:958:958) (1126:1126:1126)) - (PORT datad (1020:1020:1020) (1207:1207:1207)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (786:786:786)) - (PORT datab (468:468:468) (545:545:545)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (327:327:327) (383:383:383)) + (PORT dataa (770:770:770) (890:890:890)) + (PORT datab (613:613:613) (728:728:728)) + (PORT datac (402:402:402) (458:458:458)) + (PORT datad (679:679:679) (797:797:797)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -5537,58 +2793,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) + (INSTANCE z80_\|execute_\|ctl_ir_we\~6) (DELAY (ABSOLUTE - (PORT dataa (618:618:618) (719:719:719)) - (PORT datab (656:656:656) (753:753:753)) - (PORT datac (995:995:995) (1145:1145:1145)) - (PORT datad (557:557:557) (631:631:631)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1219:1219:1219)) - (PORT datab (603:603:603) (700:700:700)) - (PORT datac (624:624:624) (731:731:731)) - (PORT datad (993:993:993) (1141:1141:1141)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1485:1485:1485) (1717:1717:1717)) - (PORT datac (276:276:276) (315:315:315)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (547:547:547) (645:645:645)) + (PORT datac (625:625:625) (720:720:720)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (INSTANCE z80_\|execute_\|ctl_ir_we\~8) (DELAY (ABSOLUTE - (PORT dataa (214:214:214) (268:268:268)) - (PORT datab (750:750:750) (870:870:870)) - (PORT datac (751:751:751) (879:879:879)) - (PORT datad (196:196:196) (225:225:225)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (162:162:162) (210:210:210)) + (PORT datab (252:252:252) (307:307:307)) + (PORT datac (666:666:666) (779:779:779)) + (PORT datad (777:777:777) (921:921:921)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -5597,15 +2821,193 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~8) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) (DELAY (ABSOLUTE - (PORT dataa (311:311:311) (368:368:368)) - (PORT datab (523:523:523) (606:606:606)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (624:624:624) (721:721:721)) + (PORT dataa (659:659:659) (794:794:794)) + (PORT datab (1230:1230:1230) (1413:1413:1413)) + (PORT datac (749:749:749) (886:886:886)) + (PORT datad (534:534:534) (628:628:628)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1176:1176:1176)) + (PORT datab (728:728:728) (854:854:854)) + (PORT datac (751:751:751) (855:855:855)) + (PORT datad (477:477:477) (546:546:546)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (374:374:374)) + (PORT datac (295:295:295) (337:337:337)) + (PORT datad (703:703:703) (813:813:813)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (455:455:455) (527:527:527)) + (PORT datad (472:472:472) (544:544:544)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) + (DELAY + (ABSOLUTE + (PORT datac (1152:1152:1152) (1344:1344:1344)) + (PORT datad (536:536:536) (632:632:632)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (1087:1087:1087)) + (PORT datab (861:861:861) (992:992:992)) + (PORT datac (978:978:978) (1128:1128:1128)) + (PORT datad (854:854:854) (1001:1001:1001)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (446:446:446)) + (PORT datab (844:844:844) (979:979:979)) + (PORT datac (635:635:635) (741:741:741)) + (PORT datad (782:782:782) (889:889:889)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1213:1213:1213) (1420:1420:1420)) + (PORT datab (379:379:379) (463:463:463)) + (PORT datac (930:930:930) (1068:1068:1068)) + (PORT datad (110:110:110) (130:130:130)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (831:831:831)) + (PORT datad (1162:1162:1162) (1373:1373:1373)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (599:599:599)) + (PORT datab (241:241:241) (281:281:281)) + (PORT datac (213:213:213) (262:262:262)) + (PORT datad (880:880:880) (1017:1017:1017)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (393:393:393)) + (PORT datab (640:640:640) (745:745:745)) + (PORT datac (805:805:805) (935:935:935)) + (PORT datad (173:173:173) (205:205:205)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) + (DELAY + (ABSOLUTE + (PORT datac (845:845:845) (986:986:986)) + (PORT datad (630:630:630) (726:726:726)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -5616,326 +3018,26 @@ (INSTANCE z80_\|execute_\|ctl_ir_we\~11) (DELAY (ABSOLUTE - (PORT dataa (804:804:804) (932:932:932)) - (PORT datab (711:711:711) (822:822:822)) - (PORT datac (320:320:320) (374:374:374)) - (PORT datad (330:330:330) (383:383:383)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (1065:1065:1065)) - (PORT datab (749:749:749) (855:855:855)) - (PORT datac (275:275:275) (314:314:314)) - (PORT datad (349:349:349) (403:403:403)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (732:732:732) (859:859:859)) - (PORT datab (310:310:310) (363:363:363)) - (PORT datac (586:586:586) (680:680:680)) - (PORT datad (1569:1569:1569) (1792:1792:1792)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT datac (289:289:289) (342:342:342)) - (PORT datad (575:575:575) (660:660:660)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (148:148:148)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (526:526:526) (618:618:618)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) - (DELAY - (ABSOLUTE - (PORT dataa (306:306:306) (358:358:358)) - (PORT datab (568:568:568) (685:685:685)) - (PORT datac (692:692:692) (780:780:780)) - (PORT datad (617:617:617) (719:719:719)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (544:544:544)) - (PORT datab (346:346:346) (407:407:407)) - (PORT datac (619:619:619) (705:705:705)) - (PORT datad (706:706:706) (809:809:809)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (978:978:978) (1141:1141:1141)) - (PORT datab (395:395:395) (476:476:476)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (658:658:658) (751:751:751)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (238:238:238)) - (PORT datab (596:596:596) (678:678:678)) - (PORT datac (552:552:552) (635:635:635)) - (PORT datad (660:660:660) (753:753:753)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (719:719:719)) - (PORT datab (114:114:114) (141:141:141)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (455:455:455) (529:529:529)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (1055:1055:1055) (1247:1247:1247)) - (PORT datab (127:127:127) (161:161:161)) - (PORT datac (739:739:739) (859:859:859)) - (PORT datad (469:469:469) (541:541:541)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (1081:1081:1081) (1264:1264:1264)) - (PORT datab (481:481:481) (560:560:560)) - (PORT datac (515:515:515) (619:619:619)) - (PORT datad (514:514:514) (612:612:612)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (724:724:724)) - (PORT datab (589:589:589) (689:689:689)) - (PORT datac (633:633:633) (725:725:725)) - (PORT datad (546:546:546) (626:626:626)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (749:749:749)) - (PORT datab (675:675:675) (785:785:785)) - (PORT datac (758:758:758) (878:878:878)) - (PORT datad (571:571:571) (647:647:647)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (126:126:126) (161:161:161)) - (PORT datab (767:767:767) (903:903:903)) - (PORT datac (685:685:685) (819:819:819)) - (PORT datad (612:612:612) (720:720:720)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (762:762:762) (895:895:895)) - (PORT datab (702:702:702) (844:844:844)) - (PORT datac (749:749:749) (884:884:884)) - (PORT datad (645:645:645) (774:774:774)) + (PORT dataa (703:703:703) (836:836:836)) + (PORT datab (473:473:473) (549:549:549)) + (PORT datac (934:934:934) (1077:1077:1077)) + (PORT datad (148:148:148) (184:184:184)) (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (747:747:747)) - (PORT datab (482:482:482) (566:566:566)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (671:671:671) (780:780:780)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (685:685:685)) - (PORT datab (584:584:584) (670:670:670)) - (PORT datac (445:445:445) (515:515:515)) - (PORT datad (613:613:613) (722:722:722)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1134:1134:1134) (1308:1308:1308)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (99:99:99) (125:125:125)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (429:429:429)) - (PORT datab (627:627:627) (739:739:739)) - (PORT datac (741:741:741) (852:852:852)) - (PORT datad (1314:1314:1314) (1522:1522:1522)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (790:790:790)) - (PORT datab (1070:1070:1070) (1213:1213:1213)) - (PORT datac (1114:1114:1114) (1283:1283:1283)) - (PORT datad (490:490:490) (570:570:570)) + (PORT dataa (702:702:702) (834:834:834)) + (PORT datab (252:252:252) (307:307:307)) + (PORT datac (936:936:936) (1079:1079:1079)) + (PORT datad (147:147:147) (183:183:183)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -5945,163 +3047,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~26) + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) (DELAY (ABSOLUTE - (PORT dataa (822:822:822) (963:963:963)) - (PORT datab (855:855:855) (993:993:993)) - (PORT datac (637:637:637) (727:727:727)) - (PORT datad (890:890:890) (1020:1020:1020)) + (PORT dataa (793:793:793) (907:907:907)) + (PORT datab (596:596:596) (688:688:688)) + (PORT datac (582:582:582) (663:663:663)) + (PORT datad (527:527:527) (618:618:618)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) (DELAY (ABSOLUTE - (PORT dataa (1137:1137:1137) (1313:1313:1313)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (97:97:97) (122:122:122)) - (PORT datad (100:100:100) (121:121:121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (844:844:844)) - (PORT datac (757:757:757) (902:902:902)) - (PORT datad (445:445:445) (514:514:514)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (970:970:970)) - (PORT datab (715:715:715) (830:830:830)) - (PORT datac (734:734:734) (849:849:849)) - (PORT datad (1192:1192:1192) (1366:1366:1366)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (966:966:966)) - (PORT datab (853:853:853) (991:991:991)) - (PORT datac (1179:1179:1179) (1377:1377:1377)) - (PORT datad (1315:1315:1315) (1524:1524:1524)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (533:533:533) (624:624:624)) - (PORT datab (137:137:137) (173:173:173)) - (PORT datac (815:815:815) (943:943:943)) - (PORT datad (282:282:282) (325:325:325)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT datac (702:702:702) (802:802:802)) - (PORT datad (425:425:425) (494:494:494)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT datac (702:702:702) (802:802:802)) - (PORT datad (425:425:425) (493:493:493)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (518:518:518) (600:600:600)) - (PORT datab (462:462:462) (535:535:535)) - (PORT datac (459:459:459) (531:531:531)) - (PORT datad (440:440:440) (510:510:510)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (421:421:421)) - (PORT datab (484:484:484) (560:560:560)) - (PORT datac (277:277:277) (316:316:316)) - (PORT datad (315:315:315) (366:366:366)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (652:652:652)) - (PORT datab (542:542:542) (648:648:648)) - (PORT datac (1237:1237:1237) (1423:1423:1423)) - (PORT datad (742:742:742) (844:844:844)) + (PORT dataa (376:376:376) (447:447:447)) + (PORT datab (650:650:650) (762:762:762)) + (PORT datac (811:811:811) (941:941:941)) + (PORT datad (831:831:831) (957:957:957)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -6111,27 +3079,147 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) (DELAY (ABSOLUTE - (PORT dataa (708:708:708) (851:851:851)) - (PORT datab (674:674:674) (807:807:807)) - (PORT datad (476:476:476) (547:547:547)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (201:201:201) (241:241:241)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (344:344:344) (400:400:400)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) (DELAY (ABSOLUTE - (PORT dataa (764:764:764) (905:905:905)) - (PORT datab (716:716:716) (843:843:843)) - (PORT datac (429:429:429) (495:495:495)) - (PORT datad (423:423:423) (484:484:484)) + (PORT dataa (298:298:298) (349:349:349)) + (PORT datab (466:466:466) (534:534:534)) + (PORT datac (467:467:467) (542:542:542)) + (PORT datad (428:428:428) (494:494:494)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (721:721:721)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (101:101:101) (128:128:128)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (276:276:276)) + (PORT datab (685:685:685) (797:797:797)) + (PORT datac (360:360:360) (430:430:430)) + (PORT datad (725:725:725) (861:861:861)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) + (DELAY + (ABSOLUTE + (PORT datab (1663:1663:1663) (1925:1925:1925)) + (PORT datac (1123:1123:1123) (1307:1307:1307)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1045:1045:1045) (1187:1187:1187)) + (PORT datab (1192:1192:1192) (1397:1397:1397)) + (PORT datac (618:618:618) (703:703:703)) + (PORT datad (109:109:109) (130:130:130)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (670:670:670) (795:795:795)) + (PORT datad (335:335:335) (398:398:398)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (758:758:758)) + (PORT datab (516:516:516) (598:598:598)) + (PORT datac (1136:1136:1136) (1290:1290:1290)) + (PORT datad (826:826:826) (963:963:963)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (701:701:701)) + (PORT datab (1350:1350:1350) (1567:1567:1567)) + (PORT datad (1175:1175:1175) (1364:1364:1364)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (974:974:974)) + (PORT datab (563:563:563) (662:662:662)) + (PORT datac (491:491:491) (576:576:576)) + (PORT datad (627:627:627) (719:719:719)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -6139,141 +3227,63 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (489:489:489)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (468:468:468) (542:542:542)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (571:571:571) (653:653:653)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (651:651:651)) - (PORT datab (311:311:311) (359:359:359)) - (PORT datac (186:186:186) (225:225:225)) - (PORT datad (175:175:175) (209:209:209)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1243:1243:1243)) - (PORT datab (776:776:776) (906:906:906)) - (PORT datac (778:778:778) (905:905:905)) - (PORT datad (489:489:489) (567:567:567)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (750:750:750)) - (PORT datab (367:367:367) (436:436:436)) - (PORT datac (454:454:454) (530:530:530)) - (PORT datad (348:348:348) (401:401:401)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) (DELAY (ABSOLUTE - (PORT dataa (884:884:884) (1012:1012:1012)) - (PORT datab (429:429:429) (519:519:519)) - (PORT datac (112:112:112) (138:138:138)) - (PORT datad (853:853:853) (986:986:986)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (804:804:804) (914:914:914)) + (PORT datab (633:633:633) (730:730:730)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (629:629:629) (717:717:717)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) (DELAY (ABSOLUTE - (PORT dataa (655:655:655) (784:784:784)) - (PORT datab (338:338:338) (397:397:397)) - (PORT datac (731:731:731) (868:868:868)) - (PORT datad (436:436:436) (501:501:501)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT dataa (195:195:195) (235:235:235)) + (PORT datab (588:588:588) (678:678:678)) + (PORT datac (874:874:874) (992:992:992)) + (PORT datad (439:439:439) (505:505:505)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) (DELAY (ABSOLUTE - (PORT dataa (579:579:579) (679:679:679)) - (PORT datab (1589:1589:1589) (1822:1822:1822)) - (PORT datac (489:489:489) (566:566:566)) - (PORT datad (551:551:551) (630:630:630)) - (IOPATH dataa combout (159:159:159) (163:163:163)) + (PORT dataa (632:632:632) (734:734:734)) + (PORT datab (643:643:643) (735:735:735)) + (PORT datac (464:464:464) (527:527:527)) + (PORT datad (440:440:440) (503:503:503)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) + (INSTANCE z80_\|alu_\|db_low\[2\]\~4) (DELAY (ABSOLUTE - (PORT dataa (286:286:286) (337:337:337)) - (PORT datab (200:200:200) (238:238:238)) - (PORT datac (346:346:346) (406:406:406)) - (PORT datad (627:627:627) (730:730:730)) + (PORT dataa (650:650:650) (755:755:755)) + (PORT datab (153:153:153) (197:197:197)) + (PORT datac (138:138:138) (178:178:178)) + (PORT datad (136:136:136) (167:167:167)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -6283,15 +3293,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~51) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (503:503:503) (612:612:612)) - (PORT datab (629:629:629) (748:748:748)) - (PORT datac (441:441:441) (514:514:514)) - (PORT datad (99:99:99) (121:121:121)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (527:527:527) (616:616:616)) + (PORT datad (1139:1139:1139) (1332:1332:1332)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -6299,13 +3305,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) (DELAY (ABSOLUTE - (PORT dataa (823:823:823) (963:963:963)) - (PORT datab (367:367:367) (436:436:436)) - (PORT datac (632:632:632) (725:725:725)) - (PORT datad (541:541:541) (612:612:612)) + (PORT dataa (472:472:472) (546:546:546)) + (PORT datab (563:563:563) (662:662:662)) + (PORT datac (682:682:682) (798:798:798)) + (PORT datad (626:626:626) (718:718:718)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -6315,89 +3321,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~28) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) (DELAY (ABSOLUTE - (PORT dataa (1042:1042:1042) (1203:1203:1203)) - (PORT datab (128:128:128) (156:156:156)) - (PORT datac (294:294:294) (334:334:334)) - (PORT datad (104:104:104) (128:128:128)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (628:628:628)) - (PORT datab (489:489:489) (574:574:574)) - (PORT datac (755:755:755) (864:864:864)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (654:654:654)) - (PORT datab (536:536:536) (642:642:642)) - (PORT datac (1242:1242:1242) (1428:1428:1428)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) (PORT datab (114:114:114) (142:142:142)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (698:698:698) (787:787:787)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) (DELAY (ABSOLUTE - (PORT datab (921:921:921) (1077:1077:1077)) - (PORT datac (992:992:992) (1145:1145:1145)) - (PORT datad (1559:1559:1559) (1780:1780:1780)) - (IOPATH datab combout (188:188:188) (181:181:181)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (456:456:456) (522:522:522)) - (PORT datab (443:443:443) (510:510:510)) - (PORT datac (689:689:689) (786:786:786)) - (PORT datad (351:351:351) (416:416:416)) + (PORT dataa (655:655:655) (755:755:755)) + (PORT datab (562:562:562) (662:662:662)) + (PORT datac (1135:1135:1135) (1289:1289:1289)) + (PORT datad (827:827:827) (964:964:964)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -6407,31 +3349,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) (DELAY (ABSOLUTE - (PORT dataa (559:559:559) (643:643:643)) - (PORT datab (283:283:283) (325:325:325)) - (PORT datac (787:787:787) (910:910:910)) - (PORT datad (691:691:691) (784:784:784)) + (PORT dataa (741:741:741) (866:866:866)) + (PORT datab (650:650:650) (759:759:759)) + (PORT datac (469:469:469) (538:538:538)) + (PORT datad (755:755:755) (896:896:896)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (771:771:771)) - (PORT datab (451:451:451) (544:544:544)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (689:689:689) (778:778:778)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -6439,13 +3365,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~5) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (272:272:272)) - (PORT datab (137:137:137) (174:174:174)) - (PORT datac (298:298:298) (338:338:338)) - (PORT datad (582:582:582) (660:660:660)) + (PORT dataa (516:516:516) (608:608:608)) + (PORT datab (533:533:533) (618:618:618)) + (PORT datac (671:671:671) (792:792:792)) + (PORT datad (361:361:361) (422:422:422)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (768:768:768) (921:921:921)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (201:201:201) (232:232:232)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal69\~0) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (577:577:577)) + (PORT datab (956:956:956) (1113:1113:1113)) + (PORT datac (618:618:618) (701:701:701)) + (PORT datad (356:356:356) (419:419:419)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -6455,73 +3413,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~32) + (INSTANCE z80_\|pla_decode_\|Equal1\~5) (DELAY (ABSOLUTE - (PORT dataa (111:111:111) (147:147:147)) - (PORT datab (119:119:119) (148:148:148)) - (PORT datac (460:460:460) (535:535:535)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (470:470:470) (544:544:544)) - (PORT datab (114:114:114) (146:146:146)) - (PORT datac (331:331:331) (390:390:390)) - (PORT datad (93:93:93) (113:113:113)) + (PORT dataa (660:660:660) (791:791:791)) + (PORT datad (648:648:648) (770:770:770)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) (DELAY (ABSOLUTE - (PORT dataa (483:483:483) (575:575:575)) - (PORT datab (464:464:464) (529:529:529)) - (PORT datac (895:895:895) (1035:1035:1035)) - (PORT datad (701:701:701) (807:807:807)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT datab (364:364:364) (430:430:430)) - (PORT datac (98:98:98) (123:123:123)) - (PORT datad (297:297:297) (350:350:350)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (731:731:731) (858:858:858)) - (PORT datab (1584:1584:1584) (1815:1815:1815)) - (PORT datac (453:453:453) (526:526:526)) - (PORT datad (577:577:577) (663:663:663)) + (PORT dataa (561:561:561) (653:653:653)) + (PORT datab (1135:1135:1135) (1296:1296:1296)) + (PORT datac (623:623:623) (708:708:708)) + (PORT datad (351:351:351) (414:414:414)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -6531,152 +3441,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) (DELAY (ABSOLUTE - (PORT dataa (629:629:629) (718:718:718)) - (PORT datab (318:318:318) (363:363:363)) - (PORT datac (764:764:764) (896:896:896)) - (PORT datad (969:969:969) (1116:1116:1116)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~1) - (DELAY - (ABSOLUTE - (PORT datac (1013:1013:1013) (1158:1158:1158)) - (PORT datad (970:970:970) (1118:1118:1118)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (661:661:661)) - (PORT datab (1222:1222:1222) (1436:1436:1436)) - (PORT datac (768:768:768) (900:900:900)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (436:436:436) (505:505:505)) - (PORT datab (107:107:107) (138:138:138)) - (PORT datac (302:302:302) (339:339:339)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (169:169:169) (206:206:206)) - (PORT datac (533:533:533) (622:622:622)) - (PORT datad (163:163:163) (190:190:190)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (285:285:285) (335:335:335)) - (PORT datab (528:528:528) (617:617:617)) - (PORT datac (827:827:827) (950:950:950)) - (PORT datad (492:492:492) (581:581:581)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (637:637:637)) - (PORT datab (1374:1374:1374) (1578:1578:1578)) - (PORT datac (452:452:452) (522:522:522)) - (PORT datad (688:688:688) (789:789:789)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT datab (468:468:468) (545:545:545)) - (PORT datac (674:674:674) (767:767:767)) - (PORT datad (965:965:965) (1083:1083:1083)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (943:943:943) (1076:1076:1076)) - (PORT datab (120:120:120) (151:151:151)) - (PORT datac (651:651:651) (761:761:761)) - (PORT datad (170:170:170) (199:199:199)) + (PORT dataa (991:991:991) (1166:1166:1166)) + (PORT datab (511:511:511) (594:594:594)) + (PORT datad (117:117:117) (134:134:134)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~12) + (INSTANCE z80_\|pla_decode_\|Equal56\~0) (DELAY (ABSOLUTE - (PORT dataa (764:764:764) (886:886:886)) - (PORT datab (746:746:746) (866:866:866)) - (PORT datac (745:745:745) (872:872:872)) - (PORT datad (202:202:202) (249:249:249)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (345:345:345) (415:415:415)) + (PORT datab (638:638:638) (748:748:748)) + (PORT datac (520:520:520) (626:626:626)) + (PORT datad (500:500:500) (583:583:583)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (970:970:970)) + (PORT datab (687:687:687) (811:811:811)) + (PORT datac (812:812:812) (944:944:944)) + (PORT datad (441:441:441) (498:498:498)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -6685,15 +3488,119 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~46) + (INSTANCE z80_\|execute_\|nextM\~2) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (228:228:228)) - (PORT datab (462:462:462) (532:532:532)) - (PORT datac (426:426:426) (494:494:494)) - (PORT datad (332:332:332) (388:388:388)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) + (PORT dataa (447:447:447) (515:515:515)) + (PORT datab (465:465:465) (538:538:538)) + (PORT datad (364:364:364) (427:427:427)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1300:1300:1300)) + (PORT datab (1182:1182:1182) (1366:1366:1366)) + (PORT datac (284:284:284) (330:330:330)) + (PORT datad (971:971:971) (1107:1107:1107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (463:463:463) (539:539:539)) + (PORT datab (533:533:533) (615:615:615)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (816:816:816) (946:946:946)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT datac (627:627:627) (734:734:734)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (798:798:798)) + (PORT datab (551:551:551) (659:659:659)) + (PORT datac (371:371:371) (438:438:438)) + (PORT datad (713:713:713) (830:830:830)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) + (DELAY + (ABSOLUTE + (PORT datab (611:611:611) (734:734:734)) + (PORT datac (830:830:830) (972:972:972)) + (PORT datad (1305:1305:1305) (1526:1526:1526)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (440:440:440)) + (PORT datab (997:997:997) (1144:1144:1144)) + (PORT datac (553:553:553) (652:652:652)) + (PORT datad (665:665:665) (764:764:764)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (673:673:673)) + (PORT datab (683:683:683) (789:789:789)) + (PORT datac (613:613:613) (700:700:700)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -6701,45 +3608,91 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) (DELAY (ABSOLUTE - (PORT dataa (693:693:693) (831:831:831)) - (PORT datab (113:113:113) (141:141:141)) - (PORT datac (829:829:829) (941:941:941)) - (PORT datad (337:337:337) (397:397:397)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (525:525:525) (605:605:605)) + (PORT datab (616:616:616) (732:732:732)) + (PORT datac (561:561:561) (661:661:661)) + (PORT datad (639:639:639) (736:736:736)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (683:683:683)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (701:701:701) (826:826:826)) + (PORT datad (598:598:598) (707:707:707)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT datab (842:842:842) (985:985:985)) + (PORT datac (831:831:831) (968:968:968)) + (PORT datad (727:727:727) (823:823:823)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (432:432:432) (499:499:499)) + (PORT datab (457:457:457) (527:527:527)) + (PORT datac (680:680:680) (759:759:759)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (906:906:906)) + (PORT datab (1159:1159:1159) (1325:1325:1325)) + (PORT datac (457:457:457) (530:530:530)) + (PORT datad (425:425:425) (487:487:487)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pla_decode_\|Equal48\~0) (DELAY (ABSOLUTE - (PORT dataa (694:694:694) (798:798:798)) - (PORT datab (785:785:785) (912:912:912)) - (PORT datac (1370:1370:1370) (1567:1567:1567)) - (PORT datad (1315:1315:1315) (1517:1517:1517)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (722:722:722)) - (PORT datab (549:549:549) (630:630:630)) - (PORT datac (616:616:616) (723:723:723)) - (PORT datad (554:554:554) (635:635:635)) + (PORT dataa (479:479:479) (576:576:576)) + (PORT datab (955:955:955) (1113:1113:1113)) + (PORT datac (618:618:618) (701:701:701)) + (PORT datad (357:357:357) (420:420:420)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -6749,31 +3702,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) + (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (552:552:552) (645:645:645)) - (PORT datac (451:451:451) (521:521:521)) - (PORT datad (570:570:570) (659:659:659)) + (PORT dataa (517:517:517) (604:604:604)) + (PORT datab (491:491:491) (589:589:589)) + (PORT datac (524:524:524) (617:617:617)) + (PORT datad (714:714:714) (820:820:820)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) (DELAY (ABSOLUTE - (PORT dataa (930:930:930) (1081:1081:1081)) - (PORT datab (119:119:119) (148:148:148)) - (PORT datac (452:452:452) (522:522:522)) - (PORT datad (564:564:564) (646:646:646)) + (PORT dataa (701:701:701) (837:837:837)) + (PORT datab (547:547:547) (646:646:646)) + (PORT datac (112:112:112) (138:138:138)) + (PORT datad (688:688:688) (791:791:791)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -6784,74 +3737,26 @@ (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) (DELAY (ABSOLUTE - (PORT dataa (640:640:640) (757:757:757)) - (PORT datab (585:585:585) (670:670:670)) - (PORT datac (687:687:687) (822:822:822)) - (PORT datad (613:613:613) (718:718:718)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (687:687:687)) - (PORT datab (467:467:467) (539:539:539)) - (PORT datac (543:543:543) (621:621:621)) - (PORT datad (868:868:868) (991:991:991)) + (PORT dataa (1010:1010:1010) (1177:1177:1177)) + (PORT datab (733:733:733) (860:860:860)) + (PORT datac (1145:1145:1145) (1334:1334:1334)) + (PORT datad (450:450:450) (514:514:514)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (268:268:268)) - (PORT datab (140:140:140) (178:178:178)) - (PORT datac (1172:1172:1172) (1349:1349:1349)) - (PORT datad (628:628:628) (719:719:719)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (485:485:485) (562:562:562)) - (PORT datab (511:511:511) (594:594:594)) - (PORT datac (442:442:442) (513:513:513)) - (PORT datad (711:711:711) (800:800:800)) - (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) (DELAY (ABSOLUTE - (PORT dataa (684:684:684) (801:801:801)) - (PORT datab (444:444:444) (521:521:521)) - (PORT datac (345:345:345) (412:412:412)) - (PORT datad (113:113:113) (135:135:135)) + (PORT dataa (664:664:664) (771:771:771)) + (PORT datab (562:562:562) (662:662:662)) + (PORT datac (344:344:344) (398:398:398)) + (PORT datad (631:631:631) (724:724:724)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -6861,29 +3766,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) (DELAY (ABSOLUTE - (PORT dataa (722:722:722) (823:823:823)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (356:356:356) (419:419:419)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (655:655:655)) - (PORT datab (873:873:873) (998:998:998)) - (PORT datac (277:277:277) (315:315:315)) - (PORT datad (582:582:582) (661:661:661)) + (PORT dataa (487:487:487) (573:573:573)) + (PORT datab (600:600:600) (713:713:713)) + (PORT datac (310:310:310) (364:364:364)) + (PORT datad (595:595:595) (683:683:683)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -6893,29 +3782,223 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (INSTANCE z80_\|execute_\|ctl_iorw\~10) (DELAY (ABSOLUTE - (PORT dataa (644:644:644) (737:737:737)) - (PORT datab (450:450:450) (524:524:524)) - (PORT datac (470:470:470) (536:536:536)) + (PORT dataa (921:921:921) (1086:1086:1086)) + (PORT datab (872:872:872) (1027:1027:1027)) + (PORT datac (978:978:978) (1128:1128:1128)) + (PORT datad (820:820:820) (936:936:936)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1064:1064:1064)) + (PORT datab (853:853:853) (1005:1005:1005)) + (PORT datac (524:524:524) (616:616:616)) + (PORT datad (657:657:657) (760:760:760)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (366:366:366)) + (PORT datab (496:496:496) (581:581:581)) + (PORT datac (528:528:528) (621:621:621)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (1079:1079:1079)) + (PORT datab (630:630:630) (743:743:743)) + (PORT datac (1001:1001:1001) (1169:1169:1169)) + (PORT datad (529:529:529) (621:621:621)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (797:797:797)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (542:542:542) (622:622:622)) + (PORT datad (515:515:515) (597:597:597)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (754:754:754) (879:879:879)) + (PORT datab (544:544:544) (643:643:643)) + (PORT datac (304:304:304) (357:357:357)) + (PORT datad (349:349:349) (410:410:410)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1319:1319:1319)) + (PORT datab (852:852:852) (1008:1008:1008)) + (PORT datac (123:123:123) (151:151:151)) + (PORT datad (617:617:617) (712:712:712)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (1086:1086:1086)) + (PORT datab (873:873:873) (1028:1028:1028)) + (PORT datac (978:978:978) (1128:1128:1128)) + (PORT datad (819:819:819) (935:935:935)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (605:605:605)) + (PORT datab (792:792:792) (918:918:918)) + (PORT datac (749:749:749) (887:887:887)) + (PORT datad (855:855:855) (1000:1000:1000)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (433:433:433)) + (PORT datab (883:883:883) (1009:1009:1009)) + (PORT datac (709:709:709) (807:807:807)) + (PORT datad (820:820:820) (956:956:956)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (1028:1028:1028)) + (PORT datab (766:766:766) (906:906:906)) + (PORT datac (624:624:624) (718:718:718)) + (PORT datad (436:436:436) (498:498:498)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (441:441:441)) + (PORT datab (550:550:550) (651:651:651)) + (PORT datac (631:631:631) (756:756:756)) (PORT datad (90:90:90) (106:106:106)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal76\~0) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) (DELAY (ABSOLUTE - (PORT dataa (1205:1205:1205) (1406:1406:1406)) - (PORT datac (795:795:795) (933:933:933)) - (PORT datad (1317:1317:1317) (1526:1526:1526)) + (PORT dataa (1268:1268:1268) (1469:1469:1469)) + (PORT datab (459:459:459) (530:530:530)) + (PORT datac (1182:1182:1182) (1375:1375:1375)) + (PORT datad (362:362:362) (424:424:424)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (602:602:602)) + (PORT datab (548:548:548) (647:647:647)) + (PORT datac (815:815:815) (942:942:942)) + (PORT datad (843:843:843) (988:988:988)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -6926,44 +4009,12 @@ (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) (DELAY (ABSOLUTE - (PORT dataa (293:293:293) (345:345:345)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (550:550:550) (647:647:647)) - (PORT datad (721:721:721) (829:829:829)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (813:813:813)) - (PORT datab (307:307:307) (362:362:362)) - (PORT datac (507:507:507) (588:588:588)) - (PORT datad (600:600:600) (703:703:703)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (658:658:658)) - (PORT datab (613:613:613) (725:725:725)) - (PORT datac (764:764:764) (885:885:885)) - (PORT datad (577:577:577) (663:663:663)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (344:344:344) (407:407:407)) + (PORT datab (232:232:232) (277:277:277)) + (PORT datac (107:107:107) (130:130:130)) + (PORT datad (776:776:776) (892:892:892)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -6974,12 +4025,12 @@ (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) (DELAY (ABSOLUTE - (PORT dataa (643:643:643) (737:737:737)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (285:285:285) (340:340:340)) - (PORT datad (297:297:297) (344:344:344)) + (PORT dataa (333:333:333) (390:390:390)) + (PORT datab (544:544:544) (642:642:642)) + (PORT datac (479:479:479) (551:551:551)) + (PORT datad (450:450:450) (513:513:513)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -6987,13 +4038,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (602:602:602) (689:689:689)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (91:91:91) (109:109:109)) + (PORT dataa (189:189:189) (225:225:225)) + (PORT datab (169:169:169) (206:206:206)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (91:91:91) (108:108:108)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -7006,10 +4057,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) (DELAY (ABSOLUTE - (PORT dataa (461:461:461) (535:535:535)) - (PORT datab (178:178:178) (218:218:218)) - (PORT datac (452:452:452) (519:519:519)) - (PORT datad (328:328:328) (381:381:381)) + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (119:119:119) (149:149:149)) + (PORT datac (106:106:106) (129:129:129)) + (PORT datad (106:106:106) (124:124:124)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -7017,47 +4068,15 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (964:964:964)) - (PORT datab (565:565:565) (665:665:665)) - (PORT datac (1179:1179:1179) (1377:1377:1377)) - (PORT datad (1315:1315:1315) (1524:1524:1524)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (318:318:318) (378:378:378)) - (PORT datab (573:573:573) (675:675:675)) - (PORT datac (428:428:428) (503:503:503)) - (PORT datad (992:992:992) (1135:1135:1135)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (563:563:563) (646:646:646)) - (PORT datac (610:610:610) (694:694:694)) - (PORT datad (574:574:574) (654:654:654)) + (PORT dataa (337:337:337) (395:395:395)) + (PORT datab (810:810:810) (932:932:932)) + (PORT datac (336:336:336) (400:400:400)) + (PORT datad (917:917:917) (1055:1055:1055)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -7067,13 +4086,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) (DELAY (ABSOLUTE - (PORT dataa (511:511:511) (589:589:589)) - (PORT datab (188:188:188) (226:226:226)) - (PORT datac (496:496:496) (571:571:571)) - (PORT datad (104:104:104) (121:121:121)) + (PORT dataa (357:357:357) (427:427:427)) + (PORT datab (549:549:549) (650:650:650)) + (PORT datac (631:631:631) (755:755:755)) + (PORT datad (1285:1285:1285) (1467:1467:1467)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -7083,27 +4102,89 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) (DELAY (ABSOLUTE - (PORT dataa (595:595:595) (708:708:708)) - (PORT datad (419:419:419) (485:485:485)) + (PORT dataa (515:515:515) (604:604:604)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (175:175:175) (210:210:210)) + (PORT datad (1286:1286:1286) (1469:1469:1469)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~4) + (DELAY + (ABSOLUTE + (PORT datab (589:589:589) (720:720:720)) + (PORT datac (812:812:812) (935:935:935)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (900:900:900)) + (PORT datab (535:535:535) (623:623:623)) + (PORT datac (614:614:614) (721:721:721)) + (PORT datad (788:788:788) (903:903:903)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (635:635:635)) + (PORT datab (798:798:798) (921:921:921)) + (PORT datac (544:544:544) (624:624:624)) + (PORT datad (103:103:103) (121:121:121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (687:687:687)) + (PORT datab (653:653:653) (762:762:762)) + (PORT datac (371:371:371) (437:437:437)) + (PORT datad (483:483:483) (565:565:565)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (371:371:371)) + (PORT datac (294:294:294) (345:345:345)) + (PORT datad (285:285:285) (323:323:323)) (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (760:760:760) (881:881:881)) - (PORT datab (129:129:129) (162:162:162)) - (PORT datac (1330:1330:1330) (1515:1515:1515)) - (PORT datad (1033:1033:1033) (1220:1220:1220)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -7111,15 +4192,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) (DELAY (ABSOLUTE - (PORT dataa (454:454:454) (530:530:530)) - (PORT datab (481:481:481) (564:564:564)) - (PORT datac (474:474:474) (550:550:550)) - (PORT datad (645:645:645) (746:746:746)) + (PORT dataa (133:133:133) (171:171:171)) + (PORT datab (689:689:689) (799:799:799)) + (PORT datac (642:642:642) (742:742:742)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -7127,419 +4208,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~7) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) (DELAY (ABSOLUTE - (PORT dataa (533:533:533) (624:624:624)) - (PORT datab (880:880:880) (1012:1012:1012)) - (PORT datac (899:899:899) (1030:1030:1030)) - (PORT datad (458:458:458) (518:518:518)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (306:306:306) (359:359:359)) - (PORT datab (728:728:728) (826:826:826)) - (PORT datac (457:457:457) (530:530:530)) - (PORT datad (611:611:611) (695:695:695)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (719:719:719) (817:817:817)) - (PORT datab (131:131:131) (164:164:164)) - (PORT datac (689:689:689) (811:811:811)) - (PORT datad (831:831:831) (959:959:959)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (280:280:280) (327:327:327)) - (PORT datab (462:462:462) (544:544:544)) - (PORT datac (548:548:548) (630:630:630)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) - (DELAY - (ABSOLUTE - (PORT datac (941:941:941) (1092:1092:1092)) - (PORT datad (900:900:900) (1042:1042:1042)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (746:746:746)) - (PORT datab (181:181:181) (243:243:243)) - (PORT datac (164:164:164) (222:222:222)) - (PORT datad (489:489:489) (586:586:586)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (772:772:772) (912:912:912)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (713:713:713) (826:826:826)) - (PORT datad (751:751:751) (878:878:878)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1161:1161:1161) (1334:1334:1334)) - (PORT datab (467:467:467) (538:538:538)) - (PORT datac (825:825:825) (952:952:952)) - (PORT datad (479:479:479) (561:561:561)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1162:1162:1162) (1336:1336:1336)) - (PORT datab (748:748:748) (869:869:869)) - (PORT datac (749:749:749) (877:877:877)) - (PORT datad (477:477:477) (559:559:559)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (121:121:121) (152:152:152)) - (PORT datac (1176:1176:1176) (1353:1353:1353)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (520:520:520) (602:602:602)) - (PORT datab (690:690:690) (818:818:818)) - (PORT datac (653:653:653) (751:751:751)) - (PORT datad (737:737:737) (851:851:851)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (407:407:407)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (437:437:437) (506:506:506)) - (PORT datad (278:278:278) (315:315:315)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (447:447:447)) - (PORT datab (443:443:443) (519:519:519)) - (PORT datac (1368:1368:1368) (1568:1568:1568)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (385:385:385)) - (PORT datab (360:360:360) (420:420:420)) - (PORT datac (1023:1023:1023) (1169:1169:1169)) - (PORT datad (438:438:438) (503:503:503)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla21M3T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (636:636:636)) - (PORT datab (730:730:730) (850:850:850)) - (PORT datac (623:623:623) (731:731:731)) - (PORT datad (642:642:642) (754:754:754)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (151:151:151)) - (PORT datab (432:432:432) (503:503:503)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (102:102:102) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (732:732:732)) - (PORT datab (665:665:665) (777:777:777)) - (PORT datac (98:98:98) (123:123:123)) - (PORT datad (833:833:833) (939:939:939)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (795:795:795) (922:922:922)) - (PORT datab (490:490:490) (569:569:569)) - (PORT datac (280:280:280) (321:321:321)) - (PORT datad (463:463:463) (527:527:527)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (397:397:397)) - (PORT datab (492:492:492) (571:571:571)) - (PORT datac (442:442:442) (511:511:511)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~56) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (862:862:862)) - (PORT datab (640:640:640) (756:756:756)) - (PORT datac (604:604:604) (715:715:715)) - (PORT datad (429:429:429) (493:493:493)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (687:687:687)) - (PORT datab (508:508:508) (591:591:591)) - (PORT datac (903:903:903) (1040:1040:1040)) - (PORT datad (624:624:624) (721:721:721)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (225:225:225)) - (PORT datab (305:305:305) (354:354:354)) - (PORT datac (328:328:328) (384:384:384)) - (PORT datad (107:107:107) (126:126:126)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (744:744:744)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (776:776:776) (903:903:903)) - (PORT datad (513:513:513) (593:593:593)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT datab (464:464:464) (540:540:540)) - (PORT datac (579:579:579) (663:663:663)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (684:684:684)) - (PORT datab (720:720:720) (834:834:834)) - (PORT datac (456:456:456) (524:524:524)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (345:345:345) (407:407:407)) - (PORT datac (619:619:619) (704:704:704)) - (PORT datad (320:320:320) (373:373:373)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (460:460:460) (529:529:529)) - (PORT datac (93:93:93) (117:117:117)) + (PORT dataa (487:487:487) (571:571:571)) + (PORT datab (459:459:459) (531:531:531)) + (PORT datac (173:173:173) (208:208:208)) (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1321:1321:1321)) + (PORT datab (503:503:503) (587:587:587)) + (PORT datac (120:120:120) (149:149:149)) + (PORT datad (788:788:788) (906:906:906)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -7549,13 +4240,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) (DELAY (ABSOLUTE - (PORT dataa (1068:1068:1068) (1230:1230:1230)) - (PORT datab (529:529:529) (617:617:617)) - (PORT datac (292:292:292) (339:339:339)) - (PORT datad (118:118:118) (140:140:140)) + (PORT dataa (1018:1018:1018) (1199:1199:1199)) + (PORT datab (890:890:890) (1045:1045:1045)) + (PORT datad (790:790:790) (920:920:920)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1317:1317:1317)) + (PORT datab (529:529:529) (620:620:620)) + (PORT datac (591:591:591) (687:687:687)) + (PORT datad (502:502:502) (603:603:603)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -7563,28 +4268,910 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (731:731:731) (831:831:831)) + (PORT datab (648:648:648) (761:761:761)) + (PORT datac (824:824:824) (943:943:943)) + (PORT datad (832:832:832) (958:958:958)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (722:722:722)) + (PORT datab (118:118:118) (153:153:153)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (459:459:459) (527:527:527)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT datab (532:532:532) (631:631:631)) + (PORT datac (308:308:308) (355:355:355)) + (PORT datad (372:372:372) (443:443:443)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT datac (509:509:509) (606:606:606)) + (PORT datad (376:376:376) (447:447:447)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (653:653:653)) + (PORT datab (394:394:394) (463:463:463)) + (PORT datac (485:485:485) (568:568:568)) + (PORT datad (984:984:984) (1149:1149:1149)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (998:998:998)) + (PORT datab (833:833:833) (979:979:979)) + (PORT datac (1038:1038:1038) (1201:1201:1201)) + (PORT datad (215:215:215) (255:255:255)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (781:781:781)) + (PORT datac (522:522:522) (609:609:609)) + (PORT datad (685:685:685) (795:795:795)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (790:790:790)) + (PORT datab (795:795:795) (904:904:904)) + (PORT datac (597:597:597) (680:680:680)) + (PORT datad (723:723:723) (824:824:824)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) (DELAY (ABSOLUTE - (PORT dataa (595:595:595) (707:707:707)) - (PORT datab (438:438:438) (509:509:509)) - (PORT datad (555:555:555) (647:647:647)) + (PORT datab (511:511:511) (594:594:594)) + (PORT datac (279:279:279) (321:321:321)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (651:651:651)) + (PORT datab (394:394:394) (463:463:463)) + (PORT datac (484:484:484) (566:566:566)) + (PORT datad (983:983:983) (1148:1148:1148)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (866:866:866)) + (PORT datab (509:509:509) (593:593:593)) + (PORT datad (334:334:334) (391:391:391)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) (DELAY (ABSOLUTE - (PORT datab (122:122:122) (152:152:152)) - (PORT datac (650:650:650) (761:761:761)) - (PORT datad (172:172:172) (202:202:202)) + (PORT dataa (469:469:469) (544:544:544)) + (PORT datab (840:840:840) (975:975:975)) + (PORT datac (739:739:739) (871:871:871)) + (PORT datad (1222:1222:1222) (1416:1416:1416)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1293:1293:1293) (1503:1503:1503)) + (PORT datab (499:499:499) (582:582:582)) + (PORT datac (192:192:192) (228:228:228)) + (PORT datad (821:821:821) (954:954:954)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (128:128:128) (160:160:160)) + (PORT datac (456:456:456) (522:522:522)) + (PORT datad (291:291:291) (331:331:331)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (DELAY + (ABSOLUTE + (PORT datac (1434:1434:1434) (1701:1701:1701)) + (PORT datad (1109:1109:1109) (1285:1285:1285)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (951:951:951)) + (PORT datab (458:458:458) (530:530:530)) + (PORT datac (530:530:530) (608:608:608)) + (PORT datad (362:362:362) (424:424:424)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) + (DELAY + (ABSOLUTE + (PORT dataa (790:790:790) (902:902:902)) + (PORT datab (730:730:730) (837:837:837)) + (PORT datac (453:453:453) (531:531:531)) + (PORT datad (428:428:428) (489:489:489)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (690:690:690)) + (PORT datab (1442:1442:1442) (1669:1669:1669)) + (PORT datac (871:871:871) (1031:1031:1031)) + (PORT datad (948:948:948) (1102:1102:1102)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) + (DELAY + (ABSOLUTE + (PORT datac (112:112:112) (138:138:138)) + (PORT datad (112:112:112) (132:132:132)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (799:799:799)) + (PORT datab (727:727:727) (862:862:862)) + (PORT datac (985:985:985) (1124:1124:1124)) + (PORT datad (446:446:446) (511:511:511)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (242:242:242)) + (PORT datab (204:204:204) (243:243:243)) + (PORT datac (189:189:189) (225:225:225)) + (PORT datad (110:110:110) (134:134:134)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (975:975:975)) + (PORT datab (729:729:729) (862:862:862)) + (PORT datac (491:491:491) (575:575:575)) + (PORT datad (630:630:630) (722:722:722)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (454:454:454)) + (PORT datab (1530:1530:1530) (1769:1769:1769)) + (PORT datac (725:725:725) (854:854:854)) + (PORT datad (307:307:307) (354:354:354)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (556:556:556)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (104:104:104) (132:132:132)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (414:414:414)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (306:306:306) (350:350:350)) + (PORT datad (816:816:816) (927:927:927)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (897:897:897)) + (PORT datab (1023:1023:1023) (1165:1165:1165)) + (PORT datac (627:627:627) (722:722:722)) + (PORT datad (986:986:986) (1115:1115:1115)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1049:1049:1049) (1198:1198:1198)) + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (657:657:657) (749:749:749)) + (PORT datad (325:325:325) (380:380:380)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (395:395:395)) + (PORT datab (578:578:578) (690:690:690)) + (PORT datac (482:482:482) (550:550:550)) + (PORT datad (893:893:893) (1048:1048:1048)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (188:188:188) (226:226:226)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (562:562:562) (628:628:628)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (911:911:911)) + (PORT datab (797:797:797) (920:920:920)) + (PORT datac (330:330:330) (380:380:380)) + (PORT datad (512:512:512) (593:593:593)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (1079:1079:1079)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (1001:1001:1001) (1169:1169:1169)) + (PORT datad (519:519:519) (601:601:601)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (911:911:911)) + (PORT datab (797:797:797) (921:921:921)) + (PORT datac (617:617:617) (724:724:724)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1016:1016:1016) (1164:1164:1164)) + (PORT datab (173:173:173) (209:209:209)) + (PORT datac (614:614:614) (721:721:721)) + (PORT datad (657:657:657) (768:768:768)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (905:905:905)) + (PORT datab (796:796:796) (920:920:920)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (526:526:526) (617:617:617)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (547:547:547) (644:644:644)) + (PORT datac (585:585:585) (667:667:667)) + (PORT datad (656:656:656) (767:767:767)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1268:1268:1268)) + (PORT datab (1019:1019:1019) (1160:1160:1160)) + (PORT datac (624:624:624) (719:719:719)) + (PORT datad (1134:1134:1134) (1315:1315:1315)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (232:232:232)) + (PORT datab (1020:1020:1020) (1161:1161:1161)) + (PORT datac (877:877:877) (996:996:996)) + (PORT datad (98:98:98) (121:121:121)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (409:409:409)) + (PORT datab (570:570:570) (660:660:660)) + (PORT datac (708:708:708) (805:805:805)) + (PORT datad (439:439:439) (498:498:498)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (405:405:405)) + (PORT datac (580:580:580) (650:650:650)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (636:636:636)) + (PORT datab (795:795:795) (919:919:919)) + (PORT datac (546:546:546) (626:626:626)) + (PORT datad (661:661:661) (773:773:773)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (236:236:236)) + (PORT datab (111:111:111) (144:144:144)) + (PORT datac (182:182:182) (221:221:221)) + (PORT datad (178:178:178) (207:207:207)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT datab (349:349:349) (409:409:409)) + (PORT datac (485:485:485) (563:563:563)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (355:355:355)) + (PORT datab (483:483:483) (559:559:559)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (511:511:511)) + (PORT datab (376:376:376) (447:447:447)) + (PORT datac (530:530:530) (609:609:609)) + (PORT datad (443:443:443) (505:505:505)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datab (460:460:460) (537:537:537)) + (PORT datad (436:436:436) (495:495:495)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT datab (113:113:113) (146:146:146)) + (PORT datac (182:182:182) (221:221:221)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (1079:1079:1079)) + (PORT datab (1019:1019:1019) (1194:1194:1194)) + (PORT datac (1001:1001:1001) (1169:1169:1169)) + (PORT datad (533:533:533) (609:609:609)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (911:911:911)) + (PORT datab (796:796:796) (919:919:919)) + (PORT datac (545:545:545) (626:626:626)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1017:1017:1017) (1164:1164:1164)) + (PORT datab (560:560:560) (645:645:645)) + (PORT datac (161:161:161) (190:190:190)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (420:420:420)) + (PORT datab (325:325:325) (375:375:375)) + (PORT datac (441:441:441) (508:508:508)) + (PORT datad (171:171:171) (202:202:202)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (720:720:720) (841:841:841)) + (PORT datab (551:551:551) (651:651:651)) + (PORT datac (608:608:608) (730:730:730)) + (PORT datad (550:550:550) (651:651:651)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (913:913:913)) + (PORT datab (733:733:733) (835:835:835)) + (PORT datac (878:878:878) (998:998:998)) + (PORT datad (718:718:718) (838:838:838)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (760:760:760)) + (PORT datab (583:583:583) (702:702:702)) + (PORT datad (763:763:763) (910:910:910)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (448:448:448)) + (PORT datab (535:535:535) (630:630:630)) + (PORT datac (291:291:291) (336:336:336)) + (PORT datad (119:119:119) (137:137:137)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (491:491:491)) + (PORT datab (531:531:531) (621:621:621)) + (PORT datac (591:591:591) (686:686:686)) + (PORT datad (497:497:497) (597:597:597)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (810:810:810)) + (PORT datab (119:119:119) (153:153:153)) + (PORT datac (1335:1335:1335) (1559:1559:1559)) + (PORT datad (88:88:88) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT datab (1162:1162:1162) (1349:1349:1349)) + (PORT datac (963:963:963) (1116:1116:1116)) + (PORT datad (644:644:644) (755:755:755)) (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -7593,13 +5180,999 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) (DELAY (ABSOLUTE - (PORT dataa (460:460:460) (535:535:535)) - (PORT datab (468:468:468) (542:542:542)) - (PORT datac (197:197:197) (237:237:237)) - (PORT datad (97:97:97) (116:116:116)) + (PORT dataa (803:803:803) (934:934:934)) + (PORT datab (791:791:791) (908:908:908)) + (PORT datac (457:457:457) (519:519:519)) + (PORT datad (205:205:205) (245:245:245)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (472:472:472) (546:546:546)) + (PORT datab (639:639:639) (740:740:740)) + (PORT datac (544:544:544) (643:643:643)) + (PORT datad (551:551:551) (647:647:647)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1360:1360:1360)) + (PORT datab (237:237:237) (277:277:277)) + (PORT datac (560:560:560) (651:651:651)) + (PORT datad (490:490:490) (579:579:579)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~1) + (DELAY + (ABSOLUTE + (PORT datac (908:908:908) (1064:1064:1064)) + (PORT datad (858:858:858) (1006:1006:1006)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (631:631:631)) + (PORT datab (650:650:650) (745:745:745)) + (PORT datac (1107:1107:1107) (1270:1270:1270)) + (PORT datad (361:361:361) (419:419:419)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (331:331:331) (396:396:396)) + (PORT datac (990:990:990) (1152:1152:1152)) + (PORT datad (339:339:339) (397:397:397)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (992:992:992)) + (PORT datab (187:187:187) (227:227:227)) + (PORT datac (1177:1177:1177) (1366:1366:1366)) + (PORT datad (306:306:306) (360:360:360)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (491:491:491)) + (PORT datab (530:530:530) (620:620:620)) + (PORT datac (591:591:591) (686:686:686)) + (PORT datad (499:499:499) (600:600:600)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (969:969:969)) + (PORT datab (689:689:689) (813:813:813)) + (PORT datac (812:812:812) (946:946:946)) + (PORT datad (630:630:630) (718:718:718)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1014:1014:1014) (1193:1193:1193)) + (PORT datab (1143:1143:1143) (1332:1332:1332)) + (PORT datac (720:720:720) (823:823:823)) + (PORT datad (1122:1122:1122) (1302:1302:1302)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (753:753:753)) + (PORT datab (348:348:348) (399:399:399)) + (PORT datac (674:674:674) (787:787:787)) + (PORT datad (322:322:322) (364:364:364)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (711:711:711)) + (PORT datab (455:455:455) (523:523:523)) + (PORT datad (296:296:296) (342:342:342)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) + (DELAY + (ABSOLUTE + (PORT datac (989:989:989) (1149:1149:1149)) + (PORT datad (879:879:879) (1038:1038:1038)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (657:657:657)) + (PORT datab (587:587:587) (695:695:695)) + (PORT datac (594:594:594) (709:709:709)) + (PORT datad (341:341:341) (395:395:395)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (1056:1056:1056)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (595:595:595) (710:710:710)) + (PORT datad (1013:1013:1013) (1180:1180:1180)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (770:770:770)) + (PORT datab (362:362:362) (426:426:426)) + (PORT datac (716:716:716) (846:846:846)) + (PORT datad (886:886:886) (1036:1036:1036)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (111:111:111) (142:142:142)) + (PORT datac (714:714:714) (844:844:844)) + (PORT datad (888:888:888) (1038:1038:1038)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (789:789:789)) + (PORT datab (900:900:900) (1019:1019:1019)) + (PORT datac (423:423:423) (478:478:478)) + (PORT datad (317:317:317) (366:366:366)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (387:387:387)) + (PORT datab (361:361:361) (425:425:425)) + (PORT datac (382:382:382) (448:448:448)) + (PORT datad (467:467:467) (555:555:555)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (652:652:652)) + (PORT datab (912:912:912) (1061:1061:1061)) + (PORT datac (886:886:886) (1038:1038:1038)) + (PORT datad (539:539:539) (626:626:626)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (837:837:837)) + (PORT datab (509:509:509) (594:594:594)) + (PORT datac (543:543:543) (642:642:642)) + (PORT datad (632:632:632) (725:725:725)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (223:223:223)) + (PORT datab (807:807:807) (925:925:925)) + (PORT datac (598:598:598) (678:678:678)) + (PORT datad (743:743:743) (846:846:846)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (225:225:225)) + (PORT datab (126:126:126) (154:154:154)) + (PORT datac (581:581:581) (690:690:690)) + (PORT datad (768:768:768) (885:885:885)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (543:543:543)) + (PORT datab (190:190:190) (228:228:228)) + (PORT datac (365:365:365) (419:419:419)) + (PORT datad (449:449:449) (521:521:521)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (485:485:485)) + (PORT datab (522:522:522) (616:616:616)) + (PORT datac (534:534:534) (632:632:632)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (959:959:959)) + (PORT datab (327:327:327) (388:388:388)) + (PORT datac (677:677:677) (785:785:785)) + (PORT datad (447:447:447) (511:511:511)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (152:152:152)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datac (309:309:309) (352:352:352)) + (PORT datad (464:464:464) (538:538:538)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (774:774:774)) + (PORT datab (537:537:537) (628:628:628)) + (PORT datac (608:608:608) (716:716:716)) + (PORT datad (810:810:810) (922:922:922)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (741:741:741)) + (PORT datab (543:543:543) (635:635:635)) + (PORT datac (158:158:158) (190:190:190)) + (PORT datad (346:346:346) (400:400:400)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (674:674:674)) + (PORT datab (761:761:761) (862:862:862)) + (PORT datac (650:650:650) (750:750:750)) + (PORT datad (664:664:664) (763:763:763)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (684:684:684) (790:790:790)) + (PORT datac (553:553:553) (651:651:651)) + (PORT datad (344:344:344) (398:398:398)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (546:546:546)) + (PORT datab (793:793:793) (910:910:910)) + (PORT datac (931:931:931) (1064:1064:1064)) + (PORT datad (1156:1156:1156) (1339:1339:1339)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (390:390:390)) + (PORT datab (111:111:111) (142:142:142)) + (PORT datac (802:802:802) (918:918:918)) + (PORT datad (792:792:792) (911:911:911)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1014:1014:1014) (1189:1189:1189)) + (PORT datab (452:452:452) (517:517:517)) + (PORT datac (459:459:459) (521:521:521)) + (PORT datad (1156:1156:1156) (1340:1340:1340)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (511:511:511)) + (PORT datab (419:419:419) (486:486:486)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (178:178:178) (218:218:218)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (287:287:287) (330:330:330)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (618:618:618)) + (PORT datab (463:463:463) (527:527:527)) + (PORT datac (958:958:958) (1116:1116:1116)) + (PORT datad (640:640:640) (747:747:747)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (831:831:831)) + (PORT datab (658:658:658) (760:760:760)) + (PORT datac (619:619:619) (706:706:706)) + (PORT datad (370:370:370) (438:438:438)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (763:763:763)) + (PORT datac (314:314:314) (366:366:366)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (757:757:757)) + (PORT datab (349:349:349) (411:411:411)) + (PORT datac (103:103:103) (133:133:133)) + (PORT datad (329:329:329) (379:379:379)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (153:153:153)) + (PORT datac (1178:1178:1178) (1367:1367:1367)) + (PORT datad (827:827:827) (965:965:965)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (266:266:266)) + (PORT datab (640:640:640) (738:738:738)) + (PORT datac (814:814:814) (949:949:949)) + (PORT datad (618:618:618) (707:707:707)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (739:739:739)) + (PORT datab (588:588:588) (702:702:702)) + (PORT datac (650:650:650) (750:750:750)) + (PORT datad (663:663:663) (763:763:763)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (540:540:540)) + (PORT datab (362:362:362) (423:423:423)) + (PORT datac (598:598:598) (686:686:686)) + (PORT datad (410:410:410) (473:473:473)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (704:704:704)) + (PORT datab (881:881:881) (1027:1027:1027)) + (PORT datac (339:339:339) (403:403:403)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (469:469:469)) + (PORT datab (459:459:459) (531:531:531)) + (PORT datac (429:429:429) (487:487:487)) + (PORT datad (362:362:362) (424:424:424)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (675:675:675)) + (PORT datab (541:541:541) (634:634:634)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (810:810:810) (922:922:922)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (859:859:859)) + (PORT datab (541:541:541) (633:633:633)) + (PORT datac (608:608:608) (717:717:717)) + (PORT datad (875:875:875) (1029:1029:1029)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (859:859:859)) + (PORT datab (684:684:684) (790:790:790)) + (PORT datac (553:553:553) (651:651:651)) + (PORT datad (875:875:875) (1030:1030:1030)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datac (92:92:92) (115:115:115)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (341:341:341)) + (PORT datab (127:127:127) (161:161:161)) + (PORT datac (282:282:282) (323:323:323)) + (PORT datad (801:801:801) (933:933:933)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (735:735:735) (853:853:853)) + (PORT datac (296:296:296) (342:342:342)) + (PORT datad (313:313:313) (366:366:366)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (448:448:448)) + (PORT datab (608:608:608) (701:701:701)) + (PORT datac (519:519:519) (611:611:611)) + (PORT datad (647:647:647) (744:744:744)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (609:609:609)) + (PORT datab (533:533:533) (618:618:618)) + (PORT datac (671:671:671) (792:792:792)) + (PORT datad (199:199:199) (230:230:230)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (1110:1110:1110)) + (PORT datab (896:896:896) (1028:1028:1028)) + (PORT datac (730:730:730) (858:858:858)) + (PORT datad (881:881:881) (1044:1044:1044)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (704:704:704)) + (PORT datab (597:597:597) (694:694:694)) + (PORT datac (528:528:528) (615:615:615)) + (PORT datad (438:438:438) (504:504:504)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (639:639:639)) + (PORT datab (374:374:374) (440:440:440)) + (PORT datac (115:115:115) (143:143:143)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (463:463:463) (536:536:536)) + (PORT datab (349:349:349) (410:410:410)) + (PORT datac (485:485:485) (557:557:557)) + (PORT datad (444:444:444) (508:508:508)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (186:186:186) (226:226:226)) + (PORT datac (556:556:556) (646:646:646)) + (PORT datad (305:305:305) (359:359:359)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datac (952:952:952) (1085:1085:1085)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (165:165:165)) + (PORT datab (654:654:654) (759:759:759)) + (PORT datac (672:672:672) (775:775:775)) + (PORT datad (283:283:283) (329:329:329)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (705:705:705)) + (PORT datab (132:132:132) (166:166:166)) + (PORT datac (484:484:484) (566:566:566)) + (PORT datad (1090:1090:1090) (1242:1242:1242)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (440:440:440) (509:509:509)) + (PORT datab (459:459:459) (533:533:533)) + (PORT datac (305:305:305) (363:363:363)) + (PORT datad (437:437:437) (496:496:496)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1198:1198:1198) (1392:1392:1392)) + (PORT datab (994:994:994) (1150:1150:1150)) + (PORT datac (474:474:474) (554:554:554)) + (PORT datad (1331:1331:1331) (1541:1541:1541)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -7609,15 +6182,267 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~29) + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (348:348:348) (419:419:419)) - (PORT datac (359:359:359) (427:427:427)) - (PORT datad (441:441:441) (510:510:510)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (536:536:536) (632:632:632)) + (PORT datab (1179:1179:1179) (1363:1363:1363)) + (PORT datac (287:287:287) (333:333:333)) + (PORT datad (1092:1092:1092) (1271:1271:1271)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~54) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1156:1156:1156)) + (PORT datab (631:631:631) (745:745:745)) + (PORT datac (542:542:542) (622:622:622)) + (PORT datad (1123:1123:1123) (1309:1309:1309)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (789:789:789)) + (PORT datab (648:648:648) (756:756:756)) + (PORT datac (320:320:320) (378:378:378)) + (PORT datad (1286:1286:1286) (1469:1469:1469)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (627:627:627)) + (PORT datab (626:626:626) (720:720:720)) + (PORT datac (181:181:181) (222:222:222)) + (PORT datad (341:341:341) (406:406:406)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (548:548:548)) + (PORT datac (464:464:464) (528:528:528)) + (PORT datad (279:279:279) (316:316:316)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (165:165:165)) + (PORT datab (133:133:133) (168:168:168)) + (PORT datac (1121:1121:1121) (1299:1299:1299)) + (PORT datad (107:107:107) (132:132:132)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (919:919:919)) + (PORT datab (731:731:731) (841:841:841)) + (PORT datac (471:471:471) (548:548:548)) + (PORT datad (816:816:816) (944:944:944)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (753:753:753)) + (PORT datab (386:386:386) (461:461:461)) + (PORT datac (538:538:538) (632:632:632)) + (PORT datad (327:327:327) (376:376:376)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (390:390:390)) + (PORT datab (545:545:545) (654:654:654)) + (PORT datac (970:970:970) (1135:1135:1135)) + (PORT datad (621:621:621) (720:720:720)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1260:1260:1260)) + (PORT datab (471:471:471) (556:556:556)) + (PORT datac (765:765:765) (900:900:900)) + (PORT datad (784:784:784) (899:899:899)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (381:381:381)) + (PORT datab (594:594:594) (706:706:706)) + (PORT datac (109:109:109) (135:135:135)) + (PORT datad (488:488:488) (568:568:568)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (374:374:374)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (482:482:482) (557:557:557)) + (PORT datad (463:463:463) (533:533:533)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (967:967:967) (1114:1114:1114)) + (PORT datab (591:591:591) (723:723:723)) + (PORT datac (676:676:676) (794:794:794)) + (PORT datad (467:467:467) (542:542:542)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (450:450:450)) + (PORT datab (648:648:648) (760:760:760)) + (PORT datac (824:824:824) (943:943:943)) + (PORT datad (832:832:832) (958:958:958)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (463:463:463) (539:539:539)) + (PORT datab (747:747:747) (852:852:852)) + (PORT datac (415:415:415) (480:480:480)) + (PORT datad (970:970:970) (1105:1105:1105)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (770:770:770) (910:910:910)) + (PORT datab (1305:1305:1305) (1522:1522:1522)) + (PORT datac (615:615:615) (716:716:716)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (624:624:624)) + (PORT datab (567:567:567) (659:659:659)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (354:354:354) (414:414:414)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -7625,12 +6450,104 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~24) + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) (DELAY (ABSOLUTE - (PORT datab (500:500:500) (588:588:588)) - (PORT datac (1369:1369:1369) (1570:1570:1570)) - (PORT datad (734:734:734) (840:840:840)) + (PORT dataa (310:310:310) (369:369:369)) + (PORT datab (369:369:369) (432:432:432)) + (PORT datac (264:264:264) (301:301:301)) + (PORT datad (463:463:463) (533:533:533)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (486:486:486) (561:561:561)) + (PORT datac (485:485:485) (559:559:559)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1469:1469:1469)) + (PORT datac (812:812:812) (947:947:947)) + (PORT datad (1276:1276:1276) (1472:1472:1472)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (DELAY + (ABSOLUTE + (PORT datab (530:530:530) (627:627:627)) + (PORT datac (861:861:861) (1011:1011:1011)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (446:446:446)) + (PORT datab (460:460:460) (536:536:536)) + (PORT datac (734:734:734) (872:872:872)) + (PORT datad (483:483:483) (564:564:564)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (964:964:964)) + (PORT datab (107:107:107) (136:136:136)) + (PORT datac (572:572:572) (655:655:655)) + (PORT datad (573:573:573) (670:670:670)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (124:124:124) (160:160:160)) + (PORT datab (190:190:190) (227:227:227)) + (PORT datac (331:331:331) (387:387:387)) + (PORT datad (106:106:106) (129:129:129)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -7639,14 +6556,286 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (INSTANCE z80_\|execute_\|ctl_iorw\~11) (DELAY (ABSOLUTE - (PORT dataa (1303:1303:1303) (1513:1513:1513)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (652:652:652) (773:773:773)) - (PORT datad (104:104:104) (121:121:121)) + (PORT dataa (923:923:923) (1088:1088:1088)) + (PORT datab (874:874:874) (1029:1029:1029)) + (PORT datac (978:978:978) (1128:1128:1128)) + (PORT datad (817:817:817) (933:933:933)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (992:992:992) (1133:1133:1133)) + (PORT datab (370:370:370) (439:439:439)) + (PORT datac (287:287:287) (334:334:334)) + (PORT datad (622:622:622) (722:722:722)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (463:463:463)) + (PORT datab (555:555:555) (664:664:664)) + (PORT datac (101:101:101) (121:121:121)) + (PORT datad (716:716:716) (833:833:833)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (368:368:368)) + (PORT datab (477:477:477) (554:554:554)) + (PORT datac (175:175:175) (209:209:209)) + (PORT datad (384:384:384) (454:454:454)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (422:422:422)) + (PORT datab (530:530:530) (611:611:611)) + (PORT datac (315:315:315) (365:365:365)) + (PORT datad (356:356:356) (417:417:417)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (705:705:705)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (298:298:298) (348:348:348)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (283:283:283)) + (PORT datab (723:723:723) (852:852:852)) + (PORT datac (383:383:383) (464:464:464)) + (PORT datad (731:731:731) (868:868:868)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (1020:1020:1020)) + (PORT datab (492:492:492) (582:582:582)) + (PORT datac (706:706:706) (818:818:818)) + (PORT datad (917:917:917) (1048:1048:1048)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (229:229:229)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (366:366:366) (437:437:437)) + (PORT datad (918:918:918) (1050:1050:1050)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (866:866:866)) + (PORT datab (663:663:663) (763:763:763)) + (PORT datac (634:634:634) (740:740:740)) + (PORT datad (752:752:752) (892:892:892)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (561:561:561)) + (PORT datab (193:193:193) (235:235:235)) + (PORT datac (360:360:360) (431:431:431)) + (PORT datad (661:661:661) (765:765:765)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (672:672:672)) + (PORT datab (482:482:482) (567:567:567)) + (PORT datac (579:579:579) (678:678:678)) + (PORT datad (481:481:481) (566:566:566)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (138:138:138)) + (PORT datab (534:534:534) (641:641:641)) + (PORT datac (469:469:469) (537:537:537)) + (PORT datad (501:501:501) (584:584:584)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (649:649:649)) + (PORT datab (658:658:658) (766:766:766)) + (PORT datac (883:883:883) (1035:1035:1035)) + (PORT datad (636:636:636) (741:741:741)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (405:405:405)) + (PORT datab (1177:1177:1177) (1396:1396:1396)) + (PORT datac (470:470:470) (542:542:542)) + (PORT datad (682:682:682) (803:803:803)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (578:578:578)) + (PORT datab (477:477:477) (561:561:561)) + (PORT datac (603:603:603) (695:695:695)) + (PORT datad (482:482:482) (568:568:568)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (682:682:682)) + (PORT datab (908:908:908) (1071:1071:1071)) + (PORT datac (341:341:341) (391:391:391)) + (PORT datad (959:959:959) (1118:1118:1118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1348:1348:1348) (1572:1572:1572)) + (PORT datab (930:930:930) (1114:1114:1114)) + (PORT datac (515:515:515) (597:597:597)) + (PORT datad (376:376:376) (440:440:440)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -7655,43 +6844,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~31) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) (DELAY (ABSOLUTE - (PORT dataa (325:325:325) (381:381:381)) - (PORT datab (551:551:551) (650:650:650)) - (PORT datac (340:340:340) (397:397:397)) - (PORT datad (472:472:472) (545:545:545)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (568:568:568) (676:676:676)) + (PORT datad (880:880:880) (1030:1030:1030)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) (DELAY (ABSOLUTE - (PORT dataa (611:611:611) (700:700:700)) - (PORT datab (774:774:774) (904:904:904)) - (PORT datad (513:513:513) (593:593:593)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (742:742:742) (866:866:866)) + (PORT datab (360:360:360) (425:425:425)) + (PORT datac (754:754:754) (862:862:862)) + (PORT datad (479:479:479) (556:556:556)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) (DELAY (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datac (355:355:355) (422:422:422)) - (PORT datad (340:340:340) (396:396:396)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (625:625:625) (720:720:720)) + (PORT datab (973:973:973) (1143:1143:1143)) + (PORT datac (891:891:891) (1050:1050:1050)) + (PORT datad (559:559:559) (657:657:657)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (DELAY + (ABSOLUTE + (PORT dataa (772:772:772) (924:924:924)) + (PORT datab (455:455:455) (530:530:530)) + (PORT datac (609:609:609) (694:694:694)) + (PORT datad (355:355:355) (422:422:422)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -7699,13 +6904,339 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) (DELAY (ABSOLUTE - (PORT dataa (541:541:541) (623:623:623)) - (PORT datab (499:499:499) (568:568:568)) - (PORT datac (622:622:622) (737:737:737)) - (PORT datad (410:410:410) (475:475:475)) + (PORT datab (653:653:653) (759:759:759)) + (PORT datac (103:103:103) (124:124:124)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (466:466:466) (543:543:543)) + (PORT datac (103:103:103) (131:131:131)) + (PORT datad (372:372:372) (448:448:448)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (637:637:637)) + (PORT datab (518:518:518) (603:603:603)) + (PORT datac (782:782:782) (906:906:906)) + (PORT datad (285:285:285) (323:323:323)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (373:373:373)) + (PORT datab (472:472:472) (548:548:548)) + (PORT datac (768:768:768) (902:902:902)) + (PORT datad (837:837:837) (992:992:992)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (605:605:605)) + (PORT datab (478:478:478) (562:562:562)) + (PORT datac (502:502:502) (594:594:594)) + (PORT datad (861:861:861) (1018:1018:1018)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (735:735:735)) + (PORT datab (345:345:345) (419:419:419)) + (PORT datac (496:496:496) (578:578:578)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (DELAY + (ABSOLUTE + (PORT datab (841:841:841) (988:988:988)) + (PORT datac (974:974:974) (1125:1125:1125)) + (PORT datad (587:587:587) (666:666:666)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (441:441:441)) + (PORT datab (657:657:657) (752:752:752)) + (PORT datac (468:468:468) (540:540:540)) + (PORT datad (660:660:660) (773:773:773)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (595:595:595)) + (PORT datab (520:520:520) (613:613:613)) + (PORT datac (345:345:345) (409:409:409)) + (PORT datad (629:629:629) (732:732:732)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT datab (476:476:476) (555:555:555)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (465:465:465) (535:535:535)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (633:633:633)) + (PORT datab (811:811:811) (939:939:939)) + (PORT datac (711:711:711) (816:816:816)) + (PORT datad (463:463:463) (532:532:532)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (1083:1083:1083)) + (PORT datab (919:919:919) (1069:1069:1069)) + (PORT datac (837:837:837) (986:986:986)) + (PORT datad (465:465:465) (533:533:533)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (936:936:936)) + (PORT datab (920:920:920) (1071:1071:1071)) + (PORT datac (925:925:925) (1058:1058:1058)) + (PORT datad (655:655:655) (760:760:760)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (576:576:576)) + (PORT datab (318:318:318) (370:370:370)) + (PORT datac (836:836:836) (966:966:966)) + (PORT datad (306:306:306) (350:350:350)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (597:597:597)) + (PORT datab (500:500:500) (584:584:584)) + (PORT datac (481:481:481) (564:564:564)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) + (DELAY + (ABSOLUTE + (PORT dataa (1015:1015:1015) (1177:1177:1177)) + (PORT datab (971:971:971) (1140:1140:1140)) + (PORT datac (892:892:892) (1051:1051:1051)) + (PORT datad (561:561:561) (658:658:658)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (1090:1090:1090)) + (PORT datac (1406:1406:1406) (1623:1623:1623)) + (PORT datad (835:835:835) (990:990:990)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (733:733:733)) + (PORT datab (652:652:652) (753:753:753)) + (PORT datac (103:103:103) (124:124:124)) + (PORT datad (469:469:469) (539:539:539)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (365:365:365) (434:434:434)) + (PORT datac (201:201:201) (241:241:241)) + (PORT datad (107:107:107) (127:127:127)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (285:285:285)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (432:432:432) (496:496:496)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (236:236:236)) + (PORT datab (480:480:480) (553:553:553)) + (PORT datac (336:336:336) (397:397:397)) + (PORT datad (667:667:667) (771:771:771)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (831:831:831)) + (PORT datab (935:935:935) (1119:1119:1119)) + (PORT datac (518:518:518) (601:601:601)) + (PORT datad (517:517:517) (606:606:606)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -7718,10 +7249,10 @@ (INSTANCE z80_\|pla_decode_\|Equal1\~6) (DELAY (ABSOLUTE - (PORT dataa (679:679:679) (775:775:775)) - (PORT datab (459:459:459) (530:530:530)) - (PORT datac (467:467:467) (548:548:548)) - (PORT datad (680:680:680) (778:778:778)) + (PORT dataa (822:822:822) (960:960:960)) + (PORT datab (959:959:959) (1114:1114:1114)) + (PORT datac (446:446:446) (515:515:515)) + (PORT datad (358:358:358) (424:424:424)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -7734,11 +7265,11 @@ (INSTANCE z80_\|reg_control_\|bank_exx\~2) (DELAY (ABSOLUTE - (PORT dataa (718:718:718) (833:833:833)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datad (667:667:667) (787:787:787)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (190:190:190) (205:205:205)) + (PORT dataa (787:787:787) (943:943:943)) + (PORT datab (491:491:491) (569:569:569)) + (PORT datad (1310:1310:1310) (1532:1532:1532)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -7749,9 +7280,9 @@ (INSTANCE z80_\|reg_control_\|bank_exx) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) + (PORT clk (903:903:903) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (896:896:896)) + (PORT clrn (914:914:914) (898:898:898)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -7762,13 +7293,338 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (1086:1086:1086)) - (PORT datab (693:693:693) (830:830:830)) - (PORT datac (543:543:543) (625:625:625)) - (PORT datad (487:487:487) (551:551:551)) + (PORT dataa (635:635:635) (739:739:739)) + (PORT datab (660:660:660) (759:759:759)) + (PORT datad (671:671:671) (796:796:796)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (929:929:929) (911:911:911)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (597:597:597)) + (PORT datab (1135:1135:1135) (1296:1296:1296)) + (PORT datac (427:427:427) (493:493:493)) + (PORT datad (177:177:177) (207:207:207)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (593:593:593)) + (PORT datab (953:953:953) (1084:1084:1084)) + (PORT datac (698:698:698) (818:818:818)) + (PORT datad (630:630:630) (733:733:733)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (472:472:472)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (698:698:698) (819:819:819)) + (PORT datad (863:863:863) (1020:1020:1020)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (793:793:793)) + (PORT datab (732:732:732) (861:861:861)) + (PORT datac (629:629:629) (733:733:733)) + (PORT datad (403:403:403) (485:485:485)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (395:395:395)) + (PORT datab (308:308:308) (356:356:356)) + (PORT datac (494:494:494) (576:576:576)) + (PORT datad (981:981:981) (1128:1128:1128)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (597:597:597)) + (PORT datab (186:186:186) (222:222:222)) + (PORT datac (645:645:645) (746:746:746)) + (PORT datad (1145:1145:1145) (1339:1339:1339)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (489:489:489) (568:568:568)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (652:652:652)) + (PORT datab (518:518:518) (615:615:615)) + (PORT datac (584:584:584) (657:657:657)) + (PORT datad (581:581:581) (648:648:648)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (897:897:897)) + (PORT datab (498:498:498) (585:585:585)) + (PORT datac (356:356:356) (420:420:420)) + (PORT datad (635:635:635) (739:739:739)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1325:1325:1325)) + (PORT datac (919:919:919) (1039:1039:1039)) + (PORT datad (967:967:967) (1114:1114:1114)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (657:657:657)) + (PORT datab (729:729:729) (840:840:840)) + (PORT datac (765:765:765) (881:881:881)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT datab (355:355:355) (410:410:410)) + (PORT datac (347:347:347) (408:408:408)) + (PORT datad (506:506:506) (589:589:589)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (418:418:418)) + (PORT datab (384:384:384) (447:447:447)) + (PORT datac (369:369:369) (448:448:448)) + (PORT datad (440:440:440) (506:506:506)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (541:541:541)) + (PORT datac (1089:1089:1089) (1248:1248:1248)) + (PORT datad (106:106:106) (130:130:130)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (408:408:408)) + (PORT datab (484:484:484) (566:566:566)) + (PORT datac (603:603:603) (690:690:690)) + (PORT datad (450:450:450) (521:521:521)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (734:734:734)) + (PORT datab (567:567:567) (668:668:668)) + (PORT datac (770:770:770) (894:894:894)) + (PORT datad (106:106:106) (131:131:131)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (736:736:736)) + (PORT datab (1101:1101:1101) (1277:1277:1277)) + (PORT datac (627:627:627) (722:722:722)) + (PORT datad (523:523:523) (615:615:615)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (104:104:104) (134:134:134)) + (PORT datac (1507:1507:1507) (1752:1752:1752)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (627:627:627)) + (PORT datac (614:614:614) (716:716:716)) + (PORT datad (629:629:629) (727:727:727)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (627:627:627)) + (PORT datab (449:449:449) (517:517:517)) + (PORT datac (1117:1117:1117) (1276:1276:1276)) + (PORT datad (774:774:774) (885:885:885)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -7778,14 +7634,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) (DELAY (ABSOLUTE - (PORT dataa (987:987:987) (1161:1161:1161)) - (PORT datab (435:435:435) (506:506:506)) - (PORT datac (968:968:968) (1118:1118:1118)) - (PORT datad (671:671:671) (800:800:800)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT dataa (902:902:902) (1057:1057:1057)) + (PORT datab (498:498:498) (586:586:586)) + (PORT datac (510:510:510) (598:598:598)) + (PORT datad (857:857:857) (1010:1010:1010)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (407:407:407)) + (PORT datab (461:461:461) (537:537:537)) + (PORT datac (338:338:338) (398:398:398)) + (PORT datad (435:435:435) (494:494:494)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (758:758:758)) + (PORT datac (784:784:784) (900:900:900)) + (PORT datad (1170:1170:1170) (1359:1359:1359)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (599:599:599)) + (PORT datab (901:901:901) (1063:1063:1063)) + (PORT datac (114:114:114) (141:141:141)) + (PORT datad (334:334:334) (384:384:384)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (761:761:761) (889:889:889)) + (PORT datab (330:330:330) (387:387:387)) + (PORT datac (415:415:415) (481:481:481)) + (PORT datad (318:318:318) (369:369:369)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -7794,44 +7712,1541 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (637:637:637) (750:750:750)) - (PORT datac (912:912:912) (1054:1054:1054)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (1079:1079:1079)) - (PORT datab (688:688:688) (824:824:824)) - (PORT datac (538:538:538) (620:620:620)) - (PORT datad (484:484:484) (548:548:548)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT dataa (932:932:932) (1074:1074:1074)) + (PORT datab (609:609:609) (691:691:691)) + (PORT datac (596:596:596) (705:705:705)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (240:240:240)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datad (103:103:103) (119:119:119)) + (PORT dataa (743:743:743) (891:891:891)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (325:325:325) (376:376:376)) + (PORT datad (819:819:819) (947:947:947)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (357:357:357)) + (PORT datab (344:344:344) (408:408:408)) + (PORT datac (325:325:325) (383:383:383)) + (PORT datad (304:304:304) (348:348:348)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1261:1261:1261) (1461:1461:1461)) + (PORT datab (140:140:140) (187:187:187)) + (PORT datac (637:637:637) (730:730:730)) + (PORT datad (128:128:128) (165:165:165)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (92:92:92) (116:116:116)) + (PORT datad (480:480:480) (556:556:556)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (110:110:110) (140:140:140)) + (PORT datad (361:361:361) (422:422:422)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (152:152:152)) + (PORT datab (565:565:565) (667:667:667)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (387:387:387) (457:457:457)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (794:794:794)) + (PORT datac (495:495:495) (585:585:585)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) + (DELAY + (ABSOLUTE + (PORT datac (369:369:369) (448:448:448)) + (PORT datad (488:488:488) (560:560:560)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (928:928:928)) + (PORT datab (331:331:331) (393:393:393)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (624:624:624) (709:709:709)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~47) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (371:371:371)) + (PORT datab (340:340:340) (397:397:397)) + (PORT datac (479:479:479) (553:553:553)) + (PORT datad (482:482:482) (556:556:556)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (219:219:219)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (335:335:335) (395:395:395)) + (PORT datad (573:573:573) (656:656:656)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1326:1326:1326)) + (PORT datac (919:919:919) (1039:1039:1039)) + (PORT datad (967:967:967) (1114:1114:1114)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (765:765:765) (907:907:907)) + (PORT datab (604:604:604) (690:690:690)) + (PORT datac (516:516:516) (599:599:599)) + (PORT datad (293:293:293) (334:334:334)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (156:156:156)) + (PORT datab (120:120:120) (150:150:150)) + (PORT datac (654:654:654) (762:762:762)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (515:515:515)) + (PORT datab (712:712:712) (832:832:832)) + (PORT datac (1031:1031:1031) (1187:1187:1187)) + (PORT datad (1174:1174:1174) (1364:1364:1364)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (328:328:328) (385:385:385)) + (PORT datac (305:305:305) (362:362:362)) + (PORT datad (463:463:463) (529:529:529)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) + (DELAY + (ABSOLUTE + (PORT dataa (771:771:771) (923:923:923)) + (PORT datab (414:414:414) (500:500:500)) + (PORT datac (475:475:475) (552:552:552)) + (PORT datad (502:502:502) (582:582:582)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (542:542:542)) + (PORT datab (383:383:383) (458:458:458)) + (PORT datac (538:538:538) (636:636:636)) + (PORT datad (996:996:996) (1148:1148:1148)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (836:836:836)) + (PORT datab (488:488:488) (567:567:567)) + (PORT datac (342:342:342) (392:392:392)) + (PORT datad (963:963:963) (1107:1107:1107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (926:926:926)) + (PORT datab (366:366:366) (431:431:431)) + (PORT datac (477:477:477) (555:555:555)) + (PORT datad (199:199:199) (229:229:229)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (582:582:582)) + (PORT datab (386:386:386) (461:461:461)) + (PORT datac (547:547:547) (642:642:642)) + (PORT datad (335:335:335) (387:387:387)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (941:941:941)) + (PORT datab (505:505:505) (589:589:589)) + (PORT datac (100:100:100) (122:122:122)) + (PORT datad (789:789:789) (906:906:906)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (1060:1060:1060)) + (PORT datab (872:872:872) (999:999:999)) + (PORT datac (560:560:560) (651:651:651)) + (PORT datad (878:878:878) (1014:1014:1014)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (954:954:954)) + (PORT datab (516:516:516) (618:618:618)) + (PORT datac (467:467:467) (556:556:556)) + (PORT datad (307:307:307) (356:356:356)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (950:950:950)) + (PORT datab (517:517:517) (619:619:619)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (505:505:505) (591:591:591)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (309:309:309) (359:359:359)) + (PORT datab (475:475:475) (554:554:554)) + (PORT datac (449:449:449) (536:536:536)) + (PORT datad (442:442:442) (526:526:526)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (406:406:406)) + (PORT datab (127:127:127) (160:160:160)) + (PORT datac (739:739:739) (871:871:871)) + (PORT datad (1224:1224:1224) (1419:1419:1419)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1204:1204:1204)) + (PORT datab (900:900:900) (1065:1065:1065)) + (PORT datac (729:729:729) (864:864:864)) + (PORT datad (1439:1439:1439) (1664:1664:1664)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (825:825:825)) + (PORT datab (461:461:461) (536:536:536)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (313:313:313) (365:365:365)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (958:958:958)) + (PORT datab (143:143:143) (176:176:176)) + (PORT datac (676:676:676) (784:784:784)) + (PORT datad (447:447:447) (511:511:511)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~2) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (573:573:573)) + (PORT datab (480:480:480) (559:559:559)) + (PORT datac (464:464:464) (541:541:541)) + (PORT datad (488:488:488) (587:587:587)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (554:554:554)) + (PORT datab (510:510:510) (610:610:610)) + (PORT datac (102:102:102) (128:128:128)) + (PORT datad (653:653:653) (748:748:748)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (920:920:920)) + (PORT datab (842:842:842) (981:981:981)) + (PORT datac (610:610:610) (703:703:703)) + (PORT datad (212:212:212) (252:252:252)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (570:570:570)) + (PORT datab (482:482:482) (561:561:561)) + (PORT datac (467:467:467) (545:545:545)) + (PORT datad (490:490:490) (589:589:589)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (489:489:489)) + (PORT datab (437:437:437) (539:539:539)) + (PORT datad (641:641:641) (743:743:743)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (369:369:369)) + (PORT datab (640:640:640) (739:739:739)) + (PORT datac (472:472:472) (550:550:550)) + (PORT datad (504:504:504) (582:582:582)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (958:958:958)) + (PORT datab (461:461:461) (536:536:536)) + (PORT datac (714:714:714) (822:822:822)) + (PORT datad (879:879:879) (1038:1038:1038)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (998:998:998)) + (PORT datab (789:789:789) (902:902:902)) + (PORT datac (816:816:816) (958:958:958)) + (PORT datad (214:214:214) (254:254:254)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (655:655:655)) + (PORT datac (425:425:425) (486:486:486)) + (PORT datad (548:548:548) (625:625:625)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (132:132:132)) + (PORT datab (214:214:214) (257:257:257)) + (PORT datac (547:547:547) (625:625:625)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (320:320:320) (367:367:367)) + (PORT datad (862:862:862) (1021:1021:1021)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (788:788:788)) + (PORT datab (680:680:680) (797:797:797)) + (PORT datac (492:492:492) (568:568:568)) + (PORT datad (877:877:877) (1018:1018:1018)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (459:459:459) (542:542:542)) + (PORT datab (119:119:119) (152:152:152)) + (PORT datac (654:654:654) (764:764:764)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (1081:1081:1081)) + (PORT datab (921:921:921) (1072:1072:1072)) + (PORT datac (838:838:838) (987:987:987)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (523:523:523) (628:628:628)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (666:666:666) (777:777:777)) + (PORT datad (496:496:496) (567:567:567)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (660:660:660) (761:761:761)) + (PORT datac (678:678:678) (804:804:804)) + (PORT datad (424:424:424) (481:481:481)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (580:580:580)) + (PORT datab (502:502:502) (601:601:601)) + (PORT datac (628:628:628) (727:727:727)) + (PORT datad (200:200:200) (241:241:241)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (823:823:823)) + (PORT datab (657:657:657) (758:758:758)) + (PORT datac (626:626:626) (725:725:725)) + (PORT datad (423:423:423) (480:480:480)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (190:190:190)) + (PORT datab (119:119:119) (153:153:153)) + (PORT datac (178:178:178) (212:212:212)) + (PORT datad (681:681:681) (806:806:806)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (742:742:742)) + (PORT datab (658:658:658) (758:758:758)) + (PORT datad (677:677:677) (802:802:802)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (929:929:929) (911:911:911)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (231:231:231)) + (PORT datab (117:117:117) (151:151:151)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (668:668:668) (791:791:791)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (339:339:339)) + (PORT datab (567:567:567) (669:669:669)) + (PORT datac (175:175:175) (209:209:209)) + (PORT datad (384:384:384) (454:454:454)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (423:423:423)) + (PORT datab (975:975:975) (1126:1126:1126)) + (PORT datad (469:469:469) (536:536:536)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (1477:1477:1477) (1704:1704:1704)) + (PORT datab (970:970:970) (1139:1139:1139)) + (PORT datac (568:568:568) (656:656:656)) + (PORT datad (861:861:861) (996:996:996)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (464:464:464) (548:548:548)) + (PORT datac (841:841:841) (978:978:978)) + (PORT datad (687:687:687) (788:788:788)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (626:626:626)) + (PORT datab (106:106:106) (137:137:137)) + (PORT datac (527:527:527) (615:615:615)) + (PORT datad (111:111:111) (132:132:132)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla30npla13M5T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (520:520:520) (613:613:613)) + (PORT datab (120:120:120) (154:154:154)) + (PORT datac (770:770:770) (895:895:895)) + (PORT datad (844:844:844) (974:974:974)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (737:737:737)) + (PORT datab (849:849:849) (985:985:985)) + (PORT datac (329:329:329) (386:386:386)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (224:224:224)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (573:573:573)) + (PORT datab (355:355:355) (418:418:418)) + (PORT datac (598:598:598) (686:686:686)) + (PORT datad (410:410:410) (473:473:473)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (1088:1088:1088)) + (PORT datab (861:861:861) (993:993:993)) + (PORT datac (978:978:978) (1128:1128:1128)) + (PORT datad (577:577:577) (656:656:656)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1388:1388:1388)) + (PORT datab (845:845:845) (992:992:992)) + (PORT datac (835:835:835) (979:979:979)) + (PORT datad (1090:1090:1090) (1237:1237:1237)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (596:596:596)) + (PORT datab (481:481:481) (558:558:558)) + (PORT datac (472:472:472) (562:562:562)) + (PORT datad (885:885:885) (1041:1041:1041)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (399:399:399)) + (PORT datab (369:369:369) (437:437:437)) + (PORT datac (514:514:514) (596:596:596)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (447:447:447)) + (PORT datab (678:678:678) (781:781:781)) + (PORT datac (357:357:357) (421:421:421)) + (PORT datad (741:741:741) (871:871:871)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (892:892:892)) + (PORT datab (350:350:350) (409:409:409)) + (PORT datac (717:717:717) (828:828:828)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (755:755:755)) + (PORT datab (1014:1014:1014) (1171:1171:1171)) + (PORT datad (550:550:550) (651:651:651)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (561:561:561)) + (PORT datab (376:376:376) (446:446:446)) + (PORT datac (107:107:107) (130:130:130)) + (PORT datad (1233:1233:1233) (1400:1400:1400)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (805:805:805)) + (PORT datab (841:841:841) (994:994:994)) + (PORT datac (668:668:668) (785:785:785)) + (PORT datad (675:675:675) (774:774:774)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1061:1061:1061) (1218:1218:1218)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (500:500:500) (596:596:596)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (375:375:375)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (497:497:497) (568:568:568)) + (PORT datad (464:464:464) (555:555:555)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (469:469:469) (560:560:560)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (289:289:289) (340:340:340)) + (PORT datad (344:344:344) (402:402:402)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (540:540:540)) + (PORT datac (112:112:112) (139:139:139)) + (PORT datad (106:106:106) (130:130:130)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (837:837:837)) + (PORT datab (324:324:324) (381:381:381)) + (PORT datac (455:455:455) (526:526:526)) + (PORT datad (318:318:318) (373:373:373)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (923:923:923)) + (PORT datab (495:495:495) (579:579:579)) + (PORT datac (643:643:643) (731:731:731)) + (PORT datad (660:660:660) (773:773:773)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (1138:1138:1138)) + (PORT datab (445:445:445) (512:512:512)) + (PORT datac (1117:1117:1117) (1277:1277:1277)) + (PORT datad (1145:1145:1145) (1327:1327:1327)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~40) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (597:597:597)) + (PORT datab (619:619:619) (713:713:713)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (330:330:330)) + (PORT datab (364:364:364) (430:430:430)) + (PORT datac (1103:1103:1103) (1260:1260:1260)) + (PORT datad (281:281:281) (320:320:320)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (498:498:498) (594:594:594)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (103:103:103) (121:121:121)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (465:465:465) (539:539:539)) + (PORT datac (299:299:299) (348:348:348)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (774:774:774)) + (PORT datab (555:555:555) (630:630:630)) + (PORT datac (642:642:642) (731:731:731)) + (PORT datad (735:735:735) (845:845:845)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (185:185:185)) + (PORT datab (117:117:117) (150:150:150)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (668:668:668) (792:792:792)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT datab (758:758:758) (873:873:873)) + (PORT datac (634:634:634) (722:722:722)) + (PORT datad (325:325:325) (377:377:377)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) + (DELAY + (ABSOLUTE + (PORT datac (504:504:504) (580:580:580)) + (PORT datad (733:733:733) (840:840:840)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (758:758:758)) + (PORT datab (118:118:118) (152:152:152)) + (PORT datac (631:631:631) (727:727:727)) + (PORT datad (374:374:374) (434:434:434)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (466:466:466)) + (PORT datab (817:817:817) (959:959:959)) + (PORT datac (634:634:634) (731:731:731)) + (PORT datad (107:107:107) (132:132:132)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (461:461:461)) + (PORT datab (821:821:821) (964:964:964)) + (PORT datac (628:628:628) (724:724:724)) + (PORT datad (103:103:103) (128:128:128)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (743:743:743) (872:872:872)) + (PORT datab (472:472:472) (548:548:548)) + (PORT datac (1037:1037:1037) (1204:1204:1204)) + (PORT datad (878:878:878) (1011:1011:1011)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datad (467:467:467) (543:543:543)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (653:653:653)) + (PORT datab (349:349:349) (411:411:411)) + (PORT datac (514:514:514) (595:595:595)) + (PORT datad (833:833:833) (968:968:968)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (713:713:713)) + (PORT datab (399:399:399) (482:482:482)) + (PORT datac (817:817:817) (959:959:959)) + (PORT datad (835:835:835) (972:972:972)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (310:310:310) (366:366:366)) + (PORT datab (106:106:106) (137:137:137)) + (PORT datac (337:337:337) (397:397:397)) + (PORT datad (591:591:591) (668:668:668)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (241:241:241)) + (PORT datab (643:643:643) (746:746:746)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (593:593:593) (677:677:677)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (814:814:814)) + (PORT datab (882:882:882) (1040:1040:1040)) + (PORT datac (1221:1221:1221) (1398:1398:1398)) + (PORT datad (597:597:597) (722:722:722)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (615:615:615)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (686:686:686) (808:808:808)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (398:398:398)) + (PORT datac (352:352:352) (414:414:414)) + (PORT datad (292:292:292) (332:332:332)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (736:736:736)) + (PORT datab (113:113:113) (146:146:146)) + (PORT datac (625:625:625) (721:721:721)) + (PORT datad (369:369:369) (429:429:429)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -7841,9 +9256,9 @@ (INSTANCE z80_\|pla_decode_\|Equal21\~2) (DELAY (ABSOLUTE - (PORT dataa (1029:1029:1029) (1187:1187:1187)) - (PORT datab (470:470:470) (555:555:555)) - (PORT datac (504:504:504) (602:602:602)) + (PORT dataa (489:489:489) (571:571:571)) + (PORT datab (486:486:486) (563:563:563)) + (PORT datac (499:499:499) (608:608:608)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -7855,11 +9270,11 @@ (INSTANCE z80_\|reg_control_\|bank_af\~0) (DELAY (ABSOLUTE - (PORT dataa (458:458:458) (538:538:538)) - (PORT datab (129:129:129) (162:162:162)) - (PORT datad (453:453:453) (522:522:522)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (161:161:161) (174:174:174)) + (PORT dataa (383:383:383) (447:447:447)) + (PORT datab (643:643:643) (742:742:742)) + (PORT datad (509:509:509) (596:596:596)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -7870,9 +9285,9 @@ (INSTANCE z80_\|reg_control_\|bank_af) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) + (PORT clk (907:907:907) (911:911:911)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (896:896:896)) + (PORT clrn (918:918:918) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -7886,13 +9301,27 @@ (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (1054:1054:1054)) - (PORT datab (138:138:138) (188:188:188)) - (PORT datac (557:557:557) (646:646:646)) - (PORT datad (825:825:825) (933:933:933)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT dataa (633:633:633) (736:736:736)) + (PORT datab (133:133:133) (182:182:182)) + (PORT datac (634:634:634) (730:730:730)) + (PORT datad (376:376:376) (436:436:436)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (432:432:432)) + (PORT datab (745:745:745) (856:856:856)) + (PORT datad (516:516:516) (594:594:594)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -7902,40 +9331,40 @@ (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) (DELAY (ABSOLUTE - (PORT dataa (905:905:905) (1055:1055:1055)) - (PORT datab (135:135:135) (186:186:186)) - (PORT datac (554:554:554) (643:643:643)) - (PORT datad (823:823:823) (932:932:932)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (959:959:959) (1118:1118:1118)) - (PORT datab (588:588:588) (677:677:677)) - (PORT datad (902:902:902) (1044:1044:1044)) + (PORT dataa (632:632:632) (736:736:736)) + (PORT datab (134:134:134) (183:183:183)) + (PORT datac (627:627:627) (723:723:723)) + (PORT datad (371:371:371) (431:431:431)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) (DELAY (ABSOLUTE - (PORT dataa (496:496:496) (587:587:587)) - (PORT datab (614:614:614) (711:711:711)) - (PORT datac (461:461:461) (537:537:537)) - (PORT datad (658:658:658) (746:746:746)) + (PORT dataa (971:971:971) (1123:1123:1123)) + (PORT datab (648:648:648) (745:745:745)) + (PORT datad (431:431:431) (486:486:486)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (455:455:455)) + (PORT datab (502:502:502) (588:588:588)) + (PORT datac (1028:1028:1028) (1200:1200:1200)) + (PORT datad (612:612:612) (705:705:705)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -7945,15 +9374,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) (DELAY (ABSOLUTE - (PORT dataa (920:920:920) (1063:1063:1063)) - (PORT datab (293:293:293) (345:345:345)) - (PORT datac (748:748:748) (860:860:860)) - (PORT datad (546:546:546) (637:637:637)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (830:830:830) (978:978:978)) + (PORT datac (587:587:587) (665:665:665)) + (PORT datad (166:166:166) (198:198:198)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -7961,63 +9388,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) (DELAY (ABSOLUTE - (PORT dataa (680:680:680) (789:789:789)) - (PORT datab (1465:1465:1465) (1681:1681:1681)) - (PORT datac (447:447:447) (522:522:522)) - (PORT datad (906:906:906) (1050:1050:1050)) + (PORT dataa (784:784:784) (904:904:904)) + (PORT datab (654:654:654) (760:760:760)) + (PORT datac (1151:1151:1151) (1341:1341:1341)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) (DELAY (ABSOLUTE - (PORT dataa (556:556:556) (633:633:633)) - (PORT datab (595:595:595) (683:683:683)) - (PORT datac (542:542:542) (620:620:620)) - (PORT datad (611:611:611) (706:706:706)) + (PORT dataa (648:648:648) (747:747:747)) + (PORT datab (1147:1147:1147) (1325:1325:1325)) + (PORT datac (527:527:527) (620:620:620)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (843:843:843) (962:962:962)) - (PORT datab (466:466:466) (542:542:542)) - (PORT datac (676:676:676) (767:767:767)) - (PORT datad (612:612:612) (707:707:707)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (562:562:562)) - (PORT datab (103:103:103) (133:133:133)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (612:612:612) (707:707:707)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -8025,31 +9418,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (INSTANCE z80_\|execute_\|fMRead\~24) (DELAY (ABSOLUTE - (PORT dataa (626:626:626) (724:724:724)) - (PORT datab (396:396:396) (476:476:476)) - (PORT datac (463:463:463) (542:542:542)) - (PORT datad (368:368:368) (422:422:422)) + (PORT dataa (484:484:484) (575:575:575)) + (PORT datab (853:853:853) (990:990:990)) + (PORT datac (714:714:714) (819:819:819)) + (PORT datad (469:469:469) (539:539:539)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (409:409:409)) - (PORT datab (345:345:345) (409:409:409)) - (PORT datac (607:607:607) (693:693:693)) - (PORT datad (459:459:459) (521:521:521)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -8057,13 +9434,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) + (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) (DELAY (ABSOLUTE - (PORT dataa (745:745:745) (864:864:864)) - (PORT datab (807:807:807) (928:928:928)) - (PORT datac (358:358:358) (417:417:417)) - (PORT datad (427:427:427) (483:483:483)) + (PORT datab (119:119:119) (149:149:149)) + (PORT datac (106:106:106) (129:129:129)) + (PORT datad (107:107:107) (125:125:125)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (914:914:914) (1068:1068:1068)) + (PORT datac (108:108:108) (134:134:134)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (364:364:364)) + (PORT datab (477:477:477) (553:553:553)) + (PORT datac (753:753:753) (873:873:873)) + (PORT datad (1084:1084:1084) (1240:1240:1240)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (149:149:149)) + (PORT datab (1128:1128:1128) (1305:1305:1305)) + (PORT datac (431:431:431) (494:494:494)) + (PORT datad (102:102:102) (120:120:120)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (454:454:454)) + (PORT datab (808:808:808) (935:935:935)) + (PORT datac (188:188:188) (222:222:222)) + (PORT datad (640:640:640) (734:734:734)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -8073,13 +9512,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) (DELAY (ABSOLUTE - (PORT dataa (121:121:121) (155:155:155)) - (PORT datab (475:475:475) (547:547:547)) - (PORT datac (822:822:822) (934:934:934)) - (PORT datad (178:178:178) (207:207:207)) + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (293:293:293) (340:340:340)) + (PORT datac (435:435:435) (496:496:496)) + (PORT datad (315:315:315) (366:366:366)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (772:772:772)) + (PORT datab (310:310:310) (361:361:361)) + (PORT datac (359:359:359) (431:431:431)) + (PORT datad (462:462:462) (531:531:531)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (454:454:454)) + (PORT datab (649:649:649) (751:751:751)) + (PORT datac (659:659:659) (753:753:753)) + (PORT datad (314:314:314) (361:361:361)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (556:556:556)) + (PORT datab (677:677:677) (783:783:783)) + (PORT datac (489:489:489) (563:563:563)) + (PORT datad (354:354:354) (417:417:417)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (310:310:310) (360:360:360)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (89:89:89) (106:106:106)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -8087,31 +9590,15 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (676:676:676)) - (PORT datab (712:712:712) (826:826:826)) - (PORT datac (831:831:831) (959:959:959)) - (PORT datad (362:362:362) (430:430:430)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) (DELAY (ABSOLUTE - (PORT dataa (1064:1064:1064) (1217:1217:1217)) - (PORT datab (304:304:304) (351:351:351)) - (PORT datac (173:173:173) (209:209:209)) - (PORT datad (103:103:103) (121:121:121)) + (PORT dataa (498:498:498) (577:577:577)) + (PORT datab (676:676:676) (782:782:782)) + (PORT datac (191:191:191) (226:226:226)) + (PORT datad (639:639:639) (733:733:733)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -8124,108 +9611,12 @@ (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (919:919:919) (1053:1053:1053)) - (PORT datad (436:436:436) (499:499:499)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (1001:1001:1001)) - (PORT datab (598:598:598) (695:695:695)) - (PORT datac (574:574:574) (657:657:657)) - (PORT datad (458:458:458) (522:522:522)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (702:702:702)) - (PORT datab (473:473:473) (548:548:548)) - (PORT datac (437:437:437) (494:494:494)) - (PORT datad (446:446:446) (522:522:522)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (953:953:953) (1106:1106:1106)) - (PORT datab (472:472:472) (543:543:543)) - (PORT datac (586:586:586) (678:678:678)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (451:451:451) (523:523:523)) - (PORT datab (491:491:491) (573:573:573)) - (PORT datac (382:382:382) (434:434:434)) - (PORT datad (998:998:998) (1126:1126:1126)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (701:701:701)) - (PORT datab (491:491:491) (573:573:573)) - (PORT datac (894:894:894) (1028:1028:1028)) - (PORT datad (342:342:342) (406:406:406)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (211:211:211)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (658:658:658) (771:771:771)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (660:660:660) (754:754:754)) + (PORT datad (460:460:460) (530:530:530)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -8236,10 +9627,290 @@ (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) (DELAY (ABSOLUTE - (PORT dataa (337:337:337) (398:398:398)) - (PORT datab (224:224:224) (267:267:267)) - (PORT datac (434:434:434) (501:501:501)) - (PORT datad (781:781:781) (895:895:895)) + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (360:360:360) (431:431:431)) + (PORT datad (467:467:467) (543:543:543)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (312:312:312) (370:370:370)) + (PORT datab (366:366:366) (434:434:434)) + (PORT datac (201:201:201) (241:241:241)) + (PORT datad (108:108:108) (128:128:128)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (322:322:322) (373:373:373)) + (PORT datac (272:272:272) (312:312:312)) + (PORT datad (473:473:473) (544:544:544)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (595:595:595)) + (PORT datab (880:880:880) (1044:1044:1044)) + (PORT datac (767:767:767) (891:891:891)) + (PORT datad (106:106:106) (129:129:129)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (385:385:385)) + (PORT datab (535:535:535) (642:642:642)) + (PORT datac (970:970:970) (1136:1136:1136)) + (PORT datad (626:626:626) (726:726:726)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~49) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (712:712:712)) + (PORT datab (832:832:832) (978:978:978)) + (PORT datac (904:904:904) (1039:1039:1039)) + (PORT datad (643:643:643) (748:748:748)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (875:875:875)) + (PORT datab (693:693:693) (802:802:802)) + (PORT datac (688:688:688) (789:789:789)) + (PORT datad (713:713:713) (830:830:830)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (717:717:717)) + (PORT datac (326:326:326) (385:385:385)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (126:126:126) (161:161:161)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (623:623:623) (726:726:726)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~35) + (DELAY + (ABSOLUTE + (PORT datab (1124:1124:1124) (1293:1293:1293)) + (PORT datac (736:736:736) (840:840:840)) + (PORT datad (461:461:461) (530:530:530)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (147:147:147)) + (PORT datab (490:490:490) (568:568:568)) + (PORT datac (331:331:331) (391:391:391)) + (PORT datad (516:516:516) (598:598:598)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (973:973:973)) + (PORT datab (646:646:646) (742:742:742)) + (PORT datac (620:620:620) (707:707:707)) + (PORT datad (288:288:288) (330:330:330)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (392:392:392)) + (PORT datab (123:123:123) (154:154:154)) + (PORT datac (619:619:619) (716:716:716)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (1082:1082:1082)) + (PORT datab (563:563:563) (663:663:663)) + (PORT datac (574:574:574) (685:685:685)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (756:756:756)) + (PORT datab (861:861:861) (1015:1015:1015)) + (PORT datad (106:106:106) (124:124:124)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (562:562:562)) + (PORT datab (304:304:304) (350:350:350)) + (PORT datac (309:309:309) (367:367:367)) + (PORT datad (316:316:316) (362:362:362)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (795:795:795)) + (PORT datab (730:730:730) (859:859:859)) + (PORT datac (626:626:626) (729:729:729)) + (PORT datad (399:399:399) (481:481:481)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (448:448:448)) + (PORT datab (713:713:713) (821:821:821)) + (PORT datac (662:662:662) (773:773:773)) + (PORT datad (928:928:928) (1065:1065:1065)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (692:692:692)) + (PORT datab (490:490:490) (570:570:570)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (119:119:119) (137:137:137)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -8249,13 +9920,195 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~16) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) (DELAY (ABSOLUTE - (PORT dataa (347:347:347) (417:417:417)) - (PORT datab (454:454:454) (528:528:528)) - (PORT datac (104:104:104) (126:126:126)) - (PORT datad (453:453:453) (522:522:522)) + (PORT dataa (581:581:581) (703:703:703)) + (PORT datac (1206:1206:1206) (1387:1387:1387)) + (PORT datad (371:371:371) (437:437:437)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (473:473:473)) + (PORT datab (615:615:615) (712:712:712)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (620:620:620) (713:713:713)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (672:672:672)) + (PORT datab (349:349:349) (415:415:415)) + (PORT datac (559:559:559) (671:671:671)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (515:515:515) (599:599:599)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (152:152:152) (203:203:203)) + (PORT datac (130:130:130) (173:173:173)) + (PORT datad (135:135:135) (175:175:175)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (612:612:612)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (605:605:605) (688:688:688)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (755:755:755)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (368:368:368) (439:439:439)) + (PORT datad (550:550:550) (651:651:651)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1417:1417:1417) (1651:1651:1651)) + (PORT datab (891:891:891) (1048:1048:1048)) + (PORT datac (102:102:102) (124:124:124)) + (PORT datad (117:117:117) (141:141:141)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (682:682:682)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (481:481:481) (555:555:555)) + (PORT datad (452:452:452) (517:517:517)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (512:512:512) (597:597:597)) + (PORT datad (334:334:334) (397:397:397)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (412:412:412)) + (PORT datab (516:516:516) (605:605:605)) + (PORT datac (600:600:600) (684:684:684)) + (PORT datad (105:105:105) (124:124:124)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (577:577:577)) + (PORT datab (490:490:490) (573:573:573)) + (PORT datac (345:345:345) (403:403:403)) + (PORT datad (480:480:480) (557:557:557)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1322:1322:1322)) + (PORT datab (506:506:506) (590:590:590)) + (PORT datac (117:117:117) (145:145:145)) + (PORT datad (619:619:619) (717:717:717)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -8263,47 +10116,139 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (593:593:593)) + (PORT datab (498:498:498) (586:586:586)) + (PORT datac (476:476:476) (560:560:560)) + (PORT datad (326:326:326) (381:381:381)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (585:585:585)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (673:673:673)) + (PORT datab (494:494:494) (579:579:579)) + (PORT datac (340:340:340) (402:402:402)) + (PORT datad (481:481:481) (557:557:557)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1373:1373:1373) (1595:1595:1595)) + (PORT datab (1019:1019:1019) (1196:1196:1196)) + (PORT datac (581:581:581) (652:652:652)) + (PORT datad (902:902:902) (1065:1065:1065)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) (DELAY (ABSOLUTE - (PORT dataa (722:722:722) (831:831:831)) - (PORT datab (497:497:497) (584:584:584)) - (PORT datac (480:480:480) (570:570:570)) - (PORT datad (467:467:467) (542:542:542)) + (PORT dataa (446:446:446) (511:511:511)) + (PORT datab (476:476:476) (564:564:564)) + (PORT datac (443:443:443) (521:521:521)) + (PORT datad (90:90:90) (108:108:108)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (109:109:109) (140:140:140)) - (PORT datac (429:429:429) (498:498:498)) - (PORT datad (431:431:431) (497:497:497)) - (IOPATH dataa combout (159:159:159) (163:163:163)) + (PORT dataa (1375:1375:1375) (1597:1597:1597)) + (PORT datab (1373:1373:1373) (1593:1593:1593)) + (PORT datac (780:780:780) (900:900:900)) + (PORT datad (901:901:901) (1063:1063:1063)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datac (109:109:109) (133:133:133)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (827:827:827)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (436:436:436) (498:498:498)) + (PORT datad (475:475:475) (552:552:552)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_al_we\~4) (DELAY (ABSOLUTE - (PORT dataa (480:480:480) (557:557:557)) - (PORT datab (828:828:828) (972:972:972)) - (PORT datac (600:600:600) (690:690:690)) - (PORT datad (644:644:644) (742:742:742)) + (PORT dataa (473:473:473) (549:549:549)) + (PORT datab (126:126:126) (158:158:158)) + (PORT datac (347:347:347) (409:409:409)) + (PORT datad (752:752:752) (857:857:857)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -8313,76 +10258,130 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~40) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) (DELAY (ABSOLUTE - (PORT dataa (749:749:749) (883:883:883)) - (PORT datab (643:643:643) (749:749:749)) - (PORT datac (811:811:811) (963:963:963)) - (PORT datad (98:98:98) (121:121:121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (273:273:273)) - (PORT datab (639:639:639) (749:749:749)) - (PORT datac (298:298:298) (339:339:339)) - (PORT datad (110:110:110) (131:131:131)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~18) - (DELAY - (ABSOLUTE - (PORT dataa (286:286:286) (336:336:336)) - (PORT datab (528:528:528) (617:617:617)) - (PORT datac (408:408:408) (467:467:467)) - (PORT datad (328:328:328) (385:385:385)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (534:534:534)) - (PORT datac (457:457:457) (530:530:530)) - (PORT datad (538:538:538) (611:611:611)) + (PORT dataa (690:690:690) (814:814:814)) + (PORT datab (773:773:773) (932:932:932)) + (PORT datac (486:486:486) (570:570:570)) + (PORT datad (444:444:444) (510:510:510)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1145:1145:1145) (1330:1330:1330)) + (PORT datab (1472:1472:1472) (1749:1749:1749)) + (PORT datac (1647:1647:1647) (1903:1903:1903)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (458:458:458) (537:537:537)) + (PORT datac (551:551:551) (649:649:649)) + (PORT datad (778:778:778) (883:883:883)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (150:150:150)) + (PORT datac (354:354:354) (417:417:417)) + (PORT datad (595:595:595) (705:705:705)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) + (DELAY + (ABSOLUTE + (PORT dataa (754:754:754) (904:904:904)) + (PORT datac (642:642:642) (743:743:743)) + (PORT datad (1138:1138:1138) (1332:1332:1332)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (697:697:697)) + (PORT datab (117:117:117) (147:147:147)) + (PORT datac (321:321:321) (376:376:376)) + (PORT datad (646:646:646) (746:746:746)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (780:780:780)) + (PORT datac (631:631:631) (719:719:719)) + (PORT datad (529:529:529) (623:623:623)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT datab (1181:1181:1181) (1364:1364:1364)) + (PORT datac (512:512:512) (606:606:606)) + (PORT datad (1094:1094:1094) (1273:1273:1273)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) (DELAY (ABSOLUTE - (PORT dataa (567:567:567) (653:653:653)) - (PORT datab (658:658:658) (768:768:768)) - (PORT datac (938:938:938) (1094:1094:1094)) - (PORT datad (445:445:445) (518:518:518)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (656:656:656) (766:766:766)) + (PORT datab (306:306:306) (356:356:356)) + (PORT datac (495:495:495) (571:571:571)) + (PORT datad (625:625:625) (719:719:719)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -8394,10 +10393,40 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) (DELAY (ABSOLUTE - (PORT dataa (562:562:562) (641:641:641)) - (PORT datab (118:118:118) (148:148:148)) - (PORT datac (630:630:630) (720:720:720)) - (PORT datad (90:90:90) (108:108:108)) + (PORT dataa (619:619:619) (717:717:717)) + (PORT datab (303:303:303) (352:352:352)) + (PORT datac (624:624:624) (716:716:716)) + (PORT datad (468:468:468) (543:543:543)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1011:1011:1011) (1173:1173:1173)) + (PORT datab (882:882:882) (1025:1025:1025)) + (PORT datad (553:553:553) (642:642:642)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (586:586:586)) + (PORT datab (643:643:643) (754:754:754)) + (PORT datac (834:834:834) (971:971:971)) + (PORT datad (609:609:609) (698:698:698)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -8407,155 +10436,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (729:729:729)) - (PORT datab (1056:1056:1056) (1200:1200:1200)) - (PORT datac (711:711:711) (818:818:818)) - (PORT datad (296:296:296) (350:350:350)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (573:573:573)) - (PORT datab (765:765:765) (888:888:888)) - (PORT datac (1029:1029:1029) (1176:1176:1176)) - (PORT datad (445:445:445) (506:506:506)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (790:790:790)) - (PORT datab (719:719:719) (817:817:817)) - (PORT datac (1110:1110:1110) (1278:1278:1278)) - (PORT datad (488:488:488) (568:568:568)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (953:953:953) (1105:1105:1105)) - (PORT datab (894:894:894) (1022:1022:1022)) - (PORT datac (340:340:340) (392:392:392)) - (PORT datad (447:447:447) (523:523:523)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (555:555:555)) - (PORT datab (478:478:478) (558:558:558)) - (PORT datac (441:441:441) (512:512:512)) - (PORT datad (281:281:281) (321:321:321)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (139:139:139)) - (PORT datac (107:107:107) (130:130:130)) - (PORT datad (343:343:343) (402:402:402)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~40) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1087:1087:1087)) - (PORT datab (502:502:502) (595:595:595)) - (PORT datac (290:290:290) (331:331:331)) - (PORT datad (1354:1354:1354) (1553:1553:1553)) + (PORT dataa (378:378:378) (441:441:441)) + (PORT datab (491:491:491) (569:569:569)) + (PORT datac (328:328:328) (388:388:388)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (987:987:987)) - (PORT datab (562:562:562) (648:648:648)) - (PORT datac (321:321:321) (379:379:379)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (1013:1013:1013)) - (PORT datab (424:424:424) (513:513:513)) - (PORT datac (720:720:720) (826:826:826)) - (PORT datad (312:312:312) (359:359:359)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (176:176:176) (217:217:217)) - (PORT datab (946:946:946) (1089:1089:1089)) - (PORT datac (326:326:326) (384:384:384)) - (PORT datad (795:795:795) (904:904:904)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -8566,13 +10455,29 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (106:106:106) (137:137:137)) - (PORT datac (674:674:674) (772:772:772)) - (PORT datad (325:325:325) (376:376:376)) + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (857:857:857) (971:971:971)) + (PORT datad (89:89:89) (107:107:107)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (586:586:586)) + (PORT datab (505:505:505) (595:595:595)) + (PORT datac (97:97:97) (123:123:123)) + (PORT datad (476:476:476) (545:545:545)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -8580,140 +10485,28 @@ (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (519:519:519) (609:609:609)) - (PORT datab (775:775:775) (898:898:898)) - (PORT datac (749:749:749) (865:865:865)) - (PORT datad (498:498:498) (574:574:574)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (736:736:736) (854:854:854)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) (DELAY (ABSOLUTE (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (535:535:535) (616:616:616)) - (PORT datad (90:90:90) (108:108:108)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (976:976:976) (1116:1116:1116)) + (PORT datad (173:173:173) (202:202:202)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (802:802:802)) - (PORT datab (894:894:894) (1049:1049:1049)) - (PORT datac (1196:1196:1196) (1380:1380:1380)) - (PORT datad (348:348:348) (400:400:400)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (137:137:137)) - (PORT datab (533:533:533) (609:609:609)) - (PORT datac (548:548:548) (625:625:625)) - (PORT datad (105:105:105) (123:123:123)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (816:816:816)) - (PORT datab (846:846:846) (985:985:985)) - (PORT datac (1197:1197:1197) (1380:1380:1380)) - (PORT datad (876:876:876) (1026:1026:1026)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (460:460:460) (534:534:534)) - (PORT datab (105:105:105) (133:133:133)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (332:332:332) (392:392:392)) - (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) (DELAY (ABSOLUTE - (PORT dataa (527:527:527) (617:617:617)) - (PORT datab (547:547:547) (639:639:639)) - (PORT datac (716:716:716) (822:822:822)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (178:178:178) (217:217:217)) - (PORT datab (291:291:291) (338:338:338)) - (PORT datac (346:346:346) (407:407:407)) - (PORT datad (341:341:341) (401:401:401)) + (PORT dataa (651:651:651) (750:750:750)) + (PORT datab (436:436:436) (510:510:510)) + (PORT datac (453:453:453) (529:529:529)) + (PORT datad (92:92:92) (111:111:111)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -8723,14 +10516,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) (DELAY (ABSOLUTE - (PORT dataa (568:568:568) (656:656:656)) - (PORT datab (594:594:594) (677:677:677)) - (PORT datac (340:340:340) (405:405:405)) - (PORT datad (658:658:658) (750:750:750)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (867:867:867) (1021:1021:1021)) + (PORT datab (977:977:977) (1131:1131:1131)) + (PORT datac (1461:1461:1461) (1688:1688:1688)) + (PORT datad (636:636:636) (733:733:733)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1480:1480:1480) (1707:1707:1707)) + (PORT datab (909:909:909) (1072:1072:1072)) + (PORT datac (343:343:343) (393:393:393)) + (PORT datad (108:108:108) (128:128:128)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (311:311:311) (362:362:362)) + (PORT datab (354:354:354) (417:417:417)) + (PORT datac (357:357:357) (412:412:412)) + (PORT datad (484:484:484) (555:555:555)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -8739,13 +10564,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) (DELAY (ABSOLUTE - (PORT dataa (608:608:608) (720:720:720)) - (PORT datab (575:575:575) (656:656:656)) - (PORT datac (564:564:564) (639:639:639)) - (PORT datad (469:469:469) (545:545:545)) + (PORT datab (377:377:377) (446:446:446)) + (PORT datac (568:568:568) (654:654:654)) + (PORT datad (503:503:503) (584:584:584)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (231:231:231)) + (PORT datab (610:610:610) (698:698:698)) + (PORT datac (569:569:569) (645:645:645)) + (PORT datad (455:455:455) (523:523:523)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -8755,137 +10594,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) (DELAY (ABSOLUTE - (PORT dataa (1312:1312:1312) (1503:1503:1503)) - (PORT datab (474:474:474) (550:550:550)) - (PORT datac (631:631:631) (729:729:729)) - (PORT datad (577:577:577) (664:664:664)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (670:670:670)) - (PORT datab (757:757:757) (888:888:888)) - (PORT datac (734:734:734) (875:875:875)) - (PORT datad (446:446:446) (530:530:530)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (812:812:812)) - (PORT datab (614:614:614) (711:711:711)) - (PORT datac (529:529:529) (596:596:596)) - (PORT datad (287:287:287) (336:336:336)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (545:545:545)) - (PORT datab (470:470:470) (541:541:541)) - (PORT datac (258:258:258) (291:291:291)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (145:145:145)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (351:351:351) (412:412:412)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (725:725:725)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (676:676:676) (774:774:774)) - (PORT datad (597:597:597) (686:686:686)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT datac (164:164:164) (194:194:194)) - (PORT datad (329:329:329) (383:383:383)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (570:570:570) (648:648:648)) - (PORT datab (499:499:499) (591:591:591)) - (PORT datac (345:345:345) (407:407:407)) - (PORT datad (661:661:661) (754:754:754)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (456:456:456) (526:526:526)) - (PORT datab (451:451:451) (524:524:524)) - (PORT datac (725:725:725) (823:823:823)) - (PORT datad (487:487:487) (574:574:574)) + (PORT dataa (966:966:966) (1113:1113:1113)) + (PORT datab (482:482:482) (562:562:562)) + (PORT datac (866:866:866) (1010:1010:1010)) + (PORT datad (630:630:630) (738:738:738)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -8895,30 +10610,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) (DELAY (ABSOLUTE - (PORT dataa (303:303:303) (355:355:355)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (185:185:185) (215:215:215)) + (PORT dataa (621:621:621) (716:716:716)) + (PORT datab (911:911:911) (1046:1046:1046)) + (PORT datac (623:623:623) (725:725:725)) + (PORT datad (114:114:114) (137:137:137)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (975:975:975) (1136:1136:1136)) - (PORT datab (343:343:343) (404:404:404)) - (PORT datac (572:572:572) (655:655:655)) - (PORT datad (388:388:388) (459:459:459)) - (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -8927,14 +10626,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) (DELAY (ABSOLUTE - (PORT dataa (499:499:499) (581:581:581)) - (PORT datab (923:923:923) (1057:1057:1057)) - (PORT datac (338:338:338) (403:403:403)) - (PORT datad (748:748:748) (846:846:846)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (364:364:364) (423:423:423)) + (PORT datab (628:628:628) (731:731:731)) + (PORT datac (641:641:641) (735:735:735)) + (PORT datad (539:539:539) (628:628:628)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~1) + (DELAY + (ABSOLUTE + (PORT dataa (159:159:159) (204:204:204)) + (PORT datac (940:940:940) (1084:1084:1084)) + (PORT datad (238:238:238) (284:284:284)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (422:422:422)) + (PORT datab (636:636:636) (742:742:742)) + (PORT datac (850:850:850) (970:970:970)) + (PORT datad (715:715:715) (832:832:832)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -8943,169 +10672,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) (DELAY (ABSOLUTE - (PORT dataa (979:979:979) (1141:1141:1141)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (103:103:103) (125:125:125)) + (PORT dataa (784:784:784) (914:914:914)) + (PORT datab (496:496:496) (583:583:583)) + (PORT datac (475:475:475) (562:562:562)) + (PORT datad (530:530:530) (618:618:618)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (546:546:546)) + (PORT datac (568:568:568) (667:667:667)) (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (753:753:753)) - (PORT datab (773:773:773) (893:893:893)) - (PORT datac (702:702:702) (816:816:816)) - (PORT datad (897:897:897) (1038:1038:1038)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (767:767:767) (890:890:890)) - (PORT datab (704:704:704) (815:815:815)) - (PORT datac (551:551:551) (651:651:651)) - (PORT datad (109:109:109) (130:130:130)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (401:401:401)) - (PORT datab (462:462:462) (538:538:538)) - (PORT datac (1195:1195:1195) (1371:1371:1371)) - (PORT datad (480:480:480) (557:557:557)) (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (641:641:641)) - (PORT datab (112:112:112) (144:144:144)) - (PORT datac (715:715:715) (833:833:833)) - (PORT datad (595:595:595) (689:689:689)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (803:803:803)) - (PORT datab (783:783:783) (909:909:909)) - (PORT datac (1362:1362:1362) (1559:1559:1559)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (529:529:529) (608:608:608)) - (PORT datab (681:681:681) (783:783:783)) - (PORT datac (554:554:554) (639:639:639)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (1043:1043:1043)) - (PORT datab (1082:1082:1082) (1219:1219:1219)) - (PORT datac (443:443:443) (506:506:506)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (306:306:306) (362:362:362)) - (PORT datab (857:857:857) (976:976:976)) - (PORT datac (381:381:381) (451:451:451)) - (PORT datad (634:634:634) (740:740:740)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (536:536:536)) - (PORT datab (346:346:346) (406:406:406)) - (PORT datac (453:453:453) (520:520:520)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (794:794:794) (920:920:920)) - (PORT datac (468:468:468) (539:539:539)) - (PORT datad (439:439:439) (501:501:501)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -9113,93 +10702,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) (DELAY (ABSOLUTE - (PORT dataa (766:766:766) (889:889:889)) - (PORT datac (547:547:547) (646:646:646)) - (PORT datad (689:689:689) (790:790:790)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (754:754:754) (896:896:896)) - (PORT datab (417:417:417) (483:483:483)) - (PORT datac (443:443:443) (509:509:509)) - (PORT datad (555:555:555) (651:651:651)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (756:756:756)) - (PORT datab (584:584:584) (670:670:670)) - (PORT datac (445:445:445) (516:516:516)) - (PORT datad (463:463:463) (541:541:541)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (867:867:867)) - (PORT datab (1207:1207:1207) (1387:1387:1387)) - (PORT datac (703:703:703) (812:812:812)) - (PORT datad (868:868:868) (990:990:990)) + (PORT dataa (593:593:593) (713:713:713)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (593:593:593) (674:674:674)) + (PORT datad (93:93:93) (113:113:113)) (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1651:1651:1651) (1896:1896:1896)) - (PORT datab (751:751:751) (858:858:858)) - (PORT datac (465:465:465) (548:548:548)) - (PORT datad (558:558:558) (638:638:638)) - (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (524:524:524)) - (PORT datab (457:457:457) (546:546:546)) - (PORT datac (458:458:458) (560:560:560)) - (PORT datad (693:693:693) (789:789:789)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -9207,41 +10718,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) (DELAY (ABSOLUTE - (PORT datac (365:365:365) (428:428:428)) - (PORT datad (99:99:99) (121:121:121)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (395:395:395)) - (PORT datab (359:359:359) (418:418:418)) - (PORT datad (295:295:295) (345:345:345)) + (PORT dataa (177:177:177) (214:214:214)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (182:182:182) (222:222:222)) + (PORT datad (467:467:467) (538:538:538)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) - (DELAY - (ABSOLUTE - (PORT dataa (1197:1197:1197) (1395:1395:1395)) - (PORT datab (793:793:793) (911:911:911)) - (PORT datac (810:810:810) (952:952:952)) - (PORT datad (1310:1310:1310) (1518:1518:1518)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -9249,528 +10734,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (479:479:479) (558:558:558)) - (PORT datac (96:96:96) (121:121:121)) - (PORT datad (749:749:749) (860:860:860)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (606:606:606)) - (PORT datab (705:705:705) (809:809:809)) - (PORT datac (858:858:858) (993:993:993)) - (PORT datad (747:747:747) (859:859:859)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (986:986:986)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (797:797:797) (932:932:932)) - (PORT datad (613:613:613) (723:723:723)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (785:785:785)) - (PORT datab (459:459:459) (529:529:529)) - (PORT datac (729:729:729) (867:867:867)) - (PORT datad (693:693:693) (789:789:789)) + (PORT dataa (755:755:755) (871:871:871)) + (PORT datab (439:439:439) (502:502:502)) + (PORT datac (946:946:946) (1093:1093:1093)) + (PORT datad (508:508:508) (588:588:588)) (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (747:747:747) (880:880:880)) - (PORT datab (452:452:452) (539:539:539)) - (PORT datac (701:701:701) (809:809:809)) - (PORT datad (841:841:841) (1012:1012:1012)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (573:573:573)) - (PORT datab (617:617:617) (732:732:732)) - (PORT datac (616:616:616) (734:734:734)) - (PORT datad (714:714:714) (830:830:830)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (138:138:138) (175:175:175)) - (PORT datad (624:624:624) (716:716:716)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (653:653:653)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (92:92:92) (115:115:115)) - (PORT datad (361:361:361) (430:430:430)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (404:404:404)) - (PORT datab (478:478:478) (557:557:557)) - (PORT datac (280:280:280) (323:323:323)) - (PORT datad (462:462:462) (533:533:533)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (790:790:790)) - (PORT datab (481:481:481) (559:559:559)) - (PORT datad (167:167:167) (198:198:198)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) - (DELAY - (ABSOLUTE - (PORT datac (356:356:356) (424:424:424)) - (PORT datad (573:573:573) (657:657:657)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (690:690:690)) - (PORT datab (479:479:479) (562:562:562)) - (PORT datac (481:481:481) (557:557:557)) - (PORT datad (643:643:643) (744:744:744)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (748:748:748) (861:861:861)) - (PORT datab (472:472:472) (548:548:548)) - (PORT datac (670:670:670) (771:771:771)) - (PORT datad (646:646:646) (754:754:754)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (118:118:118) (149:149:149)) - (PORT datab (659:659:659) (769:769:769)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (911:911:911) (1039:1039:1039)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (317:317:317) (380:380:380)) - (PORT datab (651:651:651) (744:744:744)) - (PORT datac (646:646:646) (753:753:753)) - (PORT datad (564:564:564) (638:638:638)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (763:763:763) (893:893:893)) - (PORT datab (459:459:459) (536:536:536)) - (PORT datac (695:695:695) (790:790:790)) - (PORT datad (649:649:649) (757:757:757)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (482:482:482) (575:575:575)) - (PORT datab (721:721:721) (831:831:831)) - (PORT datac (641:641:641) (761:761:761)) - (PORT datad (718:718:718) (837:837:837)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (960:960:960)) - (PORT datab (465:465:465) (549:549:549)) - (PORT datac (758:758:758) (878:878:878)) - (PORT datad (587:587:587) (669:669:669)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1200:1200:1200) (1399:1399:1399)) - (PORT datab (794:794:794) (912:912:912)) - (PORT datac (804:804:804) (944:944:944)) - (PORT datad (1313:1313:1313) (1521:1521:1521)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (1058:1058:1058)) - (PORT datab (959:959:959) (1112:1112:1112)) - (PORT datac (468:468:468) (545:545:545)) - (PORT datad (618:618:618) (706:706:706)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (330:330:330) (388:388:388)) - (PORT datad (105:105:105) (125:125:125)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (471:471:471) (549:549:549)) - (PORT datab (631:631:631) (735:735:735)) - (PORT datac (337:337:337) (400:400:400)) - (PORT datad (321:321:321) (375:375:375)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (958:958:958)) - (PORT datab (857:857:857) (996:996:996)) - (PORT datac (1182:1182:1182) (1381:1381:1381)) - (PORT datad (1318:1318:1318) (1527:1527:1527)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (853:853:853)) - (PORT datab (672:672:672) (805:805:805)) - (PORT datac (841:841:841) (978:978:978)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (412:412:412)) - (PORT datab (475:475:475) (547:547:547)) - (PORT datac (699:699:699) (808:808:808)) - (PORT datad (592:592:592) (685:685:685)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (661:661:661)) - (PORT datab (723:723:723) (834:834:834)) - (PORT datac (306:306:306) (356:356:356)) - (PORT datad (283:283:283) (326:326:326)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1149:1149:1149)) - (PORT datab (1223:1223:1223) (1437:1437:1437)) - (PORT datac (913:913:913) (1048:1048:1048)) - (PORT datad (466:466:466) (545:545:545)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (471:471:471) (534:534:534)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (299:299:299) (344:344:344)) - (PORT datab (433:433:433) (504:504:504)) - (PORT datac (716:716:716) (834:834:834)) - (PORT datad (592:592:592) (686:686:686)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (943:943:943)) - (PORT datab (630:630:630) (752:752:752)) - (PORT datac (634:634:634) (762:762:762)) - (PORT datad (924:924:924) (1069:1069:1069)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (720:720:720)) - (PORT datab (575:575:575) (666:666:666)) - (PORT datac (625:625:625) (753:753:753)) - (PORT datad (571:571:571) (661:661:661)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (985:985:985)) - (PORT datab (735:735:735) (878:878:878)) - (PORT datac (321:321:321) (379:379:379)) - (PORT datad (727:727:727) (848:848:848)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (491:491:491) (571:571:571)) - (PORT datac (480:480:480) (556:556:556)) - (PORT datad (355:355:355) (410:410:410)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) - (DELAY - (ABSOLUTE - (PORT datab (830:830:830) (985:985:985)) - (PORT datac (769:769:769) (901:901:901)) - (PORT datad (752:752:752) (863:863:863)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -9779,205 +10750,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) (DELAY (ABSOLUTE - (PORT dataa (785:785:785) (917:917:917)) - (PORT datab (1215:1215:1215) (1428:1428:1428)) - (PORT datac (917:917:917) (1053:1053:1053)) - (PORT datad (100:100:100) (121:121:121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (805:805:805)) - (PORT datab (782:782:782) (909:909:909)) - (PORT datac (755:755:755) (885:885:885)) - (PORT datad (114:114:114) (136:136:136)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (883:883:883)) - (PORT datab (292:292:292) (341:341:341)) - (PORT datac (645:645:645) (774:774:774)) - (PORT datad (102:102:102) (125:125:125)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (733:733:733)) - (PORT datab (623:623:623) (733:733:733)) - (PORT datac (321:321:321) (379:379:379)) - (PORT datad (768:768:768) (874:874:874)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (808:808:808)) - (PORT datab (360:360:360) (425:425:425)) - (PORT datac (624:624:624) (727:727:727)) - (PORT datad (609:609:609) (698:698:698)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (280:280:280) (329:329:329)) - (PORT datab (469:469:469) (546:546:546)) - (PORT datac (317:317:317) (371:371:371)) - (PORT datad (479:479:479) (557:557:557)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (296:296:296) (352:352:352)) - (PORT datab (321:321:321) (379:379:379)) - (PORT datac (288:288:288) (328:328:328)) - (PORT datad (284:284:284) (327:327:327)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (308:308:308) (364:364:364)) - (PORT datab (368:368:368) (428:428:428)) - (PORT datac (490:490:490) (567:567:567)) - (PORT datad (101:101:101) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (306:306:306) (354:354:354)) - (PORT datab (321:321:321) (373:373:373)) - (PORT datac (171:171:171) (196:196:196)) - (PORT datad (696:696:696) (789:789:789)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (149:149:149)) - (PORT datab (477:477:477) (553:553:553)) - (PORT datac (102:102:102) (124:124:124)) - (PORT datad (1555:1555:1555) (1775:1775:1775)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (293:293:293) (337:337:337)) - (PORT datab (282:282:282) (328:328:328)) - (PORT datac (331:331:331) (391:391:391)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (765:765:765)) - (PORT datab (583:583:583) (689:689:689)) - (PORT datac (566:566:566) (667:667:667)) - (PORT datad (561:561:561) (645:645:645)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (454:454:454) (531:531:531)) - (PORT datab (784:784:784) (896:896:896)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (732:732:732) (833:833:833)) + (PORT dataa (604:604:604) (693:693:693)) + (PORT datab (347:347:347) (408:408:408)) + (PORT datac (462:462:462) (532:532:532)) + (PORT datad (481:481:481) (559:559:559)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -9985,797 +10764,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (709:709:709)) - (PORT datab (503:503:503) (593:593:593)) - (PORT datac (1110:1110:1110) (1279:1279:1279)) - (PORT datad (667:667:667) (764:764:764)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (472:472:472)) - (PORT datab (125:125:125) (157:157:157)) - (PORT datad (151:151:151) (195:195:195)) - (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (182:182:182) (193:193:193)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (896:896:896)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (358:358:358) (427:427:427)) - (PORT datad (337:337:337) (393:393:393)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (958:958:958)) - (PORT datab (1187:1187:1187) (1380:1380:1380)) - (PORT datac (891:891:891) (1033:1033:1033)) - (PORT datad (951:951:951) (1124:1124:1124)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (264:264:264)) - (PORT datab (164:164:164) (221:221:221)) - (PORT datac (459:459:459) (531:531:531)) - (PORT datad (101:101:101) (124:124:124)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (1008:1008:1008) (1177:1177:1177)) - (PORT datac (584:584:584) (666:666:666)) - (PORT datad (897:897:897) (1033:1033:1033)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (262:262:262)) - (PORT datab (162:162:162) (217:217:217)) - (PORT datac (463:463:463) (534:534:534)) - (PORT datad (104:104:104) (127:127:127)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT dataa (745:745:745) (858:858:858)) - (PORT datac (752:752:752) (868:868:868)) - (PORT datad (865:865:865) (988:988:988)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT asdata (814:814:814) (908:908:908)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (588:588:588) (680:680:680)) - (PORT datac (992:992:992) (1159:1159:1159)) - (PORT datad (896:896:896) (1033:1033:1033)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (474:474:474)) - (PORT datab (127:127:127) (161:161:161)) - (PORT datad (152:152:152) (200:200:200)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (161:161:161) (174:174:174)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (896:896:896)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (135:135:135) (186:186:186)) - (PORT datab (164:164:164) (221:221:221)) - (PORT datac (458:458:458) (530:530:530)) - (PORT datad (100:100:100) (123:123:123)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (746:746:746) (860:860:860)) - (PORT datac (748:748:748) (862:862:862)) - (PORT datad (1023:1023:1023) (1177:1177:1177)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT asdata (817:817:817) (911:911:911)) - (PORT ena (518:518:518) (563:563:563)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (862:862:862)) - (PORT datac (751:751:751) (867:867:867)) - (PORT datad (865:865:865) (988:988:988)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datab (385:385:385) (460:460:460)) - (PORT datad (121:121:121) (144:144:144)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) - (DELAY - (ABSOLUTE - (PORT datab (1006:1006:1006) (1174:1174:1174)) - (PORT datac (585:585:585) (667:667:667)) - (PORT datad (897:897:897) (1034:1034:1034)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (650:650:650) (717:717:717)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (135:135:135) (186:186:186)) - (PORT datab (164:164:164) (221:221:221)) - (PORT datac (459:459:459) (530:530:530)) - (PORT datad (101:101:101) (124:124:124)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (681:681:681)) - (PORT datab (938:938:938) (1083:1083:1083)) - (PORT datad (901:901:901) (1041:1041:1041)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (646:646:646) (712:712:712)) - (PORT ena (422:422:422) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[7\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (686:686:686)) - (PORT datab (943:943:943) (1089:1089:1089)) - (PORT datad (899:899:899) (1039:1039:1039)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (273:273:273)) - (PORT datab (351:351:351) (419:419:419)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT datab (770:770:770) (889:889:889)) - (PORT datac (660:660:660) (769:769:769)) - (PORT datad (1021:1021:1021) (1174:1174:1174)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (665:665:665) (721:721:721)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) - (DELAY - (ABSOLUTE - (PORT datac (914:914:914) (1057:1057:1057)) - (PORT datad (615:615:615) (722:722:722)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (642:642:642)) - (PORT datab (687:687:687) (823:823:823)) - (PORT datac (876:876:876) (1057:1057:1057)) - (PORT datad (105:105:105) (129:129:129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (503:503:503) (550:550:550)) - (PORT ena (494:494:494) (536:536:536)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (643:643:643)) - (PORT datab (688:688:688) (824:824:824)) - (PORT datac (876:876:876) (1057:1057:1057)) - (PORT datad (105:105:105) (129:129:129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (498:498:498) (539:539:539)) - (PORT ena (794:794:794) (877:877:877)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (285:285:285)) - (PORT datab (223:223:223) (271:271:271)) - (PORT datad (337:337:337) (405:405:405)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (715:715:715) (816:816:816)) - (PORT datab (613:613:613) (711:711:711)) - (PORT datac (457:457:457) (533:533:533)) - (PORT datad (289:289:289) (339:339:339)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (148:148:148)) - (PORT datab (372:372:372) (436:436:436)) - (PORT datac (473:473:473) (563:563:563)) - (PORT datad (600:600:600) (688:688:688)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (451:451:451)) - (PORT datab (320:320:320) (369:369:369)) - (PORT datac (562:562:562) (641:641:641)) - (PORT datad (331:331:331) (385:385:385)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (725:725:725) (847:847:847)) - (PORT datab (695:695:695) (838:838:838)) - (PORT datac (566:566:566) (640:640:640)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (456:456:456) (525:525:525)) - (PORT datab (310:310:310) (363:363:363)) - (PORT datac (186:186:186) (226:226:226)) - (PORT datad (293:293:293) (335:335:335)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (177:177:177) (211:211:211)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (188:188:188) (226:226:226)) - (PORT datac (106:106:106) (131:131:131)) - (PORT datad (556:556:556) (623:623:623)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (961:961:961) (1119:1119:1119)) - (PORT datab (588:588:588) (678:678:678)) - (PORT datad (903:903:903) (1045:1045:1045)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (498:498:498) (539:539:539)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (811:811:811)) - (PORT datab (575:575:575) (678:678:678)) - (PORT datad (203:203:203) (235:235:235)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (754:754:754)) - (PORT datac (909:909:909) (1051:1051:1051)) - (PORT datad (107:107:107) (126:126:126)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (805:805:805) (901:901:901)) - (PORT ena (631:631:631) (678:678:678)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (764:764:764)) - (PORT datab (114:114:114) (148:148:148)) - (PORT datac (968:968:968) (1119:1119:1119)) - (PORT datad (417:417:417) (483:483:483)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (808:808:808) (904:904:904)) - (PORT ena (649:649:649) (709:709:709)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (761:761:761)) - (PORT datab (431:431:431) (501:501:501)) - (PORT datac (970:970:970) (1120:1120:1120)) - (PORT datad (482:482:482) (546:546:546)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (277:277:277)) - (PORT datab (344:344:344) (397:397:397)) - (PORT datad (328:328:328) (373:373:373)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) (DELAY (ABSOLUTE - (PORT dataa (667:667:667) (762:762:762)) - (PORT datab (362:362:362) (425:425:425)) - (PORT datac (274:274:274) (319:319:319)) - (PORT datad (617:617:617) (715:715:715)) + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (345:345:345) (407:407:407)) + (PORT datac (773:773:773) (892:892:892)) + (PORT datad (627:627:627) (723:723:723)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (536:536:536)) - (PORT datab (122:122:122) (153:153:153)) - (PORT datac (629:629:629) (727:727:727)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (544:544:544)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (327:327:327) (385:385:385)) - (PORT datad (775:775:775) (888:888:888)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -10783,124 +10782,150 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) (DELAY (ABSOLUTE - (PORT dataa (489:489:489) (584:584:584)) - (PORT datac (1135:1135:1135) (1301:1301:1301)) - (PORT datad (1131:1131:1131) (1281:1281:1281)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (920:920:920) (1084:1084:1084)) + (PORT datab (563:563:563) (663:663:663)) + (PORT datac (1072:1072:1072) (1218:1218:1218)) + (PORT datad (906:906:906) (1050:1050:1050)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (547:547:547)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (586:586:586) (676:676:676)) - (PORT datad (617:617:617) (713:713:713)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (233:233:233)) - (PORT datab (626:626:626) (732:732:732)) - (PORT datac (460:460:460) (536:536:536)) - (PORT datad (332:332:332) (387:387:387)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (229:229:229)) - (PORT datab (382:382:382) (446:446:446)) - (PORT datac (880:880:880) (1007:1007:1007)) - (PORT datad (874:874:874) (1007:1007:1007)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~39) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (648:648:648)) - (PORT datab (197:197:197) (239:239:239)) - (PORT datac (629:629:629) (719:719:719)) - (PORT datad (510:510:510) (594:594:594)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (530:530:530)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (747:747:747) (863:863:863)) - (PORT datad (345:345:345) (405:405:405)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (699:699:699)) - (PORT datab (490:490:490) (569:569:569)) - (PORT datac (693:693:693) (789:789:789)) - (PORT datad (664:664:664) (750:750:750)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) (DELAY (ABSOLUTE - (PORT dataa (461:461:461) (534:534:534)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (357:357:357) (419:419:419)) - (PORT datad (457:457:457) (527:527:527)) + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (364:364:364) (431:431:431)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (154:154:154)) + (PORT datab (342:342:342) (402:402:402)) + (PORT datac (106:106:106) (128:128:128)) + (PORT datad (657:657:657) (748:748:748)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (580:580:580) (687:687:687)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (331:331:331) (385:385:385)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (DELAY + (ABSOLUTE + (PORT dataa (509:509:509) (599:599:599)) + (PORT datab (622:622:622) (721:721:721)) + (PORT datac (480:480:480) (563:563:563)) + (PORT datad (634:634:634) (736:736:736)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) + (DELAY + (ABSOLUTE + (PORT datab (114:114:114) (141:141:141)) + (PORT datac (335:335:335) (393:393:393)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (147:147:147)) + (PORT datac (286:286:286) (335:335:335)) + (PORT datad (478:478:478) (567:567:567)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (873:873:873)) + (PORT datab (362:362:362) (420:420:420)) + (PORT datac (104:104:104) (125:125:125)) + (PORT datad (634:634:634) (743:743:743)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (338:338:338)) + (PORT datac (450:450:450) (537:537:537)) + (PORT datad (442:442:442) (526:526:526)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (570:570:570)) + (PORT datab (363:363:363) (428:428:428)) + (PORT datac (196:196:196) (235:235:235)) + (PORT datad (335:335:335) (388:388:388)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -10909,15 +10934,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (INSTANCE z80_\|execute_\|setM1\~45) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (244:244:244)) - (PORT datab (436:436:436) (506:506:506)) - (PORT datac (176:176:176) (213:213:213)) - (PORT datad (452:452:452) (521:521:521)) + (PORT dataa (347:347:347) (416:416:416)) + (PORT datab (456:456:456) (527:527:527)) + (PORT datac (482:482:482) (553:553:553)) + (PORT datad (351:351:351) (418:418:418)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~46) + (DELAY + (ABSOLUTE + (PORT datab (438:438:438) (503:503:503)) + (PORT datac (105:105:105) (127:127:127)) + (PORT datad (821:821:821) (939:939:939)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -10925,92 +10964,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) (DELAY (ABSOLUTE - (PORT dataa (571:571:571) (658:658:658)) - (PORT datab (522:522:522) (603:603:603)) - (PORT datad (549:549:549) (627:627:627)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (503:503:503) (545:545:545)) - (PORT ena (767:767:767) (833:833:833)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (621:621:621)) - (PORT datab (690:690:690) (827:827:827)) - (PORT datac (541:541:541) (623:623:623)) - (PORT datad (103:103:103) (127:127:127)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (311:311:311) (357:357:357)) + (PORT datab (496:496:496) (585:585:585)) + (PORT datac (306:306:306) (346:346:346)) + (PORT datad (311:311:311) (363:363:363)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (505:505:505) (547:547:547)) - (PORT ena (774:774:774) (865:865:865)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (524:524:524) (599:599:599)) + (PORT datab (904:904:904) (1066:1066:1066)) + (PORT datac (466:466:466) (536:536:536)) + (PORT datad (198:198:198) (231:231:231)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~27) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) (DELAY (ABSOLUTE - (PORT dataa (237:237:237) (297:297:297)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (354:354:354) (415:415:415)) + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (177:177:177) (214:214:214)) + (PORT datac (114:114:114) (140:140:140)) + (PORT datad (91:91:91) (109:109:109)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (392:392:392)) - (PORT datab (190:190:190) (228:228:228)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (330:330:330) (383:383:383)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -11018,12 +11012,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_32) + (INSTANCE z80_\|execute_\|fMRead\~4) (DELAY (ABSOLUTE - (PORT dataa (635:635:635) (740:740:740)) - (PORT datac (944:944:944) (1096:1096:1096)) - (PORT datad (905:905:905) (1048:1048:1048)) + (PORT dataa (502:502:502) (586:586:586)) + (PORT datac (488:488:488) (572:572:572)) + (PORT datad (442:442:442) (507:507:507)) (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -11032,409 +11026,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~29) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) (DELAY (ABSOLUTE - (PORT dataa (323:323:323) (386:386:386)) - (PORT datab (130:130:130) (177:177:177)) - (PORT datac (91:91:91) (112:112:112)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (382:382:382)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (170:170:170) (207:207:207)) - (PORT datad (744:744:744) (875:875:875)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (469:469:469) (541:541:541)) - (PORT datab (313:313:313) (369:369:369)) - (PORT datac (546:546:546) (620:620:620)) - (PORT datad (751:751:751) (862:862:862)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (833:833:833)) - (PORT datab (141:141:141) (174:174:174)) - (PORT datac (483:483:483) (572:572:572)) - (PORT datad (426:426:426) (487:487:487)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (437:437:437)) - (PORT datab (489:489:489) (575:575:575)) - (PORT datac (307:307:307) (351:351:351)) - (PORT datad (697:697:697) (787:787:787)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1042:1042:1042) (1203:1203:1203)) - (PORT datab (117:117:117) (150:150:150)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (464:464:464) (541:541:541)) - (PORT datab (452:452:452) (532:532:532)) - (PORT datac (280:280:280) (327:327:327)) - (PORT datad (450:450:450) (513:513:513)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (719:719:719) (826:826:826)) - (PORT datab (400:400:400) (471:471:471)) - (PORT datac (695:695:695) (795:795:795)) - (PORT datad (448:448:448) (518:518:518)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT datab (667:667:667) (771:771:771)) - (PORT datad (447:447:447) (533:533:533)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (764:764:764)) - (PORT datab (964:964:964) (1113:1113:1113)) - (PORT datac (448:448:448) (516:516:516)) - (PORT datad (747:747:747) (869:869:869)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (793:793:793)) - (PORT datab (484:484:484) (572:572:572)) - (PORT datac (688:688:688) (797:797:797)) - (PORT datad (612:612:612) (707:707:707)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (811:811:811) (942:942:942)) - (PORT datab (364:364:364) (434:434:434)) - (PORT datac (621:621:621) (713:713:713)) - (PORT datad (160:160:160) (188:188:188)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (641:641:641)) - (PORT datab (354:354:354) (417:417:417)) - (PORT datac (454:454:454) (530:530:530)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (574:574:574) (663:663:663)) - (PORT datab (402:402:402) (484:484:484)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (105:105:105) (122:122:122)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (764:764:764) (886:886:886)) - (PORT datab (361:361:361) (418:418:418)) - (PORT datac (327:327:327) (388:388:388)) - (PORT datad (728:728:728) (833:833:833)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (569:569:569)) - (PORT datab (194:194:194) (234:234:234)) - (PORT datac (482:482:482) (558:558:558)) - (PORT datad (356:356:356) (412:412:412)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (762:762:762) (884:884:884)) - (PORT datab (584:584:584) (675:675:675)) - (PORT datac (678:678:678) (777:777:777)) - (PORT datad (703:703:703) (799:799:799)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (106:106:106) (137:137:137)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (326:326:326) (380:380:380)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (237:237:237)) - (PORT datab (443:443:443) (520:520:520)) - (PORT datac (841:841:841) (953:953:953)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (407:407:407)) - (PORT datab (109:109:109) (139:139:139)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (325:325:325) (380:380:380)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (571:571:571) (655:655:655)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (436:436:436) (497:497:497)) - (PORT datad (858:858:858) (961:961:961)) + (PORT dataa (344:344:344) (411:411:411)) + (PORT datab (835:835:835) (969:969:969)) + (PORT datac (450:450:450) (512:512:512)) + (PORT datad (458:458:458) (527:527:527)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (727:727:727) (856:856:856)) - (PORT datab (635:635:635) (748:748:748)) - (PORT datac (465:465:465) (525:525:525)) - (PORT datad (589:589:589) (673:673:673)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (726:726:726)) - (PORT datab (594:594:594) (688:688:688)) - (PORT datac (282:282:282) (326:326:326)) - (PORT datad (849:849:849) (974:974:974)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (588:588:588)) - (PORT datab (473:473:473) (546:546:546)) - (PORT datac (457:457:457) (528:528:528)) - (PORT datad (665:665:665) (770:770:770)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (847:847:847)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (321:321:321) (376:376:376)) - (PORT datad (335:335:335) (392:392:392)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) - (DELAY - (ABSOLUTE - (PORT datab (612:612:612) (712:712:712)) - (PORT datac (715:715:715) (834:834:834)) - (PORT datad (99:99:99) (122:122:122)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -11442,251 +11042,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) (DELAY (ABSOLUTE - (PORT dataa (719:719:719) (825:825:825)) - (PORT datab (285:285:285) (332:332:332)) - (PORT datac (438:438:438) (506:506:506)) - (PORT datad (450:450:450) (514:514:514)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (563:563:563)) - (PORT datab (374:374:374) (441:441:441)) - (PORT datac (562:562:562) (649:649:649)) - (PORT datad (436:436:436) (489:489:489)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (442:442:442)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (1216:1216:1216) (1390:1390:1390)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (290:290:290) (335:335:335)) - (PORT datac (94:94:94) (119:119:119)) - (PORT datad (343:343:343) (404:404:404)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (234:234:234)) - (PORT datab (119:119:119) (149:149:149)) - (PORT datac (476:476:476) (558:558:558)) - (PORT datad (420:420:420) (481:481:481)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (868:868:868)) - (PORT datab (320:320:320) (374:374:374)) - (PORT datac (870:870:870) (987:987:987)) - (PORT datad (744:744:744) (854:854:854)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (870:870:870)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (682:682:682) (805:805:805)) - (PORT datad (745:745:745) (855:855:855)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (947:947:947)) - (PORT datab (320:320:320) (373:373:373)) - (PORT datac (870:870:870) (988:988:988)) - (PORT datad (923:923:923) (1068:1068:1068)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (811:811:811) (949:949:949)) - (PORT datab (107:107:107) (136:136:136)) - (PORT datac (682:682:682) (805:805:805)) - (PORT datad (922:922:922) (1067:1067:1067)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT datab (955:955:955) (1108:1108:1108)) - (PORT datac (886:886:886) (1030:1030:1030)) - (PORT datad (750:750:750) (867:867:867)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (713:713:713)) - (PORT datab (373:373:373) (445:445:445)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (447:447:447) (515:515:515)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (418:418:418)) - (PORT datab (631:631:631) (735:735:735)) - (PORT datac (683:683:683) (784:784:784)) - (PORT datad (464:464:464) (539:539:539)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla83M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (538:538:538) (638:638:638)) - (PORT datab (783:783:783) (910:910:910)) - (PORT datac (681:681:681) (778:778:778)) - (PORT datad (112:112:112) (134:134:134)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1056:1056:1056) (1215:1215:1215)) - (PORT datab (851:851:851) (991:991:991)) - (PORT datac (765:765:765) (885:885:885)) - (PORT datad (295:295:295) (345:345:345)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (567:567:567)) - (PORT datab (742:742:742) (870:870:870)) - (PORT datac (739:739:739) (878:878:878)) - (PORT datad (651:651:651) (761:761:761)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (525:525:525)) - (PORT datab (358:358:358) (424:424:424)) - (PORT datac (322:322:322) (376:376:376)) - (PORT datad (553:553:553) (628:628:628)) + (PORT dataa (245:245:245) (295:295:295)) + (PORT datab (520:520:520) (602:602:602)) + (PORT datac (201:201:201) (234:234:234)) + (PORT datad (1100:1100:1100) (1292:1292:1292)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -11696,558 +11058,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) (DELAY (ABSOLUTE - (PORT dataa (473:473:473) (552:552:552)) - (PORT datab (463:463:463) (529:529:529)) - (PORT datac (384:384:384) (435:435:435)) - (PORT datad (574:574:574) (649:649:649)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (602:602:602)) - (PORT datab (710:710:710) (814:814:814)) - (PORT datac (961:961:961) (1083:1083:1083)) - (PORT datad (750:750:750) (863:863:863)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (871:871:871) (1008:1008:1008)) - (PORT datac (383:383:383) (435:435:435)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (496:496:496) (586:586:586)) - (PORT datab (640:640:640) (741:741:741)) - (PORT datac (439:439:439) (502:502:502)) - (PORT datad (918:918:918) (1055:1055:1055)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (991:991:991)) - (PORT datab (582:582:582) (666:666:666)) - (PORT datac (320:320:320) (378:378:378)) - (PORT datad (883:883:883) (1007:1007:1007)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (148:148:148)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (444:444:444) (508:508:508)) - (PORT datad (884:884:884) (1007:1007:1007)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (558:558:558)) - (PORT datac (439:439:439) (504:504:504)) - (PORT datad (569:569:569) (647:647:647)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (562:562:562)) - (PORT datab (583:583:583) (660:660:660)) - (PORT datac (440:440:440) (500:500:500)) - (PORT datad (354:354:354) (413:413:413)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1199:1199:1199) (1398:1398:1398)) - (PORT datab (795:795:795) (912:912:912)) - (PORT datac (809:809:809) (951:951:951)) - (PORT datad (1311:1311:1311) (1520:1520:1520)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (553:553:553)) - (PORT datab (362:362:362) (426:426:426)) - (PORT datac (896:896:896) (1014:1014:1014)) - (PORT datad (564:564:564) (640:640:640)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (727:727:727)) - (PORT datac (604:604:604) (696:696:696)) - (PORT datad (489:489:489) (576:576:576)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (727:727:727)) - (PORT datad (490:490:490) (576:576:576)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (665:665:665) (721:721:721)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (800:800:800) (891:891:891)) - (PORT ena (422:422:422) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (683:683:683)) - (PORT datab (940:940:940) (1085:1085:1085)) - (PORT datad (900:900:900) (1041:1041:1041)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (800:800:800) (890:890:890)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT asdata (528:528:528) (595:595:595)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT asdata (527:527:527) (594:594:594)) - (PORT ena (518:518:518) (563:563:563)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (262:262:262)) - (PORT datab (386:386:386) (461:461:461)) - (PORT datad (123:123:123) (145:145:145)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (274:274:274)) - (PORT datab (172:172:172) (210:210:210)) - (PORT datad (338:338:338) (394:394:394)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (769:769:769) (862:862:862)) - (PORT ena (631:631:631) (678:678:678)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (772:772:772) (864:864:864)) - (PORT ena (649:649:649) (709:709:709)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (405:405:405)) - (PORT datab (130:130:130) (178:178:178)) - (PORT datad (331:331:331) (377:377:377)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (622:622:622) (686:686:686)) - (PORT ena (494:494:494) (536:536:536)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (621:621:621) (684:684:684)) - (PORT ena (504:504:504) (535:535:535)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (277:277:277)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (491:491:491) (542:542:542)) - (PORT ena (774:774:774) (865:865:865)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (491:491:491) (542:542:542)) - (PORT ena (767:767:767) (833:833:833)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (234:234:234) (293:293:293)) - (PORT datab (370:370:370) (440:440:440)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (780:780:780) (873:873:873)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (809:809:809)) - (PORT datab (488:488:488) (573:573:573)) - (PORT datad (203:203:203) (235:235:235)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (173:173:173) (210:210:210)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (321:321:321) (377:377:377)) - (PORT datad (315:315:315) (366:366:366)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (336:336:336) (396:396:396)) - (PORT datac (455:455:455) (524:524:524)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (468:468:468) (546:546:546)) - (PORT datab (337:337:337) (404:404:404)) - (PORT datac (1059:1059:1059) (1214:1214:1214)) - (PORT datad (292:292:292) (334:334:334)) + (PORT dataa (1449:1449:1449) (1724:1724:1724)) + (PORT datab (289:289:289) (333:333:333)) + (PORT datac (486:486:486) (560:560:560)) + (PORT datad (633:633:633) (727:727:727)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -12260,39 +11077,13 @@ (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) (DELAY (ABSOLUTE - (PORT datac (693:693:693) (789:789:789)) - (PORT datad (589:589:589) (671:671:671)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (548:548:548)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (472:472:472) (550:550:550)) - (PORT datad (167:167:167) (196:196:196)) + (PORT dataa (348:348:348) (419:419:419)) + (PORT datab (306:306:306) (354:354:354)) + (PORT datac (444:444:444) (524:524:524)) + (PORT datad (108:108:108) (126:126:126)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) - (DELAY - (ABSOLUTE - (PORT datab (115:115:115) (147:147:147)) - (PORT datac (633:633:633) (732:732:732)) - (PORT datad (448:448:448) (521:521:521)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -12302,12 +11093,28 @@ (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) (DELAY (ABSOLUTE - (PORT dataa (401:401:401) (477:477:477)) - (PORT datab (465:465:465) (536:536:536)) - (PORT datac (440:440:440) (505:505:505)) - (PORT datad (326:326:326) (378:378:378)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (308:308:308) (363:363:363)) + (PORT datab (477:477:477) (554:554:554)) + (PORT datac (1115:1115:1115) (1290:1290:1290)) + (PORT datad (318:318:318) (364:364:364)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (715:715:715)) + (PORT datab (900:900:900) (1058:1058:1058)) + (PORT datac (353:353:353) (417:417:417)) + (PORT datad (336:336:336) (386:386:386)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -12318,10 +11125,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) (DELAY (ABSOLUTE - (PORT dataa (459:459:459) (534:534:534)) - (PORT datab (405:405:405) (460:460:460)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (90:90:90) (106:106:106)) + (PORT dataa (481:481:481) (561:561:561)) + (PORT datab (298:298:298) (343:343:343)) + (PORT datac (338:338:338) (390:390:390)) + (PORT datad (91:91:91) (109:109:109)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -12329,34 +11136,18 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (471:471:471) (554:554:554)) - (PORT datab (535:535:535) (643:643:643)) - (PORT datac (724:724:724) (850:850:850)) - (PORT datad (290:290:290) (340:340:340)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) (DELAY (ABSOLUTE - (PORT dataa (484:484:484) (556:556:556)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (347:347:347) (413:413:413)) - (PORT datad (603:603:603) (689:689:689)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (346:346:346) (413:413:413)) + (PORT datab (515:515:515) (604:604:604)) + (PORT datac (273:273:273) (312:312:312)) + (PORT datad (477:477:477) (558:558:558)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -12364,1027 +11155,14 @@ (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (467:467:467) (535:535:535)) - (PORT datac (1160:1160:1160) (1300:1300:1300)) - (PORT datad (589:589:589) (672:672:672)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) - (DELAY - (ABSOLUTE - (PORT datab (669:669:669) (788:788:788)) - (PORT datac (547:547:547) (625:625:625)) - (PORT datad (932:932:932) (1074:1074:1074)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (784:784:784)) - (PORT datac (753:753:753) (883:883:883)) - (PORT datad (1095:1095:1095) (1274:1274:1274)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) (DELAY (ABSOLUTE (PORT dataa (121:121:121) (153:153:153)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (458:458:458) (532:532:532)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) - (DELAY - (ABSOLUTE - (PORT datab (566:566:566) (654:654:654)) - (PORT datac (548:548:548) (626:626:626)) - (PORT datad (652:652:652) (766:766:766)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (505:505:505)) - (PORT datab (285:285:285) (329:329:329)) - (PORT datac (357:357:357) (426:426:426)) - (PORT datad (1069:1069:1069) (1233:1233:1233)) + (PORT datab (351:351:351) (414:414:414)) + (PORT datac (452:452:452) (520:520:520)) + (PORT datad (175:175:175) (207:207:207)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (435:435:435) (506:506:506)) - (PORT datad (451:451:451) (520:520:520)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (823:823:823)) - (PORT datab (422:422:422) (510:510:510)) - (PORT datac (721:721:721) (828:828:828)) - (PORT datad (447:447:447) (519:519:519)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (829:829:829)) - (PORT datab (350:350:350) (420:420:420)) - (PORT datac (352:352:352) (419:419:419)) - (PORT datad (477:477:477) (550:550:550)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1114:1114:1114)) - (PORT datab (356:356:356) (420:420:420)) - (PORT datac (288:288:288) (333:333:333)) - (PORT datad (562:562:562) (643:643:643)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (1034:1034:1034)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (476:476:476) (564:564:564)) - (PORT datad (549:549:549) (626:626:626)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT datab (464:464:464) (536:536:536)) - (PORT datac (183:183:183) (212:212:212)) - (PORT datad (163:163:163) (190:190:190)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (443:443:443) (508:508:508)) - (PORT datad (93:93:93) (113:113:113)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (336:336:336) (389:389:389)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (102:102:102) (120:120:120)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (725:725:725)) - (PORT datab (673:673:673) (790:790:790)) - (PORT datac (673:673:673) (789:789:789)) - (PORT datad (675:675:675) (768:768:768)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT datab (565:565:565) (653:653:653)) - (PORT datac (548:548:548) (626:626:626)) - (PORT datad (651:651:651) (765:765:765)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (915:915:915)) - (PORT asdata (455:455:455) (494:494:494)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (142:142:142) (188:188:188)) - (PORT datab (534:534:534) (648:648:648)) - (PORT datad (333:333:333) (387:387:387)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) - (DELAY - (ABSOLUTE - (PORT datab (669:669:669) (789:789:789)) - (PORT datac (548:548:548) (626:626:626)) - (PORT datad (932:932:932) (1074:1074:1074)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (505:505:505) (546:546:546)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (238:238:238) (284:284:284)) - (PORT datac (161:161:161) (188:188:188)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[11\]) - (DELAY - (ABSOLUTE - (PORT datac (866:866:866) (1017:1017:1017)) - (PORT datad (344:344:344) (402:402:402)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (495:495:495) (580:580:580)) - (PORT datab (475:475:475) (552:552:552)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (335:335:335) (395:395:395)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (478:478:478) (561:561:561)) - (PORT datac (904:904:904) (1026:1026:1026)) - (PORT datad (873:873:873) (992:992:992)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (804:804:804)) - (PORT datab (895:895:895) (1051:1051:1051)) - (PORT datad (506:506:506) (600:600:600)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (444:444:444)) - (PORT datab (343:343:343) (405:405:405)) - (PORT datac (336:336:336) (393:393:393)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (311:311:311) (359:359:359)) - (PORT datab (504:504:504) (591:591:591)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (96:96:96) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (231:231:231)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (450:450:450) (514:514:514)) - (PORT datad (399:399:399) (454:454:454)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (352:352:352) (414:414:414)) - (PORT datad (173:173:173) (205:205:205)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (528:528:528) (619:619:619)) - (PORT datab (548:548:548) (640:640:640)) - (PORT datac (715:715:715) (821:821:821)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (905:905:905) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (892:892:892)) - (PORT ena (1352:1352:1352) (1505:1505:1505)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) - (DELAY - (ABSOLUTE - (PORT datab (254:254:254) (318:318:318)) - (PORT datad (280:280:280) (324:324:324)) - (IOPATH datab combout (192:192:192) (181:181:181)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (681:681:681)) - (PORT datab (129:129:129) (158:158:158)) - (PORT datac (275:275:275) (310:310:310)) - (PORT datad (112:112:112) (133:133:133)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (148:148:148)) - (PORT datab (351:351:351) (406:406:406)) - (PORT datac (422:422:422) (484:484:484)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (459:459:459) (528:528:528)) - (PORT datac (325:325:325) (373:373:373)) - (PORT datad (457:457:457) (529:529:529)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (529:529:529)) - (PORT datab (900:900:900) (1024:1024:1024)) - (PORT datac (428:428:428) (484:484:484)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (438:438:438)) - (PORT datab (638:638:638) (752:752:752)) - (PORT datac (715:715:715) (829:829:829)) - (PORT datad (655:655:655) (757:757:757)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (395:395:395)) - (PORT datab (639:639:639) (742:742:742)) - (PORT datac (279:279:279) (327:327:327)) - (PORT datad (282:282:282) (324:324:324)) - (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (742:742:742) (843:843:843)) - (PORT datac (1110:1110:1110) (1278:1278:1278)) - (PORT datad (327:327:327) (376:376:376)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (422:422:422)) - (PORT datab (493:493:493) (592:592:592)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (488:488:488) (580:580:580)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (688:688:688)) - (PORT datab (477:477:477) (555:555:555)) - (PORT datac (1110:1110:1110) (1278:1278:1278)) - (PORT datad (622:622:622) (715:715:715)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (272:272:272) (316:316:316)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (526:526:526)) - (PORT datab (469:469:469) (544:544:544)) - (PORT datac (426:426:426) (483:483:483)) - (PORT datad (702:702:702) (802:802:802)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (145:145:145) (192:192:192)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (802:802:802) (953:953:953)) - (PORT datad (507:507:507) (613:613:613)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (512:512:512) (591:591:591)) - (PORT datac (964:964:964) (1144:1144:1144)) - (PORT datad (190:190:190) (224:224:224)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (316:316:316) (375:375:375)) - (PORT datac (170:170:170) (207:207:207)) - (PORT datad (744:744:744) (875:875:875)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (552:552:552)) - (PORT datab (625:625:625) (736:736:736)) - (PORT datac (457:457:457) (525:525:525)) - (PORT datad (458:458:458) (527:527:527)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (698:698:698)) - (PORT datab (343:343:343) (403:403:403)) - (PORT datac (578:578:578) (667:667:667)) - (PORT datad (579:579:579) (657:657:657)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (862:862:862)) - (PORT datab (442:442:442) (509:509:509)) - (PORT datac (734:734:734) (855:855:855)) - (PORT datad (334:334:334) (393:393:393)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (138:138:138) (176:176:176)) - (PORT datab (603:603:603) (702:702:702)) - (PORT datac (205:205:205) (247:247:247)) - (PORT datad (324:324:324) (381:381:381)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT datab (648:648:648) (771:771:771)) - (PORT datac (648:648:648) (778:778:778)) - (PORT datad (635:635:635) (756:756:756)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (116:116:116) (149:149:149)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (526:526:526) (614:614:614)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datab (370:370:370) (434:434:434)) - (PORT datac (426:426:426) (494:494:494)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (451:451:451) (522:522:522)) - (PORT datab (131:131:131) (160:160:160)) - (PORT datac (434:434:434) (498:498:498)) - (PORT datad (433:433:433) (499:499:499)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (485:485:485) (566:566:566)) - (PORT datab (466:466:466) (545:545:545)) - (PORT datac (268:268:268) (306:306:306)) - (PORT datad (450:450:450) (520:520:520)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (121:121:121) (152:152:152)) - (PORT datac (279:279:279) (314:314:314)) - (PORT datad (168:168:168) (199:199:199)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (310:310:310) (362:362:362)) - (PORT datab (287:287:287) (335:335:335)) - (PORT datac (365:365:365) (436:436:436)) - (PORT datad (300:300:300) (352:352:352)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (722:722:722)) - (PORT datab (509:509:509) (606:606:606)) - (PORT datac (920:920:920) (1029:1029:1029)) - (PORT datad (661:661:661) (747:747:747)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (929:929:929) (1068:1068:1068)) - (PORT datac (332:332:332) (398:398:398)) - (PORT datad (176:176:176) (209:209:209)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (795:795:795)) - (PORT datab (624:624:624) (741:741:741)) - (PORT datac (427:427:427) (499:499:499)) - (PORT datad (289:289:289) (337:337:337)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (478:478:478) (561:561:561)) - (PORT datab (694:694:694) (837:837:837)) - (PORT datac (566:566:566) (641:641:641)) - (PORT datad (701:701:701) (818:818:818)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (617:617:617) (701:701:701)) - (PORT datad (1727:1727:1727) (1962:1962:1962)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (585:585:585)) - (PORT datab (117:117:117) (145:145:145)) - (PORT datac (721:721:721) (847:847:847)) - (PORT datad (715:715:715) (836:836:836)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (630:630:630)) - (PORT datab (301:301:301) (346:346:346)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (726:726:726)) - (PORT datac (664:664:664) (779:779:779)) - (PORT datad (767:767:767) (885:885:885)) - (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13395,10 +11173,10 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) (DELAY (ABSOLUTE - (PORT datab (687:687:687) (803:803:803)) - (PORT datac (687:687:687) (785:785:785)) - (PORT datad (769:769:769) (887:887:887)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datab (803:803:803) (941:941:941)) + (PORT datac (498:498:498) (577:577:577)) + (PORT datad (435:435:435) (504:504:504)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13409,10 +11187,10 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (782:782:782)) - (PORT datab (821:821:821) (986:986:986)) - (PORT datac (248:248:248) (291:291:291)) - (PORT datad (215:215:215) (248:248:248)) + (PORT dataa (121:121:121) (154:154:154)) + (PORT datab (714:714:714) (816:816:816)) + (PORT datac (757:757:757) (868:868:868)) + (PORT datad (162:162:162) (189:189:189)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -13425,9 +11203,9 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) (DELAY (ABSOLUTE - (PORT datab (685:685:685) (802:802:802)) - (PORT datac (686:686:686) (785:785:785)) - (PORT datad (768:768:768) (887:887:887)) + (PORT datab (518:518:518) (608:608:608)) + (PORT datac (803:803:803) (934:934:934)) + (PORT datad (358:358:358) (423:423:423)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13436,12 +11214,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (380:380:380) (416:416:416)) - (PORT ena (420:420:420) (440:440:440)) + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (529:529:529) (593:593:593)) + (PORT ena (636:636:636) (682:682:682)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -13452,12 +11230,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) (DELAY (ABSOLUTE - (PORT dataa (805:805:805) (919:919:919)) - (PORT datab (130:130:130) (164:164:164)) - (PORT datad (675:675:675) (768:768:768)) + (PORT dataa (1037:1037:1037) (1192:1192:1192)) + (PORT datab (385:385:385) (456:456:456)) + (PORT datad (662:662:662) (772:772:772)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -13470,10 +11248,10 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) (DELAY (ABSOLUTE - (PORT dataa (627:627:627) (727:727:727)) - (PORT datac (667:667:667) (783:783:783)) - (PORT datad (768:768:768) (887:887:887)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT datab (377:377:377) (447:447:447)) + (PORT datac (570:570:570) (655:655:655)) + (PORT datad (503:503:503) (584:584:584)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13481,12 +11259,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) + (PORT clk (920:920:920) (927:927:927)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (530:530:530) (580:580:580)) + (PORT ena (679:679:679) (746:746:746)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -13497,18 +11275,1564 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) (DELAY (ABSOLUTE - (PORT datab (196:196:196) (238:238:238)) - (PORT datac (242:242:242) (285:285:285)) - (PORT datad (119:119:119) (156:156:156)) + (PORT datab (404:404:404) (479:479:479)) + (PORT datac (339:339:339) (398:398:398)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT datac (1107:1107:1107) (1285:1285:1285)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (932:932:932) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (932:932:932) (916:916:916)) + (PORT asdata (300:300:300) (342:342:342)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (932:932:932) (916:916:916)) + (PORT asdata (301:301:301) (343:343:343)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE KEY\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (705:705:705)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE reset) + (DELAY + (ABSOLUTE + (PORT datac (981:981:981) (856:856:856)) + (PORT datad (284:284:284) (306:306:306)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x1\~0) + (DELAY + (ABSOLUTE + (PORT datad (827:827:827) (963:963:963)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|fpga_reset) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|fpga_reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (391:391:391) (424:424:424)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|x1) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (1092:1092:1092) (1064:1064:1064)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc_int\~0) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (418:418:418)) + (PORT datab (321:321:321) (386:386:386)) + (PORT datad (642:642:642) (749:749:749)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|clrpc_int) + (DELAY + (ABSOLUTE + (PORT clk (932:932:932) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (928:928:928) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (187:187:187)) + (PORT datab (138:138:138) (189:189:189)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[7\]) + (DELAY + (ABSOLUTE + (PORT datac (362:362:362) (425:425:425)) + (PORT datad (330:330:330) (387:387:387)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1449:1449:1449) (1725:1725:1725)) + (PORT datac (486:486:486) (561:561:561)) + (PORT datad (1109:1109:1109) (1285:1285:1285)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (224:224:224)) + (PORT datab (294:294:294) (338:338:338)) + (PORT datac (468:468:468) (539:539:539)) + (PORT datad (632:632:632) (726:726:726)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (701:701:701)) + (PORT datab (633:633:633) (735:735:735)) + (PORT datac (425:425:425) (483:483:483)) + (PORT datad (341:341:341) (396:396:396)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (652:652:652)) + (PORT datab (908:908:908) (1030:1030:1030)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (638:638:638) (733:733:733)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (796:796:796)) + (PORT datab (556:556:556) (665:665:665)) + (PORT datac (373:373:373) (440:440:440)) + (PORT datad (717:717:717) (834:834:834)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (476:476:476)) + (PORT datab (346:346:346) (408:408:408)) + (PORT datac (473:473:473) (541:541:541)) + (PORT datad (592:592:592) (693:693:693)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (387:387:387) (450:450:450)) + (PORT datac (106:106:106) (129:129:129)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (287:287:287) (329:329:329)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (827:827:827)) + (PORT datab (440:440:440) (506:506:506)) + (PORT datac (439:439:439) (501:501:501)) + (PORT datad (477:477:477) (554:554:554)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (920:920:920) (904:904:904)) + (PORT ena (1159:1159:1159) (1318:1318:1318)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (248:248:248)) + (PORT datab (1010:1010:1010) (1167:1167:1167)) + (PORT datac (107:107:107) (131:131:131)) + (PORT datad (358:358:358) (422:422:422)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (781:781:781)) + (PORT datab (1128:1128:1128) (1312:1312:1312)) + (PORT datac (739:739:739) (880:880:880)) + (PORT datad (1144:1144:1144) (1338:1338:1338)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (234:234:234)) + (PORT datab (114:114:114) (146:146:146)) + (PORT datac (607:607:607) (700:700:700)) + (PORT datad (666:666:666) (759:759:759)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (144:144:144)) + (PORT datab (957:957:957) (1115:1115:1115)) + (PORT datac (290:290:290) (329:329:329)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) + (DELAY + (ABSOLUTE + (PORT datab (548:548:548) (641:641:641)) + (PORT datac (607:607:607) (700:700:700)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (659:659:659)) + (PORT datad (620:620:620) (707:707:707)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (679:679:679) (746:746:746)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (DELAY + (ABSOLUTE + (PORT datab (865:865:865) (1006:1006:1006)) + (PORT datac (667:667:667) (775:775:775)) + (PORT datad (578:578:578) (662:662:662)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) + (DELAY + (ABSOLUTE + (PORT datab (863:863:863) (1004:1004:1004)) + (PORT datac (675:675:675) (784:784:784)) + (PORT datad (548:548:548) (645:645:645)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (DELAY + (ABSOLUTE + (PORT datab (862:862:862) (1004:1004:1004)) + (PORT datac (677:677:677) (786:786:786)) + (PORT datad (577:577:577) (661:661:661)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (761:761:761) (846:846:846)) + (PORT ena (915:915:915) (1002:1002:1002)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT datab (866:866:866) (1008:1008:1008)) + (PORT datac (664:664:664) (771:771:771)) + (PORT datad (552:552:552) (650:650:650)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (760:760:760) (845:845:845)) + (PORT ena (756:756:756) (816:816:816)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (566:566:566)) + (PORT datab (545:545:545) (641:641:641)) + (PORT datad (116:116:116) (152:152:152)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT datab (754:754:754) (870:870:870)) + (PORT datac (642:642:642) (731:731:731)) + (PORT datad (320:320:320) (371:371:371)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (377:377:377) (413:413:413)) + (PORT ena (419:419:419) (435:435:435)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (234:234:234)) + (PORT datab (117:117:117) (151:151:151)) + (PORT datac (119:119:119) (161:161:161)) + (PORT datad (676:676:676) (801:801:801)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT datab (650:650:650) (745:745:745)) + (PORT datac (346:346:346) (410:410:410)) + (PORT datad (739:739:739) (849:849:849)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT datab (653:653:653) (749:749:749)) + (PORT datac (346:346:346) (410:410:410)) + (PORT datad (738:738:738) (848:848:848)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (375:375:375) (411:411:411)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (181:181:181)) + (PORT datab (141:141:141) (179:179:179)) + (PORT datad (126:126:126) (150:150:150)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT datac (503:503:503) (580:580:580)) + (PORT datad (731:731:731) (838:838:838)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (462:462:462)) + (PORT datab (646:646:646) (750:750:750)) + (PORT datac (104:104:104) (134:134:134)) + (PORT datad (804:804:804) (942:942:942)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (643:643:643) (714:714:714)) + (PORT ena (660:660:660) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (461:461:461)) + (PORT datab (645:645:645) (748:748:748)) + (PORT datac (105:105:105) (135:135:135)) + (PORT datad (805:805:805) (943:943:943)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (643:643:643) (714:714:714)) + (PORT ena (631:631:631) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (294:294:294)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (344:344:344) (402:402:402)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (397:397:397)) + (PORT datab (517:517:517) (608:608:608)) + (PORT datad (358:358:358) (423:423:423)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (917:917:917)) + (PORT asdata (915:915:915) (1012:1012:1012)) + (PORT ena (812:812:812) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (404:404:404)) + (PORT datab (766:766:766) (882:882:882)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (737:737:737)) + (PORT datab (644:644:644) (748:748:748)) + (PORT datac (105:105:105) (135:135:135)) + (PORT datad (371:371:371) (430:430:430)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (918:918:918)) + (PORT asdata (661:661:661) (736:736:736)) + (PORT ena (644:644:644) (698:698:698)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (581:581:581)) + (PORT datab (214:214:214) (269:269:269)) + (PORT datac (508:508:508) (591:591:591)) + (PORT datad (333:333:333) (387:387:387)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (580:580:580)) + (PORT datab (502:502:502) (600:600:600)) + (PORT datac (627:627:627) (726:726:726)) + (PORT datad (200:200:200) (242:242:242)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT datab (527:527:527) (614:614:614)) + (PORT datac (733:733:733) (838:838:838)) + (PORT datad (497:497:497) (573:573:573)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (761:761:761)) + (PORT datab (648:648:648) (752:752:752)) + (PORT datac (103:103:103) (132:132:132)) + (PORT datad (374:374:374) (434:434:434)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (917:917:917)) + (PORT asdata (915:915:915) (1012:1012:1012)) + (PORT ena (649:649:649) (703:703:703)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1102:1102:1102)) + (PORT datab (510:510:510) (597:597:597)) + (PORT datad (515:515:515) (592:592:592)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (918:918:918)) + (PORT asdata (662:662:662) (738:738:738)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (264:264:264)) + (PORT datab (344:344:344) (406:406:406)) + (PORT datad (187:187:187) (230:230:230)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1122:1122:1122)) + (PORT datab (650:650:650) (747:747:747)) + (PORT datad (431:431:431) (486:486:486)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT asdata (762:762:762) (844:844:844)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (465:465:465) (528:528:528)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT datab (562:562:562) (646:646:646)) + (PORT datac (491:491:491) (581:581:581)) + (PORT datad (481:481:481) (559:559:559)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (669:669:669) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (274:274:274)) + (PORT datab (313:313:313) (371:371:371)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (275:275:275) (313:313:313)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (415:415:415)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datad (426:426:426) (485:485:485)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (228:228:228)) + (PORT datab (323:323:323) (376:376:376)) + (PORT datac (748:748:748) (865:865:865)) + (PORT datad (346:346:346) (405:405:405)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (762:762:762) (847:847:847)) + (PORT ena (636:636:636) (682:682:682)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (147:147:147)) + (PORT datab (675:675:675) (791:791:791)) + (PORT datad (362:362:362) (425:425:425)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (431:431:431)) + (PORT datac (622:622:622) (719:719:719)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (679:679:679) (746:746:746)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (769:769:769) (850:850:850)) + (PORT ena (419:419:419) (435:435:435)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (769:769:769) (849:849:849)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (181:181:181)) + (PORT datab (141:141:141) (179:179:179)) + (PORT datad (126:126:126) (151:151:151)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (645:645:645) (709:709:709)) + (PORT ena (421:421:421) (441:441:441)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (749:749:749)) + (PORT datab (862:862:862) (1003:1003:1003)) + (PORT datad (577:577:577) (660:660:660)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (810:810:810) (910:910:910)) + (PORT ena (756:756:756) (816:816:816)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (415:415:415)) + (PORT datab (610:610:610) (699:699:699)) + (PORT datad (528:528:528) (614:614:614)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (918:918:918)) + (PORT asdata (648:648:648) (715:715:715)) + (PORT ena (644:644:644) (698:698:698)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (918:918:918)) + (PORT asdata (649:649:649) (715:715:715)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (427:427:427)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (191:191:191) (225:225:225)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (809:809:809) (908:908:908)) + (PORT ena (794:794:794) (880:880:880)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (180:180:180) (214:214:214)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (660:660:660) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (806:806:806) (905:905:905)) + (PORT ena (736:736:736) (793:793:793)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (283:283:283)) + (PORT datab (346:346:346) (408:408:408)) + (PORT datad (436:436:436) (508:508:508)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (794:794:794)) + (PORT datab (493:493:493) (580:580:580)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (486:486:486) (535:535:535)) + (PORT ena (631:631:631) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (283:283:283)) + (PORT datab (624:624:624) (718:718:718)) + (PORT datad (283:283:283) (328:328:328)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT asdata (927:927:927) (1045:1045:1045)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT asdata (927:927:927) (1045:1045:1045)) + (PORT ena (669:669:669) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (277:277:277)) + (PORT datab (306:306:306) (363:363:363)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (390:390:390)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (173:173:173) (208:208:208)) + (PORT datad (317:317:317) (368:368:368)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (761:761:761)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (621:621:621) (707:707:707)) + (PORT datad (446:446:446) (510:510:510)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (867:867:867) (954:954:954)) + (PORT ena (636:636:636) (682:682:682)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (715:715:715)) + (PORT datab (381:381:381) (451:451:451)) + (PORT datad (654:654:654) (763:763:763)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (131:131:131) (180:180:180)) + (PORT datac (386:386:386) (461:461:461)) + (PORT datad (455:455:455) (520:520:520)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (DELAY + (ABSOLUTE + (PORT dataa (501:501:501) (593:593:593)) + (PORT datab (516:516:516) (603:603:603)) + (PORT datac (843:843:843) (964:964:964)) + (PORT datad (375:375:375) (446:446:446)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_clkctrl") (INSTANCE ula_\|pll_\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) @@ -13518,24 +12842,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~0) - (DELAY - (ABSOLUTE - (PORT datab (362:362:362) (439:439:439)) - (IOPATH datab combout (192:192:192) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~14) (DELAY (ABSOLUTE - (PORT datab (215:215:215) (274:274:274)) + (PORT datab (773:773:773) (898:898:898)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13549,9 +12861,9 @@ (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT datab (671:671:671) (789:789:789)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -13563,9 +12875,9 @@ (INSTANCE ula_\|video_\|vga_hc\~2) (DELAY (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datad (201:201:201) (237:237:237)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT datac (457:457:457) (527:527:527)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -13575,13 +12887,13 @@ (INSTANCE ula_\|video_\|vga_hc\[8\]) (DELAY (ABSOLUTE - (PORT clk (922:922:922) (926:926:926)) - (PORT asdata (732:732:732) (800:800:800)) + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) ) ) (CELL @@ -13589,8 +12901,8 @@ (INSTANCE ula_\|video_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datab (837:837:837) (980:980:980)) - (IOPATH datab combout (196:196:196) (205:205:205)) + (PORT datad (363:363:363) (425:425:425)) + (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) ) ) @@ -13600,8 +12912,8 @@ (INSTANCE ula_\|video_\|vga_hc\~1) (DELAY (ABSOLUTE - (PORT datab (105:105:105) (134:134:134)) - (PORT datad (200:200:200) (236:236:236)) + (PORT datab (120:120:120) (149:149:149)) + (PORT datad (295:295:295) (343:343:343)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13612,59 +12924,23 @@ (INSTANCE ula_\|video_\|vga_hc\[9\]) (DELAY (ABSOLUTE - (PORT clk (922:922:922) (926:926:926)) - (PORT asdata (343:343:343) (374:374:374)) + (PORT clk (917:917:917) (921:921:921)) + (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~0) + (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT dataa (544:544:544) (651:651:651)) - (PORT datab (380:380:380) (462:462:462)) - (PORT datac (671:671:671) (782:782:782)) - (PORT datad (370:370:370) (446:446:446)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (777:777:777) (915:915:915)) - (PORT datab (337:337:337) (407:407:407)) - (PORT datac (631:631:631) (736:736:736)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (1002:1002:1002)) - (PORT datab (658:658:658) (780:780:780)) - (PORT datac (94:94:94) (117:117:117)) - (PORT datad (637:637:637) (731:731:731)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT datab (571:571:571) (658:658:658)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -13674,8 +12950,8 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (159:159:159) (185:185:185)) - (PORT datad (109:109:109) (129:129:129)) + (PORT datac (457:457:457) (535:535:535)) + (PORT datad (505:505:505) (580:580:580)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13687,72 +12963,6 @@ (DELAY (ABSOLUTE (PORT clk (918:918:918) (923:923:923)) - (PORT asdata (482:482:482) (520:520:520)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~2) - (DELAY - (ABSOLUTE - (PORT datab (381:381:381) (461:461:461)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT asdata (503:503:503) (543:543:543)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (537:537:537) (646:646:646)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (464:464:464) (525:525:525)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13763,10 +12973,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~6) + (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (641:641:641) (745:745:745)) + (PORT datab (360:360:360) (430:430:430)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13775,12 +12985,88 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (307:307:307) (358:358:358)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT datab (217:217:217) (275:275:275)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (340:340:340) (367:367:367)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (366:366:366) (441:441:441)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (339:339:339)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (922:922:922) (926:926:926)) + (PORT clk (918:918:918) (922:922:922)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13794,9 +13080,9 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (213:213:213) (273:273:273)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (561:561:561) (647:647:647)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -13808,8 +13094,8 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (922:922:922) (926:926:926)) - (PORT asdata (467:467:467) (509:509:509)) + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (340:340:340) (367:367:367)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -13817,12 +13103,59 @@ (HOLD asdata (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (808:808:808)) + (PORT datab (530:530:530) (634:634:634)) + (PORT datac (534:534:534) (639:639:639)) + (PORT datad (156:156:156) (204:204:204)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (423:423:423)) + (PORT datab (774:774:774) (900:900:900)) + (PORT datad (508:508:508) (565:565:565)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (295:295:295)) + (PORT datab (366:366:366) (440:440:440)) + (PORT datac (343:343:343) (414:414:414)) + (PORT datad (299:299:299) (344:344:344)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (752:752:752) (874:874:874)) + (PORT dataa (346:346:346) (418:418:418)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13836,9 +13169,9 @@ (INSTANCE ula_\|video_\|vga_hc\~0) (DELAY (ABSOLUTE - (PORT dataa (175:175:175) (211:211:211)) - (PORT datad (195:195:195) (231:231:231)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT datac (460:460:460) (530:530:530)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -13848,13 +13181,13 @@ (INSTANCE ula_\|video_\|vga_hc\[5\]) (DELAY (ABSOLUTE - (PORT clk (922:922:922) (926:926:926)) - (PORT asdata (472:472:472) (515:515:515)) + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) ) ) (CELL @@ -13862,7 +13195,7 @@ (INSTANCE ula_\|video_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (287:287:287)) + (PORT dataa (326:326:326) (394:394:394)) (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13876,8 +13209,8 @@ (INSTANCE ula_\|video_\|vga_hc\[6\]) (DELAY (ABSOLUTE - (PORT clk (922:922:922) (926:926:926)) - (PORT asdata (341:341:341) (373:373:373)) + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (268:268:268) (288:288:288)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -13890,8 +13223,8 @@ (INSTANCE ula_\|video_\|vga_hc\[7\]) (DELAY (ABSOLUTE - (PORT clk (922:922:922) (926:926:926)) - (PORT asdata (435:435:435) (470:470:470)) + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (446:446:446) (483:483:483)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -13904,48 +13237,19 @@ (INSTANCE ula_\|video_\|Add1\~0) (DELAY (ABSOLUTE - (PORT dataa (684:684:684) (801:801:801)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (393:393:393) (474:474:474)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (486:486:486)) - (PORT datab (397:397:397) (464:464:464)) - (PORT datad (166:166:166) (194:194:194)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~2) (DELAY (ABSOLUTE - (PORT dataa (248:248:248) (311:311:311)) + (PORT dataa (388:388:388) (464:464:464)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13959,9 +13263,9 @@ (INSTANCE ula_\|video_\|Add1\~4) (DELAY (ABSOLUTE - (PORT datab (234:234:234) (293:293:293)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (362:362:362) (437:437:437)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -13973,10 +13277,10 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (413:413:413) (485:485:485)) - (PORT datab (174:174:174) (208:208:208)) - (PORT datad (375:375:375) (432:432:432)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (266:266:266) (332:332:332)) + (PORT datab (313:313:313) (364:364:364)) + (PORT datad (476:476:476) (552:552:552)) + (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13988,7 +13292,7 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) + (PORT clk (914:914:914) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -14002,7 +13306,7 @@ (INSTANCE ula_\|video_\|Add1\~6) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (419:419:419)) + (PORT dataa (376:376:376) (456:456:456)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14016,12 +13320,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (414:414:414) (487:487:487)) - (PORT datab (399:399:399) (466:466:466)) - (PORT datad (157:157:157) (182:182:182)) + (PORT dataa (322:322:322) (377:377:377)) + (PORT datab (354:354:354) (417:417:417)) + (PORT datac (358:358:358) (437:437:437)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -14031,13 +13336,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (914:914:914) (918:918:918)) + (PORT asdata (707:707:707) (780:780:780)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) ) ) (CELL @@ -14045,9 +13350,9 @@ (INSTANCE ula_\|video_\|Add1\~8) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (291:291:291)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (373:373:373) (454:454:454)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -14059,10 +13364,10 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) (DELAY (ABSOLUTE - (PORT dataa (413:413:413) (485:485:485)) - (PORT datab (391:391:391) (458:458:458)) - (PORT datad (168:168:168) (196:196:196)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (266:266:266) (332:332:332)) + (PORT datab (327:327:327) (381:381:381)) + (PORT datad (474:474:474) (549:549:549)) + (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14074,7 +13379,7 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) + (PORT clk (914:914:914) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -14088,9 +13393,9 @@ (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT datab (159:159:159) (210:210:210)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (382:382:382) (469:469:469)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -14102,12 +13407,13 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) (DELAY (ABSOLUTE - (PORT dataa (364:364:364) (420:420:420)) - (PORT datab (766:766:766) (865:865:865)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (322:322:322) (377:377:377)) + (PORT datab (354:354:354) (417:417:417)) + (PORT datac (384:384:384) (465:465:465)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -14117,13 +13423,13 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (914:914:914) (918:918:918)) + (PORT asdata (467:467:467) (503:503:503)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) ) ) (CELL @@ -14131,9 +13437,9 @@ (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT dataa (233:233:233) (295:295:295)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (389:389:389) (469:469:469)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -14145,10 +13451,10 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (414:414:414) (487:487:487)) - (PORT datab (397:397:397) (465:465:465)) - (PORT datad (161:161:161) (187:187:187)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (266:266:266) (332:332:332)) + (PORT datab (310:310:310) (365:365:365)) + (PORT datad (477:477:477) (553:553:553)) + (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14160,7 +13466,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) + (PORT clk (914:914:914) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -14174,9 +13480,9 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT dataa (368:368:368) (438:438:438)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (376:376:376) (449:449:449)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -14188,10 +13494,10 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (413:413:413) (485:485:485)) - (PORT datab (304:304:304) (349:349:349)) - (PORT datad (376:376:376) (433:433:433)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (266:266:266) (332:332:332)) + (PORT datab (639:639:639) (726:726:726)) + (PORT datad (476:476:476) (551:551:551)) + (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14203,7 +13509,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) + (PORT clk (914:914:914) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -14217,7 +13523,7 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (247:247:247) (305:305:305)) + (PORT datab (399:399:399) (484:484:484)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14231,10 +13537,10 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (414:414:414) (487:487:487)) - (PORT datab (400:400:400) (467:467:467)) - (PORT datad (160:160:160) (186:186:186)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (266:266:266) (332:332:332)) + (PORT datab (521:521:521) (599:599:599)) + (PORT datad (473:473:473) (548:548:548)) + (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14246,7 +13552,47 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datad (351:351:351) (415:415:415)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (332:332:332)) + (PORT datab (537:537:537) (608:608:608)) + (PORT datad (477:477:477) (552:552:552)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -14260,10 +13606,10 @@ (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (159:159:159) (211:211:211)) - (PORT datab (158:158:158) (208:208:208)) - (PORT datac (145:145:145) (188:188:188)) - (PORT datad (144:144:144) (183:183:183)) + (PORT dataa (147:147:147) (200:200:200)) + (PORT datab (146:146:146) (195:195:195)) + (PORT datac (144:144:144) (186:186:186)) + (PORT datad (133:133:133) (172:172:172)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -14273,24 +13619,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~18) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT datad (210:210:210) (260:260:260)) + (PORT dataa (650:650:650) (772:772:772)) + (PORT datab (457:457:457) (535:535:535)) + (PORT datac (339:339:339) (397:397:397)) + (PORT datad (370:370:370) (443:443:443)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) + (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (413:413:413) (484:484:484)) - (PORT datab (389:389:389) (455:455:455)) - (PORT datad (168:168:168) (197:197:197)) + (PORT dataa (340:340:340) (409:409:409)) + (PORT datab (359:359:359) (427:427:427)) + (PORT datac (300:300:300) (343:343:343)) + (PORT datad (156:156:156) (182:182:182)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (331:331:331)) + (PORT datab (295:295:295) (339:339:339)) + (PORT datad (472:472:472) (547:547:547)) + (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14299,10 +13666,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[9\]) + (INSTANCE ula_\|video_\|vga_vc\[0\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) + (PORT clk (914:914:914) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -14311,47 +13678,15 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (917:917:917)) - (PORT datab (720:720:720) (845:845:845)) - (PORT datac (695:695:695) (810:810:810)) - (PORT datad (627:627:627) (725:725:725)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (431:431:431)) - (PORT datab (400:400:400) (481:481:481)) - (PORT datac (382:382:382) (465:465:465)) - (PORT datad (161:161:161) (191:191:191)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (413:413:413) (484:484:484)) - (PORT datab (174:174:174) (211:211:211)) - (PORT datad (373:373:373) (429:429:429)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (266:266:266) (332:332:332)) + (PORT datab (301:301:301) (348:348:348)) + (PORT datad (474:474:474) (549:549:549)) + (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14363,7 +13698,7 @@ (INSTANCE ula_\|video_\|vga_vc\[1\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) + (PORT clk (914:914:914) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -14386,10 +13721,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (836:836:836) (975:975:975)) - (PORT datab (822:822:822) (703:703:703)) - (PORT datac (690:690:690) (798:798:798)) - (PORT datad (812:812:812) (938:938:938)) + (PORT dataa (784:784:784) (902:902:902)) + (PORT datab (396:396:396) (475:475:475)) + (PORT datac (1149:1149:1149) (995:995:995)) + (PORT datad (359:359:359) (424:424:424)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -14402,10 +13737,10 @@ (INSTANCE z80_\|pla_decode_\|Equal79\~0) (DELAY (ABSOLUTE - (PORT dataa (680:680:680) (789:789:789)) - (PORT datab (508:508:508) (599:599:599)) - (PORT datac (896:896:896) (1038:1038:1038)) - (PORT datad (908:908:908) (1052:1052:1052)) + (PORT dataa (712:712:712) (834:834:834)) + (PORT datab (535:535:535) (631:631:631)) + (PORT datac (917:917:917) (1101:1101:1101)) + (PORT datad (676:676:676) (800:800:800)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -14413,30 +13748,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (145:145:145) (196:196:196)) - (PORT datab (454:454:454) (523:523:523)) - (PORT datac (1587:1587:1587) (1814:1814:1814)) - (PORT datad (538:538:538) (606:606:606)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) (DELAY (ABSOLUTE - (PORT dataa (1593:1593:1593) (1818:1818:1818)) - (PORT datab (551:551:551) (629:629:629)) - (PORT datad (442:442:442) (500:500:500)) + (PORT dataa (833:833:833) (979:979:979)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datad (365:365:365) (435:435:435)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -14449,11 +13768,11 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) (DELAY (ABSOLUTE - (PORT dataa (189:189:189) (255:255:255)) - (PORT datac (649:649:649) (768:768:768)) - (PORT datad (152:152:152) (201:201:201)) + (PORT dataa (208:208:208) (286:286:286)) + (PORT datab (1139:1139:1139) (1327:1327:1327)) + (PORT datad (152:152:152) (195:195:195)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -14463,7 +13782,7 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (709:709:709) (768:768:768)) + (PORT inclk[0] (890:890:890) (988:988:988)) ) ) ) @@ -14472,9 +13791,9 @@ (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (917:917:917)) + (PORT clk (916:916:916) (923:923:923)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (891:891:891) (894:894:894)) + (PORT clrn (890:890:890) (894:894:894)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -14483,17 +13802,33 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (463:463:463)) + (PORT datab (144:144:144) (193:193:193)) + (PORT datac (109:109:109) (134:134:134)) + (PORT datad (808:808:808) (948:948:948)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|interrupts_\|iff1\~1) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (143:143:143) (191:191:191)) - (PORT datac (870:870:870) (992:992:992)) - (PORT datad (520:520:520) (596:596:596)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (723:723:723) (832:832:832)) + (PORT datab (142:142:142) (191:191:191)) + (PORT datac (481:481:481) (565:565:565)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -14504,11 +13839,11 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT dataa (197:197:197) (265:265:265)) - (PORT datac (650:650:650) (769:769:769)) - (PORT datad (159:159:159) (209:209:209)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT datab (781:781:781) (906:906:906)) + (PORT datac (840:840:840) (975:975:975)) + (PORT datad (711:711:711) (827:827:827)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -14518,9 +13853,9 @@ (INSTANCE z80_\|interrupts_\|iff1) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (917:917:917)) + (PORT clk (916:916:916) (923:923:923)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (748:748:748) (817:817:817)) + (PORT clrn (739:739:739) (803:803:803)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -14534,10 +13869,10 @@ (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (709:709:709) (834:834:834)) - (PORT datab (720:720:720) (845:845:845)) - (PORT datac (381:381:381) (463:463:463)) - (PORT datad (627:627:627) (725:725:725)) + (PORT dataa (872:872:872) (1011:1011:1011)) + (PORT datab (456:456:456) (534:534:534)) + (PORT datac (342:342:342) (402:402:402)) + (PORT datad (233:233:233) (287:287:287)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -14550,10 +13885,10 @@ (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT datab (399:399:399) (479:479:479)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (346:346:346) (401:401:401)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (301:301:301) (343:343:343)) + (PORT datad (239:239:239) (295:295:295)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -14564,10 +13899,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT dataa (867:867:867) (1002:1002:1002)) - (PORT datab (489:489:489) (564:564:564)) - (PORT datac (1059:1059:1059) (1218:1218:1218)) - (PORT datad (819:819:819) (915:915:915)) + (PORT dataa (636:636:636) (749:749:749)) + (PORT datab (338:338:338) (394:394:394)) + (PORT datac (873:873:873) (1017:1017:1017)) + (PORT datad (456:456:456) (527:527:527)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -14580,9 +13915,9 @@ (INSTANCE z80_\|interrupts_\|int_armed) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (893:893:893) (897:897:897)) + (PORT clrn (900:900:900) (904:904:904)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -14591,59 +13926,33 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_inst44\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (797:797:797) (920:920:920)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|interrupts_\|DFFE_inst44) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (916:916:916) (901:901:901)) - (PORT ena (491:491:491) (528:528:528)) + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (1177:1177:1177) (1361:1361:1361)) + (PORT clrn (928:928:928) (910:910:910)) + (PORT ena (890:890:890) (972:972:972)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (INSTANCE z80_\|execute_\|pc_inc_hold\~38) (DELAY (ABSOLUTE - (PORT dataa (190:190:190) (256:256:256)) - (PORT datab (168:168:168) (226:226:226)) - (PORT datac (137:137:137) (183:183:183)) + (PORT dataa (201:201:201) (275:275:275)) + (PORT datac (655:655:655) (768:768:768)) + (PORT datad (147:147:147) (189:189:189)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT dataa (456:456:456) (540:540:540)) - (PORT datab (526:526:526) (614:614:614)) - (PORT datac (526:526:526) (616:616:616)) - (PORT datad (270:270:270) (311:311:311)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -14651,78 +13960,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) (DELAY (ABSOLUTE - (PORT dataa (629:629:629) (738:738:738)) - (PORT datab (222:222:222) (266:266:266)) - (PORT datac (693:693:693) (787:787:787)) - (PORT datad (653:653:653) (737:737:737)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) - (DELAY - (ABSOLUTE - (PORT dataa (954:954:954) (1109:1109:1109)) - (PORT datab (721:721:721) (825:825:825)) - (PORT datac (661:661:661) (764:764:764)) - (PORT datad (946:946:946) (1091:1091:1091)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (453:453:453) (524:524:524)) - (PORT datab (345:345:345) (406:406:406)) - (PORT datac (428:428:428) (496:496:496)) - (PORT datad (338:338:338) (396:396:396)) + (PORT dataa (942:942:942) (1111:1111:1111)) + (PORT datab (680:680:680) (788:788:788)) + (PORT datac (543:543:543) (644:644:644)) + (PORT datad (466:466:466) (541:541:541)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (INSTANCE z80_\|execute_\|pc_inc_hold\~45) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (433:433:433) (500:500:500)) - (PORT datad (779:779:779) (893:893:893)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (584:584:584) (679:679:679)) + (PORT datab (394:394:394) (470:470:470)) + (PORT datac (663:663:663) (783:783:783)) + (PORT datad (349:349:349) (403:403:403)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (INSTANCE z80_\|execute_\|pc_inc_hold\~44) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (358:358:358) (422:422:422)) - (PORT datac (360:360:360) (422:422:422)) - (PORT datad (460:460:460) (530:530:530)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (584:584:584) (679:679:679)) + (PORT datab (514:514:514) (601:601:601)) + (PORT datac (474:474:474) (540:540:540)) + (PORT datad (588:588:588) (671:671:671)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14731,30 +14008,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (INSTANCE z80_\|execute_\|pc_inc_hold\~46) (DELAY (ABSOLUTE - (PORT dataa (353:353:353) (429:429:429)) - (PORT datab (350:350:350) (425:425:425)) - (PORT datac (408:408:408) (467:467:467)) - (PORT datad (331:331:331) (388:388:388)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~22) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (565:565:565)) - (PORT datab (820:820:820) (950:950:950)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (163:163:163)) + (PORT dataa (172:172:172) (212:212:212)) + (PORT datab (395:395:395) (471:471:471)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (592:592:592) (676:676:676)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14763,13 +14024,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (INSTANCE z80_\|execute_\|pc_inc_hold\~37) (DELAY (ABSOLUTE - (PORT dataa (657:657:657) (758:758:758)) - (PORT datab (466:466:466) (535:535:535)) - (PORT datac (635:635:635) (731:731:731)) - (PORT datad (877:877:877) (998:998:998)) + (PORT dataa (643:643:643) (753:753:753)) + (PORT datab (502:502:502) (579:579:579)) + (PORT datac (578:578:578) (652:652:652)) + (PORT datad (106:106:106) (124:124:124)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~50) + (DELAY + (ABSOLUTE + (PORT dataa (442:442:442) (518:518:518)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (892:892:892) (1053:1053:1053)) + (PORT datad (1280:1280:1280) (1481:1481:1481)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (155:155:155)) + (PORT datab (650:650:650) (755:755:755)) + (PORT datac (592:592:592) (674:674:674)) + (PORT datad (314:314:314) (365:365:365)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -14782,10 +14075,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) (DELAY (ABSOLUTE - (PORT dataa (507:507:507) (595:595:595)) - (PORT datab (682:682:682) (780:780:780)) - (PORT datac (646:646:646) (748:748:748)) - (PORT datad (944:944:944) (1068:1068:1068)) + (PORT dataa (943:943:943) (1083:1083:1083)) + (PORT datab (328:328:328) (388:388:388)) + (PORT datac (902:902:902) (1048:1048:1048)) + (PORT datad (656:656:656) (761:761:761)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -14795,365 +14088,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) (DELAY (ABSOLUTE - (PORT dataa (605:605:605) (697:697:697)) - (PORT datab (402:402:402) (487:487:487)) - (PORT datac (291:291:291) (334:334:334)) - (PORT datad (586:586:586) (668:668:668)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~25) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (233:233:233)) - (PORT datab (499:499:499) (582:582:582)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~20) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (699:699:699)) - (PORT datab (474:474:474) (553:553:553)) - (PORT datac (384:384:384) (464:464:464)) - (PORT datad (434:434:434) (495:495:495)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~41) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (672:672:672)) - (PORT datab (547:547:547) (658:658:658)) - (PORT datac (671:671:671) (783:783:783)) - (PORT datad (529:529:529) (635:635:635)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~21) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (495:495:495)) - (PORT datab (563:563:563) (643:643:643)) - (PORT datac (396:396:396) (475:475:475)) - (PORT datad (552:552:552) (662:662:662)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~26) - (DELAY - (ABSOLUTE - (PORT dataa (118:118:118) (155:155:155)) - (PORT datab (114:114:114) (145:145:145)) - (PORT datac (342:342:342) (403:403:403)) - (PORT datad (335:335:335) (390:390:390)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (660:660:660)) - (PORT datab (468:468:468) (538:538:538)) - (PORT datac (546:546:546) (622:622:622)) - (PORT datad (468:468:468) (530:530:530)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (230:230:230)) - (PORT datab (469:469:469) (549:549:549)) - (PORT datac (562:562:562) (642:642:642)) - (PORT datad (441:441:441) (511:511:511)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (944:944:944) (1087:1087:1087)) - (PORT datac (540:540:540) (632:632:632)) - (PORT datad (449:449:449) (511:511:511)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (407:407:407)) - (PORT datab (109:109:109) (140:140:140)) - (PORT datac (423:423:423) (489:489:489)) - (PORT datad (779:779:779) (909:909:909)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (101:101:101) (122:122:122)) - (PORT datad (423:423:423) (483:483:483)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (711:711:711)) - (PORT datab (606:606:606) (702:702:702)) - (PORT datac (288:288:288) (327:327:327)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (603:603:603)) - (PORT datac (385:385:385) (437:437:437)) - (PORT datad (493:493:493) (594:594:594)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~42) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (788:788:788)) - (PORT datab (769:769:769) (897:897:897)) - (PORT datac (622:622:622) (736:736:736)) - (PORT datad (640:640:640) (743:743:743)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~27) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (424:424:424)) - (PORT datab (717:717:717) (807:807:807)) - (PORT datac (418:418:418) (475:475:475)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (434:434:434)) - (PORT datab (506:506:506) (616:616:616)) - (PORT datac (349:349:349) (415:415:415)) - (PORT datad (483:483:483) (575:575:575)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (359:359:359) (420:420:420)) - (PORT datac (541:541:541) (618:618:618)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (707:707:707)) - (PORT datab (453:453:453) (529:529:529)) - (PORT datac (321:321:321) (372:372:372)) - (PORT datad (458:458:458) (532:532:532)) + (PORT dataa (396:396:396) (481:481:481)) + (PORT datab (368:368:368) (440:440:440)) + (PORT datac (623:623:623) (726:726:726)) + (PORT datad (114:114:114) (137:137:137)) (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (642:642:642)) - (PORT datab (359:359:359) (419:419:419)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (671:671:671)) - (PORT datab (547:547:547) (658:658:658)) - (PORT datac (558:558:558) (630:630:630)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (519:519:519)) - (PORT datab (457:457:457) (533:533:533)) - (PORT datac (604:604:604) (691:691:691)) - (PORT datad (455:455:455) (529:529:529)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (264:264:264)) - (PORT datab (173:173:173) (232:232:232)) - (PORT datac (135:135:135) (180:180:180)) - (PORT datad (468:468:468) (532:532:532)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (234:234:234)) - (PORT datab (403:403:403) (488:488:488)) - (PORT datac (254:254:254) (287:287:287)) - (PORT datad (897:897:897) (1028:1028:1028)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -15164,10 +14107,10 @@ (INSTANCE z80_\|execute_\|pc_inc_hold\~31) (DELAY (ABSOLUTE - (PORT dataa (599:599:599) (694:694:694)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (590:590:590) (673:673:673)) - (PORT datad (177:177:177) (207:207:207)) + (PORT dataa (609:609:609) (697:697:697)) + (PORT datab (455:455:455) (525:525:525)) + (PORT datac (683:683:683) (777:777:777)) + (PORT datad (442:442:442) (508:508:508)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -15175,281 +14118,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) - (DELAY - (ABSOLUTE - (PORT dataa (307:307:307) (359:359:359)) - (PORT datab (654:654:654) (761:761:761)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (772:772:772)) - (PORT datab (401:401:401) (486:486:486)) - (PORT datac (485:485:485) (571:571:571)) - (PORT datad (944:944:944) (1068:1068:1068)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (233:233:233)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (696:696:696) (785:785:785)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) - (DELAY - (ABSOLUTE - (PORT dataa (755:755:755) (871:871:871)) - (PORT datab (388:388:388) (474:474:474)) - (PORT datac (400:400:400) (497:497:497)) - (PORT datad (549:549:549) (659:659:659)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (154:154:154)) - (PORT datab (285:285:285) (332:332:332)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (354:354:354) (416:416:416)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|pc_inc_hold\~32) (DELAY (ABSOLUTE - (PORT dataa (122:122:122) (160:160:160)) - (PORT datac (345:345:345) (406:406:406)) - (PORT datad (98:98:98) (119:119:119)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT dataa (427:427:427) (527:527:527)) - (PORT datab (579:579:579) (697:697:697)) - (PORT datac (370:370:370) (449:449:449)) - (PORT datad (693:693:693) (793:793:793)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (333:333:333) (388:388:388)) + (PORT dataa (610:610:610) (697:697:697)) + (PORT datab (329:329:329) (389:389:389)) + (PORT datac (110:110:110) (135:135:135)) + (PORT datad (915:915:915) (1056:1056:1056)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (954:954:954) (1110:1110:1110)) - (PORT datab (732:732:732) (853:853:853)) - (PORT datac (660:660:660) (763:763:763)) - (PORT datad (598:598:598) (697:697:697)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT datab (452:452:452) (521:521:521)) - (PORT datac (535:535:535) (609:609:609)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (160:160:160)) - (PORT datac (692:692:692) (781:781:781)) - (PORT datad (96:96:96) (118:118:118)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (325:325:325) (377:377:377)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (417:417:417)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (440:440:440) (505:505:505)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (273:273:273) (323:323:323)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (96:96:96) (121:121:121)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (220:220:220)) - (PORT datab (437:437:437) (506:506:506)) - (PORT datad (452:452:452) (519:519:519)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (732:732:732)) - (PORT datab (636:636:636) (737:737:737)) - (PORT datac (658:658:658) (770:770:770)) - (PORT datad (543:543:543) (616:616:616)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (767:767:767)) - (PORT datab (114:114:114) (143:143:143)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (334:334:334) (391:391:391)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (760:760:760) (881:881:881)) - (PORT datab (128:128:128) (162:162:162)) - (PORT datac (1329:1329:1329) (1514:1514:1514)) - (PORT datad (1032:1032:1032) (1220:1220:1220)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -15460,10 +14139,152 @@ (INSTANCE z80_\|execute_\|pc_inc_hold\~34) (DELAY (ABSOLUTE - (PORT dataa (397:397:397) (475:475:475)) - (PORT datab (651:651:651) (764:764:764)) - (PORT datac (1078:1078:1078) (1258:1258:1258)) - (PORT datad (383:383:383) (430:430:430)) + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (103:103:103) (132:132:132)) + (PORT datad (93:93:93) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~51) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (744:744:744)) + (PORT datab (786:786:786) (922:922:922)) + (PORT datac (1403:1403:1403) (1620:1620:1620)) + (PORT datad (839:839:839) (994:994:994)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (454:454:454)) + (PORT datab (652:652:652) (755:755:755)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (461:461:461) (529:529:529)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~52) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (1011:1011:1011)) + (PORT datab (783:783:783) (918:918:918)) + (PORT datac (1408:1408:1408) (1626:1626:1626)) + (PORT datad (595:595:595) (700:700:700)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (236:236:236)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (324:324:324) (385:385:385)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (697:697:697)) + (PORT datab (345:345:345) (407:407:407)) + (PORT datac (335:335:335) (384:384:384)) + (PORT datad (773:773:773) (885:885:885)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1139:1139:1139) (1333:1333:1333)) + (PORT datab (514:514:514) (601:601:601)) + (PORT datac (788:788:788) (904:904:904)) + (PORT datad (352:352:352) (421:421:421)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (876:876:876)) + (PORT datab (989:989:989) (1158:1158:1158)) + (PORT datad (354:354:354) (418:418:418)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (148:148:148)) + (PORT datab (115:115:115) (147:147:147)) + (PORT datac (366:366:366) (431:431:431)) + (PORT datad (302:302:302) (349:349:349)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~43) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (908:908:908)) + (PORT datab (369:369:369) (428:428:428)) + (PORT datac (1100:1100:1100) (1281:1281:1281)) + (PORT datad (710:710:710) (816:816:816)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -15476,12 +14297,92 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) (DELAY (ABSOLUTE - (PORT dataa (614:614:614) (707:707:707)) - (PORT datab (503:503:503) (584:584:584)) - (PORT datac (712:712:712) (812:812:812)) - (PORT datad (457:457:457) (530:530:530)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (117:117:117) (145:145:145)) + (PORT datac (346:346:346) (410:410:410)) + (PORT datad (101:101:101) (123:123:123)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (241:241:241)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (341:341:341) (395:395:395)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (433:433:433)) + (PORT datab (393:393:393) (469:469:469)) + (PORT datac (344:344:344) (398:398:398)) + (PORT datad (642:642:642) (741:741:741)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~53) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (1083:1083:1083)) + (PORT datab (591:591:591) (704:704:704)) + (PORT datac (328:328:328) (388:388:388)) + (PORT datad (545:545:545) (639:639:639)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~39) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (147:147:147)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (334:334:334) (383:383:383)) + (PORT datad (297:297:297) (344:344:344)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~47) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (238:238:238)) + (PORT datab (110:110:110) (143:143:143)) + (PORT datac (346:346:346) (409:409:409)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -15492,13 +14393,43 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) (DELAY (ABSOLUTE - (PORT dataa (110:110:110) (143:143:143)) - (PORT datab (443:443:443) (511:511:511)) - (PORT datac (444:444:444) (516:516:516)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (117:117:117) (149:149:149)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (472:472:472) (539:539:539)) + (PORT datad (102:102:102) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (DELAY + (ABSOLUTE + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (353:353:353) (411:411:411)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (143:143:143)) + (PORT datab (174:174:174) (214:214:214)) + (PORT datac (343:343:343) (397:397:397)) + (PORT datad (96:96:96) (117:117:117)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -15508,130 +14439,10 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) (DELAY (ABSOLUTE - (PORT dataa (109:109:109) (143:143:143)) - (PORT datab (331:331:331) (387:387:387)) - (PORT datac (443:443:443) (515:515:515)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (800:800:800)) - (PORT datac (671:671:671) (762:762:762)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (530:530:530) (580:580:580)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1206:1206:1206)) - (PORT datab (110:110:110) (141:141:141)) - (PORT datac (441:441:441) (513:513:513)) - (PORT datad (698:698:698) (787:787:787)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) - (DELAY - (ABSOLUTE - (PORT datab (437:437:437) (508:508:508)) - (PORT datad (554:554:554) (647:647:647)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (450:450:450)) - (PORT datab (1086:1086:1086) (1257:1257:1257)) - (PORT datac (431:431:431) (486:486:486)) - (PORT datad (767:767:767) (886:886:886)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (1028:1028:1028)) - (PORT datab (566:566:566) (683:683:683)) - (PORT datac (178:178:178) (216:216:216)) - (PORT datad (520:520:520) (624:624:624)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (750:750:750) (875:875:875)) - (PORT datab (278:278:278) (328:328:328)) - (PORT datac (651:651:651) (749:749:749)) - (PORT datad (416:416:416) (476:476:476)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (771:771:771)) - (PORT datab (290:290:290) (342:342:342)) - (PORT datac (695:695:695) (803:803:803)) - (PORT datad (291:291:291) (332:332:332)) + (PORT dataa (369:369:369) (435:435:435)) + (PORT datab (517:517:517) (604:604:604)) + (PORT datac (663:663:663) (782:782:782)) + (PORT datad (99:99:99) (121:121:121)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -15641,1658 +14452,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~54) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) (DELAY (ABSOLUTE - (PORT dataa (624:624:624) (725:725:725)) - (PORT datab (1200:1200:1200) (1393:1393:1393)) - (PORT datac (465:465:465) (533:533:533)) - (PORT datad (505:505:505) (596:596:596)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (721:721:721) (829:829:829)) - (PORT datab (336:336:336) (398:398:398)) - (PORT datac (347:347:347) (404:404:404)) - (PORT datad (621:621:621) (706:706:706)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (650:650:650) (758:758:758)) - (PORT datac (443:443:443) (512:512:512)) - (PORT datad (106:106:106) (125:125:125)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (993:993:993)) - (PORT datab (480:480:480) (560:560:560)) - (PORT datac (464:464:464) (527:527:527)) - (PORT datad (1094:1094:1094) (1234:1234:1234)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (976:976:976) (1107:1107:1107)) - (PORT datab (120:120:120) (150:150:150)) - (PORT datac (195:195:195) (235:235:235)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (279:279:279) (325:325:325)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (273:273:273) (307:307:307)) - (PORT datad (497:497:497) (577:577:577)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (437:437:437) (508:508:508)) - (PORT datab (350:350:350) (410:410:410)) - (PORT datac (599:599:599) (691:691:691)) - (PORT datad (160:160:160) (188:188:188)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (508:508:508)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (274:274:274) (317:317:317)) - (PORT datad (97:97:97) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (288:288:288) (323:323:323)) - (PORT datad (331:331:331) (379:379:379)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (958:958:958) (1117:1117:1117)) - (PORT datac (912:912:912) (1045:1045:1045)) - (PORT datad (808:808:808) (914:914:914)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (540:540:540) (601:601:601)) - (PORT ena (433:433:433) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|db\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1115:1115:1115)) - (PORT datab (1084:1084:1084) (1240:1240:1240)) - (PORT datad (809:809:809) (915:915:915)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (1012:1012:1012) (1181:1181:1181)) - (PORT datac (584:584:584) (666:666:666)) - (PORT datad (726:726:726) (836:836:836)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (528:528:528) (588:588:588)) - (PORT ena (630:630:630) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT datab (1014:1014:1014) (1184:1184:1184)) - (PORT datac (567:567:567) (653:653:653)) - (PORT datad (725:725:725) (835:835:835)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT datab (1021:1021:1021) (1191:1191:1191)) - (PORT datac (570:570:570) (657:657:657)) - (PORT datad (722:722:722) (831:831:831)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (528:528:528) (589:589:589)) - (PORT ena (617:617:617) (660:660:660)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT datab (1001:1001:1001) (1168:1168:1168)) - (PORT datac (585:585:585) (667:667:667)) - (PORT datad (731:731:731) (842:842:842)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (131:131:131) (181:181:181)) - (PORT datab (360:360:360) (433:433:433)) - (PORT datad (353:353:353) (418:418:418)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT datab (591:591:591) (682:682:682)) - (PORT datac (981:981:981) (1148:1148:1148)) - (PORT datad (731:731:731) (841:841:841)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (531:531:531) (594:594:594)) - (PORT ena (421:421:421) (441:441:441)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT datab (589:589:589) (681:681:681)) - (PORT datac (986:986:986) (1153:1153:1153)) - (PORT datad (728:728:728) (838:838:838)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (226:226:226)) - (PORT datab (339:339:339) (400:400:400)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT datac (1084:1084:1084) (1247:1247:1247)) - (PORT datad (542:542:542) (624:624:624)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (949:949:949)) - (PORT datab (345:345:345) (418:418:418)) - (PORT datac (285:285:285) (328:328:328)) - (PORT datad (696:696:696) (794:794:794)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (571:571:571) (671:671:671)) - (PORT datab (466:466:466) (541:541:541)) - (PORT datac (515:515:515) (591:591:591)) - (PORT datad (622:622:622) (714:714:714)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) - (DELAY - (ABSOLUTE - (PORT dataa (766:766:766) (889:889:889)) - (PORT datac (672:672:672) (801:801:801)) - (PORT datad (722:722:722) (834:834:834)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) - (DELAY - (ABSOLUTE - (PORT dataa (766:766:766) (889:889:889)) - (PORT datab (756:756:756) (891:891:891)) - (PORT datac (732:732:732) (834:834:834)) - (PORT datad (719:719:719) (837:837:837)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (415:415:415)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (469:469:469) (545:545:545)) - (PORT datad (467:467:467) (540:540:540)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT dataa (470:470:470) (546:546:546)) - (PORT datab (928:928:928) (1062:1062:1062)) - (PORT datac (479:479:479) (555:555:555)) - (PORT datad (644:644:644) (745:745:745)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) - (DELAY - (ABSOLUTE - (PORT dataa (719:719:719) (825:825:825)) - (PORT datab (705:705:705) (808:808:808)) - (PORT datac (1845:1845:1845) (2095:2095:2095)) - (PORT datad (380:380:380) (445:445:445)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (671:671:671)) - (PORT datab (512:512:512) (610:610:610)) - (PORT datad (552:552:552) (633:633:633)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (795:795:795) (942:942:942)) - (PORT datab (579:579:579) (664:664:664)) - (PORT datac (749:749:749) (884:884:884)) - (PORT datad (605:605:605) (696:696:696)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (125:125:125) (159:159:159)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (484:484:484) (569:569:569)) - (PORT datad (588:588:588) (669:669:669)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT datac (516:516:516) (596:596:596)) - (PORT datad (439:439:439) (501:501:501)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) - (DELAY - (ABSOLUTE - (PORT dataa (701:701:701) (832:832:832)) - (PORT datab (949:949:949) (1092:1092:1092)) - (PORT datac (463:463:463) (538:538:538)) - (PORT datad (485:485:485) (557:557:557)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (725:725:725)) - (PORT datab (811:811:811) (957:957:957)) - (PORT datac (790:790:790) (926:926:926)) - (PORT datad (647:647:647) (768:768:768)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (139:139:139)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datac (169:169:169) (199:199:199)) - (PORT datad (529:529:529) (616:616:616)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (233:233:233)) - (PORT datab (281:281:281) (330:330:330)) - (PORT datac (293:293:293) (335:335:335)) - (PORT datad (367:367:367) (434:434:434)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (146:146:146)) - (PORT datab (118:118:118) (152:152:152)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (348:348:348) (405:405:405)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (837:837:837)) - (PORT datab (949:949:949) (1092:1092:1092)) - (PORT datac (290:290:290) (340:340:340)) - (PORT datad (642:642:642) (735:735:735)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1258:1258:1258) (1450:1450:1450)) - (PORT datab (1218:1218:1218) (1432:1432:1432)) - (PORT datac (765:765:765) (897:897:897)) - (PORT datad (98:98:98) (119:119:119)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (655:655:655)) - (PORT datab (779:779:779) (907:907:907)) - (PORT datac (959:959:959) (1127:1127:1127)) - (PORT datad (945:945:945) (1100:1100:1100)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (495:495:495) (576:576:576)) - (PORT datab (328:328:328) (386:386:386)) - (PORT datac (409:409:409) (472:472:472)) - (PORT datad (852:852:852) (1002:1002:1002)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (713:713:713)) - (PORT datab (343:343:343) (408:408:408)) - (PORT datac (459:459:459) (528:528:528)) - (PORT datad (331:331:331) (384:384:384)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT dataa (494:494:494) (589:589:589)) - (PORT datab (490:490:490) (564:564:564)) - (PORT datac (693:693:693) (788:788:788)) - (PORT datad (677:677:677) (778:778:778)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (231:231:231)) - (PORT datab (384:384:384) (457:457:457)) - (PORT datac (295:295:295) (337:337:337)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (870:870:870)) - (PORT datab (488:488:488) (558:558:558)) - (PORT datac (637:637:637) (731:731:731)) - (PORT datad (745:745:745) (855:855:855)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) - (DELAY - (ABSOLUTE - (PORT dataa (748:748:748) (865:865:865)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (395:395:395) (454:454:454)) - (PORT datad (742:742:742) (851:851:851)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (967:967:967)) - (PORT datab (853:853:853) (991:991:991)) - (PORT datac (638:638:638) (728:728:728)) - (PORT datad (775:775:775) (888:888:888)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (179:179:179) (220:220:220)) - (PORT datab (682:682:682) (818:818:818)) - (PORT datac (638:638:638) (769:769:769)) - (PORT datad (544:544:544) (622:622:622)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (562:562:562)) - (PORT datab (341:341:341) (404:404:404)) - (PORT datac (179:179:179) (213:213:213)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (538:538:538) (609:609:609)) - (PORT datad (343:343:343) (400:400:400)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (615:615:615)) - (PORT datab (121:121:121) (152:152:152)) - (PORT datac (550:550:550) (651:651:651)) - (PORT datad (348:348:348) (405:405:405)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (127:127:127) (162:162:162)) - (PORT datab (503:503:503) (591:591:591)) - (PORT datac (99:99:99) (125:125:125)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal72\~2) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (653:653:653)) - (PORT datab (541:541:541) (647:647:647)) - (PORT datac (1239:1239:1239) (1425:1425:1425)) - (PORT datad (309:309:309) (365:365:365)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (693:693:693)) - (PORT datab (1254:1254:1254) (1443:1443:1443)) - (PORT datac (308:308:308) (364:364:364)) - (PORT datad (305:305:305) (362:362:362)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (544:544:544) (654:654:654)) - (PORT datab (538:538:538) (644:644:644)) - (PORT datac (1241:1241:1241) (1427:1427:1427)) - (PORT datad (309:309:309) (366:366:366)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (783:783:783)) - (PORT datab (637:637:637) (728:728:728)) - (PORT datac (476:476:476) (552:552:552)) - (PORT datad (577:577:577) (654:654:654)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~3) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (701:701:701)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (544:544:544) (617:617:617)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (399:399:399)) - (PORT datab (111:111:111) (142:142:142)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (783:783:783) (881:881:881)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (436:436:436) (504:504:504)) - (PORT datab (358:358:358) (421:421:421)) - (PORT datac (469:469:469) (546:546:546)) - (PORT datad (349:349:349) (410:410:410)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (350:350:350) (410:410:410)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (344:344:344) (396:396:396)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) - (DELAY - (ABSOLUTE - (PORT dataa (766:766:766) (889:889:889)) - (PORT datab (732:732:732) (860:860:860)) - (PORT datac (851:851:851) (984:984:984)) - (PORT datad (722:722:722) (834:834:834)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (429:429:429)) - (PORT datab (119:119:119) (153:153:153)) - (PORT datac (164:164:164) (200:200:200)) - (PORT datad (100:100:100) (122:122:122)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (226:226:226)) - (PORT datab (459:459:459) (531:531:531)) - (PORT datac (293:293:293) (343:343:343)) - (PORT datad (105:105:105) (123:123:123)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (853:853:853)) - (PORT datab (655:655:655) (764:764:764)) - (PORT datac (620:620:620) (731:731:731)) - (PORT datad (654:654:654) (782:782:782)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (132:132:132) (162:162:162)) - (PORT datac (837:837:837) (974:974:974)) - (PORT datad (281:281:281) (324:324:324)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (990:990:990)) - (PORT datab (339:339:339) (398:398:398)) - (PORT datac (445:445:445) (509:509:509)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (429:429:429) (494:494:494)) - (PORT datab (452:452:452) (527:527:527)) - (PORT datac (599:599:599) (679:679:679)) - (PORT datad (262:262:262) (299:299:299)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (485:485:485) (561:561:561)) - (PORT datab (110:110:110) (142:142:142)) - (PORT datac (451:451:451) (527:527:527)) - (PORT datad (461:461:461) (532:532:532)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (674:674:674)) - (PORT datab (604:604:604) (701:701:701)) - (PORT datac (427:427:427) (492:492:492)) - (PORT datad (463:463:463) (536:536:536)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (561:561:561)) - (PORT datab (613:613:613) (714:714:714)) - (PORT datac (921:921:921) (1031:1031:1031)) - (PORT datad (722:722:722) (825:825:825)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (241:241:241)) - (PORT datab (126:126:126) (159:159:159)) - (PORT datac (580:580:580) (673:673:673)) - (PORT datad (883:883:883) (1003:1003:1003)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (353:353:353)) - (PORT datab (134:134:134) (170:170:170)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (364:364:364)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (450:450:450) (514:514:514)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (472:472:472) (556:556:556)) - (PORT datab (1219:1219:1219) (1433:1433:1433)) - (PORT datac (915:915:915) (1050:1050:1050)) - (PORT datad (466:466:466) (545:545:545)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (425:425:425)) - (PORT datab (1326:1326:1326) (1544:1544:1544)) - (PORT datac (614:614:614) (724:724:724)) - (PORT datad (351:351:351) (413:413:413)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (180:180:180) (221:221:221)) - (PORT datab (196:196:196) (237:237:237)) - (PORT datac (329:329:329) (386:386:386)) - (PORT datad (442:442:442) (502:502:502)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (544:544:544)) - (PORT datab (303:303:303) (355:355:355)) - (PORT datac (487:487:487) (567:567:567)) - (PORT datad (448:448:448) (516:516:516)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) - (DELAY - (ABSOLUTE - (PORT dataa (451:451:451) (526:526:526)) - (PORT datab (548:548:548) (642:642:642)) - (PORT datac (513:513:513) (593:593:593)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (230:230:230)) - (PORT datab (476:476:476) (553:553:553)) - (PORT datac (296:296:296) (338:338:338)) - (PORT datad (341:341:341) (393:393:393)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (148:148:148)) - (PORT datab (117:117:117) (150:150:150)) - (PORT datac (435:435:435) (497:497:497)) - (PORT datad (333:333:333) (381:381:381)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (424:424:424)) - (PORT datab (369:369:369) (439:439:439)) - (PORT datac (105:105:105) (127:127:127)) - (PORT datad (102:102:102) (118:118:118)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) - (DELAY - (ABSOLUTE - (PORT dataa (1169:1169:1169) (1354:1354:1354)) - (PORT datab (186:186:186) (223:223:223)) - (PORT datac (853:853:853) (991:991:991)) - (PORT datad (357:357:357) (416:416:416)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1082:1082:1082)) - (PORT datab (645:645:645) (775:775:775)) - (PORT datac (450:450:450) (520:520:520)) - (PORT datad (651:651:651) (783:783:783)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (400:400:400)) - (PORT datab (709:709:709) (843:843:843)) - (PORT datac (992:992:992) (1131:1131:1131)) - (PORT datad (589:589:589) (691:691:691)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1010:1010:1010) (1149:1149:1149)) - (PORT datab (807:807:807) (952:952:952)) - (PORT datac (736:736:736) (856:856:856)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (718:718:718)) - (PORT datab (708:708:708) (841:841:841)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (711:711:711) (806:806:806)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (377:377:377)) - (PORT datab (529:529:529) (615:615:615)) - (PORT datac (273:273:273) (318:318:318)) - (PORT datad (883:883:883) (1007:1007:1007)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (317:317:317) (380:380:380)) - (PORT datab (650:650:650) (744:744:744)) - (PORT datac (677:677:677) (775:775:775)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (380:380:380)) - (PORT datab (576:576:576) (660:660:660)) - (PORT datac (302:302:302) (356:356:356)) - (PORT datad (88:88:88) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1082:1082:1082)) - (PORT datab (111:111:111) (142:142:142)) - (PORT datac (261:261:261) (300:300:300)) - (PORT datad (650:650:650) (749:749:749)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (667:667:667)) - (PORT datab (577:577:577) (664:664:664)) - (PORT datac (449:449:449) (518:518:518)) - (PORT datad (482:482:482) (561:561:561)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (223:223:223)) - (PORT datab (111:111:111) (143:143:143)) - (PORT datac (97:97:97) (123:123:123)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (716:716:716)) - (PORT datab (685:685:685) (799:799:799)) - (PORT datac (453:453:453) (513:513:513)) - (PORT datad (557:557:557) (636:636:636)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datac (536:536:536) (606:606:606)) - (PORT datad (102:102:102) (120:120:120)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT datab (114:114:114) (146:146:146)) - (PORT datac (106:106:106) (129:129:129)) - (PORT datad (98:98:98) (120:120:120)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (498:498:498) (587:587:587)) - (PORT datab (104:104:104) (134:134:134)) - (PORT datac (626:626:626) (720:720:720)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) - (DELAY - (ABSOLUTE - (PORT dataa (471:471:471) (552:552:552)) - (PORT datab (444:444:444) (506:506:506)) - (PORT datac (443:443:443) (503:503:503)) - (PORT datad (92:92:92) (112:112:112)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (495:495:495) (574:574:574)) - (PORT datab (335:335:335) (397:397:397)) - (PORT datac (328:328:328) (373:373:373)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (717:717:717) (860:860:860)) - (PORT datab (515:515:515) (598:598:598)) - (PORT datac (610:610:610) (695:695:695)) - (PORT datad (745:745:745) (877:877:877)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (560:560:560)) - (PORT datab (481:481:481) (567:567:567)) - (PORT datac (679:679:679) (779:779:779)) - (PORT datad (589:589:589) (679:679:679)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (674:674:674)) - (PORT datab (109:109:109) (139:139:139)) - (PORT datac (469:469:469) (543:543:543)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (543:543:543)) - (PORT datab (462:462:462) (534:534:534)) - (PORT datac (583:583:583) (671:671:671)) - (PORT datad (166:166:166) (196:196:196)) + (PORT dataa (483:483:483) (566:566:566)) + (PORT datab (377:377:377) (447:447:447)) + (PORT datac (546:546:546) (641:641:641)) + (PORT datad (345:345:345) (406:406:406)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -17302,61 +14468,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (147:147:147)) - (PORT datab (369:369:369) (438:438:438)) - (PORT datac (441:441:441) (511:511:511)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (408:408:408)) - (PORT datab (145:145:145) (195:195:195)) - (PORT datac (136:136:136) (181:181:181)) - (PORT datad (132:132:132) (172:172:172)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (579:579:579)) - (PORT datab (680:680:680) (793:793:793)) - (PORT datac (556:556:556) (645:645:645)) - (PORT datad (538:538:538) (610:610:610)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) (DELAY (ABSOLUTE (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (646:646:646) (742:742:742)) - (PORT datac (556:556:556) (645:645:645)) - (PORT datad (94:94:94) (113:113:113)) + (PORT datab (383:383:383) (458:458:458)) + (PORT datac (538:538:538) (636:636:636)) + (PORT datad (919:919:919) (1050:1050:1050)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -17366,14 +14484,106 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) (DELAY (ABSOLUTE - (PORT dataa (280:280:280) (334:334:334)) - (PORT datab (345:345:345) (405:405:405)) - (PORT datac (511:511:511) (594:594:594)) - (PORT datad (413:413:413) (468:468:468)) + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (173:173:173) (210:210:210)) + (PORT datac (343:343:343) (396:396:396)) + (PORT datad (183:183:183) (213:213:213)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) + (DELAY + (ABSOLUTE + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~42) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (404:404:404)) + (PORT datac (176:176:176) (211:211:211)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (668:668:668)) + (PORT datab (610:610:610) (722:722:722)) + (PORT datac (648:648:648) (744:744:744)) + (PORT datad (838:838:838) (993:993:993)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~41) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (161:161:161)) + (PORT datab (330:330:330) (390:390:390)) + (PORT datac (110:110:110) (135:135:135)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (281:281:281)) + (PORT datab (508:508:508) (586:586:586)) + (PORT datac (652:652:652) (766:766:766)) + (PORT datad (149:149:149) (193:193:193)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (698:698:698)) + (PORT datab (122:122:122) (152:152:152)) + (PORT datac (106:106:106) (136:136:136)) + (PORT datad (491:491:491) (559:559:559)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -17382,13 +14592,109 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) (DELAY (ABSOLUTE - (PORT dataa (443:443:443) (509:509:509)) - (PORT datab (450:450:450) (520:520:520)) + (PORT dataa (808:808:808) (935:935:935)) + (PORT datab (101:101:101) (129:129:129)) (PORT datac (88:88:88) (109:109:109)) - (PORT datad (92:92:92) (110:110:110)) + (PORT datad (916:916:916) (1058:1058:1058)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (698:698:698)) + (PORT datab (124:124:124) (156:156:156)) + (PORT datac (106:106:106) (136:136:136)) + (PORT datad (315:315:315) (367:367:367)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (529:529:529)) + (PORT datab (627:627:627) (716:716:716)) + (PORT datac (177:177:177) (212:212:212)) + (PORT datad (470:470:470) (537:537:537)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (741:741:741)) + (PORT datab (191:191:191) (229:229:229)) + (PORT datac (157:157:157) (183:183:183)) + (PORT datad (88:88:88) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (166:166:166) (197:197:197)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (432:432:432)) + (PORT datab (211:211:211) (252:252:252)) + (PORT datac (603:603:603) (696:696:696)) + (PORT datad (467:467:467) (541:541:541)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (434:434:434)) + (PORT datab (519:519:519) (612:612:612)) + (PORT datac (622:622:622) (717:717:717)) + (PORT datad (972:972:972) (1106:1106:1106)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -17398,29 +14704,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) (DELAY (ABSOLUTE - (PORT dataa (613:613:613) (720:720:720)) - (PORT datab (1041:1041:1041) (1203:1203:1203)) - (PORT datac (667:667:667) (751:751:751)) - (PORT datad (891:891:891) (1017:1017:1017)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (119:119:119) (150:150:150)) - (PORT datab (836:836:836) (953:953:953)) - (PORT datac (288:288:288) (341:341:341)) - (PORT datad (718:718:718) (813:813:813)) + (PORT dataa (189:189:189) (225:225:225)) + (PORT datab (622:622:622) (722:722:722)) + (PORT datac (564:564:564) (638:638:638)) + (PORT datad (665:665:665) (757:757:757)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -17430,104 +14720,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) (DELAY (ABSOLUTE - (PORT dataa (462:462:462) (544:544:544)) - (PORT datab (310:310:310) (363:363:363)) - (PORT datac (290:290:290) (330:330:330)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (538:538:538) (616:616:616)) - (PORT datad (464:464:464) (536:536:536)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (441:441:441)) - (PORT datab (573:573:573) (665:665:665)) - (PORT datac (635:635:635) (729:729:729)) - (PORT datad (450:450:450) (515:515:515)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (944:944:944)) - (PORT datab (938:938:938) (1091:1091:1091)) - (PORT datac (636:636:636) (729:729:729)) - (PORT datad (472:472:472) (536:536:536)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (951:951:951)) - (PORT datab (110:110:110) (140:140:140)) - (PORT datac (394:394:394) (453:453:453)) - (PORT datad (921:921:921) (1066:1066:1066)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (485:485:485) (580:580:580)) - (PORT datab (807:807:807) (951:951:951)) - (PORT datac (970:970:970) (1144:1144:1144)) - (PORT datad (613:613:613) (723:723:723)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (101:101:101) (123:123:123)) + (PORT dataa (364:364:364) (433:433:433)) + (PORT datab (484:484:484) (569:569:569)) + (PORT datac (501:501:501) (593:593:593)) (PORT datad (161:161:161) (189:189:189)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) @@ -17538,15 +14736,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) (DELAY (ABSOLUTE - (PORT dataa (484:484:484) (560:560:560)) - (PORT datab (592:592:592) (686:686:686)) - (PORT datac (597:597:597) (699:699:699)) - (PORT datad (852:852:852) (977:977:977)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (514:514:514) (605:605:605)) + (PORT datab (488:488:488) (571:571:571)) + (PORT datac (760:760:760) (876:876:876)) + (PORT datad (474:474:474) (551:551:551)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (DELAY + (ABSOLUTE + (PORT dataa (779:779:779) (905:905:905)) + (PORT datab (509:509:509) (608:608:608)) + (PORT datac (166:166:166) (201:201:201)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (159:159:159)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (315:315:315) (360:360:360)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (777:777:777)) + (PORT datab (652:652:652) (755:755:755)) + (PORT datac (192:192:192) (227:227:227)) + (PORT datad (645:645:645) (746:746:746)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -17554,13 +14800,1406 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) (DELAY (ABSOLUTE - (PORT dataa (455:455:455) (524:524:524)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (102:102:102) (124:124:124)) + (PORT dataa (605:605:605) (700:700:700)) + (PORT datab (652:652:652) (754:754:754)) (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (609:609:609)) + (PORT datab (483:483:483) (568:568:568)) + (PORT datac (347:347:347) (408:408:408)) + (PORT datad (864:864:864) (1021:1021:1021)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (288:288:288)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (430:430:430) (494:494:494)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (876:876:876)) + (PORT datab (624:624:624) (715:715:715)) + (PORT datac (785:785:785) (899:899:899)) + (PORT datad (466:466:466) (543:543:543)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (456:456:456) (518:518:518)) + (PORT datac (160:160:160) (188:188:188)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (560:560:560)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (317:317:317) (362:362:362)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (741:741:741)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (291:291:291) (331:331:331)) + (PORT datad (295:295:295) (341:341:341)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (693:693:693)) + (PORT datab (110:110:110) (142:142:142)) + (PORT datac (579:579:579) (653:653:653)) + (PORT datad (100:100:100) (122:122:122)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (1089:1089:1089)) + (PORT datab (473:473:473) (548:548:548)) + (PORT datac (1407:1407:1407) (1624:1624:1624)) + (PORT datad (834:834:834) (989:989:989)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (356:356:356)) + (PORT datab (298:298:298) (346:346:346)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (631:631:631) (718:718:718)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~40) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (404:404:404)) + (PORT datac (175:175:175) (210:210:210)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (154:154:154)) + (PORT datab (112:112:112) (145:145:145)) + (PORT datac (579:579:579) (652:652:652)) + (PORT datad (628:628:628) (724:724:724)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (744:744:744)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (285:285:285) (332:332:332)) + (PORT datad (212:212:212) (249:249:249)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (710:710:710)) + (PORT datab (608:608:608) (701:701:701)) + (PORT datac (590:590:590) (677:677:677)) + (PORT datad (648:648:648) (752:752:752)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (386:386:386) (469:469:469)) + (PORT datad (189:189:189) (220:220:220)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (527:527:527) (619:619:619)) + (PORT datac (375:375:375) (447:447:447)) + (PORT datad (174:174:174) (206:206:206)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[0\]) + (DELAY + (ABSOLUTE + (PORT datac (541:541:541) (617:617:617)) + (PORT datad (498:498:498) (573:573:573)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (93:93:93) (113:113:113)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (920:920:920) (904:904:904)) + (PORT ena (1125:1125:1125) (1271:1271:1271)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (725:725:725)) + (PORT datab (549:549:549) (642:642:642)) + (PORT datac (382:382:382) (465:465:465)) + (PORT datad (107:107:107) (126:126:126)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (679:679:679) (746:746:746)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (535:535:535) (593:593:593)) + (PORT ena (636:636:636) (682:682:682)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (228:228:228)) + (PORT datab (381:381:381) (451:451:451)) + (PORT datad (655:655:655) (764:764:764)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (405:405:405) (481:481:481)) + (PORT datac (119:119:119) (160:160:160)) + (PORT datad (339:339:339) (396:396:396)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (441:441:441) (521:521:521)) + (PORT datab (207:207:207) (245:245:245)) + (PORT datac (103:103:103) (125:125:125)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (527:527:527) (618:618:618)) + (PORT datac (376:376:376) (448:448:448)) + (PORT datad (174:174:174) (205:205:205)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT datab (204:204:204) (241:241:241)) + (PORT datad (176:176:176) (210:210:210)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (928:928:928)) + (PORT asdata (279:279:279) (298:298:298)) + (PORT clrn (927:927:927) (909:909:909)) + (PORT ena (1168:1168:1168) (1321:1321:1321)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (664:664:664)) + (PORT datab (635:635:635) (731:731:731)) + (PORT datac (426:426:426) (498:498:498)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (253:253:253)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (128:128:128) (169:169:169)) + (PORT datad (167:167:167) (198:198:198)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (469:469:469)) + (PORT datab (528:528:528) (619:619:619)) + (PORT datac (344:344:344) (405:405:405)) + (PORT datad (277:277:277) (315:315:315)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (342:342:342)) + (PORT datad (114:114:114) (137:137:137)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (102:102:102) (119:119:119)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (928:928:928) (909:909:909)) + (PORT ena (1169:1169:1169) (1320:1320:1320)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (635:635:635) (730:730:730)) + (PORT datac (548:548:548) (641:641:641)) + (PORT datad (207:207:207) (252:252:252)) + (IOPATH dataa combout (181:181:181) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (249:249:249)) + (PORT datab (605:605:605) (698:698:698)) + (PORT datac (589:589:589) (671:671:671)) + (PORT datad (652:652:652) (757:757:757)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (720:720:720)) + (PORT datab (545:545:545) (637:637:637)) + (PORT datac (540:540:540) (631:631:631)) + (PORT datad (619:619:619) (706:706:706)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (442:442:442) (522:522:522)) + (PORT datab (758:758:758) (874:874:874)) + (PORT datac (381:381:381) (464:464:464)) + (PORT datad (192:192:192) (224:224:224)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT datab (107:107:107) (138:138:138)) + (PORT datac (169:169:169) (201:201:201)) + (PORT datad (132:132:132) (170:170:170)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT asdata (747:747:747) (829:829:829)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT asdata (748:748:748) (829:829:829)) + (PORT ena (669:669:669) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (279:279:279)) + (PORT datab (311:311:311) (370:370:370)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (443:443:443) (510:510:510)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (736:736:736) (793:793:793)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (621:621:621) (686:686:686)) + (PORT ena (660:660:660) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (387:387:387)) + (PORT datab (444:444:444) (522:522:522)) + (PORT datad (348:348:348) (407:407:407)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (918:918:918)) + (PORT asdata (644:644:644) (719:719:719)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (918:918:918)) + (PORT asdata (644:644:644) (719:719:719)) + (PORT ena (644:644:644) (698:698:698)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (433:433:433)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (195:195:195) (229:229:229)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (440:440:440) (507:507:507)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (794:794:794) (880:880:880)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (625:625:625) (689:689:689)) + (PORT ena (631:631:631) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (580:580:580)) + (PORT datab (322:322:322) (376:376:376)) + (PORT datac (285:285:285) (331:331:331)) + (PORT datad (877:877:877) (1019:1019:1019)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (626:626:626)) + (PORT datab (313:313:313) (361:361:361)) + (PORT datac (549:549:549) (639:639:639)) + (PORT datad (490:490:490) (559:559:559)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (371:371:371) (440:440:440)) + (PORT datac (91:91:91) (112:112:112)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (326:326:326)) + (PORT datab (322:322:322) (378:378:378)) + (PORT datac (466:466:466) (543:543:543)) + (PORT datad (317:317:317) (372:372:372)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (412:412:412)) + (PORT datab (350:350:350) (409:409:409)) + (PORT datac (661:661:661) (758:758:758)) + (PORT datad (311:311:311) (362:362:362)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (327:327:327) (384:384:384)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (DELAY + (ABSOLUTE + (PORT datab (790:790:790) (915:915:915)) + (PORT datac (670:670:670) (778:778:778)) + (PORT datad (466:466:466) (542:542:542)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT datab (791:791:791) (916:916:916)) + (PORT datac (674:674:674) (783:783:783)) + (PORT datad (465:465:465) (533:533:533)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT datab (789:789:789) (914:914:914)) + (PORT datac (665:665:665) (773:773:773)) + (PORT datad (465:465:465) (533:533:533)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (548:548:548) (616:616:616)) + (PORT ena (515:515:515) (556:556:556)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) + (DELAY + (ABSOLUTE + (PORT datab (789:789:789) (914:914:914)) + (PORT datac (666:666:666) (774:774:774)) + (PORT datad (468:468:468) (544:544:544)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (551:551:551) (620:620:620)) + (PORT ena (506:506:506) (537:537:537)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (256:256:256) (309:309:309)) + (PORT datab (268:268:268) (320:320:320)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT datab (790:790:790) (915:915:915)) + (PORT datac (669:669:669) (777:777:777)) + (PORT datad (578:578:578) (662:662:662)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT datab (791:791:791) (916:916:916)) + (PORT datac (673:673:673) (782:782:782)) + (PORT datad (549:549:549) (646:646:646)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (623:623:623) (692:692:692)) + (PORT ena (759:759:759) (842:842:842)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) + (DELAY + (ABSOLUTE + (PORT datab (791:791:791) (916:916:916)) + (PORT datac (672:672:672) (781:781:781)) + (PORT datad (578:578:578) (661:661:661)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (625:625:625) (694:694:694)) + (PORT ena (753:753:753) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT datab (793:793:793) (918:918:918)) + (PORT datac (678:678:678) (788:788:788)) + (PORT datad (547:547:547) (644:644:644)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (624:624:624)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (498:498:498) (596:596:596)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT datab (669:669:669) (791:791:791)) + (PORT datac (488:488:488) (577:577:577)) + (PORT datad (488:488:488) (567:567:567)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (638:638:638) (715:715:715)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (609:609:609)) + (PORT datab (669:669:669) (792:792:792)) + (PORT datad (480:480:480) (558:558:558)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (730:730:730)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (1031:1031:1031) (1204:1204:1204)) + (PORT datad (110:110:110) (135:135:135)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (539:539:539)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (339:339:339) (401:401:401)) + (PORT datad (482:482:482) (558:558:558)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (949:949:949)) + (PORT datac (442:442:442) (513:513:513)) + (PORT datad (617:617:617) (712:712:712)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (537:537:537) (596:596:596)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (952:952:952)) + (PORT datac (443:443:443) (515:515:515)) + (PORT datad (619:619:619) (714:714:714)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (683:683:683)) + (PORT datab (650:650:650) (752:752:752)) + (PORT datad (129:129:129) (157:157:157)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (370:370:370) (434:434:434)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (DELAY + (ABSOLUTE + (PORT datab (613:613:613) (713:713:713)) + (PORT datac (756:756:756) (883:883:883)) + (PORT datad (454:454:454) (522:522:522)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (605:605:605)) + (PORT datab (669:669:669) (791:791:791)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (264:264:264)) + (PORT datab (506:506:506) (605:605:605)) + (PORT datac (635:635:635) (735:735:735)) + (PORT datad (354:354:354) (415:415:415)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) + (DELAY + (ABSOLUTE + (PORT datac (795:795:795) (928:928:928)) + (PORT datad (618:618:618) (713:713:713)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (764:764:764)) + (PORT datab (431:431:431) (504:504:504)) + (PORT datac (626:626:626) (722:722:722)) + (PORT datad (370:370:370) (430:430:430)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (810:810:810) (913:913:913)) + (PORT ena (582:582:582) (618:618:618)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (DELAY + (ABSOLUTE + (PORT datab (613:613:613) (713:713:713)) + (PORT datac (756:756:756) (883:883:883)) + (PORT datad (453:453:453) (522:522:522)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (257:257:257)) + (PORT datab (483:483:483) (564:564:564)) + (PORT datad (193:193:193) (221:221:221)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (268:268:268)) + (PORT datab (779:779:779) (899:899:899)) + (PORT datac (628:628:628) (727:727:727)) + (PORT datad (351:351:351) (412:412:412)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -17570,13 +16209,2274 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~1) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) (DELAY (ABSOLUTE - (PORT dataa (728:728:728) (836:836:836)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (708:708:708) (806:806:806)) - (PORT datad (446:446:446) (516:516:516)) + (PORT dataa (633:633:633) (737:737:737)) + (PORT datab (432:432:432) (506:506:506)) + (PORT datac (632:632:632) (729:729:729)) + (PORT datad (375:375:375) (435:435:435)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (776:776:776) (851:851:851)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1180:1180:1180)) + (PORT datab (530:530:530) (614:614:614)) + (PORT datac (805:805:805) (923:923:923)) + (PORT datad (1092:1092:1092) (1244:1244:1244)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (391:391:391)) + (PORT datab (688:688:688) (797:797:797)) + (PORT datac (1033:1033:1033) (1205:1205:1205)) + (PORT datad (605:605:605) (696:696:696)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (421:421:421)) + (PORT datab (500:500:500) (585:585:585)) + (PORT datac (474:474:474) (552:552:552)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (646:646:646) (737:737:737)) + (PORT datad (109:109:109) (133:133:133)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (461:461:461)) + (PORT datab (107:107:107) (136:136:136)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (627:627:627) (725:725:725)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (DELAY + (ABSOLUTE + (PORT datab (502:502:502) (587:587:587)) + (PORT datac (301:301:301) (353:353:353)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (547:547:547)) + (PORT datac (614:614:614) (717:717:717)) + (PORT datad (449:449:449) (516:516:516)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (810:810:810) (913:913:913)) + (PORT ena (673:673:673) (745:745:745)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (545:545:545)) + (PORT datac (610:610:610) (713:713:713)) + (PORT datad (450:450:450) (517:517:517)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (685:685:685)) + (PORT datab (736:736:736) (875:875:875)) + (PORT datad (454:454:454) (523:523:523)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (415:415:415)) + (PORT datab (700:700:700) (833:833:833)) + (PORT datac (634:634:634) (734:734:734)) + (PORT datad (197:197:197) (238:238:238)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (539:539:539) (600:600:600)) + (PORT ena (627:627:627) (675:675:675)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (265:265:265)) + (PORT datab (697:697:697) (830:830:830)) + (PORT datac (633:633:633) (732:732:732)) + (PORT datad (353:353:353) (414:414:414)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (417:417:417)) + (PORT datab (695:695:695) (827:827:827)) + (PORT datac (630:630:630) (729:729:729)) + (PORT datad (200:200:200) (241:241:241)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (538:538:538) (599:599:599)) + (PORT ena (670:670:670) (742:742:742)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (264:264:264)) + (PORT datab (700:700:700) (832:832:832)) + (PORT datac (635:635:635) (734:734:734)) + (PORT datad (354:354:354) (415:415:415)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (272:272:272)) + (PORT datab (898:898:898) (1047:1047:1047)) + (PORT datad (644:644:644) (749:749:749)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (386:386:386)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (415:415:415) (471:471:471)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (393:393:393)) + (PORT datab (172:172:172) (210:210:210)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (334:334:334) (392:392:392)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (599:599:599)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (346:346:346) (396:396:396)) + (PORT datad (416:416:416) (473:473:473)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (699:699:699)) + (PORT datab (459:459:459) (531:531:531)) + (PORT datac (116:116:116) (144:144:144)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (410:410:410)) + (PORT datab (458:458:458) (536:536:536)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (470:470:470) (548:548:548)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (145:145:145)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (955:955:955)) + (PORT datab (475:475:475) (575:575:575)) + (PORT datac (623:623:623) (711:711:711)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (872:872:872)) + (PORT datac (613:613:613) (716:716:716)) + (PORT datad (449:449:449) (516:516:516)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (679:679:679) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (659:659:659) (734:734:734)) + (PORT ena (515:515:515) (556:556:556)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (658:658:658) (734:734:734)) + (PORT ena (506:506:506) (537:537:537)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (256:256:256) (310:310:310)) + (PORT datab (267:267:267) (319:319:319)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (1077:1077:1077) (1197:1197:1197)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (609:609:609)) + (PORT datab (669:669:669) (792:792:792)) + (PORT datad (479:479:479) (557:557:557)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (923:923:923)) + (PORT asdata (286:286:286) (308:308:308)) + (PORT ena (776:776:776) (851:851:851)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (937:937:937) (1041:1041:1041)) + (PORT ena (673:673:673) (745:745:745)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (685:685:685)) + (PORT datab (357:357:357) (432:432:432)) + (PORT datad (459:459:459) (529:529:529)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (1203:1203:1203) (1346:1346:1346)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (528:528:528)) + (PORT datab (650:650:650) (752:752:752)) + (PORT datad (130:130:130) (158:158:158)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1082:1082:1082) (1206:1206:1206)) + (PORT ena (627:627:627) (675:675:675)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1084:1084:1084) (1208:1208:1208)) + (PORT ena (670:670:670) (742:742:742)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (266:266:266)) + (PORT datab (890:890:890) (1038:1038:1038)) + (PORT datad (642:642:642) (746:746:746)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (935:935:935) (1038:1038:1038)) + (PORT ena (582:582:582) (618:618:618)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (879:879:879) (1000:1000:1000)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (248:248:248)) + (PORT datab (482:482:482) (562:562:562)) + (PORT datad (462:462:462) (542:542:542)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (334:334:334) (392:392:392)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (1313:1313:1313) (1470:1470:1470)) + (PORT ena (753:753:753) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (1313:1313:1313) (1469:1469:1469)) + (PORT ena (759:759:759) (842:842:842)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (621:621:621)) + (PORT datab (514:514:514) (622:622:622)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (405:405:405)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (321:321:321) (375:375:375)) + (PORT datad (160:160:160) (183:183:183)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (602:602:602)) + (PORT datab (284:284:284) (333:333:333)) + (PORT datac (591:591:591) (692:692:692)) + (PORT datad (731:731:731) (840:840:840)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (542:542:542)) + (PORT datac (609:609:609) (712:712:712)) + (PORT datad (459:459:459) (536:536:536)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (542:542:542)) + (PORT datac (612:612:612) (714:714:714)) + (PORT datad (460:460:460) (536:536:536)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (923:923:923)) + (PORT asdata (768:768:768) (868:868:868)) + (PORT ena (480:480:480) (509:509:509)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (739:739:739)) + (PORT datab (446:446:446) (520:520:520)) + (PORT datac (613:613:613) (716:716:716)) + (PORT datad (460:460:460) (536:536:536)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (213:213:213) (257:257:257)) + (PORT datad (203:203:203) (241:241:241)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (871:871:871)) + (PORT datac (613:613:613) (715:715:715)) + (PORT datad (449:449:449) (516:516:516)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datac (428:428:428) (511:511:511)) + (PORT datad (343:343:343) (399:399:399)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (164:164:164)) + (PORT datab (122:122:122) (153:153:153)) + (PORT datac (589:589:589) (685:685:685)) + (PORT datad (115:115:115) (137:137:137)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (288:288:288)) + (PORT datab (150:150:150) (202:202:202)) + (PORT datac (723:723:723) (827:827:827)) + (PORT datad (95:95:95) (116:116:116)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (434:434:434) (466:466:466)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (504:504:504) (554:554:554)) + (PORT ena (753:753:753) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (504:504:504) (554:554:554)) + (PORT ena (759:759:759) (842:842:842)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (616:616:616)) + (PORT datab (516:516:516) (624:624:624)) + (PORT datad (115:115:115) (152:152:152)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (753:753:753) (853:853:853)) + (PORT ena (515:515:515) (556:556:556)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (749:749:749) (850:850:850)) + (PORT ena (506:506:506) (537:537:537)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (255:255:255) (309:309:309)) + (PORT datab (269:269:269) (321:321:321)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (691:691:691) (767:767:767)) + (PORT ena (670:670:670) (742:742:742)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (691:691:691) (768:768:768)) + (PORT ena (627:627:627) (675:675:675)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (258:258:258)) + (PORT datab (897:897:897) (1046:1046:1046)) + (PORT datad (644:644:644) (749:749:749)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (682:682:682) (746:746:746)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (645:645:645)) + (PORT datab (649:649:649) (751:751:751)) + (PORT datad (127:127:127) (156:156:156)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (463:463:463) (542:542:542)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (622:622:622) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (688:688:688) (764:764:764)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (184:184:184)) + (PORT datab (130:130:130) (163:163:163)) + (PORT datad (471:471:471) (549:549:549)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (356:356:356) (383:383:383)) + (PORT ena (747:747:747) (810:810:810)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (778:778:778) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (644:644:644)) + (PORT datab (720:720:720) (850:850:850)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (453:453:453) (524:524:524)) + (PORT datab (568:568:568) (676:676:676)) + (PORT datac (457:457:457) (544:544:544)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (512:512:512) (563:563:563)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (604:604:604)) + (PORT datab (669:669:669) (791:791:791)) + (PORT datad (488:488:488) (568:568:568)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (249:249:249)) + (PORT datab (466:466:466) (557:557:557)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (295:295:295) (341:341:341)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (524:524:524)) + (PORT datab (476:476:476) (550:550:550)) + (PORT datac (455:455:455) (546:546:546)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (923:923:923)) + (PORT asdata (451:451:451) (491:491:491)) + (PORT ena (482:482:482) (509:509:509)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (126:126:126) (160:160:160)) + (PORT datab (505:505:505) (574:574:574)) + (PORT datad (112:112:112) (133:133:133)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (127:127:127) (163:163:163)) + (PORT datac (116:116:116) (156:156:156)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (709:709:709)) + (PORT datab (442:442:442) (512:512:512)) + (PORT datac (104:104:104) (128:128:128)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (449:449:449)) + (PORT datac (424:424:424) (492:492:492)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (920:920:920) (904:904:904)) + (PORT ena (1159:1159:1159) (1318:1318:1318)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (293:293:293)) + (PORT datab (152:152:152) (204:204:204)) + (PORT datac (720:720:720) (824:824:824)) + (PORT datad (100:100:100) (121:121:121)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (136:136:136) (185:185:185)) + (PORT datad (166:166:166) (195:195:195)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (389:389:389) (459:459:459)) + (PORT datac (438:438:438) (508:508:508)) + (PORT datad (303:303:303) (347:347:347)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datab (185:185:185) (222:222:222)) + (PORT datac (481:481:481) (555:555:555)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (286:286:286) (329:329:329)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (920:920:920) (904:904:904)) + (PORT ena (1125:1125:1125) (1271:1271:1271)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (201:201:201)) + (PORT datab (154:154:154) (211:211:211)) + (PORT datac (729:729:729) (840:840:840)) + (PORT datad (166:166:166) (195:195:195)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (612:612:612) (684:684:684)) + (PORT ena (753:753:753) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (612:612:612) (684:684:684)) + (PORT ena (759:759:759) (842:842:842)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (617:617:617)) + (PORT datab (516:516:516) (623:623:623)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (1078:1078:1078) (1235:1235:1235)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (434:434:434) (502:502:502)) + (PORT datab (651:651:651) (753:753:753)) + (PORT datad (130:130:130) (159:159:159)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (806:806:806) (926:926:926)) + (PORT ena (582:582:582) (618:618:618)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (456:456:456) (544:544:544)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (248:248:248)) + (PORT datab (481:481:481) (561:561:561)) + (PORT datad (183:183:183) (228:228:228)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (573:573:573) (673:673:673)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (627:627:627) (675:675:675)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1123:1123:1123) (1280:1280:1280)) + (PORT ena (670:670:670) (742:742:742)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (365:365:365)) + (PORT datab (895:895:895) (1044:1044:1044)) + (PORT datad (643:643:643) (748:748:748)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (776:776:776) (851:851:851)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (805:805:805) (926:926:926)) + (PORT ena (673:673:673) (745:745:745)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (685:685:685)) + (PORT datab (371:371:371) (448:448:448)) + (PORT datad (462:462:462) (533:533:533)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (391:391:391)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (317:317:317) (374:374:374)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1225:1225:1225) (1404:1404:1404)) + (PORT ena (506:506:506) (537:537:537)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1227:1227:1227) (1407:1407:1407)) + (PORT ena (515:515:515) (556:556:556)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (257:257:257) (311:311:311)) + (PORT datab (132:132:132) (181:181:181)) + (PORT datad (245:245:245) (290:290:290)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (1237:1237:1237) (1417:1417:1417)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (605:605:605)) + (PORT datab (669:669:669) (791:791:791)) + (PORT datad (486:486:486) (565:565:565)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (440:440:440) (531:531:531)) + (PORT datab (297:297:297) (349:349:349)) + (PORT datac (292:292:292) (336:336:336)) + (PORT datad (462:462:462) (537:537:537)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (579:579:579)) + (PORT datab (202:202:202) (239:239:239)) + (PORT datac (489:489:489) (580:580:580)) + (PORT datad (730:730:730) (840:840:840)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (923:923:923)) + (PORT asdata (284:284:284) (306:306:306)) + (PORT ena (482:482:482) (509:509:509)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1080:1080:1080) (1264:1264:1264)) + (PORT datab (125:125:125) (156:156:156)) + (PORT datad (113:113:113) (135:135:135)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (434:434:434) (466:466:466)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (126:126:126) (160:160:160)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (185:185:185) (232:232:232)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (713:713:713)) + (PORT datab (283:283:283) (325:325:325)) + (PORT datac (108:108:108) (132:132:132)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (DELAY + (ABSOLUTE + (PORT datac (105:105:105) (128:128:128)) + (PORT datad (479:479:479) (549:549:549)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (276:276:276) (318:318:318)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (920:920:920) (904:904:904)) + (PORT ena (1125:1125:1125) (1271:1271:1271)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (206:206:206)) + (PORT datab (149:149:149) (204:204:204)) + (PORT datac (732:732:732) (843:843:843)) + (PORT datad (167:167:167) (196:196:196)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[11\]) + (DELAY + (ABSOLUTE + (PORT datab (328:328:328) (387:387:387)) + (PORT datad (499:499:499) (574:574:574)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (920:920:920) (904:904:904)) + (PORT ena (1125:1125:1125) (1271:1271:1271)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (145:145:145)) + (PORT datac (300:300:300) (361:361:361)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (679:679:679) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (923:923:923)) + (PORT asdata (389:389:389) (432:432:432)) + (PORT ena (480:480:480) (509:509:509)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (145:145:145)) + (PORT datab (210:210:210) (253:253:253)) + (PORT datad (206:206:206) (244:244:244)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (186:186:186)) + (PORT datac (465:465:465) (547:547:547)) + (PORT datad (340:340:340) (396:396:396)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (293:293:293) (339:339:339)) + (PORT datab (461:461:461) (536:536:536)) + (PORT datac (372:372:372) (442:442:442)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (389:389:389)) + (PORT datab (469:469:469) (565:565:565)) + (PORT datac (209:209:209) (254:254:254)) + (PORT datad (731:731:731) (840:840:840)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (484:484:484) (570:570:570)) + (PORT datab (118:118:118) (152:152:152)) + (PORT datac (628:628:628) (734:734:734)) + (PORT datad (329:329:329) (379:379:379)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (652:652:652)) + (PORT datab (1201:1201:1201) (1376:1376:1376)) + (PORT datac (377:377:377) (439:439:439)) + (PORT datad (981:981:981) (1147:1147:1147)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT datab (530:530:530) (628:628:628)) + (PORT datac (626:626:626) (726:726:726)) + (PORT datad (375:375:375) (446:446:446)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (419:419:419)) + (PORT datac (345:345:345) (409:409:409)) + (PORT datad (344:344:344) (397:397:397)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (419:419:419)) + (PORT datab (344:344:344) (416:416:416)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (301:301:301) (348:348:348)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (719:719:719)) + (PORT datab (730:730:730) (864:864:864)) + (PORT datac (331:331:331) (378:378:378)) + (PORT datad (608:608:608) (689:689:689)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (1387:1387:1387)) + (PORT datab (701:701:701) (819:819:819)) + (PORT datac (545:545:545) (643:643:643)) + (PORT datad (828:828:828) (966:966:966)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (657:657:657)) + (PORT datab (893:893:893) (1051:1051:1051)) + (PORT datac (617:617:617) (699:699:699)) + (PORT datad (358:358:358) (422:422:422)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1651:1651:1651)) + (PORT datab (887:887:887) (1038:1038:1038)) + (PORT datac (470:470:470) (547:547:547)) + (PORT datad (101:101:101) (124:124:124)) (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -17586,843 +18486,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~2) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) (DELAY (ABSOLUTE - (PORT dataa (496:496:496) (586:586:586)) - (PORT datab (398:398:398) (487:487:487)) - (PORT datac (361:361:361) (443:443:443)) - (PORT datad (566:566:566) (654:654:654)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT datab (699:699:699) (799:799:799)) - (PORT datac (350:350:350) (413:413:413)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (393:393:393)) - (PORT datab (723:723:723) (857:857:857)) - (PORT datac (564:564:564) (643:643:643)) - (PORT datad (95:95:95) (115:115:115)) + (PORT dataa (195:195:195) (235:235:235)) + (PORT datab (457:457:457) (533:533:533)) + (PORT datac (446:446:446) (511:511:511)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (1081:1081:1081) (1215:1215:1215)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (381:381:381) (461:461:461)) - (PORT datad (471:471:471) (550:550:550)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (425:425:425)) - (PORT datab (491:491:491) (571:571:571)) - (PORT datac (584:584:584) (681:681:681)) - (PORT datad (503:503:503) (582:582:582)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (537:537:537)) - (PORT datab (620:620:620) (719:719:719)) - (PORT datac (292:292:292) (341:341:341)) - (PORT datad (494:494:494) (581:581:581)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (727:727:727)) - (PORT datac (443:443:443) (510:510:510)) - (PORT datad (447:447:447) (509:509:509)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (399:399:399) (495:495:495)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (743:743:743) (861:861:861)) - (PORT datad (383:383:383) (463:463:463)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1082:1082:1082)) - (PORT datab (631:631:631) (740:740:740)) - (PORT datac (533:533:533) (608:608:608)) - (PORT datad (652:652:652) (784:784:784)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (402:402:402)) - (PORT datac (343:343:343) (400:400:400)) - (PORT datad (489:489:489) (565:565:565)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (691:691:691) (785:785:785)) - (PORT datac (344:344:344) (407:407:407)) - (PORT datad (477:477:477) (544:544:544)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT datac (166:166:166) (196:196:196)) - (PORT datad (299:299:299) (347:347:347)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (299:299:299) (349:349:349)) - (PORT datad (161:161:161) (190:190:190)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (915:915:915)) - (PORT asdata (459:459:459) (499:499:499)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (147:147:147) (194:194:194)) - (PORT datab (341:341:341) (397:397:397)) - (PORT datad (504:504:504) (611:611:611)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (505:505:505) (546:546:546)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (192:192:192) (230:230:230)) - (PORT datac (116:116:116) (157:157:157)) - (PORT datad (223:223:223) (263:263:263)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) - (DELAY - (ABSOLUTE - (PORT datac (852:852:852) (987:987:987)) - (PORT datad (345:345:345) (401:401:401)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (893:893:893)) - (PORT ena (1338:1338:1338) (1484:1484:1484)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (409:409:409)) - (PORT datab (349:349:349) (412:412:412)) - (PORT datac (606:606:606) (707:707:707)) - (PORT datad (98:98:98) (118:118:118)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (166:166:166) (174:174:174)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (350:350:350) (412:412:412)) - (PORT datac (956:956:956) (1134:1134:1134)) - (PORT datad (195:195:195) (231:231:231)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT asdata (692:692:692) (782:782:782)) - (PORT ena (433:433:433) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (793:793:793)) - (PORT datab (767:767:767) (885:885:885)) - (PORT datad (1023:1023:1023) (1176:1176:1176)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (681:681:681) (760:760:760)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (681:681:681) (760:760:760)) - (PORT ena (422:422:422) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) - (DELAY - (ABSOLUTE - (PORT datab (1017:1017:1017) (1186:1186:1186)) - (PORT datac (568:568:568) (654:654:654)) - (PORT datad (896:896:896) (1032:1032:1032)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (274:274:274)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (210:210:210) (248:248:248)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (705:705:705) (803:803:803)) - (PORT ena (494:494:494) (536:536:536)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (704:704:704) (802:802:802)) - (PORT ena (504:504:504) (535:535:535)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (287:287:287)) - (PORT datab (223:223:223) (271:271:271)) - (PORT datad (116:116:116) (152:152:152)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (806:806:806) (908:908:908)) - (PORT ena (631:631:631) (678:678:678)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (809:809:809) (911:911:911)) - (PORT ena (649:649:649) (709:709:709)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (261:261:261)) - (PORT datab (341:341:341) (394:394:394)) - (PORT datad (330:330:330) (375:375:375)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (774:774:774) (865:865:865)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (634:634:634) (712:712:712)) - (PORT ena (767:767:767) (833:833:833)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (306:306:306)) - (PORT datab (130:130:130) (178:178:178)) - (PORT datad (351:351:351) (412:412:412)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (531:531:531) (600:600:600)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (808:808:808)) - (PORT datab (741:741:741) (848:848:848)) - (PORT datad (202:202:202) (234:234:234)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (170:170:170) (207:207:207)) - (PORT datac (334:334:334) (396:396:396)) - (PORT datad (316:316:316) (369:369:369)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (647:647:647) (752:752:752)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT asdata (692:692:692) (782:782:782)) - (PORT ena (421:421:421) (441:441:441)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (274:274:274)) - (PORT datab (211:211:211) (251:251:251)) - (PORT datad (364:364:364) (436:436:436)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (358:358:358) (421:421:421)) - (PORT datac (317:317:317) (366:366:366)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (313:313:313) (374:374:374)) - (PORT datab (1141:1141:1141) (1346:1346:1346)) - (PORT datac (336:336:336) (389:389:389)) - (PORT datad (297:297:297) (344:344:344)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|im2\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (95:95:95) (114:114:114)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (895:895:895)) - (PORT ena (1043:1043:1043) (1160:1160:1160)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (262:262:262)) - (PORT datac (532:532:532) (605:605:605)) - (PORT datad (157:157:157) (207:207:207)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (260:260:260)) - (PORT datab (180:180:180) (217:217:217)) - (PORT datac (568:568:568) (643:643:643)) - (PORT datad (582:582:582) (660:660:660)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (294:294:294) (344:344:344)) - (PORT datac (686:686:686) (785:785:785)) - (PORT datad (349:349:349) (419:419:419)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (441:441:441)) - (PORT datab (577:577:577) (662:662:662)) - (PORT datac (681:681:681) (780:780:780)) - (PORT datad (710:710:710) (840:840:840)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) - (DELAY - (ABSOLUTE - (PORT dataa (719:719:719) (826:826:826)) - (PORT datab (706:706:706) (809:809:809)) - (PORT datac (1846:1846:1846) (2096:2096:2096)) - (PORT datad (381:381:381) (446:446:446)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (473:473:473) (549:549:549)) - (PORT datad (603:603:603) (701:701:701)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) (DELAY (ABSOLUTE - (PORT dataa (754:754:754) (886:886:886)) - (PORT datab (117:117:117) (151:151:151)) - (PORT datac (342:342:342) (403:403:403)) - (PORT datad (638:638:638) (760:760:760)) + (PORT dataa (331:331:331) (385:385:385)) + (PORT datab (672:672:672) (771:771:771)) + (PORT datac (289:289:289) (323:323:323)) + (PORT datad (323:323:323) (372:372:372)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (368:368:368)) + (PORT datab (621:621:621) (741:741:741)) + (PORT datac (290:290:290) (338:338:338)) + (PORT datad (504:504:504) (590:590:590)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -18432,93 +18534,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~12) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) (DELAY (ABSOLUTE - (PORT dataa (551:551:551) (636:636:636)) - (PORT datab (373:373:373) (444:444:444)) - (PORT datac (493:493:493) (565:565:565)) - (PORT datad (574:574:574) (658:658:658)) + (PORT dataa (143:143:143) (190:190:190)) + (PORT datac (88:88:88) (109:109:109)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (606:606:606)) - (PORT datab (870:870:870) (993:993:993)) - (PORT datac (1060:1060:1060) (1215:1215:1215)) - (PORT datad (575:575:575) (650:650:650)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (288:288:288) (332:332:332)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (322:322:322) (378:378:378)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (727:727:727)) - (PORT datab (365:365:365) (430:430:430)) - (PORT datac (601:601:601) (704:704:704)) - (PORT datad (479:479:479) (563:563:563)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (716:716:716)) - (PORT datab (117:117:117) (150:150:150)) - (PORT datac (107:107:107) (131:131:131)) - (PORT datad (459:459:459) (529:529:529)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (102:102:102) (131:131:131)) - (PORT datad (649:649:649) (743:743:743)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -18527,9 +18549,9 @@ (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (724:724:724)) - (PORT datac (611:611:611) (715:715:715)) - (PORT datad (649:649:649) (744:744:744)) + (PORT dataa (145:145:145) (193:193:193)) + (PORT datac (605:605:605) (725:725:725)) + (PORT datad (499:499:499) (585:585:585)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -18541,9 +18563,9 @@ (INSTANCE z80_\|alu_\|op2_high\[1\]) (DELAY (ABSOLUTE - (PORT clk (926:926:926) (911:911:911)) + (PORT clk (915:915:915) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (435:435:435) (467:467:467)) + (PORT ena (420:420:420) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -18557,10 +18579,10 @@ (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) (DELAY (ABSOLUTE - (PORT dataa (618:618:618) (726:726:726)) - (PORT datac (347:347:347) (396:396:396)) - (PORT datad (486:486:486) (572:572:572)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (533:533:533) (632:632:632)) + (PORT datac (191:191:191) (233:233:233)) + (PORT datad (371:371:371) (441:441:441)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -18571,7 +18593,55 @@ (INSTANCE z80_\|alu_\|op1_high\[1\]) (DELAY (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) + (PORT clk (916:916:916) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (422:422:422)) + (PORT datab (627:627:627) (749:749:749)) + (PORT datac (315:315:315) (362:362:362)) + (PORT datad (201:201:201) (247:247:247)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (194:194:194)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (297:297:297) (342:342:342)) + (PORT datad (498:498:498) (583:583:583)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (900:900:900)) (PORT d (37:37:37) (50:50:50)) (PORT ena (420:420:420) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) @@ -18584,15 +18654,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~3) + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) (DELAY (ABSOLUTE - (PORT dataa (475:475:475) (572:572:572)) - (PORT datab (554:554:554) (639:639:639)) - (PORT datac (492:492:492) (577:577:577)) - (PORT datad (465:465:465) (538:538:538)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (798:798:798) (920:920:920)) + (PORT datab (843:843:843) (982:982:982)) + (PORT datac (1035:1035:1035) (1198:1198:1198)) + (PORT datad (212:212:212) (252:252:252)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~20) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (925:925:925)) + (PORT datab (897:897:897) (1061:1061:1061)) + (PORT datac (580:580:580) (670:670:670)) + (PORT datad (732:732:732) (861:861:861)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (551:551:551)) + (PORT datab (527:527:527) (606:606:606)) + (PORT datac (462:462:462) (539:539:539)) + (PORT datad (351:351:351) (409:409:409)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -18600,13 +18702,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~2) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (440:440:440)) - (PORT datab (580:580:580) (666:666:666)) - (PORT datac (682:682:682) (781:781:781)) - (PORT datad (707:707:707) (837:837:837)) + (PORT dataa (253:253:253) (301:301:301)) + (PORT datab (660:660:660) (765:765:765)) + (PORT datac (501:501:501) (611:611:611)) + (PORT datad (786:786:786) (923:923:923)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -18616,60 +18718,752 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~9) + (INSTANCE z80_\|pla_decode_\|Equal61\~2) (DELAY (ABSOLUTE - (PORT dataa (603:603:603) (698:698:698)) - (PORT datab (473:473:473) (551:551:551)) - (PORT datad (614:614:614) (720:720:720)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (997:997:997) (1156:1156:1156)) + (PORT datab (779:779:779) (892:892:892)) + (PORT datac (909:909:909) (1065:1065:1065)) + (PORT datad (859:859:859) (1007:1007:1007)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (984:984:984) (1101:1101:1101)) - (PORT ena (631:631:631) (678:678:678)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT datab (1021:1021:1021) (1197:1197:1197)) + (PORT datac (945:945:945) (1094:1094:1094)) + (PORT datad (520:520:520) (608:608:608)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (985:985:985) (1102:1102:1102)) - (PORT ena (649:649:649) (709:709:709)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~70) + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) (DELAY (ABSOLUTE - (PORT dataa (342:342:342) (403:403:403)) - (PORT datab (132:132:132) (181:181:181)) - (PORT datad (333:333:333) (379:379:379)) + (PORT dataa (1015:1015:1015) (1160:1160:1160)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (471:471:471) (535:535:535)) + (PORT datad (427:427:427) (493:493:493)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (888:888:888)) + (PORT datab (980:980:980) (1147:1147:1147)) + (PORT datac (812:812:812) (935:935:935)) + (PORT datad (102:102:102) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (987:987:987)) + (PORT datab (517:517:517) (606:606:606)) + (PORT datac (100:100:100) (121:121:121)) + (PORT datad (108:108:108) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (145:145:145)) + (PORT datab (109:109:109) (139:139:139)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~22) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (1110:1110:1110)) + (PORT datab (448:448:448) (525:525:525)) + (PORT datac (731:731:731) (858:858:858)) + (PORT datad (1411:1411:1411) (1636:1636:1636)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (372:372:372)) + (PORT datab (132:132:132) (161:161:161)) + (PORT datac (120:120:120) (143:143:143)) + (PORT datad (490:490:490) (589:589:589)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (641:641:641)) + (PORT datab (892:892:892) (1024:1024:1024)) + (PORT datac (662:662:662) (770:770:770)) + (PORT datad (960:960:960) (1087:1087:1087)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (555:555:555)) + (PORT datab (511:511:511) (611:611:611)) + (PORT datac (117:117:117) (139:139:139)) + (PORT datad (487:487:487) (585:585:585)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (106:106:106) (130:130:130)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (770:770:770)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datac (1168:1168:1168) (1352:1352:1352)) + (PORT datad (796:796:796) (914:914:914)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (431:431:431)) + (PORT datab (826:826:826) (963:963:963)) + (PORT datac (824:824:824) (944:944:944)) + (PORT datad (340:340:340) (393:393:393)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (516:516:516)) + (PORT datab (828:828:828) (965:965:965)) + (PORT datac (869:869:869) (992:992:992)) + (PORT datad (821:821:821) (957:957:957)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (111:111:111) (142:142:142)) + (PORT datac (449:449:449) (518:518:518)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (586:586:586) (666:666:666)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal72\~2) + (DELAY + (ABSOLUTE + (PORT dataa (768:768:768) (908:908:908)) + (PORT datab (1306:1306:1306) (1524:1524:1524)) + (PORT datac (614:614:614) (714:714:714)) + (PORT datad (453:453:453) (513:513:513)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1306:1306:1306)) + (PORT datab (619:619:619) (727:727:727)) + (PORT datac (752:752:752) (871:871:871)) + (PORT datad (463:463:463) (523:523:523)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (552:552:552) (647:647:647)) + (PORT datab (549:549:549) (651:651:651)) + (PORT datac (1000:1000:1000) (1140:1140:1140)) + (PORT datad (819:819:819) (951:951:951)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (657:657:657)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (329:329:329) (388:388:388)) + (PORT datad (318:318:318) (372:372:372)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (980:980:980)) + (PORT datab (1112:1112:1112) (1276:1276:1276)) + (PORT datac (715:715:715) (835:835:835)) + (PORT datad (526:526:526) (615:615:615)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT datab (467:467:467) (539:539:539)) + (PORT datac (445:445:445) (513:513:513)) + (PORT datad (444:444:444) (508:508:508)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1417:1417:1417) (1652:1652:1652)) + (PORT datac (871:871:871) (1016:1016:1016)) + (PORT datad (878:878:878) (1033:1033:1033)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (172:172:172)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (644:644:644) (743:743:743)) + (PORT datad (102:102:102) (125:125:125)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (539:539:539)) + (PORT datab (337:337:337) (399:399:399)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (470:470:470) (559:559:559)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (509:509:509) (588:588:588)) + (PORT datac (457:457:457) (527:527:527)) + (PORT datad (352:352:352) (408:408:408)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (593:593:593)) + (PORT datab (187:187:187) (226:226:226)) + (PORT datac (320:320:320) (372:372:372)) + (PORT datad (175:175:175) (203:203:203)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) + (DELAY + (ABSOLUTE + (PORT datac (486:486:486) (564:564:564)) + (PORT datad (448:448:448) (512:512:512)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (384:384:384)) + (PORT datab (609:609:609) (696:696:696)) + (PORT datac (403:403:403) (461:461:461)) + (PORT datad (333:333:333) (388:388:388)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (565:565:565)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1286:1286:1286)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datac (978:978:978) (1128:1128:1128)) + (PORT datad (846:846:846) (969:969:969)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (738:738:738)) + (PORT datab (894:894:894) (1056:1056:1056)) + (PORT datac (1399:1399:1399) (1627:1627:1627)) + (PORT datad (100:100:100) (122:122:122)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (652:652:652)) + (PORT datab (739:739:739) (866:866:866)) + (PORT datac (485:485:485) (560:560:560)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (397:397:397)) + (PORT datab (1270:1270:1270) (1476:1476:1476)) + (PORT datac (1157:1157:1157) (1345:1345:1345)) + (PORT datad (635:635:635) (733:733:733)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (378:378:378)) + (PORT datab (324:324:324) (384:384:384)) + (PORT datac (292:292:292) (335:335:335)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (664:664:664)) + (PORT datab (1124:1124:1124) (1307:1307:1307)) + (PORT datac (436:436:436) (501:501:501)) + (PORT datad (1392:1392:1392) (1610:1610:1610)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (1001:1001:1001)) + (PORT datab (524:524:524) (626:626:626)) + (PORT datac (338:338:338) (398:398:398)) + (PORT datad (302:302:302) (342:342:342)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (583:583:583)) + (PORT datab (115:115:115) (142:142:142)) + (PORT datac (359:359:359) (422:422:422)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (409:409:409)) + (PORT datab (644:644:644) (748:748:748)) + (PORT datac (354:354:354) (418:418:418)) + (PORT datad (157:157:157) (184:184:184)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (416:416:416)) + (PORT datab (464:464:464) (557:557:557)) + (PORT datac (613:613:613) (698:698:698)) + (PORT datad (329:329:329) (376:376:376)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (390:390:390)) + (PORT datab (347:347:347) (398:398:398)) + (PORT datac (523:523:523) (629:629:629)) + (PORT datad (452:452:452) (514:514:514)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (981:981:981)) + (PORT datab (577:577:577) (656:656:656)) + (PORT datac (716:716:716) (836:836:836)) + (PORT datad (524:524:524) (612:612:612)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~19) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (917:917:917)) + (PORT datab (635:635:635) (733:733:733)) + (PORT datac (669:669:669) (792:792:792)) + (PORT datad (632:632:632) (721:721:721)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (384:384:384)) + (PORT datab (578:578:578) (678:678:678)) + (PORT datac (408:408:408) (468:468:468)) + (PORT datad (331:331:331) (381:381:381)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (152:152:152)) + (PORT datab (581:581:581) (678:678:678)) + (PORT datac (463:463:463) (533:533:533)) + (PORT datad (324:324:324) (374:374:374)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (315:315:315) (373:373:373)) + (PORT datab (117:117:117) (152:152:152)) + (PORT datac (447:447:447) (523:523:523)) + (PORT datad (800:800:800) (932:932:932)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (533:533:533)) + (PORT datab (452:452:452) (524:524:524)) + (PORT datac (445:445:445) (535:535:535)) + (PORT datad (431:431:431) (511:511:511)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -18677,12 +19471,246 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) + (PORT clk (896:896:896) (901:901:901)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (774:774:774) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (789:789:789)) + (PORT datab (382:382:382) (457:457:457)) + (PORT datac (505:505:505) (595:595:595)) + (PORT datad (585:585:585) (669:669:669)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (389:389:389)) + (PORT datab (347:347:347) (397:397:397)) + (PORT datac (522:522:522) (629:629:629)) + (PORT datad (200:200:200) (232:232:232)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (639:639:639)) + (PORT datab (1012:1012:1012) (1158:1158:1158)) + (PORT datac (715:715:715) (835:835:835)) + (PORT datad (582:582:582) (657:657:657)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1121:1121:1121) (1298:1298:1298)) + (PORT datab (1374:1374:1374) (1594:1594:1594)) + (PORT datac (763:763:763) (873:873:873)) + (PORT datad (903:903:903) (1066:1066:1066)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (977:977:977)) + (PORT datab (196:196:196) (231:231:231)) + (PORT datac (714:714:714) (833:833:833)) + (PORT datad (489:489:489) (565:565:565)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (778:778:778)) + (PORT datab (174:174:174) (213:213:213)) + (PORT datac (584:584:584) (667:667:667)) + (PORT datad (171:171:171) (202:202:202)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (343:343:343) (403:403:403)) + (PORT datac (87:87:87) (109:109:109)) + (PORT datad (335:335:335) (382:382:382)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (456:456:456) (533:533:533)) + (PORT datab (629:629:629) (726:726:726)) + (PORT datac (466:466:466) (540:540:540)) + (PORT datad (191:191:191) (239:239:239)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) + (DELAY + (ABSOLUTE + (PORT dataa (1417:1417:1417) (1651:1651:1651)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (775:775:775) (886:886:886)) + (PORT datad (1053:1053:1053) (1215:1215:1215)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (303:303:303)) + (PORT datab (240:240:240) (302:302:302)) + (PORT datac (469:469:469) (547:547:547)) + (PORT datad (356:356:356) (422:422:422)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (335:335:335)) + (PORT datab (346:346:346) (413:413:413)) + (PORT datac (335:335:335) (386:386:386)) + (PORT datad (346:346:346) (404:404:404)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (443:443:443) (511:511:511)) + (PORT datab (319:319:319) (379:379:379)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (483:483:483)) + (PORT datab (325:325:325) (379:379:379)) + (PORT datac (607:607:607) (727:727:727)) + (PORT datad (498:498:498) (582:582:582)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (129:129:129) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -18691,267 +19719,113 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (1105:1105:1105) (1260:1260:1260)) - (PORT ena (767:767:767) (833:833:833)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~72) + (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (303:303:303)) - (PORT datab (132:132:132) (180:180:180)) - (PORT datad (352:352:352) (413:413:413)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (235:235:235) (302:302:302)) + (PORT datab (358:358:358) (435:435:435)) + (PORT datac (469:469:469) (547:547:547)) + (PORT datad (357:357:357) (423:423:423)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (362:362:362) (400:400:400)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~71) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) (DELAY (ABSOLUTE - (PORT dataa (695:695:695) (810:810:810)) - (PORT datab (458:458:458) (535:535:535)) - (PORT datad (203:203:203) (235:235:235)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (466:466:466) (556:556:556)) + (PORT datab (117:117:117) (151:151:151)) + (PORT datac (451:451:451) (526:526:526)) + (PORT datad (493:493:493) (588:588:588)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (978:978:978) (1094:1094:1094)) - (PORT ena (494:494:494) (536:536:536)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (441:441:441) (526:526:526)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (986:986:986) (1116:1116:1116)) + (PORT datad (432:432:432) (495:495:495)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (975:975:975) (1090:1090:1090)) - (PORT ena (417:417:417) (434:434:434)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~69) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (274:274:274)) - (PORT datab (226:226:226) (274:274:274)) - (PORT datad (191:191:191) (240:240:240)) + (PORT dataa (360:360:360) (423:423:423)) + (PORT datab (977:977:977) (1099:1099:1099)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (443:443:443) (508:508:508)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~73) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) (DELAY (ABSOLUTE - (PORT dataa (306:306:306) (356:356:356)) - (PORT datab (342:342:342) (402:402:402)) - (PORT datac (318:318:318) (372:372:372)) - (PORT datad (89:89:89) (107:107:107)) + (PORT dataa (1328:1328:1328) (1554:1554:1554)) + (PORT datab (847:847:847) (991:991:991)) + (PORT datac (471:471:471) (546:546:546)) + (PORT datad (574:574:574) (679:679:679)) (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (310:310:310) (357:357:357)) + (PORT datab (556:556:556) (654:654:654)) + (PORT datac (365:365:365) (433:433:433)) + (PORT datad (450:450:450) (510:510:510)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT asdata (884:884:884) (1008:1008:1008)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT asdata (888:888:888) (1012:1012:1012)) - (PORT ena (518:518:518) (563:563:563)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~67) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) (DELAY (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datab (385:385:385) (460:460:460)) - (PORT datad (121:121:121) (144:144:144)) + (PORT dataa (544:544:544) (627:627:627)) + (PORT datab (227:227:227) (274:274:274)) + (PORT datac (528:528:528) (616:616:616)) + (PORT datad (642:642:642) (749:749:749)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT asdata (782:782:782) (864:864:864)) - (PORT ena (433:433:433) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (791:791:791)) - (PORT datab (772:772:772) (891:891:891)) - (PORT datad (1019:1019:1019) (1172:1172:1172)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (650:650:650) (727:727:727)) - (PORT ena (422:422:422) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (654:654:654) (732:732:732)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (275:275:275)) - (PORT datab (228:228:228) (271:271:271)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (391:391:391)) - (PORT datab (168:168:168) (205:205:205)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (333:333:333) (385:385:385)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -18959,14 +19833,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~75) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) (DELAY (ABSOLUTE - (PORT dataa (332:332:332) (384:384:384)) - (PORT datab (1144:1144:1144) (1350:1350:1350)) - (PORT datac (325:325:325) (375:375:375)) - (PORT datad (295:295:295) (342:342:342)) - (IOPATH dataa combout (159:159:159) (163:163:163)) + (PORT dataa (124:124:124) (158:158:158)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (109:109:109) (129:129:129)) + (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -18975,15 +19849,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~23) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) (DELAY (ABSOLUTE - (PORT dataa (606:606:606) (702:702:702)) - (PORT datab (636:636:636) (750:750:750)) - (PORT datac (542:542:542) (629:629:629)) - (PORT datad (958:958:958) (1123:1123:1123)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datab (123:123:123) (158:158:158)) + (PORT datac (102:102:102) (129:129:129)) + (PORT datad (196:196:196) (226:226:226)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -18991,47 +19863,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (438:438:438)) - (PORT datab (131:131:131) (172:172:172)) + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (343:343:343) (402:402:402)) (PORT datac (90:90:90) (111:111:111)) - (PORT datad (458:458:458) (527:527:527)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (532:532:532)) - (PORT datab (810:810:810) (952:952:952)) - (PORT datac (845:845:845) (963:963:963)) - (PORT datad (606:606:606) (709:709:709)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (784:784:784)) - (PORT datab (580:580:580) (658:658:658)) - (PORT datac (384:384:384) (462:462:462)) - (PORT datad (509:509:509) (585:585:585)) + (PORT datad (103:103:103) (120:120:120)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (DELAY + (ABSOLUTE + (PORT datab (730:730:730) (863:863:863)) + (PORT datac (490:490:490) (574:574:574)) + (PORT datad (634:634:634) (727:727:727)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19039,28 +19893,765 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) (DELAY (ABSOLUTE - (PORT dataa (277:277:277) (325:325:325)) - (PORT datab (331:331:331) (393:393:393)) - (PORT datac (348:348:348) (400:400:400)) + (PORT dataa (714:714:714) (833:833:833)) + (PORT datab (568:568:568) (671:671:671)) + (PORT datac (830:830:830) (949:949:949)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1315:1315:1315)) + (PORT datab (528:528:528) (618:618:618)) + (PORT datac (659:659:659) (762:762:762)) + (PORT datad (597:597:597) (687:687:687)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (584:584:584)) + (PORT datab (581:581:581) (661:661:661)) + (PORT datac (499:499:499) (576:576:576)) + (PORT datad (301:301:301) (346:346:346)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (994:994:994)) + (PORT datab (228:228:228) (276:276:276)) + (PORT datac (520:520:520) (602:602:602)) + (PORT datad (643:643:643) (751:751:751)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (996:996:996)) + (PORT datab (122:122:122) (153:153:153)) + (PORT datac (1117:1117:1117) (1275:1275:1275)) (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (334:334:334) (392:392:392)) + (PORT datad (102:102:102) (119:119:119)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (113:113:113) (142:142:142)) + (PORT datac (464:464:464) (541:541:541)) + (PORT datad (291:291:291) (331:331:331)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (952:952:952)) + (PORT datab (777:777:777) (887:887:887)) + (PORT datac (874:874:874) (993:993:993)) + (PORT datad (576:576:576) (656:656:656)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (468:468:468)) + (PORT datab (378:378:378) (450:450:450)) + (PORT datac (865:865:865) (979:979:979)) + (PORT datad (810:810:810) (926:926:926)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~43) + (DELAY + (ABSOLUTE + (PORT dataa (753:753:753) (894:894:894)) + (PORT datab (587:587:587) (675:675:675)) + (PORT datac (873:873:873) (991:991:991)) + (PORT datad (1006:1006:1006) (1178:1178:1178)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (458:458:458) (529:529:529)) + (PORT datac (869:869:869) (983:983:983)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~42) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (528:528:528)) + (PORT datab (591:591:591) (680:680:680)) + (PORT datac (1181:1181:1181) (1374:1374:1374)) + (PORT datad (1001:1001:1001) (1172:1172:1172)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (543:543:543) (616:616:616)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~41) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (427:427:427)) + (PORT datab (1124:1124:1124) (1291:1291:1291)) + (PORT datac (822:822:822) (957:957:957)) + (PORT datad (767:767:767) (909:909:909)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (981:981:981)) + (PORT datab (1110:1110:1110) (1274:1274:1274)) + (PORT datac (715:715:715) (835:835:835)) + (PORT datad (487:487:487) (562:562:562)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1156:1156:1156)) + (PORT datab (578:578:578) (684:684:684)) + (PORT datac (104:104:104) (127:127:127)) + (PORT datad (847:847:847) (970:970:970)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (717:717:717)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (756:756:756) (863:863:863)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~44) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (511:511:511)) + (PORT datab (1029:1029:1029) (1201:1201:1201)) + (PORT datac (731:731:731) (871:871:871)) + (PORT datad (1007:1007:1007) (1179:1179:1179)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (378:378:378) (449:449:449)) + (PORT datac (465:465:465) (531:531:531)) + (PORT datad (381:381:381) (441:441:441)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) + (DELAY + (ABSOLUTE + (PORT dataa (276:276:276) (319:319:319)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (342:342:342) (406:406:406)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (376:376:376)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (325:325:325) (381:381:381)) + (PORT datad (177:177:177) (203:203:203)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (519:519:519) (594:594:594)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (162:162:162) (191:191:191)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (1084:1084:1084)) + (PORT datab (810:810:810) (933:933:933)) + (PORT datac (337:337:337) (400:400:400)) + (PORT datad (468:468:468) (534:534:534)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (935:935:935)) + (PORT datab (454:454:454) (519:519:519)) + (PORT datac (456:456:456) (518:518:518)) + (PORT datad (773:773:773) (884:884:884)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (518:518:518)) + (PORT datab (977:977:977) (1099:1099:1099)) + (PORT datac (330:330:330) (389:389:389)) + (PORT datad (442:442:442) (508:508:508)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (763:763:763)) + (PORT datab (116:116:116) (150:150:150)) + (PORT datac (495:495:495) (580:580:580)) + (PORT datad (328:328:328) (378:378:378)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (189:189:189)) + (PORT datab (523:523:523) (615:615:615)) + (PORT datac (272:272:272) (314:314:314)) + (PORT datad (614:614:614) (701:701:701)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (315:315:315) (389:389:389)) + (PORT datab (620:620:620) (740:740:740)) + (PORT datac (310:310:310) (357:357:357)) + (PORT datad (205:205:205) (248:248:248)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (193:193:193)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (290:290:290) (339:339:339)) + (PORT datad (499:499:499) (584:584:584)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (295:295:295)) + (PORT datab (226:226:226) (289:289:289)) + (PORT datac (471:471:471) (549:549:549)) + (PORT datad (352:352:352) (418:418:418)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (341:341:341) (395:395:395)) + (PORT datac (181:181:181) (220:220:220)) + (PORT datad (439:439:439) (506:506:506)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (240:240:240)) + (PORT datab (348:348:348) (420:420:420)) + (PORT datac (346:346:346) (410:410:410)) + (PORT datad (344:344:344) (397:397:397)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (254:254:254)) + (PORT datab (128:128:128) (161:161:161)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (453:453:453)) + (PORT datab (646:646:646) (772:772:772)) + (PORT datac (468:468:468) (546:546:546)) + (PORT datad (360:360:360) (420:420:420)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (739:739:739) (860:860:860)) + (PORT datab (1112:1112:1112) (1276:1276:1276)) + (PORT datac (821:821:821) (956:956:956)) + (PORT datad (848:848:848) (984:984:984)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (723:723:723)) + (PORT datab (334:334:334) (392:392:392)) + (PORT datac (447:447:447) (512:512:512)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (146:146:146)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datad (423:423:423) (484:484:484)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (727:727:727)) + (PORT datac (306:306:306) (350:350:350)) + (PORT datad (911:911:911) (1051:1051:1051)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (567:567:567)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (1037:1037:1037) (1212:1212:1212)) + (PORT datad (302:302:302) (345:345:345)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (1171:1171:1171) (1361:1361:1361)) + (PORT datac (739:739:739) (871:871:871)) + (PORT datad (497:497:497) (586:586:586)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (260:260:260)) + (PORT datab (314:314:314) (364:364:364)) + (PORT datac (654:654:654) (765:765:765)) + (PORT datad (449:449:449) (520:520:520)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (182:182:182) (188:188:188)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (353:353:353)) + (PORT datab (319:319:319) (370:370:370)) + (PORT datad (288:288:288) (330:330:330)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (411:411:411)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (428:428:428) (490:490:490)) + (PORT datad (107:107:107) (125:125:125)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (1091:1091:1091)) + (PORT datab (499:499:499) (574:574:574)) + (PORT datac (486:486:486) (558:558:558)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_latch_\|abusz\[12\]) (DELAY (ABSOLUTE - (PORT datac (861:861:861) (1012:1012:1012)) - (PORT datad (342:342:342) (400:400:400)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (217:217:217) (260:260:260)) + (PORT datac (484:484:484) (559:559:559)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[12\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (162:162:162) (189:189:189)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -19070,10 +20661,10 @@ (INSTANCE z80_\|address_latch_\|Q\[12\]) (DELAY (ABSOLUTE - (PORT clk (905:905:905) (912:912:912)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (892:892:892)) - (PORT ena (1352:1352:1352) (1505:1505:1505)) + (PORT clrn (920:920:920) (905:905:905)) + (PORT ena (1106:1106:1106) (1248:1248:1248)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -19088,24 +20679,101 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (306:306:306)) - (PORT datab (255:255:255) (319:319:319)) - (PORT datac (539:539:539) (641:641:641)) - (PORT datad (281:281:281) (324:324:324)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (166:166:166) (174:174:174)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (323:323:323) (376:376:376)) + (PORT datab (479:479:479) (565:565:565)) + (PORT datac (132:132:132) (179:179:179)) + (PORT datad (309:309:309) (369:369:369)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (679:679:679) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (915:915:915)) - (PORT asdata (769:769:769) (861:861:861)) + (PORT clk (915:915:915) (923:923:923)) + (PORT asdata (694:694:694) (776:776:776)) + (PORT ena (480:480:480) (509:509:509)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (263:263:263)) + (PORT datab (217:217:217) (260:260:260)) + (PORT datad (102:102:102) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (428:428:428)) + (PORT datac (117:117:117) (158:158:158)) + (PORT datad (441:441:441) (509:509:509)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (241:241:241)) + (PORT datab (452:452:452) (526:526:526)) + (PORT datac (369:369:369) (438:438:438)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (1107:1107:1107) (1234:1234:1234)) (PORT ena (405:405:405) (422:422:422)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -19117,136 +20785,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~22) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) (DELAY (ABSOLUTE - (PORT dataa (142:142:142) (188:188:188)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datad (514:514:514) (622:622:622)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (505:505:505) (546:546:546)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (239:239:239) (286:286:286)) - (PORT datac (156:156:156) (185:185:185)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (429:429:429)) - (PORT datab (207:207:207) (251:251:251)) - (PORT datac (960:960:960) (1140:1140:1140)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT asdata (672:672:672) (750:750:750)) - (PORT ena (433:433:433) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (793:793:793)) - (PORT datab (768:768:768) (887:887:887)) - (PORT datad (1022:1022:1022) (1175:1175:1175)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (659:659:659) (730:730:730)) - (PORT ena (422:422:422) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (659:659:659) (730:730:730)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (276:276:276)) - (PORT datab (226:226:226) (269:269:269)) - (PORT datad (116:116:116) (152:152:152)) + (PORT dataa (210:210:210) (248:248:248)) + (PORT datab (648:648:648) (750:750:750)) + (PORT datad (384:384:384) (437:437:437)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -19254,186 +20798,14 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT asdata (699:699:699) (789:789:789)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT asdata (699:699:699) (789:789:789)) - (PORT ena (518:518:518) (563:563:563)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (590:590:590)) - (PORT datab (128:128:128) (176:176:176)) - (PORT datad (125:125:125) (149:149:149)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (684:684:684) (771:771:771)) - (PORT ena (631:631:631) (678:678:678)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (683:683:683) (770:770:770)) - (PORT ena (649:649:649) (709:709:709)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (404:404:404)) - (PORT datab (130:130:130) (178:178:178)) - (PORT datad (332:332:332) (378:378:378)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (662:662:662) (736:736:736)) - (PORT ena (494:494:494) (536:536:536)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (663:663:663) (736:736:736)) - (PORT ena (504:504:504) (535:535:535)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (284:284:284)) - (PORT datab (224:224:224) (272:272:272)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (498:498:498) (546:546:546)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (808:808:808)) - (PORT datab (454:454:454) (531:531:531)) - (PORT datad (202:202:202) (234:234:234)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (915:915:915)) + (PORT clk (915:915:915) (923:923:923)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (759:759:759) (847:847:847)) + (PORT ena (776:776:776) (851:851:851)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -19447,9 +20819,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (484:484:484) (526:526:526)) - (PORT ena (767:767:767) (833:833:833)) + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (1105:1105:1105) (1232:1232:1232)) + (PORT ena (663:663:663) (731:731:731)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -19460,376 +20832,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~81) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) (DELAY (ABSOLUTE - (PORT dataa (245:245:245) (307:307:307)) - (PORT datab (242:242:242) (305:305:305)) - (PORT datad (351:351:351) (412:412:412)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (381:381:381) (461:461:461)) + (PORT datab (470:470:470) (545:545:545)) + (PORT datad (480:480:480) (550:550:550)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (448:448:448) (522:522:522)) - (PORT datab (335:335:335) (397:397:397)) - (PORT datac (321:321:321) (374:374:374)) - (PORT datad (323:323:323) (373:373:373)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (406:406:406)) - (PORT datab (290:290:290) (340:340:340)) - (PORT datac (477:477:477) (542:542:542)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1354:1354:1354)) - (PORT datab (312:312:312) (360:360:360)) - (PORT datac (591:591:591) (685:685:685)) - (PORT datad (458:458:458) (547:547:547)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) - (DELAY - (ABSOLUTE - (PORT dataa (961:961:961) (1119:1119:1119)) - (PORT datac (912:912:912) (1045:1045:1045)) - (PORT datad (807:807:807) (912:912:912)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (693:693:693)) - (PORT datab (578:578:578) (669:669:669)) - (PORT datac (983:983:983) (1150:1150:1150)) - (PORT datad (729:729:729) (839:839:839)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT datab (1015:1015:1015) (1184:1184:1184)) - (PORT datac (473:473:473) (542:542:542)) - (PORT datad (724:724:724) (833:833:833)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (658:658:658)) - (PORT datac (660:660:660) (770:770:770)) - (PORT datad (763:763:763) (874:874:874)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT datab (1103:1103:1103) (1267:1267:1267)) - (PORT datac (398:398:398) (456:456:456)) - (PORT datad (542:542:542) (624:624:624)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (731:731:731)) - (PORT datac (940:940:940) (1090:1090:1090)) - (PORT datad (808:808:808) (914:914:914)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (659:659:659)) - (PORT datab (326:326:326) (371:371:371)) - (PORT datac (562:562:562) (652:652:652)) - (PORT datad (787:787:787) (914:914:914)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (417:417:417)) - (PORT datab (184:184:184) (224:224:224)) - (PORT datac (469:469:469) (547:547:547)) - (PORT datad (303:303:303) (345:345:345)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (1082:1082:1082)) - (PORT datab (301:301:301) (348:348:348)) - (PORT datac (942:942:942) (1094:1094:1094)) - (PORT datad (1356:1356:1356) (1555:1555:1555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (386:386:386) (441:441:441)) - (PORT datac (292:292:292) (345:345:345)) - (PORT datad (550:550:550) (620:620:620)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (945:945:945)) - (PORT datab (344:344:344) (416:416:416)) - (PORT datac (283:283:283) (326:326:326)) - (PORT datad (693:693:693) (791:791:791)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (530:530:530)) - (PORT datab (196:196:196) (236:236:236)) - (PORT datac (173:173:173) (205:205:205)) - (PORT datad (1040:1040:1040) (1211:1211:1211)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (819:819:819)) - (PORT datab (871:871:871) (1004:1004:1004)) - (PORT datac (290:290:290) (327:327:327)) - (PORT datad (1264:1264:1264) (1458:1458:1458)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (402:402:402)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (191:191:191) (217:217:217)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (468:468:468)) - (PORT datab (378:378:378) (448:448:448)) - (PORT datac (321:321:321) (370:370:370)) - (PORT datad (313:313:313) (362:362:362)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (487:487:487)) - (PORT datab (426:426:426) (495:495:495)) - (PORT datac (384:384:384) (438:438:438)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (505:505:505) (599:599:599)) - (PORT datad (102:102:102) (124:124:124)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (192:192:192) (181:181:181)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (530:530:530) (580:580:580)) + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (775:775:775) (861:861:861)) + (PORT ena (622:622:622) (680:680:680)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) - (DELAY - (ABSOLUTE - (PORT datac (998:998:998) (1167:1167:1167)) - (PORT datad (722:722:722) (832:832:832)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (551:551:551)) - (PORT datab (576:576:576) (673:673:673)) - (PORT datac (554:554:554) (637:637:637)) - (PORT datad (788:788:788) (915:915:915)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT asdata (291:291:291) (309:309:309)) + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (774:774:774) (861:861:861)) (PORT ena (405:405:405) (422:422:422)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -19841,26 +20879,134 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) (DELAY (ABSOLUTE - (PORT datac (415:415:415) (476:476:476)) - (PORT datad (123:123:123) (146:146:146)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (488:488:488) (578:578:578)) + (PORT datab (130:130:130) (164:164:164)) + (PORT datad (117:117:117) (152:152:152)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (476:476:476) (562:562:562)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datad (326:326:326) (380:380:380)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datad (764:764:764) (865:865:865)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (627:627:627) (675:675:675)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (933:933:933) (1030:1030:1030)) + (PORT ena (670:670:670) (742:742:742)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (262:262:262)) + (PORT datab (892:892:892) (1040:1040:1040)) + (PORT datad (642:642:642) (747:747:747)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (422:422:422) (489:489:489)) + (PORT datad (328:328:328) (384:384:384)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (1062:1062:1062) (1195:1195:1195)) + (PORT ena (753:753:753) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (1061:1061:1061) (1195:1195:1195)) + (PORT ena (759:759:759) (842:842:842)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (629:629:629)) + (PORT datab (511:511:511) (618:618:618)) + (PORT datad (115:115:115) (152:152:152)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19868,29 +21014,93 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1044:1044:1044) (1156:1156:1156)) + (PORT ena (515:515:515) (556:556:556)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1043:1043:1043) (1155:1155:1155)) + (PORT ena (506:506:506) (537:537:537)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) (DELAY (ABSOLUTE - (PORT dataa (467:467:467) (546:546:546)) - (PORT datab (396:396:396) (487:487:487)) - (PORT datac (373:373:373) (446:446:446)) - (PORT datad (552:552:552) (631:631:631)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (257:257:257) (310:310:310)) + (PORT datab (266:266:266) (318:318:318)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (1059:1059:1059) (1190:1190:1190)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (606:606:606)) + (PORT datab (669:669:669) (791:791:791)) + (PORT datad (485:485:485) (564:564:564)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (415:415:415)) + (PORT datab (168:168:168) (205:205:205)) + (PORT datac (310:310:310) (357:357:357)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19898,14 +21108,78 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[1\]\~1) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) (DELAY (ABSOLUTE - (PORT dataa (602:602:602) (705:705:705)) - (PORT datab (580:580:580) (672:672:672)) - (PORT datac (374:374:374) (455:455:455)) - (PORT datad (454:454:454) (519:519:519)) - (IOPATH dataa combout (166:166:166) (159:159:159)) + (PORT dataa (508:508:508) (606:606:606)) + (PORT datab (479:479:479) (577:577:577)) + (PORT datac (439:439:439) (509:509:509)) + (PORT datad (730:730:730) (839:839:839)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (715:715:715) (846:846:846)) + (PORT datab (537:537:537) (630:630:630)) + (PORT datac (464:464:464) (539:539:539)) + (PORT datad (804:804:804) (906:906:906)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (830:830:830)) + (PORT datab (666:666:666) (773:773:773)) + (PORT datac (507:507:507) (583:583:583)) + (PORT datad (522:522:522) (608:608:608)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (129:129:129) (168:168:168)) + (PORT datac (562:562:562) (636:636:636)) + (PORT datad (527:527:527) (614:614:614)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (845:845:845)) + (PORT datab (522:522:522) (615:615:615)) + (PORT datac (192:192:192) (229:229:229)) + (PORT datad (665:665:665) (793:793:793)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -19914,13 +21188,315 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) (DELAY (ABSOLUTE - (PORT dataa (308:308:308) (355:355:355)) - (PORT datab (315:315:315) (369:369:369)) - (PORT datad (294:294:294) (338:338:338)) - (IOPATH dataa combout (166:166:166) (159:159:159)) + (PORT dataa (648:648:648) (781:781:781)) + (PORT datab (1031:1031:1031) (1199:1199:1199)) + (PORT datac (487:487:487) (576:576:576)) + (PORT datad (858:858:858) (1004:1004:1004)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) + (DELAY + (ABSOLUTE + (PORT dataa (519:519:519) (610:610:610)) + (PORT datab (346:346:346) (403:403:403)) + (PORT datac (799:799:799) (940:940:940)) + (PORT datad (320:320:320) (371:371:371)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datac (504:504:504) (590:590:590)) + (PORT datad (127:127:127) (156:156:156)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (756:756:756)) + (PORT datab (158:158:158) (203:203:203)) + (PORT datac (141:141:141) (181:181:181)) + (PORT datad (131:131:131) (162:162:162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT datab (185:185:185) (226:226:226)) + (PORT datac (513:513:513) (610:610:610)) + (PORT datad (371:371:371) (441:441:441)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (407:407:407)) + (PORT datab (656:656:656) (758:758:758)) + (PORT datac (341:341:341) (416:416:416)) + (PORT datad (370:370:370) (437:437:437)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (379:379:379)) + (PORT datab (168:168:168) (204:204:204)) + (PORT datac (632:632:632) (738:738:738)) + (PORT datad (281:281:281) (324:324:324)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (396:396:396)) + (PORT datab (546:546:546) (645:645:645)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (119:119:119) (149:149:149)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (372:372:372)) + (PORT datab (529:529:529) (627:627:627)) + (PORT datac (478:478:478) (551:551:551)) + (PORT datad (175:175:175) (205:205:205)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (369:369:369) (439:439:439)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (585:585:585)) + (PORT datab (394:394:394) (473:473:473)) + (PORT datac (511:511:511) (608:608:608)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (409:409:409)) + (PORT datab (342:342:342) (411:411:411)) + (PORT datac (331:331:331) (386:386:386)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (379:379:379)) + (PORT datab (515:515:515) (607:607:607)) + (PORT datac (609:609:609) (729:729:729)) + (PORT datad (307:307:307) (355:355:355)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (192:192:192)) + (PORT datac (90:90:90) (112:112:112)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (302:302:302)) + (PORT datac (341:341:341) (416:416:416)) + (PORT datad (355:355:355) (421:421:421)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (345:345:345)) + (PORT datab (451:451:451) (516:516:516)) + (PORT datac (426:426:426) (488:488:488)) + (PORT datad (106:106:106) (125:125:125)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (429:429:429)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (109:109:109) (133:133:133)) + (PORT datad (438:438:438) (502:502:502)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (409:409:409)) + (PORT datab (345:345:345) (412:412:412)) + (PORT datad (346:346:346) (404:404:404)) + (IOPATH dataa combout (172:172:172) (165:165:165)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19931,11 +21507,73 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (764:764:764) (890:890:890)) - (PORT datab (389:389:389) (472:472:472)) - (PORT datac (589:589:589) (683:683:683)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (188:188:188) (179:179:179)) + (PORT dataa (360:360:360) (423:423:423)) + (PORT datab (462:462:462) (533:533:533)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (267:267:267) (304:304:304)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (141:141:141)) + (PORT datab (111:111:111) (144:144:144)) + (PORT datac (108:108:108) (132:132:132)) + (PORT datad (97:97:97) (116:116:116)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (414:414:414)) + (PORT datab (358:358:358) (421:421:421)) + (PORT datad (326:326:326) (386:386:386)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (233:233:233)) + (PORT datab (341:341:341) (396:396:396)) + (PORT datac (95:95:95) (120:120:120)) + (PORT datad (439:439:439) (506:506:506)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (237:237:237)) + (PORT datab (203:203:203) (245:245:245)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (186:186:186) (220:220:220)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -19944,15 +21582,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~15) + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) (DELAY (ABSOLUTE - (PORT dataa (606:606:606) (702:702:702)) - (PORT datab (662:662:662) (777:777:777)) - (PORT datac (557:557:557) (658:658:658)) - (PORT datad (614:614:614) (721:721:721)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (960:960:960) (1080:1080:1080)) + (PORT datad (442:442:442) (507:507:507)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19960,14 +21594,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~16) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (466:466:466)) - (PORT datab (133:133:133) (174:174:174)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (458:458:458) (527:527:527)) - (IOPATH dataa combout (159:159:159) (163:163:163)) + (PORT dataa (192:192:192) (234:234:234)) + (PORT datab (123:123:123) (155:155:155)) + (PORT datac (92:92:92) (116:116:116)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (125:125:125) (158:158:158)) + (PORT datac (179:179:179) (218:218:218)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -19975,13 +21625,23 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) + (PORT datad (614:614:614) (710:710:710)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (505:505:505) (546:546:546)) + (PORT ena (627:627:627) (675:675:675)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -19992,11 +21652,58 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (915:915:915)) - (PORT asdata (480:480:480) (532:532:532)) + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (803:803:803) (911:911:911)) + (PORT ena (670:670:670) (742:742:742)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (181:181:181)) + (PORT datab (893:893:893) (1041:1041:1041)) + (PORT datad (643:643:643) (748:748:748)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (920:920:920) (1042:1042:1042)) + (PORT ena (622:622:622) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (918:918:918) (1040:1040:1040)) (PORT ena (405:405:405) (422:422:422)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -20008,12 +21715,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~10) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) (DELAY (ABSOLUTE - (PORT dataa (142:142:142) (188:188:188)) - (PORT datab (536:536:536) (651:651:651)) - (PORT datad (301:301:301) (348:348:348)) + (PORT dataa (484:484:484) (573:573:573)) + (PORT datab (130:130:130) (163:163:163)) + (PORT datad (119:119:119) (156:156:156)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -20022,41 +21729,29 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~11) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (239:239:239) (285:285:285)) - (PORT datac (168:168:168) (200:200:200)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT clk (915:915:915) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (776:776:776) (851:851:851)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT datab (1103:1103:1103) (1268:1268:1268)) - (PORT datac (399:399:399) (456:456:456)) - (PORT datad (542:542:542) (624:624:624)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (662:662:662) (741:741:741)) - (PORT ena (659:659:659) (712:712:712)) + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (798:798:798) (895:895:895)) + (PORT ena (663:663:663) (731:731:731)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20067,26 +21762,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) (DELAY (ABSOLUTE - (PORT dataa (470:470:470) (552:552:552)) - (PORT datab (939:939:939) (1084:1084:1084)) - (PORT datad (684:684:684) (778:778:778)) + (PORT dataa (386:386:386) (470:470:470)) + (PORT datab (470:470:470) (545:545:545)) + (PORT datad (480:480:480) (550:550:550)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (798:798:798) (895:895:895)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (761:761:761) (870:870:870)) + (PORT datab (650:650:650) (752:752:752)) + (PORT datad (129:129:129) (157:157:157)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (513:513:513)) + (PORT datab (600:600:600) (712:712:712)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (90:90:90) (108:108:108)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (666:666:666) (745:745:745)) - (PORT ena (759:759:759) (815:815:815)) + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (803:803:803) (913:913:913)) + (PORT ena (515:515:515) (556:556:556)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (803:803:803) (913:913:913)) + (PORT ena (506:506:506) (537:537:537)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20097,12 +21856,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) (DELAY (ABSOLUTE - (PORT dataa (332:332:332) (405:405:405)) - (PORT datab (488:488:488) (565:565:565)) - (PORT datad (118:118:118) (155:155:155)) + (PORT dataa (257:257:257) (311:311:311)) + (PORT datab (266:266:266) (317:317:317)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (765:765:765) (858:858:858)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (607:607:607)) + (PORT datab (669:669:669) (791:791:791)) + (PORT datad (483:483:483) (561:561:561)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (664:664:664) (748:748:748)) + (PORT ena (753:753:753) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (663:663:663) (747:747:747)) + (PORT ena (759:759:759) (842:842:842)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (619:619:619)) + (PORT datab (515:515:515) (623:623:623)) + (PORT datad (117:117:117) (154:154:154)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -20112,15 +21949,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (1088:1088:1088)) - (PORT datab (693:693:693) (830:830:830)) - (PORT datac (629:629:629) (724:724:724)) - (PORT datad (417:417:417) (483:483:483)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (194:194:194) (234:234:234)) + (PORT datab (339:339:339) (406:406:406)) + (PORT datac (342:342:342) (405:405:405)) + (PORT datad (462:462:462) (547:547:547)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -20128,12 +21965,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (503:503:503) (556:556:556)) - (PORT ena (804:804:804) (906:906:906)) + (PORT clk (915:915:915) (923:923:923)) + (PORT asdata (632:632:632) (700:700:700)) + (PORT ena (480:480:480) (509:509:509)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20144,46 +21981,150 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) (DELAY (ABSOLUTE - (PORT dataa (901:901:901) (1084:1084:1084)) - (PORT datab (690:690:690) (827:827:827)) - (PORT datac (631:631:631) (725:725:725)) - (PORT datad (415:415:415) (481:481:481)) + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (210:210:210) (253:253:253)) + (PORT datad (206:206:206) (243:243:243)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (679:679:679) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (451:451:451) (544:544:544)) + (PORT datac (115:115:115) (156:156:156)) + (PORT datad (349:349:349) (406:406:406)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (374:374:374)) + (PORT datab (486:486:486) (573:573:573)) + (PORT datac (129:129:129) (176:176:176)) + (PORT datad (306:306:306) (366:366:366)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT datac (144:144:144) (192:192:192)) + (PORT datad (98:98:98) (120:120:120)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (796:796:796) (899:899:899)) + (PORT ena (673:673:673) (745:745:745)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (776:776:776) (851:851:851)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (685:685:685)) + (PORT datab (478:478:478) (553:553:553)) + (PORT datad (361:361:361) (437:437:437)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (1146:1146:1146) (1300:1300:1300)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (1038:1038:1038)) + (PORT datab (647:647:647) (748:748:748)) + (PORT datad (121:121:121) (149:149:149)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (499:499:499) (551:551:551)) - (PORT ena (641:641:641) (691:691:691)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (154:154:154) (201:201:201)) - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (307:307:307) (359:359:359)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -20191,26 +22132,38 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (572:572:572) (664:664:664)) - (PORT datac (665:665:665) (775:775:775)) - (PORT datad (762:762:762) (873:873:873)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datad (628:628:628) (736:736:736)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (913:913:913)) - (PORT asdata (473:473:473) (516:516:516)) - (PORT ena (421:421:421) (441:441:441)) + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (627:627:627) (675:675:675)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (795:795:795) (894:894:894)) + (PORT ena (670:670:670) (742:742:742)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20221,11 +22174,123 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) (DELAY (ABSOLUTE - (PORT datab (195:195:195) (237:237:237)) - (PORT datad (114:114:114) (136:136:136)) + (PORT dataa (198:198:198) (259:259:259)) + (PORT datab (896:896:896) (1045:1045:1045)) + (PORT datad (644:644:644) (749:749:749)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (1005:1005:1005) (1137:1137:1137)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (796:796:796) (899:899:899)) + (PORT ena (582:582:582) (618:618:618)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (270:270:270)) + (PORT datab (477:477:477) (557:557:557)) + (PORT datad (191:191:191) (219:219:219)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (172:172:172) (209:209:209)) + (PORT datac (421:421:421) (477:477:477)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (805:805:805) (908:908:908)) + (PORT ena (506:506:506) (537:537:537)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (805:805:805) (908:908:908)) + (PORT ena (515:515:515) (556:556:556)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (255:255:255) (308:308:308)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (249:249:249) (295:295:295)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -20234,11 +22299,359 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT asdata (356:356:356) (382:382:382)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (958:958:958) (1085:1085:1085)) + (PORT ena (759:759:759) (842:842:842)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (959:959:959) (1086:1086:1086)) + (PORT ena (753:753:753) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (627:627:627)) + (PORT datab (132:132:132) (180:180:180)) + (PORT datad (497:497:497) (594:594:594)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (979:979:979) (1116:1116:1116)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (606:606:606)) + (PORT datab (669:669:669) (791:791:791)) + (PORT datad (486:486:486) (565:565:565)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (417:417:417)) + (PORT datab (473:473:473) (555:555:555)) + (PORT datac (323:323:323) (380:380:380)) + (PORT datad (438:438:438) (504:504:504)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (509:509:509) (607:607:607)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (463:463:463) (547:547:547)) + (PORT datad (729:729:729) (839:839:839)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (923:923:923)) + (PORT asdata (641:641:641) (723:723:723)) + (PORT ena (480:480:480) (509:509:509)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (262:262:262)) + (PORT datab (113:113:113) (141:141:141)) + (PORT datad (204:204:204) (240:240:240)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (679:679:679) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (428:428:428)) + (PORT datab (202:202:202) (245:245:245)) + (PORT datac (116:116:116) (156:156:156)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (336:336:336)) + (PORT datab (459:459:459) (533:533:533)) + (PORT datac (372:372:372) (441:441:441)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT datab (204:204:204) (251:251:251)) + (PORT datac (486:486:486) (561:561:561)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (172:172:172) (202:202:202)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (920:920:920) (905:905:905)) + (PORT ena (1106:1106:1106) (1248:1248:1248)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (DELAY + (ABSOLUTE + (PORT datac (144:144:144) (193:193:193)) + (PORT datad (467:467:467) (548:548:548)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (DELAY + (ABSOLUTE + (PORT datac (183:183:183) (215:215:215)) + (PORT datad (471:471:471) (541:541:541)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (920:920:920) (905:905:905)) + (PORT ena (1106:1106:1106) (1248:1248:1248)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (157:157:157) (212:212:212)) + (PORT datab (113:113:113) (146:146:146)) + (PORT datac (134:134:134) (178:178:178)) + (PORT datad (463:463:463) (544:544:544)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (679:679:679) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1314:1314:1314) (1518:1518:1518)) + (PORT ena (515:515:515) (556:556:556)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1314:1314:1314) (1517:1517:1517)) + (PORT ena (506:506:506) (537:537:537)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (255:255:255) (309:309:309)) + (PORT datab (268:268:268) (320:320:320)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (1077:1077:1077) (1239:1239:1239)) (PORT ena (405:405:405) (422:422:422)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -20250,152 +22663,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) (DELAY (ABSOLUTE - (PORT dataa (310:310:310) (367:367:367)) - (PORT datab (136:136:136) (172:172:172)) - (PORT datad (615:615:615) (707:707:707)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (818:818:818)) - (PORT datab (870:870:870) (1003:1003:1003)) - (PORT datac (323:323:323) (381:381:381)) - (PORT datad (1265:1265:1265) (1460:1460:1460)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (489:489:489) (532:532:532)) - (PORT ena (417:417:417) (434:434:434)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT datab (1019:1019:1019) (1188:1188:1188)) - (PORT datac (473:473:473) (543:543:543)) - (PORT datad (723:723:723) (833:833:833)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (491:491:491) (535:535:535)) - (PORT ena (772:772:772) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (159:159:159) (201:201:201)) - (PORT datab (378:378:378) (456:456:456)) - (PORT datad (120:120:120) (158:158:158)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (453:453:453) (539:539:539)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (178:178:178) (214:214:214)) - (PORT datad (299:299:299) (346:346:346)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (663:663:663) (741:741:741)) - (PORT ena (630:630:630) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (658:658:658) (735:735:735)) - (PORT ena (617:617:617) (660:660:660)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (264:264:264)) - (PORT datab (371:371:371) (442:442:442)) - (PORT datad (344:344:344) (407:407:407)) + (PORT dataa (441:441:441) (511:511:511)) + (PORT datab (651:651:651) (753:753:753)) + (PORT datad (130:130:130) (158:158:158)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -20405,12 +22678,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (667:667:667) (746:746:746)) - (PORT ena (641:641:641) (690:690:690)) + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (676:676:676) (761:761:761)) + (PORT ena (405:405:405) (422:422:422)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20421,12 +22694,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (664:664:664) (743:743:743)) - (PORT ena (688:688:688) (756:756:756)) + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (1217:1217:1217) (1390:1390:1390)) + (PORT ena (582:582:582) (618:618:618)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20437,12 +22710,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (381:381:381) (451:451:451)) - (PORT datad (372:372:372) (438:438:438)) + (PORT dataa (203:203:203) (261:261:261)) + (PORT datab (478:478:478) (558:558:558)) + (PORT datad (192:192:192) (220:220:220)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -20451,28 +22724,784 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (299:299:299) (343:343:343)) - (PORT datad (454:454:454) (518:518:518)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (808:808:808) (912:912:912)) + (PORT ena (670:670:670) (742:742:742)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (808:808:808) (913:913:913)) + (PORT ena (627:627:627) (675:675:675)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (841:841:841)) + (PORT datab (662:662:662) (774:774:774)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (776:776:776) (851:851:851)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (1217:1217:1217) (1391:1391:1391)) + (PORT ena (673:673:673) (745:745:745)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (685:685:685)) + (PORT datab (372:372:372) (450:450:450)) + (PORT datad (461:461:461) (531:531:531)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) (DELAY (ABSOLUTE - (PORT dataa (872:872:872) (1023:1023:1023)) - (PORT datab (184:184:184) (220:220:220)) - (PORT datac (428:428:428) (490:490:490)) - (PORT datad (320:320:320) (372:372:372)) + (PORT dataa (321:321:321) (376:376:376)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (317:317:317) (369:369:369)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (666:666:666) (766:766:766)) + (PORT ena (753:753:753) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (666:666:666) (766:766:766)) + (PORT ena (759:759:759) (842:842:842)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (625:625:625)) + (PORT datab (512:512:512) (620:620:620)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (1196:1196:1196) (1350:1350:1350)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (509:509:509) (608:608:608)) + (PORT datab (669:669:669) (792:792:792)) + (PORT datad (482:482:482) (561:561:561)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (390:390:390)) + (PORT datab (338:338:338) (404:404:404)) + (PORT datac (254:254:254) (292:292:292)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (602:602:602)) + (PORT datab (349:349:349) (415:415:415)) + (PORT datac (440:440:440) (529:529:529)) + (PORT datad (731:731:731) (840:840:840)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (923:923:923)) + (PORT asdata (618:618:618) (706:706:706)) + (PORT ena (480:480:480) (509:509:509)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (266:266:266)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datad (199:199:199) (234:234:234)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (348:348:348) (415:415:415)) + (PORT datad (347:347:347) (404:404:404)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (388:388:388) (458:458:458)) + (PORT datac (436:436:436) (506:506:506)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (583:583:583)) + (PORT datac (191:191:191) (227:227:227)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (163:163:163) (188:188:188)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (920:920:920) (905:905:905)) + (PORT ena (1106:1106:1106) (1248:1248:1248)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (727:727:727)) + (PORT datab (213:213:213) (269:269:269)) + (PORT datac (602:602:602) (688:688:688)) + (PORT datad (345:345:345) (400:400:400)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (127:127:127) (173:173:173)) + (PORT datad (171:171:171) (203:203:203)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (391:391:391) (461:461:461)) + (PORT datac (443:443:443) (513:513:513)) + (PORT datad (288:288:288) (331:331:331)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (606:606:606)) + (PORT datab (356:356:356) (422:422:422)) + (PORT datac (452:452:452) (521:521:521)) + (PORT datad (729:729:729) (839:839:839)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (708:708:708) (836:836:836)) + (PORT datab (543:543:543) (638:638:638)) + (PORT datac (1055:1055:1055) (1229:1229:1229)) + (PORT datad (441:441:441) (512:512:512)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (138:138:138) (178:178:178)) + (PORT datac (648:648:648) (749:749:749)) + (PORT datad (521:521:521) (607:607:607)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (584:584:584)) + (PORT datab (661:661:661) (793:793:793)) + (PORT datac (497:497:497) (566:566:566)) + (PORT datad (768:768:768) (892:892:892)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (569:569:569)) + (PORT datab (353:353:353) (410:410:410)) + (PORT datac (359:359:359) (429:429:429)) + (PORT datad (361:361:361) (420:420:420)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (1031:1031:1031)) + (PORT datab (803:803:803) (960:960:960)) + (PORT datac (791:791:791) (910:910:910)) + (PORT datad (459:459:459) (527:527:527)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (312:312:312) (371:371:371)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (596:596:596) (686:686:686)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (747:747:747)) + (PORT datab (550:550:550) (650:650:650)) + (PORT datac (114:114:114) (141:141:141)) + (PORT datad (1129:1129:1129) (1300:1300:1300)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (112:112:112) (147:147:147)) + (PORT datab (334:334:334) (391:391:391)) + (PORT datac (318:318:318) (373:373:373)) + (PORT datad (335:335:335) (384:384:384)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (461:461:461)) + (PORT datac (738:738:738) (842:842:842)) + (PORT datad (620:620:620) (724:724:724)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (1100:1100:1100)) + (PORT datab (830:830:830) (971:971:971)) + (PORT datac (1441:1441:1441) (1671:1671:1671)) + (PORT datad (1064:1064:1064) (1245:1245:1245)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1278:1278:1278)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (514:514:514) (598:598:598)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (409:409:409)) + (PORT datab (344:344:344) (403:403:403)) + (PORT datad (484:484:484) (562:562:562)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (786:786:786)) + (PORT datab (135:135:135) (186:186:186)) + (PORT datac (749:749:749) (866:866:866)) + (PORT datad (649:649:649) (771:771:771)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datad (643:643:643) (762:762:762)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (487:487:487) (552:552:552)) + (PORT datad (768:768:768) (891:891:891)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (254:254:254)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (483:483:483) (561:561:561)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (295:295:295)) + (PORT datab (647:647:647) (748:748:748)) + (PORT datac (321:321:321) (379:379:379)) + (PORT datad (368:368:368) (435:435:435)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (752:752:752)) + (PORT datab (152:152:152) (195:195:195)) + (PORT datac (135:135:135) (174:174:174)) + (PORT datad (140:140:140) (171:171:171)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (216:216:216)) + (PORT datab (433:433:433) (505:505:505)) + (PORT datac (258:258:258) (289:289:289)) + (PORT datad (604:604:604) (695:695:695)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (378:378:378)) + (PORT datab (549:549:549) (648:648:648)) + (PORT datac (311:311:311) (363:363:363)) + (PORT datad (121:121:121) (151:151:151)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (230:230:230)) + (PORT datab (493:493:493) (573:573:573)) + (PORT datac (627:627:627) (727:727:727)) + (PORT datad (373:373:373) (444:444:444)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (440:440:440)) + (PORT datab (659:659:659) (762:762:762)) + (PORT datac (332:332:332) (403:403:403)) + (PORT datad (370:370:370) (438:438:438)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (199:199:199)) + (PORT datad (134:134:134) (165:165:165)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (153:153:153) (198:198:198)) + (PORT datab (321:321:321) (379:379:379)) + (PORT datac (630:630:630) (728:728:728)) + (PORT datad (91:91:91) (108:108:108)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -20482,43 +23511,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (INSTANCE z80_\|alu_\|result_lo\[3\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (473:473:473) (516:516:516)) - (PORT ena (420:420:420) (440:440:440)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (538:538:538)) - (PORT datab (130:130:130) (164:164:164)) - (PORT datad (675:675:675) (768:768:768)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) + (PORT clk (901:901:901) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (530:530:530) (580:580:580)) + (PORT ena (676:676:676) (740:740:740)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20529,14 +23527,1129 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (INSTANCE z80_\|alu_\|db_low\[3\]\~7) (DELAY (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (130:130:130) (158:158:158)) - (PORT datad (222:222:222) (277:277:277)) + (PORT dataa (523:523:523) (609:609:609)) + (PORT datac (914:914:914) (1063:1063:1063)) + (PORT datad (777:777:777) (877:877:877)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (693:693:693)) + (PORT datab (615:615:615) (716:716:716)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (131:131:131) (159:159:159)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (311:311:311)) + (PORT datab (466:466:466) (560:560:560)) + (PORT datac (520:520:520) (618:618:618)) + (PORT datad (316:316:316) (367:367:367)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (761:761:761)) + (PORT datab (328:328:328) (388:388:388)) + (PORT datac (102:102:102) (129:129:129)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (417:417:417)) + (PORT datab (503:503:503) (584:584:584)) + (PORT datac (459:459:459) (534:534:534)) + (PORT datad (647:647:647) (738:738:738)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (405:405:405)) + (PORT datab (539:539:539) (632:632:632)) + (PORT datac (635:635:635) (724:724:724)) + (PORT datad (120:120:120) (151:151:151)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (155:155:155)) + (PORT datab (817:817:817) (945:945:945)) + (PORT datac (620:620:620) (709:709:709)) + (PORT datad (92:92:92) (111:111:111)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~49) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (763:763:763)) + (PORT datab (510:510:510) (590:590:590)) + (PORT datac (275:275:275) (319:319:319)) + (PORT datad (447:447:447) (511:511:511)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (957:957:957)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (127:127:127) (154:154:154)) + (PORT datad (782:782:782) (893:893:893)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (PORT datab (337:337:337) (394:394:394)) + (PORT datac (351:351:351) (419:419:419)) + (PORT datad (369:369:369) (431:431:431)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datab (334:334:334) (395:395:395)) + (PORT datad (467:467:467) (556:556:556)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (398:398:398)) + (PORT datab (1272:1272:1272) (1479:1479:1479)) + (PORT datac (1155:1155:1155) (1344:1344:1344)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (247:247:247)) + (PORT datab (922:922:922) (1054:1054:1054)) + (PORT datac (453:453:453) (515:515:515)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (559:559:559)) + (PORT datab (185:185:185) (226:226:226)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (607:607:607)) + (PORT datab (369:369:369) (432:432:432)) + (PORT datac (302:302:302) (347:347:347)) + (PORT datad (332:332:332) (387:387:387)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (515:515:515) (602:602:602)) + (PORT datac (354:354:354) (422:422:422)) + (PORT datad (355:355:355) (423:423:423)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (178:178:178) (215:215:215)) + (PORT datab (110:110:110) (142:142:142)) + (PORT datac (92:92:92) (115:115:115)) + (PORT datad (354:354:354) (414:414:414)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (542:542:542)) + (PORT datab (561:561:561) (649:649:649)) + (PORT datac (813:813:813) (945:945:945)) + (PORT datad (636:636:636) (725:725:725)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (419:419:419)) + (PORT datab (510:510:510) (596:596:596)) + (PORT datac (831:831:831) (950:950:950)) + (PORT datad (625:625:625) (717:717:717)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (384:384:384)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (479:479:479) (558:558:558)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT datab (926:926:926) (1053:1053:1053)) + (PORT datac (804:804:804) (935:935:935)) + (PORT datad (645:645:645) (743:743:743)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (284:284:284)) + (PORT datab (687:687:687) (799:799:799)) + (PORT datac (631:631:631) (721:721:721)) + (PORT datad (503:503:503) (574:574:574)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (552:552:552)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (476:476:476) (549:549:549)) + (PORT datad (342:342:342) (397:397:397)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (391:391:391)) + (PORT datab (133:133:133) (168:168:168)) + (PORT datac (627:627:627) (722:722:722)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (299:299:299)) + (PORT datab (630:630:630) (725:725:725)) + (PORT datad (805:805:805) (920:920:920)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (274:274:274)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (881:881:881) (999:999:999)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) + (DELAY + (ABSOLUTE + (PORT datab (182:182:182) (224:224:224)) + (PORT datac (419:419:419) (476:476:476)) + (PORT datad (164:164:164) (193:193:193)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (527:527:527) (588:588:588)) + (PORT ena (756:756:756) (816:816:816)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (527:527:527) (588:588:588)) + (PORT ena (915:915:915) (1002:1002:1002)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (187:187:187)) + (PORT datab (546:546:546) (643:643:643)) + (PORT datad (470:470:470) (544:544:544)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (451:451:451) (486:486:486)) + (PORT ena (419:419:419) (435:435:435)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (451:451:451) (486:486:486)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (137:137:137) (176:176:176)) + (PORT datad (121:121:121) (146:146:146)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (451:451:451) (520:520:520)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (327:327:327) (382:382:382)) + (PORT datad (335:335:335) (393:393:393)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (542:542:542)) + (PORT datab (328:328:328) (383:383:383)) + (PORT datac (172:172:172) (202:202:202)) + (PORT datad (603:603:603) (692:692:692)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (515:515:515) (573:573:573)) + (PORT ena (636:636:636) (682:682:682)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (825:825:825)) + (PORT datab (383:383:383) (454:454:454)) + (PORT datad (659:659:659) (768:768:768)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (679:679:679) (746:746:746)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (401:401:401)) + (PORT datac (386:386:386) (461:461:461)) + (PORT datad (119:119:119) (157:157:157)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (230:230:230)) + (PORT datab (526:526:526) (617:617:617)) + (PORT datac (376:376:376) (448:448:448)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT datab (129:129:129) (162:162:162)) + (PORT datac (283:283:283) (331:331:331)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (928:928:928)) + (PORT asdata (447:447:447) (488:488:488)) + (PORT clrn (927:927:927) (909:909:909)) + (PORT ena (1168:1168:1168) (1321:1321:1321)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (245:245:245)) + (PORT datab (634:634:634) (730:730:730)) + (PORT datac (543:543:543) (635:635:635)) + (PORT datad (132:132:132) (170:170:170)) + (IOPATH dataa combout (181:181:181) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (179:179:179) (223:223:223)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (177:177:177) (209:209:209)) + (PORT datad (165:165:165) (195:195:195)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (659:659:659) (731:731:731)) + (PORT ena (419:419:419) (435:435:435)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (655:655:655) (727:727:727)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (137:137:137) (175:175:175)) + (PORT datad (122:122:122) (147:147:147)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (387:387:387)) + (PORT datab (627:627:627) (721:721:721)) + (PORT datad (336:336:336) (393:393:393)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT asdata (634:634:634) (705:705:705)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT asdata (638:638:638) (710:710:710)) + (PORT ena (669:669:669) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (273:273:273)) + (PORT datab (314:314:314) (372:372:372)) + (PORT datad (119:119:119) (157:157:157)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (794:794:794) (880:880:880)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (492:492:492) (533:533:533)) + (PORT ena (631:631:631) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (493:493:493) (533:533:533)) + (PORT ena (660:660:660) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (294:294:294)) + (PORT datab (359:359:359) (425:425:425)) + (PORT datad (117:117:117) (152:152:152)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (PORT datab (493:493:493) (580:580:580)) + (PORT datac (114:114:114) (155:155:155)) + (PORT datad (170:170:170) (201:201:201)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (531:531:531) (590:590:590)) + (PORT ena (915:915:915) (1002:1002:1002)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (534:534:534) (593:593:593)) + (PORT ena (756:756:756) (816:816:816)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (572:572:572)) + (PORT datab (537:537:537) (632:632:632)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (918:918:918)) + (PORT asdata (523:523:523) (580:580:580)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (918:918:918)) + (PORT asdata (523:523:523) (579:579:579)) + (PORT ena (644:644:644) (698:698:698)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (431:431:431)) + (PORT datab (209:209:209) (253:253:253)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (453:453:453) (485:485:485)) + (PORT ena (736:736:736) (793:793:793)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (317:317:317)) + (PORT datad (433:433:433) (505:505:505)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (215:215:215)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (544:544:544) (619:619:619)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (463:463:463) (533:533:533)) + (PORT datac (614:614:614) (701:701:701)) + (PORT datad (635:635:635) (735:735:735)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (729:729:729) (807:807:807)) + (PORT ena (636:636:636) (682:682:682)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (546:546:546)) + (PORT datab (681:681:681) (797:797:797)) + (PORT datad (365:365:365) (428:428:428)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (679:679:679) (746:746:746)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (349:349:349) (408:408:408)) + (PORT datac (385:385:385) (459:459:459)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (230:230:230)) + (PORT datab (527:527:527) (619:619:619)) + (PORT datac (375:375:375) (448:448:448)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -20546,9 +24659,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[4\]) (DELAY (ABSOLUTE - (PORT datac (477:477:477) (552:552:552)) - (PORT datad (730:730:730) (859:859:859)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (126:126:126) (159:159:159)) + (PORT datad (272:272:272) (314:314:314)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -20558,10 +24671,10 @@ (INSTANCE z80_\|address_latch_\|Q\[4\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (914:914:914)) - (PORT asdata (281:281:281) (301:301:301)) - (PORT clrn (909:909:909) (894:894:894)) - (PORT ena (1199:1199:1199) (1327:1327:1327)) + (PORT clk (920:920:920) (928:928:928)) + (PORT asdata (441:441:441) (473:473:473)) + (PORT clrn (927:927:927) (909:909:909)) + (PORT ena (1168:1168:1168) (1321:1321:1321)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -20576,10 +24689,13 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) (DELAY (ABSOLUTE - (PORT datab (601:601:601) (716:716:716)) - (PORT datac (501:501:501) (619:619:619)) - (IOPATH datab combout (196:196:196) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (620:620:620) (721:721:721)) + (PORT datab (546:546:546) (639:639:639)) + (PORT datad (106:106:106) (124:124:124)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -20588,71 +24704,12 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) (DELAY (ABSOLUTE - (PORT dataa (494:494:494) (577:577:577)) - (PORT datab (518:518:518) (643:643:643)) - (PORT datac (582:582:582) (696:696:696)) - (PORT datad (370:370:370) (449:449:449)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (190:190:190) (205:205:205)) + (PORT dataa (362:362:362) (439:439:439)) + (PORT datab (642:642:642) (741:741:741)) + (PORT datac (338:338:338) (393:393:393)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (501:501:501) (578:578:578)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (641:641:641) (690:690:690)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (658:658:658) (722:722:722)) - (PORT ena (688:688:688) (756:756:756)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (385:385:385) (457:457:457)) - (PORT datad (373:373:373) (440:440:440)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -20661,9 +24718,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (1013:1013:1013) (1136:1136:1136)) - (PORT ena (630:630:630) (680:680:680)) + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (458:458:458) (495:495:495)) + (PORT ena (756:756:756) (816:816:816)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20677,9 +24734,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (1008:1008:1008) (1131:1131:1131)) - (PORT ena (617:617:617) (660:660:660)) + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (458:458:458) (495:495:495)) + (PORT ena (915:915:915) (1002:1002:1002)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20693,9 +24750,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) (DELAY (ABSOLUTE - (PORT dataa (204:204:204) (262:262:262)) - (PORT datab (379:379:379) (452:452:452)) - (PORT datad (353:353:353) (417:417:417)) + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (541:541:541) (636:636:636)) + (PORT datad (470:470:470) (544:544:544)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -20705,12 +24762,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (544:544:544) (598:598:598)) - (PORT ena (659:659:659) (712:712:712)) + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (359:359:359) (387:387:387)) + (PORT ena (781:781:781) (840:840:840)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20721,12 +24778,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (544:544:544) (598:598:598)) - (PORT ena (759:759:759) (815:815:815)) + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (359:359:359) (387:387:387)) + (PORT ena (662:662:662) (720:720:720)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20737,71 +24794,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) (DELAY (ABSOLUTE - (PORT dataa (335:335:335) (409:409:409)) - (PORT datab (484:484:484) (561:561:561)) - (PORT datad (117:117:117) (153:153:153)) + (PORT dataa (613:613:613) (704:704:704)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (358:358:358) (416:416:416)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (658:658:658) (754:754:754)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (417:417:417) (434:434:434)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (913:913:913)) - (PORT asdata (504:504:504) (552:552:552)) - (PORT ena (807:807:807) (897:897:897)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (403:403:403)) - (PORT datab (340:340:340) (408:408:408)) - (PORT datad (310:310:310) (357:357:357)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -20809,12 +24809,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (284:284:284) (307:307:307)) - (PORT ena (766:766:766) (843:843:843)) + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (764:764:764) (851:851:851)) + (PORT ena (794:794:794) (880:880:880)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20823,45 +24823,14 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT asdata (494:494:494) (531:531:531)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (606:606:606)) - (PORT datab (493:493:493) (567:567:567)) - (PORT datad (125:125:125) (150:150:150)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (378:378:378) (412:412:412)) - (PORT ena (641:641:641) (691:691:691)) + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (774:774:774) (864:864:864)) + (PORT ena (631:631:631) (680:680:680)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20875,11 +24844,24 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) (DELAY (ABSOLUTE - (PORT dataa (157:157:157) (204:204:204)) - (PORT datab (516:516:516) (611:611:611)) - (PORT datad (436:436:436) (498:498:498)) + (PORT dataa (224:224:224) (284:284:284)) + (PORT datab (625:625:625) (718:718:718)) + (PORT datad (334:334:334) (382:382:382)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT datab (492:492:492) (579:579:579)) + (PORT datad (171:171:171) (203:203:203)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -20887,12 +24869,28 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (913:913:913)) - (PORT asdata (502:502:502) (550:550:550)) - (PORT ena (421:421:421) (441:441:441)) + (PORT clk (911:911:911) (918:918:918)) + (PORT asdata (638:638:638) (711:711:711)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT asdata (637:637:637) (710:710:710)) + (PORT ena (669:669:669) (725:725:725)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20903,12 +24901,128 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) (DELAY (ABSOLUTE - (PORT datab (197:197:197) (239:239:239)) - (PORT datad (115:115:115) (136:136:136)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (217:217:217) (273:273:273)) + (PORT datab (315:315:315) (374:374:374)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (918:918:918)) + (PORT asdata (789:789:789) (871:871:871)) + (PORT ena (644:644:644) (698:698:698)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (329:329:329) (377:377:377)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (426:426:426)) + (PORT datab (202:202:202) (245:245:245)) + (PORT datad (115:115:115) (152:152:152)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (461:461:461) (525:525:525)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (736:736:736) (793:793:793)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (774:774:774) (864:864:864)) + (PORT ena (660:660:660) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (366:366:366)) + (PORT datab (441:441:441) (518:518:518)) + (PORT datad (347:347:347) (405:405:405)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -20919,10 +25033,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) (DELAY (ABSOLUTE - (PORT dataa (453:453:453) (540:540:540)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (173:173:173) (209:209:209)) - (PORT datad (91:91:91) (108:108:108)) + (PORT dataa (343:343:343) (401:401:401)) + (PORT datab (609:609:609) (697:697:697)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (320:320:320) (370:370:370)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -20935,11 +25049,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) (DELAY (ABSOLUTE - (PORT dataa (450:450:450) (525:525:525)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datad (446:446:446) (513:513:513)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (189:189:189) (226:226:226)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -20949,12 +25063,12 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) (DELAY (ABSOLUTE - (PORT dataa (724:724:724) (824:824:824)) - (PORT datab (298:298:298) (347:347:347)) - (PORT datac (181:181:181) (211:211:211)) - (PORT datad (746:746:746) (880:880:880)) + (PORT dataa (354:354:354) (419:419:419)) + (PORT datab (522:522:522) (603:603:603)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (878:878:878) (998:998:998)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -20965,9 +25079,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (359:359:359) (388:388:388)) - (PORT ena (420:420:420) (440:440:440)) + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (650:650:650) (724:724:724)) + (PORT ena (636:636:636) (682:682:682)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20981,34 +25095,24 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) (DELAY (ABSOLUTE - (PORT dataa (123:123:123) (157:157:157)) - (PORT datab (129:129:129) (163:163:163)) - (PORT datad (676:676:676) (768:768:768)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (649:649:649) (740:740:740)) + (PORT datab (681:681:681) (798:798:798)) + (PORT datad (365:365:365) (428:428:428)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (102:102:102) (119:119:119)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) + (PORT clk (914:914:914) (922:922:922)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (655:655:655) (721:721:721)) + (PORT ena (419:419:419) (435:435:435)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21022,11 +25126,11 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) (DELAY (ABSOLUTE - (PORT dataa (192:192:192) (231:231:231)) - (PORT datac (202:202:202) (237:237:237)) - (PORT datad (120:120:120) (157:157:157)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (120:120:120) (153:153:153)) + (PORT datac (333:333:333) (385:385:385)) + (PORT datad (119:119:119) (157:157:157)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -21036,12 +25140,12 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) (DELAY (ABSOLUTE - (PORT dataa (713:713:713) (841:841:841)) - (PORT datab (324:324:324) (383:383:383)) - (PORT datac (299:299:299) (344:344:344)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (348:348:348) (404:404:404)) + (PORT datab (715:715:715) (816:816:816)) + (PORT datac (101:101:101) (121:121:121)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -21052,19 +25156,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[5\]) (DELAY (ABSOLUTE - (PORT datac (345:345:345) (394:394:394)) - (PORT datad (734:734:734) (863:863:863)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (102:102:102) (118:118:118)) + (PORT datac (358:358:358) (420:420:420)) + (PORT datad (437:437:437) (498:498:498)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -21074,10 +25168,10 @@ (INSTANCE z80_\|address_latch_\|Q\[5\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (914:914:914)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (894:894:894)) - (PORT ena (1199:1199:1199) (1327:1327:1327)) + (PORT clrn (920:920:920) (904:904:904)) + (PORT ena (1159:1159:1159) (1318:1318:1318)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -21089,15 +25183,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) (DELAY (ABSOLUTE - (PORT dataa (327:327:327) (403:403:403)) - (PORT datab (603:603:603) (702:702:702)) - (PORT datac (98:98:98) (125:125:125)) - (PORT datad (574:574:574) (659:659:659)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (190:190:190) (197:197:197)) + (PORT dataa (493:493:493) (588:588:588)) + (PORT datab (633:633:633) (729:729:729)) + (PORT datac (541:541:541) (633:633:633)) + (PORT datad (190:190:190) (221:221:221)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (182:182:182) (188:188:188)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -21108,10 +25202,10 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) (DELAY (ABSOLUTE - (PORT dataa (495:495:495) (578:578:578)) - (PORT datab (108:108:108) (140:140:140)) - (PORT datac (320:320:320) (389:389:389)) - (PORT datad (473:473:473) (549:549:549)) + (PORT dataa (354:354:354) (419:419:419)) + (PORT datab (640:640:640) (739:739:739)) + (PORT datac (422:422:422) (496:496:496)) + (PORT datad (332:332:332) (388:388:388)) (IOPATH dataa combout (158:158:158) (173:173:173)) (IOPATH datab combout (160:160:160) (176:176:176)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -21119,18 +25213,451 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (679:679:679) (746:746:746)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (903:903:903) (1009:1009:1009)) + (PORT ena (915:915:915) (1002:1002:1002)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (724:724:724) (832:832:832)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (756:756:756) (816:816:816)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (571:571:571)) + (PORT datab (538:538:538) (634:634:634)) + (PORT datad (118:118:118) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (1013:1013:1013) (1123:1123:1123)) + (PORT ena (781:781:781) (840:840:840)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (1011:1011:1011) (1120:1120:1120)) + (PORT ena (662:662:662) (720:720:720)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (701:701:701)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (354:354:354) (412:412:412)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (917:917:917)) + (PORT asdata (1171:1171:1171) (1302:1302:1302)) + (PORT ena (649:649:649) (703:703:703)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (571:571:571) (650:650:650)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (266:266:266)) + (PORT datab (346:346:346) (409:409:409)) + (PORT datad (194:194:194) (242:242:242)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (764:764:764) (834:834:834)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (456:456:456)) + (PORT datab (525:525:525) (610:610:610)) + (PORT datac (479:479:479) (549:549:549)) + (PORT datad (332:332:332) (386:386:386)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (917:917:917)) + (PORT asdata (1171:1171:1171) (1301:1301:1301)) + (PORT ena (812:812:812) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (703:703:703) (802:802:802)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (660:660:660) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (875:875:875) (968:968:968)) + (PORT ena (631:631:631) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (292:292:292)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (345:345:345) (403:403:403)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT datab (767:767:767) (883:883:883)) + (PORT datad (302:302:302) (347:347:347)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT asdata (724:724:724) (793:793:793)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (788:788:788) (871:871:871)) + (PORT ena (433:433:433) (461:461:461)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (277:277:277)) + (PORT datab (305:305:305) (362:362:362)) + (PORT datad (454:454:454) (533:533:533)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (227:227:227)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (422:422:422) (480:480:480)) + (PORT datad (410:410:410) (465:465:465)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (386:386:386)) + (PORT datab (367:367:367) (432:432:432)) + (PORT datac (747:747:747) (864:864:864)) + (PORT datad (309:309:309) (352:352:352)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (527:527:527) (588:588:588)) + (PORT ena (636:636:636) (682:682:682)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (841:841:841)) + (PORT datab (676:676:676) (792:792:792)) + (PORT datad (362:362:362) (425:425:425)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (369:369:369) (432:432:432)) + (PORT datac (372:372:372) (446:446:446)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) (DELAY (ABSOLUTE - (PORT dataa (325:325:325) (378:378:378)) - (PORT datab (716:716:716) (815:815:815)) - (PORT datac (296:296:296) (347:347:347)) - (PORT datad (807:807:807) (964:964:964)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (392:392:392) (472:472:472)) + (PORT datab (352:352:352) (417:417:417)) + (PORT datac (511:511:511) (598:598:598)) + (PORT datad (335:335:335) (391:391:391)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -21140,9 +25667,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[6\]) (DELAY (ABSOLUTE - (PORT datac (467:467:467) (538:538:538)) - (PORT datad (683:683:683) (808:808:808)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datac (359:359:359) (421:421:421)) + (PORT datad (442:442:442) (510:510:510)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -21152,10 +25679,10 @@ (INSTANCE z80_\|address_latch_\|Q\[6\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (923:923:923) (905:905:905)) - (PORT ena (1450:1450:1450) (1621:1621:1621)) + (PORT clrn (920:920:920) (904:904:904)) + (PORT ena (1159:1159:1159) (1318:1318:1318)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -21167,16 +25694,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~2) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) (DELAY (ABSOLUTE - (PORT dataa (794:794:794) (941:941:941)) - (PORT datab (738:738:738) (873:873:873)) - (PORT datac (338:338:338) (406:406:406)) - (PORT datad (329:329:329) (381:381:381)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (344:344:344) (407:407:407)) + (PORT datab (346:346:346) (408:408:408)) + (PORT datac (422:422:422) (497:497:497)) + (PORT datad (625:625:625) (721:721:721)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -21186,10 +25713,10 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) (DELAY (ABSOLUTE - (PORT dataa (327:327:327) (386:386:386)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (480:480:480) (554:554:554)) - (PORT datad (473:473:473) (548:548:548)) + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (636:636:636) (735:735:735)) + (PORT datac (341:341:341) (397:397:397)) + (PORT datad (333:333:333) (389:389:389)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -21202,35 +25729,25 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) (DELAY (ABSOLUTE - (PORT datac (487:487:487) (573:573:573)) - (PORT datad (326:326:326) (375:375:375)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (227:227:227) (295:295:295)) + (PORT datad (101:101:101) (122:122:122)) + (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (651:651:651) (733:733:733)) - (PORT ena (688:688:688) (756:756:756)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]\~feeder) + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) (DELAY (ABSOLUTE - (PORT datad (469:469:469) (547:547:547)) + (PORT dataa (388:388:388) (467:467:467)) + (PORT datab (529:529:529) (620:620:620)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (337:337:337) (390:390:390)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -21240,40 +25757,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (641:641:641) (690:690:690)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (397:397:397) (470:470:470)) - (PORT datab (384:384:384) (455:455:455)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (820:820:820) (928:928:928)) - (PORT ena (630:630:630) (680:680:680)) + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (644:644:644) (723:723:723)) + (PORT ena (781:781:781) (840:840:840)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21282,14 +25768,61 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (643:643:643) (722:722:722)) + (PORT ena (662:662:662) (720:720:720)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (702:702:702)) + (PORT datab (130:130:130) (179:179:179)) + (PORT datad (355:355:355) (414:414:414)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (819:819:819) (927:927:927)) - (PORT ena (617:617:617) (660:660:660)) + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (761:761:761) (847:847:847)) + (PORT ena (915:915:915) (1002:1002:1002)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (762:762:762) (848:848:848)) + (PORT ena (756:756:756) (816:816:816)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21303,10 +25836,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (258:258:258)) - (PORT datab (376:376:376) (449:449:449)) - (PORT datad (349:349:349) (413:413:413)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (489:489:489) (574:574:574)) + (PORT datab (534:534:534) (629:629:629)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -21318,9 +25851,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (809:809:809) (915:915:915)) - (PORT ena (417:417:417) (434:434:434)) + (PORT clk (910:910:910) (917:917:917)) + (PORT asdata (1049:1049:1049) (1178:1178:1178)) + (PORT ena (649:649:649) (703:703:703)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21329,19 +25862,29 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (880:880:880) (1011:1011:1011)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (809:809:809) (915:915:915)) - (PORT ena (772:772:772) (842:842:842)) + (PORT clk (910:910:910) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -21350,9 +25893,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) (DELAY (ABSOLUTE - (PORT dataa (155:155:155) (197:197:197)) - (PORT datab (379:379:379) (457:457:457)) - (PORT datad (117:117:117) (154:154:154)) + (PORT dataa (221:221:221) (268:268:268)) + (PORT datab (348:348:348) (411:411:411)) + (PORT datad (193:193:193) (240:240:240)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -21362,12 +25905,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (359:359:359) (400:400:400)) - (PORT ena (434:434:434) (462:462:462)) + (PORT clk (910:910:910) (917:917:917)) + (PORT asdata (1047:1047:1047) (1177:1177:1177)) + (PORT ena (812:812:812) (885:885:885)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21376,60 +25919,19 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (336:336:336) (392:392:392)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (759:759:759) (815:815:815)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (570:570:570)) - (PORT datab (184:184:184) (223:223:223)) - (PORT datad (334:334:334) (401:401:401)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (804:804:804) (906:906:906)) + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (1058:1058:1058) (1183:1183:1183)) + (PORT ena (660:660:660) (723:723:723)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -21438,9 +25940,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (355:355:355) (389:389:389)) - (PORT ena (641:641:641) (691:691:691)) + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (1057:1057:1057) (1183:1183:1183)) + (PORT ena (631:631:631) (680:680:680)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21454,9 +25956,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) (DELAY (ABSOLUTE - (PORT dataa (151:151:151) (196:196:196)) - (PORT datab (132:132:132) (180:180:180)) - (PORT datad (310:310:310) (362:362:362)) + (PORT dataa (225:225:225) (285:285:285)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (347:347:347) (405:405:405)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -21465,13 +25967,42 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (360:360:360) (401:401:401)) - (PORT ena (771:771:771) (831:831:831)) + (PORT datab (768:768:768) (884:884:884)) + (PORT datad (312:312:312) (360:360:360)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT asdata (942:942:942) (1061:1061:1061)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT asdata (941:941:941) (1060:1060:1060)) + (PORT ena (669:669:669) (725:725:725)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21482,12 +26013,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) (DELAY (ABSOLUTE - (PORT dataa (175:175:175) (217:217:217)) - (PORT datad (331:331:331) (389:389:389)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (218:218:218) (274:274:274)) + (PORT datab (313:313:313) (371:371:371)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -21498,14 +26031,14 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT asdata (945:945:945) (1065:1065:1065)) - (PORT ena (405:405:405) (422:422:422)) + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (764:764:764) (834:834:834)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -21514,12 +26047,13 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) (DELAY (ABSOLUTE - (PORT dataa (313:313:313) (371:371:371)) - (PORT datab (139:139:139) (176:176:176)) - (PORT datad (327:327:327) (385:385:385)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (356:356:356) (437:437:437)) + (PORT datab (525:525:525) (610:610:610)) + (PORT datac (444:444:444) (513:513:513)) + (PORT datad (330:330:330) (383:383:383)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -21529,10 +26063,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) (DELAY (ABSOLUTE - (PORT dataa (173:173:173) (210:210:210)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (293:293:293) (338:338:338)) + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (260:260:260) (292:292:292)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -21545,11 +26079,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) (DELAY (ABSOLUTE - (PORT datab (322:322:322) (377:377:377)) - (PORT datac (314:314:314) (361:361:361)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (183:183:183) (219:219:219)) + (PORT datad (306:306:306) (353:353:353)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -21559,125 +26093,42 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) (DELAY (ABSOLUTE - (PORT dataa (731:731:731) (869:869:869)) - (PORT datab (878:878:878) (994:994:994)) - (PORT datac (322:322:322) (378:378:378)) - (PORT datad (167:167:167) (195:195:195)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (371:371:371) (437:437:437)) + (PORT datab (358:358:358) (423:423:423)) + (PORT datac (746:746:746) (863:863:863)) + (PORT datad (310:310:310) (353:353:353)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (339:339:339) (366:366:366)) - (PORT ena (420:420:420) (440:440:440)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~0) (DELAY (ABSOLUTE - (PORT dataa (347:347:347) (420:420:420)) - (PORT datab (131:131:131) (165:165:165)) - (PORT datad (677:677:677) (770:770:770)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (655:655:655) (721:721:721)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (220:220:220)) - (PORT datac (202:202:202) (237:237:237)) - (PORT datad (116:116:116) (152:152:152)) + (PORT dataa (830:830:830) (963:963:963)) + (PORT datab (929:929:929) (1057:1057:1057)) + (PORT datac (467:467:467) (549:549:549)) + (PORT datad (646:646:646) (745:745:745)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (713:713:713) (841:841:841)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (300:300:300) (344:344:344)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT datac (338:338:338) (391:391:391)) - (PORT datad (735:735:735) (866:866:866)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (101:101:101) (119:119:119)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) + (INSTANCE z80_\|interrupts_\|im2) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (914:914:914)) + (PORT clk (906:906:906) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (894:894:894)) - (PORT ena (1199:1199:1199) (1327:1327:1327)) + (PORT clrn (911:911:911) (895:895:895)) + (PORT ena (667:667:667) (732:732:732)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -21689,45 +26140,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (INSTANCE z80_\|execute_\|ctl_mRead\~12) (DELAY (ABSOLUTE - (PORT datac (521:521:521) (609:609:609)) - (PORT datad (679:679:679) (804:804:804)) + (PORT dataa (206:206:206) (284:284:284)) + (PORT datac (681:681:681) (805:805:805)) + (PORT datad (150:150:150) (194:194:194)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (923:923:923) (905:905:905)) - (PORT ena (1450:1450:1450) (1621:1621:1621)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + (PORT dataa (208:208:208) (286:286:286)) + (PORT datab (382:382:382) (455:455:455)) + (PORT datac (100:100:100) (121:121:121)) + (PORT datad (733:733:733) (870:870:870)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (INSTANCE z80_\|alu_control_\|db\[7\]\~17) (DELAY (ABSOLUTE - (PORT dataa (123:123:123) (156:156:156)) - (PORT datab (603:603:603) (719:719:719)) - (PORT datac (366:366:366) (443:443:443)) - (PORT datad (205:205:205) (251:251:251)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (190:190:190) (205:205:205)) + (PORT dataa (473:473:473) (545:545:545)) + (PORT datab (493:493:493) (571:571:571)) + (PORT datac (347:347:347) (410:410:410)) + (PORT datad (343:343:343) (394:394:394)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -21735,374 +26186,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~12) + (INSTANCE z80_\|alu_control_\|db\[7\]\~16) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (488:488:488) (563:563:563)) - (PORT datac (958:958:958) (1137:1137:1137)) - (PORT datad (193:193:193) (229:229:229)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (926:926:926) (1028:1028:1028)) - (PORT ena (422:422:422) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (926:926:926) (1028:1028:1028)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (275:275:275)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (480:480:480) (522:522:522)) - (PORT ena (665:665:665) (721:721:721)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (732:732:732)) - (PORT datab (1040:1040:1040) (1200:1200:1200)) - (PORT datad (898:898:898) (1040:1040:1040)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (520:520:520) (582:582:582)) - (PORT ena (504:504:504) (535:535:535)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (520:520:520) (582:582:582)) - (PORT ena (494:494:494) (536:536:536)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (276:276:276)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (814:814:814) (918:918:918)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (811:811:811)) - (PORT datab (674:674:674) (781:781:781)) - (PORT datad (203:203:203) (235:235:235)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (449:449:449) (521:521:521)) + (PORT datab (460:460:460) (533:533:533)) + (PORT datac (491:491:491) (567:567:567)) + (PORT datad (352:352:352) (423:423:423)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (767:767:767) (833:833:833)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (599:599:599) (657:657:657)) - (PORT ena (774:774:774) (865:865:865)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (296:296:296)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (354:354:354) (416:416:416)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (650:650:650) (725:725:725)) - (PORT ena (649:649:649) (709:709:709)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (649:649:649) (724:724:724)) - (PORT ena (631:631:631) (678:678:678)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (343:343:343) (396:396:396)) - (PORT datad (328:328:328) (374:374:374)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~46) + (INSTANCE z80_\|alu_control_\|db\[7\]\~18) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (397:397:397)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (304:304:304) (350:350:350)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT asdata (794:794:794) (880:880:880)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT asdata (794:794:794) (880:880:880)) - (PORT ena (518:518:518) (563:563:563)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (501:501:501) (589:589:589)) - (PORT datab (129:129:129) (176:176:176)) - (PORT datad (122:122:122) (144:144:144)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (399:399:399)) - (PORT datab (187:187:187) (224:224:224)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (435:435:435) (499:499:499)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (371:371:371)) - (PORT datab (1142:1142:1142) (1347:1347:1347)) - (PORT datac (277:277:277) (316:316:316)) - (PORT datad (296:296:296) (343:343:343)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (478:478:478) (558:558:558)) - (PORT datab (472:472:472) (551:551:551)) - (PORT datac (677:677:677) (793:793:793)) - (PORT datad (606:606:606) (711:711:711)) + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (131:131:131) (166:166:166)) + (PORT datac (354:354:354) (422:422:422)) + (PORT datad (328:328:328) (381:381:381)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -22112,15 +26218,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) (DELAY (ABSOLUTE - (PORT dataa (603:603:603) (698:698:698)) - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (308:308:308) (361:361:361)) - (PORT datad (124:124:124) (155:155:155)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (378:378:378) (444:444:444)) + (PORT datab (499:499:499) (575:575:575)) + (PORT datac (461:461:461) (530:530:530)) + (PORT datad (107:107:107) (125:125:125)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -22128,13 +26234,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) (DELAY (ABSOLUTE - (PORT dataa (628:628:628) (726:726:726)) - (PORT datab (494:494:494) (590:590:590)) - (PORT datac (653:653:653) (785:785:785)) - (PORT datad (573:573:573) (664:664:664)) + (PORT dataa (739:739:739) (872:872:872)) + (PORT datab (486:486:486) (575:575:575)) + (PORT datac (333:333:333) (392:392:392)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (435:435:435) (466:466:466)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (973:973:973)) + (PORT datab (820:820:820) (963:963:963)) + (PORT datac (607:607:607) (704:704:704)) + (PORT datad (358:358:358) (409:409:409)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (712:712:712)) + (PORT datab (401:401:401) (473:473:473)) + (PORT datac (779:779:779) (893:893:893)) + (PORT datad (669:669:669) (779:779:779)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (599:599:599)) + (PORT datab (647:647:647) (748:748:748)) + (PORT datac (404:404:404) (501:501:501)) + (PORT datad (1079:1079:1079) (1263:1263:1263)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -22144,15 +26314,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) (DELAY (ABSOLUTE - (PORT dataa (405:405:405) (499:499:499)) - (PORT datab (488:488:488) (581:581:581)) - (PORT datac (652:652:652) (784:784:784)) - (PORT datad (573:573:573) (664:664:664)) + (PORT dataa (411:411:411) (492:492:492)) + (PORT datab (803:803:803) (961:961:961)) + (PORT datac (614:614:614) (693:693:693)) + (PORT datad (105:105:105) (130:130:130)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (400:400:400)) + (PORT datab (440:440:440) (497:497:497)) + (PORT datac (617:617:617) (699:699:699)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (418:418:418)) + (PORT datab (579:579:579) (679:679:679)) + (PORT datac (302:302:302) (347:347:347)) + (PORT datad (502:502:502) (580:580:580)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -22160,27 +26362,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) (DELAY (ABSOLUTE - (PORT dataa (408:408:408) (502:502:502)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (90:90:90) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (809:809:809)) - (PORT datac (465:465:465) (538:538:538)) + (PORT dataa (380:380:380) (450:450:450)) + (PORT datab (315:315:315) (366:366:366)) + (PORT datac (128:128:128) (169:169:169)) (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -22188,1267 +26378,1173 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~17) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (714:714:714)) + (PORT datab (399:399:399) (471:471:471)) + (PORT datac (509:509:509) (590:590:590)) + (PORT datad (650:650:650) (742:742:742)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (926:926:926)) + (PORT datab (360:360:360) (432:432:432)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (791:791:791) (904:904:904)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (906:906:906)) + (PORT datab (399:399:399) (470:470:470)) + (PORT datac (636:636:636) (731:731:731)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (282:282:282)) + (PORT datab (146:146:146) (201:201:201)) + (PORT datac (124:124:124) (170:170:170)) + (PORT datad (313:313:313) (370:370:370)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (442:442:442) (522:522:522)) + (PORT datab (403:403:403) (487:487:487)) + (PORT datad (208:208:208) (253:253:253)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (293:293:293)) + (PORT datab (205:205:205) (263:263:263)) + (PORT datac (345:345:345) (421:421:421)) + (PORT datad (374:374:374) (448:448:448)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (208:208:208)) + (PORT datab (315:315:315) (383:383:383)) + (PORT datac (134:134:134) (182:182:182)) + (PORT datad (196:196:196) (239:239:239)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (349:349:349)) + (PORT datab (486:486:486) (556:556:556)) + (PORT datac (301:301:301) (340:340:340)) + (PORT datad (158:158:158) (184:184:184)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (908:908:908)) + (PORT datab (874:874:874) (1011:1011:1011)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (919:919:919) (904:904:904)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (713:713:713)) + (PORT datab (358:358:358) (430:430:430)) + (PORT datac (510:510:510) (591:591:591)) + (PORT datad (648:648:648) (740:740:740)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (630:630:630)) + (PORT datab (146:146:146) (195:195:195)) + (PORT datac (633:633:633) (728:728:728)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (399:399:399) (470:470:470)) + (PORT datac (771:771:771) (882:882:882)) + (PORT datad (133:133:133) (172:172:172)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (676:676:676) (740:740:740)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (113:113:113) (145:145:145)) + (PORT datac (94:94:94) (119:119:119)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (284:284:284) (333:333:333)) + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (92:92:92) (116:116:116)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (479:479:479)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out) + (DELAY + (ABSOLUTE + (PORT dataa (179:179:179) (217:217:217)) + (PORT datab (358:358:358) (421:421:421)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (714:714:714)) + (PORT datab (650:650:650) (752:752:752)) + (PORT datac (772:772:772) (883:883:883)) + (PORT datad (649:649:649) (742:742:742)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (616:616:616)) + (PORT datab (401:401:401) (473:473:473)) + (PORT datac (342:342:342) (408:408:408)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) (DELAY (ABSOLUTE (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (864:864:864) (1020:1020:1020)) - (PORT datac (613:613:613) (710:710:710)) - (PORT datad (712:712:712) (816:816:816)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (778:778:778) (888:888:888)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (140:140:140)) + (PORT datab (173:173:173) (208:208:208)) + (PORT datac (680:680:680) (776:776:776)) + (PORT datad (364:364:364) (424:424:424)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (574:574:574)) + (PORT datab (1125:1125:1125) (1288:1288:1288)) + (PORT datac (502:502:502) (612:612:612)) + (PORT datad (466:466:466) (538:538:538)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (257:257:257)) + (PORT datab (642:642:642) (749:749:749)) + (PORT datac (309:309:309) (355:355:355)) + (PORT datad (173:173:173) (203:203:203)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (518:518:518)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (160:160:160)) + (PORT datab (117:117:117) (152:152:152)) + (PORT datac (330:330:330) (391:391:391)) + (PORT datad (116:116:116) (146:146:146)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (370:370:370)) + (PORT datab (358:358:358) (422:422:422)) + (PORT datac (302:302:302) (348:348:348)) + (PORT datad (160:160:160) (183:183:183)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (385:385:385)) + (PORT datab (345:345:345) (395:395:395)) + (PORT datac (131:131:131) (173:173:173)) + (PORT datad (198:198:198) (230:230:230)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (417:417:417)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (334:334:334) (392:392:392)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (661:661:661) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (1048:1048:1048)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (479:479:479) (570:570:570)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (451:451:451)) + (PORT datab (347:347:347) (416:416:416)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1203:1203:1203)) + (PORT datab (1126:1126:1126) (1289:1289:1289)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|flags_cond_true) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (392:392:392)) + (PORT datab (985:985:985) (1144:1144:1144)) + (PORT datac (1024:1024:1024) (1196:1196:1196)) + (PORT datad (302:302:302) (349:349:349)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (121:121:121) (155:155:155)) + (PORT datac (301:301:301) (349:349:349)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (550:550:550)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (337:337:337) (398:398:398)) + (PORT datad (670:670:670) (775:775:775)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (398:398:398)) + (PORT datab (517:517:517) (608:608:608)) + (PORT datad (358:358:358) (423:423:423)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (429:429:429)) + (PORT datab (268:268:268) (309:309:309)) + (PORT datac (384:384:384) (430:430:430)) + (PORT datad (604:604:604) (691:691:691)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (331:331:331)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (316:316:316) (370:370:370)) + (PORT datad (341:341:341) (393:393:393)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (139:139:139) (175:175:175)) + (PORT datac (322:322:322) (372:372:372)) + (PORT datad (128:128:128) (157:157:157)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (918:918:918)) + (PORT asdata (1007:1007:1007) (1124:1124:1124)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (917:917:917)) + (PORT asdata (989:989:989) (1095:1095:1095)) + (PORT ena (649:649:649) (703:703:703)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (265:265:265)) + (PORT datab (198:198:198) (255:255:255)) + (PORT datad (331:331:331) (384:384:384)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (917:917:917)) + (PORT asdata (988:988:988) (1095:1095:1095)) + (PORT ena (812:812:812) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (1163:1163:1163) (1294:1294:1294)) + (PORT ena (631:631:631) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (1168:1168:1168) (1299:1299:1299)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (288:288:288)) + (PORT datab (360:360:360) (427:427:427)) + (PORT datad (338:338:338) (407:407:407)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (768:768:768) (884:884:884)) + (PORT datad (311:311:311) (359:359:359)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (918:918:918)) + (PORT asdata (1006:1006:1006) (1123:1123:1123)) + (PORT ena (644:644:644) (698:698:698)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (403:403:403)) + (PORT datab (525:525:525) (610:610:610)) + (PORT datac (488:488:488) (565:565:565)) + (PORT datad (333:333:333) (386:386:386)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT asdata (875:875:875) (973:973:973)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (450:450:450) (519:519:519)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (669:669:669) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (278:278:278)) + (PORT datab (305:305:305) (362:362:362)) + (PORT datad (300:300:300) (360:360:360)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (137:137:137)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (282:282:282) (322:322:322)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (833:833:833) (949:949:949)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (756:756:756) (816:816:816)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (1002:1002:1002) (1110:1110:1110)) + (PORT ena (915:915:915) (1002:1002:1002)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (536:536:536) (631:631:631)) + (PORT datad (474:474:474) (547:547:547)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (368:368:368) (408:408:408)) + (PORT ena (419:419:419) (435:435:435)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (368:368:368) (408:408:408)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (142:142:142) (180:180:180)) + (PORT datad (127:127:127) (152:152:152)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (434:434:434)) + (PORT datab (346:346:346) (405:405:405)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (727:727:727) (836:836:836)) + (PORT datab (323:323:323) (375:375:375)) + (PORT datac (356:356:356) (416:416:416)) + (PORT datad (158:158:158) (184:184:184)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (961:961:961)) + (PORT datab (928:928:928) (1056:1056:1056)) + (PORT datac (831:831:831) (943:943:943)) + (PORT datad (647:647:647) (747:747:747)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (608:608:608)) + (PORT datab (489:489:489) (559:559:559)) + (PORT datac (506:506:506) (591:591:591)) + (PORT datad (488:488:488) (556:556:556)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (434:434:434)) + (PORT datab (612:612:612) (709:709:709)) + (PORT datac (491:491:491) (582:582:582)) + (PORT datad (652:652:652) (747:747:747)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (498:498:498) (583:583:583)) + (PORT datac (342:342:342) (402:402:402)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (844:844:844)) + (PORT datab (508:508:508) (596:596:596)) + (PORT datac (805:805:805) (914:914:914)) + (PORT datad (517:517:517) (603:603:603)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (545:545:545) (638:638:638)) + (PORT datac (484:484:484) (567:567:567)) + (PORT datad (118:118:118) (149:149:149)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1087:1087:1087)) + (PORT datac (492:492:492) (566:566:566)) + (PORT datad (186:186:186) (217:217:217)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (503:503:503) (580:580:580)) + (PORT datad (122:122:122) (149:149:149)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (754:754:754)) + (PORT datab (152:152:152) (196:196:196)) + (PORT datac (137:137:137) (175:175:175)) + (PORT datad (138:138:138) (168:168:168)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|db_low\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (586:586:586) (675:675:675)) - (PORT datab (491:491:491) (579:579:579)) - (PORT datac (494:494:494) (587:587:587)) - (PORT datad (127:127:127) (169:169:169)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (463:463:463) (547:547:547)) - (PORT datab (320:320:320) (373:373:373)) - (PORT datac (440:440:440) (508:508:508)) - (PORT datad (447:447:447) (515:515:515)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (270:270:270)) - (PORT datab (583:583:583) (668:668:668)) - (PORT datac (410:410:410) (471:471:471)) - (PORT datad (127:127:127) (151:151:151)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (1025:1025:1025)) - (PORT datab (574:574:574) (676:676:676)) - (PORT datac (431:431:431) (506:506:506)) - (PORT datad (993:993:993) (1137:1137:1137)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (439:439:439) (516:516:516)) - (PORT datab (441:441:441) (510:510:510)) - (PORT datac (451:451:451) (523:523:523)) - (PORT datad (304:304:304) (355:355:355)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (230:230:230)) - (PORT datab (338:338:338) (396:396:396)) - (PORT datad (281:281:281) (319:319:319)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (399:399:399)) - (PORT datab (750:750:750) (857:857:857)) - (PORT datac (584:584:584) (680:680:680)) - (PORT datad (584:584:584) (664:664:664)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (140:140:140)) - (PORT datab (124:124:124) (156:156:156)) - (PORT datac (504:504:504) (588:588:588)) - (PORT datad (123:123:123) (148:148:148)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (1057:1057:1057)) - (PORT datab (604:604:604) (699:699:699)) - (PORT datac (631:631:631) (729:729:729)) - (PORT datad (1573:1573:1573) (1798:1798:1798)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (1020:1020:1020)) - (PORT datab (574:574:574) (676:676:676)) - (PORT datac (403:403:403) (465:465:465)) - (PORT datad (978:978:978) (1117:1117:1117)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (1030:1030:1030)) - (PORT datab (327:327:327) (385:385:385)) - (PORT datac (427:427:427) (501:501:501)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (427:427:427)) - (PORT datab (440:440:440) (506:506:506)) - (PORT datac (204:204:204) (246:246:246)) - (PORT datad (457:457:457) (523:523:523)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (521:521:521)) - (PORT datab (479:479:479) (566:566:566)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (124:124:124) (149:149:149)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (705:705:705)) - (PORT datab (662:662:662) (768:768:768)) - (PORT datac (452:452:452) (519:519:519)) - (PORT datad (568:568:568) (667:667:667)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (1057:1057:1057)) - (PORT datab (958:958:958) (1111:1111:1111)) - (PORT datac (426:426:426) (491:491:491)) - (PORT datad (749:749:749) (866:866:866)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (427:427:427)) - (PORT datab (350:350:350) (416:416:416)) - (PORT datac (646:646:646) (720:720:720)) - (PORT datad (479:479:479) (546:546:546)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (116:116:116) (144:144:144)) - (PORT datac (1238:1238:1238) (1424:1424:1424)) - (PORT datad (309:309:309) (365:365:365)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (434:434:434)) - (PORT datab (120:120:120) (150:150:150)) - (PORT datac (454:454:454) (517:517:517)) - (PORT datad (103:103:103) (121:121:121)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (1032:1032:1032)) - (PORT datab (328:328:328) (386:386:386)) - (PORT datac (425:425:425) (499:499:499)) - (PORT datad (990:990:990) (1133:1133:1133)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (354:354:354) (416:416:416)) - (PORT datac (428:428:428) (496:496:496)) - (PORT datad (351:351:351) (408:408:408)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) - (DELAY - (ABSOLUTE - (PORT datac (453:453:453) (517:517:517)) - (PORT datad (107:107:107) (127:127:127)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (571:571:571)) - (PORT datab (475:475:475) (561:561:561)) - (PORT datac (931:931:931) (1073:1073:1073)) - (PORT datad (635:635:635) (729:729:729)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (486:486:486) (566:566:566)) - (PORT datac (101:101:101) (123:123:123)) - (PORT datad (447:447:447) (510:510:510)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (285:285:285) (335:335:335)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (750:750:750)) - (PORT datab (465:465:465) (549:549:549)) - (PORT datad (571:571:571) (647:647:647)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (173:173:173) (210:210:210)) - (PORT datab (468:468:468) (540:540:540)) - (PORT datac (840:840:840) (977:977:977)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (500:500:500) (584:584:584)) - (PORT datab (486:486:486) (580:580:580)) - (PORT datac (542:542:542) (613:613:613)) - (PORT datad (547:547:547) (621:621:621)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (554:554:554)) - (PORT datab (751:751:751) (859:859:859)) - (PORT datac (118:118:118) (158:158:158)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (191:191:191) (188:188:188)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (723:723:723)) - (PORT datab (464:464:464) (540:540:540)) - (PORT datac (536:536:536) (608:608:608)) - (PORT datad (579:579:579) (670:670:670)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (630:630:630)) - (PORT datab (440:440:440) (511:511:511)) - (PORT datac (565:565:565) (665:665:665)) - (PORT datad (555:555:555) (648:648:648)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (570:570:570)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (587:587:587) (671:671:671)) - (PORT datad (810:810:810) (933:933:933)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (420:420:420)) - (PORT datab (368:368:368) (438:438:438)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (88:88:88) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (795:795:795) (922:922:922)) - (PORT datab (915:915:915) (1053:1053:1053)) - (PORT datac (886:886:886) (1029:1029:1029)) - (PORT datad (311:311:311) (375:375:375)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (552:552:552)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (309:309:309) (372:372:372)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (973:973:973)) - (PORT datab (794:794:794) (912:912:912)) - (PORT datac (639:639:639) (729:729:729)) - (PORT datad (178:178:178) (206:206:206)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (815:815:815)) - (PORT datab (414:414:414) (487:487:487)) - (PORT datac (857:857:857) (989:989:989)) - (PORT datad (982:982:982) (1122:1122:1122)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) - (DELAY - (ABSOLUTE - (PORT dataa (118:118:118) (150:150:150)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (274:274:274) (311:311:311)) - (PORT datad (327:327:327) (384:384:384)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (552:552:552)) - (PORT datab (384:384:384) (456:456:456)) - (PORT datac (337:337:337) (396:396:396)) - (PORT datad (101:101:101) (118:118:118)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (725:725:725)) - (PORT datab (812:812:812) (957:957:957)) - (PORT datac (1104:1104:1104) (1285:1285:1285)) - (PORT datad (647:647:647) (768:768:768)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (570:570:570)) - (PORT datab (118:118:118) (149:149:149)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (549:549:549) (635:635:635)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (998:998:998)) - (PORT datab (459:459:459) (547:547:547)) - (PORT datac (767:767:767) (888:888:888)) - (PORT datad (295:295:295) (345:345:345)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (574:574:574)) - (PORT datab (452:452:452) (521:521:521)) - (PORT datac (641:641:641) (736:736:736)) - (PORT datad (645:645:645) (740:740:740)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (574:574:574)) - (PORT datab (618:618:618) (732:732:732)) - (PORT datac (641:641:641) (736:736:736)) - (PORT datad (655:655:655) (783:783:783)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (660:660:660)) - (PORT datab (505:505:505) (583:583:583)) - (PORT datac (470:470:470) (546:546:546)) - (PORT datad (1336:1336:1336) (1524:1524:1524)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (449:449:449) (521:521:521)) - (PORT datac (477:477:477) (549:549:549)) - (PORT datad (907:907:907) (1034:1034:1034)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (406:406:406)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (281:281:281) (324:324:324)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (661:661:661)) - (PORT datab (724:724:724) (835:835:835)) - (PORT datac (642:642:642) (762:762:762)) - (PORT datad (716:716:716) (835:835:835)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (663:663:663)) - (PORT datab (729:729:729) (832:832:832)) - (PORT datac (468:468:468) (551:551:551)) - (PORT datad (1237:1237:1237) (1425:1425:1425)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (305:305:305) (364:364:364)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (523:523:523) (610:610:610)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (333:333:333) (387:387:387)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) - (DELAY - (ABSOLUTE - (PORT datab (606:606:606) (699:699:699)) - (PORT datac (642:642:642) (717:717:717)) - (PORT datad (446:446:446) (508:508:508)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) - (DELAY - (ABSOLUTE - (PORT dataa (579:579:579) (668:668:668)) - (PORT datab (482:482:482) (562:562:562)) - (PORT datac (270:270:270) (310:310:310)) - (PORT datad (582:582:582) (660:660:660)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (369:369:369) (439:439:439)) - (PORT datac (424:424:424) (491:491:491)) - (PORT datad (102:102:102) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (400:400:400)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (1105:1105:1105) (1261:1261:1261)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (556:556:556)) - (PORT datab (111:111:111) (142:142:142)) - (PORT datad (286:286:286) (328:328:328)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (833:833:833) (956:956:956)) - (PORT datab (755:755:755) (891:891:891)) - (PORT datac (327:327:327) (377:377:377)) - (PORT datad (876:876:876) (1016:1016:1016)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (439:439:439)) - (PORT datab (581:581:581) (666:666:666)) - (PORT datac (680:680:680) (779:779:779)) - (PORT datad (703:703:703) (832:832:832)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (727:727:727)) - (PORT datac (364:364:364) (422:422:422)) - (PORT datad (494:494:494) (581:581:581)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (672:672:672)) - (PORT datab (139:139:139) (190:190:190)) - (PORT datac (472:472:472) (556:556:556)) - (PORT datad (385:385:385) (462:462:462)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (804:804:804)) - (PORT datab (382:382:382) (455:455:455)) - (PORT datac (366:366:366) (438:438:438)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (495:495:495) (584:584:584)) - (PORT datac (848:848:848) (1005:1005:1005)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (402:402:402)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (792:792:792) (894:894:894)) - (PORT datad (335:335:335) (393:393:393)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (151:151:151)) - (PORT datab (176:176:176) (211:211:211)) - (PORT datac (441:441:441) (516:516:516)) - (PORT datad (447:447:447) (506:506:506)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (775:775:775) (905:905:905)) - (PORT datab (114:114:114) (141:141:141)) - (PORT datac (342:342:342) (411:411:411)) - (PORT datad (562:562:562) (651:651:651)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (471:471:471) (550:550:550)) - (PORT datac (90:90:90) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (666:666:666) (718:718:718)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (774:774:774) (890:890:890)) - (PORT datab (371:371:371) (448:448:448)) - (PORT datac (558:558:558) (629:629:629)) - (PORT datad (278:278:278) (315:315:315)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (147:147:147)) - (PORT datab (106:106:106) (137:137:137)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (95:95:95) (116:116:116)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (487:487:487)) - (PORT datab (1221:1221:1221) (1401:1401:1401)) - (PORT datac (861:861:861) (993:993:993)) - (PORT datad (979:979:979) (1118:1118:1118)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (1028:1028:1028)) - (PORT datab (177:177:177) (219:219:219)) - (PORT datac (307:307:307) (364:364:364)) - (PORT datad (582:582:582) (665:665:665)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (808:808:808)) - (PORT datab (579:579:579) (671:671:671)) - (PORT datac (431:431:431) (505:505:505)) - (PORT datad (846:846:846) (995:995:995)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (281:281:281) (322:322:322)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) - (DELAY - (ABSOLUTE - (PORT dataa (285:285:285) (335:335:335)) - (PORT datab (488:488:488) (568:568:568)) - (PORT datac (490:490:490) (564:564:564)) - (PORT datad (103:103:103) (121:121:121)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (853:853:853)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (107:107:107) (131:131:131)) - (PORT datad (330:330:330) (379:379:379)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (594:594:594) (688:688:688)) - (PORT datad (102:102:102) (118:118:118)) + (PORT dataa (235:235:235) (302:302:302)) + (PORT datab (650:650:650) (752:752:752)) + (PORT datac (635:635:635) (744:744:744)) + (PORT datad (368:368:368) (436:436:436)) (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (315:315:315) (381:381:381)) - (PORT datab (138:138:138) (190:190:190)) - (PORT datac (124:124:124) (169:169:169)) - (PORT datad (617:617:617) (710:710:710)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (460:460:460) (534:534:534)) - (PORT datab (114:114:114) (147:147:147)) - (PORT datac (178:178:178) (215:215:215)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -23459,9 +27555,9 @@ (INSTANCE z80_\|alu_\|result_lo\[0\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) - (PORT asdata (284:284:284) (305:305:305)) - (PORT ena (910:910:910) (1014:1014:1014)) + (PORT clk (901:901:901) (909:909:909)) + (PORT asdata (348:348:348) (380:380:380)) + (PORT ena (676:676:676) (740:740:740)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -23470,32 +27566,16 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (440:440:440)) - (PORT datab (579:579:579) (665:665:665)) - (PORT datac (682:682:682) (781:781:781)) - (PORT datad (708:708:708) (838:838:838)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|db_low\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (458:458:458) (544:544:544)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datad (451:451:451) (515:515:515)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (334:334:334) (387:387:387)) + (PORT datab (186:186:186) (223:223:223)) + (PORT datad (630:630:630) (723:723:723)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -23503,129 +27583,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) + (INSTANCE z80_\|alu_\|db_low\[0\]\~23) (DELAY (ABSOLUTE - (PORT datab (496:496:496) (576:576:576)) - (PORT datac (308:308:308) (355:355:355)) - (PORT datad (582:582:582) (659:659:659)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (460:460:460) (535:535:535)) - (PORT datab (470:470:470) (546:546:546)) - (PORT datac (367:367:367) (425:425:425)) - (PORT datad (603:603:603) (701:701:701)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (489:489:489) (575:575:575)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (593:593:593) (698:698:698)) - (PORT datac (492:492:492) (584:584:584)) - (PORT datad (386:386:386) (462:462:462)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (771:771:771) (899:899:899)) - (PORT datab (110:110:110) (143:143:143)) - (PORT datac (340:340:340) (409:409:409)) - (PORT datad (566:566:566) (655:655:655)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (454:454:454) (524:524:524)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (307:307:307) (358:358:358)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (610:610:610) (705:705:705)) + (PORT datad (170:170:170) (200:200:200)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (666:666:666) (718:718:718)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) + (INSTANCE z80_\|alu_\|db\[0\]\~18) (DELAY (ABSOLUTE - (PORT datab (140:140:140) (192:192:192)) - (PORT datac (124:124:124) (168:168:168)) - (PORT datad (300:300:300) (353:353:353)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (707:707:707) (834:834:834)) + (PORT datab (489:489:489) (568:568:568)) + (PORT datac (627:627:627) (702:702:702)) + (PORT datad (525:525:525) (611:611:611)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -23633,71 +27615,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (INSTANCE z80_\|alu_\|db\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (537:537:537) (630:630:630)) + (PORT datac (430:430:430) (491:491:491)) + (PORT datad (122:122:122) (153:153:153)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (611:611:611)) + (PORT datac (914:914:914) (1063:1063:1063)) + (PORT datad (777:777:777) (876:876:876)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~16) (DELAY (ABSOLUTE (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (634:634:634) (733:733:733)) - (PORT datac (178:178:178) (214:214:214)) - (PORT datad (102:102:102) (125:125:125)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (119:119:119) (153:153:153)) - (PORT datac (440:440:440) (509:509:509)) - (PORT datad (299:299:299) (348:348:348)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (116:116:116) (150:150:150)) - (PORT datac (159:159:159) (190:190:190)) - (PORT datad (99:99:99) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (549:549:549)) - (PORT datad (447:447:447) (514:514:514)) + (PORT datac (494:494:494) (569:569:569)) + (PORT datad (129:129:129) (157:157:157)) (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (290:290:290) (338:338:338)) - (PORT datac (178:178:178) (206:206:206)) - (PORT datad (302:302:302) (351:351:351)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -23705,518 +27659,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) + (INSTANCE z80_\|alu_\|db_low\[1\]\~12) (DELAY (ABSOLUTE - (PORT dataa (193:193:193) (232:232:232)) - (PORT datab (120:120:120) (148:148:148)) - (PORT datac (100:100:100) (126:126:126)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (289:289:289) (337:337:337)) - (PORT datab (192:192:192) (228:228:228)) - (PORT datac (98:98:98) (123:123:123)) - (PORT datad (160:160:160) (186:186:186)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (1081:1081:1081) (1215:1215:1215)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT datab (699:699:699) (799:799:799)) - (PORT datac (352:352:352) (416:416:416)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (597:597:597)) - (PORT datab (389:389:389) (470:470:470)) - (PORT datac (363:363:363) (437:437:437)) - (PORT datad (573:573:573) (662:662:662)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (753:753:753)) - (PORT datab (588:588:588) (678:678:678)) - (PORT datac (710:710:710) (808:808:808)) - (PORT datad (177:177:177) (209:209:209)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (634:634:634) (703:703:703)) - (PORT ena (422:422:422) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (635:635:635) (704:704:704)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (273:273:273)) - (PORT datab (230:230:230) (273:273:273)) - (PORT datad (117:117:117) (153:153:153)) + (PORT dataa (651:651:651) (756:756:756)) + (PORT datab (155:155:155) (200:200:200)) + (PORT datac (141:141:141) (181:181:181)) + (PORT datad (132:132:132) (163:163:163)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (489:489:489) (540:540:540)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (808:808:808)) - (PORT datab (467:467:467) (542:542:542)) - (PORT datad (202:202:202) (234:234:234)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (774:774:774) (865:865:865)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (474:474:474) (519:519:519)) - (PORT ena (767:767:767) (833:833:833)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (305:305:305)) - (PORT datab (129:129:129) (176:176:176)) - (PORT datad (351:351:351) (412:412:412)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (486:486:486) (562:562:562)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (631:631:631) (678:678:678)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (665:665:665) (743:743:743)) - (PORT ena (649:649:649) (709:709:709)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (260:260:260)) - (PORT datab (338:338:338) (391:391:391)) - (PORT datad (331:331:331) (377:377:377)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (772:772:772) (854:854:854)) - (PORT ena (494:494:494) (536:536:536)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (768:768:768) (850:850:850)) - (PORT ena (504:504:504) (535:535:535)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (274:274:274)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (193:193:193) (232:232:232)) - (PORT datac (305:305:305) (350:350:350)) - (PORT datad (321:321:321) (375:375:375)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT asdata (923:923:923) (1026:1026:1026)) - (PORT ena (433:433:433) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (791:791:791)) - (PORT datab (770:770:770) (890:890:890)) - (PORT datad (1020:1020:1020) (1173:1173:1173)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (508:508:508) (594:594:594)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT asdata (680:680:680) (758:758:758)) - (PORT ena (518:518:518) (563:563:563)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (260:260:260)) - (PORT datab (386:386:386) (462:462:462)) - (PORT datad (124:124:124) (148:148:148)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (429:429:429)) - (PORT datab (342:342:342) (401:401:401)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (168:168:168) (197:197:197)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (310:310:310) (370:370:370)) - (PORT datab (333:333:333) (395:395:395)) - (PORT datac (1117:1117:1117) (1310:1310:1310)) - (PORT datad (301:301:301) (348:348:348)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (630:630:630)) - (PORT datab (718:718:718) (816:816:816)) - (PORT datac (572:572:572) (664:664:664)) - (PORT datad (547:547:547) (615:615:615)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (217:217:217)) - (PORT datab (135:135:135) (176:176:176)) - (PORT datac (584:584:584) (670:670:670)) - (PORT datad (458:458:458) (527:527:527)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (807:807:807)) - (PORT datab (479:479:479) (554:554:554)) - (PORT datac (364:364:364) (436:436:436)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (571:571:571)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (841:841:841) (997:997:997)) - (PORT datad (712:712:712) (816:816:816)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -24224,13 +27675,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~9) + (INSTANCE z80_\|alu_\|db_low\[1\]\~13) (DELAY (ABSOLUTE - (PORT dataa (328:328:328) (396:396:396)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (272:272:272) (313:313:313)) - (PORT datad (445:445:445) (515:515:515)) + (PORT dataa (357:357:357) (433:433:433)) + (PORT datab (651:651:651) (752:752:752)) + (PORT datac (328:328:328) (390:390:390)) + (PORT datad (368:368:368) (436:436:436)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (909:909:909)) + (PORT asdata (579:579:579) (631:631:631)) + (PORT ena (676:676:676) (740:740:740)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (294:294:294) (344:344:344)) + (PORT datab (170:170:170) (207:207:207)) + (PORT datad (629:629:629) (722:722:722)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (430:430:430)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datac (433:433:433) (492:492:492)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (367:367:367)) + (PORT datab (534:534:534) (632:632:632)) + (PORT datac (190:190:190) (233:233:233)) + (PORT datad (481:481:481) (558:558:558)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -24240,39 +27754,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~22) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) (DELAY (ABSOLUTE - (PORT datab (490:490:490) (569:569:569)) - (PORT datac (326:326:326) (380:380:380)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (727:727:727)) - (PORT datab (347:347:347) (414:414:414)) - (PORT datac (409:409:409) (470:470:470)) - (PORT datad (447:447:447) (509:509:509)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (492:492:492) (578:578:578)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (376:376:376) (447:447:447)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -24280,10 +27766,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) + (INSTANCE z80_\|alu_\|op1_low\[1\]) (DELAY (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) + (PORT clk (916:916:916) (901:901:901)) (PORT d (37:37:37) (50:50:50)) (PORT ena (405:405:405) (422:422:422)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) @@ -24299,58 +27785,10 @@ (INSTANCE z80_\|alu_control_\|out\[6\]\~0) (DELAY (ABSOLUTE - (PORT datab (140:140:140) (187:187:187)) - (PORT datac (133:133:133) (177:177:177)) + (PORT datab (144:144:144) (192:192:192)) + (PORT datac (128:128:128) (169:169:169)) (PORT datad (128:128:128) (164:164:164)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (786:786:786)) - (PORT datab (612:612:612) (710:710:710)) - (PORT datac (566:566:566) (648:648:648)) - (PORT datad (585:585:585) (697:697:697)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (129:129:129) (179:179:179)) - (PORT datab (365:365:365) (428:428:428)) - (PORT datac (724:724:724) (829:829:829)) - (PORT datad (296:296:296) (347:347:347)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (1052:1052:1052)) - (PORT datab (476:476:476) (553:553:553)) - (PORT datac (582:582:582) (678:678:678)) - (PORT datad (556:556:556) (634:634:634)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -24358,47 +27796,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~23) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) (DELAY (ABSOLUTE - (PORT dataa (503:503:503) (593:593:593)) - (PORT datab (437:437:437) (500:500:500)) - (PORT datac (899:899:899) (1032:1032:1032)) - (PORT datad (348:348:348) (410:410:410)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (518:518:518)) - (PORT datab (110:110:110) (141:141:141)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (625:625:625) (710:710:710)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (284:284:284) (327:327:327)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (683:683:683) (781:781:781)) - (PORT datad (351:351:351) (420:420:420)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (464:464:464) (542:542:542)) + (PORT datad (365:365:365) (428:428:428)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -24406,1615 +27808,213 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) (DELAY (ABSOLUTE - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (111:111:111) (131:131:131)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (371:371:371)) - (PORT datab (139:139:139) (176:176:176)) - (PORT datad (615:615:615) (715:715:715)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (336:336:336) (386:386:386)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (804:804:804) (906:906:906)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (498:498:498) (539:539:539)) - (PORT ena (641:641:641) (691:691:691)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (151:151:151) (195:195:195)) - (PORT datab (131:131:131) (180:180:180)) - (PORT datad (309:309:309) (361:361:361)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (518:518:518) (573:573:573)) - (PORT ena (771:771:771) (831:831:831)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (176:176:176) (218:218:218)) - (PORT datad (331:331:331) (389:389:389)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (756:756:756) (855:855:855)) - (PORT ena (759:759:759) (815:815:815)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (755:755:755) (853:853:853)) - (PORT ena (659:659:659) (712:712:712)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (404:404:404)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (475:475:475) (543:543:543)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (525:525:525) (582:582:582)) - (PORT ena (417:417:417) (434:434:434)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (525:525:525) (582:582:582)) - (PORT ena (772:772:772) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (155:155:155) (195:195:195)) - (PORT datab (379:379:379) (457:457:457)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (375:375:375)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (327:327:327) (388:388:388)) - (PORT datad (157:157:157) (182:182:182)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (789:789:789) (876:876:876)) - (PORT ena (630:630:630) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (784:784:784) (870:870:870)) - (PORT ena (617:617:617) (660:660:660)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (278:278:278)) - (PORT datab (372:372:372) (444:444:444)) - (PORT datad (345:345:345) (408:408:408)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (664:664:664) (737:737:737)) - (PORT ena (688:688:688) (756:756:756)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (669:669:669) (743:743:743)) - (PORT ena (641:641:641) (690:690:690)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (398:398:398) (471:471:471)) - (PORT datab (387:387:387) (458:458:458)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (520:520:520)) - (PORT datab (340:340:340) (406:406:406)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (520:520:520)) - (PORT datab (473:473:473) (552:552:552)) - (PORT datac (862:862:862) (1004:1004:1004)) - (PORT datad (451:451:451) (517:517:517)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT asdata (372:372:372) (408:408:408)) - (PORT ena (514:514:514) (543:543:543)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (783:783:783)) - (PORT datab (657:657:657) (759:759:759)) - (PORT datad (216:216:216) (249:249:249)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datac (245:245:245) (288:288:288)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (469:469:469) (548:548:548)) - (PORT datab (823:823:823) (988:988:988)) - (PORT datac (298:298:298) (350:350:350)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (558:558:558)) - (PORT datad (685:685:685) (810:810:810)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (96:96:96) (115:115:115)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (923:923:923) (905:905:905)) - (PORT ena (1450:1450:1450) (1621:1621:1621)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datac (555:555:555) (640:640:640)) - (PORT datad (444:444:444) (512:512:512)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (800:800:800)) - (PORT datab (685:685:685) (781:781:781)) - (PORT datac (756:756:756) (871:871:871)) - (PORT datad (715:715:715) (813:813:813)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (182:182:182) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (530:530:530) (580:580:580)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (831:831:831) (932:932:932)) - (PORT ena (630:630:630) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (830:830:830) (931:931:931)) - (PORT ena (617:617:617) (660:660:660)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (259:259:259)) - (PORT datab (378:378:378) (451:451:451)) - (PORT datad (352:352:352) (415:415:415)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (654:654:654) (723:723:723)) - (PORT ena (641:641:641) (690:690:690)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (658:658:658) (728:728:728)) - (PORT ena (688:688:688) (756:756:756)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (133:133:133) (185:185:185)) - (PORT datab (379:379:379) (450:450:450)) - (PORT datad (372:372:372) (438:438:438)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (900:900:900) (1020:1020:1020)) - (PORT ena (659:659:659) (712:712:712)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (898:898:898) (1017:1017:1017)) - (PORT ena (759:759:759) (815:815:815)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (410:410:410)) - (PORT datab (483:483:483) (559:559:559)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT asdata (279:279:279) (298:298:298)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (312:312:312) (370:370:370)) - (PORT datab (340:340:340) (399:399:399)) - (PORT datad (124:124:124) (149:149:149)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (489:489:489) (534:534:534)) - (PORT ena (417:417:417) (434:434:434)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (488:488:488) (533:533:533)) - (PORT ena (772:772:772) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (158:158:158) (200:200:200)) - (PORT datab (378:378:378) (456:456:456)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (492:492:492) (540:540:540)) - (PORT ena (804:804:804) (906:906:906)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (495:495:495) (542:542:542)) - (PORT ena (641:641:641) (691:691:691)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (155:155:155) (202:202:202)) - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (307:307:307) (358:358:358)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (913:913:913)) - (PORT asdata (896:896:896) (999:999:999)) - (PORT ena (421:421:421) (441:441:441)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT datab (196:196:196) (237:237:237)) - (PORT datad (114:114:114) (135:135:135)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (533:533:533)) - (PORT datab (189:189:189) (228:228:228)) - (PORT datac (286:286:286) (322:322:322)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (463:463:463) (536:536:536)) - (PORT datac (440:440:440) (507:507:507)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (1027:1027:1027)) - (PORT datab (433:433:433) (498:498:498)) - (PORT datac (433:433:433) (496:496:496)) - (PORT datad (161:161:161) (185:185:185)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT asdata (280:280:280) (299:299:299)) - (PORT ena (514:514:514) (543:543:543)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (782:782:782)) - (PORT datab (783:783:783) (893:893:893)) - (PORT datad (215:215:215) (248:248:248)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (226:226:226) (287:287:287)) - (PORT datac (243:243:243) (287:287:287)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (151:151:151)) - (PORT datab (112:112:112) (145:145:145)) - (PORT datac (342:342:342) (414:414:414)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (346:346:346) (407:407:407)) - (PORT datac (298:298:298) (350:350:350)) - (PORT datad (809:809:809) (965:965:965)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT datac (854:854:854) (990:990:990)) - (PORT datad (340:340:340) (395:395:395)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (893:893:893)) - (PORT ena (1338:1338:1338) (1484:1484:1484)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (800:800:800)) - (PORT datab (686:686:686) (782:782:782)) - (PORT datac (343:343:343) (415:415:415)) - (PORT datad (715:715:715) (814:814:814)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (182:182:182) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT datac (856:856:856) (991:991:991)) - (PORT datad (327:327:327) (374:374:374)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (893:893:893)) - (PORT ena (1338:1338:1338) (1484:1484:1484)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~0) - (DELAY - (ABSOLUTE - (PORT dataa (735:735:735) (839:839:839)) - (PORT datab (683:683:683) (779:779:779)) - (PORT datac (673:673:673) (779:779:779)) - (PORT datad (367:367:367) (448:448:448)) - (IOPATH dataa combout (181:181:181) (180:180:180)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (152:152:152)) - (PORT datab (109:109:109) (140:140:140)) - (PORT datac (94:94:94) (119:119:119)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (494:494:494) (577:577:577)) - (PORT datac (502:502:502) (620:620:620)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (530:530:530) (580:580:580)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT asdata (278:278:278) (298:298:298)) - (PORT ena (514:514:514) (543:543:543)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (782:782:782)) - (PORT datab (596:596:596) (687:687:687)) - (PORT datad (215:215:215) (248:248:248)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (287:287:287)) - (PORT datac (244:244:244) (287:287:287)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (527:527:527)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (298:298:298) (349:349:349)) - (PORT datad (808:808:808) (965:965:965)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (359:359:359) (391:391:391)) - (PORT ena (641:641:641) (690:690:690)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (358:358:358) (390:390:390)) - (PORT ena (688:688:688) (756:756:756)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (258:258:258)) - (PORT datab (388:388:388) (460:460:460)) - (PORT datad (374:374:374) (441:441:441)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (862:862:862)) - (PORT datab (499:499:499) (582:582:582)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (637:637:637) (700:700:700)) - (PORT ena (630:630:630) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (637:637:637) (700:700:700)) - (PORT ena (617:617:617) (660:660:660)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (262:262:262)) - (PORT datab (377:377:377) (450:450:450)) - (PORT datad (351:351:351) (414:414:414)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (1048:1048:1048) (1188:1188:1188)) - (PORT ena (417:417:417) (434:434:434)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT asdata (642:642:642) (708:708:708)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (1051:1051:1051) (1192:1192:1192)) - (PORT ena (772:772:772) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (402:402:402)) - (PORT datab (379:379:379) (457:457:457)) - (PORT datad (331:331:331) (384:384:384)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (159:159:159) (200:200:200)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (762:762:762) (836:836:836)) - (PORT ena (804:804:804) (906:906:906)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (763:763:763) (837:837:837)) - (PORT ena (641:641:641) (691:691:691)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (155:155:155) (202:202:202)) - (PORT datab (130:130:130) (178:178:178)) - (PORT datad (306:306:306) (358:358:358)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (628:628:628) (672:672:672)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (496:496:496) (541:541:541)) - (PORT ena (659:659:659) (712:712:712)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (497:497:497) (542:542:542)) - (PORT ena (759:759:759) (815:815:815)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (411:411:411)) - (PORT datab (481:481:481) (558:558:558)) - (PORT datad (120:120:120) (158:158:158)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (381:381:381)) - (PORT datab (131:131:131) (179:179:179)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (448:448:448) (508:508:508)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (173:173:173) (210:210:210)) - (PORT datab (345:345:345) (407:407:407)) - (PORT datac (316:316:316) (364:364:364)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (234:234:234)) - (PORT datab (498:498:498) (581:581:581)) - (PORT datac (692:692:692) (820:820:820)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (300:300:300) (348:348:348)) - (PORT datab (489:489:489) (567:567:567)) - (PORT datac (485:485:485) (549:549:549)) - (PORT datad (332:332:332) (391:391:391)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (106:106:106) (137:137:137)) - (PORT datac (909:909:909) (1046:1046:1046)) - (PORT datad (174:174:174) (207:207:207)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (448:448:448)) - (PORT datab (333:333:333) (390:390:390)) - (PORT datac (165:165:165) (198:198:198)) - (PORT datad (112:112:112) (133:133:133)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (702:702:702)) - (PORT datab (362:362:362) (423:423:423)) - (PORT datac (469:469:469) (544:544:544)) - (PORT datad (613:613:613) (719:719:719)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (137:137:137) (178:178:178)) - (PORT datac (738:738:738) (865:865:865)) - (PORT datad (458:458:458) (527:527:527)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (581:581:581)) - (PORT datab (380:380:380) (455:455:455)) - (PORT datac (644:644:644) (773:773:773)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (181:181:181) (219:219:219)) - (PORT datac (761:761:761) (893:893:893)) - (PORT datad (311:311:311) (359:359:359)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (337:337:337) (399:399:399)) - (PORT datac (707:707:707) (813:813:813)) - (PORT datad (324:324:324) (376:376:376)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (288:288:288) (336:336:336)) - (PORT datad (447:447:447) (517:517:517)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (536:536:536)) + (PORT dataa (368:368:368) (429:429:429)) (PORT datab (103:103:103) (132:132:132)) - (PORT datac (347:347:347) (396:396:396)) - (PORT datad (488:488:488) (574:574:574)) + (PORT datad (330:330:330) (381:381:381)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (755:755:755)) + (PORT datab (357:357:357) (420:420:420)) + (PORT datac (641:641:641) (735:735:735)) + (PORT datad (358:358:358) (432:432:432)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (777:777:777)) + (PORT datab (925:925:925) (1052:1052:1052)) + (PORT datac (801:801:801) (932:932:932)) + (PORT datad (471:471:471) (543:543:543)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) (DELAY (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) + (PORT dataa (352:352:352) (410:410:410)) + (PORT datab (492:492:492) (569:569:569)) + (PORT datac (349:349:349) (411:411:411)) + (PORT datad (457:457:457) (516:516:516)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (515:515:515)) + (PORT datab (500:500:500) (573:573:573)) + (PORT datac (215:215:215) (270:270:270)) + (PORT datad (452:452:452) (516:516:516)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (425:425:425)) + (PORT datab (498:498:498) (583:583:583)) + (PORT datac (310:310:310) (358:358:358)) + (PORT datad (163:163:163) (191:191:191)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (847:847:847)) + (PORT datab (535:535:535) (629:629:629)) + (PORT datac (498:498:498) (575:575:575)) + (PORT datad (889:889:889) (1031:1031:1031)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (389:389:389)) + (PORT datab (546:546:546) (639:639:639)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (117:117:117) (147:147:147)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1087:1087:1087)) + (PORT datab (497:497:497) (571:571:571)) + (PORT datac (496:496:496) (571:571:571)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (903:903:903)) + (PORT datab (617:617:617) (717:717:717)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (125:125:125) (153:153:153)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (158:158:158)) + (PORT datab (133:133:133) (171:171:171)) + (PORT datac (331:331:331) (392:392:392)) + (PORT datad (471:471:471) (545:545:545)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (330:330:330)) + (PORT datab (390:390:390) (468:468:468)) + (PORT datac (310:310:310) (356:356:356)) + (PORT datad (481:481:481) (558:558:558)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (901:901:901)) (PORT d (37:37:37) (50:50:50)) (PORT ena (405:405:405) (422:422:422)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) @@ -26027,245 +28027,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (708:708:708) (815:815:815)) - (PORT datab (694:694:694) (799:799:799)) - (PORT datac (136:136:136) (180:180:180)) - (PORT datad (137:137:137) (176:176:176)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (232:232:232)) - (PORT datab (491:491:491) (585:585:585)) - (PORT datac (604:604:604) (708:708:708)) - (PORT datad (648:648:648) (743:743:743)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (926:926:926) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (435:435:435) (467:467:467)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (479:479:479)) - (PORT datab (379:379:379) (463:463:463)) - (PORT datac (450:450:450) (526:526:526)) - (PORT datad (468:468:468) (543:543:543)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (140:140:140)) - (PORT datab (120:120:120) (149:149:149)) - (PORT datac (164:164:164) (195:195:195)) - (PORT datad (99:99:99) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (308:308:308) (355:355:355)) - (PORT datab (111:111:111) (142:142:142)) - (PORT datac (87:87:87) (109:109:109)) - (PORT datad (295:295:295) (338:338:338)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (1081:1081:1081) (1215:1215:1215)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (597:597:597)) - (PORT datab (398:398:398) (482:482:482)) - (PORT datac (373:373:373) (462:462:462)) - (PORT datad (573:573:573) (662:662:662)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (414:414:414)) - (PORT datab (354:354:354) (438:438:438)) - (PORT datac (285:285:285) (331:331:331)) - (PORT datad (318:318:318) (368:368:368)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (386:386:386)) - (PORT datab (294:294:294) (343:343:343)) - (PORT datad (1167:1167:1167) (1348:1348:1348)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (307:307:307) (361:361:361)) - (PORT datac (752:752:752) (880:880:880)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (305:305:305) (352:352:352)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (543:543:543) (615:615:615)) - (PORT datad (466:466:466) (530:530:530)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (428:428:428)) - (PORT datab (489:489:489) (568:568:568)) - (PORT datac (325:325:325) (379:379:379)) - (PORT datad (506:506:506) (585:585:585)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (551:551:551)) - (PORT datab (354:354:354) (422:422:422)) - (PORT datac (364:364:364) (440:440:440)) - (PORT datad (328:328:328) (383:383:383)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) - (DELAY - (ABSOLUTE - (PORT datac (363:363:363) (429:429:429)) - (PORT datad (116:116:116) (132:132:132)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (276:276:276) (318:318:318)) - (PORT datad (170:170:170) (200:200:200)) + (PORT dataa (345:345:345) (415:415:415)) + (PORT datab (626:626:626) (748:748:748)) + (PORT datac (314:314:314) (362:362:362)) + (PORT datad (210:210:210) (258:258:258)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -26275,311 +28043,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~1) (DELAY (ABSOLUTE - (PORT dataa (880:880:880) (1013:1013:1013)) - (PORT datab (504:504:504) (602:602:602)) - (PORT datac (679:679:679) (794:794:794)) - (PORT datad (402:402:402) (466:466:466)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (273:273:273)) - (PORT datab (364:364:364) (431:431:431)) - (PORT datac (321:321:321) (377:377:377)) - (PORT datad (452:452:452) (519:519:519)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (354:354:354)) - (PORT datab (572:572:572) (660:660:660)) - (PORT datac (557:557:557) (632:632:632)) - (PORT datad (287:287:287) (333:333:333)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (408:408:408) (428:428:428)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (141:141:141) (191:191:191)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (130:130:130) (171:171:171)) - (PORT datad (130:130:130) (169:169:169)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (431:431:431)) - (PORT datab (464:464:464) (542:542:542)) - (PORT datac (133:133:133) (176:176:176)) - (PORT datad (385:385:385) (462:462:462)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (750:750:750) (860:860:860)) - (PORT datab (386:386:386) (470:470:470)) - (PORT datac (345:345:345) (403:403:403)) - (PORT datad (334:334:334) (390:390:390)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (463:463:463) (538:538:538)) - (PORT datad (344:344:344) (403:403:403)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (824:824:824)) - (PORT datab (449:449:449) (527:527:527)) - (PORT datac (161:161:161) (190:190:190)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (628:628:628)) - (PORT datab (472:472:472) (552:552:552)) - (PORT datac (852:852:852) (989:989:989)) - (PORT datad (1154:1154:1154) (1327:1327:1327)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (236:236:236)) - (PORT datab (377:377:377) (442:442:442)) - (PORT datac (100:100:100) (121:121:121)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (173:173:173) (213:213:213)) - (PORT datab (116:116:116) (144:144:144)) - (PORT datac (538:538:538) (612:612:612)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (655:655:655)) - (PORT datab (580:580:580) (674:674:674)) - (PORT datac (331:331:331) (380:380:380)) - (PORT datad (116:116:116) (139:139:139)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (389:389:389)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (348:348:348) (405:405:405)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (702:702:702)) - (PORT datab (630:630:630) (743:743:743)) - (PORT datac (459:459:459) (541:541:541)) - (PORT datad (458:458:458) (528:528:528)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (479:479:479) (563:563:563)) - (PORT datab (473:473:473) (551:551:551)) - (PORT datac (189:189:189) (221:221:221)) - (PORT datad (125:125:125) (157:157:157)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (799:799:799)) - (PORT datab (381:381:381) (454:454:454)) - (PORT datac (486:486:486) (579:579:579)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (838:838:838)) - (PORT datab (510:510:510) (595:595:595)) - (PORT datac (803:803:803) (936:936:936)) - (PORT datad (170:170:170) (200:200:200)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (724:724:724)) - (PORT datac (326:326:326) (379:379:379)) - (PORT datad (475:475:475) (546:546:546)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (664:664:664) (768:768:768)) - (PORT datab (365:365:365) (434:434:434)) - (PORT datac (609:609:609) (713:713:713)) - (PORT datad (90:90:90) (107:107:107)) + (PORT dataa (144:144:144) (189:189:189)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (288:288:288) (335:335:335)) + (PORT datad (502:502:502) (587:587:587)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -26589,90 +28059,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) + (INSTANCE z80_\|alu_\|op2_low\[2\]) (DELAY (ABSOLUTE - (PORT clk (926:926:926) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (435:435:435) (467:467:467)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (686:686:686)) - (PORT datab (397:397:397) (487:487:487)) - (PORT datac (352:352:352) (423:423:423)) - (PORT datad (477:477:477) (564:564:564)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (756:756:756)) - (PORT datab (584:584:584) (672:672:672)) - (PORT datac (711:711:711) (809:809:809)) - (PORT datad (171:171:171) (201:201:201)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (263:263:263) (301:301:301)) - (PORT datad (452:452:452) (523:523:523)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (726:726:726)) - (PORT datab (358:358:358) (426:426:426)) - (PORT datac (352:352:352) (411:411:411)) - (PORT datad (488:488:488) (574:574:574)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) + (PORT clk (915:915:915) (900:900:900)) (PORT d (37:37:37) (50:50:50)) (PORT ena (420:420:420) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) @@ -26685,44 +28075,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) + (INSTANCE z80_\|alu_\|db_low\[2\]\~5) (DELAY (ABSOLUTE - (PORT dataa (766:766:766) (891:891:891)) - (PORT datab (400:400:400) (491:491:491)) - (PORT datac (369:369:369) (443:443:443)) - (PORT datad (566:566:566) (648:648:648)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (393:393:393)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (603:603:603) (707:707:707)) - (PORT datad (648:648:648) (742:742:742)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (247:247:247) (310:310:310)) + (PORT datab (342:342:342) (414:414:414)) + (PORT datac (609:609:609) (701:701:701)) + (PORT datad (367:367:367) (435:435:435)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) + (INSTANCE z80_\|alu_\|result_lo\[2\]) (DELAY (ABSOLUTE - (PORT clk (926:926:926) (911:911:911)) + (PORT clk (901:901:901) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (435:435:435) (467:467:467)) + (PORT ena (676:676:676) (740:740:740)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -26733,79 +28107,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~2) + (INSTANCE z80_\|alu_\|db_low\[2\]\~6) (DELAY (ABSOLUTE - (PORT dataa (377:377:377) (460:460:460)) - (PORT datab (463:463:463) (545:545:545)) - (PORT datac (349:349:349) (419:419:419)) - (PORT datad (466:466:466) (541:541:541)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (383:383:383) (462:462:462)) - (PORT datac (749:749:749) (868:868:868)) - (PORT datad (385:385:385) (466:466:466)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (115:115:115) (149:149:149)) - (PORT datac (96:96:96) (122:122:122)) - (PORT datad (93:93:93) (112:112:112)) + (PORT dataa (174:174:174) (211:211:211)) + (PORT datab (324:324:324) (381:381:381)) + (PORT datac (530:530:530) (629:629:629)) + (PORT datad (317:317:317) (378:378:378)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (231:231:231)) - (PORT datab (117:117:117) (151:151:151)) - (PORT datac (169:169:169) (200:200:200)) - (PORT datad (109:109:109) (131:131:131)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (427:427:427) (497:497:497)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (204:204:204) (247:247:247)) - (PORT datad (441:441:441) (499:499:499)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26813,225 +28123,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~0) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) (DELAY (ABSOLUTE - (PORT dataa (550:550:550) (638:638:638)) - (PORT datab (516:516:516) (614:614:614)) - (PORT datac (602:602:602) (694:694:694)) - (PORT datad (724:724:724) (827:827:827)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (672:672:672)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (717:717:717) (835:835:835)) - (PORT datad (577:577:577) (667:667:667)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (330:330:330) (393:393:393)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (664:664:664) (796:796:796)) - (PORT datab (500:500:500) (597:597:597)) - (PORT datac (610:610:610) (707:707:707)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (771:771:771) (911:911:911)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (430:430:430) (487:487:487)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (771:771:771) (911:911:911)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (330:330:330) (387:387:387)) - (PORT datad (501:501:501) (589:589:589)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (518:518:518) (617:617:617)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (549:549:549)) - (PORT datab (616:616:616) (721:721:721)) - (PORT datac (132:132:132) (174:174:174)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (651:651:651)) - (PORT datab (544:544:544) (651:651:651)) - (PORT datac (1236:1236:1236) (1421:1421:1421)) - (PORT datad (308:308:308) (364:364:364)) - (IOPATH dataa combout (159:159:159) (173:173:173)) + (PORT dataa (118:118:118) (156:156:156)) + (PORT datab (350:350:350) (411:411:411)) + (PORT datac (497:497:497) (583:583:583)) + (PORT datad (120:120:120) (150:150:150)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (767:767:767)) - (PORT datab (682:682:682) (818:818:818)) - (PORT datac (839:839:839) (968:968:968)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (974:974:974)) - (PORT datab (302:302:302) (352:352:352)) - (PORT datac (785:785:785) (889:889:889)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~4) (DELAY (ABSOLUTE - (PORT dataa (179:179:179) (218:218:218)) - (PORT datab (126:126:126) (159:159:159)) - (PORT datac (187:187:187) (221:221:221)) - (PORT datad (159:159:159) (186:186:186)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (414:414:414)) - (PORT datab (138:138:138) (174:174:174)) - (PORT datac (417:417:417) (476:476:476)) - (PORT datad (93:93:93) (111:111:111)) + (PORT dataa (147:147:147) (195:195:195)) + (PORT datab (306:306:306) (357:357:357)) + (PORT datac (305:305:305) (346:346:346)) + (PORT datad (496:496:496) (581:581:581)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -27040,159 +28154,31 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) (DELAY (ABSOLUTE - (PORT dataa (338:338:338) (406:406:406)) - (PORT datab (460:460:460) (532:532:532)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (584:584:584) (678:678:678)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (915:915:915) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (372:372:372) (441:441:441)) - (PORT datab (654:654:654) (754:754:754)) - (PORT datac (742:742:742) (851:851:851)) - (PORT datad (938:938:938) (1089:1089:1089)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (961:961:961)) - (PORT datab (796:796:796) (913:913:913)) - (PORT datac (650:650:650) (743:743:743)) - (PORT datad (837:837:837) (970:970:970)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (753:753:753) (869:869:869)) - (PORT datab (1208:1208:1208) (1388:1388:1388)) - (PORT datac (703:703:703) (811:811:811)) - (PORT datad (781:781:781) (883:883:883)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (143:143:143) (191:191:191)) - (PORT datac (528:528:528) (594:594:594)) - (PORT datad (325:325:325) (376:376:376)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (491:491:491) (570:570:570)) - (PORT datab (655:655:655) (754:754:754)) - (PORT datac (342:342:342) (406:406:406)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (725:725:725)) - (PORT datab (811:811:811) (957:957:957)) - (PORT datac (424:424:424) (477:477:477)) - (PORT datad (646:646:646) (768:768:768)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1360:1360:1360) (1554:1554:1554)) - (PORT datab (121:121:121) (151:151:151)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (598:598:598) (703:703:703)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (562:562:562)) - (PORT datab (363:363:363) (428:428:428)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (443:443:443) (502:502:502)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (284:284:284) (333:333:333)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (435:435:435) (495:495:495)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (245:245:245) (307:307:307)) + (PORT datab (373:373:373) (444:444:444)) + (PORT datac (470:470:470) (548:548:548)) + (PORT datad (223:223:223) (280:280:280)) + (IOPATH dataa combout (188:188:188) (203:203:203)) (IOPATH datab combout (190:190:190) (205:205:205)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -27201,874 +28187,74 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~8) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (374:374:374) (450:450:450)) - (PORT datab (733:733:733) (846:846:846)) - (PORT datac (685:685:685) (785:785:785)) - (PORT datad (314:314:314) (365:365:365)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (284:284:284) (324:324:324)) - (PORT datad (336:336:336) (395:395:395)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (395:395:395)) - (PORT datab (490:490:490) (568:568:568)) - (PORT datac (480:480:480) (545:545:545)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (555:555:555)) - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (910:910:910) (1046:1046:1046)) - (PORT datad (332:332:332) (384:384:384)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (481:481:481) (527:527:527)) - (PORT ena (641:641:641) (691:691:691)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (153:153:153) (201:201:201)) - (PORT datab (576:576:576) (674:674:674)) - (PORT datad (435:435:435) (497:497:497)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (526:526:526) (584:584:584)) - (PORT ena (759:759:759) (815:815:815)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (527:527:527) (585:585:585)) - (PORT ena (659:659:659) (712:712:712)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (403:403:403)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (476:476:476) (545:545:545)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT asdata (510:510:510) (562:562:562)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (486:486:486) (528:528:528)) - (PORT ena (772:772:772) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (408:408:408)) - (PORT datab (378:378:378) (456:456:456)) - (PORT datad (330:330:330) (383:383:383)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (293:293:293) (332:332:332)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (804:804:804) (906:906:906)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (484:484:484) (526:526:526)) - (PORT ena (417:417:417) (434:434:434)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (154:154:154) (195:195:195)) - (PORT datab (361:361:361) (437:437:437)) - (PORT datad (301:301:301) (346:346:346)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (771:771:771) (831:831:831)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (417:417:417)) - (PORT datab (189:189:189) (226:226:226)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (453:453:453) (524:524:524)) - (PORT datab (173:173:173) (212:212:212)) - (PORT datac (316:316:316) (371:371:371)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (562:562:562) (637:637:637)) - (PORT datac (300:300:300) (342:342:342)) - (PORT datad (1038:1038:1038) (1209:1209:1209)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT asdata (278:278:278) (298:298:298)) - (PORT ena (514:514:514) (543:543:543)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (783:783:783)) - (PORT datab (482:482:482) (562:562:562)) - (PORT datad (216:216:216) (248:248:248)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (292:292:292)) - (PORT datac (242:242:242) (285:285:285)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (414:414:414)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datac (296:296:296) (347:347:347)) - (PORT datad (807:807:807) (964:964:964)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (1034:1034:1034)) - (PORT datac (339:339:339) (394:394:394)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (905:905:905) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (892:892:892)) - (PORT ena (1352:1352:1352) (1505:1505:1505)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (154:154:154)) - (PORT datab (604:604:604) (703:703:703)) - (PORT datac (373:373:373) (454:454:454)) - (PORT datad (579:579:579) (665:665:665)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (484:484:484)) - (PORT datab (427:427:427) (496:496:496)) - (PORT datac (384:384:384) (437:437:437)) - (PORT datad (101:101:101) (123:123:123)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (99:99:99) (126:126:126)) - (PORT datad (368:368:368) (450:450:450)) - (IOPATH dataa combout (181:181:181) (180:180:180)) - (IOPATH datab combout (182:182:182) (181:181:181)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (372:372:372)) - (PORT datab (822:822:822) (987:987:987)) - (PORT datac (316:316:316) (368:368:368)) - (PORT datad (338:338:338) (394:394:394)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (802:802:802) (886:886:886)) - (PORT ena (659:659:659) (712:712:712)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (805:805:805) (889:889:889)) - (PORT ena (759:759:759) (815:815:815)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (401:401:401)) - (PORT datab (492:492:492) (569:569:569)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT asdata (924:924:924) (1021:1021:1021)) - (PORT ena (657:657:657) (713:713:713)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (913:913:913)) - (PORT asdata (814:814:814) (911:911:911)) - (PORT ena (807:807:807) (897:897:897)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (401:401:401)) - (PORT datab (216:216:216) (274:274:274)) - (PORT datad (312:312:312) (359:359:359)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (811:811:811) (908:908:908)) - (PORT ena (641:641:641) (691:691:691)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (152:152:152) (197:197:197)) - (PORT datab (467:467:467) (545:545:545)) - (PORT datad (435:435:435) (497:497:497)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (913:913:913)) - (PORT asdata (815:815:815) (911:911:911)) - (PORT ena (421:421:421) (441:441:441)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (212:212:212) (253:253:253)) - (PORT datad (115:115:115) (136:136:136)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (102:102:102) (119:119:119)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (766:766:766) (843:843:843)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (915:915:915)) - (PORT asdata (925:925:925) (1023:1023:1023)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (735:735:735)) - (PORT datab (494:494:494) (569:569:569)) - (PORT datad (123:123:123) (147:147:147)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (541:541:541)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (161:161:161) (189:189:189)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (512:512:512) (559:559:559)) - (PORT ena (630:630:630) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (512:512:512) (560:560:560)) - (PORT ena (617:617:617) (660:660:660)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (418:418:418)) - (PORT datab (374:374:374) (446:446:446)) - (PORT datad (347:347:347) (411:411:411)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (685:685:685) (763:763:763)) - (PORT ena (641:641:641) (690:690:690)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (682:682:682) (759:759:759)) - (PORT ena (688:688:688) (756:756:756)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (382:382:382) (453:453:453)) - (PORT datad (372:372:372) (439:439:439)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (533:533:533)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datad (333:333:333) (390:390:390)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (264:264:264)) - (PORT datab (290:290:290) (338:338:338)) - (PORT datac (711:711:711) (802:802:802)) - (PORT datad (745:745:745) (879:879:879)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (683:683:683)) - (PORT datab (124:124:124) (157:157:157)) - (PORT datac (681:681:681) (780:780:780)) - (PORT datad (331:331:331) (384:384:384)) + (PORT dataa (196:196:196) (237:237:237)) + (PORT datab (203:203:203) (246:246:246)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (179:179:179) (209:209:209)) (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (494:494:494) (574:574:574)) - (PORT datac (915:915:915) (1042:1042:1042)) - (PORT datad (344:344:344) (404:404:404)) - (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) (DELAY (ABSOLUTE - (PORT dataa (347:347:347) (412:412:412)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (302:302:302) (354:354:354)) - (PORT datad (336:336:336) (395:395:395)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (698:698:698)) + (PORT dataa (194:194:194) (233:233:233)) (PORT datab (102:102:102) (131:131:131)) - (PORT datac (287:287:287) (331:331:331)) - (PORT datad (123:123:123) (154:154:154)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (183:183:183) (219:219:219)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (752:752:752)) + (PORT datab (152:152:152) (194:194:194)) + (PORT datac (136:136:136) (173:173:173)) + (PORT datad (140:140:140) (170:170:170)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1087:1087:1087)) + (PORT datac (486:486:486) (558:558:558)) + (PORT datad (479:479:479) (548:548:548)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (499:499:499) (575:575:575)) + (PORT datad (130:130:130) (158:158:158)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -28077,291 +28263,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~0) + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) (DELAY (ABSOLUTE - (PORT dataa (474:474:474) (568:568:568)) - (PORT datac (654:654:654) (787:787:787)) - (PORT datad (466:466:466) (547:547:547)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (702:702:702)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (844:844:844) (999:999:999)) - (PORT datad (712:712:712) (816:816:816)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (424:424:424)) - (PORT datab (491:491:491) (571:571:571)) - (PORT datad (503:503:503) (584:584:584)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (725:725:725)) - (PORT datab (221:221:221) (282:282:282)) - (PORT datac (213:213:213) (266:266:266)) - (PORT datad (607:607:607) (708:708:708)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (219:219:219)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (602:602:602) (706:706:706)) - (PORT datad (648:648:648) (742:742:742)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (926:926:926) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (435:435:435) (467:467:467)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (427:427:427)) - (PORT datab (490:490:490) (569:569:569)) - (PORT datac (604:604:604) (701:701:701)) - (PORT datad (505:505:505) (584:584:584)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (353:353:353) (414:414:414)) - (PORT datac (612:612:612) (717:717:717)) - (PORT datad (650:650:650) (744:744:744)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (926:926:926) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (435:435:435) (467:467:467)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (465:465:465)) - (PORT datab (465:465:465) (547:547:547)) - (PORT datac (357:357:357) (442:442:442)) - (PORT datad (468:468:468) (543:543:543)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (496:496:496)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (746:746:746) (864:864:864)) - (PORT datad (384:384:384) (464:464:464)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (232:232:232)) - (PORT datab (115:115:115) (142:142:142)) - (PORT datac (174:174:174) (200:200:200)) - (PORT datad (113:113:113) (134:134:134)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~1) - (DELAY - (ABSOLUTE - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (166:166:166) (197:197:197)) - (PORT datad (111:111:111) (132:132:132)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (381:381:381) (456:456:456)) - (PORT datac (649:649:649) (781:781:781)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (132:132:132)) - (PORT datab (496:496:496) (593:593:593)) - (PORT datac (841:841:841) (997:997:997)) - (PORT datad (713:713:713) (817:817:817)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (588:588:588)) - (PORT datab (371:371:371) (462:462:462)) - (PORT datac (384:384:384) (472:472:472)) - (PORT datad (567:567:567) (655:655:655)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (700:700:700) (800:800:800)) - (PORT datac (349:349:349) (412:412:412)) - (PORT datad (703:703:703) (832:832:832)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (373:373:373)) - (PORT datab (189:189:189) (228:228:228)) - (PORT datac (710:710:710) (808:808:808)) - (PORT datad (322:322:322) (372:372:372)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (294:294:294) (342:342:342)) - (PORT datab (635:635:635) (730:730:730)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (452:452:452) (523:523:523)) + (PORT dataa (346:346:346) (419:419:419)) + (PORT datab (649:649:649) (750:750:750)) + (PORT datac (222:222:222) (282:282:282)) + (PORT datad (368:368:368) (436:436:436)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -28371,1139 +28279,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (401:401:401)) - (PORT datab (472:472:472) (551:551:551)) - (PORT datac (352:352:352) (419:419:419)) - (PORT datad (126:126:126) (158:158:158)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (453:453:453)) - (PORT datab (336:336:336) (390:390:390)) - (PORT datac (903:903:903) (1036:1036:1036)) - (PORT datad (352:352:352) (416:416:416)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (650:650:650)) - (PORT datab (576:576:576) (668:668:668)) - (PORT datac (186:186:186) (219:219:219)) - (PORT datad (467:467:467) (543:543:543)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (800:800:800)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (318:318:318) (373:373:373)) - (PORT datad (443:443:443) (508:508:508)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (407:407:407)) - (PORT datab (366:366:366) (428:428:428)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (335:335:335) (391:391:391)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (274:274:274)) - (PORT datab (195:195:195) (233:233:233)) - (PORT datac (347:347:347) (402:402:402)) - (PORT datad (434:434:434) (496:496:496)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (408:408:408) (428:428:428)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1029:1029:1029) (1188:1188:1188)) - (PORT datab (473:473:473) (558:558:558)) - (PORT datac (505:505:505) (603:603:603)) - (PORT datad (770:770:770) (877:877:877)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1485:1485:1485) (1717:1717:1717)) - (PORT datab (724:724:724) (829:829:829)) - (PORT datac (485:485:485) (575:575:575)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (308:308:308) (358:358:358)) - (PORT datab (364:364:364) (426:426:426)) - (PORT datac (261:261:261) (298:298:298)) - (PORT datad (270:270:270) (313:313:313)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (534:534:534)) - (PORT datab (313:313:313) (366:366:366)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (628:628:628) (684:684:684)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (653:653:653)) - (PORT datab (544:544:544) (650:650:650)) - (PORT datac (1238:1238:1238) (1424:1424:1424)) - (PORT datad (308:308:308) (365:365:365)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (710:710:710)) - (PORT datab (463:463:463) (531:531:531)) - (PORT datac (468:468:468) (538:538:538)) - (PORT datad (448:448:448) (519:519:519)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1243:1243:1243)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (476:476:476) (560:560:560)) - (PORT datad (178:178:178) (211:211:211)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (133:133:133) (184:184:184)) - (PORT datab (310:310:310) (362:362:362)) - (PORT datac (441:441:441) (509:509:509)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (294:294:294) (341:341:341)) - (PORT datab (639:639:639) (743:743:743)) - (PORT datac (456:456:456) (527:527:527)) - (PORT datad (665:665:665) (770:770:770)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (562:562:562)) - (PORT datab (772:772:772) (919:919:919)) - (PORT datac (680:680:680) (823:823:823)) - (PORT datad (586:586:586) (691:691:691)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (464:464:464) (534:534:534)) - (PORT datab (1187:1187:1187) (1351:1351:1351)) - (PORT datac (462:462:462) (534:534:534)) - (PORT datad (648:648:648) (748:748:748)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (147:147:147)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (348:348:348) (404:404:404)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (378:378:378)) - (PORT datab (479:479:479) (554:554:554)) - (PORT datac (368:368:368) (438:438:438)) - (PORT datad (469:469:469) (539:539:539)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) - (DELAY - (ABSOLUTE - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (126:126:126) (151:151:151)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (495:495:495) (589:589:589)) - (PORT datac (445:445:445) (512:512:512)) - (PORT datad (450:450:450) (521:521:521)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (709:709:709)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (468:468:468) (538:538:538)) - (PORT datad (177:177:177) (209:209:209)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (451:451:451)) - (PORT datab (245:245:245) (314:314:314)) - (PORT datac (237:237:237) (295:295:295)) - (PORT datad (618:618:618) (714:714:714)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (479:479:479)) - (PORT datab (510:510:510) (605:605:605)) - (PORT datac (340:340:340) (412:412:412)) - (PORT datad (370:370:370) (452:452:452)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (263:263:263)) - (PORT datab (517:517:517) (641:641:641)) - (PORT datac (361:361:361) (437:437:437)) - (PORT datad (369:369:369) (448:448:448)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (893:893:893)) - (PORT ena (1338:1338:1338) (1484:1484:1484)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (416:416:416)) - (PORT datab (141:141:141) (193:193:193)) - (PORT datac (602:602:602) (703:703:703)) - (PORT datad (214:214:214) (262:262:262)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (394:394:394)) - (PORT datab (339:339:339) (397:397:397)) - (PORT datac (837:837:837) (979:979:979)) - (PORT datad (165:165:165) (193:193:193)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (707:707:707)) - (PORT datab (490:490:490) (574:574:574)) - (PORT datad (278:278:278) (317:317:317)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (897:897:897)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (499:499:499) (596:596:596)) - (PORT datac (469:469:469) (539:539:539)) - (PORT datad (123:123:123) (163:163:163)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (586:586:586)) - (PORT datab (467:467:467) (544:544:544)) - (PORT datac (445:445:445) (512:512:512)) - (PORT datad (1051:1051:1051) (1214:1214:1214)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (375:375:375) (440:440:440)) - (PORT datab (194:194:194) (236:236:236)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (334:334:334) (391:391:391)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (485:485:485) (564:564:564)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (591:591:591) (691:691:691)) - (PORT datad (1050:1050:1050) (1213:1213:1213)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (849:849:849)) - (PORT datab (770:770:770) (917:917:917)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (229:229:229)) - (PORT datab (117:117:117) (145:145:145)) - (PORT datac (132:132:132) (174:174:174)) - (PORT datad (446:446:446) (510:510:510)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~13) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (401:401:401)) - (PORT datab (185:185:185) (222:222:222)) - (PORT datac (334:334:334) (386:386:386)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (559:559:559)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (469:469:469) (547:547:547)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) (DELAY (ABSOLUTE (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (787:787:787) (901:901:901)) - (PORT datad (1156:1156:1156) (1329:1329:1329)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|flags_cond_true) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (665:665:665)) - (PORT datab (483:483:483) (569:569:569)) - (PORT datac (436:436:436) (506:506:506)) - (PORT datad (872:872:872) (995:995:995)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (143:143:143)) - (PORT datab (370:370:370) (433:433:433)) - (PORT datac (553:553:553) (619:619:619)) - (PORT datad (320:320:320) (374:374:374)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (286:286:286) (325:325:325)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) - (DELAY - (ABSOLUTE - (PORT dataa (571:571:571) (658:658:658)) - (PORT datac (508:508:508) (582:582:582)) - (PORT datad (548:548:548) (626:626:626)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (738:738:738)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (101:101:101) (121:121:121)) - (PORT datad (317:317:317) (367:367:367)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (114:114:114) (145:145:145)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (452:452:452) (518:518:518)) - (PORT datad (102:102:102) (118:118:118)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (179:179:179) (224:224:224)) - (PORT datab (117:117:117) (145:145:145)) - (PORT datac (102:102:102) (122:122:122)) - (PORT datad (357:357:357) (415:415:415)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (393:393:393)) - (PORT datab (304:304:304) (354:354:354)) - (PORT datac (880:880:880) (1031:1031:1031)) - (PORT datad (670:670:670) (777:777:777)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (966:966:966) (1085:1085:1085)) - (PORT ena (422:422:422) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (962:962:962) (1081:1081:1081)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (275:275:275)) - (PORT datab (227:227:227) (270:270:270)) - (PORT datad (188:188:188) (235:235:235)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT asdata (783:783:783) (868:868:868)) - (PORT ena (433:433:433) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (792:792:792)) - (PORT datab (769:769:769) (888:888:888)) - (PORT datad (1021:1021:1021) (1174:1174:1174)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (920:920:920)) - (PORT asdata (962:962:962) (1089:1089:1089)) - (PORT ena (494:494:494) (536:536:536)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (971:971:971) (1088:1088:1088)) - (PORT ena (794:794:794) (877:877:877)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (281:281:281)) - (PORT datab (224:224:224) (272:272:272)) - (PORT datad (189:189:189) (235:235:235)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (489:489:489) (540:540:540)) - (PORT ena (774:774:774) (865:865:865)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (493:493:493) (544:544:544)) - (PORT ena (767:767:767) (833:833:833)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (234:234:234) (292:292:292)) - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (355:355:355) (417:417:417)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (947:947:947) (1062:1062:1062)) - (PORT ena (631:631:631) (678:678:678)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT asdata (946:946:946) (1061:1061:1061)) - (PORT ena (649:649:649) (709:709:709)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (407:407:407)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (329:329:329) (375:375:375)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (920:920:920)) - (PORT asdata (973:973:973) (1090:1090:1090)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (810:810:810)) - (PORT datab (584:584:584) (672:672:672)) - (PORT datad (203:203:203) (235:235:235)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (404:404:404)) - (PORT datab (366:366:366) (434:434:434)) - (PORT datac (322:322:322) (372:372:372)) - (PORT datad (322:322:322) (375:375:375)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (487:487:487) (563:563:563)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (926:926:926)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT asdata (781:781:781) (865:865:865)) - (PORT ena (421:421:421) (441:441:441)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (257:257:257)) - (PORT datab (211:211:211) (250:250:250)) - (PORT datad (364:364:364) (436:436:436)) + (PORT datab (606:606:606) (705:705:705)) + (PORT datac (320:320:320) (375:375:375)) + (PORT datad (335:335:335) (389:389:389)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (429:429:429)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -29511,13 +28295,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~39) + (INSTANCE z80_\|alu_\|db_high\[2\]\~14) (DELAY (ABSOLUTE - (PORT dataa (1147:1147:1147) (1351:1351:1351)) - (PORT datab (315:315:315) (363:363:363)) - (PORT datac (290:290:290) (341:341:341)) - (PORT datad (468:468:468) (542:542:542)) + (PORT dataa (689:689:689) (813:813:813)) + (PORT datab (128:128:128) (167:167:167)) + (PORT datac (521:521:521) (619:619:619)) + (PORT datad (167:167:167) (197:197:197)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (839:839:839)) + (PORT datab (536:536:536) (629:629:629)) + (PORT datac (915:915:915) (1056:1056:1056)) + (PORT datad (471:471:471) (544:544:544)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -29525,363 +28325,16 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (915:915:915)) - (PORT asdata (465:465:465) (514:514:514)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~7) + (INSTANCE z80_\|alu_\|db\[6\]\~23) (DELAY (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (531:531:531) (645:645:645)) - (PORT datad (128:128:128) (164:164:164)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (505:505:505) (546:546:546)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (213:213:213)) - (PORT datab (237:237:237) (283:283:283)) - (PORT datad (120:120:120) (158:158:158)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (155:155:155)) - (PORT datab (599:599:599) (715:715:715)) - (PORT datac (364:364:364) (440:440:440)) - (PORT datad (207:207:207) (253:253:253)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (357:357:357) (428:428:428)) - (PORT datad (579:579:579) (667:667:667)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (211:211:211) (255:255:255)) - (PORT datac (954:954:954) (1133:1133:1133)) - (PORT datad (342:342:342) (392:392:392)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) - (DELAY - (ABSOLUTE - (PORT datac (860:860:860) (1011:1011:1011)) - (PORT datad (552:552:552) (648:648:648)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (905:905:905) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (892:892:892)) - (PORT ena (1352:1352:1352) (1505:1505:1505)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (562:562:562) (666:666:666)) - (PORT datab (244:244:244) (313:313:313)) - (PORT datac (356:356:356) (427:427:427)) - (PORT datad (579:579:579) (667:667:667)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (915:915:915)) - (PORT asdata (347:347:347) (380:380:380)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (317:317:317) (366:366:366)) - (PORT datab (531:531:531) (646:646:646)) - (PORT datad (128:128:128) (161:161:161)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (505:505:505) (546:546:546)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (228:228:228)) - (PORT datab (244:244:244) (291:291:291)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (683:683:683)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (962:962:962) (1141:1141:1141)) - (PORT datad (191:191:191) (226:226:226)) + (PORT dataa (342:342:342) (401:401:401)) + (PORT datab (542:542:542) (634:634:634)) + (PORT datac (161:161:161) (194:194:194)) + (PORT datad (123:123:123) (154:154:154)) (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (1034:1034:1034)) - (PORT datac (325:325:325) (379:379:379)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (905:905:905) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (892:892:892)) - (PORT ena (1352:1352:1352) (1505:1505:1505)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (665:665:665)) - (PORT datab (242:242:242) (311:311:311)) - (PORT datac (355:355:355) (426:426:426)) - (PORT datad (579:579:579) (667:667:667)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (217:217:217)) - (PORT datab (214:214:214) (270:270:270)) - (PORT datac (332:332:332) (393:393:393)) - (PORT datad (209:209:209) (257:257:257)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT datab (211:211:211) (274:274:274)) - (PORT datad (100:100:100) (122:122:122)) - (IOPATH datab combout (192:192:192) (181:181:181)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (505:505:505) (546:546:546)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (915:915:915)) - (PORT asdata (367:367:367) (400:400:400)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (147:147:147) (194:194:194)) - (PORT datab (524:524:524) (637:637:637)) - (PORT datad (307:307:307) (352:352:352)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (242:242:242) (289:289:289)) - (PORT datac (116:116:116) (157:157:157)) - (PORT datad (157:157:157) (183:183:183)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -29890,15 +28343,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~21) + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) (DELAY (ABSOLUTE - (PORT dataa (345:345:345) (415:415:415)) - (PORT datab (209:209:209) (253:253:253)) - (PORT datac (957:957:957) (1136:1136:1136)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (204:204:204) (261:261:261)) + (PORT datab (141:141:141) (189:189:189)) + (PORT datac (128:128:128) (169:169:169)) + (PORT datad (104:104:104) (122:122:122)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (752:752:752)) + (PORT datab (344:344:344) (406:406:406)) + (PORT datac (338:338:338) (413:413:413)) + (PORT datad (128:128:128) (170:170:170)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (716:716:716)) + (PORT datab (499:499:499) (574:574:574)) + (PORT datac (348:348:348) (415:415:415)) + (PORT datad (470:470:470) (539:539:539)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (503:503:503) (574:574:574)) + (PORT datac (597:597:597) (687:687:687)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -29906,25 +28405,73 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (INSTANCE z80_\|alu_control_\|db\[6\]\~21) (DELAY (ABSOLUTE - (PORT datac (852:852:852) (987:987:987)) - (PORT datad (338:338:338) (387:387:387)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (527:527:527) (617:617:617)) + (PORT datab (520:520:520) (607:607:607)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (487:487:487) (555:555:555)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (430:430:430)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (881:881:881) (1001:1001:1001)) + (PORT datad (480:480:480) (538:538:538)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (381:381:381)) + (PORT datab (696:696:696) (795:795:795)) + (PORT datac (627:627:627) (732:732:732)) + (PORT datad (174:174:174) (208:208:208)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) + (DELAY + (ABSOLUTE + (PORT datab (155:155:155) (199:199:199)) + (PORT datad (133:133:133) (164:164:164)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) + (INSTANCE z80_\|interrupts_\|im1) (DELAY (ABSOLUTE (PORT clk (906:906:906) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (893:893:893)) - (PORT ena (1338:1338:1338) (1484:1484:1484)) + (PORT clrn (911:911:911) (895:895:895)) + (PORT ena (667:667:667) (732:732:732)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -29936,11 +28483,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) (DELAY (ABSOLUTE - (PORT datac (329:329:329) (389:389:389)) - (PORT datad (198:198:198) (250:250:250)) + (PORT dataa (666:666:666) (769:769:769)) + (PORT datab (669:669:669) (790:790:790)) + (PORT datac (676:676:676) (800:800:800)) + (PORT datad (147:147:147) (190:190:190)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (276:276:276)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (631:631:631) (720:720:720)) + (PORT datad (644:644:644) (741:741:741)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (643:643:643)) + (PORT datab (644:644:644) (740:740:740)) + (PORT datac (366:366:366) (427:427:427)) + (PORT datad (345:345:345) (403:403:403)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (471:471:471) (544:544:544)) + (PORT datac (520:520:520) (612:612:612)) + (PORT datad (113:113:113) (136:136:136)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -29948,15 +28545,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) + (INSTANCE z80_\|execute_\|ctl_mRead\~37) (DELAY (ABSOLUTE - (PORT dataa (116:116:116) (153:153:153)) - (PORT datab (604:604:604) (703:703:703)) - (PORT datac (351:351:351) (421:421:421)) - (PORT datad (577:577:577) (663:663:663)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (188:188:188) (177:177:177)) + (PORT dataa (705:705:705) (831:831:831)) + (PORT datab (1183:1183:1183) (1403:1403:1403)) + (PORT datac (467:467:467) (556:556:556)) + (PORT datad (515:515:515) (607:607:607)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (694:694:694) (800:800:800)) + (PORT datac (778:778:778) (887:887:887)) + (PORT datad (504:504:504) (590:590:590)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -29964,60 +28577,187 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) + (INSTANCE z80_\|execute_\|ctl_mRead\~29) (DELAY (ABSOLUTE - (PORT dataa (389:389:389) (443:443:443)) - (PORT datab (111:111:111) (141:141:141)) - (PORT datac (125:125:125) (170:170:170)) - (PORT datad (426:426:426) (487:487:487)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (130:130:130) (159:159:159)) + (PORT datac (1120:1120:1120) (1313:1313:1313)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (915:915:915)) - (PORT asdata (488:488:488) (539:539:539)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (480:480:480) (563:563:563)) + (PORT datab (119:119:119) (154:154:154)) + (PORT datac (337:337:337) (393:393:393)) + (PORT datad (523:523:523) (610:610:610)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~4) + (INSTANCE z80_\|execute_\|setM1\~37) (DELAY (ABSOLUTE - (PORT dataa (144:144:144) (191:191:191)) - (PORT datab (332:332:332) (385:385:385)) - (PORT datad (509:509:509) (616:616:616)) + (PORT dataa (580:580:580) (677:677:677)) + (PORT datab (604:604:604) (708:708:708)) + (PORT datac (553:553:553) (632:632:632)) + (PORT datad (335:335:335) (389:389:389)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (646:646:646)) + (PORT datab (608:608:608) (690:690:690)) + (PORT datac (536:536:536) (633:633:633)) + (PORT datad (581:581:581) (648:648:648)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~38) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (562:562:562)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (280:280:280) (321:321:321)) + (PORT datad (285:285:285) (327:327:327)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (427:427:427)) + (PORT datab (500:500:500) (578:578:578)) + (PORT datac (1097:1097:1097) (1249:1249:1249)) + (PORT datad (437:437:437) (502:502:502)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~3) + (DELAY + (ABSOLUTE + (PORT datab (457:457:457) (536:536:536)) + (PORT datac (349:349:349) (411:411:411)) + (PORT datad (108:108:108) (130:130:130)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (156:156:156)) + (PORT datab (127:127:127) (160:160:160)) + (PORT datac (183:183:183) (220:220:220)) + (PORT datad (582:582:582) (649:649:649)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (485:485:485)) + (PORT datab (879:879:879) (1005:1005:1005)) + (PORT datac (332:332:332) (392:392:392)) + (PORT datad (288:288:288) (334:334:334)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (334:334:334)) + (PORT datac (729:729:729) (812:812:812)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (661:661:661)) + (PORT datab (300:300:300) (349:349:349)) + (PORT datac (420:420:420) (472:472:472)) + (PORT datad (417:417:417) (464:464:464)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) + (PORT clk (916:916:916) (923:923:923)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (505:505:505) (546:546:546)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (689:689:689) (767:767:767)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK @@ -30027,55 +28767,105 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~5) + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (288:288:288)) - (PORT datac (161:161:161) (189:189:189)) - (PORT datad (118:118:118) (155:155:155)) + (PORT datad (453:453:453) (528:528:528)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (925:925:925) (908:908:908)) + (PORT ena (602:602:602) (646:646:646)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (912:912:912)) + (PORT asdata (661:661:661) (755:755:755)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (704:704:704) (789:789:789)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (601:601:601)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~4) + (DELAY + (ABSOLUTE + (PORT dataa (125:125:125) (159:159:159)) + (PORT datab (399:399:399) (483:483:483)) + (PORT datac (471:471:471) (548:548:548)) + (PORT datad (606:606:606) (687:687:687)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (415:415:415)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (963:963:963) (1142:1142:1142)) - (PORT datad (190:190:190) (225:225:225)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (427:427:427)) - (PORT datac (855:855:855) (991:991:991)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (INSTANCE z80_\|execute_\|ctl_iorw\~12) (DELAY (ABSOLUTE - (PORT datab (572:572:572) (660:660:660)) - (PORT datac (174:174:174) (204:204:204)) - (PORT datad (736:736:736) (850:850:850)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (1064:1064:1064) (1229:1229:1229)) + (PORT datab (829:829:829) (953:953:953)) + (PORT datac (830:830:830) (962:962:962)) + (PORT datad (1098:1098:1098) (1256:1256:1256)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~8) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (713:713:713)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (105:105:105) (128:128:128)) + (PORT datad (388:388:388) (461:461:461)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -30083,29 +28873,112 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) + (INSTANCE z80_\|execute_\|ctl_iorw\~9) (DELAY (ABSOLUTE - (PORT dataa (413:413:413) (473:473:473)) - (PORT datab (859:859:859) (1019:1019:1019)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (896:896:896)) - (PORT datab (459:459:459) (548:548:548)) - (PORT datac (639:639:639) (759:759:759)) + (PORT dataa (467:467:467) (537:537:537)) + (PORT datab (648:648:648) (746:746:746)) + (PORT datac (457:457:457) (517:517:517)) + (PORT datad (435:435:435) (495:495:495)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (689:689:689) (767:767:767)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (120:120:120) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (689:689:689) (767:767:767)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (912:912:912)) + (PORT asdata (307:307:307) (347:347:347)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (704:704:704) (789:789:789)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (912:912:912)) + (PORT asdata (298:298:298) (339:339:339)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (704:704:704) (789:789:789)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|iorq\~0) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (183:183:183)) + (PORT datad (316:316:316) (377:377:377)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -30114,12 +28987,12 @@ (INSTANCE z80_\|execute_\|fIORead\~1) (DELAY (ABSOLUTE - (PORT dataa (1025:1025:1025) (1164:1164:1164)) - (PORT datab (652:652:652) (767:767:767)) - (PORT datac (1083:1083:1083) (1263:1263:1263)) - (PORT datad (103:103:103) (121:121:121)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (116:116:116) (146:146:146)) + (PORT datab (542:542:542) (637:637:637)) + (PORT datac (192:192:192) (230:230:230)) + (PORT datad (118:118:118) (135:135:135)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -30130,12 +29003,12 @@ (INSTANCE z80_\|execute_\|fIORead\~2) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (237:237:237)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (494:494:494) (566:566:566)) - (PORT datad (505:505:505) (585:585:585)) + (PORT dataa (476:476:476) (554:554:554)) + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (659:659:659) (755:755:755)) + (PORT datad (604:604:604) (693:693:693)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -30146,10 +29019,10 @@ (INSTANCE z80_\|execute_\|fIORead\~0) (DELAY (ABSOLUTE - (PORT dataa (305:305:305) (361:361:361)) - (PORT datab (651:651:651) (765:765:765)) - (PORT datac (1079:1079:1079) (1258:1258:1258)) - (PORT datad (297:297:297) (342:342:342)) + (PORT dataa (1045:1045:1045) (1187:1187:1187)) + (PORT datab (859:859:859) (999:999:999)) + (PORT datac (1202:1202:1202) (1386:1386:1386)) + (PORT datad (113:113:113) (135:135:135)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -30162,10 +29035,10 @@ (INSTANCE z80_\|execute_\|fIORead\~3) (DELAY (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (539:539:539) (632:632:632)) - (PORT datac (656:656:656) (746:746:746)) - (PORT datad (93:93:93) (111:111:111)) + (PORT dataa (115:115:115) (145:145:145)) + (PORT datab (173:173:173) (211:211:211)) + (PORT datac (305:305:305) (347:347:347)) + (PORT datad (188:188:188) (222:222:222)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -30174,14 +29047,195 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) (DELAY (ABSOLUTE - (PORT dataa (567:567:567) (655:655:655)) - (PORT datab (107:107:107) (138:138:138)) - (PORT datac (645:645:645) (767:767:767)) - (PORT datad (570:570:570) (653:653:653)) + (PORT clk (924:924:924) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (920:920:920) (902:902:902)) + (PORT ena (983:983:983) (1112:1112:1112)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) + (DELAY + (ABSOLUTE + (PORT datad (309:309:309) (371:371:371)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (912:912:912)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (704:704:704) (789:789:789)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (923:923:923)) + (PORT asdata (298:298:298) (340:340:340)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (689:689:689) (767:767:767)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (940:940:940)) + (PORT datab (134:134:134) (184:184:184)) + (PORT datad (824:824:824) (959:959:959)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (214:214:214)) + (PORT datab (183:183:183) (225:225:225)) + (PORT datac (557:557:557) (634:634:634)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (975:975:975) (1134:1134:1134)) + (PORT datab (898:898:898) (1064:1064:1064)) + (PORT datac (659:659:659) (776:776:776)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1334:1334:1334) (1561:1561:1561)) + (PORT datad (572:572:572) (677:677:677)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~5) + (DELAY + (ABSOLUTE + (PORT datab (745:745:745) (882:882:882)) + (PORT datac (1646:1646:1646) (1901:1901:1901)) + (PORT datad (1457:1457:1457) (1728:1728:1728)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (230:230:230)) + (PORT datab (470:470:470) (547:547:547)) + (PORT datac (546:546:546) (629:629:629)) + (PORT datad (576:576:576) (646:646:646)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (617:617:617)) + (PORT datac (650:650:650) (757:757:757)) + (PORT datad (1146:1146:1146) (1341:1341:1341)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (781:781:781) (907:907:907)) + (PORT datab (509:509:509) (601:601:601)) + (PORT datac (185:185:185) (217:217:217)) + (PORT datad (101:101:101) (118:118:118)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (446:446:446)) + (PORT datab (450:450:450) (528:528:528)) + (PORT datac (462:462:462) (539:539:539)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -30191,60 +29245,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (752:752:752) (893:893:893)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (646:646:646) (768:768:768)) - (PORT datad (585:585:585) (697:697:697)) + (PORT dataa (719:719:719) (828:828:828)) + (PORT datab (468:468:468) (534:534:534)) + (PORT datac (714:714:714) (810:810:810)) + (PORT datad (352:352:352) (411:411:411)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (902:902:902)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (302:302:302) (345:345:345)) - (PORT sload (1014:1014:1014) (1133:1133:1133)) - (PORT ena (1029:1029:1029) (1122:1122:1122)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (660:660:660) (772:772:772)) - (PORT datad (1553:1553:1553) (1821:1821:1821)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) (DELAY (ABSOLUTE - (PORT datab (150:150:150) (205:205:205)) - (PORT datac (366:366:366) (442:442:442)) - (PORT datad (169:169:169) (199:199:199)) + (PORT dataa (102:102:102) (134:134:134)) + (PORT datab (590:590:590) (677:677:677)) + (PORT datac (191:191:191) (226:226:226)) + (PORT datad (1006:1006:1006) (1174:1174:1174)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -30253,521 +29277,137 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (INSTANCE z80_\|execute_\|fMWrite\~7) (DELAY (ABSOLUTE - (PORT dataa (352:352:352) (423:423:423)) - (PORT datab (176:176:176) (232:232:232)) - (PORT datac (503:503:503) (607:607:607)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (500:500:500) (588:588:588)) + (PORT datac (481:481:481) (557:557:557)) + (PORT datad (407:407:407) (466:466:466)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (995:995:995)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (940:940:940) (1095:1095:1095)) + (PORT datad (482:482:482) (558:558:558)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (787:787:787) (919:919:919)) + (PORT datab (636:636:636) (729:729:729)) + (PORT datac (472:472:472) (558:558:558)) + (PORT datad (407:407:407) (465:465:465)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (994:994:994)) + (PORT datab (632:632:632) (739:739:739)) + (PORT datac (605:605:605) (693:693:693)) + (PORT datad (332:332:332) (389:389:389)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~9) + (DELAY + (ABSOLUTE + (PORT dataa (696:696:696) (827:827:827)) + (PORT datab (475:475:475) (551:551:551)) + (PORT datac (943:943:943) (1088:1088:1088)) + (PORT datad (143:143:143) (178:178:178)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (726:726:726)) + (PORT datab (112:112:112) (143:143:143)) + (PORT datac (101:101:101) (123:123:123)) + (PORT datad (343:343:343) (401:401:401)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (118:118:118) (147:147:147)) + (PORT datac (574:574:574) (650:650:650)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (INSTANCE z80_\|execute_\|fMWrite\~8) (DELAY (ABSOLUTE - (PORT dataa (359:359:359) (440:440:440)) - (PORT datab (251:251:251) (316:316:316)) - (PORT datac (595:595:595) (697:697:697)) - (PORT datad (630:630:630) (749:749:749)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (458:458:458)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datad (636:636:636) (746:746:746)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (495:495:495)) - (PORT datab (324:324:324) (378:378:378)) - (PORT datad (446:446:446) (513:513:513)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (497:497:497)) - (PORT datab (225:225:225) (292:292:292)) - (PORT datac (511:511:511) (601:601:601)) + (PORT dataa (590:590:590) (673:673:673)) + (PORT datab (466:466:466) (542:542:542)) + (PORT datac (326:326:326) (377:377:377)) + (PORT datad (657:657:657) (763:763:763)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (428:428:428)) - (PORT datab (512:512:512) (616:616:616)) - (PORT datac (479:479:479) (578:578:578)) - (PORT datad (211:211:211) (251:251:251)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) (DELAY (ABSOLUTE - (PORT dataa (506:506:506) (607:607:607)) - (PORT datab (524:524:524) (627:627:627)) - (PORT datac (511:511:511) (601:601:601)) - (PORT datad (402:402:402) (489:489:489)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (425:425:425) (494:494:494)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (474:474:474) (563:563:563)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (283:283:283) (333:333:333)) - (PORT datab (856:856:856) (1016:1016:1016)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (902:902:902)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (492:492:492) (563:563:563)) - (PORT sload (1014:1014:1014) (1133:1133:1133)) - (PORT ena (1029:1029:1029) (1122:1122:1122)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[14\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (1766:1766:1766) (2073:2073:2073)) - (PORT datac (833:833:833) (966:966:966)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (441:441:441)) - (PORT datab (468:468:468) (540:540:540)) - (PORT datac (330:330:330) (395:395:395)) - (PORT datad (493:493:493) (582:582:582)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (483:483:483)) - (PORT datab (150:150:150) (206:206:206)) - (PORT datac (367:367:367) (442:442:442)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT datac (627:627:627) (737:737:737)) - (PORT datad (234:234:234) (294:294:294)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (427:427:427)) - (PORT datab (297:297:297) (351:351:351)) - (PORT datac (104:104:104) (126:126:126)) - (PORT datad (494:494:494) (588:588:588)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT datab (487:487:487) (563:563:563)) - (PORT datac (344:344:344) (412:412:412)) - (PORT datad (604:604:604) (707:707:707)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (444:444:444)) - (PORT datab (196:196:196) (236:236:236)) - (PORT datad (243:243:243) (301:301:301)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (868:868:868) (1031:1031:1031)) - (PORT datad (189:189:189) (223:223:223)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (992:992:992) (1156:1156:1156)) - (PORT sload (892:892:892) (1000:1000:1000)) - (PORT ena (1155:1155:1155) (1286:1286:1286)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (1901:1901:1901) (2224:2224:2224)) - (PORT datad (471:471:471) (556:556:556)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (328:328:328)) - (PORT datac (354:354:354) (420:420:420)) - (PORT datad (467:467:467) (554:554:554)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (358:358:358)) - (PORT datab (593:593:593) (699:699:699)) - (PORT datac (212:212:212) (273:273:273)) - (PORT datad (335:335:335) (393:393:393)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (444:444:444)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datad (843:843:843) (1001:1001:1001)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (418:418:418) (475:475:475)) - (PORT sload (892:892:892) (1000:1000:1000)) - (PORT ena (1155:1155:1155) (1286:1286:1286)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[11\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (1902:1902:1902) (2225:2225:2225)) - (PORT datad (822:822:822) (963:963:963)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datab (493:493:493) (576:576:576)) - (PORT datac (115:115:115) (156:156:156)) - (PORT datad (435:435:435) (501:501:501)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (438:438:438)) - (PORT datac (522:522:522) (620:620:620)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (457:457:457)) - (PORT datab (508:508:508) (609:609:609)) - (PORT datad (229:229:229) (288:288:288)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (590:590:590)) - (PORT datab (312:312:312) (370:370:370)) - (PORT datac (493:493:493) (584:584:584)) - (PORT datad (282:282:282) (322:322:322)) + (PORT dataa (491:491:491) (584:584:584)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (314:314:314) (362:362:362)) + (PORT datad (105:105:105) (123:123:123)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -30777,363 +29417,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) (DELAY (ABSOLUTE - (PORT dataa (120:120:120) (152:152:152)) - (PORT datab (111:111:111) (143:143:143)) - (PORT datad (389:389:389) (476:476:476)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (926:926:926)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (251:251:251)) - (PORT datab (863:863:863) (1026:1026:1026)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (407:407:407) (458:458:458)) - (PORT sload (892:892:892) (1000:1000:1000)) - (PORT ena (1155:1155:1155) (1286:1286:1286)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (1402:1402:1402) (1646:1646:1646)) - (PORT datad (1394:1394:1394) (1610:1610:1610)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (861:861:861) (1021:1021:1021)) - (PORT datad (162:162:162) (192:192:192)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (902:902:902)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (780:780:780) (879:879:879)) - (PORT sload (1014:1014:1014) (1133:1133:1133)) - (PORT ena (1029:1029:1029) (1122:1122:1122)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~23) - (DELAY - (ABSOLUTE - (PORT datac (1752:1752:1752) (2055:2055:2055)) - (PORT datad (805:805:805) (947:947:947)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (526:526:526) (631:631:631)) - (PORT datab (599:599:599) (705:705:705)) - (PORT datad (472:472:472) (559:559:559)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT datab (175:175:175) (231:231:231)) - (PORT datac (340:340:340) (405:405:405)) - (PORT datad (501:501:501) (595:595:595)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (630:630:630)) - (PORT datab (638:638:638) (746:746:746)) - (PORT datad (502:502:502) (599:599:599)) + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (168:168:168) (200:200:200)) + (PORT datad (439:439:439) (509:509:509)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (INSTANCE z80_\|execute_\|fMWrite\~10) (DELAY (ABSOLUTE - (PORT dataa (403:403:403) (496:496:496)) - (PORT datab (225:225:225) (293:293:293)) - (PORT datac (488:488:488) (583:583:583)) + (PORT dataa (477:477:477) (549:549:549)) + (PORT datab (578:578:578) (685:685:685)) + (PORT datac (604:604:604) (692:692:692)) + (PORT datad (616:616:616) (702:702:702)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datad (160:160:160) (185:185:185)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (924:924:924)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (533:533:533)) - (PORT datab (805:805:805) (921:921:921)) - (PORT datac (468:468:468) (542:542:542)) - (PORT datad (119:119:119) (157:157:157)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datad (847:847:847) (1005:1005:1005)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (534:534:534) (603:603:603)) - (PORT sload (892:892:892) (1000:1000:1000)) - (PORT ena (1155:1155:1155) (1286:1286:1286)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~19) - (DELAY - (ABSOLUTE - (PORT datac (924:924:924) (1072:1072:1072)) - (PORT datad (1374:1374:1374) (1611:1611:1611)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (425:425:425) (492:492:492)) - (PORT datad (934:934:934) (1096:1096:1096)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (923:923:923) (907:907:907)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1483:1483:1483) (1686:1686:1686)) - (PORT sload (953:953:953) (1073:1073:1073)) - (PORT ena (900:900:900) (990:990:990)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~20) - (DELAY - (ABSOLUTE - (PORT datac (463:463:463) (540:540:540)) - (PORT datad (1743:1743:1743) (2039:2039:2039)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (225:225:225) (293:293:293)) - (PORT datac (378:378:378) (471:471:471)) - (PORT datad (405:405:405) (493:493:493)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (327:327:327)) - (PORT datab (361:361:361) (430:430:430)) - (PORT datac (506:506:506) (600:600:600)) - (PORT datad (465:465:465) (552:552:552)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (519:519:519) (623:623:623)) - (PORT datab (495:495:495) (601:601:601)) - (PORT datac (325:325:325) (392:392:392)) - (PORT datad (282:282:282) (325:325:325)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -31141,133 +29465,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) (DELAY (ABSOLUTE - (PORT dataa (195:195:195) (234:234:234)) - (PORT datab (105:105:105) (133:133:133)) - (PORT datad (316:316:316) (367:367:367)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (423:423:423)) - (PORT datac (216:216:216) (278:278:278)) - (PORT datad (579:579:579) (675:675:675)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (378:378:378) (457:457:457)) - (PORT datac (514:514:514) (619:619:619)) - (PORT datad (602:602:602) (709:709:709)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (327:327:327)) - (PORT datac (504:504:504) (599:599:599)) - (PORT datad (298:298:298) (339:339:339)) + (PORT dataa (302:302:302) (352:352:352)) + (PORT datab (606:606:606) (708:708:708)) + (PORT datac (940:940:940) (1096:1096:1096)) + (PORT datad (93:93:93) (111:111:111)) (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~23) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) (DELAY (ABSOLUTE - (PORT dataa (364:364:364) (448:448:448)) - (PORT datab (189:189:189) (227:227:227)) - (PORT datad (161:161:161) (184:184:184)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1148:1148:1148) (1307:1307:1307)) - (PORT datab (308:308:308) (360:360:360)) - (PORT datac (294:294:294) (347:347:347)) - (PORT datad (187:187:187) (235:235:235)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (381:381:381)) + (PORT dataa (376:376:376) (440:440:440)) (PORT datab (102:102:102) (130:130:130)) - (PORT datac (437:437:437) (501:501:501)) - (PORT datad (89:89:89) (107:107:107)) + (PORT datac (327:327:327) (385:385:385)) + (PORT datad (103:103:103) (121:121:121)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -31275,12 +29495,28 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (498:498:498) (581:581:581)) + (PORT datac (597:597:597) (720:720:720)) + (PORT datad (637:637:637) (733:733:733)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) (DELAY (ABSOLUTE - (PORT datad (455:455:455) (537:537:537)) + (PORT datad (120:120:120) (159:159:159)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -31290,9 +29526,9 @@ (INSTANCE z80_\|clk_delay_\|DFF_inst5) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) + (PORT clk (910:910:910) (917:917:917)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (910:910:910)) + (PORT clrn (924:924:924) (906:906:906)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -31316,9 +29552,9 @@ (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) (DELAY (ABSOLUTE - (PORT clk (927:927:927) (911:911:911)) + (PORT clk (921:921:921) (906:906:906)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (910:910:910)) + (PORT clrn (924:924:924) (906:906:906)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -31332,9 +29568,9 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (301:301:301) (344:344:344)) - (PORT clrn (928:928:928) (910:910:910)) + (PORT clk (910:910:910) (917:917:917)) + (PORT asdata (299:299:299) (342:342:342)) + (PORT clrn (924:924:924) (906:906:906)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -31343,624 +29579,244 @@ (HOLD asdata (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (441:441:441)) - (PORT datab (549:549:549) (629:629:629)) - (PORT datac (556:556:556) (622:622:622)) - (PORT datad (457:457:457) (530:530:530)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~8) - (DELAY - (ABSOLUTE - (PORT dataa (309:309:309) (364:364:364)) - (PORT datab (614:614:614) (707:707:707)) - (PORT datac (522:522:522) (612:612:612)) - (PORT datad (447:447:447) (512:512:512)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~9) - (DELAY - (ABSOLUTE - (PORT dataa (280:280:280) (323:323:323)) - (PORT datab (193:193:193) (232:232:232)) - (PORT datac (438:438:438) (506:506:506)) - (PORT datad (337:337:337) (397:397:397)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (776:776:776) (851:851:851)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (119:119:119) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (776:776:776) (851:851:851)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (122:122:122) (159:159:159)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (761:761:761) (826:826:826)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (911:911:911)) - (PORT asdata (298:298:298) (339:339:339)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (761:761:761) (826:826:826)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|iorq\~0) - (DELAY - (ABSOLUTE - (PORT datab (134:134:134) (184:184:184)) - (PORT datad (121:121:121) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (138:138:138) (191:191:191)) - (PORT datad (425:425:425) (480:480:480)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (426:426:426)) - (PORT datab (464:464:464) (534:534:534)) - (PORT datac (337:337:337) (397:397:397)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~57) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (977:977:977)) - (PORT datab (507:507:507) (606:606:606)) - (PORT datac (508:508:508) (595:595:595)) - (PORT datad (468:468:468) (536:536:536)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (137:137:137)) - (PORT datab (285:285:285) (329:329:329)) - (PORT datac (471:471:471) (549:549:549)) - (PORT datad (291:291:291) (333:333:333)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (797:797:797)) - (PORT datab (331:331:331) (392:392:392)) - (PORT datac (497:497:497) (589:589:589)) - (PORT datad (423:423:423) (483:483:483)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (738:738:738)) - (PORT datab (223:223:223) (267:267:267)) - (PORT datac (943:943:943) (1097:1097:1097)) - (PORT datad (654:654:654) (738:738:738)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (403:403:403)) - (PORT datab (349:349:349) (415:415:415)) - (PORT datad (1003:1003:1003) (1117:1117:1117)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~40) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (747:747:747)) - (PORT datab (768:768:768) (904:904:904)) - (PORT datac (606:606:606) (689:689:689)) - (PORT datad (783:783:783) (918:918:918)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~39) - (DELAY - (ABSOLUTE - (PORT dataa (976:976:976) (1109:1109:1109)) - (PORT datab (479:479:479) (559:559:559)) - (PORT datac (519:519:519) (621:621:621)) - (PORT datad (643:643:643) (768:768:768)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (796:796:796)) - (PORT datab (451:451:451) (518:518:518)) - (PORT datac (520:520:520) (622:622:622)) - (PORT datad (345:345:345) (398:398:398)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (668:668:668)) - (PORT datab (464:464:464) (534:534:534)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~4) - (DELAY - (ABSOLUTE - (PORT datab (358:358:358) (423:423:423)) - (PORT datac (434:434:434) (503:503:503)) - (PORT datad (313:313:313) (366:366:366)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (831:831:831)) - (PORT datab (530:530:530) (619:619:619)) - (PORT datac (108:108:108) (132:132:132)) - (PORT datad (119:119:119) (142:142:142)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (353:353:353) (414:414:414)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (903:903:903)) - (PORT ena (764:764:764) (831:831:831)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (188:188:188) (231:231:231)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (761:761:761) (826:826:826)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (911:911:911)) - (PORT asdata (304:304:304) (348:348:348)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (761:761:761) (826:826:826)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (140:140:140) (193:193:193)) - (PORT datac (116:116:116) (157:157:157)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (911:911:911)) - (PORT asdata (979:979:979) (1089:1089:1089)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (761:761:761) (826:826:826)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) - (DELAY - (ABSOLUTE - (PORT datad (120:120:120) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (761:761:761) (826:826:826)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (300:300:300) (342:342:342)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (776:776:776) (851:851:851)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE (PORT dataa (136:136:136) (189:189:189)) - (PORT datab (496:496:496) (579:579:579)) - (PORT datad (380:380:380) (453:453:453)) + (PORT datad (334:334:334) (390:390:390)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (320:320:320) (371:371:371)) - (PORT datad (108:108:108) (127:127:127)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (1144:1144:1144) (1300:1300:1300)) - (PORT datab (841:841:841) (991:991:991)) - (PORT datac (1761:1761:1761) (2066:2066:2066)) - (PORT datad (1368:1368:1368) (1588:1588:1588)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (977:977:977) (1136:1136:1136)) + (PORT datab (898:898:898) (1063:1063:1063)) + (PORT datac (658:658:658) (774:774:774)) + (PORT datad (680:680:680) (795:795:795)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (905:905:905) (910:910:910)) - (PORT asdata (904:904:904) (1010:1010:1010)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (118:118:118) (155:155:155)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (905:905:905) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ExtRamWE\~0) (DELAY (ABSOLUTE - (PORT dataa (1440:1440:1440) (1667:1667:1667)) - (PORT datab (1766:1766:1766) (2072:2072:2072)) - (PORT datac (966:966:966) (1095:1095:1095)) - (PORT datad (979:979:979) (1139:1139:1139)) + (PORT dataa (976:976:976) (1134:1134:1134)) + (PORT datab (898:898:898) (1064:1064:1064)) + (PORT datac (659:659:659) (775:775:775)) + (PORT datad (679:679:679) (794:794:794)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (1095:1095:1095)) + (PORT datab (451:451:451) (522:522:522)) + (PORT datad (171:171:171) (201:201:201)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (616:616:616)) + (PORT datab (539:539:539) (651:651:651)) + (PORT datac (1077:1077:1077) (1266:1266:1266)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (1117:1117:1117)) + (PORT datab (543:543:543) (633:633:633)) + (PORT datac (535:535:535) (624:624:624)) + (PORT datad (683:683:683) (785:785:785)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (615:615:615)) + (PORT datab (540:540:540) (651:651:651)) + (PORT datac (1077:1077:1077) (1266:1266:1266)) + (PORT datad (341:341:341) (400:400:400)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (319:319:319) (365:365:365)) + (PORT sload (583:583:583) (639:639:639)) + (PORT ena (599:599:599) (635:635:635)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (755:755:755)) + (PORT datad (1152:1152:1152) (1332:1332:1332)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1094:1094:1094)) + (PORT datab (115:115:115) (142:142:142)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (313:313:313) (356:356:356)) + (PORT sload (583:583:583) (639:639:639)) + (PORT ena (599:599:599) (635:635:635)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (1165:1165:1165) (1354:1354:1354)) + (PORT datad (628:628:628) (735:735:735)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (1097:1097:1097)) + (PORT datab (173:173:173) (212:212:212)) + (PORT datad (282:282:282) (323:323:323)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (305:305:305) (349:349:349)) + (PORT sload (583:583:583) (639:639:639)) + (PORT ena (599:599:599) (635:635:635)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (915:915:915) (1073:1073:1073)) + (PORT datac (840:840:840) (974:974:974)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (146:146:146) (189:189:189)) - (PORT datab (127:127:127) (165:165:165)) - (PORT datac (124:124:124) (157:157:157)) - (PORT datad (649:649:649) (746:746:746)) + (PORT dataa (368:368:368) (445:445:445)) + (PORT datab (139:139:139) (177:177:177)) + (PORT datac (191:191:191) (232:232:232)) + (PORT datad (702:702:702) (789:789:789)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -31973,11 +29829,23 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (1767:1767:1767) (2074:2074:2074)) - (PORT datac (834:834:834) (967:967:967)) - (PORT datad (808:808:808) (951:951:951)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (1159:1159:1159) (1347:1347:1347)) + (PORT datac (617:617:617) (726:726:726)) + (PORT datad (626:626:626) (733:733:733)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (592:592:592)) + (PORT datad (1119:1119:1119) (1292:1292:1292)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -31987,9 +29855,9 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (956:956:956) (1124:1124:1124)) - (PORT datab (505:505:505) (596:596:596)) - (PORT datad (93:93:93) (112:112:112)) + (PORT dataa (459:459:459) (534:534:534)) + (PORT datab (189:189:189) (226:226:226)) + (PORT datad (173:173:173) (195:195:195)) (IOPATH dataa combout (172:172:172) (165:165:165)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -32001,11 +29869,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (907:907:907)) + (PORT clk (931:931:931) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (659:659:659) (745:745:745)) - (PORT sload (953:953:953) (1073:1073:1073)) - (PORT ena (900:900:900) (990:990:990)) + (PORT asdata (586:586:586) (648:648:648)) + (PORT sload (640:640:640) (715:715:715)) + (PORT ena (763:763:763) (829:829:829)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -32021,9 +29889,9 @@ (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) (DELAY (ABSOLUTE - (PORT datac (598:598:598) (726:726:726)) - (PORT datad (1886:1886:1886) (2193:2193:2193)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (1006:1006:1006) (1180:1180:1180)) + (PORT datad (359:359:359) (438:438:438)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -32033,11 +29901,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (320:320:320) (377:377:377)) - (PORT datab (859:859:859) (1020:1020:1020)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) + (PORT dataa (461:461:461) (536:536:536)) + (PORT datab (316:316:316) (363:363:363)) + (PORT datad (277:277:277) (315:315:315)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -32047,11 +29915,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (902:902:902)) + (PORT clk (931:931:931) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (647:647:647) (739:739:739)) - (PORT sload (1014:1014:1014) (1133:1133:1133)) - (PORT ena (1029:1029:1029) (1122:1122:1122)) + (PORT asdata (518:518:518) (582:582:582)) + (PORT sload (640:640:640) (715:715:715)) + (PORT ena (763:763:763) (829:829:829)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -32067,8 +29935,8 @@ (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) (DELAY (ABSOLUTE - (PORT datac (1714:1714:1714) (1991:1991:1991)) - (PORT datad (611:611:611) (715:715:715)) + (PORT datac (980:980:980) (1153:1153:1153)) + (PORT datad (345:345:345) (415:415:415)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -32079,11 +29947,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (853:853:853) (1013:1013:1013)) - (PORT datad (429:429:429) (492:492:492)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) + (PORT dataa (465:465:465) (541:541:541)) + (PORT datab (276:276:276) (318:318:318)) + (PORT datad (171:171:171) (203:203:203)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -32093,11 +29961,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (902:902:902)) + (PORT clk (931:931:931) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (371:371:371) (424:424:424)) - (PORT sload (1014:1014:1014) (1133:1133:1133)) - (PORT ena (1029:1029:1029) (1122:1122:1122)) + (PORT asdata (390:390:390) (439:439:439)) + (PORT sload (640:640:640) (715:715:715)) + (PORT ena (763:763:763) (829:829:829)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -32113,9 +29981,9 @@ (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) (DELAY (ABSOLUTE - (PORT datab (1400:1400:1400) (1644:1644:1644)) - (PORT datad (770:770:770) (900:900:900)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datac (986:986:986) (1159:1159:1159)) + (PORT datad (193:193:193) (241:241:241)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -32125,11 +29993,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) (DELAY (ABSOLUTE - (PORT dataa (354:354:354) (412:412:412)) - (PORT datab (116:116:116) (144:144:144)) - (PORT datad (933:933:933) (1096:1096:1096)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (459:459:459) (533:533:533)) + (PORT datab (278:278:278) (323:323:323)) + (PORT datad (172:172:172) (204:204:204)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -32139,11 +30007,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (907:907:907)) + (PORT clk (931:931:931) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (678:678:678) (795:795:795)) - (PORT sload (953:953:953) (1073:1073:1073)) - (PORT ena (900:900:900) (990:990:990)) + (PORT asdata (516:516:516) (572:572:572)) + (PORT sload (640:640:640) (715:715:715)) + (PORT ena (763:763:763) (829:829:829)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -32159,9 +30027,9 @@ (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) (DELAY (ABSOLUTE - (PORT datac (851:851:851) (1002:1002:1002)) - (PORT datad (1372:1372:1372) (1609:1609:1609)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datac (989:989:989) (1163:1163:1163)) + (PORT datad (350:350:350) (423:423:423)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -32171,11 +30039,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) (DELAY (ABSOLUTE - (PORT dataa (483:483:483) (554:554:554)) - (PORT datab (325:325:325) (384:384:384)) - (PORT datad (793:793:793) (926:926:926)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (737:737:737) (848:848:848)) + (PORT datab (173:173:173) (212:212:212)) + (PORT datad (104:104:104) (122:122:122)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -32185,11 +30053,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (907:907:907)) + (PORT clk (918:918:918) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (547:547:547) (626:626:626)) - (PORT sload (843:843:843) (936:936:936)) - (PORT ena (1056:1056:1056) (1163:1163:1163)) + (PORT asdata (522:522:522) (598:598:598)) + (PORT sload (591:591:591) (660:660:660)) + (PORT ena (606:606:606) (650:650:650)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -32205,10 +30073,10 @@ (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) (DELAY (ABSOLUTE - (PORT dataa (142:142:142) (191:191:191)) - (PORT datad (1886:1886:1886) (2194:2194:2194)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datab (1121:1121:1121) (1302:1302:1302)) + (PORT datac (365:365:365) (442:442:442)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) @@ -32217,11 +30085,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) (DELAY (ABSOLUTE - (PORT dataa (956:956:956) (1123:1123:1123)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datad (316:316:316) (366:366:366)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datad (723:723:723) (822:822:822)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -32231,11 +30099,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (907:907:907)) + (PORT clk (918:918:918) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (498:498:498) (566:566:566)) - (PORT sload (953:953:953) (1073:1073:1073)) - (PORT ena (900:900:900) (990:990:990)) + (PORT asdata (601:601:601) (673:673:673)) + (PORT sload (591:591:591) (660:660:660)) + (PORT ena (606:606:606) (650:650:650)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -32251,10 +30119,10 @@ (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) (DELAY (ABSOLUTE - (PORT datac (693:693:693) (825:825:825)) - (PORT datad (1906:1906:1906) (2220:2220:2220)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datab (385:385:385) (466:466:466)) + (PORT datac (980:980:980) (1152:1152:1152)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -32263,11 +30131,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) (DELAY (ABSOLUTE - (PORT dataa (344:344:344) (406:406:406)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datad (793:793:793) (927:927:927)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (740:740:740) (852:852:852)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -32277,11 +30145,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (907:907:907)) + (PORT clk (918:918:918) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (667:667:667) (752:752:752)) - (PORT sload (843:843:843) (936:936:936)) - (PORT ena (1056:1056:1056) (1163:1163:1163)) + (PORT asdata (866:866:866) (977:977:977)) + (PORT sload (591:591:591) (660:660:660)) + (PORT ena (606:606:606) (650:650:650)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -32297,612 +30165,249 @@ (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) (DELAY (ABSOLUTE - (PORT datab (1901:1901:1901) (2224:2224:2224)) - (PORT datad (681:681:681) (803:803:803)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1297:1297:1297) (1485:1485:1485)) - (PORT clk (1096:1096:1096) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1616:1616:1616) (1873:1873:1873)) - (PORT d[1] (963:963:963) (1140:1140:1140)) - (PORT d[2] (1661:1661:1661) (1935:1935:1935)) - (PORT d[3] (1358:1358:1358) (1610:1610:1610)) - (PORT d[4] (1279:1279:1279) (1497:1497:1497)) - (PORT d[5] (1594:1594:1594) (1860:1860:1860)) - (PORT d[6] (977:977:977) (1128:1128:1128)) - (PORT d[7] (2356:2356:2356) (2706:2706:2706)) - (PORT d[8] (1392:1392:1392) (1614:1614:1614)) - (PORT d[9] (1623:1623:1623) (1854:1854:1854)) - (PORT d[10] (1047:1047:1047) (1233:1233:1233)) - (PORT d[11] (1086:1086:1086) (1277:1277:1277)) - (PORT d[12] (1966:1966:1966) (2242:2242:2242)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1552:1552:1552) (1714:1714:1714)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (PORT d[0] (1599:1599:1599) (1761:1761:1761)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT asdata (639:639:639) (709:709:709)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT asdata (294:294:294) (333:333:333)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (184:184:184)) - (PORT datab (131:131:131) (168:168:168)) - (PORT datac (126:126:126) (160:160:160)) - (PORT datad (647:647:647) (744:744:744)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1769:1769:1769) (2076:2076:2076)) - (PORT datac (836:836:836) (969:969:969)) - (PORT datad (807:807:807) (949:949:949)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (981:981:981) (1154:1154:1154)) + (PORT datad (513:513:513) (600:600:600)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) (DELAY (ABSOLUTE - (PORT d[0] (794:794:794) (911:911:911)) - (PORT clk (1084:1084:1084) (1102:1102:1102)) + (PORT dataa (176:176:176) (217:217:217)) + (PORT datab (737:737:737) (840:840:840)) + (PORT datad (104:104:104) (122:122:122)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (316:316:316) (360:360:360)) + (PORT sload (591:591:591) (660:660:660)) + (PORT ena (606:606:606) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1283:1283:1283) (1494:1494:1494)) - (PORT d[1] (1400:1400:1400) (1637:1637:1637)) - (PORT d[2] (1208:1208:1208) (1434:1434:1434)) - (PORT d[3] (2302:2302:2302) (2705:2705:2705)) - (PORT d[4] (1059:1059:1059) (1249:1249:1249)) - (PORT d[5] (2501:2501:2501) (2898:2898:2898)) - (PORT d[6] (1276:1276:1276) (1474:1474:1474)) - (PORT d[7] (1408:1408:1408) (1609:1609:1609)) - (PORT d[8] (1949:1949:1949) (2253:2253:2253)) - (PORT d[9] (1440:1440:1440) (1641:1641:1641)) - (PORT d[10] (903:903:903) (1057:1057:1057)) - (PORT d[11] (1569:1569:1569) (1812:1812:1812)) - (PORT d[12] (1061:1061:1061) (1209:1209:1209)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1199:1199:1199) (1328:1328:1328)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1084:1084:1084) (1102:1102:1102)) - (PORT d[0] (1613:1613:1613) (1785:1785:1785)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1064:1064:1064) (1081:1081:1081)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (604:604:604) (613:613:613)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) + (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) (DELAY (ABSOLUTE - (PORT dataa (192:192:192) (263:263:263)) - (PORT datab (707:707:707) (817:817:817)) - (PORT datac (640:640:640) (761:761:761)) - (PORT datad (501:501:501) (565:565:565)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (508:508:508) (604:604:604)) + (PORT datad (1141:1141:1141) (1320:1320:1320)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (142:142:142) (182:182:182)) - (PORT datab (131:131:131) (169:169:169)) - (PORT datac (127:127:127) (161:161:161)) - (PORT datad (646:646:646) (743:743:743)) + (PORT dataa (757:757:757) (876:876:876)) + (PORT datab (115:115:115) (142:142:142)) + (PORT datad (284:284:284) (327:327:327)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (314:314:314) (361:361:361)) + (PORT sload (575:575:575) (630:630:630)) + (PORT ena (419:419:419) (435:435:435)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) + (DELAY + (ABSOLUTE + (PORT datac (988:988:988) (1162:1162:1162)) + (PORT datad (372:372:372) (453:453:453)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (294:294:294) (342:342:342)) + (PORT datad (745:745:745) (852:852:852)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (307:307:307) (354:354:354)) + (PORT sload (575:575:575) (630:630:630)) + (PORT ena (419:419:419) (435:435:435)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) + (DELAY + (ABSOLUTE + (PORT datac (495:495:495) (592:592:592)) + (PORT datad (829:829:829) (968:968:968)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (145:145:145)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (741:741:741) (848:848:848)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (477:477:477) (537:537:537)) + (PORT sload (575:575:575) (630:630:630)) + (PORT ena (419:419:419) (435:435:435)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (606:606:606)) + (PORT datad (831:831:831) (970:970:970)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (215:215:215)) + (PORT datab (435:435:435) (497:497:497)) + (PORT datad (841:841:841) (952:952:952)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (307:307:307) (353:353:353)) + (PORT sload (583:583:583) (639:639:639)) + (PORT ena (599:599:599) (635:635:635)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1176:1176:1176)) + (PORT datad (472:472:472) (553:553:553)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1770:1770:1770) (2077:2077:2077)) - (PORT datac (837:837:837) (971:971:971)) - (PORT datad (805:805:805) (947:947:947)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (945:945:945) (1073:1073:1073)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1130:1130:1130) (1322:1322:1322)) - (PORT d[1] (1423:1423:1423) (1669:1669:1669)) - (PORT d[2] (1213:1213:1213) (1433:1433:1433)) - (PORT d[3] (2298:2298:2298) (2697:2697:2697)) - (PORT d[4] (1078:1078:1078) (1272:1272:1272)) - (PORT d[5] (2687:2687:2687) (3115:3115:3115)) - (PORT d[6] (1106:1106:1106) (1280:1280:1280)) - (PORT d[7] (1245:1245:1245) (1427:1427:1427)) - (PORT d[8] (1955:1955:1955) (2264:2264:2264)) - (PORT d[9] (1462:1462:1462) (1671:1671:1671)) - (PORT d[10] (1302:1302:1302) (1537:1537:1537)) - (PORT d[11] (1409:1409:1409) (1630:1630:1630)) - (PORT d[12] (895:895:895) (1017:1017:1017)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1288:1288:1288) (1421:1421:1421)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (PORT d[0] (1443:1443:1443) (1578:1578:1578)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1070:1070:1070) (1086:1086:1086)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (147:147:147) (189:189:189)) - (PORT datab (125:125:125) (163:163:163)) - (PORT datac (123:123:123) (156:156:156)) - (PORT datad (649:649:649) (746:746:746)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1770:1770:1770) (2077:2077:2077)) - (PORT datac (837:837:837) (970:970:970)) - (PORT datad (806:806:806) (948:948:948)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (961:961:961) (1097:1097:1097)) + (PORT d[0] (565:565:565) (645:645:645)) (PORT clk (1094:1094:1094) (1111:1111:1111)) ) ) @@ -32912,22 +30417,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1112:1112:1112) (1301:1301:1301)) - (PORT d[1] (1567:1567:1567) (1830:1830:1830)) - (PORT d[2] (1241:1241:1241) (1468:1468:1468)) - (PORT d[3] (844:844:844) (985:985:985)) - (PORT d[4] (1249:1249:1249) (1465:1465:1465)) - (PORT d[5] (2693:2693:2693) (3119:3119:3119)) - (PORT d[6] (1267:1267:1267) (1463:1463:1463)) - (PORT d[7] (1226:1226:1226) (1404:1404:1404)) - (PORT d[8] (1775:1775:1775) (2055:2055:2055)) - (PORT d[9] (1652:1652:1652) (1891:1891:1891)) - (PORT d[10] (1271:1271:1271) (1499:1499:1499)) - (PORT d[11] (1390:1390:1390) (1612:1612:1612)) - (PORT d[12] (874:874:874) (995:995:995)) + (PORT d[0] (568:568:568) (645:645:645)) + (PORT d[1] (1218:1218:1218) (1443:1443:1443)) + (PORT d[2] (828:828:828) (946:946:946)) + (PORT d[3] (1657:1657:1657) (1939:1939:1939)) + (PORT d[4] (1525:1525:1525) (1792:1792:1792)) + (PORT d[5] (1840:1840:1840) (2134:2134:2134)) + (PORT d[6] (790:790:790) (920:920:920)) + (PORT d[7] (1703:1703:1703) (1928:1928:1928)) + (PORT d[8] (558:558:558) (640:640:640)) + (PORT d[9] (903:903:903) (1044:1044:1044)) + (PORT d[10] (932:932:932) (1066:1066:1066)) + (PORT d[11] (1275:1275:1275) (1489:1489:1489)) + (PORT d[12] (927:927:927) (1071:1071:1071)) (PORT clk (1092:1092:1092) (1109:1109:1109)) ) ) @@ -32937,10 +30442,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (941:941:941) (1028:1028:1028)) + (PORT d[0] (528:528:528) (555:555:555)) (PORT clk (1092:1092:1092) (1109:1109:1109)) ) ) @@ -32950,17 +30455,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (1807:1807:1807) (1963:1963:1963)) + (PORT d[0] (804:804:804) (836:836:836)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1095:1095:1095) (1112:1112:1112)) @@ -32970,7 +30475,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1095:1095:1095) (1112:1112:1112)) @@ -32980,7 +30485,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1095:1095:1095) (1112:1112:1112)) @@ -32990,7 +30495,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1095:1095:1095) (1112:1112:1112)) @@ -33000,7 +30505,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1074:1074:1074) (1090:1090:1090)) @@ -33014,7 +30519,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (614:614:614) (622:622:622)) @@ -33023,7 +30528,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE (PORT clk (615:615:615) (623:623:623)) @@ -33032,7 +30537,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (615:615:615) (623:623:623)) @@ -33042,7 +30547,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (615:615:615) (623:623:623)) @@ -33050,722 +30555,13 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (699:699:699) (801:801:801)) - (PORT datac (635:635:635) (754:754:754)) - (PORT datad (681:681:681) (788:788:788)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (146:146:146) (188:188:188)) - (PORT datab (128:128:128) (167:167:167)) - (PORT datac (124:124:124) (158:158:158)) - (PORT datad (648:648:648) (745:745:745)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE CLOCK_50\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (91:91:91) (78:78:78)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\~0) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (760:760:760)) - (PORT datab (801:801:801) (934:934:934)) - (PORT datac (639:639:639) (747:747:747)) - (PORT datad (472:472:472) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[0\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT asdata (683:683:683) (768:768:768)) - (PORT ena (479:479:479) (508:508:508)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT asdata (681:681:681) (761:761:761)) - (PORT ena (479:479:479) (508:508:508)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT datad (525:525:525) (612:612:612)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (479:479:479) (508:508:508)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~0) - (DELAY - (ABSOLUTE - (PORT datac (537:537:537) (641:641:641)) - (PORT datad (525:525:525) (613:613:613)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (479:479:479) (508:508:508)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (625:625:625)) - (PORT datac (532:532:532) (635:635:635)) - (PORT datad (522:522:522) (608:608:608)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (479:479:479) (508:508:508)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (521:521:521) (618:618:618)) - (PORT datab (374:374:374) (455:455:455)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~2) - (DELAY - (ABSOLUTE - (PORT datab (391:391:391) (475:475:475)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~4) - (DELAY - (ABSOLUTE - (PORT datab (632:632:632) (734:734:734)) - (IOPATH datab combout (188:188:188) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~6) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (594:594:594)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (479:479:479) (508:508:508)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~8) - (DELAY - (ABSOLUTE - (PORT datab (392:392:392) (475:475:475)) - (IOPATH datab combout (188:188:188) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (479:479:479) (508:508:508)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~10) - (DELAY - (ABSOLUTE - (PORT dataa (491:491:491) (576:576:576)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (479:479:479) (508:508:508)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~12) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (467:467:467)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector6\~0) - (DELAY - (ABSOLUTE - (PORT datab (681:681:681) (804:804:804)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[9\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (753:753:753)) - (PORT datab (801:801:801) (934:934:934)) - (PORT datac (645:645:645) (753:753:753)) - (PORT datad (465:465:465) (547:547:547)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (494:494:494) (532:532:532)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~14) - (DELAY - (ABSOLUTE - (PORT datad (481:481:481) (558:558:558)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT datab (681:681:681) (804:804:804)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (494:494:494) (532:532:532)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (544:544:544) (651:651:651)) - (PORT datab (380:380:380) (463:463:463)) - (PORT datac (672:672:672) (784:784:784)) - (PORT datad (369:369:369) (446:446:446)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (491:491:491) (562:562:562)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datad (371:371:371) (447:447:447)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (922:922:922) (926:926:926)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector3\~0) - (DELAY - (ABSOLUTE - (PORT datac (663:663:663) (779:779:779)) - (PORT datad (96:96:96) (115:115:115)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (494:494:494) (532:532:532)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector2\~0) - (DELAY - (ABSOLUTE - (PORT datab (679:679:679) (801:801:801)) - (PORT datac (95:95:95) (119:119:119)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (494:494:494) (532:532:532)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (800:800:800) (906:906:906)) - (PORT clk (1096:1096:1096) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (634:634:634) (745:745:745)) - (PORT d[1] (966:966:966) (1135:1135:1135)) - (PORT d[2] (2339:2339:2339) (2737:2737:2737)) - (PORT d[3] (1955:1955:1955) (2304:2304:2304)) - (PORT d[4] (1245:1245:1245) (1456:1456:1456)) - (PORT d[5] (733:733:733) (849:849:849)) - (PORT d[6] (642:642:642) (731:731:731)) - (PORT d[7] (1368:1368:1368) (1600:1600:1600)) - (PORT d[8] (746:746:746) (855:855:855)) - (PORT d[9] (2668:2668:2668) (3024:3024:3024)) - (PORT d[10] (772:772:772) (896:896:896)) - (PORT d[11] (2208:2208:2208) (2561:2561:2561)) - (PORT d[12] (1394:1394:1394) (1590:1590:1590)) - (PORT clk (1094:1094:1094) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (684:684:684) (724:724:724)) - (PORT clk (1094:1094:1094) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1112:1112:1112)) - (PORT d[0] (1288:1288:1288) (1389:1389:1389)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1051:1051:1051) (1069:1069:1069)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1589:1589:1589) (1795:1795:1795)) - (PORT clk (1056:1056:1056) (1072:1072:1072)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1073:1073:1073) (1246:1246:1246)) - (PORT d[1] (1049:1049:1049) (1218:1218:1218)) - (PORT d[2] (1074:1074:1074) (1241:1241:1241)) - (PORT d[3] (1066:1066:1066) (1227:1227:1227)) - (PORT d[4] (1093:1093:1093) (1259:1259:1259)) - (PORT d[5] (1019:1019:1019) (1175:1175:1175)) - (PORT d[6] (1032:1032:1032) (1204:1204:1204)) - (PORT d[7] (1090:1090:1090) (1283:1283:1283)) - (PORT d[8] (1109:1109:1109) (1292:1292:1292)) - (PORT d[9] (1111:1111:1111) (1280:1280:1280)) - (PORT d[10] (1054:1054:1054) (1234:1234:1234)) - (PORT d[11] (1118:1118:1118) (1287:1287:1287)) - (PORT d[12] (1058:1058:1058) (1216:1216:1216)) - (PORT clk (1053:1053:1053) (1071:1071:1071)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1072:1072:1072)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1073:1073:1073)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) - (PORT asdata (641:641:641) (712:712:712)) + (PORT clk (1110:1110:1110) (1139:1139:1139)) + (PORT asdata (1127:1127:1127) (1272:1272:1272)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -33775,11 +30571,11 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (660:660:660) (741:741:741)) + (PORT clk (912:912:912) (917:917:917)) + (PORT asdata (755:755:755) (842:842:842)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -33787,713 +30583,17 @@ (HOLD asdata (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1606:1606:1606) (1846:1846:1846)) - (PORT d[1] (897:897:897) (1037:1037:1037)) - (PORT d[2] (1714:1714:1714) (2020:2020:2020)) - (PORT d[3] (1509:1509:1509) (1770:1770:1770)) - (PORT d[4] (1311:1311:1311) (1547:1547:1547)) - (PORT d[5] (1271:1271:1271) (1449:1449:1449)) - (PORT d[6] (1359:1359:1359) (1575:1575:1575)) - (PORT d[7] (2912:2912:2912) (3311:3311:3311)) - (PORT d[8] (1714:1714:1714) (1997:1997:1997)) - (PORT d[9] (1862:1862:1862) (2116:2116:2116)) - (PORT d[10] (1465:1465:1465) (1724:1724:1724)) - (PORT d[11] (1431:1431:1431) (1679:1679:1679)) - (PORT d[12] (2104:2104:2104) (2403:2403:2403)) - (PORT clk (1106:1106:1106) (1123:1123:1123)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1123:1123:1123)) - (PORT d[0] (1142:1142:1142) (1267:1267:1267)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1124:1124:1124)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1104:1104:1104)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (628:628:628) (636:636:636)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (629:629:629) (637:637:637)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (629:629:629) (637:637:637)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (629:629:629) (637:637:637)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (427:427:427) (498:498:498)) - (PORT d[1] (1797:1797:1797) (2117:2117:2117)) - (PORT d[2] (1281:1281:1281) (1488:1488:1488)) - (PORT d[3] (577:577:577) (672:672:672)) - (PORT d[4] (1788:1788:1788) (2086:2086:2086)) - (PORT d[5] (532:532:532) (616:616:616)) - (PORT d[6] (1635:1635:1635) (1881:1881:1881)) - (PORT d[7] (1483:1483:1483) (1727:1727:1727)) - (PORT d[8] (2323:2323:2323) (2684:2684:2684)) - (PORT d[9] (1713:1713:1713) (1944:1944:1944)) - (PORT d[10] (1676:1676:1676) (1948:1948:1948)) - (PORT d[11] (1297:1297:1297) (1521:1521:1521)) - (PORT d[12] (1200:1200:1200) (1368:1368:1368)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (PORT d[0] (1469:1469:1469) (1317:1317:1317)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1070:1070:1070) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (145:145:145) (187:187:187)) - (PORT datab (129:129:129) (167:167:167)) - (PORT datac (125:125:125) (159:159:159)) - (PORT datad (648:648:648) (745:745:745)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1023:1023:1023) (1172:1172:1172)) - (PORT clk (1104:1104:1104) (1120:1120:1120)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1459:1459:1459) (1682:1682:1682)) - (PORT d[1] (766:766:766) (901:901:901)) - (PORT d[2] (1821:1821:1821) (2153:2153:2153)) - (PORT d[3] (1559:1559:1559) (1846:1846:1846)) - (PORT d[4] (1473:1473:1473) (1731:1731:1731)) - (PORT d[5] (1210:1210:1210) (1380:1380:1380)) - (PORT d[6] (1172:1172:1172) (1366:1366:1366)) - (PORT d[7] (1534:1534:1534) (1791:1791:1791)) - (PORT d[8] (1204:1204:1204) (1379:1379:1379)) - (PORT d[9] (2134:2134:2134) (2420:2420:2420)) - (PORT d[10] (1269:1269:1269) (1501:1501:1501)) - (PORT d[11] (1768:1768:1768) (2056:2056:2056)) - (PORT d[12] (1957:1957:1957) (2238:2238:2238)) - (PORT clk (1102:1102:1102) (1118:1118:1118)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1147:1147:1147) (1250:1250:1250)) - (PORT clk (1102:1102:1102) (1118:1118:1118)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1104:1104:1104) (1120:1120:1120)) - (PORT d[0] (1928:1928:1928) (1800:1800:1800)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1059:1059:1059) (1077:1077:1077)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2134:2134:2134) (2416:2416:2416)) - (PORT clk (1064:1064:1064) (1080:1080:1080)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1077:1077:1077) (1252:1252:1252)) - (PORT d[1] (1119:1119:1119) (1313:1313:1313)) - (PORT d[2] (1008:1008:1008) (1174:1174:1174)) - (PORT d[3] (1101:1101:1101) (1300:1300:1300)) - (PORT d[4] (1032:1032:1032) (1190:1190:1190)) - (PORT d[5] (1232:1232:1232) (1431:1431:1431)) - (PORT d[6] (1112:1112:1112) (1278:1278:1278)) - (PORT d[7] (1095:1095:1095) (1260:1260:1260)) - (PORT d[8] (1157:1157:1157) (1334:1334:1334)) - (PORT d[9] (1053:1053:1053) (1215:1215:1215)) - (PORT d[10] (1195:1195:1195) (1393:1393:1393)) - (PORT d[11] (1123:1123:1123) (1294:1294:1294)) - (PORT d[12] (1071:1071:1071) (1232:1232:1232)) - (PORT clk (1061:1061:1061) (1079:1079:1079)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1064:1064:1064) (1080:1080:1080)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (762:762:762)) - (PORT datab (160:160:160) (214:214:214)) - (PORT datac (507:507:507) (570:570:570)) - (PORT datad (889:889:889) (1021:1021:1021)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (795:795:795)) - (PORT datab (162:162:162) (218:218:218)) - (PORT datac (863:863:863) (997:997:997)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (526:526:526) (608:608:608)) - (PORT datab (535:535:535) (619:619:619)) - (PORT datac (572:572:572) (646:646:646)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1023:1023:1023) (1202:1202:1202)) - (PORT datab (1204:1204:1204) (1412:1412:1412)) - (PORT datac (1886:1886:1886) (2195:2195:2195)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (469:469:469)) - (PORT datab (175:175:175) (213:213:213)) - (PORT datac (370:370:370) (440:440:440)) - (PORT datad (474:474:474) (542:542:542)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (457:457:457)) - (PORT datab (657:657:657) (783:783:783)) - (PORT datac (200:200:200) (245:245:245)) - (PORT datad (325:325:325) (377:377:377)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (861:861:861)) - (PORT datab (686:686:686) (816:816:816)) - (PORT datac (440:440:440) (502:502:502)) - (PORT datad (291:291:291) (338:338:338)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (725:725:725)) - (PORT datab (572:572:572) (676:676:676)) - (PORT datac (646:646:646) (768:768:768)) - (PORT datad (571:571:571) (654:654:654)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (483:483:483)) - (PORT datab (570:570:570) (674:674:674)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (546:546:546) (629:629:629)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (928:928:928) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (896:896:896) (984:984:984)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (790:790:790)) - (PORT datac (617:617:617) (722:722:722)) - (PORT datad (543:543:543) (626:626:626)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (1011:1011:1011)) - (PORT datab (551:551:551) (633:633:633)) - (PORT datac (415:415:415) (498:498:498)) - (PORT datad (379:379:379) (445:445:445)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (724:724:724)) - (PORT datab (402:402:402) (460:460:460)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (679:679:679) (803:803:803)) + (PORT dataa (369:369:369) (445:445:445)) + (PORT datab (140:140:140) (179:179:179)) + (PORT datac (192:192:192) (233:233:233)) + (PORT datad (702:702:702) (789:789:789)) (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (362:362:362)) - (PORT datac (403:403:403) (463:463:463)) - (PORT datad (101:101:101) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (508:508:508) (590:590:590)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (326:326:326) (392:392:392)) - (PORT datad (338:338:338) (402:402:402)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (446:446:446)) - (PORT datab (597:597:597) (682:682:682)) - (PORT datac (319:319:319) (374:374:374)) - (PORT datad (555:555:555) (631:631:631)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (896:896:896)) - (PORT ena (996:996:996) (1096:1096:1096)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (924:924:924)) - (PORT datab (817:817:817) (919:919:919)) - (PORT datac (691:691:691) (780:780:780)) - (PORT datad (748:748:748) (875:875:875)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -34501,505 +30601,24 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (196:196:196) (235:235:235)) - (PORT datab (645:645:645) (756:756:756)) - (PORT datac (505:505:505) (603:603:603)) - (PORT datad (841:841:841) (975:975:975)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT datac (158:158:158) (215:215:215)) - (PORT datad (160:160:160) (212:212:212)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (268:268:268)) - (PORT datab (749:749:749) (869:869:869)) - (PORT datac (750:750:750) (878:878:878)) - (PORT datad (1149:1149:1149) (1318:1318:1318)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (707:707:707)) - (PORT datab (506:506:506) (596:596:596)) - (PORT datac (1119:1119:1119) (1288:1288:1288)) - (PORT datad (666:666:666) (764:764:764)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (682:682:682)) - (PORT datab (476:476:476) (549:549:549)) - (PORT datac (691:691:691) (780:780:780)) - (PORT datad (184:184:184) (210:210:210)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (758:758:758) (896:896:896)) - (PORT datab (722:722:722) (829:829:829)) - (PORT datac (159:159:159) (217:217:217)) - (PORT datad (162:162:162) (214:214:214)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datab (1160:1160:1160) (1348:1348:1348)) + (PORT datac (618:618:618) (727:727:727)) + (PORT datad (626:626:626) (733:733:733)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (824:824:824)) - (PORT datac (405:405:405) (488:488:488)) - (PORT datad (448:448:448) (519:519:519)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (284:284:284) (335:335:335)) - (PORT datab (506:506:506) (605:605:605)) - (PORT datac (827:827:827) (949:949:949)) - (PORT datad (332:332:332) (388:388:388)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (396:396:396)) - (PORT datab (631:631:631) (721:721:721)) - (PORT datac (297:297:297) (344:344:344)) - (PORT datad (953:953:953) (1107:1107:1107)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (829:829:829) (978:978:978)) - (PORT datab (810:810:810) (931:931:931)) - (PORT datac (354:354:354) (413:413:413)) - (PORT datad (764:764:764) (866:866:866)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (137:137:137)) - (PORT datab (712:712:712) (811:811:811)) - (PORT datac (884:884:884) (999:999:999)) - (PORT datad (98:98:98) (118:118:118)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) - (DELAY - (ABSOLUTE - (PORT dataa (284:284:284) (339:339:339)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (696:696:696) (796:796:796)) - (PORT datad (426:426:426) (483:483:483)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (428:428:428)) - (PORT datab (344:344:344) (407:407:407)) - (PORT datac (719:719:719) (822:822:822)) - (PORT datad (439:439:439) (500:500:500)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (776:776:776) (851:851:851)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (118:118:118) (155:155:155)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (761:761:761) (826:826:826)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|mwr_wr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (124:124:124) (164:164:164)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (761:761:761) (826:826:826)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (132:132:132) (182:182:182)) - (PORT datac (543:543:543) (615:615:615)) - (PORT datad (105:105:105) (124:124:124)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1387:1387:1387) (1621:1621:1621)) - (PORT datab (835:835:835) (983:983:983)) - (PORT datac (1765:1765:1765) (2071:2071:2071)) - (PORT datad (908:908:908) (1052:1052:1052)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1083:1083:1083) (1219:1219:1219)) - (PORT clk (1095:1095:1095) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1070:1070:1070) (1252:1252:1252)) - (PORT d[1] (1425:1425:1425) (1666:1666:1666)) - (PORT d[2] (1386:1386:1386) (1614:1614:1614)) - (PORT d[3] (997:997:997) (1154:1154:1154)) - (PORT d[4] (1266:1266:1266) (1488:1488:1488)) - (PORT d[5] (2846:2846:2846) (3292:3292:3292)) - (PORT d[6] (1273:1273:1273) (1469:1469:1469)) - (PORT d[7] (1199:1199:1199) (1368:1368:1368)) - (PORT d[8] (1767:1767:1767) (2045:2045:2045)) - (PORT d[9] (1652:1652:1652) (1892:1892:1892)) - (PORT d[10] (1104:1104:1104) (1312:1312:1312)) - (PORT d[11] (1210:1210:1210) (1402:1402:1402)) - (PORT d[12] (724:724:724) (826:826:826)) - (PORT clk (1093:1093:1093) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1103:1103:1103) (1215:1215:1215)) - (PORT clk (1093:1093:1093) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (PORT d[0] (1438:1438:1438) (1571:1571:1571)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1075:1075:1075) (1092:1092:1092)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1258:1258:1258) (1421:1421:1421)) + (PORT d[0] (555:555:555) (632:632:632)) (PORT clk (1092:1092:1092) (1110:1110:1110)) ) ) @@ -35012,19 +30631,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1278:1278:1278) (1491:1491:1491)) - (PORT d[1] (1555:1555:1555) (1817:1817:1817)) - (PORT d[2] (1372:1372:1372) (1609:1609:1609)) - (PORT d[3] (2285:2285:2285) (2677:2677:2677)) - (PORT d[4] (1246:1246:1246) (1465:1465:1465)) - (PORT d[5] (2692:2692:2692) (3118:3118:3118)) - (PORT d[6] (1243:1243:1243) (1433:1433:1433)) - (PORT d[7] (1234:1234:1234) (1412:1412:1412)) - (PORT d[8] (1776:1776:1776) (2056:2056:2056)) - (PORT d[9] (1631:1631:1631) (1863:1863:1863)) - (PORT d[10] (1293:1293:1293) (1526:1526:1526)) - (PORT d[11] (1390:1390:1390) (1608:1608:1608)) - (PORT d[12] (887:887:887) (1009:1009:1009)) + (PORT d[0] (569:569:569) (646:646:646)) + (PORT d[1] (1219:1219:1219) (1447:1447:1447)) + (PORT d[2] (1946:1946:1946) (2222:2222:2222)) + (PORT d[3] (1649:1649:1649) (1930:1930:1930)) + (PORT d[4] (1489:1489:1489) (1749:1749:1749)) + (PORT d[5] (1847:1847:1847) (2145:2145:2145)) + (PORT d[6] (933:933:933) (1077:1077:1077)) + (PORT d[7] (1691:1691:1691) (1915:1915:1915)) + (PORT d[8] (572:572:572) (660:660:660)) + (PORT d[9] (1843:1843:1843) (2130:2130:2130)) + (PORT d[10] (955:955:955) (1096:1096:1096)) + (PORT d[11] (1109:1109:1109) (1291:1291:1291)) + (PORT d[12] (1075:1075:1075) (1236:1236:1236)) (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) @@ -35037,7 +30656,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1221:1221:1221) (1348:1348:1348)) + (PORT d[0] (523:523:523) (545:545:545)) (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) @@ -35051,7 +30670,7 @@ (DELAY (ABSOLUTE (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (1558:1558:1558) (1711:1711:1711)) + (PORT d[0] (928:928:928) (968:968:968)) ) ) ) @@ -35148,28 +30767,269 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12) + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) (DELAY (ABSOLUTE - (PORT dataa (187:187:187) (257:257:257)) - (PORT datab (895:895:895) (1034:1034:1034)) - (PORT datac (627:627:627) (746:746:746)) - (PORT datad (691:691:691) (794:794:794)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT clk (913:913:913) (917:917:917)) + (PORT asdata (801:801:801) (910:910:910)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT asdata (367:367:367) (416:416:416)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (447:447:447)) + (PORT datab (144:144:144) (182:182:182)) + (PORT datac (195:195:195) (237:237:237)) + (PORT datad (702:702:702) (789:789:789)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (1157:1157:1157) (1345:1345:1345)) + (PORT datac (616:616:616) (725:725:725)) + (PORT datad (625:625:625) (732:732:732)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (659:659:659) (756:756:756)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2260:2260:2260) (2618:2618:2618)) + (PORT d[1] (967:967:967) (1145:1145:1145)) + (PORT d[2] (1935:1935:1935) (2216:2216:2216)) + (PORT d[3] (1210:1210:1210) (1410:1410:1410)) + (PORT d[4] (1232:1232:1232) (1428:1428:1428)) + (PORT d[5] (955:955:955) (1125:1125:1125)) + (PORT d[6] (1005:1005:1005) (1163:1163:1163)) + (PORT d[7] (1786:1786:1786) (2020:2020:2020)) + (PORT d[8] (1927:1927:1927) (2239:2239:2239)) + (PORT d[9] (1000:1000:1000) (1155:1155:1155)) + (PORT d[10] (1873:1873:1873) (2157:2157:2157)) + (PORT d[11] (1185:1185:1185) (1369:1369:1369)) + (PORT d[12] (1018:1018:1018) (1175:1175:1175)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1271:1271:1271) (1396:1396:1396)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (1658:1658:1658) (1820:1820:1820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1083:1083:1083)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (615:615:615)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (368:368:368)) + (PORT datab (518:518:518) (618:618:618)) + (PORT datac (460:460:460) (513:513:513)) + (PORT datad (632:632:632) (741:741:741)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (447:447:447)) + (PORT datab (143:143:143) (181:181:181)) + (PORT datac (194:194:194) (236:236:236)) + (PORT datad (702:702:702) (789:789:789)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (1165:1165:1165) (1354:1354:1354)) + (PORT datac (622:622:622) (731:731:731)) + (PORT datad (628:628:628) (735:735:735)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (863:863:863) (970:970:970)) - (PORT clk (1102:1102:1102) (1119:1119:1119)) + (PORT d[0] (679:679:679) (760:760:760)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) ) ) (TIMINGCHECK @@ -35181,20 +31041,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (779:779:779) (900:900:900)) - (PORT d[1] (1811:1811:1811) (2128:2128:2128)) - (PORT d[2] (946:946:946) (1107:1107:1107)) - (PORT d[3] (390:390:390) (463:463:463)) - (PORT d[4] (377:377:377) (436:436:436)) - (PORT d[5] (894:894:894) (1036:1036:1036)) - (PORT d[6] (1644:1644:1644) (1898:1898:1898)) - (PORT d[7] (1278:1278:1278) (1491:1491:1491)) - (PORT d[8] (2147:2147:2147) (2490:2490:2490)) - (PORT d[9] (375:375:375) (432:432:432)) - (PORT d[10] (1471:1471:1471) (1716:1716:1716)) - (PORT d[11] (1294:1294:1294) (1518:1518:1518)) - (PORT d[12] (1533:1533:1533) (1742:1742:1742)) - (PORT clk (1100:1100:1100) (1117:1117:1117)) + (PORT d[0] (2377:2377:2377) (2744:2744:2744)) + (PORT d[1] (1350:1350:1350) (1590:1590:1590)) + (PORT d[2] (1850:1850:1850) (2107:2107:2107)) + (PORT d[3] (1476:1476:1476) (1736:1736:1736)) + (PORT d[4] (1493:1493:1493) (1748:1748:1748)) + (PORT d[5] (1642:1642:1642) (1906:1906:1906)) + (PORT d[6] (1107:1107:1107) (1279:1279:1279)) + (PORT d[7] (1510:1510:1510) (1712:1712:1712)) + (PORT d[8] (1945:1945:1945) (2280:2280:2280)) + (PORT d[9] (1660:1660:1660) (1922:1922:1922)) + (PORT d[10] (2963:2963:2963) (3389:3389:3389)) + (PORT d[11] (1075:1075:1075) (1261:1261:1261)) + (PORT d[12] (1256:1256:1256) (1442:1442:1442)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) (TIMINGCHECK @@ -35206,8 +31066,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1195:1195:1195) (1289:1289:1289)) - (PORT clk (1100:1100:1100) (1117:1117:1117)) + (PORT d[0] (1116:1116:1116) (1216:1216:1216)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) (TIMINGCHECK @@ -35219,8 +31079,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1102:1102:1102) (1119:1119:1119)) - (PORT d[0] (1417:1417:1417) (1520:1520:1520)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (1226:1226:1226) (1303:1303:1303)) ) ) ) @@ -35229,7 +31089,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) + (PORT clk (1093:1093:1093) (1111:1111:1111)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -35239,7 +31099,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) + (PORT clk (1093:1093:1093) (1111:1111:1111)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -35249,7 +31109,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) + (PORT clk (1093:1093:1093) (1111:1111:1111)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -35259,7 +31119,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) + (PORT clk (1093:1093:1093) (1111:1111:1111)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -35269,7 +31129,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1082:1082:1082) (1098:1098:1098)) + (PORT clk (1072:1072:1072) (1089:1089:1089)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -35283,7 +31143,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (622:622:622) (630:630:630)) + (PORT clk (612:612:612) (621:621:621)) ) ) ) @@ -35292,7 +31152,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (623:623:623) (631:631:631)) + (PORT clk (613:613:613) (622:622:622)) ) ) ) @@ -35301,7 +31161,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (623:623:623) (631:631:631)) + (PORT clk (613:613:613) (622:622:622)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -35311,582 +31171,536 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (623:623:623) (631:631:631)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1602:1602:1602) (1802:1802:1802)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2235:2235:2235) (2590:2590:2590)) - (PORT d[1] (1242:1242:1242) (1460:1460:1460)) - (PORT d[2] (2332:2332:2332) (2692:2692:2692)) - (PORT d[3] (1928:1928:1928) (2266:2266:2266)) - (PORT d[4] (1664:1664:1664) (1944:1944:1944)) - (PORT d[5] (2308:2308:2308) (2678:2678:2678)) - (PORT d[6] (935:935:935) (1066:1066:1066)) - (PORT d[7] (1773:1773:1773) (2030:2030:2030)) - (PORT d[8] (1444:1444:1444) (1682:1682:1682)) - (PORT d[9] (1625:1625:1625) (1858:1858:1858)) - (PORT d[10] (1486:1486:1486) (1740:1740:1740)) - (PORT d[11] (870:870:870) (1018:1018:1018)) - (PORT d[12] (1257:1257:1257) (1434:1434:1434)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (758:758:758) (813:813:813)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1037:1037:1037) (1093:1093:1093)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (613:613:613) (622:622:622)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13) + (INSTANCE D\[6\]\~91) (DELAY (ABSOLUTE - (PORT dataa (187:187:187) (256:256:256)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (1049:1049:1049) (1199:1199:1199)) - (PORT datad (517:517:517) (586:586:586)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (192:192:192) (177:177:177)) + (PORT dataa (456:456:456) (524:524:524)) + (PORT datab (782:782:782) (914:914:914)) + (PORT datac (163:163:163) (191:191:191)) + (PORT datad (617:617:617) (704:704:704)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (444:444:444)) + (PORT datab (136:136:136) (174:174:174)) + (PORT datac (189:189:189) (231:231:231)) + (PORT datad (702:702:702) (789:789:789)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE CLOCK_50\~inputclkctrl) (DELAY (ABSOLUTE - (PORT d[0] (428:428:428) (485:485:485)) - (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT inclk[0] (91:91:91) (78:78:78)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (558:558:558) (639:639:639)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\~0) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (811:811:811)) + (PORT datab (535:535:535) (640:640:640)) + (PORT datac (530:530:530) (634:634:634)) + (PORT datad (151:151:151) (199:199:199)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (629:629:629) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[1\]) (DELAY (ABSOLUTE - (PORT d[0] (430:430:430) (504:504:504)) - (PORT d[1] (1153:1153:1153) (1344:1344:1344)) - (PORT d[2] (731:731:731) (855:855:855)) - (PORT d[3] (2153:2153:2153) (2527:2527:2527)) - (PORT d[4] (1614:1614:1614) (1895:1895:1895)) - (PORT d[5] (557:557:557) (648:648:648)) - (PORT d[6] (1835:1835:1835) (2106:2106:2106)) - (PORT d[7] (1521:1521:1521) (1771:1771:1771)) - (PORT d[8] (562:562:562) (642:642:642)) - (PORT d[9] (1536:1536:1536) (1742:1742:1742)) - (PORT d[10] (571:571:571) (660:660:660)) - (PORT d[11] (1470:1470:1470) (1725:1725:1725)) - (PORT d[12] (1198:1198:1198) (1365:1365:1365)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT clk (919:919:919) (923:923:923)) + (PORT asdata (643:643:643) (725:725:725)) + (PORT ena (629:629:629) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[2\]\~4) (DELAY (ABSOLUTE - (PORT d[0] (499:499:499) (514:514:514)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT datac (479:479:479) (568:568:568)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (629:629:629) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~0) (DELAY (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (PORT d[0] (805:805:805) (832:832:832)) + (PORT datac (475:475:475) (562:562:562)) + (PORT datad (789:789:789) (916:916:916)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[3\]) (DELAY (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1053:1053:1053) (1072:1072:1072)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (629:629:629) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~1) (DELAY (ABSOLUTE - (PORT d[0] (1253:1253:1253) (1406:1406:1406)) - (PORT clk (1058:1058:1058) (1075:1075:1075)) + (PORT dataa (497:497:497) (586:586:586)) + (PORT datac (762:762:762) (879:879:879)) + (PORT datad (789:789:789) (916:916:916)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (629:629:629) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~0) (DELAY (ABSOLUTE - (PORT d[0] (1094:1094:1094) (1263:1263:1263)) - (PORT d[1] (1124:1124:1124) (1316:1316:1316)) - (PORT d[2] (1100:1100:1100) (1260:1260:1260)) - (PORT d[3] (1130:1130:1130) (1342:1342:1342)) - (PORT d[4] (1126:1126:1126) (1298:1298:1298)) - (PORT d[5] (1065:1065:1065) (1233:1233:1233)) - (PORT d[6] (1044:1044:1044) (1203:1203:1203)) - (PORT d[7] (1077:1077:1077) (1244:1244:1244)) - (PORT d[8] (1088:1088:1088) (1263:1263:1263)) - (PORT d[9] (1053:1053:1053) (1225:1225:1225)) - (PORT d[10] (1071:1071:1071) (1253:1253:1253)) - (PORT d[11] (1147:1147:1147) (1318:1318:1318)) - (PORT d[12] (1054:1054:1054) (1216:1216:1216)) - (PORT clk (1055:1055:1055) (1074:1074:1074)) + (PORT dataa (384:384:384) (465:465:465)) + (PORT datab (398:398:398) (477:477:477)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~2) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (425:425:425)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~4) + (DELAY + (ABSOLUTE + (PORT datab (372:372:372) (452:452:452)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~6) + (DELAY + (ABSOLUTE + (PORT datab (376:376:376) (457:457:457)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (629:629:629) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~8) (DELAY (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) + (PORT dataa (387:387:387) (470:470:470)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[6\]) (DELAY (ABSOLUTE - (PORT clk (1059:1059:1059) (1076:1076:1076)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1059:1059:1059) (1076:1076:1076)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1059:1059:1059) (1076:1076:1076)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1059:1059:1059) (1076:1076:1076)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2255:2255:2255) (2612:2612:2612)) - (PORT d[1] (1397:1397:1397) (1634:1634:1634)) - (PORT d[2] (2501:2501:2501) (2882:2882:2882)) - (PORT d[3] (2111:2111:2111) (2482:2482:2482)) - (PORT d[4] (1848:1848:1848) (2152:2152:2152)) - (PORT d[5] (2329:2329:2329) (2702:2702:2702)) - (PORT d[6] (1432:1432:1432) (1649:1649:1649)) - (PORT d[7] (1595:1595:1595) (1826:1826:1826)) - (PORT d[8] (2121:2121:2121) (2445:2445:2445)) - (PORT d[9] (1248:1248:1248) (1420:1420:1420)) - (PORT d[10] (880:880:880) (1032:1032:1032)) - (PORT d[11] (869:869:869) (1020:1020:1020)) - (PORT d[12] (1239:1239:1239) (1413:1413:1413)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (629:629:629) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~10) (DELAY (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (723:723:723) (798:798:798)) + (PORT dataa (520:520:520) (618:618:618)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[7\]) (DELAY (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (629:629:629) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~12) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) + (PORT datab (379:379:379) (452:452:452)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector6\~0) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT datab (331:331:331) (390:390:390)) + (PORT datac (306:306:306) (357:357:357)) + (PORT datad (526:526:526) (625:625:625)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[9\]\~1) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + (PORT dataa (682:682:682) (811:811:811)) + (PORT datab (533:533:533) (638:638:638)) + (PORT datac (533:533:533) (638:638:638)) + (PORT datad (155:155:155) (204:204:204)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[8\]) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (414:414:414) (487:487:487)) - (PORT d[1] (372:372:372) (432:432:432)) - (PORT d[2] (922:922:922) (1076:1076:1076)) - (PORT d[3] (2336:2336:2336) (2740:2740:2740)) - (PORT d[4] (1615:1615:1615) (1892:1892:1892)) - (PORT d[5] (373:373:373) (432:432:432)) - (PORT d[6] (1811:1811:1811) (2082:2082:2082)) - (PORT d[7] (1476:1476:1476) (1718:1718:1718)) - (PORT d[8] (552:552:552) (628:628:628)) - (PORT d[9] (1480:1480:1480) (1669:1669:1669)) - (PORT d[10] (537:537:537) (616:616:616)) - (PORT d[11] (819:819:819) (934:934:934)) - (PORT d[12] (989:989:989) (1121:1121:1121)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT clk (918:918:918) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~14) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (1670:1670:1670) (1495:1495:1495)) + (PORT datad (384:384:384) (462:462:462)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector5\~0) (DELAY (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + (PORT dataa (354:354:354) (413:413:413)) + (PORT datac (429:429:429) (491:491:491)) + (PORT datad (526:526:526) (625:625:625)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[9\]) (DELAY (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + (PORT clk (918:918:918) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~2) (DELAY (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) + (PORT dataa (680:680:680) (809:809:809)) + (PORT datab (529:529:529) (634:634:634)) + (PORT datac (538:538:538) (643:643:643)) + (PORT datad (158:158:158) (207:207:207)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~3) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) + (PORT dataa (334:334:334) (392:392:392)) + (PORT datab (557:557:557) (667:667:667)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[10\]) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + (PORT clk (918:918:918) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datab (332:332:332) (391:391:391)) + (PORT datad (526:526:526) (625:625:625)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[11\]) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + (PORT clk (918:918:918) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datac (333:333:333) (392:392:392)) + (PORT datad (525:525:525) (625:625:625)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (416:416:416) (476:476:476)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (875:875:875) (1007:1007:1007)) + (PORT clk (1099:1099:1099) (1117:1117:1117)) ) ) (TIMINGCHECK @@ -35898,20 +31712,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (620:620:620) (729:729:729)) - (PORT d[1] (1141:1141:1141) (1331:1331:1331)) - (PORT d[2] (755:755:755) (888:888:888)) - (PORT d[3] (2149:2149:2149) (2522:2522:2522)) - (PORT d[4] (1416:1416:1416) (1659:1659:1659)) - (PORT d[5] (551:551:551) (640:640:640)) - (PORT d[6] (483:483:483) (554:554:554)) - (PORT d[7] (1530:1530:1530) (1786:1786:1786)) - (PORT d[8] (659:659:659) (748:748:748)) - (PORT d[9] (1533:1533:1533) (1734:1734:1734)) - (PORT d[10] (735:735:735) (848:848:848)) - (PORT d[11] (1474:1474:1474) (1735:1735:1735)) - (PORT d[12] (1189:1189:1189) (1349:1349:1349)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (1463:1463:1463) (1667:1667:1667)) + (PORT d[1] (1368:1368:1368) (1613:1613:1613)) + (PORT d[2] (1329:1329:1329) (1557:1557:1557)) + (PORT d[3] (1137:1137:1137) (1317:1317:1317)) + (PORT d[4] (1716:1716:1716) (2014:2014:2014)) + (PORT d[5] (1231:1231:1231) (1458:1458:1458)) + (PORT d[6] (908:908:908) (1038:1038:1038)) + (PORT d[7] (933:933:933) (1073:1073:1073)) + (PORT d[8] (1605:1605:1605) (1884:1884:1884)) + (PORT d[9] (1200:1200:1200) (1368:1368:1368)) + (PORT d[10] (1231:1231:1231) (1400:1400:1400)) + (PORT d[11] (1813:1813:1813) (2074:2074:2074)) + (PORT d[12] (1246:1246:1246) (1439:1439:1439)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) ) ) (TIMINGCHECK @@ -35923,8 +31737,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (646:646:646) (684:684:684)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (1536:1536:1536) (1684:1684:1684)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) ) ) (TIMINGCHECK @@ -35936,8 +31750,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (1383:1383:1383) (1313:1313:1313)) + (PORT clk (1099:1099:1099) (1117:1117:1117)) + (PORT d[0] (1721:1721:1721) (1605:1605:1605)) ) ) ) @@ -35946,7 +31760,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT clk (1100:1100:1100) (1118:1118:1118)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -35956,7 +31770,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT clk (1100:1100:1100) (1118:1118:1118)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -35966,7 +31780,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT clk (1100:1100:1100) (1118:1118:1118)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -35976,7 +31790,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT clk (1100:1100:1100) (1118:1118:1118)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -35986,7 +31800,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1052:1052:1052) (1071:1071:1071)) + (PORT clk (1054:1054:1054) (1074:1074:1074)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -36000,8 +31814,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1578:1578:1578) (1786:1786:1786)) - (PORT clk (1057:1057:1057) (1074:1074:1074)) + (PORT d[0] (1208:1208:1208) (1358:1358:1358)) + (PORT clk (1059:1059:1059) (1077:1077:1077)) ) ) (TIMINGCHECK @@ -36013,20 +31827,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1085:1085:1085) (1254:1254:1254)) - (PORT d[1] (1122:1122:1122) (1314:1314:1314)) - (PORT d[2] (1107:1107:1107) (1272:1272:1272)) - (PORT d[3] (1139:1139:1139) (1350:1350:1350)) - (PORT d[4] (1064:1064:1064) (1223:1223:1223)) - (PORT d[5] (1048:1048:1048) (1209:1209:1209)) - (PORT d[6] (1040:1040:1040) (1204:1204:1204)) - (PORT d[7] (1061:1061:1061) (1220:1220:1220)) - (PORT d[8] (1122:1122:1122) (1306:1306:1306)) - (PORT d[9] (1131:1131:1131) (1301:1301:1301)) - (PORT d[10] (1062:1062:1062) (1243:1243:1243)) - (PORT d[11] (1144:1144:1144) (1314:1314:1314)) - (PORT d[12] (1075:1075:1075) (1248:1248:1248)) - (PORT clk (1054:1054:1054) (1073:1073:1073)) + (PORT d[0] (2557:2557:2557) (2902:2902:2902)) + (PORT d[1] (2446:2446:2446) (2755:2755:2755)) + (PORT d[2] (2547:2547:2547) (2893:2893:2893)) + (PORT d[3] (2605:2605:2605) (2960:2960:2960)) + (PORT d[4] (2353:2353:2353) (2651:2651:2651)) + (PORT d[5] (2406:2406:2406) (2710:2710:2710)) + (PORT d[6] (2575:2575:2575) (2938:2938:2938)) + (PORT d[7] (2406:2406:2406) (2709:2709:2709)) + (PORT d[8] (2610:2610:2610) (2940:2940:2940)) + (PORT d[9] (2605:2605:2605) (2984:2984:2984)) + (PORT d[10] (2474:2474:2474) (2781:2781:2781)) + (PORT d[11] (2556:2556:2556) (2881:2881:2881)) + (PORT d[12] (2476:2476:2476) (2788:2788:2788)) + (PORT clk (1056:1056:1056) (1076:1076:1076)) ) ) (TIMINGCHECK @@ -36038,7 +31852,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1057:1057:1057) (1074:1074:1074)) + (PORT clk (1059:1059:1059) (1077:1077:1077)) ) ) ) @@ -36047,7 +31861,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) + (PORT clk (1060:1060:1060) (1078:1078:1078)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -36057,7 +31871,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) + (PORT clk (1060:1060:1060) (1078:1078:1078)) (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) ) ) @@ -36067,7 +31881,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) + (PORT clk (1060:1060:1060) (1078:1078:1078)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -36077,7 +31891,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) + (PORT clk (1060:1060:1060) (1078:1078:1078)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -36085,6 +31899,12430 @@ (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1075:1075:1075)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (682:682:682) (804:804:804)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1122:1122:1122) (1154:1154:1154)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT asdata (927:927:927) (1048:1048:1048)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (445:445:445)) + (PORT datab (139:139:139) (178:178:178)) + (PORT datac (191:191:191) (233:233:233)) + (PORT datad (702:702:702) (789:789:789)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (857:857:857) (982:982:982)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1642:1642:1642) (1871:1871:1871)) + (PORT d[1] (1395:1395:1395) (1637:1637:1637)) + (PORT d[2] (688:688:688) (789:789:789)) + (PORT d[3] (1143:1143:1143) (1331:1331:1331)) + (PORT d[4] (1700:1700:1700) (1997:1997:1997)) + (PORT d[5] (1414:1414:1414) (1670:1670:1670)) + (PORT d[6] (879:879:879) (1002:1002:1002)) + (PORT d[7] (737:737:737) (847:847:847)) + (PORT d[8] (979:979:979) (1123:1123:1123)) + (PORT d[9] (882:882:882) (1016:1016:1016)) + (PORT d[10] (1266:1266:1266) (1445:1445:1445)) + (PORT d[11] (1830:1830:1830) (2093:2093:2093)) + (PORT d[12] (1100:1100:1100) (1269:1269:1269)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1509:1509:1509) (1656:1656:1656)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (1739:1739:1739) (1900:1900:1900)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1068:1068:1068)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1204:1204:1204) (1366:1366:1366)) + (PORT clk (1054:1054:1054) (1071:1071:1071)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2539:2539:2539) (2882:2882:2882)) + (PORT d[1] (2319:2319:2319) (2617:2617:2617)) + (PORT d[2] (2377:2377:2377) (2701:2701:2701)) + (PORT d[3] (2488:2488:2488) (2836:2836:2836)) + (PORT d[4] (2376:2376:2376) (2699:2699:2699)) + (PORT d[5] (2409:2409:2409) (2733:2733:2733)) + (PORT d[6] (2476:2476:2476) (2830:2830:2830)) + (PORT d[7] (2266:2266:2266) (2556:2556:2556)) + (PORT d[8] (2430:2430:2430) (2726:2726:2726)) + (PORT d[9] (2585:2585:2585) (2963:2963:2963)) + (PORT d[10] (2471:2471:2471) (2777:2777:2777)) + (PORT d[11] (2523:2523:2523) (2853:2853:2853)) + (PORT d[12] (2469:2469:2469) (2781:2781:2781)) + (PORT clk (1051:1051:1051) (1070:1070:1070)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1071:1071:1071)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1426:1426:1426) (1615:1615:1615)) + (PORT d[1] (1269:1269:1269) (1482:1482:1482)) + (PORT d[2] (1336:1336:1336) (1564:1564:1564)) + (PORT d[3] (1228:1228:1228) (1448:1448:1448)) + (PORT d[4] (1698:1698:1698) (1990:1990:1990)) + (PORT d[5] (1326:1326:1326) (1565:1565:1565)) + (PORT d[6] (1094:1094:1094) (1247:1247:1247)) + (PORT d[7] (1243:1243:1243) (1418:1418:1418)) + (PORT d[8] (1582:1582:1582) (1856:1856:1856)) + (PORT d[9] (1014:1014:1014) (1157:1157:1157)) + (PORT d[10] (1002:1002:1002) (1126:1126:1126)) + (PORT d[11] (1757:1757:1757) (2009:2009:2009)) + (PORT d[12] (728:728:728) (843:843:843)) + (PORT clk (1106:1106:1106) (1123:1123:1123)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1123:1123:1123)) + (PORT d[0] (1273:1273:1273) (1427:1427:1427)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1104:1104:1104)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (629:629:629) (637:637:637)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (629:629:629) (637:637:637)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (629:629:629) (637:637:637)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (855:855:855)) + (PORT datab (148:148:148) (201:201:201)) + (PORT datac (794:794:794) (897:897:897)) + (PORT datad (908:908:908) (1038:1038:1038)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2075:2075:2075) (2400:2400:2400)) + (PORT d[1] (1515:1515:1515) (1769:1769:1769)) + (PORT d[2] (1420:1420:1420) (1623:1623:1623)) + (PORT d[3] (1217:1217:1217) (1428:1428:1428)) + (PORT d[4] (1287:1287:1287) (1509:1509:1509)) + (PORT d[5] (1213:1213:1213) (1425:1425:1425)) + (PORT d[6] (1122:1122:1122) (1294:1294:1294)) + (PORT d[7] (1157:1157:1157) (1309:1309:1309)) + (PORT d[8] (1735:1735:1735) (2028:2028:2028)) + (PORT d[9] (1494:1494:1494) (1731:1731:1731)) + (PORT d[10] (2747:2747:2747) (3134:3134:3134)) + (PORT d[11] (1194:1194:1194) (1379:1379:1379)) + (PORT d[12] (1423:1423:1423) (1629:1629:1629)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (1992:1992:1992) (1801:1801:1801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (786:786:786)) + (PORT datab (637:637:637) (730:730:730)) + (PORT datac (884:884:884) (1011:1011:1011)) + (PORT datad (93:93:93) (113:113:113)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (790:790:790) (926:926:926)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (326:326:326) (394:394:394)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (409:409:409)) + (PORT datab (1129:1129:1129) (1312:1312:1312)) + (PORT datac (494:494:494) (589:589:589)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE raw_loader_in\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (588:588:588)) + (PORT datac (913:913:913) (1067:1067:1067)) + (PORT datad (1114:1114:1114) (1287:1287:1287)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (509:509:509) (602:602:602)) + (PORT datab (728:728:728) (836:836:836)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~101) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (596:596:596)) + (PORT datab (479:479:479) (578:578:578)) + (PORT datac (902:902:902) (1028:1028:1028)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (194:194:194)) + (PORT datab (772:772:772) (880:880:880)) + (PORT datac (525:525:525) (620:620:620)) + (PORT datad (443:443:443) (498:498:498)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (1115:1115:1115)) + (PORT datab (426:426:426) (518:518:518)) + (PORT datac (519:519:519) (605:605:605)) + (PORT datad (686:686:686) (789:789:789)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (643:643:643)) + (PORT datab (549:549:549) (639:639:639)) + (PORT datac (520:520:520) (608:608:608)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (635:635:635) (752:752:752)) + (PORT datac (121:121:121) (151:151:151)) + (PORT datad (112:112:112) (133:133:133)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (102:102:102) (119:119:119)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (754:754:754)) + (PORT datab (501:501:501) (593:593:593)) + (PORT datac (369:369:369) (435:435:435)) + (PORT datad (198:198:198) (225:225:225)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (917:917:917) (902:902:902)) + (PORT ena (645:645:645) (697:697:697)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (DELAY + (ABSOLUTE + (PORT datac (941:941:941) (1085:1085:1085)) + (PORT datad (683:683:683) (800:800:800)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (970:970:970)) + (PORT datab (1296:1296:1296) (1497:1497:1497)) + (PORT datac (1238:1238:1238) (1445:1445:1445)) + (PORT datad (817:817:817) (953:953:953)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (297:297:297)) + (PORT datab (895:895:895) (1020:1020:1020)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (609:609:609) (701:701:701)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1268:1268:1268)) + (PORT datab (611:611:611) (701:701:701)) + (PORT datac (1150:1150:1150) (1342:1342:1342)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (757:757:757)) + (PORT datab (159:159:159) (204:204:204)) + (PORT datac (143:143:143) (184:184:184)) + (PORT datad (130:130:130) (160:160:160)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (714:714:714)) + (PORT datab (655:655:655) (757:757:757)) + (PORT datac (221:221:221) (280:280:280)) + (PORT datad (369:369:369) (437:437:437)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (599:599:599)) + (PORT datac (916:916:916) (1066:1066:1066)) + (PORT datad (490:490:490) (565:565:565)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (489:489:489) (561:561:561)) + (PORT datad (132:132:132) (161:161:161)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (222:222:222)) + (PORT datab (336:336:336) (392:392:392)) + (PORT datac (630:630:630) (736:736:736)) + (PORT datad (322:322:322) (376:376:376)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (547:547:547) (647:647:647)) + (PORT datac (309:309:309) (360:360:360)) + (PORT datad (120:120:120) (150:150:150)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (839:839:839)) + (PORT datab (504:504:504) (587:587:587)) + (PORT datac (1033:1033:1033) (1182:1182:1182)) + (PORT datad (520:520:520) (607:607:607)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (406:406:406)) + (PORT datab (139:139:139) (179:179:179)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (520:520:520) (605:605:605)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (283:283:283)) + (PORT datab (747:747:747) (871:871:871)) + (PORT datac (632:632:632) (721:721:721)) + (PORT datad (674:674:674) (776:776:776)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (338:338:338)) + (PORT datab (337:337:337) (396:396:396)) + (PORT datac (353:353:353) (422:422:422)) + (PORT datad (366:366:366) (429:429:429)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (409:409:409)) + (PORT datab (502:502:502) (579:579:579)) + (PORT datac (352:352:352) (420:420:420)) + (PORT datad (473:473:473) (542:542:542)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (611:611:611)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (522:522:522) (600:600:600)) + (PORT datad (482:482:482) (540:540:540)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (429:429:429)) + (PORT datab (658:658:658) (756:756:756)) + (PORT datac (594:594:594) (684:684:684)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1140:1140:1140)) + (PORT datab (673:673:673) (794:794:794)) + (PORT datac (879:879:879) (1043:1043:1043)) + (PORT datad (607:607:607) (694:694:694)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (659:659:659) (755:755:755)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2092:2092:2092) (2427:2427:2427)) + (PORT d[1] (1003:1003:1003) (1187:1187:1187)) + (PORT d[2] (1762:1762:1762) (2022:2022:2022)) + (PORT d[3] (1066:1066:1066) (1248:1248:1248)) + (PORT d[4] (1270:1270:1270) (1482:1482:1482)) + (PORT d[5] (1549:1549:1549) (1816:1816:1816)) + (PORT d[6] (1190:1190:1190) (1376:1376:1376)) + (PORT d[7] (1606:1606:1606) (1818:1818:1818)) + (PORT d[8] (1757:1757:1757) (2045:2045:2045)) + (PORT d[9] (1602:1602:1602) (1842:1842:1842)) + (PORT d[10] (2054:2054:2054) (2366:2366:2366)) + (PORT d[11] (1012:1012:1012) (1176:1176:1176)) + (PORT d[12] (1207:1207:1207) (1391:1391:1391)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1093:1093:1093) (1194:1194:1194)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (1481:1481:1481) (1623:1623:1623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1083:1083:1083)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (615:615:615)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (643:643:643) (736:736:736)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2264:2264:2264) (2626:2626:2626)) + (PORT d[1] (976:976:976) (1155:1155:1155)) + (PORT d[2] (1924:1924:1924) (2200:2200:2200)) + (PORT d[3] (1054:1054:1054) (1231:1231:1231)) + (PORT d[4] (1073:1073:1073) (1242:1242:1242)) + (PORT d[5] (954:954:954) (1119:1119:1119)) + (PORT d[6] (1009:1009:1009) (1167:1167:1167)) + (PORT d[7] (1774:1774:1774) (2007:2007:2007)) + (PORT d[8] (1932:1932:1932) (2243:2243:2243)) + (PORT d[9] (1635:1635:1635) (1882:1882:1882)) + (PORT d[10] (2007:2007:2007) (2303:2303:2303)) + (PORT d[11] (861:861:861) (1003:1003:1003)) + (PORT d[12] (1003:1003:1003) (1150:1150:1150)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1068:1068:1068) (1159:1159:1159)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1102:1102:1102)) + (PORT d[0] (1327:1327:1327) (1422:1422:1422)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1081:1081:1081)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (604:604:604) (613:613:613)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (673:673:673) (772:772:772)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2093:2093:2093) (2428:2428:2428)) + (PORT d[1] (983:983:983) (1158:1158:1158)) + (PORT d[2] (1742:1742:1742) (1993:1993:1993)) + (PORT d[3] (1189:1189:1189) (1381:1381:1381)) + (PORT d[4] (1286:1286:1286) (1504:1504:1504)) + (PORT d[5] (1557:1557:1557) (1827:1827:1827)) + (PORT d[6] (1042:1042:1042) (1211:1211:1211)) + (PORT d[7] (1613:1613:1613) (1825:1825:1825)) + (PORT d[8] (1938:1938:1938) (2254:2254:2254)) + (PORT d[9] (1639:1639:1639) (1892:1892:1892)) + (PORT d[10] (2034:2034:2034) (2338:2338:2338)) + (PORT d[11] (1022:1022:1022) (1190:1190:1190)) + (PORT d[12] (1170:1170:1170) (1342:1342:1342)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1059:1059:1059) (1151:1151:1151)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1102:1102:1102)) + (PORT d[0] (1375:1375:1375) (1493:1493:1493)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1081:1081:1081)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (604:604:604) (613:613:613)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (913:913:913)) + (PORT datab (781:781:781) (913:913:913)) + (PORT datac (638:638:638) (717:717:717)) + (PORT datad (631:631:631) (709:709:709)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (707:707:707) (817:817:817)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1636:1636:1636) (1864:1864:1864)) + (PORT d[1] (1552:1552:1552) (1823:1823:1823)) + (PORT d[2] (682:682:682) (782:782:782)) + (PORT d[3] (962:962:962) (1117:1117:1117)) + (PORT d[4] (1687:1687:1687) (1968:1968:1968)) + (PORT d[5] (1407:1407:1407) (1658:1658:1658)) + (PORT d[6] (722:722:722) (827:827:827)) + (PORT d[7] (750:750:750) (869:869:869)) + (PORT d[8] (995:995:995) (1153:1153:1153)) + (PORT d[9] (708:708:708) (820:820:820)) + (PORT d[10] (1411:1411:1411) (1604:1604:1604)) + (PORT d[11] (1846:1846:1846) (2146:2146:2146)) + (PORT d[12] (1264:1264:1264) (1454:1454:1454)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (854:854:854) (919:919:919)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (PORT d[0] (1185:1185:1185) (1273:1273:1273)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1088:1088:1088)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (729:729:729)) + (PORT datab (935:935:935) (1086:1086:1086)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (785:785:785) (911:911:911)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (898:898:898) (1053:1053:1053)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1785:1785:1785) (2045:2045:2045)) + (PORT d[1] (1164:1164:1164) (1373:1373:1373)) + (PORT d[2] (1221:1221:1221) (1417:1417:1417)) + (PORT d[3] (1049:1049:1049) (1230:1230:1230)) + (PORT d[4] (1442:1442:1442) (1668:1668:1668)) + (PORT d[5] (1305:1305:1305) (1532:1532:1532)) + (PORT d[6] (976:976:976) (1119:1119:1119)) + (PORT d[7] (940:940:940) (1092:1092:1092)) + (PORT d[8] (1488:1488:1488) (1732:1732:1732)) + (PORT d[9] (1134:1134:1134) (1301:1301:1301)) + (PORT d[10] (1133:1133:1133) (1307:1307:1307)) + (PORT d[11] (1381:1381:1381) (1598:1598:1598)) + (PORT d[12] (1446:1446:1446) (1655:1655:1655)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1438:1438:1438) (1584:1584:1584)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (2262:2262:2262) (2502:2502:2502)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1046:1046:1046) (1065:1065:1065)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (946:946:946) (1050:1050:1050)) + (PORT clk (1051:1051:1051) (1068:1068:1068)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2446:2446:2446) (2778:2778:2778)) + (PORT d[1] (2362:2362:2362) (2678:2678:2678)) + (PORT d[2] (2423:2423:2423) (2755:2755:2755)) + (PORT d[3] (2615:2615:2615) (2968:2968:2968)) + (PORT d[4] (2392:2392:2392) (2714:2714:2714)) + (PORT d[5] (2550:2550:2550) (2906:2906:2906)) + (PORT d[6] (2637:2637:2637) (3014:3014:3014)) + (PORT d[7] (2422:2422:2422) (2758:2758:2758)) + (PORT d[8] (2414:2414:2414) (2749:2749:2749)) + (PORT d[9] (2559:2559:2559) (2937:2937:2937)) + (PORT d[10] (2575:2575:2575) (2895:2895:2895)) + (PORT d[11] (2424:2424:2424) (2742:2742:2742)) + (PORT d[12] (2554:2554:2554) (2908:2908:2908)) + (PORT clk (1048:1048:1048) (1067:1067:1067)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1051:1051:1051) (1068:1068:1068)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1069:1069:1069)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1069:1069:1069)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1069:1069:1069)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1069:1069:1069)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1599:1599:1599) (1833:1833:1833)) + (PORT d[1] (989:989:989) (1178:1178:1178)) + (PORT d[2] (1107:1107:1107) (1292:1292:1292)) + (PORT d[3] (1072:1072:1072) (1258:1258:1258)) + (PORT d[4] (1602:1602:1602) (1841:1841:1841)) + (PORT d[5] (1316:1316:1316) (1540:1540:1540)) + (PORT d[6] (1129:1129:1129) (1293:1293:1293)) + (PORT d[7] (1227:1227:1227) (1432:1432:1432)) + (PORT d[8] (1367:1367:1367) (1595:1595:1595)) + (PORT d[9] (1129:1129:1129) (1298:1298:1298)) + (PORT d[10] (959:959:959) (1096:1096:1096)) + (PORT d[11] (1135:1135:1135) (1299:1299:1299)) + (PORT d[12] (1423:1423:1423) (1625:1625:1625)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (1578:1578:1578) (1775:1775:1775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2216:2216:2216) (2563:2563:2563)) + (PORT d[1] (1659:1659:1659) (1935:1935:1935)) + (PORT d[2] (1569:1569:1569) (1794:1794:1794)) + (PORT d[3] (1294:1294:1294) (1526:1526:1526)) + (PORT d[4] (1452:1452:1452) (1691:1691:1691)) + (PORT d[5] (1461:1461:1461) (1699:1699:1699)) + (PORT d[6] (1104:1104:1104) (1269:1269:1269)) + (PORT d[7] (1321:1321:1321) (1494:1494:1494)) + (PORT d[8] (1792:1792:1792) (2113:2113:2113)) + (PORT d[9] (1529:1529:1529) (1780:1780:1780)) + (PORT d[10] (2637:2637:2637) (3017:3017:3017)) + (PORT d[11] (1109:1109:1109) (1296:1296:1296)) + (PORT d[12] (1409:1409:1409) (1611:1611:1611)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (2281:2281:2281) (2058:2058:2058)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (839:839:839) (963:963:963)) + (PORT clk (1104:1104:1104) (1120:1120:1120)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1582:1582:1582) (1791:1791:1791)) + (PORT d[1] (1211:1211:1211) (1427:1427:1427)) + (PORT d[2] (1254:1254:1254) (1474:1474:1474)) + (PORT d[3] (1306:1306:1306) (1512:1512:1512)) + (PORT d[4] (1722:1722:1722) (2020:2020:2020)) + (PORT d[5] (1375:1375:1375) (1614:1614:1614)) + (PORT d[6] (917:917:917) (1047:1047:1047)) + (PORT d[7] (907:907:907) (1040:1040:1040)) + (PORT d[8] (1585:1585:1585) (1863:1863:1863)) + (PORT d[9] (1205:1205:1205) (1379:1379:1379)) + (PORT d[10] (1085:1085:1085) (1238:1238:1238)) + (PORT d[11] (1643:1643:1643) (1882:1882:1882)) + (PORT d[12] (905:905:905) (1047:1047:1047)) + (PORT clk (1102:1102:1102) (1118:1118:1118)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1389:1389:1389) (1525:1525:1525)) + (PORT clk (1102:1102:1102) (1118:1118:1118)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1104:1104:1104) (1120:1120:1120)) + (PORT d[0] (1751:1751:1751) (1627:1627:1627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1077:1077:1077)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1400:1400:1400) (1590:1590:1590)) + (PORT clk (1064:1064:1064) (1080:1080:1080)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2480:2480:2480) (2801:2801:2801)) + (PORT d[1] (2279:2279:2279) (2566:2566:2566)) + (PORT d[2] (2448:2448:2448) (2750:2750:2750)) + (PORT d[3] (2483:2483:2483) (2821:2821:2821)) + (PORT d[4] (2520:2520:2520) (2837:2837:2837)) + (PORT d[5] (2430:2430:2430) (2762:2762:2762)) + (PORT d[6] (2545:2545:2545) (2901:2901:2901)) + (PORT d[7] (2265:2265:2265) (2556:2556:2556)) + (PORT d[8] (2566:2566:2566) (2898:2898:2898)) + (PORT d[9] (2550:2550:2550) (2915:2915:2915)) + (PORT d[10] (2580:2580:2580) (2904:2904:2904)) + (PORT d[11] (2430:2430:2430) (2736:2736:2736)) + (PORT d[12] (2483:2483:2483) (2802:2802:2802)) + (PORT clk (1061:1061:1061) (1079:1079:1079)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1080:1080:1080)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1081:1081:1081)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1081:1081:1081)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1081:1081:1081)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1081:1081:1081)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (802:802:802) (931:931:931)) + (PORT datab (528:528:528) (629:629:629)) + (PORT datac (650:650:650) (748:748:748)) + (PORT datad (918:918:918) (1051:1051:1051)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (1000:1000:1000)) + (PORT datab (528:528:528) (629:629:629)) + (PORT datac (963:963:963) (1090:1090:1090)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (666:666:666) (787:787:787)) + (PORT datac (899:899:899) (1036:1036:1036)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (854:854:854)) + (PORT datab (747:747:747) (855:855:855)) + (PORT datac (467:467:467) (550:550:550)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~99) + (DELAY + (ABSOLUTE + (PORT dataa (442:442:442) (512:512:512)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (645:645:645)) + (PORT datab (566:566:566) (642:642:642)) + (PORT datac (132:132:132) (169:169:169)) + (PORT datad (527:527:527) (607:607:607)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (374:374:374) (442:442:442)) + (PORT datac (127:127:127) (168:168:168)) + (PORT datad (186:186:186) (216:216:216)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (623:623:623)) + (PORT datab (519:519:519) (599:599:599)) + (PORT datac (435:435:435) (493:493:493)) + (PORT datad (491:491:491) (558:558:558)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (914:914:914)) + (PORT asdata (317:317:317) (356:356:356)) + (PORT clrn (911:911:911) (895:895:895)) + (PORT ena (780:780:780) (849:849:849)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (814:814:814)) + (PORT datab (474:474:474) (551:551:551)) + (PORT datac (470:470:470) (534:534:534)) + (PORT datad (1077:1077:1077) (1218:1218:1218)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|use_ixiy) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (659:659:659)) + (PORT datac (528:528:528) (621:621:621)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (752:752:752)) + (PORT datab (554:554:554) (663:663:663)) + (PORT datac (372:372:372) (440:440:440)) + (PORT datad (715:715:715) (832:832:832)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (563:563:563)) + (PORT datab (353:353:353) (408:408:408)) + (PORT datac (506:506:506) (589:589:589)) + (PORT datad (187:187:187) (217:217:217)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (745:745:745)) + (PORT datab (877:877:877) (1003:1003:1003)) + (PORT datac (330:330:330) (389:389:389)) + (PORT datad (608:608:608) (690:690:690)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (828:828:828)) + (PORT datab (254:254:254) (310:310:310)) + (PORT datac (945:945:945) (1090:1090:1090)) + (PORT datad (144:144:144) (179:179:179)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (258:258:258)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (602:602:602) (684:684:684)) + (PORT datad (107:107:107) (126:126:126)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (747:747:747)) + (PORT datab (301:301:301) (357:357:357)) + (PORT datac (600:600:600) (688:688:688)) + (PORT datad (164:164:164) (193:193:193)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (542:542:542)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (311:311:311) (362:362:362)) + (PORT datad (92:92:92) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (153:153:153)) + (PORT datab (342:342:342) (402:402:402)) + (PORT datac (101:101:101) (130:130:130)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (563:563:563)) + (PORT datab (611:611:611) (699:699:699)) + (PORT datac (785:785:785) (905:905:905)) + (PORT datad (506:506:506) (590:590:590)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (549:549:549)) + (PORT datab (512:512:512) (603:603:603)) + (PORT datac (547:547:547) (631:631:631)) + (PORT datad (615:615:615) (700:700:700)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (564:564:564)) + (PORT datab (472:472:472) (554:554:554)) + (PORT datac (616:616:616) (700:700:700)) + (PORT datad (169:169:169) (200:200:200)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (1032:1032:1032)) + (PORT datab (107:107:107) (136:136:136)) + (PORT datac (1068:1068:1068) (1218:1218:1218)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (793:793:793)) + (PORT datab (553:553:553) (655:655:655)) + (PORT datac (934:934:934) (1076:1076:1076)) + (PORT datad (653:653:653) (755:755:755)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (888:888:888)) + (PORT datab (611:611:611) (699:699:699)) + (PORT datac (570:570:570) (646:646:646)) + (PORT datad (171:171:171) (202:202:202)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (322:322:322) (366:366:366)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (374:374:374)) + (PORT datab (578:578:578) (680:680:680)) + (PORT datac (294:294:294) (344:344:344)) + (PORT datad (337:337:337) (390:390:390)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~48) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (583:583:583)) + (PORT datab (644:644:644) (749:749:749)) + (PORT datac (834:834:834) (982:982:982)) + (PORT datad (370:370:370) (429:429:429)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (743:743:743) (842:842:842)) + (PORT datab (463:463:463) (538:538:538)) + (PORT datac (592:592:592) (674:674:674)) + (PORT datad (103:103:103) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (600:600:600)) + (PORT datab (525:525:525) (628:628:628)) + (PORT datac (856:856:856) (976:976:976)) + (PORT datad (675:675:675) (763:763:763)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (469:469:469) (543:543:543)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (427:427:427) (493:493:493)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1359:1359:1359)) + (PORT datab (657:657:657) (756:756:756)) + (PORT datac (636:636:636) (734:734:734)) + (PORT datad (649:649:649) (747:747:747)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1406:1406:1406) (1620:1620:1620)) + (PORT datab (297:297:297) (343:343:343)) + (PORT datac (101:101:101) (121:121:121)) + (PORT datad (557:557:557) (639:639:639)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (1026:1026:1026)) + (PORT datab (477:477:477) (571:571:571)) + (PORT datac (582:582:582) (688:688:688)) + (PORT datad (438:438:438) (519:519:519)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (640:640:640)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (470:470:470) (561:561:561)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (463:463:463) (536:536:536)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (463:463:463) (549:549:549)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT datab (553:553:553) (643:643:643)) + (PORT datac (523:523:523) (610:610:610)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (581:581:581) (665:665:665)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (648:648:648) (731:731:731)) + (PORT d[1] (1411:1411:1411) (1666:1666:1666)) + (PORT d[2] (993:993:993) (1127:1127:1127)) + (PORT d[3] (570:570:570) (662:662:662)) + (PORT d[4] (1533:1533:1533) (1796:1796:1796)) + (PORT d[5] (2036:2036:2036) (2359:2359:2359)) + (PORT d[6] (588:588:588) (683:683:683)) + (PORT d[7] (1881:1881:1881) (2126:2126:2126)) + (PORT d[8] (688:688:688) (792:792:792)) + (PORT d[9] (574:574:574) (672:672:672)) + (PORT d[10] (753:753:753) (864:864:864)) + (PORT d[11] (1435:1435:1435) (1666:1666:1666)) + (PORT d[12] (744:744:744) (861:861:861)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (508:508:508) (530:530:530)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (920:920:920) (961:961:961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (397:397:397) (457:457:457)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (546:546:546) (622:622:622)) + (PORT d[1] (1745:1745:1745) (2043:2043:2043)) + (PORT d[2] (693:693:693) (795:795:795)) + (PORT d[3] (737:737:737) (857:857:857)) + (PORT d[4] (1511:1511:1511) (1768:1768:1768)) + (PORT d[5] (1749:1749:1749) (2050:2050:2050)) + (PORT d[6] (379:379:379) (434:434:434)) + (PORT d[7] (386:386:386) (446:446:446)) + (PORT d[8] (571:571:571) (657:657:657)) + (PORT d[9] (390:390:390) (452:452:452)) + (PORT d[10] (585:585:585) (673:673:673)) + (PORT d[11] (1495:1495:1495) (1741:1741:1741)) + (PORT d[12] (704:704:704) (811:811:811)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (536:536:536) (563:563:563)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (1141:1141:1141) (1215:1215:1215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (439:439:439)) + (PORT datab (358:358:358) (429:429:429)) + (PORT datac (429:429:429) (482:482:482)) + (PORT datad (479:479:479) (551:551:551)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (392:392:392) (449:449:449)) + (PORT clk (1096:1096:1096) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1810:1810:1810) (2056:2056:2056)) + (PORT d[1] (1721:1721:1721) (2012:2012:2012)) + (PORT d[2] (533:533:533) (613:613:613)) + (PORT d[3] (755:755:755) (880:880:880)) + (PORT d[4] (1533:1533:1533) (1796:1796:1796)) + (PORT d[5] (1573:1573:1573) (1841:1841:1841)) + (PORT d[6] (533:533:533) (609:609:609)) + (PORT d[7] (720:720:720) (823:823:823)) + (PORT d[8] (819:819:819) (944:944:944)) + (PORT d[9] (535:535:535) (619:619:619)) + (PORT d[10] (565:565:565) (652:652:652)) + (PORT d[11] (1679:1679:1679) (1958:1958:1958)) + (PORT d[12] (537:537:537) (624:624:624)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (691:691:691) (739:739:739)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1114:1114:1114)) + (PORT d[0] (1110:1110:1110) (1180:1180:1180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (408:408:408) (473:473:473)) + (PORT clk (1096:1096:1096) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1820:1820:1820) (2069:2069:2069)) + (PORT d[1] (1574:1574:1574) (1849:1849:1849)) + (PORT d[2] (717:717:717) (831:831:831)) + (PORT d[3] (756:756:756) (884:884:884)) + (PORT d[4] (1541:1541:1541) (1805:1805:1805)) + (PORT d[5] (1574:1574:1574) (1853:1853:1853)) + (PORT d[6] (692:692:692) (791:791:791)) + (PORT d[7] (625:625:625) (715:715:715)) + (PORT d[8] (837:837:837) (967:967:967)) + (PORT d[9] (877:877:877) (1007:1007:1007)) + (PORT d[10] (398:398:398) (459:459:459)) + (PORT d[11] (1680:1680:1680) (1954:1954:1954)) + (PORT d[12] (548:548:548) (636:636:636)) + (PORT clk (1094:1094:1094) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (690:690:690) (738:738:738)) + (PORT clk (1094:1094:1094) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1112:1112:1112)) + (PORT d[0] (1009:1009:1009) (1075:1075:1075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1091:1091:1091)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (803:803:803)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (547:547:547) (632:632:632)) + (PORT datad (621:621:621) (701:701:701)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (411:411:411) (475:475:475)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1643:1643:1643) (1872:1872:1872)) + (PORT d[1] (1390:1390:1390) (1638:1638:1638)) + (PORT d[2] (876:876:876) (1010:1010:1010)) + (PORT d[3] (1125:1125:1125) (1310:1310:1310)) + (PORT d[4] (1706:1706:1706) (2004:2004:2004)) + (PORT d[5] (1570:1570:1570) (1848:1848:1848)) + (PORT d[6] (730:730:730) (836:836:836)) + (PORT d[7] (750:750:750) (866:866:866)) + (PORT d[8] (999:999:999) (1150:1150:1150)) + (PORT d[9] (872:872:872) (1005:1005:1005)) + (PORT d[10] (1264:1264:1264) (1440:1440:1440)) + (PORT d[11] (1844:1844:1844) (2112:2112:2112)) + (PORT d[12] (729:729:729) (841:841:841)) + (PORT clk (1087:1087:1087) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1646:1646:1646) (1803:1803:1803)) + (PORT clk (1087:1087:1087) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (PORT d[0] (1744:1744:1744) (1905:1905:1905)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1044:1044:1044) (1064:1064:1064)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1177:1177:1177) (1330:1330:1330)) + (PORT clk (1049:1049:1049) (1067:1067:1067)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2414:2414:2414) (2742:2742:2742)) + (PORT d[1] (2309:2309:2309) (2604:2604:2604)) + (PORT d[2] (2377:2377:2377) (2705:2705:2705)) + (PORT d[3] (2410:2410:2410) (2738:2738:2738)) + (PORT d[4] (2388:2388:2388) (2717:2717:2717)) + (PORT d[5] (2415:2415:2415) (2707:2707:2707)) + (PORT d[6] (2588:2588:2588) (2951:2951:2951)) + (PORT d[7] (2446:2446:2446) (2756:2756:2756)) + (PORT d[8] (2454:2454:2454) (2760:2760:2760)) + (PORT d[9] (2548:2548:2548) (2918:2918:2918)) + (PORT d[10] (2469:2469:2469) (2774:2774:2774)) + (PORT d[11] (2511:2511:2511) (2836:2836:2836)) + (PORT d[12] (2491:2491:2491) (2835:2835:2835)) + (PORT clk (1046:1046:1046) (1066:1066:1066)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1438:1438:1438) (1631:1631:1631)) + (PORT d[1] (1172:1172:1172) (1379:1379:1379)) + (PORT d[2] (1335:1335:1335) (1563:1563:1563)) + (PORT d[3] (1428:1428:1428) (1670:1670:1670)) + (PORT d[4] (1729:1729:1729) (2027:2027:2027)) + (PORT d[5] (1311:1311:1311) (1534:1534:1534)) + (PORT d[6] (1094:1094:1094) (1246:1246:1246)) + (PORT d[7] (1420:1420:1420) (1623:1623:1623)) + (PORT d[8] (1591:1591:1591) (1868:1868:1868)) + (PORT d[9] (1016:1016:1016) (1161:1161:1161)) + (PORT d[10] (873:873:873) (992:992:992)) + (PORT d[11] (1938:1938:1938) (2221:2221:2221)) + (PORT d[12] (889:889:889) (1021:1021:1021)) + (PORT clk (1105:1105:1105) (1122:1122:1122)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1122:1122:1122)) + (PORT d[0] (1274:1274:1274) (1426:1426:1426)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1123:1123:1123)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1103:1103:1103)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (627:627:627) (635:635:635)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (847:847:847) (954:954:954)) + (PORT d[1] (1579:1579:1579) (1848:1848:1848)) + (PORT d[2] (553:553:553) (640:640:640)) + (PORT d[3] (947:947:947) (1108:1108:1108)) + (PORT d[4] (1531:1531:1531) (1791:1791:1791)) + (PORT d[5] (1588:1588:1588) (1867:1867:1867)) + (PORT d[6] (553:553:553) (632:632:632)) + (PORT d[7] (541:541:541) (622:622:622)) + (PORT d[8] (817:817:817) (941:941:941)) + (PORT d[9] (884:884:884) (1019:1019:1019)) + (PORT d[10] (1446:1446:1446) (1649:1649:1649)) + (PORT d[11] (1701:1701:1701) (1982:1982:1982)) + (PORT d[12] (715:715:715) (824:824:824)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT d[0] (546:546:546) (501:501:501)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1075:1075:1075) (1091:1091:1091)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (494:494:494) (554:554:554)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1800:1800:1800) (2048:2048:2048)) + (PORT d[1] (1566:1566:1566) (1841:1841:1841)) + (PORT d[2] (873:873:873) (1009:1009:1009)) + (PORT d[3] (961:961:961) (1116:1116:1116)) + (PORT d[4] (1712:1712:1712) (2007:2007:2007)) + (PORT d[5] (1587:1587:1587) (1867:1867:1867)) + (PORT d[6] (553:553:553) (633:633:633)) + (PORT d[7] (863:863:863) (998:998:998)) + (PORT d[8] (1771:1771:1771) (2072:2072:2072)) + (PORT d[9] (557:557:557) (646:646:646)) + (PORT d[10] (1448:1448:1448) (1654:1654:1654)) + (PORT d[11] (1688:1688:1688) (1963:1963:1963)) + (PORT d[12] (1278:1278:1278) (1473:1473:1473)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1724:1724:1724) (1898:1898:1898)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT d[0] (1046:1046:1046) (1015:1015:1015)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1067:1067:1067)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1342:1342:1342) (1511:1511:1511)) + (PORT clk (1053:1053:1053) (1070:1070:1070)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2545:2545:2545) (2890:2890:2890)) + (PORT d[1] (2355:2355:2355) (2682:2682:2682)) + (PORT d[2] (2365:2365:2365) (2686:2686:2686)) + (PORT d[3] (2422:2422:2422) (2765:2765:2765)) + (PORT d[4] (2372:2372:2372) (2696:2696:2696)) + (PORT d[5] (2509:2509:2509) (2830:2830:2830)) + (PORT d[6] (2634:2634:2634) (3005:3005:3005)) + (PORT d[7] (2483:2483:2483) (2824:2824:2824)) + (PORT d[8] (2457:2457:2457) (2761:2761:2761)) + (PORT d[9] (2566:2566:2566) (2937:2937:2937)) + (PORT d[10] (2510:2510:2510) (2831:2831:2831)) + (PORT d[11] (2433:2433:2433) (2735:2735:2735)) + (PORT d[12] (2433:2433:2433) (2739:2739:2739)) + (PORT clk (1050:1050:1050) (1069:1069:1069)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1053:1053:1053) (1070:1070:1070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1071:1071:1071)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1071:1071:1071)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1071:1071:1071)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1071:1071:1071)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1068:1068:1068)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (440:440:440)) + (PORT datab (638:638:638) (739:739:739)) + (PORT datac (453:453:453) (513:513:513)) + (PORT datad (481:481:481) (546:546:546)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (748:748:748)) + (PORT datab (638:638:638) (740:740:740)) + (PORT datac (870:870:870) (992:992:992)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~103) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (1137:1137:1137)) + (PORT datab (787:787:787) (919:919:919)) + (PORT datac (358:358:358) (424:424:424)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_DAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (477:477:477) (502:502:502)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (157:157:157) (218:218:218)) + (PORT datab (159:159:159) (214:214:214)) + (PORT datad (131:131:131) (175:175:175)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_CLK\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1960:1960:1960) (2226:2226:2226)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (901:901:901) (907:907:907)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (901:901:901) (907:907:907)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (124:124:124) (164:164:164)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (901:901:901) (907:907:907)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (901:901:901) (907:907:907)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (PORT datab (135:135:135) (186:186:186)) + (PORT datac (200:200:200) (245:245:245)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (123:123:123) (162:162:162)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (901:901:901) (907:907:907)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (125:125:125) (164:164:164)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (901:901:901) (907:907:907)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (901:901:901) (907:907:907)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (122:122:122) (164:164:164)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (123:123:123) (166:166:166)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (901:901:901) (907:907:907)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) + (DELAY + (ABSOLUTE + (PORT datab (108:108:108) (139:139:139)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (901:901:901) (907:907:907)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) + (DELAY + (ABSOLUTE + (PORT datab (109:109:109) (140:140:140)) + (PORT datac (119:119:119) (161:161:161)) + (PORT datad (121:121:121) (159:159:159)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (901:901:901) (907:907:907)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (908:908:908)) + (PORT ena (1092:1092:1092) (1217:1217:1217)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (218:218:218)) + (PORT datab (160:160:160) (214:214:214)) + (PORT datad (128:128:128) (170:170:170)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (908:908:908)) + (PORT ena (1092:1092:1092) (1217:1217:1217)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (153:153:153) (213:213:213)) + (PORT datab (152:152:152) (207:207:207)) + (PORT datad (132:132:132) (175:175:175)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (908:908:908)) + (PORT ena (1092:1092:1092) (1217:1217:1217)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (269:269:269)) + (PORT datab (153:153:153) (209:209:209)) + (PORT datad (133:133:133) (177:177:177)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (908:908:908)) + (PORT ena (1092:1092:1092) (1217:1217:1217)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (151:151:151) (210:210:210)) + (PORT datab (156:156:156) (210:210:210)) + (PORT datac (2001:2001:2001) (2280:2280:2280)) + (PORT datad (138:138:138) (182:182:182)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT datab (157:157:157) (212:212:212)) + (PORT datac (139:139:139) (189:189:189)) + (PORT datad (135:135:135) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (143:143:143) (196:196:196)) + (PORT datac (760:760:760) (876:876:876)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT asdata (2292:2292:2292) (2579:2579:2579)) + (PORT clrn (909:909:909) (914:914:914)) + (PORT ena (638:638:638) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT asdata (294:294:294) (333:333:333)) + (PORT clrn (909:909:909) (914:914:914)) + (PORT ena (638:638:638) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT asdata (320:320:320) (365:365:365)) + (PORT clrn (909:909:909) (914:914:914)) + (PORT ena (638:638:638) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT asdata (310:310:310) (352:352:352)) + (PORT clrn (909:909:909) (914:914:914)) + (PORT ena (638:638:638) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT asdata (499:499:499) (556:556:556)) + (PORT clrn (908:908:908) (914:914:914)) + (PORT ena (632:632:632) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT asdata (506:506:506) (568:568:568)) + (PORT clrn (909:909:909) (914:914:914)) + (PORT ena (638:638:638) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT asdata (499:499:499) (563:563:563)) + (PORT clrn (908:908:908) (914:914:914)) + (PORT ena (632:632:632) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT asdata (402:402:402) (464:464:464)) + (PORT clrn (908:908:908) (914:914:914)) + (PORT ena (632:632:632) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT asdata (405:405:405) (477:477:477)) + (PORT clrn (908:908:908) (914:914:914)) + (PORT ena (632:632:632) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (640:640:640)) + (PORT datab (370:370:370) (447:447:447)) + (PORT datac (426:426:426) (527:527:527)) + (PORT datad (425:425:425) (531:531:531)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (953:953:953)) + (PORT datab (514:514:514) (619:619:619)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (422:422:422) (528:528:528)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT datab (592:592:592) (716:716:716)) + (PORT datad (423:423:423) (484:484:484)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (413:413:413)) + (PORT datab (157:157:157) (211:211:211)) + (PORT datad (440:440:440) (513:513:513)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (492:492:492)) + (PORT datab (357:357:357) (432:432:432)) + (PORT datac (340:340:340) (413:413:413)) + (PORT datad (234:234:234) (292:292:292)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (433:433:433)) + (PORT datac (174:174:174) (210:210:210)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (141:141:141)) + (PORT datab (2011:2011:2011) (2305:2305:2305)) + (PORT datac (760:760:760) (876:876:876)) + (PORT datad (192:192:192) (226:226:226)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (908:908:908)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|extended) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (915:915:915)) + (PORT ena (933:933:933) (1038:1038:1038)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (PORT datab (359:359:359) (424:424:424)) + (PORT datac (142:142:142) (190:190:190)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (257:257:257) (316:316:316)) + (PORT datac (759:759:759) (914:914:914)) + (PORT datad (448:448:448) (517:517:517)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (771:771:771)) + (PORT datac (346:346:346) (412:412:412)) + (PORT datad (492:492:492) (585:585:585)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (246:246:246)) + (PORT datac (322:322:322) (381:381:381)) + (PORT datad (403:403:403) (480:480:480)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (427:427:427)) + (PORT datab (359:359:359) (423:423:423)) + (PORT datad (730:730:730) (836:836:836)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (328:328:328)) + (PORT datab (352:352:352) (427:427:427)) + (PORT datac (322:322:322) (387:387:387)) + (PORT datad (141:141:141) (183:183:183)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datac (221:221:221) (285:285:285)) + (PORT datad (347:347:347) (422:422:422)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (352:352:352)) + (PORT datab (227:227:227) (289:289:289)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (908:908:908) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (504:504:504)) + (PORT datab (538:538:538) (642:642:642)) + (PORT datad (526:526:526) (622:622:622)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT datab (419:419:419) (519:519:519)) + (PORT datac (410:410:410) (505:505:505)) + (PORT datad (414:414:414) (506:506:506)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (225:225:225)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (911:911:911) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (516:516:516) (623:623:623)) + (PORT datad (412:412:412) (504:504:504)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (492:492:492)) + (PORT datab (157:157:157) (211:211:211)) + (PORT datac (351:351:351) (426:426:426)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (421:421:421)) + (PORT datac (210:210:210) (264:264:264)) + (PORT datad (342:342:342) (420:420:420)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (240:240:240)) + (PORT datab (117:117:117) (150:150:150)) + (PORT datac (345:345:345) (419:419:419)) + (PORT datad (229:229:229) (286:286:286)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (119:119:119) (151:151:151)) + (PORT datab (343:343:343) (405:405:405)) + (PORT datad (525:525:525) (621:621:621)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (911:911:911) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (743:743:743)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datac (117:117:117) (158:158:158)) + (PORT datad (289:289:289) (337:337:337)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (633:633:633)) + (PORT datac (493:493:493) (593:593:593)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (950:950:950)) + (PORT datab (379:379:379) (444:444:444)) + (PORT datac (518:518:518) (616:616:616)) + (PORT datad (100:100:100) (122:122:122)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (536:536:536) (640:640:640)) + (PORT datac (405:405:405) (503:503:503)) + (PORT datad (413:413:413) (506:506:506)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (547:547:547)) + (PORT datab (349:349:349) (412:412:412)) + (PORT datad (259:259:259) (295:295:295)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (787:787:787) (948:948:948)) + (PORT datab (111:111:111) (143:143:143)) + (PORT datac (364:364:364) (422:422:422)) + (PORT datad (426:426:426) (532:532:532)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (490:490:490)) + (PORT datab (187:187:187) (226:226:226)) + (PORT datac (396:396:396) (487:487:487)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (1025:1025:1025)) + (PORT datab (521:521:521) (620:620:620)) + (PORT datad (268:268:268) (306:306:306)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~0) + (DELAY + (ABSOLUTE + (PORT datab (844:844:844) (993:993:993)) + (PORT datac (497:497:497) (594:594:594)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (227:227:227) (288:288:288)) + (PORT datac (605:605:605) (707:707:707)) + (PORT datad (347:347:347) (421:421:421)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (451:451:451)) + (PORT datab (217:217:217) (280:280:280)) + (PORT datac (322:322:322) (387:387:387)) + (PORT datad (141:141:141) (183:183:183)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (329:329:329)) + (PORT datab (353:353:353) (428:428:428)) + (PORT datac (259:259:259) (297:297:297)) + (PORT datad (349:349:349) (423:423:423)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (353:353:353)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (908:908:908) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (457:457:457)) + (PORT datab (668:668:668) (791:791:791)) + (PORT datac (229:229:229) (287:287:287)) + (PORT datad (580:580:580) (661:661:661)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (502:502:502)) + (PORT datab (777:777:777) (933:933:933)) + (PORT datac (489:489:489) (592:592:592)) + (PORT datad (461:461:461) (545:545:545)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (119:119:119) (156:156:156)) + (PORT datab (117:117:117) (145:145:145)) + (PORT datac (403:403:403) (499:499:499)) + (PORT datad (864:864:864) (1017:1017:1017)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (269:269:269) (309:309:309)) + (PORT datad (503:503:503) (596:596:596)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (434:434:434)) + (PORT datab (636:636:636) (744:744:744)) + (PORT datac (347:347:347) (415:415:415)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (450:450:450)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (313:313:313)) + (PORT datab (666:666:666) (789:789:789)) + (PORT datac (407:407:407) (504:504:504)) + (PORT datad (448:448:448) (518:518:518)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (523:523:523)) + (PORT datab (491:491:491) (586:586:586)) + (PORT datac (597:597:597) (701:701:701)) + (PORT datad (385:385:385) (471:471:471)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (226:226:226)) + (PORT datac (383:383:383) (467:467:467)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (518:518:518)) + (PORT datab (489:489:489) (584:584:584)) + (PORT datac (360:360:360) (437:437:437)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (419:419:419)) + (PORT datab (272:272:272) (339:339:339)) + (PORT datac (209:209:209) (264:264:264)) + (PORT datad (312:312:312) (367:367:367)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (562:562:562)) + (PORT datab (516:516:516) (621:621:621)) + (PORT datac (428:428:428) (529:529:529)) + (PORT datad (421:421:421) (528:528:528)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (555:555:555)) + (PORT datab (439:439:439) (541:541:541)) + (PORT datad (424:424:424) (530:530:530)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (558:558:558)) + (PORT datab (514:514:514) (619:619:619)) + (PORT datac (424:424:424) (525:525:525)) + (PORT datad (423:423:423) (529:529:529)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (155:155:155)) + (PORT datab (516:516:516) (622:622:622)) + (PORT datac (159:159:159) (192:192:192)) + (PORT datad (779:779:779) (929:929:929)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (954:954:954)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (508:508:508) (604:604:604)) + (PORT datad (264:264:264) (302:302:302)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (229:229:229)) + (PORT datab (147:147:147) (198:198:198)) + (PORT datad (328:328:328) (379:379:379)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (899:899:899)) + (PORT datab (211:211:211) (266:266:266)) + (PORT datac (770:770:770) (877:877:877)) + (PORT datad (305:305:305) (361:361:361)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (485:485:485)) + (PORT datab (1903:1903:1903) (2161:2161:2161)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (1064:1064:1064)) + (PORT datab (709:709:709) (818:818:818)) + (PORT datac (348:348:348) (407:407:407)) + (PORT datad (638:638:638) (725:725:725)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (997:997:997)) + (PORT datab (709:709:709) (819:819:819)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (721:721:721) (842:842:842)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (643:643:643)) + (PORT datab (346:346:346) (408:408:408)) + (PORT datac (129:129:129) (165:165:165)) + (PORT datad (944:944:944) (1074:1074:1074)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (500:500:500) (577:577:577)) + (PORT datac (517:517:517) (610:610:610)) + (PORT datad (119:119:119) (142:142:142)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (173:173:173)) + (PORT datab (378:378:378) (461:461:461)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (110:110:110) (131:131:131)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (103:103:103) (120:120:120)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (917:917:917) (902:902:902)) + (PORT ena (645:645:645) (697:697:697)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (157:157:157) (214:214:214)) + (PORT datac (501:501:501) (586:586:586)) + (PORT datad (505:505:505) (592:592:592)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (947:947:947)) + (PORT datab (481:481:481) (557:557:557)) + (PORT datac (501:501:501) (610:610:610)) + (PORT datad (468:468:468) (544:544:544)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (1034:1034:1034)) + (PORT datab (1302:1302:1302) (1480:1480:1480)) + (PORT datac (364:364:364) (432:432:432)) + (PORT datad (1513:1513:1513) (1746:1746:1746)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (122:122:122) (157:157:157)) + (PORT datac (101:101:101) (128:128:128)) + (PORT datad (195:195:195) (226:226:226)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (383:383:383)) + (PORT datab (230:230:230) (273:273:273)) + (PORT datac (290:290:290) (331:331:331)) + (PORT datad (651:651:651) (746:746:746)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (994:994:994)) + (PORT datab (229:229:229) (277:277:277)) + (PORT datac (519:519:519) (601:601:601)) + (PORT datad (112:112:112) (133:133:133)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (643:643:643)) + (PORT datab (627:627:627) (714:714:714)) + (PORT datac (714:714:714) (833:833:833)) + (PORT datad (756:756:756) (864:864:864)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (683:683:683)) + (PORT datab (552:552:552) (654:654:654)) + (PORT datac (716:716:716) (835:835:835)) + (PORT datad (697:697:697) (795:795:795)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (814:814:814) (919:919:919)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (461:461:461) (519:519:519)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (1001:1001:1001)) + (PORT datab (450:450:450) (525:525:525)) + (PORT datad (557:557:557) (632:632:632)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (1003:1003:1003)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (348:348:348) (413:413:413)) + (PORT datad (295:295:295) (338:338:338)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (399:399:399)) + (PORT datab (288:288:288) (333:333:333)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (193:193:193) (226:226:226)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1408:1408:1408)) + (PORT datab (883:883:883) (1032:1032:1032)) + (PORT datac (492:492:492) (577:577:577)) + (PORT datad (622:622:622) (713:713:713)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT datab (120:120:120) (155:155:155)) + (PORT datac (176:176:176) (209:209:209)) + (PORT datad (191:191:191) (224:224:224)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (829:829:829)) + (PORT datab (511:511:511) (600:600:600)) + (PORT datac (1119:1119:1119) (1312:1312:1312)) + (PORT datad (1169:1169:1169) (1381:1381:1381)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (553:553:553)) + (PORT datab (120:120:120) (155:155:155)) + (PORT datac (104:104:104) (132:132:132)) + (PORT datad (191:191:191) (223:223:223)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (721:721:721)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (117:117:117) (151:151:151)) + (PORT datac (105:105:105) (128:128:128)) + (PORT datad (120:120:120) (138:138:138)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1273:1273:1273)) + (PORT datab (1458:1458:1458) (1689:1689:1689)) + (PORT datad (811:811:811) (945:945:945)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (434:434:434)) + (PORT datab (383:383:383) (458:458:458)) + (PORT datac (593:593:593) (676:676:676)) + (PORT datad (358:358:358) (416:416:416)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (140:140:140)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (325:325:325) (382:382:382)) + (PORT datad (424:424:424) (480:480:480)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (539:539:539)) + (PORT datab (171:171:171) (208:208:208)) + (PORT datac (191:191:191) (228:228:228)) + (PORT datad (330:330:330) (383:383:383)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1014:1014:1014) (1196:1196:1196)) + (PORT datab (498:498:498) (595:595:595)) + (PORT datac (499:499:499) (608:608:608)) + (PORT datad (227:227:227) (269:269:269)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (583:583:583)) + (PORT datac (494:494:494) (563:563:563)) + (PORT datad (768:768:768) (891:891:891)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (257:257:257)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (759:759:759)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (310:310:310) (366:366:366)) + (PORT datad (190:190:190) (226:226:226)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (759:759:759)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (480:480:480) (559:559:559)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1338:1338:1338) (1530:1530:1530)) + (PORT datab (891:891:891) (1046:1046:1046)) + (PORT datac (1005:1005:1005) (1176:1176:1176)) + (PORT datad (938:938:938) (1076:1076:1076)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (942:942:942)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (585:585:585) (679:679:679)) + (PORT datad (727:727:727) (829:829:829)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (786:786:786)) + (PORT datac (490:490:490) (579:579:579)) + (PORT datad (531:531:531) (625:625:625)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (570:570:570)) + (PORT datab (528:528:528) (618:618:618)) + (PORT datac (310:310:310) (355:355:355)) + (PORT datad (282:282:282) (315:315:315)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (452:452:452) (520:520:520)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (100:100:100) (124:124:124)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (769:769:769)) + (PORT datab (139:139:139) (191:191:191)) + (PORT datac (116:116:116) (157:157:157)) + (PORT datad (318:318:318) (367:367:367)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) + (DELAY + (ABSOLUTE + (PORT dataa (303:303:303) (355:355:355)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (326:326:326) (377:377:377)) + (PORT datad (318:318:318) (359:359:359)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (1057:1057:1057)) + (PORT datab (1441:1441:1441) (1668:1668:1668)) + (PORT datac (584:584:584) (667:667:667)) + (PORT datad (486:486:486) (557:557:557)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (690:690:690)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (662:662:662) (752:752:752)) + (PORT datad (292:292:292) (331:331:331)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (552:552:552)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (128:128:128) (154:154:154)) + (PORT datad (319:319:319) (372:372:372)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (620:620:620)) + (PORT datab (143:143:143) (176:176:176)) + (PORT datac (778:778:778) (901:901:901)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (585:585:585)) + (PORT datab (613:613:613) (718:718:718)) + (PORT datac (497:497:497) (574:574:574)) + (PORT datad (550:550:550) (616:616:616)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (297:297:297)) + (PORT datab (484:484:484) (559:559:559)) + (PORT datac (499:499:499) (608:608:608)) + (PORT datad (218:218:218) (252:252:252)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT datab (582:582:582) (662:662:662)) + (PORT datac (110:110:110) (135:135:135)) + (PORT datad (110:110:110) (130:130:130)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (279:279:279) (322:322:322)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (309:309:309) (361:361:361)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (299:299:299) (346:346:346)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (448:448:448)) + (PORT datab (362:362:362) (431:431:431)) + (PORT datac (481:481:481) (550:550:550)) + (PORT datad (477:477:477) (548:548:548)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (629:629:629) (724:724:724)) + (PORT datad (336:336:336) (387:387:387)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (230:230:230)) + (PORT datab (344:344:344) (402:402:402)) + (PORT datac (476:476:476) (549:549:549)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (436:436:436)) + (PORT datab (513:513:513) (599:599:599)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (113:113:113) (137:137:137)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (460:460:460)) + (PORT datac (596:596:596) (699:699:699)) + (PORT datad (408:408:408) (499:499:499)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (524:524:524)) + (PORT datab (394:394:394) (484:484:484)) + (PORT datac (598:598:598) (701:701:701)) + (PORT datad (385:385:385) (471:471:471)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (493:493:493) (588:588:588)) + (PORT datac (597:597:597) (700:700:700)) + (PORT datad (172:172:172) (200:200:200)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (112:112:112) (148:148:148)) + (PORT datab (103:103:103) (132:132:132)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (482:482:482)) + (PORT datab (535:535:535) (638:638:638)) + (PORT datac (408:408:408) (506:506:506)) + (PORT datad (413:413:413) (505:505:505)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (545:545:545)) + (PORT datab (410:410:410) (500:500:500)) + (PORT datac (400:400:400) (487:487:487)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (224:224:224)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (171:171:171) (202:202:202)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (911:911:911) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (742:742:742)) + (PORT datab (392:392:392) (480:480:480)) + (PORT datac (116:116:116) (156:156:156)) + (PORT datad (290:290:290) (338:338:338)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (614:614:614)) + (PORT datab (430:430:430) (528:528:528)) + (PORT datac (758:758:758) (914:914:914)) + (PORT datad (644:644:644) (761:761:761)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (161:161:161) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~76) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (219:219:219)) + (PORT datab (153:153:153) (201:201:201)) + (PORT datac (517:517:517) (597:597:597)) + (PORT datad (839:839:839) (979:979:979)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT datac (406:406:406) (503:503:503)) + (PORT datad (647:647:647) (765:765:765)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (519:519:519)) + (PORT datab (397:397:397) (487:487:487)) + (PORT datac (477:477:477) (565:565:565)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (499:499:499)) + (PORT datab (846:846:846) (997:997:997)) + (PORT datac (491:491:491) (594:594:594)) + (PORT datad (459:459:459) (543:543:543)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~74) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (361:361:361)) + (PORT datab (174:174:174) (210:210:210)) + (PORT datac (756:756:756) (911:911:911)) + (PORT datad (864:864:864) (1017:1017:1017)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (234:234:234) (293:293:293)) + (PORT datad (448:448:448) (518:518:518)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (330:330:330)) + (PORT datab (171:171:171) (209:209:209)) + (PORT datad (404:404:404) (493:493:493)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (513:513:513)) + (PORT datab (404:404:404) (495:495:495)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (610:610:610) (712:712:712)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) + (DELAY + (ABSOLUTE + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (403:403:403) (484:484:484)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (257:257:257)) + (PORT datab (639:639:639) (748:748:748)) + (PORT datac (350:350:350) (419:419:419)) + (PORT datad (337:337:337) (404:404:404)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (1025:1025:1025)) + (PORT datab (520:520:520) (619:619:619)) + (PORT datad (267:267:267) (305:305:305)) + (IOPATH dataa combout (159:159:159) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (255:255:255) (330:330:330)) + (PORT datac (321:321:321) (387:387:387)) + (PORT datad (142:142:142) (184:184:184)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (243:243:243)) + (PORT datab (443:443:443) (515:515:515)) + (PORT datad (401:401:401) (491:491:491)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~1) + (DELAY + (ABSOLUTE + (PORT datab (845:845:845) (994:994:994)) + (PORT datac (181:181:181) (230:230:230)) + (PORT datad (489:489:489) (577:577:577)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (117:117:117) (158:158:158)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~1) + (DELAY + (ABSOLUTE + (PORT datac (598:598:598) (727:727:727)) + (PORT datad (577:577:577) (691:691:691)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (949:949:949)) + (PORT datab (437:437:437) (539:539:539)) + (PORT datac (518:518:518) (616:616:616)) + (PORT datad (420:420:420) (525:525:525)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (142:142:142)) + (PORT datab (359:359:359) (429:429:429)) + (PORT datac (321:321:321) (376:376:376)) + (PORT datad (487:487:487) (584:584:584)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) + (DELAY + (ABSOLUTE + (PORT datab (525:525:525) (630:630:630)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (915:915:915)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT datac (341:341:341) (415:415:415)) + (PORT datad (342:342:342) (406:406:406)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (418:418:418)) + (PORT datac (361:361:361) (461:461:461)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (249:249:249) (312:312:312)) + (PORT datac (343:343:343) (412:412:412)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (354:354:354) (429:429:429)) + (PORT datad (348:348:348) (423:423:423)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (541:541:541)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (280:280:280) (323:323:323)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (494:494:494)) + (PORT datad (503:503:503) (597:597:597)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (900:900:900)) + (PORT datab (311:311:311) (377:377:377)) + (PORT datac (770:770:770) (877:877:877)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (488:488:488)) + (PORT datab (1905:1905:1905) (2163:2163:2163)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (489:489:489) (554:554:554)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (692:692:692) (785:785:785)) + (PORT d[1] (555:555:555) (645:645:645)) + (PORT d[2] (539:539:539) (612:612:612)) + (PORT d[3] (570:570:570) (664:664:664)) + (PORT d[4] (1524:1524:1524) (1787:1787:1787)) + (PORT d[5] (567:567:567) (665:665:665)) + (PORT d[6] (566:566:566) (652:652:652)) + (PORT d[7] (538:538:538) (620:620:620)) + (PORT d[8] (582:582:582) (677:677:677)) + (PORT d[9] (556:556:556) (651:651:651)) + (PORT d[10] (600:600:600) (694:694:694)) + (PORT d[11] (1498:1498:1498) (1745:1745:1745)) + (PORT d[12] (743:743:743) (860:860:860)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (519:519:519) (547:547:547)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (809:809:809) (845:845:845)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (528:528:528) (606:606:606)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (388:388:388) (446:446:446)) + (PORT d[1] (1400:1400:1400) (1651:1651:1651)) + (PORT d[2] (850:850:850) (968:968:968)) + (PORT d[3] (558:558:558) (641:641:641)) + (PORT d[4] (1510:1510:1510) (1771:1771:1771)) + (PORT d[5] (2023:2023:2023) (2340:2340:2340)) + (PORT d[6] (729:729:729) (838:838:838)) + (PORT d[7] (1869:1869:1869) (2113:2113:2113)) + (PORT d[8] (377:377:377) (441:441:441)) + (PORT d[9] (912:912:912) (1053:1053:1053)) + (PORT d[10] (777:777:777) (894:894:894)) + (PORT d[11] (1301:1301:1301) (1515:1515:1515)) + (PORT d[12] (893:893:893) (1028:1028:1028)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (355:355:355) (356:356:356)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (800:800:800) (826:826:826)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (593:593:593) (668:668:668)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (539:539:539) (619:619:619)) + (PORT d[1] (2026:2026:2026) (2346:2346:2346)) + (PORT d[2] (705:705:705) (808:808:808)) + (PORT d[3] (715:715:715) (826:826:826)) + (PORT d[4] (1504:1504:1504) (1764:1764:1764)) + (PORT d[5] (2029:2029:2029) (2352:2352:2352)) + (PORT d[6] (754:754:754) (872:872:872)) + (PORT d[7] (692:692:692) (792:792:792)) + (PORT d[8] (552:552:552) (638:638:638)) + (PORT d[9] (891:891:891) (1024:1024:1024)) + (PORT d[10] (788:788:788) (909:909:909)) + (PORT d[11] (1310:1310:1310) (1527:1527:1527)) + (PORT d[12] (919:919:919) (1062:1062:1062)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (518:518:518) (544:544:544)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (912:912:912) (949:949:949)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (246:246:246)) + (PORT datab (355:355:355) (426:426:426)) + (PORT datac (352:352:352) (416:416:416)) + (PORT datad (349:349:349) (402:402:402)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (652:652:652) (746:746:746)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2062:2062:2062) (2392:2392:2392)) + (PORT d[1] (795:795:795) (938:938:938)) + (PORT d[2] (1144:1144:1144) (1312:1312:1312)) + (PORT d[3] (1386:1386:1386) (1609:1609:1609)) + (PORT d[4] (1274:1274:1274) (1480:1480:1480)) + (PORT d[5] (775:775:775) (917:917:917)) + (PORT d[6] (824:824:824) (954:954:954)) + (PORT d[7] (1952:1952:1952) (2204:2204:2204)) + (PORT d[8] (2104:2104:2104) (2435:2435:2435)) + (PORT d[9] (1815:1815:1815) (2090:2090:2090)) + (PORT d[10] (1826:1826:1826) (2094:2094:2094)) + (PORT d[11] (1007:1007:1007) (1167:1167:1167)) + (PORT d[12] (814:814:814) (935:935:935)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (890:890:890) (960:960:960)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1554:1554:1554) (1684:1684:1684)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (652:652:652)) + (PORT datab (785:785:785) (918:918:918)) + (PORT datac (276:276:276) (323:323:323)) + (PORT datad (654:654:654) (746:746:746)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (914:914:914) (1070:1070:1070)) + (PORT clk (1096:1096:1096) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1612:1612:1612) (1843:1843:1843)) + (PORT d[1] (1155:1155:1155) (1367:1367:1367)) + (PORT d[2] (1117:1117:1117) (1292:1292:1292)) + (PORT d[3] (1070:1070:1070) (1255:1255:1255)) + (PORT d[4] (1763:1763:1763) (2023:2023:2023)) + (PORT d[5] (1312:1312:1312) (1534:1534:1534)) + (PORT d[6] (982:982:982) (1126:1126:1126)) + (PORT d[7] (1219:1219:1219) (1414:1414:1414)) + (PORT d[8] (1382:1382:1382) (1622:1622:1622)) + (PORT d[9] (965:965:965) (1112:1112:1112)) + (PORT d[10] (820:820:820) (943:943:943)) + (PORT d[11] (960:960:960) (1098:1098:1098)) + (PORT d[12] (1308:1308:1308) (1499:1499:1499)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1425:1425:1425) (1591:1591:1591)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1114:1114:1114)) + (PORT d[0] (2282:2282:2282) (2098:2098:2098)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1051:1051:1051) (1071:1071:1071)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1117:1117:1117) (1240:1240:1240)) + (PORT clk (1056:1056:1056) (1074:1074:1074)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2452:2452:2452) (2784:2784:2784)) + (PORT d[1] (2314:2314:2314) (2623:2623:2623)) + (PORT d[2] (2389:2389:2389) (2699:2699:2699)) + (PORT d[3] (2550:2550:2550) (2907:2907:2907)) + (PORT d[4] (2364:2364:2364) (2679:2679:2679)) + (PORT d[5] (2568:2568:2568) (2916:2916:2916)) + (PORT d[6] (2462:2462:2462) (2816:2816:2816)) + (PORT d[7] (2364:2364:2364) (2657:2657:2657)) + (PORT d[8] (2551:2551:2551) (2900:2900:2900)) + (PORT d[9] (2545:2545:2545) (2918:2918:2918)) + (PORT d[10] (2631:2631:2631) (2982:2982:2982)) + (PORT d[11] (2413:2413:2413) (2724:2724:2724)) + (PORT d[12] (2561:2561:2561) (2915:2915:2915)) + (PORT clk (1053:1053:1053) (1073:1073:1073)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1056:1056:1056) (1074:1074:1074)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1072:1072:1072)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1588:1588:1588) (1816:1816:1816)) + (PORT d[1] (992:992:992) (1179:1179:1179)) + (PORT d[2] (1103:1103:1103) (1283:1283:1283)) + (PORT d[3] (1062:1062:1062) (1246:1246:1246)) + (PORT d[4] (1617:1617:1617) (1864:1864:1864)) + (PORT d[5] (1317:1317:1317) (1540:1540:1540)) + (PORT d[6] (1154:1154:1154) (1319:1319:1319)) + (PORT d[7] (1225:1225:1225) (1427:1427:1427)) + (PORT d[8] (1375:1375:1375) (1606:1606:1606)) + (PORT d[9] (1130:1130:1130) (1297:1297:1297)) + (PORT d[10] (1111:1111:1111) (1274:1274:1274)) + (PORT d[11] (1134:1134:1134) (1293:1293:1293)) + (PORT d[12] (1458:1458:1458) (1670:1670:1670)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT d[0] (1576:1576:1576) (1776:1776:1776)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1079:1079:1079) (1096:1096:1096)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (628:628:628)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (620:620:620) (629:629:629)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (620:620:620) (629:629:629)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (620:620:620) (629:629:629)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (906:906:906) (1058:1058:1058)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1607:1607:1607) (1841:1841:1841)) + (PORT d[1] (1178:1178:1178) (1395:1395:1395)) + (PORT d[2] (1073:1073:1073) (1246:1246:1246)) + (PORT d[3] (1061:1061:1061) (1246:1246:1246)) + (PORT d[4] (1778:1778:1778) (2032:2032:2032)) + (PORT d[5] (1152:1152:1152) (1354:1354:1354)) + (PORT d[6] (984:984:984) (1132:1132:1132)) + (PORT d[7] (1029:1029:1029) (1190:1190:1190)) + (PORT d[8] (1394:1394:1394) (1627:1627:1627)) + (PORT d[9] (1130:1130:1130) (1298:1298:1298)) + (PORT d[10] (1118:1118:1118) (1290:1290:1290)) + (PORT d[11] (1424:1424:1424) (1619:1619:1619)) + (PORT d[12] (1271:1271:1271) (1457:1457:1457)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1419:1419:1419) (1556:1556:1556)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1112:1112:1112)) + (PORT d[0] (2096:2096:2096) (2313:2313:2313)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1069:1069:1069)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1117:1117:1117) (1241:1241:1241)) + (PORT clk (1054:1054:1054) (1072:1072:1072)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2473:2473:2473) (2812:2812:2812)) + (PORT d[1] (2361:2361:2361) (2677:2677:2677)) + (PORT d[2] (2402:2402:2402) (2727:2727:2727)) + (PORT d[3] (2543:2543:2543) (2900:2900:2900)) + (PORT d[4] (2378:2378:2378) (2698:2698:2698)) + (PORT d[5] (2560:2560:2560) (2905:2905:2905)) + (PORT d[6] (2623:2623:2623) (2996:2996:2996)) + (PORT d[7] (2364:2364:2364) (2664:2664:2664)) + (PORT d[8] (2457:2457:2457) (2789:2789:2789)) + (PORT d[9] (2540:2540:2540) (2926:2926:2926)) + (PORT d[10] (2593:2593:2593) (2922:2922:2922)) + (PORT d[11] (2412:2412:2412) (2719:2719:2719)) + (PORT d[12] (2561:2561:2561) (2914:2914:2914)) + (PORT clk (1051:1051:1051) (1071:1071:1071)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1072:1072:1072)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1073:1073:1073)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (789:789:789)) + (PORT datab (803:803:803) (920:920:920)) + (PORT datac (624:624:624) (734:734:734)) + (PORT datad (798:798:798) (908:908:908)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2050:2050:2050) (2378:2378:2378)) + (PORT d[1] (1539:1539:1539) (1803:1803:1803)) + (PORT d[2] (930:930:930) (1089:1089:1089)) + (PORT d[3] (1196:1196:1196) (1398:1398:1398)) + (PORT d[4] (1249:1249:1249) (1444:1444:1444)) + (PORT d[5] (957:957:957) (1133:1133:1133)) + (PORT d[6] (636:636:636) (734:734:734)) + (PORT d[7] (650:650:650) (750:750:750)) + (PORT d[8] (1254:1254:1254) (1478:1478:1478)) + (PORT d[9] (1328:1328:1328) (1519:1519:1519)) + (PORT d[10] (1463:1463:1463) (1678:1678:1678)) + (PORT d[11] (502:502:502) (579:579:579)) + (PORT d[12] (986:986:986) (1140:1140:1140)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT d[0] (2202:2202:2202) (1954:1954:1954)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1086:1086:1086)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (763:763:763)) + (PORT datab (588:588:588) (669:669:669)) + (PORT datac (96:96:96) (121:121:121)) + (PORT datad (788:788:788) (884:884:884)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (986:986:986)) + (PORT datab (506:506:506) (601:601:601)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (465:465:465)) + (PORT datab (646:646:646) (769:769:769)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1282:1282:1282)) + (PORT datab (639:639:639) (743:743:743)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (454:454:454) (532:532:532)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (1114:1114:1114) (1284:1284:1284)) + (PORT datab (341:341:341) (410:410:410)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (884:884:884) (1007:1007:1007)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (648:648:648)) + (PORT datab (512:512:512) (593:593:593)) + (PORT datac (135:135:135) (172:172:172)) + (PORT datad (877:877:877) (993:993:993)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (211:211:211) (262:262:262)) + (PORT datad (359:359:359) (422:422:422)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (622:622:622)) + (PORT datab (735:735:735) (841:841:841)) + (PORT datac (505:505:505) (580:580:580)) + (PORT datad (489:489:489) (557:557:557)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (833:833:833) (925:925:925)) + (PORT clrn (915:915:915) (899:899:899)) + (PORT ena (784:784:784) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1318:1318:1318)) + (PORT datab (852:852:852) (1008:1008:1008)) + (PORT datac (123:123:123) (152:152:152)) + (PORT datad (617:617:617) (712:712:712)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (998:998:998)) + (PORT datab (837:837:837) (983:983:983)) + (PORT datac (1033:1033:1033) (1196:1196:1196)) + (PORT datad (211:211:211) (250:250:250)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (282:282:282)) + (PORT datab (380:380:380) (452:452:452)) + (PORT datac (820:820:820) (948:948:948)) + (PORT datad (730:730:730) (867:867:867)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (443:443:443)) + (PORT datac (629:629:629) (724:724:724)) + (PORT datad (495:495:495) (576:576:576)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (366:366:366) (433:433:433)) + (PORT datac (477:477:477) (551:551:551)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (322:322:322)) + (PORT datab (495:495:495) (569:569:569)) + (PORT datac (306:306:306) (352:352:352)) + (PORT datad (626:626:626) (722:722:722)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (406:406:406)) + (PORT datab (513:513:513) (599:599:599)) + (PORT datac (353:353:353) (420:420:420)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (571:571:571)) + (PORT datab (132:132:132) (167:167:167)) + (PORT datac (344:344:344) (405:405:405)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (518:518:518)) + (PORT datab (404:404:404) (495:495:495)) + (PORT datac (636:636:636) (744:744:744)) + (PORT datad (495:495:495) (588:588:588)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (432:432:432)) + (PORT datab (175:175:175) (210:210:210)) + (PORT datac (403:403:403) (491:491:491)) + (PORT datad (406:406:406) (506:506:506)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (545:545:545)) + (PORT datac (395:395:395) (479:479:479)) + (PORT datad (640:640:640) (745:745:745)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (305:305:305)) + (PORT datab (349:349:349) (423:423:423)) + (PORT datad (400:400:400) (477:477:477)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~136) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (338:338:338)) + (PORT datab (237:237:237) (296:296:296)) + (PORT datad (346:346:346) (420:420:420)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (450:450:450)) + (PORT datab (358:358:358) (422:422:422)) + (PORT datad (440:440:440) (514:514:514)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (548:548:548)) + (PORT datab (340:340:340) (399:399:399)) + (PORT datad (335:335:335) (383:383:383)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (469:469:469) (542:542:542)) + (PORT datab (466:466:466) (538:538:538)) + (PORT datac (329:329:329) (399:399:399)) + (PORT datad (347:347:347) (419:419:419)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (557:557:557)) + (PORT datab (380:380:380) (445:445:445)) + (PORT datac (517:517:517) (616:616:616)) + (PORT datad (775:775:775) (924:924:924)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (634:634:634)) + (PORT datab (435:435:435) (537:537:537)) + (PORT datac (493:493:493) (594:594:594)) + (PORT datad (427:427:427) (533:533:533)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (180:180:180) (220:220:220)) + (PORT datab (103:103:103) (133:133:133)) + (PORT datad (493:493:493) (582:582:582)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (383:383:383)) + (PORT datab (519:519:519) (623:623:623)) + (PORT datad (295:295:295) (337:337:337)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (915:915:915)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (1047:1047:1047)) + (PORT datac (414:414:414) (511:511:511)) + (PORT datad (387:387:387) (476:476:476)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (441:441:441)) + (PORT datab (669:669:669) (792:792:792)) + (PORT datac (493:493:493) (597:597:597)) + (PORT datad (172:172:172) (201:201:201)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (142:142:142)) + (PORT datab (521:521:521) (625:625:625)) + (PORT datad (179:179:179) (219:219:219)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (915:915:915)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (753:753:753) (856:856:856)) + (PORT datab (674:674:674) (793:793:793)) + (PORT datac (118:118:118) (160:160:160)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (307:307:307)) + (PORT datab (348:348:348) (422:422:422)) + (PORT datad (401:401:401) (478:478:478)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (351:351:351)) + (PORT datab (402:402:402) (496:496:496)) + (PORT datac (860:860:860) (1023:1023:1023)) + (PORT datad (317:317:317) (366:366:366)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (422:422:422)) + (PORT datab (416:416:416) (509:509:509)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~3) + (DELAY + (ABSOLUTE + (PORT datab (848:848:848) (999:999:999)) + (PORT datac (477:477:477) (571:571:571)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (256:256:256)) + (PORT datab (339:339:339) (392:392:392)) + (PORT datac (744:744:744) (860:860:860)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (548:548:548)) + (PORT datac (389:389:389) (472:472:472)) + (PORT datad (633:633:633) (736:736:736)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (772:772:772)) + (PORT datab (407:407:407) (498:498:498)) + (PORT datac (347:347:347) (413:413:413)) + (PORT datad (491:491:491) (584:584:584)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (235:235:235)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datad (96:96:96) (117:117:117)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (351:351:351)) + (PORT datab (188:188:188) (227:227:227)) + (PORT datad (403:403:403) (484:484:484)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (687:687:687)) + (PORT datab (643:643:643) (753:753:753)) + (PORT datac (342:342:342) (417:417:417)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (1015:1015:1015)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (91:91:91) (112:112:112)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1903:1903:1903) (2207:2207:2207)) + (PORT d[1] (924:924:924) (1081:1081:1081)) + (PORT d[2] (1394:1394:1394) (1602:1602:1602)) + (PORT d[3] (1060:1060:1060) (1235:1235:1235)) + (PORT d[4] (1100:1100:1100) (1278:1278:1278)) + (PORT d[5] (1202:1202:1202) (1421:1421:1421)) + (PORT d[6] (1313:1313:1313) (1508:1508:1508)) + (PORT d[7] (1246:1246:1246) (1411:1411:1411)) + (PORT d[8] (1678:1678:1678) (1943:1943:1943)) + (PORT d[9] (1275:1275:1275) (1470:1470:1470)) + (PORT d[10] (2344:2344:2344) (2687:2687:2687)) + (PORT d[11] (1008:1008:1008) (1166:1166:1166)) + (PORT d[12] (1364:1364:1364) (1560:1560:1560)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (1428:1428:1428) (1591:1591:1591)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (858:858:858) (978:978:978)) + (PORT clk (1087:1087:1087) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1958:1958:1958) (2237:2237:2237)) + (PORT d[1] (952:952:952) (1135:1135:1135)) + (PORT d[2] (1019:1019:1019) (1175:1175:1175)) + (PORT d[3] (1176:1176:1176) (1375:1375:1375)) + (PORT d[4] (1274:1274:1274) (1480:1480:1480)) + (PORT d[5] (965:965:965) (1137:1137:1137)) + (PORT d[6] (813:813:813) (936:936:936)) + (PORT d[7] (825:825:825) (950:950:950)) + (PORT d[8] (1671:1671:1671) (1934:1934:1934)) + (PORT d[9] (1320:1320:1320) (1511:1511:1511)) + (PORT d[10] (1313:1313:1313) (1512:1512:1512)) + (PORT d[11] (1209:1209:1209) (1403:1403:1403)) + (PORT d[12] (1130:1130:1130) (1305:1305:1305)) + (PORT clk (1085:1085:1085) (1103:1103:1103)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1619:1619:1619) (1787:1787:1787)) + (PORT clk (1085:1085:1085) (1103:1103:1103)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (PORT d[0] (2447:2447:2447) (2710:2710:2710)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1042:1042:1042) (1062:1062:1062)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (941:941:941) (1043:1043:1043)) + (PORT clk (1047:1047:1047) (1065:1065:1065)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2450:2450:2450) (2777:2777:2777)) + (PORT d[1] (2392:2392:2392) (2704:2704:2704)) + (PORT d[2] (2394:2394:2394) (2721:2721:2721)) + (PORT d[3] (2491:2491:2491) (2861:2861:2861)) + (PORT d[4] (2566:2566:2566) (2910:2910:2910)) + (PORT d[5] (2373:2373:2373) (2706:2706:2706)) + (PORT d[6] (2612:2612:2612) (2990:2990:2990)) + (PORT d[7] (2373:2373:2373) (2714:2714:2714)) + (PORT d[8] (2476:2476:2476) (2808:2808:2808)) + (PORT d[9] (2554:2554:2554) (2935:2935:2935)) + (PORT d[10] (2444:2444:2444) (2765:2765:2765)) + (PORT d[11] (2421:2421:2421) (2728:2728:2728)) + (PORT d[12] (2407:2407:2407) (2712:2712:2712)) + (PORT clk (1044:1044:1044) (1064:1064:1064)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2356:2356:2356) (2720:2720:2720)) + (PORT d[1] (1675:1675:1675) (1954:1954:1954)) + (PORT d[2] (1571:1571:1571) (1793:1793:1793)) + (PORT d[3] (1306:1306:1306) (1539:1539:1539)) + (PORT d[4] (1463:1463:1463) (1705:1705:1705)) + (PORT d[5] (1474:1474:1474) (1713:1713:1713)) + (PORT d[6] (1093:1093:1093) (1258:1258:1258)) + (PORT d[7] (1344:1344:1344) (1523:1523:1523)) + (PORT d[8] (1807:1807:1807) (2124:2124:2124)) + (PORT d[9] (1492:1492:1492) (1734:1734:1734)) + (PORT d[10] (2804:2804:2804) (3207:3207:3207)) + (PORT d[11] (1095:1095:1095) (1275:1275:1275)) + (PORT d[12] (1289:1289:1289) (1483:1483:1483)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (2275:2275:2275) (2058:2058:2058)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (876:876:876) (1020:1020:1020)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1688:1688:1688) (1964:1964:1964)) + (PORT d[1] (1334:1334:1334) (1569:1569:1569)) + (PORT d[2] (1223:1223:1223) (1416:1416:1416)) + (PORT d[3] (1064:1064:1064) (1252:1252:1252)) + (PORT d[4] (1419:1419:1419) (1629:1629:1629)) + (PORT d[5] (1143:1143:1143) (1344:1344:1344)) + (PORT d[6] (986:986:986) (1130:1130:1130)) + (PORT d[7] (1372:1372:1372) (1582:1582:1582)) + (PORT d[8] (1652:1652:1652) (1914:1914:1914)) + (PORT d[9] (1153:1153:1153) (1324:1324:1324)) + (PORT d[10] (1141:1141:1141) (1317:1317:1317)) + (PORT d[11] (1383:1383:1383) (1601:1601:1601)) + (PORT d[12] (1451:1451:1451) (1660:1660:1660)) + (PORT clk (1086:1086:1086) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1453:1453:1453) (1609:1609:1609)) + (PORT clk (1086:1086:1086) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT d[0] (2488:2488:2488) (2278:2278:2278)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1043:1043:1043) (1063:1063:1063)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1108:1108:1108) (1228:1228:1228)) + (PORT clk (1048:1048:1048) (1066:1066:1066)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2443:2443:2443) (2777:2777:2777)) + (PORT d[1] (2372:2372:2372) (2684:2684:2684)) + (PORT d[2] (2405:2405:2405) (2732:2732:2732)) + (PORT d[3] (2484:2484:2484) (2833:2833:2833)) + (PORT d[4] (2401:2401:2401) (2725:2725:2725)) + (PORT d[5] (2571:2571:2571) (2915:2915:2915)) + (PORT d[6] (2478:2478:2478) (2831:2831:2831)) + (PORT d[7] (2422:2422:2422) (2757:2757:2757)) + (PORT d[8] (2472:2472:2472) (2808:2808:2808)) + (PORT d[9] (2555:2555:2555) (2931:2931:2931)) + (PORT d[10] (2414:2414:2414) (2717:2717:2717)) + (PORT d[11] (2582:2582:2582) (2920:2920:2920)) + (PORT d[12] (2506:2506:2506) (2850:2850:2850)) + (PORT clk (1045:1045:1045) (1065:1065:1065)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1044:1044:1044) (1064:1064:1064)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (757:757:757)) + (PORT datab (501:501:501) (596:596:596)) + (PORT datac (785:785:785) (890:890:890)) + (PORT datad (804:804:804) (913:913:913)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (849:849:849)) + (PORT datab (508:508:508) (603:603:603)) + (PORT datac (801:801:801) (924:924:924)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (496:496:496) (569:569:569)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1898:1898:1898) (2205:2205:2205)) + (PORT d[1] (1002:1002:1002) (1185:1185:1185)) + (PORT d[2] (1140:1140:1140) (1304:1304:1304)) + (PORT d[3] (1203:1203:1203) (1403:1403:1403)) + (PORT d[4] (1057:1057:1057) (1219:1219:1219)) + (PORT d[5] (774:774:774) (921:921:921)) + (PORT d[6] (820:820:820) (948:948:948)) + (PORT d[7] (1963:1963:1963) (2216:2216:2216)) + (PORT d[8] (1431:1431:1431) (1674:1674:1674)) + (PORT d[9] (2015:2015:2015) (2327:2327:2327)) + (PORT d[10] (1692:1692:1692) (1948:1948:1948)) + (PORT d[11] (827:827:827) (959:959:959)) + (PORT d[12] (830:830:830) (960:960:960)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1893:1893:1893) (2093:2093:2093)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (1046:1046:1046) (1116:1116:1116)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1088:1088:1088)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (828:828:828) (944:944:944)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2082:2082:2082) (2419:2419:2419)) + (PORT d[1] (977:977:977) (1152:1152:1152)) + (PORT d[2] (1908:1908:1908) (2182:2182:2182)) + (PORT d[3] (1200:1200:1200) (1400:1400:1400)) + (PORT d[4] (1473:1473:1473) (1710:1710:1710)) + (PORT d[5] (973:973:973) (1145:1145:1145)) + (PORT d[6] (1035:1035:1035) (1202:1202:1202)) + (PORT d[7] (970:970:970) (1112:1112:1112)) + (PORT d[8] (1931:1931:1931) (2242:2242:2242)) + (PORT d[9] (1624:1624:1624) (1868:1868:1868)) + (PORT d[10] (2021:2021:2021) (2323:2323:2323)) + (PORT d[11] (1010:1010:1010) (1172:1172:1172)) + (PORT d[12] (1004:1004:1004) (1151:1151:1151)) + (PORT clk (1080:1080:1080) (1098:1098:1098)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1078:1078:1078) (1178:1178:1178)) + (PORT clk (1080:1080:1080) (1098:1098:1098)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1082:1082:1082) (1100:1100:1100)) + (PORT d[0] (1538:1538:1538) (1677:1677:1677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1062:1062:1062) (1079:1079:1079)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (602:602:602) (611:611:611)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (696:696:696) (802:802:802)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1891:1891:1891) (2200:2200:2200)) + (PORT d[1] (764:764:764) (903:903:903)) + (PORT d[2] (1115:1115:1115) (1298:1298:1298)) + (PORT d[3] (861:861:861) (1007:1007:1007)) + (PORT d[4] (1071:1071:1071) (1242:1242:1242)) + (PORT d[5] (927:927:927) (1087:1087:1087)) + (PORT d[6] (665:665:665) (775:775:775)) + (PORT d[7] (836:836:836) (960:960:960)) + (PORT d[8] (1455:1455:1455) (1707:1707:1707)) + (PORT d[9] (2011:2011:2011) (2318:2318:2318)) + (PORT d[10] (1658:1658:1658) (1903:1903:1903)) + (PORT d[11] (696:696:696) (800:800:800)) + (PORT d[12] (623:623:623) (719:719:719)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1641:1641:1641) (1814:1814:1814)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (1828:1828:1828) (2013:2013:2013)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1002:1002:1002) (1135:1135:1135)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1907:1907:1907) (2218:2218:2218)) + (PORT d[1] (982:982:982) (1157:1157:1157)) + (PORT d[2] (1569:1569:1569) (1801:1801:1801)) + (PORT d[3] (1205:1205:1205) (1398:1398:1398)) + (PORT d[4] (1266:1266:1266) (1475:1475:1475)) + (PORT d[5] (1387:1387:1387) (1637:1637:1637)) + (PORT d[6] (1227:1227:1227) (1424:1424:1424)) + (PORT d[7] (1427:1427:1427) (1617:1617:1617)) + (PORT d[8] (1747:1747:1747) (2037:2037:2037)) + (PORT d[9] (1449:1449:1449) (1675:1675:1675)) + (PORT d[10] (2215:2215:2215) (2545:2545:2545)) + (PORT d[11] (992:992:992) (1149:1149:1149)) + (PORT d[12] (1348:1348:1348) (1543:1543:1543)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1269:1269:1269) (1391:1391:1391)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1504:1504:1504) (1616:1616:1616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (962:962:962) (1111:1111:1111)) + (PORT datab (660:660:660) (745:745:745)) + (PORT datad (964:964:964) (1091:1091:1091)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (962:962:962)) + (PORT datab (834:834:834) (948:948:948)) + (PORT datac (1159:1159:1159) (1329:1329:1329)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (465:465:465)) + (PORT datab (646:646:646) (769:769:769)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (562:562:562)) + (PORT datab (877:877:877) (1025:1025:1025)) + (PORT datac (833:833:833) (962:962:962)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (768:768:768)) + (PORT datab (898:898:898) (1028:1028:1028)) + (PORT datac (834:834:834) (963:963:963)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (641:641:641)) + (PORT datab (817:817:817) (925:925:925)) + (PORT datac (126:126:126) (162:162:162)) + (PORT datad (642:642:642) (729:729:729)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (265:265:265)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (356:356:356) (418:418:418)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (624:624:624)) + (PORT datab (504:504:504) (580:580:580)) + (PORT datac (503:503:503) (577:577:577)) + (PORT datad (492:492:492) (560:560:560)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (911:911:911) (895:895:895)) + (PORT ena (780:780:780) (849:849:849)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~0) + (DELAY + (ABSOLUTE + (PORT datac (814:814:814) (956:956:956)) + (PORT datad (835:835:835) (972:972:972)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (756:756:756) (873:873:873)) + (PORT datab (538:538:538) (635:635:635)) + (PORT datac (913:913:913) (1096:1096:1096)) + (PORT datad (690:690:690) (800:800:800)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (731:731:731) (854:854:854)) + (PORT datab (861:861:861) (1001:1001:1001)) + (PORT datac (440:440:440) (506:506:506)) + (PORT datad (106:106:106) (124:124:124)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT datab (853:853:853) (1003:1003:1003)) + (PORT datac (752:752:752) (882:882:882)) + (PORT datad (1442:1442:1442) (1705:1705:1705)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (551:551:551)) + (PORT datab (488:488:488) (576:576:576)) + (PORT datac (944:944:944) (1100:1100:1100)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (265:265:265)) + (PORT datab (667:667:667) (778:778:778)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (594:594:594)) + (PORT datab (340:340:340) (405:405:405)) + (PORT datac (484:484:484) (567:567:567)) + (PORT datad (482:482:482) (551:551:551)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1103:1103:1103) (1266:1266:1266)) + (PORT datab (609:609:609) (706:706:706)) + (PORT datac (460:460:460) (531:531:531)) + (PORT datad (349:349:349) (411:411:411)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (315:315:315) (367:367:367)) + (PORT datac (278:278:278) (323:323:323)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (1032:1032:1032)) + (PORT datab (468:468:468) (544:544:544)) + (PORT datac (835:835:835) (945:945:945)) + (PORT datad (577:577:577) (648:648:648)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (384:384:384)) + (PORT datab (478:478:478) (556:556:556)) + (PORT datac (459:459:459) (532:532:532)) + (PORT datad (670:670:670) (781:781:781)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (689:689:689) (767:767:767)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (120:120:120) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (912:912:912)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (704:704:704) (789:789:789)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (912:912:912)) + (PORT asdata (299:299:299) (341:341:341)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (704:704:704) (789:789:789)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (459:459:459) (532:532:532)) + (PORT datab (182:182:182) (225:225:225)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1142:1142:1142)) + (PORT datab (897:897:897) (1062:1062:1062)) + (PORT datac (653:653:653) (769:769:769)) + (PORT datad (683:683:683) (799:799:799)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (657:657:657) (743:743:743)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2376:2376:2376) (2743:2743:2743)) + (PORT d[1] (1673:1673:1673) (1949:1949:1949)) + (PORT d[2] (1859:1859:1859) (2120:2120:2120)) + (PORT d[3] (1457:1457:1457) (1704:1704:1704)) + (PORT d[4] (1308:1308:1308) (1532:1532:1532)) + (PORT d[5] (1495:1495:1495) (1741:1741:1741)) + (PORT d[6] (1079:1079:1079) (1242:1242:1242)) + (PORT d[7] (1355:1355:1355) (1538:1538:1538)) + (PORT d[8] (1818:1818:1818) (2136:2136:2136)) + (PORT d[9] (1647:1647:1647) (1909:1909:1909)) + (PORT d[10] (2810:2810:2810) (3210:3210:3210)) + (PORT d[11] (1259:1259:1259) (1464:1464:1464)) + (PORT d[12] (1279:1279:1279) (1469:1469:1469)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1104:1104:1104) (1196:1196:1196)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (1283:1283:1283) (1376:1376:1376)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1074:1074:1074) (1090:1090:1090)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (614:614:614) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (667:667:667) (755:755:755)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2370:2370:2370) (2737:2737:2737)) + (PORT d[1] (1682:1682:1682) (1961:1961:1961)) + (PORT d[2] (1599:1599:1599) (1830:1830:1830)) + (PORT d[3] (1456:1456:1456) (1704:1704:1704)) + (PORT d[4] (1317:1317:1317) (1545:1545:1545)) + (PORT d[5] (1481:1481:1481) (1721:1721:1721)) + (PORT d[6] (1111:1111:1111) (1275:1275:1275)) + (PORT d[7] (1341:1341:1341) (1517:1517:1517)) + (PORT d[8] (1821:1821:1821) (2141:2141:2141)) + (PORT d[9] (1479:1479:1479) (1716:1716:1716)) + (PORT d[10] (2803:2803:2803) (3202:3202:3202)) + (PORT d[11] (1087:1087:1087) (1266:1266:1266)) + (PORT d[12] (1288:1288:1288) (1482:1482:1482)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1335:1335:1335) (1450:1450:1450)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (1595:1595:1595) (1711:1711:1711)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1092:1092:1092)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (490:490:490) (554:554:554)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (756:756:756) (870:870:870)) + (PORT d[1] (1184:1184:1184) (1400:1400:1400)) + (PORT d[2] (1753:1753:1753) (2001:2001:2001)) + (PORT d[3] (1487:1487:1487) (1749:1749:1749)) + (PORT d[4] (1499:1499:1499) (1753:1753:1753)) + (PORT d[5] (1655:1655:1655) (1919:1919:1919)) + (PORT d[6] (1127:1127:1127) (1303:1303:1303)) + (PORT d[7] (1522:1522:1522) (1724:1724:1724)) + (PORT d[8] (1982:1982:1982) (2322:2322:2322)) + (PORT d[9] (1666:1666:1666) (1930:1930:1930)) + (PORT d[10] (2976:2976:2976) (3402:3402:3402)) + (PORT d[11] (1099:1099:1099) (1284:1284:1284)) + (PORT d[12] (1108:1108:1108) (1277:1277:1277)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (692:692:692) (734:734:734)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (1395:1395:1395) (1506:1506:1506)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (912:912:912)) + (PORT datab (518:518:518) (617:617:617)) + (PORT datac (611:611:611) (694:694:694)) + (PORT datad (462:462:462) (525:525:525)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (657:657:657) (752:752:752)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1900:1900:1900) (2210:2210:2210)) + (PORT d[1] (990:990:990) (1167:1167:1167)) + (PORT d[2] (1735:1735:1735) (1988:1988:1988)) + (PORT d[3] (1232:1232:1232) (1433:1433:1433)) + (PORT d[4] (1437:1437:1437) (1671:1671:1671)) + (PORT d[5] (1395:1395:1395) (1645:1645:1645)) + (PORT d[6] (1220:1220:1220) (1416:1416:1416)) + (PORT d[7] (1434:1434:1434) (1624:1624:1624)) + (PORT d[8] (1748:1748:1748) (2034:2034:2034)) + (PORT d[9] (1434:1434:1434) (1651:1651:1651)) + (PORT d[10] (2203:2203:2203) (2532:2532:2532)) + (PORT d[11] (965:965:965) (1112:1112:1112)) + (PORT d[12] (1353:1353:1353) (1550:1550:1550)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1241:1241:1241) (1352:1352:1352)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (1519:1519:1519) (1646:1646:1646)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1086:1086:1086)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (914:914:914)) + (PORT datab (635:635:635) (736:736:736)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (807:807:807) (907:907:907)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (969:969:969) (1123:1123:1123)) + (PORT clk (1083:1083:1083) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1865:1865:1865) (2172:2172:2172)) + (PORT d[1] (1358:1358:1358) (1599:1599:1599)) + (PORT d[2] (1247:1247:1247) (1438:1438:1438)) + (PORT d[3] (1075:1075:1075) (1261:1261:1261)) + (PORT d[4] (1421:1421:1421) (1634:1634:1634)) + (PORT d[5] (1142:1142:1142) (1347:1347:1347)) + (PORT d[6] (807:807:807) (930:930:930)) + (PORT d[7] (834:834:834) (959:959:959)) + (PORT d[8] (1664:1664:1664) (1927:1927:1927)) + (PORT d[9] (1154:1154:1154) (1325:1325:1325)) + (PORT d[10] (1129:1129:1129) (1298:1298:1298)) + (PORT d[11] (789:789:789) (907:907:907)) + (PORT d[12] (1148:1148:1148) (1322:1322:1322)) + (PORT clk (1081:1081:1081) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1601:1601:1601) (1763:1763:1763)) + (PORT clk (1081:1081:1081) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1102:1102:1102)) + (PORT d[0] (2271:2271:2271) (2510:2510:2510)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1038:1038:1038) (1059:1059:1059)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (654:654:654) (722:722:722)) + (PORT clk (1043:1043:1043) (1062:1062:1062)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2436:2436:2436) (2780:2780:2780)) + (PORT d[1] (2375:2375:2375) (2685:2685:2685)) + (PORT d[2] (2392:2392:2392) (2718:2718:2718)) + (PORT d[3] (2528:2528:2528) (2881:2881:2881)) + (PORT d[4] (2391:2391:2391) (2711:2711:2711)) + (PORT d[5] (2412:2412:2412) (2738:2738:2738)) + (PORT d[6] (2618:2618:2618) (2985:2985:2985)) + (PORT d[7] (2437:2437:2437) (2782:2782:2782)) + (PORT d[8] (2483:2483:2483) (2820:2820:2820)) + (PORT d[9] (2692:2692:2692) (3085:3085:3085)) + (PORT d[10] (2446:2446:2446) (2770:2770:2770)) + (PORT d[11] (2402:2402:2402) (2710:2710:2710)) + (PORT d[12] (2596:2596:2596) (2931:2931:2931)) + (PORT clk (1040:1040:1040) (1061:1061:1061)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1043:1043:1043) (1062:1062:1062)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1044:1044:1044) (1063:1063:1063)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1044:1044:1044) (1063:1063:1063)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1044:1044:1044) (1063:1063:1063)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1044:1044:1044) (1063:1063:1063)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1451:1451:1451) (1655:1655:1655)) + (PORT d[1] (1198:1198:1198) (1420:1420:1420)) + (PORT d[2] (1305:1305:1305) (1527:1527:1527)) + (PORT d[3] (1317:1317:1317) (1517:1517:1517)) + (PORT d[4] (1725:1725:1725) (2024:2024:2024)) + (PORT d[5] (1210:1210:1210) (1433:1433:1433)) + (PORT d[6] (1075:1075:1075) (1227:1227:1227)) + (PORT d[7] (1440:1440:1440) (1645:1645:1645)) + (PORT d[8] (1584:1584:1584) (1869:1869:1869)) + (PORT d[9] (893:893:893) (1030:1030:1030)) + (PORT d[10] (1067:1067:1067) (1215:1215:1215)) + (PORT d[11] (1632:1632:1632) (1870:1870:1870)) + (PORT d[12] (881:881:881) (1013:1013:1013)) + (PORT clk (1103:1103:1103) (1121:1121:1121)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1121:1121:1121)) + (PORT d[0] (1263:1263:1263) (1416:1416:1416)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1104:1104:1104) (1122:1122:1122)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1102:1102:1102)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (625:625:625) (634:634:634)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (626:626:626) (635:635:635)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (626:626:626) (635:635:635)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (626:626:626) (635:635:635)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2011:2011:2011) (2313:2313:2313)) + (PORT d[1] (987:987:987) (1165:1165:1165)) + (PORT d[2] (1558:1558:1558) (1787:1787:1787)) + (PORT d[3] (1194:1194:1194) (1385:1385:1385)) + (PORT d[4] (1098:1098:1098) (1286:1286:1286)) + (PORT d[5] (1372:1372:1372) (1616:1616:1616)) + (PORT d[6] (1346:1346:1346) (1556:1556:1556)) + (PORT d[7] (1416:1416:1416) (1605:1605:1605)) + (PORT d[8] (1556:1556:1556) (1811:1811:1811)) + (PORT d[9] (1412:1412:1412) (1625:1625:1625)) + (PORT d[10] (2235:2235:2235) (2571:2571:2571)) + (PORT d[11] (1016:1016:1016) (1179:1179:1179)) + (PORT d[12] (1382:1382:1382) (1587:1587:1587)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (1590:1590:1590) (1427:1427:1427)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1088:1088:1088)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (936:936:936) (1083:1083:1083)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1645:1645:1645) (1877:1877:1877)) + (PORT d[1] (1382:1382:1382) (1630:1630:1630)) + (PORT d[2] (1485:1485:1485) (1730:1730:1730)) + (PORT d[3] (1144:1144:1144) (1334:1334:1334)) + (PORT d[4] (1707:1707:1707) (2004:2004:2004)) + (PORT d[5] (1389:1389:1389) (1638:1638:1638)) + (PORT d[6] (1065:1065:1065) (1219:1219:1219)) + (PORT d[7] (939:939:939) (1085:1085:1085)) + (PORT d[8] (1741:1741:1741) (2030:2030:2030)) + (PORT d[9] (699:699:699) (802:802:802)) + (PORT d[10] (1255:1255:1255) (1430:1430:1430)) + (PORT d[11] (2096:2096:2096) (2391:2391:2391)) + (PORT d[12] (1086:1086:1086) (1248:1248:1248)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1554:1554:1554) (1710:1710:1710)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (1889:1889:1889) (1754:1754:1754)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1071:1071:1071)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1217:1217:1217) (1382:1382:1382)) + (PORT clk (1057:1057:1057) (1074:1074:1074)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2540:2540:2540) (2882:2882:2882)) + (PORT d[1] (2318:2318:2318) (2609:2609:2609)) + (PORT d[2] (2339:2339:2339) (2654:2654:2654)) + (PORT d[3] (2599:2599:2599) (2954:2954:2954)) + (PORT d[4] (2392:2392:2392) (2719:2719:2719)) + (PORT d[5] (2428:2428:2428) (2730:2730:2730)) + (PORT d[6] (2583:2583:2583) (2943:2943:2943)) + (PORT d[7] (2268:2268:2268) (2562:2562:2562)) + (PORT d[8] (2620:2620:2620) (2939:2939:2939)) + (PORT d[9] (2601:2601:2601) (2982:2982:2982)) + (PORT d[10] (2462:2462:2462) (2771:2771:2771)) + (PORT d[11] (2504:2504:2504) (2828:2828:2828)) + (PORT d[12] (2488:2488:2488) (2807:2807:2807)) + (PORT clk (1054:1054:1054) (1073:1073:1073)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1074:1074:1074)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) (DELAY (ABSOLUTE (PORT clk (1053:1053:1053) (1072:1072:1072)) @@ -36098,28 +44336,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector6\~0) + (INSTANCE Mux0\~0) (DELAY (ABSOLUTE - (PORT dataa (659:659:659) (762:762:762)) - (PORT datab (344:344:344) (392:392:392)) - (PORT datad (531:531:531) (608:608:608)) - (IOPATH dataa combout (188:188:188) (193:193:193)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (798:798:798) (926:926:926)) + (PORT datab (532:532:532) (633:633:633)) + (PORT datac (791:791:791) (901:901:901)) + (PORT datad (781:781:781) (900:900:900)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~70) + (INSTANCE Mux0\~1) (DELAY (ABSOLUTE - (PORT dataa (492:492:492) (566:566:566)) - (PORT datab (402:402:402) (491:491:491)) - (PORT datac (565:565:565) (631:631:631)) - (PORT datad (319:319:319) (371:371:371)) + (PORT dataa (841:841:841) (994:994:994)) + (PORT datab (530:530:530) (632:632:632)) + (PORT datac (833:833:833) (959:959:959)) + (PORT datad (90:90:90) (108:108:108)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (169:169:169) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -36129,20 +44368,5925 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~71) + (INSTANCE D\[7\]\~112) (DELAY (ABSOLUTE - (PORT dataa (412:412:412) (469:469:469)) - (PORT datab (476:476:476) (549:549:549)) - (PORT datac (825:825:825) (973:973:973)) + (PORT dataa (826:826:826) (971:971:971)) + (PORT datab (666:666:666) (787:787:787)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (854:854:854)) + (PORT datab (484:484:484) (576:576:576)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (729:729:729) (831:831:831)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~102) + (DELAY + (ABSOLUTE + (PORT datac (100:100:100) (121:121:121)) + (PORT datad (430:430:430) (487:487:487)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (616:616:616)) + (PORT datab (121:121:121) (152:152:152)) + (PORT datac (125:125:125) (161:161:161)) + (PORT datad (480:480:480) (551:551:551)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (638:638:638) (735:735:735)) + (PORT datac (527:527:527) (622:622:622)) + (PORT datad (193:193:193) (224:224:224)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (197:197:197)) + (PORT datab (377:377:377) (445:445:445)) + (PORT datac (457:457:457) (523:523:523)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (285:285:285) (306:306:306)) + (PORT clrn (918:918:918) (903:903:903)) + (PORT ena (800:800:800) (873:873:873)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (483:483:483)) + (PORT datab (684:684:684) (818:818:818)) + (PORT datac (539:539:539) (638:638:638)) + (PORT datad (758:758:758) (907:907:907)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (463:463:463)) + (PORT datab (553:553:553) (661:661:661)) + (PORT datac (624:624:624) (727:727:727)) + (PORT datad (648:648:648) (766:766:766)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (470:470:470)) + (PORT datab (197:197:197) (244:244:244)) + (PORT datac (595:595:595) (689:689:689)) + (PORT datad (962:962:962) (1116:1116:1116)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (628:628:628)) + (PORT datab (625:625:625) (719:719:719)) + (PORT datac (611:611:611) (714:714:714)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (1112:1112:1112)) + (PORT datab (590:590:590) (722:722:722)) + (PORT datac (677:677:677) (795:795:795)) + (PORT datad (620:620:620) (714:714:714)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (962:962:962) (1108:1108:1108)) + (PORT datab (197:197:197) (244:244:244)) + (PORT datac (865:865:865) (1010:1010:1010)) + (PORT datad (607:607:607) (695:695:695)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (124:124:124) (158:158:158)) + (PORT datab (585:585:585) (684:684:684)) + (PORT datac (601:601:601) (700:700:700)) + (PORT datad (605:605:605) (686:686:686)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (551:551:551)) + (PORT datab (821:821:821) (960:960:960)) + (PORT datac (435:435:435) (510:510:510)) + (PORT datad (467:467:467) (542:542:542)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT datac (600:600:600) (730:730:730)) + (PORT datad (576:576:576) (691:691:691)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (250:250:250)) + (PORT datab (524:524:524) (628:628:628)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (915:915:915)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (158:158:158)) + (PORT datab (424:424:424) (522:522:522)) + (PORT datac (757:757:757) (913:913:913)) + (PORT datad (864:864:864) (1018:1018:1018)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (178:178:178) (219:219:219)) + (PORT datab (116:116:116) (144:144:144)) + (PORT datad (406:406:406) (496:496:496)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1321:1321:1321) (1555:1555:1555)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datac (303:303:303) (362:362:362)) + (PORT datad (707:707:707) (810:810:810)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (521:521:521) (629:629:629)) + (PORT datad (414:414:414) (506:506:506)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (342:342:342) (405:405:405)) + (PORT datad (525:525:525) (620:620:620)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (911:911:911) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (329:329:329)) + (PORT datab (353:353:353) (428:428:428)) + (PORT datac (321:321:321) (387:387:387)) + (PORT datad (398:398:398) (474:474:474)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~131) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (308:308:308)) + (PORT datab (176:176:176) (216:216:216)) + (PORT datad (141:141:141) (183:183:183)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (548:548:548)) + (PORT datab (575:575:575) (662:662:662)) + (PORT datad (336:336:336) (383:383:383)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (737:737:737)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datac (298:298:298) (357:357:357)) + (PORT datad (293:293:293) (342:342:342)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT datac (601:601:601) (730:730:730)) + (PORT datad (575:575:575) (689:689:689)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (161:161:161)) + (PORT datab (199:199:199) (234:234:234)) + (PORT datac (489:489:489) (592:592:592)) + (PORT datad (169:169:169) (198:198:198)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT datab (527:527:527) (632:632:632)) + (PORT datad (172:172:172) (203:203:203)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (915:915:915)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (252:252:252)) + (PORT datab (528:528:528) (632:632:632)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (915:915:915)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (131:131:131) (180:180:180)) + (PORT datac (296:296:296) (342:342:342)) + (PORT datad (291:291:291) (332:332:332)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (523:523:523) (627:627:627)) + (PORT datab (445:445:445) (548:548:548)) + (PORT datac (498:498:498) (598:598:598)) + (PORT datad (422:422:422) (528:528:528)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (226:226:226)) + (PORT datab (397:397:397) (494:494:494)) + (PORT datad (311:311:311) (362:362:362)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (150:150:150)) + (PORT datab (106:106:106) (135:135:135)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT datac (134:134:134) (177:177:177)) + (PORT datad (440:440:440) (513:513:513)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (450:450:450)) + (PORT datab (179:179:179) (219:219:219)) + (PORT datac (346:346:346) (420:420:420)) + (PORT datad (340:340:340) (404:404:404)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (248:248:248) (310:310:310)) + (PORT datac (188:188:188) (220:220:220)) + (PORT datad (104:104:104) (127:127:127)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (486:486:486)) + (PORT datab (269:269:269) (336:336:336)) + (PORT datac (300:300:300) (353:353:353)) (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (507:507:507)) + (PORT datab (428:428:428) (525:525:525)) + (PORT datad (523:523:523) (618:618:618)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (211:211:211)) + (PORT datad (344:344:344) (402:402:402)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (1056:1056:1056)) + (PORT datab (322:322:322) (390:390:390)) + (PORT datac (601:601:601) (690:690:690)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (339:339:339) (397:397:397)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (312:312:312) (363:363:363)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~104) + (DELAY + (ABSOLUTE + (PORT datab (674:674:674) (795:795:795)) + (PORT datac (364:364:364) (433:433:433)) + (PORT datad (776:776:776) (881:881:881)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (515:515:515) (582:582:582)) + (PORT clk (1087:1087:1087) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (756:756:756) (869:869:869)) + (PORT d[1] (1131:1131:1131) (1346:1346:1346)) + (PORT d[2] (1781:1781:1781) (2038:2038:2038)) + (PORT d[3] (1638:1638:1638) (1913:1913:1913)) + (PORT d[4] (1489:1489:1489) (1740:1740:1740)) + (PORT d[5] (1662:1662:1662) (1928:1928:1928)) + (PORT d[6] (1114:1114:1114) (1285:1285:1285)) + (PORT d[7] (1518:1518:1518) (1718:1718:1718)) + (PORT d[8] (1996:1996:1996) (2341:2341:2341)) + (PORT d[9] (919:919:919) (1060:1060:1060)) + (PORT d[10] (2974:2974:2974) (3396:3396:3396)) + (PORT d[11] (1099:1099:1099) (1281:1281:1281)) + (PORT d[12] (1107:1107:1107) (1276:1276:1276)) + (PORT clk (1085:1085:1085) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (686:686:686) (730:730:730)) + (PORT clk (1085:1085:1085) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1106:1106:1106)) + (PORT d[0] (1382:1382:1382) (1484:1484:1484)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (383:383:383) (431:431:431)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (701:701:701) (805:805:805)) + (PORT d[1] (1229:1229:1229) (1458:1458:1458)) + (PORT d[2] (713:713:713) (805:805:805)) + (PORT d[3] (726:726:726) (840:840:840)) + (PORT d[4] (1534:1534:1534) (1791:1791:1791)) + (PORT d[5] (2015:2015:2015) (2334:2334:2334)) + (PORT d[6] (770:770:770) (891:891:891)) + (PORT d[7] (1699:1699:1699) (1922:1922:1922)) + (PORT d[8] (552:552:552) (633:633:633)) + (PORT d[9] (736:736:736) (855:855:855)) + (PORT d[10] (789:789:789) (910:910:910)) + (PORT d[11] (1418:1418:1418) (1644:1644:1644)) + (PORT d[12] (926:926:926) (1070:1070:1070)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (534:534:534) (564:564:564)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (811:811:811) (848:848:848)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1092:1092:1092)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (515:515:515) (584:584:584)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (758:758:758) (875:875:875)) + (PORT d[1] (1852:1852:1852) (2153:2153:2153)) + (PORT d[2] (2023:2023:2023) (2302:2302:2302)) + (PORT d[3] (1638:1638:1638) (1914:1914:1914)) + (PORT d[4] (1483:1483:1483) (1743:1743:1743)) + (PORT d[5] (1676:1676:1676) (1948:1948:1948)) + (PORT d[6] (967:967:967) (1121:1121:1121)) + (PORT d[7] (864:864:864) (987:987:987)) + (PORT d[8] (2007:2007:2007) (2356:2356:2356)) + (PORT d[9] (1837:1837:1837) (2124:2124:2124)) + (PORT d[10] (2979:2979:2979) (3401:3401:3401)) + (PORT d[11] (1122:1122:1122) (1311:1311:1311)) + (PORT d[12] (1098:1098:1098) (1263:1263:1263)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (944:944:944) (1020:1020:1020)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (1118:1118:1118) (1193:1193:1193)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (619:619:619) (707:707:707)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2084:2084:2084) (2418:2418:2418)) + (PORT d[1] (974:974:974) (1149:1149:1149)) + (PORT d[2] (1121:1121:1121) (1283:1283:1283)) + (PORT d[3] (1195:1195:1195) (1397:1397:1397)) + (PORT d[4] (1263:1263:1263) (1466:1466:1466)) + (PORT d[5] (793:793:793) (940:940:940)) + (PORT d[6] (850:850:850) (989:989:989)) + (PORT d[7] (1005:1005:1005) (1152:1152:1152)) + (PORT d[8] (2103:2103:2103) (2435:2435:2435)) + (PORT d[9] (1804:1804:1804) (2075:2075:2075)) + (PORT d[10] (1840:1840:1840) (2114:2114:2114)) + (PORT d[11] (1182:1182:1182) (1363:1363:1363)) + (PORT d[12] (815:815:815) (935:935:935)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (914:914:914) (988:988:988)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (1497:1497:1497) (1612:1612:1612)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1086:1086:1086)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (623:623:623)) + (PORT datab (629:629:629) (737:737:737)) + (PORT datac (452:452:452) (516:516:516)) + (PORT datad (577:577:577) (637:637:637)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (711:711:711)) + (PORT datab (899:899:899) (1055:1055:1055)) + (PORT datac (625:625:625) (722:722:722)) + (PORT datad (160:160:160) (186:186:186)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1711:1711:1711) (1985:1985:1985)) + (PORT d[1] (1692:1692:1692) (1969:1969:1969)) + (PORT d[2] (951:951:951) (1114:1114:1114)) + (PORT d[3] (838:838:838) (978:978:978)) + (PORT d[4] (1077:1077:1077) (1247:1247:1247)) + (PORT d[5] (774:774:774) (919:919:919)) + (PORT d[6] (631:631:631) (730:730:730)) + (PORT d[7] (846:846:846) (976:976:976)) + (PORT d[8] (1434:1434:1434) (1682:1682:1682)) + (PORT d[9] (2200:2200:2200) (2538:2538:2538)) + (PORT d[10] (1484:1484:1484) (1701:1701:1701)) + (PORT d[11] (1006:1006:1006) (1165:1165:1165)) + (PORT d[12] (1141:1141:1141) (1316:1316:1316)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (720:720:720) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (908:908:908) (1039:1039:1039)) + (PORT clk (1102:1102:1102) (1119:1119:1119)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1462:1462:1462) (1666:1666:1666)) + (PORT d[1] (1206:1206:1206) (1428:1428:1428)) + (PORT d[2] (1461:1461:1461) (1705:1705:1705)) + (PORT d[3] (1294:1294:1294) (1499:1499:1499)) + (PORT d[4] (1739:1739:1739) (2032:2032:2032)) + (PORT d[5] (1231:1231:1231) (1457:1457:1457)) + (PORT d[6] (916:916:916) (1046:1046:1046)) + (PORT d[7] (1592:1592:1592) (1814:1814:1814)) + (PORT d[8] (1611:1611:1611) (1895:1895:1895)) + (PORT d[9] (1199:1199:1199) (1367:1367:1367)) + (PORT d[10] (1075:1075:1075) (1225:1225:1225)) + (PORT d[11] (2079:2079:2079) (2374:2374:2374)) + (PORT d[12] (1066:1066:1066) (1228:1228:1228)) + (PORT clk (1100:1100:1100) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1776:1776:1776) (1945:1945:1945)) + (PORT clk (1100:1100:1100) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1102:1102:1102) (1119:1119:1119)) + (PORT d[0] (1621:1621:1621) (1764:1764:1764)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1076:1076:1076)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1215:1215:1215) (1378:1378:1378)) + (PORT clk (1062:1062:1062) (1079:1079:1079)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2485:2485:2485) (2804:2804:2804)) + (PORT d[1] (2412:2412:2412) (2731:2731:2731)) + (PORT d[2] (2546:2546:2546) (2889:2889:2889)) + (PORT d[3] (2481:2481:2481) (2823:2823:2823)) + (PORT d[4] (2356:2356:2356) (2667:2667:2667)) + (PORT d[5] (2416:2416:2416) (2742:2742:2742)) + (PORT d[6] (2567:2567:2567) (2926:2926:2926)) + (PORT d[7] (2254:2254:2254) (2544:2544:2544)) + (PORT d[8] (2452:2452:2452) (2774:2774:2774)) + (PORT d[9] (2619:2619:2619) (3004:3004:3004)) + (PORT d[10] (2502:2502:2502) (2822:2822:2822)) + (PORT d[11] (2565:2565:2565) (2889:2889:2889)) + (PORT d[12] (2495:2495:2495) (2818:2818:2818)) + (PORT clk (1059:1059:1059) (1078:1078:1078)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1062:1062:1062) (1079:1079:1079)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1063:1063:1063) (1080:1080:1080)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1063:1063:1063) (1080:1080:1080)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1063:1063:1063) (1080:1080:1080)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1063:1063:1063) (1080:1080:1080)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (738:738:738) (852:852:852)) + (PORT datab (151:151:151) (204:204:204)) + (PORT datac (754:754:754) (847:847:847)) + (PORT datad (835:835:835) (953:953:953)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (892:892:892) (1016:1016:1016)) + (PORT clk (1106:1106:1106) (1124:1124:1124)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1300:1300:1300) (1471:1471:1471)) + (PORT d[1] (1184:1184:1184) (1402:1402:1402)) + (PORT d[2] (1329:1329:1329) (1558:1558:1558)) + (PORT d[3] (1296:1296:1296) (1525:1525:1525)) + (PORT d[4] (1717:1717:1717) (2015:2015:2015)) + (PORT d[5] (1375:1375:1375) (1630:1630:1630)) + (PORT d[6] (1087:1087:1087) (1239:1239:1239)) + (PORT d[7] (1420:1420:1420) (1618:1618:1618)) + (PORT d[8] (1816:1816:1816) (2139:2139:2139)) + (PORT d[9] (1026:1026:1026) (1177:1177:1177)) + (PORT d[10] (1040:1040:1040) (1180:1180:1180)) + (PORT d[11] (1650:1650:1650) (1901:1901:1901)) + (PORT d[12] (1068:1068:1068) (1234:1234:1234)) + (PORT clk (1104:1104:1104) (1122:1122:1122)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1222:1222:1222) (1331:1331:1331)) + (PORT clk (1104:1104:1104) (1122:1122:1122)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (PORT d[0] (1921:1921:1921) (1784:1784:1784)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1125:1125:1125)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1061:1061:1061) (1081:1081:1081)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1396:1396:1396) (1583:1583:1583)) + (PORT clk (1066:1066:1066) (1084:1084:1084)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2485:2485:2485) (2802:2802:2802)) + (PORT d[1] (2296:2296:2296) (2585:2585:2585)) + (PORT d[2] (2499:2499:2499) (2826:2826:2826)) + (PORT d[3] (2489:2489:2489) (2856:2856:2856)) + (PORT d[4] (2486:2486:2486) (2819:2819:2819)) + (PORT d[5] (2590:2590:2590) (2938:2938:2938)) + (PORT d[6] (2582:2582:2582) (2952:2952:2952)) + (PORT d[7] (2284:2284:2284) (2579:2579:2579)) + (PORT d[8] (2592:2592:2592) (2930:2930:2930)) + (PORT d[9] (2569:2569:2569) (2938:2938:2938)) + (PORT d[10] (2524:2524:2524) (2834:2834:2834)) + (PORT d[11] (2504:2504:2504) (2829:2829:2829)) + (PORT d[12] (2553:2553:2553) (2895:2895:2895)) + (PORT clk (1063:1063:1063) (1083:1083:1083)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1066:1066:1066) (1084:1084:1084)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1085:1085:1085)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1085:1085:1085)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1085:1085:1085)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1085:1085:1085)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1062:1062:1062) (1082:1082:1082)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (556:556:556) (637:637:637)) + (PORT d[1] (542:542:542) (629:629:629)) + (PORT d[2] (685:685:685) (787:787:787)) + (PORT d[3] (734:734:734) (855:855:855)) + (PORT d[4] (1524:1524:1524) (1788:1788:1788)) + (PORT d[5] (1750:1750:1750) (2051:2051:2051)) + (PORT d[6] (544:544:544) (626:626:626)) + (PORT d[7] (730:730:730) (835:835:835)) + (PORT d[8] (580:580:580) (669:669:669)) + (PORT d[9] (534:534:534) (619:619:619)) + (PORT d[10] (745:745:745) (856:856:856)) + (PORT d[11] (1492:1492:1492) (1736:1736:1736)) + (PORT d[12] (729:729:729) (842:842:842)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (356:356:356) (332:332:332)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (786:786:786)) + (PORT datab (482:482:482) (556:556:556)) + (PORT datac (468:468:468) (545:545:545)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (155:155:155) (208:208:208)) + (PORT datac (901:901:901) (1024:1024:1024)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (503:503:503) (592:592:592)) + (PORT datac (652:652:652) (768:768:768)) + (PORT datad (311:311:311) (358:358:358)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (237:237:237)) + (PORT datab (125:125:125) (156:156:156)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (288:288:288)) + (PORT datab (125:125:125) (156:156:156)) + (PORT datac (613:613:613) (702:702:702)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (638:638:638)) + (PORT datab (345:345:345) (406:406:406)) + (PORT datac (317:317:317) (356:356:356)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (652:652:652) (703:703:703)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (493:493:493) (580:580:580)) + (PORT datac (518:518:518) (611:611:611)) + (PORT datad (117:117:117) (140:140:140)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (286:286:286)) + (PORT datab (125:125:125) (158:158:158)) + (PORT datac (122:122:122) (151:151:151)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (917:917:917) (902:902:902)) + (PORT ena (645:645:645) (697:697:697)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT datac (811:811:811) (946:946:946)) + (PORT datad (1279:1279:1279) (1475:1475:1475)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (594:594:594)) + (PORT datab (535:535:535) (622:622:622)) + (PORT datac (916:916:916) (1100:1100:1100)) + (PORT datad (695:695:695) (806:806:806)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (104:104:104) (128:128:128)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (525:525:525)) + (PORT datab (1139:1139:1139) (1322:1322:1322)) + (PORT datac (717:717:717) (840:840:840)) + (PORT datad (595:595:595) (674:674:674)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (928:928:928) (910:910:910)) + (PORT ena (890:890:890) (972:972:972)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (786:786:786)) + (PORT datab (1137:1137:1137) (1320:1320:1320)) + (PORT datac (723:723:723) (853:853:853)) + (PORT datad (1052:1052:1052) (1203:1203:1203)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (924:924:924) (906:906:906)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (186:186:186)) + (PORT datad (124:124:124) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (927:927:927) (908:908:908)) + (PORT ena (1086:1086:1086) (1232:1232:1232)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (PORT datac (600:600:600) (695:695:695)) + (PORT datad (605:605:605) (699:699:699)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (927:927:927) (908:908:908)) + (PORT ena (1086:1086:1086) (1232:1232:1232)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x3) + (DELAY + (ABSOLUTE + (PORT dataa (1330:1330:1330) (1557:1557:1557)) + (PORT datac (130:130:130) (172:172:172)) + (PORT datad (763:763:763) (913:913:913)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (1092:1092:1092) (1064:1064:1064)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (903:903:903) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (927:927:927) (908:908:908)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (720:720:720)) + (PORT datab (152:152:152) (205:205:205)) + (PORT datad (607:607:607) (702:702:702)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (927:927:927) (908:908:908)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~3) + (DELAY + (ABSOLUTE + (PORT datac (595:595:595) (716:716:716)) + (PORT datad (1126:1126:1126) (1302:1302:1302)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (951:951:951)) + (PORT datab (464:464:464) (536:536:536)) + (PORT datac (431:431:431) (489:489:489)) + (PORT datad (364:364:364) (427:427:427)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (656:656:656)) + (PORT datab (359:359:359) (422:422:422)) + (PORT datac (531:531:531) (627:627:627)) + (PORT datad (1266:1266:1266) (1455:1455:1455)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (547:547:547)) + (PORT datab (452:452:452) (517:517:517)) + (PORT datac (520:520:520) (602:602:602)) + (PORT datad (212:212:212) (253:253:253)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (435:435:435)) + (PORT datab (171:171:171) (208:208:208)) + (PORT datac (833:833:833) (964:964:964)) + (PORT datad (1187:1187:1187) (1363:1363:1363)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (243:243:243)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1287:1287:1287)) + (PORT datab (467:467:467) (544:544:544)) + (PORT datac (786:786:786) (909:909:909)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (157:157:157)) + (PORT datab (125:125:125) (157:157:157)) + (PORT datac (180:180:180) (218:218:218)) + (PORT datad (582:582:582) (648:648:648)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (124:124:124) (158:158:158)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (554:554:554) (656:656:656)) + (PORT datad (428:428:428) (489:489:489)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT datab (602:602:602) (697:697:697)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (161:161:161) (190:190:190)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT datac (411:411:411) (470:470:470)) + (PORT datad (333:333:333) (382:382:382)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~5) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (139:139:139)) + (PORT datab (1136:1136:1136) (1298:1298:1298)) + (PORT datac (345:345:345) (408:408:408)) + (PORT datad (173:173:173) (194:194:194)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (508:508:508)) + (PORT datab (478:478:478) (557:557:557)) + (PORT datac (564:564:564) (640:640:640)) + (PORT datad (281:281:281) (321:321:321)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT datab (147:147:147) (198:198:198)) + (PORT datac (596:596:596) (691:691:691)) + (PORT datad (609:609:609) (703:703:703)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (927:927:927) (908:908:908)) + (PORT ena (1086:1086:1086) (1232:1232:1232)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (715:715:715)) + (PORT datac (133:133:133) (177:177:177)) + (PORT datad (611:611:611) (706:706:706)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (927:927:927) (908:908:908)) + (PORT ena (1086:1086:1086) (1232:1232:1232)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT datab (143:143:143) (191:191:191)) + (PORT datac (589:589:589) (684:684:684)) + (PORT datad (614:614:614) (709:709:709)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (927:927:927) (908:908:908)) + (PORT ena (1086:1086:1086) (1232:1232:1232)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (367:367:367)) + (PORT datab (483:483:483) (558:558:558)) + (PORT datac (325:325:325) (377:377:377)) + (PORT datad (510:510:510) (594:594:594)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal77\~1) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (695:695:695)) + (PORT datab (658:658:658) (767:767:767)) + (PORT datac (372:372:372) (439:439:439)) + (PORT datad (717:717:717) (834:834:834)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (431:431:431)) + (PORT datab (915:915:915) (1053:1053:1053)) + (PORT datac (469:469:469) (544:544:544)) + (PORT datad (464:464:464) (535:535:535)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~14) + (DELAY + (ABSOLUTE + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (352:352:352) (408:408:408)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~41) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (260:260:260)) + (PORT datac (576:576:576) (672:672:672)) + (PORT datad (108:108:108) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (599:599:599)) + (PORT datab (614:614:614) (734:734:734)) + (PORT datac (216:216:216) (266:266:266)) + (PORT datad (1392:1392:1392) (1611:1611:1611)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1358:1358:1358)) + (PORT datab (437:437:437) (524:524:524)) + (PORT datac (526:526:526) (610:610:610)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (557:557:557)) + (PORT datab (184:184:184) (223:223:223)) + (PORT datac (108:108:108) (131:131:131)) + (PORT datad (406:406:406) (458:458:458)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (230:230:230)) + (PORT datab (586:586:586) (660:660:660)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (729:729:729) (821:821:821)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (707:707:707)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (105:105:105) (128:128:128)) + (PORT datad (95:95:95) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (453:453:453) (522:522:522)) + (PORT datab (908:908:908) (1071:1071:1071)) + (PORT datac (339:339:339) (389:389:389)) + (PORT datad (960:960:960) (1120:1120:1120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~7) + (DELAY + (ABSOLUTE + (PORT datab (495:495:495) (584:584:584)) + (PORT datac (492:492:492) (563:563:563)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (928:928:928)) + (PORT datab (471:471:471) (548:548:548)) + (PORT datac (484:484:484) (562:562:562)) + (PORT datad (338:338:338) (387:387:387)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (998:998:998)) + (PORT datab (1114:1114:1114) (1277:1277:1277)) + (PORT datac (759:759:759) (892:892:892)) + (PORT datad (616:616:616) (699:699:699)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (144:144:144)) + (PORT datab (622:622:622) (714:714:714)) + (PORT datac (266:266:266) (299:299:299)) + (PORT datad (351:351:351) (408:408:408)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~11) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (652:652:652) (767:767:767)) + (PORT datac (562:562:562) (667:667:667)) + (PORT datad (174:174:174) (206:206:206)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (405:405:405)) + (PORT datab (585:585:585) (659:659:659)) + (PORT datac (1117:1117:1117) (1277:1277:1277)) + (PORT datad (333:333:333) (385:385:385)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (391:391:391)) + (PORT datab (500:500:500) (587:587:587)) + (PORT datac (1026:1026:1026) (1197:1197:1197)) + (PORT datad (475:475:475) (555:555:555)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (232:232:232)) + (PORT datab (670:670:670) (786:786:786)) + (PORT datac (786:786:786) (906:906:906)) + (PORT datad (457:457:457) (524:524:524)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (463:463:463) (545:545:545)) + (PORT datab (503:503:503) (579:579:579)) + (PORT datac (500:500:500) (569:569:569)) + (PORT datad (453:453:453) (528:528:528)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (592:592:592)) + (PORT datab (186:186:186) (224:224:224)) + (PORT datac (481:481:481) (558:558:558)) + (PORT datad (610:610:610) (697:697:697)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (364:364:364)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (496:496:496) (577:577:577)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (731:731:731)) + (PORT datac (331:331:331) (393:393:393)) + (PORT datad (900:900:900) (1053:1053:1053)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (564:564:564)) + (PORT datab (864:864:864) (1009:1009:1009)) + (PORT datac (485:485:485) (555:555:555)) + (PORT datad (638:638:638) (731:731:731)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (433:433:433)) + (PORT datab (359:359:359) (421:421:421)) + (PORT datac (1113:1113:1113) (1238:1238:1238)) + (PORT datad (530:530:530) (626:626:626)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (354:354:354) (420:420:420)) + (PORT datad (380:380:380) (450:450:450)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~22) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (596:596:596)) + (PORT datab (485:485:485) (566:566:566)) + (PORT datac (482:482:482) (565:565:565)) + (PORT datad (329:329:329) (379:379:379)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1155:1155:1155)) + (PORT datab (875:875:875) (1044:1044:1044)) + (PORT datac (680:680:680) (794:794:794)) + (PORT datad (846:846:846) (968:968:968)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~53) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (620:620:620)) + (PORT datab (519:519:519) (605:605:605)) + (PORT datac (347:347:347) (411:411:411)) + (PORT datad (711:711:711) (805:805:805)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~23) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (190:190:190) (228:228:228)) + (PORT datac (866:866:866) (1002:1002:1002)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (236:236:236)) + (PORT datab (533:533:533) (619:619:619)) + (PORT datac (844:844:844) (991:991:991)) + (PORT datad (101:101:101) (119:119:119)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (387:387:387)) + (PORT datab (388:388:388) (463:463:463)) + (PORT datac (364:364:364) (431:431:431)) + (PORT datad (744:744:744) (877:877:877)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (414:414:414)) + (PORT datab (645:645:645) (743:743:743)) + (PORT datac (495:495:495) (574:574:574)) + (PORT datad (332:332:332) (388:388:388)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~34) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (394:394:394)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (160:160:160) (190:190:190)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~52) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (159:159:159) (187:187:187)) + (PORT datad (542:542:542) (636:636:636)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (712:712:712)) + (PORT datac (135:135:135) (179:179:179)) + (PORT datad (613:613:613) (708:708:708)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (927:927:927) (908:908:908)) + (PORT ena (1086:1086:1086) (1232:1232:1232)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (DELAY + (ABSOLUTE + (PORT datac (551:551:551) (648:648:648)) + (PORT datad (763:763:763) (910:910:910)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (285:285:285)) + (PORT datac (652:652:652) (766:766:766)) + (PORT datad (151:151:151) (195:195:195)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (422:422:422)) + (PORT datab (878:878:878) (991:991:991)) + (PORT datad (347:347:347) (409:409:409)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (914:914:914) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (641:641:641)) + (PORT datab (645:645:645) (740:740:740)) + (PORT datac (367:367:367) (429:429:429)) + (PORT datad (349:349:349) (407:407:407)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (785:785:785)) + (PORT datab (550:550:550) (651:651:651)) + (PORT datac (635:635:635) (737:737:737)) + (PORT datad (485:485:485) (566:566:566)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (249:249:249)) + (PORT datab (382:382:382) (454:454:454)) + (PORT datac (493:493:493) (572:572:572)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (576:576:576) (667:667:667)) + (PORT datad (344:344:344) (397:397:397)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (145:145:145)) + (PORT datab (516:516:516) (610:610:610)) + (PORT datac (335:335:335) (396:396:396)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (173:173:173)) + (PORT datac (517:517:517) (609:609:609)) + (PORT datad (174:174:174) (202:202:202)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (161:161:161)) + (PORT datab (432:432:432) (531:531:531)) + (PORT datac (759:759:759) (915:915:915)) + (PORT datad (296:296:296) (336:336:336)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (398:398:398)) + (PORT datab (408:408:408) (499:499:499)) + (PORT datad (402:402:402) (484:484:484)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (511:511:511)) + (PORT datab (657:657:657) (772:772:772)) + (PORT datac (407:407:407) (493:493:493)) + (PORT datad (410:410:410) (510:510:510)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (688:688:688)) + (PORT datab (644:644:644) (754:754:754)) + (PORT datac (118:118:118) (160:160:160)) + (PORT datad (189:189:189) (235:235:235)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~99) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (521:521:521)) + (PORT datab (397:397:397) (488:488:488)) + (PORT datac (478:478:478) (565:565:565)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (217:217:217)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (402:402:402) (492:492:492)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (505:505:505)) + (PORT datab (538:538:538) (645:645:645)) + (PORT datad (507:507:507) (606:606:606)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (513:513:513)) + (PORT datab (406:406:406) (497:497:497)) + (PORT datac (639:639:639) (748:748:748)) + (PORT datad (492:492:492) (585:585:585)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~133) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (429:429:429)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (409:409:409) (495:495:495)) + (PORT datad (404:404:404) (504:504:504)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datad (165:165:165) (195:195:195)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (911:911:911) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (364:364:364)) + (PORT datab (217:217:217) (275:275:275)) + (PORT datac (294:294:294) (339:339:339)) + (PORT datad (338:338:338) (406:406:406)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (488:488:488)) + (PORT datab (404:404:404) (494:494:494)) + (PORT datac (399:399:399) (489:489:489)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (191:191:191) (231:231:231)) + (PORT datad (402:402:402) (484:484:484)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (916:916:916)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (952:952:952)) + (PORT datab (114:114:114) (147:147:147)) + (PORT datac (517:517:517) (615:615:615)) + (PORT datad (108:108:108) (128:128:128)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (479:479:479)) + (PORT datab (355:355:355) (429:429:429)) + (PORT datac (345:345:345) (419:419:419)) + (PORT datad (228:228:228) (285:285:285)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (156:156:156)) + (PORT datab (217:217:217) (280:280:280)) + (PORT datac (333:333:333) (402:402:402)) + (PORT datad (214:214:214) (265:265:265)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~134) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (229:229:229)) + (PORT datab (193:193:193) (232:232:232)) + (PORT datad (440:440:440) (513:513:513)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (492:492:492)) + (PORT datab (327:327:327) (387:387:387)) + (PORT datac (328:328:328) (391:391:391)) + (PORT datad (271:271:271) (307:307:307)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~135) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (491:491:491)) + (PORT datab (148:148:148) (198:198:198)) + (PORT datad (595:595:595) (692:692:692)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (190:190:190) (235:235:235)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (179:179:179)) + (PORT datab (663:663:663) (779:779:779)) + (PORT datac (342:342:342) (408:408:408)) + (PORT datad (418:418:418) (478:478:478)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (535:535:535)) + (PORT datab (119:119:119) (153:153:153)) + (PORT datac (342:342:342) (411:411:411)) + (PORT datad (167:167:167) (196:196:196)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (478:478:478)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (297:297:297) (351:351:351)) + (PORT datad (251:251:251) (308:308:308)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) + (DELAY + (ABSOLUTE + (PORT datab (296:296:296) (344:344:344)) + (PORT datad (470:470:470) (539:539:539)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (912:912:912)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (908:908:908)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (488:488:488)) + (PORT datab (345:345:345) (418:418:418)) + (PORT datac (343:343:343) (411:411:411)) + (PORT datad (424:424:424) (495:495:495)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (483:483:483)) + (PORT datab (117:117:117) (150:150:150)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (341:341:341) (406:406:406)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~137) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (485:485:485)) + (PORT datab (171:171:171) (209:209:209)) + (PORT datad (177:177:177) (212:212:212)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~138) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (714:714:714)) + (PORT datab (361:361:361) (425:425:425)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (DELAY + (ABSOLUTE + (PORT datab (749:749:749) (881:881:881)) + (PORT datac (902:902:902) (1053:1053:1053)) + (PORT datad (669:669:669) (791:791:791)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (152:152:152)) + (PORT datab (639:639:639) (743:743:743)) + (PORT datac (660:660:660) (773:773:773)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (721:721:721)) + (PORT datab (1854:1854:1854) (2144:2144:2144)) + (PORT datac (639:639:639) (741:741:741)) + (PORT datad (285:285:285) (326:326:326)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (583:583:583) (669:669:669)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2271:2271:2271) (2633:2633:2633)) + (PORT d[1] (973:973:973) (1149:1149:1149)) + (PORT d[2] (959:959:959) (1102:1102:1102)) + (PORT d[3] (1046:1046:1046) (1227:1227:1227)) + (PORT d[4] (1245:1245:1245) (1443:1443:1443)) + (PORT d[5] (784:784:784) (927:927:927)) + (PORT d[6] (857:857:857) (998:998:998)) + (PORT d[7] (1954:1954:1954) (2213:2213:2213)) + (PORT d[8] (2109:2109:2109) (2446:2446:2446)) + (PORT d[9] (838:838:838) (972:972:972)) + (PORT d[10] (1853:1853:1853) (2129:2129:2129)) + (PORT d[11] (1194:1194:1194) (1380:1380:1380)) + (PORT d[12] (992:992:992) (1139:1139:1139)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1463:1463:1463) (1618:1618:1618)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (1670:1670:1670) (1837:1837:1837)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (609:609:609) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (364:364:364) (418:418:418)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1714:1714:1714) (1988:1988:1988)) + (PORT d[1] (791:791:791) (936:936:936)) + (PORT d[2] (1150:1150:1150) (1318:1318:1318)) + (PORT d[3] (1214:1214:1214) (1418:1418:1418)) + (PORT d[4] (898:898:898) (1045:1045:1045)) + (PORT d[5] (787:787:787) (936:936:936)) + (PORT d[6] (673:673:673) (784:784:784)) + (PORT d[7] (1969:1969:1969) (2223:2223:2223)) + (PORT d[8] (1446:1446:1446) (1694:1694:1694)) + (PORT d[9] (2000:2000:2000) (2303:2303:2303)) + (PORT d[10] (1670:1670:1670) (1918:1918:1918)) + (PORT d[11] (977:977:977) (1132:1132:1132)) + (PORT d[12] (803:803:803) (924:924:924)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1087:1087:1087) (1186:1186:1186)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (1674:1674:1674) (1813:1813:1813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (556:556:556) (636:636:636)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1698:1698:1698) (1965:1965:1965)) + (PORT d[1] (791:791:791) (935:935:935)) + (PORT d[2] (940:940:940) (1098:1098:1098)) + (PORT d[3] (839:839:839) (978:978:978)) + (PORT d[4] (1094:1094:1094) (1277:1277:1277)) + (PORT d[5] (937:937:937) (1106:1106:1106)) + (PORT d[6] (760:760:760) (866:866:866)) + (PORT d[7] (824:824:824) (946:946:946)) + (PORT d[8] (1251:1251:1251) (1469:1469:1469)) + (PORT d[9] (2197:2197:2197) (2532:2532:2532)) + (PORT d[10] (1497:1497:1497) (1720:1720:1720)) + (PORT d[11] (1017:1017:1017) (1179:1179:1179)) + (PORT d[12] (1136:1136:1136) (1310:1310:1310)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (919:919:919) (997:997:997)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1219:1219:1219) (1309:1309:1309)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (400:400:400)) + (PORT datab (718:718:718) (841:841:841)) + (PORT datac (507:507:507) (574:574:574)) + (PORT datad (630:630:630) (739:739:739)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (717:717:717) (828:828:828)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2086:2086:2086) (2416:2416:2416)) + (PORT d[1] (989:989:989) (1166:1166:1166)) + (PORT d[2] (1751:1751:1751) (2006:2006:2006)) + (PORT d[3] (1216:1216:1216) (1416:1416:1416)) + (PORT d[4] (1303:1303:1303) (1522:1522:1522)) + (PORT d[5] (1396:1396:1396) (1646:1646:1646)) + (PORT d[6] (1194:1194:1194) (1381:1381:1381)) + (PORT d[7] (1595:1595:1595) (1805:1805:1805)) + (PORT d[8] (1756:1756:1756) (2044:2044:2044)) + (PORT d[9] (1448:1448:1448) (1671:1671:1671)) + (PORT d[10] (2188:2188:2188) (2512:2512:2512)) + (PORT d[11] (1010:1010:1010) (1170:1170:1170)) + (PORT d[12] (1191:1191:1191) (1366:1366:1366)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1555:1555:1555) (1720:1720:1720)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (1507:1507:1507) (1632:1632:1632)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (609:609:609) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (759:759:759)) + (PORT datab (522:522:522) (603:603:603)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (825:825:825) (930:930:930)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2056:2056:2056) (2379:2379:2379)) + (PORT d[1] (1524:1524:1524) (1781:1781:1781)) + (PORT d[2] (942:942:942) (1103:1103:1103)) + (PORT d[3] (1197:1197:1197) (1399:1399:1399)) + (PORT d[4] (1073:1073:1073) (1250:1250:1250)) + (PORT d[5] (783:783:783) (928:928:928)) + (PORT d[6] (636:636:636) (739:739:739)) + (PORT d[7] (818:818:818) (941:941:941)) + (PORT d[8] (1260:1260:1260) (1481:1481:1481)) + (PORT d[9] (2208:2208:2208) (2547:2547:2547)) + (PORT d[10] (1476:1476:1476) (1692:1692:1692)) + (PORT d[11] (1175:1175:1175) (1361:1361:1361)) + (PORT d[12] (1122:1122:1122) (1295:1295:1295)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (1966:1966:1966) (2218:2218:2218)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (822:822:822) (936:936:936)) + (PORT clk (1086:1086:1086) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1883:1883:1883) (2185:2185:2185)) + (PORT d[1] (1343:1343:1343) (1577:1577:1577)) + (PORT d[2] (1232:1232:1232) (1425:1425:1425)) + (PORT d[3] (1027:1027:1027) (1201:1201:1201)) + (PORT d[4] (1250:1250:1250) (1450:1450:1450)) + (PORT d[5] (965:965:965) (1138:1138:1138)) + (PORT d[6] (836:836:836) (965:965:965)) + (PORT d[7] (843:843:843) (972:972:972)) + (PORT d[8] (1670:1670:1670) (1933:1933:1933)) + (PORT d[9] (1320:1320:1320) (1516:1516:1516)) + (PORT d[10] (1292:1292:1292) (1485:1485:1485)) + (PORT d[11] (1399:1399:1399) (1626:1626:1626)) + (PORT d[12] (1114:1114:1114) (1279:1279:1279)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1608:1608:1608) (1771:1771:1771)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1086:1086:1086) (1104:1104:1104)) + (PORT d[0] (2283:2283:2283) (2527:2527:2527)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1041:1041:1041) (1061:1061:1061)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1252:1252:1252) (1392:1392:1392)) + (PORT clk (1046:1046:1046) (1064:1064:1064)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2408:2408:2408) (2741:2741:2741)) + (PORT d[1] (2392:2392:2392) (2698:2698:2698)) + (PORT d[2] (2372:2372:2372) (2705:2705:2705)) + (PORT d[3] (2539:2539:2539) (2894:2894:2894)) + (PORT d[4] (2352:2352:2352) (2674:2674:2674)) + (PORT d[5] (2403:2403:2403) (2727:2727:2727)) + (PORT d[6] (2496:2496:2496) (2860:2860:2860)) + (PORT d[7] (2413:2413:2413) (2753:2753:2753)) + (PORT d[8] (2542:2542:2542) (2856:2856:2856)) + (PORT d[9] (2555:2555:2555) (2936:2936:2936)) + (PORT d[10] (2442:2442:2442) (2755:2755:2755)) + (PORT d[11] (2400:2400:2400) (2708:2708:2708)) + (PORT d[12] (2571:2571:2571) (2895:2895:2895)) + (PORT clk (1043:1043:1043) (1063:1063:1063)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1046:1046:1046) (1064:1064:1064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (472:472:472) (563:563:563)) + (PORT datab (938:938:938) (1094:1094:1094)) + (PORT datac (517:517:517) (591:591:591)) + (PORT datad (685:685:685) (776:776:776)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2029:2029:2029) (2354:2354:2354)) + (PORT d[1] (1516:1516:1516) (1773:1773:1773)) + (PORT d[2] (872:872:872) (1012:1012:1012)) + (PORT d[3] (1178:1178:1178) (1374:1374:1374)) + (PORT d[4] (1252:1252:1252) (1447:1447:1447)) + (PORT d[5] (957:957:957) (1129:1129:1129)) + (PORT d[6] (783:783:783) (903:903:903)) + (PORT d[7] (825:825:825) (954:954:954)) + (PORT d[8] (1234:1234:1234) (1452:1452:1452)) + (PORT d[9] (1340:1340:1340) (1538:1538:1538)) + (PORT d[10] (1301:1301:1301) (1494:1494:1494)) + (PORT d[11] (1198:1198:1198) (1388:1388:1388)) + (PORT d[12] (1288:1288:1288) (1479:1479:1479)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (2195:2195:2195) (1948:1948:1948)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (609:609:609) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (154:154:154)) + (PORT datab (513:513:513) (583:583:583)) + (PORT datac (627:627:627) (715:715:715)) + (PORT datad (95:95:95) (113:113:113)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (860:860:860) (991:991:991)) + (PORT clk (1101:1101:1101) (1118:1118:1118)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1412:1412:1412) (1614:1614:1614)) + (PORT d[1] (1124:1124:1124) (1322:1322:1322)) + (PORT d[2] (1114:1114:1114) (1299:1299:1299)) + (PORT d[3] (1054:1054:1054) (1236:1236:1236)) + (PORT d[4] (1594:1594:1594) (1834:1834:1834)) + (PORT d[5] (1318:1318:1318) (1541:1541:1541)) + (PORT d[6] (1175:1175:1175) (1347:1347:1347)) + (PORT d[7] (1389:1389:1389) (1610:1610:1610)) + (PORT d[8] (1374:1374:1374) (1604:1604:1604)) + (PORT d[9] (1149:1149:1149) (1321:1321:1321)) + (PORT d[10] (975:975:975) (1114:1114:1114)) + (PORT d[11] (1153:1153:1153) (1319:1319:1319)) + (PORT d[12] (1441:1441:1441) (1644:1644:1644)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1465:1465:1465) (1612:1612:1612)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1101:1101:1101) (1118:1118:1118)) + (PORT d[0] (2068:2068:2068) (1911:1911:1911)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1102:1102:1102) (1119:1119:1119)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1102:1102:1102) (1119:1119:1119)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1102:1102:1102) (1119:1119:1119)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1102:1102:1102) (1119:1119:1119)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1056:1056:1056) (1075:1075:1075)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1143:1143:1143) (1275:1275:1275)) + (PORT clk (1061:1061:1061) (1078:1078:1078)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2565:2565:2565) (2902:2902:2902)) + (PORT d[1] (2379:2379:2379) (2698:2698:2698)) + (PORT d[2] (2538:2538:2538) (2875:2875:2875)) + (PORT d[3] (2480:2480:2480) (2809:2809:2809)) + (PORT d[4] (2379:2379:2379) (2694:2694:2694)) + (PORT d[5] (2552:2552:2552) (2893:2893:2893)) + (PORT d[6] (2642:2642:2642) (3020:3020:3020)) + (PORT d[7] (2531:2531:2531) (2886:2886:2886)) + (PORT d[8] (2543:2543:2543) (2891:2891:2891)) + (PORT d[9] (2572:2572:2572) (2952:2952:2952)) + (PORT d[10] (2438:2438:2438) (2753:2753:2753)) + (PORT d[11] (2584:2584:2584) (2914:2914:2914)) + (PORT d[12] (2592:2592:2592) (2978:2978:2978)) + (PORT clk (1058:1058:1058) (1077:1077:1077)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1061:1061:1061) (1078:1078:1078)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1062:1062:1062) (1079:1079:1079)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1062:1062:1062) (1079:1079:1079)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1062:1062:1062) (1079:1079:1079)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1062:1062:1062) (1079:1079:1079)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1076:1076:1076)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (472:472:472) (563:563:563)) + (PORT datab (107:107:107) (136:136:136)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (831:831:831) (945:945:945)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (995:995:995)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (904:904:904) (1055:1055:1055)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (112:112:112) (148:148:148)) + (PORT datab (765:765:765) (879:879:879)) + (PORT datac (730:730:730) (844:844:844)) + (PORT datad (179:179:179) (205:205:205)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (1024:1024:1024)) + (PORT datab (761:761:761) (876:876:876)) + (PORT datac (610:610:610) (720:720:720)) + (PORT datad (161:161:161) (189:189:189)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (647:647:647)) + (PORT datab (926:926:926) (1052:1052:1052)) + (PORT datac (134:134:134) (171:171:171)) + (PORT datad (486:486:486) (557:557:557)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (177:177:177)) + (PORT datab (356:356:356) (436:436:436)) + (PORT datad (112:112:112) (135:135:135)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (629:629:629)) + (PORT datab (498:498:498) (571:571:571)) + (PORT datac (499:499:499) (573:573:573)) + (PORT datad (501:501:501) (577:577:577)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (911:911:911) (895:895:895)) + (PORT ena (780:780:780) (849:849:849)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (969:969:969)) + (PORT datab (649:649:649) (747:747:747)) + (PORT datac (667:667:667) (790:790:790)) + (PORT datad (778:778:778) (892:892:892)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (598:598:598)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (488:488:488) (553:553:553)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (757:757:757) (876:876:876)) + (PORT datab (339:339:339) (406:406:406)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (306:306:306) (344:344:344)) + (PORT sload (575:575:575) (630:630:630)) + (PORT ena (419:419:419) (435:435:435)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (559:559:559)) + (PORT datab (639:639:639) (743:743:743)) + (PORT datac (94:94:94) (117:117:117)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (597:597:597)) + (PORT datab (337:337:337) (405:405:405)) + (PORT datac (901:901:901) (1028:1028:1028)) + (PORT datad (168:168:168) (197:197:197)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (778:778:778) (898:898:898)) + (PORT datac (455:455:455) (518:518:518)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (781:781:781) (899:899:899)) + (PORT datab (539:539:539) (634:634:634)) + (PORT datac (551:551:551) (659:659:659)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (238:238:238)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (286:286:286)) + (PORT datab (125:125:125) (156:156:156)) + (PORT datac (613:613:613) (702:702:702)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (148:148:148)) + (PORT datac (730:730:730) (844:844:844)) + (PORT datad (105:105:105) (123:123:123)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (736:736:736)) + (PORT datab (634:634:634) (729:729:729)) + (PORT datac (838:838:838) (949:949:949)) + (PORT datad (167:167:167) (195:195:195)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (563:563:563)) + (PORT datab (877:877:877) (1024:1024:1024)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (602:602:602)) + (PORT datab (788:788:788) (926:926:926)) + (PORT datac (898:898:898) (1025:1025:1025)) + (PORT datad (168:168:168) (198:198:198)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~92) + (DELAY + (ABSOLUTE + (PORT datab (728:728:728) (837:837:837)) + (PORT datac (95:95:95) (118:118:118)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (597:597:597)) + (PORT datab (479:479:479) (578:578:578)) + (PORT datac (901:901:901) (1028:1028:1028)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~3) + (DELAY + (ABSOLUTE + (PORT datab (789:789:789) (939:939:939)) + (PORT datac (1301:1301:1301) (1509:1509:1509)) + (PORT datad (288:288:288) (332:332:332)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (689:689:689) (767:767:767)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (133:133:133) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (912:912:912)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (704:704:704) (789:789:789)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (912:912:912)) + (PORT asdata (298:298:298) (340:340:340)) + (PORT clrn (922:922:922) (904:904:904)) + (PORT ena (704:704:704) (789:789:789)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (188:188:188)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (603:603:603)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_clkctrl") (INSTANCE ula_\|pll_\|altpll_component\|auto_generated\|wire_pll1_clk\[2\]\~clkctrl) @@ -36154,15 +50298,202 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (INSTANCE ula_\|i2c_loader_\|divider\[0\]\~15) (DELAY (ABSOLUTE - (PORT dataa (706:706:706) (863:863:863)) - (PORT datab (688:688:688) (818:818:818)) - (PORT datac (448:448:448) (508:508:508)) - (PORT datad (436:436:436) (501:501:501)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (913:913:913)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (PORT datab (135:135:135) (186:186:186)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (913:913:913)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (913:913:913)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (913:913:913)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (913:913:913)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (913:913:913)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|WideAnd0) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -36170,13 +50501,15 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[3\]) + (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (928:928:928) (912:912:912)) + (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (896:896:896) (984:984:984)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT ena (810:810:810) (754:754:754)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK @@ -36186,56 +50519,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~64) + (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datac (514:514:514) (618:618:618)) - (PORT datad (603:603:603) (709:709:709)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (510:510:510) (613:613:613)) - (PORT datab (496:496:496) (591:591:591)) - (PORT datac (432:432:432) (492:492:492)) - (PORT datad (355:355:355) (436:436:436)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (644:644:644)) - (PORT datab (381:381:381) (461:461:461)) - (PORT datac (102:102:102) (130:130:130)) - (PORT datad (104:104:104) (127:127:127)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (379:379:379)) - (PORT datad (390:390:390) (476:476:476)) - (IOPATH dataa combout (186:186:186) (180:180:180)) + (PORT datad (132:132:132) (171:171:171)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -36243,60 +50530,98 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) + (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (917:917:917)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT ena (810:810:810) (754:754:754)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) + (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT datab (525:525:525) (630:630:630)) - (PORT datac (630:630:630) (738:738:738)) - (PORT datad (378:378:378) (461:461:461)) + (PORT datab (183:183:183) (249:249:249)) + (PORT datad (135:135:135) (174:174:174)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|phase\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT ena (810:810:810) (754:754:754)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~5) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (412:412:412)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (166:166:166) (225:225:225)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|Mux42\~0) + (DELAY + (ABSOLUTE + (PORT datac (381:381:381) (465:465:465)) + (PORT datad (369:369:369) (445:445:445)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (DELAY + (ABSOLUTE + (PORT dataa (157:157:157) (214:214:214)) + (PORT datab (187:187:187) (253:253:253)) + (PORT datad (340:340:340) (406:406:406)) + (IOPATH dataa combout (181:181:181) (193:193:193)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (781:781:781)) - (PORT datab (250:250:250) (315:315:315)) - (PORT datac (614:614:614) (714:714:714)) - (PORT datad (496:496:496) (587:587:587)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~135) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (721:721:721)) - (PORT datab (722:722:722) (828:828:828)) - (PORT datad (162:162:162) (186:186:186)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -36304,256 +50629,35 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~105) + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (192:192:192) (228:228:228)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (590:590:590)) - (PORT datab (128:128:128) (176:176:176)) - (PORT datac (475:475:475) (548:548:548)) - (PORT datad (291:291:291) (342:342:342)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (256:256:256) (326:326:326)) - (PORT datac (503:503:503) (597:597:597)) - (PORT datad (299:299:299) (340:340:340)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (439:439:439) (509:509:509)) - (PORT datab (519:519:519) (627:627:627)) - (PORT datac (488:488:488) (581:581:581)) - (PORT datad (310:310:310) (359:359:359)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (512:512:512) (622:622:622)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (924:924:924)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (478:478:478)) - (PORT datab (489:489:489) (586:586:586)) - (PORT datac (507:507:507) (611:611:611)) - (PORT datad (504:504:504) (601:601:601)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (511:511:511) (620:620:620)) - (PORT datab (519:519:519) (627:627:627)) - (PORT datad (211:211:211) (270:270:270)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (158:158:158) (213:213:213)) + (PORT datac (299:299:299) (354:354:354)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (627:627:627)) - (PORT datab (634:634:634) (743:743:743)) - (PORT datac (489:489:489) (583:583:583)) - (PORT datad (506:506:506) (603:603:603)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (119:119:119) (148:148:148)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (924:924:924)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (524:524:524)) - (PORT datab (131:131:131) (179:179:179)) - (PORT datac (115:115:115) (156:156:156)) - (PORT datad (1278:1278:1278) (1441:1441:1441)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (599:599:599)) - (PORT datab (519:519:519) (621:621:621)) - (PORT datac (515:515:515) (605:605:605)) - (PORT datad (472:472:472) (560:560:560)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE I2C_SDAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (705:705:705)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (378:378:378) (463:463:463)) - (PORT datac (510:510:510) (616:616:616)) - (PORT datad (604:604:604) (711:711:711)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (155:155:155) (211:211:211)) - (PORT datab (520:520:520) (625:625:625)) - (PORT datad (283:283:283) (325:325:325)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~136) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (580:580:580)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (506:506:506) (607:607:607)) - (PORT datad (607:607:607) (713:713:713)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT dataa (155:155:155) (212:212:212)) + (PORT datab (148:148:148) (198:198:198)) + (PORT datac (168:168:168) (228:228:228)) + (PORT datad (278:278:278) (297:297:297)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -36562,106 +50666,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (342:342:342) (404:404:404)) - (PORT datab (299:299:299) (346:346:346)) - (PORT datac (504:504:504) (605:605:605)) - (PORT datad (603:603:603) (709:709:709)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (307:307:307)) - (PORT datab (289:289:289) (338:338:338)) - (PORT datac (637:637:637) (746:746:746)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~137) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (300:300:300)) - (PORT datab (378:378:378) (457:457:457)) - (PORT datac (482:482:482) (575:575:575)) - (PORT datad (500:500:500) (597:597:597)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (336:336:336)) - (PORT datab (342:342:342) (404:404:404)) - (PORT datad (344:344:344) (406:406:406)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT datab (359:359:359) (434:434:434)) - (PORT datac (356:356:356) (422:422:422)) - (PORT datad (605:605:605) (708:708:708)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (445:445:445)) - (PORT datab (488:488:488) (564:564:564)) + (PORT dataa (352:352:352) (429:429:429)) + (PORT datab (341:341:341) (398:398:398)) + (PORT datac (90:90:90) (112:112:112)) (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (445:445:445) (522:522:522)) + (PORT datac (222:222:222) (278:278:278)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT ena (422:422:422) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (449:449:449)) + (PORT datab (381:381:381) (459:459:459)) + (PORT datac (138:138:138) (185:185:185)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) + (DELAY + (ABSOLUTE + (PORT dataa (310:310:310) (366:366:366)) + (PORT datab (140:140:140) (177:177:177)) + (PORT datad (174:174:174) (205:205:205)) + (IOPATH dataa combout (181:181:181) (175:175:175)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -36670,12 +50743,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) + (PORT clrn (907:907:907) (913:913:913)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36686,14 +50759,365 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~56) + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) (DELAY (ABSOLUTE - (PORT dataa (353:353:353) (421:421:421)) - (PORT datab (1076:1076:1076) (1220:1220:1220)) - (PORT datac (470:470:470) (552:552:552)) - (PORT datad (365:365:365) (444:444:444)) - (IOPATH dataa combout (165:165:165) (163:163:163)) + (PORT dataa (159:159:159) (218:218:218)) + (PORT datab (142:142:142) (195:195:195)) + (PORT datac (127:127:127) (171:171:171)) + (PORT datad (295:295:295) (350:350:350)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (413:413:413)) + (PORT datab (142:142:142) (194:194:194)) + (PORT datad (128:128:128) (170:170:170)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (913:913:913)) + (PORT ena (612:612:612) (664:664:664)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (194:194:194)) + (PORT datab (134:134:134) (185:185:185)) + (PORT datac (320:320:320) (383:383:383)) + (PORT datad (129:129:129) (172:172:172)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (490:490:490) (579:579:579)) + (PORT datad (167:167:167) (198:198:198)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (297:297:297) (354:354:354)) + (PORT datad (232:232:232) (290:290:290)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (913:913:913)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (214:214:214)) + (PORT datab (146:146:146) (196:196:196)) + (PORT datac (170:170:170) (230:230:230)) + (PORT datad (278:278:278) (297:297:297)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (276:276:276)) + (PORT datab (304:304:304) (366:366:366)) + (PORT datac (448:448:448) (524:524:524)) + (PORT datad (159:159:159) (185:185:185)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (593:593:593) (659:659:659)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT sload (571:571:571) (535:535:535)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (161:161:161) (217:217:217)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (594:594:594) (660:660:660)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT sload (571:571:571) (535:535:535)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (156:156:156) (208:208:208)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT sload (571:571:571) (535:535:535)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (165:165:165) (221:221:221)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (595:595:595) (661:661:661)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT sload (571:571:571) (535:535:535)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (289:289:289)) + (PORT datab (163:163:163) (218:218:218)) + (PORT datac (151:151:151) (201:201:201)) + (PORT datad (154:154:154) (202:202:202)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (476:476:476)) + (PORT datab (143:143:143) (196:196:196)) + (PORT datac (384:384:384) (469:469:469)) + (PORT datad (141:141:141) (185:185:185)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (170:170:170) (228:228:228)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT sload (571:571:571) (535:535:535)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT datab (329:329:329) (385:385:385)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (353:353:353) (421:421:421)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (149:149:149)) + (PORT datab (155:155:155) (209:209:209)) + (PORT datac (127:127:127) (171:171:171)) + (PORT datad (250:250:250) (281:281:281)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -36702,30 +51126,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~115) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) (DELAY (ABSOLUTE - (PORT dataa (655:655:655) (771:771:771)) - (PORT datab (221:221:221) (279:279:279)) - (PORT datac (504:504:504) (604:604:604)) - (PORT datad (602:602:602) (708:708:708)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (412:412:412)) - (PORT datab (179:179:179) (216:216:216)) - (PORT datac (138:138:138) (182:182:182)) - (PORT datad (458:458:458) (544:544:544)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (142:142:142) (181:181:181)) + (PORT datac (144:144:144) (194:194:194)) + (PORT datad (222:222:222) (275:275:275)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -36734,43 +51142,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~139) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) (DELAY (ABSOLUTE - (PORT dataa (276:276:276) (323:323:323)) - (PORT datab (363:363:363) (431:431:431)) - (PORT datad (231:231:231) (282:282:282)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (601:601:601)) - (PORT datab (520:520:520) (625:625:625)) - (PORT datac (210:210:210) (267:267:267)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~140) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (430:430:430)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datad (182:182:182) (210:210:210)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (161:161:161) (174:174:174)) + (PORT dataa (176:176:176) (218:218:218)) + (PORT datab (310:310:310) (366:366:366)) + (PORT datad (91:91:91) (107:107:107)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -36778,12 +51157,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) + (INSTANCE ula_\|i2c_loader_\|state\.Pause) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) + (PORT clrn (907:907:907) (913:913:913)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36794,55 +51173,123 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) + (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT datab (524:524:524) (630:630:630)) - (PORT datac (329:329:329) (397:397:397)) - (PORT datad (360:360:360) (437:437:437)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (142:142:142) (196:196:196)) + (PORT datab (144:144:144) (183:183:183)) + (PORT datad (219:219:219) (272:272:272)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Start) (DELAY (ABSOLUTE - (PORT datab (336:336:336) (411:411:411)) - (PORT datad (331:331:331) (399:399:399)) + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (913:913:913)) + (PORT ena (654:654:654) (617:617:617)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~0) + (DELAY + (ABSOLUTE + (PORT datab (181:181:181) (247:247:247)) + (PORT datad (333:333:333) (398:398:398)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT ena (422:422:422) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (449:449:449)) + (PORT datac (366:366:366) (437:437:437)) + (PORT datad (233:233:233) (292:292:292)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (652:652:652) (767:767:767)) - (PORT datab (425:425:425) (486:486:486)) - (PORT datac (326:326:326) (379:379:379)) - (PORT datad (330:330:330) (386:386:386)) + (PORT dataa (549:549:549) (642:642:642)) + (PORT datab (260:260:260) (324:324:324)) + (PORT datac (142:142:142) (188:188:188)) + (PORT datad (359:359:359) (431:431:431)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (314:314:314) (372:372:372)) + (PORT datad (167:167:167) (197:197:197)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) (DELAY (ABSOLUTE - (PORT dataa (245:245:245) (308:308:308)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (137:137:137) (182:182:182)) - (PORT datad (343:343:343) (406:406:406)) + (PORT dataa (178:178:178) (221:221:221)) + (PORT datab (139:139:139) (177:177:177)) + (PORT datac (292:292:292) (341:341:341)) + (PORT datad (226:226:226) (279:279:279)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -36851,12 +51298,30 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) (DELAY (ABSOLUTE - (PORT dataa (113:113:113) (148:148:148)) - (PORT datad (92:92:92) (110:110:110)) + (PORT clk (1106:1106:1106) (1137:1137:1137)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (913:913:913)) + (PORT ena (595:595:595) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (408:408:408)) + (PORT datad (131:131:131) (174:174:174)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -36865,675 +51330,45 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) + (PORT clk (908:908:908) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) + (PORT clrn (906:906:906) (913:913:913)) + (PORT ena (612:612:612) (664:664:664)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~57) + (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (257:257:257)) - (PORT datab (198:198:198) (255:255:255)) - (PORT datac (367:367:367) (436:436:436)) - (PORT datad (716:716:716) (809:809:809)) + (PORT dataa (140:140:140) (196:196:196)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datad (132:132:132) (175:175:175)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~58) + (INSTANCE ula_\|i2c_loader_\|state\~27) (DELAY (ABSOLUTE - (PORT dataa (290:290:290) (341:341:341)) - (PORT datab (462:462:462) (531:531:531)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (319:319:319) (373:373:373)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (957:957:957) (1092:1092:1092)) - (PORT clk (1093:1093:1093) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1875:1875:1875) (2177:2177:2177)) - (PORT d[1] (1231:1231:1231) (1446:1446:1446)) - (PORT d[2] (1348:1348:1348) (1581:1581:1581)) - (PORT d[3] (1553:1553:1553) (1834:1834:1834)) - (PORT d[4] (1447:1447:1447) (1692:1692:1692)) - (PORT d[5] (1956:1956:1956) (2273:2273:2273)) - (PORT d[6] (1313:1313:1313) (1506:1506:1506)) - (PORT d[7] (1989:1989:1989) (2283:2283:2283)) - (PORT d[8] (1237:1237:1237) (1451:1451:1451)) - (PORT d[9] (1442:1442:1442) (1641:1641:1641)) - (PORT d[10] (1108:1108:1108) (1304:1304:1304)) - (PORT d[11] (1066:1066:1066) (1253:1253:1253)) - (PORT d[12] (1628:1628:1628) (1860:1860:1860)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1435:1435:1435) (1573:1573:1573)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (PORT d[0] (1576:1576:1576) (1726:1726:1726)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1073:1073:1073) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (614:614:614) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (614:614:614) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (614:614:614) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1249:1249:1249) (1428:1428:1428)) - (PORT clk (1095:1095:1095) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2061:2061:2061) (2392:2392:2392)) - (PORT d[1] (1354:1354:1354) (1586:1586:1586)) - (PORT d[2] (2000:2000:2000) (2313:2313:2313)) - (PORT d[3] (1736:1736:1736) (2043:2043:2043)) - (PORT d[4] (1469:1469:1469) (1718:1718:1718)) - (PORT d[5] (1936:1936:1936) (2245:2245:2245)) - (PORT d[6] (918:918:918) (1044:1044:1044)) - (PORT d[7] (1957:1957:1957) (2241:2241:2241)) - (PORT d[8] (1274:1274:1274) (1490:1490:1490)) - (PORT d[9] (1785:1785:1785) (2032:2032:2032)) - (PORT d[10] (1299:1299:1299) (1527:1527:1527)) - (PORT d[11] (1064:1064:1064) (1262:1262:1262)) - (PORT d[12] (1453:1453:1453) (1657:1657:1657)) - (PORT clk (1093:1093:1093) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1234:1234:1234) (1351:1351:1351)) - (PORT clk (1093:1093:1093) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (PORT d[0] (1676:1676:1676) (1854:1854:1854)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1075:1075:1075) (1092:1092:1092)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1336:1336:1336) (1523:1523:1523)) - (PORT clk (1099:1099:1099) (1116:1116:1116)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1666:1666:1666) (1933:1933:1933)) - (PORT d[1] (1035:1035:1035) (1219:1219:1219)) - (PORT d[2] (1520:1520:1520) (1780:1780:1780)) - (PORT d[3] (1322:1322:1322) (1559:1559:1559)) - (PORT d[4] (1261:1261:1261) (1477:1477:1477)) - (PORT d[5] (1567:1567:1567) (1825:1825:1825)) - (PORT d[6] (1117:1117:1117) (1280:1280:1280)) - (PORT d[7] (2518:2518:2518) (2884:2884:2884)) - (PORT d[8] (1403:1403:1403) (1627:1627:1627)) - (PORT d[9] (1612:1612:1612) (1849:1849:1849)) - (PORT d[10] (1078:1078:1078) (1271:1271:1271)) - (PORT d[11] (1082:1082:1082) (1269:1269:1269)) - (PORT d[12] (1983:1983:1983) (2261:2261:2261)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1385:1385:1385) (1525:1525:1525)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (PORT d[0] (1579:1579:1579) (1737:1737:1737)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1117:1117:1117)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1117:1117:1117)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1117:1117:1117)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1117:1117:1117)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1079:1079:1079) (1095:1095:1095)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (628:628:628)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (628:628:628)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (628:628:628)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1333:1333:1333) (1522:1522:1522)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2246:2246:2246) (2601:2601:2601)) - (PORT d[1] (1239:1239:1239) (1452:1452:1452)) - (PORT d[2] (2333:2333:2333) (2693:2693:2693)) - (PORT d[3] (1928:1928:1928) (2266:2266:2266)) - (PORT d[4] (1839:1839:1839) (2146:2146:2146)) - (PORT d[5] (2325:2325:2325) (2698:2698:2698)) - (PORT d[6] (942:942:942) (1074:1074:1074)) - (PORT d[7] (1591:1591:1591) (1816:1816:1816)) - (PORT d[8] (1611:1611:1611) (1875:1875:1875)) - (PORT d[9] (1117:1117:1117) (1276:1276:1276)) - (PORT d[10] (897:897:897) (1050:1050:1050)) - (PORT d[11] (870:870:870) (1022:1022:1022)) - (PORT d[12] (1262:1262:1262) (1443:1443:1443)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1541:1541:1541) (1712:1712:1712)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1596:1596:1596) (1772:1772:1772)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (261:261:261)) - (PORT datab (1034:1034:1034) (1183:1183:1183)) - (PORT datac (637:637:637) (757:757:757)) - (PORT datad (500:500:500) (565:565:565)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (382:382:382) (471:471:471)) + (PORT datac (381:381:381) (465:465:465)) + (PORT datad (249:249:249) (280:280:280)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37541,658 +51376,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) + (INSTANCE ula_\|i2c_loader_\|state\~24) (DELAY (ABSOLUTE - (PORT dataa (927:927:927) (1044:1044:1044)) - (PORT datab (513:513:513) (612:612:612)) - (PORT datac (925:925:925) (1045:1045:1045)) - (PORT datad (570:570:570) (645:645:645)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (395:395:395) (460:460:460)) - (PORT clk (1096:1096:1096) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (644:644:644) (760:760:760)) - (PORT d[1] (956:956:956) (1120:1120:1120)) - (PORT d[2] (912:912:912) (1063:1063:1063)) - (PORT d[3] (1954:1954:1954) (2305:2305:2305)) - (PORT d[4] (1099:1099:1099) (1307:1307:1307)) - (PORT d[5] (707:707:707) (815:815:815)) - (PORT d[6] (1658:1658:1658) (1909:1909:1909)) - (PORT d[7] (1485:1485:1485) (1729:1729:1729)) - (PORT d[8] (764:764:764) (878:878:878)) - (PORT d[9] (1686:1686:1686) (1907:1907:1907)) - (PORT d[10] (758:758:758) (874:874:874)) - (PORT d[11] (2356:2356:2356) (2722:2722:2722)) - (PORT d[12] (1398:1398:1398) (1599:1599:1599)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (991:991:991) (1074:1074:1074)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (PORT d[0] (1302:1302:1302) (1404:1404:1404)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1051:1051:1051) (1071:1071:1071)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1589:1589:1589) (1796:1796:1796)) - (PORT clk (1056:1056:1056) (1074:1074:1074)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1072:1072:1072) (1238:1238:1238)) - (PORT d[1] (1095:1095:1095) (1273:1273:1273)) - (PORT d[2] (1073:1073:1073) (1230:1230:1230)) - (PORT d[3] (1111:1111:1111) (1310:1310:1310)) - (PORT d[4] (1097:1097:1097) (1254:1254:1254)) - (PORT d[5] (1040:1040:1040) (1205:1205:1205)) - (PORT d[6] (1067:1067:1067) (1249:1249:1249)) - (PORT d[7] (1039:1039:1039) (1196:1196:1196)) - (PORT d[8] (1143:1143:1143) (1335:1335:1335)) - (PORT d[9] (1123:1123:1123) (1292:1292:1292)) - (PORT d[10] (1075:1075:1075) (1258:1258:1258)) - (PORT d[11] (1123:1123:1123) (1293:1293:1293)) - (PORT d[12] (1063:1063:1063) (1221:1221:1221)) - (PORT clk (1053:1053:1053) (1073:1073:1073)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1074:1074:1074)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (603:603:603) (697:697:697)) - (PORT d[1] (534:534:534) (621:621:621)) - (PORT d[2] (926:926:926) (1082:1082:1082)) - (PORT d[3] (2323:2323:2323) (2735:2735:2735)) - (PORT d[4] (1610:1610:1610) (1883:1883:1883)) - (PORT d[5] (536:536:536) (626:626:626)) - (PORT d[6] (1855:1855:1855) (2132:2132:2132)) - (PORT d[7] (633:633:633) (725:725:725)) - (PORT d[8] (378:378:378) (430:430:430)) - (PORT d[9] (1346:1346:1346) (1523:1523:1523)) - (PORT d[10] (550:550:550) (631:631:631)) - (PORT d[11] (641:641:641) (733:733:733)) - (PORT d[12] (1311:1311:1311) (1496:1496:1496)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (1496:1496:1496) (1671:1671:1671)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (439:439:439) (518:518:518)) - (PORT d[1] (1154:1154:1154) (1345:1345:1345)) - (PORT d[2] (914:914:914) (1070:1070:1070)) - (PORT d[3] (2146:2146:2146) (2529:2529:2529)) - (PORT d[4] (1617:1617:1617) (1897:1897:1897)) - (PORT d[5] (552:552:552) (646:646:646)) - (PORT d[6] (1836:1836:1836) (2107:2107:2107)) - (PORT d[7] (1339:1339:1339) (1565:1565:1565)) - (PORT d[8] (557:557:557) (637:637:637)) - (PORT d[9] (1509:1509:1509) (1707:1707:1707)) - (PORT d[10] (558:558:558) (640:640:640)) - (PORT d[11] (652:652:652) (745:745:745)) - (PORT d[12] (1201:1201:1201) (1370:1370:1370)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (496:496:496) (461:461:461)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (916:916:916) (1046:1046:1046)) - (PORT clk (1106:1106:1106) (1124:1124:1124)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1749:1749:1749) (2008:2008:2008)) - (PORT d[1] (793:793:793) (935:935:935)) - (PORT d[2] (1966:1966:1966) (2317:2317:2317)) - (PORT d[3] (1525:1525:1525) (1794:1794:1794)) - (PORT d[4] (1495:1495:1495) (1760:1760:1760)) - (PORT d[5] (1229:1229:1229) (1401:1401:1401)) - (PORT d[6] (1317:1317:1317) (1519:1519:1519)) - (PORT d[7] (1657:1657:1657) (1928:1928:1928)) - (PORT d[8] (1699:1699:1699) (1980:1980:1980)) - (PORT d[9] (2013:2013:2013) (2282:2282:2282)) - (PORT d[10] (1445:1445:1445) (1698:1698:1698)) - (PORT d[11] (1746:1746:1746) (2034:2034:2034)) - (PORT d[12] (1956:1956:1956) (2236:2236:2236)) - (PORT clk (1104:1104:1104) (1122:1122:1122)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1155:1155:1155) (1259:1259:1259)) - (PORT clk (1104:1104:1104) (1122:1122:1122)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1124:1124:1124)) - (PORT d[0] (1936:1936:1936) (1804:1804:1804)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1125:1125:1125)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1125:1125:1125)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1125:1125:1125)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1125:1125:1125)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1061:1061:1061) (1081:1081:1081)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2419:2419:2419) (2730:2730:2730)) - (PORT clk (1066:1066:1066) (1084:1084:1084)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1020:1020:1020) (1183:1183:1183)) - (PORT d[1] (1099:1099:1099) (1283:1283:1283)) - (PORT d[2] (984:984:984) (1142:1142:1142)) - (PORT d[3] (1109:1109:1109) (1308:1308:1308)) - (PORT d[4] (1039:1039:1039) (1198:1198:1198)) - (PORT d[5] (1158:1158:1158) (1339:1339:1339)) - (PORT d[6] (1083:1083:1083) (1241:1241:1241)) - (PORT d[7] (1039:1039:1039) (1201:1201:1201)) - (PORT d[8] (1163:1163:1163) (1335:1335:1335)) - (PORT d[9] (1070:1070:1070) (1232:1232:1232)) - (PORT d[10] (1197:1197:1197) (1392:1392:1392)) - (PORT d[11] (1158:1158:1158) (1342:1342:1342)) - (PORT d[12] (1153:1153:1153) (1348:1348:1348)) - (PORT clk (1063:1063:1063) (1083:1083:1083)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1066:1066:1066) (1084:1084:1084)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1082:1082:1082)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (247:247:247)) - (PORT datab (358:358:358) (434:434:434)) - (PORT datac (555:555:555) (664:664:664)) - (PORT datad (810:810:810) (927:927:927)) + (PORT dataa (369:369:369) (450:450:450)) + (PORT datab (382:382:382) (459:459:459)) + (PORT datac (135:135:135) (181:181:181)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector3\~1) + (INSTANCE ula_\|i2c_loader_\|state\~26) (DELAY (ABSOLUTE - (PORT dataa (493:493:493) (565:565:565)) - (PORT datab (571:571:571) (683:683:683)) - (PORT datac (354:354:354) (414:414:414)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) + (PORT dataa (387:387:387) (475:475:475)) + (PORT datac (384:384:384) (468:468:468)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -38200,30 +51404,177 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~52) + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) (DELAY (ABSOLUTE - (PORT dataa (778:778:778) (893:893:893)) - (PORT datab (124:124:124) (156:156:156)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1385:1385:1385) (1619:1619:1619)) - (PORT datab (837:837:837) (986:986:986)) - (PORT datac (1764:1764:1764) (2069:2069:2069)) + (PORT dataa (107:107:107) (139:139:139)) (PORT datad (91:91:91) (109:109:109)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Data) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (305:305:305) (334:334:334)) + (PORT clrn (907:907:907) (913:913:913)) + (PORT sload (461:461:461) (529:529:529)) + (PORT ena (654:654:654) (617:617:617)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|scl_out\~0) + (DELAY + (ABSOLUTE + (PORT datab (158:158:158) (212:212:212)) + (PORT datac (311:311:311) (375:375:375)) + (PORT datad (126:126:126) (169:169:169)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT ena (810:810:810) (754:754:754)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|scl_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (427:427:427)) + (PORT datab (184:184:184) (250:250:250)) + (PORT datac (141:141:141) (190:190:190)) + (PORT datad (117:117:117) (155:155:155)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|scl_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (403:403:403)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (334:334:334) (399:399:399)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|scl_out) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (887:887:887)) + (PORT d (555:555:555) (509:509:509)) + (PORT aload (1017:1017:1017) (1062:1062:1062)) + (PORT ena (487:487:487) (454:454:454)) + (IOPATH (posedge clk) q (345:345:345) (339:339:339)) + (IOPATH (posedge aload) q (286:286:286) (280:280:280)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (SETUP ena (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + (HOLD ena (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|sda_out\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT ena (810:810:810) (754:754:754)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) + (DELAY + (ABSOLUTE + (PORT datac (473:473:473) (559:559:559)) + (PORT datad (326:326:326) (387:387:387)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|Mux35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (295:295:295)) + (PORT datab (239:239:239) (296:296:296)) + (PORT datac (205:205:205) (252:252:252)) + (PORT datad (209:209:209) (257:257:257)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (170:170:170) (230:230:230)) + (PORT datab (162:162:162) (218:218:218)) + (PORT datac (153:153:153) (206:206:206)) + (PORT datad (143:143:143) (186:186:186)) + (IOPATH dataa combout (192:192:192) (184:184:184)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -38232,13 +51583,69 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (419:419:419) (496:496:496)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (110:110:110) (135:135:135)) - (PORT datad (281:281:281) (318:318:318)) + (PORT datac (153:153:153) (206:206:206)) + (PORT datad (143:143:143) (185:185:185)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (167:167:167) (225:225:225)) + (PORT datac (151:151:151) (200:200:200)) + (PORT datad (105:105:105) (122:122:122)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (238:238:238) (295:295:295)) + (PORT datac (474:474:474) (560:560:560)) + (PORT datad (220:220:220) (268:268:268)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (472:472:472)) + (PORT datac (382:382:382) (467:467:467)) + (PORT datad (144:144:144) (189:189:189)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (164:164:164) (223:223:223)) + (PORT datab (139:139:139) (177:177:177)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (183:183:183) (212:212:212)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -38248,15 +51655,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~77) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) (DELAY (ABSOLUTE - (PORT dataa (824:824:824) (952:952:952)) - (PORT datab (926:926:926) (1076:1076:1076)) - (PORT datac (101:101:101) (122:122:122)) + (PORT datab (239:239:239) (301:301:301)) + (PORT datac (293:293:293) (342:342:342)) (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT sclr (554:554:554) (649:649:649)) + (PORT ena (724:724:724) (781:781:781)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (170:170:170) (229:229:229)) + (PORT datab (164:164:164) (221:221:221)) + (PORT datac (152:152:152) (206:206:206)) + (PORT datad (143:143:143) (185:185:185)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (227:227:227)) + (PORT datab (194:194:194) (230:230:230)) + (PORT datac (204:204:204) (251:251:251)) + (PORT datad (221:221:221) (269:269:269)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datac (477:477:477) (564:564:564)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (461:461:461)) + (PORT datab (258:258:258) (321:321:321)) + (PORT datac (313:313:313) (371:371:371)) + (PORT datad (105:105:105) (123:123:123)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -38264,27 +51751,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|always0\~0) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1145:1145:1145) (1301:1301:1301)) - (PORT datab (1778:1778:1778) (2087:2087:2087)) - (PORT datac (1246:1246:1246) (1442:1442:1442)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|always0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1382:1382:1382) (1615:1615:1615)) - (PORT datab (842:842:842) (992:992:992)) - (PORT datac (1761:1761:1761) (2066:2066:2066)) - (PORT datad (89:89:89) (106:106:106)) + (PORT dataa (548:548:548) (641:641:641)) + (PORT datab (296:296:296) (352:352:352)) + (PORT datac (492:492:492) (580:580:580)) + (PORT datad (92:92:92) (109:109:109)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -38294,13 +51767,15 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[13\]) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) + (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (419:419:419) (435:435:435)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT ena (629:629:629) (676:676:676)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK @@ -38308,6 +51783,371 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (172:172:172) (232:232:232)) + (PORT datab (167:167:167) (225:225:225)) + (PORT datac (151:151:151) (201:201:201)) + (PORT datad (149:149:149) (193:193:193)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (297:297:297)) + (PORT datab (221:221:221) (279:279:279)) + (PORT datac (159:159:159) (189:189:189)) + (PORT datad (104:104:104) (122:122:122)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (185:185:185)) + (PORT datac (472:472:472) (558:558:558)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT ena (629:629:629) (676:676:676)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (287:287:287)) + (PORT datab (162:162:162) (218:218:218)) + (PORT datac (153:153:153) (207:207:207)) + (PORT datad (151:151:151) (196:196:196)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (297:297:297)) + (PORT datab (237:237:237) (293:293:293)) + (PORT datac (259:259:259) (293:293:293)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (413:413:413)) + (PORT datab (130:130:130) (179:179:179)) + (PORT datac (473:473:473) (559:559:559)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT ena (629:629:629) (676:676:676)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (359:359:359) (435:435:435)) + (PORT datac (323:323:323) (379:379:379)) + (PORT datad (189:189:189) (236:236:236)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT ena (728:728:728) (796:796:796)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (286:286:286) (330:330:330)) + (PORT datab (260:260:260) (324:324:324)) + (PORT datad (191:191:191) (237:237:237)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (913:913:913)) + (PORT sload (627:627:627) (704:704:704)) + (PORT ena (419:419:419) (435:435:435)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (418:418:418)) + (PORT datac (476:476:476) (563:563:563)) + (PORT datad (105:105:105) (123:123:123)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT sclr (554:554:554) (649:649:649)) + (PORT ena (629:629:629) (676:676:676)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (472:472:472) (558:558:558)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (915:915:915)) + (PORT sclr (554:554:554) (649:649:649)) + (PORT ena (724:724:724) (781:781:781)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|sda_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (440:440:440)) + (PORT datab (220:220:220) (277:277:277)) + (PORT datac (290:290:290) (344:344:344)) + (PORT datad (198:198:198) (249:249:249)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|sda_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (324:324:324)) + (PORT datab (180:180:180) (245:245:245)) + (PORT datac (174:174:174) (211:211:211)) + (PORT datad (279:279:279) (297:297:297)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|sda_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (PORT datab (181:181:181) (246:246:246)) + (PORT datac (142:142:142) (189:189:189)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|sda_out\~3) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (194:194:194)) + (PORT datab (178:178:178) (243:243:243)) + (PORT datac (143:143:143) (190:190:190)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|sda_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (430:430:430)) + (PORT datab (430:430:430) (496:496:496)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|sda_out) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (889:889:889)) + (PORT d (381:381:381) (356:356:356)) + (PORT aload (1028:1028:1028) (1070:1070:1070)) + (PORT ena (725:725:725) (672:672:672)) + (IOPATH (posedge clk) q (345:345:345) (339:339:339)) + (IOPATH (posedge aload) q (286:286:286) (280:280:280)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (SETUP ena (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + (HOLD ena (posedge clk) (58:58:58)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|mclk_r\~0) @@ -38322,9 +52162,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1103:1103:1103) (1133:1133:1133)) + (PORT clk (1105:1105:1105) (1134:1134:1134)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (904:904:904) (910:910:910)) + (PORT clrn (905:905:905) (911:911:911)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -38333,12 +52173,29 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|mclk_r) + (DELAY + (ABSOLUTE + (PORT clk (891:891:891) (913:913:913)) + (PORT d (1491:1491:1491) (1301:1301:1301)) + (PORT clrn (1029:1029:1029) (1076:1076:1076)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT dataa (387:387:387) (470:470:470)) + (PORT dataa (379:379:379) (460:460:460)) (IOPATH dataa cout (226:226:226) (171:171:171)) ) ) @@ -38348,7 +52205,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (138:138:138) (188:188:188)) + (PORT datab (137:137:137) (187:187:187)) (IOPATH datab combout (167:167:167) (174:174:174)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -38362,10 +52219,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT datac (106:106:106) (130:130:130)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (120:120:120) (154:154:154)) + (PORT datac (92:92:92) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) @@ -38374,9 +52231,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1104:1104:1104) (1134:1134:1134)) + (PORT clk (1105:1105:1105) (1134:1134:1134)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (911:911:911)) + (PORT clrn (905:905:905) (911:911:911)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -38390,7 +52247,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (284:284:284)) + (PORT dataa (207:207:207) (271:271:271)) (IOPATH dataa combout (166:166:166) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -38404,8 +52261,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datac (156:156:156) (185:185:185)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datad (167:167:167) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -38414,9 +52271,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1104:1104:1104) (1134:1134:1134)) + (PORT clk (1105:1105:1105) (1134:1134:1134)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (911:911:911)) + (PORT clrn (905:905:905) (911:911:911)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -38430,7 +52287,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (209:209:209) (266:266:266)) + (PORT datab (203:203:203) (259:259:259)) (IOPATH datab combout (191:191:191) (181:181:181)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -38444,8 +52301,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datad (316:316:316) (366:366:366)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (174:174:174) (211:211:211)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -38454,7 +52311,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1104:1104:1104) (1134:1134:1134)) + (PORT clk (1105:1105:1105) (1134:1134:1134)) (PORT d (37:37:37) (50:50:50)) (PORT clrn (905:905:905) (911:911:911)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) @@ -38470,7 +52327,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (136:136:136) (186:186:186)) + (PORT datab (135:135:135) (186:186:186)) (IOPATH datab combout (188:188:188) (181:181:181)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -38484,8 +52341,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT dataa (122:122:122) (155:155:155)) - (PORT datac (91:91:91) (113:113:113)) + (PORT dataa (125:125:125) (160:160:160)) + (PORT datac (90:90:90) (111:111:111)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) ) @@ -38496,9 +52353,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1104:1104:1104) (1134:1134:1134)) + (PORT clk (1105:1105:1105) (1134:1134:1134)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (911:911:911)) + (PORT clrn (905:905:905) (911:911:911)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -38512,9 +52369,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (206:206:206) (264:264:264)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (136:136:136) (186:186:186)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -38526,8 +52383,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datac (162:162:162) (195:195:195)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -38536,7 +52393,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1104:1104:1104) (1134:1134:1134)) + (PORT clk (1105:1105:1105) (1134:1134:1134)) (PORT d (37:37:37) (50:50:50)) (PORT clrn (905:905:905) (911:911:911)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) @@ -38547,12 +52404,28 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (273:273:273)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datac (191:191:191) (240:240:240)) + (PORT datad (124:124:124) (164:164:164)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (206:206:206) (265:265:265)) + (PORT dataa (222:222:222) (278:278:278)) (IOPATH dataa combout (166:166:166) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -38566,8 +52439,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datac (174:174:174) (211:211:211)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datad (172:172:172) (203:203:203)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -38576,7 +52449,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1104:1104:1104) (1134:1134:1134)) + (PORT clk (1105:1105:1105) (1134:1134:1134)) (PORT d (37:37:37) (50:50:50)) (PORT clrn (905:905:905) (911:911:911)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) @@ -38592,7 +52465,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (219:219:219) (275:275:275)) + (PORT dataa (227:227:227) (287:287:287)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -38606,8 +52479,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datac (174:174:174) (210:210:210)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datad (169:169:169) (199:199:199)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -38616,7 +52489,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1104:1104:1104) (1134:1134:1134)) + (PORT clk (1105:1105:1105) (1134:1134:1134)) (PORT d (37:37:37) (50:50:50)) (PORT clrn (905:905:905) (911:911:911)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) @@ -38632,9 +52505,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~16) (DELAY (ABSOLUTE - (PORT datab (352:352:352) (432:432:432)) - (IOPATH datab combout (188:188:188) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (207:207:207) (265:265:265)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -38646,10 +52519,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datac (308:308:308) (348:348:348)) - (PORT datad (302:302:302) (346:346:346)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datab (190:190:190) (229:229:229)) + (PORT datac (197:197:197) (236:236:236)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -38658,9 +52531,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1111:1111:1111) (1140:1140:1140)) + (PORT clk (1105:1105:1105) (1134:1134:1134)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (917:917:917)) + (PORT clrn (905:905:905) (911:911:911)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -38674,7 +52547,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (122:122:122) (160:160:160)) + (PORT datad (199:199:199) (249:249:249)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) ) @@ -38685,7 +52558,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datad (90:90:90) (108:108:108)) + (PORT datad (171:171:171) (202:202:202)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -38695,9 +52568,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1104:1104:1104) (1134:1134:1134)) + (PORT clk (1105:1105:1105) (1134:1134:1134)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (911:911:911)) + (PORT clrn (905:905:905) (911:911:911)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -38711,28 +52584,12 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (206:206:206) (264:264:264)) - (PORT datab (134:134:134) (182:182:182)) - (PORT datac (199:199:199) (254:254:254)) - (PORT datad (333:333:333) (405:405:405)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (288:288:288)) - (PORT datab (203:203:203) (261:261:261)) - (PORT datac (191:191:191) (239:239:239)) - (PORT datad (120:120:120) (159:159:159)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (207:207:207) (266:266:266)) + (PORT datab (220:220:220) (276:276:276)) + (PORT datac (202:202:202) (259:259:259)) + (PORT datad (201:201:201) (254:254:254)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -38745,8 +52602,8 @@ (ABSOLUTE (PORT dataa (103:103:103) (134:134:134)) (PORT datab (132:132:132) (182:182:182)) - (PORT datac (364:364:364) (445:445:445)) - (PORT datad (158:158:158) (187:187:187)) + (PORT datac (360:360:360) (431:431:431)) + (PORT datad (94:94:94) (112:112:112)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -38754,6 +52611,78 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) + (DELAY + (ABSOLUTE + (PORT datad (105:105:105) (123:123:123)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (912:912:912)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) + (DELAY + (ABSOLUTE + (PORT datab (492:492:492) (573:573:573)) + (PORT datad (128:128:128) (168:168:168)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrclk_r) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (911:911:911)) + (PORT d (1273:1273:1273) (1412:1412:1412)) + (PORT clrn (1027:1027:1027) (1074:1074:1074)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (891:891:891) (912:912:912)) + (PORT d (1390:1390:1390) (1547:1547:1547)) + (PORT clrn (1029:1029:1029) (1075:1075:1075)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) @@ -38765,336 +52694,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (138:138:138) (191:191:191)) - (PORT datab (138:138:138) (188:188:188)) - (PORT datac (123:123:123) (166:166:166)) - (PORT datad (124:124:124) (164:164:164)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) - (DELAY - (ABSOLUTE - (PORT datab (151:151:151) (207:207:207)) - (PORT datac (134:134:134) (177:177:177)) - (PORT datad (107:107:107) (126:126:126)) - (IOPATH datab combout (188:188:188) (193:193:193)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~7) - (DELAY - (ABSOLUTE - (PORT datab (152:152:152) (208:208:208)) - (IOPATH datab cout (227:227:227) (175:175:175)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~8) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (185:185:185)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~20) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (212:212:212)) - (PORT datab (149:149:149) (205:205:205)) - (PORT datac (835:835:835) (970:970:970)) - (PORT datad (111:111:111) (134:134:134)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1114:1114:1114) (1144:1144:1144)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (920:920:920)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (135:135:135) (188:188:188)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~17) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (111:111:111) (138:138:138)) - (PORT datad (837:837:837) (967:967:967)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1114:1114:1114) (1144:1144:1144)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (920:920:920)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (189:189:189)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~19) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (215:215:215)) - (PORT datab (148:148:148) (204:204:204)) - (PORT datac (835:835:835) (970:970:970)) - (PORT datad (111:111:111) (134:134:134)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1114:1114:1114) (1144:1144:1144)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (920:920:920)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~14) - (DELAY - (ABSOLUTE - (PORT datad (123:123:123) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~16) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (244:244:244)) - (PORT datab (848:848:848) (989:989:989)) - (PORT datac (111:111:111) (137:137:137)) - (PORT datad (161:161:161) (187:187:187)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1114:1114:1114) (1144:1144:1144)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (920:920:920)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (134:134:134) (186:186:186)) - (PORT datab (137:137:137) (188:188:188)) - (PORT datac (123:123:123) (167:167:167)) - (PORT datad (122:122:122) (161:161:161)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (271:271:271)) - (PORT datab (154:154:154) (210:210:210)) - (PORT datac (289:289:289) (325:325:325)) - (PORT datad (104:104:104) (129:129:129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (998:998:998)) - (PORT datab (129:129:129) (162:162:162)) - (PORT datad (111:111:111) (135:135:135)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1114:1114:1114) (1144:1144:1144)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (920:920:920)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT datab (155:155:155) (211:211:211)) - (PORT datad (103:103:103) (128:128:128)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (202:202:202) (245:245:245)) - (PORT datac (134:134:134) (185:185:185)) - (PORT datad (713:713:713) (823:823:823)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) - (DELAY - (ABSOLUTE - (PORT datad (294:294:294) (336:336:336)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (909:909:909) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (920:920:920)) + (PORT clrn (907:907:907) (912:912:912)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39108,11 +52715,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) (DELAY (ABSOLUTE - (PORT dataa (727:727:727) (848:848:848)) - (PORT datac (134:134:134) (183:183:183)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (124:124:124) (159:159:159)) + (PORT datac (471:471:471) (543:543:543)) + (PORT datad (132:132:132) (176:176:176)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -39122,12 +52729,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (909:909:909) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (375:375:375) (409:409:409)) - (PORT clrn (915:915:915) (920:920:920)) - (PORT sload (1027:1027:1027) (1159:1159:1159)) - (PORT ena (405:405:405) (422:422:422)) + (PORT asdata (1507:1507:1507) (1683:1683:1683)) + (PORT clrn (907:907:907) (912:912:912)) + (PORT sload (777:777:777) (867:867:867)) + (PORT ena (407:407:407) (424:424:424)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39158,12 +52765,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (909:909:909) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (375:375:375) (409:409:409)) - (PORT clrn (915:915:915) (920:920:920)) - (PORT sload (1027:1027:1027) (1159:1159:1159)) - (PORT ena (405:405:405) (422:422:422)) + (PORT asdata (1507:1507:1507) (1683:1683:1683)) + (PORT clrn (907:907:907) (912:912:912)) + (PORT sload (777:777:777) (867:867:867)) + (PORT ena (407:407:407) (424:424:424)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39194,12 +52801,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (909:909:909) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (374:374:374) (408:408:408)) - (PORT clrn (915:915:915) (920:920:920)) - (PORT sload (1027:1027:1027) (1159:1159:1159)) - (PORT ena (405:405:405) (422:422:422)) + (PORT asdata (1506:1506:1506) (1683:1683:1683)) + (PORT clrn (907:907:907) (912:912:912)) + (PORT sload (777:777:777) (867:867:867)) + (PORT ena (407:407:407) (424:424:424)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39230,12 +52837,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (909:909:909) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (374:374:374) (408:408:408)) - (PORT clrn (915:915:915) (920:920:920)) - (PORT sload (1027:1027:1027) (1159:1159:1159)) - (PORT ena (405:405:405) (422:422:422)) + (PORT asdata (1506:1506:1506) (1682:1682:1682)) + (PORT clrn (907:907:907) (912:912:912)) + (PORT sload (777:777:777) (867:867:867)) + (PORT ena (407:407:407) (424:424:424)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39247,12 +52854,28 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (191:191:191)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (122:122:122) (166:166:166)) + (PORT datad (124:124:124) (163:163:163)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) (DELAY (ABSOLUTE - (PORT datab (147:147:147) (197:197:197)) + (PORT datab (145:145:145) (199:199:199)) (IOPATH datab combout (196:196:196) (205:205:205)) (IOPATH cin combout (187:187:187) (204:204:204)) ) @@ -39263,12 +52886,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (909:909:909) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (373:373:373) (407:407:407)) - (PORT clrn (915:915:915) (920:920:920)) - (PORT sload (1027:1027:1027) (1159:1159:1159)) - (PORT ena (405:405:405) (422:422:422)) + (PORT asdata (1506:1506:1506) (1682:1682:1682)) + (PORT clrn (907:907:907) (912:912:912)) + (PORT sload (777:777:777) (867:867:867)) + (PORT ena (407:407:407) (424:424:424)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39282,13 +52905,204 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) + (INSTANCE ula_\|i2s_intf_\|Add2\~7) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (280:280:280)) - (PORT datab (154:154:154) (209:209:209)) - (PORT datac (188:188:188) (230:230:230)) - (PORT datad (106:106:106) (125:125:125)) + (PORT dataa (241:241:241) (304:304:304)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (190:190:190)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~20) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (305:305:305)) + (PORT datab (491:491:491) (572:572:572)) + (PORT datac (109:109:109) (134:134:134)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (912:912:912)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (267:267:267)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~17) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (158:158:158)) + (PORT datab (124:124:124) (160:160:160)) + (PORT datac (472:472:472) (545:545:545)) + (PORT datad (172:172:172) (203:203:203)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (912:912:912)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT datab (138:138:138) (189:189:189)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~19) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (305:305:305)) + (PORT datab (492:492:492) (574:574:574)) + (PORT datac (110:110:110) (135:135:135)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (912:912:912)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT datad (189:189:189) (236:236:236)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (158:158:158)) + (PORT datab (124:124:124) (159:159:159)) + (PORT datac (472:472:472) (545:545:545)) + (PORT datad (172:172:172) (203:203:203)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (912:912:912)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (138:138:138) (189:189:189)) + (PORT datac (193:193:193) (243:243:243)) + (PORT datad (189:189:189) (235:235:235)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -39296,6 +53110,183 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (PORT datab (113:113:113) (145:145:145)) + (PORT datac (131:131:131) (180:180:180)) + (PORT datad (193:193:193) (226:226:226)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (573:573:573)) + (PORT datab (124:124:124) (160:160:160)) + (PORT datad (195:195:195) (229:229:229)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (912:912:912)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datac (201:201:201) (253:253:253)) + (PORT datad (193:193:193) (226:226:226)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) + (DELAY + (ABSOLUTE + (PORT datab (114:114:114) (146:146:146)) + (PORT datac (130:130:130) (178:178:178)) + (PORT datad (128:128:128) (172:172:172)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (160:160:160)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datad (466:466:466) (535:535:535)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bclk_r) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (910:910:910)) + (PORT d (1273:1273:1273) (1428:1428:1428)) + (PORT clrn (1026:1026:1026) (1073:1073:1073)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outl\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (471:471:471) (541:541:541)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1142:1142:1142)) + (PORT datab (897:897:897) (1062:1062:1062)) + (PORT datac (653:653:653) (769:769:769)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|always0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (457:457:457)) + (PORT datab (693:693:693) (818:818:818)) + (PORT datac (659:659:659) (775:775:775)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1089:1089:1089) (1200:1200:1200)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (119:119:119) (156:156:156)) + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (132:132:132) (181:181:181)) + (PORT datad (132:132:132) (175:175:175)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE AUD_ADCDAT\~input) @@ -39310,9 +53301,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (238:238:238)) - (PORT datab (805:805:805) (954:954:954)) - (PORT datad (429:429:429) (469:469:469)) + (PORT dataa (751:751:751) (865:865:865)) + (PORT datab (734:734:734) (861:861:861)) + (PORT datad (433:433:433) (467:467:467)) (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (182:182:182) (177:177:177)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -39325,9 +53316,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1098:1098:1098) (1117:1117:1117)) + (PORT clk (1102:1102:1102) (1123:1123:1123)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) + (PORT clrn (913:913:913) (919:919:919)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39341,22 +53332,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT datac (783:783:783) (931:931:931)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (131:131:131) (178:178:178)) + (PORT datad (711:711:711) (829:829:829)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]\~2) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~2) (DELAY (ABSOLUTE - (PORT dataa (727:727:727) (849:849:849)) - (PORT datac (136:136:136) (186:186:186)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (123:123:123) (159:159:159)) + (PORT datac (470:470:470) (543:543:543)) + (PORT datad (133:133:133) (176:176:176)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -39367,10 +53358,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) - (PORT ena (619:619:619) (670:670:670)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39385,9 +53376,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (788:788:788) (936:936:936)) - (PORT datad (119:119:119) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datac (117:117:117) (157:157:157)) + (PORT datad (712:712:712) (830:830:830)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -39397,10 +53388,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) - (PORT ena (619:619:619) (670:670:670)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39415,9 +53406,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datac (790:790:790) (939:939:939)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (714:714:714) (833:833:833)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -39427,10 +53418,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) - (PORT ena (619:619:619) (670:670:670)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39445,9 +53436,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datac (789:789:789) (938:938:938)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (132:132:132) (181:181:181)) + (PORT datad (723:723:723) (843:843:843)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -39457,10 +53448,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) - (PORT ena (619:619:619) (670:670:670)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39475,10 +53466,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (132:132:132) (182:182:182)) - (PORT datac (788:788:788) (937:937:937)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datab (131:131:131) (180:180:180)) + (PORT datad (719:719:719) (838:838:838)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -39487,10 +53478,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) - (PORT ena (619:619:619) (670:670:670)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39505,9 +53496,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT datac (786:786:786) (934:934:934)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (132:132:132) (183:183:183)) + (PORT datad (715:715:715) (834:834:834)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -39517,10 +53508,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) - (PORT ena (619:619:619) (670:670:670)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39536,9 +53527,9 @@ (DELAY (ABSOLUTE (PORT datab (131:131:131) (180:180:180)) - (PORT datac (789:789:789) (938:938:938)) + (PORT datad (709:709:709) (827:827:827)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -39547,10 +53538,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) - (PORT ena (619:619:619) (670:670:670)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39565,9 +53556,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datac (785:785:785) (933:933:933)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datac (116:116:116) (157:157:157)) + (PORT datad (710:710:710) (828:828:828)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -39577,10 +53568,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) - (PORT ena (619:619:619) (670:670:670)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39595,9 +53586,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datac (785:785:785) (933:933:933)) - (PORT datad (118:118:118) (154:154:154)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (713:713:713) (831:831:831)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -39607,10 +53598,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) - (PORT ena (619:619:619) (670:670:670)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39625,10 +53616,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datab (133:133:133) (182:182:182)) - (PORT datac (790:790:790) (939:939:939)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datac (118:118:118) (159:159:159)) + (PORT datad (718:718:718) (837:837:837)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -39637,10 +53628,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) - (PORT ena (619:619:619) (670:670:670)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39655,10 +53646,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT dataa (133:133:133) (185:185:185)) - (PORT datac (786:786:786) (934:934:934)) + (PORT dataa (132:132:132) (182:182:182)) + (PORT datad (722:722:722) (842:842:842)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -39667,10 +53658,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) - (PORT ena (619:619:619) (670:670:670)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39685,9 +53676,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) (DELAY (ABSOLUTE - (PORT datac (788:788:788) (937:937:937)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (130:130:130) (179:179:179)) + (PORT datad (720:720:720) (839:839:839)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -39697,10 +53688,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) - (PORT ena (619:619:619) (670:670:670)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39710,54 +53701,16 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) - (DELAY - (ABSOLUTE - (PORT datab (648:648:648) (746:746:746)) - (PORT datad (132:132:132) (170:170:170)) - (IOPATH datab combout (192:192:192) (181:181:181)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT datad (275:275:275) (317:317:317)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (443:443:443) (522:522:522)) - (PORT datab (651:651:651) (750:750:750)) - (PORT datad (198:198:198) (250:250:250)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) + (PORT dataa (783:783:783) (903:903:903)) + (PORT datab (487:487:487) (568:568:568)) + (PORT datad (124:124:124) (165:165:165)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -39768,9 +53721,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (908:908:908) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) + (PORT clrn (906:906:906) (912:912:912)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39781,11 +53734,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ula_data\~0) + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) (DELAY (ABSOLUTE - (PORT datac (478:478:478) (558:558:558)) - (PORT datad (387:387:387) (463:463:463)) + (PORT dataa (783:783:783) (903:903:903)) + (PORT datab (487:487:487) (568:568:568)) + (PORT datad (125:125:125) (165:165:165)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (912:912:912)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outr\~0) + (DELAY + (ABSOLUTE + (PORT datac (119:119:119) (161:161:161)) + (PORT datad (120:120:120) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -39796,9 +53780,9 @@ (INSTANCE ula_\|pcm_outl\[12\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) + (PORT clk (911:911:911) (915:915:915)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (844:844:844)) + (PORT ena (1148:1148:1148) (1270:1270:1270)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -39812,12 +53796,12 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT dataa (132:132:132) (182:182:182)) - (PORT datab (1127:1127:1127) (1300:1300:1300)) - (PORT datac (787:787:787) (936:936:936)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datab (738:738:738) (865:865:865)) + (PORT datac (117:117:117) (158:158:158)) + (PORT datad (720:720:720) (842:842:842)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -39826,10 +53810,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (920:920:920)) - (PORT ena (619:619:619) (670:670:670)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39844,12 +53828,12 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT dataa (393:393:393) (481:481:481)) - (PORT datab (655:655:655) (754:754:754)) - (PORT datac (1254:1254:1254) (1429:1429:1429)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (188:188:188)) + (PORT datab (698:698:698) (823:823:823)) + (PORT datac (117:117:117) (158:158:158)) + (PORT datad (722:722:722) (841:841:841)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -39858,10 +53842,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) (DELAY (ABSOLUTE - (PORT clk (1094:1094:1094) (1112:1112:1112)) + (PORT clk (1117:1117:1117) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (PORT ena (1552:1552:1552) (1715:1715:1715)) + (PORT clrn (913:913:913) (919:919:919)) + (PORT ena (1166:1166:1166) (1303:1303:1303)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -39871,13742 +53855,14 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (274:274:274)) - (PORT datab (656:656:656) (755:755:755)) - (PORT datad (134:134:134) (174:174:174)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (524:524:524)) - (PORT datab (843:843:843) (993:993:993)) - (PORT datac (129:129:129) (170:170:170)) - (PORT datad (128:128:128) (165:165:165)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (1848:1848:1848) (2159:2159:2159)) - (PORT datab (456:456:456) (525:525:525)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (174:174:174)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1282:1282:1282) (1490:1490:1490)) - (PORT datab (636:636:636) (757:757:757)) - (PORT datac (300:300:300) (359:359:359)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (457:457:457)) - (PORT datab (188:188:188) (227:227:227)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (859:859:859)) - (PORT datab (684:684:684) (813:813:813)) - (PORT datac (445:445:445) (508:508:508)) - (PORT datad (117:117:117) (134:134:134)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (928:928:928) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (896:896:896) (984:984:984)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (795:795:795)) - (PORT datac (335:335:335) (395:395:395)) - (PORT datad (545:545:545) (628:628:628)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (434:434:434)) - (PORT datab (503:503:503) (588:588:588)) - (PORT datac (327:327:327) (392:392:392)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (896:896:896)) - (PORT ena (996:996:996) (1096:1096:1096)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (758:758:758) (896:896:896)) - (PORT datab (722:722:722) (829:829:829)) - (PORT datad (161:161:161) (213:213:213)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (715:715:715)) - (PORT datab (603:603:603) (699:699:699)) - (PORT datac (736:736:736) (856:856:856)) - (PORT datad (795:795:795) (930:930:930)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (155:155:155)) - (PORT datab (142:142:142) (176:176:176)) - (PORT datac (736:736:736) (837:837:837)) - (PORT datad (102:102:102) (125:125:125)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (728:728:728) (836:836:836)) - (PORT datab (570:570:570) (651:651:651)) - (PORT datac (547:547:547) (626:626:626)) - (PORT datad (591:591:591) (675:675:675)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (579:579:579) (674:674:674)) - (PORT datab (126:126:126) (158:158:158)) - (PORT datad (324:324:324) (376:376:376)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (739:739:739) (851:851:851)) - (PORT datac (899:899:899) (1032:1032:1032)) - (PORT datad (293:293:293) (344:344:344)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (446:446:446)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (439:439:439) (498:498:498)) - (PORT datad (346:346:346) (409:409:409)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (521:521:521)) - (PORT datab (396:396:396) (478:478:478)) - (PORT datac (900:900:900) (1033:1033:1033)) - (PORT datad (350:350:350) (413:413:413)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (656:656:656)) - (PORT datab (580:580:580) (675:675:675)) - (PORT datac (462:462:462) (535:535:535)) - (PORT datad (114:114:114) (137:137:137)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (512:512:512)) - (PORT datab (350:350:350) (414:414:414)) - (PORT datac (684:684:684) (784:784:784)) - (PORT datad (353:353:353) (424:424:424)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (124:124:124) (159:159:159)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (90:90:90) (113:113:113)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (789:789:789)) - (PORT datac (168:168:168) (203:203:203)) - (PORT datad (543:543:543) (626:626:626)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (432:432:432)) - (PORT datac (526:526:526) (625:625:625)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (111:111:111) (143:143:143)) - (PORT datad (388:388:388) (475:475:475)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (926:926:926)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (757:757:757)) - (PORT datab (531:531:531) (625:625:625)) - (PORT datac (138:138:138) (183:183:183)) - (PORT datad (327:327:327) (396:396:396)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (756:756:756)) - (PORT datab (339:339:339) (417:417:417)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (420:420:420)) - (PORT datab (382:382:382) (464:464:464)) - (PORT datad (169:169:169) (199:199:199)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (217:217:217)) - (PORT datab (523:523:523) (628:628:628)) - (PORT datad (167:167:167) (198:198:198)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (550:550:550)) - (PORT datab (1051:1051:1051) (1190:1190:1190)) - (PORT datac (115:115:115) (156:156:156)) - (PORT datad (289:289:289) (343:343:343)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT datab (353:353:353) (428:428:428)) - (PORT datac (357:357:357) (423:423:423)) - (PORT datad (609:609:609) (713:713:713)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (428:428:428)) - (PORT datab (513:513:513) (614:614:614)) - (PORT datac (283:283:283) (330:330:330)) - (PORT datad (284:284:284) (323:323:323)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT datac (628:628:628) (738:738:738)) - (PORT datad (235:235:235) (295:295:295)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (118:118:118) (149:149:149)) - (PORT datab (404:404:404) (495:495:495)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (428:428:428)) - (PORT datac (283:283:283) (330:330:330)) - (PORT datad (494:494:494) (589:589:589)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT datab (254:254:254) (320:320:320)) - (PORT datac (629:629:629) (740:740:740)) - (PORT datad (283:283:283) (322:322:322)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (406:406:406) (498:498:498)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (570:570:570)) - (PORT datab (129:129:129) (176:176:176)) - (PORT datac (116:116:116) (157:157:157)) - (PORT datad (477:477:477) (565:565:565)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (644:644:644)) - (PORT datab (123:123:123) (154:154:154)) - (PORT datad (103:103:103) (126:126:126)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (382:382:382)) - (PORT datad (384:384:384) (471:471:471)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (926:926:926)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT datab (665:665:665) (790:790:790)) - (PORT datac (528:528:528) (627:627:627)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (235:235:235)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datad (391:391:391) (478:478:478)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (926:926:926)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (673:673:673)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datac (1039:1039:1039) (1180:1180:1180)) - (PORT datad (119:119:119) (157:157:157)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (384:384:384)) - (PORT datab (625:625:625) (739:739:739)) - (PORT datac (509:509:509) (614:614:614)) - (PORT datad (521:521:521) (618:618:618)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (148:148:148)) - (PORT datab (444:444:444) (514:514:514)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (355:355:355) (436:436:436)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (427:427:427)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datac (158:158:158) (208:208:208)) - (PORT datad (340:340:340) (406:406:406)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~68) - (DELAY - (ABSOLUTE - (PORT datab (226:226:226) (293:293:293)) - (PORT datac (377:377:377) (469:469:469)) - (PORT datad (407:407:407) (494:494:494)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (419:419:419) (517:517:517)) - (PORT datab (523:523:523) (626:626:626)) - (PORT datac (512:512:512) (602:602:602)) - (PORT datad (476:476:476) (565:565:565)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT datac (485:485:485) (579:579:579)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (493:493:493)) - (PORT datab (109:109:109) (139:139:139)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (445:445:445)) - (PORT datab (463:463:463) (535:535:535)) - (PORT datac (330:330:330) (395:395:395)) - (PORT datad (497:497:497) (587:587:587)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (191:191:191) (229:229:229)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (421:421:421) (480:480:480)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (532:532:532)) - (PORT datab (1902:1902:1902) (2225:2225:2225)) - (PORT datac (659:659:659) (782:782:782)) - (PORT datad (392:392:392) (465:465:465)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1655:1655:1655) (1873:1873:1873)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2243:2243:2243) (2595:2595:2595)) - (PORT d[1] (1390:1390:1390) (1627:1627:1627)) - (PORT d[2] (2498:2498:2498) (2880:2880:2880)) - (PORT d[3] (1926:1926:1926) (2267:2267:2267)) - (PORT d[4] (1851:1851:1851) (2158:2158:2158)) - (PORT d[5] (2331:2331:2331) (2708:2708:2708)) - (PORT d[6] (1110:1110:1110) (1271:1271:1271)) - (PORT d[7] (1600:1600:1600) (1829:1829:1829)) - (PORT d[8] (1622:1622:1622) (1885:1885:1885)) - (PORT d[9] (1244:1244:1244) (1417:1417:1417)) - (PORT d[10] (881:881:881) (1031:1031:1031)) - (PORT d[11] (860:860:860) (1020:1020:1020)) - (PORT d[12] (1261:1261:1261) (1442:1442:1442)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1380:1380:1380) (1530:1530:1530)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (1591:1591:1591) (1766:1766:1766)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1070:1070:1070) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1482:1482:1482) (1679:1679:1679)) - (PORT clk (1096:1096:1096) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2079:2079:2079) (2415:2415:2415)) - (PORT d[1] (1242:1242:1242) (1463:1463:1463)) - (PORT d[2] (2305:2305:2305) (2660:2660:2660)) - (PORT d[3] (1734:1734:1734) (2043:2043:2043)) - (PORT d[4] (1652:1652:1652) (1930:1930:1930)) - (PORT d[5] (2141:2141:2141) (2488:2488:2488)) - (PORT d[6] (1479:1479:1479) (1692:1692:1692)) - (PORT d[7] (1808:1808:1808) (2077:2077:2077)) - (PORT d[8] (1280:1280:1280) (1493:1493:1493)) - (PORT d[9] (1471:1471:1471) (1682:1682:1682)) - (PORT d[10] (1475:1475:1475) (1729:1729:1729)) - (PORT d[11] (968:968:968) (1129:1129:1129)) - (PORT d[12] (1444:1444:1444) (1647:1647:1647)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1077:1077:1077) (1179:1179:1179)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (PORT d[0] (1502:1502:1502) (1654:1654:1654)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (258:258:258)) - (PORT datab (500:500:500) (576:576:576)) - (PORT datac (633:633:633) (752:752:752)) - (PORT datad (662:662:662) (751:751:751)) - (IOPATH dataa combout (188:188:188) (193:193:193)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1140:1140:1140) (1291:1291:1291)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1877:1877:1877) (2181:2181:2181)) - (PORT d[1] (1240:1240:1240) (1459:1459:1459)) - (PORT d[2] (1363:1363:1363) (1598:1598:1598)) - (PORT d[3] (1556:1556:1556) (1834:1834:1834)) - (PORT d[4] (1269:1269:1269) (1486:1486:1486)) - (PORT d[5] (1949:1949:1949) (2265:2265:2265)) - (PORT d[6] (1306:1306:1306) (1498:1498:1498)) - (PORT d[7] (2125:2125:2125) (2433:2433:2433)) - (PORT d[8] (1242:1242:1242) (1447:1447:1447)) - (PORT d[9] (1612:1612:1612) (1839:1839:1839)) - (PORT d[10] (1109:1109:1109) (1310:1310:1310)) - (PORT d[11] (1072:1072:1072) (1260:1260:1260)) - (PORT d[12] (1635:1635:1635) (1869:1869:1869)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1735:1735:1735) (1921:1921:1921)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1929:1929:1929) (2129:2129:2129)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1312:1312:1312) (1486:1486:1486)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2067:2067:2067) (2399:2399:2399)) - (PORT d[1] (1365:1365:1365) (1597:1597:1597)) - (PORT d[2] (2167:2167:2167) (2501:2501:2501)) - (PORT d[3] (1737:1737:1737) (2044:2044:2044)) - (PORT d[4] (1460:1460:1460) (1705:1705:1705)) - (PORT d[5] (2133:2133:2133) (2478:2478:2478)) - (PORT d[6] (921:921:921) (1051:1051:1051)) - (PORT d[7] (1944:1944:1944) (2227:2227:2227)) - (PORT d[8] (1279:1279:1279) (1492:1492:1492)) - (PORT d[9] (1456:1456:1456) (1666:1666:1666)) - (PORT d[10] (1289:1289:1289) (1515:1515:1515)) - (PORT d[11] (1080:1080:1080) (1271:1271:1271)) - (PORT d[12] (1452:1452:1452) (1656:1656:1656)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (960:960:960) (1051:1051:1051)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (1746:1746:1746) (1916:1916:1916)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1092:1092:1092)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (262:262:262)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (846:846:846) (962:962:962)) - (PORT datad (668:668:668) (754:754:754)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (566:566:566) (649:649:649)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (733:733:733) (847:847:847)) - (PORT d[1] (1135:1135:1135) (1326:1326:1326)) - (PORT d[2] (917:917:917) (1065:1065:1065)) - (PORT d[3] (2137:2137:2137) (2517:2517:2517)) - (PORT d[4] (1651:1651:1651) (1933:1933:1933)) - (PORT d[5] (704:704:704) (812:812:812)) - (PORT d[6] (614:614:614) (691:691:691)) - (PORT d[7] (1510:1510:1510) (1760:1760:1760)) - (PORT d[8] (742:742:742) (852:852:852)) - (PORT d[9] (2683:2683:2683) (3040:3040:3040)) - (PORT d[10] (749:749:749) (864:864:864)) - (PORT d[11] (2373:2373:2373) (2745:2745:2745)) - (PORT d[12] (1510:1510:1510) (1728:1728:1728)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (980:980:980) (1059:1059:1059)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (1298:1298:1298) (1396:1396:1396)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1071:1071:1071)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1580:1580:1580) (1785:1785:1785)) - (PORT clk (1057:1057:1057) (1074:1074:1074)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1072:1072:1072) (1238:1238:1238)) - (PORT d[1] (1056:1056:1056) (1225:1225:1225)) - (PORT d[2] (1095:1095:1095) (1267:1267:1267)) - (PORT d[3] (1157:1157:1157) (1373:1373:1373)) - (PORT d[4] (1073:1073:1073) (1238:1238:1238)) - (PORT d[5] (1055:1055:1055) (1222:1222:1222)) - (PORT d[6] (1014:1014:1014) (1172:1172:1172)) - (PORT d[7] (1064:1064:1064) (1226:1226:1226)) - (PORT d[8] (1129:1129:1129) (1314:1314:1314)) - (PORT d[9] (1140:1140:1140) (1314:1314:1314)) - (PORT d[10] (1056:1056:1056) (1232:1232:1232)) - (PORT d[11] (1118:1118:1118) (1285:1285:1285)) - (PORT d[12] (1168:1168:1168) (1336:1336:1336)) - (PORT clk (1054:1054:1054) (1073:1073:1073)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1074:1074:1074)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (406:406:406) (475:475:475)) - (PORT d[1] (1954:1954:1954) (2289:2289:2289)) - (PORT d[2] (931:931:931) (1098:1098:1098)) - (PORT d[3] (2316:2316:2316) (2720:2720:2720)) - (PORT d[4] (1793:1793:1793) (2094:2094:2094)) - (PORT d[5] (685:685:685) (791:791:791)) - (PORT d[6] (1826:1826:1826) (2106:2106:2106)) - (PORT d[7] (1491:1491:1491) (1736:1736:1736)) - (PORT d[8] (573:573:573) (652:652:652)) - (PORT d[9] (1551:1551:1551) (1764:1764:1764)) - (PORT d[10] (668:668:668) (771:771:771)) - (PORT d[11] (827:827:827) (942:942:942)) - (PORT d[12] (1187:1187:1187) (1350:1350:1350)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (PORT d[0] (685:685:685) (630:630:630)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1074:1074:1074) (1090:1090:1090)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (614:614:614) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (574:574:574) (656:656:656)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (817:817:817) (955:955:955)) - (PORT d[1] (947:947:947) (1110:1110:1110)) - (PORT d[2] (2175:2175:2175) (2554:2554:2554)) - (PORT d[3] (1960:1960:1960) (2304:2304:2304)) - (PORT d[4] (1278:1278:1278) (1501:1501:1501)) - (PORT d[5] (741:741:741) (859:859:859)) - (PORT d[6] (656:656:656) (748:748:748)) - (PORT d[7] (1498:1498:1498) (1750:1750:1750)) - (PORT d[8] (839:839:839) (958:958:958)) - (PORT d[9] (1703:1703:1703) (1925:1925:1925)) - (PORT d[10] (1110:1110:1110) (1288:1288:1288)) - (PORT d[11] (1530:1530:1530) (1783:1783:1783)) - (PORT d[12] (1385:1385:1385) (1577:1577:1577)) - (PORT clk (1093:1093:1093) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (852:852:852) (916:916:916)) - (PORT clk (1093:1093:1093) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (1207:1207:1207) (1157:1157:1157)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1069:1069:1069)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1759:1759:1759) (1990:1990:1990)) - (PORT clk (1055:1055:1055) (1072:1072:1072)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1092:1092:1092) (1261:1261:1261)) - (PORT d[1] (1037:1037:1037) (1203:1203:1203)) - (PORT d[2] (1056:1056:1056) (1221:1221:1221)) - (PORT d[3] (1064:1064:1064) (1220:1220:1220)) - (PORT d[4] (1088:1088:1088) (1255:1255:1255)) - (PORT d[5] (1019:1019:1019) (1174:1174:1174)) - (PORT d[6] (1029:1029:1029) (1198:1198:1198)) - (PORT d[7] (1053:1053:1053) (1215:1215:1215)) - (PORT d[8] (1076:1076:1076) (1252:1252:1252)) - (PORT d[9] (1046:1046:1046) (1218:1218:1218)) - (PORT d[10] (1054:1054:1054) (1229:1229:1229)) - (PORT d[11] (1117:1117:1117) (1286:1286:1286)) - (PORT d[12] (1034:1034:1034) (1195:1195:1195)) - (PORT clk (1052:1052:1052) (1071:1071:1071)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1051:1051:1051) (1070:1070:1070)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (583:583:583)) - (PORT datab (670:670:670) (777:777:777)) - (PORT datac (146:146:146) (194:194:194)) - (PORT datad (677:677:677) (763:763:763)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (417:417:417) (485:485:485)) - (PORT d[1] (1796:1796:1796) (2116:2116:2116)) - (PORT d[2] (1267:1267:1267) (1470:1470:1470)) - (PORT d[3] (572:572:572) (666:666:666)) - (PORT d[4] (1946:1946:1946) (2260:2260:2260)) - (PORT d[5] (718:718:718) (838:838:838)) - (PORT d[6] (1616:1616:1616) (1858:1858:1858)) - (PORT d[7] (1305:1305:1305) (1521:1521:1521)) - (PORT d[8] (2310:2310:2310) (2665:2665:2665)) - (PORT d[9] (1733:1733:1733) (1972:1972:1972)) - (PORT d[10] (1659:1659:1659) (1928:1928:1928)) - (PORT d[11] (1301:1301:1301) (1527:1527:1527)) - (PORT d[12] (1377:1377:1377) (1568:1568:1568)) - (PORT clk (1085:1085:1085) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1104:1104:1104)) - (PORT d[0] (1309:1309:1309) (1460:1460:1460)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1086:1086:1086) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (607:607:607) (617:617:617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (288:288:288)) - (PORT datab (687:687:687) (779:779:779)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (648:648:648) (728:728:728)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (528:528:528) (610:610:610)) - (PORT datab (534:534:534) (618:618:618)) - (PORT datac (559:559:559) (628:628:628)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1200:1200:1200)) - (PORT datab (1903:1903:1903) (2214:2214:2214)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (1194:1194:1194) (1393:1393:1393)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (781:781:781)) - (PORT datab (641:641:641) (767:767:767)) - (PORT datac (619:619:619) (722:722:722)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (391:391:391)) - (PORT datac (366:366:366) (439:439:439)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (871:871:871)) - (PORT datab (697:697:697) (829:829:829)) - (PORT datac (109:109:109) (133:133:133)) - (PORT datad (446:446:446) (508:508:508)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (928:928:928) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (896:896:896) (984:984:984)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (351:351:351) (419:419:419)) - (PORT datac (624:624:624) (727:727:727)) - (PORT datad (342:342:342) (407:407:407)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (896:896:896)) - (PORT ena (996:996:996) (1096:1096:1096)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (1034:1034:1034)) - (PORT datad (874:874:874) (1012:1012:1012)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (758:758:758)) - (PORT datab (1461:1461:1461) (1677:1677:1677)) - (PORT datac (446:446:446) (520:520:520)) - (PORT datad (1052:1052:1052) (1189:1189:1189)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) - (DELAY - (ABSOLUTE - (PORT dataa (290:290:290) (334:334:334)) - (PORT datab (992:992:992) (1147:1147:1147)) - (PORT datac (494:494:494) (581:581:581)) - (PORT datad (484:484:484) (573:573:573)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (834:834:834) (922:922:922)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (288:288:288)) - (PORT datab (592:592:592) (688:688:688)) - (PORT datac (321:321:321) (396:396:396)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (733:733:733) (849:849:849)) - (PORT datab (329:329:329) (390:390:390)) - (PORT datac (789:789:789) (909:909:909)) - (PORT datad (512:512:512) (589:589:589)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (575:575:575)) - (PORT datab (588:588:588) (684:684:684)) - (PORT datac (532:532:532) (607:607:607)) - (PORT datad (560:560:560) (642:642:642)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (495:495:495) (584:584:584)) - (PORT datab (114:114:114) (147:147:147)) - (PORT datac (554:554:554) (643:643:643)) - (PORT datad (560:560:560) (641:641:641)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) - (DELAY - (ABSOLUTE - (PORT datab (359:359:359) (423:423:423)) - (PORT datad (323:323:323) (373:373:373)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (443:443:443)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (595:595:595) (679:679:679)) - (PORT datac (388:388:388) (434:434:434)) - (PORT datad (555:555:555) (631:631:631)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (549:549:549) (631:631:631)) - (PORT datac (289:289:289) (338:338:338)) - (PORT datad (430:430:430) (486:486:486)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (521:521:521)) - (PORT datab (520:520:520) (623:623:623)) - (PORT datac (484:484:484) (578:578:578)) - (PORT datad (473:473:473) (562:562:562)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (531:531:531) (629:629:629)) - (PORT datac (410:410:410) (470:470:470)) - (PORT datad (409:409:409) (497:497:497)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (182:182:182) (181:181:181)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT datab (110:110:110) (140:140:140)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (300:300:300)) - (PORT datac (374:374:374) (454:454:454)) - (PORT datad (499:499:499) (596:596:596)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (477:477:477)) - (PORT datab (598:598:598) (704:704:704)) - (PORT datac (505:505:505) (609:609:609)) - (PORT datad (474:474:474) (561:561:561)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (924:924:924)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (269:269:269)) - (PORT datab (803:803:803) (919:919:919)) - (PORT datac (466:466:466) (540:540:540)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (442:442:442)) - (PORT datab (195:195:195) (235:235:235)) - (PORT datad (243:243:243) (302:302:302)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (440:440:440)) - (PORT datab (291:291:291) (335:335:335)) - (PORT datad (96:96:96) (115:115:115)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (257:257:257)) - (PORT datab (489:489:489) (571:571:571)) - (PORT datac (115:115:115) (157:157:157)) - (PORT datad (434:434:434) (499:499:499)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~134) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (765:765:765)) - (PORT datab (523:523:523) (629:629:629)) - (PORT datad (285:285:285) (327:327:327)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT datac (480:480:480) (568:568:568)) - (PORT datad (366:366:366) (437:437:437)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (463:463:463)) - (PORT datab (176:176:176) (212:212:212)) - (PORT datac (102:102:102) (129:129:129)) - (PORT datad (521:521:521) (618:618:618)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (303:303:303)) - (PORT datab (173:173:173) (211:211:211)) - (PORT datac (266:266:266) (302:302:302)) - (PORT datad (337:337:337) (395:395:395)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (421:421:421)) - (PORT datad (161:161:161) (189:189:189)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datab (666:666:666) (792:792:792)) - (PORT datac (524:524:524) (622:622:622)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (786:786:786)) - (PORT datab (350:350:350) (428:428:428)) - (PORT datac (332:332:332) (412:412:412)) - (PORT datad (315:315:315) (376:376:376)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (496:496:496) (594:594:594)) - (PORT datab (309:309:309) (367:367:367)) - (PORT datac (95:95:95) (120:120:120)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datad (386:386:386) (473:473:473)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (926:926:926)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (283:283:283)) - (PORT datab (472:472:472) (551:551:551)) - (PORT datac (347:347:347) (415:415:415)) - (PORT datad (612:612:612) (705:705:705)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (695:695:695)) - (PORT datab (514:514:514) (619:619:619)) - (PORT datac (323:323:323) (390:390:390)) - (PORT datad (503:503:503) (596:596:596)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~77) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (175:175:175) (231:231:231)) - (PORT datac (327:327:327) (379:379:379)) - (PORT datad (316:316:316) (376:376:376)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (694:694:694)) - (PORT datab (519:519:519) (624:624:624)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (465:465:465)) - (PORT datab (623:623:623) (737:737:737)) - (PORT datac (513:513:513) (618:618:618)) - (PORT datad (364:364:364) (435:435:435)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~75) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (464:464:464)) - (PORT datab (122:122:122) (154:154:154)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (522:522:522) (619:619:619)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (174:174:174) (232:232:232)) - (PORT datac (337:337:337) (402:402:402)) - (PORT datad (169:169:169) (198:198:198)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (293:293:293)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (447:447:447)) - (PORT datab (619:619:619) (732:732:732)) - (PORT datac (343:343:343) (412:412:412)) - (PORT datad (469:469:469) (539:539:539)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (447:447:447)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (307:307:307) (375:375:375)) - (PORT datab (121:121:121) (151:151:151)) - (PORT datac (1138:1138:1138) (1288:1288:1288)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (470:470:470) (547:547:547)) - (PORT datab (170:170:170) (207:207:207)) - (PORT datac (278:278:278) (314:314:314)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1287:1287:1287) (1451:1451:1451)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1688:1688:1688) (1963:1963:1963)) - (PORT d[1] (1055:1055:1055) (1250:1250:1250)) - (PORT d[2] (1536:1536:1536) (1797:1797:1797)) - (PORT d[3] (1370:1370:1370) (1622:1622:1622)) - (PORT d[4] (1097:1097:1097) (1295:1295:1295)) - (PORT d[5] (1770:1770:1770) (2062:2062:2062)) - (PORT d[6] (1121:1121:1121) (1287:1287:1287)) - (PORT d[7] (2338:2338:2338) (2683:2683:2683)) - (PORT d[8] (1421:1421:1421) (1649:1649:1649)) - (PORT d[9] (1602:1602:1602) (1829:1829:1829)) - (PORT d[10] (1045:1045:1045) (1231:1231:1231)) - (PORT d[11] (1090:1090:1090) (1284:1284:1284)) - (PORT d[12] (1809:1809:1809) (2067:2067:2067)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1570:1570:1570) (1738:1738:1738)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (1762:1762:1762) (1942:1942:1942)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (909:909:909) (1051:1051:1051)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1125:1125:1125) (1312:1312:1312)) - (PORT d[1] (1426:1426:1426) (1670:1670:1670)) - (PORT d[2] (1216:1216:1216) (1432:1432:1432)) - (PORT d[3] (705:705:705) (841:841:841)) - (PORT d[4] (1393:1393:1393) (1624:1624:1624)) - (PORT d[5] (2866:2866:2866) (3315:3315:3315)) - (PORT d[6] (1101:1101:1101) (1271:1271:1271)) - (PORT d[7] (926:926:926) (1067:1067:1067)) - (PORT d[8] (1575:1575:1575) (1823:1823:1823)) - (PORT d[9] (1797:1797:1797) (2049:2049:2049)) - (PORT d[10] (1116:1116:1116) (1317:1317:1317)) - (PORT d[11] (1192:1192:1192) (1384:1384:1384)) - (PORT d[12] (730:730:730) (839:839:839)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (942:942:942) (1030:1030:1030)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (1670:1670:1670) (1817:1817:1817)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (915:915:915) (1061:1061:1061)) - (PORT clk (1096:1096:1096) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1105:1105:1105) (1288:1288:1288)) - (PORT d[1] (1574:1574:1574) (1838:1838:1838)) - (PORT d[2] (1216:1216:1216) (1431:1431:1431)) - (PORT d[3] (839:839:839) (973:973:973)) - (PORT d[4] (1257:1257:1257) (1475:1475:1475)) - (PORT d[5] (2860:2860:2860) (3309:3309:3309)) - (PORT d[6] (1232:1232:1232) (1411:1411:1411)) - (PORT d[7] (1069:1069:1069) (1222:1222:1222)) - (PORT d[8] (1766:1766:1766) (2049:2049:2049)) - (PORT d[9] (1786:1786:1786) (2038:2038:2038)) - (PORT d[10] (1107:1107:1107) (1307:1307:1307)) - (PORT d[11] (1213:1213:1213) (1405:1405:1405)) - (PORT d[12] (603:603:603) (699:699:699)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1222:1222:1222) (1337:1337:1337)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (PORT d[0] (1440:1440:1440) (1576:1576:1576)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1023:1023:1023) (1179:1179:1179)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1421:1421:1421) (1654:1654:1654)) - (PORT d[1] (1567:1567:1567) (1835:1835:1835)) - (PORT d[2] (1223:1223:1223) (1448:1448:1448)) - (PORT d[3] (2298:2298:2298) (2697:2697:2697)) - (PORT d[4] (1077:1077:1077) (1271:1271:1271)) - (PORT d[5] (2671:2671:2671) (3095:3095:3095)) - (PORT d[6] (1252:1252:1252) (1445:1445:1445)) - (PORT d[7] (1384:1384:1384) (1580:1580:1580)) - (PORT d[8] (1949:1949:1949) (2252:2252:2252)) - (PORT d[9] (1461:1461:1461) (1670:1670:1670)) - (PORT d[10] (1289:1289:1289) (1518:1518:1518)) - (PORT d[11] (1399:1399:1399) (1618:1618:1618)) - (PORT d[12] (896:896:896) (1018:1018:1018)) - (PORT clk (1085:1085:1085) (1103:1103:1103)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1162:1162:1162) (1283:1283:1283)) - (PORT clk (1085:1085:1085) (1103:1103:1103)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (PORT d[0] (1610:1610:1610) (1788:1788:1788)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1084:1084:1084)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (607:607:607) (616:616:616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (617:617:617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (617:617:617)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (617:617:617)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (260:260:260)) - (PORT datab (860:860:860) (979:979:979)) - (PORT datac (635:635:635) (755:755:755)) - (PORT datad (658:658:658) (741:741:741)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (256:256:256)) - (PORT datab (1011:1011:1011) (1142:1142:1142)) - (PORT datac (832:832:832) (935:935:935)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (598:598:598) (696:696:696)) - (PORT d[1] (1937:1937:1937) (2262:2262:2262)) - (PORT d[2] (1274:1274:1274) (1475:1475:1475)) - (PORT d[3] (571:571:571) (665:665:665)) - (PORT d[4] (403:403:403) (473:473:473)) - (PORT d[5] (709:709:709) (821:821:821)) - (PORT d[6] (1615:1615:1615) (1862:1862:1862)) - (PORT d[7] (1314:1314:1314) (1534:1534:1534)) - (PORT d[8] (2303:2303:2303) (2657:2657:2657)) - (PORT d[9] (1734:1734:1734) (1973:1973:1973)) - (PORT d[10] (1648:1648:1648) (1916:1916:1916)) - (PORT d[11] (1288:1288:1288) (1515:1515:1515)) - (PORT d[12] (1386:1386:1386) (1581:1581:1581)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (PORT d[0] (791:791:791) (866:866:866)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1070:1070:1070) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1052:1052:1052) (1185:1185:1185)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1586:1586:1586) (1821:1821:1821)) - (PORT d[1] (772:772:772) (911:911:911)) - (PORT d[2] (2000:2000:2000) (2357:2357:2357)) - (PORT d[3] (1583:1583:1583) (1874:1874:1874)) - (PORT d[4] (1455:1455:1455) (1712:1712:1712)) - (PORT d[5] (1053:1053:1053) (1205:1205:1205)) - (PORT d[6] (1474:1474:1474) (1704:1704:1704)) - (PORT d[7] (1829:1829:1829) (2118:2118:2118)) - (PORT d[8] (1097:1097:1097) (1247:1247:1247)) - (PORT d[9] (2335:2335:2335) (2652:2652:2652)) - (PORT d[10] (1112:1112:1112) (1281:1281:1281)) - (PORT d[11] (1296:1296:1296) (1530:1530:1530)) - (PORT d[12] (1775:1775:1775) (2032:2032:2032)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (987:987:987) (1068:1068:1068)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (1632:1632:1632) (1774:1774:1774)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1071:1071:1071)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1962:1962:1962) (2222:2222:2222)) - (PORT clk (1057:1057:1057) (1074:1074:1074)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1074:1074:1074) (1242:1242:1242)) - (PORT d[1] (1031:1031:1031) (1190:1190:1190)) - (PORT d[2] (1003:1003:1003) (1163:1163:1163)) - (PORT d[3] (1125:1125:1125) (1336:1336:1336)) - (PORT d[4] (1084:1084:1084) (1251:1251:1251)) - (PORT d[5] (1186:1186:1186) (1371:1371:1371)) - (PORT d[6] (1135:1135:1135) (1304:1304:1304)) - (PORT d[7] (1044:1044:1044) (1209:1209:1209)) - (PORT d[8] (1084:1084:1084) (1261:1261:1261)) - (PORT d[9] (1127:1127:1127) (1301:1301:1301)) - (PORT d[10] (1055:1055:1055) (1233:1233:1233)) - (PORT d[11] (1061:1061:1061) (1229:1229:1229)) - (PORT d[12] (1089:1089:1089) (1257:1257:1257)) - (PORT clk (1054:1054:1054) (1073:1073:1073)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1074:1074:1074)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (419:419:419) (489:489:489)) - (PORT d[1] (1965:1965:1965) (2307:2307:2307)) - (PORT d[2] (1104:1104:1104) (1285:1285:1285)) - (PORT d[3] (578:578:578) (673:673:673)) - (PORT d[4] (1796:1796:1796) (2097:2097:2097)) - (PORT d[5] (531:531:531) (615:615:615)) - (PORT d[6] (1625:1625:1625) (1868:1868:1868)) - (PORT d[7] (1500:1500:1500) (1748:1748:1748)) - (PORT d[8] (561:561:561) (634:634:634)) - (PORT d[9] (1552:1552:1552) (1765:1765:1765)) - (PORT d[10] (1690:1690:1690) (1968:1968:1968)) - (PORT d[11] (1433:1433:1433) (1682:1682:1682)) - (PORT d[12] (1199:1199:1199) (1367:1367:1367)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (1469:1469:1469) (1318:1318:1318)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (900:900:900) (1020:1020:1020)) - (PORT clk (1099:1099:1099) (1117:1117:1117)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1012:1012:1012) (1174:1174:1174)) - (PORT d[1] (989:989:989) (1161:1161:1161)) - (PORT d[2] (2144:2144:2144) (2519:2519:2519)) - (PORT d[3] (1588:1588:1588) (1873:1873:1873)) - (PORT d[4] (1475:1475:1475) (1736:1736:1736)) - (PORT d[5] (1025:1025:1025) (1175:1175:1175)) - (PORT d[6] (1465:1465:1465) (1687:1687:1687)) - (PORT d[7] (1700:1700:1700) (1977:1977:1977)) - (PORT d[8] (1185:1185:1185) (1357:1357:1357)) - (PORT d[9] (2315:2315:2315) (2624:2624:2624)) - (PORT d[10] (1282:1282:1282) (1476:1476:1476)) - (PORT d[11] (1707:1707:1707) (1992:1992:1992)) - (PORT d[12] (1763:1763:1763) (2013:2013:2013)) - (PORT clk (1097:1097:1097) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1007:1007:1007) (1093:1093:1093)) - (PORT clk (1097:1097:1097) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1117:1117:1117)) - (PORT d[0] (1730:1730:1730) (1623:1623:1623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1074:1074:1074)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1970:1970:1970) (2231:2231:2231)) - (PORT clk (1059:1059:1059) (1077:1077:1077)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1053:1053:1053) (1218:1218:1218)) - (PORT d[1] (988:988:988) (1134:1134:1134)) - (PORT d[2] (1045:1045:1045) (1212:1212:1212)) - (PORT d[3] (1072:1072:1072) (1275:1275:1275)) - (PORT d[4] (1101:1101:1101) (1272:1272:1272)) - (PORT d[5] (1211:1211:1211) (1403:1403:1403)) - (PORT d[6] (1112:1112:1112) (1275:1275:1275)) - (PORT d[7] (1035:1035:1035) (1198:1198:1198)) - (PORT d[8] (1157:1157:1157) (1323:1323:1323)) - (PORT d[9] (1026:1026:1026) (1179:1179:1179)) - (PORT d[10] (1031:1031:1031) (1207:1207:1207)) - (PORT d[11] (1060:1060:1060) (1229:1229:1229)) - (PORT d[12] (1086:1086:1086) (1256:1256:1256)) - (PORT clk (1056:1056:1056) (1076:1076:1076)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1059:1059:1059) (1077:1077:1077)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1075:1075:1075)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (759:759:759)) - (PORT datab (164:164:164) (219:219:219)) - (PORT datac (508:508:508) (573:573:573)) - (PORT datad (982:982:982) (1109:1109:1109)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (775:775:775)) - (PORT datab (162:162:162) (218:218:218)) - (PORT datac (816:816:816) (925:925:925)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (609:609:609)) - (PORT datab (534:534:534) (618:618:618)) - (PORT datac (661:661:661) (737:737:737)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1020:1020:1020) (1199:1199:1199)) - (PORT datab (1209:1209:1209) (1418:1418:1418)) - (PORT datac (1885:1885:1885) (2194:2194:2194)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (439:439:439)) - (PORT datab (120:120:120) (151:151:151)) - (PORT datac (715:715:715) (811:811:811)) - (PORT datad (394:394:394) (468:468:468)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (456:456:456)) - (PORT datab (657:657:657) (783:783:783)) - (PORT datac (140:140:140) (181:181:181)) - (PORT datad (303:303:303) (348:348:348)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (864:864:864)) - (PORT datab (119:119:119) (149:149:149)) - (PORT datac (670:670:670) (798:798:798)) - (PORT datad (471:471:471) (542:542:542)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (928:928:928) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (896:896:896) (984:984:984)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (437:437:437)) - (PORT datac (508:508:508) (582:582:582)) - (PORT datad (545:545:545) (628:628:628)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (784:784:784)) - (PORT datab (105:105:105) (135:135:135)) - (PORT datac (320:320:320) (384:384:384)) - (PORT datad (441:441:441) (503:503:503)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (896:896:896)) - (PORT ena (996:996:996) (1096:1096:1096)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT datab (1187:1187:1187) (1369:1369:1369)) - (PORT datac (756:756:756) (897:897:897)) - (PORT datad (747:747:747) (874:874:874)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (825:825:825)) - (PORT datab (424:424:424) (513:513:513)) - (PORT datac (719:719:719) (825:825:825)) - (PORT datad (448:448:448) (520:520:520)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (742:742:742) (849:849:849)) - (PORT datab (894:894:894) (1015:1015:1015)) - (PORT datac (456:456:456) (526:526:526)) - (PORT datad (351:351:351) (417:417:417)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) - (DELAY - (ABSOLUTE - (PORT datab (344:344:344) (406:406:406)) - (PORT datac (107:107:107) (130:130:130)) - (PORT datad (287:287:287) (329:329:329)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (483:483:483) (555:555:555)) - (PORT datab (351:351:351) (411:411:411)) - (PORT datac (459:459:459) (528:528:528)) - (PORT datad (442:442:442) (499:499:499)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (152:152:152)) - (PORT datab (111:111:111) (144:144:144)) - (PORT datac (457:457:457) (532:532:532)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) - (DELAY - (ABSOLUTE - (PORT datab (577:577:577) (670:670:670)) - (PORT datac (549:549:549) (628:628:628)) - (PORT datad (114:114:114) (137:137:137)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (801:801:801)) - (PORT datab (350:350:350) (409:409:409)) - (PORT datac (563:563:563) (659:659:659)) - (PORT datad (112:112:112) (134:134:134)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (275:275:275)) - (PORT datab (472:472:472) (540:540:540)) - (PORT datac (454:454:454) (529:529:529)) - (PORT datad (122:122:122) (146:146:146)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (861:861:861)) - (PORT datab (352:352:352) (419:419:419)) - (PORT datac (346:346:346) (404:404:404)) - (PORT datad (368:368:368) (445:445:445)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (148:148:148)) - (PORT datab (336:336:336) (394:394:394)) - (PORT datac (481:481:481) (545:545:545)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (367:367:367) (429:429:429)) - (PORT datac (442:442:442) (505:505:505)) - (PORT datad (344:344:344) (403:403:403)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1298:1298:1298)) - (PORT datab (835:835:835) (983:983:983)) - (PORT datac (1765:1765:1765) (2070:2070:2070)) - (PORT datad (1372:1372:1372) (1595:1595:1595)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1072:1072:1072) (1248:1248:1248)) - (PORT clk (1096:1096:1096) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2060:2060:2060) (2392:2392:2392)) - (PORT d[1] (1391:1391:1391) (1632:1632:1632)) - (PORT d[2] (1338:1338:1338) (1570:1570:1570)) - (PORT d[3] (1928:1928:1928) (2270:2270:2270)) - (PORT d[4] (1659:1659:1659) (1939:1939:1939)) - (PORT d[5] (2129:2129:2129) (2470:2470:2470)) - (PORT d[6] (930:930:930) (1065:1065:1065)) - (PORT d[7] (1795:1795:1795) (2057:2057:2057)) - (PORT d[8] (1446:1446:1446) (1683:1683:1683)) - (PORT d[9] (1477:1477:1477) (1689:1689:1689)) - (PORT d[10] (1492:1492:1492) (1750:1750:1750)) - (PORT d[11] (878:878:878) (1027:1027:1027)) - (PORT d[12] (1431:1431:1431) (1633:1633:1633)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1118:1118:1118) (1224:1224:1224)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (PORT d[0] (1925:1925:1925) (2119:2119:2119)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1278:1278:1278) (1491:1491:1491)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1297:1297:1297) (1508:1508:1508)) - (PORT d[1] (1592:1592:1592) (1853:1853:1853)) - (PORT d[2] (2519:2519:2519) (2904:2904:2904)) - (PORT d[3] (2119:2119:2119) (2485:2485:2485)) - (PORT d[4] (878:878:878) (1042:1042:1042)) - (PORT d[5] (2505:2505:2505) (2908:2908:2908)) - (PORT d[6] (1287:1287:1287) (1489:1489:1489)) - (PORT d[7] (1429:1429:1429) (1638:1638:1638)) - (PORT d[8] (2127:2127:2127) (2456:2456:2456)) - (PORT d[9] (1270:1270:1270) (1451:1451:1451)) - (PORT d[10] (887:887:887) (1042:1042:1042)) - (PORT d[11] (890:890:890) (1045:1045:1045)) - (PORT d[12] (1084:1084:1084) (1235:1235:1235)) - (PORT clk (1085:1085:1085) (1103:1103:1103)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1463:1463:1463) (1616:1616:1616)) - (PORT clk (1085:1085:1085) (1103:1103:1103)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (PORT d[0] (1286:1286:1286) (1402:1402:1402)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1084:1084:1084)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (607:607:607) (616:616:616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (617:617:617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (617:617:617)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (617:617:617)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1637:1637:1637) (1860:1860:1860)) - (PORT clk (1098:1098:1098) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1819:1819:1819) (2105:2105:2105)) - (PORT d[1] (1013:1013:1013) (1192:1192:1192)) - (PORT d[2] (1673:1673:1673) (1953:1953:1953)) - (PORT d[3] (1322:1322:1322) (1559:1559:1559)) - (PORT d[4] (1273:1273:1273) (1490:1490:1490)) - (PORT d[5] (1572:1572:1572) (1829:1829:1829)) - (PORT d[6] (1118:1118:1118) (1286:1286:1286)) - (PORT d[7] (2493:2493:2493) (2853:2853:2853)) - (PORT d[8] (1397:1397:1397) (1620:1620:1620)) - (PORT d[9] (1610:1610:1610) (1837:1837:1837)) - (PORT d[10] (1069:1069:1069) (1260:1260:1260)) - (PORT d[11] (1098:1098:1098) (1295:1295:1295)) - (PORT d[12] (2002:2002:2002) (2294:2294:2294)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1107:1107:1107) (1220:1220:1220)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (PORT d[0] (1509:1509:1509) (1654:1654:1654)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1254:1254:1254) (1428:1428:1428)) - (PORT clk (1105:1105:1105) (1123:1123:1123)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1597:1597:1597) (1835:1835:1835)) - (PORT d[1] (917:917:917) (1063:1063:1063)) - (PORT d[2] (1810:1810:1810) (2141:2141:2141)) - (PORT d[3] (1510:1510:1510) (1772:1772:1772)) - (PORT d[4] (1312:1312:1312) (1551:1551:1551)) - (PORT d[5] (1364:1364:1364) (1551:1551:1551)) - (PORT d[6] (1320:1320:1320) (1523:1523:1523)) - (PORT d[7] (1547:1547:1547) (1807:1807:1807)) - (PORT d[8] (1720:1720:1720) (2005:2005:2005)) - (PORT d[9] (2016:2016:2016) (2292:2292:2292)) - (PORT d[10] (1451:1451:1451) (1705:1705:1705)) - (PORT d[11] (1587:1587:1587) (1854:1854:1854)) - (PORT d[12] (2090:2090:2090) (2385:2385:2385)) - (PORT clk (1103:1103:1103) (1121:1121:1121)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1169:1169:1169) (1268:1268:1268)) - (PORT clk (1103:1103:1103) (1121:1121:1121)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1123:1123:1123)) - (PORT d[0] (1376:1376:1376) (1487:1487:1487)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1124:1124:1124)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1124:1124:1124)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1124:1124:1124)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1124:1124:1124)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1102:1102:1102)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (625:625:625) (634:634:634)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (626:626:626) (635:635:635)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (626:626:626) (635:635:635)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (626:626:626) (635:635:635)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1311:1311:1311)) - (PORT datab (655:655:655) (781:781:781)) - (PORT datac (1234:1234:1234) (1418:1418:1418)) - (PORT datad (175:175:175) (234:234:234)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (517:517:517) (594:594:594)) - (PORT datab (520:520:520) (595:595:595)) - (PORT datac (631:631:631) (751:751:751)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (788:788:788) (909:909:909)) - (PORT d[1] (1670:1670:1670) (1968:1968:1968)) - (PORT d[2] (1148:1148:1148) (1351:1351:1351)) - (PORT d[3] (217:217:217) (257:257:257)) - (PORT d[4] (354:354:354) (412:412:412)) - (PORT d[5] (890:890:890) (1027:1027:1027)) - (PORT d[6] (1634:1634:1634) (1889:1889:1889)) - (PORT d[7] (1288:1288:1288) (1502:1502:1502)) - (PORT d[8] (2285:2285:2285) (2644:2644:2644)) - (PORT d[9] (503:503:503) (568:568:568)) - (PORT d[10] (1322:1322:1322) (1552:1552:1552)) - (PORT d[11] (1295:1295:1295) (1519:1519:1519)) - (PORT d[12] (599:599:599) (680:680:680)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (985:985:985) (1090:1090:1090)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (915:915:915) (1051:1051:1051)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (817:817:817) (951:951:951)) - (PORT d[1] (1172:1172:1172) (1372:1372:1372)) - (PORT d[2] (1252:1252:1252) (1443:1443:1443)) - (PORT d[3] (1781:1781:1781) (2099:2099:2099)) - (PORT d[4] (1466:1466:1466) (1728:1728:1728)) - (PORT d[5] (898:898:898) (1029:1029:1029)) - (PORT d[6] (1460:1460:1460) (1680:1680:1680)) - (PORT d[7] (1531:1531:1531) (1789:1789:1789)) - (PORT d[8] (1023:1023:1023) (1173:1173:1173)) - (PORT d[9] (2494:2494:2494) (2831:2831:2831)) - (PORT d[10] (1094:1094:1094) (1261:1261:1261)) - (PORT d[11] (2033:2033:2033) (2365:2365:2365)) - (PORT d[12] (1572:1572:1572) (1792:1792:1792)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (857:857:857) (916:916:916)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (PORT d[0] (1629:1629:1629) (1766:1766:1766)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1044:1044:1044) (1064:1064:1064)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1780:1780:1780) (2014:2014:2014)) - (PORT clk (1049:1049:1049) (1067:1067:1067)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1083:1083:1083) (1251:1251:1251)) - (PORT d[1] (1096:1096:1096) (1279:1279:1279)) - (PORT d[2] (1073:1073:1073) (1237:1237:1237)) - (PORT d[3] (1053:1053:1053) (1215:1215:1215)) - (PORT d[4] (1208:1208:1208) (1391:1391:1391)) - (PORT d[5] (1190:1190:1190) (1378:1378:1378)) - (PORT d[6] (1011:1011:1011) (1169:1169:1169)) - (PORT d[7] (1080:1080:1080) (1273:1273:1273)) - (PORT d[8] (1094:1094:1094) (1274:1274:1274)) - (PORT d[9] (1054:1054:1054) (1214:1214:1214)) - (PORT d[10] (1045:1045:1045) (1221:1221:1221)) - (PORT d[11] (1129:1129:1129) (1299:1299:1299)) - (PORT d[12] (1081:1081:1081) (1247:1247:1247)) - (PORT clk (1046:1046:1046) (1066:1066:1066)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (611:611:611) (710:710:710)) - (PORT d[1] (1785:1785:1785) (2105:2105:2105)) - (PORT d[2] (945:945:945) (1098:1098:1098)) - (PORT d[3] (411:411:411) (487:487:487)) - (PORT d[4] (542:542:542) (623:623:623)) - (PORT d[5] (717:717:717) (831:831:831)) - (PORT d[6] (1455:1455:1455) (1682:1682:1682)) - (PORT d[7] (1296:1296:1296) (1511:1511:1511)) - (PORT d[8] (1832:1832:1832) (2136:2136:2136)) - (PORT d[9] (1712:1712:1712) (1943:1943:1943)) - (PORT d[10] (1515:1515:1515) (1772:1772:1772)) - (PORT d[11] (1267:1267:1267) (1499:1499:1499)) - (PORT d[12] (1387:1387:1387) (1582:1582:1582)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (1259:1259:1259) (1134:1134:1134)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (908:908:908) (1032:1032:1032)) - (PORT clk (1091:1091:1091) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (827:827:827) (966:966:966)) - (PORT d[1] (776:776:776) (918:918:918)) - (PORT d[2] (1094:1094:1094) (1268:1268:1268)) - (PORT d[3] (1782:1782:1782) (2100:2100:2100)) - (PORT d[4] (1654:1654:1654) (1934:1934:1934)) - (PORT d[5] (873:873:873) (993:993:993)) - (PORT d[6] (1483:1483:1483) (1709:1709:1709)) - (PORT d[7] (1517:1517:1517) (1769:1769:1769)) - (PORT d[8] (944:944:944) (1079:1079:1079)) - (PORT d[9] (2492:2492:2492) (2825:2825:2825)) - (PORT d[10] (1102:1102:1102) (1271:1271:1271)) - (PORT d[11] (2033:2033:2033) (2366:2366:2366)) - (PORT d[12] (1577:1577:1577) (1803:1803:1803)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (837:837:837) (902:902:902)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (PORT d[0] (1237:1237:1237) (1181:1181:1181)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1046:1046:1046) (1066:1066:1066)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1780:1780:1780) (2016:2016:2016)) - (PORT clk (1051:1051:1051) (1069:1069:1069)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1087:1087:1087) (1256:1256:1256)) - (PORT d[1] (1091:1091:1091) (1271:1271:1271)) - (PORT d[2] (1050:1050:1050) (1214:1214:1214)) - (PORT d[3] (1057:1057:1057) (1220:1220:1220)) - (PORT d[4] (1043:1043:1043) (1204:1204:1204)) - (PORT d[5] (1001:1001:1001) (1155:1155:1155)) - (PORT d[6] (1018:1018:1018) (1179:1179:1179)) - (PORT d[7] (1086:1086:1086) (1278:1278:1278)) - (PORT d[8] (1069:1069:1069) (1243:1243:1243)) - (PORT d[9] (1138:1138:1138) (1314:1314:1314)) - (PORT d[10] (1061:1061:1061) (1237:1237:1237)) - (PORT d[11] (1110:1110:1110) (1280:1280:1280)) - (PORT d[12] (1068:1068:1068) (1232:1232:1232)) - (PORT clk (1048:1048:1048) (1068:1068:1068)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1051:1051:1051) (1069:1069:1069)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1070:1070:1070)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1070:1070:1070)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1070:1070:1070)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1070:1070:1070)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1067:1067:1067)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (443:443:443)) - (PORT datab (555:555:555) (648:648:648)) - (PORT datac (549:549:549) (654:654:654)) - (PORT datad (870:870:870) (986:986:986)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (677:677:677)) - (PORT datab (559:559:559) (645:645:645)) - (PORT datac (793:793:793) (924:924:924)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (648:648:648)) - (PORT datab (666:666:666) (779:779:779)) - (PORT datac (1538:1538:1538) (1800:1800:1800)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (515:515:515) (593:593:593)) - (PORT datab (679:679:679) (799:799:799)) - (PORT datac (757:757:757) (874:874:874)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~80) - (DELAY - (ABSOLUTE - (PORT datac (519:519:519) (603:603:603)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (868:868:868)) - (PORT datab (694:694:694) (825:825:825)) - (PORT datac (465:465:465) (537:537:537)) - (PORT datad (492:492:492) (570:570:570)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (928:928:928) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (896:896:896) (984:984:984)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (655:655:655)) - (PORT datab (609:609:609) (707:707:707)) - (PORT datad (335:335:335) (398:398:398)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (784:784:784)) - (PORT datab (452:452:452) (532:532:532)) - (PORT datac (320:320:320) (384:384:384)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (896:896:896)) - (PORT ena (996:996:996) (1096:1096:1096)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1267:1267:1267) (1467:1467:1467)) - (PORT datab (1042:1042:1042) (1203:1203:1203)) - (PORT datac (1135:1135:1135) (1301:1301:1301)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (916:916:916)) - (PORT datab (505:505:505) (594:594:594)) - (PORT datad (734:734:734) (840:840:840)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (562:562:562) (640:640:640)) - (PORT datab (361:361:361) (427:427:427)) - (PORT datac (631:631:631) (731:731:731)) - (PORT datad (447:447:447) (520:520:520)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) - (DELAY - (ABSOLUTE - (PORT dataa (500:500:500) (602:602:602)) - (PORT datab (381:381:381) (448:448:448)) - (PORT datac (432:432:432) (515:515:515)) - (PORT datad (320:320:320) (371:371:371)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (504:504:504)) - (PORT datab (357:357:357) (420:420:420)) - (PORT datac (466:466:466) (536:536:536)) - (PORT datad (554:554:554) (623:623:623)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (180:180:180) (221:221:221)) - (PORT datab (189:189:189) (229:229:229)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (465:465:465) (523:523:523)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (428:428:428)) - (PORT datab (565:565:565) (682:682:682)) - (PORT datac (103:103:103) (124:124:124)) - (PORT datad (278:278:278) (316:316:316)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (732:732:732) (848:848:848)) - (PORT datab (337:337:337) (400:400:400)) - (PORT datac (788:788:788) (908:908:908)) - (PORT datad (511:511:511) (587:587:587)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (525:525:525)) - (PORT datab (376:376:376) (454:454:454)) - (PORT datac (968:968:968) (1108:1108:1108)) - (PORT datad (592:592:592) (675:675:675)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (572:572:572)) - (PORT datab (604:604:604) (688:688:688)) - (PORT datac (206:206:206) (248:248:248)) - (PORT datad (344:344:344) (401:401:401)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (763:763:763)) - (PORT datab (605:605:605) (689:689:689)) - (PORT datac (852:852:852) (963:963:963)) - (PORT datad (615:615:615) (713:713:713)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (91:91:91) (112:112:112)) - (PORT datad (98:98:98) (119:119:119)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (524:524:524) (627:627:627)) - (PORT datab (372:372:372) (440:440:440)) - (PORT datac (858:858:858) (970:970:970)) - (PORT datad (516:516:516) (620:620:620)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (475:475:475)) - (PORT datab (309:309:309) (364:364:364)) - (PORT datac (858:858:858) (971:971:971)) - (PORT datad (356:356:356) (417:417:417)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (353:353:353) (416:416:416)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (829:829:829)) - (PORT datab (326:326:326) (382:382:382)) - (PORT datac (717:717:717) (823:823:823)) - (PORT datad (450:450:450) (523:523:523)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (299:299:299) (349:349:349)) - (PORT datab (638:638:638) (741:741:741)) - (PORT datac (438:438:438) (509:509:509)) - (PORT datad (289:289:289) (330:330:330)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (982:982:982)) - (PORT datab (529:529:529) (618:618:618)) - (PORT datac (650:650:650) (730:730:730)) - (PORT datad (118:118:118) (142:142:142)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (303:303:303) (353:353:353)) - (PORT datab (641:641:641) (745:745:745)) - (PORT datac (337:337:337) (397:397:397)) - (PORT datad (161:161:161) (188:188:188)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (684:684:684)) - (PORT datab (587:587:587) (675:675:675)) - (PORT datac (329:329:329) (389:389:389)) - (PORT datad (608:608:608) (700:700:700)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (309:309:309) (356:356:356)) - (PORT datab (289:289:289) (337:337:337)) - (PORT datac (814:814:814) (924:924:924)) - (PORT datad (288:288:288) (330:330:330)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (111:111:111) (145:145:145)) - (PORT datab (973:973:973) (1134:1134:1134)) - (PORT datac (820:820:820) (944:944:944)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (734:734:734)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (529:529:529)) - (PORT datab (452:452:452) (525:525:525)) - (PORT datac (433:433:433) (502:502:502)) - (PORT datad (322:322:322) (378:378:378)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (438:438:438)) - (PORT datab (211:211:211) (256:256:256)) - (PORT datac (532:532:532) (606:606:606)) - (PORT datad (170:170:170) (199:199:199)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (555:555:555)) - (PORT datab (836:836:836) (949:949:949)) - (PORT datac (544:544:544) (621:621:621)) - (PORT datad (553:553:553) (625:625:625)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~39) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (722:722:722) (820:820:820)) - (PORT datac (462:462:462) (538:538:538)) - (PORT datad (570:570:570) (645:645:645)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (416:416:416)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (317:317:317) (365:365:365)) - (PORT datad (695:695:695) (789:789:789)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (346:346:346) (411:411:411)) - (PORT datac (263:263:263) (297:297:297)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (657:657:657)) - (PORT datab (110:110:110) (141:141:141)) - (PORT datad (556:556:556) (650:650:650)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (991:991:991) (1166:1166:1166)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1697:1697:1697) (1975:1975:1975)) - (PORT d[1] (1053:1053:1053) (1244:1244:1244)) - (PORT d[2] (1371:1371:1371) (1612:1612:1612)) - (PORT d[3] (1559:1559:1559) (1841:1841:1841)) - (PORT d[4] (1260:1260:1260) (1476:1476:1476)) - (PORT d[5] (1765:1765:1765) (2052:2052:2052)) - (PORT d[6] (1129:1129:1129) (1296:1296:1296)) - (PORT d[7] (2155:2155:2155) (2469:2469:2469)) - (PORT d[8] (1247:1247:1247) (1448:1448:1448)) - (PORT d[9] (1596:1596:1596) (1821:1821:1821)) - (PORT d[10] (1084:1084:1084) (1277:1277:1277)) - (PORT d[11] (1073:1073:1073) (1258:1258:1258)) - (PORT d[12] (1818:1818:1818) (2082:2082:2082)) - (PORT clk (1085:1085:1085) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1266:1266:1266) (1386:1386:1386)) - (PORT clk (1085:1085:1085) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1104:1104:1104)) - (PORT d[0] (1558:1558:1558) (1705:1705:1705)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1083:1083:1083)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (607:607:607) (615:615:615)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1129:1129:1129) (1307:1307:1307)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1864:1864:1864) (2167:2167:2167)) - (PORT d[1] (1223:1223:1223) (1438:1438:1438)) - (PORT d[2] (1822:1822:1822) (2116:2116:2116)) - (PORT d[3] (1555:1555:1555) (1833:1833:1833)) - (PORT d[4] (1278:1278:1278) (1499:1499:1499)) - (PORT d[5] (1761:1761:1761) (2048:2048:2048)) - (PORT d[6] (1303:1303:1303) (1497:1497:1497)) - (PORT d[7] (2138:2138:2138) (2447:2447:2447)) - (PORT d[8] (1241:1241:1241) (1441:1441:1441)) - (PORT d[9] (1607:1607:1607) (1833:1833:1833)) - (PORT d[10] (1101:1101:1101) (1300:1300:1300)) - (PORT d[11] (1073:1073:1073) (1261:1261:1261)) - (PORT d[12] (1818:1818:1818) (2087:2087:2087)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1120:1120:1120) (1233:1233:1233)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (PORT d[0] (1774:1774:1774) (1959:1959:1959)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1069:1069:1069) (1086:1086:1086)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (609:609:609) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (964:964:964) (1099:1099:1099)) - (PORT clk (1085:1085:1085) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1292:1292:1292) (1503:1503:1503)) - (PORT d[1] (1575:1575:1575) (1839:1839:1839)) - (PORT d[2] (1202:1202:1202) (1421:1421:1421)) - (PORT d[3] (2114:2114:2114) (2486:2486:2486)) - (PORT d[4] (1055:1055:1055) (1246:1246:1246)) - (PORT d[5] (2510:2510:2510) (2910:2910:2910)) - (PORT d[6] (1273:1273:1273) (1469:1469:1469)) - (PORT d[7] (1418:1418:1418) (1624:1624:1624)) - (PORT d[8] (1946:1946:1946) (2251:2251:2251)) - (PORT d[9] (1436:1436:1436) (1638:1638:1638)) - (PORT d[10] (887:887:887) (1037:1037:1037)) - (PORT d[11] (1567:1567:1567) (1806:1806:1806)) - (PORT d[12] (1075:1075:1075) (1226:1226:1226)) - (PORT clk (1083:1083:1083) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1209:1209:1209) (1341:1341:1341)) - (PORT clk (1083:1083:1083) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1104:1104:1104)) - (PORT d[0] (1591:1591:1591) (1765:1765:1765)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1086:1086:1086) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1086:1086:1086) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1086:1086:1086) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1086:1086:1086) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1083:1083:1083)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (615:615:615)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (606:606:606) (616:616:616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (606:606:606) (616:616:616)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (606:606:606) (616:616:616)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (257:257:257)) - (PORT datab (851:851:851) (970:970:970)) - (PORT datac (629:629:629) (748:748:748)) - (PORT datad (513:513:513) (584:584:584)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (782:782:782) (899:899:899)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1593:1593:1593) (1845:1845:1845)) - (PORT d[1] (1397:1397:1397) (1635:1635:1635)) - (PORT d[2] (2518:2518:2518) (2903:2903:2903)) - (PORT d[3] (2112:2112:2112) (2473:2473:2473)) - (PORT d[4] (1848:1848:1848) (2153:2153:2153)) - (PORT d[5] (2489:2489:2489) (2888:2888:2888)) - (PORT d[6] (1431:1431:1431) (1649:1649:1649)) - (PORT d[7] (1569:1569:1569) (1791:1791:1791)) - (PORT d[8] (2120:2120:2120) (2444:2444:2444)) - (PORT d[9] (1269:1269:1269) (1450:1450:1450)) - (PORT d[10] (721:721:721) (857:857:857)) - (PORT d[11] (884:884:884) (1038:1038:1038)) - (PORT d[12] (1084:1084:1084) (1236:1236:1236)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1460:1460:1460) (1619:1619:1619)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (1239:1239:1239) (1347:1347:1347)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1069:1069:1069) (1085:1085:1085)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (609:609:609) (617:617:617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (985:985:985)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (628:628:628) (747:747:747)) - (PORT datad (479:479:479) (534:534:534)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (788:788:788) (920:920:920)) - (PORT clk (1093:1093:1093) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (834:834:834) (977:977:977)) - (PORT d[1] (944:944:944) (1107:1107:1107)) - (PORT d[2] (1092:1092:1092) (1261:1261:1261)) - (PORT d[3] (1771:1771:1771) (2083:2083:2083)) - (PORT d[4] (1483:1483:1483) (1748:1748:1748)) - (PORT d[5] (849:849:849) (977:977:977)) - (PORT d[6] (1496:1496:1496) (1726:1726:1726)) - (PORT d[7] (1499:1499:1499) (1746:1746:1746)) - (PORT d[8] (932:932:932) (1067:1067:1067)) - (PORT d[9] (1717:1717:1717) (1944:1944:1944)) - (PORT d[10] (1033:1033:1033) (1184:1184:1184)) - (PORT d[11] (2201:2201:2201) (2553:2553:2553)) - (PORT d[12] (1587:1587:1587) (1819:1819:1819)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (838:838:838) (900:900:900)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (PORT d[0] (1150:1150:1150) (1226:1226:1226)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1048:1048:1048) (1067:1067:1067)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1771:1771:1771) (2004:2004:2004)) - (PORT clk (1053:1053:1053) (1070:1070:1070)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1087:1087:1087) (1255:1255:1255)) - (PORT d[1] (1076:1076:1076) (1250:1250:1250)) - (PORT d[2] (1064:1064:1064) (1231:1231:1231)) - (PORT d[3] (1080:1080:1080) (1249:1249:1249)) - (PORT d[4] (1086:1086:1086) (1255:1255:1255)) - (PORT d[5] (1025:1025:1025) (1186:1186:1186)) - (PORT d[6] (1042:1042:1042) (1218:1218:1218)) - (PORT d[7] (1083:1083:1083) (1276:1276:1276)) - (PORT d[8] (1156:1156:1156) (1328:1328:1328)) - (PORT d[9] (1128:1128:1128) (1304:1304:1304)) - (PORT d[10] (1071:1071:1071) (1250:1250:1250)) - (PORT d[11] (1098:1098:1098) (1260:1260:1260)) - (PORT d[12] (1120:1120:1120) (1327:1327:1327)) - (PORT clk (1050:1050:1050) (1069:1069:1069)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1053:1053:1053) (1070:1070:1070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (794:794:794) (915:915:915)) - (PORT d[1] (1670:1670:1670) (1969:1969:1969)) - (PORT d[2] (980:980:980) (1159:1159:1159)) - (PORT d[3] (343:343:343) (394:394:394)) - (PORT d[4] (356:356:356) (416:416:416)) - (PORT d[5] (891:891:891) (1027:1027:1027)) - (PORT d[6] (1467:1467:1467) (1698:1698:1698)) - (PORT d[7] (1280:1280:1280) (1489:1489:1489)) - (PORT d[8] (1838:1838:1838) (2138:2138:2138)) - (PORT d[9] (508:508:508) (573:573:573)) - (PORT d[10] (1310:1310:1310) (1532:1532:1532)) - (PORT d[11] (1600:1600:1600) (1831:1831:1831)) - (PORT d[12] (617:617:617) (700:700:700)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (975:975:975) (1075:1075:1075)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (610:610:610) (707:707:707)) - (PORT d[1] (1630:1630:1630) (1913:1913:1913)) - (PORT d[2] (1156:1156:1156) (1357:1357:1357)) - (PORT d[3] (549:549:549) (635:635:635)) - (PORT d[4] (397:397:397) (465:465:465)) - (PORT d[5] (718:718:718) (832:832:832)) - (PORT d[6] (1665:1665:1665) (1927:1927:1927)) - (PORT d[7] (1296:1296:1296) (1515:1515:1515)) - (PORT d[8] (2146:2146:2146) (2484:2484:2484)) - (PORT d[9] (1897:1897:1897) (2155:2155:2155)) - (PORT d[10] (1501:1501:1501) (1751:1751:1751)) - (PORT d[11] (1276:1276:1276) (1499:1499:1499)) - (PORT d[12] (1373:1373:1373) (1565:1565:1565)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (PORT d[0] (1258:1258:1258) (1133:1133:1133)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1074:1074:1074) (1090:1090:1090)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (614:614:614) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (772:772:772) (903:903:903)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (990:990:990) (1149:1149:1149)) - (PORT d[1] (1172:1172:1172) (1371:1371:1371)) - (PORT d[2] (2003:2003:2003) (2359:2359:2359)) - (PORT d[3] (1735:1735:1735) (2046:2046:2046)) - (PORT d[4] (1291:1291:1291) (1528:1528:1528)) - (PORT d[5] (1007:1007:1007) (1151:1151:1151)) - (PORT d[6] (1316:1316:1316) (1525:1525:1525)) - (PORT d[7] (1677:1677:1677) (1953:1953:1953)) - (PORT d[8] (1013:1013:1013) (1160:1160:1160)) - (PORT d[9] (2323:2323:2323) (2633:2633:2633)) - (PORT d[10] (1106:1106:1106) (1274:1274:1274)) - (PORT d[11] (1282:1282:1282) (1511:1511:1511)) - (PORT d[12] (1562:1562:1562) (1779:1779:1779)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1011:1011:1011) (1094:1094:1094)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (1767:1767:1767) (1654:1654:1654)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1068:1068:1068)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1950:1950:1950) (2208:2208:2208)) - (PORT clk (1054:1054:1054) (1071:1071:1071)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1079:1079:1079) (1248:1248:1248)) - (PORT d[1] (1030:1030:1030) (1190:1190:1190)) - (PORT d[2] (1056:1056:1056) (1224:1224:1224)) - (PORT d[3] (1108:1108:1108) (1314:1314:1314)) - (PORT d[4] (1041:1041:1041) (1195:1195:1195)) - (PORT d[5] (1039:1039:1039) (1213:1213:1213)) - (PORT d[6] (1142:1142:1142) (1311:1311:1311)) - (PORT d[7] (1082:1082:1082) (1278:1278:1278)) - (PORT d[8] (1152:1152:1152) (1320:1320:1320)) - (PORT d[9] (1137:1137:1137) (1313:1313:1313)) - (PORT d[10] (1041:1041:1041) (1214:1214:1214)) - (PORT d[11] (1117:1117:1117) (1282:1282:1282)) - (PORT d[12] (1075:1075:1075) (1236:1236:1236)) - (PORT clk (1051:1051:1051) (1070:1070:1070)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1069:1069:1069)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (679:679:679)) - (PORT datab (554:554:554) (647:647:647)) - (PORT datac (483:483:483) (554:554:554)) - (PORT datad (851:851:851) (959:959:959)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (676:676:676)) - (PORT datab (860:860:860) (983:983:983)) - (PORT datac (625:625:625) (710:710:710)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1576:1576:1576) (1849:1849:1849)) - (PORT datab (661:661:661) (774:774:774)) - (PORT datac (540:540:540) (613:613:613)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (182:182:182) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (485:485:485) (582:582:582)) - (PORT datab (679:679:679) (800:800:800)) - (PORT datac (493:493:493) (570:570:570)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (625:625:625)) - (PORT datac (102:102:102) (123:123:123)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (870:870:870)) - (PORT datab (696:696:696) (827:827:827)) - (PORT datac (442:442:442) (505:505:505)) - (PORT datad (360:360:360) (427:427:427)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (928:928:928) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (896:896:896) (984:984:984)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (411:411:411)) - (PORT datac (635:635:635) (771:771:771)) - (PORT datad (545:545:545) (628:628:628)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (494:494:494) (585:585:585)) - (PORT datab (342:342:342) (409:409:409)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (335:335:335) (398:398:398)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (896:896:896)) - (PORT ena (996:996:996) (1096:1096:1096)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (761:761:761) (901:901:901)) - (PORT datab (724:724:724) (831:831:831)) - (PORT datac (154:154:154) (211:211:211)) - (PORT datad (156:156:156) (207:207:207)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (412:412:412)) - (PORT datab (593:593:593) (685:685:685)) - (PORT datac (297:297:297) (344:344:344)) - (PORT datad (1565:1565:1565) (1788:1788:1788)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT asdata (344:344:344) (372:372:372)) - (PORT clrn (911:911:911) (895:895:895)) - (PORT ena (1043:1043:1043) (1160:1160:1160)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (354:354:354)) - (PORT datab (140:140:140) (188:188:188)) - (PORT datad (647:647:647) (777:777:777)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (307:307:307) (358:358:358)) - (PORT datab (349:349:349) (408:408:408)) - (PORT datac (563:563:563) (658:658:658)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (724:724:724)) - (PORT datab (402:402:402) (460:460:460)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (680:680:680) (803:803:803)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (655:655:655)) - (PORT datab (487:487:487) (573:573:573)) - (PORT datad (334:334:334) (397:397:397)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (348:348:348) (415:415:415)) - (PORT datac (633:633:633) (769:769:769)) - (PORT datad (579:579:579) (664:664:664)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (896:896:896)) - (PORT ena (996:996:996) (1096:1096:1096)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (1173:1173:1173) (1371:1371:1371)) - (PORT datad (1310:1310:1310) (1518:1518:1518)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) - (DELAY - (ABSOLUTE - (PORT dataa (774:774:774) (879:879:879)) - (PORT datab (903:903:903) (1044:1044:1044)) - (PORT datac (471:471:471) (540:540:540)) - (PORT datad (335:335:335) (390:390:390)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (259:259:259)) - (PORT datab (169:169:169) (229:229:229)) - (PORT datac (139:139:139) (185:185:185)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (149:149:149)) - (PORT datab (597:597:597) (686:686:686)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (916:916:916) (901:901:901)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (828:828:828)) - (PORT datab (325:325:325) (380:380:380)) - (PORT datac (410:410:410) (493:493:493)) - (PORT datad (450:450:450) (522:522:522)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (312:312:312) (367:367:367)) - (PORT datab (294:294:294) (346:346:346)) - (PORT datac (571:571:571) (652:652:652)) - (PORT datad (706:706:706) (807:807:807)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (735:735:735)) - (PORT datab (401:401:401) (471:471:471)) - (PORT datac (1060:1060:1060) (1200:1200:1200)) - (PORT datad (443:443:443) (506:506:506)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (523:523:523) (606:606:606)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (400:400:400)) - (PORT datab (705:705:705) (839:839:839)) - (PORT datac (452:452:452) (528:528:528)) - (PORT datad (706:706:706) (807:807:807)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (479:479:479) (560:560:560)) - (PORT datab (891:891:891) (1024:1024:1024)) - (PORT datac (597:597:597) (680:680:680)) - (PORT datad (285:285:285) (320:320:320)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (313:313:313) (368:368:368)) - (PORT datab (477:477:477) (546:546:546)) - (PORT datac (614:614:614) (697:697:697)) - (PORT datad (493:493:493) (567:567:567)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (290:290:290) (337:337:337)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (644:644:644)) - (PORT datab (382:382:382) (462:462:462)) - (PORT datac (508:508:508) (613:613:613)) - (PORT datad (606:606:606) (714:714:714)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~125) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (298:298:298)) - (PORT datab (105:105:105) (135:135:135)) - (PORT datad (102:102:102) (125:125:125)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~126) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (764:764:764)) - (PORT datab (516:516:516) (619:619:619)) - (PORT datad (331:331:331) (400:400:400)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (254:254:254) (320:320:320)) - (PORT datac (577:577:577) (672:672:672)) - (PORT datad (282:282:282) (320:320:320)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (195:195:195) (237:237:237)) - (PORT datad (384:384:384) (470:470:470)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (442:442:442)) - (PORT datab (1048:1048:1048) (1186:1186:1186)) - (PORT datac (117:117:117) (158:158:158)) - (PORT datad (461:461:461) (536:536:536)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (484:484:484)) - (PORT datab (338:338:338) (417:417:417)) - (PORT datac (626:626:626) (733:733:733)) - (PORT datad (327:327:327) (397:397:397)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~138) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (761:761:761)) - (PORT datab (148:148:148) (198:198:198)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (225:225:225)) - (PORT datab (175:175:175) (212:212:212)) - (PORT datad (503:503:503) (603:603:603)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (736:736:736)) - (PORT datab (250:250:250) (314:314:314)) - (PORT datac (344:344:344) (426:426:426)) - (PORT datad (495:495:495) (586:586:586)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~122) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (781:781:781)) - (PORT datab (244:244:244) (307:307:307)) - (PORT datac (708:708:708) (807:807:807)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~123) - (DELAY - (ABSOLUTE - (PORT datab (358:358:358) (414:414:414)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (573:573:573)) - (PORT datab (213:213:213) (269:269:269)) - (PORT datac (447:447:447) (509:509:509)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~129) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (141:141:141)) - (PORT datab (397:397:397) (492:492:492)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (926:926:926)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (912:912:912) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (537:537:537) (646:646:646)) - (PORT datab (380:380:380) (460:460:460)) - (PORT datac (513:513:513) (617:617:617)) - (PORT datad (604:604:604) (711:711:711)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (298:298:298)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datad (102:102:102) (124:124:124)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (917:917:917)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (431:431:431)) - (PORT datab (481:481:481) (570:570:570)) - (PORT datac (528:528:528) (615:615:615)) - (PORT datad (450:450:450) (529:529:529)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (148:148:148)) - (PORT datab (345:345:345) (408:408:408)) - (PORT datad (186:186:186) (216:216:216)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (449:449:449)) - (PORT datab (490:490:490) (565:565:565)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (433:433:433)) - (PORT datab (119:119:119) (148:148:148)) - (PORT datac (1139:1139:1139) (1290:1290:1290)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (569:569:569)) - (PORT datab (338:338:338) (394:394:394)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (316:316:316) (366:366:366)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1424:1424:1424) (1637:1637:1637)) - (PORT clk (1099:1099:1099) (1117:1117:1117)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1682:1682:1682) (1953:1953:1953)) - (PORT d[1] (1040:1040:1040) (1225:1225:1225)) - (PORT d[2] (1639:1639:1639) (1912:1912:1912)) - (PORT d[3] (1321:1321:1321) (1556:1556:1556)) - (PORT d[4] (1083:1083:1083) (1274:1274:1274)) - (PORT d[5] (1422:1422:1422) (1657:1657:1657)) - (PORT d[6] (1133:1133:1133) (1300:1300:1300)) - (PORT d[7] (2522:2522:2522) (2886:2886:2886)) - (PORT d[8] (1404:1404:1404) (1627:1627:1627)) - (PORT d[9] (1567:1567:1567) (1784:1784:1784)) - (PORT d[10] (1066:1066:1066) (1252:1252:1252)) - (PORT d[11] (1091:1091:1091) (1280:1280:1280)) - (PORT d[12] (1984:1984:1984) (2262:2262:2262)) - (PORT clk (1097:1097:1097) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1510:1510:1510) (1663:1663:1663)) - (PORT clk (1097:1097:1097) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1117:1117:1117)) - (PORT d[0] (1417:1417:1417) (1554:1554:1554)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1079:1079:1079) (1096:1096:1096)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (628:628:628)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1566:1566:1566) (1805:1805:1805)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1685:1685:1685) (1958:1958:1958)) - (PORT d[1] (1052:1052:1052) (1243:1243:1243)) - (PORT d[2] (1687:1687:1687) (1965:1965:1965)) - (PORT d[3] (1371:1371:1371) (1623:1623:1623)) - (PORT d[4] (1257:1257:1257) (1476:1476:1476)) - (PORT d[5] (1777:1777:1777) (2070:2070:2070)) - (PORT d[6] (1128:1128:1128) (1295:1295:1295)) - (PORT d[7] (2169:2169:2169) (2489:2489:2489)) - (PORT d[8] (1248:1248:1248) (1448:1448:1448)) - (PORT d[9] (1613:1613:1613) (1841:1841:1841)) - (PORT d[10] (953:953:953) (1129:1129:1129)) - (PORT d[11] (1101:1101:1101) (1298:1298:1298)) - (PORT d[12] (1824:1824:1824) (2090:2090:2090)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1268:1268:1268) (1393:1393:1393)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (PORT d[0] (1412:1412:1412) (1544:1544:1544)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1069:1069:1069) (1086:1086:1086)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (609:609:609) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1738:1738:1738) (1995:1995:1995)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2058:2058:2058) (2391:2391:2391)) - (PORT d[1] (1231:1231:1231) (1449:1449:1449)) - (PORT d[2] (1978:1978:1978) (2287:2287:2287)) - (PORT d[3] (1741:1741:1741) (2051:2051:2051)) - (PORT d[4] (1451:1451:1451) (1695:1695:1695)) - (PORT d[5] (1943:1943:1943) (2255:2255:2255)) - (PORT d[6] (1314:1314:1314) (1507:1507:1507)) - (PORT d[7] (1975:1975:1975) (2263:2263:2263)) - (PORT d[8] (1245:1245:1245) (1451:1451:1451)) - (PORT d[9] (1432:1432:1432) (1631:1631:1631)) - (PORT d[10] (1304:1304:1304) (1538:1538:1538)) - (PORT d[11] (1054:1054:1054) (1241:1241:1241)) - (PORT d[12] (1615:1615:1615) (1845:1845:1845)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1272:1272:1272) (1399:1399:1399)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1112:1112:1112)) - (PORT d[0] (1682:1682:1682) (1861:1861:1861)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1074:1074:1074) (1091:1091:1091)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (614:614:614) (623:623:623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1391:1391:1391) (1606:1606:1606)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1675:1675:1675) (1950:1950:1950)) - (PORT d[1] (1021:1021:1021) (1204:1204:1204)) - (PORT d[2] (1548:1548:1548) (1811:1811:1811)) - (PORT d[3] (1351:1351:1351) (1598:1598:1598)) - (PORT d[4] (1280:1280:1280) (1498:1498:1498)) - (PORT d[5] (1582:1582:1582) (1840:1840:1840)) - (PORT d[6] (1108:1108:1108) (1272:1272:1272)) - (PORT d[7] (2343:2343:2343) (2686:2686:2686)) - (PORT d[8] (1416:1416:1416) (1644:1644:1644)) - (PORT d[9] (1604:1604:1604) (1830:1830:1830)) - (PORT d[10] (1059:1059:1059) (1242:1242:1242)) - (PORT d[11] (1083:1083:1083) (1271:1271:1271)) - (PORT d[12] (1809:1809:1809) (2067:2067:2067)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1285:1285:1285) (1424:1424:1424)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1112:1112:1112)) - (PORT d[0] (1503:1503:1503) (1649:1649:1649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1074:1074:1074) (1091:1091:1091)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (614:614:614) (623:623:623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (950:950:950)) - (PORT datab (343:343:343) (391:391:391)) - (PORT datac (540:540:540) (630:630:630)) - (PORT datad (664:664:664) (746:746:746)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (950:950:950)) - (PORT datab (554:554:554) (650:650:650)) - (PORT datac (644:644:644) (723:723:723)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (621:621:621) (721:721:721)) - (PORT d[1] (1660:1660:1660) (1959:1959:1959)) - (PORT d[2] (1155:1155:1155) (1354:1354:1354)) - (PORT d[3] (403:403:403) (477:477:477)) - (PORT d[4] (386:386:386) (455:455:455)) - (PORT d[5] (895:895:895) (1038:1038:1038)) - (PORT d[6] (1642:1642:1642) (1893:1893:1893)) - (PORT d[7] (1142:1142:1142) (1335:1335:1335)) - (PORT d[8] (2293:2293:2293) (2652:2652:2652)) - (PORT d[9] (460:460:460) (526:526:526)) - (PORT d[10] (1483:1483:1483) (1729:1729:1729)) - (PORT d[11] (1301:1301:1301) (1530:1530:1530)) - (PORT d[12] (739:739:739) (838:838:838)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (1125:1125:1125) (1250:1250:1250)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1092:1092:1092)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (924:924:924) (1054:1054:1054)) - (PORT clk (1102:1102:1102) (1119:1119:1119)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1001:1001:1001) (1160:1160:1160)) - (PORT d[1] (988:988:988) (1160:1160:1160)) - (PORT d[2] (1994:1994:1994) (2350:2350:2350)) - (PORT d[3] (1501:1501:1501) (1748:1748:1748)) - (PORT d[4] (1473:1473:1473) (1730:1730:1730)) - (PORT d[5] (1063:1063:1063) (1218:1218:1218)) - (PORT d[6] (1283:1283:1283) (1482:1482:1482)) - (PORT d[7] (1688:1688:1688) (1969:1969:1969)) - (PORT d[8] (1197:1197:1197) (1370:1370:1370)) - (PORT d[9] (2315:2315:2315) (2628:2628:2628)) - (PORT d[10] (1294:1294:1294) (1488:1488:1488)) - (PORT d[11] (1764:1764:1764) (2049:2049:2049)) - (PORT d[12] (1932:1932:1932) (2207:2207:2207)) - (PORT clk (1100:1100:1100) (1117:1117:1117)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (982:982:982) (1059:1059:1059)) - (PORT clk (1100:1100:1100) (1117:1117:1117)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1102:1102:1102) (1119:1119:1119)) - (PORT d[0] (1474:1474:1474) (1592:1592:1592)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1076:1076:1076)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1971:1971:1971) (2232:2232:2232)) - (PORT clk (1062:1062:1062) (1079:1079:1079)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1098:1098:1098) (1281:1281:1281)) - (PORT d[1] (1103:1103:1103) (1293:1293:1293)) - (PORT d[2] (1008:1008:1008) (1170:1170:1170)) - (PORT d[3] (1098:1098:1098) (1298:1298:1298)) - (PORT d[4] (1091:1091:1091) (1259:1259:1259)) - (PORT d[5] (1208:1208:1208) (1397:1397:1397)) - (PORT d[6] (967:967:967) (1120:1120:1120)) - (PORT d[7] (1159:1159:1159) (1359:1359:1359)) - (PORT d[8] (1122:1122:1122) (1296:1296:1296)) - (PORT d[9] (1136:1136:1136) (1306:1306:1306)) - (PORT d[10] (1195:1195:1195) (1393:1393:1393)) - (PORT d[11] (1054:1054:1054) (1222:1222:1222)) - (PORT d[12] (1070:1070:1070) (1231:1231:1231)) - (PORT clk (1059:1059:1059) (1078:1078:1078)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (229:229:229) (268:268:268)) - (PORT d[1] (1969:1969:1969) (2309:2309:2309)) - (PORT d[2] (1095:1095:1095) (1276:1276:1276)) - (PORT d[3] (2331:2331:2331) (2742:2742:2742)) - (PORT d[4] (1775:1775:1775) (2071:2071:2071)) - (PORT d[5] (533:533:533) (623:623:623)) - (PORT d[6] (1810:1810:1810) (2081:2081:2081)) - (PORT d[7] (352:352:352) (405:405:405)) - (PORT d[8] (554:554:554) (626:626:626)) - (PORT d[9] (1543:1543:1543) (1755:1755:1755)) - (PORT d[10] (496:496:496) (576:576:576)) - (PORT d[11] (826:826:826) (941:941:941)) - (PORT d[12] (1176:1176:1176) (1338:1338:1338)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (1662:1662:1662) (1488:1488:1488)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1092:1092:1092)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1111:1111:1111) (1268:1268:1268)) - (PORT clk (1105:1105:1105) (1123:1123:1123)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1737:1737:1737) (1990:1990:1990)) - (PORT d[1] (967:967:967) (1137:1137:1137)) - (PORT d[2] (1925:1925:1925) (2266:2266:2266)) - (PORT d[3] (1380:1380:1380) (1638:1638:1638)) - (PORT d[4] (1477:1477:1477) (1726:1726:1726)) - (PORT d[5] (1233:1233:1233) (1407:1407:1407)) - (PORT d[6] (1320:1320:1320) (1528:1528:1528)) - (PORT d[7] (1676:1676:1676) (1941:1941:1941)) - (PORT d[8] (1379:1379:1379) (1581:1581:1581)) - (PORT d[9] (2146:2146:2146) (2438:2438:2438)) - (PORT d[10] (1465:1465:1465) (1682:1682:1682)) - (PORT d[11] (1537:1537:1537) (1801:1801:1801)) - (PORT d[12] (1965:1965:1965) (2248:2248:2248)) - (PORT clk (1103:1103:1103) (1121:1121:1121)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1165:1165:1165) (1274:1274:1274)) - (PORT clk (1103:1103:1103) (1121:1121:1121)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1123:1123:1123)) - (PORT d[0] (1928:1928:1928) (1800:1800:1800)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1124:1124:1124)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1124:1124:1124)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1124:1124:1124)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1124:1124:1124)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1060:1060:1060) (1080:1080:1080)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2145:2145:2145) (2428:2428:2428)) - (PORT clk (1065:1065:1065) (1083:1083:1083)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1011:1011:1011) (1172:1172:1172)) - (PORT d[1] (1120:1120:1120) (1311:1311:1311)) - (PORT d[2] (1150:1150:1150) (1327:1327:1327)) - (PORT d[3] (1119:1119:1119) (1323:1323:1323)) - (PORT d[4] (1049:1049:1049) (1213:1213:1213)) - (PORT d[5] (992:992:992) (1146:1146:1146)) - (PORT d[6] (1125:1125:1125) (1292:1292:1292)) - (PORT d[7] (1031:1031:1031) (1194:1194:1194)) - (PORT d[8] (1147:1147:1147) (1321:1321:1321)) - (PORT d[9] (1077:1077:1077) (1244:1244:1244)) - (PORT d[10] (1210:1210:1210) (1411:1411:1411)) - (PORT d[11] (1145:1145:1145) (1325:1325:1325)) - (PORT d[12] (1254:1254:1254) (1441:1441:1441)) - (PORT clk (1062:1062:1062) (1082:1082:1082)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1083:1083:1083)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1066:1066:1066) (1084:1084:1084)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1066:1066:1066) (1084:1084:1084)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1066:1066:1066) (1084:1084:1084)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1066:1066:1066) (1084:1084:1084)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1061:1061:1061) (1081:1081:1081)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (638:638:638)) - (PORT datab (308:308:308) (352:352:352)) - (PORT datac (513:513:513) (603:603:603)) - (PORT datad (797:797:797) (909:909:909)) - (IOPATH dataa combout (188:188:188) (193:193:193)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~1) - (DELAY - (ABSOLUTE - (PORT dataa (529:529:529) (628:628:628)) - (PORT datab (550:550:550) (630:630:630)) - (PORT datac (902:902:902) (1028:1028:1028)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (496:496:496)) - (PORT datab (909:909:909) (1038:1038:1038)) - (PORT datac (343:343:343) (406:406:406)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (984:984:984)) - (PORT datab (1903:1903:1903) (2226:2226:2226)) - (PORT datac (1015:1015:1015) (1189:1189:1189)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (141:141:141)) - (PORT datab (119:119:119) (149:149:149)) - (PORT datac (174:174:174) (202:202:202)) - (PORT datad (396:396:396) (470:470:470)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (394:394:394)) - (PORT datab (141:141:141) (189:189:189)) - (PORT datac (359:359:359) (430:430:430)) - (PORT datad (643:643:643) (759:759:759)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (869:869:869)) - (PORT datab (695:695:695) (826:826:826)) - (PORT datac (471:471:471) (550:550:550)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (928:928:928) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (896:896:896) (984:984:984)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (434:434:434)) - (PORT datac (515:515:515) (598:598:598)) - (PORT datad (544:544:544) (627:627:627)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (786:786:786)) - (PORT datab (208:208:208) (246:246:246)) - (PORT datac (321:321:321) (385:385:385)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (896:896:896)) - (PORT ena (996:996:996) (1096:1096:1096)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) - (DELAY - (ABSOLUTE - (PORT datab (537:537:537) (643:643:643)) - (PORT datac (527:527:527) (629:629:629)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (707:707:707)) - (PORT datab (506:506:506) (596:596:596)) - (PORT datac (1118:1118:1118) (1287:1287:1287)) - (PORT datad (636:636:636) (731:731:731)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (954:954:954)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (499:499:499) (594:594:594)) - (PORT datad (439:439:439) (501:501:501)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (916:916:916) (901:901:901)) - (PORT ena (491:491:491) (528:528:528)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (261:261:261)) - (PORT datab (499:499:499) (597:597:597)) - (PORT datac (482:482:482) (575:575:575)) - (PORT datad (156:156:156) (206:206:206)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (916:916:916) (901:901:901)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) - (DELAY - (ABSOLUTE - (PORT datab (467:467:467) (560:560:560)) - (PORT datad (119:119:119) (158:158:158)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (903:903:903)) - (PORT ena (639:639:639) (693:693:693)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT datab (151:151:151) (201:201:201)) - (PORT datac (486:486:486) (563:563:563)) - (PORT datad (481:481:481) (559:559:559)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (903:903:903)) - (PORT ena (639:639:639) (693:693:693)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (595:595:595)) - (PORT datac (129:129:129) (171:171:171)) - (PORT datad (478:478:478) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (903:903:903)) - (PORT ena (639:639:639) (693:693:693)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (146:146:146) (196:196:196)) - (PORT datac (491:491:491) (569:569:569)) - (PORT datad (476:476:476) (553:553:553)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (903:903:903)) - (PORT ena (639:639:639) (693:693:693)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) - (DELAY - (ABSOLUTE - (PORT dataa (769:769:769) (908:908:908)) - (PORT datac (630:630:630) (750:750:750)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT dataa (274:274:274) (323:323:323)) - (PORT datad (717:717:717) (817:817:817)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) - (DELAY - (ABSOLUTE - (PORT dataa (125:125:125) (159:159:159)) - (PORT datab (122:122:122) (153:153:153)) - (PORT datac (929:929:929) (1054:1054:1054)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (733:733:733)) - (PORT datab (479:479:479) (554:554:554)) - (PORT datac (92:92:92) (116:116:116)) - (PORT datad (439:439:439) (506:506:506)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (306:306:306) (357:357:357)) - (PORT datab (916:916:916) (1054:1054:1054)) - (PORT datac (886:886:886) (1030:1030:1030)) - (PORT datad (1032:1032:1032) (1220:1220:1220)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (684:684:684)) - (PORT datab (481:481:481) (560:560:560)) - (PORT datac (424:424:424) (487:487:487)) - (PORT datad (1002:1002:1002) (1116:1116:1116)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT datab (685:685:685) (781:781:781)) - (PORT datac (546:546:546) (615:615:615)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (409:409:409)) - (PORT datab (349:349:349) (424:424:424)) - (PORT datac (96:96:96) (121:121:121)) - (PORT datad (307:307:307) (365:365:365)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (119:119:119) (151:151:151)) - (PORT datab (528:528:528) (617:617:617)) - (PORT datac (104:104:104) (128:128:128)) - (PORT datad (120:120:120) (145:145:145)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (428:428:428)) - (PORT datab (549:549:549) (629:629:629)) - (PORT datac (627:627:627) (720:720:720)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (743:743:743)) - (PORT datab (645:645:645) (746:746:746)) - (PORT datac (428:428:428) (493:493:493)) - (PORT datad (552:552:552) (627:627:627)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (344:344:344) (407:407:407)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (323:323:323) (380:380:380)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (450:450:450) (518:518:518)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (601:601:601)) - (PORT datad (473:473:473) (549:549:549)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (903:903:903)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT dataa (144:144:144) (196:196:196)) - (PORT datac (487:487:487) (564:564:564)) - (PORT datad (481:481:481) (558:558:558)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (903:903:903)) - (PORT ena (639:639:639) (693:693:693)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (813:813:813)) - (PORT datab (725:725:725) (846:846:846)) - (PORT datad (623:623:623) (722:722:722)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (796:796:796)) - (PORT datab (735:735:735) (864:864:864)) - (PORT datac (546:546:546) (624:624:624)) - (PORT datad (465:465:465) (536:536:536)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (474:474:474) (544:544:544)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (495:495:495) (571:571:571)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (403:403:403)) - (PORT datab (120:120:120) (150:150:150)) - (PORT datac (647:647:647) (759:759:759)) - (PORT datad (832:832:832) (938:938:938)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (787:787:787)) - (PORT datab (735:735:735) (845:845:845)) - (PORT datac (336:336:336) (392:392:392)) - (PORT datad (452:452:452) (520:520:520)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) - (DELAY - (ABSOLUTE - (PORT datab (518:518:518) (589:589:589)) - (PORT datac (543:543:543) (620:620:620)) - (PORT datad (93:93:93) (113:113:113)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (472:472:472)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (386:386:386) (429:429:429)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (453:453:453) (523:523:523)) - (PORT datac (352:352:352) (414:414:414)) - (PORT datad (562:562:562) (636:636:636)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (560:560:560)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (107:107:107) (125:125:125)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (931:931:931)) - (PORT datab (872:872:872) (1005:1005:1005)) - (PORT datac (1011:1011:1011) (1182:1182:1182)) - (PORT datad (1028:1028:1028) (1215:1215:1215)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) - (DELAY - (ABSOLUTE - (PORT dataa (768:768:768) (891:891:891)) - (PORT datab (480:480:480) (557:557:557)) - (PORT datac (748:748:748) (865:865:865)) - (PORT datad (489:489:489) (567:567:567)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~12) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (615:615:615)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (281:281:281) (322:322:322)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (432:432:432)) - (PORT datab (572:572:572) (674:674:674)) - (PORT datac (482:482:482) (581:581:581)) - (PORT datad (480:480:480) (565:565:565)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT datab (122:122:122) (152:152:152)) - (PORT datac (285:285:285) (333:333:333)) - (PORT datad (602:602:602) (707:707:707)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (533:533:533)) - (PORT datab (723:723:723) (830:830:830)) - (PORT datac (601:601:601) (697:697:697)) - (PORT datad (414:414:414) (472:472:472)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (140:140:140)) - (PORT datab (111:111:111) (141:141:141)) - (PORT datac (365:365:365) (427:427:427)) - (PORT datad (752:752:752) (864:864:864)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (728:728:728)) - (PORT datab (574:574:574) (658:658:658)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (419:419:419) (476:476:476)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (442:442:442) (516:516:516)) - (PORT datab (348:348:348) (413:413:413)) - (PORT datac (561:561:561) (636:636:636)) - (PORT datad (1002:1002:1002) (1116:1116:1116)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (743:743:743)) - (PORT datab (591:591:591) (681:681:681)) - (PORT datac (1104:1104:1104) (1271:1271:1271)) - (PORT datad (168:168:168) (199:199:199)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (713:713:713) (841:841:841)) - (PORT datab (644:644:644) (756:756:756)) - (PORT datac (313:313:313) (373:373:373)) - (PORT datad (118:118:118) (157:157:157)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (778:778:778) (924:924:924)) - (PORT datab (527:527:527) (634:634:634)) - (PORT datac (680:680:680) (763:763:763)) - (PORT datad (530:530:530) (635:635:635)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~24) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (997:997:997)) - (PORT datab (520:520:520) (611:611:611)) - (PORT datac (456:456:456) (522:522:522)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (463:463:463) (548:548:548)) - (PORT datab (141:141:141) (190:190:190)) - (PORT datac (101:101:101) (121:121:121)) - (PORT datad (574:574:574) (657:657:657)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (496:496:496) (591:591:591)) - (PORT datac (742:742:742) (854:854:854)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~28) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (640:640:640)) - (PORT datab (564:564:564) (654:654:654)) - (PORT datac (958:958:958) (1114:1114:1114)) - (PORT datad (323:323:323) (375:375:375)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (402:402:402)) - (PORT datab (662:662:662) (767:767:767)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (631:631:631) (728:728:728)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (657:657:657)) - (PORT datab (595:595:595) (677:677:677)) - (PORT datac (555:555:555) (638:638:638)) - (PORT datad (442:442:442) (516:516:516)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~29) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (397:397:397)) - (PORT datab (696:696:696) (788:788:788)) - (PORT datac (284:284:284) (325:325:325)) - (PORT datad (284:284:284) (326:326:326)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (339:339:339)) - (PORT datab (555:555:555) (650:650:650)) - (PORT datac (105:105:105) (128:128:128)) - (PORT datad (556:556:556) (626:626:626)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~34) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (148:148:148)) - (PORT datab (460:460:460) (534:534:534)) - (PORT datac (282:282:282) (327:327:327)) - (PORT datad (447:447:447) (516:516:516)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~54) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (558:558:558)) - (PORT datab (622:622:622) (720:720:720)) - (PORT datac (741:741:741) (876:876:876)) - (PORT datad (712:712:712) (830:830:830)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (819:819:819)) - (PORT datab (477:477:477) (563:563:563)) - (PORT datac (542:542:542) (620:620:620)) - (PORT datad (456:456:456) (519:519:519)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (464:464:464) (553:553:553)) - (PORT datab (291:291:291) (336:336:336)) - (PORT datac (527:527:527) (601:601:601)) - (PORT datad (581:581:581) (671:671:671)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~35) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (857:857:857)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (158:158:158) (190:190:190)) - (PORT datad (418:418:418) (476:476:476)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (594:594:594)) - (PORT datab (154:154:154) (207:207:207)) - (PORT datad (479:479:479) (556:556:556)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (903:903:903)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT datac (390:390:390) (472:472:472)) - (PORT datad (555:555:555) (666:666:666)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (446:446:446)) - (PORT datab (891:891:891) (1005:1005:1005)) - (PORT datac (999:999:999) (1124:1124:1124)) - (PORT datad (571:571:571) (645:645:645)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (148:148:148)) - (PORT datab (965:965:965) (1113:1113:1113)) - (PORT datac (445:445:445) (513:513:513)) - (PORT datad (111:111:111) (132:132:132)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) - (DELAY - (ABSOLUTE - (PORT dataa (468:468:468) (547:547:547)) - (PORT datab (762:762:762) (876:876:876)) - (PORT datac (440:440:440) (509:509:509)) - (PORT datad (601:601:601) (687:687:687)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~37) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (132:132:132)) - (PORT datab (122:122:122) (154:154:154)) - (PORT datac (450:450:450) (519:519:519)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~38) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (707:707:707)) - (PORT datab (185:185:185) (222:222:222)) - (PORT datac (713:713:713) (813:813:813)) - (PORT datad (456:456:456) (529:529:529)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (140:140:140)) - (PORT datab (775:775:775) (890:890:890)) - (PORT datac (291:291:291) (333:333:333)) - (PORT datad (594:594:594) (682:682:682)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (356:356:356)) - (PORT datab (776:776:776) (892:892:892)) - (PORT datac (347:347:347) (403:403:403)) - (PORT datad (708:708:708) (796:796:796)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (143:143:143)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (443:443:443) (515:515:515)) - (PORT datad (443:443:443) (501:501:501)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (487:487:487)) - (PORT datab (426:426:426) (495:495:495)) - (PORT datac (373:373:373) (455:455:455)) - (PORT datad (392:392:392) (450:450:450)) - (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (191:191:191) (188:188:188)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (323:323:323) (386:386:386)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datad (844:844:844) (1001:1001:1001)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (404:404:404) (454:454:454)) - (PORT sload (892:892:892) (1000:1000:1000)) - (PORT ena (1155:1155:1155) (1286:1286:1286)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (444:444:444)) - (PORT datab (1903:1903:1903) (2226:2226:2226)) - (PORT datac (658:658:658) (781:781:781)) - (PORT datad (389:389:389) (461:461:461)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (551:551:551)) - (PORT datab (645:645:645) (771:771:771)) - (PORT datac (378:378:378) (450:450:450)) - (PORT datad (101:101:101) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (459:459:459)) - (PORT datab (1255:1255:1255) (1455:1455:1455)) - (PORT datac (164:164:164) (196:196:196)) - (PORT datad (1746:1746:1746) (2042:2042:2042)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (762:762:762)) - (PORT datab (368:368:368) (441:441:441)) - (PORT datac (314:314:314) (359:359:359)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1460:1460:1460)) - (PORT datab (127:127:127) (159:159:159)) - (PORT datac (1764:1764:1764) (2069:2069:2069)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (949:949:949)) - (PORT datab (927:927:927) (1077:1077:1077)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (102:102:102) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (1900:1900:1900) (2223:2223:2223)) - (PORT datac (662:662:662) (785:785:785)) - (PORT datad (397:397:397) (471:471:471)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (574:574:574)) - (PORT datab (798:798:798) (929:929:929)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~3) - (DELAY - (ABSOLUTE - (PORT dataa (514:514:514) (602:602:602)) - (PORT datab (145:145:145) (196:196:196)) - (PORT datac (136:136:136) (182:182:182)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (903:903:903)) - (PORT ena (639:639:639) (693:693:693)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (361:361:361) (430:430:430)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (654:654:654) (712:712:712)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (911:911:911)) - (PORT asdata (468:468:468) (523:523:523)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (761:761:761) (826:826:826)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (305:305:305) (371:371:371)) - (PORT datab (134:134:134) (184:184:184)) - (PORT datad (122:122:122) (161:161:161)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (141:141:141) (196:196:196)) - (PORT datab (107:107:107) (138:138:138)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[0\]\~15) - (DELAY - (ABSOLUTE - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1141:1141:1141) (1103:1103:1103)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (190:190:190)) - (PORT datab (135:135:135) (185:185:185)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1141:1141:1141) (1103:1103:1103)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT datab (134:134:134) (184:184:184)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1141:1141:1141) (1103:1103:1103)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (185:185:185)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1141:1141:1141) (1103:1103:1103)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (136:136:136) (185:185:185)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1141:1141:1141) (1103:1103:1103)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (137:137:137) (188:188:188)) - (IOPATH dataa combout (188:188:188) (193:193:193)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1141:1141:1141) (1103:1103:1103)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (189:189:189)) - (PORT datab (136:136:136) (187:187:187)) - (PORT datac (121:121:121) (164:164:164)) - (PORT datad (123:123:123) (162:162:162)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|WideAnd0) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (185:185:185)) - (PORT datac (121:121:121) (164:164:164)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Idle) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT ena (546:546:546) (523:523:523)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|phase\~0) - (DELAY - (ABSOLUTE - (PORT datad (147:147:147) (191:191:191)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|phase\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT ena (546:546:546) (523:523:523)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|phase\~1) - (DELAY - (ABSOLUTE - (PORT dataa (161:161:161) (217:217:217)) - (PORT datad (134:134:134) (173:173:173)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|phase\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT ena (546:546:546) (523:523:523)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Mux42\~0) - (DELAY - (ABSOLUTE - (PORT datac (602:602:602) (708:708:708)) - (PORT datad (356:356:356) (425:425:425)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~6) - (DELAY - (ABSOLUTE - (PORT dataa (148:148:148) (206:206:206)) - (PORT datab (466:466:466) (555:555:555)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~0) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (737:737:737)) - (PORT datab (405:405:405) (492:492:492)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT datac (230:230:230) (290:290:290)) - (PORT datad (357:357:357) (426:426:426)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE I2C_SDAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (153:153:153) (705:705:705)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (294:294:294)) - (PORT datab (581:581:581) (673:673:673)) - (PORT datac (223:223:223) (282:282:282)) - (PORT datad (274:274:274) (291:291:291)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (126:126:126) (158:158:158)) - (PORT datac (385:385:385) (471:471:471)) - (PORT datad (168:168:168) (196:196:196)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT datab (370:370:370) (448:448:448)) - (PORT datac (415:415:415) (468:468:468)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (916:916:916) (922:922:922)) - (PORT ena (421:421:421) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (302:302:302)) - (PORT datab (467:467:467) (555:555:555)) - (PORT datad (210:210:210) (267:267:267)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (699:699:699)) - (PORT datab (467:467:467) (556:556:556)) - (PORT datac (342:342:342) (418:418:418)) - (PORT datad (366:366:366) (442:442:442)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (449:449:449) (528:528:528)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (212:212:212)) - (PORT datab (429:429:429) (496:496:496)) - (PORT datac (111:111:111) (137:137:137)) - (PORT datad (351:351:351) (423:423:423)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1112:1112:1112) (1138:1138:1138)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (916:916:916) (922:922:922)) - (PORT ena (576:576:576) (620:620:620)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) - (DELAY - (ABSOLUTE - (PORT dataa (151:151:151) (210:210:210)) - (PORT datab (138:138:138) (188:188:188)) - (PORT datac (442:442:442) (525:525:525)) - (PORT datad (127:127:127) (167:167:167)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) - (DELAY - (ABSOLUTE - (PORT dataa (145:145:145) (202:202:202)) - (PORT datab (147:147:147) (197:197:197)) - (PORT datac (132:132:132) (175:175:175)) - (PORT datad (139:139:139) (180:180:180)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (399:399:399)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (417:417:417) (482:482:482)) - (PORT datad (147:147:147) (192:192:192)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~2) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (235:235:235)) - (PORT datab (219:219:219) (259:259:259)) - (PORT datad (138:138:138) (179:179:179)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (182:182:182) (177:177:177)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT dataa (147:147:147) (202:202:202)) - (PORT datac (233:233:233) (292:292:292)) - (PORT datad (401:401:401) (471:471:471)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (153:153:153)) - (PORT datac (605:605:605) (711:711:711)) - (PORT datad (358:358:358) (428:428:428)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT datab (149:149:149) (199:199:199)) - (PORT datac (265:265:265) (301:301:301)) - (PORT datad (203:203:203) (252:252:252)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT datab (325:325:325) (379:379:379)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (598:598:598) (662:662:662)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT sload (450:450:450) (512:512:512)) - (PORT ena (546:546:546) (523:523:523)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~5) - (DELAY - (ABSOLUTE - (PORT datab (469:469:469) (558:558:558)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1112:1112:1112) (1138:1138:1138)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (916:916:916) (922:922:922)) - (PORT ena (576:576:576) (620:620:620)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~0) - (DELAY - (ABSOLUTE - (PORT dataa (147:147:147) (205:205:205)) - (PORT datab (467:467:467) (556:556:556)) - (PORT datad (125:125:125) (165:165:165)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1112:1112:1112) (1138:1138:1138)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (916:916:916) (922:922:922)) - (PORT ena (576:576:576) (620:620:620)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) - (DELAY - (ABSOLUTE - (PORT datab (138:138:138) (189:189:189)) - (PORT datac (136:136:136) (186:186:186)) - (PORT datad (127:127:127) (168:168:168)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) - (DELAY - (ABSOLUTE - (PORT dataa (145:145:145) (202:202:202)) - (PORT datab (178:178:178) (217:217:217)) - (PORT datac (264:264:264) (299:299:299)) - (PORT datad (138:138:138) (178:178:178)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (400:400:400)) - (PORT datab (152:152:152) (204:204:204)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (147:147:147) (191:191:191)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (454:454:454)) - (PORT datab (332:332:332) (398:398:398)) - (PORT datac (389:389:389) (475:475:475)) - (PORT datad (561:561:561) (646:646:646)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (233:233:233) (297:297:297)) - (IOPATH datab combout (192:192:192) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (383:383:383)) - (PORT datab (472:472:472) (557:557:557)) - (PORT datac (317:317:317) (372:372:372)) - (PORT datad (388:388:388) (419:419:419)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (541:541:541)) - (PORT datab (331:331:331) (396:396:396)) - (PORT datac (412:412:412) (464:464:464)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1131:1131:1131)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1291:1291:1291) (1458:1458:1458)) - (PORT clrn (915:915:915) (922:922:922)) - (PORT sload (971:971:971) (894:894:894)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (159:159:159) (216:216:216)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1131:1131:1131)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1292:1292:1292) (1459:1459:1459)) - (PORT clrn (915:915:915) (922:922:922)) - (PORT sload (971:971:971) (894:894:894)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT datab (162:162:162) (219:219:219)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1131:1131:1131)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (922:922:922)) - (PORT sload (971:971:971) (894:894:894)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (159:159:159) (214:214:214)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1131:1131:1131)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1293:1293:1293) (1460:1460:1460)) - (PORT clrn (915:915:915) (922:922:922)) - (PORT sload (971:971:971) (894:894:894)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (412:412:412)) - (PORT datab (242:242:242) (301:301:301)) - (PORT datac (215:215:215) (275:275:275)) - (PORT datad (213:213:213) (263:263:263)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT datad (146:146:146) (191:191:191)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1131:1131:1131)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (922:922:922)) - (PORT sload (971:971:971) (894:894:894)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) - (DELAY - (ABSOLUTE - (PORT datab (105:105:105) (135:135:135)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (217:217:217) (269:269:269)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (224:224:224) (265:265:265)) - (PORT datad (317:317:317) (368:368:368)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (182:182:182) (177:177:177)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Pause) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~25) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (200:200:200)) - (PORT datab (436:436:436) (507:507:507)) - (PORT datad (147:147:147) (193:193:193)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Start) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT ena (546:546:546) (523:523:523)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~4) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (727:727:727)) - (PORT datab (413:413:413) (502:502:502)) - (PORT datad (403:403:403) (473:473:473)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (916:916:916) (922:922:922)) - (PORT ena (421:421:421) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) - (DELAY - (ABSOLUTE - (PORT dataa (152:152:152) (207:207:207)) - (PORT datac (228:228:228) (287:287:287)) - (PORT datad (396:396:396) (466:466:466)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (403:403:403)) - (PORT datab (220:220:220) (260:260:260)) - (PORT datad (161:161:161) (188:188:188)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (182:182:182) (177:177:177)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Stop) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|scl_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (147:147:147) (196:196:196)) - (PORT datac (133:133:133) (177:177:177)) - (PORT datad (138:138:138) (177:177:177)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1127:1127:1127) (1160:1160:1160)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (916:916:916) (922:922:922)) - (PORT ena (731:731:731) (693:693:693)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|scl_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (698:698:698)) - (PORT datab (133:133:133) (181:181:181)) - (PORT datac (452:452:452) (532:532:532)) - (PORT datad (366:366:366) (442:442:442)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (188:188:188) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|scl_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (308:308:308) (369:369:369)) - (PORT datac (448:448:448) (527:527:527)) - (PORT datad (92:92:92) (111:111:111)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|scl_out) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (887:887:887)) - (PORT d (557:557:557) (510:510:510)) - (PORT aload (1026:1026:1026) (1069:1069:1069)) - (PORT ena (365:365:365) (351:351:351)) - (IOPATH (posedge clk) q (345:345:345) (339:339:339)) - (IOPATH (posedge aload) q (286:286:286) (280:280:280)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (40:40:40)) - (SETUP ena (posedge clk) (40:40:40)) - (HOLD d (posedge clk) (58:58:58)) - (HOLD ena (posedge clk) (58:58:58)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|sda_out\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1127:1127:1127) (1160:1160:1160)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (916:916:916) (922:922:922)) - (PORT ena (731:731:731) (693:693:693)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Mux35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (409:409:409)) - (PORT datab (241:241:241) (300:300:300)) - (PORT datac (212:212:212) (272:272:272)) - (PORT datad (214:214:214) (264:264:264)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (404:404:404) (495:495:495)) - (PORT datac (213:213:213) (273:273:273)) - (PORT datad (213:213:213) (264:264:264)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (442:442:442)) - (PORT datac (598:598:598) (703:703:703)) - (PORT datad (351:351:351) (421:421:421)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (148:148:148)) - (PORT datab (411:411:411) (500:500:500)) - (PORT datac (112:112:112) (137:137:137)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (429:429:429) (496:496:496)) - (PORT datad (351:351:351) (423:423:423)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (922:922:922)) - (PORT sclr (601:601:601) (718:718:718)) - (PORT ena (484:484:484) (512:512:512)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) - (DELAY - (ABSOLUTE - (PORT datac (459:459:459) (545:545:545)) - (PORT datad (454:454:454) (534:534:534)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (412:412:412)) - (PORT datab (234:234:234) (292:292:292)) - (PORT datac (214:214:214) (275:275:275)) - (PORT datad (213:213:213) (264:264:264)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (325:325:325)) - (PORT datab (240:240:240) (300:300:300)) - (PORT datac (212:212:212) (271:271:271)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datac (391:391:391) (477:477:477)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (438:438:438)) - (PORT datab (406:406:406) (493:493:493)) - (PORT datac (101:101:101) (128:128:128)) - (PORT datad (357:357:357) (427:427:427)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (429:429:429) (496:496:496)) - (PORT datac (599:599:599) (705:705:705)) - (PORT datad (351:351:351) (423:423:423)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (922:922:922)) - (PORT ena (515:515:515) (553:553:553)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (160:160:160) (218:218:218)) - (PORT datab (160:160:160) (214:214:214)) - (PORT datac (217:217:217) (277:277:277)) - (PORT datad (145:145:145) (190:190:190)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (180:180:180) (218:218:218)) - (PORT datab (163:163:163) (220:220:220)) - (PORT datac (217:217:217) (278:278:278)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (182:182:182)) - (PORT datac (388:388:388) (474:474:474)) - (PORT datad (172:172:172) (203:203:203)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (922:922:922)) - (PORT ena (515:515:515) (553:553:553)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) - (DELAY - (ABSOLUTE - (PORT datac (148:148:148) (198:198:198)) - (PORT datad (146:146:146) (191:191:191)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (160:160:160) (217:217:217)) - (PORT datab (163:163:163) (218:218:218)) - (PORT datac (147:147:147) (197:197:197)) - (PORT datad (149:149:149) (194:194:194)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (149:149:149)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (216:216:216) (276:276:276)) - (PORT datad (148:148:148) (193:193:193)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (481:481:481)) - (PORT datab (130:130:130) (179:179:179)) - (PORT datac (389:389:389) (475:475:475)) - (PORT datad (165:165:165) (194:194:194)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (922:922:922)) - (PORT ena (515:515:515) (553:553:553)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (159:159:159) (216:216:216)) - (PORT datab (162:162:162) (218:218:218)) - (PORT datac (216:216:216) (276:276:276)) - (PORT datad (148:148:148) (193:193:193)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (148:148:148)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (216:216:216) (276:276:276)) - (PORT datad (148:148:148) (193:193:193)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (477:477:477)) - (PORT datab (132:132:132) (180:180:180)) - (PORT datac (383:383:383) (468:468:468)) - (PORT datad (172:172:172) (204:204:204)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (922:922:922)) - (PORT ena (515:515:515) (553:553:553)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (231:231:231)) - (PORT datab (435:435:435) (516:516:516)) - (PORT datad (198:198:198) (249:249:249)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (916:916:916) (922:922:922)) - (PORT sload (740:740:740) (837:837:837)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (257:257:257)) - (PORT datac (385:385:385) (471:471:471)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (922:922:922)) - (PORT sclr (601:601:601) (718:718:718)) - (PORT ena (515:515:515) (553:553:553)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT datac (393:393:393) (479:479:479)) - (PORT datad (119:119:119) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (922:922:922)) - (PORT sclr (601:601:601) (718:718:718)) - (PORT ena (484:484:484) (512:512:512)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|sda_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (258:258:258)) - (PORT datab (409:409:409) (501:501:501)) - (PORT datac (313:313:313) (370:370:370)) - (PORT datad (560:560:560) (645:645:645)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|sda_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (270:270:270) (316:316:316)) - (PORT datab (293:293:293) (340:340:340)) - (PORT datac (589:589:589) (682:682:682)) - (PORT datad (274:274:274) (292:292:292)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|sda_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (140:140:140) (195:195:195)) - (PORT datab (388:388:388) (470:470:470)) - (PORT datac (590:590:590) (683:683:683)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|sda_out\~3) - (DELAY - (ABSOLUTE - (PORT dataa (140:140:140) (195:195:195)) - (PORT datab (388:388:388) (470:470:470)) - (PORT datac (588:588:588) (681:681:681)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (174:174:174)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|sda_out\~4) - (DELAY - (ABSOLUTE - (PORT dataa (313:313:313) (374:374:374)) - (PORT datab (469:469:469) (555:555:555)) - (PORT datac (92:92:92) (115:115:115)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|sda_out) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (889:889:889)) - (PORT d (382:382:382) (357:357:357)) - (PORT aload (1034:1034:1034) (1078:1078:1078)) - (PORT ena (595:595:595) (557:557:557)) - (IOPATH (posedge clk) q (345:345:345) (339:339:339)) - (IOPATH (posedge aload) q (286:286:286) (280:280:280)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (40:40:40)) - (SETUP ena (posedge clk) (40:40:40)) - (HOLD d (posedge clk) (58:58:58)) - (HOLD ena (posedge clk) (58:58:58)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|mclk_r) - (DELAY - (ABSOLUTE - (PORT clk (891:891:891) (913:913:913)) - (PORT d (1402:1402:1402) (1266:1266:1266)) - (PORT clrn (1029:1029:1029) (1076:1076:1076)) - (IOPATH (posedge clk) q (329:329:329) (329:329:329)) - (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (41:41:41)) - (HOLD d (posedge clk) (56:56:56)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrclk_r) - (DELAY - (ABSOLUTE - (PORT clk (889:889:889) (911:911:911)) - (PORT d (1603:1603:1603) (1789:1789:1789)) - (PORT clrn (1027:1027:1027) (1074:1074:1074)) - (IOPATH (posedge clk) q (329:329:329) (329:329:329)) - (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (41:41:41)) - (HOLD d (posedge clk) (56:56:56)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (891:891:891) (912:912:912)) - (PORT d (1824:1824:1824) (2024:2024:2024)) - (PORT clrn (1029:1029:1029) (1075:1075:1075)) - (IOPATH (posedge clk) q (329:329:329) (329:329:329)) - (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (41:41:41)) - (HOLD d (posedge clk) (56:56:56)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bclk_r) - (DELAY - (ABSOLUTE - (PORT clk (888:888:888) (910:910:910)) - (PORT d (812:812:812) (890:890:890)) - (PORT clrn (1026:1026:1026) (1073:1073:1073)) - (IOPATH (posedge clk) q (329:329:329) (329:329:329)) - (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (41:41:41)) - (HOLD d (posedge clk) (56:56:56)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|pcm_outl\[14\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (924:924:924)) + (PORT clk (909:909:909) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (658:658:658) (708:708:708)) + (PORT ena (1213:1213:1213) (1335:1335:1335)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -53620,11 +53876,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (213:213:213) (277:277:277)) - (PORT datab (650:650:650) (749:749:749)) - (PORT datad (191:191:191) (240:240:240)) + (PORT dataa (683:683:683) (796:796:796)) + (PORT datac (555:555:555) (662:662:662)) + (PORT datad (356:356:356) (415:415:415)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53634,10 +53890,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1094:1094:1094) (1112:1112:1112)) + (PORT clk (1108:1108:1108) (1141:1141:1141)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (PORT ena (1552:1552:1552) (1715:1715:1715)) + (PORT clrn (907:907:907) (913:913:913)) + (PORT ena (599:599:599) (641:641:641)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53652,10 +53908,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) (DELAY (ABSOLUTE - (PORT datab (649:649:649) (748:748:748)) - (PORT datac (308:308:308) (364:364:364)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datac (116:116:116) (157:157:157)) + (PORT datad (357:357:357) (416:416:416)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -53664,10 +53920,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1094:1094:1094) (1112:1112:1112)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (PORT ena (1552:1552:1552) (1715:1715:1715)) + (PORT clrn (907:907:907) (913:913:913)) + (PORT ena (617:617:617) (670:670:670)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53682,10 +53938,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (647:647:647) (746:746:746)) - (PORT datac (188:188:188) (236:236:236)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (354:354:354) (413:413:413)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -53695,9 +53951,9 @@ (DELAY (ABSOLUTE (PORT clk (893:893:893) (915:915:915)) - (PORT d (1084:1084:1084) (1192:1192:1192)) + (PORT d (827:827:827) (902:902:902)) (PORT clrn (1031:1031:1031) (1077:1077:1077)) - (PORT ena (451:451:451) (477:477:477)) + (PORT ena (946:946:946) (1053:1053:1053)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) ) @@ -53711,10 +53967,106 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[1\]\~feeder) + (INSTANCE ula_\|video_\|LessThan2\~0) (DELAY (ABSOLUTE - (PORT datad (290:290:290) (337:337:337)) + (PORT dataa (159:159:159) (210:210:210)) + (PORT datab (147:147:147) (197:197:197)) + (PORT datac (144:144:144) (185:185:185)) + (PORT datad (133:133:133) (172:172:172)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (PORT datab (140:140:140) (188:188:188)) + (PORT datac (141:141:141) (182:182:182)) + (PORT datad (131:131:131) (168:168:168)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (310:310:310)) + (PORT datab (146:146:146) (196:196:196)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (188:188:188) (214:214:214)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (159:159:159) (212:212:212)) + (PORT datab (129:129:129) (157:157:157)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (201:201:201)) + (PORT datab (141:141:141) (189:189:189)) + (PORT datad (136:136:136) (176:176:176)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~0) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (215:215:215) (273:273:273)) + (PORT datad (361:361:361) (423:423:423)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~1) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (148:148:148)) + (PORT datab (109:109:109) (140:140:140)) + (PORT datad (179:179:179) (213:213:213)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53724,23 +54076,86 @@ (INSTANCE ula_\|border\[1\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (924:924:924)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (658:658:658) (708:708:708)) + (PORT clk (911:911:911) (915:915:915)) + (PORT asdata (279:279:279) (298:298:298)) + (PORT ena (1148:1148:1148) (1270:1270:1270)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (312:312:312)) + (PORT datab (252:252:252) (318:318:318)) + (PORT datac (232:232:232) (290:290:290)) + (PORT datad (220:220:220) (255:255:255)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (199:199:199)) + (PORT datab (149:149:149) (200:200:200)) + (PORT datad (128:128:128) (164:164:164)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (294:294:294)) + (PORT datab (249:249:249) (311:311:311)) + (PORT datac (288:288:288) (330:330:330)) + (PORT datad (348:348:348) (416:416:416)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (435:435:435)) + (PORT datab (258:258:258) (322:322:322)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (190:190:190) (222:222:222)) + (PORT datad (823:823:823) (939:939:939)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53750,10 +54165,10 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (648:648:648) (757:757:757)) - (PORT datab (800:800:800) (933:933:933)) - (PORT datac (640:640:640) (748:748:748)) - (PORT datad (470:470:470) (552:552:552)) + (PORT dataa (682:682:682) (811:811:811)) + (PORT datab (533:533:533) (638:638:638)) + (PORT datac (532:532:532) (636:636:636)) + (PORT datad (153:153:153) (202:202:202)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -53766,9 +54181,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1118:1118:1118) (1147:1147:1147)) + (PORT clk (1138:1138:1138) (1170:1170:1170)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (766:766:766) (830:830:830)) + (PORT ena (772:772:772) (840:840:840)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -53777,25 +54192,15 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (476:476:476) (556:556:556)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (474:474:474) (560:560:560)) - (PORT datab (632:632:632) (746:746:746)) - (PORT datac (511:511:511) (599:599:599)) - (PORT datad (628:628:628) (726:726:726)) + (PORT dataa (682:682:682) (810:810:810)) + (PORT datab (533:533:533) (638:638:638)) + (PORT datac (532:532:532) (637:637:637)) + (PORT datad (154:154:154) (203:203:203)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -53808,14 +54213,14 @@ (INSTANCE ula_\|video_\|attr\[1\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (920:920:920)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (620:620:620) (664:664:664)) + (PORT clk (917:917:917) (921:921:921)) + (PORT asdata (974:974:974) (1094:1094:1094)) + (PORT ena (745:745:745) (812:812:812)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -53824,7 +54229,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (356:356:356) (414:414:414)) + (PORT datad (859:859:859) (961:961:961)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53834,9 +54239,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1136:1136:1136) (1168:1168:1168)) + (PORT clk (1138:1138:1138) (1170:1170:1170)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (655:655:655) (712:712:712)) + (PORT ena (772:772:772) (840:840:840)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -53850,9 +54255,9 @@ (INSTANCE ula_\|video_\|attr\[4\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (903:903:903) (1013:1013:1013)) - (PORT ena (761:761:761) (837:837:837)) + (PORT clk (917:917:917) (921:921:921)) + (PORT asdata (538:538:538) (609:609:609)) + (PORT ena (745:745:745) (812:812:812)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -53861,226 +54266,12 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (337:337:337) (386:386:386)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Decoder0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (760:760:760)) - (PORT datab (800:800:800) (934:934:934)) - (PORT datac (638:638:638) (746:746:746)) - (PORT datad (472:472:472) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1115:1115:1115) (1144:1144:1144)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (1312:1312:1312) (1459:1459:1459)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (1167:1167:1167) (1314:1314:1314)) - (PORT ena (761:761:761) (837:837:837)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (356:356:356) (413:413:413)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1121:1121:1121) (1146:1146:1146)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (674:674:674) (748:748:748)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (675:675:675) (758:758:758)) - (PORT ena (761:761:761) (837:837:837)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (345:345:345) (397:397:397)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1110:1110:1110) (1139:1139:1139)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (1145:1145:1145) (1267:1267:1267)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (968:968:968) (1089:1089:1089)) - (PORT ena (761:761:761) (837:837:837)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (189:189:189) (220:220:220)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1109:1109:1109) (1139:1139:1139)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (1273:1273:1273) (1415:1415:1415)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (836:836:836) (954:954:954)) - (PORT ena (761:761:761) (837:837:837)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (287:287:287)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (214:214:214) (264:264:264)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (288:288:288)) - (PORT datab (201:201:201) (256:256:256)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (189:189:189) (220:220:220)) + (PORT datad (684:684:684) (780:780:780)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54090,9 +54281,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1113:1113:1113)) + (PORT clk (1138:1138:1138) (1170:1170:1170)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (958:958:958) (1056:1056:1056)) + (PORT ena (772:772:772) (840:840:840)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54106,9 +54297,9 @@ (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (795:795:795) (894:894:894)) - (PORT ena (761:761:761) (837:837:837)) + (PORT clk (918:918:918) (922:922:922)) + (PORT asdata (535:535:535) (606:606:606)) + (PORT ena (747:747:747) (817:817:817)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54122,9 +54313,9 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT datad (744:744:744) (836:836:836)) + (PORT dataa (326:326:326) (380:380:380)) + (IOPATH dataa combout (195:195:195) (203:203:203)) (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -54133,7 +54324,7 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) + (PORT clk (919:919:919) (923:923:923)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -54147,8 +54338,8 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (357:357:357) (432:432:432)) - (PORT datab (317:317:317) (385:385:385)) + (PORT dataa (319:319:319) (383:383:383)) + (PORT datab (130:130:130) (178:178:178)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datab combout (190:190:190) (181:181:181)) @@ -54162,14 +54353,14 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (500:500:500) (554:554:554)) - (PORT ena (923:923:923) (1000:1000:1000)) + (PORT clk (918:918:918) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (642:642:642) (697:697:697)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -54178,9 +54369,9 @@ (INSTANCE ula_\|video_\|frame\[2\]\~6) (DELAY (ABSOLUTE - (PORT datab (571:571:571) (656:656:656)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (131:131:131) (182:182:182)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -54192,14 +54383,14 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (1131:1131:1131) (1163:1163:1163)) - (PORT asdata (639:639:639) (706:706:706)) - (PORT ena (729:729:729) (783:783:783)) + (PORT clk (918:918:918) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (642:642:642) (697:697:697)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -54208,9 +54399,9 @@ (INSTANCE ula_\|video_\|frame\[3\]\~8) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (265:265:265)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (130:130:130) (178:178:178)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -54222,9 +54413,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) + (PORT clk (918:918:918) (923:923:923)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (733:733:733)) + (PORT ena (642:642:642) (697:697:697)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54238,8 +54429,8 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT datad (121:121:121) (160:160:160)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (142:142:142) (193:193:193)) + (IOPATH dataa combout (195:195:195) (203:203:203)) (IOPATH cin combout (187:187:187) (204:204:204)) ) ) @@ -54249,14 +54440,14 @@ (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (339:339:339) (366:366:366)) - (PORT ena (679:679:679) (733:733:733)) + (PORT clk (918:918:918) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (642:642:642) (697:697:697)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -54265,7 +54456,7 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (120:120:120) (159:159:159)) + (PORT datad (196:196:196) (239:239:239)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54273,22 +54464,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) + (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (191:191:191) (222:222:222)) + (PORT datad (646:646:646) (734:734:734)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Decoder0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (811:811:811)) + (PORT datab (534:534:534) (639:639:639)) + (PORT datac (531:531:531) (635:635:635)) + (PORT datad (152:152:152) (201:201:201)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[2\]) + (INSTANCE ula_\|video_\|bits_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1109:1109:1109) (1139:1139:1139)) + (PORT clk (1123:1123:1123) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (1270:1270:1270) (1399:1399:1399)) + (PORT ena (773:773:773) (844:844:844)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (335:335:335) (394:394:394)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (747:747:747) (817:817:817)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (858:858:858) (960:960:960)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (773:773:773) (844:844:844)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54299,12 +54558,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[2\]) + (INSTANCE ula_\|video_\|bits\[4\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (978:978:978) (1096:1096:1096)) - (PORT ena (761:761:761) (837:837:837)) + (PORT clk (918:918:918) (922:922:922)) + (PORT asdata (535:535:535) (601:601:601)) + (PORT ena (747:747:747) (817:817:817)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54313,12 +54572,188 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (522:522:522) (600:600:600)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (773:773:773) (844:844:844)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (356:356:356) (420:420:420)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (747:747:747) (817:817:817)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (688:688:688) (785:785:785)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (773:773:773) (844:844:844)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (922:922:922)) + (PORT asdata (648:648:648) (729:729:729)) + (PORT ena (747:747:747) (817:817:817)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (262:262:262)) + (PORT datab (158:158:158) (212:212:212)) + (PORT datad (338:338:338) (401:401:401)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (155:155:155) (209:209:209)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (485:485:485) (555:555:555)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (773:773:773) (844:844:844)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (350:350:350) (413:413:413)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (747:747:747) (817:817:817)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (190:190:190) (222:222:222)) + (PORT datad (800:800:800) (885:885:885)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54328,9 +54763,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1114:1114:1114) (1144:1144:1144)) + (PORT clk (1123:1123:1123) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (1280:1280:1280) (1424:1424:1424)) + (PORT ena (773:773:773) (844:844:844)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54344,9 +54779,9 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (643:643:643) (728:728:728)) - (PORT ena (761:761:761) (837:837:837)) + (PORT clk (918:918:918) (922:922:922)) + (PORT asdata (526:526:526) (585:585:585)) + (PORT ena (747:747:747) (817:817:817)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54360,7 +54795,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (190:190:190) (222:222:222)) + (PORT datad (821:821:821) (936:936:936)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54370,9 +54805,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1103:1103:1103) (1122:1122:1122)) + (PORT clk (1123:1123:1123) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (1464:1464:1464) (1641:1641:1641)) + (PORT ena (773:773:773) (844:844:844)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54386,7 +54821,7 @@ (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (452:452:452) (526:526:526)) + (PORT datad (347:347:347) (411:411:411)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54396,9 +54831,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (920:920:920)) + (PORT clk (918:918:918) (922:922:922)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (620:620:620) (664:664:664)) + (PORT ena (747:747:747) (817:817:817)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54412,8 +54847,8 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datac (339:339:339) (390:390:390)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datad (687:687:687) (771:771:771)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -54422,9 +54857,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (922:922:922) (926:926:926)) + (PORT clk (1123:1123:1123) (1148:1148:1148)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (812:812:812) (892:892:892)) + (PORT ena (773:773:773) (844:844:844)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54438,9 +54873,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (522:522:522) (588:588:588)) - (PORT ena (761:761:761) (837:837:837)) + (PORT clk (918:918:918) (922:922:922)) + (PORT asdata (762:762:762) (848:848:848)) + (PORT ena (747:747:747) (817:817:817)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54454,9 +54889,9 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (224:224:224) (288:288:288)) - (PORT datab (217:217:217) (276:276:276)) - (PORT datad (216:216:216) (267:267:267)) + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (155:155:155) (209:209:209)) + (PORT datad (335:335:335) (398:398:398)) (IOPATH dataa combout (166:166:166) (159:159:159)) (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -54469,11 +54904,11 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (287:287:287)) - (PORT datab (131:131:131) (179:179:179)) + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (157:157:157) (211:211:211)) (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (177:177:177)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54484,12 +54919,12 @@ (INSTANCE ula_\|video_\|cindex\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (499:499:499) (589:589:589)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (182:182:182) (193:193:193)) + (PORT dataa (210:210:210) (268:268:268)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (181:181:181) (184:184:184)) + (IOPATH datab combout (192:192:192) (188:188:188)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54500,196 +54935,26 @@ (INSTANCE ula_\|video_\|cindex\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (280:280:280)) - (PORT datad (108:108:108) (128:128:128)) + (PORT dataa (131:131:131) (183:183:183)) + (PORT datad (179:179:179) (206:206:206)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (144:144:144) (196:196:196)) - (PORT datab (143:143:143) (191:191:191)) - (PORT datac (127:127:127) (168:168:168)) - (PORT datad (128:128:128) (164:164:164)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (234:234:234) (295:295:295)) - (PORT datab (161:161:161) (211:211:211)) - (PORT datac (214:214:214) (265:265:265)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (233:233:233) (296:296:296)) - (PORT datab (149:149:149) (199:199:199)) - (PORT datac (132:132:132) (175:175:175)) - (PORT datad (212:212:212) (263:263:263)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (441:441:441)) - (PORT datab (221:221:221) (281:281:281)) - (PORT datac (356:356:356) (422:422:422)) - (PORT datad (308:308:308) (348:348:348)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~1) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (435:435:435)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (476:476:476) (551:551:551)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (161:161:161) (174:174:174)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (159:159:159) (211:211:211)) - (PORT datab (147:147:147) (198:198:198)) - (PORT datac (145:145:145) (188:188:188)) - (PORT datad (145:145:145) (184:184:184)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (301:301:301)) - (PORT datab (157:157:157) (206:206:206)) - (PORT datac (108:108:108) (132:132:132)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (120:120:120) (151:151:151)) - (PORT datac (222:222:222) (275:275:275)) - (PORT datad (134:134:134) (174:174:174)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT datab (140:140:140) (188:188:188)) - (PORT datad (131:131:131) (170:170:170)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~0) - (DELAY - (ABSOLUTE - (PORT dataa (146:146:146) (199:199:199)) - (PORT datab (142:142:142) (190:190:190)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~1) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datad (337:337:337) (392:392:392)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1266:1266:1266) (1456:1456:1456)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (812:812:812) (925:925:925)) - (PORT datad (296:296:296) (342:342:342)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (214:214:214) (266:266:266)) + (PORT datab (820:820:820) (958:958:958)) + (PORT datac (128:128:128) (155:155:155)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54699,7 +54964,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (336:336:336) (384:384:384)) + (PORT datad (648:648:648) (736:736:736)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54709,9 +54974,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1100:1100:1100) (1119:1119:1119)) + (PORT clk (1138:1138:1138) (1170:1170:1170)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (1346:1346:1346) (1507:1507:1507)) + (PORT ena (772:772:772) (840:840:840)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54725,9 +54990,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT asdata (1153:1153:1153) (1296:1296:1296)) - (PORT ena (769:769:769) (847:847:847)) + (PORT clk (914:914:914) (918:918:918)) + (PORT asdata (655:655:655) (731:731:731)) + (PORT ena (858:858:858) (937:937:937)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54741,11 +55006,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (334:334:334) (386:386:386)) - (PORT datab (321:321:321) (373:373:373)) - (PORT datad (337:337:337) (392:392:392)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (114:114:114) (149:149:149)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datad (179:179:179) (214:214:214)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54756,11 +55021,11 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (827:827:827) (949:949:949)) - (PORT datab (107:107:107) (138:138:138)) - (PORT datad (166:166:166) (195:195:195)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (147:147:147) (185:185:185)) + (PORT datac (207:207:207) (250:250:250)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54770,9 +55035,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (924:924:924)) - (PORT asdata (282:282:282) (303:303:303)) - (PORT ena (658:658:658) (708:708:708)) + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (495:495:495) (538:538:538)) + (PORT ena (418:418:418) (434:434:434)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54786,7 +55051,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (187:187:187) (219:219:219)) + (PORT datad (486:486:486) (555:555:555)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54796,9 +55061,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1094:1094:1094) (1113:1113:1113)) + (PORT clk (1138:1138:1138) (1170:1170:1170)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (1149:1149:1149) (1279:1279:1279)) + (PORT ena (772:772:772) (840:840:840)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54812,9 +55077,9 @@ (INSTANCE ula_\|video_\|attr\[2\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (965:965:965) (1076:1076:1076)) - (PORT ena (761:761:761) (837:837:837)) + (PORT clk (918:918:918) (922:922:922)) + (PORT asdata (641:641:641) (711:711:711)) + (PORT ena (747:747:747) (817:817:817)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54828,7 +55093,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (346:346:346) (398:398:398)) + (PORT datad (521:521:521) (599:599:599)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54838,9 +55103,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1094:1094:1094) (1114:1114:1114)) + (PORT clk (1138:1138:1138) (1170:1170:1170)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (1025:1025:1025) (1151:1151:1151)) + (PORT ena (772:772:772) (840:840:840)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54854,9 +55119,9 @@ (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (867:867:867) (981:981:981)) - (PORT ena (761:761:761) (837:837:837)) + (PORT clk (918:918:918) (922:922:922)) + (PORT asdata (528:528:528) (588:588:588)) + (PORT ena (747:747:747) (817:817:817)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54870,9 +55135,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (181:181:181)) - (PORT datad (110:110:110) (130:130:130)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT datab (130:130:130) (177:177:177)) + (PORT datad (106:106:106) (126:126:126)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54883,13 +55148,13 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1188:1188:1188) (1361:1361:1361)) - (PORT datab (308:308:308) (364:364:364)) - (PORT datac (812:812:812) (924:924:924)) - (PORT datad (99:99:99) (120:120:120)) + (PORT dataa (1315:1315:1315) (1534:1534:1534)) + (PORT datab (221:221:221) (262:262:262)) + (PORT datac (203:203:203) (246:246:246)) + (PORT datad (294:294:294) (329:329:329)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54899,33 +55164,49 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (827:827:827) (949:949:949)) - (PORT datab (110:110:110) (142:142:142)) - (PORT datad (166:166:166) (195:195:195)) + (PORT dataa (340:340:340) (400:400:400)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datad (195:195:195) (224:224:224)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (108:108:108) (128:128:128)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (924:924:924)) + (PORT clk (911:911:911) (915:915:915)) + (PORT asdata (823:823:823) (908:908:908)) + (PORT ena (1148:1148:1148) (1270:1270:1270)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (799:799:799) (884:884:884)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1138:1138:1138) (1170:1170:1170)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (658:658:658) (708:708:708)) + (PORT ena (772:772:772) (840:840:840)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54936,22 +55217,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (INSTANCE ula_\|video_\|attr\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (190:190:190) (222:222:222)) + (PORT datad (455:455:455) (523:523:523)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (INSTANCE ula_\|video_\|attr\[0\]) (DELAY (ABSOLUTE - (PORT clk (1099:1099:1099) (1119:1119:1119)) + (PORT clk (917:917:917) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (811:811:811) (901:901:901)) + (PORT ena (745:745:745) (812:812:812)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (687:687:687) (770:770:770)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1138:1138:1138) (1170:1170:1170)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (772:772:772) (840:840:840)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54960,46 +55267,14 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (920:920:920)) - (PORT asdata (657:657:657) (736:736:736)) - (PORT ena (620:620:620) (664:664:664)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1119:1119:1119)) - (PORT asdata (671:671:671) (739:739:739)) - (PORT ena (957:957:957) (1064:1064:1064)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (920:920:920)) - (PORT asdata (468:468:468) (524:524:524)) - (PORT ena (620:620:620) (664:664:664)) + (PORT clk (918:918:918) (922:922:922)) + (PORT asdata (520:520:520) (583:583:583)) + (PORT ena (747:747:747) (817:817:817)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55013,9 +55288,9 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT datab (200:200:200) (258:258:258)) + (PORT datad (108:108:108) (127:127:127)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55026,13 +55301,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1273:1273:1273) (1457:1457:1457)) - (PORT datab (115:115:115) (142:142:142)) - (PORT datac (288:288:288) (323:323:323)) - (PORT datad (281:281:281) (315:315:315)) + (PORT dataa (215:215:215) (267:267:267)) + (PORT datab (933:933:933) (1067:1067:1067)) + (PORT datac (128:128:128) (155:155:155)) + (PORT datad (170:170:170) (200:200:200)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55042,9 +55317,9 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (455:455:455) (520:520:520)) - (PORT datac (305:305:305) (345:345:345)) - (PORT datad (310:310:310) (356:356:356)) + (PORT dataa (148:148:148) (185:185:185)) + (PORT datac (207:207:207) (250:250:250)) + (PORT datad (175:175:175) (206:206:206)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -55056,11 +55331,11 @@ (INSTANCE ula_\|video_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (848:848:848) (997:997:997)) - (PORT datac (641:641:641) (757:757:757)) - (PORT datad (634:634:634) (727:727:727)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (364:364:364) (435:435:435)) + (PORT datab (154:154:154) (201:201:201)) + (PORT datad (346:346:346) (414:414:414)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55070,7 +55345,7 @@ (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (922:922:922) (926:926:926)) + (PORT clk (917:917:917) (921:921:921)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -55084,10 +55359,10 @@ (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (174:174:174) (216:216:216)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datad (108:108:108) (128:128:128)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (540:540:540) (616:616:616)) + (PORT datab (120:120:120) (151:151:151)) + (PORT datad (300:300:300) (346:346:346)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -55100,7 +55375,7 @@ (DELAY (ABSOLUTE (PORT clk (893:893:893) (915:915:915)) - (PORT d (937:937:937) (1015:1015:1015)) + (PORT d (917:917:917) (975:975:975)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -55114,7 +55389,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (922:922:922) (926:926:926)) + (PORT clk (919:919:919) (923:923:923)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -55128,11 +55403,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (118:118:118) (149:149:149)) - (PORT datab (391:391:391) (470:470:470)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (325:325:325) (380:380:380)) + (PORT datab (627:627:627) (727:727:727)) + (PORT datad (383:383:383) (452:452:452)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55144,7 +55419,7 @@ (DELAY (ABSOLUTE (PORT clk (892:892:892) (914:914:914)) - (PORT d (870:870:870) (948:948:948)) + (PORT d (979:979:979) (1050:1050:1050)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -55158,7 +55433,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (141:141:141) (183:183:183)) + (PORT datad (323:323:323) (383:383:383)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55168,10 +55443,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) + (PORT clk (918:918:918) (925:925:925)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (903:903:903)) - (PORT ena (639:639:639) (693:693:693)) + (PORT clrn (924:924:924) (906:906:906)) + (PORT ena (783:783:783) (862:862:862)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55186,10 +55461,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (296:296:296) (336:336:336)) - (PORT clrn (918:918:918) (903:903:903)) - (PORT ena (639:639:639) (693:693:693)) + (PORT clk (918:918:918) (925:925:925)) + (PORT asdata (296:296:296) (335:335:335)) + (PORT clrn (924:924:924) (906:906:906)) + (PORT ena (783:783:783) (862:862:862)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55204,7 +55479,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (135:135:135) (176:176:176)) + (PORT datad (326:326:326) (386:386:386)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55215,9 +55490,9 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT dataa (382:382:382) (477:477:477)) - (PORT datad (139:139:139) (181:181:181)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datac (730:730:730) (833:833:833)) + (PORT datad (326:326:326) (387:387:387)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55227,12 +55502,10 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT dataa (441:441:441) (517:517:517)) - (PORT datab (492:492:492) (579:579:579)) - (PORT datac (476:476:476) (549:549:549)) - (PORT datad (386:386:386) (463:463:463)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (193:193:193)) + (PORT datab (972:972:972) (1130:1130:1130)) + (PORT datac (1872:1872:1872) (2097:2097:2097)) + (PORT datad (705:705:705) (818:818:818)) + (IOPATH datab combout (196:196:196) (205:205:205)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55243,9 +55516,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) + (PORT clk (902:902:902) (907:907:907)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (844:844:844)) + (PORT ena (1416:1416:1416) (1569:1569:1569)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) diff --git a/simulation/modelsim/spectrum_modelsim.xrf b/simulation/modelsim/spectrum_modelsim.xrf index d29f4a4..a3e8bc9 100644 --- a/simulation/modelsim/spectrum_modelsim.xrf +++ b/simulation/modelsim/spectrum_modelsim.xrf @@ -60,6 +60,8 @@ source_file = 1, /home/benny/work/fpga/spectrum/rom_scr.v source_file = 1, /home/benny/work/fpga/spectrum/pll_video.qip source_file = 1, /home/benny/work/fpga/spectrum/pll_video.v source_file = 1, /home/benny/work/fpga/spectrum/spectrum.sdc +source_file = 1, /home/benny/work/fpga/spectrum/ram_video.qip +source_file = 1, /home/benny/work/fpga/spectrum/ram_video.v source_file = 1, /home/benny/work/fpga/spectrum/db/spectrum.cbx.xml source_file = 1, /home/benny/work/fpga/spectrum/cpu/toplevel/globals.vh source_file = 1, /home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh @@ -172,843 +174,797 @@ instance = comp, \SW[2]~input , SW[2]~input, spectrum, 1 instance = comp, \ula_|clocks_|clk_cpu~0 , ula_|clocks_|clk_cpu~0, spectrum, 1 instance = comp, \ula_|clocks_|clk_cpu , ula_|clocks_|clk_cpu, spectrum, 1 instance = comp, \ula_|clocks_|clk_cpu~clkctrl , ula_|clocks_|clk_cpu~clkctrl, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M1_ff~0 , z80_|sequencer_|DFFE_M1_ff~0, spectrum, 1 instance = comp, \z80_|sequencer_|ena_M , z80_|sequencer_|ena_M, spectrum, 1 +instance = comp, \KEY[1]~input , KEY[1]~input, spectrum, 1 +instance = comp, \z80_|interrupts_|nmi_armed~feeder , z80_|interrupts_|nmi_armed~feeder, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_9 , z80_|interrupts_|SYNTHESIZED_WIRE_9, spectrum, 1 +instance = comp, \z80_|interrupts_|nmi_armed , z80_|interrupts_|nmi_armed, spectrum, 1 +instance = comp, \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder , z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder, spectrum, 1 +instance = comp, \z80_|execute_|ctl_eval_cond~0 , z80_|execute_|ctl_eval_cond~0, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~4 , z80_|execute_|ixy_d~4, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M3_ff~0 , z80_|sequencer_|DFFE_M3_ff~0, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M3_ff , z80_|sequencer_|DFFE_M3_ff, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~1 , z80_|execute_|fIOWrite~1, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M4_ff~0 , z80_|sequencer_|DFFE_M4_ff~0, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M4_ff , z80_|sequencer_|DFFE_M4_ff, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal32~0 , z80_|pla_decode_|Equal32~0, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_11 , z80_|resets_|SYNTHESIZED_WIRE_11, spectrum, 1 +instance = comp, \z80_|decode_state_|table_xx~0 , z80_|decode_state_|table_xx~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~7 , z80_|pla_decode_|Equal1~7, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal2~0 , z80_|pla_decode_|Equal2~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal36~0 , z80_|pla_decode_|Equal36~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_tbl_cb_set , z80_|execute_|ctl_state_tbl_cb_set, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_tbl_we~8 , z80_|execute_|ctl_state_tbl_we~8, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instCB , z80_|decode_state_|DFFE_instCB, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal52~0 , z80_|pla_decode_|Equal52~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal2~1 , z80_|pla_decode_|Equal2~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_tbl_ed_set , z80_|execute_|ctl_state_tbl_ed_set, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instED , z80_|decode_state_|DFFE_instED, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal13~0 , z80_|pla_decode_|Equal13~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~0 , z80_|pla_decode_|Equal33~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_im_we , z80_|execute_|ctl_im_we, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal49~0 , z80_|pla_decode_|Equal49~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~1 , z80_|pla_decode_|Equal33~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal6~0 , z80_|pla_decode_|Equal6~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~14 , z80_|execute_|ctl_mRead~14, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal12~0 , z80_|pla_decode_|Equal12~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~8 , z80_|execute_|ctl_sw_1d~8, spectrum, 1 +instance = comp, \z80_|nM1_int~2 , z80_|nM1_int~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~5 , z80_|execute_|ctl_sw_1d~5, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal3~0 , z80_|pla_decode_|Equal3~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~4 , z80_|execute_|ctl_mRead~4, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~7 , z80_|execute_|ixy_d~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~4 , z80_|execute_|ctl_state_alu~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~4 , z80_|execute_|ctl_sw_1d~4, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal40~1 , z80_|pla_decode_|Equal40~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal39~0 , z80_|pla_decode_|Equal39~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~1 , z80_|execute_|ctl_bus_db_oe~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal13~1 , z80_|pla_decode_|Equal13~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal13~2 , z80_|pla_decode_|Equal13~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal3~2 , z80_|pla_decode_|Equal3~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_iy_set~2 , z80_|execute_|ctl_state_iy_set~2, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~8 , z80_|execute_|ixy_d~8, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~6 , z80_|execute_|ixy_d~6, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~9 , z80_|execute_|ixy_d~9, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~12 , z80_|execute_|ixy_d~12, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~10 , z80_|execute_|ixy_d~10, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal44~0 , z80_|pla_decode_|Equal44~0, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~16 , z80_|execute_|ixy_d~16, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~13 , z80_|execute_|ixy_d~13, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal50~0 , z80_|pla_decode_|Equal50~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~2 , z80_|pla_decode_|Equal33~2, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~17 , z80_|execute_|ixy_d~17, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~5 , z80_|execute_|ixy_d~5, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~14 , z80_|execute_|ixy_d~14, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~11 , z80_|execute_|ixy_d~11, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~15 , z80_|execute_|ixy_d~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_ixiy_we~2 , z80_|execute_|ctl_state_ixiy_we~2, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instIY1 , z80_|decode_state_|DFFE_instIY1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~5 , z80_|execute_|ctl_ir_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~14 , z80_|execute_|ctl_ir_we~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~2 , z80_|execute_|ctl_mWrite~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~16 , z80_|execute_|ctl_mWrite~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~18 , z80_|execute_|ctl_flags_alu~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~26 , z80_|execute_|ctl_mRead~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~27 , z80_|execute_|ctl_mRead~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~7 , z80_|execute_|ctl_bus_db_oe~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~5 , z80_|execute_|ctl_sw_2d~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~18 , z80_|execute_|ctl_mRead~18, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal55~0 , z80_|pla_decode_|Equal55~0, spectrum, 1 +instance = comp, \z80_|execute_|comb~1 , z80_|execute_|comb~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~15 , z80_|execute_|ctl_mRead~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~17 , z80_|execute_|ctl_mRead~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~5 , z80_|execute_|ctl_reg_in_hi~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~9 , z80_|execute_|ctl_mRead~9, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal9~0 , z80_|pla_decode_|Equal9~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~10 , z80_|execute_|ctl_mRead~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~8 , z80_|execute_|ctl_mRead~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~20 , z80_|execute_|ctl_mRead~20, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal12~1 , z80_|pla_decode_|Equal12~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal9~1 , z80_|pla_decode_|Equal9~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal25~0 , z80_|pla_decode_|Equal25~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~21 , z80_|execute_|ctl_mRead~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~6 , z80_|execute_|ctl_state_alu~6, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal19~0 , z80_|pla_decode_|Equal19~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~4 , z80_|pla_decode_|Equal1~4, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal29~0 , z80_|pla_decode_|Equal29~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal24~1 , z80_|pla_decode_|Equal24~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal34~0 , z80_|pla_decode_|Equal34~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal37~0 , z80_|pla_decode_|Equal37~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal35~0 , z80_|pla_decode_|Equal35~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal38~2 , z80_|pla_decode_|Equal38~2, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~2 , z80_|reg_control_|reg_sys_we_lo~2, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~3 , z80_|reg_control_|reg_sys_we_lo~3, spectrum, 1 +instance = comp, \z80_|execute_|comb~0 , z80_|execute_|comb~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal47~0 , z80_|pla_decode_|Equal47~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~4 , z80_|reg_control_|reg_sys_we_lo~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~22 , z80_|execute_|ctl_mRead~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~24 , z80_|execute_|ctl_mRead~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~6 , z80_|execute_|ctl_reg_in_hi~6, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal6~1 , z80_|pla_decode_|Equal6~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~16 , z80_|execute_|ctl_mRead~16, spectrum, 1 +instance = comp, \z80_|sequencer_|M5~0 , z80_|sequencer_|M5~0, spectrum, 1 +instance = comp, \z80_|sequencer_|M5 , z80_|sequencer_|M5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~2 , z80_|execute_|ctl_reg_in_hi~2, spectrum, 1 +instance = comp, \z80_|execute_|setM1~29 , z80_|execute_|setM1~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~25 , z80_|execute_|ctl_mRead~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~6 , z80_|execute_|ctl_reg_gp_sel[0]~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~7 , z80_|execute_|ctl_ir_we~7, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal52~1 , z80_|pla_decode_|Equal52~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~14 , z80_|execute_|ctl_state_alu~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~8 , z80_|execute_|ctl_state_alu~8, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal24~0 , z80_|pla_decode_|Equal24~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~0 , z80_|reg_control_|reg_sel_pc~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~1 , z80_|reg_control_|reg_sel_pc~1, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~2 , z80_|reg_control_|reg_sel_pc~2, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~17 , z80_|execute_|fMRead~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~6 , z80_|execute_|ctl_mRead~6, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal11~0 , z80_|pla_decode_|Equal11~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal10~0 , z80_|pla_decode_|Equal10~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~9 , z80_|execute_|ctl_alu_op2_sel_bus~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~4 , z80_|execute_|ctl_sw_2d~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~15 , z80_|execute_|ctl_ir_we~15, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~16 , z80_|execute_|fMRead~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~9 , z80_|execute_|ctl_ir_we~9, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal46~0 , z80_|pla_decode_|Equal46~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~10 , z80_|execute_|ctl_ir_we~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~17 , z80_|execute_|ctl_flags_alu~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~6 , z80_|execute_|ctl_flags_alu~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~6 , z80_|execute_|ctl_ir_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~8 , z80_|execute_|ctl_ir_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~16 , z80_|execute_|ctl_flags_alu~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~3 , z80_|execute_|ctl_reg_in_hi~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~8 , z80_|execute_|ctl_mWrite~8, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~18 , z80_|execute_|fMRead~18, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~19 , z80_|execute_|fMRead~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~16 , z80_|execute_|ctl_alu_shift_oe~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~36 , z80_|execute_|ctl_mRead~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~9 , z80_|execute_|ctl_alu_op_low~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~44 , z80_|execute_|ctl_alu_shift_oe~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~11 , z80_|execute_|ctl_mRead~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~6 , z80_|execute_|ctl_sw_2d~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~7 , z80_|execute_|ctl_sw_2d~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~7 , z80_|execute_|ctl_mWrite~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~11 , z80_|execute_|ctl_ir_we~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~12 , z80_|execute_|ctl_ir_we~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~0 , z80_|execute_|ctl_flags_sz_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~8 , z80_|execute_|ctl_sw_2d~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~9 , z80_|execute_|ctl_sw_2d~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~6 , z80_|execute_|ctl_sw_1d~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~7 , z80_|execute_|ctl_sw_1d~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~8 , z80_|execute_|ctl_alu_op_low~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~39 , z80_|execute_|ctl_reg_gp_hilo[1]~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 , z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~4 , z80_|execute_|ctl_reg_out_hi~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~15 , z80_|execute_|ctl_alu_shift_oe~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~38 , z80_|execute_|ctl_alu_shift_oe~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_zero , z80_|execute_|ctl_alu_op2_sel_zero, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~4 , z80_|alu_|db_low[2]~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~14 , z80_|execute_|ctl_alu_shift_oe~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~11 , z80_|execute_|ctl_reg_sys_hilo[0]~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~1 , z80_|execute_|ctl_sw_4u~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~5 , z80_|execute_|ctl_alu_sel_op2_neg~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~30 , z80_|execute_|ctl_alu_shift_oe~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~29 , z80_|execute_|ctl_alu_shift_oe~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~31 , z80_|execute_|ctl_alu_shift_oe~31, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal69~0 , z80_|pla_decode_|Equal69~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~5 , z80_|pla_decode_|Equal1~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~14 , z80_|execute_|ctl_alu_op_low~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~12 , z80_|execute_|ctl_alu_op_low~12, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal56~0 , z80_|pla_decode_|Equal56~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~11 , z80_|execute_|ctl_alu_op_low~11, spectrum, 1 +instance = comp, \z80_|execute_|nextM~2 , z80_|execute_|nextM~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~16 , z80_|execute_|ctl_alu_op1_sel_bus~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~4 , z80_|execute_|ctl_alu_op1_sel_bus~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~5 , z80_|execute_|ctl_alu_op1_sel_bus~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~3 , z80_|execute_|ctl_alu_oe~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~15 , z80_|execute_|ctl_alu_op_low~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~8 , z80_|execute_|ctl_alu_op1_sel_bus~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~9 , z80_|execute_|ctl_alu_op1_sel_bus~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~3 , z80_|execute_|ctl_alu_core_R~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~4 , z80_|execute_|ctl_alu_core_R~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~10 , z80_|execute_|ctl_alu_op1_sel_bus~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~11 , z80_|execute_|ctl_alu_op1_sel_bus~11, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal48~0 , z80_|pla_decode_|Equal48~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf2_we , z80_|execute_|ctl_flags_hf2_we, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~41 , z80_|execute_|ctl_alu_shift_oe~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~18 , z80_|execute_|ctl_flags_xy_we~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~17 , z80_|execute_|ctl_alu_shift_oe~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~19 , z80_|execute_|ctl_alu_shift_oe~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~10 , z80_|execute_|ctl_iorw~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~18 , z80_|execute_|ctl_alu_shift_oe~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~20 , z80_|execute_|ctl_alu_shift_oe~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~13 , z80_|execute_|ctl_alu_bs_oe~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~9 , z80_|execute_|ctl_alu_bs_oe~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~3 , z80_|execute_|ctl_bus_db_oe~3, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal20~0 , z80_|pla_decode_|Equal20~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal68~2 , z80_|pla_decode_|Equal68~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~14 , z80_|execute_|ctl_flags_bus~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~13 , z80_|execute_|ctl_alu_op_low~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~15 , z80_|execute_|ctl_flags_bus~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~11 , z80_|execute_|ctl_flags_bus~11, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~11 , z80_|alu_flags_|DFFE_inst_latch_nf~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~10 , z80_|execute_|ctl_flags_bus~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~8 , z80_|execute_|ctl_flags_bus~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~9 , z80_|execute_|ctl_flags_bus~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~12 , z80_|execute_|ctl_flags_bus~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~11 , z80_|execute_|ctl_flags_xy_we~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~12 , z80_|execute_|ctl_flags_xy_we~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~6 , z80_|execute_|ctl_alu_op1_sel_bus~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~7 , z80_|execute_|ctl_alu_op1_sel_bus~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~4 , z80_|execute_|ctl_ir_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~8 , z80_|execute_|ctl_alu_bs_oe~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~0 , z80_|execute_|ctl_bus_db_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~12 , z80_|execute_|ctl_alu_op1_sel_bus~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~13 , z80_|execute_|ctl_alu_op1_sel_bus~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~14 , z80_|execute_|ctl_alu_op1_sel_bus~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~15 , z80_|execute_|ctl_alu_op1_sel_bus~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_66_oe~2 , z80_|execute_|ctl_66_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla11M1T1_11 , z80_|execute_|ctl_pf_sel_pla11M1T1_11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~5 , z80_|execute_|ctl_alu_op1_sel_zero~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~4 , z80_|execute_|ctl_alu_op1_sel_zero~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero , z80_|execute_|ctl_alu_op1_sel_zero, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[2] , z80_|alu_|b2v_op1_latch_mux_high|Q[2], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|ena~0 , z80_|alu_|b2v_op1_latch_mux_high|ena~0, spectrum, 1 +instance = comp, \z80_|alu_|op1_high[2] , z80_|alu_|op1_high[2], spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_lq , z80_|execute_|ctl_alu_op2_sel_lq, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~10 , z80_|execute_|ctl_alu_op_low~10, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~11 , z80_|execute_|fMWrite~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~21 , z80_|execute_|ctl_alu_op_low~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~22 , z80_|execute_|ctl_alu_op_low~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~16 , z80_|execute_|ctl_alu_op_low~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~17 , z80_|execute_|ctl_alu_op_low~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel~36 , z80_|execute_|ctl_reg_gp_sel~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~4 , z80_|execute_|ctl_alu_op2_sel_bus~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~5 , z80_|execute_|ctl_state_alu~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~18 , z80_|execute_|ctl_alu_op_low~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~19 , z80_|execute_|ctl_alu_op_low~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~33 , z80_|execute_|ctl_alu_op_low~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~20 , z80_|execute_|ctl_alu_op_low~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~23 , z80_|execute_|ctl_alu_op_low~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~24 , z80_|execute_|ctl_alu_op_low~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~25 , z80_|execute_|ctl_alu_op_low~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~34 , z80_|execute_|ctl_alu_op_low~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low , z80_|execute_|ctl_alu_op_low, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~40 , z80_|execute_|ctl_alu_shift_oe~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~37 , z80_|execute_|ctl_alu_shift_oe~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~39 , z80_|execute_|ctl_alu_shift_oe~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~46 , z80_|execute_|ctl_alu_shift_oe~46, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~42 , z80_|execute_|ctl_alu_shift_oe~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~21 , z80_|execute_|ctl_alu_shift_oe~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~45 , z80_|execute_|ctl_alu_shift_oe~45, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~22 , z80_|execute_|ctl_alu_shift_oe~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~23 , z80_|execute_|ctl_alu_shift_oe~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~24 , z80_|execute_|ctl_alu_shift_oe~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~25 , z80_|execute_|ctl_alu_shift_oe~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~14 , z80_|execute_|ctl_alu_bs_oe~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~26 , z80_|execute_|ctl_alu_shift_oe~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~27 , z80_|execute_|ctl_alu_shift_oe~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~28 , z80_|execute_|ctl_alu_shift_oe~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~10 , z80_|execute_|ctl_alu_bs_oe~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~11 , z80_|execute_|ctl_alu_bs_oe~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~32 , z80_|execute_|ctl_alu_shift_oe~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~33 , z80_|execute_|ctl_alu_shift_oe~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~0 , z80_|execute_|ctl_reg_use_sp~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~1 , z80_|execute_|ctl_reg_use_sp~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~12 , z80_|execute_|ctl_alu_bs_oe~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~47 , z80_|execute_|ctl_alu_shift_oe~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~34 , z80_|execute_|ctl_alu_shift_oe~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~35 , z80_|execute_|ctl_alu_shift_oe~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~36 , z80_|execute_|ctl_alu_shift_oe~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~43 , z80_|execute_|ctl_alu_shift_oe~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_lo~9 , z80_|execute_|ctl_reg_in_lo~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_oe~0 , z80_|execute_|ctl_alu_op1_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 , z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_oe~1 , z80_|execute_|ctl_alu_op1_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~8 , z80_|execute_|ctl_flags_xy_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~9 , z80_|execute_|ctl_flags_xy_we~9, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal8~0 , z80_|pla_decode_|Equal8~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~9 , z80_|execute_|ctl_flags_alu~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~4 , z80_|execute_|ctl_alu_sel_op2_neg~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~3 , z80_|execute_|ctl_flags_sz_we~3, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal11~1 , z80_|pla_decode_|Equal11~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 , z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~10 , z80_|execute_|ctl_flags_alu~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~11 , z80_|execute_|ctl_flags_alu~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla82M1T1_16 , z80_|execute_|ctl_pf_sel_pla82M1T1_16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~13 , z80_|execute_|ctl_flags_use_cf2~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~7 , z80_|execute_|ctl_flags_cf_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel[0]~2 , z80_|execute_|ctl_pf_sel[0]~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~2 , z80_|execute_|ctl_alu_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~25 , z80_|execute_|ctl_bus_inc_oe~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_we~5 , z80_|execute_|ctl_flags_hf_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~10 , z80_|execute_|ctl_flags_pf_we~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~48 , z80_|execute_|ctl_reg_gp_hilo[1]~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~2 , z80_|execute_|ctl_flags_pf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~3 , z80_|execute_|ctl_flags_pf_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~17 , z80_|execute_|ctl_flags_xy_we~17, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~5 , z80_|reg_control_|reg_sys_we_lo~5, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~6 , z80_|reg_control_|reg_sys_we_lo~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~10 , z80_|execute_|ctl_flags_xy_we~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~7 , z80_|execute_|ctl_state_alu~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~1 , z80_|execute_|ctl_flags_sz_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~2 , z80_|execute_|ctl_flags_cf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~6 , z80_|execute_|ctl_alu_core_S~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~7 , z80_|execute_|ctl_alu_core_S~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~4 , z80_|execute_|ctl_alu_core_S~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~5 , z80_|execute_|ctl_alu_core_S~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 , z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_res_oe~0 , z80_|execute_|ctl_alu_res_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~15 , z80_|execute_|ctl_alu_oe~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_res_oe~1 , z80_|execute_|ctl_alu_res_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_res_oe~2 , z80_|execute_|ctl_alu_res_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_oe~0 , z80_|execute_|ctl_alu_op2_oe~0, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~2 , z80_|alu_|db_high[3]~2, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~3 , z80_|alu_|db_high[3]~3, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~24 , z80_|alu_|db_low[2]~24, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~7 , z80_|reg_control_|reg_sys_we_lo~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 , z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~19 , z80_|execute_|ctl_reg_gp_hilo[1]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~8 , z80_|execute_|ctl_reg_in_hi~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~8 , z80_|execute_|ctl_alu_oe~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~4 , z80_|execute_|ctl_alu_oe~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~9 , z80_|execute_|ctl_mWrite~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~10 , z80_|execute_|ctl_alu_core_S~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~43 , z80_|execute_|ctl_bus_inc_oe~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~26 , z80_|execute_|ctl_bus_inc_oe~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~5 , z80_|execute_|ctl_bus_db_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~9 , z80_|execute_|ctl_alu_oe~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~11 , z80_|execute_|ctl_alu_oe~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~5 , z80_|execute_|ctl_alu_oe~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~11 , z80_|execute_|ctl_alu_core_S~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~6 , z80_|execute_|ctl_alu_oe~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~7 , z80_|execute_|ctl_alu_oe~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~12 , z80_|execute_|ctl_alu_oe~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~13 , z80_|execute_|ctl_alu_oe~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~14 , z80_|execute_|ctl_alu_oe~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~24 , z80_|execute_|ctl_reg_gp_sel[0]~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~27 , z80_|execute_|ctl_reg_gp_sel[0]~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~40 , z80_|execute_|ctl_reg_gp_hilo[1]~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~53 , z80_|execute_|ctl_reg_gp_hilo[1]~53, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~8 , z80_|execute_|ctl_reg_out_hi~8, spectrum, 1 +instance = comp, \z80_|execute_|setM1~54 , z80_|execute_|setM1~54, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~1 , z80_|execute_|ctl_sw_2u~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~4 , z80_|execute_|ctl_sw_2u~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~5 , z80_|execute_|ctl_sw_2u~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~6 , z80_|execute_|ctl_sw_2u~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~35 , z80_|execute_|ctl_inc_cy~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~35 , z80_|execute_|ctl_reg_sys_hilo[1]~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~6 , z80_|execute_|ctl_mWrite~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~2 , z80_|execute_|ctl_sw_2u~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~0 , z80_|execute_|ctl_sw_2u~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~3 , z80_|execute_|ctl_sw_2u~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~52 , z80_|execute_|ctl_reg_gp_hilo[1]~52, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 , z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~2 , z80_|execute_|ctl_reg_out_lo~2, spectrum, 1 +instance = comp, \z80_|execute_|rsel3 , z80_|execute_|rsel3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~5 , z80_|execute_|ctl_reg_out_hi~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~6 , z80_|execute_|ctl_reg_out_hi~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~7 , z80_|execute_|ctl_reg_out_hi~7, spectrum, 1 +instance = comp, \z80_|execute_|rsel0 , z80_|execute_|rsel0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~33 , z80_|execute_|ctl_reg_gp_hilo[0]~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~6 , z80_|execute_|ctl_reg_out_lo~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~7 , z80_|execute_|ctl_reg_out_lo~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~11 , z80_|execute_|ctl_iorw~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~10 , z80_|execute_|ctl_sw_2d~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~14 , z80_|execute_|ctl_sw_2d~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~11 , z80_|execute_|ctl_sw_2d~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~12 , z80_|execute_|ctl_sw_2d~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~13 , z80_|execute_|ctl_sw_2d~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_66_oe , z80_|execute_|ctl_66_oe, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~34 , z80_|execute_|ctl_inc_cy~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_apin_mux~0 , z80_|execute_|ctl_apin_mux~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~5 , z80_|execute_|ctl_sw_4u~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~75 , z80_|execute_|ctl_inc_cy~75, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~76 , z80_|execute_|ctl_inc_cy~76, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal4~0 , z80_|pla_decode_|Equal4~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~48 , z80_|execute_|ctl_bus_inc_oe~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~46 , z80_|execute_|ctl_bus_inc_oe~46, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~53 , z80_|execute_|ctl_inc_cy~53, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~92 , z80_|execute_|ctl_inc_cy~92, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal19~1 , z80_|pla_decode_|Equal19~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~0 , z80_|execute_|ctl_sw_4u~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~38 , z80_|execute_|ctl_inc_cy~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~93 , z80_|execute_|ctl_inc_cy~93, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~39 , z80_|execute_|ctl_inc_cy~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~24 , z80_|execute_|ctl_bus_inc_oe~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~1 , z80_|execute_|ctl_reg_gp_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 , z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~44 , z80_|execute_|ctl_bus_inc_oe~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~5 , z80_|execute_|ctl_reg_gp_sel[1]~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~0 , z80_|execute_|ctl_reg_gp_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~35 , z80_|execute_|ctl_reg_gp_hilo[1]~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~2 , z80_|execute_|ctl_sw_4u~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~3 , z80_|execute_|ctl_sw_4u~3, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~3 , z80_|execute_|fMRead~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~4 , z80_|execute_|ctl_sw_4u~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~15 , z80_|execute_|ctl_reg_sel_wz~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~8 , z80_|execute_|ctl_reg_sys_hilo[1]~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~94 , z80_|execute_|ctl_inc_cy~94, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~87 , z80_|execute_|ctl_inc_cy~87, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~42 , z80_|execute_|ctl_inc_cy~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~34 , z80_|execute_|ctl_reg_sys_hilo[1]~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~16 , z80_|execute_|ctl_reg_sel_wz~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~6 , z80_|execute_|ctl_sw_4u~6, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal2~2 , z80_|pla_decode_|Equal2~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~6 , z80_|pla_decode_|Equal1~6, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_exx~2 , z80_|reg_control_|bank_exx~2, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_exx , z80_|reg_control_|bank_exx, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de1~0 , z80_|reg_control_|bank_hl_de1~0, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de1 , z80_|reg_control_|bank_hl_de1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~10 , z80_|execute_|ctl_reg_gp_sel[1]~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~11 , z80_|execute_|ctl_reg_gp_sel[1]~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~12 , z80_|execute_|ctl_reg_gp_sel[1]~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~7 , z80_|execute_|ctl_mRead~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~9 , z80_|execute_|ctl_reg_gp_sel[1]~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~37 , z80_|execute_|ctl_reg_gp_sel[1]~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~13 , z80_|execute_|ctl_reg_gp_sel[1]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~47 , z80_|execute_|ctl_reg_gp_hilo[1]~47, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~3 , z80_|execute_|fMWrite~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~5 , z80_|execute_|ctl_flags_bus~5, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~2 , z80_|execute_|fMRead~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~19 , z80_|execute_|ctl_mRead~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~7 , z80_|execute_|ctl_reg_gp_sel[1]~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~8 , z80_|execute_|ctl_reg_gp_sel[1]~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~14 , z80_|execute_|ctl_reg_gp_sel[1]~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~16 , z80_|execute_|ctl_reg_gp_sel[1]~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~15 , z80_|execute_|ctl_reg_gp_sel[1]~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~17 , z80_|execute_|ctl_reg_gp_sel[1]~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~19 , z80_|execute_|ctl_reg_gp_sel[1]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~2 , z80_|execute_|ctl_reg_use_sp~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~47 , z80_|execute_|ctl_bus_inc_oe~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~3 , z80_|execute_|ctl_reg_use_sp~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~9 , z80_|execute_|ctl_sw_1d~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~21 , z80_|execute_|ctl_reg_gp_sel[0]~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~20 , z80_|execute_|ctl_reg_gp_hilo[1]~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~20 , z80_|execute_|ctl_reg_gp_sel[0]~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~49 , z80_|execute_|ctl_reg_gp_hilo[1]~49, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~22 , z80_|execute_|ctl_reg_gp_sel[0]~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~18 , z80_|execute_|ctl_reg_gp_sel[1]~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~23 , z80_|execute_|ctl_reg_gp_sel[1]~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~28 , z80_|execute_|ctl_reg_gp_sel[0]~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~23 , z80_|execute_|ctl_reg_gp_hilo[1]~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~2 , z80_|execute_|ctl_flags_cf2_sel_shift~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~14 , z80_|execute_|ctl_flags_hf_cpl~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~10 , z80_|execute_|ctl_flags_hf_cpl~10, spectrum, 1 +instance = comp, \z80_|execute_|setM1~47 , z80_|execute_|setM1~47, spectrum, 1 +instance = comp, \z80_|execute_|setM1~48 , z80_|execute_|setM1~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~13 , z80_|execute_|ctl_al_we~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_oe~0 , z80_|execute_|ctl_flags_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_oe~1 , z80_|execute_|ctl_flags_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~13 , z80_|execute_|ctl_reg_in_hi~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~29 , z80_|execute_|ctl_reg_gp_sel[0]~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~40 , z80_|execute_|ctl_inc_cy~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~2 , z80_|execute_|ctl_inc_dec~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~12 , z80_|execute_|ctl_inc_dec~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~43 , z80_|execute_|ctl_inc_cy~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~5 , z80_|execute_|ctl_inc_dec~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~4 , z80_|execute_|ctl_reg_gp_sel[1]~4, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~6 , z80_|execute_|fMRead~6, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~7 , z80_|execute_|fMRead~7, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~8 , z80_|execute_|fMRead~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~26 , z80_|execute_|ctl_reg_gp_sel[1]~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~13 , z80_|execute_|ctl_state_alu~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~10 , z80_|execute_|ctl_state_alu~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~11 , z80_|execute_|ctl_state_alu~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~9 , z80_|execute_|ctl_state_alu~9, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal62~2 , z80_|pla_decode_|Equal62~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~4 , z80_|execute_|ctl_flags_pf_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~21 , z80_|execute_|ctl_reg_gp_hilo[1]~21, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal64~0 , z80_|pla_decode_|Equal64~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel[0]~3 , z80_|execute_|ctl_pf_sel[0]~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~22 , z80_|execute_|ctl_reg_gp_hilo[1]~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~15 , z80_|execute_|ctl_state_alu~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~25 , z80_|execute_|ctl_reg_gp_sel[0]~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~30 , z80_|execute_|ctl_reg_gp_sel[0]~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~31 , z80_|execute_|ctl_reg_gp_sel[1]~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~33 , z80_|execute_|ctl_reg_gp_sel[0]~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~34 , z80_|execute_|ctl_reg_gp_sel[0]~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo~20 , z80_|execute_|ctl_reg_sys_hilo~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~32 , z80_|execute_|ctl_reg_gp_sel[0]~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~35 , z80_|execute_|ctl_reg_gp_sel[0]~35, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de2~5 , z80_|reg_control_|reg_sel_de2~5, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de2~6 , z80_|reg_control_|reg_sel_de2~6, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_hl~0 , z80_|reg_control_|reg_sel_hl~0, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de2~0 , z80_|reg_control_|bank_hl_de2~0, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de2 , z80_|reg_control_|bank_hl_de2, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_hl2~0 , z80_|reg_control_|reg_sel_hl2~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~7 , z80_|execute_|ctl_reg_in_hi~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~4 , z80_|execute_|ctl_reg_gp_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 , z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~3 , z80_|execute_|ctl_reg_gp_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~13 , z80_|execute_|ctl_alu_sel_op2_neg~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 , z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~2 , z80_|execute_|ctl_reg_gp_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~5 , z80_|execute_|ctl_reg_gp_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~6 , z80_|execute_|ctl_reg_gp_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~14 , z80_|execute_|ctl_al_we~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~50 , z80_|execute_|ctl_reg_gp_hilo[0]~50, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~26 , z80_|execute_|ctl_reg_gp_hilo[0]~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~27 , z80_|execute_|ctl_reg_gp_hilo[0]~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~28 , z80_|execute_|ctl_reg_gp_hilo[0]~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~29 , z80_|execute_|ctl_reg_gp_hilo[0]~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~31 , z80_|execute_|ctl_reg_gp_hilo[0]~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~51 , z80_|execute_|ctl_reg_gp_hilo[0]~51, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~30 , z80_|execute_|ctl_reg_gp_hilo[0]~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~32 , z80_|execute_|ctl_reg_gp_hilo[0]~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~34 , z80_|execute_|ctl_reg_gp_hilo[0]~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~24 , z80_|execute_|ctl_reg_gp_hilo[1]~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~25 , z80_|execute_|ctl_reg_gp_hilo[0]~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~36 , z80_|execute_|ctl_reg_gp_hilo[1]~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|setM1~40 , z80_|execute_|setM1~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~18 , z80_|execute_|ctl_reg_gp_hilo[1]~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~37 , z80_|execute_|ctl_reg_gp_hilo[1]~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~38 , z80_|execute_|ctl_reg_gp_hilo[0]~38, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~93 , z80_|reg_file_|gdfx_temp0[0]~93, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de~0 , z80_|reg_control_|reg_sel_de~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_50 , z80_|reg_file_|SYNTHESIZED_WIRE_50, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 , z80_|reg_file_|SYNTHESIZED_WIRE_70~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 , z80_|reg_file_|SYNTHESIZED_WIRE_66~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 , z80_|reg_file_|SYNTHESIZED_WIRE_38~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 , z80_|reg_file_|SYNTHESIZED_WIRE_42~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~9 , z80_|execute_|ctl_reg_in_hi~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~10 , z80_|execute_|ctl_reg_in_hi~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~19 , z80_|execute_|ctl_reg_sel_wz~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 , z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_lo~8 , z80_|execute_|ctl_reg_in_lo~8, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~19 , z80_|reg_file_|gdfx_temp0[0]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~4 , z80_|execute_|ctl_reg_use_sp~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~5 , z80_|execute_|ctl_reg_use_sp~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~6 , z80_|execute_|ctl_reg_use_sp~6, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 , z80_|reg_file_|SYNTHESIZED_WIRE_78~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal21~2 , z80_|pla_decode_|Equal21~2, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_af~0 , z80_|reg_control_|bank_af~0, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_af , z80_|reg_control_|bank_af, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_af~0 , z80_|reg_control_|reg_sel_af~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_34 , z80_|reg_file_|SYNTHESIZED_WIRE_34, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_af2~0 , z80_|reg_control_|reg_sel_af2~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_30 , z80_|reg_file_|SYNTHESIZED_WIRE_30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~12 , z80_|execute_|ctl_reg_sel_wz~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~4 , z80_|execute_|ctl_flags_bus~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~6 , z80_|execute_|ctl_flags_bus~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~7 , z80_|execute_|ctl_flags_bus~7, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~24 , z80_|execute_|fMRead~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~13 , z80_|execute_|ctl_flags_bus~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus , z80_|execute_|ctl_flags_bus, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~3 , z80_|execute_|ctl_inc_dec~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~14 , z80_|execute_|ctl_reg_sys_hilo[1]~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~2 , z80_|execute_|ctl_reg_sel_pc~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~3 , z80_|execute_|ctl_reg_sel_pc~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~6 , z80_|execute_|ctl_reg_sel_pc~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~5 , z80_|execute_|ctl_reg_sel_pc~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~4 , z80_|execute_|ctl_reg_sel_pc~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~7 , z80_|execute_|ctl_reg_sel_pc~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~8 , z80_|execute_|ctl_reg_sel_pc~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~9 , z80_|execute_|ctl_reg_sel_pc~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~10 , z80_|execute_|ctl_reg_sel_pc~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~13 , z80_|execute_|ctl_reg_sys_hilo[1]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~15 , z80_|execute_|ctl_reg_sys_hilo[1]~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~29 , z80_|execute_|ctl_bus_inc_oe~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~13 , z80_|execute_|ctl_mRead~13, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~49 , z80_|execute_|pc_inc_hold~49, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~9 , z80_|execute_|ctl_reg_sys_hilo[1]~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~10 , z80_|execute_|ctl_reg_sys_hilo[1]~10, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~28 , z80_|execute_|pc_inc_hold~28, spectrum, 1 +instance = comp, \z80_|execute_|setM1~35 , z80_|execute_|setM1~35, spectrum, 1 +instance = comp, \z80_|execute_|setM1~36 , z80_|execute_|setM1~36, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~5 , z80_|execute_|fMRead~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~31 , z80_|execute_|ctl_bus_inc_oe~31, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~29 , z80_|execute_|pc_inc_hold~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~1 , z80_|execute_|ctl_reg_sys_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~2 , z80_|execute_|ctl_reg_sys_we~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~3 , z80_|pla_decode_|Equal33~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~0 , z80_|execute_|ctl_reg_sys_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~3 , z80_|execute_|ctl_reg_sys_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~2 , z80_|execute_|ctl_reg_sys_we_lo~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~3 , z80_|execute_|ctl_reg_sys_we_lo~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~4 , z80_|execute_|ctl_reg_sys_we_lo~4, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo , z80_|reg_control_|reg_sys_we_lo, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_ir~0 , z80_|execute_|ctl_reg_sel_ir~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_ir~1 , z80_|execute_|ctl_reg_sel_ir~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~9 , z80_|execute_|ctl_reg_out_lo~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~36 , z80_|execute_|ctl_reg_sys_hilo[1]~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~12 , z80_|execute_|ctl_reg_sys_hilo[0]~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 , z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~4 , z80_|execute_|ctl_reg_in_hi~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~4 , z80_|execute_|ctl_reg_sel_wz~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~5 , z80_|execute_|ctl_reg_sel_wz~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~6 , z80_|execute_|ctl_reg_sel_wz~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~7 , z80_|execute_|ctl_reg_sel_wz~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo~16 , z80_|execute_|ctl_reg_sys_hilo~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~11 , z80_|execute_|ctl_reg_sel_pc~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~17 , z80_|execute_|ctl_reg_sys_hilo[1]~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~12 , z80_|execute_|ctl_reg_sel_pc~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~13 , z80_|execute_|ctl_reg_sel_pc~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~4 , z80_|execute_|ctl_al_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~38 , z80_|execute_|ctl_reg_sys_hilo[1]~38, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~0 , z80_|execute_|fMRead~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~24 , z80_|execute_|ctl_reg_sys_hilo[1]~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~25 , z80_|execute_|ctl_reg_sys_hilo[1]~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~4 , z80_|execute_|ctl_inc_dec~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~21 , z80_|execute_|ctl_reg_sys_hilo[1]~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~9 , z80_|execute_|ctl_reg_sel_wz~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 , z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~22 , z80_|execute_|ctl_reg_sys_hilo[1]~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~23 , z80_|execute_|ctl_reg_sys_hilo[1]~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~8 , z80_|execute_|ctl_reg_sel_wz~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~18 , z80_|execute_|ctl_reg_sys_hilo[1]~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~19 , z80_|execute_|ctl_reg_sys_hilo[1]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~26 , z80_|execute_|ctl_reg_sys_hilo[1]~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~5 , z80_|execute_|ctl_al_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~27 , z80_|execute_|ctl_reg_sys_hilo[1]~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~28 , z80_|execute_|ctl_reg_sys_hilo[1]~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~18 , z80_|execute_|ctl_reg_sel_wz~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~37 , z80_|execute_|ctl_reg_sys_hilo[0]~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~29 , z80_|execute_|ctl_reg_sys_hilo[0]~29, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_62 , z80_|reg_file_|SYNTHESIZED_WIRE_62, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~38 , z80_|execute_|ctl_bus_inc_oe~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~39 , z80_|execute_|ctl_bus_inc_oe~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~30 , z80_|execute_|ctl_bus_inc_oe~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~45 , z80_|execute_|ctl_bus_inc_oe~45, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~1 , z80_|execute_|fMRead~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~36 , z80_|execute_|ctl_bus_inc_oe~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~27 , z80_|execute_|ctl_bus_inc_oe~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~28 , z80_|execute_|ctl_bus_inc_oe~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~37 , z80_|execute_|ctl_bus_inc_oe~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~40 , z80_|execute_|ctl_bus_inc_oe~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~35 , z80_|execute_|ctl_bus_inc_oe~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~77 , z80_|execute_|ctl_inc_cy~77, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~32 , z80_|execute_|ctl_bus_inc_oe~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 , z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~33 , z80_|execute_|ctl_bus_inc_oe~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~34 , z80_|execute_|ctl_bus_inc_oe~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~41 , z80_|execute_|ctl_bus_inc_oe~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~10 , z80_|execute_|ctl_reg_sel_wz~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~11 , z80_|execute_|ctl_reg_sel_wz~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~3 , z80_|execute_|ctl_sw_4d~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~4 , z80_|execute_|ctl_sw_4d~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~2 , z80_|execute_|ctl_sw_4d~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~5 , z80_|execute_|ctl_sw_4d~5, spectrum, 1 +instance = comp, \z80_|execute_|setM1~45 , z80_|execute_|setM1~45, spectrum, 1 +instance = comp, \z80_|execute_|setM1~46 , z80_|execute_|setM1~46, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~1 , z80_|execute_|ctl_sw_4d~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~0 , z80_|execute_|ctl_sw_4d~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~6 , z80_|execute_|ctl_sw_4d~6, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~4 , z80_|execute_|fMRead~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~16 , z80_|execute_|ctl_reg_sel_pc~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~14 , z80_|execute_|ctl_reg_sel_pc~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~20 , z80_|execute_|ctl_reg_sel_pc~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~15 , z80_|execute_|ctl_reg_sel_pc~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~17 , z80_|execute_|ctl_reg_sel_pc~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~18 , z80_|execute_|ctl_reg_sel_pc~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~19 , z80_|execute_|ctl_reg_sel_pc~19, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~3 , z80_|reg_control_|reg_sel_pc~3, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc , z80_|reg_control_|reg_sel_pc, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_74 , z80_|reg_file_|SYNTHESIZED_WIRE_74, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~2 , z80_|reg_file_|db_lo_as[0]~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_75 , z80_|reg_file_|SYNTHESIZED_WIRE_75, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[7] , z80_|reg_file_|b2v_latch_pc_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[7]~22 , z80_|reg_file_|db_lo_as[7]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_63 , z80_|reg_file_|SYNTHESIZED_WIRE_63, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[7] , z80_|reg_file_|b2v_latch_ir_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[7]~23 , z80_|reg_file_|db_lo_as[7]~23, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10~0 , z80_|resets_|SYNTHESIZED_WIRE_10~0, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10 , z80_|resets_|SYNTHESIZED_WIRE_10, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_9 , z80_|resets_|SYNTHESIZED_WIRE_9, spectrum, 1 +instance = comp, \z80_|resets_|DFFE_intr_ff3 , z80_|resets_|DFFE_intr_ff3, spectrum, 1 instance = comp, \KEY[0]~input , KEY[0]~input, spectrum, 1 instance = comp, \z80_|resets_|x1~0 , z80_|resets_|x1~0, spectrum, 1 instance = comp, \z80_|fpga_reset~feeder , z80_|fpga_reset~feeder, spectrum, 1 instance = comp, \z80_|fpga_reset , z80_|fpga_reset, spectrum, 1 instance = comp, \z80_|fpga_reset~clkctrl , z80_|fpga_reset~clkctrl, spectrum, 1 instance = comp, \z80_|resets_|x1 , z80_|resets_|x1, spectrum, 1 -instance = comp, \z80_|resets_|x3 , z80_|resets_|x3, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12 , z80_|resets_|SYNTHESIZED_WIRE_12, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl , z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 -instance = comp, \KEY[1]~input , KEY[1]~input, spectrum, 1 -instance = comp, \z80_|interrupts_|nmi_armed~feeder , z80_|interrupts_|nmi_armed~feeder, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_9 , z80_|interrupts_|SYNTHESIZED_WIRE_9, spectrum, 1 -instance = comp, \z80_|interrupts_|nmi_armed , z80_|interrupts_|nmi_armed, spectrum, 1 -instance = comp, \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder , z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_11 , z80_|resets_|SYNTHESIZED_WIRE_11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 , z80_|execute_|ctl_reg_sys_hilo_1M1T3_3, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M3_ff~0 , z80_|sequencer_|DFFE_M3_ff~0, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M3_ff , z80_|sequencer_|DFFE_M3_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M4_ff~0 , z80_|sequencer_|DFFE_M4_ff~0, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M4_ff , z80_|sequencer_|DFFE_M4_ff, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~4 , z80_|execute_|ctl_ir_we~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal2~0 , z80_|pla_decode_|Equal2~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal9~0 , z80_|pla_decode_|Equal9~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal9~1 , z80_|pla_decode_|Equal9~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal6~0 , z80_|pla_decode_|Equal6~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal55~0 , z80_|pla_decode_|Equal55~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~12 , z80_|execute_|ctl_mRead~12, spectrum, 1 -instance = comp, \z80_|sequencer_|M5~0 , z80_|sequencer_|M5~0, spectrum, 1 -instance = comp, \z80_|sequencer_|M5 , z80_|sequencer_|M5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~2 , z80_|execute_|ctl_reg_in_hi~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~2 , z80_|execute_|ctl_alu_oe~2, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~8 , z80_|execute_|fMWrite~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~7 , z80_|execute_|ctl_ir_we~7, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal46~0 , z80_|pla_decode_|Equal46~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~10 , z80_|execute_|ctl_ir_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~44 , z80_|execute_|ctl_bus_inc_oe~44, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal41~0 , z80_|pla_decode_|Equal41~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~9 , z80_|execute_|ctl_ir_we~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~10 , z80_|execute_|ctl_alu_core_S~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~14 , z80_|execute_|ctl_ir_we~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~6 , z80_|execute_|ctl_ir_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~8 , z80_|execute_|ctl_ir_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~7 , z80_|execute_|ixy_d~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~27 , z80_|execute_|ctl_bus_inc_oe~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~28 , z80_|execute_|ctl_bus_inc_oe~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~10 , z80_|execute_|ctl_mRead~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~49 , z80_|execute_|ctl_bus_inc_oe~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~3 , z80_|execute_|ctl_mWrite~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~16 , z80_|execute_|ctl_mWrite~16, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~4 , z80_|execute_|ixy_d~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~29 , z80_|execute_|ctl_bus_inc_oe~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~30 , z80_|execute_|ctl_bus_inc_oe~30, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~5 , z80_|execute_|ixy_d~5, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_16 , z80_|sequencer_|SYNTHESIZED_WIRE_16, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T5_ff , z80_|sequencer_|DFFE_T5_ff, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal41~1 , z80_|pla_decode_|Equal41~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal41~2 , z80_|pla_decode_|Equal41~2, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~10 , z80_|execute_|ixy_d~10, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal44~0 , z80_|pla_decode_|Equal44~0, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~16 , z80_|execute_|ixy_d~16, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~13 , z80_|execute_|ixy_d~13, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~9 , z80_|execute_|ixy_d~9, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~8 , z80_|execute_|ixy_d~8, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~12 , z80_|execute_|ixy_d~12, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~14 , z80_|execute_|ixy_d~14, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~6 , z80_|execute_|ixy_d~6, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~11 , z80_|execute_|ixy_d~11, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal49~0 , z80_|pla_decode_|Equal49~0, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~15 , z80_|execute_|ixy_d~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 , z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7, spectrum, 1 -instance = comp, \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 , z80_|decode_state_|SYNTHESIZED_WIRE_0~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_ixiy_we~2 , z80_|execute_|ctl_state_ixiy_we~2, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_inst4 , z80_|decode_state_|DFFE_inst4, spectrum, 1 -instance = comp, \z80_|decode_state_|use_ixiy , z80_|decode_state_|use_ixiy, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~9 , z80_|execute_|ctl_mRead~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~4 , z80_|execute_|ctl_mWrite~4, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~5 , z80_|execute_|fMWrite~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~4 , z80_|execute_|ctl_state_alu~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal19~0 , z80_|pla_decode_|Equal19~0, spectrum, 1 -instance = comp, \z80_|execute_|comb~0 , z80_|execute_|comb~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal47~0 , z80_|pla_decode_|Equal47~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal34~0 , z80_|pla_decode_|Equal34~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~2 , z80_|execute_|ctl_state_alu~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~36 , z80_|execute_|ctl_inc_cy~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~0 , z80_|execute_|ctl_inc_dec~0, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~6 , z80_|pin_control_|bus_db_pin_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~7 , z80_|execute_|fMWrite~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~14 , z80_|execute_|ctl_alu_shift_oe~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~0 , z80_|execute_|ctl_sw_4u~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~10 , z80_|execute_|ctl_reg_sys_hilo[1]~10, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~8 , z80_|pin_control_|bus_db_pin_oe~8, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal13~1 , z80_|pla_decode_|Equal13~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal13~2 , z80_|pla_decode_|Equal13~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~16 , z80_|pin_control_|bus_db_pin_oe~16, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~5 , z80_|execute_|fIOWrite~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~6 , z80_|execute_|ctl_mWrite~6, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~0 , z80_|execute_|fMWrite~0, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~6 , z80_|execute_|fMWrite~6, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~9 , z80_|pin_control_|bus_db_pin_oe~9, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~3 , z80_|execute_|fMRead~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~8 , z80_|execute_|ctl_mRead~8, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~7 , z80_|pin_control_|bus_db_pin_oe~7, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~10 , z80_|pin_control_|bus_db_pin_oe~10, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal19~1 , z80_|pla_decode_|Equal19~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~4 , z80_|execute_|ctl_reg_sel_wz~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~5 , z80_|execute_|ctl_reg_sel_wz~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~6 , z80_|execute_|ctl_reg_sel_wz~6, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~11 , z80_|pin_control_|bus_db_pin_oe~11, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~12 , z80_|pin_control_|bus_db_pin_oe~12, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal11~0 , z80_|pla_decode_|Equal11~0, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~4 , z80_|pin_control_|bus_db_pin_oe~4, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~5 , z80_|pin_control_|bus_db_pin_oe~5, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~13 , z80_|pin_control_|bus_db_pin_oe~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~3 , z80_|execute_|ctl_state_alu~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~31 , z80_|execute_|ctl_inc_cy~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~38 , z80_|execute_|ctl_reg_sys_hilo[1]~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~30 , z80_|execute_|ctl_inc_cy~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_apin_mux~0 , z80_|execute_|ctl_apin_mux~0, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~1 , z80_|execute_|fMWrite~1, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~2 , z80_|execute_|fMWrite~2, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~3 , z80_|execute_|fMWrite~3, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~4 , z80_|execute_|fMWrite~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~85 , z80_|execute_|ctl_inc_cy~85, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~34 , z80_|execute_|ctl_inc_cy~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~86 , z80_|execute_|ctl_inc_cy~86, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~35 , z80_|execute_|ctl_inc_cy~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~26 , z80_|execute_|ctl_bus_inc_oe~26, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~3 , z80_|execute_|fIOWrite~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~6 , z80_|execute_|ctl_mRead~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~38 , z80_|execute_|ctl_mRead~38, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~1 , z80_|execute_|fIOWrite~1, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~2 , z80_|execute_|fIOWrite~2, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~2 , z80_|execute_|fMRead~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~2 , z80_|execute_|ctl_mWrite~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~10 , z80_|execute_|ctl_iorw~10, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~0 , z80_|execute_|fIOWrite~0, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~4 , z80_|execute_|fIOWrite~4, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~3 , z80_|pin_control_|bus_db_pin_oe~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~0 , z80_|execute_|ctl_sw_2u~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~32 , z80_|execute_|ctl_inc_cy~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~33 , z80_|execute_|ctl_inc_cy~33, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~14 , z80_|pin_control_|bus_db_pin_oe~14, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~2 , z80_|pin_control_|bus_db_pin_oe~2, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~15 , z80_|pin_control_|bus_db_pin_oe~15, spectrum, 1 -instance = comp, \z80_|address_pins_|abus[0]~18 , z80_|address_pins_|abus[0]~18, spectrum, 1 -instance = comp, \PS2_DAT~input , PS2_DAT~input, spectrum, 1 -instance = comp, \reset~clkctrl , reset~clkctrl, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~0 , ula_|ps2_keyboard_|bit_count~0, spectrum, 1 -instance = comp, \PS2_CLK~input , PS2_CLK~input, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[7] , ula_|ps2_keyboard_|clk_filter[7], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[6]~feeder , ula_|ps2_keyboard_|clk_filter[6]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[6] , ula_|ps2_keyboard_|clk_filter[6], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[5]~feeder , ula_|ps2_keyboard_|clk_filter[5]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[5] , ula_|ps2_keyboard_|clk_filter[5], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[4]~feeder , ula_|ps2_keyboard_|clk_filter[4]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[4] , ula_|ps2_keyboard_|clk_filter[4], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[3] , ula_|ps2_keyboard_|clk_filter[3], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[2]~feeder , ula_|ps2_keyboard_|clk_filter[2]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[2] , ula_|ps2_keyboard_|clk_filter[2], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[1]~feeder , ula_|ps2_keyboard_|clk_filter[1]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[1] , ula_|ps2_keyboard_|clk_filter[1], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|Equal0~0 , ula_|ps2_keyboard_|Equal0~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|Equal0~1 , ula_|ps2_keyboard_|Equal0~1, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[0]~0 , ula_|ps2_keyboard_|clk_filter[0]~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[0] , ula_|ps2_keyboard_|clk_filter[0], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|ps2_clk_in~0 , ula_|ps2_keyboard_|ps2_clk_in~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|ps2_clk_in , ula_|ps2_keyboard_|ps2_clk_in, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_edge~0 , ula_|ps2_keyboard_|clk_edge~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_edge , ula_|ps2_keyboard_|clk_edge, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[0] , ula_|ps2_keyboard_|bit_count[0], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~1 , ula_|ps2_keyboard_|bit_count~1, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[2] , ula_|ps2_keyboard_|bit_count[2], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~2 , ula_|ps2_keyboard_|bit_count~2, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[1] , ula_|ps2_keyboard_|bit_count[1], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~3 , ula_|ps2_keyboard_|bit_count~3, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[3] , ula_|ps2_keyboard_|bit_count[3], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|always1~0 , ula_|ps2_keyboard_|always1~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|LessThan0~0 , ula_|ps2_keyboard_|LessThan0~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[0]~0 , ula_|ps2_keyboard_|shiftreg[0]~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[8] , ula_|ps2_keyboard_|shiftreg[8], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[7] , ula_|ps2_keyboard_|shiftreg[7], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[6] , ula_|ps2_keyboard_|shiftreg[6], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[5] , ula_|ps2_keyboard_|shiftreg[5], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[4] , ula_|ps2_keyboard_|shiftreg[4], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[3] , ula_|ps2_keyboard_|shiftreg[3], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[2] , ula_|ps2_keyboard_|shiftreg[2], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[1] , ula_|ps2_keyboard_|shiftreg[1], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[0] , ula_|ps2_keyboard_|shiftreg[0], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|WideXor0~0 , ula_|ps2_keyboard_|WideXor0~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|WideXor0~1 , ula_|ps2_keyboard_|WideXor0~1, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|WideXor0~2 , ula_|ps2_keyboard_|WideXor0~2, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|scan_code_ready~0 , ula_|ps2_keyboard_|scan_code_ready~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|scan_code_ready , ula_|ps2_keyboard_|scan_code_ready, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Equal0~0 , ula_|zx_keyboard_|Equal0~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Equal0~1 , ula_|zx_keyboard_|Equal0~1, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|extended~0 , ula_|zx_keyboard_|extended~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|extended , ula_|zx_keyboard_|extended, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1]~45 , ula_|zx_keyboard_|keys[7][1]~45, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|released~0 , ula_|zx_keyboard_|released~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|released , ula_|zx_keyboard_|released, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~5 , ula_|zx_keyboard_|WideOr16~5, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~2 , ula_|zx_keyboard_|WideOr16~2, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~4 , ula_|zx_keyboard_|WideOr16~4, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~7 , ula_|zx_keyboard_|WideOr16~7, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~6 , ula_|zx_keyboard_|WideOr16~6, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1]~46 , ula_|zx_keyboard_|keys[7][1]~46, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1] , ula_|zx_keyboard_|keys[7][1], spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 , z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal10~0 , z80_|pla_decode_|Equal10~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal8~0 , z80_|pla_decode_|Equal8~0, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~19 , z80_|execute_|pc_inc_hold~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~0 , z80_|execute_|ctl_reg_sys_we~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~34 , z80_|execute_|ctl_bus_inc_oe~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~35 , z80_|execute_|ctl_bus_inc_oe~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~7 , z80_|execute_|ctl_inc_dec~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~13 , z80_|execute_|ctl_mRead~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~37 , z80_|execute_|ctl_inc_cy~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~1 , z80_|execute_|ctl_inc_dec~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~2 , z80_|execute_|ctl_inc_dec~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~3 , z80_|execute_|ctl_inc_dec~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~4 , z80_|execute_|ctl_inc_dec~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~4 , z80_|execute_|ctl_reg_gp_sel[1]~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 , z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~45 , z80_|execute_|ctl_bus_inc_oe~45, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~2 , z80_|execute_|ctl_reg_gp_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~7 , z80_|execute_|ctl_mWrite~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~5 , z80_|execute_|ctl_inc_dec~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~6 , z80_|execute_|ctl_inc_dec~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~8 , z80_|execute_|ctl_inc_dec~8, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10~0 , z80_|resets_|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10 , z80_|resets_|SYNTHESIZED_WIRE_10, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_9~feeder , z80_|resets_|SYNTHESIZED_WIRE_9~feeder, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_9 , z80_|resets_|SYNTHESIZED_WIRE_9, spectrum, 1 -instance = comp, \z80_|resets_|DFFE_intr_ff3 , z80_|resets_|DFFE_intr_ff3, spectrum, 1 instance = comp, \z80_|resets_|clrpc_int~0 , z80_|resets_|clrpc_int~0, spectrum, 1 instance = comp, \z80_|resets_|clrpc_int , z80_|resets_|clrpc_int, spectrum, 1 instance = comp, \z80_|resets_|clrpc~0 , z80_|resets_|clrpc~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~34 , z80_|execute_|ctl_reg_gp_hilo[1]~34, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal38~2 , z80_|pla_decode_|Equal38~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~4 , z80_|pla_decode_|Equal1~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal37~0 , z80_|pla_decode_|Equal37~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~76 , z80_|execute_|ctl_inc_cy~76, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal29~0 , z80_|pla_decode_|Equal29~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~77 , z80_|execute_|ctl_inc_cy~77, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~18 , z80_|execute_|ctl_mRead~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~47 , z80_|execute_|ctl_inc_cy~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~50 , z80_|execute_|ctl_bus_inc_oe~50, spectrum, 1 -instance = comp, \z80_|execute_|comb~1 , z80_|execute_|comb~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal4~0 , z80_|pla_decode_|Equal4~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~48 , z80_|execute_|ctl_bus_inc_oe~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~3 , z80_|execute_|ctl_reg_gp_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~17 , z80_|execute_|ctl_alu_op_low~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~18 , z80_|execute_|ctl_alu_op_low~18, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal56~0 , z80_|pla_decode_|Equal56~0, spectrum, 1 -instance = comp, \z80_|execute_|nextM~2 , z80_|execute_|nextM~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~2 , z80_|execute_|ctl_sw_4u~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~3 , z80_|execute_|ctl_sw_4u~3, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal12~0 , z80_|pla_decode_|Equal12~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~12 , z80_|execute_|ctl_ir_we~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 , z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~15 , z80_|execute_|ctl_reg_sel_wz~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~82 , z80_|execute_|ctl_inc_cy~82, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal12~1 , z80_|pla_decode_|Equal12~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal25~0 , z80_|pla_decode_|Equal25~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~38 , z80_|execute_|ctl_inc_cy~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~19 , z80_|execute_|ctl_mRead~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~87 , z80_|execute_|ctl_inc_cy~87, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~37 , z80_|execute_|ctl_reg_sys_hilo[1]~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 , z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~17 , z80_|execute_|ctl_mRead~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~17 , z80_|execute_|ctl_reg_sys_hilo[1]~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~16 , z80_|execute_|ctl_reg_sel_wz~16, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal40~0 , z80_|pla_decode_|Equal40~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal21~1 , z80_|pla_decode_|Equal21~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal3~0 , z80_|pla_decode_|Equal3~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal39~0 , z80_|pla_decode_|Equal39~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal40~1 , z80_|pla_decode_|Equal40~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~34 , z80_|execute_|ctl_reg_sys_hilo[0]~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~4 , z80_|execute_|ctl_reg_out_hi~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~1 , z80_|execute_|ctl_sw_4u~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~5 , z80_|pla_decode_|Equal1~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~20 , z80_|execute_|ctl_alu_op_low~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~4 , z80_|execute_|ctl_sw_4u~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~5 , z80_|execute_|ctl_sw_4u~5, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal6~1 , z80_|pla_decode_|Equal6~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~4 , z80_|execute_|ctl_reg_use_sp~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~5 , z80_|execute_|ctl_reg_use_sp~5, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~12 , z80_|execute_|fMRead~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~3 , z80_|execute_|ctl_reg_gp_sel[1]~3, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~13 , z80_|execute_|fMRead~13, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~14 , z80_|execute_|fMRead~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~25 , z80_|execute_|ctl_reg_gp_sel[1]~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~2 , z80_|execute_|ctl_reg_use_sp~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~0 , z80_|execute_|ctl_reg_use_sp~0, spectrum, 1 -instance = comp, \z80_|execute_|nextM~11 , z80_|execute_|nextM~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~3 , z80_|execute_|ctl_reg_use_sp~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~6 , z80_|execute_|ctl_reg_use_sp~6, spectrum, 1 -instance = comp, \z80_|nM1_int~2 , z80_|nM1_int~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~19 , z80_|execute_|ctl_reg_gp_hilo[1]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 , z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~5 , z80_|execute_|ctl_reg_gp_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~8 , z80_|execute_|ctl_sw_1d~8, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal69~0 , z80_|pla_decode_|Equal69~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~16 , z80_|execute_|ctl_mRead~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~12 , z80_|execute_|ctl_reg_gp_sel[0]~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~8 , z80_|execute_|ctl_reg_in_hi~8, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal52~1 , z80_|pla_decode_|Equal52~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~6 , z80_|execute_|ctl_state_alu~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~13 , z80_|execute_|ctl_state_alu~13, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal63~0 , z80_|pla_decode_|Equal63~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~5 , z80_|execute_|ctl_flags_bus~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~11 , z80_|execute_|ctl_iorw~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_oe~0 , z80_|execute_|ctl_flags_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~13 , z80_|execute_|ctl_al_we~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_oe~1 , z80_|execute_|ctl_flags_oe~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~19 , z80_|execute_|ctl_alu_op_low~19, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal68~2 , z80_|pla_decode_|Equal68~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~12 , z80_|execute_|ctl_flags_hf_cpl~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~5 , z80_|execute_|ctl_state_alu~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~8 , z80_|execute_|ctl_flags_hf_cpl~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~11 , z80_|execute_|ctl_ir_we~11, spectrum, 1 -instance = comp, \z80_|execute_|setM1~47 , z80_|execute_|setM1~47, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal20~0 , z80_|pla_decode_|Equal20~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~2 , z80_|execute_|ctl_flags_cf2_sel_shift~2, spectrum, 1 -instance = comp, \z80_|execute_|setM1~48 , z80_|execute_|setM1~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~13 , z80_|execute_|ctl_reg_in_hi~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~6 , z80_|execute_|ctl_reg_gp_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~27 , z80_|execute_|ctl_mRead~27, spectrum, 1 -instance = comp, \z80_|execute_|setM1~30 , z80_|execute_|setM1~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~2 , z80_|execute_|ctl_reg_gp_sel[0]~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 , z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~10 , z80_|execute_|ctl_alu_sel_op2_neg~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~7 , z80_|execute_|ctl_state_alu~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~12 , z80_|execute_|ctl_state_alu~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~9 , z80_|execute_|ctl_state_alu~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~10 , z80_|execute_|ctl_state_alu~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~8 , z80_|execute_|ctl_state_alu~8, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal62~2 , z80_|pla_decode_|Equal62~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~4 , z80_|execute_|ctl_flags_pf_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~7 , z80_|execute_|ctl_mRead~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~26 , z80_|execute_|ctl_reg_gp_hilo[1]~26, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal64~0 , z80_|pla_decode_|Equal64~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel[0]~3 , z80_|execute_|ctl_pf_sel[0]~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla82M1T1_16 , z80_|execute_|ctl_pf_sel_pla82M1T1_16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~9 , z80_|execute_|ctl_alu_oe~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~22 , z80_|execute_|ctl_mRead~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~28 , z80_|execute_|ctl_mRead~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~10 , z80_|execute_|ctl_alu_oe~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~27 , z80_|execute_|ctl_reg_gp_hilo[1]~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~20 , z80_|execute_|ctl_mRead~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~9 , z80_|execute_|ctl_sw_1d~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~9 , z80_|execute_|ctl_reg_gp_we~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~4 , z80_|execute_|ctl_reg_gp_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~7 , z80_|execute_|ctl_reg_gp_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~8 , z80_|execute_|ctl_reg_gp_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~14 , z80_|execute_|ctl_al_we~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~30 , z80_|execute_|ctl_reg_gp_hilo[1]~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~15 , z80_|execute_|ctl_alu_shift_oe~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~49 , z80_|execute_|ctl_reg_gp_hilo[1]~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 , z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~24 , z80_|execute_|ctl_reg_gp_hilo[1]~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~51 , z80_|execute_|ctl_reg_gp_hilo[1]~51, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~4 , z80_|execute_|ctl_sw_1d~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~28 , z80_|execute_|ctl_reg_gp_hilo[1]~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~29 , z80_|execute_|ctl_reg_gp_hilo[1]~29, spectrum, 1 -instance = comp, \z80_|execute_|rsel3 , z80_|execute_|rsel3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~31 , z80_|execute_|ctl_reg_gp_hilo[1]~31, spectrum, 1 -instance = comp, \z80_|execute_|rsel0 , z80_|execute_|rsel0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~2 , z80_|execute_|ctl_sw_2u~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~3 , z80_|execute_|ctl_sw_2u~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~50 , z80_|execute_|ctl_reg_gp_hilo[1]~50, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel~5 , z80_|execute_|ctl_reg_gp_sel~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~32 , z80_|execute_|ctl_reg_gp_hilo[1]~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~33 , z80_|execute_|ctl_reg_gp_hilo[1]~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~35 , z80_|execute_|ctl_reg_gp_hilo[1]~35, spectrum, 1 -instance = comp, \z80_|execute_|setM1~41 , z80_|execute_|setM1~41, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal2~1 , z80_|pla_decode_|Equal2~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal11~1 , z80_|pla_decode_|Equal11~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 , z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~18 , z80_|execute_|ctl_reg_gp_hilo[1]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~36 , z80_|execute_|ctl_reg_gp_hilo[1]~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~48 , z80_|execute_|ctl_reg_gp_hilo[1]~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~15 , z80_|execute_|ctl_mRead~15, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~5 , z80_|execute_|fMRead~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~21 , z80_|execute_|ctl_mRead~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~12 , z80_|execute_|ctl_iorw~12, spectrum, 1 -instance = comp, \z80_|execute_|setM1~46 , z80_|execute_|setM1~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~37 , z80_|execute_|ctl_reg_gp_hilo[1]~37, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal48~0 , z80_|pla_decode_|Equal48~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~11 , z80_|execute_|ctl_alu_bs_oe~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~7 , z80_|execute_|ctl_alu_bs_oe~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~2 , z80_|execute_|ctl_bus_db_oe~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~18 , z80_|execute_|ctl_flags_xy_we~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~27 , z80_|execute_|ctl_alu_shift_oe~27, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal35~0 , z80_|pla_decode_|Equal35~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~25 , z80_|execute_|ctl_alu_shift_oe~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~26 , z80_|execute_|ctl_alu_shift_oe~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~28 , z80_|execute_|ctl_alu_shift_oe~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~6 , z80_|execute_|ctl_flags_bus~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~7 , z80_|execute_|ctl_flags_bus~7, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal76~0 , z80_|pla_decode_|Equal76~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~8 , z80_|execute_|ctl_flags_bus~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~14 , z80_|execute_|ctl_flags_bus~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~15 , z80_|execute_|ctl_flags_bus~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~9 , z80_|execute_|ctl_flags_bus~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~10 , z80_|execute_|ctl_flags_bus~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~11 , z80_|execute_|ctl_flags_xy_we~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf2_we , z80_|execute_|ctl_flags_hf2_we, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~41 , z80_|execute_|ctl_alu_shift_oe~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~12 , z80_|execute_|ctl_flags_xy_we~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~6 , z80_|execute_|ctl_reg_gp_sel[0]~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~21 , z80_|execute_|ctl_reg_gp_hilo[1]~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~7 , z80_|execute_|ctl_reg_gp_sel[0]~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~22 , z80_|execute_|ctl_reg_gp_hilo[1]~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~52 , z80_|execute_|ctl_reg_gp_hilo[1]~52, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~38 , z80_|execute_|ctl_reg_gp_hilo[1]~38, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 , z80_|reg_file_|SYNTHESIZED_WIRE_68~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~11 , z80_|execute_|ctl_reg_gp_sel[1]~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~34 , z80_|execute_|ctl_reg_gp_sel[1]~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~9 , z80_|execute_|ctl_reg_gp_sel[1]~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~8 , z80_|execute_|ctl_reg_gp_sel[1]~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~10 , z80_|execute_|ctl_reg_gp_sel[1]~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~13 , z80_|execute_|ctl_reg_gp_sel[0]~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~14 , z80_|execute_|ctl_reg_gp_sel[0]~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~15 , z80_|execute_|ctl_reg_gp_sel[1]~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~18 , z80_|execute_|ctl_reg_gp_sel[1]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 , z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~19 , z80_|execute_|ctl_reg_gp_sel[1]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~20 , z80_|execute_|ctl_reg_gp_sel[1]~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~21 , z80_|execute_|ctl_reg_gp_sel[1]~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~22 , z80_|execute_|ctl_reg_gp_sel[1]~22, spectrum, 1 -instance = comp, \z80_|execute_|setM1~56 , z80_|execute_|setM1~56, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~1 , z80_|execute_|ctl_sw_2u~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~25 , z80_|execute_|ctl_reg_gp_hilo[1]~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~23 , z80_|execute_|ctl_reg_gp_sel[1]~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~26 , z80_|execute_|ctl_reg_gp_sel[0]~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~27 , z80_|execute_|ctl_reg_gp_sel[0]~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~24 , z80_|execute_|ctl_reg_gp_sel[0]~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~28 , z80_|execute_|ctl_reg_gp_sel[0]~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~16 , z80_|execute_|ctl_reg_gp_sel[1]~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~22 , z80_|execute_|ctl_alu_op_low~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~29 , z80_|execute_|ctl_mRead~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~17 , z80_|execute_|ctl_reg_gp_sel[1]~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~29 , z80_|execute_|ctl_reg_gp_sel[1]~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo~24 , z80_|execute_|ctl_reg_sys_hilo~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~30 , z80_|execute_|ctl_reg_gp_sel[0]~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~31 , z80_|execute_|ctl_reg_gp_sel[0]~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~32 , z80_|execute_|ctl_reg_gp_sel[0]~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~33 , z80_|execute_|ctl_reg_gp_sel[0]~33, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 , z80_|reg_file_|SYNTHESIZED_WIRE_76~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~6 , z80_|pla_decode_|Equal1~6, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_exx~2 , z80_|reg_control_|bank_exx~2, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_exx , z80_|reg_control_|bank_exx, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 , z80_|reg_file_|SYNTHESIZED_WIRE_40~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_iy~2 , z80_|reg_control_|reg_sel_iy~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68 , z80_|reg_file_|SYNTHESIZED_WIRE_68, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 , z80_|reg_file_|SYNTHESIZED_WIRE_36~0, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~18 , z80_|reg_file_|gdfx_temp1[0]~18, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal21~2 , z80_|pla_decode_|Equal21~2, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_af~0 , z80_|reg_control_|bank_af~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_af , z80_|reg_control_|bank_af, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_af~0 , z80_|reg_control_|reg_sel_af~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_af2~0 , z80_|reg_control_|reg_sel_af2~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_28 , z80_|reg_file_|SYNTHESIZED_WIRE_28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~10 , z80_|execute_|ctl_reg_sel_wz~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~4 , z80_|execute_|ctl_alu_oe~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal24~0 , z80_|pla_decode_|Equal24~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~0 , z80_|reg_control_|reg_sel_pc~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~1 , z80_|reg_control_|reg_sel_pc~1, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~2 , z80_|reg_control_|reg_sel_pc~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~2 , z80_|execute_|ctl_alu_sel_op2_neg~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~6 , z80_|execute_|ctl_reg_in_hi~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~5 , z80_|execute_|ctl_reg_in_hi~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~8 , z80_|execute_|ctl_reg_sel_wz~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~18 , z80_|execute_|ctl_reg_sys_hilo[1]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~8 , z80_|execute_|ctl_reg_sel_pc~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~9 , z80_|execute_|ctl_reg_sel_pc~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~5 , z80_|execute_|ctl_reg_sel_pc~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~2 , z80_|execute_|ctl_reg_sel_pc~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~3 , z80_|execute_|ctl_reg_sel_pc~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~4 , z80_|execute_|ctl_reg_sel_pc~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~6 , z80_|execute_|ctl_reg_sel_pc~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~7 , z80_|execute_|ctl_reg_sel_pc~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~10 , z80_|execute_|ctl_reg_sel_pc~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~16 , z80_|execute_|ctl_reg_sys_hilo[1]~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~11 , z80_|execute_|ctl_reg_sel_pc~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~19 , z80_|execute_|ctl_reg_sys_hilo[1]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~4 , z80_|execute_|ctl_al_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~40 , z80_|execute_|ctl_reg_sys_hilo[1]~40, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~2 , z80_|pla_decode_|Equal33~2, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~18 , z80_|execute_|pc_inc_hold~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~7 , z80_|execute_|ctl_reg_sel_wz~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~22 , z80_|execute_|ctl_reg_sys_hilo[1]~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~23 , z80_|execute_|ctl_reg_sys_hilo[1]~23, spectrum, 1 -instance = comp, \z80_|execute_|setM1~36 , z80_|execute_|setM1~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~28 , z80_|execute_|ctl_reg_sys_hilo[1]~28, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal24~1 , z80_|pla_decode_|Equal24~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~11 , z80_|execute_|ctl_reg_sys_hilo[1]~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~12 , z80_|execute_|ctl_reg_sys_hilo[1]~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~29 , z80_|execute_|ctl_reg_sys_hilo[1]~29, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~40 , z80_|execute_|pc_inc_hold~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~9 , z80_|execute_|ctl_reg_sel_wz~9, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~3 , z80_|pla_decode_|Equal33~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~25 , z80_|execute_|ctl_reg_sys_hilo[1]~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~26 , z80_|execute_|ctl_reg_sys_hilo[1]~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~27 , z80_|execute_|ctl_reg_sys_hilo[1]~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~30 , z80_|execute_|ctl_reg_sys_hilo[1]~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~31 , z80_|execute_|ctl_reg_sys_hilo[1]~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo~20 , z80_|execute_|ctl_reg_sys_hilo~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~12 , z80_|execute_|ctl_reg_sel_pc~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~21 , z80_|execute_|ctl_reg_sys_hilo[1]~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~13 , z80_|execute_|ctl_reg_sel_pc~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~14 , z80_|execute_|ctl_reg_sel_pc~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~32 , z80_|execute_|ctl_reg_sys_hilo[1]~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~3 , z80_|execute_|ctl_reg_in_hi~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~14 , z80_|execute_|ctl_reg_sys_hilo[1]~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_lo~9 , z80_|execute_|ctl_reg_in_lo~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~13 , z80_|execute_|ctl_reg_sys_hilo[1]~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~15 , z80_|execute_|ctl_reg_sys_hilo[1]~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~33 , z80_|execute_|ctl_reg_sys_hilo[1]~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~12 , z80_|execute_|ctl_reg_sel_wz~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~13 , z80_|execute_|ctl_reg_sel_wz~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~24 , z80_|execute_|ctl_mRead~24, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~0 , z80_|reg_control_|reg_sys_we_lo~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~1 , z80_|reg_control_|reg_sys_we_lo~1, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~2 , z80_|reg_control_|reg_sys_we_lo~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~23 , z80_|execute_|ctl_mRead~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~25 , z80_|execute_|ctl_mRead~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~17 , z80_|execute_|ctl_flags_xy_we~17, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~3 , z80_|reg_control_|reg_sys_we_lo~3, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~4 , z80_|reg_control_|reg_sys_we_lo~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~19 , z80_|execute_|ctl_reg_sel_wz~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~4 , z80_|execute_|ctl_flags_bus~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~11 , z80_|execute_|ctl_flags_bus~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~12 , z80_|execute_|ctl_flags_bus~12, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~27 , z80_|execute_|fMRead~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~13 , z80_|execute_|ctl_flags_bus~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus , z80_|execute_|ctl_flags_bus, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~7 , z80_|execute_|ctl_bus_db_oe~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~11 , z80_|execute_|ctl_alu_op2_sel_bus~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~1 , z80_|execute_|ctl_flags_sz_we~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~4 , z80_|execute_|ctl_alu_op1_sel_zero~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~15 , z80_|execute_|ctl_alu_op_low~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~36 , z80_|execute_|ctl_alu_op_low~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~21 , z80_|execute_|ctl_alu_op_low~21, spectrum, 1 -instance = comp, \z80_|execute_|setM1~17 , z80_|execute_|setM1~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_daa , z80_|execute_|ctl_flags_cf2_sel_daa, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~6 , z80_|execute_|ctl_flags_xy_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~6 , z80_|execute_|ctl_alu_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_we~5 , z80_|execute_|ctl_flags_hf_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~10 , z80_|execute_|ctl_flags_pf_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~7 , z80_|execute_|ctl_flags_cf_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~13 , z80_|execute_|ctl_flags_use_cf2~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel[0]~2 , z80_|execute_|ctl_pf_sel[0]~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~2 , z80_|execute_|ctl_flags_pf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~7 , z80_|execute_|ctl_flags_xy_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~2 , z80_|execute_|ctl_flags_sz_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~1 , z80_|execute_|ctl_reg_use_sp~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~3 , z80_|execute_|ctl_alu_sel_op2_neg~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~13 , z80_|execute_|ctl_flags_alu~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~0 , z80_|execute_|ctl_flags_sz_we~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~4 , z80_|execute_|ctl_flags_sz_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~10 , z80_|execute_|ctl_alu_op2_sel_bus~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~4 , z80_|execute_|ctl_sw_2d~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~16 , z80_|execute_|ctl_alu_op_low~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~16 , z80_|execute_|ctl_flags_xy_we~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~14 , z80_|execute_|ctl_flags_alu~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~15 , z80_|execute_|ctl_flags_alu~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~8 , z80_|execute_|ctl_flags_xy_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla11M1T1_11 , z80_|execute_|ctl_pf_sel_pla11M1T1_11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~9 , z80_|execute_|ctl_flags_xy_we~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~3 , z80_|execute_|ctl_flags_sz_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~10 , z80_|execute_|ctl_flags_alu~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~11 , z80_|execute_|ctl_flags_alu~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~12 , z80_|execute_|ctl_flags_alu~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~18 , z80_|execute_|ctl_flags_alu~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~6 , z80_|execute_|ctl_flags_alu~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~17 , z80_|execute_|ctl_flags_alu~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~8 , z80_|execute_|ctl_flags_alu~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 , z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 , z80_|execute_|ctl_pf_sel_pla12M1T1_12~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~0 , z80_|execute_|ctl_alu_core_R~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~1 , z80_|execute_|ctl_alu_core_R~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~19 , z80_|execute_|ctl_flags_alu~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~7 , z80_|execute_|ctl_flags_alu~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~9 , z80_|execute_|ctl_flags_alu~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~16 , z80_|execute_|ctl_flags_alu~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~2 , z80_|execute_|ctl_reg_out_lo~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~5 , z80_|execute_|ctl_reg_out_hi~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~6 , z80_|execute_|ctl_sw_2u~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~6 , z80_|execute_|ctl_reg_out_hi~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~8 , z80_|execute_|ctl_reg_out_hi~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~7 , z80_|execute_|ctl_reg_out_hi~7, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal2~2 , z80_|pla_decode_|Equal2~2, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de1~0 , z80_|reg_control_|bank_hl_de1~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de1 , z80_|reg_control_|bank_hl_de1, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de2~6 , z80_|reg_control_|reg_sel_de2~6, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de2~5 , z80_|reg_control_|reg_sel_de2~5, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_hl~0 , z80_|reg_control_|reg_sel_hl~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_56 , z80_|reg_file_|SYNTHESIZED_WIRE_56, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de~0 , z80_|reg_control_|reg_sel_de~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_49 , z80_|reg_file_|SYNTHESIZED_WIRE_49, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[7] , z80_|reg_file_|b2v_latch_de_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_48 , z80_|reg_file_|SYNTHESIZED_WIRE_48, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de2~0 , z80_|reg_control_|bank_hl_de2~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de2 , z80_|reg_control_|bank_hl_de2, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de2~4 , z80_|reg_control_|reg_sel_de2~4, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_45 , z80_|reg_file_|SYNTHESIZED_WIRE_45, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[7] , z80_|reg_file_|b2v_latch_de2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_44 , z80_|reg_file_|SYNTHESIZED_WIRE_44, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~22 , z80_|reg_file_|gdfx_temp1[7]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_57 , z80_|reg_file_|SYNTHESIZED_WIRE_57, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[7] , z80_|reg_file_|b2v_latch_hl_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_hl2~0 , z80_|reg_control_|reg_sel_hl2~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_53 , z80_|reg_file_|SYNTHESIZED_WIRE_53, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] , z80_|reg_file_|b2v_latch_hl2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4 , z80_|reg_file_|b2v_latch_hl2_hi|db[7]~4, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~23 , z80_|reg_file_|gdfx_temp1[7]~23, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_33 , z80_|reg_file_|SYNTHESIZED_WIRE_33, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[7] , z80_|reg_file_|b2v_latch_af_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 , z80_|reg_file_|SYNTHESIZED_WIRE_69~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 , z80_|reg_file_|SYNTHESIZED_WIRE_37~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] , z80_|reg_file_|b2v_latch_bc2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 , z80_|reg_file_|SYNTHESIZED_WIRE_41~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[7] , z80_|reg_file_|b2v_latch_bc_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~24 , z80_|reg_file_|gdfx_temp1[7]~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~4 , z80_|execute_|ctl_reg_in_hi~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~9 , z80_|execute_|ctl_reg_in_hi~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~10 , z80_|execute_|ctl_reg_in_hi~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 , z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~7 , z80_|execute_|ctl_reg_in_hi~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~11 , z80_|execute_|ctl_reg_in_hi~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~12 , z80_|execute_|ctl_reg_in_hi~12, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_29 , z80_|reg_file_|SYNTHESIZED_WIRE_29, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[7] , z80_|reg_file_|b2v_latch_af2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~26 , z80_|reg_file_|gdfx_temp1[7]~26, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69 , z80_|reg_file_|SYNTHESIZED_WIRE_69, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[7] , z80_|reg_file_|b2v_latch_iy_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 , z80_|reg_file_|SYNTHESIZED_WIRE_65~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[7] , z80_|reg_file_|b2v_latch_ix_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 , z80_|reg_file_|SYNTHESIZED_WIRE_64~0, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~25 , z80_|reg_file_|gdfx_temp1[7]~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~32 , z80_|execute_|ctl_bus_inc_oe~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~1 , z80_|execute_|ctl_reg_sys_we~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~2 , z80_|execute_|ctl_reg_sys_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~0 , z80_|execute_|ctl_reg_sys_we_lo~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~1 , z80_|execute_|ctl_reg_sys_we_lo~1, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_hi~0 , z80_|reg_control_|reg_sys_we_hi~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~31 , z80_|execute_|ctl_bus_inc_oe~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo~39 , z80_|execute_|ctl_reg_sys_hilo~39, spectrum, 1 -instance = comp, \z80_|execute_|setM1~37 , z80_|execute_|setM1~37, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~11 , z80_|execute_|fMRead~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~33 , z80_|execute_|ctl_bus_inc_oe~33, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_hi , z80_|reg_control_|reg_sys_we_hi, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_81 , z80_|reg_file_|SYNTHESIZED_WIRE_81, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[7] , z80_|reg_file_|b2v_latch_wz_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 , z80_|reg_file_|SYNTHESIZED_WIRE_77~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[7] , z80_|reg_file_|b2v_latch_sp_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~27 , z80_|reg_file_|gdfx_temp1[7]~27, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~28 , z80_|reg_file_|gdfx_temp1[7]~28, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_32 , z80_|reg_file_|SYNTHESIZED_WIRE_32, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~29 , z80_|reg_file_|gdfx_temp1[7]~29, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~30 , z80_|reg_file_|gdfx_temp1[7]~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~12 , z80_|execute_|ctl_sw_2d~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~14 , z80_|execute_|ctl_sw_2d~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~10 , z80_|execute_|ctl_sw_2d~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~11 , z80_|execute_|ctl_sw_2d~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~6 , z80_|execute_|ctl_bus_db_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~5 , z80_|execute_|ctl_sw_2d~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~16 , z80_|execute_|ctl_alu_shift_oe~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~44 , z80_|execute_|ctl_alu_shift_oe~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~6 , z80_|execute_|ctl_sw_2d~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~7 , z80_|execute_|ctl_sw_2d~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~8 , z80_|execute_|ctl_sw_2d~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~26 , z80_|execute_|ctl_mRead~26, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~7 , z80_|execute_|fMRead~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~9 , z80_|execute_|ctl_mWrite~9, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~6 , z80_|execute_|fMRead~6, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~8 , z80_|execute_|fMRead~8, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~9 , z80_|execute_|fMRead~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~9 , z80_|execute_|ctl_sw_2d~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~13 , z80_|execute_|ctl_sw_2d~13, spectrum, 1 -instance = comp, \z80_|alu_|db[7]~19 , z80_|alu_|db[7]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~12 , z80_|execute_|ctl_alu_oe~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~11 , z80_|execute_|ctl_alu_oe~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~13 , z80_|execute_|ctl_alu_oe~13, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~5 , z80_|reg_control_|reg_sys_we_lo~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~7 , z80_|execute_|ctl_alu_oe~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~8 , z80_|execute_|ctl_mWrite~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~5 , z80_|execute_|ctl_bus_db_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~8 , z80_|execute_|ctl_alu_oe~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~14 , z80_|execute_|ctl_alu_oe~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~3 , z80_|execute_|ctl_alu_core_R~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~4 , z80_|execute_|ctl_alu_core_R~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~7 , z80_|execute_|ctl_alu_op1_sel_bus~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~8 , z80_|execute_|ctl_alu_op1_sel_bus~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~9 , z80_|execute_|ctl_alu_op1_sel_bus~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~10 , z80_|execute_|ctl_alu_op1_sel_bus~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 , z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~38 , z80_|execute_|ctl_alu_shift_oe~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~15 , z80_|execute_|ctl_alu_op1_sel_bus~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~4 , z80_|execute_|ctl_alu_op1_sel_bus~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~31 , z80_|execute_|ctl_alu_shift_oe~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~30 , z80_|execute_|ctl_alu_shift_oe~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~32 , z80_|execute_|ctl_alu_shift_oe~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~11 , z80_|execute_|ctl_alu_op1_sel_bus~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~5 , z80_|execute_|ctl_alu_op1_sel_bus~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~6 , z80_|execute_|ctl_alu_op1_sel_bus~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~12 , z80_|execute_|ctl_alu_op1_sel_bus~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~13 , z80_|execute_|ctl_alu_op1_sel_bus~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~14 , z80_|execute_|ctl_alu_op1_sel_bus~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~5 , z80_|execute_|ctl_alu_op1_sel_zero~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero , z80_|execute_|ctl_alu_op1_sel_zero, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[3] , z80_|alu_|b2v_op1_latch_mux_high|Q[3], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|ena~0 , z80_|alu_|b2v_op1_latch_mux_high|ena~0, spectrum, 1 -instance = comp, \z80_|alu_|op1_high[3] , z80_|alu_|op1_high[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[3] , z80_|reg_file_|b2v_latch_af_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] , z80_|reg_file_|b2v_latch_hl2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5 , z80_|reg_file_|b2v_latch_hl2_hi|db[3]~5, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[3] , z80_|reg_file_|b2v_latch_hl_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[3] , z80_|reg_file_|b2v_latch_de_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[3] , z80_|reg_file_|b2v_latch_de2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~49 , z80_|reg_file_|gdfx_temp1[3]~49, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~50 , z80_|reg_file_|gdfx_temp1[3]~50, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[3] , z80_|reg_file_|b2v_latch_iy_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[3] , z80_|reg_file_|b2v_latch_ix_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~52 , z80_|reg_file_|gdfx_temp1[3]~52, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] , z80_|reg_file_|b2v_latch_bc2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[3] , z80_|reg_file_|b2v_latch_bc_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~51 , z80_|reg_file_|gdfx_temp1[3]~51, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[3] , z80_|reg_file_|b2v_latch_sp_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[3] , z80_|reg_file_|b2v_latch_wz_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~54 , z80_|reg_file_|gdfx_temp1[3]~54, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[3] , z80_|reg_file_|b2v_latch_af2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~53 , z80_|reg_file_|gdfx_temp1[3]~53, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~55 , z80_|reg_file_|gdfx_temp1[3]~55, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~56 , z80_|reg_file_|gdfx_temp1[3]~56, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~18 , z80_|execute_|ctl_reg_sel_pc~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~15 , z80_|execute_|ctl_reg_sel_pc~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~16 , z80_|execute_|ctl_reg_sel_pc~16, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~4 , z80_|execute_|fMRead~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~17 , z80_|execute_|ctl_reg_sel_pc~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~19 , z80_|execute_|ctl_reg_sel_pc~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~18 , z80_|execute_|ctl_reg_sel_wz~18, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~3 , z80_|reg_control_|reg_sel_pc~3, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc , z80_|reg_control_|reg_sel_pc, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_72 , z80_|reg_file_|SYNTHESIZED_WIRE_72, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_ir~0 , z80_|execute_|ctl_reg_sel_ir~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_ir~1 , z80_|execute_|ctl_reg_sel_ir~1, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_60 , z80_|reg_file_|SYNTHESIZED_WIRE_60, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~6 , z80_|reg_control_|reg_sys_we_lo~6, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo , z80_|reg_control_|reg_sys_we_lo, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~5 , z80_|execute_|ctl_alu_oe~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~0 , z80_|execute_|ctl_sw_4d~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~1 , z80_|execute_|ctl_sw_4d~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~4 , z80_|execute_|ctl_sw_4d~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~3 , z80_|execute_|ctl_sw_4d~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~2 , z80_|execute_|ctl_sw_4d~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~5 , z80_|execute_|ctl_sw_4d~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~6 , z80_|execute_|ctl_sw_4d~6, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sw_4d_hi~0 , z80_|reg_control_|reg_sw_4d_hi~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_61 , z80_|reg_file_|SYNTHESIZED_WIRE_61, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[3] , z80_|reg_file_|b2v_latch_ir_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[3]~13 , z80_|reg_file_|db_hi_as[3]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_73 , z80_|reg_file_|SYNTHESIZED_WIRE_73, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[3] , z80_|reg_file_|b2v_latch_pc_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[3]~14 , z80_|reg_file_|db_hi_as[3]~14, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[11] , z80_|address_latch_|abusz[11], spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~9 , z80_|execute_|ctl_al_we~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~10 , z80_|execute_|ctl_al_we~10, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[7] , z80_|address_latch_|abusz[7], spectrum, 1 instance = comp, \z80_|execute_|ctl_apin_mux~1 , z80_|execute_|ctl_apin_mux~1, spectrum, 1 instance = comp, \z80_|execute_|ctl_al_we~6 , z80_|execute_|ctl_al_we~6, spectrum, 1 instance = comp, \z80_|execute_|ctl_al_we~7 , z80_|execute_|ctl_al_we~7, spectrum, 1 instance = comp, \z80_|execute_|ctl_al_we~8 , z80_|execute_|ctl_al_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~10 , z80_|execute_|ctl_alu_oe~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~9 , z80_|execute_|ctl_al_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~10 , z80_|execute_|ctl_al_we~10, spectrum, 1 instance = comp, \z80_|execute_|ctl_al_we~11 , z80_|execute_|ctl_al_we~11, spectrum, 1 instance = comp, \z80_|execute_|ctl_al_we~12 , z80_|execute_|ctl_al_we~12, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[11] , z80_|address_latch_|Q[11], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[11] , z80_|address_latch_|b2v_inst_inc_dec|address[11], spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~78 , z80_|execute_|ctl_inc_cy~78, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~42 , z80_|execute_|ctl_bus_inc_oe~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~39 , z80_|execute_|ctl_bus_inc_oe~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~40 , z80_|execute_|ctl_bus_inc_oe~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~47 , z80_|execute_|ctl_bus_inc_oe~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~38 , z80_|execute_|ctl_bus_inc_oe~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~37 , z80_|execute_|ctl_bus_inc_oe~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~46 , z80_|execute_|ctl_bus_inc_oe~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~36 , z80_|execute_|ctl_bus_inc_oe~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~41 , z80_|execute_|ctl_bus_inc_oe~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~43 , z80_|execute_|ctl_bus_inc_oe~43, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[0]~2 , z80_|reg_file_|db_hi_as[0]~2, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[3]~15 , z80_|reg_file_|db_hi_as[3]~15, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~57 , z80_|reg_file_|gdfx_temp1[3]~57, spectrum, 1 -instance = comp, \z80_|alu_|db[3]~13 , z80_|alu_|db[3]~13, spectrum, 1 -instance = comp, \z80_|execute_|setM1~49 , z80_|execute_|setM1~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_oe~2 , z80_|execute_|ctl_flags_oe~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_35 , z80_|alu_flags_|SYNTHESIZED_WIRE_35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~5 , z80_|execute_|ctl_flags_sz_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~6 , z80_|execute_|ctl_flags_sz_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~7 , z80_|execute_|ctl_flags_sz_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~10 , z80_|execute_|ctl_flags_xy_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~13 , z80_|execute_|ctl_flags_xy_we~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~14 , z80_|execute_|ctl_flags_xy_we~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~15 , z80_|execute_|ctl_flags_xy_we~15, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_xf , z80_|alu_flags_|flags_xf, spectrum, 1 -instance = comp, \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 , z80_|alu_control_|SYNTHESIZED_WIRE_2~0, spectrum, 1 -instance = comp, \z80_|alu_control_|db[3]~33 , z80_|alu_control_|db[3]~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~9 , z80_|execute_|ctl_reg_out_lo~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~41 , z80_|execute_|ctl_reg_sys_hilo[1]~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~35 , z80_|execute_|ctl_reg_sys_hilo[0]~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~42 , z80_|execute_|ctl_reg_sys_hilo[0]~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~36 , z80_|execute_|ctl_reg_sys_hilo[0]~36, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_62 , z80_|reg_file_|SYNTHESIZED_WIRE_62, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_74 , z80_|reg_file_|SYNTHESIZED_WIRE_74, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~2 , z80_|reg_file_|db_lo_as[0]~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_75 , z80_|reg_file_|SYNTHESIZED_WIRE_75, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[3] , z80_|reg_file_|b2v_latch_pc_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[3]~10 , z80_|reg_file_|db_lo_as[3]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_63 , z80_|reg_file_|SYNTHESIZED_WIRE_63, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[3] , z80_|reg_file_|b2v_latch_ir_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[3]~11 , z80_|reg_file_|db_lo_as[3]~11, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[7] , z80_|address_latch_|Q[7], spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~6 , z80_|execute_|ctl_inc_dec~6, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~0 , z80_|execute_|fIOWrite~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~8 , z80_|execute_|ctl_inc_dec~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~9 , z80_|execute_|ctl_inc_dec~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~10 , z80_|execute_|ctl_inc_dec~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~7 , z80_|execute_|ctl_inc_dec~7, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[2] , z80_|reg_file_|b2v_latch_ir_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_54 , z80_|reg_file_|SYNTHESIZED_WIRE_54, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_58 , z80_|reg_file_|SYNTHESIZED_WIRE_58, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_55 , z80_|reg_file_|SYNTHESIZED_WIRE_55, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] , z80_|reg_file_|b2v_latch_hl2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_59 , z80_|reg_file_|SYNTHESIZED_WIRE_59, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[2] , z80_|reg_file_|b2v_latch_hl_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~34 , z80_|reg_file_|gdfx_temp0[2]~34, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_51 , z80_|reg_file_|SYNTHESIZED_WIRE_51, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[2] , z80_|reg_file_|b2v_latch_de_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de2~4 , z80_|reg_control_|reg_sel_de2~4, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_46 , z80_|reg_file_|SYNTHESIZED_WIRE_46, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_47 , z80_|reg_file_|SYNTHESIZED_WIRE_47, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[2] , z80_|reg_file_|b2v_latch_de2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~33 , z80_|reg_file_|gdfx_temp0[2]~33, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 , z80_|reg_file_|SYNTHESIZED_WIRE_71~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 , z80_|reg_file_|SYNTHESIZED_WIRE_43~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[2] , z80_|reg_file_|b2v_latch_bc_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 , z80_|reg_file_|SYNTHESIZED_WIRE_39~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] , z80_|reg_file_|b2v_latch_bc2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~36 , z80_|reg_file_|gdfx_temp0[2]~36, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_83 , z80_|reg_file_|SYNTHESIZED_WIRE_83, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[2] , z80_|reg_file_|b2v_latch_wz_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~37 , z80_|reg_file_|gdfx_temp0[2]~37, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 , z80_|reg_file_|SYNTHESIZED_WIRE_79~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[2] , z80_|reg_file_|b2v_latch_sp_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~39 , z80_|reg_file_|gdfx_temp0[2]~39, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_iy~2 , z80_|reg_control_|reg_sel_iy~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70 , z80_|reg_file_|SYNTHESIZED_WIRE_70, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 , z80_|reg_file_|SYNTHESIZED_WIRE_67~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[2] , z80_|reg_file_|b2v_latch_ix_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71 , z80_|reg_file_|SYNTHESIZED_WIRE_71, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[2] , z80_|reg_file_|b2v_latch_iy_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~38 , z80_|reg_file_|gdfx_temp0[2]~38, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_31 , z80_|reg_file_|SYNTHESIZED_WIRE_31, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[2] , z80_|reg_file_|b2v_latch_af2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_35 , z80_|reg_file_|SYNTHESIZED_WIRE_35, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[2] , z80_|reg_file_|b2v_latch_af_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~35 , z80_|reg_file_|gdfx_temp0[2]~35, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~40 , z80_|reg_file_|gdfx_temp0[2]~40, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~41 , z80_|reg_file_|gdfx_temp0[2]~41, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~42 , z80_|reg_file_|gdfx_temp0[2]~42, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[2] , z80_|reg_file_|b2v_latch_pc_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[2]~7 , z80_|reg_file_|db_lo_as[2]~7, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[2]~8 , z80_|reg_file_|db_lo_as[2]~8, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[0] , z80_|reg_file_|b2v_latch_ir_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[0] , z80_|reg_file_|b2v_latch_de_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[0] , z80_|reg_file_|b2v_latch_de2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~10 , z80_|reg_file_|gdfx_temp0[0]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] , z80_|reg_file_|b2v_latch_hl2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 , z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[0] , z80_|reg_file_|b2v_latch_hl_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~11 , z80_|reg_file_|gdfx_temp0[0]~11, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[0] , z80_|reg_file_|b2v_latch_sp_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[0] , z80_|reg_file_|b2v_latch_iy_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~15 , z80_|reg_file_|gdfx_temp0[0]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[0] , z80_|reg_file_|b2v_latch_wz_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[0] , z80_|reg_file_|b2v_latch_bc_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[0] , z80_|reg_file_|b2v_latch_ix_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~14 , z80_|reg_file_|gdfx_temp0[0]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~16 , z80_|reg_file_|gdfx_temp0[0]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] , z80_|reg_file_|b2v_latch_bc2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~12 , z80_|reg_file_|gdfx_temp0[0]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[0] , z80_|reg_file_|b2v_latch_af2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[0] , z80_|reg_file_|b2v_latch_af_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~13 , z80_|reg_file_|gdfx_temp0[0]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~17 , z80_|reg_file_|gdfx_temp0[0]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~22 , z80_|reg_file_|gdfx_temp0[0]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[0] , z80_|reg_file_|b2v_latch_pc_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~0 , z80_|reg_file_|db_lo_as[0]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~1 , z80_|reg_file_|db_lo_as[0]~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~72 , z80_|execute_|ctl_inc_cy~72, spectrum, 1 instance = comp, \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, spectrum, 1 -instance = comp, \ula_|video_|Add0~0 , ula_|video_|Add0~0, spectrum, 1 instance = comp, \ula_|video_|Add0~14 , ula_|video_|Add0~14, spectrum, 1 instance = comp, \ula_|video_|Add0~16 , ula_|video_|Add0~16, spectrum, 1 instance = comp, \ula_|video_|vga_hc~2 , ula_|video_|vga_hc~2, spectrum, 1 @@ -1016,20 +972,22 @@ instance = comp, \ula_|video_|vga_hc[8] , ula_|video_|vga_hc[8], spectrum, 1 instance = comp, \ula_|video_|Add0~18 , ula_|video_|Add0~18, spectrum, 1 instance = comp, \ula_|video_|vga_hc~1 , ula_|video_|vga_hc~1, spectrum, 1 instance = comp, \ula_|video_|vga_hc[9] , ula_|video_|vga_hc[9], spectrum, 1 -instance = comp, \ula_|video_|Equal0~0 , ula_|video_|Equal0~0, spectrum, 1 -instance = comp, \ula_|video_|Equal0~1 , ula_|video_|Equal0~1, spectrum, 1 -instance = comp, \ula_|video_|Equal1~0 , ula_|video_|Equal1~0, spectrum, 1 +instance = comp, \ula_|video_|Add0~0 , ula_|video_|Add0~0, spectrum, 1 instance = comp, \ula_|video_|vga_hc~3 , ula_|video_|vga_hc~3, spectrum, 1 instance = comp, \ula_|video_|vga_hc[0] , ula_|video_|vga_hc[0], spectrum, 1 instance = comp, \ula_|video_|Add0~2 , ula_|video_|Add0~2, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[1]~feeder , ula_|video_|vga_hc[1]~feeder, spectrum, 1 instance = comp, \ula_|video_|vga_hc[1] , ula_|video_|vga_hc[1], spectrum, 1 instance = comp, \ula_|video_|Add0~4 , ula_|video_|Add0~4, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[2]~feeder , ula_|video_|vga_hc[2]~feeder, spectrum, 1 instance = comp, \ula_|video_|vga_hc[2] , ula_|video_|vga_hc[2], spectrum, 1 instance = comp, \ula_|video_|Add0~6 , ula_|video_|Add0~6, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[3]~feeder , ula_|video_|vga_hc[3]~feeder, spectrum, 1 instance = comp, \ula_|video_|vga_hc[3] , ula_|video_|vga_hc[3], spectrum, 1 instance = comp, \ula_|video_|Add0~8 , ula_|video_|Add0~8, spectrum, 1 instance = comp, \ula_|video_|vga_hc[4] , ula_|video_|vga_hc[4], spectrum, 1 +instance = comp, \ula_|video_|Equal0~0 , ula_|video_|Equal0~0, spectrum, 1 +instance = comp, \ula_|video_|Equal0~1 , ula_|video_|Equal0~1, spectrum, 1 +instance = comp, \ula_|video_|Equal1~0 , ula_|video_|Equal1~0, spectrum, 1 instance = comp, \ula_|video_|Add0~10 , ula_|video_|Add0~10, spectrum, 1 instance = comp, \ula_|video_|vga_hc~0 , ula_|video_|vga_hc~0, spectrum, 1 instance = comp, \ula_|video_|vga_hc[5] , ula_|video_|vga_hc[5], spectrum, 1 @@ -1037,8 +995,6 @@ instance = comp, \ula_|video_|Add0~12 , ula_|video_|Add0~12, spectrum, 1 instance = comp, \ula_|video_|vga_hc[6] , ula_|video_|vga_hc[6], spectrum, 1 instance = comp, \ula_|video_|vga_hc[7] , ula_|video_|vga_hc[7], spectrum, 1 instance = comp, \ula_|video_|Add1~0 , ula_|video_|Add1~0, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[0]~0 , ula_|video_|vga_vc[0]~0, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[0] , ula_|video_|vga_vc[0], spectrum, 1 instance = comp, \ula_|video_|Add1~2 , ula_|video_|Add1~2, spectrum, 1 instance = comp, \ula_|video_|Add1~4 , ula_|video_|Add1~4, spectrum, 1 instance = comp, \ula_|video_|vga_vc[2]~2 , ula_|video_|vga_vc[2]~2, spectrum, 1 @@ -1061,22 +1017,24 @@ instance = comp, \ula_|video_|vga_vc[7] , ula_|video_|vga_vc[7], spectrum, 1 instance = comp, \ula_|video_|Add1~16 , ula_|video_|Add1~16, spectrum, 1 instance = comp, \ula_|video_|vga_vc[8]~7 , ula_|video_|vga_vc[8]~7, spectrum, 1 instance = comp, \ula_|video_|vga_vc[8] , ula_|video_|vga_vc[8], spectrum, 1 -instance = comp, \ula_|video_|Equal2~0 , ula_|video_|Equal2~0, spectrum, 1 instance = comp, \ula_|video_|Add1~18 , ula_|video_|Add1~18, spectrum, 1 instance = comp, \ula_|video_|vga_vc[9]~9 , ula_|video_|vga_vc[9]~9, spectrum, 1 instance = comp, \ula_|video_|vga_vc[9] , ula_|video_|vga_vc[9], spectrum, 1 +instance = comp, \ula_|video_|Equal2~0 , ula_|video_|Equal2~0, spectrum, 1 instance = comp, \ula_|video_|Equal3~0 , ula_|video_|Equal3~0, spectrum, 1 instance = comp, \ula_|video_|Equal3~1 , ula_|video_|Equal3~1, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[0]~0 , ula_|video_|vga_vc[0]~0, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[0] , ula_|video_|vga_vc[0], spectrum, 1 instance = comp, \ula_|video_|vga_vc[1]~1 , ula_|video_|vga_vc[1]~1, spectrum, 1 instance = comp, \ula_|video_|vga_vc[1] , ula_|video_|vga_vc[1], spectrum, 1 instance = comp, \SW[1]~input , SW[1]~input, spectrum, 1 instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 , z80_|interrupts_|SYNTHESIZED_WIRE_13~0, spectrum, 1 instance = comp, \z80_|pla_decode_|Equal79~0 , z80_|pla_decode_|Equal79~0, spectrum, 1 -instance = comp, \z80_|interrupts_|iff1~0 , z80_|interrupts_|iff1~0, spectrum, 1 instance = comp, \z80_|interrupts_|DFFE_instIFF2~0 , z80_|interrupts_|DFFE_instIFF2~0, spectrum, 1 instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12 , z80_|interrupts_|SYNTHESIZED_WIRE_12, spectrum, 1 instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl , z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 instance = comp, \z80_|interrupts_|DFFE_instIFF2 , z80_|interrupts_|DFFE_instIFF2, spectrum, 1 +instance = comp, \z80_|interrupts_|iff1~0 , z80_|interrupts_|iff1~0, spectrum, 1 instance = comp, \z80_|interrupts_|iff1~1 , z80_|interrupts_|iff1~1, spectrum, 1 instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_15 , z80_|interrupts_|SYNTHESIZED_WIRE_15, spectrum, 1 instance = comp, \z80_|interrupts_|iff1 , z80_|interrupts_|iff1, spectrum, 1 @@ -1084,868 +1042,657 @@ instance = comp, \ula_|video_|Equal2~1 , ula_|video_|Equal2~1, spectrum, 1 instance = comp, \ula_|video_|Equal2~2 , ula_|video_|Equal2~2, spectrum, 1 instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_13 , z80_|interrupts_|SYNTHESIZED_WIRE_13, spectrum, 1 instance = comp, \z80_|interrupts_|int_armed , z80_|interrupts_|int_armed, spectrum, 1 -instance = comp, \z80_|interrupts_|DFFE_inst44~feeder , z80_|interrupts_|DFFE_inst44~feeder, spectrum, 1 instance = comp, \z80_|interrupts_|DFFE_inst44 , z80_|interrupts_|DFFE_inst44, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~30 , z80_|execute_|pc_inc_hold~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~53 , z80_|execute_|ctl_inc_cy~53, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~51 , z80_|execute_|ctl_inc_cy~51, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~49 , z80_|execute_|ctl_inc_cy~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~50 , z80_|execute_|ctl_inc_cy~50, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~52 , z80_|execute_|ctl_inc_cy~52, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~54 , z80_|execute_|ctl_inc_cy~54, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 , z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~22 , z80_|execute_|pc_inc_hold~22, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~24 , z80_|execute_|pc_inc_hold~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~23 , z80_|execute_|pc_inc_hold~23, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~25 , z80_|execute_|pc_inc_hold~25, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~20 , z80_|execute_|pc_inc_hold~20, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~41 , z80_|execute_|pc_inc_hold~41, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~21 , z80_|execute_|pc_inc_hold~21, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~26 , z80_|execute_|pc_inc_hold~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~44 , z80_|execute_|ctl_inc_cy~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~45 , z80_|execute_|ctl_inc_cy~45, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~46 , z80_|execute_|ctl_inc_cy~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~43 , z80_|execute_|ctl_inc_cy~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~48 , z80_|execute_|ctl_inc_cy~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~55 , z80_|execute_|ctl_inc_cy~55, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 , z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~42 , z80_|execute_|pc_inc_hold~42, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~27 , z80_|execute_|pc_inc_hold~27, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~28 , z80_|execute_|pc_inc_hold~28, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~29 , z80_|execute_|pc_inc_hold~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~40 , z80_|execute_|ctl_inc_cy~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~41 , z80_|execute_|ctl_inc_cy~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~83 , z80_|execute_|ctl_inc_cy~83, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~42 , z80_|execute_|ctl_inc_cy~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~62 , z80_|execute_|ctl_inc_cy~62, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~63 , z80_|execute_|ctl_inc_cy~63, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~31 , z80_|execute_|pc_inc_hold~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~64 , z80_|execute_|ctl_inc_cy~64, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~58 , z80_|execute_|ctl_inc_cy~58, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~59 , z80_|execute_|ctl_inc_cy~59, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~60 , z80_|execute_|ctl_inc_cy~60, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~61 , z80_|execute_|ctl_inc_cy~61, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~32 , z80_|execute_|pc_inc_hold~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~84 , z80_|execute_|ctl_inc_cy~84, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~65 , z80_|execute_|ctl_inc_cy~65, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~56 , z80_|execute_|ctl_inc_cy~56, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~57 , z80_|execute_|ctl_inc_cy~57, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~38 , z80_|execute_|pc_inc_hold~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~91 , z80_|execute_|ctl_inc_cy~91, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~45 , z80_|execute_|pc_inc_hold~45, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~44 , z80_|execute_|pc_inc_hold~44, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~46 , z80_|execute_|pc_inc_hold~46, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~37 , z80_|execute_|pc_inc_hold~37, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~50 , z80_|execute_|pc_inc_hold~50, spectrum, 1 instance = comp, \z80_|execute_|pc_inc_hold~33 , z80_|execute_|pc_inc_hold~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 , z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~31 , z80_|execute_|pc_inc_hold~31, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~32 , z80_|execute_|pc_inc_hold~32, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~34 , z80_|execute_|pc_inc_hold~34, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~51 , z80_|execute_|pc_inc_hold~51, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~30 , z80_|execute_|pc_inc_hold~30, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~52 , z80_|execute_|pc_inc_hold~52, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~35 , z80_|execute_|pc_inc_hold~35, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~36 , z80_|execute_|pc_inc_hold~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~44 , z80_|execute_|ctl_inc_cy~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 , z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~45 , z80_|execute_|ctl_inc_cy~45, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~43 , z80_|execute_|pc_inc_hold~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~71 , z80_|execute_|ctl_inc_cy~71, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~73 , z80_|execute_|ctl_inc_cy~73, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~46 , z80_|execute_|ctl_inc_cy~46, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~53 , z80_|execute_|pc_inc_hold~53, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~39 , z80_|execute_|pc_inc_hold~39, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~47 , z80_|execute_|pc_inc_hold~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~74 , z80_|execute_|ctl_inc_cy~74, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~78 , z80_|execute_|ctl_inc_cy~78, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~79 , z80_|execute_|ctl_inc_cy~79, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~80 , z80_|execute_|ctl_inc_cy~80, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~81 , z80_|execute_|ctl_inc_cy~81, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~82 , z80_|execute_|ctl_inc_cy~82, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~83 , z80_|execute_|ctl_inc_cy~83, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~84 , z80_|execute_|ctl_inc_cy~84, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~42 , z80_|execute_|pc_inc_hold~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~90 , z80_|execute_|ctl_inc_cy~90, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~41 , z80_|execute_|pc_inc_hold~41, spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_cy~66 , z80_|execute_|ctl_inc_cy~66, spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_cy~67 , z80_|execute_|ctl_inc_cy~67, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~75 , z80_|execute_|ctl_inc_cy~75, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~79 , z80_|execute_|ctl_inc_cy~79, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~72 , z80_|execute_|ctl_inc_cy~72, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~73 , z80_|execute_|ctl_inc_cy~73, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 , z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~34 , z80_|execute_|pc_inc_hold~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~71 , z80_|execute_|ctl_inc_cy~71, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~74 , z80_|execute_|ctl_inc_cy~74, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~80 , z80_|execute_|ctl_inc_cy~80, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~9 , z80_|execute_|ctl_inc_dec~9, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[0] , z80_|reg_file_|b2v_latch_ir_lo|latch[0], spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~41 , z80_|execute_|ctl_reg_gp_hilo[0]~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~23 , z80_|execute_|ctl_reg_gp_hilo[0]~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~53 , z80_|execute_|ctl_reg_gp_hilo[0]~53, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~40 , z80_|execute_|ctl_reg_gp_hilo[0]~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 , z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~54 , z80_|execute_|ctl_reg_gp_hilo[0]~54, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~44 , z80_|execute_|ctl_reg_gp_hilo[0]~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~20 , z80_|execute_|ctl_reg_gp_hilo[0]~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~42 , z80_|execute_|ctl_reg_gp_hilo[0]~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~43 , z80_|execute_|ctl_reg_gp_hilo[0]~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~45 , z80_|execute_|ctl_reg_gp_hilo[0]~45, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~46 , z80_|execute_|ctl_reg_gp_hilo[0]~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~39 , z80_|execute_|ctl_reg_gp_hilo[0]~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~47 , z80_|execute_|ctl_reg_gp_hilo[0]~47, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_47 , z80_|reg_file_|SYNTHESIZED_WIRE_47, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[0] , z80_|reg_file_|b2v_latch_de2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|db[0]~0 , z80_|reg_file_|b2v_latch_de2_lo|db[0]~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_59 , z80_|reg_file_|SYNTHESIZED_WIRE_59, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[0] , z80_|reg_file_|b2v_latch_hl_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_54 , z80_|reg_file_|SYNTHESIZED_WIRE_54, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_55 , z80_|reg_file_|SYNTHESIZED_WIRE_55, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] , z80_|reg_file_|b2v_latch_hl2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_58 , z80_|reg_file_|SYNTHESIZED_WIRE_58, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~10 , z80_|reg_file_|gdfx_temp0[0]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_51 , z80_|reg_file_|SYNTHESIZED_WIRE_51, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[0] , z80_|reg_file_|b2v_latch_de_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_50 , z80_|reg_file_|SYNTHESIZED_WIRE_50, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~11 , z80_|reg_file_|gdfx_temp0[0]~11, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 , z80_|reg_file_|SYNTHESIZED_WIRE_70~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 , z80_|reg_file_|SYNTHESIZED_WIRE_38~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~31 , z80_|execute_|ctl_alu_op_low~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 , z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~28 , z80_|execute_|ctl_alu_op_low~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~29 , z80_|execute_|ctl_alu_op_low~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~23 , z80_|execute_|ctl_alu_op_low~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~24 , z80_|execute_|ctl_alu_op_low~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~6 , z80_|execute_|ctl_alu_op2_sel_bus~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~26 , z80_|execute_|ctl_alu_op_low~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~25 , z80_|execute_|ctl_alu_op_low~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~39 , z80_|execute_|ctl_alu_op_low~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~27 , z80_|execute_|ctl_alu_op_low~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~30 , z80_|execute_|ctl_alu_op_low~30, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~10 , z80_|execute_|ctl_mWrite~10, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal61~2 , z80_|pla_decode_|Equal61~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~5, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~2 , z80_|execute_|ctl_flags_cf_cpl~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~3 , z80_|execute_|ctl_flags_cf_cpl~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~6 , z80_|execute_|ctl_alu_core_S~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~7 , z80_|execute_|ctl_alu_core_S~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~4 , z80_|execute_|ctl_alu_sel_op2_neg~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~13 , z80_|execute_|ctl_alu_sel_op2_neg~13, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~4, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~8, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~11 , z80_|execute_|ctl_state_alu~11, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal72~2 , z80_|pla_decode_|Equal72~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~0 , z80_|execute_|ctl_flags_nf_we~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal73~2 , z80_|pla_decode_|Equal73~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~2 , z80_|alu_flags_|DFFE_inst_latch_nf~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~3 , z80_|alu_flags_|DFFE_inst_latch_nf~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~4 , z80_|alu_flags_|DFFE_inst_latch_nf~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~1 , z80_|execute_|ctl_flags_nf_we~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~38 , z80_|execute_|ctl_alu_op_low~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~32 , z80_|execute_|ctl_alu_op_low~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~4 , z80_|execute_|ctl_flags_cf_cpl~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~10 , z80_|execute_|ctl_flags_use_cf2~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~11 , z80_|execute_|ctl_flags_use_cf2~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~8 , z80_|execute_|ctl_flags_use_cf2~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~9 , z80_|execute_|ctl_flags_use_cf2~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~12 , z80_|execute_|ctl_flags_use_cf2~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~2 , z80_|execute_|ctl_flags_cf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_we~2 , z80_|execute_|ctl_flags_hf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~3 , z80_|execute_|ctl_flags_cf_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~4 , z80_|execute_|ctl_flags_cf_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~5 , z80_|execute_|ctl_flags_cf_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~6 , z80_|execute_|ctl_flags_cf_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~2 , z80_|execute_|ctl_alu_core_R~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~9 , z80_|alu_flags_|DFFE_inst_latch_nf~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~8 , z80_|execute_|ctl_alu_core_S~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R , z80_|execute_|ctl_alu_core_R, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~33 , z80_|execute_|ctl_alu_op_low~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~34 , z80_|execute_|ctl_alu_op_low~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~35 , z80_|execute_|ctl_alu_op_low~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low , z80_|execute_|ctl_alu_op_low, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_low , z80_|execute_|ctl_alu_op1_sel_low, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~12 , z80_|execute_|ctl_alu_bs_oe~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~17 , z80_|execute_|ctl_alu_shift_oe~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~45 , z80_|execute_|ctl_alu_shift_oe~45, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~18 , z80_|execute_|ctl_alu_shift_oe~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~19 , z80_|execute_|ctl_alu_shift_oe~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~20 , z80_|execute_|ctl_alu_shift_oe~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~21 , z80_|execute_|ctl_alu_shift_oe~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~22 , z80_|execute_|ctl_alu_shift_oe~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~9 , z80_|execute_|ctl_alu_bs_oe~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~10 , z80_|execute_|ctl_alu_bs_oe~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~24 , z80_|execute_|ctl_alu_shift_oe~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~29 , z80_|execute_|ctl_alu_shift_oe~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~8 , z80_|execute_|ctl_alu_bs_oe~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe , z80_|execute_|ctl_alu_bs_oe, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~23 , z80_|execute_|ctl_alu_shift_oe~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~33 , z80_|execute_|ctl_alu_shift_oe~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~46 , z80_|execute_|ctl_alu_shift_oe~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~37 , z80_|execute_|ctl_alu_shift_oe~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~39 , z80_|execute_|ctl_alu_shift_oe~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~40 , z80_|execute_|ctl_alu_shift_oe~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~42 , z80_|execute_|ctl_alu_shift_oe~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~47 , z80_|execute_|ctl_alu_shift_oe~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~34 , z80_|execute_|ctl_alu_shift_oe~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~35 , z80_|execute_|ctl_alu_shift_oe~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~36 , z80_|execute_|ctl_alu_shift_oe~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~43 , z80_|execute_|ctl_alu_shift_oe~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_oe~0 , z80_|execute_|ctl_alu_op2_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_oe~0 , z80_|execute_|ctl_alu_op1_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_oe~1 , z80_|execute_|ctl_alu_op1_oe~1, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~0 , z80_|alu_|db_high[3]~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_res_oe~0 , z80_|execute_|ctl_alu_res_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~4 , z80_|execute_|ctl_alu_core_S~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~5 , z80_|execute_|ctl_alu_core_S~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~15 , z80_|execute_|ctl_alu_oe~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_res_oe~1 , z80_|execute_|ctl_alu_res_oe~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~3 , z80_|execute_|ctl_flags_pf_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_res_oe~2 , z80_|execute_|ctl_alu_res_oe~2, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~1 , z80_|alu_|db_high[3]~1, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~2 , z80_|alu_|db_low[3]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~3 , z80_|alu_|db_low[3]~3, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[3] , z80_|alu_|result_lo[3], spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~4 , z80_|alu_|db_low[3]~4, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|ena , z80_|alu_|b2v_op1_latch_mux_low|ena, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[3] , z80_|alu_|op1_low[3], spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_8~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~11 , z80_|execute_|ctl_alu_core_S~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~9 , z80_|execute_|ctl_alu_core_S~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S , z80_|execute_|ctl_alu_core_S, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~25 , z80_|alu_|db_high[2]~25, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[6] , z80_|reg_file_|b2v_latch_ir_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[6]~0 , z80_|reg_file_|db_hi_as[6]~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[6] , z80_|reg_file_|b2v_latch_pc_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[6]~1 , z80_|reg_file_|db_hi_as[6]~1, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[14] , z80_|address_latch_|abusz[14], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[14] , z80_|address_latch_|Q[14], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[14] , z80_|address_latch_|b2v_inst_inc_dec|address[14], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[6]~3 , z80_|reg_file_|db_hi_as[6]~3, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[6] , z80_|reg_file_|b2v_latch_af_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 , z80_|reg_file_|b2v_latch_af_hi|db[6]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[6] , z80_|reg_file_|b2v_latch_hl_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] , z80_|reg_file_|b2v_latch_hl2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~68 , z80_|execute_|ctl_inc_cy~68, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~64 , z80_|execute_|ctl_inc_cy~64, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~63 , z80_|execute_|ctl_inc_cy~63, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~65 , z80_|execute_|ctl_inc_cy~65, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~69 , z80_|execute_|ctl_inc_cy~69, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~49 , z80_|execute_|ctl_inc_cy~49, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~50 , z80_|execute_|ctl_inc_cy~50, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~51 , z80_|execute_|ctl_inc_cy~51, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~52 , z80_|execute_|ctl_inc_cy~52, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~36 , z80_|execute_|ctl_inc_cy~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~37 , z80_|execute_|ctl_inc_cy~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~54 , z80_|execute_|ctl_inc_cy~54, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~41 , z80_|execute_|ctl_inc_cy~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~58 , z80_|execute_|ctl_inc_cy~58, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~55 , z80_|execute_|ctl_inc_cy~55, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~56 , z80_|execute_|ctl_inc_cy~56, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~89 , z80_|execute_|ctl_inc_cy~89, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~57 , z80_|execute_|ctl_inc_cy~57, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~59 , z80_|execute_|ctl_inc_cy~59, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~60 , z80_|execute_|ctl_inc_cy~60, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~47 , z80_|execute_|ctl_inc_cy~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~88 , z80_|execute_|ctl_inc_cy~88, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~48 , z80_|execute_|ctl_inc_cy~48, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~40 , z80_|execute_|pc_inc_hold~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~61 , z80_|execute_|ctl_inc_cy~61, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~62 , z80_|execute_|ctl_inc_cy~62, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~70 , z80_|execute_|ctl_inc_cy~70, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~85 , z80_|execute_|ctl_inc_cy~85, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~3 , z80_|reg_file_|db_lo_as[0]~3, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[0] , z80_|address_latch_|abusz[0], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[0]~feeder , z80_|address_latch_|Q[0]~feeder, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[0] , z80_|address_latch_|Q[0], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[1] , z80_|reg_file_|b2v_latch_ir_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[1] , z80_|reg_file_|b2v_latch_pc_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[1]~4 , z80_|reg_file_|db_lo_as[1]~4, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[1]~5 , z80_|reg_file_|db_lo_as[1]~5, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[1]~6 , z80_|reg_file_|db_lo_as[1]~6, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[1] , z80_|address_latch_|abusz[1], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[1] , z80_|address_latch_|Q[1], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[2]~9 , z80_|reg_file_|db_lo_as[2]~9, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[2] , z80_|address_latch_|abusz[2], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[2]~feeder , z80_|address_latch_|Q[2]~feeder, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[2] , z80_|address_latch_|Q[2], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~86 , z80_|execute_|ctl_inc_cy~86, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~11 , z80_|execute_|ctl_inc_dec~11, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[3] , z80_|reg_file_|b2v_latch_af2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[3] , z80_|reg_file_|b2v_latch_af_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~45 , z80_|reg_file_|gdfx_temp0[3]~45, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[3] , z80_|reg_file_|b2v_latch_ix_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[3] , z80_|reg_file_|b2v_latch_bc_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~48 , z80_|reg_file_|gdfx_temp0[3]~48, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[3] , z80_|reg_file_|b2v_latch_iy_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[3] , z80_|reg_file_|b2v_latch_sp_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~49 , z80_|reg_file_|gdfx_temp0[3]~49, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[3] , z80_|reg_file_|b2v_latch_wz_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] , z80_|reg_file_|b2v_latch_bc2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~41 , z80_|execute_|ctl_reg_gp_hilo[1]~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~42 , z80_|execute_|ctl_reg_gp_hilo[1]~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~43 , z80_|execute_|ctl_reg_gp_hilo[1]~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~44 , z80_|execute_|ctl_reg_gp_hilo[1]~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~45 , z80_|execute_|ctl_reg_gp_hilo[1]~45, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~46 , z80_|execute_|ctl_reg_gp_hilo[1]~46, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_48 , z80_|reg_file_|SYNTHESIZED_WIRE_48, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_44 , z80_|reg_file_|SYNTHESIZED_WIRE_44, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_45 , z80_|reg_file_|SYNTHESIZED_WIRE_45, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[3] , z80_|reg_file_|b2v_latch_de2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_49 , z80_|reg_file_|SYNTHESIZED_WIRE_49, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[3] , z80_|reg_file_|b2v_latch_de_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~40 , z80_|reg_file_|gdfx_temp1[3]~40, spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_52 , z80_|reg_file_|SYNTHESIZED_WIRE_52, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~9 , z80_|reg_file_|gdfx_temp1[6]~9, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] , z80_|reg_file_|b2v_latch_bc2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[6] , z80_|reg_file_|b2v_latch_bc_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~10 , z80_|reg_file_|gdfx_temp1[6]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[6] , z80_|reg_file_|b2v_latch_iy_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[6] , z80_|reg_file_|b2v_latch_ix_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~11 , z80_|reg_file_|gdfx_temp1[6]~11, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[6] , z80_|reg_file_|b2v_latch_sp_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[6] , z80_|reg_file_|b2v_latch_wz_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~13 , z80_|reg_file_|gdfx_temp1[6]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[6] , z80_|reg_file_|b2v_latch_af2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~12 , z80_|reg_file_|gdfx_temp1[6]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~14 , z80_|reg_file_|gdfx_temp1[6]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[6] , z80_|reg_file_|b2v_latch_de_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[6] , z80_|reg_file_|b2v_latch_de2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~8 , z80_|reg_file_|gdfx_temp1[6]~8, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~15 , z80_|reg_file_|gdfx_temp1[6]~15, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~21 , z80_|reg_file_|gdfx_temp1[6]~21, spectrum, 1 -instance = comp, \z80_|interrupts_|im2~feeder , z80_|interrupts_|im2~feeder, spectrum, 1 -instance = comp, \z80_|interrupts_|im2 , z80_|interrupts_|im2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~14 , z80_|execute_|ctl_mRead~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_mask543_en~0 , z80_|execute_|ctl_sw_mask543_en~0, spectrum, 1 -instance = comp, \z80_|sw1_|db_down[6]~0 , z80_|sw1_|db_down[6]~0, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~10 , z80_|alu_|db_low[1]~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_lq , z80_|execute_|ctl_alu_op2_sel_lq, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~8 , z80_|execute_|ctl_alu_op2_sel_bus~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~12 , z80_|execute_|ctl_alu_op2_sel_bus~12, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_57 , z80_|reg_file_|SYNTHESIZED_WIRE_57, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[3] , z80_|reg_file_|b2v_latch_hl_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_53 , z80_|reg_file_|SYNTHESIZED_WIRE_53, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] , z80_|reg_file_|b2v_latch_hl2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_56 , z80_|reg_file_|SYNTHESIZED_WIRE_56, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~41 , z80_|reg_file_|gdfx_temp1[3]~41, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_33 , z80_|reg_file_|SYNTHESIZED_WIRE_33, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[3] , z80_|reg_file_|b2v_latch_af_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 , z80_|reg_file_|b2v_latch_af_hi|db[3]~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~11 , z80_|execute_|ctl_reg_in_hi~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~12 , z80_|execute_|ctl_reg_in_hi~12, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_29 , z80_|reg_file_|SYNTHESIZED_WIRE_29, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[3] , z80_|reg_file_|b2v_latch_af2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_28 , z80_|reg_file_|SYNTHESIZED_WIRE_28, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~44 , z80_|reg_file_|gdfx_temp1[3]~44, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69 , z80_|reg_file_|SYNTHESIZED_WIRE_69, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[3] , z80_|reg_file_|b2v_latch_iy_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 , z80_|reg_file_|SYNTHESIZED_WIRE_68~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 , z80_|reg_file_|SYNTHESIZED_WIRE_64~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 , z80_|reg_file_|SYNTHESIZED_WIRE_69~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 , z80_|reg_file_|SYNTHESIZED_WIRE_65~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[3] , z80_|reg_file_|b2v_latch_ix_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68 , z80_|reg_file_|SYNTHESIZED_WIRE_68, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~43 , z80_|reg_file_|gdfx_temp1[3]~43, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 , z80_|reg_file_|SYNTHESIZED_WIRE_76~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 , z80_|reg_file_|SYNTHESIZED_WIRE_77~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[3] , z80_|reg_file_|b2v_latch_sp_hi|latch[3], spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~31 , z80_|execute_|ctl_reg_sys_hilo[1]~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~30 , z80_|execute_|ctl_reg_sys_hilo[1]~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~32 , z80_|execute_|ctl_reg_sys_hilo[1]~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~33 , z80_|execute_|ctl_reg_sys_hilo[1]~33, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_hi~0 , z80_|reg_control_|reg_sys_we_hi~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_hi , z80_|reg_control_|reg_sys_we_hi, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_81 , z80_|reg_file_|SYNTHESIZED_WIRE_81, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[3] , z80_|reg_file_|b2v_latch_wz_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_80 , z80_|reg_file_|SYNTHESIZED_WIRE_80, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~45 , z80_|reg_file_|gdfx_temp1[3]~45, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 , z80_|reg_file_|SYNTHESIZED_WIRE_41~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[3] , z80_|reg_file_|b2v_latch_bc_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 , z80_|reg_file_|SYNTHESIZED_WIRE_36~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 , z80_|reg_file_|SYNTHESIZED_WIRE_37~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] , z80_|reg_file_|b2v_latch_bc2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 , z80_|reg_file_|SYNTHESIZED_WIRE_40~0, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~42 , z80_|reg_file_|gdfx_temp1[3]~42, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~46 , z80_|reg_file_|gdfx_temp1[3]~46, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~47 , z80_|reg_file_|gdfx_temp1[3]~47, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~17 , z80_|reg_file_|gdfx_temp1[0]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~18 , z80_|reg_file_|gdfx_temp1[0]~18, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~19 , z80_|reg_file_|gdfx_temp1[0]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~16 , z80_|reg_file_|gdfx_temp1[0]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~20 , z80_|reg_file_|gdfx_temp1[0]~20, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_73 , z80_|reg_file_|SYNTHESIZED_WIRE_73, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[1] , z80_|reg_file_|b2v_latch_pc_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[1] , z80_|reg_file_|b2v_latch_de2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[1] , z80_|reg_file_|b2v_latch_de_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~8 , z80_|reg_file_|gdfx_temp1[1]~8, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[1] , z80_|reg_file_|b2v_latch_af_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 , z80_|reg_file_|b2v_latch_af_hi|db[1]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[1] , z80_|reg_file_|b2v_latch_sp_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[1] , z80_|reg_file_|b2v_latch_wz_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~13 , z80_|reg_file_|gdfx_temp1[1]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[1] , z80_|reg_file_|b2v_latch_af2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~12 , z80_|reg_file_|gdfx_temp1[1]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[1] , z80_|reg_file_|b2v_latch_bc_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] , z80_|reg_file_|b2v_latch_bc2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~10 , z80_|reg_file_|gdfx_temp1[1]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[1] , z80_|reg_file_|b2v_latch_ix_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[1] , z80_|reg_file_|b2v_latch_iy_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~11 , z80_|reg_file_|gdfx_temp1[1]~11, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~14 , z80_|reg_file_|gdfx_temp1[1]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] , z80_|reg_file_|b2v_latch_hl2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[1] , z80_|reg_file_|b2v_latch_hl_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~9 , z80_|reg_file_|gdfx_temp1[1]~9, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~15 , z80_|reg_file_|gdfx_temp1[1]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~21 , z80_|reg_file_|gdfx_temp1[1]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_60 , z80_|reg_file_|SYNTHESIZED_WIRE_60, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_61 , z80_|reg_file_|SYNTHESIZED_WIRE_61, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[1] , z80_|reg_file_|b2v_latch_ir_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sw_4d_hi~0 , z80_|reg_control_|reg_sw_4d_hi~0, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[1]~0 , z80_|reg_file_|db_hi_as[1]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_72 , z80_|reg_file_|SYNTHESIZED_WIRE_72, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[1]~1 , z80_|reg_file_|db_hi_as[1]~1, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[0]~2 , z80_|reg_file_|db_hi_as[0]~2, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[0] , z80_|reg_file_|b2v_latch_pc_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] , z80_|reg_file_|b2v_latch_hl2_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[0] , z80_|reg_file_|b2v_latch_hl_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~23 , z80_|reg_file_|gdfx_temp1[0]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[0] , z80_|reg_file_|b2v_latch_de2_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[0] , z80_|reg_file_|b2v_latch_de_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~22 , z80_|reg_file_|gdfx_temp1[0]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] , z80_|reg_file_|b2v_latch_bc2_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[0] , z80_|reg_file_|b2v_latch_bc_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~24 , z80_|reg_file_|gdfx_temp1[0]~24, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[0] , z80_|reg_file_|b2v_latch_af2_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~26 , z80_|reg_file_|gdfx_temp1[0]~26, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder , z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[0] , z80_|reg_file_|b2v_latch_ix_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[0] , z80_|reg_file_|b2v_latch_iy_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~25 , z80_|reg_file_|gdfx_temp1[0]~25, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[0] , z80_|reg_file_|b2v_latch_sp_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[0] , z80_|reg_file_|b2v_latch_wz_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~27 , z80_|reg_file_|gdfx_temp1[0]~27, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~28 , z80_|reg_file_|gdfx_temp1[0]~28, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[0] , z80_|reg_file_|b2v_latch_af_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 , z80_|reg_file_|b2v_latch_af_hi|db[0]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~29 , z80_|reg_file_|gdfx_temp1[0]~29, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~30 , z80_|reg_file_|gdfx_temp1[0]~30, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[0] , z80_|reg_file_|b2v_latch_ir_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[0]~4 , z80_|reg_file_|db_hi_as[0]~4, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[0]~5 , z80_|reg_file_|db_hi_as[0]~5, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[0]~6 , z80_|reg_file_|db_hi_as[0]~6, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[8] , z80_|address_latch_|abusz[8], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[8] , z80_|address_latch_|Q[8], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[1]~3 , z80_|reg_file_|db_hi_as[1]~3, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[9] , z80_|address_latch_|abusz[9], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[9]~feeder , z80_|address_latch_|Q[9]~feeder, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[9] , z80_|address_latch_|Q[9], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] , z80_|reg_file_|b2v_latch_hl2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[2] , z80_|reg_file_|b2v_latch_hl_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~32 , z80_|reg_file_|gdfx_temp1[2]~32, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[2] , z80_|reg_file_|b2v_latch_af2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~35 , z80_|reg_file_|gdfx_temp1[2]~35, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[2] , z80_|reg_file_|b2v_latch_ix_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[2] , z80_|reg_file_|b2v_latch_iy_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~34 , z80_|reg_file_|gdfx_temp1[2]~34, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[2] , z80_|reg_file_|b2v_latch_bc_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] , z80_|reg_file_|b2v_latch_bc2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~33 , z80_|reg_file_|gdfx_temp1[2]~33, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[2] , z80_|reg_file_|b2v_latch_sp_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[2] , z80_|reg_file_|b2v_latch_wz_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~36 , z80_|reg_file_|gdfx_temp1[2]~36, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~37 , z80_|reg_file_|gdfx_temp1[2]~37, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[2] , z80_|reg_file_|b2v_latch_de_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[2] , z80_|reg_file_|b2v_latch_de2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~31 , z80_|reg_file_|gdfx_temp1[2]~31, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[2] , z80_|reg_file_|b2v_latch_af_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 , z80_|reg_file_|b2v_latch_af_hi|db[2]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~38 , z80_|reg_file_|gdfx_temp1[2]~38, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~39 , z80_|reg_file_|gdfx_temp1[2]~39, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[2] , z80_|reg_file_|b2v_latch_ir_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[2]~7 , z80_|reg_file_|db_hi_as[2]~7, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[2] , z80_|reg_file_|b2v_latch_pc_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[2]~8 , z80_|reg_file_|db_hi_as[2]~8, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[2]~9 , z80_|reg_file_|db_hi_as[2]~9, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[10] , z80_|address_latch_|abusz[10], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[10]~feeder , z80_|address_latch_|Q[10]~feeder, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[10] , z80_|address_latch_|Q[10], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[11] , z80_|address_latch_|abusz[11], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[11] , z80_|address_latch_|Q[11], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[11] , z80_|address_latch_|b2v_inst_inc_dec|address[11], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[3] , z80_|reg_file_|b2v_latch_pc_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[3] , z80_|reg_file_|b2v_latch_ir_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[3]~10 , z80_|reg_file_|db_hi_as[3]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[3]~11 , z80_|reg_file_|db_hi_as[3]~11, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[3]~12 , z80_|reg_file_|db_hi_as[3]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~48 , z80_|reg_file_|gdfx_temp1[3]~48, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_low , z80_|execute_|ctl_alu_op1_sel_low, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[3] , z80_|alu_|b2v_op1_latch_mux_high|Q[3], spectrum, 1 +instance = comp, \z80_|alu_|op1_high[3] , z80_|alu_|op1_high[3], spectrum, 1 +instance = comp, \z80_|alu_|alu_op1[3]~3 , z80_|alu_|alu_op1[3]~3, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~6 , z80_|execute_|ctl_alu_op2_sel_bus~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~10 , z80_|execute_|ctl_alu_op2_sel_bus~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~0 , z80_|execute_|ctl_alu_core_R~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~5 , z80_|execute_|ctl_alu_op2_sel_bus~5, spectrum, 1 instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~7 , z80_|execute_|ctl_alu_op2_sel_bus~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~9 , z80_|execute_|ctl_alu_op2_sel_bus~9, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_zero , z80_|execute_|ctl_alu_op2_sel_zero, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~8 , z80_|execute_|ctl_alu_op2_sel_bus~8, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6, spectrum, 1 instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|ena , z80_|alu_|b2v_op2_latch_mux_high|ena, spectrum, 1 instance = comp, \z80_|alu_|op2_high[1] , z80_|alu_|op2_high[1], spectrum, 1 instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[1] , z80_|alu_|b2v_op1_latch_mux_high|Q[1], spectrum, 1 instance = comp, \z80_|alu_|op1_high[1] , z80_|alu_|op1_high[1], spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~3 , z80_|alu_|db_high[1]~3, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~2 , z80_|alu_|db_high[1]~2, spectrum, 1 -instance = comp, \z80_|alu_|db[7]~9 , z80_|alu_|db[7]~9, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[5] , z80_|reg_file_|b2v_latch_iy_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[5] , z80_|reg_file_|b2v_latch_ix_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~70 , z80_|reg_file_|gdfx_temp1[5]~70, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[5] , z80_|reg_file_|b2v_latch_sp_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[5] , z80_|reg_file_|b2v_latch_wz_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~72 , z80_|reg_file_|gdfx_temp1[5]~72, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[5] , z80_|reg_file_|b2v_latch_af2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~71 , z80_|reg_file_|gdfx_temp1[5]~71, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] , z80_|reg_file_|b2v_latch_bc2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[5] , z80_|reg_file_|b2v_latch_bc_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~69 , z80_|reg_file_|gdfx_temp1[5]~69, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~73 , z80_|reg_file_|gdfx_temp1[5]~73, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[5] , z80_|reg_file_|b2v_latch_de_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[5] , z80_|reg_file_|b2v_latch_de2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~67 , z80_|reg_file_|gdfx_temp1[5]~67, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[5] , z80_|reg_file_|b2v_latch_af_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[5]~16 , z80_|reg_file_|b2v_latch_af_hi|db[5]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] , z80_|reg_file_|b2v_latch_hl2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[5] , z80_|reg_file_|b2v_latch_hl_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~68 , z80_|reg_file_|gdfx_temp1[5]~68, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~74 , z80_|reg_file_|gdfx_temp1[5]~74, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~75 , z80_|reg_file_|gdfx_temp1[5]~75, spectrum, 1 -instance = comp, \z80_|alu_|db[5]~23 , z80_|alu_|db[5]~23, spectrum, 1 -instance = comp, \z80_|alu_|db[5]~24 , z80_|alu_|db[5]~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~5 , z80_|execute_|ctl_flags_cf2_sel_shift~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~3 , z80_|execute_|ctl_flags_cf2_sel_shift~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~4 , z80_|execute_|ctl_flags_cf2_sel_shift~4, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[12] , z80_|address_latch_|abusz[12], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[12] , z80_|address_latch_|Q[12], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[4] , z80_|reg_file_|b2v_latch_ir_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[4]~22 , z80_|reg_file_|db_hi_as[4]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[4] , z80_|reg_file_|b2v_latch_pc_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[4]~23 , z80_|reg_file_|db_hi_as[4]~23, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[4]~24 , z80_|reg_file_|db_hi_as[4]~24, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[4] , z80_|reg_file_|b2v_latch_af_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[4]~17 , z80_|reg_file_|b2v_latch_af_hi|db[4]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] , z80_|reg_file_|b2v_latch_hl2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[4] , z80_|reg_file_|b2v_latch_hl_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~77 , z80_|reg_file_|gdfx_temp1[4]~77, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[4] , z80_|reg_file_|b2v_latch_de_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[4] , z80_|reg_file_|b2v_latch_de2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~76 , z80_|reg_file_|gdfx_temp1[4]~76, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[4] , z80_|reg_file_|b2v_latch_iy_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[4] , z80_|reg_file_|b2v_latch_ix_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~79 , z80_|reg_file_|gdfx_temp1[4]~79, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] , z80_|reg_file_|b2v_latch_bc2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[4] , z80_|reg_file_|b2v_latch_bc_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~78 , z80_|reg_file_|gdfx_temp1[4]~78, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[4] , z80_|reg_file_|b2v_latch_af2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~80 , z80_|reg_file_|gdfx_temp1[4]~80, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[4] , z80_|reg_file_|b2v_latch_sp_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[4] , z80_|reg_file_|b2v_latch_wz_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~81 , z80_|reg_file_|gdfx_temp1[4]~81, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~82 , z80_|reg_file_|gdfx_temp1[4]~82, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~83 , z80_|reg_file_|gdfx_temp1[4]~83, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~84 , z80_|reg_file_|gdfx_temp1[4]~84, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_46 , z80_|reg_file_|SYNTHESIZED_WIRE_46, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~93 , z80_|reg_file_|gdfx_temp0[0]~93, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70 , z80_|reg_file_|SYNTHESIZED_WIRE_70, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_82 , z80_|reg_file_|SYNTHESIZED_WIRE_82, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_30 , z80_|reg_file_|SYNTHESIZED_WIRE_30, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_34 , z80_|reg_file_|SYNTHESIZED_WIRE_34, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 , z80_|reg_file_|SYNTHESIZED_WIRE_78~0, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~18 , z80_|reg_file_|gdfx_temp0[0]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 , z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_lo~8 , z80_|execute_|ctl_reg_in_lo~8, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 , z80_|reg_file_|SYNTHESIZED_WIRE_42~0, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~19 , z80_|reg_file_|gdfx_temp0[0]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 , z80_|reg_file_|SYNTHESIZED_WIRE_66~0, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~20 , z80_|reg_file_|gdfx_temp0[0]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~21 , z80_|reg_file_|gdfx_temp0[0]~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~81 , z80_|execute_|ctl_inc_cy~81, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[1] , z80_|reg_file_|b2v_latch_ir_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 , z80_|reg_file_|SYNTHESIZED_WIRE_71~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 , z80_|reg_file_|SYNTHESIZED_WIRE_79~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[1] , z80_|reg_file_|b2v_latch_sp_lo|latch[1], spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~2 , z80_|alu_flags_|DFFE_inst_latch_cf~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_hf2~0 , z80_|alu_flags_|flags_hf2~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_hf2 , z80_|alu_flags_|flags_hf2, spectrum, 1 -instance = comp, \z80_|alu_|alu_op1[2]~2 , z80_|alu_|alu_op1[2]~2, spectrum, 1 -instance = comp, \z80_|alu_|alu_op1[1]~1 , z80_|alu_|alu_op1[1]~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[1] , z80_|alu_|op2_low[1], spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~6 , z80_|execute_|ctl_alu_sel_op2_neg~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~20 , z80_|execute_|ctl_alu_sel_op2_neg~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~12 , z80_|execute_|ctl_state_alu~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~18 , z80_|execute_|ctl_alu_core_hf~18, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal61~2 , z80_|pla_decode_|Equal61~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~16 , z80_|execute_|ctl_alu_sel_op2_neg~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~17 , z80_|execute_|ctl_alu_sel_op2_neg~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~21 , z80_|execute_|ctl_alu_sel_op2_neg~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~15 , z80_|execute_|ctl_alu_sel_op2_neg~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~12 , z80_|execute_|ctl_alu_sel_op2_neg~12, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~20 , z80_|execute_|ctl_alu_core_hf~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~4 , z80_|execute_|ctl_flags_sz_we~4, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal71~2 , z80_|pla_decode_|Equal71~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~8 , z80_|alu_flags_|DFFE_inst_latch_nf~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~31 , z80_|execute_|ctl_alu_op_low~31, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~4 , z80_|alu_flags_|DFFE_inst_latch_nf~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~5 , z80_|alu_flags_|DFFE_inst_latch_nf~5, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~6 , z80_|alu_flags_|DFFE_inst_latch_nf~6, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal72~2 , z80_|pla_decode_|Equal72~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal73~2 , z80_|pla_decode_|Equal73~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~0 , z80_|execute_|ctl_flags_nf_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~1 , z80_|execute_|ctl_flags_nf_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~2 , z80_|execute_|ctl_flags_nf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~3 , z80_|execute_|ctl_flags_nf_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~5 , z80_|execute_|ctl_flags_sz_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~6 , z80_|execute_|ctl_flags_sz_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~4 , z80_|execute_|ctl_flags_nf_we~4, spectrum, 1 +instance = comp, \z80_|execute_|setM1~15 , z80_|execute_|setM1~15, spectrum, 1 +instance = comp, \z80_|execute_|setM1~16 , z80_|execute_|setM1~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~6 , z80_|execute_|ctl_flags_xy_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~7 , z80_|execute_|ctl_flags_xy_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~2 , z80_|execute_|ctl_flags_sz_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 , z80_|execute_|ctl_pf_sel_pla12M1T1_12~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~1 , z80_|execute_|ctl_alu_core_R~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~7 , z80_|execute_|ctl_flags_alu~7, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~8 , z80_|reg_control_|reg_sys_we_lo~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~8 , z80_|execute_|ctl_flags_alu~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~16 , z80_|execute_|ctl_flags_xy_we~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~12 , z80_|execute_|ctl_flags_alu~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~13 , z80_|execute_|ctl_flags_alu~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~14 , z80_|execute_|ctl_flags_alu~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~15 , z80_|execute_|ctl_flags_alu~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 , z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~19 , z80_|execute_|ctl_alu_sel_op2_neg~19, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~7 , z80_|alu_flags_|DFFE_inst_latch_nf~7, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~9 , z80_|alu_flags_|DFFE_inst_latch_nf~9, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~10 , z80_|alu_flags_|DFFE_inst_latch_nf~10, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf , z80_|alu_flags_|DFFE_inst_latch_nf, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~7 , z80_|execute_|ctl_alu_sel_op2_neg~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 , z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~10 , z80_|execute_|ctl_alu_sel_op2_neg~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~8 , z80_|execute_|ctl_alu_sel_op2_neg~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~9 , z80_|execute_|ctl_alu_sel_op2_neg~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~11 , z80_|execute_|ctl_alu_sel_op2_neg~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~14 , z80_|execute_|ctl_alu_sel_op2_neg~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~18 , z80_|execute_|ctl_alu_sel_op2_neg~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_high , z80_|execute_|ctl_alu_sel_op2_high, spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[1]~1 , z80_|alu_|alu_op2[1]~1, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|alu_|db[1]~15 , z80_|alu_|db[1]~15, spectrum, 1 -instance = comp, \z80_|alu_|db[1]~16 , z80_|alu_|db[1]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[0] , z80_|reg_file_|b2v_latch_pc_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[0] , z80_|reg_file_|b2v_latch_ir_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[0]~10 , z80_|reg_file_|db_hi_as[0]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[0]~11 , z80_|reg_file_|db_hi_as[0]~11, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_31 , z80_|reg_file_|SYNTHESIZED_WIRE_31, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[6] , z80_|reg_file_|b2v_latch_af2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_35 , z80_|reg_file_|SYNTHESIZED_WIRE_35, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[6] , z80_|reg_file_|b2v_latch_af_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~75 , z80_|reg_file_|gdfx_temp0[6]~75, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 , z80_|reg_file_|SYNTHESIZED_WIRE_43~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[6] , z80_|reg_file_|b2v_latch_bc_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 , z80_|reg_file_|SYNTHESIZED_WIRE_39~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] , z80_|reg_file_|b2v_latch_bc2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~76 , z80_|reg_file_|gdfx_temp0[6]~76, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_83 , z80_|reg_file_|SYNTHESIZED_WIRE_83, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[6] , z80_|reg_file_|b2v_latch_wz_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~77 , z80_|reg_file_|gdfx_temp0[6]~77, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[6] , z80_|reg_file_|b2v_latch_sp_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~79 , z80_|reg_file_|gdfx_temp0[6]~79, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 , z80_|reg_file_|SYNTHESIZED_WIRE_67~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[6] , z80_|reg_file_|b2v_latch_ix_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71 , z80_|reg_file_|SYNTHESIZED_WIRE_71, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[6] , z80_|reg_file_|b2v_latch_iy_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~78 , z80_|reg_file_|gdfx_temp0[6]~78, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~80 , z80_|reg_file_|gdfx_temp0[6]~80, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[6] , z80_|reg_file_|b2v_latch_hl_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] , z80_|reg_file_|b2v_latch_hl2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~74 , z80_|reg_file_|gdfx_temp0[6]~74, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[6] , z80_|reg_file_|b2v_latch_de_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[6] , z80_|reg_file_|b2v_latch_de2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~73 , z80_|reg_file_|gdfx_temp0[6]~73, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~81 , z80_|reg_file_|gdfx_temp0[6]~81, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~82 , z80_|reg_file_|gdfx_temp0[6]~82, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[6] , z80_|reg_file_|b2v_latch_pc_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[6]~19 , z80_|reg_file_|db_lo_as[6]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[6] , z80_|reg_file_|b2v_latch_ir_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[6]~20 , z80_|reg_file_|db_lo_as[6]~20, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[4] , z80_|address_latch_|abusz[4], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[4] , z80_|address_latch_|Q[4], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder , z80_|reg_file_|b2v_latch_de_lo|latch[5]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[5] , z80_|reg_file_|b2v_latch_de_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[5] , z80_|reg_file_|b2v_latch_de2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~63 , z80_|reg_file_|gdfx_temp0[5]~63, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[5] , z80_|reg_file_|b2v_latch_hl_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] , z80_|reg_file_|b2v_latch_hl2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~64 , z80_|reg_file_|gdfx_temp0[5]~64, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[5] , z80_|reg_file_|b2v_latch_af2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[5] , z80_|reg_file_|b2v_latch_af_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~65 , z80_|reg_file_|gdfx_temp0[5]~65, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder , z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[5] , z80_|reg_file_|b2v_latch_ix_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[5] , z80_|reg_file_|b2v_latch_bc_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~68 , z80_|reg_file_|gdfx_temp0[5]~68, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[5] , z80_|reg_file_|b2v_latch_iy_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[5] , z80_|reg_file_|b2v_latch_sp_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~69 , z80_|reg_file_|gdfx_temp0[5]~69, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] , z80_|reg_file_|b2v_latch_bc2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~66 , z80_|reg_file_|gdfx_temp0[5]~66, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[5] , z80_|reg_file_|b2v_latch_wz_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~67 , z80_|reg_file_|gdfx_temp0[5]~67, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~70 , z80_|reg_file_|gdfx_temp0[5]~70, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~71 , z80_|reg_file_|gdfx_temp0[5]~71, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~72 , z80_|reg_file_|gdfx_temp0[5]~72, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[5] , z80_|reg_file_|b2v_latch_pc_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[5]~16 , z80_|reg_file_|db_lo_as[5]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder , z80_|reg_file_|b2v_latch_ir_lo|latch[5]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[5] , z80_|reg_file_|b2v_latch_ir_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[5]~17 , z80_|reg_file_|db_lo_as[5]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[5]~18 , z80_|reg_file_|db_lo_as[5]~18, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[5] , z80_|address_latch_|abusz[5], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[5]~feeder , z80_|address_latch_|Q[5]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[5] , z80_|address_latch_|Q[5], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[6] , z80_|address_latch_|b2v_inst_inc_dec|address[6], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[6]~21 , z80_|reg_file_|db_lo_as[6]~21, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[6] , z80_|address_latch_|abusz[6], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[6] , z80_|address_latch_|Q[6], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~2, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[7] , z80_|reg_file_|b2v_latch_de2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder , z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[7] , z80_|reg_file_|b2v_latch_de_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~83 , z80_|reg_file_|gdfx_temp0[7]~83, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[7] , z80_|reg_file_|b2v_latch_hl_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] , z80_|reg_file_|b2v_latch_hl2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~84 , z80_|reg_file_|gdfx_temp0[7]~84, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[7] , z80_|reg_file_|b2v_latch_ix_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[7] , z80_|reg_file_|b2v_latch_iy_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~88 , z80_|reg_file_|gdfx_temp0[7]~88, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[7] , z80_|reg_file_|b2v_latch_af2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[7]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[7] , z80_|reg_file_|b2v_latch_af_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~85 , z80_|reg_file_|gdfx_temp0[7]~85, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[7] , z80_|reg_file_|b2v_latch_bc_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] , z80_|reg_file_|b2v_latch_bc2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~86 , z80_|reg_file_|gdfx_temp0[7]~86, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[7] , z80_|reg_file_|b2v_latch_wz_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~87 , z80_|reg_file_|gdfx_temp0[7]~87, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[7] , z80_|reg_file_|b2v_latch_sp_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~89 , z80_|reg_file_|gdfx_temp0[7]~89, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~90 , z80_|reg_file_|gdfx_temp0[7]~90, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~91 , z80_|reg_file_|gdfx_temp0[7]~91, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~92 , z80_|reg_file_|gdfx_temp0[7]~92, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[7] , z80_|reg_file_|b2v_latch_pc_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[7]~22 , z80_|reg_file_|db_lo_as[7]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[7] , z80_|reg_file_|b2v_latch_ir_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[7]~23 , z80_|reg_file_|db_lo_as[7]~23, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[7]~24 , z80_|reg_file_|db_lo_as[7]~24, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[7] , z80_|address_latch_|abusz[7], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[7]~feeder , z80_|address_latch_|Q[7]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[7] , z80_|address_latch_|Q[7], spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[8] , z80_|address_latch_|abusz[8], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[8] , z80_|address_latch_|Q[8], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[0]~12 , z80_|reg_file_|db_hi_as[0]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] , z80_|reg_file_|b2v_latch_hl2_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[0] , z80_|reg_file_|b2v_latch_hl_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~41 , z80_|reg_file_|gdfx_temp1[0]~41, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[0] , z80_|reg_file_|b2v_latch_af_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[0]~14 , z80_|reg_file_|b2v_latch_af_hi|db[0]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[0] , z80_|reg_file_|b2v_latch_bc_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] , z80_|reg_file_|b2v_latch_bc2_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~42 , z80_|reg_file_|gdfx_temp1[0]~42, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[0] , z80_|reg_file_|b2v_latch_af2_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~44 , z80_|reg_file_|gdfx_temp1[0]~44, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[0] , z80_|reg_file_|b2v_latch_wz_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[0] , z80_|reg_file_|b2v_latch_sp_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~45 , z80_|reg_file_|gdfx_temp1[0]~45, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[0] , z80_|reg_file_|b2v_latch_ix_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[0] , z80_|reg_file_|b2v_latch_iy_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~43 , z80_|reg_file_|gdfx_temp1[0]~43, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~46 , z80_|reg_file_|gdfx_temp1[0]~46, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[0] , z80_|reg_file_|b2v_latch_de_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[0] , z80_|reg_file_|b2v_latch_de2_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~40 , z80_|reg_file_|gdfx_temp1[0]~40, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~47 , z80_|reg_file_|gdfx_temp1[0]~47, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~48 , z80_|reg_file_|gdfx_temp1[0]~48, spectrum, 1 -instance = comp, \z80_|alu_|db[0]~17 , z80_|alu_|db[0]~17, spectrum, 1 -instance = comp, \z80_|alu_|db[0]~18 , z80_|alu_|db[0]~18, spectrum, 1 -instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~1 , z80_|alu_control_|b2v_inst_shift_mux|out~1, spectrum, 1 -instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~0 , z80_|alu_control_|b2v_inst_shift_mux|out~0, spectrum, 1 -instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~2 , z80_|alu_control_|b2v_inst_shift_mux|out~2, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~16 , z80_|alu_|db_low[0]~16, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~17 , z80_|alu_|db_low[0]~17, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~19 , z80_|alu_|db_low[0]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~9 , z80_|execute_|ctl_alu_core_S~9, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[0] , z80_|alu_|op2_high[0], spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[0]~3 , z80_|alu_|alu_op2[0]~3, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~12 , z80_|alu_flags_|DFFE_inst_latch_nf~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~8 , z80_|execute_|ctl_alu_core_S~8, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~21 , z80_|execute_|ctl_alu_core_hf~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~22 , z80_|execute_|ctl_alu_core_hf~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~19 , z80_|execute_|ctl_alu_core_hf~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~27 , z80_|execute_|ctl_alu_op_low~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~29 , z80_|execute_|ctl_alu_op_low~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~23 , z80_|execute_|ctl_alu_core_hf~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~37 , z80_|execute_|ctl_alu_core_hf~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~38 , z80_|execute_|ctl_alu_core_hf~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~24 , z80_|execute_|ctl_alu_core_hf~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~25 , z80_|execute_|ctl_alu_core_hf~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~26 , z80_|execute_|ctl_alu_core_hf~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~27 , z80_|execute_|ctl_alu_core_hf~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~28 , z80_|execute_|ctl_alu_core_hf~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~30 , z80_|execute_|ctl_alu_op_low~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~34 , z80_|execute_|ctl_alu_core_hf~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~32 , z80_|execute_|ctl_alu_core_hf~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~43 , z80_|execute_|ctl_alu_core_hf~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~33 , z80_|execute_|ctl_alu_core_hf~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~42 , z80_|execute_|ctl_alu_core_hf~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~35 , z80_|execute_|ctl_alu_core_hf~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~41 , z80_|execute_|ctl_alu_core_hf~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~30 , z80_|execute_|ctl_alu_core_hf~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~10 , z80_|execute_|ctl_mWrite~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~31 , z80_|execute_|ctl_alu_core_hf~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~44 , z80_|execute_|ctl_alu_core_hf~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~29 , z80_|execute_|ctl_alu_core_hf~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~36 , z80_|execute_|ctl_alu_core_hf~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~39 , z80_|execute_|ctl_alu_core_hf~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~40 , z80_|execute_|ctl_alu_core_hf~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_we~2 , z80_|execute_|ctl_flags_hf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~2 , z80_|execute_|ctl_alu_core_R~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R , z80_|execute_|ctl_alu_core_R, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[3] , z80_|alu_|op2_high[3], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[3] , z80_|alu_|op2_low[3], spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[3]~2 , z80_|alu_|alu_op2[3]~2, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf~0 , z80_|alu_flags_|DFFE_inst_latch_hf~0, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_hf_we~3 , z80_|execute_|ctl_flags_hf_we~3, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_hf_we~4 , z80_|execute_|ctl_flags_hf_we~4, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf~1 , z80_|alu_flags_|DFFE_inst_latch_hf~1, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf , z80_|alu_flags_|DFFE_inst_latch_hf, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~14 , z80_|execute_|ctl_alu_core_hf~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~14 , z80_|execute_|ctl_alu_sel_op2_neg~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~17 , z80_|execute_|ctl_alu_sel_op2_neg~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 , z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~18 , z80_|execute_|ctl_alu_sel_op2_neg~18, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~15, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~16 , z80_|execute_|ctl_alu_core_hf~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~2 , z80_|execute_|ctl_flags_nf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~3 , z80_|execute_|ctl_flags_nf_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~4 , z80_|execute_|ctl_flags_nf_we~4, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~5 , z80_|alu_flags_|DFFE_inst_latch_nf~5, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~6 , z80_|alu_flags_|DFFE_inst_latch_nf~6, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~7 , z80_|alu_flags_|DFFE_inst_latch_nf~7, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~8 , z80_|alu_flags_|DFFE_inst_latch_nf~8, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf , z80_|alu_flags_|DFFE_inst_latch_nf, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~9 , z80_|execute_|ctl_flags_hf_cpl~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~10 , z80_|execute_|ctl_flags_hf_cpl~10, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_hf_cpl~11 , z80_|execute_|ctl_flags_hf_cpl~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~12 , z80_|execute_|ctl_flags_hf_cpl~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~13 , z80_|execute_|ctl_flags_hf_cpl~13, spectrum, 1 instance = comp, \z80_|alu_flags_|flags_hf , z80_|alu_flags_|flags_hf, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~15 , z80_|execute_|ctl_alu_core_hf~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~17 , z80_|execute_|ctl_alu_core_hf~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~18 , z80_|execute_|ctl_alu_core_hf~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~19 , z80_|execute_|ctl_alu_core_hf~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~22 , z80_|execute_|ctl_alu_core_hf~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~23 , z80_|execute_|ctl_alu_core_hf~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~20 , z80_|execute_|ctl_alu_core_hf~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 , z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~21 , z80_|execute_|ctl_alu_core_hf~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~24 , z80_|execute_|ctl_alu_core_hf~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~38 , z80_|execute_|ctl_alu_core_hf~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~25 , z80_|execute_|ctl_alu_core_hf~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~36 , z80_|execute_|ctl_alu_core_hf~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~31 , z80_|execute_|ctl_alu_core_hf~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~37 , z80_|execute_|ctl_alu_core_hf~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~29 , z80_|execute_|ctl_alu_core_hf~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~30 , z80_|execute_|ctl_alu_core_hf~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~32 , z80_|execute_|ctl_alu_core_hf~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~26 , z80_|execute_|ctl_alu_core_hf~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~27 , z80_|execute_|ctl_alu_core_hf~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~28 , z80_|execute_|ctl_alu_core_hf~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~33 , z80_|execute_|ctl_alu_core_hf~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~39 , z80_|execute_|ctl_alu_core_hf~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~40 , z80_|execute_|ctl_alu_core_hf~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~34 , z80_|execute_|ctl_alu_core_hf~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~35 , z80_|execute_|ctl_alu_core_hf~35, spectrum, 1 instance = comp, \z80_|alu_control_|alu_core_cf_in~0 , z80_|alu_control_|alu_core_cf_in~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_high , z80_|execute_|ctl_alu_sel_op2_high, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~8 , z80_|alu_|db_high[0]~8, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~23 , z80_|alu_|db_high[0]~23, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[12] , z80_|address_latch_|abusz[12], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[12]~feeder , z80_|address_latch_|Q[12]~feeder, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[12] , z80_|address_latch_|Q[12], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[4] , z80_|reg_file_|b2v_latch_pc_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[4] , z80_|reg_file_|b2v_latch_ir_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[4]~16 , z80_|reg_file_|db_hi_as[4]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[4]~17 , z80_|reg_file_|db_hi_as[4]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[4]~18 , z80_|reg_file_|db_hi_as[4]~18, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[4] , z80_|reg_file_|b2v_latch_af2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~62 , z80_|reg_file_|gdfx_temp1[4]~62, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[4] , z80_|reg_file_|b2v_latch_sp_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[4] , z80_|reg_file_|b2v_latch_wz_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~63 , z80_|reg_file_|gdfx_temp1[4]~63, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[4] , z80_|reg_file_|b2v_latch_ix_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[4] , z80_|reg_file_|b2v_latch_iy_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~61 , z80_|reg_file_|gdfx_temp1[4]~61, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[4] , z80_|reg_file_|b2v_latch_bc_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] , z80_|reg_file_|b2v_latch_bc2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~60 , z80_|reg_file_|gdfx_temp1[4]~60, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~64 , z80_|reg_file_|gdfx_temp1[4]~64, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] , z80_|reg_file_|b2v_latch_hl2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[4] , z80_|reg_file_|b2v_latch_hl_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~59 , z80_|reg_file_|gdfx_temp1[4]~59, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[4] , z80_|reg_file_|b2v_latch_de2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[4] , z80_|reg_file_|b2v_latch_de_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~58 , z80_|reg_file_|gdfx_temp1[4]~58, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[4] , z80_|reg_file_|b2v_latch_af_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 , z80_|reg_file_|b2v_latch_af_hi|db[4]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~65 , z80_|reg_file_|gdfx_temp1[4]~65, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~66 , z80_|reg_file_|gdfx_temp1[4]~66, spectrum, 1 +instance = comp, \z80_|alu_|db[4]~16 , z80_|alu_|db[4]~16, spectrum, 1 +instance = comp, \z80_|alu_|db[7]~26 , z80_|alu_|db[7]~26, spectrum, 1 +instance = comp, \z80_|alu_|db[4]~17 , z80_|alu_|db[4]~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~3 , z80_|execute_|ctl_flags_cf2_sel_shift~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~5 , z80_|execute_|ctl_flags_cf2_sel_shift~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~4 , z80_|execute_|ctl_flags_cf2_sel_shift~4, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~24 , z80_|alu_|db_high[0]~24, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~21 , z80_|alu_|db_high[0]~21, spectrum, 1 instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[0] , z80_|alu_|b2v_op1_latch_mux_high|Q[0], spectrum, 1 instance = comp, \z80_|alu_|op1_high[0] , z80_|alu_|op1_high[0], spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~9 , z80_|alu_|db_high[0]~9, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~10 , z80_|alu_|db_high[0]~10, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~11 , z80_|alu_|db_high[0]~11, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~12 , z80_|alu_|db_high[0]~12, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~13 , z80_|alu_|db_high[0]~13, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~3, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[0] , z80_|alu_|op2_high[0], spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~5 , z80_|execute_|ctl_alu_sel_op2_neg~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~9 , z80_|execute_|ctl_alu_sel_op2_neg~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 , z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~7 , z80_|execute_|ctl_alu_sel_op2_neg~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~6 , z80_|execute_|ctl_alu_sel_op2_neg~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~8 , z80_|execute_|ctl_alu_sel_op2_neg~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~11 , z80_|execute_|ctl_alu_sel_op2_neg~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~12 , z80_|execute_|ctl_alu_sel_op2_neg~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~15 , z80_|execute_|ctl_alu_sel_op2_neg~15, spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[0]~1 , z80_|alu_|alu_op2[0]~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[0] , z80_|alu_|result_lo[0], spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~18 , z80_|alu_|db_low[0]~18, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~20 , z80_|alu_|db_low[0]~20, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~21 , z80_|alu_|db_low[0]~21, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~22 , z80_|alu_|db_high[0]~22, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~25 , z80_|alu_|db_high[0]~25, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~26 , z80_|alu_|db_high[0]~26, spectrum, 1 instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|ena , z80_|alu_|b2v_op1_latch_mux_low|ena, spectrum, 1 instance = comp, \z80_|alu_|op1_low[0] , z80_|alu_|op1_low[0], spectrum, 1 -instance = comp, \z80_|alu_|alu_op1[0]~0 , z80_|alu_|alu_op1[0]~0, spectrum, 1 +instance = comp, \z80_|alu_|alu_op1[0]~1 , z80_|alu_|alu_op1[0]~1, spectrum, 1 instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6, spectrum, 1 instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7, spectrum, 1 instance = comp, \z80_|alu_|op2_low[0] , z80_|alu_|op2_low[0], spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0, spectrum, 1 +instance = comp, \z80_|alu_|alu_op1[1]~0 , z80_|alu_|alu_op1[1]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~5 , z80_|execute_|ctl_alu_core_R~5, spectrum, 1 +instance = comp, \z80_|alu_|alu_op1[2]~2 , z80_|alu_|alu_op1[2]~2, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[2] , z80_|alu_|result_lo[2], spectrum, 1 -instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~7 , z80_|alu_|db_low[2]~7, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~8 , z80_|alu_|db_low[2]~8, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] , z80_|reg_file_|b2v_latch_hl2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[2] , z80_|reg_file_|b2v_latch_hl_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~59 , z80_|reg_file_|gdfx_temp1[2]~59, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[2] , z80_|reg_file_|b2v_latch_af2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~62 , z80_|reg_file_|gdfx_temp1[2]~62, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[2] , z80_|reg_file_|b2v_latch_sp_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[2] , z80_|reg_file_|b2v_latch_wz_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~63 , z80_|reg_file_|gdfx_temp1[2]~63, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[2] , z80_|reg_file_|b2v_latch_iy_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[2] , z80_|reg_file_|b2v_latch_ix_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~61 , z80_|reg_file_|gdfx_temp1[2]~61, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] , z80_|reg_file_|b2v_latch_bc2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[2] , z80_|reg_file_|b2v_latch_bc_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~60 , z80_|reg_file_|gdfx_temp1[2]~60, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~64 , z80_|reg_file_|gdfx_temp1[2]~64, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[2] , z80_|reg_file_|b2v_latch_af_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[2]~15 , z80_|reg_file_|b2v_latch_af_hi|db[2]~15, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[2] , z80_|reg_file_|b2v_latch_de_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[2] , z80_|reg_file_|b2v_latch_de2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~58 , z80_|reg_file_|gdfx_temp1[2]~58, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~65 , z80_|reg_file_|gdfx_temp1[2]~65, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~66 , z80_|reg_file_|gdfx_temp1[2]~66, spectrum, 1 -instance = comp, \z80_|alu_|db[2]~11 , z80_|alu_|db[2]~11, spectrum, 1 -instance = comp, \z80_|alu_|db[2]~12 , z80_|alu_|db[2]~12, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~5 , z80_|alu_|db_low[2]~5, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~6 , z80_|alu_|db_low[2]~6, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~9 , z80_|alu_|db_low[2]~9, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~22 , z80_|alu_|db_low[2]~22, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[2] , z80_|alu_|op1_low[2], spectrum, 1 -instance = comp, \z80_|alu_control_|out[6]~0 , z80_|alu_control_|out[6]~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_66_oe , z80_|execute_|ctl_66_oe, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~19 , z80_|alu_control_|db[2]~19, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~5 , z80_|execute_|ctl_alu_core_R~5, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[7] , z80_|reg_file_|b2v_latch_bc_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] , z80_|reg_file_|b2v_latch_bc2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~69 , z80_|reg_file_|gdfx_temp1[7]~69, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[7] , z80_|reg_file_|b2v_latch_ix_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[7] , z80_|reg_file_|b2v_latch_iy_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~70 , z80_|reg_file_|gdfx_temp1[7]~70, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[7] , z80_|reg_file_|b2v_latch_sp_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[7] , z80_|reg_file_|b2v_latch_wz_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~72 , z80_|reg_file_|gdfx_temp1[7]~72, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[7] , z80_|reg_file_|b2v_latch_af2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~71 , z80_|reg_file_|gdfx_temp1[7]~71, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~73 , z80_|reg_file_|gdfx_temp1[7]~73, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[7] , z80_|reg_file_|b2v_latch_de2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[7] , z80_|reg_file_|b2v_latch_de_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~67 , z80_|reg_file_|gdfx_temp1[7]~67, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[7] , z80_|reg_file_|b2v_latch_af_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 , z80_|reg_file_|b2v_latch_af_hi|db[7]~20, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] , z80_|reg_file_|b2v_latch_hl2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[7] , z80_|reg_file_|b2v_latch_hl_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~68 , z80_|reg_file_|gdfx_temp1[7]~68, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~74 , z80_|reg_file_|gdfx_temp1[7]~74, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[7] , z80_|reg_file_|b2v_latch_ir_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[7]~19 , z80_|reg_file_|db_hi_as[7]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[7] , z80_|reg_file_|b2v_latch_pc_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[7]~20 , z80_|reg_file_|db_hi_as[7]~20, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[5] , z80_|reg_file_|b2v_latch_wz_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[5] , z80_|reg_file_|b2v_latch_sp_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~54 , z80_|reg_file_|gdfx_temp1[5]~54, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[5] , z80_|reg_file_|b2v_latch_af2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~53 , z80_|reg_file_|gdfx_temp1[5]~53, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[5] , z80_|reg_file_|b2v_latch_bc_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] , z80_|reg_file_|b2v_latch_bc2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~51 , z80_|reg_file_|gdfx_temp1[5]~51, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[5] , z80_|reg_file_|b2v_latch_iy_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[5] , z80_|reg_file_|b2v_latch_ix_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~52 , z80_|reg_file_|gdfx_temp1[5]~52, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~55 , z80_|reg_file_|gdfx_temp1[5]~55, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[5] , z80_|reg_file_|b2v_latch_de_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[5] , z80_|reg_file_|b2v_latch_de2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~49 , z80_|reg_file_|gdfx_temp1[5]~49, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[5] , z80_|reg_file_|b2v_latch_hl_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] , z80_|reg_file_|b2v_latch_hl2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~50 , z80_|reg_file_|gdfx_temp1[5]~50, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[5] , z80_|reg_file_|b2v_latch_af_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 , z80_|reg_file_|b2v_latch_af_hi|db[5]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~56 , z80_|reg_file_|gdfx_temp1[5]~56, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~57 , z80_|reg_file_|gdfx_temp1[5]~57, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[5] , z80_|reg_file_|b2v_latch_ir_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[5]~13 , z80_|reg_file_|db_hi_as[5]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[5] , z80_|reg_file_|b2v_latch_pc_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[5]~14 , z80_|reg_file_|db_hi_as[5]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[5]~15 , z80_|reg_file_|db_hi_as[5]~15, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[13] , z80_|address_latch_|abusz[13], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[13]~feeder , z80_|address_latch_|Q[13]~feeder, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[13] , z80_|address_latch_|Q[13], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[15] , z80_|address_latch_|abusz[15], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[15] , z80_|address_latch_|Q[15], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[14] , z80_|address_latch_|b2v_inst_inc_dec|address[14], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[6] , z80_|reg_file_|b2v_latch_pc_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[6] , z80_|reg_file_|b2v_latch_de2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[6] , z80_|reg_file_|b2v_latch_de_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~76 , z80_|reg_file_|gdfx_temp1[6]~76, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[6] , z80_|reg_file_|b2v_latch_af2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~80 , z80_|reg_file_|gdfx_temp1[6]~80, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[6] , z80_|reg_file_|b2v_latch_iy_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[6] , z80_|reg_file_|b2v_latch_ix_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~79 , z80_|reg_file_|gdfx_temp1[6]~79, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] , z80_|reg_file_|b2v_latch_bc2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[6] , z80_|reg_file_|b2v_latch_bc_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~78 , z80_|reg_file_|gdfx_temp1[6]~78, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[6] , z80_|reg_file_|b2v_latch_sp_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[6] , z80_|reg_file_|b2v_latch_wz_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~81 , z80_|reg_file_|gdfx_temp1[6]~81, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~82 , z80_|reg_file_|gdfx_temp1[6]~82, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] , z80_|reg_file_|b2v_latch_hl2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[6] , z80_|reg_file_|b2v_latch_hl_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~77 , z80_|reg_file_|gdfx_temp1[6]~77, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[6] , z80_|reg_file_|b2v_latch_af_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 , z80_|reg_file_|b2v_latch_af_hi|db[6]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~83 , z80_|reg_file_|gdfx_temp1[6]~83, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~84 , z80_|reg_file_|gdfx_temp1[6]~84, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[6] , z80_|reg_file_|b2v_latch_ir_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[6]~22 , z80_|reg_file_|db_hi_as[6]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[6]~23 , z80_|reg_file_|db_hi_as[6]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[6]~24 , z80_|reg_file_|db_hi_as[6]~24, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[14] , z80_|address_latch_|abusz[14], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[14]~feeder , z80_|address_latch_|Q[14]~feeder, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[14] , z80_|address_latch_|Q[14], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[15] , z80_|address_latch_|b2v_inst_inc_dec|address[15], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[7]~21 , z80_|reg_file_|db_hi_as[7]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~75 , z80_|reg_file_|gdfx_temp1[7]~75, spectrum, 1 +instance = comp, \z80_|alu_|db[7]~20 , z80_|alu_|db[7]~20, spectrum, 1 +instance = comp, \z80_|alu_|db[7]~21 , z80_|alu_|db[7]~21, spectrum, 1 +instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~1 , z80_|alu_control_|b2v_inst_shift_mux|out~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~0 , z80_|alu_flags_|DFFE_inst_latch_cf~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~4 , z80_|execute_|ctl_flags_cf_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~5 , z80_|execute_|ctl_flags_cf_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~3 , z80_|execute_|ctl_flags_cf_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~6 , z80_|execute_|ctl_flags_cf_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_we~2 , z80_|execute_|ctl_flags_cf2_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_we~4 , z80_|execute_|ctl_flags_cf2_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_we~3 , z80_|execute_|ctl_flags_cf2_we~3, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~1 , z80_|alu_flags_|DFFE_inst_latch_cf~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf , z80_|alu_flags_|DFFE_inst_latch_cf, spectrum, 1 +instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~0 , z80_|alu_control_|b2v_inst_shift_mux|out~0, spectrum, 1 +instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~2 , z80_|alu_control_|b2v_inst_shift_mux|out~2, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~5 , z80_|alu_|db_high[3]~5, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~6 , z80_|alu_|db_high[3]~6, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~4 , z80_|alu_|db_high[3]~4, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~27 , z80_|alu_|db_high[3]~27, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~7 , z80_|alu_|db_high[3]~7, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~8 , z80_|alu_|db_high[3]~8, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[3] , z80_|alu_|op1_low[3], spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~9 , z80_|alu_|db_low[3]~9, spectrum, 1 +instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~10 , z80_|alu_|db_low[3]~10, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[3] , z80_|alu_|result_lo[3], spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~7 , z80_|alu_|db_low[3]~7, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~8 , z80_|alu_|db_low[3]~8, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~11 , z80_|alu_|db_low[3]~11, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~25 , z80_|alu_|db_low[3]~25, spectrum, 1 +instance = comp, \z80_|alu_|db[3]~10 , z80_|alu_|db[3]~10, spectrum, 1 +instance = comp, \z80_|alu_|db[3]~11 , z80_|alu_|db[3]~11, spectrum, 1 instance = comp, \z80_|execute_|ctl_sw_2u~7 , z80_|execute_|ctl_sw_2u~7, spectrum, 1 -instance = comp, \z80_|alu_control_|db[1]~23 , z80_|alu_control_|db[1]~23, spectrum, 1 -instance = comp, \z80_|alu_control_|db[1]~24 , z80_|alu_control_|db[1]~24, spectrum, 1 -instance = comp, \z80_|alu_control_|db[1]~25 , z80_|alu_control_|db[1]~25, spectrum, 1 -instance = comp, \z80_|alu_control_|db[1]~26 , z80_|alu_control_|db[1]~26, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~29 , z80_|reg_file_|gdfx_temp0[1]~29, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[1] , z80_|reg_file_|b2v_latch_bc_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] , z80_|reg_file_|b2v_latch_bc2_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~26 , z80_|reg_file_|gdfx_temp0[1]~26, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[1] , z80_|reg_file_|b2v_latch_wz_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~27 , z80_|reg_file_|gdfx_temp0[1]~27, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1] , z80_|reg_file_|b2v_latch_af_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[1] , z80_|reg_file_|b2v_latch_af2_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~25 , z80_|reg_file_|gdfx_temp0[1]~25, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[1] , z80_|reg_file_|b2v_latch_ix_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[1] , z80_|reg_file_|b2v_latch_iy_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~28 , z80_|reg_file_|gdfx_temp0[1]~28, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~30 , z80_|reg_file_|gdfx_temp0[1]~30, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[1] , z80_|reg_file_|b2v_latch_hl_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] , z80_|reg_file_|b2v_latch_hl2_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~24 , z80_|reg_file_|gdfx_temp0[1]~24, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[1] , z80_|reg_file_|b2v_latch_de2_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[1] , z80_|reg_file_|b2v_latch_de_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~23 , z80_|reg_file_|gdfx_temp0[1]~23, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~31 , z80_|reg_file_|gdfx_temp0[1]~31, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~32 , z80_|reg_file_|gdfx_temp0[1]~32, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[1] , z80_|reg_file_|b2v_latch_pc_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[1]~4 , z80_|reg_file_|db_lo_as[1]~4, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[1]~5 , z80_|reg_file_|db_lo_as[1]~5, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[1]~6 , z80_|reg_file_|db_lo_as[1]~6, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[1] , z80_|address_latch_|abusz[1], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[1]~feeder , z80_|address_latch_|Q[1]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[1] , z80_|address_latch_|Q[1], spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~10 , z80_|execute_|ctl_inc_dec~10, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[2] , z80_|reg_file_|b2v_latch_ir_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[2] , z80_|reg_file_|b2v_latch_hl_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] , z80_|reg_file_|b2v_latch_hl2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~34 , z80_|reg_file_|gdfx_temp0[2]~34, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[2] , z80_|reg_file_|b2v_latch_de_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[2] , z80_|reg_file_|b2v_latch_de2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~33 , z80_|reg_file_|gdfx_temp0[2]~33, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[2] , z80_|reg_file_|b2v_latch_af2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[2] , z80_|reg_file_|b2v_latch_af_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~35 , z80_|reg_file_|gdfx_temp0[2]~35, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[2] , z80_|reg_file_|b2v_latch_sp_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~39 , z80_|reg_file_|gdfx_temp0[2]~39, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[2] , z80_|reg_file_|b2v_latch_ix_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[2] , z80_|reg_file_|b2v_latch_iy_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~38 , z80_|reg_file_|gdfx_temp0[2]~38, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[2] , z80_|reg_file_|b2v_latch_bc_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] , z80_|reg_file_|b2v_latch_bc2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~36 , z80_|reg_file_|gdfx_temp0[2]~36, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[2] , z80_|reg_file_|b2v_latch_wz_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~37 , z80_|reg_file_|gdfx_temp0[2]~37, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~40 , z80_|reg_file_|gdfx_temp0[2]~40, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~41 , z80_|reg_file_|gdfx_temp0[2]~41, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~42 , z80_|reg_file_|gdfx_temp0[2]~42, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[2] , z80_|reg_file_|b2v_latch_pc_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[2]~7 , z80_|reg_file_|db_lo_as[2]~7, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[2]~8 , z80_|reg_file_|db_lo_as[2]~8, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[2]~9 , z80_|reg_file_|db_lo_as[2]~9, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[2] , z80_|address_latch_|abusz[2], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[2] , z80_|address_latch_|Q[2], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[3] , z80_|address_latch_|abusz[3], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[3] , z80_|address_latch_|Q[3], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[4] , z80_|reg_file_|b2v_latch_ir_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[4] , z80_|reg_file_|b2v_latch_pc_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[4]~13 , z80_|reg_file_|db_lo_as[4]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[4]~14 , z80_|reg_file_|db_lo_as[4]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[4]~15 , z80_|reg_file_|db_lo_as[4]~15, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[4] , z80_|reg_file_|b2v_latch_de_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[4] , z80_|reg_file_|b2v_latch_de2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~53 , z80_|reg_file_|gdfx_temp0[4]~53, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~54 , z80_|reg_file_|gdfx_temp0[4]~54, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[4] , z80_|reg_file_|b2v_latch_hl_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] , z80_|reg_file_|b2v_latch_hl2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~57 , z80_|reg_file_|gdfx_temp0[4]~57, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[4] , z80_|reg_file_|b2v_latch_ix_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[4] , z80_|reg_file_|b2v_latch_sp_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[4] , z80_|reg_file_|b2v_latch_iy_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~55 , z80_|reg_file_|gdfx_temp0[4]~55, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~56 , z80_|reg_file_|gdfx_temp0[4]~56, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[4] , z80_|reg_file_|b2v_latch_bc_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] , z80_|reg_file_|b2v_latch_bc2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~59 , z80_|reg_file_|gdfx_temp0[4]~59, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[4] , z80_|reg_file_|b2v_latch_wz_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[4] , z80_|reg_file_|b2v_latch_af2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[4] , z80_|reg_file_|b2v_latch_af_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~58 , z80_|reg_file_|gdfx_temp0[4]~58, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~60 , z80_|reg_file_|gdfx_temp0[4]~60, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~61 , z80_|reg_file_|gdfx_temp0[4]~61, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~62 , z80_|reg_file_|gdfx_temp0[4]~62, spectrum, 1 -instance = comp, \z80_|alu_control_|db[4]~30 , z80_|alu_control_|db[4]~30, spectrum, 1 -instance = comp, \z80_|alu_control_|db[4]~31 , z80_|alu_control_|db[4]~31, spectrum, 1 -instance = comp, \z80_|alu_control_|db[4]~32 , z80_|alu_control_|db[4]~32, spectrum, 1 -instance = comp, \z80_|alu_|db[4]~8 , z80_|alu_|db[4]~8, spectrum, 1 -instance = comp, \z80_|alu_|db[4]~10 , z80_|alu_|db[4]~10, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~4 , z80_|alu_|db_high[1]~4, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~5 , z80_|alu_|db_high[1]~5, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~6 , z80_|alu_|db_high[1]~6, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~7 , z80_|alu_|db_high[1]~7, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[1] , z80_|alu_|op1_low[1], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[1] , z80_|alu_|op2_low[1], spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[1]~0 , z80_|alu_|alu_op2[1]~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[1] , z80_|alu_|result_lo[1], spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~11 , z80_|alu_|db_low[1]~11, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~12 , z80_|alu_|db_low[1]~12, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~13 , z80_|alu_|db_low[1]~13, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~14 , z80_|alu_|db_low[1]~14, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~15 , z80_|alu_|db_low[1]~15, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11 , z80_|alu_flags_|SYNTHESIZED_WIRE_11, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~8 , z80_|execute_|ctl_flags_sz_we~8, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_39 , z80_|alu_flags_|SYNTHESIZED_WIRE_39, spectrum, 1 -instance = comp, \z80_|alu_control_|out[6]~1 , z80_|alu_control_|out[6]~1, spectrum, 1 -instance = comp, \z80_|alu_control_|out[6]~2 , z80_|alu_control_|out[6]~2, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~13 , z80_|alu_control_|db[6]~13, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~14 , z80_|alu_control_|db[6]~14, spectrum, 1 +instance = comp, \z80_|execute_|setM1~49 , z80_|execute_|setM1~49, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_oe~2 , z80_|execute_|ctl_flags_oe~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_35 , z80_|alu_flags_|SYNTHESIZED_WIRE_35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~7 , z80_|execute_|ctl_flags_sz_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 , z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~13 , z80_|execute_|ctl_flags_xy_we~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~14 , z80_|execute_|ctl_flags_xy_we~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~15 , z80_|execute_|ctl_flags_xy_we~15, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_xf , z80_|alu_flags_|flags_xf, spectrum, 1 +instance = comp, \z80_|alu_control_|db[3]~33 , z80_|alu_control_|db[3]~33, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_out_lo~3 , z80_|execute_|ctl_reg_out_lo~3, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 , z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_out_lo~4 , z80_|execute_|ctl_reg_out_lo~4, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_out_lo~5 , z80_|execute_|ctl_reg_out_lo~5, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_ds[6]~0 , z80_|reg_file_|db_lo_ds[6]~0, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~15 , z80_|alu_control_|db[6]~15, spectrum, 1 -instance = comp, \z80_|alu_|db[6]~21 , z80_|alu_|db[6]~21, spectrum, 1 -instance = comp, \z80_|alu_|db[6]~22 , z80_|alu_|db[6]~22, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~20 , z80_|alu_|db_high[2]~20, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~21 , z80_|alu_|db_high[2]~21, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~6, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~7, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[2] , z80_|alu_|op2_high[2], spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~22 , z80_|alu_|db_high[2]~22, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~23 , z80_|alu_|db_high[2]~23, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~24 , z80_|alu_|db_high[2]~24, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[2] , z80_|alu_|b2v_op1_latch_mux_high|Q[2], spectrum, 1 -instance = comp, \z80_|alu_|op1_high[2] , z80_|alu_|op1_high[2], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[2] , z80_|alu_|op2_low[2], spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[2]~2 , z80_|alu_|alu_op2[2]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~0 , z80_|alu_flags_|DFFE_inst_latch_cf~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_we~0 , z80_|execute_|ctl_flags_cf2_we~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_we~1 , z80_|execute_|ctl_flags_cf2_we~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~1 , z80_|alu_flags_|DFFE_inst_latch_cf~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf , z80_|alu_flags_|DFFE_inst_latch_cf, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~0 , z80_|alu_flags_|DFFE_inst_latch_cf2~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~1 , z80_|alu_flags_|DFFE_inst_latch_cf2~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~2 , z80_|alu_flags_|DFFE_inst_latch_cf2~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~3 , z80_|alu_flags_|DFFE_inst_latch_cf2~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2 , z80_|alu_flags_|DFFE_inst_latch_cf2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~12, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~37 , z80_|execute_|ctl_alu_op_low~37, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~13, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~14, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~17, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~6 , z80_|execute_|ctl_flags_cf_cpl~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~16 , z80_|execute_|ctl_alu_sel_op2_neg~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~5 , z80_|execute_|ctl_flags_cf_cpl~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~7 , z80_|execute_|ctl_flags_cf_cpl~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~8 , z80_|execute_|ctl_flags_cf_cpl~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~11 , z80_|execute_|ctl_flags_cf_cpl~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~9 , z80_|execute_|ctl_flags_cf_cpl~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~10 , z80_|execute_|ctl_flags_cf_cpl~10, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_cf , z80_|alu_flags_|flags_cf, spectrum, 1 -instance = comp, \z80_|alu_control_|db[0]~8 , z80_|alu_control_|db[0]~8, spectrum, 1 -instance = comp, \z80_|sw2_|db_up[0]~0 , z80_|sw2_|db_up[0]~0, spectrum, 1 -instance = comp, \z80_|alu_control_|db[0]~9 , z80_|alu_control_|db[0]~9, spectrum, 1 -instance = comp, \z80_|alu_control_|db[0]~12 , z80_|alu_control_|db[0]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] , z80_|reg_file_|b2v_latch_bc2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~12 , z80_|reg_file_|gdfx_temp0[0]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[0] , z80_|reg_file_|b2v_latch_af_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[0] , z80_|reg_file_|b2v_latch_af2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~13 , z80_|reg_file_|gdfx_temp0[0]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[0] , z80_|reg_file_|b2v_latch_sp_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[0] , z80_|reg_file_|b2v_latch_iy_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~15 , z80_|reg_file_|gdfx_temp0[0]~15, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[0] , z80_|reg_file_|b2v_latch_bc_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[0] , z80_|reg_file_|b2v_latch_ix_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~14 , z80_|reg_file_|gdfx_temp0[0]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[0] , z80_|reg_file_|b2v_latch_wz_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~16 , z80_|reg_file_|gdfx_temp0[0]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~17 , z80_|reg_file_|gdfx_temp0[0]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~22 , z80_|reg_file_|gdfx_temp0[0]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[0] , z80_|reg_file_|b2v_latch_pc_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~0 , z80_|reg_file_|db_lo_as[0]~0, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~1 , z80_|reg_file_|db_lo_as[0]~1, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~3 , z80_|reg_file_|db_lo_as[0]~3, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[0] , z80_|address_latch_|abusz[0], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[0] , z80_|address_latch_|Q[0], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[3]~12 , z80_|reg_file_|db_lo_as[3]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[3] , z80_|reg_file_|b2v_latch_af2_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[3] , z80_|reg_file_|b2v_latch_af_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~45 , z80_|reg_file_|gdfx_temp0[3]~45, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[3] , z80_|reg_file_|b2v_latch_ix_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[3] , z80_|reg_file_|b2v_latch_bc_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~48 , z80_|reg_file_|gdfx_temp0[3]~48, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] , z80_|reg_file_|b2v_latch_bc2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~8 , z80_|execute_|ctl_reg_out_lo~8, spectrum, 1 +instance = comp, \z80_|sw1_|db_down[3]~1 , z80_|sw1_|db_down[3]~1, spectrum, 1 +instance = comp, \z80_|alu_control_|db[3]~34 , z80_|alu_control_|db[3]~34, spectrum, 1 +instance = comp, \z80_|alu_control_|db[3]~35 , z80_|alu_control_|db[3]~35, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[3]~46 , z80_|reg_file_|gdfx_temp0[3]~46, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[3] , z80_|reg_file_|b2v_latch_wz_lo|latch[3], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[3]~47 , z80_|reg_file_|gdfx_temp0[3]~47, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[3] , z80_|reg_file_|b2v_latch_iy_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[3] , z80_|reg_file_|b2v_latch_sp_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~49 , z80_|reg_file_|gdfx_temp0[3]~49, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[3]~50 , z80_|reg_file_|gdfx_temp0[3]~50, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[3] , z80_|reg_file_|b2v_latch_hl_lo|latch[3], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] , z80_|reg_file_|b2v_latch_hl2_lo|latch[3], spectrum, 1 @@ -1955,266 +1702,381 @@ instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[3] , z80_|reg_file_|b2v_ instance = comp, \z80_|reg_file_|gdfx_temp0[3]~43 , z80_|reg_file_|gdfx_temp0[3]~43, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[3]~51 , z80_|reg_file_|gdfx_temp0[3]~51, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[3]~52 , z80_|reg_file_|gdfx_temp0[3]~52, spectrum, 1 -instance = comp, \z80_|sw1_|db_down[3]~2 , z80_|sw1_|db_down[3]~2, spectrum, 1 -instance = comp, \z80_|alu_control_|db[3]~34 , z80_|alu_control_|db[3]~34, spectrum, 1 -instance = comp, \z80_|alu_control_|db[3]~35 , z80_|alu_control_|db[3]~35, spectrum, 1 -instance = comp, \z80_|alu_|db[3]~14 , z80_|alu_|db[3]~14, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~0 , z80_|alu_|db_low[3]~0, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~1 , z80_|alu_|db_low[3]~1, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~23 , z80_|alu_|db_low[3]~23, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[3] , z80_|alu_|op2_low[3], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~4, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~5, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[3] , z80_|alu_|op2_high[3], spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[3]~3 , z80_|alu_|alu_op2[3]~3, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~14 , z80_|alu_|db_high[3]~14, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~15 , z80_|alu_|db_high[3]~15, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~16 , z80_|alu_|db_high[3]~16, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~17 , z80_|alu_|db_high[3]~17, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~18 , z80_|alu_|db_high[3]~18, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~19 , z80_|alu_|db_high[3]~19, spectrum, 1 -instance = comp, \z80_|alu_|db[7]~20 , z80_|alu_|db[7]~20, spectrum, 1 -instance = comp, \z80_|alu_control_|db[7]~16 , z80_|alu_control_|db[7]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_ds[7]~1 , z80_|reg_file_|db_lo_ds[7]~1, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[3] , z80_|reg_file_|b2v_latch_pc_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[3]~10 , z80_|reg_file_|db_lo_as[3]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[3] , z80_|reg_file_|b2v_latch_ir_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[3]~11 , z80_|reg_file_|db_lo_as[3]~11, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[3]~12 , z80_|reg_file_|db_lo_as[3]~12, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[3] , z80_|address_latch_|abusz[3], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[3] , z80_|address_latch_|Q[3], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[4] , z80_|reg_file_|b2v_latch_de_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[4] , z80_|reg_file_|b2v_latch_de2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~53 , z80_|reg_file_|gdfx_temp0[4]~53, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~54 , z80_|reg_file_|gdfx_temp0[4]~54, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[4] , z80_|reg_file_|b2v_latch_af2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[4] , z80_|reg_file_|b2v_latch_af_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~58 , z80_|reg_file_|gdfx_temp0[4]~58, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[4] , z80_|reg_file_|b2v_latch_wz_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] , z80_|reg_file_|b2v_latch_bc2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[4] , z80_|reg_file_|b2v_latch_bc_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~59 , z80_|reg_file_|gdfx_temp0[4]~59, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~60 , z80_|reg_file_|gdfx_temp0[4]~60, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] , z80_|reg_file_|b2v_latch_hl2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[4] , z80_|reg_file_|b2v_latch_hl_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~57 , z80_|reg_file_|gdfx_temp0[4]~57, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[4] , z80_|reg_file_|b2v_latch_iy_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[4] , z80_|reg_file_|b2v_latch_sp_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~55 , z80_|reg_file_|gdfx_temp0[4]~55, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[4] , z80_|reg_file_|b2v_latch_ix_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~56 , z80_|reg_file_|gdfx_temp0[4]~56, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~61 , z80_|reg_file_|gdfx_temp0[4]~61, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~62 , z80_|reg_file_|gdfx_temp0[4]~62, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[4] , z80_|reg_file_|b2v_latch_pc_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[4]~13 , z80_|reg_file_|db_lo_as[4]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[4] , z80_|reg_file_|b2v_latch_ir_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[4]~14 , z80_|reg_file_|db_lo_as[4]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[4]~15 , z80_|reg_file_|db_lo_as[4]~15, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[4] , z80_|address_latch_|abusz[4], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[4] , z80_|address_latch_|Q[4], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[5] , z80_|reg_file_|b2v_latch_hl_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] , z80_|reg_file_|b2v_latch_hl2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~64 , z80_|reg_file_|gdfx_temp0[5]~64, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[5] , z80_|reg_file_|b2v_latch_de_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[5] , z80_|reg_file_|b2v_latch_de2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~63 , z80_|reg_file_|gdfx_temp0[5]~63, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[5] , z80_|reg_file_|b2v_latch_wz_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] , z80_|reg_file_|b2v_latch_bc2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~66 , z80_|reg_file_|gdfx_temp0[5]~66, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~67 , z80_|reg_file_|gdfx_temp0[5]~67, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[5] , z80_|reg_file_|b2v_latch_af2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[5] , z80_|reg_file_|b2v_latch_af_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~65 , z80_|reg_file_|gdfx_temp0[5]~65, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[5] , z80_|reg_file_|b2v_latch_sp_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[5] , z80_|reg_file_|b2v_latch_iy_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~69 , z80_|reg_file_|gdfx_temp0[5]~69, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder , z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[5] , z80_|reg_file_|b2v_latch_ix_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[5] , z80_|reg_file_|b2v_latch_bc_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~68 , z80_|reg_file_|gdfx_temp0[5]~68, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~70 , z80_|reg_file_|gdfx_temp0[5]~70, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~71 , z80_|reg_file_|gdfx_temp0[5]~71, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~72 , z80_|reg_file_|gdfx_temp0[5]~72, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[5] , z80_|reg_file_|b2v_latch_pc_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[5]~16 , z80_|reg_file_|db_lo_as[5]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[5] , z80_|reg_file_|b2v_latch_ir_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[5]~17 , z80_|reg_file_|db_lo_as[5]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[5]~18 , z80_|reg_file_|db_lo_as[5]~18, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[5] , z80_|address_latch_|abusz[5], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[5] , z80_|address_latch_|Q[5], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[6] , z80_|address_latch_|b2v_inst_inc_dec|address[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[6] , z80_|reg_file_|b2v_latch_ir_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] , z80_|reg_file_|b2v_latch_hl2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[6] , z80_|reg_file_|b2v_latch_hl_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~74 , z80_|reg_file_|gdfx_temp0[6]~74, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[6] , z80_|reg_file_|b2v_latch_de_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[6] , z80_|reg_file_|b2v_latch_de2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~73 , z80_|reg_file_|gdfx_temp0[6]~73, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[6] , z80_|reg_file_|b2v_latch_ix_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[6] , z80_|reg_file_|b2v_latch_iy_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~78 , z80_|reg_file_|gdfx_temp0[6]~78, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[6] , z80_|reg_file_|b2v_latch_sp_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~79 , z80_|reg_file_|gdfx_temp0[6]~79, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[6] , z80_|reg_file_|b2v_latch_wz_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[6] , z80_|reg_file_|b2v_latch_bc_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] , z80_|reg_file_|b2v_latch_bc2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~76 , z80_|reg_file_|gdfx_temp0[6]~76, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~77 , z80_|reg_file_|gdfx_temp0[6]~77, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~80 , z80_|reg_file_|gdfx_temp0[6]~80, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[6] , z80_|reg_file_|b2v_latch_af2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[6] , z80_|reg_file_|b2v_latch_af_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~75 , z80_|reg_file_|gdfx_temp0[6]~75, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~81 , z80_|reg_file_|gdfx_temp0[6]~81, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~82 , z80_|reg_file_|gdfx_temp0[6]~82, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[6] , z80_|reg_file_|b2v_latch_pc_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[6]~19 , z80_|reg_file_|db_lo_as[6]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[6]~20 , z80_|reg_file_|db_lo_as[6]~20, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[6]~21 , z80_|reg_file_|db_lo_as[6]~21, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[6] , z80_|address_latch_|abusz[6], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[6] , z80_|address_latch_|Q[6], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[7]~24 , z80_|reg_file_|db_lo_as[7]~24, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[7] , z80_|reg_file_|b2v_latch_de_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[7] , z80_|reg_file_|b2v_latch_de2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~83 , z80_|reg_file_|gdfx_temp0[7]~83, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] , z80_|reg_file_|b2v_latch_hl2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[7] , z80_|reg_file_|b2v_latch_hl_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~84 , z80_|reg_file_|gdfx_temp0[7]~84, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[7] , z80_|reg_file_|b2v_latch_ix_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[7] , z80_|reg_file_|b2v_latch_iy_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~88 , z80_|reg_file_|gdfx_temp0[7]~88, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[7] , z80_|reg_file_|b2v_latch_wz_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[7] , z80_|reg_file_|b2v_latch_bc_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] , z80_|reg_file_|b2v_latch_bc2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~86 , z80_|reg_file_|gdfx_temp0[7]~86, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~87 , z80_|reg_file_|gdfx_temp0[7]~87, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[7] , z80_|reg_file_|b2v_latch_af2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[7] , z80_|reg_file_|b2v_latch_af_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~85 , z80_|reg_file_|gdfx_temp0[7]~85, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[7] , z80_|reg_file_|b2v_latch_sp_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~89 , z80_|reg_file_|gdfx_temp0[7]~89, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~90 , z80_|reg_file_|gdfx_temp0[7]~90, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~91 , z80_|reg_file_|gdfx_temp0[7]~91, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~92 , z80_|reg_file_|gdfx_temp0[7]~92, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_ds[7]~0 , z80_|reg_file_|db_lo_ds[7]~0, spectrum, 1 +instance = comp, \z80_|interrupts_|im2 , z80_|interrupts_|im2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~12 , z80_|execute_|ctl_mRead~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_mask543_en~0 , z80_|execute_|ctl_sw_mask543_en~0, spectrum, 1 instance = comp, \z80_|alu_control_|db[7]~17 , z80_|alu_control_|db[7]~17, spectrum, 1 +instance = comp, \z80_|alu_control_|db[7]~16 , z80_|alu_control_|db[7]~16, spectrum, 1 instance = comp, \z80_|alu_control_|db[7]~18 , z80_|alu_control_|db[7]~18, spectrum, 1 instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_34 , z80_|alu_flags_|SYNTHESIZED_WIRE_34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~8 , z80_|execute_|ctl_flags_sz_we~8, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_sf , z80_|alu_flags_|DFFE_inst_latch_sf, spectrum, 1 -instance = comp, \z80_|alu_control_|sel[1]~0 , z80_|alu_control_|sel[1]~0, spectrum, 1 -instance = comp, \z80_|alu_control_|b2v_inst_cond_mux|out~0 , z80_|alu_control_|b2v_inst_cond_mux|out~0, spectrum, 1 -instance = comp, \z80_|alu_|alu_parity_out~0 , z80_|alu_|alu_parity_out~0, spectrum, 1 -instance = comp, \z80_|alu_|alu_parity_out , z80_|alu_|alu_parity_out, spectrum, 1 -instance = comp, \z80_|alu_control_|DFFE_latch_pf_tmp , z80_|alu_control_|DFFE_latch_pf_tmp, spectrum, 1 instance = comp, \z80_|pla_decode_|Equal62~3 , z80_|pla_decode_|Equal62~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~4 , z80_|alu_flags_|DFFE_inst_latch_pf~4, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~5 , z80_|alu_flags_|DFFE_inst_latch_pf~5, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~6 , z80_|alu_flags_|DFFE_inst_latch_pf~6, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_pf_we~5 , z80_|execute_|ctl_flags_pf_we~5, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_pf_we~6 , z80_|execute_|ctl_flags_pf_we~6, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_pf_we~7 , z80_|execute_|ctl_flags_pf_we~7, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_pf_we~8 , z80_|execute_|ctl_flags_pf_we~8, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_pf_we~9 , z80_|execute_|ctl_flags_pf_we~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~3 , z80_|alu_flags_|DFFE_inst_latch_pf~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~10 , z80_|alu_flags_|DFFE_inst_latch_pf~10, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~11 , z80_|alu_flags_|DFFE_inst_latch_pf~11, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instNonRep~1 , z80_|decode_state_|DFFE_instNonRep~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~0 , z80_|alu_flags_|DFFE_inst_latch_pf~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~4 , z80_|alu_flags_|DFFE_inst_latch_pf~4, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~5 , z80_|alu_flags_|DFFE_inst_latch_pf~5, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~6 , z80_|alu_flags_|DFFE_inst_latch_pf~6, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instNonRep~0 , z80_|decode_state_|DFFE_instNonRep~0, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep~3 , z80_|decode_state_|DFFE_instNonRep~3, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep~2 , z80_|decode_state_|DFFE_instNonRep~2, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[15] , z80_|address_latch_|Q[15], spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instNonRep~0 , z80_|decode_state_|DFFE_instNonRep~0, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instNonRep~1 , z80_|decode_state_|DFFE_instNonRep~1, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep~4 , z80_|decode_state_|DFFE_instNonRep~4, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep~5 , z80_|decode_state_|DFFE_instNonRep~5, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep , z80_|decode_state_|DFFE_instNonRep, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~12 , z80_|alu_flags_|DFFE_inst_latch_pf~12, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~1 , z80_|alu_flags_|DFFE_inst_latch_pf~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~2 , z80_|alu_flags_|DFFE_inst_latch_pf~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~3 , z80_|alu_flags_|DFFE_inst_latch_pf~3, spectrum, 1 +instance = comp, \z80_|alu_control_|DFFE_latch_pf_tmp , z80_|alu_control_|DFFE_latch_pf_tmp, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0, spectrum, 1 +instance = comp, \z80_|alu_|alu_parity_out~0 , z80_|alu_|alu_parity_out~0, spectrum, 1 +instance = comp, \z80_|alu_|alu_parity_out , z80_|alu_|alu_parity_out, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~7 , z80_|alu_flags_|DFFE_inst_latch_pf~7, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~8 , z80_|alu_flags_|DFFE_inst_latch_pf~8, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~9 , z80_|alu_flags_|DFFE_inst_latch_pf~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~14 , z80_|alu_flags_|DFFE_inst_latch_pf~14, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~2 , z80_|alu_flags_|DFFE_inst_latch_pf~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~13 , z80_|alu_flags_|DFFE_inst_latch_pf~13, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~10 , z80_|alu_flags_|DFFE_inst_latch_pf~10, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf , z80_|alu_flags_|DFFE_inst_latch_pf, spectrum, 1 +instance = comp, \z80_|alu_control_|sel[1]~0 , z80_|alu_control_|sel[1]~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_12 , z80_|alu_flags_|SYNTHESIZED_WIRE_12, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_39 , z80_|alu_flags_|SYNTHESIZED_WIRE_39, spectrum, 1 +instance = comp, \z80_|alu_control_|b2v_inst_cond_mux|out~0 , z80_|alu_control_|b2v_inst_cond_mux|out~0, spectrum, 1 instance = comp, \z80_|alu_control_|b2v_inst_cond_mux|out~1 , z80_|alu_control_|b2v_inst_cond_mux|out~1, spectrum, 1 instance = comp, \z80_|alu_control_|flags_cond_true~0 , z80_|alu_control_|flags_cond_true~0, spectrum, 1 instance = comp, \z80_|alu_control_|flags_cond_true , z80_|alu_control_|flags_cond_true, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~11 , z80_|execute_|ctl_reg_sel_wz~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~13 , z80_|execute_|ctl_reg_sel_wz~13, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_sel_wz~14 , z80_|execute_|ctl_reg_sel_wz~14, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_sel_wz~17 , z80_|execute_|ctl_reg_sel_wz~17, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_80 , z80_|reg_file_|SYNTHESIZED_WIRE_80, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~17 , z80_|reg_file_|gdfx_temp1[0]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~19 , z80_|reg_file_|gdfx_temp1[0]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~16 , z80_|reg_file_|gdfx_temp1[0]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~20 , z80_|reg_file_|gdfx_temp1[0]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] , z80_|reg_file_|b2v_latch_hl2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[1] , z80_|reg_file_|b2v_latch_hl_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~32 , z80_|reg_file_|gdfx_temp1[1]~32, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[1] , z80_|reg_file_|b2v_latch_af_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[1]~13 , z80_|reg_file_|b2v_latch_af_hi|db[1]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] , z80_|reg_file_|b2v_latch_bc2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[1] , z80_|reg_file_|b2v_latch_bc_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~33 , z80_|reg_file_|gdfx_temp1[1]~33, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[1] , z80_|reg_file_|b2v_latch_sp_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[1] , z80_|reg_file_|b2v_latch_wz_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~36 , z80_|reg_file_|gdfx_temp1[1]~36, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[1] , z80_|reg_file_|b2v_latch_iy_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[1] , z80_|reg_file_|b2v_latch_ix_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~34 , z80_|reg_file_|gdfx_temp1[1]~34, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[1] , z80_|reg_file_|b2v_latch_af2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~35 , z80_|reg_file_|gdfx_temp1[1]~35, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~37 , z80_|reg_file_|gdfx_temp1[1]~37, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[1] , z80_|reg_file_|b2v_latch_de_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[1] , z80_|reg_file_|b2v_latch_de2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~31 , z80_|reg_file_|gdfx_temp1[1]~31, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~38 , z80_|reg_file_|gdfx_temp1[1]~38, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~39 , z80_|reg_file_|gdfx_temp1[1]~39, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[1] , z80_|reg_file_|b2v_latch_ir_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[1]~7 , z80_|reg_file_|db_hi_as[1]~7, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[1] , z80_|reg_file_|b2v_latch_pc_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[1]~8 , z80_|reg_file_|db_hi_as[1]~8, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[1]~9 , z80_|reg_file_|db_hi_as[1]~9, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[9] , z80_|address_latch_|abusz[9], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[9] , z80_|address_latch_|Q[9], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[2] , z80_|reg_file_|b2v_latch_ir_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[2]~16 , z80_|reg_file_|db_hi_as[2]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[2] , z80_|reg_file_|b2v_latch_pc_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[2]~17 , z80_|reg_file_|db_hi_as[2]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[2]~18 , z80_|reg_file_|db_hi_as[2]~18, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[10] , z80_|address_latch_|abusz[10], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[10] , z80_|address_latch_|Q[10], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[5] , z80_|reg_file_|b2v_latch_pc_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[5] , z80_|reg_file_|b2v_latch_ir_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[5]~19 , z80_|reg_file_|db_hi_as[5]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[5]~20 , z80_|reg_file_|db_hi_as[5]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[5]~21 , z80_|reg_file_|db_hi_as[5]~21, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[13] , z80_|address_latch_|abusz[13], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[13] , z80_|address_latch_|Q[13], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[15] , z80_|address_latch_|b2v_inst_inc_dec|address[15], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[7] , z80_|reg_file_|b2v_latch_ir_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[7]~4 , z80_|reg_file_|db_hi_as[7]~4, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[7] , z80_|reg_file_|b2v_latch_pc_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[7]~5 , z80_|reg_file_|db_hi_as[7]~5, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[7]~6 , z80_|reg_file_|db_hi_as[7]~6, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[15] , z80_|address_latch_|abusz[15], spectrum, 1 -instance = comp, \z80_|execute_|ctl_apin_mux~2 , z80_|execute_|ctl_apin_mux~2, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[15]~15 , z80_|address_pins_|DFFE_apin_latch[15]~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_apin_mux2~0 , z80_|execute_|ctl_apin_mux2~0, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~1 , z80_|execute_|fIORead~1, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~2 , z80_|execute_|fIORead~2, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~0 , z80_|execute_|fIORead~0, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~3 , z80_|execute_|fIORead~3, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_ab_pin_we~2 , z80_|pin_control_|bus_ab_pin_we~2, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_ab_pin_we~3 , z80_|pin_control_|bus_ab_pin_we~3, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[15] , z80_|address_pins_|DFFE_apin_latch[15], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[15]~17 , z80_|address_pins_|abus[15]~17, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0]~15 , ula_|zx_keyboard_|keys[0][0]~15, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~0 , ula_|zx_keyboard_|shifted~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr17~0 , ula_|zx_keyboard_|WideOr17~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~2 , ula_|zx_keyboard_|shifted~2, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~3 , ula_|zx_keyboard_|shifted~3, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted , ula_|zx_keyboard_|shifted, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~40 , ula_|zx_keyboard_|keys[6][1]~40, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~41 , ula_|zx_keyboard_|keys[6][1]~41, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~42 , ula_|zx_keyboard_|keys[6][1]~42, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~43 , ula_|zx_keyboard_|keys[6][1]~43, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~44 , ula_|zx_keyboard_|keys[6][1]~44, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1] , ula_|zx_keyboard_|keys[6][1], spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[14]~14 , z80_|address_pins_|DFFE_apin_latch[14]~14, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[14] , z80_|address_pins_|DFFE_apin_latch[14], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[14]~16 , z80_|address_pins_|abus[14]~16, spectrum, 1 -instance = comp, \D[1]~27 , D[1]~27, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1]~19 , ula_|zx_keyboard_|keys[7][1]~19, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~24 , ula_|zx_keyboard_|keys[5][4]~24, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][4]~25 , ula_|zx_keyboard_|keys[1][4]~25, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][1]~26 , ula_|zx_keyboard_|keys[2][1]~26, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][1]~27 , ula_|zx_keyboard_|keys[2][1]~27, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][1] , ula_|zx_keyboard_|keys[2][1], spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[10]~10 , z80_|address_pins_|DFFE_apin_latch[10]~10, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[10] , z80_|address_pins_|DFFE_apin_latch[10], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[10]~22 , z80_|address_pins_|abus[10]~22, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1]~29 , ula_|zx_keyboard_|keys[3][1]~29, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1]~28 , ula_|zx_keyboard_|keys[3][1]~28, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1]~30 , ula_|zx_keyboard_|keys[3][1]~30, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1] , ula_|zx_keyboard_|keys[3][1], spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[11]~11 , z80_|address_pins_|DFFE_apin_latch[11]~11, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[11] , z80_|address_pins_|DFFE_apin_latch[11], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[11]~21 , z80_|address_pins_|abus[11]~21, spectrum, 1 -instance = comp, \D[1]~25 , D[1]~25, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][1]~31 , ula_|zx_keyboard_|keys[4][1]~31, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~32 , ula_|zx_keyboard_|keys[7][2]~32, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2]~33 , ula_|zx_keyboard_|keys[5][2]~33, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][1]~34 , ula_|zx_keyboard_|keys[4][1]~34, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][1] , ula_|zx_keyboard_|keys[4][1], spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[12]~12 , z80_|address_pins_|DFFE_apin_latch[12]~12, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[12] , z80_|address_pins_|DFFE_apin_latch[12], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[12]~24 , z80_|address_pins_|abus[12]~24, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[13]~13 , z80_|address_pins_|DFFE_apin_latch[13]~13, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[13] , z80_|address_pins_|DFFE_apin_latch[13], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[13]~23 , z80_|address_pins_|abus[13]~23, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~38 , ula_|zx_keyboard_|keys[5][1]~38, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~36 , ula_|zx_keyboard_|keys[5][1]~36, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~37 , ula_|zx_keyboard_|keys[5][1]~37, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~35 , ula_|zx_keyboard_|keys[5][1]~35, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~39 , ula_|zx_keyboard_|keys[5][1]~39, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1] , ula_|zx_keyboard_|keys[5][1], spectrum, 1 -instance = comp, \D[1]~26 , D[1]~26, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[9]~9 , z80_|address_pins_|DFFE_apin_latch[9]~9, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[9] , z80_|address_pins_|DFFE_apin_latch[9], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[9]~19 , z80_|address_pins_|abus[9]~19, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[8]~8 , z80_|address_pins_|DFFE_apin_latch[8]~8, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[8] , z80_|address_pins_|DFFE_apin_latch[8], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[8]~20 , z80_|address_pins_|abus[8]~20, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~14 , ula_|zx_keyboard_|keys[0][1]~14, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~16 , ula_|zx_keyboard_|keys[0][1]~16, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~17 , ula_|zx_keyboard_|keys[0][1]~17, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~18 , ula_|zx_keyboard_|keys[0][1]~18, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1] , ula_|zx_keyboard_|keys[0][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][1]~20 , ula_|zx_keyboard_|keys[1][1]~20, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~21 , ula_|zx_keyboard_|keys[6][4]~21, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][1]~22 , ula_|zx_keyboard_|keys[1][1]~22, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][1]~23 , ula_|zx_keyboard_|keys[1][1]~23, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][1] , ula_|zx_keyboard_|keys[1][1], spectrum, 1 -instance = comp, \D[1]~24 , D[1]~24, spectrum, 1 -instance = comp, \D[1]~28 , D[1]~28, spectrum, 1 -instance = comp, \z80_|clk_delay_|DFF_inst5~feeder , z80_|clk_delay_|DFF_inst5~feeder, spectrum, 1 -instance = comp, \z80_|clk_delay_|DFF_inst5 , z80_|clk_delay_|DFF_inst5, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_iorqinta~feeder , z80_|memory_ifc_|wait_iorqinta~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_iorqinta , z80_|memory_ifc_|wait_iorqinta, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_intr_ff3 , z80_|memory_ifc_|DFFE_intr_ff3, spectrum, 1 -instance = comp, \z80_|execute_|nextM~6 , z80_|execute_|nextM~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~8 , z80_|execute_|ctl_iorw~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~9 , z80_|execute_|ctl_iorw~9, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff1 , z80_|memory_ifc_|DFFE_iorq_ff1, spectrum, 1 -instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder , z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 , z80_|memory_ifc_|SYNTHESIZED_WIRE_15, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_iorq~feeder , z80_|memory_ifc_|wait_iorq~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_iorq , z80_|memory_ifc_|wait_iorq, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff4 , z80_|memory_ifc_|DFFE_iorq_ff4, spectrum, 1 -instance = comp, \z80_|memory_ifc_|iorq~0 , z80_|memory_ifc_|iorq~0, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nIORQ_out~0 , z80_|memory_ifc_|nIORQ_out~0, spectrum, 1 -instance = comp, \z80_|execute_|setM1~38 , z80_|execute_|setM1~38, spectrum, 1 -instance = comp, \z80_|execute_|setM1~57 , z80_|execute_|setM1~57, spectrum, 1 -instance = comp, \z80_|execute_|setM1~39 , z80_|execute_|setM1~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~36 , z80_|execute_|ctl_mRead~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~34 , z80_|execute_|ctl_mRead~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~35 , z80_|execute_|ctl_mRead~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~40 , z80_|execute_|ctl_mRead~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~39 , z80_|execute_|ctl_mRead~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~30 , z80_|execute_|ctl_mRead~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~31 , z80_|execute_|ctl_mRead~31, spectrum, 1 -instance = comp, \z80_|execute_|nextM~4 , z80_|execute_|nextM~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~33 , z80_|execute_|ctl_mRead~33, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_82 , z80_|reg_file_|SYNTHESIZED_WIRE_82, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~18 , z80_|reg_file_|gdfx_temp0[0]~18, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~20 , z80_|reg_file_|gdfx_temp0[0]~20, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~21 , z80_|reg_file_|gdfx_temp0[0]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[1] , z80_|reg_file_|b2v_latch_iy_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[1] , z80_|reg_file_|b2v_latch_ix_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~28 , z80_|reg_file_|gdfx_temp0[1]~28, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[1] , z80_|reg_file_|b2v_latch_wz_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] , z80_|reg_file_|b2v_latch_bc2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[1] , z80_|reg_file_|b2v_latch_bc_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~26 , z80_|reg_file_|gdfx_temp0[1]~26, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~27 , z80_|reg_file_|gdfx_temp0[1]~27, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[1] , z80_|reg_file_|b2v_latch_sp_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~29 , z80_|reg_file_|gdfx_temp0[1]~29, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[1] , z80_|reg_file_|b2v_latch_af2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1] , z80_|reg_file_|b2v_latch_af_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~25 , z80_|reg_file_|gdfx_temp0[1]~25, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~30 , z80_|reg_file_|gdfx_temp0[1]~30, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[1] , z80_|reg_file_|b2v_latch_hl_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] , z80_|reg_file_|b2v_latch_hl2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~24 , z80_|reg_file_|gdfx_temp0[1]~24, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[1] , z80_|reg_file_|b2v_latch_de_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[1] , z80_|reg_file_|b2v_latch_de2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~23 , z80_|reg_file_|gdfx_temp0[1]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~31 , z80_|reg_file_|gdfx_temp0[1]~31, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~32 , z80_|reg_file_|gdfx_temp0[1]~32, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_ds[1]~1 , z80_|reg_file_|db_lo_ds[1]~1, spectrum, 1 +instance = comp, \z80_|alu_control_|db[1]~25 , z80_|alu_control_|db[1]~25, spectrum, 1 +instance = comp, \z80_|alu_control_|db[1]~24 , z80_|alu_control_|db[1]~24, spectrum, 1 +instance = comp, \z80_|alu_control_|db[1]~26 , z80_|alu_control_|db[1]~26, spectrum, 1 +instance = comp, \z80_|alu_|db[1]~12 , z80_|alu_|db[1]~12, spectrum, 1 +instance = comp, \z80_|alu_|db[1]~13 , z80_|alu_|db[1]~13, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~21 , z80_|alu_|db_low[0]~21, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~22 , z80_|alu_|db_low[0]~22, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~18 , z80_|alu_|db_low[0]~18, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~19 , z80_|alu_|db_low[0]~19, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[0] , z80_|alu_|result_lo[0], spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~20 , z80_|alu_|db_low[0]~20, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~23 , z80_|alu_|db_low[0]~23, spectrum, 1 +instance = comp, \z80_|alu_|db[0]~18 , z80_|alu_|db[0]~18, spectrum, 1 +instance = comp, \z80_|alu_|db[0]~19 , z80_|alu_|db[0]~19, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~15 , z80_|alu_|db_low[1]~15, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~16 , z80_|alu_|db_low[1]~16, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~12 , z80_|alu_|db_low[1]~12, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~13 , z80_|alu_|db_low[1]~13, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[1] , z80_|alu_|result_lo[1], spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~14 , z80_|alu_|db_low[1]~14, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~17 , z80_|alu_|db_low[1]~17, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[1] , z80_|alu_|op1_low[1], spectrum, 1 +instance = comp, \z80_|alu_control_|out[6]~0 , z80_|alu_control_|out[6]~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~2 , z80_|alu_flags_|DFFE_inst_latch_cf~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_hf2~0 , z80_|alu_flags_|flags_hf2~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_hf2 , z80_|alu_flags_|flags_hf2, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~23 , z80_|alu_control_|db[2]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_ds[2]~2 , z80_|reg_file_|db_lo_ds[2]~2, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~28 , z80_|alu_control_|db[2]~28, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~27 , z80_|alu_control_|db[2]~27, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~29 , z80_|alu_control_|db[2]~29, spectrum, 1 +instance = comp, \z80_|alu_|db[2]~14 , z80_|alu_|db[2]~14, spectrum, 1 +instance = comp, \z80_|alu_|db[2]~15 , z80_|alu_|db[2]~15, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~2 , z80_|alu_|db_low[2]~2, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~3 , z80_|alu_|db_low[2]~3, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[2] , z80_|alu_|op1_low[2], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[2] , z80_|alu_|op2_low[2], spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~5 , z80_|alu_|db_low[2]~5, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[2] , z80_|alu_|result_lo[2], spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~6 , z80_|alu_|db_low[2]~6, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[2] , z80_|alu_|op2_high[2], spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[2]~0 , z80_|alu_|alu_op2[2]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~9 , z80_|alu_|db_high[2]~9, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~11 , z80_|alu_|db_high[2]~11, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~12 , z80_|alu_|db_high[2]~12, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~10 , z80_|alu_|db_high[2]~10, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~13 , z80_|alu_|db_high[2]~13, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~14 , z80_|alu_|db_high[2]~14, spectrum, 1 +instance = comp, \z80_|alu_|db[6]~22 , z80_|alu_|db[6]~22, spectrum, 1 +instance = comp, \z80_|alu_|db[6]~23 , z80_|alu_|db[6]~23, spectrum, 1 +instance = comp, \z80_|alu_control_|out[6]~1 , z80_|alu_control_|out[6]~1, spectrum, 1 +instance = comp, \z80_|alu_control_|out[6]~2 , z80_|alu_control_|out[6]~2, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~19 , z80_|alu_control_|db[6]~19, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~20 , z80_|alu_control_|db[6]~20, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~21 , z80_|alu_control_|db[6]~21, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~22 , z80_|alu_control_|db[6]~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_zero_oe~0 , z80_|execute_|ctl_bus_zero_oe~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3, spectrum, 1 +instance = comp, \z80_|interrupts_|im1 , z80_|interrupts_|im1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_ff_oe~0 , z80_|execute_|ctl_bus_ff_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_ff_oe~1 , z80_|execute_|ctl_bus_ff_oe~1, spectrum, 1 +instance = comp, \z80_|bus_control_|db[0]~4 , z80_|bus_control_|db[0]~4, spectrum, 1 +instance = comp, \z80_|bus_control_|db[6]~8 , z80_|bus_control_|db[6]~8, spectrum, 1 instance = comp, \z80_|execute_|ctl_mRead~37 , z80_|execute_|ctl_mRead~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~28 , z80_|execute_|ctl_mRead~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~29 , z80_|execute_|ctl_mRead~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~30 , z80_|execute_|ctl_mRead~30, spectrum, 1 +instance = comp, \z80_|execute_|setM1~37 , z80_|execute_|setM1~37, spectrum, 1 +instance = comp, \z80_|execute_|setM1~55 , z80_|execute_|setM1~55, spectrum, 1 +instance = comp, \z80_|execute_|setM1~38 , z80_|execute_|setM1~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~34 , z80_|execute_|ctl_mRead~34, spectrum, 1 +instance = comp, \z80_|execute_|nextM~3 , z80_|execute_|nextM~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~31 , z80_|execute_|ctl_mRead~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~32 , z80_|execute_|ctl_mRead~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~33 , z80_|execute_|ctl_mRead~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~35 , z80_|execute_|ctl_mRead~35, spectrum, 1 instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff1 , z80_|memory_ifc_|DFFE_mrd_ff1, spectrum, 1 instance = comp, \z80_|memory_ifc_|wait_mrd~feeder , z80_|memory_ifc_|wait_mrd~feeder, spectrum, 1 instance = comp, \z80_|memory_ifc_|wait_mrd , z80_|memory_ifc_|wait_mrd, spectrum, 1 instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff3 , z80_|memory_ifc_|DFFE_mrd_ff3, spectrum, 1 instance = comp, \z80_|memory_ifc_|nRD_out~1 , z80_|memory_ifc_|nRD_out~1, spectrum, 1 +instance = comp, \z80_|execute_|nextM~4 , z80_|execute_|nextM~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~12 , z80_|execute_|ctl_iorw~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~8 , z80_|execute_|ctl_iorw~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~9 , z80_|execute_|ctl_iorw~9, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff1 , z80_|memory_ifc_|DFFE_iorq_ff1, spectrum, 1 +instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder , z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 , z80_|memory_ifc_|SYNTHESIZED_WIRE_15, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_iorq , z80_|memory_ifc_|wait_iorq, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff4 , z80_|memory_ifc_|DFFE_iorq_ff4, spectrum, 1 +instance = comp, \z80_|memory_ifc_|iorq~0 , z80_|memory_ifc_|iorq~0, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~1 , z80_|execute_|fIORead~1, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~2 , z80_|execute_|fIORead~2, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~0 , z80_|execute_|fIORead~0, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~3 , z80_|execute_|fIORead~3, spectrum, 1 instance = comp, \z80_|memory_ifc_|DFFE_m1_ff1 , z80_|memory_ifc_|DFFE_m1_ff1, spectrum, 1 instance = comp, \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 , z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0, spectrum, 1 instance = comp, \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 , z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1, spectrum, 1 instance = comp, \z80_|memory_ifc_|DFFE_m1_ff3 , z80_|memory_ifc_|DFFE_m1_ff3, spectrum, 1 instance = comp, \z80_|memory_ifc_|nRD_out~0 , z80_|memory_ifc_|nRD_out~0, spectrum, 1 instance = comp, \z80_|memory_ifc_|nRD_out~2 , z80_|memory_ifc_|nRD_out~2, spectrum, 1 +instance = comp, \Equal2~1 , Equal2~1, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~0 , z80_|pin_control_|bus_db_pin_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~5 , z80_|execute_|fMWrite~5, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~6 , z80_|execute_|fMWrite~6, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~2 , z80_|execute_|fMWrite~2, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~4 , z80_|execute_|fMWrite~4, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~1 , z80_|pin_control_|bus_db_pin_oe~1, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~2 , z80_|pin_control_|bus_db_pin_oe~2, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~3 , z80_|pin_control_|bus_db_pin_oe~3, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~7 , z80_|execute_|fMWrite~7, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~4 , z80_|pin_control_|bus_db_pin_oe~4, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~7 , z80_|pin_control_|bus_db_pin_oe~7, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~6 , z80_|pin_control_|bus_db_pin_oe~6, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~9 , z80_|execute_|fMWrite~9, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~8 , z80_|pin_control_|bus_db_pin_oe~8, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~9 , z80_|pin_control_|bus_db_pin_oe~9, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~8 , z80_|execute_|fMWrite~8, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~5 , z80_|pin_control_|bus_db_pin_oe~5, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~10 , z80_|pin_control_|bus_db_pin_oe~10, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~10 , z80_|execute_|fMWrite~10, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~11 , z80_|pin_control_|bus_db_pin_oe~11, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~12 , z80_|pin_control_|bus_db_pin_oe~12, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~13 , z80_|pin_control_|bus_db_pin_oe~13, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~14 , z80_|pin_control_|bus_db_pin_oe~14, spectrum, 1 +instance = comp, \z80_|clk_delay_|DFF_inst5~feeder , z80_|clk_delay_|DFF_inst5~feeder, spectrum, 1 +instance = comp, \z80_|clk_delay_|DFF_inst5 , z80_|clk_delay_|DFF_inst5, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_iorqinta~feeder , z80_|memory_ifc_|wait_iorqinta~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_iorqinta , z80_|memory_ifc_|wait_iorqinta, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_intr_ff3 , z80_|memory_ifc_|DFFE_intr_ff3, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nIORQ_out~0 , z80_|memory_ifc_|nIORQ_out~0, spectrum, 1 instance = comp, \Equal2~0 , Equal2~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[0] , ram1|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder , ram1|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] , ram1|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 instance = comp, \ExtRamWE~0 , ExtRamWE~0, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[13]~13 , z80_|address_pins_|DFFE_apin_latch[13]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_apin_mux2~0 , z80_|execute_|ctl_apin_mux2~0, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_ab_pin_we~2 , z80_|pin_control_|bus_ab_pin_we~2, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_ab_pin_we~3 , z80_|pin_control_|bus_ab_pin_we~3, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[13] , z80_|address_pins_|DFFE_apin_latch[13], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[13]~20 , z80_|address_pins_|abus[13]~20, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[14]~14 , z80_|address_pins_|DFFE_apin_latch[14]~14, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[14] , z80_|address_pins_|DFFE_apin_latch[14], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[14]~23 , z80_|address_pins_|abus[14]~23, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[15]~15 , z80_|address_pins_|DFFE_apin_latch[15]~15, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[15] , z80_|address_pins_|DFFE_apin_latch[15], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[15]~22 , z80_|address_pins_|abus[15]~22, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 , ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0, spectrum, 1 +instance = comp, \z80_|address_pins_|abus[0]~16 , z80_|address_pins_|abus[0]~16, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[1]~1 , z80_|address_pins_|DFFE_apin_latch[1]~1, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[1] , z80_|address_pins_|DFFE_apin_latch[1], spectrum, 1 instance = comp, \z80_|address_pins_|abus[1]~25 , z80_|address_pins_|abus[1]~25, spectrum, 1 @@ -2236,23 +2098,41 @@ instance = comp, \z80_|address_pins_|abus[6]~30 , z80_|address_pins_|abus[6]~30, instance = comp, \z80_|address_pins_|DFFE_apin_latch[7]~7 , z80_|address_pins_|DFFE_apin_latch[7]~7, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[7] , z80_|address_pins_|DFFE_apin_latch[7], spectrum, 1 instance = comp, \z80_|address_pins_|abus[7]~31 , z80_|address_pins_|abus[7]~31, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a9 , ram1|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[1] , ram1|altsyncram_component|auto_generated|address_reg_a[1], spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] , ram1|altsyncram_component|auto_generated|out_address_reg_a[1], spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[8]~8 , z80_|address_pins_|DFFE_apin_latch[8]~8, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[8] , z80_|address_pins_|DFFE_apin_latch[8], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[8]~18 , z80_|address_pins_|abus[8]~18, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[9]~9 , z80_|address_pins_|DFFE_apin_latch[9]~9, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[9] , z80_|address_pins_|DFFE_apin_latch[9], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[9]~17 , z80_|address_pins_|abus[9]~17, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[10]~10 , z80_|address_pins_|DFFE_apin_latch[10]~10, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[10] , z80_|address_pins_|DFFE_apin_latch[10], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[10]~24 , z80_|address_pins_|abus[10]~24, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[11]~11 , z80_|address_pins_|DFFE_apin_latch[11]~11, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[11] , z80_|address_pins_|DFFE_apin_latch[11], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[11]~19 , z80_|address_pins_|abus[11]~19, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[12]~12 , z80_|address_pins_|DFFE_apin_latch[12]~12, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[12] , z80_|address_pins_|DFFE_apin_latch[12], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[12]~21 , z80_|address_pins_|abus[12]~21, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a14 , ram1|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[0] , ram1|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] , ram1|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a1 , ram1|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a6 , ram1|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[1] , ram1|altsyncram_component|auto_generated|address_reg_a[1], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] , ram1|altsyncram_component|auto_generated|out_address_reg_a[1], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a17 , ram1|altsyncram_component|auto_generated|ram_block1a17, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a22 , ram1|altsyncram_component|auto_generated|ram_block1a22, spectrum, 1 +instance = comp, \D[6]~90 , D[6]~90, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a25 , ram1|altsyncram_component|auto_generated|ram_block1a25, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 , ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a30 , ram1|altsyncram_component|auto_generated|ram_block1a30, spectrum, 1 +instance = comp, \D[6]~91 , D[6]~91, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 , ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0, spectrum, 1 instance = comp, \CLOCK_50~inputclkctrl , CLOCK_50~inputclkctrl, spectrum, 1 instance = comp, \~GND , ~GND, spectrum, 1 +instance = comp, \ula_|video_|vram_address[0]~feeder , ula_|video_|vram_address[0]~feeder, spectrum, 1 instance = comp, \ula_|video_|vram_address~0 , ula_|video_|vram_address~0, spectrum, 1 instance = comp, \ula_|video_|vram_address[0] , ula_|video_|vram_address[0], spectrum, 1 instance = comp, \ula_|video_|vram_address[1] , ula_|video_|vram_address[1], spectrum, 1 @@ -2285,138 +2165,802 @@ instance = comp, \ula_|video_|Selector3~0 , ula_|video_|Selector3~0, spectrum, 1 instance = comp, \ula_|video_|vram_address[11] , ula_|video_|vram_address[11], spectrum, 1 instance = comp, \ula_|video_|Selector2~0 , ula_|video_|Selector2~0, spectrum, 1 instance = comp, \ula_|video_|vram_address[12] , ula_|video_|vram_address[12], spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a9 , ram0|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a6 , ram0|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder , ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|address_reg_a[0] , ram0|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] , ram0|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 , ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a14 , ram0|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \D[6]~87 , D[6]~87, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a6 , rom|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \D[6]~88 , D[6]~88, spectrum, 1 +instance = comp, \D[6]~89 , D[6]~89, spectrum, 1 +instance = comp, \D[6]~111 , D[6]~111, spectrum, 1 +instance = comp, \raw_loader_in~input , raw_loader_in~input, spectrum, 1 +instance = comp, \D[6]~86 , D[6]~86, spectrum, 1 +instance = comp, \D[6]~100 , D[6]~100, spectrum, 1 +instance = comp, \D[6]~101 , D[6]~101, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] , z80_|data_pins_|SYNTHESIZED_WIRE_0[6], spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_re~2 , z80_|pin_control_|bus_db_pin_re~2, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_2 , z80_|data_pins_|SYNTHESIZED_WIRE_2, spectrum, 1 +instance = comp, \z80_|data_pins_|dout[6] , z80_|data_pins_|dout[6], spectrum, 1 +instance = comp, \z80_|bus_control_|db[6]~9 , z80_|bus_control_|db[6]~9, spectrum, 1 +instance = comp, \z80_|ir_|opcode[6]~feeder , z80_|ir_|opcode[6]~feeder, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~13 , z80_|execute_|ctl_ir_we~13, spectrum, 1 +instance = comp, \z80_|ir_|opcode[6] , z80_|ir_|opcode[6], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal41~0 , z80_|pla_decode_|Equal41~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal41~1 , z80_|pla_decode_|Equal41~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal41~2 , z80_|pla_decode_|Equal41~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe , z80_|execute_|ctl_alu_bs_oe, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~15 , z80_|alu_|db_high[1]~15, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~16 , z80_|alu_|db_high[1]~16, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~17 , z80_|alu_|db_high[1]~17, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~18 , z80_|alu_|db_high[1]~18, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~19 , z80_|alu_|db_high[1]~19, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~20 , z80_|alu_|db_high[1]~20, spectrum, 1 +instance = comp, \z80_|alu_|db[5]~24 , z80_|alu_|db[5]~24, spectrum, 1 +instance = comp, \z80_|alu_|db[5]~25 , z80_|alu_|db[5]~25, spectrum, 1 +instance = comp, \z80_|sw1_|db_down[5]~0 , z80_|sw1_|db_down[5]~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_36 , z80_|alu_flags_|SYNTHESIZED_WIRE_36, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_yf , z80_|alu_flags_|flags_yf, spectrum, 1 +instance = comp, \z80_|alu_control_|db[5]~13 , z80_|alu_control_|db[5]~13, spectrum, 1 +instance = comp, \z80_|alu_control_|db[5]~14 , z80_|alu_control_|db[5]~14, spectrum, 1 +instance = comp, \z80_|alu_control_|db[5]~15 , z80_|alu_control_|db[5]~15, spectrum, 1 +instance = comp, \D[0]~107 , D[0]~107, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a21 , ram1|altsyncram_component|auto_generated|ram_block1a21, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a5 , ram1|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a13 , ram1|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a29 , ram1|altsyncram_component|auto_generated|ram_block1a29, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a13 , ram0|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a13 , rom|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a5 , rom|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a5 , ram0|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 +instance = comp, \Mux2~0 , Mux2~0, spectrum, 1 +instance = comp, \Mux2~1 , Mux2~1, spectrum, 1 +instance = comp, \D[5]~110 , D[5]~110, spectrum, 1 +instance = comp, \D[5]~85 , D[5]~85, spectrum, 1 +instance = comp, \D[5]~99 , D[5]~99, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] , z80_|data_pins_|SYNTHESIZED_WIRE_0[5], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[5] , z80_|data_pins_|dout[5], spectrum, 1 +instance = comp, \z80_|bus_control_|db[5]~14 , z80_|bus_control_|db[5]~14, spectrum, 1 +instance = comp, \z80_|bus_control_|db[5]~15 , z80_|bus_control_|db[5]~15, spectrum, 1 +instance = comp, \z80_|ir_|opcode[5] , z80_|ir_|opcode[5], spectrum, 1 +instance = comp, \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 , z80_|decode_state_|SYNTHESIZED_WIRE_0~0, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_inst4 , z80_|decode_state_|DFFE_inst4, spectrum, 1 +instance = comp, \z80_|decode_state_|use_ixiy , z80_|decode_state_|use_ixiy, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~23 , z80_|execute_|ctl_mRead~23, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~34 , z80_|execute_|fMRead~34, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~31 , z80_|execute_|fMRead~31, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~29 , z80_|execute_|fMRead~29, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~30 , z80_|execute_|fMRead~30, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~28 , z80_|execute_|fMRead~28, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~32 , z80_|execute_|fMRead~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~42 , z80_|execute_|ctl_bus_inc_oe~42, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~14 , z80_|execute_|fMRead~14, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~10 , z80_|execute_|fMRead~10, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~9 , z80_|execute_|fMRead~9, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~11 , z80_|execute_|fMRead~11, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~12 , z80_|execute_|fMRead~12, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~13 , z80_|execute_|fMRead~13, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~15 , z80_|execute_|fMRead~15, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~20 , z80_|execute_|fMRead~20, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~48 , z80_|execute_|pc_inc_hold~48, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~22 , z80_|execute_|fMRead~22, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~21 , z80_|execute_|fMRead~21, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~23 , z80_|execute_|fMRead~23, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~26 , z80_|execute_|fMRead~26, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~25 , z80_|execute_|fMRead~25, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~27 , z80_|execute_|fMRead~27, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~33 , z80_|execute_|fMRead~33, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~35 , z80_|execute_|fMRead~35, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_re , z80_|pin_control_|bus_db_pin_re, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a1 , ram1|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a9 , ram1|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a17 , ram1|altsyncram_component|auto_generated|ram_block1a17, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a25 , ram1|altsyncram_component|auto_generated|ram_block1a25, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a9 , ram0|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a9 , rom|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a1 , rom|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 , ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0, spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a1 , ram0|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 instance = comp, \Selector1~0 , Selector1~0, spectrum, 1 instance = comp, \Selector1~1 , Selector1~1, spectrum, 1 -instance = comp, \D[1]~22 , D[1]~22, spectrum, 1 -instance = comp, \D[1]~23 , D[1]~23, spectrum, 1 +instance = comp, \D[1]~103 , D[1]~103, spectrum, 1 +instance = comp, \PS2_DAT~input , PS2_DAT~input, spectrum, 1 +instance = comp, \reset~clkctrl , reset~clkctrl, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~0 , ula_|ps2_keyboard_|bit_count~0, spectrum, 1 +instance = comp, \PS2_CLK~input , PS2_CLK~input, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[7]~feeder , ula_|ps2_keyboard_|clk_filter[7]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[7] , ula_|ps2_keyboard_|clk_filter[7], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[6]~feeder , ula_|ps2_keyboard_|clk_filter[6]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[6] , ula_|ps2_keyboard_|clk_filter[6], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[5]~feeder , ula_|ps2_keyboard_|clk_filter[5]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[5] , ula_|ps2_keyboard_|clk_filter[5], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[4]~feeder , ula_|ps2_keyboard_|clk_filter[4]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[4] , ula_|ps2_keyboard_|clk_filter[4], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|Equal0~0 , ula_|ps2_keyboard_|Equal0~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[3]~feeder , ula_|ps2_keyboard_|clk_filter[3]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[3] , ula_|ps2_keyboard_|clk_filter[3], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[2]~feeder , ula_|ps2_keyboard_|clk_filter[2]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[2] , ula_|ps2_keyboard_|clk_filter[2], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[1]~feeder , ula_|ps2_keyboard_|clk_filter[1]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[1] , ula_|ps2_keyboard_|clk_filter[1], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|Equal0~1 , ula_|ps2_keyboard_|Equal0~1, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[0]~0 , ula_|ps2_keyboard_|clk_filter[0]~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[0] , ula_|ps2_keyboard_|clk_filter[0], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|ps2_clk_in~0 , ula_|ps2_keyboard_|ps2_clk_in~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|ps2_clk_in , ula_|ps2_keyboard_|ps2_clk_in, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_edge~0 , ula_|ps2_keyboard_|clk_edge~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_edge , ula_|ps2_keyboard_|clk_edge, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[0] , ula_|ps2_keyboard_|bit_count[0], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~1 , ula_|ps2_keyboard_|bit_count~1, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[2] , ula_|ps2_keyboard_|bit_count[2], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~3 , ula_|ps2_keyboard_|bit_count~3, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[3] , ula_|ps2_keyboard_|bit_count[3], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~2 , ula_|ps2_keyboard_|bit_count~2, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[1] , ula_|ps2_keyboard_|bit_count[1], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|always1~0 , ula_|ps2_keyboard_|always1~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|LessThan0~0 , ula_|ps2_keyboard_|LessThan0~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[0]~0 , ula_|ps2_keyboard_|shiftreg[0]~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[8] , ula_|ps2_keyboard_|shiftreg[8], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[7] , ula_|ps2_keyboard_|shiftreg[7], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[6] , ula_|ps2_keyboard_|shiftreg[6], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[5] , ula_|ps2_keyboard_|shiftreg[5], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[4] , ula_|ps2_keyboard_|shiftreg[4], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[3] , ula_|ps2_keyboard_|shiftreg[3], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[2] , ula_|ps2_keyboard_|shiftreg[2], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[1] , ula_|ps2_keyboard_|shiftreg[1], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[0] , ula_|ps2_keyboard_|shiftreg[0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Equal0~0 , ula_|zx_keyboard_|Equal0~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Equal0~1 , ula_|zx_keyboard_|Equal0~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|extended~0 , ula_|zx_keyboard_|extended~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|WideXor0~1 , ula_|ps2_keyboard_|WideXor0~1, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|WideXor0~0 , ula_|ps2_keyboard_|WideXor0~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|WideXor0~2 , ula_|ps2_keyboard_|WideXor0~2, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|scan_code_ready~0 , ula_|ps2_keyboard_|scan_code_ready~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|scan_code_ready , ula_|ps2_keyboard_|scan_code_ready, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|extended , ula_|zx_keyboard_|extended, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0]~15 , ula_|zx_keyboard_|keys[0][0]~15, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~36 , ula_|zx_keyboard_|keys[5][1]~36, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~37 , ula_|zx_keyboard_|keys[5][1]~37, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~0 , ula_|zx_keyboard_|shifted~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|released~0 , ula_|zx_keyboard_|released~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|released , ula_|zx_keyboard_|released, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr17~0 , ula_|zx_keyboard_|WideOr17~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~2 , ula_|zx_keyboard_|shifted~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~3 , ula_|zx_keyboard_|shifted~3, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted , ula_|zx_keyboard_|shifted, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~35 , ula_|zx_keyboard_|keys[5][1]~35, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~38 , ula_|zx_keyboard_|keys[5][1]~38, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~39 , ula_|zx_keyboard_|keys[5][1]~39, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1] , ula_|zx_keyboard_|keys[5][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][1]~31 , ula_|zx_keyboard_|keys[4][1]~31, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1]~23 , ula_|zx_keyboard_|keys[7][1]~23, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~32 , ula_|zx_keyboard_|keys[7][2]~32, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2]~33 , ula_|zx_keyboard_|keys[5][2]~33, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][1]~34 , ula_|zx_keyboard_|keys[4][1]~34, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][1] , ula_|zx_keyboard_|keys[4][1], spectrum, 1 +instance = comp, \D[1]~30 , D[1]~30, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~24 , ula_|zx_keyboard_|keys[5][4]~24, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1]~28 , ula_|zx_keyboard_|keys[3][1]~28, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1]~29 , ula_|zx_keyboard_|keys[3][1]~29, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1]~30 , ula_|zx_keyboard_|keys[3][1]~30, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1] , ula_|zx_keyboard_|keys[3][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][4]~25 , ula_|zx_keyboard_|keys[1][4]~25, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][1]~26 , ula_|zx_keyboard_|keys[2][1]~26, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][1]~27 , ula_|zx_keyboard_|keys[2][1]~27, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][1] , ula_|zx_keyboard_|keys[2][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row~0 , ula_|zx_keyboard_|key_row~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~14 , ula_|zx_keyboard_|keys[0][1]~14, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~16 , ula_|zx_keyboard_|keys[0][1]~16, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~17 , ula_|zx_keyboard_|keys[0][1]~17, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~18 , ula_|zx_keyboard_|keys[0][1]~18, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1] , ula_|zx_keyboard_|keys[0][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4]~19 , ula_|zx_keyboard_|keys[7][4]~19, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~20 , ula_|zx_keyboard_|keys[6][4]~20, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][1]~21 , ula_|zx_keyboard_|keys[1][1]~21, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][1]~22 , ula_|zx_keyboard_|keys[1][1]~22, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][1] , ula_|zx_keyboard_|keys[1][1], spectrum, 1 +instance = comp, \D[1]~28 , D[1]~28, spectrum, 1 instance = comp, \D[1]~29 , D[1]~29, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~41 , ula_|zx_keyboard_|keys[6][1]~41, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~42 , ula_|zx_keyboard_|keys[6][1]~42, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~43 , ula_|zx_keyboard_|keys[6][1]~43, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~40 , ula_|zx_keyboard_|keys[6][1]~40, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~44 , ula_|zx_keyboard_|keys[6][1]~44, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1] , ula_|zx_keyboard_|keys[6][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1]~45 , ula_|zx_keyboard_|keys[7][1]~45, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~5 , ula_|zx_keyboard_|WideOr16~5, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~2 , ula_|zx_keyboard_|WideOr16~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~4 , ula_|zx_keyboard_|WideOr16~4, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~7 , ula_|zx_keyboard_|WideOr16~7, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~6 , ula_|zx_keyboard_|WideOr16~6, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1]~46 , ula_|zx_keyboard_|keys[7][1]~46, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1] , ula_|zx_keyboard_|keys[7][1], spectrum, 1 instance = comp, \D[1]~31 , D[1]~31, spectrum, 1 +instance = comp, \D[1]~32 , D[1]~32, spectrum, 1 +instance = comp, \D[1]~33 , D[1]~33, spectrum, 1 +instance = comp, \D[1]~34 , D[1]~34, spectrum, 1 instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] , z80_|data_pins_|SYNTHESIZED_WIRE_0[1], spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_re~2 , z80_|pin_control_|bus_db_pin_re~2, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_2 , z80_|data_pins_|SYNTHESIZED_WIRE_2, spectrum, 1 instance = comp, \z80_|data_pins_|dout[1] , z80_|data_pins_|dout[1], spectrum, 1 -instance = comp, \z80_|bus_control_|db[1]~12 , z80_|bus_control_|db[1]~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_zero_oe~0 , z80_|execute_|ctl_bus_zero_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~0 , z80_|execute_|ctl_bus_db_oe~0, spectrum, 1 -instance = comp, \z80_|bus_control_|db[0]~6 , z80_|bus_control_|db[0]~6, spectrum, 1 -instance = comp, \z80_|bus_control_|db[1]~13 , z80_|bus_control_|db[1]~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~13 , z80_|execute_|ctl_ir_we~13, spectrum, 1 +instance = comp, \z80_|bus_control_|db[1]~10 , z80_|bus_control_|db[1]~10, spectrum, 1 +instance = comp, \z80_|bus_control_|db[1]~11 , z80_|bus_control_|db[1]~11, spectrum, 1 +instance = comp, \z80_|ir_|opcode[1]~feeder , z80_|ir_|opcode[1]~feeder, spectrum, 1 instance = comp, \z80_|ir_|opcode[1] , z80_|ir_|opcode[1], spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_tbl_ed_set , z80_|execute_|ctl_state_tbl_ed_set, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_tbl_we~8 , z80_|execute_|ctl_state_tbl_we~8, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instED , z80_|decode_state_|DFFE_instED, spectrum, 1 -instance = comp, \z80_|decode_state_|table_xx~0 , z80_|decode_state_|table_xx~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~7 , z80_|pla_decode_|Equal1~7, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal36~0 , z80_|pla_decode_|Equal36~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_tbl_cb_set , z80_|execute_|ctl_state_tbl_cb_set, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instCB , z80_|decode_state_|DFFE_instCB, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal77~0 , z80_|pla_decode_|Equal77~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal50~0 , z80_|pla_decode_|Equal50~0, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~17 , z80_|execute_|ixy_d~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~14 , z80_|execute_|ctl_mWrite~14, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal40~0 , z80_|pla_decode_|Equal40~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal21~1 , z80_|pla_decode_|Equal21~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~26 , z80_|execute_|ctl_alu_op_low~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~28 , z80_|execute_|ctl_alu_op_low~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~3 , z80_|execute_|ctl_flags_cf_cpl~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~2 , z80_|execute_|ctl_flags_cf_cpl~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~5, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~6, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~7, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~4, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~8, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~9, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~21, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~12, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~10, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~11, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~13, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~32 , z80_|execute_|ctl_alu_op_low~32, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~15, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~16, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~18, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~19, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~0 , z80_|alu_flags_|DFFE_inst_latch_cf2~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~1 , z80_|alu_flags_|DFFE_inst_latch_cf2~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~2 , z80_|alu_flags_|DFFE_inst_latch_cf2~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~3 , z80_|alu_flags_|DFFE_inst_latch_cf2~3, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2 , z80_|alu_flags_|DFFE_inst_latch_cf2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~10 , z80_|execute_|ctl_flags_use_cf2~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~11 , z80_|execute_|ctl_flags_use_cf2~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~8 , z80_|execute_|ctl_flags_use_cf2~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~9 , z80_|execute_|ctl_flags_use_cf2~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~12 , z80_|execute_|ctl_flags_use_cf2~12, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~14, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~10 , z80_|execute_|ctl_flags_cf_cpl~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~8 , z80_|execute_|ctl_flags_cf_cpl~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~5 , z80_|execute_|ctl_flags_cf_cpl~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~6 , z80_|execute_|ctl_flags_cf_cpl~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~7 , z80_|execute_|ctl_flags_cf_cpl~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_set~0 , z80_|execute_|ctl_flags_cf_set~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~4 , z80_|execute_|ctl_flags_cf_cpl~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~9 , z80_|execute_|ctl_flags_cf_cpl~9, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_cf , z80_|alu_flags_|flags_cf, spectrum, 1 +instance = comp, \z80_|alu_control_|db[0]~8 , z80_|alu_control_|db[0]~8, spectrum, 1 +instance = comp, \z80_|sw2_|db_up[0]~0 , z80_|sw2_|db_up[0]~0, spectrum, 1 +instance = comp, \z80_|alu_control_|db[0]~9 , z80_|alu_control_|db[0]~9, spectrum, 1 +instance = comp, \z80_|alu_control_|db[0]~12 , z80_|alu_control_|db[0]~12, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~67 , ula_|zx_keyboard_|keys[5][0]~67, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~81 , ula_|zx_keyboard_|keys[5][0]~81, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~82 , ula_|zx_keyboard_|keys[5][0]~82, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~83 , ula_|zx_keyboard_|keys[5][0]~83, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0] , ula_|zx_keyboard_|keys[5][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][0]~84 , ula_|zx_keyboard_|keys[4][0]~84, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][0]~85 , ula_|zx_keyboard_|keys[4][0]~85, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][0]~86 , ula_|zx_keyboard_|keys[4][0]~86, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][0] , ula_|zx_keyboard_|keys[4][0], spectrum, 1 +instance = comp, \D[0]~49 , D[0]~49, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr4~0 , ula_|zx_keyboard_|WideOr4~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys~76 , ula_|zx_keyboard_|keys~76, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~73 , ula_|zx_keyboard_|keys[4][3]~73, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~47 , ula_|zx_keyboard_|keys[6][4]~47, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr0~0 , ula_|zx_keyboard_|WideOr0~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys~74 , ula_|zx_keyboard_|keys~74, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0]~75 , ula_|zx_keyboard_|keys[0][0]~75, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0]~77 , ula_|zx_keyboard_|keys[0][0]~77, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0] , ula_|zx_keyboard_|keys[0][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][0]~71 , ula_|zx_keyboard_|keys[1][0]~71, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][0]~72 , ula_|zx_keyboard_|keys[1][0]~72, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][0] , ula_|zx_keyboard_|keys[1][0], spectrum, 1 +instance = comp, \D[0]~47 , D[0]~47, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][0]~80 , ula_|zx_keyboard_|keys[2][0]~80, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][0] , ula_|zx_keyboard_|keys[2][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][0]~78 , ula_|zx_keyboard_|keys[3][0]~78, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][0]~79 , ula_|zx_keyboard_|keys[3][0]~79, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][0] , ula_|zx_keyboard_|keys[3][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row~1 , ula_|zx_keyboard_|key_row~1, spectrum, 1 +instance = comp, \D[0]~48 , D[0]~48, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~1 , ula_|zx_keyboard_|shifted~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][0]~90 , ula_|zx_keyboard_|keys[6][0]~90, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][0]~91 , ula_|zx_keyboard_|keys[6][0]~91, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][0]~92 , ula_|zx_keyboard_|keys[6][0]~92, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][0] , ula_|zx_keyboard_|keys[6][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~63 , ula_|zx_keyboard_|keys[5][4]~63, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~3 , ula_|zx_keyboard_|WideOr16~3, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~87 , ula_|zx_keyboard_|keys[7][0]~87, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~132 , ula_|zx_keyboard_|keys[7][0]~132, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~88 , ula_|zx_keyboard_|keys[7][0]~88, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~89 , ula_|zx_keyboard_|keys[7][0]~89, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0] , ula_|zx_keyboard_|keys[7][0], spectrum, 1 +instance = comp, \D[0]~50 , D[0]~50, spectrum, 1 +instance = comp, \D[0]~51 , D[0]~51, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a24 , ram1|altsyncram_component|auto_generated|ram_block1a24, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a16 , ram1|altsyncram_component|auto_generated|ram_block1a16, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a0 , ram1|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \D[0]~55 , D[0]~55, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a8 , ram1|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 +instance = comp, \D[0]~56 , D[0]~56, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a0 , ram0|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a8 , rom|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a8 , ram0|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 +instance = comp, \D[0]~52 , D[0]~52, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \D[0]~53 , D[0]~53, spectrum, 1 +instance = comp, \D[0]~54 , D[0]~54, spectrum, 1 +instance = comp, \D[0]~106 , D[0]~106, spectrum, 1 +instance = comp, \D[0]~57 , D[0]~57, spectrum, 1 +instance = comp, \D[0]~58 , D[0]~58, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] , z80_|data_pins_|SYNTHESIZED_WIRE_0[0], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[0] , z80_|data_pins_|dout[0], spectrum, 1 +instance = comp, \z80_|bus_control_|db[0]~16 , z80_|bus_control_|db[0]~16, spectrum, 1 +instance = comp, \z80_|bus_control_|db[0]~17 , z80_|bus_control_|db[0]~17, spectrum, 1 +instance = comp, \z80_|ir_|opcode[0] , z80_|ir_|opcode[0], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal63~0 , z80_|pla_decode_|Equal63~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_daa , z80_|execute_|ctl_flags_cf2_sel_daa, spectrum, 1 +instance = comp, \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 , z80_|alu_control_|SYNTHESIZED_WIRE_2~0, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~10 , z80_|alu_control_|db[6]~10, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~11 , z80_|alu_control_|db[6]~11, spectrum, 1 +instance = comp, \z80_|alu_control_|db[4]~30 , z80_|alu_control_|db[4]~30, spectrum, 1 +instance = comp, \z80_|alu_control_|db[4]~31 , z80_|alu_control_|db[4]~31, spectrum, 1 +instance = comp, \z80_|alu_control_|db[4]~32 , z80_|alu_control_|db[4]~32, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~119 , ula_|zx_keyboard_|keys[2][4]~119, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~120 , ula_|zx_keyboard_|keys[2][4]~120, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~95 , ula_|zx_keyboard_|keys[2][4]~95, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~121 , ula_|zx_keyboard_|keys[2][4]~121, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4] , ula_|zx_keyboard_|keys[2][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~117 , ula_|zx_keyboard_|keys[3][4]~117, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~136 , ula_|zx_keyboard_|keys[3][4]~136, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~130 , ula_|zx_keyboard_|keys[3][4]~130, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~118 , ula_|zx_keyboard_|keys[3][4]~118, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4] , ula_|zx_keyboard_|keys[3][4], spectrum, 1 +instance = comp, \D[4]~78 , D[4]~78, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~126 , ula_|zx_keyboard_|keys[6][4]~126, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~128 , ula_|zx_keyboard_|keys[5][4]~128, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~129 , ula_|zx_keyboard_|keys[5][4]~129, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4] , ula_|zx_keyboard_|keys[5][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~127 , ula_|zx_keyboard_|keys[6][4]~127, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4] , ula_|zx_keyboard_|keys[6][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Equal0~2 , ula_|zx_keyboard_|Equal0~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4]~51 , ula_|zx_keyboard_|keys[7][4]~51, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4]~125 , ula_|zx_keyboard_|keys[7][4]~125, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4] , ula_|zx_keyboard_|keys[7][4], spectrum, 1 +instance = comp, \D[4]~79 , D[4]~79, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4]~122 , ula_|zx_keyboard_|keys[4][4]~122, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4]~123 , ula_|zx_keyboard_|keys[4][4]~123, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4]~124 , ula_|zx_keyboard_|keys[4][4]~124, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4] , ula_|zx_keyboard_|keys[4][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row~3 , ula_|zx_keyboard_|key_row~3, spectrum, 1 +instance = comp, \D[4]~80 , D[4]~80, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4]~111 , ula_|zx_keyboard_|keys[0][4]~111, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4]~97 , ula_|zx_keyboard_|keys[0][4]~97, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4]~116 , ula_|zx_keyboard_|keys[0][4]~116, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4] , ula_|zx_keyboard_|keys[0][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][4]~115 , ula_|zx_keyboard_|keys[1][4]~115, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][4] , ula_|zx_keyboard_|keys[1][4], spectrum, 1 +instance = comp, \D[4]~77 , D[4]~77, spectrum, 1 +instance = comp, \D[4]~81 , D[4]~81, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a12 , ram0|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a4 , ram0|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \Selector4~0 , Selector4~0, spectrum, 1 +instance = comp, \Selector4~1 , Selector4~1, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a28 , ram1|altsyncram_component|auto_generated|ram_block1a28, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a12 , ram1|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a20 , ram1|altsyncram_component|auto_generated|ram_block1a20, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a4 , ram1|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3, spectrum, 1 +instance = comp, \D[4]~109 , D[4]~109, spectrum, 1 +instance = comp, \D[4]~97 , D[4]~97, spectrum, 1 +instance = comp, \D[4]~98 , D[4]~98, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] , z80_|data_pins_|SYNTHESIZED_WIRE_0[4], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[4] , z80_|data_pins_|dout[4], spectrum, 1 +instance = comp, \z80_|bus_control_|db[4]~18 , z80_|bus_control_|db[4]~18, spectrum, 1 +instance = comp, \z80_|bus_control_|db[4]~19 , z80_|bus_control_|db[4]~19, spectrum, 1 +instance = comp, \z80_|ir_|opcode[4] , z80_|ir_|opcode[4], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal21~0 , z80_|pla_decode_|Equal21~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~5 , z80_|execute_|ctl_mRead~5, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~2 , z80_|execute_|fIOWrite~2, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~3 , z80_|execute_|fIOWrite~3, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~4 , z80_|execute_|fIOWrite~4, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~5 , z80_|execute_|fIOWrite~5, spectrum, 1 instance = comp, \z80_|execute_|ctl_mWrite~11 , z80_|execute_|ctl_mWrite~11, spectrum, 1 instance = comp, \z80_|execute_|ctl_mWrite~12 , z80_|execute_|ctl_mWrite~12, spectrum, 1 instance = comp, \z80_|execute_|ctl_mWrite~13 , z80_|execute_|ctl_mWrite~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~14 , z80_|execute_|ctl_mWrite~14, spectrum, 1 instance = comp, \z80_|execute_|ctl_mWrite~15 , z80_|execute_|ctl_mWrite~15, spectrum, 1 instance = comp, \z80_|memory_ifc_|DFFE_mwr_ff1 , z80_|memory_ifc_|DFFE_mwr_ff1, spectrum, 1 instance = comp, \z80_|memory_ifc_|wait_mwr~feeder , z80_|memory_ifc_|wait_mwr~feeder, spectrum, 1 instance = comp, \z80_|memory_ifc_|wait_mwr , z80_|memory_ifc_|wait_mwr, spectrum, 1 -instance = comp, \z80_|memory_ifc_|mwr_wr~feeder , z80_|memory_ifc_|mwr_wr~feeder, spectrum, 1 instance = comp, \z80_|memory_ifc_|mwr_wr , z80_|memory_ifc_|mwr_wr, spectrum, 1 instance = comp, \z80_|memory_ifc_|nWR_out~0 , z80_|memory_ifc_|nWR_out~0, spectrum, 1 -instance = comp, \D[0]~30 , D[0]~30, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a22 , ram1|altsyncram_component|auto_generated|ram_block1a22, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a6 , ram1|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 , ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a30 , ram1|altsyncram_component|auto_generated|ram_block1a30, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a14 , ram1|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 , ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a14 , ram0|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a6 , rom|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a6 , ram0|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 -instance = comp, \Selector6~0 , Selector6~0, spectrum, 1 -instance = comp, \D[6]~70 , D[6]~70, spectrum, 1 -instance = comp, \D[6]~71 , D[6]~71, spectrum, 1 -instance = comp, \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl , ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] , z80_|data_pins_|SYNTHESIZED_WIRE_0[3], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[3] , z80_|data_pins_|dout[3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~64 , ula_|zx_keyboard_|keys[5][4]~64, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~47 , ula_|zx_keyboard_|keys[6][4]~47, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3]~101 , ula_|zx_keyboard_|keys[3][3]~101, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3]~102 , ula_|zx_keyboard_|keys[3][3]~102, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3] , ula_|zx_keyboard_|keys[3][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~103 , ula_|zx_keyboard_|keys[2][3]~103, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~104 , ula_|zx_keyboard_|keys[2][3]~104, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~135 , ula_|zx_keyboard_|keys[2][3]~135, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~105 , ula_|zx_keyboard_|keys[2][3]~105, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3] , ula_|zx_keyboard_|keys[2][3], spectrum, 1 -instance = comp, \D[3]~55 , D[3]~55, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][3]~94 , ula_|zx_keyboard_|keys[1][3]~94, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][3]~95 , ula_|zx_keyboard_|keys[1][3]~95, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][3]~96 , ula_|zx_keyboard_|keys[1][3]~96, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][3] , ula_|zx_keyboard_|keys[1][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][3]~98 , ula_|zx_keyboard_|keys[0][3]~98, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~97 , ula_|zx_keyboard_|keys[2][4]~97, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4]~99 , ula_|zx_keyboard_|keys[0][4]~99, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][3]~100 , ula_|zx_keyboard_|keys[0][3]~100, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][3] , ula_|zx_keyboard_|keys[0][3], spectrum, 1 -instance = comp, \D[3]~54 , D[3]~54, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Selector5~1 , ula_|zx_keyboard_|Selector5~1, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][0]~79 , ula_|zx_keyboard_|keys[3][0]~79, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Selector5~0 , ula_|zx_keyboard_|Selector5~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~136 , ula_|zx_keyboard_|keys[4][3]~136, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~108 , ula_|zx_keyboard_|keys[4][3]~108, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~109 , ula_|zx_keyboard_|keys[4][3]~109, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~137 , ula_|zx_keyboard_|keys[4][3]~137, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~110 , ula_|zx_keyboard_|keys[4][3]~110, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3] , ula_|zx_keyboard_|keys[4][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][3]~106 , ula_|zx_keyboard_|keys[5][3]~106, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][3]~107 , ula_|zx_keyboard_|keys[5][3]~107, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][3] , ula_|zx_keyboard_|keys[5][3], spectrum, 1 -instance = comp, \D[3]~56 , D[3]~56, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~115 , ula_|zx_keyboard_|keys[6][3]~115, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~116 , ula_|zx_keyboard_|keys[6][3]~116, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~139 , ula_|zx_keyboard_|keys[6][3]~139, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Selector13~0 , ula_|zx_keyboard_|Selector13~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~140 , ula_|zx_keyboard_|keys[6][3]~140, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3] , ula_|zx_keyboard_|keys[6][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4]~111 , ula_|zx_keyboard_|keys[0][4]~111, spectrum, 1 +instance = comp, \D[5]~84 , D[5]~84, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a23 , ram1|altsyncram_component|auto_generated|ram_block1a23, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a7 , ram1|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a15 , ram1|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a31 , ram1|altsyncram_component|auto_generated|ram_block1a31, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a15 , ram0|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a7 , ram0|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \Mux0~0 , Mux0~0, spectrum, 1 +instance = comp, \Mux0~1 , Mux0~1, spectrum, 1 +instance = comp, \D[7]~112 , D[7]~112, spectrum, 1 +instance = comp, \D[7]~94 , D[7]~94, spectrum, 1 +instance = comp, \D[7]~102 , D[7]~102, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] , z80_|data_pins_|SYNTHESIZED_WIRE_0[7], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[7] , z80_|data_pins_|dout[7], spectrum, 1 +instance = comp, \z80_|bus_control_|db[7]~5 , z80_|bus_control_|db[7]~5, spectrum, 1 +instance = comp, \z80_|bus_control_|db[7]~7 , z80_|bus_control_|db[7]~7, spectrum, 1 +instance = comp, \z80_|ir_|opcode[7] , z80_|ir_|opcode[7], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal77~0 , z80_|pla_decode_|Equal77~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~5 , z80_|execute_|ctl_mWrite~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 , z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~3 , z80_|execute_|ctl_bus_db_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~8 , z80_|execute_|ctl_bus_db_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~2 , z80_|execute_|ctl_bus_db_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~4 , z80_|execute_|ctl_bus_db_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~6 , z80_|execute_|ctl_bus_db_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~7 , z80_|execute_|ctl_bus_db_we~7, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][2]~50 , ula_|zx_keyboard_|keys[0][2]~50, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][2]~52 , ula_|zx_keyboard_|keys[0][2]~52, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][2] , ula_|zx_keyboard_|keys[0][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3]~48 , ula_|zx_keyboard_|keys[3][3]~48, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][2]~49 , ula_|zx_keyboard_|keys[1][2]~49, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][2] , ula_|zx_keyboard_|keys[1][2], spectrum, 1 +instance = comp, \D[2]~35 , D[2]~35, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2]~57 , ula_|zx_keyboard_|keys[5][2]~57, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2]~58 , ula_|zx_keyboard_|keys[5][2]~58, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2] , ula_|zx_keyboard_|keys[5][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2]~59 , ula_|zx_keyboard_|keys[4][2]~59, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2]~131 , ula_|zx_keyboard_|keys[4][2]~131, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2]~60 , ula_|zx_keyboard_|keys[4][2]~60, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2] , ula_|zx_keyboard_|keys[4][2], spectrum, 1 +instance = comp, \D[2]~37 , D[2]~37, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][2]~53 , ula_|zx_keyboard_|keys[3][2]~53, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][2]~55 , ula_|zx_keyboard_|keys[2][2]~55, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][2]~56 , ula_|zx_keyboard_|keys[2][2]~56, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][2] , ula_|zx_keyboard_|keys[2][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][2]~54 , ula_|zx_keyboard_|keys[3][2]~54, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][2] , ula_|zx_keyboard_|keys[3][2], spectrum, 1 +instance = comp, \D[2]~36 , D[2]~36, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2]~68 , ula_|zx_keyboard_|keys[6][2]~68, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2]~69 , ula_|zx_keyboard_|keys[6][2]~69, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2]~70 , ula_|zx_keyboard_|keys[6][2]~70, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2] , ula_|zx_keyboard_|keys[6][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~61 , ula_|zx_keyboard_|keys[7][2]~61, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[7][2]~62 , ula_|zx_keyboard_|keys[7][2]~62, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~64 , ula_|zx_keyboard_|keys[7][2]~64, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~65 , ula_|zx_keyboard_|keys[7][2]~65, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Selector13~0 , ula_|zx_keyboard_|Selector13~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~66 , ula_|zx_keyboard_|keys[7][2]~66, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2] , ula_|zx_keyboard_|keys[7][2], spectrum, 1 +instance = comp, \D[2]~38 , D[2]~38, spectrum, 1 +instance = comp, \D[2]~39 , D[2]~39, spectrum, 1 +instance = comp, \D[2]~104 , D[2]~104, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a26 , ram1|altsyncram_component|auto_generated|ram_block1a26, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a10 , ram1|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a18 , ram1|altsyncram_component|auto_generated|ram_block1a18, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a2 , ram1|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \D[2]~43 , D[2]~43, spectrum, 1 +instance = comp, \D[2]~44 , D[2]~44, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a10 , rom|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a10 , ram0|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 +instance = comp, \D[2]~40 , D[2]~40, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a2 , ram0|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a2 , rom|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \D[2]~41 , D[2]~41, spectrum, 1 +instance = comp, \D[2]~42 , D[2]~42, spectrum, 1 +instance = comp, \D[2]~105 , D[2]~105, spectrum, 1 +instance = comp, \D[2]~45 , D[2]~45, spectrum, 1 +instance = comp, \D[2]~46 , D[2]~46, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] , z80_|data_pins_|SYNTHESIZED_WIRE_0[2], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[2] , z80_|data_pins_|dout[2], spectrum, 1 +instance = comp, \z80_|bus_control_|db[2]~12 , z80_|bus_control_|db[2]~12, spectrum, 1 +instance = comp, \z80_|bus_control_|db[2]~13 , z80_|bus_control_|db[2]~13, spectrum, 1 +instance = comp, \z80_|ir_|opcode[2] , z80_|ir_|opcode[2], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal3~1 , z80_|pla_decode_|Equal3~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal43~0 , z80_|pla_decode_|Equal43~0, spectrum, 1 +instance = comp, \z80_|interrupts_|test1~2 , z80_|interrupts_|test1~2, spectrum, 1 +instance = comp, \z80_|interrupts_|test1~3 , z80_|interrupts_|test1~3, spectrum, 1 +instance = comp, \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED , z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED, spectrum, 1 +instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_4 , z80_|clk_delay_|SYNTHESIZED_WIRE_4, spectrum, 1 +instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_7 , z80_|clk_delay_|SYNTHESIZED_WIRE_7, spectrum, 1 +instance = comp, \z80_|clk_delay_|hold_clk_iorq , z80_|clk_delay_|hold_clk_iorq, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T1_ff , z80_|sequencer_|DFFE_T1_ff, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_13 , z80_|sequencer_|SYNTHESIZED_WIRE_13, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T2_ff , z80_|sequencer_|DFFE_T2_ff, spectrum, 1 +instance = comp, \z80_|resets_|x3 , z80_|resets_|x3, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12 , z80_|resets_|SYNTHESIZED_WIRE_12, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl , z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M1_ff , z80_|sequencer_|DFFE_M1_ff, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M2_ff~0 , z80_|sequencer_|DFFE_M2_ff~0, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M2_ff , z80_|sequencer_|DFFE_M2_ff, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~3 , z80_|execute_|ctl_mWrite~3, spectrum, 1 +instance = comp, \z80_|execute_|nextM~11 , z80_|execute_|nextM~11, spectrum, 1 +instance = comp, \z80_|execute_|nextM~8 , z80_|execute_|nextM~8, spectrum, 1 +instance = comp, \z80_|execute_|nextM~9 , z80_|execute_|nextM~9, spectrum, 1 +instance = comp, \z80_|execute_|nextM~10 , z80_|execute_|nextM~10, spectrum, 1 +instance = comp, \z80_|execute_|nextM~12 , z80_|execute_|nextM~12, spectrum, 1 +instance = comp, \z80_|execute_|nextM~15 , z80_|execute_|nextM~15, spectrum, 1 +instance = comp, \z80_|execute_|nextM~6 , z80_|execute_|nextM~6, spectrum, 1 +instance = comp, \z80_|execute_|nextM~7 , z80_|execute_|nextM~7, spectrum, 1 +instance = comp, \z80_|execute_|nextM~13 , z80_|execute_|nextM~13, spectrum, 1 +instance = comp, \z80_|execute_|setM1~39 , z80_|execute_|setM1~39, spectrum, 1 +instance = comp, \z80_|execute_|nextM~5 , z80_|execute_|nextM~5, spectrum, 1 +instance = comp, \z80_|execute_|nextM~14 , z80_|execute_|nextM~14, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_15 , z80_|sequencer_|SYNTHESIZED_WIRE_15, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T4_ff , z80_|sequencer_|DFFE_T4_ff, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_16 , z80_|sequencer_|SYNTHESIZED_WIRE_16, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T5_ff , z80_|sequencer_|DFFE_T5_ff, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_17 , z80_|sequencer_|SYNTHESIZED_WIRE_17, spectrum, 1 +instance = comp, \z80_|sequencer_|T6 , z80_|sequencer_|T6, spectrum, 1 +instance = comp, \z80_|execute_|setM1~13 , z80_|execute_|setM1~13, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal77~1 , z80_|pla_decode_|Equal77~1, spectrum, 1 +instance = comp, \z80_|execute_|setM1~12 , z80_|execute_|setM1~12, spectrum, 1 +instance = comp, \z80_|execute_|setM1~14 , z80_|execute_|setM1~14, spectrum, 1 +instance = comp, \z80_|execute_|setM1~41 , z80_|execute_|setM1~41, spectrum, 1 +instance = comp, \z80_|execute_|setM1~42 , z80_|execute_|setM1~42, spectrum, 1 +instance = comp, \z80_|execute_|setM1~43 , z80_|execute_|setM1~43, spectrum, 1 +instance = comp, \z80_|execute_|setM1~44 , z80_|execute_|setM1~44, spectrum, 1 +instance = comp, \z80_|execute_|setM1~50 , z80_|execute_|setM1~50, spectrum, 1 +instance = comp, \z80_|execute_|setM1~51 , z80_|execute_|setM1~51, spectrum, 1 +instance = comp, \z80_|execute_|setM1~6 , z80_|execute_|setM1~6, spectrum, 1 +instance = comp, \z80_|execute_|setM1~7 , z80_|execute_|setM1~7, spectrum, 1 +instance = comp, \z80_|execute_|setM1~8 , z80_|execute_|setM1~8, spectrum, 1 +instance = comp, \z80_|execute_|setM1~9 , z80_|execute_|setM1~9, spectrum, 1 +instance = comp, \z80_|execute_|setM1~10 , z80_|execute_|setM1~10, spectrum, 1 +instance = comp, \z80_|execute_|setM1~11 , z80_|execute_|setM1~11, spectrum, 1 +instance = comp, \z80_|execute_|setM1~17 , z80_|execute_|setM1~17, spectrum, 1 +instance = comp, \z80_|execute_|setM1~31 , z80_|execute_|setM1~31, spectrum, 1 +instance = comp, \z80_|execute_|setM1~28 , z80_|execute_|setM1~28, spectrum, 1 +instance = comp, \z80_|execute_|setM1~30 , z80_|execute_|setM1~30, spectrum, 1 +instance = comp, \z80_|execute_|setM1~32 , z80_|execute_|setM1~32, spectrum, 1 +instance = comp, \z80_|execute_|setM1~33 , z80_|execute_|setM1~33, spectrum, 1 +instance = comp, \z80_|execute_|setM1~25 , z80_|execute_|setM1~25, spectrum, 1 +instance = comp, \z80_|execute_|setM1~26 , z80_|execute_|setM1~26, spectrum, 1 +instance = comp, \z80_|execute_|setM1~24 , z80_|execute_|setM1~24, spectrum, 1 +instance = comp, \z80_|execute_|setM1~27 , z80_|execute_|setM1~27, spectrum, 1 +instance = comp, \z80_|execute_|setM1~22 , z80_|execute_|setM1~22, spectrum, 1 +instance = comp, \z80_|execute_|setM1~21 , z80_|execute_|setM1~21, spectrum, 1 +instance = comp, \z80_|execute_|setM1~53 , z80_|execute_|setM1~53, spectrum, 1 +instance = comp, \z80_|execute_|setM1~23 , z80_|execute_|setM1~23, spectrum, 1 +instance = comp, \z80_|execute_|setM1~18 , z80_|execute_|setM1~18, spectrum, 1 +instance = comp, \z80_|execute_|setM1~19 , z80_|execute_|setM1~19, spectrum, 1 +instance = comp, \z80_|execute_|setM1~20 , z80_|execute_|setM1~20, spectrum, 1 +instance = comp, \z80_|execute_|setM1~34 , z80_|execute_|setM1~34, spectrum, 1 +instance = comp, \z80_|execute_|setM1~52 , z80_|execute_|setM1~52, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_14 , z80_|sequencer_|SYNTHESIZED_WIRE_14, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T3_ff , z80_|sequencer_|DFFE_T3_ff, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 , z80_|execute_|ctl_reg_sys_hilo_1M1T3_3, spectrum, 1 +instance = comp, \z80_|decode_state_|in_halt~0 , z80_|decode_state_|in_halt~0, spectrum, 1 +instance = comp, \z80_|decode_state_|in_halt~1 , z80_|decode_state_|in_halt~1, spectrum, 1 +instance = comp, \z80_|decode_state_|in_halt , z80_|decode_state_|in_halt, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~2 , z80_|execute_|ctl_bus_db_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~5 , z80_|execute_|ctl_bus_db_oe~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~6 , z80_|execute_|ctl_bus_db_oe~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~4 , z80_|execute_|ctl_bus_db_oe~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe , z80_|execute_|ctl_bus_db_oe, spectrum, 1 +instance = comp, \z80_|bus_control_|db[0]~6 , z80_|bus_control_|db[0]~6, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][3]~93 , ula_|zx_keyboard_|keys[1][3]~93, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][3]~94 , ula_|zx_keyboard_|keys[1][3]~94, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][3] , ula_|zx_keyboard_|keys[1][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][3]~96 , ula_|zx_keyboard_|keys[0][3]~96, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][3]~98 , ula_|zx_keyboard_|keys[0][3]~98, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][3] , ula_|zx_keyboard_|keys[0][3], spectrum, 1 +instance = comp, \D[3]~65 , D[3]~65, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3]~99 , ula_|zx_keyboard_|keys[3][3]~99, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3]~100 , ula_|zx_keyboard_|keys[3][3]~100, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3] , ula_|zx_keyboard_|keys[3][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~101 , ula_|zx_keyboard_|keys[2][3]~101, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~102 , ula_|zx_keyboard_|keys[2][3]~102, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~133 , ula_|zx_keyboard_|keys[2][3]~133, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~103 , ula_|zx_keyboard_|keys[2][3]~103, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3] , ula_|zx_keyboard_|keys[2][3], spectrum, 1 +instance = comp, \D[3]~66 , D[3]~66, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][3]~104 , ula_|zx_keyboard_|keys[5][3]~104, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][3]~105 , ula_|zx_keyboard_|keys[5][3]~105, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][3] , ula_|zx_keyboard_|keys[5][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~106 , ula_|zx_keyboard_|keys[4][3]~106, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Selector5~1 , ula_|zx_keyboard_|Selector5~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Selector5~0 , ula_|zx_keyboard_|Selector5~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~134 , ula_|zx_keyboard_|keys[4][3]~134, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~107 , ula_|zx_keyboard_|keys[4][3]~107, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~135 , ula_|zx_keyboard_|keys[4][3]~135, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~108 , ula_|zx_keyboard_|keys[4][3]~108, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3] , ula_|zx_keyboard_|keys[4][3], spectrum, 1 +instance = comp, \D[3]~67 , D[3]~67, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[7][3]~112 , ula_|zx_keyboard_|keys[7][3]~112, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[7][3]~113 , ula_|zx_keyboard_|keys[7][3]~113, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[7][3]~114 , ula_|zx_keyboard_|keys[7][3]~114, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[7][3] , ula_|zx_keyboard_|keys[7][3], spectrum, 1 -instance = comp, \D[3]~57 , D[3]~57, spectrum, 1 -instance = comp, \D[3]~58 , D[3]~58, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a27 , ram1|altsyncram_component|auto_generated|ram_block1a27, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~109 , ula_|zx_keyboard_|keys[6][3]~109, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~110 , ula_|zx_keyboard_|keys[6][3]~110, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~137 , ula_|zx_keyboard_|keys[6][3]~137, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~138 , ula_|zx_keyboard_|keys[6][3]~138, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3] , ula_|zx_keyboard_|keys[6][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row~2 , ula_|zx_keyboard_|key_row~2, spectrum, 1 +instance = comp, \D[3]~68 , D[3]~68, spectrum, 1 +instance = comp, \D[3]~69 , D[3]~69, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a19 , ram1|altsyncram_component|auto_generated|ram_block1a19, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a11 , ram1|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a3 , ram1|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 , ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 , ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a11 , ram0|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a11 , ram1|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \D[3]~73 , D[3]~73, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a27 , ram1|altsyncram_component|auto_generated|ram_block1a27, spectrum, 1 +instance = comp, \D[3]~74 , D[3]~74, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a11 , rom|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a11 , ram0|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \D[3]~70 , D[3]~70, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a3 , rom|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \D[3]~71 , D[3]~71, spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a3 , ram0|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 -instance = comp, \Selector3~0 , Selector3~0, spectrum, 1 -instance = comp, \Selector3~1 , Selector3~1, spectrum, 1 -instance = comp, \D[3]~52 , D[3]~52, spectrum, 1 -instance = comp, \D[3]~53 , D[3]~53, spectrum, 1 +instance = comp, \D[3]~72 , D[3]~72, spectrum, 1 +instance = comp, \D[3]~108 , D[3]~108, spectrum, 1 +instance = comp, \D[3]~95 , D[3]~95, spectrum, 1 +instance = comp, \D[3]~96 , D[3]~96, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] , z80_|data_pins_|SYNTHESIZED_WIRE_0[3], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[3] , z80_|data_pins_|dout[3], spectrum, 1 +instance = comp, \z80_|bus_control_|db[3]~20 , z80_|bus_control_|db[3]~20, spectrum, 1 +instance = comp, \z80_|bus_control_|db[3]~21 , z80_|bus_control_|db[3]~21, spectrum, 1 +instance = comp, \z80_|ir_|opcode[3] , z80_|ir_|opcode[3], spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~4 , z80_|execute_|ctl_mWrite~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_apin_mux~2 , z80_|execute_|ctl_apin_mux~2, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[0]~0 , z80_|address_pins_|DFFE_apin_latch[0]~0, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[0] , z80_|address_pins_|DFFE_apin_latch[0], spectrum, 1 +instance = comp, \D[0]~59 , D[0]~59, spectrum, 1 +instance = comp, \D[0]~60 , D[0]~60, spectrum, 1 +instance = comp, \D[1]~61 , D[1]~61, spectrum, 1 +instance = comp, \D[1]~62 , D[1]~62, spectrum, 1 +instance = comp, \D[2]~63 , D[2]~63, spectrum, 1 +instance = comp, \D[2]~64 , D[2]~64, spectrum, 1 +instance = comp, \D[3]~75 , D[3]~75, spectrum, 1 instance = comp, \D[3]~76 , D[3]~76, spectrum, 1 -instance = comp, \D[3]~77 , D[3]~77, spectrum, 1 -instance = comp, \ula_|always0~0 , ula_|always0~0, spectrum, 1 -instance = comp, \ula_|always0~1 , ula_|always0~1, spectrum, 1 -instance = comp, \ula_|pcm_outl[13] , ula_|pcm_outl[13], spectrum, 1 +instance = comp, \D[4]~82 , D[4]~82, spectrum, 1 +instance = comp, \D[4]~83 , D[4]~83, spectrum, 1 +instance = comp, \D[6]~92 , D[6]~92, spectrum, 1 +instance = comp, \D[6]~93 , D[6]~93, spectrum, 1 +instance = comp, \z80_|nM1_int~3 , z80_|nM1_int~3, spectrum, 1 +instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 , z80_|memory_ifc_|SYNTHESIZED_WIRE_16, spectrum, 1 +instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder , z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 , z80_|memory_ifc_|SYNTHESIZED_WIRE_17, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_mreq_ff2 , z80_|memory_ifc_|DFFE_mreq_ff2, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nMREQ_out~0 , z80_|memory_ifc_|nMREQ_out~0, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nMREQ_out~1 , z80_|memory_ifc_|nMREQ_out~1, spectrum, 1 +instance = comp, \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl , ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Idle~feeder , ula_|i2c_loader_|state.Idle~feeder, spectrum, 1 +instance = comp, \ula_|i2c_loader_|divider[0]~15 , ula_|i2c_loader_|divider[0]~15, spectrum, 1 +instance = comp, \ula_|i2c_loader_|divider[0] , ula_|i2c_loader_|divider[0], spectrum, 1 +instance = comp, \ula_|i2c_loader_|divider[1]~5 , ula_|i2c_loader_|divider[1]~5, spectrum, 1 +instance = comp, \ula_|i2c_loader_|divider[1] , ula_|i2c_loader_|divider[1], spectrum, 1 +instance = comp, \ula_|i2c_loader_|divider[2]~7 , ula_|i2c_loader_|divider[2]~7, spectrum, 1 +instance = comp, \ula_|i2c_loader_|divider[2] , ula_|i2c_loader_|divider[2], spectrum, 1 +instance = comp, \ula_|i2c_loader_|divider[3]~9 , ula_|i2c_loader_|divider[3]~9, spectrum, 1 +instance = comp, \ula_|i2c_loader_|divider[3] , ula_|i2c_loader_|divider[3], spectrum, 1 +instance = comp, \ula_|i2c_loader_|divider[4]~11 , ula_|i2c_loader_|divider[4]~11, spectrum, 1 +instance = comp, \ula_|i2c_loader_|divider[4] , ula_|i2c_loader_|divider[4], spectrum, 1 +instance = comp, \ula_|i2c_loader_|divider[5]~13 , ula_|i2c_loader_|divider[5]~13, spectrum, 1 +instance = comp, \ula_|i2c_loader_|divider[5] , ula_|i2c_loader_|divider[5], spectrum, 1 +instance = comp, \ula_|i2c_loader_|WideAnd0~0 , ula_|i2c_loader_|WideAnd0~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|WideAnd0 , ula_|i2c_loader_|WideAnd0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Idle , ula_|i2c_loader_|state.Idle, spectrum, 1 +instance = comp, \ula_|i2c_loader_|phase~0 , ula_|i2c_loader_|phase~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|phase[0] , ula_|i2c_loader_|phase[0], spectrum, 1 +instance = comp, \ula_|i2c_loader_|phase~1 , ula_|i2c_loader_|phase~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|phase[1] , ula_|i2c_loader_|phase[1], spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit~5 , ula_|i2c_loader_|nbit~5, spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[0]~8 , ula_|i2c_loader_|thisbyte[0]~8, spectrum, 1 +instance = comp, \ula_|i2c_loader_|Mux42~0 , ula_|i2c_loader_|Mux42~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte~4 , ula_|i2c_loader_|nbyte~4, spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[0]~7 , ula_|i2c_loader_|thisbyte[0]~7, spectrum, 1 +instance = comp, \I2C_SDAT~input , I2C_SDAT~input, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte[0]~1 , ula_|i2c_loader_|nbyte[0]~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte[0]~2 , ula_|i2c_loader_|nbyte[0]~2, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte[0]~3 , ula_|i2c_loader_|nbyte[0]~3, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte[1] , ula_|i2c_loader_|nbyte[1], spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Stop~0 , ula_|i2c_loader_|state.Stop~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Stop~1 , ula_|i2c_loader_|state.Stop~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Stop , ula_|i2c_loader_|state.Stop, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Idle~0 , ula_|i2c_loader_|state.Idle~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit~0 , ula_|i2c_loader_|nbit~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[2] , ula_|i2c_loader_|nbit[2], spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Done~0 , ula_|i2c_loader_|state.Done~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Ack~0 , ula_|i2c_loader_|state.Ack~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Ack~1 , ula_|i2c_loader_|state.Ack~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Ack , ula_|i2c_loader_|state.Ack, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte[1]~5 , ula_|i2c_loader_|nbyte[1]~5, spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[0]~18 , ula_|i2c_loader_|thisbyte[0]~18, spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[0] , ula_|i2c_loader_|thisbyte[0], spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[1]~10 , ula_|i2c_loader_|thisbyte[1]~10, spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[1] , ula_|i2c_loader_|thisbyte[1], spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[2]~12 , ula_|i2c_loader_|thisbyte[2]~12, spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[2] , ula_|i2c_loader_|thisbyte[2], spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[3]~14 , ula_|i2c_loader_|thisbyte[3]~14, spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[3] , ula_|i2c_loader_|thisbyte[3], spectrum, 1 +instance = comp, \ula_|i2c_loader_|Equal2~0 , ula_|i2c_loader_|Equal2~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause~0 , ula_|i2c_loader_|state.Pause~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[4]~16 , ula_|i2c_loader_|thisbyte[4]~16, spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[4] , ula_|i2c_loader_|thisbyte[4], spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause~1 , ula_|i2c_loader_|state.Pause~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Done~2 , ula_|i2c_loader_|state.Done~2, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause~2 , ula_|i2c_loader_|state.Pause~2, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause~3 , ula_|i2c_loader_|state.Pause~3, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause , ula_|i2c_loader_|state.Pause, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state~25 , ula_|i2c_loader_|state~25, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Start , ula_|i2c_loader_|state.Start, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte~0 , ula_|i2c_loader_|nbyte~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte[0] , ula_|i2c_loader_|nbyte[0], spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~1 , ula_|i2c_loader_|nbit[0]~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~2 , ula_|i2c_loader_|nbit[0]~2, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~3 , ula_|i2c_loader_|nbit[0]~3, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~4 , ula_|i2c_loader_|nbit[0]~4, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0] , ula_|i2c_loader_|nbit[0], spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit~6 , ula_|i2c_loader_|nbit~6, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[1] , ula_|i2c_loader_|nbit[1], spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Done~1 , ula_|i2c_loader_|state.Done~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state~27 , ula_|i2c_loader_|state~27, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state~24 , ula_|i2c_loader_|state~24, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state~26 , ula_|i2c_loader_|state~26, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Data~0 , ula_|i2c_loader_|state.Data~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Data , ula_|i2c_loader_|state.Data, spectrum, 1 +instance = comp, \ula_|i2c_loader_|scl_out~0 , ula_|i2c_loader_|scl_out~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|scl_out~_Duplicate_1 , ula_|i2c_loader_|scl_out~_Duplicate_1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|scl_out~1 , ula_|i2c_loader_|scl_out~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|scl_out~2 , ula_|i2c_loader_|scl_out~2, spectrum, 1 +instance = comp, \ula_|i2c_loader_|scl_out , ula_|i2c_loader_|scl_out, spectrum, 1 +instance = comp, \ula_|i2c_loader_|sda_out~_Duplicate_1 , ula_|i2c_loader_|sda_out~_Duplicate_1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~4 , ula_|i2c_loader_|shiftreg~4, spectrum, 1 +instance = comp, \ula_|i2c_loader_|Mux35~0 , ula_|i2c_loader_|Mux35~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~13 , ula_|i2c_loader_|shiftreg~13, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~14 , ula_|i2c_loader_|shiftreg~14, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~15 , ula_|i2c_loader_|shiftreg~15, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0]~24 , ula_|i2c_loader_|shiftreg[0]~24, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0]~6 , ula_|i2c_loader_|shiftreg[0]~6, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0]~7 , ula_|i2c_loader_|shiftreg[0]~7, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0]~8 , ula_|i2c_loader_|shiftreg[0]~8, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0] , ula_|i2c_loader_|shiftreg[0], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~21 , ula_|i2c_loader_|shiftreg~21, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~22 , ula_|i2c_loader_|shiftreg~22, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~23 , ula_|i2c_loader_|shiftreg~23, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[6]~10 , ula_|i2c_loader_|shiftreg[6]~10, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[6]~11 , ula_|i2c_loader_|shiftreg[6]~11, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[1] , ula_|i2c_loader_|shiftreg[1], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~18 , ula_|i2c_loader_|shiftreg~18, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~19 , ula_|i2c_loader_|shiftreg~19, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~20 , ula_|i2c_loader_|shiftreg~20, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[2] , ula_|i2c_loader_|shiftreg[2], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~16 , ula_|i2c_loader_|shiftreg~16, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~17 , ula_|i2c_loader_|shiftreg~17, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~26 , ula_|i2c_loader_|shiftreg~26, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[3] , ula_|i2c_loader_|shiftreg[3], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~25 , ula_|i2c_loader_|shiftreg~25, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[4] , ula_|i2c_loader_|shiftreg[4], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~12 , ula_|i2c_loader_|shiftreg~12, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[5] , ula_|i2c_loader_|shiftreg[5], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~9 , ula_|i2c_loader_|shiftreg~9, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[6] , ula_|i2c_loader_|shiftreg[6], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[7]~5 , ula_|i2c_loader_|shiftreg[7]~5, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[7] , ula_|i2c_loader_|shiftreg[7], spectrum, 1 +instance = comp, \ula_|i2c_loader_|sda_out~0 , ula_|i2c_loader_|sda_out~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|sda_out~1 , ula_|i2c_loader_|sda_out~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|sda_out~2 , ula_|i2c_loader_|sda_out~2, spectrum, 1 +instance = comp, \ula_|i2c_loader_|sda_out~3 , ula_|i2c_loader_|sda_out~3, spectrum, 1 +instance = comp, \ula_|i2c_loader_|sda_out~4 , ula_|i2c_loader_|sda_out~4, spectrum, 1 +instance = comp, \ula_|i2c_loader_|sda_out , ula_|i2c_loader_|sda_out, spectrum, 1 instance = comp, \ula_|i2s_intf_|mclk_r~0 , ula_|i2s_intf_|mclk_r~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|mclk_r~_Duplicate_1 , ula_|i2s_intf_|mclk_r~_Duplicate_1, spectrum, 1 +instance = comp, \ula_|i2s_intf_|mclk_r , ula_|i2s_intf_|mclk_r, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add0~1 , ula_|i2s_intf_|Add0~1, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add0~2 , ula_|i2s_intf_|Add0~2, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrdivider~2 , ula_|i2s_intf_|lrdivider~2, spectrum, 1 @@ -2433,6 +2977,7 @@ instance = comp, \ula_|i2s_intf_|lrdivider[4] , ula_|i2s_intf_|lrdivider[4], spe instance = comp, \ula_|i2s_intf_|Add0~10 , ula_|i2s_intf_|Add0~10, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrdivider[5]~6 , ula_|i2s_intf_|lrdivider[5]~6, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrdivider[5] , ula_|i2s_intf_|lrdivider[5], spectrum, 1 +instance = comp, \ula_|i2s_intf_|Equal0~1 , ula_|i2s_intf_|Equal0~1, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add0~12 , ula_|i2s_intf_|Add0~12, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrdivider[6]~5 , ula_|i2s_intf_|lrdivider[6]~5, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrdivider[6] , ula_|i2s_intf_|lrdivider[6], spectrum, 1 @@ -2446,11 +2991,25 @@ instance = comp, \ula_|i2s_intf_|Add0~18 , ula_|i2s_intf_|Add0~18, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrdivider[9]~3 , ula_|i2s_intf_|lrdivider[9]~3, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrdivider[9] , ula_|i2s_intf_|lrdivider[9], spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal0~0 , ula_|i2s_intf_|Equal0~0, spectrum, 1 -instance = comp, \ula_|i2s_intf_|Equal0~1 , ula_|i2s_intf_|Equal0~1, spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal0~2 , ula_|i2s_intf_|Equal0~2, spectrum, 1 +instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder , ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder, spectrum, 1 +instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_2 , ula_|i2s_intf_|lrclk_r~_Duplicate_2, spectrum, 1 +instance = comp, \ula_|i2s_intf_|lrclk_r~0 , ula_|i2s_intf_|lrclk_r~0, spectrum, 1 +instance = comp, \ula_|i2s_intf_|lrclk_r , ula_|i2s_intf_|lrclk_r, spectrum, 1 +instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_1 , ula_|i2s_intf_|lrclk_r~_Duplicate_1, spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[0]~5 , ula_|i2s_intf_|bitcount[0]~5, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bclk_r~_Duplicate_1 , ula_|i2s_intf_|bclk_r~_Duplicate_1, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[4]~15 , ula_|i2s_intf_|bitcount[4]~15, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[0] , ula_|i2s_intf_|bitcount[0], spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[1]~7 , ula_|i2s_intf_|bitcount[1]~7, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[1] , ula_|i2s_intf_|bitcount[1], spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[2]~9 , ula_|i2s_intf_|bitcount[2]~9, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[2] , ula_|i2s_intf_|bitcount[2], spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[3]~11 , ula_|i2s_intf_|bitcount[3]~11, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[3] , ula_|i2s_intf_|bitcount[3], spectrum, 1 instance = comp, \ula_|i2s_intf_|LessThan0~0 , ula_|i2s_intf_|LessThan0~0, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bclk_r~0 , ula_|i2s_intf_|bclk_r~0, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[4]~13 , ula_|i2s_intf_|bitcount[4]~13, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[4] , ula_|i2s_intf_|bitcount[4], spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~7 , ula_|i2s_intf_|Add2~7, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~8 , ula_|i2s_intf_|Add2~8, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~20 , ula_|i2s_intf_|Add2~20, spectrum, 1 @@ -2465,29 +3024,23 @@ instance = comp, \ula_|i2s_intf_|Add2~14 , ula_|i2s_intf_|Add2~14, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~16 , ula_|i2s_intf_|Add2~16, spectrum, 1 instance = comp, \ula_|i2s_intf_|bdivider[4] , ula_|i2s_intf_|bdivider[4], spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal1~0 , ula_|i2s_intf_|Equal1~0, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[8]~1 , ula_|i2s_intf_|shiftreg[8]~1, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[4]~1 , ula_|i2s_intf_|shiftreg[4]~1, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~18 , ula_|i2s_intf_|Add2~18, spectrum, 1 instance = comp, \ula_|i2s_intf_|bdivider[0] , ula_|i2s_intf_|bdivider[0], spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal1~1 , ula_|i2s_intf_|Equal1~1, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bclk_r~0 , ula_|i2s_intf_|bclk_r~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|bclk_r~1 , ula_|i2s_intf_|bclk_r~1, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder , ula_|i2s_intf_|bclk_r~_Duplicate_1feeder, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bclk_r~_Duplicate_1 , ula_|i2s_intf_|bclk_r~_Duplicate_1, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[4]~15 , ula_|i2s_intf_|bitcount[4]~15, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[0] , ula_|i2s_intf_|bitcount[0], spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[1]~7 , ula_|i2s_intf_|bitcount[1]~7, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[1] , ula_|i2s_intf_|bitcount[1], spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[2]~9 , ula_|i2s_intf_|bitcount[2]~9, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[2] , ula_|i2s_intf_|bitcount[2], spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[3]~11 , ula_|i2s_intf_|bitcount[3]~11, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[3] , ula_|i2s_intf_|bitcount[3], spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[4]~13 , ula_|i2s_intf_|bitcount[4]~13, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[4] , ula_|i2s_intf_|bitcount[4], spectrum, 1 +instance = comp, \ula_|i2s_intf_|bclk_r , ula_|i2s_intf_|bclk_r, spectrum, 1 +instance = comp, \ula_|pcm_outl[13]~feeder , ula_|pcm_outl[13]~feeder, spectrum, 1 +instance = comp, \ula_|always0~2 , ula_|always0~2, spectrum, 1 +instance = comp, \ula_|always0~3 , ula_|always0~3, spectrum, 1 +instance = comp, \ula_|pcm_outl[13] , ula_|pcm_outl[13], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[0]~19 , ula_|i2s_intf_|shiftreg[0]~19, spectrum, 1 instance = comp, \AUD_ADCDAT~input , AUD_ADCDAT~input, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[0]~20 , ula_|i2s_intf_|shiftreg[0]~20, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[0] , ula_|i2s_intf_|shiftreg[0], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~18 , ula_|i2s_intf_|shiftreg~18, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[8]~2 , ula_|i2s_intf_|shiftreg[8]~2, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[4]~2 , ula_|i2s_intf_|shiftreg[4]~2, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[1] , ula_|i2s_intf_|shiftreg[1], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~17 , ula_|i2s_intf_|shiftreg~17, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[2] , ula_|i2s_intf_|shiftreg[2], spectrum, 1 @@ -2511,546 +3064,16 @@ instance = comp, \ula_|i2s_intf_|shiftreg~8 , ula_|i2s_intf_|shiftreg~8, spectru instance = comp, \ula_|i2s_intf_|shiftreg[11] , ula_|i2s_intf_|shiftreg[11], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~7 , ula_|i2s_intf_|shiftreg~7, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[12] , ula_|i2s_intf_|shiftreg[12], spectrum, 1 -instance = comp, \ula_|i2s_intf_|lrclk_r~0 , ula_|i2s_intf_|lrclk_r~0, spectrum, 1 -instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder , ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder, spectrum, 1 -instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_2 , ula_|i2s_intf_|lrclk_r~_Duplicate_2, spectrum, 1 instance = comp, \ula_|i2s_intf_|PCM_INR[14]~0 , ula_|i2s_intf_|PCM_INR[14]~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|PCM_INR[14] , ula_|i2s_intf_|PCM_INR[14], spectrum, 1 -instance = comp, \ula_|ula_data~0 , ula_|ula_data~0, spectrum, 1 +instance = comp, \ula_|i2s_intf_|PCM_INL[14]~0 , ula_|i2s_intf_|PCM_INL[14]~0, spectrum, 1 +instance = comp, \ula_|i2s_intf_|PCM_INL[14] , ula_|i2s_intf_|PCM_INL[14], spectrum, 1 +instance = comp, \ula_|pcm_outr~0 , ula_|pcm_outr~0, spectrum, 1 instance = comp, \ula_|pcm_outl[12] , ula_|pcm_outl[12], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~6 , ula_|i2s_intf_|shiftreg~6, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[13] , ula_|i2s_intf_|shiftreg[13], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~5 , ula_|i2s_intf_|shiftreg~5, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[14] , ula_|i2s_intf_|shiftreg[14], spectrum, 1 -instance = comp, \ula_|i2s_intf_|PCM_INL[14]~0 , ula_|i2s_intf_|PCM_INL[14]~0, spectrum, 1 -instance = comp, \ula_|i2s_intf_|PCM_INL[14] , ula_|i2s_intf_|PCM_INL[14], spectrum, 1 -instance = comp, \D[6]~72 , D[6]~72, spectrum, 1 -instance = comp, \D[6]~73 , D[6]~73, spectrum, 1 -instance = comp, \D[6]~74 , D[6]~74, spectrum, 1 -instance = comp, \D[6]~81 , D[6]~81, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] , z80_|data_pins_|SYNTHESIZED_WIRE_0[6], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[6] , z80_|data_pins_|dout[6], spectrum, 1 -instance = comp, \z80_|bus_control_|db[6]~5 , z80_|bus_control_|db[6]~5, spectrum, 1 -instance = comp, \z80_|bus_control_|db[6]~7 , z80_|bus_control_|db[6]~7, spectrum, 1 -instance = comp, \z80_|ir_|opcode[6] , z80_|ir_|opcode[6], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal13~0 , z80_|pla_decode_|Equal13~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_im_we , z80_|execute_|ctl_im_we, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~5 , z80_|execute_|ctl_sw_1d~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~6 , z80_|execute_|ctl_sw_1d~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~7 , z80_|execute_|ctl_sw_1d~7, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~10 , z80_|alu_control_|db[6]~10, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~11 , z80_|alu_control_|db[6]~11, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~20 , z80_|alu_control_|db[2]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_ds[2]~2 , z80_|reg_file_|db_lo_ds[2]~2, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~21 , z80_|alu_control_|db[2]~21, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~22 , z80_|alu_control_|db[2]~22, spectrum, 1 -instance = comp, \z80_|bus_control_|db[2]~10 , z80_|bus_control_|db[2]~10, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2]~58 , ula_|zx_keyboard_|keys[5][2]~58, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2]~59 , ula_|zx_keyboard_|keys[5][2]~59, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2] , ula_|zx_keyboard_|keys[5][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2]~60 , ula_|zx_keyboard_|keys[4][2]~60, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2]~133 , ula_|zx_keyboard_|keys[4][2]~133, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~132 , ula_|zx_keyboard_|keys[3][4]~132, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2]~61 , ula_|zx_keyboard_|keys[4][2]~61, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2] , ula_|zx_keyboard_|keys[4][2], spectrum, 1 -instance = comp, \D[2]~34 , D[2]~34, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Equal0~2 , ula_|zx_keyboard_|Equal0~2, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4]~51 , ula_|zx_keyboard_|keys[7][4]~51, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][2]~53 , ula_|zx_keyboard_|keys[3][2]~53, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][2]~54 , ula_|zx_keyboard_|keys[3][2]~54, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][2] , ula_|zx_keyboard_|keys[3][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][4]~55 , ula_|zx_keyboard_|keys[1][4]~55, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][2]~56 , ula_|zx_keyboard_|keys[2][2]~56, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][2]~57 , ula_|zx_keyboard_|keys[2][2]~57, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][2] , ula_|zx_keyboard_|keys[2][2], spectrum, 1 -instance = comp, \D[2]~33 , D[2]~33, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][2]~48 , ula_|zx_keyboard_|keys[1][2]~48, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][2]~49 , ula_|zx_keyboard_|keys[1][2]~49, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][2] , ula_|zx_keyboard_|keys[1][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][2]~50 , ula_|zx_keyboard_|keys[0][2]~50, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][2]~52 , ula_|zx_keyboard_|keys[0][2]~52, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][2] , ula_|zx_keyboard_|keys[0][2], spectrum, 1 -instance = comp, \D[2]~32 , D[2]~32, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~63 , ula_|zx_keyboard_|keys[7][2]~63, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~65 , ula_|zx_keyboard_|keys[7][2]~65, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~66 , ula_|zx_keyboard_|keys[7][2]~66, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~67 , ula_|zx_keyboard_|keys[7][2]~67, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2] , ula_|zx_keyboard_|keys[7][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~68 , ula_|zx_keyboard_|keys[5][0]~68, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2]~69 , ula_|zx_keyboard_|keys[6][2]~69, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2]~70 , ula_|zx_keyboard_|keys[6][2]~70, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2]~71 , ula_|zx_keyboard_|keys[6][2]~71, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2] , ula_|zx_keyboard_|keys[6][2], spectrum, 1 -instance = comp, \D[2]~35 , D[2]~35, spectrum, 1 -instance = comp, \D[2]~36 , D[2]~36, spectrum, 1 -instance = comp, \D[2]~83 , D[2]~83, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a2 , ram1|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a18 , ram1|altsyncram_component|auto_generated|ram_block1a18, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 , ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a10 , ram1|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a26 , ram1|altsyncram_component|auto_generated|ram_block1a26, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 , ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a10 , ram0|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a2 , rom|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a2 , ram0|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \Selector0~0 , Selector0~0, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a10 , rom|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 -instance = comp, \Selector0~1 , Selector0~1, spectrum, 1 -instance = comp, \D[2]~37 , D[2]~37, spectrum, 1 -instance = comp, \D[2]~38 , D[2]~38, spectrum, 1 -instance = comp, \D[2]~39 , D[2]~39, spectrum, 1 -instance = comp, \D[2]~40 , D[2]~40, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] , z80_|data_pins_|SYNTHESIZED_WIRE_0[2], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[2] , z80_|data_pins_|dout[2], spectrum, 1 -instance = comp, \z80_|bus_control_|db[2]~11 , z80_|bus_control_|db[2]~11, spectrum, 1 -instance = comp, \z80_|ir_|opcode[2] , z80_|ir_|opcode[2], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal3~1 , z80_|pla_decode_|Equal3~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal3~2 , z80_|pla_decode_|Equal3~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_iy_set~2 , z80_|execute_|ctl_state_iy_set~2, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instIY1 , z80_|decode_state_|DFFE_instIY1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~5 , z80_|execute_|ctl_ir_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~15 , z80_|execute_|ctl_ir_we~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~6 , z80_|execute_|ctl_alu_bs_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~1 , z80_|execute_|ctl_bus_db_oe~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~3 , z80_|execute_|ctl_bus_db_oe~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~4 , z80_|execute_|ctl_bus_db_oe~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~5 , z80_|execute_|ctl_bus_db_oe~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe , z80_|execute_|ctl_bus_db_oe, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~82 , ula_|zx_keyboard_|keys[5][0]~82, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~83 , ula_|zx_keyboard_|keys[5][0]~83, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~84 , ula_|zx_keyboard_|keys[5][0]~84, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0] , ula_|zx_keyboard_|keys[5][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][0]~86 , ula_|zx_keyboard_|keys[4][0]~86, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][0]~85 , ula_|zx_keyboard_|keys[4][0]~85, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][0]~87 , ula_|zx_keyboard_|keys[4][0]~87, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][0] , ula_|zx_keyboard_|keys[4][0], spectrum, 1 -instance = comp, \D[0]~45 , D[0]~45, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][0]~81 , ula_|zx_keyboard_|keys[2][0]~81, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][0] , ula_|zx_keyboard_|keys[2][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][0]~80 , ula_|zx_keyboard_|keys[3][0]~80, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][0] , ula_|zx_keyboard_|keys[3][0], spectrum, 1 -instance = comp, \D[0]~44 , D[0]~44, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~134 , ula_|zx_keyboard_|keys[7][0]~134, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~3 , ula_|zx_keyboard_|WideOr16~3, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~88 , ula_|zx_keyboard_|keys[7][0]~88, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~89 , ula_|zx_keyboard_|keys[7][0]~89, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~90 , ula_|zx_keyboard_|keys[7][0]~90, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0] , ula_|zx_keyboard_|keys[7][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~1 , ula_|zx_keyboard_|shifted~1, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][0]~91 , ula_|zx_keyboard_|keys[6][0]~91, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][0]~92 , ula_|zx_keyboard_|keys[6][0]~92, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][0]~93 , ula_|zx_keyboard_|keys[6][0]~93, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][0] , ula_|zx_keyboard_|keys[6][0], spectrum, 1 -instance = comp, \D[0]~46 , D[0]~46, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr4~0 , ula_|zx_keyboard_|WideOr4~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys~77 , ula_|zx_keyboard_|keys~77, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~74 , ula_|zx_keyboard_|keys[4][3]~74, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr0~0 , ula_|zx_keyboard_|WideOr0~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys~75 , ula_|zx_keyboard_|keys~75, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0]~76 , ula_|zx_keyboard_|keys[0][0]~76, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0]~78 , ula_|zx_keyboard_|keys[0][0]~78, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0] , ula_|zx_keyboard_|keys[0][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][0]~72 , ula_|zx_keyboard_|keys[1][0]~72, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][0]~73 , ula_|zx_keyboard_|keys[1][0]~73, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][0] , ula_|zx_keyboard_|keys[1][0], spectrum, 1 -instance = comp, \D[0]~43 , D[0]~43, spectrum, 1 -instance = comp, \D[0]~47 , D[0]~47, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a8 , ram1|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a24 , ram1|altsyncram_component|auto_generated|ram_block1a24, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a16 , ram1|altsyncram_component|auto_generated|ram_block1a16, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a0 , ram1|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 , ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 , ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a8 , rom|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a8 , ram0|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a0 , ram0|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 -instance = comp, \Selector2~0 , Selector2~0, spectrum, 1 -instance = comp, \Selector2~1 , Selector2~1, spectrum, 1 -instance = comp, \D[0]~41 , D[0]~41, spectrum, 1 -instance = comp, \D[0]~42 , D[0]~42, spectrum, 1 -instance = comp, \D[0]~48 , D[0]~48, spectrum, 1 -instance = comp, \D[0]~49 , D[0]~49, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] , z80_|data_pins_|SYNTHESIZED_WIRE_0[0], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[0] , z80_|data_pins_|dout[0], spectrum, 1 -instance = comp, \z80_|bus_control_|db[0]~14 , z80_|bus_control_|db[0]~14, spectrum, 1 -instance = comp, \z80_|bus_control_|db[0]~15 , z80_|bus_control_|db[0]~15, spectrum, 1 -instance = comp, \z80_|ir_|opcode[0] , z80_|ir_|opcode[0], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~0 , z80_|pla_decode_|Equal33~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~3 , z80_|execute_|ctl_alu_oe~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~4 , z80_|execute_|ctl_sw_2u~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~5 , z80_|execute_|ctl_sw_2u~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~6 , z80_|execute_|ctl_reg_out_lo~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~7 , z80_|execute_|ctl_reg_out_lo~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~8 , z80_|execute_|ctl_reg_out_lo~8, spectrum, 1 -instance = comp, \z80_|sw1_|db_down[5]~1 , z80_|sw1_|db_down[5]~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_36 , z80_|alu_flags_|SYNTHESIZED_WIRE_36, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_yf , z80_|alu_flags_|flags_yf, spectrum, 1 -instance = comp, \z80_|alu_control_|db[5]~27 , z80_|alu_control_|db[5]~27, spectrum, 1 -instance = comp, \z80_|alu_control_|db[5]~28 , z80_|alu_control_|db[5]~28, spectrum, 1 -instance = comp, \z80_|alu_control_|db[5]~29 , z80_|alu_control_|db[5]~29, spectrum, 1 -instance = comp, \D[5]~68 , D[5]~68, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a29 , ram1|altsyncram_component|auto_generated|ram_block1a29, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a21 , ram1|altsyncram_component|auto_generated|ram_block1a21, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a5 , ram1|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a13 , ram1|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a13 , rom|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a13 , ram0|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a5 , rom|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a5 , ram0|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 -instance = comp, \Mux2~0 , Mux2~0, spectrum, 1 -instance = comp, \Mux2~1 , Mux2~1, spectrum, 1 -instance = comp, \D[5]~88 , D[5]~88, spectrum, 1 -instance = comp, \D[5]~69 , D[5]~69, spectrum, 1 -instance = comp, \D[5]~80 , D[5]~80, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] , z80_|data_pins_|SYNTHESIZED_WIRE_0[5], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[5] , z80_|data_pins_|dout[5], spectrum, 1 -instance = comp, \z80_|bus_control_|db[5]~16 , z80_|bus_control_|db[5]~16, spectrum, 1 -instance = comp, \z80_|bus_control_|db[5]~17 , z80_|bus_control_|db[5]~17, spectrum, 1 -instance = comp, \z80_|ir_|opcode[5] , z80_|ir_|opcode[5], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~1 , z80_|pla_decode_|Equal33~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~11 , z80_|execute_|ctl_mRead~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~5 , z80_|execute_|ctl_al_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~20 , z80_|execute_|ctl_reg_sel_pc~20, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~15 , z80_|execute_|fMRead~15, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~16 , z80_|execute_|fMRead~16, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~28 , z80_|execute_|fMRead~28, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~30 , z80_|execute_|fMRead~30, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~31 , z80_|execute_|fMRead~31, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~29 , z80_|execute_|fMRead~29, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~32 , z80_|execute_|fMRead~32, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~33 , z80_|execute_|fMRead~33, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~37 , z80_|execute_|fMRead~37, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~34 , z80_|execute_|fMRead~34, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~35 , z80_|execute_|fMRead~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~32 , z80_|execute_|ctl_mRead~32, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~21 , z80_|execute_|fMRead~21, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~19 , z80_|execute_|fMRead~19, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~20 , z80_|execute_|fMRead~20, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~10 , z80_|execute_|fMRead~10, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~17 , z80_|execute_|fMRead~17, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~18 , z80_|execute_|fMRead~18, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~22 , z80_|execute_|fMRead~22, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~23 , z80_|execute_|fMRead~23, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~24 , z80_|execute_|fMRead~24, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~25 , z80_|execute_|fMRead~25, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~39 , z80_|execute_|pc_inc_hold~39, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~26 , z80_|execute_|fMRead~26, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~36 , z80_|execute_|fMRead~36, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_re , z80_|pin_control_|bus_db_pin_re, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a31 , ram1|altsyncram_component|auto_generated|ram_block1a31, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a15 , ram1|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a7 , ram1|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a23 , ram1|altsyncram_component|auto_generated|ram_block1a23, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a15 , ram0|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a7 , ram0|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 -instance = comp, \Mux0~0 , Mux0~0, spectrum, 1 -instance = comp, \Mux0~1 , Mux0~1, spectrum, 1 -instance = comp, \D[7]~89 , D[7]~89, spectrum, 1 -instance = comp, \D[7]~75 , D[7]~75, spectrum, 1 -instance = comp, \D[7]~82 , D[7]~82, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] , z80_|data_pins_|SYNTHESIZED_WIRE_0[7], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[7] , z80_|data_pins_|dout[7], spectrum, 1 -instance = comp, \z80_|bus_control_|db[7]~8 , z80_|bus_control_|db[7]~8, spectrum, 1 -instance = comp, \z80_|bus_control_|db[7]~9 , z80_|bus_control_|db[7]~9, spectrum, 1 -instance = comp, \z80_|ir_|opcode[7] , z80_|ir_|opcode[7], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal52~0 , z80_|pla_decode_|Equal52~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_66_oe~2 , z80_|execute_|ctl_66_oe~2, spectrum, 1 -instance = comp, \z80_|interrupts_|im1 , z80_|interrupts_|im1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_ff_oe~0 , z80_|execute_|ctl_bus_ff_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_ff_oe~1 , z80_|execute_|ctl_bus_ff_oe~1, spectrum, 1 -instance = comp, \z80_|bus_control_|db[0]~4 , z80_|bus_control_|db[0]~4, spectrum, 1 -instance = comp, \z80_|bus_control_|db[3]~20 , z80_|bus_control_|db[3]~20, spectrum, 1 -instance = comp, \z80_|bus_control_|db[3]~21 , z80_|bus_control_|db[3]~21, spectrum, 1 -instance = comp, \z80_|ir_|opcode[3] , z80_|ir_|opcode[3], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal21~0 , z80_|pla_decode_|Equal21~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal77~1 , z80_|pla_decode_|Equal77~1, spectrum, 1 -instance = comp, \z80_|decode_state_|in_halt~0 , z80_|decode_state_|in_halt~0, spectrum, 1 -instance = comp, \z80_|decode_state_|in_halt~1 , z80_|decode_state_|in_halt~1, spectrum, 1 -instance = comp, \z80_|decode_state_|in_halt , z80_|decode_state_|in_halt, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~5 , z80_|execute_|ctl_mWrite~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~2 , z80_|execute_|ctl_bus_db_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~4 , z80_|execute_|ctl_bus_db_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~6 , z80_|execute_|ctl_bus_db_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~8 , z80_|execute_|ctl_bus_db_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 , z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~3 , z80_|execute_|ctl_bus_db_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~7 , z80_|execute_|ctl_bus_db_we~7, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~124 , ula_|zx_keyboard_|keys[5][4]~124, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~125 , ula_|zx_keyboard_|keys[5][4]~125, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4] , ula_|zx_keyboard_|keys[5][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4]~126 , ula_|zx_keyboard_|keys[4][4]~126, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4]~127 , ula_|zx_keyboard_|keys[4][4]~127, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4]~128 , ula_|zx_keyboard_|keys[4][4]~128, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4] , ula_|zx_keyboard_|keys[4][4], spectrum, 1 -instance = comp, \D[4]~64 , D[4]~64, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~119 , ula_|zx_keyboard_|keys[3][4]~119, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~138 , ula_|zx_keyboard_|keys[3][4]~138, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~120 , ula_|zx_keyboard_|keys[3][4]~120, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4] , ula_|zx_keyboard_|keys[3][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~121 , ula_|zx_keyboard_|keys[2][4]~121, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~122 , ula_|zx_keyboard_|keys[2][4]~122, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~123 , ula_|zx_keyboard_|keys[2][4]~123, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4] , ula_|zx_keyboard_|keys[2][4], spectrum, 1 -instance = comp, \D[4]~63 , D[4]~63, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4]~129 , ula_|zx_keyboard_|keys[7][4]~129, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4] , ula_|zx_keyboard_|keys[7][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~130 , ula_|zx_keyboard_|keys[6][4]~130, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~131 , ula_|zx_keyboard_|keys[6][4]~131, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4] , ula_|zx_keyboard_|keys[6][4], spectrum, 1 -instance = comp, \D[4]~65 , D[4]~65, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4]~118 , ula_|zx_keyboard_|keys[0][4]~118, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4] , ula_|zx_keyboard_|keys[0][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][4]~117 , ula_|zx_keyboard_|keys[1][4]~117, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][4] , ula_|zx_keyboard_|keys[1][4], spectrum, 1 -instance = comp, \D[4]~62 , D[4]~62, spectrum, 1 -instance = comp, \D[4]~66 , D[4]~66, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a12 , ram1|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a28 , ram1|altsyncram_component|auto_generated|ram_block1a28, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a20 , ram1|altsyncram_component|auto_generated|ram_block1a20, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a4 , ram1|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a12 , ram0|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a4 , ram0|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \Selector4~0 , Selector4~0, spectrum, 1 -instance = comp, \Selector4~1 , Selector4~1, spectrum, 1 -instance = comp, \D[4]~60 , D[4]~60, spectrum, 1 -instance = comp, \D[4]~61 , D[4]~61, spectrum, 1 -instance = comp, \D[4]~78 , D[4]~78, spectrum, 1 -instance = comp, \D[4]~79 , D[4]~79, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] , z80_|data_pins_|SYNTHESIZED_WIRE_0[4], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[4] , z80_|data_pins_|dout[4], spectrum, 1 -instance = comp, \z80_|bus_control_|db[4]~18 , z80_|bus_control_|db[4]~18, spectrum, 1 -instance = comp, \z80_|bus_control_|db[4]~19 , z80_|bus_control_|db[4]~19, spectrum, 1 -instance = comp, \z80_|ir_|opcode[4] , z80_|ir_|opcode[4], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal32~0 , z80_|pla_decode_|Equal32~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal43~0 , z80_|pla_decode_|Equal43~0, spectrum, 1 -instance = comp, \z80_|interrupts_|test1~2 , z80_|interrupts_|test1~2, spectrum, 1 -instance = comp, \z80_|interrupts_|test1~3 , z80_|interrupts_|test1~3, spectrum, 1 -instance = comp, \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED , z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED, spectrum, 1 -instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_4 , z80_|clk_delay_|SYNTHESIZED_WIRE_4, spectrum, 1 -instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_7 , z80_|clk_delay_|SYNTHESIZED_WIRE_7, spectrum, 1 -instance = comp, \z80_|clk_delay_|hold_clk_iorq , z80_|clk_delay_|hold_clk_iorq, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T1_ff , z80_|sequencer_|DFFE_T1_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_13 , z80_|sequencer_|SYNTHESIZED_WIRE_13, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T2_ff , z80_|sequencer_|DFFE_T2_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_14 , z80_|sequencer_|SYNTHESIZED_WIRE_14, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T3_ff , z80_|sequencer_|DFFE_T3_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_15 , z80_|sequencer_|SYNTHESIZED_WIRE_15, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T4_ff , z80_|sequencer_|DFFE_T4_ff, spectrum, 1 -instance = comp, \z80_|execute_|ctl_eval_cond~0 , z80_|execute_|ctl_eval_cond~0, spectrum, 1 -instance = comp, \z80_|execute_|setM1~40 , z80_|execute_|setM1~40, spectrum, 1 -instance = comp, \z80_|execute_|setM1~53 , z80_|execute_|setM1~53, spectrum, 1 -instance = comp, \z80_|execute_|nextM~3 , z80_|execute_|nextM~3, spectrum, 1 -instance = comp, \z80_|execute_|nextM~9 , z80_|execute_|nextM~9, spectrum, 1 -instance = comp, \z80_|execute_|nextM~10 , z80_|execute_|nextM~10, spectrum, 1 -instance = comp, \z80_|execute_|nextM~12 , z80_|execute_|nextM~12, spectrum, 1 -instance = comp, \z80_|execute_|nextM~15 , z80_|execute_|nextM~15, spectrum, 1 -instance = comp, \z80_|execute_|nextM~5 , z80_|execute_|nextM~5, spectrum, 1 -instance = comp, \z80_|execute_|nextM~7 , z80_|execute_|nextM~7, spectrum, 1 -instance = comp, \z80_|execute_|nextM~8 , z80_|execute_|nextM~8, spectrum, 1 -instance = comp, \z80_|execute_|nextM~13 , z80_|execute_|nextM~13, spectrum, 1 -instance = comp, \z80_|execute_|nextM~14 , z80_|execute_|nextM~14, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M1_ff~0 , z80_|sequencer_|DFFE_M1_ff~0, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M1_ff , z80_|sequencer_|DFFE_M1_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_17 , z80_|sequencer_|SYNTHESIZED_WIRE_17, spectrum, 1 -instance = comp, \z80_|sequencer_|T6 , z80_|sequencer_|T6, spectrum, 1 -instance = comp, \z80_|execute_|setM1~42 , z80_|execute_|setM1~42, spectrum, 1 -instance = comp, \z80_|execute_|setM1~43 , z80_|execute_|setM1~43, spectrum, 1 -instance = comp, \z80_|execute_|setM1~44 , z80_|execute_|setM1~44, spectrum, 1 -instance = comp, \z80_|execute_|setM1~45 , z80_|execute_|setM1~45, spectrum, 1 -instance = comp, \z80_|execute_|setM1~15 , z80_|execute_|setM1~15, spectrum, 1 -instance = comp, \z80_|execute_|setM1~14 , z80_|execute_|setM1~14, spectrum, 1 -instance = comp, \z80_|execute_|setM1~16 , z80_|execute_|setM1~16, spectrum, 1 -instance = comp, \z80_|execute_|setM1~50 , z80_|execute_|setM1~50, spectrum, 1 -instance = comp, \z80_|execute_|setM1~51 , z80_|execute_|setM1~51, spectrum, 1 -instance = comp, \z80_|execute_|setM1~11 , z80_|execute_|setM1~11, spectrum, 1 -instance = comp, \z80_|execute_|setM1~10 , z80_|execute_|setM1~10, spectrum, 1 -instance = comp, \z80_|execute_|setM1~12 , z80_|execute_|setM1~12, spectrum, 1 -instance = comp, \z80_|execute_|setM1~8 , z80_|execute_|setM1~8, spectrum, 1 -instance = comp, \z80_|execute_|setM1~9 , z80_|execute_|setM1~9, spectrum, 1 -instance = comp, \z80_|execute_|setM1~13 , z80_|execute_|setM1~13, spectrum, 1 -instance = comp, \z80_|execute_|setM1~18 , z80_|execute_|setM1~18, spectrum, 1 -instance = comp, \z80_|execute_|setM1~19 , z80_|execute_|setM1~19, spectrum, 1 -instance = comp, \z80_|execute_|setM1~25 , z80_|execute_|setM1~25, spectrum, 1 -instance = comp, \z80_|execute_|setM1~23 , z80_|execute_|setM1~23, spectrum, 1 -instance = comp, \z80_|execute_|setM1~22 , z80_|execute_|setM1~22, spectrum, 1 -instance = comp, \z80_|execute_|setM1~55 , z80_|execute_|setM1~55, spectrum, 1 -instance = comp, \z80_|execute_|setM1~24 , z80_|execute_|setM1~24, spectrum, 1 -instance = comp, \z80_|execute_|setM1~26 , z80_|execute_|setM1~26, spectrum, 1 -instance = comp, \z80_|execute_|setM1~27 , z80_|execute_|setM1~27, spectrum, 1 -instance = comp, \z80_|execute_|setM1~28 , z80_|execute_|setM1~28, spectrum, 1 -instance = comp, \z80_|execute_|setM1~33 , z80_|execute_|setM1~33, spectrum, 1 -instance = comp, \z80_|execute_|setM1~32 , z80_|execute_|setM1~32, spectrum, 1 -instance = comp, \z80_|execute_|setM1~29 , z80_|execute_|setM1~29, spectrum, 1 -instance = comp, \z80_|execute_|setM1~31 , z80_|execute_|setM1~31, spectrum, 1 -instance = comp, \z80_|execute_|setM1~34 , z80_|execute_|setM1~34, spectrum, 1 -instance = comp, \z80_|execute_|setM1~54 , z80_|execute_|setM1~54, spectrum, 1 -instance = comp, \z80_|execute_|setM1~20 , z80_|execute_|setM1~20, spectrum, 1 -instance = comp, \z80_|execute_|setM1~21 , z80_|execute_|setM1~21, spectrum, 1 -instance = comp, \z80_|execute_|setM1~35 , z80_|execute_|setM1~35, spectrum, 1 -instance = comp, \z80_|execute_|setM1~52 , z80_|execute_|setM1~52, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M2_ff~0 , z80_|sequencer_|DFFE_M2_ff~0, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M2_ff , z80_|sequencer_|DFFE_M2_ff, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~14 , z80_|execute_|ctl_alu_op_low~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~39 , z80_|execute_|ctl_inc_cy~39, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~36 , z80_|execute_|pc_inc_hold~36, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~35 , z80_|execute_|pc_inc_hold~35, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~37 , z80_|execute_|pc_inc_hold~37, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~38 , z80_|execute_|pc_inc_hold~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~68 , z80_|execute_|ctl_inc_cy~68, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~69 , z80_|execute_|ctl_inc_cy~69, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~70 , z80_|execute_|ctl_inc_cy~70, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[0]~0 , z80_|address_pins_|DFFE_apin_latch[0]~0, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[0] , z80_|address_pins_|DFFE_apin_latch[0], spectrum, 1 -instance = comp, \D[0]~84 , D[0]~84, spectrum, 1 -instance = comp, \D[0]~50 , D[0]~50, spectrum, 1 -instance = comp, \D[1]~85 , D[1]~85, spectrum, 1 -instance = comp, \D[1]~51 , D[1]~51, spectrum, 1 -instance = comp, \D[3]~86 , D[3]~86, spectrum, 1 -instance = comp, \D[3]~59 , D[3]~59, spectrum, 1 -instance = comp, \D[4]~87 , D[4]~87, spectrum, 1 -instance = comp, \D[4]~67 , D[4]~67, spectrum, 1 -instance = comp, \z80_|nM1_int~3 , z80_|nM1_int~3, spectrum, 1 -instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 , z80_|memory_ifc_|SYNTHESIZED_WIRE_16, spectrum, 1 -instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder , z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 , z80_|memory_ifc_|SYNTHESIZED_WIRE_17, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_mreq_ff2 , z80_|memory_ifc_|DFFE_mreq_ff2, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nMREQ_out~0 , z80_|memory_ifc_|nMREQ_out~0, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nMREQ_out~1 , z80_|memory_ifc_|nMREQ_out~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Idle~feeder , ula_|i2c_loader_|state.Idle~feeder, spectrum, 1 -instance = comp, \ula_|i2c_loader_|divider[0]~15 , ula_|i2c_loader_|divider[0]~15, spectrum, 1 -instance = comp, \ula_|i2c_loader_|divider[0] , ula_|i2c_loader_|divider[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|divider[1]~5 , ula_|i2c_loader_|divider[1]~5, spectrum, 1 -instance = comp, \ula_|i2c_loader_|divider[1] , ula_|i2c_loader_|divider[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|divider[2]~7 , ula_|i2c_loader_|divider[2]~7, spectrum, 1 -instance = comp, \ula_|i2c_loader_|divider[2] , ula_|i2c_loader_|divider[2], spectrum, 1 -instance = comp, \ula_|i2c_loader_|divider[3]~9 , ula_|i2c_loader_|divider[3]~9, spectrum, 1 -instance = comp, \ula_|i2c_loader_|divider[3] , ula_|i2c_loader_|divider[3], spectrum, 1 -instance = comp, \ula_|i2c_loader_|divider[4]~11 , ula_|i2c_loader_|divider[4]~11, spectrum, 1 -instance = comp, \ula_|i2c_loader_|divider[4] , ula_|i2c_loader_|divider[4], spectrum, 1 -instance = comp, \ula_|i2c_loader_|divider[5]~13 , ula_|i2c_loader_|divider[5]~13, spectrum, 1 -instance = comp, \ula_|i2c_loader_|divider[5] , ula_|i2c_loader_|divider[5], spectrum, 1 -instance = comp, \ula_|i2c_loader_|WideAnd0~0 , ula_|i2c_loader_|WideAnd0~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|WideAnd0 , ula_|i2c_loader_|WideAnd0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Idle , ula_|i2c_loader_|state.Idle, spectrum, 1 -instance = comp, \ula_|i2c_loader_|phase~0 , ula_|i2c_loader_|phase~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|phase[0] , ula_|i2c_loader_|phase[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|phase~1 , ula_|i2c_loader_|phase~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|phase[1] , ula_|i2c_loader_|phase[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|Mux42~0 , ula_|i2c_loader_|Mux42~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit~6 , ula_|i2c_loader_|nbit~6, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte~0 , ula_|i2c_loader_|nbyte~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[0]~7 , ula_|i2c_loader_|thisbyte[0]~7, spectrum, 1 -instance = comp, \I2C_SDAT~input , I2C_SDAT~input, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte[0]~1 , ula_|i2c_loader_|nbyte[0]~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte[0]~2 , ula_|i2c_loader_|nbyte[0]~2, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte[0]~3 , ula_|i2c_loader_|nbyte[0]~3, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte[0] , ula_|i2c_loader_|nbyte[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~1 , ula_|i2c_loader_|nbit[0]~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~2 , ula_|i2c_loader_|nbit[0]~2, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~3 , ula_|i2c_loader_|nbit[0]~3, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~4 , ula_|i2c_loader_|nbit[0]~4, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[1] , ula_|i2c_loader_|nbit[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Done~0 , ula_|i2c_loader_|state.Done~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Ack~0 , ula_|i2c_loader_|state.Ack~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Ack~1 , ula_|i2c_loader_|state.Ack~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Ack~2 , ula_|i2c_loader_|state.Ack~2, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Ack , ula_|i2c_loader_|state.Ack, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state~24 , ula_|i2c_loader_|state~24, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state~26 , ula_|i2c_loader_|state~26, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state~27 , ula_|i2c_loader_|state~27, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Data~0 , ula_|i2c_loader_|state.Data~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Data , ula_|i2c_loader_|state.Data, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit~5 , ula_|i2c_loader_|nbit~5, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0] , ula_|i2c_loader_|nbit[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit~0 , ula_|i2c_loader_|nbit~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[2] , ula_|i2c_loader_|nbit[2], spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Done~1 , ula_|i2c_loader_|state.Done~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Done~2 , ula_|i2c_loader_|state.Done~2, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Pause~2 , ula_|i2c_loader_|state.Pause~2, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Pause~0 , ula_|i2c_loader_|state.Pause~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[0]~8 , ula_|i2c_loader_|thisbyte[0]~8, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte[1]~5 , ula_|i2c_loader_|nbyte[1]~5, spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[0]~18 , ula_|i2c_loader_|thisbyte[0]~18, spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[0] , ula_|i2c_loader_|thisbyte[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[1]~10 , ula_|i2c_loader_|thisbyte[1]~10, spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[1] , ula_|i2c_loader_|thisbyte[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[2]~12 , ula_|i2c_loader_|thisbyte[2]~12, spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[2] , ula_|i2c_loader_|thisbyte[2], spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[3]~14 , ula_|i2c_loader_|thisbyte[3]~14, spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[3] , ula_|i2c_loader_|thisbyte[3], spectrum, 1 -instance = comp, \ula_|i2c_loader_|Equal2~0 , ula_|i2c_loader_|Equal2~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[4]~16 , ula_|i2c_loader_|thisbyte[4]~16, spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[4] , ula_|i2c_loader_|thisbyte[4], spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Pause~1 , ula_|i2c_loader_|state.Pause~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Pause~3 , ula_|i2c_loader_|state.Pause~3, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Pause , ula_|i2c_loader_|state.Pause, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state~25 , ula_|i2c_loader_|state~25, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Start , ula_|i2c_loader_|state.Start, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte~4 , ula_|i2c_loader_|nbyte~4, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte[1] , ula_|i2c_loader_|nbyte[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Stop~0 , ula_|i2c_loader_|state.Stop~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Stop~1 , ula_|i2c_loader_|state.Stop~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Stop , ula_|i2c_loader_|state.Stop, spectrum, 1 -instance = comp, \ula_|i2c_loader_|scl_out~0 , ula_|i2c_loader_|scl_out~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|scl_out~_Duplicate_1 , ula_|i2c_loader_|scl_out~_Duplicate_1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|scl_out~1 , ula_|i2c_loader_|scl_out~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|scl_out~2 , ula_|i2c_loader_|scl_out~2, spectrum, 1 -instance = comp, \ula_|i2c_loader_|scl_out , ula_|i2c_loader_|scl_out, spectrum, 1 -instance = comp, \ula_|i2c_loader_|sda_out~_Duplicate_1 , ula_|i2c_loader_|sda_out~_Duplicate_1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|Mux35~0 , ula_|i2c_loader_|Mux35~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0]~24 , ula_|i2c_loader_|shiftreg[0]~24, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0]~6 , ula_|i2c_loader_|shiftreg[0]~6, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0]~7 , ula_|i2c_loader_|shiftreg[0]~7, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0]~8 , ula_|i2c_loader_|shiftreg[0]~8, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0] , ula_|i2c_loader_|shiftreg[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~4 , ula_|i2c_loader_|shiftreg~4, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~21 , ula_|i2c_loader_|shiftreg~21, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~22 , ula_|i2c_loader_|shiftreg~22, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~23 , ula_|i2c_loader_|shiftreg~23, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[6]~10 , ula_|i2c_loader_|shiftreg[6]~10, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[6]~11 , ula_|i2c_loader_|shiftreg[6]~11, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[1] , ula_|i2c_loader_|shiftreg[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~18 , ula_|i2c_loader_|shiftreg~18, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~19 , ula_|i2c_loader_|shiftreg~19, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~20 , ula_|i2c_loader_|shiftreg~20, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[2] , ula_|i2c_loader_|shiftreg[2], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~14 , ula_|i2c_loader_|shiftreg~14, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~16 , ula_|i2c_loader_|shiftreg~16, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~17 , ula_|i2c_loader_|shiftreg~17, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~26 , ula_|i2c_loader_|shiftreg~26, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[3] , ula_|i2c_loader_|shiftreg[3], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~13 , ula_|i2c_loader_|shiftreg~13, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~15 , ula_|i2c_loader_|shiftreg~15, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~25 , ula_|i2c_loader_|shiftreg~25, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[4] , ula_|i2c_loader_|shiftreg[4], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~12 , ula_|i2c_loader_|shiftreg~12, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[5] , ula_|i2c_loader_|shiftreg[5], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~9 , ula_|i2c_loader_|shiftreg~9, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[6] , ula_|i2c_loader_|shiftreg[6], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[7]~5 , ula_|i2c_loader_|shiftreg[7]~5, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[7] , ula_|i2c_loader_|shiftreg[7], spectrum, 1 -instance = comp, \ula_|i2c_loader_|sda_out~0 , ula_|i2c_loader_|sda_out~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|sda_out~1 , ula_|i2c_loader_|sda_out~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|sda_out~2 , ula_|i2c_loader_|sda_out~2, spectrum, 1 -instance = comp, \ula_|i2c_loader_|sda_out~3 , ula_|i2c_loader_|sda_out~3, spectrum, 1 -instance = comp, \ula_|i2c_loader_|sda_out~4 , ula_|i2c_loader_|sda_out~4, spectrum, 1 -instance = comp, \ula_|i2c_loader_|sda_out , ula_|i2c_loader_|sda_out, spectrum, 1 -instance = comp, \ula_|i2s_intf_|mclk_r , ula_|i2s_intf_|mclk_r, spectrum, 1 -instance = comp, \ula_|i2s_intf_|lrclk_r , ula_|i2s_intf_|lrclk_r, spectrum, 1 -instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_1 , ula_|i2s_intf_|lrclk_r~_Duplicate_1, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bclk_r , ula_|i2s_intf_|bclk_r, spectrum, 1 instance = comp, \ula_|pcm_outl[14] , ula_|pcm_outl[14], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~4 , ula_|i2s_intf_|shiftreg~4, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[15] , ula_|i2s_intf_|shiftreg[15], spectrum, 1 @@ -3058,32 +3081,26 @@ instance = comp, \ula_|i2s_intf_|shiftreg~3 , ula_|i2s_intf_|shiftreg~3, spectru instance = comp, \ula_|i2s_intf_|shiftreg[16] , ula_|i2s_intf_|shiftreg[16], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~0 , ula_|i2s_intf_|shiftreg~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[17] , ula_|i2s_intf_|shiftreg[17], spectrum, 1 -instance = comp, \ula_|border[1]~feeder , ula_|border[1]~feeder, spectrum, 1 +instance = comp, \ula_|video_|LessThan2~0 , ula_|video_|LessThan2~0, spectrum, 1 +instance = comp, \ula_|video_|LessThan6~0 , ula_|video_|LessThan6~0, spectrum, 1 +instance = comp, \ula_|video_|LessThan2~1 , ula_|video_|LessThan2~1, spectrum, 1 +instance = comp, \ula_|video_|LessThan3~0 , ula_|video_|LessThan3~0, spectrum, 1 +instance = comp, \ula_|video_|LessThan0~0 , ula_|video_|LessThan0~0, spectrum, 1 +instance = comp, \ula_|video_|disp_enable~0 , ula_|video_|disp_enable~0, spectrum, 1 +instance = comp, \ula_|video_|disp_enable~1 , ula_|video_|disp_enable~1, spectrum, 1 instance = comp, \ula_|border[1] , ula_|border[1], spectrum, 1 +instance = comp, \ula_|video_|LessThan6~1 , ula_|video_|LessThan6~1, spectrum, 1 +instance = comp, \ula_|video_|LessThan4~0 , ula_|video_|LessThan4~0, spectrum, 1 +instance = comp, \ula_|video_|screen_en~0 , ula_|video_|screen_en~0, spectrum, 1 +instance = comp, \ula_|video_|screen_en~1 , ula_|video_|screen_en~1, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[1]~feeder , ula_|video_|attr_prefetch[1]~feeder, spectrum, 1 instance = comp, \ula_|video_|Decoder0~1 , ula_|video_|Decoder0~1, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[1] , ula_|video_|attr_prefetch[1], spectrum, 1 -instance = comp, \ula_|video_|attr[1]~feeder , ula_|video_|attr[1]~feeder, spectrum, 1 instance = comp, \ula_|video_|Decoder0~0 , ula_|video_|Decoder0~0, spectrum, 1 instance = comp, \ula_|video_|attr[1] , ula_|video_|attr[1], spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[4]~feeder , ula_|video_|attr_prefetch[4]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[4] , ula_|video_|attr_prefetch[4], spectrum, 1 instance = comp, \ula_|video_|attr[4] , ula_|video_|attr[4], spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[6]~feeder , ula_|video_|bits_prefetch[6]~feeder, spectrum, 1 -instance = comp, \ula_|video_|Decoder0~2 , ula_|video_|Decoder0~2, spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[6] , ula_|video_|bits_prefetch[6], spectrum, 1 -instance = comp, \ula_|video_|bits[6] , ula_|video_|bits[6], spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[4]~feeder , ula_|video_|bits_prefetch[4]~feeder, spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[4] , ula_|video_|bits_prefetch[4], spectrum, 1 -instance = comp, \ula_|video_|bits[4] , ula_|video_|bits[4], spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[5]~feeder , ula_|video_|bits_prefetch[5]~feeder, spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[5] , ula_|video_|bits_prefetch[5], spectrum, 1 -instance = comp, \ula_|video_|bits[5] , ula_|video_|bits[5], spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[7]~feeder , ula_|video_|bits_prefetch[7]~feeder, spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[7] , ula_|video_|bits_prefetch[7], spectrum, 1 -instance = comp, \ula_|video_|bits[7] , ula_|video_|bits[7], spectrum, 1 -instance = comp, \ula_|video_|Mux0~0 , ula_|video_|Mux0~0, spectrum, 1 -instance = comp, \ula_|video_|Mux0~1 , ula_|video_|Mux0~1, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[7]~feeder , ula_|video_|attr_prefetch[7]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[7] , ula_|video_|attr_prefetch[7], spectrum, 1 instance = comp, \ula_|video_|attr[7] , ula_|video_|attr[7], spectrum, 1 @@ -3098,8 +3115,26 @@ instance = comp, \ula_|video_|frame[3] , ula_|video_|frame[3], spectrum, 1 instance = comp, \ula_|video_|frame[4]~10 , ula_|video_|frame[4]~10, spectrum, 1 instance = comp, \ula_|video_|frame[4] , ula_|video_|frame[4], spectrum, 1 instance = comp, \ula_|video_|inverted , ula_|video_|inverted, spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[6]~feeder , ula_|video_|bits_prefetch[6]~feeder, spectrum, 1 +instance = comp, \ula_|video_|Decoder0~2 , ula_|video_|Decoder0~2, spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[6] , ula_|video_|bits_prefetch[6], spectrum, 1 +instance = comp, \ula_|video_|bits[6]~feeder , ula_|video_|bits[6]~feeder, spectrum, 1 +instance = comp, \ula_|video_|bits[6] , ula_|video_|bits[6], spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[4]~feeder , ula_|video_|bits_prefetch[4]~feeder, spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[4] , ula_|video_|bits_prefetch[4], spectrum, 1 +instance = comp, \ula_|video_|bits[4] , ula_|video_|bits[4], spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[5]~feeder , ula_|video_|bits_prefetch[5]~feeder, spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[5] , ula_|video_|bits_prefetch[5], spectrum, 1 +instance = comp, \ula_|video_|bits[5]~feeder , ula_|video_|bits[5]~feeder, spectrum, 1 +instance = comp, \ula_|video_|bits[5] , ula_|video_|bits[5], spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[7]~feeder , ula_|video_|bits_prefetch[7]~feeder, spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[7] , ula_|video_|bits_prefetch[7], spectrum, 1 +instance = comp, \ula_|video_|bits[7] , ula_|video_|bits[7], spectrum, 1 +instance = comp, \ula_|video_|Mux0~0 , ula_|video_|Mux0~0, spectrum, 1 +instance = comp, \ula_|video_|Mux0~1 , ula_|video_|Mux0~1, spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[2]~feeder , ula_|video_|bits_prefetch[2]~feeder, spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[2] , ula_|video_|bits_prefetch[2], spectrum, 1 +instance = comp, \ula_|video_|bits[2]~feeder , ula_|video_|bits[2]~feeder, spectrum, 1 instance = comp, \ula_|video_|bits[2] , ula_|video_|bits[2], spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[0]~feeder , ula_|video_|bits_prefetch[0]~feeder, spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[0] , ula_|video_|bits_prefetch[0], spectrum, 1 @@ -3115,17 +3150,6 @@ instance = comp, \ula_|video_|Mux0~2 , ula_|video_|Mux0~2, spectrum, 1 instance = comp, \ula_|video_|Mux0~3 , ula_|video_|Mux0~3, spectrum, 1 instance = comp, \ula_|video_|cindex[1]~0 , ula_|video_|cindex[1]~0, spectrum, 1 instance = comp, \ula_|video_|cindex[1]~1 , ula_|video_|cindex[1]~1, spectrum, 1 -instance = comp, \ula_|video_|LessThan6~0 , ula_|video_|LessThan6~0, spectrum, 1 -instance = comp, \ula_|video_|LessThan6~1 , ula_|video_|LessThan6~1, spectrum, 1 -instance = comp, \ula_|video_|LessThan4~0 , ula_|video_|LessThan4~0, spectrum, 1 -instance = comp, \ula_|video_|screen_en~0 , ula_|video_|screen_en~0, spectrum, 1 -instance = comp, \ula_|video_|screen_en~1 , ula_|video_|screen_en~1, spectrum, 1 -instance = comp, \ula_|video_|LessThan2~0 , ula_|video_|LessThan2~0, spectrum, 1 -instance = comp, \ula_|video_|LessThan2~1 , ula_|video_|LessThan2~1, spectrum, 1 -instance = comp, \ula_|video_|LessThan3~0 , ula_|video_|LessThan3~0, spectrum, 1 -instance = comp, \ula_|video_|LessThan0~0 , ula_|video_|LessThan0~0, spectrum, 1 -instance = comp, \ula_|video_|disp_enable~0 , ula_|video_|disp_enable~0, spectrum, 1 -instance = comp, \ula_|video_|disp_enable~1 , ula_|video_|disp_enable~1, spectrum, 1 instance = comp, \ula_|video_|VGA_R[0]~0 , ula_|video_|VGA_R[0]~0, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[6]~feeder , ula_|video_|attr_prefetch[6]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[6] , ula_|video_|attr_prefetch[6], spectrum, 1 @@ -3142,11 +3166,12 @@ instance = comp, \ula_|video_|attr[5] , ula_|video_|attr[5], spectrum, 1 instance = comp, \ula_|video_|cindex[2]~2 , ula_|video_|cindex[2]~2, spectrum, 1 instance = comp, \ula_|video_|VGA_G[0]~0 , ula_|video_|VGA_G[0]~0, spectrum, 1 instance = comp, \ula_|video_|VGA_G[1]~1 , ula_|video_|VGA_G[1]~1, spectrum, 1 -instance = comp, \ula_|border[0]~feeder , ula_|border[0]~feeder, spectrum, 1 instance = comp, \ula_|border[0] , ula_|border[0], spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[0]~feeder , ula_|video_|attr_prefetch[0]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[0] , ula_|video_|attr_prefetch[0], spectrum, 1 +instance = comp, \ula_|video_|attr[0]~feeder , ula_|video_|attr[0]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr[0] , ula_|video_|attr[0], spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[3]~feeder , ula_|video_|attr_prefetch[3]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[3] , ula_|video_|attr_prefetch[3], spectrum, 1 instance = comp, \ula_|video_|attr[3] , ula_|video_|attr[3], spectrum, 1 instance = comp, \ula_|video_|cindex[0]~3 , ula_|video_|cindex[0]~3, spectrum, 1 diff --git a/simulation/modelsim/spectrum_v.sdo b/simulation/modelsim/spectrum_v.sdo index 0d7cf17..8f29861 100644 --- a/simulation/modelsim/spectrum_v.sdo +++ b/simulation/modelsim/spectrum_v.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/31/2022 14:04:25") + (DATE "04/01/2022 18:55:53") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1853:1853:1853) (1919:1919:1919)) - (PORT oe (644:644:644) (703:703:703)) + (PORT i (2109:2109:2109) (2123:2123:2123)) + (PORT oe (1638:1638:1638) (1708:1708:1708)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1537:1537:1537) (1634:1634:1634)) - (PORT oe (2188:2188:2188) (2280:2280:2280)) + (PORT i (2133:2133:2133) (2174:2174:2174)) + (PORT oe (1897:1897:1897) (1931:1931:1931)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1289:1289:1289) (1340:1340:1340)) - (PORT oe (2188:2188:2188) (2280:2280:2280)) + (PORT i (1984:1984:1984) (2083:2083:2083)) + (PORT oe (1897:1897:1897) (1931:1931:1931)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1619:1619:1619) (1697:1697:1697)) - (PORT oe (2381:2381:2381) (2531:2531:2531)) + (PORT i (2218:2218:2218) (2284:2284:2284)) + (PORT oe (2147:2147:2147) (2236:2236:2236)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1337:1337:1337) (1380:1380:1380)) - (PORT oe (2381:2381:2381) (2531:2531:2531)) + (PORT i (2271:2271:2271) (2432:2432:2432)) + (PORT oe (2147:2147:2147) (2236:2236:2236)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1140:1140:1140) (1226:1226:1226)) - (PORT oe (2357:2357:2357) (2509:2509:2509)) + (PORT i (1973:1973:1973) (2011:2011:2011)) + (PORT oe (1910:1910:1910) (2005:2005:2005)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1346:1346:1346) (1430:1430:1430)) - (PORT oe (2357:2357:2357) (2509:2509:2509)) + (PORT i (1640:1640:1640) (1716:1716:1716)) + (PORT oe (1910:1910:1910) (2005:2005:2005)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (912:912:912) (998:998:998)) - (PORT oe (2357:2357:2357) (2509:2509:2509)) + (PORT i (1960:1960:1960) (2148:2148:2148)) + (PORT oe (1910:1910:1910) (2005:2005:2005)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (967:967:967) (1038:1038:1038)) - (PORT oe (2358:2358:2358) (2514:2514:2514)) + (PORT i (976:976:976) (1064:1064:1064)) + (PORT oe (2161:2161:2161) (2266:2266:2266)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1086:1086:1086) (1162:1162:1162)) - (PORT oe (2358:2358:2358) (2514:2514:2514)) + (PORT i (1717:1717:1717) (1803:1803:1803)) + (PORT oe (2161:2161:2161) (2266:2266:2266)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1125:1125:1125) (1197:1197:1197)) - (PORT oe (2572:2572:2572) (2731:2731:2731)) + (PORT i (1939:1939:1939) (1996:1996:1996)) + (PORT oe (2404:2404:2404) (2537:2537:2537)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) (IOPATH oe o (4578:4578:4578) (4159:4159:4159)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1099:1099:1099) (1171:1171:1171)) - (PORT oe (2358:2358:2358) (2514:2514:2514)) + (PORT i (1417:1417:1417) (1462:1462:1462)) + (PORT oe (2161:2161:2161) (2266:2266:2266)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (1576:1576:1576) (1626:1626:1626)) - (PORT oe (2182:2182:2182) (2276:2276:2276)) + (PORT i (2181:2181:2181) (2209:2209:2209)) + (PORT oe (1700:1700:1700) (1736:1736:1736)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (1096:1096:1096) (1169:1169:1169)) - (PORT oe (2572:2572:2572) (2731:2731:2731)) + (PORT i (2231:2231:2231) (2361:2361:2361)) + (PORT oe (2404:2404:2404) (2537:2537:2537)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1418:1418:1418) (1503:1503:1503)) - (PORT oe (2361:2361:2361) (2521:2521:2521)) + (PORT i (1625:1625:1625) (1715:1715:1715)) + (PORT oe (2140:2140:2140) (2250:2250:2250)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1101:1101:1101) (1148:1148:1148)) - (PORT oe (2383:2383:2383) (2521:2521:2521)) + (PORT i (1724:1724:1724) (1854:1854:1854)) + (PORT oe (1916:1916:1916) (1948:1948:1948)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (1099:1099:1099) (1117:1117:1117)) - (PORT oe (2807:2807:2807) (2896:2896:2896)) + (PORT i (1202:1202:1202) (1265:1265:1265)) + (PORT oe (2441:2441:2441) (2523:2523:2523)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (1133:1133:1133) (1158:1158:1158)) - (PORT oe (2742:2742:2742) (2835:2835:2835)) + (PORT i (1216:1216:1216) (1287:1287:1287)) + (PORT oe (2442:2442:2442) (2524:2524:2524)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (1198:1198:1198) (1245:1245:1245)) - (PORT oe (2463:2463:2463) (2537:2537:2537)) + (PORT i (1118:1118:1118) (1163:1163:1163)) + (PORT oe (2137:2137:2137) (2196:2196:2196)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (1153:1153:1153) (1202:1202:1202)) - (PORT oe (2807:2807:2807) (2896:2896:2896)) + (PORT i (1161:1161:1161) (1237:1237:1237)) + (PORT oe (2441:2441:2441) (2523:2523:2523)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (1463:1463:1463) (1514:1514:1514)) - (PORT oe (2461:2461:2461) (2522:2522:2522)) + (PORT i (1455:1455:1455) (1530:1530:1530)) + (PORT oe (2096:2096:2096) (2158:2158:2158)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (953:953:953) (993:993:993)) - (PORT oe (2462:2462:2462) (2536:2536:2536)) + (PORT i (1343:1343:1343) (1352:1352:1352)) + (PORT oe (2136:2136:2136) (2195:2195:2195)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (1327:1327:1327) (1390:1390:1390)) - (PORT oe (2391:2391:2391) (2467:2467:2467)) + (PORT i (1213:1213:1213) (1275:1275:1275)) + (PORT oe (2035:2035:2035) (2069:2069:2069)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (875:875:875) (909:909:909)) - (PORT oe (2767:2767:2767) (2861:2861:2861)) + (PORT i (1131:1131:1131) (1146:1146:1146)) + (PORT oe (2405:2405:2405) (2466:2466:2466)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (1301:1301:1301) (1303:1303:1303)) - (PORT oe (1210:1210:1210) (1309:1309:1309)) + (PORT i (1412:1412:1412) (1417:1417:1417)) + (PORT oe (1643:1643:1643) (1693:1693:1693)) (IOPATH i o (2378:2378:2378) (2455:2455:2455)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1480:1480:1480) (1473:1473:1473)) - (PORT oe (2383:2383:2383) (2521:2521:2521)) + (PORT i (1794:1794:1794) (1688:1688:1688)) + (PORT oe (1916:1916:1916) (1948:1948:1948)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -353,8 +353,8 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (628:628:628) (613:613:613)) - (PORT oe (919:919:919) (1023:1023:1023)) + (PORT i (1533:1533:1533) (1531:1531:1531)) + (PORT oe (1352:1352:1352) (1405:1405:1405)) (IOPATH i o (2502:2502:2502) (2582:2582:2582)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (772:772:772) (757:757:757)) - (PORT oe (676:676:676) (754:754:754)) + (PORT i (1050:1050:1050) (1062:1062:1062)) + (PORT oe (1327:1327:1327) (1369:1369:1369)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -377,7 +377,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1607:1607:1607) (1503:1503:1503)) + (PORT i (1615:1615:1615) (1516:1516:1516)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -392,6 +392,16 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1304:1304:1304) (1340:1340:1340)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_obuf") (INSTANCE AUD_XCK\~output) @@ -442,7 +452,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1198:1198:1198) (1239:1239:1239)) + (PORT i (1164:1164:1164) (1204:1204:1204)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -452,7 +462,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1239:1239:1239) (1278:1278:1278)) + (PORT i (1073:1073:1073) (1104:1104:1104)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -462,7 +472,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (530:530:530) (528:528:528)) + (PORT i (774:774:774) (751:751:751)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -472,7 +482,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1168:1168:1168) (1217:1217:1217)) + (PORT i (986:986:986) (968:968:968)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -482,7 +492,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (855:855:855) (854:854:854)) + (PORT i (972:972:972) (958:958:958)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -492,7 +502,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (822:822:822) (804:804:804)) + (PORT i (721:721:721) (699:699:699)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -502,7 +512,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1071:1071:1071) (1094:1094:1094)) + (PORT i (843:843:843) (812:812:812)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -512,7 +522,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1071:1071:1071) (1094:1094:1094)) + (PORT i (843:843:843) (812:812:812)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -522,7 +532,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (743:743:743) (735:735:735)) + (PORT i (717:717:717) (702:702:702)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) ) ) @@ -532,7 +542,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (509:509:509) (504:504:504)) + (PORT i (692:692:692) (667:667:667)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -542,7 +552,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1044:1044:1044) (1021:1021:1021)) + (PORT i (952:952:952) (940:940:940)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -552,7 +562,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1424:1424:1424) (1395:1395:1395)) + (PORT i (1378:1378:1378) (1350:1350:1350)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -580,7 +590,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (1273:1273:1273) (1178:1178:1178)) + (PORT i (2048:2048:2048) (1957:1957:1957)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -590,7 +600,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (630:630:630) (599:599:599)) + (PORT i (1307:1307:1307) (1281:1281:1281)) (IOPATH i o (4127:4127:4127) (4477:4477:4477)) ) ) @@ -600,7 +610,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (310:310:310) (317:317:317)) + (PORT i (927:927:927) (923:923:923)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -610,7 +620,7 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (1794:1794:1794) (1912:1912:1912)) + (PORT i (1348:1348:1348) (1373:1373:1373)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -724,7 +734,20 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (752:752:752) (781:781:781)) + (PORT inclk[0] (716:716:716) (747:747:747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1158:1158:1158)) + (PORT datad (1110:1110:1110) (1159:1159:1159)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -733,13 +756,10589 @@ (INSTANCE z80_\|sequencer_\|ena_M) (DELAY (ABSOLUTE - (PORT datac (900:900:900) (935:935:935)) - (PORT datad (855:855:855) (910:910:910)) + (PORT datac (1094:1094:1094) (1132:1132:1132)) + (PORT datad (1106:1106:1106) (1160:1160:1160)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE KEY\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (481:481:481) (733:733:733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (490:490:490)) + (PORT datad (1994:1994:1994) (2109:2109:2109)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|nmi_armed) + (DELAY + (ABSOLUTE + (PORT clk (1476:1476:1476) (1490:1490:1490)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1325:1325:1325) (1320:1320:1320)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (790:790:790) (826:826:826)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT datac (243:243:243) (323:323:323)) + (PORT datad (252:252:252) (325:325:325)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2418:2418:2418) (2567:2567:2567)) + (PORT datab (2411:2411:2411) (2541:2541:2541)) + (PORT datad (1577:1577:1577) (1737:1737:1737)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1160:1160:1160)) + (PORT datab (408:408:408) (481:481:481)) + (PORT datad (1111:1111:1111) (1161:1161:1161)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1355:1355:1355) (1381:1381:1381)) + (PORT datab (1537:1537:1537) (1647:1647:1647)) + (PORT datac (1348:1348:1348) (1441:1441:1441)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1178:1178:1178)) + (PORT datab (413:413:413) (488:488:488)) + (PORT datad (1104:1104:1104) (1156:1156:1156)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (DELAY + (ABSOLUTE + (PORT datab (393:393:393) (466:466:466)) + (PORT datad (667:667:667) (742:742:742)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) + (DELAY + (ABSOLUTE + (PORT datab (2598:2598:2598) (2742:2742:2742)) + (PORT datad (1607:1607:1607) (1729:1729:1729)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1365:1365:1365) (1484:1484:1484)) + (PORT datad (1197:1197:1197) (1317:1317:1317)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1675:1675:1675) (1712:1712:1712)) + (PORT datab (945:945:945) (983:983:983)) + (PORT datac (2134:2134:2134) (2287:2287:2287)) + (PORT datad (1162:1162:1162) (1232:1232:1232)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT datac (1459:1459:1459) (1537:1537:1537)) + (PORT datad (2262:2262:2262) (2332:2332:2332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1246:1246:1246) (1343:1343:1343)) + (PORT datab (1671:1671:1671) (1786:1786:1786)) + (PORT datac (906:906:906) (959:959:959)) + (PORT datad (943:943:943) (998:998:998)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (1739:1739:1739) (1786:1786:1786)) + (PORT datab (1426:1426:1426) (1455:1455:1455)) + (PORT datac (846:846:846) (882:882:882)) + (PORT datad (789:789:789) (792:792:792)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1224:1224:1224) (1329:1329:1329)) + (PORT datab (2644:2644:2644) (2764:2764:2764)) + (PORT datac (844:844:844) (879:879:879)) + (PORT datad (972:972:972) (1035:1035:1035)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1588:1588:1588) (1563:1563:1563)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (808:808:808)) + (PORT datab (1233:1233:1233) (1347:1347:1347)) + (PORT datac (988:988:988) (1067:1067:1067)) + (PORT datad (1323:1323:1323) (1441:1441:1441)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2337:2337:2337) (2490:2490:2490)) + (PORT datab (1667:1667:1667) (1786:1786:1786)) + (PORT datac (905:905:905) (957:957:957)) + (PORT datad (672:672:672) (720:720:720)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (DELAY + (ABSOLUTE + (PORT dataa (1761:1761:1761) (1838:1838:1838)) + (PORT datab (839:839:839) (854:854:854)) + (PORT datac (1396:1396:1396) (1420:1420:1420)) + (PORT datad (2042:2042:2042) (2106:2106:2106)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instED) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1588:1588:1588) (1563:1563:1563)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (810:810:810)) + (PORT datac (981:981:981) (1058:1058:1058)) + (PORT datad (1323:1323:1323) (1434:1434:1434)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2169:2169:2169) (2327:2327:2327)) + (PORT datac (1460:1460:1460) (1537:1537:1537)) + (PORT datad (2263:2263:2263) (2329:2329:2329)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (636:636:636)) + (PORT datab (1050:1050:1050) (1169:1169:1169)) + (PORT datac (1337:1337:1337) (1469:1469:1469)) + (PORT datad (915:915:915) (959:959:959)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT datab (997:997:997) (1105:1105:1105)) + (PORT datac (656:656:656) (719:719:719)) + (PORT datad (1244:1244:1244) (1328:1328:1328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1410:1410:1410) (1499:1499:1499)) + (PORT datab (1489:1489:1489) (1614:1614:1614)) + (PORT datac (1433:1433:1433) (1524:1524:1524)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (809:809:809)) + (PORT datab (1233:1233:1233) (1347:1347:1347)) + (PORT datac (989:989:989) (1067:1067:1067)) + (PORT datad (1323:1323:1323) (1441:1441:1441)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1301:1301:1301)) + (PORT datab (1273:1273:1273) (1368:1368:1368)) + (PORT datad (711:711:711) (773:773:773)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2639:2639:2639) (2814:2814:2814)) + (PORT datab (899:899:899) (934:934:934)) + (PORT datac (1110:1110:1110) (1167:1167:1167)) + (PORT datad (1150:1150:1150) (1194:1194:1194)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (1033:1033:1033)) + (PORT datab (1561:1561:1561) (1662:1662:1662)) + (PORT datac (1411:1411:1411) (1476:1476:1476)) + (PORT datad (201:201:201) (238:238:238)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1239:1239:1239)) + (PORT datad (2109:2109:2109) (2254:2254:2254)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1149:1149:1149)) + (PORT datab (1113:1113:1113) (1123:1123:1123)) + (PORT datac (333:333:333) (359:359:359)) + (PORT datad (689:689:689) (743:743:743)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datac (1439:1439:1439) (1545:1545:1545)) + (PORT datad (1464:1464:1464) (1551:1551:1551)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1247:1247:1247) (1335:1335:1335)) + (PORT datab (1669:1669:1669) (1782:1782:1782)) + (PORT datac (1700:1700:1700) (1785:1785:1785)) + (PORT datad (944:944:944) (1001:1001:1001)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT datac (1974:1974:1974) (2154:2154:2154)) + (PORT datad (1235:1235:1235) (1306:1306:1306)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1939:1939:1939) (2060:2060:2060)) + (PORT datac (2560:2560:2560) (2661:2661:2661)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (937:937:937)) + (PORT datab (1029:1029:1029) (1093:1093:1093)) + (PORT datac (849:849:849) (913:913:913)) + (PORT datad (929:929:929) (973:973:973)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~1) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (941:941:941)) + (PORT datab (898:898:898) (917:917:917)) + (PORT datac (919:919:919) (1011:1011:1011)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (940:940:940)) + (PORT datab (901:901:901) (913:913:913)) + (PORT datac (920:920:920) (1009:1009:1009)) + (PORT datad (1166:1166:1166) (1216:1216:1216)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (896:896:896)) + (PORT datac (977:977:977) (1048:1048:1048)) + (PORT datad (1170:1170:1170) (1184:1184:1184)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2169:2169:2169) (2322:2322:2322)) + (PORT datac (1461:1461:1461) (1534:1534:1534)) + (PORT datad (2261:2261:2261) (2326:2326:2326)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (972:972:972)) + (PORT datab (1721:1721:1721) (1812:1812:1812)) + (PORT datac (1148:1148:1148) (1153:1153:1153)) + (PORT datad (650:650:650) (690:690:690)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (975:975:975)) + (PORT datab (2317:2317:2317) (2471:2471:2471)) + (PORT datac (1702:1702:1702) (1788:1788:1788)) + (PORT datad (669:669:669) (716:716:716)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1211:1211:1211) (1331:1331:1331)) + (PORT datab (2075:2075:2075) (2256:2256:2256)) + (PORT datac (862:862:862) (881:881:881)) + (PORT datad (1458:1458:1458) (1561:1561:1561)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT datab (1418:1418:1418) (1489:1489:1489)) + (PORT datac (1562:1562:1562) (1631:1631:1631)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~6) + (DELAY + (ABSOLUTE + (PORT datac (1595:1595:1595) (1686:1686:1686)) + (PORT datad (1897:1897:1897) (2018:2018:2018)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~9) + (DELAY + (ABSOLUTE + (PORT datac (1033:1033:1033) (1103:1103:1103)) + (PORT datad (985:985:985) (1046:1046:1046)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1060:1060:1060)) + (PORT datab (989:989:989) (1052:1052:1052)) + (PORT datac (903:903:903) (941:941:941)) + (PORT datad (2055:2055:2055) (2108:2108:2108)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (461:461:461)) + (PORT datab (1160:1160:1160) (1195:1195:1195)) + (PORT datac (623:623:623) (685:685:685)) + (PORT datad (1108:1108:1108) (1138:1138:1138)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal44\~0) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (810:810:810)) + (PORT datab (1238:1238:1238) (1352:1352:1352)) + (PORT datac (982:982:982) (1059:1059:1059)) + (PORT datad (1323:1323:1323) (1435:1435:1435)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~16) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1074:1074:1074)) + (PORT datab (1336:1336:1336) (1358:1358:1358)) + (PORT datac (931:931:931) (1016:1016:1016)) + (PORT datad (1108:1108:1108) (1132:1132:1132)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT datab (836:836:836) (897:897:897)) + (PORT datac (619:619:619) (671:671:671)) + (PORT datad (213:213:213) (245:245:245)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal50\~0) + (DELAY + (ABSOLUTE + (PORT datab (998:998:998) (1107:1107:1107)) + (PORT datac (656:656:656) (717:717:717)) + (PORT datad (1193:1193:1193) (1255:1255:1255)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1300:1300:1300)) + (PORT datab (1273:1273:1273) (1368:1368:1368)) + (PORT datad (711:711:711) (773:773:773)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~17) + (DELAY + (ABSOLUTE + (PORT dataa (967:967:967) (1063:1063:1063)) + (PORT datab (1112:1112:1112) (1107:1107:1107)) + (PORT datac (928:928:928) (1011:1011:1011)) + (PORT datad (1085:1085:1085) (1082:1082:1082)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datac (1607:1607:1607) (1722:1722:1722)) + (PORT datad (984:984:984) (1047:1047:1047)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (674:674:674)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (199:199:199) (237:237:237)) + (PORT datad (1103:1103:1103) (1112:1112:1112)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1593:1593:1593) (1671:1671:1671)) + (PORT datab (1420:1420:1420) (1492:1492:1492)) + (PORT datac (372:372:372) (399:399:399)) + (PORT datad (1786:1786:1786) (1904:1904:1904)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1089:1089:1089) (1107:1107:1107)) + (PORT datab (236:236:236) (282:282:282)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1399:1399:1399)) + (PORT datab (1499:1499:1499) (1604:1604:1604)) + (PORT datac (1460:1460:1460) (1551:1551:1551)) + (PORT datad (2054:2054:2054) (2222:2222:2222)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1586:1586:1586) (1563:1563:1563)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (960:960:960)) + (PORT datac (643:643:643) (708:708:708)) + (PORT datad (1365:1365:1365) (1481:1481:1481)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1368:1368:1368)) + (PORT datab (463:463:463) (524:524:524)) + (PORT datac (1699:1699:1699) (1754:1754:1754)) + (PORT datad (267:267:267) (321:321:321)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (805:805:805)) + (PORT datab (1019:1019:1019) (1101:1101:1101)) + (PORT datac (676:676:676) (769:769:769)) + (PORT datad (1322:1322:1322) (1435:1435:1435)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1717:1717:1717)) + (PORT datab (1533:1533:1533) (1585:1585:1585)) + (PORT datac (1709:1709:1709) (1830:1830:1830)) + (PORT datad (1494:1494:1494) (1626:1626:1626)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1299:1299:1299) (1388:1388:1388)) + (PORT datab (1243:1243:1243) (1323:1323:1323)) + (PORT datac (1034:1034:1034) (1082:1082:1082)) + (PORT datad (1678:1678:1678) (1738:1738:1738)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT datac (685:685:685) (734:734:734)) + (PORT datad (1734:1734:1734) (1851:1851:1851)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (666:666:666)) + (PORT datac (1102:1102:1102) (1151:1151:1151)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (252:252:252)) + (PORT datab (244:244:244) (291:291:291)) + (PORT datac (669:669:669) (688:688:688)) + (PORT datad (2054:2054:2054) (2107:2107:2107)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1065:1065:1065)) + (PORT datab (1219:1219:1219) (1281:1281:1281)) + (PORT datac (688:688:688) (740:740:740)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1031:1031:1031)) + (PORT datab (1557:1557:1557) (1661:1661:1661)) + (PORT datac (1407:1407:1407) (1474:1474:1474)) + (PORT datad (203:203:203) (238:238:238)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (386:386:386)) + (PORT datac (902:902:902) (964:964:964)) + (PORT datad (928:928:928) (984:984:984)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1762:1762:1762) (1872:1872:1872)) + (PORT datac (1146:1146:1146) (1226:1226:1226)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (664:664:664)) + (PORT datab (1178:1178:1178) (1215:1215:1215)) + (PORT datac (934:934:934) (1030:1030:1030)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (723:723:723)) + (PORT datab (653:653:653) (674:674:674)) + (PORT datac (936:936:936) (1036:1036:1036)) + (PORT datad (898:898:898) (943:943:943)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (958:958:958)) + (PORT datab (1199:1199:1199) (1222:1222:1222)) + (PORT datac (1813:1813:1813) (1890:1890:1890)) + (PORT datad (871:871:871) (910:910:910)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1687:1687:1687) (1746:1746:1746)) + (PORT datac (1659:1659:1659) (1737:1737:1737)) + (PORT datad (1165:1165:1165) (1209:1209:1209)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datac (826:826:826) (880:880:880)) + (PORT datad (900:900:900) (971:971:971)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1685:1685:1685) (1750:1750:1750)) + (PORT datab (1691:1691:1691) (1776:1776:1776)) + (PORT datac (1479:1479:1479) (1575:1575:1575)) + (PORT datad (1244:1244:1244) (1311:1311:1311)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1537:1537:1537)) + (PORT datab (1233:1233:1233) (1318:1318:1318)) + (PORT datac (1424:1424:1424) (1514:1514:1514)) + (PORT datad (825:825:825) (838:838:838)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (914:914:914)) + (PORT datab (1241:1241:1241) (1279:1279:1279)) + (PORT datac (1377:1377:1377) (1384:1384:1384)) + (PORT datad (1263:1263:1263) (1301:1301:1301)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (657:657:657)) + (PORT datab (963:963:963) (1059:1059:1059)) + (PORT datad (1154:1154:1154) (1176:1176:1176)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1565:1565:1565) (1659:1659:1659)) + (PORT datab (982:982:982) (1039:1039:1039)) + (PORT datac (1634:1634:1634) (1749:1749:1749)) + (PORT datad (1216:1216:1216) (1293:1293:1293)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1460:1460:1460) (1559:1559:1559)) + (PORT datab (1540:1540:1540) (1676:1676:1676)) + (PORT datac (1379:1379:1379) (1439:1439:1439)) + (PORT datad (1566:1566:1566) (1596:1596:1596)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (913:913:913)) + (PORT datab (1819:1819:1819) (1900:1900:1900)) + (PORT datac (867:867:867) (883:883:883)) + (PORT datad (1475:1475:1475) (1552:1552:1552)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1220:1220:1220) (1307:1307:1307)) + (PORT datac (948:948:948) (1024:1024:1024)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (969:969:969)) + (PORT datab (936:936:936) (992:992:992)) + (PORT datac (1633:1633:1633) (1753:1753:1753)) + (PORT datad (1215:1215:1215) (1294:1294:1294)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT datac (1720:1720:1720) (1792:1792:1792)) + (PORT datad (2039:2039:2039) (2100:2100:2100)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (1158:1158:1158) (1201:1201:1201)) + (PORT datac (1618:1618:1618) (1607:1607:1607)) + (PORT datad (1454:1454:1454) (1538:1538:1538)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1564:1564:1564) (1657:1657:1657)) + (PORT datab (978:978:978) (1038:1038:1038)) + (PORT datac (1634:1634:1634) (1759:1759:1759)) + (PORT datad (1220:1220:1220) (1302:1302:1302)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2169:2169:2169) (2326:2326:2326)) + (PORT datab (948:948:948) (988:988:988)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (416:416:416) (461:461:461)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (500:500:500)) + (PORT datab (942:942:942) (982:982:982)) + (PORT datac (2138:2138:2138) (2282:2282:2282)) + (PORT datad (1141:1141:1141) (1176:1176:1176)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (504:504:504)) + (PORT datab (946:946:946) (982:982:982)) + (PORT datac (2134:2134:2134) (2284:2284:2284)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal38\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1627:1627:1627) (1717:1717:1717)) + (PORT datab (1533:1533:1533) (1663:1663:1663)) + (PORT datac (1709:1709:1709) (1827:1827:1827)) + (PORT datad (1445:1445:1445) (1492:1492:1492)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1114:1114:1114) (1137:1137:1137)) + (PORT datab (1107:1107:1107) (1172:1172:1172)) + (PORT datac (580:580:580) (611:611:611)) + (PORT datad (895:895:895) (945:945:945)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (927:927:927)) + (PORT datab (1362:1362:1362) (1426:1426:1426)) + (PORT datac (584:584:584) (617:617:617)) + (PORT datad (583:583:583) (602:602:602)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datab (1940:1940:1940) (2011:2011:2011)) + (PORT datac (1163:1163:1163) (1222:1222:1222)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (507:507:507)) + (PORT datab (949:949:949) (988:988:988)) + (PORT datac (2135:2135:2135) (2282:2282:2282)) + (PORT datad (364:364:364) (385:385:385)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1360:1360:1360)) + (PORT datab (1193:1193:1193) (1242:1242:1242)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (1264:1264:1264) (1365:1365:1365)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (717:717:717)) + (PORT datab (639:639:639) (661:661:661)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (1158:1158:1158) (1203:1203:1203)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (959:959:959)) + (PORT datab (231:231:231) (282:282:282)) + (PORT datac (629:629:629) (651:651:651)) + (PORT datad (649:649:649) (681:681:681)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (1447:1447:1447) (1493:1493:1493)) + (PORT datab (1229:1229:1229) (1315:1315:1315)) + (PORT datac (680:680:680) (717:717:717)) + (PORT datad (1141:1141:1141) (1161:1161:1161)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (708:708:708) (759:759:759)) + (PORT datab (1141:1141:1141) (1169:1169:1169)) + (PORT datac (1819:1819:1819) (1896:1896:1896)) + (PORT datad (588:588:588) (613:613:613)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1461:1461:1461) (1560:1560:1560)) + (PORT datab (1137:1137:1137) (1179:1179:1179)) + (PORT datac (1192:1192:1192) (1287:1287:1287)) + (PORT datad (655:655:655) (686:686:686)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1468:1468:1468) (1566:1566:1566)) + (PORT datab (683:683:683) (725:725:725)) + (PORT datac (1193:1193:1193) (1278:1278:1278)) + (PORT datad (1406:1406:1406) (1445:1445:1445)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|M5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1173:1173:1173)) + (PORT datab (267:267:267) (350:350:350)) + (PORT datad (1104:1104:1104) (1160:1160:1160)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|M5) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) + (DELAY + (ABSOLUTE + (PORT datab (1589:1589:1589) (1719:1719:1719)) + (PORT datac (2606:2606:2606) (2704:2704:2704)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~29) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (665:665:665)) + (PORT datab (931:931:931) (978:978:978)) + (PORT datac (1004:1004:1004) (1061:1061:1061)) + (PORT datad (662:662:662) (691:691:691)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1946:1946:1946) (2050:2050:2050)) + (PORT datab (687:687:687) (729:729:729)) + (PORT datac (658:658:658) (709:709:709)) + (PORT datad (585:585:585) (615:615:615)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1904:1904:1904) (1999:1999:1999)) + (PORT datab (898:898:898) (961:961:961)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (187:187:187) (219:219:219)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1371:1371:1371)) + (PORT datab (464:464:464) (522:522:522)) + (PORT datac (1696:1696:1696) (1755:1755:1755)) + (PORT datad (268:268:268) (323:323:323)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1481:1481:1481)) + (PORT datab (934:934:934) (992:992:992)) + (PORT datac (958:958:958) (990:990:990)) + (PORT datad (1201:1201:1201) (1318:1318:1318)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1071:1071:1071)) + (PORT datab (1335:1335:1335) (1360:1360:1360)) + (PORT datac (927:927:927) (1015:1015:1015)) + (PORT datad (1107:1107:1107) (1130:1130:1130)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (679:679:679)) + (PORT datab (1262:1262:1262) (1301:1301:1301)) + (PORT datac (566:566:566) (573:573:573)) + (PORT datad (1626:1626:1626) (1701:1701:1701)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (708:708:708) (808:808:808)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (255:255:255) (343:343:343)) + (PORT datad (881:881:881) (941:941:941)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (933:933:933)) + (PORT datab (1109:1109:1109) (1175:1175:1175)) + (PORT datac (1089:1089:1089) (1121:1121:1121)) + (PORT datad (673:673:673) (713:713:713)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (492:492:492)) + (PORT datab (1938:1938:1938) (2051:2051:2051)) + (PORT datac (1035:1035:1035) (1084:1084:1084)) + (PORT datad (1561:1561:1561) (1612:1612:1612)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (1000:1000:1000)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (895:895:895) (945:945:945)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (683:683:683)) + (PORT datab (1196:1196:1196) (1213:1213:1213)) + (PORT datac (208:208:208) (248:248:248)) + (PORT datad (624:624:624) (642:642:642)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (458:458:458)) + (PORT datab (1170:1170:1170) (1201:1201:1201)) + (PORT datac (620:620:620) (684:684:684)) + (PORT datad (1113:1113:1113) (1142:1142:1142)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1626:1626:1626) (1717:1717:1717)) + (PORT datab (1533:1533:1533) (1584:1584:1584)) + (PORT datac (1703:1703:1703) (1827:1827:1827)) + (PORT datad (1490:1490:1490) (1625:1625:1625)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1719:1719:1719)) + (PORT datab (1534:1534:1534) (1581:1581:1581)) + (PORT datac (1711:1711:1711) (1826:1826:1826)) + (PORT datad (1494:1494:1494) (1620:1620:1620)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1688:1688:1688) (1727:1727:1727)) + (PORT datab (1470:1470:1470) (1564:1564:1564)) + (PORT datac (2563:2563:2563) (2660:2660:2660)) + (PORT datad (1901:1901:1901) (2013:2013:2013)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (682:682:682)) + (PORT datab (1262:1262:1262) (1302:1302:1302)) + (PORT datac (1116:1116:1116) (1135:1135:1135)) + (PORT datad (553:553:553) (571:571:571)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1370:1370:1370)) + (PORT datab (464:464:464) (521:521:521)) + (PORT datac (1697:1697:1697) (1755:1755:1755)) + (PORT datad (267:267:267) (323:323:323)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1153:1153:1153)) + (PORT datab (1145:1145:1145) (1184:1184:1184)) + (PORT datac (548:548:548) (563:563:563)) + (PORT datad (609:609:609) (634:634:634)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (358:358:358)) + (PORT datab (465:465:465) (519:519:519)) + (PORT datac (191:191:191) (223:223:223)) + (PORT datad (1368:1368:1368) (1479:1479:1479)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal46\~0) + (DELAY + (ABSOLUTE + (PORT dataa (286:286:286) (382:382:382)) + (PORT datab (952:952:952) (1018:1018:1018)) + (PORT datac (903:903:903) (963:963:963)) + (PORT datad (1192:1192:1192) (1312:1312:1312)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1367:1367:1367)) + (PORT datab (866:866:866) (891:891:891)) + (PORT datac (1704:1704:1704) (1755:1755:1755)) + (PORT datad (263:263:263) (316:316:316)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2111:2111:2111) (2254:2254:2254)) + (PORT datab (2048:2048:2048) (2161:2161:2161)) + (PORT datac (986:986:986) (1043:1043:1043)) + (PORT datad (1210:1210:1210) (1253:1253:1253)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1380:1380:1380) (1424:1424:1424)) + (PORT datab (1059:1059:1059) (1143:1143:1143)) + (PORT datac (754:754:754) (762:762:762)) + (PORT datad (1235:1235:1235) (1269:1269:1269)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1061:1061:1061)) + (PORT datac (1148:1148:1148) (1203:1203:1203)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (369:369:369)) + (PORT datab (465:465:465) (518:518:518)) + (PORT datac (1197:1197:1197) (1289:1289:1289)) + (PORT datad (1363:1363:1363) (1476:1476:1476)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1248:1248:1248)) + (PORT datab (2197:2197:2197) (2296:2296:2296)) + (PORT datac (1334:1334:1334) (1445:1445:1445)) + (PORT datad (959:959:959) (1022:1022:1022)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1792:1792:1792) (1883:1883:1883)) + (PORT datab (1288:1288:1288) (1337:1337:1337)) + (PORT datac (1377:1377:1377) (1384:1384:1384)) + (PORT datad (883:883:883) (905:905:905)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (635:635:635)) + (PORT datac (550:550:550) (559:559:559)) + (PORT datad (1232:1232:1232) (1290:1290:1290)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (861:861:861) (876:876:876)) + (PORT datad (848:848:848) (889:889:889)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) + (DELAY + (ABSOLUTE + (PORT datac (2061:2061:2061) (2184:2184:2184)) + (PORT datad (959:959:959) (1014:1014:1014)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1615:1615:1615) (1714:1714:1714)) + (PORT datab (1532:1532:1532) (1580:1580:1580)) + (PORT datac (1706:1706:1706) (1825:1825:1825)) + (PORT datad (1489:1489:1489) (1621:1621:1621)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (717:717:717)) + (PORT datab (1494:1494:1494) (1553:1553:1553)) + (PORT datac (1138:1138:1138) (1205:1205:1205)) + (PORT datad (1383:1383:1383) (1432:1432:1432)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (2148:2148:2148) (2325:2325:2325)) + (PORT datab (675:675:675) (746:746:746)) + (PORT datac (1715:1715:1715) (1794:1794:1794)) + (PORT datad (205:205:205) (235:235:235)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1299:1299:1299) (1399:1399:1399)) + (PORT datad (2046:2046:2046) (2211:2211:2211)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (999:999:999)) + (PORT datab (454:454:454) (482:482:482)) + (PORT datac (408:408:408) (448:448:448)) + (PORT datad (1564:1564:1564) (1622:1622:1622)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (651:651:651)) + (PORT datab (1155:1155:1155) (1200:1200:1200)) + (PORT datac (1451:1451:1451) (1502:1502:1502)) + (PORT datad (337:337:337) (358:358:358)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) + (DELAY + (ABSOLUTE + (PORT datac (1520:1520:1520) (1613:1613:1613)) + (PORT datad (1159:1159:1159) (1225:1225:1225)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1261:1261:1261) (1371:1371:1371)) + (PORT datab (865:865:865) (889:889:889)) + (PORT datac (1688:1688:1688) (1749:1749:1749)) + (PORT datad (267:267:267) (323:323:323)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1371:1371:1371)) + (PORT datab (465:465:465) (519:519:519)) + (PORT datac (1689:1689:1689) (1752:1752:1752)) + (PORT datad (268:268:268) (320:320:320)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1420:1420:1420) (1451:1451:1451)) + (PORT datab (1101:1101:1101) (1122:1122:1122)) + (PORT datac (1072:1072:1072) (1084:1084:1084)) + (PORT datad (939:939:939) (973:973:973)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (719:719:719)) + (PORT datab (1167:1167:1167) (1240:1240:1240)) + (PORT datac (1455:1455:1455) (1509:1509:1509)) + (PORT datad (1468:1468:1468) (1520:1520:1520)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (420:420:420)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (623:623:623) (666:666:666)) + (PORT datad (189:189:189) (220:220:220)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (593:593:593)) + (PORT datab (860:860:860) (886:886:886)) + (PORT datac (854:854:854) (889:889:889)) + (PORT datad (805:805:805) (822:822:822)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1163:1163:1163)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (186:186:186) (228:228:228)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (483:483:483)) + (PORT datab (1218:1218:1218) (1272:1272:1272)) + (PORT datac (679:679:679) (709:709:709)) + (PORT datad (1295:1295:1295) (1387:1387:1387)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) + (DELAY + (ABSOLUTE + (PORT datab (2915:2915:2915) (3094:3094:3094)) + (PORT datac (2028:2028:2028) (2098:2098:2098)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1889:1889:1889) (1934:1934:1934)) + (PORT datab (2084:2084:2084) (2215:2215:2215)) + (PORT datac (1111:1111:1111) (1144:1144:1144)) + (PORT datad (208:208:208) (238:238:238)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (1234:1234:1234) (1326:1326:1326)) + (PORT datad (625:625:625) (665:665:665)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1232:1232:1232)) + (PORT datab (906:906:906) (961:961:961)) + (PORT datac (2032:2032:2032) (2056:2056:2056)) + (PORT datad (1479:1479:1479) (1541:1541:1541)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) + (DELAY + (ABSOLUTE + (PORT dataa (1057:1057:1057) (1151:1151:1151)) + (PORT datab (2381:2381:2381) (2493:2493:2493)) + (PORT datad (2113:2113:2113) (2257:2257:2257)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1487:1487:1487) (1536:1536:1536)) + (PORT datab (1011:1011:1011) (1078:1078:1078)) + (PORT datac (900:900:900) (921:921:921)) + (PORT datad (1172:1172:1172) (1187:1187:1187)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1479:1479:1479)) + (PORT datab (1137:1137:1137) (1178:1178:1178)) + (PORT datac (337:337:337) (365:365:365)) + (PORT datad (1137:1137:1137) (1159:1159:1159)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (412:412:412)) + (PORT datab (1088:1088:1088) (1114:1114:1114)) + (PORT datac (1575:1575:1575) (1617:1617:1617)) + (PORT datad (811:811:811) (828:828:828)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1206:1206:1206)) + (PORT datab (1169:1169:1169) (1204:1204:1204)) + (PORT datac (835:835:835) (863:863:863)) + (PORT datad (800:800:800) (827:827:827)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1212:1212:1212)) + (PORT datab (286:286:286) (351:351:351)) + (PORT datac (253:253:253) (312:312:312)) + (PORT datad (252:252:252) (297:297:297)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) + (DELAY + (ABSOLUTE + (PORT datac (948:948:948) (1024:1024:1024)) + (PORT datad (2023:2023:2023) (2146:2146:2146)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (897:897:897)) + (PORT datab (1012:1012:1012) (1081:1081:1081)) + (PORT datac (1223:1223:1223) (1284:1284:1284)) + (PORT datad (1171:1171:1171) (1183:1183:1183)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (257:257:257)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1230:1230:1230)) + (PORT datab (1013:1013:1013) (1082:1082:1082)) + (PORT datac (2030:2030:2030) (2056:2056:2056)) + (PORT datad (1479:1479:1479) (1543:1543:1543)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1377:1377:1377)) + (PORT datab (1170:1170:1170) (1231:1231:1231)) + (PORT datac (840:840:840) (887:887:887)) + (PORT datad (1322:1322:1322) (1434:1434:1434)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (984:984:984)) + (PORT datab (941:941:941) (1009:1009:1009)) + (PORT datac (1210:1210:1210) (1289:1289:1289)) + (PORT datad (658:658:658) (688:688:688)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1353:1353:1353) (1482:1482:1482)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (382:382:382) (410:410:410)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal69\~0) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (968:968:968)) + (PORT datab (1718:1718:1718) (1808:1808:1808)) + (PORT datac (1144:1144:1144) (1148:1148:1148)) + (PORT datad (653:653:653) (693:693:693)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1290:1290:1290)) + (PORT datad (1198:1198:1198) (1259:1259:1259)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1044:1044:1044)) + (PORT datab (2023:2023:2023) (2060:2060:2060)) + (PORT datac (1148:1148:1148) (1153:1153:1153)) + (PORT datad (650:650:650) (690:690:690)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1758:1758:1758) (1876:1876:1876)) + (PORT datab (915:915:915) (977:977:977)) + (PORT datad (216:216:216) (242:242:242)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (725:725:725)) + (PORT datab (1178:1178:1178) (1215:1215:1215)) + (PORT datac (934:934:934) (1029:1029:1029)) + (PORT datad (903:903:903) (950:950:950)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1467:1467:1467) (1537:1537:1537)) + (PORT datab (1228:1228:1228) (1312:1312:1312)) + (PORT datac (1432:1432:1432) (1520:1520:1520)) + (PORT datad (820:820:820) (833:833:833)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~2) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (845:845:845)) + (PORT datab (854:854:854) (887:887:887)) + (PORT datad (673:673:673) (693:693:693)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2011:2011:2011) (2114:2114:2114)) + (PORT datab (2111:2111:2111) (2221:2221:2221)) + (PORT datac (547:547:547) (569:569:569)) + (PORT datad (1739:1739:1739) (1782:1782:1782)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (882:882:882)) + (PORT datab (952:952:952) (1011:1011:1011)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (1472:1472:1472) (1533:1533:1533)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT datac (1162:1162:1162) (1174:1174:1174)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1237:1237:1237) (1303:1303:1303)) + (PORT datab (992:992:992) (1101:1101:1101)) + (PORT datac (657:657:657) (716:716:716)) + (PORT datad (1239:1239:1239) (1323:1323:1323)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) + (DELAY + (ABSOLUTE + (PORT datab (1082:1082:1082) (1193:1193:1193)) + (PORT datac (1465:1465:1465) (1548:1548:1548)) + (PORT datad (2348:2348:2348) (2497:2497:2497)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (726:726:726)) + (PORT datab (1800:1800:1800) (1830:1830:1830)) + (PORT datac (988:988:988) (1048:1048:1048)) + (PORT datad (1210:1210:1210) (1257:1257:1257)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1084:1084:1084)) + (PORT datab (1248:1248:1248) (1292:1292:1292)) + (PORT datac (1097:1097:1097) (1128:1128:1128)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (983:983:983)) + (PORT datab (1091:1091:1091) (1163:1163:1163)) + (PORT datac (985:985:985) (1050:1050:1050)) + (PORT datad (1157:1157:1157) (1206:1206:1206)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1013:1013:1013) (1086:1086:1086)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datac (1253:1253:1253) (1320:1320:1320)) + (PORT datad (1054:1054:1054) (1123:1123:1123)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT datab (1514:1514:1514) (1650:1650:1650)) + (PORT datac (1504:1504:1504) (1617:1617:1617)) + (PORT datad (1306:1306:1306) (1325:1325:1325)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (831:831:831)) + (PORT datab (860:860:860) (870:870:870)) + (PORT datac (1242:1242:1242) (1262:1262:1262)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1454:1454:1454)) + (PORT datab (2084:2084:2084) (2114:2114:2114)) + (PORT datac (835:835:835) (859:859:859)) + (PORT datad (788:788:788) (798:798:798)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal48\~0) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (968:968:968)) + (PORT datab (1718:1718:1718) (1807:1807:1807)) + (PORT datac (1144:1144:1144) (1148:1148:1148)) + (PORT datad (654:654:654) (693:693:693)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (998:998:998)) + (PORT datab (900:900:900) (985:985:985)) + (PORT datac (966:966:966) (1015:1015:1015)) + (PORT datad (1295:1295:1295) (1365:1365:1365)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1246:1246:1246) (1336:1336:1336)) + (PORT datab (1005:1005:1005) (1056:1056:1056)) + (PORT datac (209:209:209) (248:248:248)) + (PORT datad (1195:1195:1195) (1244:1244:1244)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1847:1847:1847) (1960:1960:1960)) + (PORT datab (1294:1294:1294) (1397:1397:1397)) + (PORT datac (2030:2030:2030) (2118:2118:2118)) + (PORT datad (836:836:836) (843:843:843)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1251:1251:1251)) + (PORT datab (1013:1013:1013) (1076:1076:1076)) + (PORT datac (621:621:621) (659:659:659)) + (PORT datad (1176:1176:1176) (1188:1188:1188)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (945:945:945)) + (PORT datab (1062:1062:1062) (1128:1128:1128)) + (PORT datac (579:579:579) (602:602:602)) + (PORT datad (1089:1089:1089) (1104:1104:1104)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1618:1618:1618) (1711:1711:1711)) + (PORT datab (1527:1527:1527) (1658:1658:1658)) + (PORT datac (1710:1710:1710) (1825:1825:1825)) + (PORT datad (1448:1448:1448) (1496:1496:1496)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1670:1670:1670) (1753:1753:1753)) + (PORT datab (1528:1528:1528) (1617:1617:1617)) + (PORT datac (966:966:966) (1014:1014:1014)) + (PORT datad (1159:1159:1159) (1218:1218:1218)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (622:622:622)) + (PORT datab (923:923:923) (944:944:944)) + (PORT datac (969:969:969) (1018:1018:1018)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1638:1638:1638) (1764:1764:1764)) + (PORT datab (1075:1075:1075) (1149:1149:1149)) + (PORT datac (1806:1806:1806) (1948:1948:1948)) + (PORT datad (942:942:942) (974:974:974)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1241:1241:1241) (1294:1294:1294)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (972:972:972) (992:992:992)) + (PORT datad (902:902:902) (955:955:955)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1348:1348:1348) (1398:1398:1398)) + (PORT datab (1002:1002:1002) (1057:1057:1057)) + (PORT datac (575:575:575) (596:596:596)) + (PORT datad (637:637:637) (681:681:681)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1988:1988:1988) (2128:2128:2128)) + (PORT datab (1534:1534:1534) (1632:1632:1632)) + (PORT datac (227:227:227) (272:272:272)) + (PORT datad (1108:1108:1108) (1149:1149:1149)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1617:1617:1617) (1711:1711:1711)) + (PORT datab (1528:1528:1528) (1657:1657:1657)) + (PORT datac (1709:1709:1709) (1824:1824:1824)) + (PORT datad (1448:1448:1448) (1496:1496:1496)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (983:983:983)) + (PORT datab (1427:1427:1427) (1510:1510:1510)) + (PORT datac (1333:1333:1333) (1448:1448:1448)) + (PORT datad (1550:1550:1550) (1659:1659:1659)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (721:721:721)) + (PORT datab (1637:1637:1637) (1642:1642:1642)) + (PORT datac (1298:1298:1298) (1314:1314:1314)) + (PORT datad (1443:1443:1443) (1563:1563:1563)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1580:1580:1580) (1703:1703:1703)) + (PORT datab (1365:1365:1365) (1479:1479:1479)) + (PORT datac (1152:1152:1152) (1186:1186:1186)) + (PORT datad (832:832:832) (834:834:834)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (729:729:729)) + (PORT datab (995:995:995) (1057:1057:1057)) + (PORT datac (1074:1074:1074) (1196:1196:1196)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) + (DELAY + (ABSOLUTE + (PORT dataa (2265:2265:2265) (2414:2414:2414)) + (PORT datab (848:848:848) (886:886:886)) + (PORT datac (2113:2113:2113) (2221:2221:2221)) + (PORT datad (669:669:669) (694:694:694)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (996:996:996)) + (PORT datab (1005:1005:1005) (1060:1060:1060)) + (PORT datac (1413:1413:1413) (1487:1487:1487)) + (PORT datad (1522:1522:1522) (1622:1622:1622)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (684:684:684)) + (PORT datab (440:440:440) (477:477:477)) + (PORT datac (202:202:202) (238:238:238)) + (PORT datad (1428:1428:1428) (1432:1432:1432)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (662:662:662)) + (PORT datab (1001:1001:1001) (1053:1053:1053)) + (PORT datac (870:870:870) (914:914:914)) + (PORT datad (809:809:809) (854:854:854)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (392:392:392)) + (PORT datab (331:331:331) (360:360:360)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (228:228:228) (271:271:271)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (657:657:657)) + (PORT datab (1415:1415:1415) (1491:1491:1491)) + (PORT datac (638:638:638) (658:658:658)) + (PORT datad (1624:1624:1624) (1706:1706:1706)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (702:702:702)) + (PORT datab (995:995:995) (1056:1056:1056)) + (PORT datac (1075:1075:1075) (1194:1194:1194)) + (PORT datad (2306:2306:2306) (2342:2342:2342)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (980:980:980)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (346:346:346) (371:371:371)) + (PORT datad (2307:2307:2307) (2344:2344:2344)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~4) + (DELAY + (ABSOLUTE + (PORT datab (1060:1060:1060) (1178:1178:1178)) + (PORT datac (1452:1452:1452) (1530:1530:1530)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1453:1453:1453)) + (PORT datab (942:942:942) (993:993:993)) + (PORT datac (1045:1045:1045) (1115:1115:1115)) + (PORT datad (1421:1421:1421) (1470:1470:1470)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1009:1009:1009)) + (PORT datab (1445:1445:1445) (1500:1500:1500)) + (PORT datac (972:972:972) (995:995:995)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1123:1123:1123)) + (PORT datab (1196:1196:1196) (1246:1246:1246)) + (PORT datac (663:663:663) (712:712:712)) + (PORT datad (879:879:879) (931:931:931)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (616:616:616)) + (PORT datac (573:573:573) (593:593:593)) + (PORT datad (531:531:531) (543:543:543)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (303:303:303)) + (PORT datab (1244:1244:1244) (1269:1269:1269)) + (PORT datac (1174:1174:1174) (1214:1214:1214)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (925:925:925)) + (PORT datab (852:852:852) (865:865:865)) + (PORT datac (342:342:342) (367:367:367)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1987:1987:1987) (2132:2132:2132)) + (PORT datab (903:903:903) (955:955:955)) + (PORT datac (224:224:224) (269:269:269)) + (PORT datad (1402:1402:1402) (1466:1466:1466)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT dataa (1798:1798:1798) (1933:1933:1933)) + (PORT datab (1613:1613:1613) (1726:1726:1726)) + (PORT datad (1409:1409:1409) (1475:1475:1475)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2050:2050:2050) (2089:2089:2089)) + (PORT datab (946:946:946) (1023:1023:1023)) + (PORT datac (1099:1099:1099) (1158:1158:1158)) + (PORT datad (914:914:914) (1002:1002:1002)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1335:1335:1335) (1354:1354:1354)) + (PORT datab (1166:1166:1166) (1239:1239:1239)) + (PORT datac (1485:1485:1485) (1514:1514:1514)) + (PORT datad (1468:1468:1468) (1520:1520:1520)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (1144:1144:1144) (1189:1189:1189)) + (PORT datab (222:222:222) (269:269:269)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (836:836:836) (868:868:868)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT datab (963:963:963) (1010:1010:1010)) + (PORT datac (601:601:601) (607:607:607)) + (PORT datad (676:676:676) (718:718:718)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT datac (928:928:928) (973:973:973)) + (PORT datad (680:680:680) (720:720:720)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1064:1064:1064)) + (PORT datab (717:717:717) (774:774:774)) + (PORT datac (903:903:903) (944:944:944)) + (PORT datad (1740:1740:1740) (1858:1858:1858)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1494:1494:1494) (1600:1600:1600)) + (PORT datab (1475:1475:1475) (1582:1582:1582)) + (PORT datac (1847:1847:1847) (1916:1916:1916)) + (PORT datad (402:402:402) (439:439:439)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1306:1306:1306)) + (PORT datac (943:943:943) (1021:1021:1021)) + (PORT datad (1208:1208:1208) (1293:1293:1293)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1221:1221:1221) (1285:1285:1285)) + (PORT datab (1430:1430:1430) (1456:1456:1456)) + (PORT datac (1096:1096:1096) (1116:1116:1116)) + (PORT datad (1325:1325:1325) (1332:1332:1332)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) + (DELAY + (ABSOLUTE + (PORT datab (934:934:934) (968:968:968)) + (PORT datac (531:531:531) (544:544:544)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (1063:1063:1063)) + (PORT datab (717:717:717) (773:773:773)) + (PORT datac (901:901:901) (942:942:942)) + (PORT datad (1738:1738:1738) (1857:1857:1857)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1397:1397:1397)) + (PORT datab (917:917:917) (962:962:962)) + (PORT datad (619:619:619) (654:654:654)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (915:915:915)) + (PORT datab (1463:1463:1463) (1548:1548:1548)) + (PORT datac (1313:1313:1313) (1405:1405:1405)) + (PORT datad (2215:2215:2215) (2336:2336:2336)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~36) + (DELAY + (ABSOLUTE + (PORT dataa (2340:2340:2340) (2463:2463:2463)) + (PORT datab (901:901:901) (951:951:951)) + (PORT datac (370:370:370) (398:398:398)) + (PORT datad (1461:1461:1461) (1558:1558:1558)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (258:258:258)) + (PORT datab (239:239:239) (284:284:284)) + (PORT datac (839:839:839) (874:874:874)) + (PORT datad (554:554:554) (572:572:572)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (DELAY + (ABSOLUTE + (PORT datac (2441:2441:2441) (2623:2623:2623)) + (PORT datad (1996:1996:1996) (2085:2085:2085)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1464:1464:1464) (1521:1521:1521)) + (PORT datab (843:843:843) (881:881:881)) + (PORT datac (916:916:916) (966:966:966)) + (PORT datad (669:669:669) (689:689:689)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1438:1438:1438) (1467:1467:1467)) + (PORT datab (1349:1349:1349) (1381:1381:1381)) + (PORT datac (855:855:855) (867:867:867)) + (PORT datad (805:805:805) (815:815:815)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1088:1088:1088) (1119:1119:1119)) + (PORT datab (2571:2571:2571) (2668:2668:2668)) + (PORT datac (1529:1529:1529) (1666:1666:1666)) + (PORT datad (1710:1710:1710) (1831:1831:1831)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) + (DELAY + (ABSOLUTE + (PORT datac (207:207:207) (248:248:248)) + (PORT datad (209:209:209) (239:239:239)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1221:1221:1221) (1290:1290:1290)) + (PORT datab (1275:1275:1275) (1382:1382:1382)) + (PORT datac (1752:1752:1752) (1793:1793:1793)) + (PORT datad (851:851:851) (865:865:865)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (427:427:427)) + (PORT datab (401:401:401) (428:428:428)) + (PORT datac (370:370:370) (396:396:396)) + (PORT datad (207:207:207) (244:244:244)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1486:1486:1486) (1538:1538:1538)) + (PORT datab (1265:1265:1265) (1379:1379:1379)) + (PORT datac (900:900:900) (922:922:922)) + (PORT datad (1168:1168:1168) (1190:1190:1190)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) + (DELAY + (ABSOLUTE + (PORT dataa (708:708:708) (754:754:754)) + (PORT datab (2783:2783:2783) (2910:2910:2910)) + (PORT datac (1297:1297:1297) (1413:1413:1413)) + (PORT datad (574:574:574) (587:587:587)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (898:898:898)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (196:196:196) (240:240:240)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (677:677:677)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (572:572:572) (582:582:582)) + (PORT datad (1423:1423:1423) (1458:1458:1458)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1380:1380:1380) (1439:1439:1439)) + (PORT datab (1847:1847:1847) (1876:1876:1876)) + (PORT datac (1135:1135:1135) (1170:1170:1170)) + (PORT datad (1756:1756:1756) (1776:1776:1776)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1865:1865:1865) (1941:1941:1941)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1135:1135:1135) (1190:1190:1190)) + (PORT datad (605:605:605) (619:619:619)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (655:655:655)) + (PORT datab (1026:1026:1026) (1124:1124:1124)) + (PORT datac (873:873:873) (908:908:908)) + (PORT datad (1598:1598:1598) (1712:1712:1712)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (363:363:363) (397:397:397)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (1031:1031:1031) (1049:1049:1049)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1437:1437:1437) (1449:1449:1449)) + (PORT datab (1437:1437:1437) (1503:1503:1503)) + (PORT datac (611:611:611) (628:628:628)) + (PORT datad (899:899:899) (951:951:951)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1639:1639:1639) (1765:1765:1765)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1806:1806:1806) (1948:1948:1948)) + (PORT datad (906:906:906) (958:958:958)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1436:1436:1436) (1449:1449:1449)) + (PORT datab (1436:1436:1436) (1504:1504:1504)) + (PORT datac (1048:1048:1048) (1116:1116:1116)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1814:1814:1814) (1847:1847:1847)) + (PORT datab (337:337:337) (365:365:365)) + (PORT datac (1045:1045:1045) (1115:1115:1115)) + (PORT datad (1199:1199:1199) (1246:1246:1246)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1419:1419:1419) (1450:1450:1450)) + (PORT datab (1438:1438:1438) (1497:1497:1497)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (938:938:938) (969:969:969)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (979:979:979) (1010:1010:1010)) + (PORT datac (1074:1074:1074) (1085:1085:1085)) + (PORT datad (1198:1198:1198) (1245:1245:1245)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1963:1963:1963) (2070:2070:2070)) + (PORT datab (1844:1844:1844) (1871:1871:1871)) + (PORT datac (1132:1132:1132) (1168:1168:1168)) + (PORT datad (1980:1980:1980) (2108:2108:2108)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (408:408:408)) + (PORT datab (1844:1844:1844) (1872:1872:1872)) + (PORT datac (1584:1584:1584) (1600:1600:1600)) + (PORT datad (187:187:187) (220:220:220)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (666:666:666)) + (PORT datab (1003:1003:1003) (1051:1051:1051)) + (PORT datac (1298:1298:1298) (1337:1337:1337)) + (PORT datad (805:805:805) (832:832:832)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (672:672:672)) + (PORT datac (1050:1050:1050) (1065:1065:1065)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1008:1008:1008)) + (PORT datab (1439:1439:1439) (1498:1498:1498)) + (PORT datac (975:975:975) (990:990:990)) + (PORT datad (1202:1202:1202) (1250:1250:1250)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (415:415:415)) + (PORT datab (213:213:213) (258:258:258)) + (PORT datac (354:354:354) (387:387:387)) + (PORT datad (344:344:344) (367:367:367)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT datab (642:642:642) (686:686:686)) + (PORT datac (872:872:872) (919:919:919)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (614:614:614)) + (PORT datab (892:892:892) (907:907:907)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (841:841:841)) + (PORT datab (697:697:697) (728:728:728)) + (PORT datac (916:916:916) (968:968:968)) + (PORT datad (816:816:816) (839:839:839)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datab (869:869:869) (890:890:890)) + (PORT datad (810:810:810) (826:826:826)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT datab (215:215:215) (259:259:259)) + (PORT datac (355:355:355) (387:387:387)) + (PORT datad (345:345:345) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1639:1639:1639) (1766:1766:1766)) + (PORT datab (1825:1825:1825) (1925:1925:1925)) + (PORT datac (1804:1804:1804) (1951:1951:1951)) + (PORT datad (941:941:941) (965:965:965)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1437:1437:1437) (1451:1451:1451)) + (PORT datab (1439:1439:1439) (1497:1497:1497)) + (PORT datac (974:974:974) (995:995:995)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1814:1814:1814) (1850:1850:1850)) + (PORT datab (1003:1003:1003) (1029:1029:1029)) + (PORT datac (315:315:315) (336:336:336)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (706:706:706)) + (PORT datab (608:608:608) (621:621:621)) + (PORT datac (813:813:813) (840:840:840)) + (PORT datad (337:337:337) (356:356:356)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1357:1357:1357)) + (PORT datab (986:986:986) (1070:1070:1070)) + (PORT datac (1073:1073:1073) (1153:1153:1153)) + (PORT datad (966:966:966) (1077:1077:1077)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1463:1463:1463) (1478:1478:1478)) + (PORT datab (1379:1379:1379) (1398:1398:1398)) + (PORT datac (1618:1618:1618) (1662:1662:1662)) + (PORT datad (1263:1263:1263) (1327:1327:1327)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1231:1231:1231)) + (PORT datab (1048:1048:1048) (1149:1149:1149)) + (PORT datad (1348:1348:1348) (1490:1490:1490)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (736:736:736)) + (PORT datab (1001:1001:1001) (1033:1033:1033)) + (PORT datac (553:553:553) (568:568:568)) + (PORT datad (222:222:222) (249:249:249)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (798:798:798)) + (PORT datab (948:948:948) (1025:1025:1025)) + (PORT datac (1099:1099:1099) (1159:1159:1159)) + (PORT datad (909:909:909) (998:998:998)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1225:1225:1225) (1294:1294:1294)) + (PORT datab (224:224:224) (271:271:271)) + (PORT datac (2351:2351:2351) (2449:2449:2449)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT datab (2076:2076:2076) (2143:2143:2143)) + (PORT datac (1719:1719:1719) (1796:1796:1796)) + (PORT datad (1155:1155:1155) (1236:1236:1236)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1501:1501:1501)) + (PORT datab (1425:1425:1425) (1462:1462:1462)) + (PORT datac (836:836:836) (865:865:865)) + (PORT datad (394:394:394) (429:429:429)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (894:894:894)) + (PORT datab (1197:1197:1197) (1223:1223:1223)) + (PORT datac (981:981:981) (1043:1043:1043)) + (PORT datad (972:972:972) (1036:1036:1036)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2006:2006:2006) (2147:2147:2147)) + (PORT datab (450:450:450) (480:480:480)) + (PORT datac (1000:1000:1000) (1045:1045:1045)) + (PORT datad (900:900:900) (950:950:950)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~1) + (DELAY + (ABSOLUTE + (PORT datac (1589:1589:1589) (1676:1676:1676)) + (PORT datad (1494:1494:1494) (1621:1621:1621)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (1016:1016:1016)) + (PORT datab (1194:1194:1194) (1223:1223:1223)) + (PORT datac (1942:1942:1942) (2000:2000:2000)) + (PORT datad (641:641:641) (693:693:693)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (627:627:627) (662:662:662)) + (PORT datac (1683:1683:1683) (1789:1789:1789)) + (PORT datad (633:633:633) (651:651:651)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1500:1500:1500) (1575:1575:1575)) + (PORT datab (362:362:362) (397:397:397)) + (PORT datac (2091:2091:2091) (2220:2220:2220)) + (PORT datad (590:590:590) (607:607:607)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (800:800:800)) + (PORT datab (947:947:947) (1025:1025:1025)) + (PORT datac (1098:1098:1098) (1158:1158:1158)) + (PORT datad (911:911:911) (1001:1001:1001)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1539:1539:1539)) + (PORT datab (1227:1227:1227) (1318:1318:1318)) + (PORT datac (1459:1459:1459) (1517:1517:1517)) + (PORT datad (1138:1138:1138) (1159:1159:1159)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1840:1840:1840) (1939:1939:1939)) + (PORT datab (2068:2068:2068) (2187:2187:2187)) + (PORT datac (1327:1327:1327) (1336:1336:1336)) + (PORT datad (2013:2013:2013) (2125:2125:2125)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1215:1215:1215)) + (PORT datab (653:653:653) (674:674:674)) + (PORT datac (1214:1214:1214) (1294:1294:1294)) + (PORT datad (596:596:596) (619:619:619)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1170:1170:1170)) + (PORT datab (841:841:841) (864:864:864)) + (PORT datad (579:579:579) (590:590:590)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) + (DELAY + (ABSOLUTE + (PORT datac (1753:1753:1753) (1873:1873:1873)) + (PORT datad (1571:1571:1571) (1694:1694:1694)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1056:1056:1056)) + (PORT datab (1039:1039:1039) (1096:1096:1096)) + (PORT datac (1052:1052:1052) (1117:1117:1117)) + (PORT datad (625:625:625) (651:651:651)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1726:1726:1726)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (1053:1053:1053) (1117:1117:1117)) + (PORT datad (1795:1795:1795) (1930:1930:1930)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1272:1272:1272)) + (PORT datab (689:689:689) (706:706:706)) + (PORT datac (1267:1267:1267) (1395:1395:1395)) + (PORT datad (1570:1570:1570) (1720:1720:1720)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (1265:1265:1265) (1395:1395:1395)) + (PORT datad (1573:1573:1573) (1723:1723:1723)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1230:1230:1230) (1277:1277:1277)) + (PORT datab (1647:1647:1647) (1673:1673:1673)) + (PORT datac (777:777:777) (786:786:786)) + (PORT datad (581:581:581) (600:600:600)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (652:652:652)) + (PORT datab (656:656:656) (711:711:711)) + (PORT datac (680:680:680) (730:730:730)) + (PORT datad (800:800:800) (871:871:871)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (1087:1087:1087)) + (PORT datab (1683:1683:1683) (1741:1741:1741)) + (PORT datac (1582:1582:1582) (1690:1690:1690)) + (PORT datad (964:964:964) (1004:1004:1004)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1342:1342:1342)) + (PORT datab (935:935:935) (949:949:949)) + (PORT datac (978:978:978) (1043:1043:1043)) + (PORT datad (1176:1176:1176) (1188:1188:1188)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (390:390:390)) + (PORT datab (1476:1476:1476) (1506:1506:1506)) + (PORT datac (1080:1080:1080) (1084:1084:1084)) + (PORT datad (1360:1360:1360) (1375:1375:1375)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (392:392:392)) + (PORT datab (238:238:238) (276:276:276)) + (PORT datac (1044:1044:1044) (1080:1080:1080)) + (PORT datad (1386:1386:1386) (1428:1428:1428)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (907:907:907)) + (PORT datab (364:364:364) (400:400:400)) + (PORT datac (656:656:656) (701:701:701)) + (PORT datad (837:837:837) (878:878:878)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (810:810:810)) + (PORT datab (933:933:933) (988:988:988)) + (PORT datac (981:981:981) (1058:1058:1058)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1552:1552:1552)) + (PORT datab (614:614:614) (644:644:644)) + (PORT datac (1197:1197:1197) (1258:1258:1258)) + (PORT datad (844:844:844) (855:855:855)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (588:588:588) (608:608:608)) + (PORT datad (876:876:876) (896:896:896)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (1250:1250:1250)) + (PORT datab (965:965:965) (1013:1013:1013)) + (PORT datac (1049:1049:1049) (1111:1111:1111)) + (PORT datad (1444:1444:1444) (1477:1477:1477)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1082:1082:1082) (1153:1153:1153)) + (PORT datab (970:970:970) (1019:1019:1019)) + (PORT datac (308:308:308) (334:334:334)) + (PORT datad (628:628:628) (654:654:654)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1085:1085:1085)) + (PORT datab (1386:1386:1386) (1414:1414:1414)) + (PORT datac (1180:1180:1180) (1211:1211:1211)) + (PORT datad (1209:1209:1209) (1252:1252:1252)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (1246:1246:1246) (1296:1296:1296)) + (PORT datac (984:984:984) (1048:1048:1048)) + (PORT datad (625:625:625) (654:654:654)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (910:910:910)) + (PORT datab (1428:1428:1428) (1466:1466:1466)) + (PORT datac (1688:1688:1688) (1726:1726:1726)) + (PORT datad (2057:2057:2057) (2190:2190:2190)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (642:642:642)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (1398:1398:1398) (1422:1422:1422)) + (PORT datad (1424:1424:1424) (1462:1462:1462)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1803:1803:1803) (1945:1945:1945)) + (PORT datab (847:847:847) (858:858:858)) + (PORT datac (838:838:838) (869:869:869)) + (PORT datad (2056:2056:2056) (2191:2191:2191)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (847:847:847)) + (PORT datab (783:783:783) (809:809:809)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (382:382:382)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (539:539:539) (561:561:561)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (1004:1004:1004)) + (PORT datab (876:876:876) (893:893:893)) + (PORT datac (1689:1689:1689) (1781:1781:1781)) + (PORT datad (1175:1175:1175) (1232:1232:1232)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1346:1346:1346) (1340:1340:1340)) + (PORT datab (1176:1176:1176) (1219:1219:1219)) + (PORT datac (1123:1123:1123) (1137:1137:1137)) + (PORT datad (665:665:665) (719:719:719)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1247:1247:1247)) + (PORT datac (582:582:582) (614:614:614)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1190:1190:1190) (1242:1242:1242)) + (PORT datab (650:650:650) (679:679:679)) + (PORT datac (191:191:191) (237:237:237)) + (PORT datad (607:607:607) (635:635:635)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (274:274:274)) + (PORT datac (2094:2094:2094) (2219:2219:2219)) + (PORT datad (1462:1462:1462) (1527:1527:1527)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (461:461:461)) + (PORT datab (1161:1161:1161) (1190:1190:1190)) + (PORT datac (1460:1460:1460) (1518:1518:1518)) + (PORT datad (1106:1106:1106) (1136:1136:1136)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1080:1080:1080) (1147:1147:1147)) + (PORT datab (1037:1037:1037) (1105:1105:1105)) + (PORT datac (1180:1180:1180) (1210:1210:1210)) + (PORT datad (1210:1210:1210) (1252:1252:1252)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (919:919:919)) + (PORT datab (661:661:661) (705:705:705)) + (PORT datac (1104:1104:1104) (1117:1117:1117)) + (PORT datad (766:766:766) (786:786:786)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1156:1156:1156)) + (PORT datab (1528:1528:1528) (1657:1657:1657)) + (PORT datac (609:609:609) (665:665:665)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (762:762:762)) + (PORT datab (849:849:849) (885:885:885)) + (PORT datac (787:787:787) (804:804:804)) + (PORT datad (670:670:670) (694:694:694)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1084:1084:1084)) + (PORT datab (969:969:969) (1019:1019:1019)) + (PORT datac (192:192:192) (223:223:223)) + (PORT datad (1444:1444:1444) (1475:1475:1475)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1298:1298:1298) (1390:1390:1390)) + (PORT datab (968:968:968) (1017:1017:1017)) + (PORT datac (1050:1050:1050) (1110:1110:1110)) + (PORT datad (1553:1553:1553) (1682:1682:1682)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1298:1298:1298) (1391:1391:1391)) + (PORT datab (1247:1247:1247) (1291:1291:1291)) + (PORT datac (985:985:985) (1043:1043:1043)) + (PORT datad (1553:1553:1553) (1682:1682:1682)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (579:579:579)) + (PORT datab (244:244:244) (288:288:288)) + (PORT datac (543:543:543) (551:551:551)) + (PORT datad (1454:1454:1454) (1511:1511:1511)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1400:1400:1400) (1422:1422:1422)) + (PORT datac (572:572:572) (596:596:596)) + (PORT datad (602:602:602) (630:630:630)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (737:737:737)) + (PORT datab (1115:1115:1115) (1164:1164:1164)) + (PORT datac (969:969:969) (1001:1001:1001)) + (PORT datad (1160:1160:1160) (1223:1223:1223)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (984:984:984)) + (PORT datab (941:941:941) (1009:1009:1009)) + (PORT datac (1210:1210:1210) (1289:1289:1289)) + (PORT datad (381:381:381) (406:406:406)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1765:1765:1765) (1808:1808:1808)) + (PORT datab (1620:1620:1620) (1658:1658:1658)) + (PORT datac (1305:1305:1305) (1421:1421:1421)) + (PORT datad (1541:1541:1541) (1677:1677:1677)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1103:1103:1103) (1119:1119:1119)) + (PORT datab (1046:1046:1046) (1094:1094:1094)) + (PORT datac (952:952:952) (984:984:984)) + (PORT datad (819:819:819) (844:844:844)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1023:1023:1023)) + (PORT datab (700:700:700) (721:721:721)) + (PORT datac (216:216:216) (260:260:260)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (874:874:874)) + (PORT datab (648:648:648) (669:669:669)) + (PORT datac (877:877:877) (899:899:899)) + (PORT datad (813:813:813) (834:834:834)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (363:363:363) (397:397:397)) + (PORT datac (964:964:964) (1033:1033:1033)) + (PORT datad (590:590:590) (607:607:607)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datac (1711:1711:1711) (1773:1773:1773)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (296:296:296)) + (PORT datab (1200:1200:1200) (1240:1240:1240)) + (PORT datac (1213:1213:1213) (1232:1232:1232)) + (PORT datad (559:559:559) (571:571:571)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1102:1102:1102) (1121:1121:1121)) + (PORT datab (246:246:246) (294:294:294)) + (PORT datac (901:901:901) (943:943:943)) + (PORT datad (1975:1975:1975) (2012:2012:2012)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (840:840:840)) + (PORT datab (850:850:850) (877:877:877)) + (PORT datac (595:595:595) (617:617:617)) + (PORT datad (811:811:811) (824:824:824)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (2154:2154:2154) (2304:2304:2304)) + (PORT datab (1756:1756:1756) (1875:1875:1875)) + (PORT datac (868:868:868) (905:905:905)) + (PORT datad (2343:2343:2343) (2450:2450:2450)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1025:1025:1025)) + (PORT datab (2108:2108:2108) (2222:2222:2222)) + (PORT datac (548:548:548) (573:573:573)) + (PORT datad (1982:1982:1982) (2069:2069:2069)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1779:1779:1779) (1888:1888:1888)) + (PORT datab (1077:1077:1077) (1152:1152:1152)) + (PORT datac (971:971:971) (991:991:991)) + (PORT datad (2049:2049:2049) (2156:2156:2156)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1244:1244:1244)) + (PORT datab (1192:1192:1192) (1241:1241:1241)) + (PORT datac (610:610:610) (626:626:626)) + (PORT datad (2306:2306:2306) (2345:2345:2345)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1033:1033:1033)) + (PORT datab (1150:1150:1150) (1177:1177:1177)) + (PORT datac (346:346:346) (385:385:385)) + (PORT datad (630:630:630) (669:669:669)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (890:890:890)) + (PORT datac (839:839:839) (858:858:858)) + (PORT datad (520:520:520) (531:531:531)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (288:288:288)) + (PORT datab (250:250:250) (300:300:300)) + (PORT datac (1960:1960:1960) (2089:2089:2089)) + (PORT datad (202:202:202) (238:238:238)) + (IOPATH dataa combout (303:303:303) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1478:1478:1478)) + (PORT datab (1346:1346:1346) (1363:1363:1363)) + (PORT datac (870:870:870) (896:896:896)) + (PORT datad (1449:1449:1449) (1511:1511:1511)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1189:1189:1189)) + (PORT datab (685:685:685) (754:754:754)) + (PORT datac (958:958:958) (1039:1039:1039)) + (PORT datad (613:613:613) (629:629:629)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (664:664:664)) + (PORT datab (973:973:973) (1069:1069:1069)) + (PORT datac (1733:1733:1733) (1832:1832:1832)) + (PORT datad (1149:1149:1149) (1173:1173:1173)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1999:1999:1999) (2036:2036:2036)) + (PORT datab (872:872:872) (899:899:899)) + (PORT datac (1356:1356:1356) (1432:1432:1432)) + (PORT datad (1348:1348:1348) (1396:1396:1396)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (650:650:650)) + (PORT datab (1061:1061:1061) (1123:1123:1123)) + (PORT datac (208:208:208) (247:247:247)) + (PORT datad (864:864:864) (923:923:923)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (632:632:632)) + (PORT datab (203:203:203) (245:245:245)) + (PORT datac (877:877:877) (914:914:914)) + (PORT datad (853:853:853) (874:874:874)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1749:1749:1749) (1769:1769:1769)) + (PORT datab (1064:1064:1064) (1181:1181:1181)) + (PORT datac (1204:1204:1204) (1273:1273:1273)) + (PORT datad (860:860:860) (875:875:875)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (719:719:719)) + (PORT datab (1166:1166:1166) (1236:1236:1236)) + (PORT datac (1485:1485:1485) (1511:1511:1511)) + (PORT datad (1469:1469:1469) (1516:1516:1516)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (880:880:880)) + (PORT datab (1385:1385:1385) (1395:1395:1395)) + (PORT datac (777:777:777) (796:796:796)) + (PORT datad (1739:1739:1739) (1779:1779:1779)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (1404:1404:1404) (1480:1480:1480)) + (PORT datab (2358:2358:2358) (2492:2492:2492)) + (PORT datac (1133:1133:1133) (1174:1174:1174)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (1016:1016:1016)) + (PORT datab (1031:1031:1031) (1053:1053:1053)) + (PORT datac (181:181:181) (219:219:219)) + (PORT datad (652:652:652) (692:692:692)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (616:616:616)) + (PORT datab (672:672:672) (701:701:701)) + (PORT datac (510:510:510) (522:522:522)) + (PORT datad (840:840:840) (853:853:853)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (256:256:256)) + (PORT datab (884:884:884) (911:911:911)) + (PORT datac (866:866:866) (930:930:930)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT dataa (2169:2169:2169) (2322:2322:2322)) + (PORT datac (1461:1461:1461) (1534:1534:1534)) + (PORT datad (2260:2260:2260) (2326:2326:2326)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (DELAY + (ABSOLUTE + (PORT datab (924:924:924) (1011:1011:1011)) + (PORT datac (1545:1545:1545) (1672:1672:1672)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (747:747:747)) + (PORT datab (868:868:868) (890:890:890)) + (PORT datac (1285:1285:1285) (1378:1378:1378)) + (PORT datad (896:896:896) (936:936:936)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1484:1484:1484) (1547:1547:1547)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (988:988:988) (1034:1034:1034)) + (PORT datad (1031:1031:1031) (1081:1081:1081)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (286:286:286)) + (PORT datab (373:373:373) (398:398:398)) + (PORT datac (599:599:599) (641:641:641)) + (PORT datad (200:200:200) (235:235:235)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1623:1623:1623) (1713:1713:1713)) + (PORT datab (1529:1529:1529) (1662:1662:1662)) + (PORT datac (1705:1705:1705) (1826:1826:1826)) + (PORT datad (1447:1447:1447) (1495:1495:1495)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1779:1779:1779) (1826:1826:1826)) + (PORT datab (681:681:681) (732:732:732)) + (PORT datac (551:551:551) (571:571:571)) + (PORT datad (1134:1134:1134) (1177:1177:1177)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (759:759:759)) + (PORT datab (1001:1001:1001) (1109:1109:1109)) + (PORT datac (192:192:192) (226:226:226)) + (PORT datad (1242:1242:1242) (1328:1328:1328)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (630:630:630)) + (PORT datab (875:875:875) (920:920:920)) + (PORT datac (338:338:338) (364:364:364)) + (PORT datad (685:685:685) (739:739:739)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (707:707:707)) + (PORT datab (950:950:950) (1008:1008:1008)) + (PORT datac (590:590:590) (605:605:605)) + (PORT datad (654:654:654) (692:692:692)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1171:1171:1171)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (566:566:566) (595:595:595)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (494:494:494)) + (PORT datab (1299:1299:1299) (1396:1396:1396)) + (PORT datac (680:680:680) (764:764:764)) + (PORT datad (1300:1300:1300) (1391:1391:1391)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1626:1626:1626)) + (PORT datab (906:906:906) (950:950:950)) + (PORT datac (1263:1263:1263) (1320:1320:1320)) + (PORT datad (1666:1666:1666) (1688:1688:1688)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (401:401:401)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (653:653:653) (714:714:714)) + (PORT datad (1668:1668:1668) (1689:1689:1689)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1373:1373:1373)) + (PORT datab (1184:1184:1184) (1235:1235:1235)) + (PORT datac (1139:1139:1139) (1197:1197:1197)) + (PORT datad (1323:1323:1323) (1433:1433:1433)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (940:940:940)) + (PORT datab (380:380:380) (410:410:410)) + (PORT datac (654:654:654) (698:698:698)) + (PORT datad (1204:1204:1204) (1277:1277:1277)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1116:1116:1116)) + (PORT datab (917:917:917) (963:963:963)) + (PORT datac (1010:1010:1010) (1060:1060:1060)) + (PORT datad (924:924:924) (954:954:954)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (251:251:251)) + (PORT datab (964:964:964) (1061:1061:1061)) + (PORT datac (844:844:844) (886:886:886)) + (PORT datad (905:905:905) (950:950:950)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1084:1084:1084)) + (PORT datab (1205:1205:1205) (1272:1272:1272)) + (PORT datac (1579:1579:1579) (1687:1687:1687)) + (PORT datad (1138:1138:1138) (1195:1195:1195)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (653:653:653)) + (PORT datab (2073:2073:2073) (2252:2252:2252)) + (PORT datac (861:861:861) (894:894:894)) + (PORT datad (1257:1257:1257) (1349:1349:1349)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (961:961:961)) + (PORT datab (916:916:916) (955:955:955)) + (PORT datac (1131:1131:1131) (1156:1156:1156)) + (PORT datad (926:926:926) (955:955:955)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1147:1147:1147)) + (PORT datab (1588:1588:1588) (1723:1723:1723)) + (PORT datac (637:637:637) (656:656:656)) + (PORT datad (1691:1691:1691) (1790:1790:1790)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2337:2337:2337) (2490:2490:2490)) + (PORT datab (1668:1668:1668) (1785:1785:1785)) + (PORT datac (905:905:905) (956:956:956)) + (PORT datad (672:672:672) (720:720:720)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1130:1130:1130)) + (PORT datad (1542:1542:1542) (1657:1657:1657)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1373:1373:1373)) + (PORT datab (656:656:656) (703:703:703)) + (PORT datac (1351:1351:1351) (1409:1409:1409)) + (PORT datad (881:881:881) (908:908:908)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1148:1148:1148)) + (PORT datab (1720:1720:1720) (1825:1825:1825)) + (PORT datac (1557:1557:1557) (1685:1685:1685)) + (PORT datad (1001:1001:1001) (1102:1102:1102)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1478:1478:1478)) + (PORT datab (827:827:827) (854:854:854)) + (PORT datac (1113:1113:1113) (1149:1149:1149)) + (PORT datad (635:635:635) (687:687:687)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) + (DELAY + (ABSOLUTE + (PORT datab (1169:1169:1169) (1230:1230:1230)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (851:851:851) (919:919:919)) + (PORT datac (194:194:194) (241:241:241)) + (PORT datad (673:673:673) (732:732:732)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (1052:1052:1052)) + (PORT datab (936:936:936) (1006:1006:1006)) + (PORT datac (1407:1407:1407) (1449:1449:1449)) + (PORT datad (537:537:537) (548:548:548)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (620:620:620)) + (PORT datab (867:867:867) (902:902:902)) + (PORT datac (1366:1366:1366) (1470:1470:1470)) + (PORT datad (1496:1496:1496) (1606:1606:1606)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (985:985:985)) + (PORT datab (916:916:916) (957:957:957)) + (PORT datac (915:915:915) (950:950:950)) + (PORT datad (1540:1540:1540) (1625:1625:1625)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1214:1214:1214)) + (PORT datab (649:649:649) (694:694:694)) + (PORT datac (902:902:902) (950:950:950)) + (PORT datad (338:338:338) (355:355:355)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (DELAY + (ABSOLUTE + (PORT datab (1511:1511:1511) (1618:1618:1618)) + (PORT datac (1726:1726:1726) (1837:1837:1837)) + (PORT datad (1072:1072:1072) (1082:1082:1082)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (734:734:734)) + (PORT datab (1163:1163:1163) (1210:1210:1210)) + (PORT datac (852:852:852) (881:881:881)) + (PORT datad (1173:1173:1173) (1254:1254:1254)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (1001:1001:1001)) + (PORT datab (946:946:946) (986:986:986)) + (PORT datac (632:632:632) (678:678:678)) + (PORT datad (1150:1150:1150) (1195:1195:1195)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT datab (865:865:865) (918:918:918)) + (PORT datac (179:179:179) (213:213:213)) + (PORT datad (851:851:851) (896:896:896)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1077:1077:1077)) + (PORT datab (1450:1450:1450) (1521:1521:1521)) + (PORT datac (1291:1291:1291) (1321:1321:1321)) + (PORT datad (856:856:856) (875:875:875)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1685:1685:1685) (1750:1750:1750)) + (PORT datab (1695:1695:1695) (1779:1779:1779)) + (PORT datac (1479:1479:1479) (1576:1576:1576)) + (PORT datad (855:855:855) (874:874:874)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (1444:1444:1444) (1505:1505:1505)) + (PORT datab (1695:1695:1695) (1774:1774:1774)) + (PORT datac (1653:1653:1653) (1704:1704:1704)) + (PORT datad (1165:1165:1165) (1208:1208:1208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (902:902:902)) + (PORT datab (612:612:612) (626:626:626)) + (PORT datac (1486:1486:1486) (1525:1525:1525)) + (PORT datad (572:572:572) (587:587:587)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (953:953:953)) + (PORT datab (920:920:920) (939:939:939)) + (PORT datac (888:888:888) (933:933:933)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) + (DELAY + (ABSOLUTE + (PORT dataa (1805:1805:1805) (1846:1846:1846)) + (PORT datab (1718:1718:1718) (1824:1824:1824)) + (PORT datac (1560:1560:1560) (1684:1684:1684)) + (PORT datad (1003:1003:1003) (1103:1103:1103)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1617:1617:1617) (1736:1736:1736)) + (PORT datac (2516:2516:2516) (2621:2621:2621)) + (PORT datad (1496:1496:1496) (1610:1610:1610)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1204:1204:1204)) + (PORT datab (1153:1153:1153) (1208:1208:1208)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (861:861:861) (880:880:880)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (684:684:684) (709:709:709)) + (PORT datac (378:378:378) (413:413:413)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (494:494:494)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (807:807:807) (827:827:827)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (413:413:413)) + (PORT datab (907:907:907) (914:914:914)) + (PORT datac (619:619:619) (656:656:656)) + (PORT datad (1190:1190:1190) (1243:1243:1243)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1250:1250:1250) (1344:1344:1344)) + (PORT datab (1673:1673:1673) (1790:1790:1790)) + (PORT datac (909:909:909) (958:958:958)) + (PORT datad (940:940:940) (995:995:995)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1458:1458:1458) (1556:1556:1556)) + (PORT datab (1664:1664:1664) (1735:1735:1735)) + (PORT datac (847:847:847) (861:861:861)) + (PORT datad (654:654:654) (683:683:683)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1407:1407:1407) (1552:1552:1552)) + (PORT datab (901:901:901) (929:929:929)) + (PORT datad (2354:2354:2354) (2501:2501:2501)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1575:1575:1575) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1200:1200:1200)) + (PORT datab (1193:1193:1193) (1243:1243:1243)) + (PORT datad (1206:1206:1206) (1288:1288:1288)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1553:1553:1553)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1593:1593:1593) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (961:961:961)) + (PORT datab (2051:2051:2051) (2083:2083:2083)) + (PORT datac (805:805:805) (817:817:817)) + (PORT datad (336:336:336) (360:360:360)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (998:998:998)) + (PORT datab (1733:1733:1733) (1770:1770:1770)) + (PORT datac (1229:1229:1229) (1327:1327:1327)) + (PORT datad (1151:1151:1151) (1194:1194:1194)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (785:785:785)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1230:1230:1230) (1329:1329:1329)) + (PORT datad (1542:1542:1542) (1627:1627:1627)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1298:1298:1298)) + (PORT datab (1276:1276:1276) (1367:1367:1367)) + (PORT datac (1156:1156:1156) (1195:1195:1195)) + (PORT datad (711:711:711) (777:777:777)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (656:656:656)) + (PORT datab (603:603:603) (615:615:615)) + (PORT datac (902:902:902) (950:950:950)) + (PORT datad (1750:1750:1750) (1806:1806:1806)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (985:985:985)) + (PORT datab (359:359:359) (388:388:388)) + (PORT datac (1182:1182:1182) (1242:1242:1242)) + (PORT datad (2028:2028:2028) (2153:2153:2153)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (372:372:372)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (878:878:878) (913:913:913)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1069:1069:1069)) + (PORT datab (913:913:913) (1002:1002:1002)) + (PORT datac (1084:1084:1084) (1074:1074:1074)) + (PORT datad (1060:1060:1060) (1062:1062:1062)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1344:1344:1344) (1441:1441:1441)) + (PORT datab (898:898:898) (946:946:946)) + (PORT datac (669:669:669) (692:692:692)) + (PORT datad (1162:1162:1162) (1228:1228:1228)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2046:2046:2046) (2143:2143:2143)) + (PORT datac (1652:1652:1652) (1690:1690:1690)) + (PORT datad (1726:1726:1726) (1766:1766:1766)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1068:1068:1068)) + (PORT datab (1320:1320:1320) (1358:1358:1358)) + (PORT datac (1320:1320:1320) (1375:1375:1375)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT datab (667:667:667) (677:677:677)) + (PORT datac (650:650:650) (674:674:674)) + (PORT datad (899:899:899) (937:937:937)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (691:691:691)) + (PORT datab (711:711:711) (745:745:745)) + (PORT datac (675:675:675) (730:730:730)) + (PORT datad (832:832:832) (843:843:843)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (889:889:889)) + (PORT datac (1915:1915:1915) (1982:1982:1982)) + (PORT datad (200:200:200) (239:239:239)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (677:677:677)) + (PORT datab (864:864:864) (932:932:932)) + (PORT datac (1099:1099:1099) (1123:1123:1123)) + (PORT datad (830:830:830) (852:852:852)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1166:1166:1166)) + (PORT datab (1000:1000:1000) (1115:1115:1115)) + (PORT datac (1411:1411:1411) (1477:1477:1477)) + (PORT datad (203:203:203) (239:239:239)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1061:1061:1061) (1166:1166:1166)) + (PORT datab (1976:1976:1976) (2065:2065:2065)) + (PORT datac (1151:1151:1151) (1205:1205:1205)) + (PORT datad (941:941:941) (1012:1012:1012)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (2603:2603:2603) (2772:2772:2772)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (1032:1032:1032)) + (PORT datac (1109:1109:1109) (1164:1164:1164)) + (PORT datad (1148:1148:1148) (1191:1191:1191)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1040:1040:1040)) + (PORT datab (845:845:845) (850:850:850)) + (PORT datac (2021:2021:2021) (2050:2050:2050)) + (PORT datad (1388:1388:1388) (1426:1426:1426)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1582:1582:1582) (1703:1703:1703)) + (PORT datab (917:917:917) (971:971:971)) + (PORT datac (929:929:929) (1008:1008:1008)) + (PORT datad (1530:1530:1530) (1630:1630:1630)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (674:674:674)) + (PORT datab (871:871:871) (890:890:890)) + (PORT datac (598:598:598) (661:661:661)) + (PORT datad (809:809:809) (825:825:825)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1239:1239:1239)) + (PORT datac (1383:1383:1383) (1458:1458:1458)) + (PORT datad (2108:2108:2108) (2253:2253:2253)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (968:968:968)) + (PORT datab (1559:1559:1559) (1655:1655:1655)) + (PORT datac (211:211:211) (252:252:252)) + (PORT datad (618:618:618) (634:634:634)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1375:1375:1375) (1445:1445:1445)) + (PORT datab (619:619:619) (640:640:640)) + (PORT datac (776:776:776) (799:799:799)) + (PORT datad (597:597:597) (614:614:614)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1683:1683:1683) (1739:1739:1739)) + (PORT datab (1115:1115:1115) (1125:1125:1125)) + (PORT datac (1054:1054:1054) (1110:1110:1110)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1324:1324:1324) (1411:1411:1411)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (592:592:592) (627:627:627)) + (PORT datad (1466:1466:1466) (1538:1538:1538)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (604:604:604)) + (PORT datab (614:614:614) (675:675:675)) + (PORT datac (611:611:611) (636:636:636)) + (PORT datad (573:573:573) (586:586:586)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (2248:2248:2248) (2386:2386:2386)) + (PORT datab (260:260:260) (341:341:341)) + (PORT datac (1161:1161:1161) (1218:1218:1218)) + (PORT datad (235:235:235) (303:303:303)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (874:874:874) (909:909:909)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (208:208:208) (250:250:250)) + (PORT datad (663:663:663) (707:707:707)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (266:266:266)) + (PORT datab (1027:1027:1027) (1068:1068:1068)) + (PORT datac (332:332:332) (358:358:358)) + (PORT datad (688:688:688) (740:740:740)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1247:1247:1247)) + (PORT datac (887:887:887) (944:944:944)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) + (DELAY + (ABSOLUTE + (PORT datac (663:663:663) (747:747:747)) + (PORT datad (890:890:890) (915:915:915)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1435:1435:1435) (1516:1516:1516)) + (PORT datab (619:619:619) (646:646:646)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (1126:1126:1126) (1172:1172:1172)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~47) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (640:640:640)) + (PORT datab (648:648:648) (672:672:672)) + (PORT datac (891:891:891) (929:929:929)) + (PORT datad (873:873:873) (908:908:908)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (385:385:385)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (616:616:616) (658:658:658)) + (PORT datad (1046:1046:1046) (1069:1069:1069)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (2048:2048:2048) (2143:2143:2143)) + (PORT datac (1652:1652:1652) (1688:1688:1688)) + (PORT datad (1726:1726:1726) (1766:1766:1766)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1331:1331:1331) (1424:1424:1424)) + (PORT datab (1098:1098:1098) (1141:1141:1141)) + (PORT datac (923:923:923) (945:945:945)) + (PORT datad (569:569:569) (578:578:578)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (278:278:278)) + (PORT datab (229:229:229) (272:272:272)) + (PORT datac (1186:1186:1186) (1234:1234:1234)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (855:855:855)) + (PORT datab (1257:1257:1257) (1326:1326:1326)) + (PORT datac (1798:1798:1798) (1932:1932:1932)) + (PORT datad (2112:2112:2112) (2257:2257:2257)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (632:632:632) (652:652:652)) + (PORT datac (595:595:595) (618:618:618)) + (PORT datad (847:847:847) (860:860:860)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1484:1484:1484)) + (PORT datab (742:742:742) (806:806:806)) + (PORT datac (873:873:873) (902:902:902)) + (PORT datad (887:887:887) (943:943:943)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (916:916:916)) + (PORT datab (683:683:683) (749:749:749)) + (PORT datac (971:971:971) (1032:1032:1032)) + (PORT datad (1783:1783:1783) (1858:1858:1858)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1298:1298:1298) (1401:1401:1401)) + (PORT datab (881:881:881) (925:925:925)) + (PORT datac (637:637:637) (657:657:657)) + (PORT datad (1737:1737:1737) (1788:1788:1788)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1486:1486:1486)) + (PORT datab (643:643:643) (709:709:709)) + (PORT datac (874:874:874) (901:901:901)) + (PORT datad (380:380:380) (406:406:406)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (953:953:953)) + (PORT datab (685:685:685) (750:750:750)) + (PORT datac (967:967:967) (1028:1028:1028)) + (PORT datad (629:629:629) (639:639:639)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1456:1456:1456) (1534:1534:1534)) + (PORT datab (926:926:926) (971:971:971)) + (PORT datac (191:191:191) (224:224:224)) + (PORT datad (1396:1396:1396) (1442:1442:1442)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1587:1587:1587) (1654:1654:1654)) + (PORT datab (1578:1578:1578) (1625:1625:1625)) + (PORT datac (1000:1000:1000) (1045:1045:1045)) + (PORT datad (1562:1562:1562) (1620:1620:1620)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1452:1452:1452) (1526:1526:1526)) + (PORT datab (898:898:898) (959:959:959)) + (PORT datac (823:823:823) (876:876:876)) + (PORT datad (584:584:584) (613:613:613)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1449:1449:1449) (1523:1523:1523)) + (PORT datab (899:899:899) (962:962:962)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (914:914:914) (977:977:977)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (613:613:613)) + (PORT datab (864:864:864) (919:919:919)) + (PORT datac (792:792:792) (849:849:849)) + (PORT datad (781:781:781) (835:835:835)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (665:665:665)) + (PORT datab (238:238:238) (284:284:284)) + (PORT datac (1314:1314:1314) (1404:1404:1404)) + (PORT datad (2218:2218:2218) (2338:2338:2338)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1788:1788:1788) (1938:1938:1938)) + (PORT datab (1645:1645:1645) (1766:1766:1766)) + (PORT datac (1304:1304:1304) (1398:1398:1398)) + (PORT datad (2565:2565:2565) (2702:2702:2702)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1317:1317:1317)) + (PORT datab (870:870:870) (893:893:893)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (588:588:588) (606:606:606)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1443:1443:1443) (1548:1548:1548)) + (PORT datab (263:263:263) (309:309:309)) + (PORT datac (1197:1197:1197) (1255:1255:1255)) + (PORT datad (842:842:842) (854:854:854)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~2) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (910:910:910)) + (PORT datab (891:891:891) (912:912:912)) + (PORT datac (859:859:859) (877:877:877)) + (PORT datad (902:902:902) (978:978:978)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (921:921:921)) + (PORT datab (937:937:937) (1012:1012:1012)) + (PORT datac (195:195:195) (239:239:239)) + (PORT datad (1152:1152:1152) (1199:1199:1199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1470:1470:1470) (1476:1476:1476)) + (PORT datab (1497:1497:1497) (1569:1569:1569)) + (PORT datac (1102:1102:1102) (1120:1120:1120)) + (PORT datad (400:400:400) (436:436:436)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (906:906:906)) + (PORT datab (893:893:893) (913:913:913)) + (PORT datac (861:861:861) (879:879:879)) + (PORT datad (904:904:904) (979:979:979)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (805:805:805)) + (PORT datab (775:775:775) (880:880:880)) + (PORT datad (1178:1178:1178) (1197:1197:1197)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (619:619:619)) + (PORT datab (1166:1166:1166) (1207:1207:1207)) + (PORT datac (854:854:854) (905:905:905)) + (PORT datad (902:902:902) (956:956:956)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1440:1440:1440) (1550:1550:1550)) + (PORT datab (866:866:866) (895:895:895)) + (PORT datac (1284:1284:1284) (1336:1336:1336)) + (PORT datad (1607:1607:1607) (1729:1729:1729)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1494:1494:1494) (1601:1601:1601)) + (PORT datab (1439:1439:1439) (1451:1451:1451)) + (PORT datac (1444:1444:1444) (1551:1551:1551)) + (PORT datad (402:402:402) (439:439:439)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1017:1017:1017) (1057:1057:1057)) + (PORT datac (793:793:793) (802:802:802)) + (PORT datad (1022:1022:1022) (1048:1048:1048)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (397:397:397) (440:440:440)) + (PORT datac (980:980:980) (992:992:992)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (373:373:373)) + (PORT datab (198:198:198) (235:235:235)) + (PORT datac (586:586:586) (613:613:613)) + (PORT datad (1522:1522:1522) (1622:1622:1622)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1222:1222:1222) (1272:1272:1272)) + (PORT datab (1222:1222:1222) (1263:1263:1263)) + (PORT datac (892:892:892) (922:922:922)) + (PORT datad (1507:1507:1507) (1624:1624:1624)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (886:886:886)) + (PORT datab (227:227:227) (274:274:274)) + (PORT datac (1160:1160:1160) (1222:1222:1222)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1685:1685:1685) (1744:1744:1744)) + (PORT datab (1695:1695:1695) (1779:1779:1779)) + (PORT datac (1482:1482:1482) (1577:1577:1577)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (1034:1034:1034)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (1192:1192:1192) (1254:1254:1254)) + (PORT datad (882:882:882) (917:917:917)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (1193:1193:1193) (1230:1230:1230)) + (PORT datac (1251:1251:1251) (1308:1308:1308)) + (PORT datad (780:780:780) (799:799:799)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (976:976:976)) + (PORT datab (940:940:940) (1022:1022:1022)) + (PORT datac (1140:1140:1140) (1178:1178:1178)) + (PORT datad (375:375:375) (417:417:417)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1284:1284:1284) (1345:1345:1345)) + (PORT datab (1189:1189:1189) (1228:1228:1228)) + (PORT datac (1135:1135:1135) (1177:1177:1177)) + (PORT datad (780:780:780) (799:799:799)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (343:343:343)) + (PORT datab (224:224:224) (272:272:272)) + (PORT datac (342:342:342) (371:371:371)) + (PORT datad (1219:1219:1219) (1301:1301:1301)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1203:1203:1203)) + (PORT datab (1191:1191:1191) (1242:1242:1242)) + (PORT datad (1220:1220:1220) (1299:1299:1299)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1553:1553:1553)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1593:1593:1593) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (405:405:405)) + (PORT datab (224:224:224) (269:269:269)) + (PORT datac (222:222:222) (302:302:302)) + (PORT datad (1202:1202:1202) (1285:1285:1285)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (586:586:586)) + (PORT datab (1028:1028:1028) (1073:1073:1073)) + (PORT datac (338:338:338) (364:364:364)) + (PORT datad (686:686:686) (739:739:739)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (687:687:687)) + (PORT datab (1720:1720:1720) (1802:1802:1802)) + (PORT datad (879:879:879) (876:876:876)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (2640:2640:2640) (2740:2740:2740)) + (PORT datab (1718:1718:1718) (1823:1823:1823)) + (PORT datac (1017:1017:1017) (1049:1049:1049)) + (PORT datad (1534:1534:1534) (1564:1564:1564)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (277:277:277)) + (PORT datab (894:894:894) (923:923:923)) + (PORT datac (1486:1486:1486) (1564:1564:1564)) + (PORT datad (1217:1217:1217) (1256:1256:1256)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1038:1038:1038)) + (PORT datab (204:204:204) (246:246:246)) + (PORT datac (946:946:946) (1014:1014:1014)) + (PORT datad (209:209:209) (240:240:240)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla30npla13M5T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (1011:1011:1011)) + (PORT datab (229:229:229) (278:278:278)) + (PORT datac (1408:1408:1408) (1479:1479:1479)) + (PORT datad (1499:1499:1499) (1550:1550:1550)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1181:1181:1181)) + (PORT datab (1549:1549:1549) (1573:1573:1573)) + (PORT datac (592:592:592) (626:626:626)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (391:391:391)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (178:178:178) (207:207:207)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (934:934:934)) + (PORT datab (654:654:654) (689:689:689)) + (PORT datac (1104:1104:1104) (1117:1117:1117)) + (PORT datad (766:766:766) (786:786:786)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1711:1711:1711)) + (PORT datab (1531:1531:1531) (1582:1582:1582)) + (PORT datac (1704:1704:1704) (1824:1824:1824)) + (PORT datad (1073:1073:1073) (1075:1075:1075)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (2002:2002:2002) (2195:2195:2195)) + (PORT datab (1455:1455:1455) (1549:1549:1549)) + (PORT datac (1508:1508:1508) (1592:1592:1592)) + (PORT datad (1918:1918:1918) (1978:1978:1978)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (965:965:965)) + (PORT datab (871:871:871) (909:909:909)) + (PORT datac (803:803:803) (870:870:870)) + (PORT datad (1526:1526:1526) (1620:1620:1620)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (664:664:664)) + (PORT datab (678:678:678) (735:735:735)) + (PORT datac (919:919:919) (966:966:966)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (728:728:728)) + (PORT datab (1191:1191:1191) (1244:1244:1244)) + (PORT datac (669:669:669) (694:694:694)) + (PORT datad (1304:1304:1304) (1397:1397:1397)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1369:1369:1369) (1431:1431:1431)) + (PORT datab (643:643:643) (680:680:680)) + (PORT datac (1322:1322:1322) (1362:1362:1362)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1190:1190:1190)) + (PORT datab (1820:1820:1820) (1897:1897:1897)) + (PORT datad (966:966:966) (1074:1074:1074)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (932:932:932)) + (PORT datab (680:680:680) (741:741:741)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (2206:2206:2206) (2251:2251:2251)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1348:1348:1348)) + (PORT datab (1492:1492:1492) (1598:1598:1598)) + (PORT datac (1226:1226:1226) (1277:1277:1277)) + (PORT datad (1231:1231:1231) (1263:1263:1263)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1906:1906:1906) (2000:2000:2000)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (869:869:869) (926:926:926)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (635:635:635)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (898:898:898) (931:931:931)) + (PORT datad (816:816:816) (860:860:860)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (881:881:881)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (561:561:561) (575:575:575)) + (PORT datad (613:613:613) (668:668:668)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (889:889:889)) + (PORT datac (208:208:208) (251:251:251)) + (PORT datad (202:202:202) (238:238:238)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1368:1368:1368)) + (PORT datab (614:614:614) (640:640:640)) + (PORT datac (842:842:842) (872:872:872)) + (PORT datad (607:607:607) (635:635:635)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1417:1417:1417) (1464:1464:1464)) + (PORT datab (910:910:910) (954:954:954)) + (PORT datac (1136:1136:1136) (1177:1177:1177)) + (PORT datad (1173:1173:1173) (1255:1255:1255)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1757:1757:1757) (1831:1831:1831)) + (PORT datab (836:836:836) (849:849:849)) + (PORT datac (2018:2018:2018) (2050:2050:2050)) + (PORT datad (2040:2040:2040) (2102:2102:2102)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~40) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (961:961:961)) + (PORT datab (1098:1098:1098) (1150:1150:1150)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (566:566:566)) + (PORT datab (662:662:662) (694:694:694)) + (PORT datac (2000:2000:2000) (2031:2031:2031)) + (PORT datad (538:538:538) (549:549:549)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (852:852:852) (924:924:924)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (855:855:855) (863:863:863)) + (PORT datac (568:568:568) (591:591:591)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (1191:1191:1191) (1227:1227:1227)) + (PORT datab (1050:1050:1050) (1057:1057:1057)) + (PORT datac (1185:1185:1185) (1207:1207:1207)) + (PORT datad (1343:1343:1343) (1388:1388:1388)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (338:338:338)) + (PORT datab (223:223:223) (268:268:268)) + (PORT datac (337:337:337) (367:367:367)) + (PORT datad (1203:1203:1203) (1285:1285:1285)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT datab (1384:1384:1384) (1432:1432:1432)) + (PORT datac (1179:1179:1179) (1200:1200:1200)) + (PORT datad (594:594:594) (610:610:610)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) + (DELAY + (ABSOLUTE + (PORT datac (900:900:900) (943:943:943)) + (PORT datad (1328:1328:1328) (1383:1383:1383)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1261:1261:1261)) + (PORT datab (223:223:223) (270:270:270)) + (PORT datac (1141:1141:1141) (1178:1178:1178)) + (PORT datad (671:671:671) (721:721:721)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (769:769:769)) + (PORT datab (1469:1469:1469) (1552:1552:1552)) + (PORT datac (1145:1145:1145) (1180:1180:1180)) + (PORT datad (199:199:199) (235:235:235)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (766:766:766)) + (PORT datab (1471:1471:1471) (1557:1557:1557)) + (PORT datac (1138:1138:1138) (1176:1176:1176)) + (PORT datad (196:196:196) (232:232:232)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1346:1346:1346) (1411:1411:1411)) + (PORT datab (869:869:869) (903:903:903)) + (PORT datac (1807:1807:1807) (1896:1896:1896)) + (PORT datad (1570:1570:1570) (1608:1608:1608)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datad (868:868:868) (885:885:885)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1092:1092:1092)) + (PORT datab (657:657:657) (681:681:681)) + (PORT datac (908:908:908) (975:975:975)) + (PORT datad (1438:1438:1438) (1536:1536:1536)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1154:1154:1154)) + (PORT datab (701:701:701) (782:782:782)) + (PORT datac (1444:1444:1444) (1551:1551:1551)) + (PORT datad (1465:1465:1465) (1554:1554:1554)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (634:634:634)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (622:622:622) (651:651:651)) + (PORT datad (1082:1082:1082) (1107:1107:1107)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (419:419:419)) + (PORT datab (1179:1179:1179) (1229:1229:1229)) + (PORT datac (351:351:351) (380:380:380)) + (PORT datad (1087:1087:1087) (1108:1108:1108)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1246:1246:1246) (1335:1335:1335)) + (PORT datab (1577:1577:1577) (1714:1714:1714)) + (PORT datac (2188:2188:2188) (2312:2312:2312)) + (PORT datad (1069:1069:1069) (1164:1164:1164)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (1012:1012:1012)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1253:1253:1253) (1293:1293:1293)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (660:660:660)) + (PORT datac (659:659:659) (688:688:688)) + (PORT datad (550:550:550) (559:559:559)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1144:1144:1144) (1180:1180:1180)) + (PORT datab (218:218:218) (265:265:265)) + (PORT datac (1135:1135:1135) (1168:1168:1168)) + (PORT datad (665:665:665) (712:712:712)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~2) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (938:938:938)) + (PORT datab (900:900:900) (913:913:913)) + (PORT datac (920:920:920) (1008:1008:1008)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (751:751:751)) + (PORT datab (1166:1166:1166) (1198:1198:1198)) + (PORT datad (948:948:948) (968:968:968)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1184:1184:1184)) + (PORT datab (248:248:248) (332:332:332)) + (PORT datac (1144:1144:1144) (1179:1179:1179)) + (PORT datad (672:672:672) (720:720:720)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (703:703:703)) + (PORT datab (1351:1351:1351) (1386:1386:1386)) + (PORT datad (908:908:908) (958:958:958)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1183:1183:1183)) + (PORT datab (250:250:250) (335:335:335)) + (PORT datac (1137:1137:1137) (1173:1173:1173)) + (PORT datad (664:664:664) (718:718:718)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (1721:1721:1721) (1780:1780:1780)) + (PORT datab (1170:1170:1170) (1223:1223:1223)) + (PORT datad (792:792:792) (797:797:797)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (761:761:761)) + (PORT datab (914:914:914) (975:975:975)) + (PORT datac (1817:1817:1817) (1896:1896:1896)) + (PORT datad (1153:1153:1153) (1178:1178:1178)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1482:1482:1482) (1581:1581:1581)) + (PORT datac (1016:1016:1016) (1055:1055:1055)) + (PORT datad (321:321:321) (344:344:344)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1428:1428:1428) (1487:1487:1487)) + (PORT datab (1168:1168:1168) (1215:1215:1215)) + (PORT datac (2035:2035:2035) (2124:2124:2124)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1200:1200:1200)) + (PORT datab (2031:2031:2031) (2127:2127:2127)) + (PORT datac (969:969:969) (1020:1020:1020)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (902:902:902)) + (PORT datab (1517:1517:1517) (1560:1560:1560)) + (PORT datac (1294:1294:1294) (1324:1324:1324)) + (PORT datad (862:862:862) (880:880:880)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (272:272:272)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (1544:1544:1544) (1653:1653:1653)) + (PORT datac (208:208:208) (246:246:246)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (620:620:620)) + (PORT datab (876:876:876) (893:893:893)) + (PORT datac (1384:1384:1384) (1444:1444:1444)) + (PORT datad (1947:1947:1947) (1977:1977:1977)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (266:266:266)) + (PORT datab (2017:2017:2017) (2075:2075:2075)) + (PORT datac (804:804:804) (827:827:827)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (740:740:740)) + (PORT datab (1445:1445:1445) (1514:1514:1514)) + (PORT datac (360:360:360) (389:389:389)) + (PORT datad (1121:1121:1121) (1177:1177:1177)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (277:277:277)) + (PORT datab (558:558:558) (578:578:578)) + (PORT datac (804:804:804) (818:818:818)) + (PORT datad (595:595:595) (633:633:633)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1170:1170:1170) (1229:1229:1229)) + (PORT datab (599:599:599) (614:614:614)) + (PORT datac (654:654:654) (698:698:698)) + (PORT datad (866:866:866) (893:893:893)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (692:692:692) (737:737:737)) + (PORT datab (1195:1195:1195) (1210:1210:1210)) + (PORT datac (1157:1157:1157) (1193:1193:1193)) + (PORT datad (590:590:590) (602:602:602)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (936:936:936)) + (PORT datab (1199:1199:1199) (1253:1253:1253)) + (PORT datac (889:889:889) (931:931:931)) + (PORT datad (630:630:630) (687:687:687)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (601:601:601)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (951:951:951)) + (PORT datab (1199:1199:1199) (1252:1252:1252)) + (PORT datac (361:361:361) (394:394:394)) + (PORT datad (1118:1118:1118) (1176:1176:1176)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1230:1230:1230)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1158:1158:1158) (1196:1196:1196)) + (PORT datad (863:863:863) (892:892:892)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (252:252:252)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (652:652:652) (697:697:697)) + (PORT datad (845:845:845) (894:894:894)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (637:637:637)) + (PORT datab (686:686:686) (707:707:707)) + (PORT datac (378:378:378) (410:410:410)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (607:607:607) (625:625:625)) + (PORT datac (530:530:530) (542:542:542)) + (PORT datad (838:838:838) (876:876:876)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (962:962:962)) + (PORT datab (1558:1558:1558) (1661:1661:1661)) + (PORT datac (1407:1407:1407) (1474:1474:1474)) + (PORT datad (200:200:200) (235:235:235)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (660:660:660)) + (PORT datab (965:965:965) (1060:1060:1060)) + (PORT datac (1732:1732:1732) (1835:1835:1835)) + (PORT datad (1150:1150:1150) (1179:1179:1179)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1102:1102:1102) (1150:1150:1150)) + (PORT datab (1473:1473:1473) (1583:1583:1583)) + (PORT datac (1614:1614:1614) (1681:1681:1681)) + (PORT datad (1173:1173:1173) (1219:1219:1219)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1405:1405:1405) (1418:1418:1418)) + (PORT datab (1241:1241:1241) (1276:1276:1276)) + (PORT datac (1251:1251:1251) (1275:1275:1275)) + (PORT datad (1260:1260:1260) (1298:1298:1298)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1121:1121:1121) (1151:1151:1151)) + (PORT datac (613:613:613) (636:636:636)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (284:284:284)) + (PORT datab (219:219:219) (256:256:256)) + (PORT datac (1148:1148:1148) (1190:1190:1190)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~35) + (DELAY + (ABSOLUTE + (PORT datab (2004:2004:2004) (2134:2134:2134)) + (PORT datac (1351:1351:1351) (1365:1365:1365)) + (PORT datad (859:859:859) (872:872:872)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (267:267:267)) + (PORT datab (910:910:910) (941:941:941)) + (PORT datac (621:621:621) (645:645:645)) + (PORT datad (924:924:924) (962:962:962)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1513:1513:1513) (1596:1596:1596)) + (PORT datab (1166:1166:1166) (1202:1202:1202)) + (PORT datac (1104:1104:1104) (1142:1142:1142)) + (PORT datad (548:548:548) (560:560:560)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (650:650:650)) + (PORT datab (234:234:234) (278:278:278)) + (PORT datac (1132:1132:1132) (1164:1164:1164)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1646:1646:1646) (1763:1763:1763)) + (PORT datab (1008:1008:1008) (1101:1101:1101)) + (PORT datac (1033:1033:1033) (1107:1107:1107)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1208:1208:1208)) + (PORT datab (1537:1537:1537) (1621:1621:1621)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (923:923:923)) + (PORT datab (570:570:570) (590:590:590)) + (PORT datac (603:603:603) (628:628:628)) + (PORT datad (595:595:595) (619:619:619)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1229:1229:1229) (1305:1305:1305)) + (PORT datab (1275:1275:1275) (1372:1372:1372)) + (PORT datac (1155:1155:1155) (1192:1192:1192)) + (PORT datad (709:709:709) (772:772:772)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (719:719:719)) + (PORT datab (1344:1344:1344) (1367:1367:1367)) + (PORT datac (1222:1222:1222) (1269:1269:1269)) + (PORT datad (1654:1654:1654) (1748:1748:1748)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1089:1089:1089)) + (PORT datab (887:887:887) (923:923:923)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (221:221:221) (249:249:249)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1035:1035:1035) (1133:1133:1133)) + (PORT datac (2185:2185:2185) (2272:2272:2272)) + (PORT datad (654:654:654) (711:711:711)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (782:782:782)) + (PORT datab (1135:1135:1135) (1159:1159:1159)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1153:1153:1153) (1186:1186:1186)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1016:1016:1016) (1112:1112:1112)) + (PORT datab (668:668:668) (685:685:685)) + (PORT datac (1012:1012:1012) (1113:1113:1113)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (933:933:933) (975:975:975)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (278:278:278) (366:366:366)) + (PORT datac (241:241:241) (319:319:319)) + (PORT datad (246:246:246) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (971:971:971)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (1095:1095:1095) (1116:1116:1116)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1192:1192:1192)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (650:650:650) (716:716:716)) + (PORT datad (966:966:966) (1077:1077:1077)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (2563:2563:2563) (2705:2705:2705)) + (PORT datab (1595:1595:1595) (1711:1711:1711)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (218:218:218) (258:258:258)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1067:1067:1067) (1148:1148:1148)) + (PORT datab (204:204:204) (245:245:245)) + (PORT datac (880:880:880) (911:911:911)) + (PORT datad (824:824:824) (834:834:834)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (931:931:931) (1002:1002:1002)) + (PORT datad (625:625:625) (662:662:662)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (663:663:663)) + (PORT datab (924:924:924) (986:986:986)) + (PORT datac (1079:1079:1079) (1113:1113:1113)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (951:951:951)) + (PORT datab (902:902:902) (933:933:933)) + (PORT datac (628:628:628) (672:672:672)) + (PORT datad (883:883:883) (909:909:909)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (1992:1992:1992) (2133:2133:2133)) + (PORT datab (907:907:907) (958:958:958)) + (PORT datac (224:224:224) (265:265:265)) + (PORT datad (1139:1139:1139) (1178:1178:1178)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (951:951:951)) + (PORT datab (917:917:917) (970:970:970)) + (PORT datac (879:879:879) (911:911:911)) + (PORT datad (593:593:593) (627:627:627)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (926:926:926)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1121:1121:1121)) + (PORT datab (894:894:894) (950:950:950)) + (PORT datac (601:601:601) (665:665:665)) + (PORT datad (855:855:855) (908:908:908)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2419:2419:2419) (2569:2569:2569)) + (PORT datab (1823:1823:1823) (1925:1925:1925)) + (PORT datac (1074:1074:1074) (1067:1067:1067)) + (PORT datad (1576:1576:1576) (1735:1735:1735)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (849:849:849)) + (PORT datab (912:912:912) (944:944:944)) + (PORT datac (835:835:835) (868:868:868)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2421:2421:2421) (2571:2571:2571)) + (PORT datab (2408:2408:2408) (2540:2540:2540)) + (PORT datac (1413:1413:1413) (1473:1473:1473)) + (PORT datad (1573:1573:1573) (1734:1734:1734)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (229:229:229) (272:272:272)) + (PORT datac (202:202:202) (241:241:241)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1310:1310:1310)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (832:832:832) (831:831:831)) + (PORT datad (872:872:872) (917:917:917)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (898:898:898)) + (PORT datab (237:237:237) (281:281:281)) + (PORT datac (619:619:619) (671:671:671)) + (PORT datad (1350:1350:1350) (1391:1391:1391)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1318:1318:1318)) + (PORT datab (1384:1384:1384) (1497:1497:1497)) + (PORT datac (857:857:857) (917:917:917)) + (PORT datad (831:831:831) (860:860:860)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2065:2065:2065) (2136:2136:2136)) + (PORT datab (2504:2504:2504) (2706:2706:2706)) + (PORT datac (2886:2886:2886) (3058:3058:3058)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (845:845:845) (894:894:894)) + (PORT datac (990:990:990) (1030:1030:1030)) + (PORT datad (1379:1379:1379) (1425:1425:1425)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (268:268:268)) + (PORT datac (663:663:663) (700:700:700)) + (PORT datad (1031:1031:1031) (1094:1094:1094)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1328:1328:1328) (1447:1447:1447)) + (PORT datac (1179:1179:1179) (1239:1239:1239)) + (PORT datad (2024:2024:2024) (2146:2146:2146)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1166:1166:1166)) + (PORT datab (226:226:226) (266:266:266)) + (PORT datac (604:604:604) (622:622:622)) + (PORT datad (1151:1151:1151) (1191:1191:1191)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1230:1230:1230)) + (PORT datac (1131:1131:1131) (1168:1168:1168)) + (PORT datad (957:957:957) (1017:1017:1017)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT datab (2109:2109:2109) (2224:2224:2224)) + (PORT datac (925:925:925) (983:983:983)) + (PORT datad (1982:1982:1982) (2072:2072:2072)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1250:1250:1250)) + (PORT datab (599:599:599) (617:617:617)) + (PORT datac (871:871:871) (913:913:913)) + (PORT datad (1143:1143:1143) (1193:1193:1193)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1120:1120:1120) (1154:1154:1154)) + (PORT datab (595:595:595) (609:609:609)) + (PORT datac (1115:1115:1115) (1174:1174:1174)) + (PORT datad (878:878:878) (910:910:910)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1801:1801:1801) (1843:1843:1843)) + (PORT datab (1573:1573:1573) (1608:1608:1608)) + (PORT datad (985:985:985) (1020:1020:1020)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (957:957:957)) + (PORT datab (1162:1162:1162) (1232:1232:1232)) + (PORT datac (1480:1480:1480) (1554:1554:1554)) + (PORT datad (1102:1102:1102) (1119:1119:1119)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (740:740:740)) + (PORT datab (913:913:913) (942:942:942)) + (PORT datac (618:618:618) (642:642:642)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1512:1512:1512) (1540:1540:1540)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (959:959:959)) + (PORT datab (887:887:887) (953:953:953)) + (PORT datac (185:185:185) (226:226:226)) + (PORT datad (885:885:885) (902:902:902)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1725:1725:1725) (1783:1783:1783)) + (PORT datad (330:330:330) (351:351:351)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1198:1198:1198) (1240:1240:1240)) + (PORT datab (835:835:835) (861:861:861)) + (PORT datac (841:841:841) (865:865:865)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1551:1551:1551) (1610:1610:1610)) + (PORT datab (1763:1763:1763) (1826:1826:1826)) + (PORT datac (2606:2606:2606) (2704:2704:2704)) + (PORT datad (1157:1157:1157) (1177:1177:1177)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (2641:2641:2641) (2744:2744:2744)) + (PORT datab (1587:1587:1587) (1722:1722:1722)) + (PORT datac (639:639:639) (659:659:659)) + (PORT datad (202:202:202) (233:233:233)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (638:638:638)) + (PORT datab (653:653:653) (683:683:683)) + (PORT datac (637:637:637) (684:684:684)) + (PORT datad (847:847:847) (906:906:906)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT datab (707:707:707) (739:739:739)) + (PORT datac (1055:1055:1055) (1068:1068:1068)) + (PORT datad (921:921:921) (956:956:956)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (401:401:401)) + (PORT datab (1114:1114:1114) (1146:1146:1146)) + (PORT datac (1038:1038:1038) (1080:1080:1080)) + (PORT datad (853:853:853) (854:854:854)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1748:1748:1748) (1768:1768:1768)) + (PORT datab (881:881:881) (907:907:907)) + (PORT datac (1501:1501:1501) (1630:1630:1630)) + (PORT datad (1129:1129:1129) (1199:1199:1199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1137:1137:1137) (1170:1170:1170)) + (PORT datab (1651:1651:1651) (1721:1721:1721)) + (PORT datac (1148:1148:1148) (1186:1186:1186)) + (PORT datad (212:212:212) (247:247:247)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (702:702:702)) + (PORT datab (1148:1148:1148) (1207:1207:1207)) + (PORT datac (1182:1182:1182) (1237:1237:1237)) + (PORT datad (969:969:969) (1043:1043:1043)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~1) + (DELAY + (ABSOLUTE + (PORT dataa (294:294:294) (365:365:365)) + (PORT datac (1702:1702:1702) (1757:1757:1757)) + (PORT datad (437:437:437) (482:482:482)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (685:685:685)) + (PORT datab (1154:1154:1154) (1208:1208:1208)) + (PORT datac (1484:1484:1484) (1544:1544:1544)) + (PORT datad (1270:1270:1270) (1331:1331:1331)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1443:1443:1443) (1501:1501:1501)) + (PORT datab (912:912:912) (961:961:961)) + (PORT datac (896:896:896) (925:925:925)) + (PORT datad (962:962:962) (988:988:988)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (897:897:897)) + (PORT datac (992:992:992) (1045:1045:1045)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1139:1139:1139)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1089:1089:1089) (1116:1116:1116)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (374:374:374)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (345:345:345) (385:385:385)) + (PORT datad (858:858:858) (866:866:866)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1408:1408:1408) (1444:1444:1444)) + (PORT datab (814:814:814) (844:844:844)) + (PORT datac (1711:1711:1711) (1730:1730:1730)) + (PORT datad (911:911:911) (949:949:949)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1097:1097:1097) (1124:1124:1124)) + (PORT datab (662:662:662) (693:693:693)) + (PORT datac (868:868:868) (892:892:892)) + (PORT datad (871:871:871) (914:914:914)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (275:275:275)) + (PORT datab (642:642:642) (663:663:663)) + (PORT datac (1367:1367:1367) (1431:1431:1431)) + (PORT datad (1132:1132:1132) (1158:1158:1158)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1764:1764:1764)) + (PORT datab (1009:1009:1009) (1098:1098:1098)) + (PORT datac (1939:1939:1939) (1965:1965:1965)) + (PORT datad (1664:1664:1664) (1726:1726:1726)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (264:264:264)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (646:646:646) (703:703:703)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (275:275:275)) + (PORT datab (645:645:645) (669:669:669)) + (PORT datac (199:199:199) (236:236:236)) + (PORT datad (1191:1191:1191) (1215:1215:1215)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (1028:1028:1028) (1084:1084:1084)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (593:593:593) (617:617:617)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (960:960:960)) + (PORT datab (1128:1128:1128) (1156:1156:1156)) + (PORT datac (886:886:886) (918:918:918)) + (PORT datad (1142:1142:1142) (1198:1198:1198)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) + (DELAY + (ABSOLUTE + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (593:593:593) (653:653:653)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (264:264:264)) + (PORT datac (557:557:557) (571:571:571)) + (PORT datad (812:812:812) (882:882:882)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1301:1301:1301) (1363:1363:1363)) + (PORT datab (670:670:670) (695:695:695)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (1179:1179:1179) (1216:1216:1216)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (585:585:585)) + (PORT datac (793:793:793) (849:849:849)) + (PORT datad (781:781:781) (835:835:835)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (932:932:932)) + (PORT datab (670:670:670) (713:713:713)) + (PORT datac (371:371:371) (406:406:406)) + (PORT datad (595:595:595) (643:643:643)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (677:677:677)) + (PORT datab (867:867:867) (880:880:880)) + (PORT datac (866:866:866) (892:892:892)) + (PORT datad (646:646:646) (680:680:680)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~46) + (DELAY + (ABSOLUTE + (PORT datab (821:821:821) (842:842:842)) + (PORT datac (201:201:201) (237:237:237)) + (PORT datad (1425:1425:1425) (1509:1509:1509)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (610:610:610)) + (PORT datab (926:926:926) (956:956:956)) + (PORT datac (586:586:586) (596:596:596)) + (PORT datad (582:582:582) (613:613:613)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1011:1011:1011)) + (PORT datab (1561:1561:1561) (1659:1659:1659)) + (PORT datac (842:842:842) (876:876:876)) + (PORT datad (371:371:371) (400:400:400)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (251:251:251)) + (PORT datab (340:340:340) (371:371:371)) + (PORT datac (211:211:211) (252:252:252)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (963:963:963)) + (PORT datac (857:857:857) (921:921:921)) + (PORT datad (828:828:828) (859:859:859)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (681:681:681)) + (PORT datab (1486:1486:1486) (1550:1550:1550)) + (PORT datac (820:820:820) (856:856:856)) + (PORT datad (815:815:815) (871:871:871)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (504:504:504)) + (PORT datab (946:946:946) (986:986:986)) + (PORT datac (374:374:374) (405:405:405)) + (PORT datad (1915:1915:1915) (2040:2040:2040)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) + (DELAY + (ABSOLUTE + (PORT dataa (2472:2472:2472) (2661:2661:2661)) + (PORT datab (554:554:554) (575:575:575)) + (PORT datac (892:892:892) (956:956:956)) + (PORT datad (1125:1125:1125) (1142:1142:1142)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (677:677:677)) + (PORT datab (581:581:581) (596:596:596)) + (PORT datac (785:785:785) (834:834:834)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (619:619:619)) + (PORT datab (876:876:876) (893:893:893)) + (PORT datac (1988:1988:1988) (2046:2046:2046)) + (PORT datad (596:596:596) (620:620:620)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1167:1167:1167)) + (PORT datab (1567:1567:1567) (1688:1688:1688)) + (PORT datac (635:635:635) (692:692:692)) + (PORT datad (604:604:604) (642:642:642)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (914:914:914)) + (PORT datab (562:562:562) (571:571:571)) + (PORT datac (611:611:611) (649:649:649)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (663:663:663)) + (PORT datab (925:925:925) (986:986:986)) + (PORT datac (532:532:532) (538:538:538)) + (PORT datad (873:873:873) (880:880:880)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (276:276:276)) + (PORT datab (643:643:643) (675:675:675)) + (PORT datac (842:842:842) (864:864:864)) + (PORT datad (344:344:344) (366:366:366)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT datab (1438:1438:1438) (1508:1508:1508)) + (PORT datac (915:915:915) (945:945:945)) + (PORT datad (819:819:819) (835:835:835)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (1330:1330:1330) (1334:1334:1334)) + (PORT datac (1375:1375:1375) (1393:1393:1393)) + (PORT datad (312:312:312) (330:330:330)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT datab (949:949:949) (999:999:999)) + (PORT datac (1439:1439:1439) (1498:1498:1498)) + (PORT datad (671:671:671) (702:702:702)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (974:974:974) (1028:1028:1028)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1880:1880:1880) (1905:1905:1905)) + (PORT datab (702:702:702) (730:730:730)) + (PORT datad (1198:1198:1198) (1238:1238:1238)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT datab (709:709:709) (737:737:737)) + (PORT datac (1057:1057:1057) (1070:1070:1070)) + (PORT datad (923:923:923) (954:954:954)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (738:738:738) (772:772:772)) + (PORT datac (609:609:609) (659:659:659)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT datac (1990:1990:1990) (2095:2095:2095)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (1548:1548:1548) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (1548:1548:1548) (1550:1550:1550)) + (PORT asdata (567:567:567) (646:646:646)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1548:1548:1548) (1550:1550:1550)) + (PORT asdata (569:569:569) (648:648:648)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE KEY\[0\]\~input) @@ -754,8 +11353,8 @@ (INSTANCE reset) (DELAY (ABSOLUTE - (PORT datac (1948:1948:1948) (1769:1769:1769)) - (PORT datad (820:820:820) (846:846:846)) + (PORT datac (1566:1566:1566) (1527:1527:1527)) + (PORT datad (531:531:531) (524:524:524)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -766,7 +11365,7 @@ (INSTANCE z80_\|resets_\|x1\~0) (DELAY (ABSOLUTE - (PORT datad (198:198:198) (224:224:224)) + (PORT datad (1474:1474:1474) (1549:1549:1549)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -776,7 +11375,7 @@ (INSTANCE z80_\|fpga_reset) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1542:1542:1542)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -799,9 +11398,9 @@ (INSTANCE z80_\|resets_\|x1) (DELAY (ABSOLUTE - (PORT clk (1550:1550:1550) (1550:1550:1550)) + (PORT clk (1523:1523:1523) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1547:1547:1547)) + (PORT clrn (1883:1883:1883) (1869:1869:1869)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -810,3451 +11409,16 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) - (DELAY - (ABSOLUTE - (PORT dataa (1134:1134:1134) (1226:1226:1226)) - (PORT datab (1058:1058:1058) (1141:1141:1141)) - (PORT datad (370:370:370) (433:433:433)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1559:1559:1559)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (597:597:597) (652:652:652)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE KEY\[1\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (481:481:481) (733:733:733)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT datac (3754:3754:3754) (3979:3979:3979)) - (PORT datad (1117:1117:1117) (1199:1199:1199)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|nmi_armed) - (DELAY - (ABSOLUTE - (PORT clk (1830:1830:1830) (1898:1898:1898)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (766:766:766) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1064:1064:1064) (1127:1127:1127)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT datac (1277:1277:1277) (1336:1336:1336)) - (PORT datad (1203:1203:1203) (1310:1310:1310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) - (DELAY - (ABSOLUTE - (PORT dataa (1302:1302:1302) (1430:1430:1430)) - (PORT datad (1381:1381:1381) (1462:1462:1462)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (969:969:969)) - (PORT datab (274:274:274) (360:360:360)) - (PORT datad (861:861:861) (911:911:911)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (983:983:983)) - (PORT datab (266:266:266) (349:349:349)) - (PORT datad (856:856:856) (905:905:905)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1395:1395:1395) (1486:1486:1486)) - (PORT datac (857:857:857) (940:940:940)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datac (1391:1391:1391) (1465:1465:1465)) - (PORT datad (1374:1374:1374) (1422:1422:1422)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datab (992:992:992) (1063:1063:1063)) - (PORT datac (966:966:966) (1044:1044:1044)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1204:1204:1204) (1276:1276:1276)) - (PORT datab (1359:1359:1359) (1348:1348:1348)) - (PORT datac (2035:2035:2035) (2074:2074:2074)) - (PORT datad (917:917:917) (942:942:942)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1411:1411:1411) (1462:1462:1462)) - (PORT datab (1304:1304:1304) (1363:1363:1363)) - (PORT datac (285:285:285) (382:382:382)) - (PORT datad (291:291:291) (380:380:380)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT datab (1399:1399:1399) (1485:1485:1485)) - (PORT datac (1720:1720:1720) (1815:1815:1815)) - (PORT datad (1704:1704:1704) (1780:1780:1780)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1424:1424:1424)) - (PORT datab (881:881:881) (912:912:912)) - (PORT datac (1062:1062:1062) (1123:1123:1123)) - (PORT datad (1135:1135:1135) (1189:1189:1189)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|M5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (966:966:966)) - (PORT datab (408:408:408) (478:478:478)) - (PORT datad (862:862:862) (914:914:914)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|M5) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1438:1438:1438) (1510:1510:1510)) - (PORT datac (1315:1315:1315) (1368:1368:1368)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) - (DELAY - (ABSOLUTE - (PORT datac (1157:1157:1157) (1248:1248:1248)) - (PORT datad (1780:1780:1780) (1841:1841:1841)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (920:920:920)) - (PORT datab (1641:1641:1641) (1693:1693:1693)) - (PORT datac (1019:1019:1019) (1067:1067:1067)) - (PORT datad (886:886:886) (909:909:909)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1392:1392:1392)) - (PORT datab (628:628:628) (668:668:668)) - (PORT datac (1462:1462:1462) (1490:1490:1490)) - (PORT datad (930:930:930) (960:960:960)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1436:1436:1436) (1512:1512:1512)) - (PORT datab (2151:2151:2151) (2203:2203:2203)) - (PORT datac (288:288:288) (387:387:387)) - (PORT datad (1377:1377:1377) (1417:1417:1417)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1528:1528:1528)) - (PORT datab (1294:1294:1294) (1345:1345:1345)) - (PORT datac (603:603:603) (638:638:638)) - (PORT datad (598:598:598) (638:638:638)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1502:1502:1502) (1523:1523:1523)) - (PORT datab (1184:1184:1184) (1251:1251:1251)) - (PORT datac (1601:1601:1601) (1677:1677:1677)) - (PORT datad (1668:1668:1668) (1705:1705:1705)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) - (DELAY - (ABSOLUTE - (PORT datab (1364:1364:1364) (1423:1423:1423)) - (PORT datac (1357:1357:1357) (1418:1418:1418)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (668:668:668)) - (PORT datab (620:620:620) (658:658:658)) - (PORT datac (696:696:696) (786:786:786)) - (PORT datad (936:936:936) (966:966:966)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1377:1377:1377) (1433:1433:1433)) - (PORT datab (1180:1180:1180) (1248:1248:1248)) - (PORT datac (1596:1596:1596) (1673:1673:1673)) - (PORT datad (1303:1303:1303) (1345:1345:1345)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1337:1337:1337) (1394:1394:1394)) - (PORT datab (635:635:635) (675:675:675)) - (PORT datac (1461:1461:1461) (1493:1493:1493)) - (PORT datad (932:932:932) (962:962:962)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT datab (1367:1367:1367) (1429:1429:1429)) - (PORT datac (1362:1362:1362) (1425:1425:1425)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (664:664:664) (699:699:699)) - (PORT datab (641:641:641) (680:680:680)) - (PORT datac (691:691:691) (782:782:782)) - (PORT datad (931:931:931) (959:959:959)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT datac (1124:1124:1124) (1202:1202:1202)) - (PORT datad (1175:1175:1175) (1289:1289:1289)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1115:1115:1115) (1188:1188:1188)) - (PORT datab (637:637:637) (663:663:663)) - (PORT datac (1557:1557:1557) (1548:1548:1548)) - (PORT datad (1147:1147:1147) (1165:1165:1165)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1101:1101:1101) (1131:1131:1131)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (3095:3095:3095) (3190:3190:3190)) - (PORT datab (2163:2163:2163) (2276:2276:2276)) - (PORT datac (964:964:964) (1028:1028:1028)) - (PORT datad (1038:1038:1038) (1065:1065:1065)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1193:1193:1193) (1283:1283:1283)) - (PORT datab (1159:1159:1159) (1236:1236:1236)) - (PORT datac (1168:1168:1168) (1278:1278:1278)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1406:1406:1406) (1460:1460:1460)) - (PORT datab (322:322:322) (426:426:426)) - (PORT datac (1274:1274:1274) (1326:1326:1326)) - (PORT datad (1325:1325:1325) (1362:1362:1362)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1877:1877:1877) (2007:2007:2007)) - (PORT datab (1737:1737:1737) (1823:1823:1823)) - (PORT datac (1716:1716:1716) (1809:1809:1809)) - (PORT datad (1373:1373:1373) (1449:1449:1449)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) - (DELAY - (ABSOLUTE - (PORT datac (1141:1141:1141) (1242:1242:1242)) - (PORT datad (1357:1357:1357) (1427:1427:1427)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1355:1355:1355) (1399:1399:1399)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (649:649:649) (701:701:701)) - (PORT datad (1848:1848:1848) (1913:1913:1913)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (655:655:655)) - (PORT datab (655:655:655) (705:705:705)) - (PORT datac (170:170:170) (204:204:204)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datab (1345:1345:1345) (1418:1418:1418)) - (PORT datad (1361:1361:1361) (1443:1443:1443)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (980:980:980)) - (PORT datac (238:238:238) (316:316:316)) - (PORT datad (857:857:857) (914:914:914)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2115:2115:2115) (2168:2168:2168)) - (PORT datab (1358:1358:1358) (1402:1402:1402)) - (PORT datac (1398:1398:1398) (1475:1475:1475)) - (PORT datad (1373:1373:1373) (1419:1419:1419)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1545:1545:1545) (1551:1551:1551)) - (PORT datab (262:262:262) (316:316:316)) - (PORT datac (344:344:344) (371:371:371)) - (PORT datad (1091:1091:1091) (1101:1101:1101)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1606:1606:1606) (1656:1656:1656)) - (PORT datab (235:235:235) (278:278:278)) - (PORT datac (708:708:708) (782:782:782)) - (PORT datad (585:585:585) (605:605:605)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1407:1407:1407) (1464:1464:1464)) - (PORT datab (1304:1304:1304) (1365:1365:1365)) - (PORT datac (290:290:290) (388:388:388)) - (PORT datad (297:297:297) (387:387:387)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (715:715:715)) - (PORT datab (814:814:814) (858:858:858)) - (PORT datac (870:870:870) (893:893:893)) - (PORT datad (397:397:397) (461:461:461)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT datab (644:644:644) (683:683:683)) - (PORT datac (818:818:818) (837:837:837)) - (PORT datad (591:591:591) (609:609:609)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datac (1371:1371:1371) (1445:1445:1445)) - (PORT datad (1609:1609:1609) (1666:1666:1666)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) - (DELAY - (ABSOLUTE - (PORT datac (947:947:947) (1022:1022:1022)) - (PORT datad (909:909:909) (984:984:984)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (885:885:885)) - (PORT datab (1292:1292:1292) (1333:1333:1333)) - (PORT datac (851:851:851) (858:858:858)) - (PORT datad (682:682:682) (739:739:739)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (1082:1082:1082) (1100:1100:1100)) - (PORT datac (531:531:531) (535:535:535)) - (PORT datad (202:202:202) (233:233:233)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT datab (1538:1538:1538) (1625:1625:1625)) - (PORT datac (961:961:961) (1079:1079:1079)) - (PORT datad (1782:1782:1782) (1844:1844:1844)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (690:690:690)) - (PORT datab (665:665:665) (736:736:736)) - (PORT datac (589:589:589) (641:641:641)) - (PORT datad (680:680:680) (731:731:731)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1363:1363:1363) (1379:1379:1379)) - (PORT datac (881:881:881) (959:959:959)) - (PORT datad (793:793:793) (809:809:809)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (940:940:940) (971:971:971)) - (PORT datad (223:223:223) (258:258:258)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datac (1130:1130:1130) (1183:1183:1183)) - (PORT datad (1028:1028:1028) (1045:1045:1045)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1062:1062:1062)) - (PORT datab (1794:1794:1794) (1838:1838:1838)) - (PORT datac (522:522:522) (535:535:535)) - (PORT datad (1014:1014:1014) (1025:1025:1025)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (984:984:984)) - (PORT datab (1059:1059:1059) (1144:1144:1144)) - (PORT datac (1098:1098:1098) (1144:1144:1144)) - (PORT datad (1105:1105:1105) (1181:1181:1181)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) - (PORT ena (1555:1555:1555) (1575:1575:1575)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) - (DELAY - (ABSOLUTE - (PORT datab (937:937:937) (1003:1003:1003)) - (PORT datad (1522:1522:1522) (1568:1568:1568)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1604:1604:1604) (1658:1658:1658)) - (PORT datab (747:747:747) (827:827:827)) - (PORT datac (1316:1316:1316) (1365:1365:1365)) - (PORT datad (580:580:580) (604:604:604)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (2413:2413:2413) (2489:2489:2489)) - (PORT datab (2848:2848:2848) (2922:2922:2922)) - (PORT datac (1120:1120:1120) (1192:1192:1192)) - (PORT datad (1057:1057:1057) (1089:1089:1089)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1867:1867:1867) (1894:1894:1894)) - (PORT datab (849:849:849) (887:887:887)) - (PORT datad (1308:1308:1308) (1320:1320:1320)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT datab (1542:1542:1542) (1635:1635:1635)) - (PORT datac (1212:1212:1212) (1291:1291:1291)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1149:1149:1149)) - (PORT datab (946:946:946) (980:980:980)) - (PORT datac (2035:2035:2035) (2068:2068:2068)) - (PORT datad (1149:1149:1149) (1164:1164:1164)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datac (1819:1819:1819) (1866:1866:1866)) - (PORT datad (1656:1656:1656) (1707:1707:1707)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2151:2151:2151) (2215:2215:2215)) - (PORT datab (262:262:262) (316:316:316)) - (PORT datac (369:369:369) (422:422:422)) - (PORT datad (1037:1037:1037) (1057:1057:1057)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (458:458:458)) - (PORT datab (264:264:264) (318:318:318)) - (PORT datac (2117:2117:2117) (2172:2172:2172)) - (PORT datad (1536:1536:1536) (1558:1558:1558)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1310:1310:1310)) - (PORT datac (1508:1508:1508) (1597:1597:1597)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1149:1149:1149)) - (PORT datab (689:689:689) (752:752:752)) - (PORT datac (1183:1183:1183) (1262:1262:1262)) - (PORT datad (1423:1423:1423) (1460:1460:1460)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1217:1217:1217) (1301:1301:1301)) - (PORT datab (653:653:653) (688:688:688)) - (PORT datac (887:887:887) (952:952:952)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (796:796:796)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (619:619:619) (626:626:626)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (900:900:900)) - (PORT datab (1161:1161:1161) (1177:1177:1177)) - (PORT datac (1062:1062:1062) (1095:1095:1095)) - (PORT datad (1425:1425:1425) (1480:1480:1480)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1423:1423:1423) (1492:1492:1492)) - (PORT datad (935:935:935) (1028:1028:1028)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT datac (1102:1102:1102) (1165:1165:1165)) - (PORT datad (934:934:934) (1024:1024:1024)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1316:1316:1316)) - (PORT datab (1639:1639:1639) (1692:1692:1692)) - (PORT datac (543:543:543) (551:551:551)) - (PORT datad (1664:1664:1664) (1713:1713:1713)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2003:2003:2003) (2045:2045:2045)) - (PORT datab (1218:1218:1218) (1230:1230:1230)) - (PORT datac (828:828:828) (847:847:847)) - (PORT datad (839:839:839) (862:862:862)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT datab (1402:1402:1402) (1488:1488:1488)) - (PORT datac (1718:1718:1718) (1812:1812:1812)) - (PORT datad (1705:1705:1705) (1781:1781:1781)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1341:1341:1341)) - (PORT datab (1412:1412:1412) (1481:1481:1481)) - (PORT datac (2490:2490:2490) (2528:2528:2528)) - (PORT datad (2375:2375:2375) (2441:2441:2441)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1605:1605:1605) (1663:1663:1663)) - (PORT datab (754:754:754) (834:834:834)) - (PORT datac (817:817:817) (834:834:834)) - (PORT datad (1344:1344:1344) (1388:1388:1388)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1562:1562:1562) (1626:1626:1626)) - (PORT datab (941:941:941) (1011:1011:1011)) - (PORT datac (1321:1321:1321) (1340:1340:1340)) - (PORT datad (829:829:829) (839:839:839)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (962:962:962)) - (PORT datab (1204:1204:1204) (1261:1261:1261)) - (PORT datac (1534:1534:1534) (1590:1590:1590)) - (PORT datad (876:876:876) (959:959:959)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (2058:2058:2058) (2114:2114:2114)) - (PORT datab (885:885:885) (938:938:938)) - (PORT datac (1276:1276:1276) (1345:1345:1345)) - (PORT datad (1126:1126:1126) (1182:1182:1182)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1561:1561:1561) (1623:1623:1623)) - (PORT datab (1205:1205:1205) (1265:1265:1265)) - (PORT datac (848:848:848) (908:908:908)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1497:1497:1497) (1534:1534:1534)) - (PORT datab (1297:1297:1297) (1349:1349:1349)) - (PORT datac (586:586:586) (621:621:621)) - (PORT datad (594:594:594) (633:633:633)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (414:414:414)) - (PORT datab (1336:1336:1336) (1386:1386:1386)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (326:326:326) (348:348:348)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT datab (974:974:974) (999:999:999)) - (PORT datac (588:588:588) (623:623:623)) - (PORT datad (1271:1271:1271) (1309:1309:1309)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1605:1605:1605) (1662:1662:1662)) - (PORT datab (238:238:238) (283:283:283)) - (PORT datac (718:718:718) (794:794:794)) - (PORT datad (581:581:581) (600:600:600)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (424:424:424)) - (PORT datab (1150:1150:1150) (1211:1211:1211)) - (PORT datac (613:613:613) (635:635:635)) - (PORT datad (838:838:838) (884:884:884)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1156:1156:1156)) - (PORT datab (2630:2630:2630) (2710:2710:2710)) - (PORT datac (839:839:839) (858:858:858)) - (PORT datad (1609:1609:1609) (1688:1688:1688)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1228:1228:1228)) - (PORT datab (684:684:684) (751:751:751)) - (PORT datac (960:960:960) (949:949:949)) - (PORT datad (629:629:629) (648:648:648)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (2348:2348:2348) (2418:2418:2418)) - (PORT datab (896:896:896) (926:926:926)) - (PORT datac (560:560:560) (574:574:574)) - (PORT datad (1062:1062:1062) (1090:1090:1090)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1692:1692:1692) (1758:1758:1758)) - (PORT datab (1638:1638:1638) (1688:1688:1688)) - (PORT datac (1624:1624:1624) (1660:1660:1660)) - (PORT datad (1174:1174:1174) (1183:1183:1183)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT datac (807:807:807) (852:852:852)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (366:366:366)) - (PORT datab (208:208:208) (251:251:251)) - (PORT datac (784:784:784) (817:817:817)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (902:902:902)) - (PORT datab (890:890:890) (906:906:906)) - (PORT datac (873:873:873) (905:905:905)) - (PORT datad (614:614:614) (662:662:662)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1877:1877:1877) (2008:2008:2008)) - (PORT datab (1729:1729:1729) (1814:1814:1814)) - (PORT datac (1724:1724:1724) (1821:1821:1821)) - (PORT datad (1358:1358:1358) (1437:1437:1437)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1244:1244:1244) (1332:1332:1332)) - (PORT datab (879:879:879) (901:901:901)) - (PORT datac (1574:1574:1574) (1584:1584:1584)) - (PORT datad (1371:1371:1371) (1418:1418:1418)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (996:996:996) (1099:1099:1099)) - (PORT datac (849:849:849) (864:864:864)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (881:881:881) (903:903:903)) - (PORT datac (1603:1603:1603) (1633:1633:1633)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~3) - (DELAY - (ABSOLUTE - (PORT datab (1035:1035:1035) (1113:1113:1113)) - (PORT datad (919:919:919) (1024:1024:1024)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1090:1090:1090)) - (PORT datab (684:684:684) (744:744:744)) - (PORT datac (1078:1078:1078) (1083:1083:1083)) - (PORT datad (1003:1003:1003) (1007:1007:1007)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (945:945:945) (1002:1002:1002)) - (PORT datac (1362:1362:1362) (1459:1459:1459)) - (PORT datad (631:631:631) (652:652:652)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1134:1134:1134) (1198:1198:1198)) - (PORT datab (683:683:683) (744:744:744)) - (PORT datac (622:622:622) (630:630:630)) - (PORT datad (1090:1090:1090) (1107:1107:1107)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (922:922:922)) - (PORT datab (1427:1427:1427) (1495:1495:1495)) - (PORT datac (847:847:847) (882:882:882)) - (PORT datad (819:819:819) (851:851:851)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1591:1591:1591) (1608:1608:1608)) - (PORT datab (1991:1991:1991) (2037:2037:2037)) - (PORT datac (854:854:854) (878:878:878)) - (PORT datad (1151:1151:1151) (1202:1202:1202)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1206:1206:1206)) - (PORT datab (857:857:857) (880:880:880)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (752:752:752) (761:761:761)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT datab (942:942:942) (1011:1011:1011)) - (PORT datac (1171:1171:1171) (1231:1231:1231)) - (PORT datad (874:874:874) (959:959:959)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (620:620:620)) - (PORT datab (654:654:654) (679:679:679)) - (PORT datac (1033:1033:1033) (1079:1079:1079)) - (PORT datad (594:594:594) (623:623:623)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (666:666:666)) - (PORT datab (970:970:970) (1062:1062:1062)) - (PORT datac (1102:1102:1102) (1165:1165:1165)) - (PORT datad (1382:1382:1382) (1445:1445:1445)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1188:1188:1188) (1227:1227:1227)) - (PORT datab (680:680:680) (738:738:738)) - (PORT datac (862:862:862) (864:864:864)) - (PORT datad (629:629:629) (646:646:646)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (1423:1423:1423) (1492:1492:1492)) - (PORT datab (1617:1617:1617) (1667:1667:1667)) - (PORT datac (1099:1099:1099) (1161:1161:1161)) - (PORT datad (937:937:937) (1028:1028:1028)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1098:1098:1098) (1124:1124:1124)) - (PORT datab (1105:1105:1105) (1138:1138:1138)) - (PORT datac (1440:1440:1440) (1492:1492:1492)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (626:626:626) (664:664:664)) - (PORT datad (195:195:195) (219:219:219)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (988:988:988)) - (PORT datab (654:654:654) (698:698:698)) - (PORT datac (920:920:920) (995:995:995)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1277:1277:1277)) - (PORT datab (1363:1363:1363) (1386:1386:1386)) - (PORT datac (2031:2031:2031) (2070:2070:2070)) - (PORT datad (916:916:916) (941:941:941)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1877:1877:1877) (2007:2007:2007)) - (PORT datab (1736:1736:1736) (1819:1819:1819)) - (PORT datac (1714:1714:1714) (1803:1803:1803)) - (PORT datad (1375:1375:1375) (1450:1450:1450)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1286:1286:1286)) - (PORT datab (1175:1175:1175) (1253:1253:1253)) - (PORT datac (1145:1145:1145) (1253:1253:1253)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1372:1372:1372) (1431:1431:1431)) - (PORT datab (235:235:235) (280:280:280)) - (PORT datac (1726:1726:1726) (1733:1733:1733)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1416:1416:1416) (1519:1519:1519)) - (PORT datac (1495:1495:1495) (1561:1561:1561)) - (PORT datad (1338:1338:1338) (1413:1413:1413)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~2) - (DELAY - (ABSOLUTE - (PORT datac (1373:1373:1373) (1450:1450:1450)) - (PORT datad (1324:1324:1324) (1390:1390:1390)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1679:1679:1679) (1758:1758:1758)) - (PORT datab (1682:1682:1682) (1746:1746:1746)) - (PORT datac (1078:1078:1078) (1119:1119:1119)) - (PORT datad (1847:1847:1847) (1902:1902:1902)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1598:1598:1598) (1605:1605:1605)) - (PORT datab (222:222:222) (262:262:262)) - (PORT datac (1716:1716:1716) (1808:1808:1808)) - (PORT datad (1125:1125:1125) (1166:1166:1166)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (773:773:773) (781:781:781)) - (PORT datab (1934:1934:1934) (1975:1975:1975)) - (PORT datac (780:780:780) (805:805:805)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1242:1242:1242) (1320:1320:1320)) - (PORT datab (746:746:746) (744:744:744)) - (PORT datac (743:743:743) (755:755:755)) - (PORT datad (814:814:814) (815:815:815)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1047:1047:1047) (1066:1066:1066)) - (PORT datab (568:568:568) (589:589:589)) - (PORT datac (679:679:679) (744:744:744)) - (PORT datad (849:849:849) (866:866:866)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1280:1280:1280) (1301:1301:1301)) - (PORT datab (1781:1781:1781) (1854:1854:1854)) - (PORT datac (1635:1635:1635) (1727:1727:1727)) - (PORT datad (849:849:849) (868:868:868)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~33) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1039:1039:1039)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (1247:1247:1247) (1262:1262:1262)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1079:1079:1079) (1114:1114:1114)) - (PORT datab (878:878:878) (893:893:893)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (542:542:542) (554:554:554)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1228:1228:1228)) - (PORT datad (1049:1049:1049) (1107:1107:1107)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1076:1076:1076) (1146:1146:1146)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (818:818:818) (818:818:818)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (1246:1246:1246) (1311:1311:1311)) - (PORT datad (3285:3285:3285) (3516:3516:3516)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_DAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (574:574:574) (571:571:571)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (380:380:380)) - (PORT datab (279:279:279) (371:371:371)) - (PORT datad (248:248:248) (325:325:325)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_CLK\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT asdata (3742:3742:3742) (4083:4083:4083)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (240:240:240) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (300:300:300)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT asdata (569:569:569) (647:647:647)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (300:300:300)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (480:480:480)) - (PORT datab (251:251:251) (335:335:335)) - (PORT datac (225:225:225) (304:304:304)) - (PORT datad (223:223:223) (295:295:295)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (344:344:344)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (225:225:225) (298:298:298)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (261:261:261)) - (PORT datad (227:227:227) (300:300:300)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) - (DELAY - (ABSOLUTE - (PORT dataa (212:212:212) (261:261:261)) - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (227:227:227) (300:300:300)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (PORT ena (1590:1590:1590) (1670:1670:1670)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (381:381:381)) - (PORT datab (265:265:265) (356:356:356)) - (PORT datad (245:245:245) (325:325:325)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (PORT ena (1590:1590:1590) (1670:1670:1670)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (381:381:381)) - (PORT datab (277:277:277) (371:371:371)) - (PORT datad (239:239:239) (317:317:317)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (PORT ena (1590:1590:1590) (1670:1670:1670)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (277:277:277) (376:376:376)) - (PORT datab (280:280:280) (375:375:375)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (PORT ena (1590:1590:1590) (1670:1670:1670)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (277:277:277) (380:380:380)) - (PORT datab (277:277:277) (373:373:373)) - (PORT datac (3561:3561:3561) (3920:3920:3920)) - (PORT datad (247:247:247) (328:328:328)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (276:276:276) (380:380:380)) - (PORT datac (249:249:249) (338:338:338)) - (PORT datad (248:248:248) (328:328:328)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (938:938:938) (1038:1038:1038)) - (PORT datad (242:242:242) (321:321:321)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT asdata (3947:3947:3947) (4298:4298:4298)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1255:1255:1255) (1259:1259:1259)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT asdata (560:560:560) (634:634:634)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1255:1255:1255) (1259:1259:1259)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT asdata (592:592:592) (679:679:679)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1255:1255:1255) (1259:1259:1259)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT asdata (1280:1280:1280) (1341:1341:1341)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1687:1687:1687) (1736:1736:1736)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT asdata (950:950:950) (1017:1017:1017)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1255:1255:1255) (1259:1259:1259)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT asdata (1532:1532:1532) (1590:1590:1590)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1687:1687:1687) (1736:1736:1736)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT asdata (935:935:935) (997:997:997)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1687:1687:1687) (1736:1736:1736)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT asdata (1492:1492:1492) (1552:1552:1552)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1255:1255:1255) (1259:1259:1259)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT asdata (1428:1428:1428) (1495:1495:1495)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1253:1253:1253) (1261:1261:1261)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1245:1245:1245) (1303:1303:1303)) - (PORT datab (457:457:457) (531:531:531)) - (PORT datac (648:648:648) (721:721:721)) - (PORT datad (1168:1168:1168) (1228:1228:1228)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (714:714:714)) - (PORT datab (279:279:279) (374:374:374)) - (PORT datad (628:628:628) (692:692:692)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (413:413:413)) - (PORT datac (550:550:550) (554:554:554)) - (PORT datad (246:246:246) (317:317:317)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) - (DELAY - (ABSOLUTE - (PORT dataa (973:973:973) (1081:1081:1081)) - (PORT datab (210:210:210) (252:252:252)) - (PORT datac (3561:3561:3561) (3918:3918:3918)) - (PORT datad (521:521:521) (533:533:533)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1281:1281:1281)) - (PORT datab (646:646:646) (712:712:712)) - (PORT datac (248:248:248) (337:337:337)) - (PORT datad (916:916:916) (976:976:976)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (274:274:274) (363:363:363)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (1152:1152:1152) (1213:1213:1213)) - (PORT datad (626:626:626) (689:689:689)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1057:1057:1057)) - (PORT datad (643:643:643) (661:661:661)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|extended) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1740:1740:1740) (1806:1806:1806)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (720:720:720)) - (PORT datab (278:278:278) (373:373:373)) - (PORT datac (672:672:672) (732:732:732)) - (PORT datad (702:702:702) (772:772:772)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1058:1058:1058)) - (PORT datab (1128:1128:1128) (1217:1217:1217)) - (PORT datad (643:643:643) (661:661:661)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1248:1248:1248) (1306:1306:1306)) - (PORT datab (449:449:449) (527:527:527)) - (PORT datac (653:653:653) (728:728:728)) - (PORT datad (1163:1163:1163) (1227:1227:1227)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1242:1242:1242) (1306:1306:1306)) - (PORT datac (649:649:649) (723:723:723)) - (PORT datad (424:424:424) (494:494:494)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1243:1243:1243) (1305:1305:1305)) - (PORT datab (457:457:457) (532:532:532)) - (PORT datac (649:649:649) (722:722:722)) - (PORT datad (1167:1167:1167) (1228:1228:1228)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (269:269:269)) - (PORT datab (471:471:471) (542:542:542)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (1163:1163:1163) (1227:1227:1227)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (471:471:471) (543:543:543)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (680:680:680) (743:743:743)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (981:981:981) (1047:1047:1047)) - (PORT datad (322:322:322) (340:340:340)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1488:1488:1488)) - (PORT datab (1195:1195:1195) (1239:1239:1239)) - (PORT datac (796:796:796) (820:820:820)) - (PORT datad (937:937:937) (1025:1025:1025)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1877:1877:1877) (2013:2013:2013)) - (PORT datab (1731:1731:1731) (1817:1817:1817)) - (PORT datac (1725:1725:1725) (1821:1821:1821)) - (PORT datad (1358:1358:1358) (1432:1432:1432)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT datab (1398:1398:1398) (1482:1482:1482)) - (PORT datac (1724:1724:1724) (1817:1817:1817)) - (PORT datad (1699:1699:1699) (1780:1780:1780)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1308:1308:1308)) - (PORT datab (1174:1174:1174) (1249:1249:1249)) - (PORT datad (1362:1362:1362) (1430:1430:1430)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (915:915:915)) - (PORT datab (925:925:925) (945:945:945)) - (PORT datac (794:794:794) (818:818:818)) - (PORT datad (783:783:783) (805:805:805)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (916:916:916)) - (PORT datab (1152:1152:1152) (1198:1198:1198)) - (PORT datac (799:799:799) (826:826:826)) - (PORT datad (211:211:211) (243:243:243)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1206:1206:1206) (1317:1317:1317)) - (PORT datab (1158:1158:1158) (1237:1237:1237)) - (PORT datac (542:542:542) (575:575:575)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (870:870:870)) - (PORT datab (873:873:873) (886:886:886)) - (PORT datac (543:543:543) (559:559:559)) - (PORT datad (853:853:853) (879:879:879)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (960:960:960) (1060:1060:1060)) - (PORT datad (1182:1182:1182) (1276:1276:1276)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1151:1151:1151)) - (PORT datab (684:684:684) (747:747:747)) - (PORT datac (1130:1130:1130) (1169:1169:1169)) - (PORT datad (1040:1040:1040) (1067:1067:1067)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1225:1225:1225)) - (PORT datab (204:204:204) (245:245:245)) - (PORT datac (1130:1130:1130) (1169:1169:1169)) - (PORT datad (628:628:628) (644:644:644)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (917:917:917) (986:986:986)) - (PORT datac (1127:1127:1127) (1173:1173:1173)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT datab (1164:1164:1164) (1236:1236:1236)) - (PORT datac (1315:1315:1315) (1380:1380:1380)) - (PORT datad (1151:1151:1151) (1223:1223:1223)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (667:667:667)) - (PORT datab (828:828:828) (884:884:884)) - (PORT datac (1223:1223:1223) (1221:1221:1221)) - (PORT datad (847:847:847) (865:865:865)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1724:1724:1724) (1799:1799:1799)) - (PORT datab (948:948:948) (1037:1037:1037)) - (PORT datac (1187:1187:1187) (1228:1228:1228)) - (PORT datad (1718:1718:1718) (1734:1734:1734)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (2306:2306:2306) (2356:2356:2356)) - (PORT datab (923:923:923) (939:939:939)) - (PORT datac (924:924:924) (1014:1014:1014)) - (PORT datad (943:943:943) (1006:1006:1006)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (251:251:251)) - (PORT datab (878:878:878) (898:898:898)) - (PORT datac (964:964:964) (1076:1076:1076)) - (PORT datad (964:964:964) (1056:1056:1056)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (264:264:264)) - (PORT datab (1265:1265:1265) (1294:1294:1294)) - (PORT datac (1858:1858:1858) (1882:1882:1882)) - (PORT datad (902:902:902) (916:916:916)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1249:1249:1249) (1331:1331:1331)) - (PORT datac (1305:1305:1305) (1403:1403:1403)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1039:1039:1039)) - (PORT datab (1102:1102:1102) (1119:1119:1119)) - (PORT datac (1381:1381:1381) (1423:1423:1423)) - (PORT datad (922:922:922) (967:967:967)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) - (DELAY - (ABSOLUTE - (PORT dataa (2350:2350:2350) (2446:2446:2446)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (657:657:657) (673:673:673)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1296:1296:1296) (1312:1312:1312)) - (PORT datab (1119:1119:1119) (1161:1161:1161)) - (PORT datac (1238:1238:1238) (1234:1234:1234)) - (PORT datad (1063:1063:1063) (1086:1086:1086)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datad (1149:1149:1149) (1260:1260:1260)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1542:1542:1542)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (298:298:298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1542:1542:1542)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1542:1542:1542)) - (PORT asdata (566:566:566) (644:644:644)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|resets_\|clrpc_int\~0) (DELAY (ABSOLUTE - (PORT dataa (939:939:939) (1000:1000:1000)) - (PORT datab (941:941:941) (1038:1038:1038)) - (PORT datad (908:908:908) (963:963:963)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (649:649:649) (728:728:728)) + (PORT datab (605:605:605) (665:665:665)) + (PORT datad (1168:1168:1168) (1217:1217:1217)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -4265,9 +11429,9 @@ (INSTANCE z80_\|resets_\|clrpc_int) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1542:1542:1542)) + (PORT clk (1548:1548:1548) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) + (PORT clrn (1597:1597:1597) (1572:1572:1572)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -4281,9 +11445,9 @@ (INSTANCE z80_\|resets_\|clrpc\~0) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (340:340:340)) - (PORT datab (248:248:248) (332:332:332)) - (PORT datad (219:219:219) (288:288:288)) + (PORT dataa (251:251:251) (340:340:340)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datad (217:217:217) (285:285:285)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -4293,8444 +11457,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (INSTANCE z80_\|address_latch_\|abusz\[7\]) (DELAY (ABSOLUTE - (PORT datab (573:573:573) (612:612:612)) - (PORT datac (1129:1129:1129) (1205:1205:1205)) - (PORT datad (1308:1308:1308) (1372:1372:1372)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1720:1720:1720) (1795:1795:1795)) - (PORT datab (808:808:808) (835:835:835)) - (PORT datac (1287:1287:1287) (1327:1327:1327)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal38\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2173:2173:2173) (2229:2229:2229)) - (PORT datab (1872:1872:1872) (1963:1963:1963)) - (PORT datac (1447:1447:1447) (1461:1461:1461)) - (PORT datad (1644:1644:1644) (1691:1691:1691)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) - (DELAY - (ABSOLUTE - (PORT datac (1800:1800:1800) (1850:1850:1850)) - (PORT datad (1608:1608:1608) (1625:1625:1625)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (463:463:463)) - (PORT datab (262:262:262) (312:312:312)) - (PORT datac (2122:2122:2122) (2177:2177:2177)) - (PORT datad (1377:1377:1377) (1380:1380:1380)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (953:953:953)) - (PORT datab (701:701:701) (754:754:754)) - (PORT datac (1019:1019:1019) (1030:1030:1030)) - (PORT datad (1648:1648:1648) (1732:1732:1732)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1149:1149:1149)) - (PORT datab (941:941:941) (973:973:973)) - (PORT datac (605:605:605) (631:631:631)) - (PORT datad (1608:1608:1608) (1686:1686:1686)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1686:1686:1686) (1775:1775:1775)) - (PORT datab (198:198:198) (235:235:235)) - (PORT datac (824:824:824) (871:871:871)) - (PORT datad (667:667:667) (717:717:717)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1929:1929:1929) (1987:1987:1987)) - (PORT datab (566:566:566) (574:574:574)) - (PORT datac (1183:1183:1183) (1216:1216:1216)) - (PORT datad (2316:2316:2316) (2385:2385:2385)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (883:883:883)) - (PORT datab (1669:1669:1669) (1765:1765:1765)) - (PORT datac (1248:1248:1248) (1260:1260:1260)) - (PORT datad (853:853:853) (876:876:876)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1505:1505:1505) (1560:1560:1560)) - (PORT datab (1271:1271:1271) (1295:1295:1295)) - (PORT datac (2137:2137:2137) (2227:2227:2227)) - (PORT datad (909:909:909) (984:984:984)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT datac (2486:2486:2486) (2523:2523:2523)) - (PORT datad (2373:2373:2373) (2439:2439:2439)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (821:821:821)) - (PORT datab (1216:1216:1216) (1248:1248:1248)) - (PORT datac (528:528:528) (548:548:548)) - (PORT datad (2318:2318:2318) (2388:2388:2388)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (946:946:946) (1019:1019:1019)) - (PORT datad (1312:1312:1312) (1370:1370:1370)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (654:654:654)) - (PORT datab (637:637:637) (661:661:661)) - (PORT datac (816:816:816) (850:850:850)) - (PORT datad (1029:1029:1029) (1043:1043:1043)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (974:974:974)) - (PORT datac (1082:1082:1082) (1129:1129:1129)) - (PORT datad (1852:1852:1852) (1910:1910:1910)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1246:1246:1246)) - (PORT datab (1056:1056:1056) (1096:1096:1096)) - (PORT datac (1273:1273:1273) (1310:1310:1310)) - (PORT datad (2941:2941:2941) (2984:2984:2984)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (908:908:908)) - (PORT datab (2463:2463:2463) (2519:2519:2519)) - (PORT datac (865:865:865) (889:889:889)) - (PORT datad (2937:2937:2937) (2979:2979:2979)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (940:940:940)) - (PORT datab (1144:1144:1144) (1213:1213:1213)) - (PORT datac (1648:1648:1648) (1729:1729:1729)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (961:961:961)) - (PORT datab (949:949:949) (1040:1040:1040)) - (PORT datac (1287:1287:1287) (1327:1327:1327)) - (PORT datad (1178:1178:1178) (1219:1219:1219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (263:263:263)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1038:1038:1038) (1097:1097:1097)) - (PORT datab (1401:1401:1401) (1490:1490:1490)) - (PORT datac (1717:1717:1717) (1811:1811:1811)) - (PORT datad (1706:1706:1706) (1780:1780:1780)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1337:1337:1337) (1395:1395:1395)) - (PORT datab (636:636:636) (676:676:676)) - (PORT datac (1460:1460:1460) (1490:1490:1490)) - (PORT datad (932:932:932) (963:963:963)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1214:1214:1214)) - (PORT datac (576:576:576) (612:612:612)) - (PORT datad (1351:1351:1351) (1408:1408:1408)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (394:394:394)) - (PORT datab (882:882:882) (920:920:920)) - (PORT datac (1134:1134:1134) (1185:1185:1185)) - (PORT datad (1583:1583:1583) (1638:1638:1638)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1117:1117:1117)) - (PORT datac (1023:1023:1023) (1033:1033:1033)) - (PORT datad (959:959:959) (1056:1056:1056)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2966:2966:2966) (3024:3024:3024)) - (PORT datab (2463:2463:2463) (2524:2524:2524)) - (PORT datac (822:822:822) (873:873:873)) - (PORT datad (1152:1152:1152) (1205:1205:1205)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) - (DELAY - (ABSOLUTE - (PORT dataa (961:961:961) (1025:1025:1025)) - (PORT datab (1314:1314:1314) (1346:1346:1346)) - (PORT datac (822:822:822) (871:871:871)) - (PORT datad (1621:1621:1621) (1735:1735:1735)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (887:887:887)) - (PORT datab (884:884:884) (932:932:932)) - (PORT datac (833:833:833) (862:862:862)) - (PORT datad (619:619:619) (633:633:633)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1244:1244:1244)) - (PORT datab (1061:1061:1061) (1102:1102:1102)) - (PORT datac (1268:1268:1268) (1305:1305:1305)) - (PORT datad (2936:2936:2936) (2978:2978:2978)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (769:769:769) (869:869:869)) - (PORT datab (1055:1055:1055) (1137:1137:1137)) - (PORT datac (662:662:662) (756:756:756)) - (PORT datad (993:993:993) (1019:1019:1019)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (679:679:679)) - (PORT datab (861:861:861) (876:876:876)) - (PORT datad (819:819:819) (847:847:847)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1083:1083:1083)) - (PORT datab (643:643:643) (662:662:662)) - (PORT datac (1021:1021:1021) (1013:1013:1013)) - (PORT datad (887:887:887) (905:905:905)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2352:2352:2352) (2443:2443:2443)) - (PORT datab (955:955:955) (1005:1005:1005)) - (PORT datac (1491:1491:1491) (1535:1535:1535)) - (PORT datad (799:799:799) (819:819:819)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1322:1322:1322)) - (PORT datab (208:208:208) (251:251:251)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (845:845:845) (864:864:864)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (939:939:939)) - (PORT datab (838:838:838) (877:877:877)) - (PORT datac (520:520:520) (532:532:532)) - (PORT datad (807:807:807) (823:823:823)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT datab (1403:1403:1403) (1491:1491:1491)) - (PORT datac (1716:1716:1716) (1807:1807:1807)) - (PORT datad (1704:1704:1704) (1782:1782:1782)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (715:715:715)) - (PORT datab (868:868:868) (900:900:900)) - (PORT datac (902:902:902) (992:992:992)) - (PORT datad (1823:1823:1823) (1888:1888:1888)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datab (1003:1003:1003) (1074:1074:1074)) - (PORT datac (962:962:962) (1040:1040:1040)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (939:939:939) (1029:1029:1029)) - (PORT datab (870:870:870) (897:897:897)) - (PORT datac (1154:1154:1154) (1172:1172:1172)) - (PORT datad (1822:1822:1822) (1885:1885:1885)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1852:1852:1852) (1933:1933:1933)) - (PORT datab (868:868:868) (898:898:898)) - (PORT datac (902:902:902) (992:992:992)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1427:1427:1427)) - (PORT datab (873:873:873) (892:892:892)) - (PORT datac (970:970:970) (1026:1026:1026)) - (PORT datad (1222:1222:1222) (1261:1261:1261)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1428:1428:1428)) - (PORT datab (1250:1250:1250) (1300:1300:1300)) - (PORT datac (977:977:977) (1031:1031:1031)) - (PORT datad (1141:1141:1141) (1164:1164:1164)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (202:202:202) (239:239:239)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT datac (2490:2490:2490) (2531:2531:2531)) - (PORT datad (2377:2377:2377) (2445:2445:2445)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (276:276:276)) - (PORT datab (1413:1413:1413) (1479:1479:1479)) - (PORT datac (1266:1266:1266) (1304:1304:1304)) - (PORT datad (212:212:212) (245:245:245)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (913:913:913)) - (PORT datab (1076:1076:1076) (1092:1092:1092)) - (PORT datac (734:734:734) (756:756:756)) - (PORT datad (1072:1072:1072) (1089:1089:1089)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (698:698:698)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (539:539:539) (542:542:542)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (3094:3094:3094) (3188:3188:3188)) - (PORT datab (2162:2162:2162) (2272:2272:2272)) - (PORT datac (837:837:837) (865:865:865)) - (PORT datad (1017:1017:1017) (1050:1050:1050)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (908:908:908)) - (PORT datab (1601:1601:1601) (1676:1676:1676)) - (PORT datac (815:815:815) (882:882:882)) - (PORT datad (886:886:886) (959:959:959)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (1281:1281:1281) (1284:1284:1284)) - (PORT datac (1019:1019:1019) (1067:1067:1067)) - (PORT datad (687:687:687) (750:750:750)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1270:1270:1270) (1342:1342:1342)) - (PORT datab (893:893:893) (934:934:934)) - (PORT datac (860:860:860) (927:927:927)) - (PORT datad (1689:1689:1689) (1742:1742:1742)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1319:1319:1319)) - (PORT datab (1778:1778:1778) (1851:1851:1851)) - (PORT datac (1019:1019:1019) (1042:1042:1042)) - (PORT datad (806:806:806) (850:850:850)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1271:1271:1271) (1342:1342:1342)) - (PORT datab (1259:1259:1259) (1275:1275:1275)) - (PORT datac (827:827:827) (862:862:862)) - (PORT datad (1689:1689:1689) (1741:1741:1741)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1271:1271:1271) (1346:1346:1346)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1687:1687:1687) (1744:1744:1744)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (856:856:856) (875:875:875)) - (PORT datac (1062:1062:1062) (1063:1063:1063)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (870:870:870)) - (PORT datab (583:583:583) (596:596:596)) - (PORT datac (736:736:736) (747:747:747)) - (PORT datad (1298:1298:1298) (1372:1372:1372)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (943:943:943)) - (PORT datab (1683:1683:1683) (1759:1759:1759)) - (PORT datac (1219:1219:1219) (1307:1307:1307)) - (PORT datad (1122:1122:1122) (1176:1176:1176)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (937:937:937)) - (PORT datab (1144:1144:1144) (1212:1212:1212)) - (PORT datac (1647:1647:1647) (1729:1729:1729)) - (PORT datad (879:879:879) (931:931:931)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (656:656:656) (702:702:702)) - (PORT datac (638:638:638) (695:695:695)) - (PORT datad (1045:1045:1045) (1048:1048:1048)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (869:869:869)) - (PORT datab (615:615:615) (625:625:625)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT datab (1267:1267:1267) (1389:1389:1389)) - (PORT datac (1170:1170:1170) (1280:1280:1280)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1383:1383:1383) (1413:1413:1413)) - (PORT datab (364:364:364) (401:401:401)) - (PORT datac (1219:1219:1219) (1212:1212:1212)) - (PORT datad (794:794:794) (827:827:827)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1207:1207:1207)) - (PORT datab (1118:1118:1118) (1162:1162:1162)) - (PORT datac (1103:1103:1103) (1174:1174:1174)) - (PORT datad (1015:1015:1015) (1048:1048:1048)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (2158:2158:2158) (2273:2273:2273)) - (PORT datac (838:838:838) (868:868:868)) - (PORT datad (1035:1035:1035) (1061:1061:1061)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (864:864:864)) - (PORT datab (713:713:713) (786:786:786)) - (PORT datac (635:635:635) (664:664:664)) - (PORT datad (1021:1021:1021) (1034:1034:1034)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1050:1050:1050)) - (PORT datab (2169:2169:2169) (2212:2212:2212)) - (PORT datac (2222:2222:2222) (2256:2256:2256)) - (PORT datad (1453:1453:1453) (1583:1583:1583)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal69\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1342:1342:1342)) - (PORT datab (1413:1413:1413) (1485:1485:1485)) - (PORT datac (2490:2490:2490) (2529:2529:2529)) - (PORT datad (2374:2374:2374) (2444:2444:2444)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1379:1379:1379)) - (PORT datab (1147:1147:1147) (1218:1218:1218)) - (PORT datac (859:859:859) (889:889:889)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (700:700:700)) - (PORT datab (259:259:259) (305:305:305)) - (PORT datad (204:204:204) (235:235:235)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1879:1879:1879) (1963:1963:1963)) - (PORT datab (221:221:221) (268:268:268)) - (PORT datac (552:552:552) (573:573:573)) - (PORT datad (188:188:188) (221:221:221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (323:323:323) (428:428:428)) - (PORT datab (240:240:240) (279:279:279)) - (PORT datac (523:523:523) (526:526:526)) - (PORT datad (297:297:297) (385:385:385)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (717:717:717)) - (PORT datab (816:816:816) (859:859:859)) - (PORT datac (868:868:868) (896:896:896)) - (PORT datad (398:398:398) (464:464:464)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1208:1208:1208) (1225:1225:1225)) - (PORT datab (1091:1091:1091) (1117:1117:1117)) - (PORT datac (1235:1235:1235) (1364:1364:1364)) - (PORT datad (1374:1374:1374) (1428:1428:1428)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1373:1373:1373) (1425:1425:1425)) - (PORT datab (595:595:595) (614:614:614)) - (PORT datac (1065:1065:1065) (1122:1122:1122)) - (PORT datad (2820:2820:2820) (2882:2882:2882)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1459:1459:1459) (1481:1481:1481)) - (PORT datab (2372:2372:2372) (2462:2462:2462)) - (PORT datac (1473:1473:1473) (1527:1527:1527)) - (PORT datad (2372:2372:2372) (2454:2454:2454)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1671:1671:1671) (1731:1731:1731)) - (PORT datab (1845:1845:1845) (1972:1972:1972)) - (PORT datad (2133:2133:2133) (2181:2181:2181)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1678:1678:1678) (1761:1761:1761)) - (PORT datab (1680:1680:1680) (1745:1745:1745)) - (PORT datac (1076:1076:1076) (1116:1116:1116)) - (PORT datad (1844:1844:1844) (1900:1900:1900)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (284:284:284)) - (PORT datab (1212:1212:1212) (1266:1266:1266)) - (PORT datac (857:857:857) (879:879:879)) - (PORT datad (1147:1147:1147) (1198:1198:1198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT datab (1729:1729:1729) (1822:1822:1822)) - (PORT datac (1724:1724:1724) (1819:1819:1819)) - (PORT datad (1834:1834:1834) (1966:1966:1966)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1296:1296:1296)) - (PORT datab (868:868:868) (899:899:899)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (613:613:613) (636:636:636)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1176:1176:1176)) - (PORT datab (1187:1187:1187) (1217:1217:1217)) - (PORT datac (1775:1775:1775) (1849:1849:1849)) - (PORT datad (1018:1018:1018) (1052:1052:1052)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1929:1929:1929) (1985:1985:1985)) - (PORT datab (1110:1110:1110) (1162:1162:1162)) - (PORT datac (1129:1129:1129) (1182:1182:1182)) - (PORT datad (1807:1807:1807) (1864:1864:1864)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT dataa (2669:2669:2669) (2767:2767:2767)) - (PORT datac (529:529:529) (547:547:547)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (457:457:457)) - (PORT datab (1367:1367:1367) (1424:1424:1424)) - (PORT datac (1361:1361:1361) (1425:1425:1425)) - (PORT datad (379:379:379) (399:399:399)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (632:632:632)) - (PORT datab (935:935:935) (983:983:983)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1138:1138:1138) (1192:1192:1192)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1492:1492:1492) (1528:1528:1528)) - (PORT datab (1294:1294:1294) (1344:1344:1344)) - (PORT datac (602:602:602) (637:637:637)) - (PORT datad (598:598:598) (636:636:636)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1661:1661:1661) (1717:1717:1717)) - (PORT datab (1367:1367:1367) (1414:1414:1414)) - (PORT datac (528:528:528) (545:545:545)) - (PORT datad (633:633:633) (674:674:674)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1422:1422:1422)) - (PORT datab (591:591:591) (610:610:610)) - (PORT datac (1061:1061:1061) (1121:1121:1121)) - (PORT datad (2824:2824:2824) (2889:2889:2889)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT datac (557:557:557) (583:583:583)) - (PORT datad (1067:1067:1067) (1062:1062:1062)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (923:923:923) (987:987:987)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (613:613:613)) - (PORT datab (1046:1046:1046) (1127:1127:1127)) - (PORT datac (1253:1253:1253) (1275:1275:1275)) - (PORT datad (1107:1107:1107) (1184:1184:1184)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (909:909:909)) - (PORT datab (652:652:652) (676:676:676)) - (PORT datac (1117:1117:1117) (1132:1132:1132)) - (PORT datad (1302:1302:1302) (1291:1291:1291)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1781:1781:1781) (1836:1836:1836)) - (PORT datab (712:712:712) (783:783:783)) - (PORT datac (357:357:357) (383:383:383)) - (PORT datad (1244:1244:1244) (1239:1239:1239)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (418:418:418)) - (PORT datab (1084:1084:1084) (1123:1123:1123)) - (PORT datac (1018:1018:1018) (1065:1065:1065)) - (PORT datad (1245:1245:1245) (1240:1240:1240)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1187:1187:1187)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (852:852:852) (865:865:865)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (1903:1903:1903) (2027:2027:2027)) - (PORT datab (238:238:238) (284:284:284)) - (PORT datac (1331:1331:1331) (1407:1407:1407)) - (PORT datad (877:877:877) (897:897:897)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (1957:1957:1957) (2084:2084:2084)) - (PORT datab (921:921:921) (940:940:940)) - (PORT datac (925:925:925) (1017:1017:1017)) - (PORT datad (943:943:943) (1008:1008:1008)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1187:1187:1187)) - (PORT datab (1069:1069:1069) (1129:1129:1129)) - (PORT datac (1133:1133:1133) (1184:1184:1184)) - (PORT datad (999:999:999) (1031:1031:1031)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1200:1200:1200) (1213:1213:1213)) - (PORT datab (1200:1200:1200) (1267:1267:1267)) - (PORT datac (1388:1388:1388) (1438:1438:1438)) - (PORT datad (1062:1062:1062) (1080:1080:1080)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (289:289:289)) - (PORT datab (1424:1424:1424) (1519:1519:1519)) - (PORT datac (1231:1231:1231) (1361:1361:1361)) - (PORT datad (1161:1161:1161) (1174:1174:1174)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1401:1401:1401) (1470:1470:1470)) - (PORT datab (1263:1263:1263) (1395:1395:1395)) - (PORT datac (1392:1392:1392) (1486:1486:1486)) - (PORT datad (1170:1170:1170) (1275:1275:1275)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1216:1216:1216)) - (PORT datab (885:885:885) (940:940:940)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (1204:1204:1204) (1255:1255:1255)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1097:1097:1097) (1122:1122:1122)) - (PORT datab (1090:1090:1090) (1122:1122:1122)) - (PORT datac (822:822:822) (854:854:854)) - (PORT datad (1162:1162:1162) (1170:1170:1170)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2061:2061:2061) (2126:2126:2126)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (188:188:188) (228:228:228)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (713:713:713)) - (PORT datab (1147:1147:1147) (1201:1201:1201)) - (PORT datac (1368:1368:1368) (1378:1378:1378)) - (PORT datad (2367:2367:2367) (2456:2456:2456)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1281:1281:1281)) - (PORT datab (1931:1931:1931) (1944:1944:1944)) - (PORT datac (2031:2031:2031) (2070:2070:2070)) - (PORT datad (915:915:915) (939:939:939)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1564:1564:1564)) - (PORT datab (1498:1498:1498) (1596:1596:1596)) - (PORT datac (1145:1145:1145) (1174:1174:1174)) - (PORT datad (1597:1597:1597) (1652:1652:1652)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2065:2065:2065) (2130:2130:2130)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (186:186:186) (224:224:224)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1287:1287:1287) (1405:1405:1405)) - (PORT datac (1390:1390:1390) (1483:1483:1483)) - (PORT datad (846:846:846) (837:837:837)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (1473:1473:1473) (1565:1565:1565)) - (PORT datab (1334:1334:1334) (1380:1380:1380)) - (PORT datac (1334:1334:1334) (1385:1385:1385)) - (PORT datad (2128:2128:2128) (2227:2227:2227)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (1512:1512:1512) (1566:1566:1566)) - (PORT datab (1494:1494:1494) (1598:1598:1598)) - (PORT datac (2147:2147:2147) (2227:2227:2227)) - (PORT datad (2375:2375:2375) (2456:2456:2456)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1006:1006:1006)) - (PORT datab (252:252:252) (302:302:302)) - (PORT datac (1431:1431:1431) (1522:1522:1522)) - (PORT datad (550:550:550) (558:558:558)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT datac (1277:1277:1277) (1316:1316:1316)) - (PORT datad (783:783:783) (837:837:837)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT datac (1277:1277:1277) (1315:1315:1315)) - (PORT datad (782:782:782) (837:837:837)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (970:970:970)) - (PORT datab (849:849:849) (876:876:876)) - (PORT datac (844:844:844) (880:880:880)) - (PORT datad (817:817:817) (825:825:825)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (704:704:704)) - (PORT datab (865:865:865) (910:910:910)) - (PORT datac (523:523:523) (539:539:539)) - (PORT datad (595:595:595) (606:606:606)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1083:1083:1083)) - (PORT datab (1001:1001:1001) (1073:1073:1073)) - (PORT datac (2234:2234:2234) (2299:2299:2299)) - (PORT datad (1324:1324:1324) (1358:1358:1358)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1290:1290:1290) (1414:1414:1414)) - (PORT datab (1210:1210:1210) (1326:1326:1326)) - (PORT datad (865:865:865) (879:879:879)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1436:1436:1436) (1508:1508:1508)) - (PORT datab (1341:1341:1341) (1399:1399:1399)) - (PORT datac (811:811:811) (822:822:822)) - (PORT datad (799:799:799) (806:806:806)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (820:820:820)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (895:895:895)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1072:1072:1072) (1081:1081:1081)) - (PORT datad (178:178:178) (206:206:206)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1083:1083:1083)) - (PORT datab (597:597:597) (609:609:609)) - (PORT datac (359:359:359) (391:391:391)) - (PORT datad (345:345:345) (369:369:369)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1898:1898:1898) (2022:2022:2022)) - (PORT datab (1399:1399:1399) (1458:1458:1458)) - (PORT datac (1391:1391:1391) (1464:1464:1464)) - (PORT datad (884:884:884) (921:921:921)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1234:1234:1234)) - (PORT datab (655:655:655) (721:721:721)) - (PORT datac (847:847:847) (858:858:858)) - (PORT datad (637:637:637) (657:657:657)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1643:1643:1643) (1678:1678:1678)) - (PORT datab (752:752:752) (834:834:834)) - (PORT datac (210:210:210) (250:250:250)) - (PORT datad (1562:1562:1562) (1614:1614:1614)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1318:1318:1318)) - (PORT datab (637:637:637) (658:658:658)) - (PORT datac (1360:1360:1360) (1450:1450:1450)) - (PORT datad (829:829:829) (839:839:839)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1075:1075:1075) (1117:1117:1117)) - (PORT datab (2877:2877:2877) (2935:2935:2935)) - (PORT datac (886:886:886) (936:936:936)) - (PORT datad (1009:1009:1009) (1042:1042:1042)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (577:577:577)) - (PORT datab (393:393:393) (418:418:418)) - (PORT datac (657:657:657) (674:674:674)) - (PORT datad (1139:1139:1139) (1181:1181:1181)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (1015:1015:1015)) - (PORT datab (1153:1153:1153) (1237:1237:1237)) - (PORT datac (803:803:803) (848:848:848)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1529:1529:1529)) - (PORT datab (654:654:654) (724:724:724)) - (PORT datac (1129:1129:1129) (1194:1194:1194)) - (PORT datad (1002:1002:1002) (1004:1004:1004)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1878:1878:1878) (1960:1960:1960)) - (PORT datab (239:239:239) (278:278:278)) - (PORT datac (553:553:553) (571:571:571)) - (PORT datad (195:195:195) (230:230:230)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1012:1012:1012) (1026:1026:1026)) - (PORT datab (897:897:897) (948:948:948)) - (PORT datac (1362:1362:1362) (1415:1415:1415)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (1000:1000:1000) (1086:1086:1086)) - (PORT datab (995:995:995) (1065:1065:1065)) - (PORT datac (2238:2238:2238) (2300:2300:2300)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (219:219:219) (259:259:259)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1263:1263:1263) (1278:1278:1278)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT datab (1692:1692:1692) (1749:1749:1749)) - (PORT datac (1818:1818:1818) (1865:1865:1865)) - (PORT datad (2806:2806:2806) (2871:2871:2871)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (866:866:866)) - (PORT datab (833:833:833) (851:851:851)) - (PORT datac (1249:1249:1249) (1292:1292:1292)) - (PORT datad (642:642:642) (674:674:674)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1076:1076:1076) (1090:1090:1090)) - (PORT datab (534:534:534) (551:551:551)) - (PORT datac (1393:1393:1393) (1486:1486:1486)) - (PORT datad (1289:1289:1289) (1273:1273:1273)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1282:1282:1282)) - (PORT datab (856:856:856) (917:917:917)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (1273:1273:1273) (1262:1262:1262)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~5) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (464:464:464)) - (PORT datab (259:259:259) (312:312:312)) - (PORT datac (566:566:566) (577:577:577)) - (PORT datad (1091:1091:1091) (1086:1086:1086)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (264:264:264)) - (PORT datab (226:226:226) (267:267:267)) - (PORT datac (835:835:835) (893:893:893)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (902:902:902)) - (PORT datab (214:214:214) (258:258:258)) - (PORT datac (627:627:627) (643:643:643)) - (PORT datad (179:179:179) (209:209:209)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (947:947:947)) - (PORT datab (842:842:842) (867:867:867)) - (PORT datac (1638:1638:1638) (1683:1683:1683)) - (PORT datad (1289:1289:1289) (1310:1310:1310)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT datab (656:656:656) (711:711:711)) - (PORT datac (185:185:185) (224:224:224)) - (PORT datad (578:578:578) (600:600:600)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1423:1423:1423)) - (PORT datab (2851:2851:2851) (2926:2926:2926)) - (PORT datac (849:849:849) (863:863:863)) - (PORT datad (1061:1061:1061) (1093:1093:1093)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1170:1170:1170)) - (PORT datab (601:601:601) (615:615:615)) - (PORT datac (1404:1404:1404) (1456:1456:1456)) - (PORT datad (1793:1793:1793) (1847:1847:1847)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~1) - (DELAY - (ABSOLUTE - (PORT datac (1814:1814:1814) (1891:1891:1891)) - (PORT datad (1795:1795:1795) (1848:1848:1848)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (1004:1004:1004) (1080:1080:1080)) - (PORT datab (2180:2180:2180) (2304:2304:2304)) - (PORT datac (1407:1407:1407) (1457:1457:1457)) - (PORT datad (187:187:187) (216:216:216)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (827:827:827)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (571:571:571) (579:579:579)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (330:330:330) (360:360:360)) - (PORT datac (961:961:961) (1013:1013:1013)) - (PORT datad (316:316:316) (332:332:332)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (574:574:574)) - (PORT datab (974:974:974) (1006:1006:1006)) - (PORT datac (1521:1521:1521) (1565:1565:1565)) - (PORT datad (911:911:911) (967:967:967)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (959:959:959) (1022:1022:1022)) - (PORT datab (2463:2463:2463) (2519:2519:2519)) - (PORT datac (821:821:821) (867:867:867)) - (PORT datad (1278:1278:1278) (1305:1305:1305)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT datab (866:866:866) (899:899:899)) - (PORT datac (1252:1252:1252) (1262:1262:1262)) - (PORT datad (1770:1770:1770) (1779:1779:1779)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1721:1721:1721) (1769:1769:1769)) - (PORT datab (228:228:228) (269:269:269)) - (PORT datac (1179:1179:1179) (1235:1235:1235)) - (PORT datad (331:331:331) (348:348:348)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1430:1430:1430)) - (PORT datab (1364:1364:1364) (1427:1427:1427)) - (PORT datac (1357:1357:1357) (1421:1421:1421)) - (PORT datad (383:383:383) (447:447:447)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~46) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (397:397:397)) - (PORT datab (847:847:847) (861:861:861)) - (PORT datac (795:795:795) (828:828:828)) - (PORT datad (617:617:617) (641:641:641)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1272:1272:1272) (1346:1346:1346)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (1498:1498:1498) (1531:1531:1531)) - (PORT datad (615:615:615) (658:658:658)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1337:1337:1337)) - (PORT datab (1413:1413:1413) (1484:1484:1484)) - (PORT datac (2490:2490:2490) (2531:2531:2531)) - (PORT datad (2377:2377:2377) (2445:2445:2445)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1198:1198:1198)) - (PORT datab (1019:1019:1019) (1040:1040:1040)) - (PORT datac (1117:1117:1117) (1193:1193:1193)) - (PORT datad (1048:1048:1048) (1040:1040:1040)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1035:1035:1035) (1048:1048:1048)) - (PORT datac (832:832:832) (859:859:859)) - (PORT datad (1075:1075:1075) (1074:1074:1074)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1658:1658:1658) (1752:1752:1752)) - (PORT datab (227:227:227) (267:267:267)) - (PORT datac (836:836:836) (861:861:861)) - (PORT datad (1059:1059:1059) (1061:1061:1061)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1207:1207:1207) (1224:1224:1224)) - (PORT datab (1076:1076:1076) (1098:1098:1098)) - (PORT datac (1234:1234:1234) (1363:1363:1363)) - (PORT datad (1123:1123:1123) (1194:1194:1194)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1153:1153:1153)) - (PORT datab (883:883:883) (903:903:903)) - (PORT datac (1019:1019:1019) (1030:1030:1030)) - (PORT datad (1552:1552:1552) (1602:1602:1602)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (459:459:459)) - (PORT datab (260:260:260) (313:313:313)) - (PORT datac (2117:2117:2117) (2172:2172:2172)) - (PORT datad (1145:1145:1145) (1174:1174:1174)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (924:924:924)) - (PORT datab (944:944:944) (989:989:989)) - (PORT datac (818:818:818) (836:836:836)) - (PORT datad (1306:1306:1306) (1312:1312:1312)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1239:1239:1239) (1291:1291:1291)) - (PORT datab (845:845:845) (863:863:863)) - (PORT datac (660:660:660) (686:686:686)) - (PORT datad (209:209:209) (243:243:243)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1353:1353:1353)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (652:652:652) (692:692:692)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1077:1077:1077) (1079:1079:1079)) - (PORT datab (1553:1553:1553) (1612:1612:1612)) - (PORT datac (528:528:528) (548:548:548)) - (PORT datad (1098:1098:1098) (1101:1101:1101)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1222:1222:1222)) - (PORT datab (841:841:841) (865:865:865)) - (PORT datac (871:871:871) (881:881:881)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal76\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2191:2191:2191) (2270:2270:2270)) - (PORT datac (1460:1460:1460) (1513:1513:1513)) - (PORT datad (2376:2376:2376) (2457:2457:2457)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (593:593:593)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (973:973:973) (1039:1039:1039)) - (PORT datad (1320:1320:1320) (1362:1362:1362)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1357:1357:1357)) - (PORT datab (591:591:591) (616:616:616)) - (PORT datac (904:904:904) (951:951:951)) - (PORT datad (1110:1110:1110) (1164:1164:1164)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1093:1093:1093)) - (PORT datab (1135:1135:1135) (1200:1200:1200)) - (PORT datac (1356:1356:1356) (1424:1424:1424)) - (PORT datad (1069:1069:1069) (1066:1066:1066)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1221:1221:1221)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (565:565:565) (587:587:587)) - (PORT datad (562:562:562) (580:580:580)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1069:1069:1069) (1121:1121:1121)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (891:891:891)) - (PORT datab (347:347:347) (383:383:383)) - (PORT datac (826:826:826) (864:864:864)) - (PORT datad (612:612:612) (633:633:633)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) - (DELAY - (ABSOLUTE - (PORT dataa (1511:1511:1511) (1565:1565:1565)) - (PORT datab (1002:1002:1002) (1072:1072:1072)) - (PORT datac (2146:2146:2146) (2228:2228:2228)) - (PORT datad (2372:2372:2372) (2456:2456:2456)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (628:628:628)) - (PORT datab (1015:1015:1015) (1086:1086:1086)) - (PORT datac (812:812:812) (843:843:843)) - (PORT datad (1823:1823:1823) (1841:1841:1841)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1053:1053:1053) (1078:1078:1078)) - (PORT datac (1088:1088:1088) (1146:1146:1146)) - (PORT datad (1053:1053:1053) (1094:1094:1094)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (965:965:965)) - (PORT datab (360:360:360) (393:393:393)) - (PORT datac (898:898:898) (942:942:942)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1207:1207:1207)) - (PORT datad (783:783:783) (810:810:810)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1444:1444:1444)) - (PORT datab (239:239:239) (285:285:285)) - (PORT datac (2356:2356:2356) (2436:2436:2436)) - (PORT datad (1862:1862:1862) (1982:1982:1982)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (882:882:882)) - (PORT datab (883:883:883) (937:937:937)) - (PORT datac (862:862:862) (909:909:909)) - (PORT datad (1166:1166:1166) (1193:1193:1193)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1005:1005:1005)) - (PORT datab (1629:1629:1629) (1632:1632:1632)) - (PORT datac (1625:1625:1625) (1657:1657:1657)) - (PORT datad (820:820:820) (855:855:855)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (608:608:608)) - (PORT datab (1301:1301:1301) (1347:1347:1347)) - (PORT datac (835:835:835) (885:885:885)) - (PORT datad (1094:1094:1094) (1129:1129:1129)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1324:1324:1324)) - (PORT datab (244:244:244) (290:290:290)) - (PORT datac (1240:1240:1240) (1342:1342:1342)) - (PORT datad (1522:1522:1522) (1607:1607:1607)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (535:535:535) (553:553:553)) - (PORT datab (855:855:855) (900:900:900)) - (PORT datac (1042:1042:1042) (1039:1039:1039)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) - (DELAY - (ABSOLUTE - (PORT datac (1661:1661:1661) (1762:1762:1762)) - (PORT datad (1637:1637:1637) (1691:1691:1691)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1153:1153:1153) (1221:1221:1221)) - (PORT datab (325:325:325) (428:428:428)) - (PORT datac (291:291:291) (389:389:389)) - (PORT datad (900:900:900) (966:966:966)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1435:1435:1435) (1511:1511:1511)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (1302:1302:1302) (1383:1383:1383)) - (PORT datad (1377:1377:1377) (1421:1421:1421)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (2072:2072:2072) (2159:2159:2159)) - (PORT datab (852:852:852) (895:895:895)) - (PORT datac (1503:1503:1503) (1574:1574:1574)) - (PORT datad (869:869:869) (922:922:922)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2073:2073:2073) (2161:2161:2161)) - (PORT datab (1365:1365:1365) (1429:1429:1429)) - (PORT datac (1361:1361:1361) (1424:1424:1424)) - (PORT datad (868:868:868) (921:921:921)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (227:227:227) (269:269:269)) - (PORT datac (2122:2122:2122) (2174:2174:2174)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (967:967:967)) - (PORT datab (1235:1235:1235) (1321:1321:1321)) - (PORT datac (1156:1156:1156) (1232:1232:1232)) - (PORT datad (1333:1333:1333) (1382:1382:1382)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (678:678:678)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (793:793:793) (825:825:825)) - (PORT datad (525:525:525) (541:541:541)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (746:746:746) (753:753:753)) - (PORT datab (839:839:839) (854:854:854)) - (PORT datac (2499:2499:2499) (2525:2525:2525)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (649:649:649)) - (PORT datab (673:673:673) (698:698:698)) - (PORT datac (1857:1857:1857) (1882:1882:1882)) - (PORT datad (815:815:815) (827:827:827)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla21M3T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (954:954:954) (1034:1034:1034)) - (PORT datab (1346:1346:1346) (1415:1415:1415)) - (PORT datac (1134:1134:1134) (1205:1205:1205)) - (PORT datad (1151:1151:1151) (1236:1236:1236)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (266:266:266)) - (PORT datab (808:808:808) (831:831:831)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1186:1186:1186) (1209:1209:1209)) - (PORT datab (1217:1217:1217) (1245:1245:1245)) - (PORT datac (187:187:187) (225:225:225)) - (PORT datad (1535:1535:1535) (1550:1550:1550)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1416:1416:1416) (1502:1502:1502)) - (PORT datab (915:915:915) (940:940:940)) - (PORT datac (546:546:546) (561:561:561)) - (PORT datad (836:836:836) (851:851:851)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (679:679:679)) - (PORT datab (918:918:918) (941:941:941)) - (PORT datac (811:811:811) (853:853:853)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~56) - (DELAY - (ABSOLUTE - (PORT dataa (1381:1381:1381) (1411:1411:1411)) - (PORT datab (1205:1205:1205) (1259:1259:1259)) - (PORT datac (1133:1133:1133) (1200:1200:1200)) - (PORT datad (794:794:794) (827:827:827)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1104:1104:1104)) - (PORT datab (917:917:917) (972:972:972)) - (PORT datac (1630:1630:1630) (1678:1678:1678)) - (PORT datad (1138:1138:1138) (1191:1191:1191)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (396:396:396)) - (PORT datab (596:596:596) (609:609:609)) - (PORT datac (592:592:592) (638:638:638)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1221:1221:1221)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1390:1390:1390) (1467:1467:1467)) - (PORT datad (906:906:906) (957:957:957)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT datab (863:863:863) (888:888:888)) - (PORT datac (1081:1081:1081) (1086:1086:1086)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1069:1069:1069) (1125:1125:1125)) - (PORT datab (1326:1326:1326) (1330:1330:1330)) - (PORT datac (824:824:824) (865:865:865)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (651:651:651) (675:675:675)) - (PORT datac (1115:1115:1115) (1131:1131:1131)) - (PORT datad (605:605:605) (619:619:619)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (847:847:847) (876:876:876)) - (PORT datac (178:178:178) (214:214:214)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1974:1974:1974) (1981:1981:1981)) - (PORT datab (975:975:975) (1004:1004:1004)) - (PORT datac (555:555:555) (567:567:567)) - (PORT datad (222:222:222) (258:258:258)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1209:1209:1209)) - (PORT datab (822:822:822) (852:852:852)) - (PORT datad (1041:1041:1041) (1102:1102:1102)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT datab (230:230:230) (272:272:272)) - (PORT datac (1180:1180:1180) (1234:1234:1234)) - (PORT datad (331:331:331) (351:351:351)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (876:876:876)) - (PORT datab (848:848:848) (891:891:891)) - (PORT datac (372:372:372) (414:414:414)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (645:645:645) (672:672:672)) - (PORT datac (650:650:650) (701:701:701)) - (PORT datad (818:818:818) (838:838:838)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~24) - (DELAY - (ABSOLUTE - (PORT datab (922:922:922) (973:973:973)) - (PORT datac (2499:2499:2499) (2525:2525:2525)) - (PORT datad (1299:1299:1299) (1371:1371:1371)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (2359:2359:2359) (2446:2446:2446)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1190:1190:1190) (1243:1243:1243)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (647:647:647)) - (PORT datab (952:952:952) (1038:1038:1038)) - (PORT datac (638:638:638) (662:662:662)) - (PORT datad (900:900:900) (912:912:912)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1094:1094:1094) (1127:1127:1127)) - (PORT datab (1397:1397:1397) (1459:1459:1459)) - (PORT datad (906:906:906) (957:957:957)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (254:254:254)) - (PORT datac (646:646:646) (699:699:699)) - (PORT datad (616:616:616) (641:641:641)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1012:1012:1012) (1033:1033:1033)) - (PORT datab (938:938:938) (945:945:945)) - (PORT datac (1159:1159:1159) (1228:1228:1228)) - (PORT datad (772:772:772) (800:800:800)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1279:1279:1279)) - (PORT datab (848:848:848) (866:866:866)) - (PORT datac (873:873:873) (913:913:913)) - (PORT datad (1243:1243:1243) (1277:1277:1277)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1319:1319:1319) (1382:1382:1382)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datad (1205:1205:1205) (1312:1312:1312)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1570:1570:1570) (1551:1551:1551)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1595:1595:1595) (1715:1715:1715)) - (PORT datab (1294:1294:1294) (1371:1371:1371)) - (PORT datac (1004:1004:1004) (1038:1038:1038)) - (PORT datad (906:906:906) (911:911:911)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1761:1761:1761) (1889:1889:1889)) - (PORT datab (811:811:811) (844:844:844)) - (PORT datac (1795:1795:1795) (1847:1847:1847)) - (PORT datad (1249:1249:1249) (1332:1332:1332)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) - (DELAY - (ABSOLUTE - (PORT dataa (1181:1181:1181) (1246:1246:1246)) - (PORT datac (1625:1625:1625) (1694:1694:1694)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1591:1591:1591) (1710:1710:1710)) - (PORT datab (1290:1290:1290) (1369:1369:1369)) - (PORT datac (1001:1001:1001) (1034:1034:1034)) - (PORT datad (903:903:903) (909:909:909)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (418:418:418)) - (PORT datab (220:220:220) (260:260:260)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1853:1853:1853) (1930:1930:1930)) - (PORT datab (866:866:866) (895:895:895)) - (PORT datac (904:904:904) (995:995:995)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (890:890:890)) - (PORT datab (241:241:241) (287:287:287)) - (PORT datad (828:828:828) (856:856:856)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1570:1570:1570) (1551:1551:1551)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1644:1644:1644) (1718:1718:1718)) - (PORT datab (252:252:252) (337:337:337)) - (PORT datac (1019:1019:1019) (1061:1061:1061)) - (PORT datad (1503:1503:1503) (1529:1529:1529)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1644:1644:1644) (1721:1721:1721)) - (PORT datab (250:250:250) (336:336:336)) - (PORT datac (1017:1017:1017) (1058:1058:1058)) - (PORT datad (1502:1502:1502) (1528:1528:1528)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (1695:1695:1695) (1803:1803:1803)) - (PORT datab (1079:1079:1079) (1108:1108:1108)) - (PORT datad (1636:1636:1636) (1692:1692:1692)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (964:964:964)) - (PORT datab (1117:1117:1117) (1155:1155:1155)) - (PORT datac (847:847:847) (882:882:882)) - (PORT datad (1230:1230:1230) (1240:1240:1240)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1642:1642:1642) (1701:1701:1701)) - (PORT datab (572:572:572) (595:595:595)) - (PORT datac (1349:1349:1349) (1418:1418:1418)) - (PORT datad (963:963:963) (1040:1040:1040)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1276:1276:1276)) - (PORT datab (2633:2633:2633) (2709:2709:2709)) - (PORT datac (840:840:840) (856:856:856)) - (PORT datad (1612:1612:1612) (1688:1688:1688)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1048:1048:1048)) - (PORT datab (1092:1092:1092) (1102:1102:1102)) - (PORT datac (1017:1017:1017) (1026:1026:1026)) - (PORT datad (1126:1126:1126) (1151:1151:1151)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1575:1575:1575) (1575:1575:1575)) - (PORT datab (854:854:854) (905:905:905)) - (PORT datac (1275:1275:1275) (1268:1268:1268)) - (PORT datad (1126:1126:1126) (1150:1150:1150)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (953:953:953)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1125:1125:1125) (1154:1154:1154)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1186:1186:1186)) - (PORT datab (723:723:723) (778:778:778)) - (PORT datac (868:868:868) (874:874:874)) - (PORT datad (662:662:662) (702:702:702)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (661:661:661)) - (PORT datab (653:653:653) (679:679:679)) - (PORT datac (1088:1088:1088) (1120:1120:1120)) - (PORT datad (844:844:844) (861:861:861)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1358:1358:1358) (1407:1407:1407)) - (PORT datab (1429:1429:1429) (1470:1470:1470)) - (PORT datac (648:648:648) (694:694:694)) - (PORT datad (805:805:805) (811:811:811)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (899:899:899) (906:906:906)) - (PORT datac (1500:1500:1500) (1532:1532:1532)) - (PORT datad (344:344:344) (366:366:366)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1115:1115:1115) (1131:1131:1131)) - (PORT datab (1311:1311:1311) (1377:1377:1377)) - (PORT datac (1523:1523:1523) (1593:1593:1593)) - (PORT datad (673:673:673) (713:713:713)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1923:1923:1923) (1946:1946:1946)) - (PORT datab (578:578:578) (602:602:602)) - (PORT datac (330:330:330) (364:364:364)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1632:1632:1632) (1712:1712:1712)) - (PORT datad (797:797:797) (835:835:835)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1533:1533:1533) (1618:1618:1618)) - (PORT datab (1105:1105:1105) (1138:1138:1138)) - (PORT datac (1063:1063:1063) (1096:1096:1096)) - (PORT datad (863:863:863) (873:873:873)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1124:1124:1124) (1153:1153:1153)) - (PORT datab (875:875:875) (901:901:901)) - (PORT datac (798:798:798) (808:808:808)) - (PORT datad (840:840:840) (859:859:859)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1692:1692:1692) (1758:1758:1758)) - (PORT datab (882:882:882) (899:899:899)) - (PORT datac (1083:1083:1083) (1113:1113:1113)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (857:857:857)) - (PORT datab (911:911:911) (941:941:941)) - (PORT datac (735:735:735) (740:740:740)) - (PORT datad (1793:1793:1793) (1802:1802:1802)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1153:1153:1153)) - (PORT datab (911:911:911) (945:945:945)) - (PORT datac (1609:1609:1609) (1652:1652:1652)) - (PORT datad (634:634:634) (660:660:660)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (371:371:371)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (661:661:661)) - (PORT datab (427:427:427) (465:465:465)) - (PORT datac (811:811:811) (833:833:833)) - (PORT datad (1434:1434:1434) (1466:1466:1466)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (675:675:675)) - (PORT datab (859:859:859) (872:872:872)) - (PORT datac (195:195:195) (229:229:229)) - (PORT datad (824:824:824) (851:851:851)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1356:1356:1356) (1399:1399:1399)) - (PORT datab (909:909:909) (971:971:971)) - (PORT datac (891:891:891) (932:932:932)) - (PORT datad (863:863:863) (904:904:904)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (800:800:800) (818:818:818)) - (PORT datad (813:813:813) (827:827:827)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (929:929:929)) - (PORT datab (1473:1473:1473) (1554:1554:1554)) - (PORT datac (1068:1068:1068) (1115:1115:1115)) - (PORT datad (1152:1152:1152) (1195:1195:1195)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1450:1450:1450)) - (PORT datab (1187:1187:1187) (1213:1213:1213)) - (PORT datac (1496:1496:1496) (1563:1563:1563)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (463:463:463)) - (PORT datab (1145:1145:1145) (1195:1195:1195)) - (PORT datac (567:567:567) (580:580:580)) - (PORT datad (205:205:205) (235:235:235)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~18) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (574:574:574)) - (PORT datab (975:975:975) (1007:1007:1007)) - (PORT datac (788:788:788) (802:802:802)) - (PORT datad (615:615:615) (629:629:629)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (885:885:885)) - (PORT datac (833:833:833) (859:859:859)) - (PORT datad (981:981:981) (1007:1007:1007)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1081:1081:1081) (1079:1079:1079)) - (PORT datab (1175:1175:1175) (1237:1237:1237)) - (PORT datac (1696:1696:1696) (1766:1766:1766)) - (PORT datad (811:811:811) (830:830:830)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1042:1042:1042)) - (PORT datab (226:226:226) (267:267:267)) - (PORT datac (1144:1144:1144) (1155:1155:1155)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1188:1188:1188)) - (PORT datab (1934:1934:1934) (1940:1940:1940)) - (PORT datac (1296:1296:1296) (1334:1334:1334)) - (PORT datad (578:578:578) (600:600:600)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (940:940:940)) - (PORT datab (1391:1391:1391) (1410:1410:1410)) - (PORT datac (1892:1892:1892) (1901:1901:1901)) - (PORT datad (809:809:809) (833:833:833)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1282:1282:1282)) - (PORT datab (1357:1357:1357) (1344:1344:1344)) - (PORT datac (2031:2031:2031) (2065:2065:2065)) - (PORT datad (914:914:914) (936:936:936)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1691:1691:1691) (1754:1754:1754)) - (PORT datab (1639:1639:1639) (1688:1688:1688)) - (PORT datac (636:636:636) (648:648:648)) - (PORT datad (841:841:841) (860:860:860)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (928:928:928)) - (PORT datab (891:891:891) (922:922:922)) - (PORT datac (818:818:818) (835:835:835)) - (PORT datad (542:542:542) (539:539:539)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (251:251:251)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (622:622:622) (670:670:670)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1665:1665:1665) (1784:1784:1784)) - (PORT datab (936:936:936) (967:967:967)) - (PORT datac (550:550:550) (567:567:567)) - (PORT datad (2426:2426:2426) (2479:2479:2479)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1589:1589:1589) (1589:1589:1589)) - (PORT datab (1063:1063:1063) (1059:1059:1059)) - (PORT datac (602:602:602) (631:631:631)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1605:1605:1605) (1657:1657:1657)) - (PORT datab (745:745:745) (827:827:827)) - (PORT datac (1317:1317:1317) (1366:1366:1366)) - (PORT datad (580:580:580) (601:601:601)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (379:379:379)) - (PORT datab (1669:1669:1669) (1764:1764:1764)) - (PORT datac (608:608:608) (631:631:631)) - (PORT datad (1423:1423:1423) (1472:1472:1472)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (206:206:206) (249:249:249)) - (PORT datac (1262:1262:1262) (1297:1297:1297)) - (PORT datad (601:601:601) (619:619:619)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (980:980:980)) - (PORT datab (1374:1374:1374) (1464:1464:1464)) - (PORT datac (1362:1362:1362) (1377:1377:1377)) - (PORT datad (873:873:873) (940:940:940)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1364:1364:1364) (1428:1428:1428)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (939:939:939) (1008:1008:1008)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1314:1314:1314)) - (PORT datab (1644:1644:1644) (1723:1723:1723)) - (PORT datac (2121:2121:2121) (2229:2229:2229)) - (PORT datad (631:631:631) (664:664:664)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (1004:1004:1004) (1018:1018:1018)) - (PORT datac (1032:1032:1032) (1044:1044:1044)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1329:1329:1329)) - (PORT datab (1542:1542:1542) (1632:1632:1632)) - (PORT datac (2120:2120:2120) (2229:2229:2229)) - (PORT datad (1608:1608:1608) (1685:1685:1685)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (883:883:883)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (631:631:631) (648:648:648)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT dataa (959:959:959) (1010:1010:1010)) - (PORT datab (965:965:965) (1026:1026:1026)) - (PORT datac (1321:1321:1321) (1338:1338:1338)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (383:383:383)) - (PORT datab (556:556:556) (574:574:574)) - (PORT datac (617:617:617) (672:672:672)) - (PORT datad (620:620:620) (667:667:667)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1050:1050:1050) (1080:1080:1080)) - (PORT datab (1085:1085:1085) (1123:1123:1123)) - (PORT datac (631:631:631) (666:666:666)) - (PORT datad (1244:1244:1244) (1240:1240:1240)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1173:1173:1173)) - (PORT datab (1077:1077:1077) (1091:1091:1091)) - (PORT datac (1059:1059:1059) (1072:1072:1072)) - (PORT datad (867:867:867) (900:900:900)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (2348:2348:2348) (2418:2418:2418)) - (PORT datab (894:894:894) (928:928:928)) - (PORT datac (1117:1117:1117) (1190:1190:1190)) - (PORT datad (1061:1061:1061) (1094:1094:1094)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1088:1088:1088) (1112:1112:1112)) - (PORT datab (1393:1393:1393) (1455:1455:1455)) - (PORT datac (1360:1360:1360) (1442:1442:1442)) - (PORT datad (838:838:838) (904:904:904)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1309:1309:1309) (1334:1334:1334)) - (PORT datab (1115:1115:1115) (1156:1156:1156)) - (PORT datac (975:975:975) (981:981:981)) - (PORT datad (545:545:545) (567:567:567)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (916:916:916)) - (PORT datab (857:857:857) (882:882:882)) - (PORT datac (497:497:497) (506:506:506)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (653:653:653) (687:687:687)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1186:1186:1186)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (1263:1263:1263) (1298:1298:1298)) - (PORT datad (1072:1072:1072) (1097:1097:1097)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT datac (320:320:320) (345:345:345)) - (PORT datad (601:601:601) (640:640:640)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1048:1048:1048) (1073:1073:1073)) - (PORT datab (932:932:932) (967:967:967)) - (PORT datac (635:635:635) (661:661:661)) - (PORT datad (1246:1246:1246) (1245:1245:1245)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (867:867:867)) - (PORT datab (825:825:825) (873:873:873)) - (PORT datac (1335:1335:1335) (1356:1356:1356)) - (PORT datad (903:903:903) (932:932:932)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (619:619:619)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (352:352:352) (378:378:378)) - (PORT datad (359:359:359) (377:377:377)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1777:1777:1777) (1833:1833:1833)) - (PORT datab (638:638:638) (655:655:655)) - (PORT datac (1085:1085:1085) (1095:1095:1095)) - (PORT datad (690:690:690) (747:747:747)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (971:971:971)) - (PORT datab (1640:1640:1640) (1693:1693:1693)) - (PORT datac (630:630:630) (665:665:665)) - (PORT datad (1349:1349:1349) (1404:1404:1404)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1782:1782:1782) (1839:1839:1839)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1237:1237:1237)) - (PORT datab (1385:1385:1385) (1468:1468:1468)) - (PORT datac (1313:1313:1313) (1371:1371:1371)) - (PORT datad (1597:1597:1597) (1690:1690:1690)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1431:1431:1431)) - (PORT datab (1251:1251:1251) (1304:1304:1304)) - (PORT datac (978:978:978) (1037:1037:1037)) - (PORT datad (205:205:205) (235:235:235)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (665:665:665)) - (PORT datab (849:849:849) (891:891:891)) - (PORT datac (2131:2131:2131) (2211:2211:2211)) - (PORT datad (883:883:883) (916:916:916)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1057:1057:1057) (1071:1071:1071)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (1301:1301:1301) (1374:1374:1374)) - (PORT datad (1080:1080:1080) (1109:1109:1109)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1341:1341:1341)) - (PORT datab (1411:1411:1411) (1480:1480:1480)) - (PORT datac (2485:2485:2485) (2523:2523:2523)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (1015:1015:1015)) - (PORT datab (1276:1276:1276) (1286:1286:1286)) - (PORT datac (1041:1041:1041) (1074:1074:1074)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1659:1659:1659) (1680:1680:1680)) - (PORT datab (1983:1983:1983) (1979:1979:1979)) - (PORT datac (814:814:814) (828:828:828)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (620:620:620)) - (PORT datab (1556:1556:1556) (1605:1605:1605)) - (PORT datac (663:663:663) (735:735:735)) - (PORT datad (1158:1158:1158) (1200:1200:1200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (892:892:892)) - (PORT datab (650:650:650) (673:673:673)) - (PORT datac (827:827:827) (865:865:865)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datab (1450:1450:1450) (1524:1524:1524)) - (PORT datac (859:859:859) (903:903:903)) - (PORT datad (805:805:805) (828:828:828)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1413:1413:1413) (1432:1432:1432)) - (PORT datac (972:972:972) (1032:1032:1032)) - (PORT datad (1223:1223:1223) (1265:1265:1265)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1398:1398:1398) (1483:1483:1483)) - (PORT datab (793:793:793) (810:810:810)) - (PORT datac (834:834:834) (841:841:841)) - (PORT datad (1046:1046:1046) (1116:1116:1116)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1206:1206:1206) (1224:1224:1224)) - (PORT datab (1090:1090:1090) (1116:1116:1116)) - (PORT datac (823:823:823) (852:852:852)) - (PORT datad (846:846:846) (900:900:900)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1423:1423:1423)) - (PORT datab (2162:2162:2162) (2264:2264:2264)) - (PORT datac (1308:1308:1308) (1352:1352:1352)) - (PORT datad (1606:1606:1606) (1598:1598:1598)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT dataa (2969:2969:2969) (3028:3028:3028)) - (PORT datab (1383:1383:1383) (1410:1410:1410)) - (PORT datac (867:867:867) (890:890:890)) - (PORT datad (1031:1031:1031) (1060:1060:1060)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (873:873:873)) - (PORT datab (856:856:856) (927:927:927)) - (PORT datac (861:861:861) (945:945:945)) - (PORT datad (1273:1273:1273) (1296:1296:1296)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT datac (647:647:647) (708:708:708)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (657:657:657)) - (PORT datab (656:656:656) (681:681:681)) - (PORT datad (563:563:563) (590:590:590)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) - (DELAY - (ABSOLUTE - (PORT dataa (2183:2183:2183) (2259:2259:2259)) - (PORT datab (1443:1443:1443) (1461:1461:1461)) - (PORT datac (1476:1476:1476) (1531:1531:1531)) - (PORT datad (2369:2369:2369) (2448:2448:2448)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (888:888:888) (940:940:940)) - (PORT datac (180:180:180) (218:218:218)) - (PORT datad (1342:1342:1342) (1383:1383:1383)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (979:979:979)) - (PORT datab (1307:1307:1307) (1335:1335:1335)) - (PORT datac (1569:1569:1569) (1598:1598:1598)) - (PORT datad (1351:1351:1351) (1402:1402:1402)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1588:1588:1588) (1590:1590:1590)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (1447:1447:1447) (1548:1548:1548)) - (PORT datad (1128:1128:1128) (1202:1202:1202)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1194:1194:1194) (1317:1317:1317)) - (PORT datab (854:854:854) (878:878:878)) - (PORT datac (1359:1359:1359) (1448:1448:1448)) - (PORT datad (1273:1273:1273) (1293:1293:1293)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1455:1455:1455)) - (PORT datab (854:854:854) (894:894:894)) - (PORT datac (1306:1306:1306) (1349:1349:1349)) - (PORT datad (1522:1522:1522) (1658:1658:1658)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (959:959:959)) - (PORT datab (1138:1138:1138) (1207:1207:1207)) - (PORT datac (1131:1131:1131) (1224:1224:1224)) - (PORT datad (1323:1323:1323) (1402:1402:1402)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (255:255:255)) - (PORT datab (256:256:256) (308:308:308)) - (PORT datad (1120:1120:1120) (1146:1146:1146)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1059:1059:1059) (1092:1092:1092)) - (PORT datab (219:219:219) (256:256:256)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (650:650:650) (701:701:701)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (667:667:667)) - (PORT datab (901:901:901) (931:931:931)) - (PORT datac (540:540:540) (563:563:563)) - (PORT datad (857:857:857) (878:878:878)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1217:1217:1217) (1309:1309:1309)) - (PORT datab (896:896:896) (910:910:910)) - (PORT datad (323:323:323) (343:343:343)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) - (DELAY - (ABSOLUTE - (PORT datac (637:637:637) (698:698:698)) - (PORT datad (1041:1041:1041) (1047:1047:1047)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1152:1152:1152)) - (PORT datab (882:882:882) (936:936:936)) - (PORT datac (867:867:867) (916:916:916)) - (PORT datad (1167:1167:1167) (1192:1192:1192)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (1343:1343:1343) (1415:1415:1415)) - (PORT datab (863:863:863) (907:907:907)) - (PORT datac (1234:1234:1234) (1274:1274:1274)) - (PORT datad (1190:1190:1190) (1218:1218:1218)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (267:267:267)) - (PORT datab (1193:1193:1193) (1234:1234:1234)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (1617:1617:1617) (1667:1667:1667)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (648:648:648)) - (PORT datab (1169:1169:1169) (1211:1211:1211)) - (PORT datac (1162:1162:1162) (1233:1233:1233)) - (PORT datad (1039:1039:1039) (1067:1067:1067)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1394:1394:1394) (1460:1460:1460)) - (PORT datab (847:847:847) (897:897:897)) - (PORT datac (1269:1269:1269) (1283:1283:1283)) - (PORT datad (1192:1192:1192) (1220:1220:1220)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (951:951:951)) - (PORT datab (1328:1328:1328) (1352:1352:1352)) - (PORT datac (1165:1165:1165) (1242:1242:1242)) - (PORT datad (1298:1298:1298) (1384:1384:1384)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1456:1456:1456) (1555:1555:1555)) - (PORT datab (854:854:854) (904:904:904)) - (PORT datac (1388:1388:1388) (1439:1439:1439)) - (PORT datad (1058:1058:1058) (1093:1093:1093)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2187:2187:2187) (2263:2263:2263)) - (PORT datab (1443:1443:1443) (1466:1466:1466)) - (PORT datac (1474:1474:1474) (1528:1528:1528)) - (PORT datad (2372:2372:2372) (2450:2450:2450)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1657:1657:1657) (1774:1774:1774)) - (PORT datab (1786:1786:1786) (1846:1846:1846)) - (PORT datac (872:872:872) (889:889:889)) - (PORT datad (1122:1122:1122) (1155:1155:1155)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (220:220:220) (260:260:260)) - (PORT datac (605:605:605) (646:646:646)) - (PORT datad (201:201:201) (230:230:230)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (910:910:910)) - (PORT datab (1115:1115:1115) (1173:1173:1173)) - (PORT datac (633:633:633) (660:660:660)) - (PORT datad (609:609:609) (623:623:623)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1502:1502:1502) (1555:1555:1555)) - (PORT datab (1499:1499:1499) (1599:1599:1599)) - (PORT datac (2151:2151:2151) (2229:2229:2229)) - (PORT datad (2376:2376:2376) (2457:2457:2457)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1413:1413:1413)) - (PORT datab (1207:1207:1207) (1324:1324:1324)) - (PORT datac (1498:1498:1498) (1562:1562:1562)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (663:663:663)) - (PORT datab (881:881:881) (892:892:892)) - (PORT datac (1280:1280:1280) (1329:1329:1329)) - (PORT datad (1078:1078:1078) (1109:1109:1109)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1081:1081:1081)) - (PORT datab (1330:1330:1330) (1350:1350:1350)) - (PORT datac (582:582:582) (602:602:602)) - (PORT datad (537:537:537) (553:553:553)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1848:1848:1848) (1880:1880:1880)) - (PORT datab (2180:2180:2180) (2304:2304:2304)) - (PORT datac (1640:1640:1640) (1697:1697:1697)) - (PORT datad (863:863:863) (896:896:896)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (868:868:868) (867:867:867)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (598:598:598)) - (PORT datab (802:802:802) (820:820:820)) - (PORT datac (1301:1301:1301) (1375:1375:1375)) - (PORT datad (1078:1078:1078) (1110:1110:1110)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1503:1503:1503) (1526:1526:1526)) - (PORT datab (1125:1125:1125) (1234:1234:1234)) - (PORT datac (1152:1152:1152) (1259:1259:1259)) - (PORT datad (1668:1668:1668) (1700:1700:1700)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1196:1196:1196)) - (PORT datab (1078:1078:1078) (1085:1085:1085)) - (PORT datac (1139:1139:1139) (1248:1248:1248)) - (PORT datad (1075:1075:1075) (1078:1078:1078)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1587:1587:1587) (1586:1586:1586)) - (PORT datab (1357:1357:1357) (1457:1457:1457)) - (PORT datac (605:605:605) (629:629:629)) - (PORT datad (1350:1350:1350) (1406:1406:1406)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (965:965:965)) - (PORT datac (870:870:870) (904:904:904)) - (PORT datad (637:637:637) (685:685:685)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) - (DELAY - (ABSOLUTE - (PORT datab (1532:1532:1532) (1595:1595:1595)) - (PORT datac (1385:1385:1385) (1482:1482:1482)) - (PORT datad (1361:1361:1361) (1408:1408:1408)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1492:1492:1492)) - (PORT datab (2176:2176:2176) (2297:2297:2297)) - (PORT datac (1644:1644:1644) (1702:1702:1702)) - (PORT datad (189:189:189) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1346:1346:1346)) - (PORT datab (1414:1414:1414) (1480:1480:1480)) - (PORT datac (1381:1381:1381) (1465:1465:1465)) - (PORT datad (212:212:212) (245:245:245)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1469:1469:1469)) - (PORT datab (561:561:561) (576:576:576)) - (PORT datac (1184:1184:1184) (1295:1295:1295)) - (PORT datad (192:192:192) (226:226:226)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1213:1213:1213)) - (PORT datab (1152:1152:1152) (1227:1227:1227)) - (PORT datac (603:603:603) (634:634:634)) - (PORT datad (1386:1386:1386) (1420:1420:1420)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1233:1233:1233) (1322:1322:1322)) - (PORT datab (657:657:657) (691:691:691)) - (PORT datac (1116:1116:1116) (1184:1184:1184)) - (PORT datad (1102:1102:1102) (1139:1139:1139)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (532:532:532) (560:560:560)) - (PORT datab (854:854:854) (891:891:891)) - (PORT datac (574:574:574) (600:600:600)) - (PORT datad (884:884:884) (916:916:916)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (608:608:608)) - (PORT datab (616:616:616) (633:633:633)) - (PORT datac (546:546:546) (567:567:567)) - (PORT datad (554:554:554) (552:552:552)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (627:627:627)) - (PORT datab (671:671:671) (711:711:711)) - (PORT datac (886:886:886) (936:936:936)) - (PORT datad (193:193:193) (219:219:219)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (604:604:604)) - (PORT datab (626:626:626) (647:647:647)) - (PORT datac (331:331:331) (347:347:347)) - (PORT datad (1269:1269:1269) (1265:1265:1265)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (265:265:265)) - (PORT datab (866:866:866) (921:921:921)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (2801:2801:2801) (2867:2867:2867)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (573:573:573)) - (PORT datab (552:552:552) (571:571:571)) - (PORT datac (627:627:627) (646:646:646)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1249:1249:1249)) - (PORT datab (1099:1099:1099) (1160:1160:1160)) - (PORT datac (1066:1066:1066) (1128:1128:1128)) - (PORT datad (1043:1043:1043) (1088:1088:1088)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (864:864:864)) - (PORT datab (1474:1474:1474) (1492:1492:1492)) - (PORT datac (169:169:169) (201:201:201)) - (PORT datad (1333:1333:1333) (1332:1332:1332)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1133:1133:1133) (1156:1156:1156)) - (PORT datab (943:943:943) (976:976:976)) - (PORT datac (2031:2031:2031) (2065:2065:2065)) - (PORT datad (1174:1174:1174) (1236:1236:1236)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (772:772:772) (799:799:799)) - (PORT datab (238:238:238) (284:284:284)) - (PORT datad (276:276:276) (361:361:361)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1570:1570:1570) (1551:1551:1551)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (253:253:253)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (650:650:650) (701:701:701)) - (PORT datad (613:613:613) (639:639:639)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1544:1544:1544) (1572:1572:1572)) - (PORT datab (2184:2184:2184) (2256:2256:2256)) - (PORT datac (1616:1616:1616) (1684:1684:1684)) - (PORT datad (1753:1753:1753) (1842:1842:1842)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (470:470:470)) - (PORT datab (301:301:301) (397:397:397)) - (PORT datac (827:827:827) (872:872:872)) - (PORT datad (194:194:194) (230:230:230)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (1774:1774:1774) (1891:1891:1891)) - (PORT datac (1054:1054:1054) (1086:1086:1086)) - (PORT datad (1611:1611:1611) (1671:1671:1671)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (467:467:467)) - (PORT datab (300:300:300) (392:392:392)) - (PORT datac (830:830:830) (875:875:875)) - (PORT datad (194:194:194) (228:228:228)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1371:1371:1371)) - (PORT datac (1354:1354:1354) (1406:1406:1406)) - (PORT datad (1567:1567:1567) (1612:1612:1612)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1487:1487:1487) (1528:1528:1528)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (1088:1088:1088) (1107:1107:1107)) - (PORT datac (1737:1737:1737) (1857:1857:1857)) - (PORT datad (1611:1611:1611) (1671:1671:1671)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (774:774:774) (801:801:801)) - (PORT datab (240:240:240) (286:286:286)) - (PORT datad (277:277:277) (361:361:361)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1570:1570:1570) (1551:1551:1551)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (249:249:249) (338:338:338)) - (PORT datab (301:301:301) (396:396:396)) - (PORT datac (827:827:827) (870:870:870)) - (PORT datad (192:192:192) (226:226:226)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (1341:1341:1341) (1381:1381:1381)) - (PORT datac (1343:1343:1343) (1408:1408:1408)) - (PORT datad (1864:1864:1864) (1915:1915:1915)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1490:1490:1490) (1532:1532:1532)) - (PORT ena (1011:1011:1011) (1021:1021:1021)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (1344:1344:1344) (1389:1389:1389)) - (PORT datac (1354:1354:1354) (1405:1405:1405)) - (PORT datad (1567:1567:1567) (1612:1612:1612)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (688:688:688) (758:758:758)) - (PORT datad (231:231:231) (265:265:265)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) - (DELAY - (ABSOLUTE - (PORT datab (1770:1770:1770) (1887:1887:1887)) - (PORT datac (1056:1056:1056) (1087:1087:1087)) - (PORT datad (1611:1611:1611) (1672:1672:1672)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1232:1232:1232) (1238:1238:1238)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (250:250:250) (339:339:339)) - (PORT datab (302:302:302) (395:395:395)) - (PORT datac (827:827:827) (871:871:871)) - (PORT datad (193:193:193) (227:227:227)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT dataa (1094:1094:1094) (1112:1112:1112)) - (PORT datab (1656:1656:1656) (1746:1746:1746)) - (PORT datad (1643:1643:1643) (1702:1702:1702)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1228:1228:1228) (1234:1234:1234)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[7\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1098:1098:1098) (1117:1117:1117)) - (PORT datab (1660:1660:1660) (1751:1751:1751)) - (PORT datad (1641:1641:1641) (1701:1701:1701)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (470:470:470)) - (PORT datab (632:632:632) (690:690:690)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT datab (1384:1384:1384) (1453:1453:1453)) - (PORT datac (1177:1177:1177) (1238:1238:1238)) - (PORT datad (1861:1861:1861) (1918:1918:1918)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1249:1249:1249) (1247:1247:1247)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) - (DELAY - (ABSOLUTE - (PORT datac (1626:1626:1626) (1699:1699:1699)) - (PORT datad (1140:1140:1140) (1199:1199:1199)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1074:1074:1074)) - (PORT datab (1288:1288:1288) (1364:1364:1364)) - (PORT datac (1553:1553:1553) (1671:1671:1671)) - (PORT datad (197:197:197) (233:233:233)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (945:945:945) (961:961:961)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1074:1074:1074)) - (PORT datab (1290:1290:1290) (1364:1364:1364)) - (PORT datac (1553:1553:1553) (1671:1671:1671)) - (PORT datad (197:197:197) (233:233:233)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (954:954:954) (969:969:969)) - (PORT ena (1525:1525:1525) (1527:1527:1527)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (484:484:484)) - (PORT datab (425:425:425) (467:467:467)) - (PORT datad (626:626:626) (681:681:681)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1313:1313:1313) (1336:1336:1336)) - (PORT datab (1115:1115:1115) (1155:1155:1155)) - (PORT datac (846:846:846) (877:877:877)) - (PORT datad (549:549:549) (569:569:569)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (688:688:688) (722:722:722)) - (PORT datac (852:852:852) (924:924:924)) - (PORT datad (1090:1090:1090) (1119:1119:1119)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (731:731:731) (756:756:756)) - (PORT datab (605:605:605) (623:623:623)) - (PORT datac (1037:1037:1037) (1053:1053:1053)) - (PORT datad (615:615:615) (648:648:648)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1418:1418:1418)) - (PORT datab (1268:1268:1268) (1393:1393:1393)) - (PORT datac (1035:1035:1035) (1081:1081:1081)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (865:865:865)) - (PORT datab (604:604:604) (609:609:609)) - (PORT datac (361:361:361) (389:389:389)) - (PORT datad (562:562:562) (567:567:567)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (348:348:348) (370:370:370)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (374:374:374) (398:398:398)) - (PORT datac (200:200:200) (238:238:238)) - (PORT datad (1037:1037:1037) (1034:1034:1034)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (1695:1695:1695) (1808:1808:1808)) - (PORT datab (1079:1079:1079) (1111:1111:1111)) - (PORT datad (1637:1637:1637) (1694:1694:1694)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (954:954:954) (969:969:969)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1336:1336:1336) (1360:1360:1360)) - (PORT datab (1023:1023:1023) (1079:1079:1079)) - (PORT datad (387:387:387) (413:413:413)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) - (DELAY - (ABSOLUTE - (PORT dataa (1184:1184:1184) (1249:1249:1249)) - (PORT datac (1622:1622:1622) (1693:1693:1693)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1486:1486:1486) (1505:1505:1505)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1194:1194:1194) (1268:1268:1268)) - (PORT datab (218:218:218) (265:265:265)) - (PORT datac (1797:1797:1797) (1847:1847:1847)) - (PORT datad (778:778:778) (803:803:803)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1488:1488:1488) (1508:1508:1508)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1265:1265:1265)) - (PORT datab (809:809:809) (840:840:840)) - (PORT datac (1798:1798:1798) (1847:1847:1847)) - (PORT datad (901:901:901) (906:906:906)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (425:425:425) (488:488:488)) - (PORT datab (661:661:661) (684:684:684)) - (PORT datad (626:626:626) (645:645:645)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1241:1241:1241)) - (PORT datab (656:656:656) (708:708:708)) - (PORT datac (529:529:529) (548:548:548)) - (PORT datad (1121:1121:1121) (1153:1153:1153)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (885:885:885)) - (PORT datab (234:234:234) (275:275:275)) - (PORT datac (1127:1127:1127) (1169:1169:1169)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (895:895:895)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (620:620:620) (642:642:642)) - (PORT datad (1430:1430:1430) (1460:1460:1460)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (945:945:945) (977:977:977)) - (PORT datac (2012:2012:2012) (2094:2094:2094)) - (PORT datad (2028:2028:2028) (2075:2075:2075)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (908:908:908)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1079:1079:1079) (1127:1127:1127)) - (PORT datad (1095:1095:1095) (1160:1160:1160)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (411:411:411)) - (PORT datab (1153:1153:1153) (1193:1193:1193)) - (PORT datac (857:857:857) (889:889:889)) - (PORT datad (588:588:588) (637:637:637)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (396:396:396)) - (PORT datab (702:702:702) (729:729:729)) - (PORT datac (1594:1594:1594) (1637:1637:1637)) - (PORT datad (1586:1586:1586) (1641:1641:1641)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1079:1079:1079)) - (PORT datab (387:387:387) (417:417:417)) - (PORT datac (1143:1143:1143) (1154:1154:1154)) - (PORT datad (913:913:913) (945:945:945)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (875:875:875)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1359:1359:1359) (1374:1374:1374)) - (PORT datad (625:625:625) (673:673:673)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1137:1137:1137)) - (PORT datab (909:909:909) (928:928:928)) - (PORT datac (1315:1315:1315) (1300:1300:1300)) - (PORT datad (1235:1235:1235) (1240:1240:1240)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (894:894:894)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (637:637:637) (696:696:696)) - (PORT datad (856:856:856) (880:880:880)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (429:429:429)) - (PORT datab (817:817:817) (843:843:843)) - (PORT datac (348:348:348) (374:374:374)) - (PORT datad (816:816:816) (859:859:859)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1106:1106:1106)) - (PORT datab (968:968:968) (997:997:997)) - (PORT datad (1014:1014:1014) (1024:1024:1024)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (960:960:960) (979:979:979)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1010:1010:1010) (1032:1032:1032)) - (PORT datab (1291:1291:1291) (1372:1372:1372)) - (PORT datac (1001:1001:1001) (1035:1035:1035)) - (PORT datad (195:195:195) (231:231:231)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (960:960:960) (981:981:981)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (516:516:516)) - (PORT datab (242:242:242) (325:325:325)) - (PORT datad (666:666:666) (698:698:698)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (654:654:654)) - (PORT datab (376:376:376) (399:399:399)) - (PORT datac (339:339:339) (359:359:359)) - (PORT datad (619:619:619) (642:642:642)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_32) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1223:1223:1223)) - (PORT datac (1665:1665:1665) (1766:1766:1766)) - (PORT datad (1640:1640:1640) (1695:1695:1695)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (641:641:641)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (650:650:650)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (329:329:329) (364:364:364)) - (PORT datad (1296:1296:1296) (1415:1415:1415)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (875:875:875)) - (PORT datab (598:598:598) (631:631:631)) - (PORT datac (997:997:997) (1030:1030:1030)) - (PORT datad (1344:1344:1344) (1385:1385:1385)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1362:1362:1362) (1374:1374:1374)) - (PORT datab (257:257:257) (303:303:303)) - (PORT datac (883:883:883) (959:959:959)) - (PORT datad (791:791:791) (806:806:806)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (730:730:730)) - (PORT datab (897:897:897) (950:950:950)) - (PORT datac (580:580:580) (599:599:599)) - (PORT datad (1264:1264:1264) (1277:1277:1277)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1878:1878:1878) (1960:1960:1960)) - (PORT datab (219:219:219) (266:266:266)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (905:905:905)) - (PORT datab (841:841:841) (861:861:861)) - (PORT datac (543:543:543) (568:568:568)) - (PORT datad (823:823:823) (840:840:840)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1312:1312:1312) (1357:1357:1357)) - (PORT datab (722:722:722) (780:780:780)) - (PORT datac (1286:1286:1286) (1296:1296:1296)) - (PORT datad (837:837:837) (845:845:845)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT datab (1246:1246:1246) (1261:1261:1261)) - (PORT datad (833:833:833) (906:906:906)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1286:1286:1286)) - (PORT datab (1754:1754:1754) (1769:1769:1769)) - (PORT datac (837:837:837) (859:859:859)) - (PORT datad (1358:1358:1358) (1431:1431:1431)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1307:1307:1307) (1308:1308:1308)) - (PORT datab (904:904:904) (943:943:943)) - (PORT datac (1266:1266:1266) (1288:1288:1288)) - (PORT datad (1126:1126:1126) (1153:1153:1153)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1408:1408:1408) (1524:1524:1524)) - (PORT datab (680:680:680) (705:705:705)) - (PORT datac (1127:1127:1127) (1149:1149:1149)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1049:1049:1049)) - (PORT datab (650:650:650) (695:695:695)) - (PORT datac (845:845:845) (889:889:889)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1056:1056:1056) (1086:1086:1086)) - (PORT datab (717:717:717) (791:791:791)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1390:1390:1390) (1447:1447:1447)) - (PORT datab (655:655:655) (695:695:695)) - (PORT datac (619:619:619) (645:645:645)) - (PORT datad (1356:1356:1356) (1363:1363:1363)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (962:962:962)) - (PORT datab (371:371:371) (405:405:405)) - (PORT datac (871:871:871) (905:905:905)) - (PORT datad (638:638:638) (686:686:686)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1388:1388:1388) (1444:1444:1444)) - (PORT datab (1084:1084:1084) (1097:1097:1097)) - (PORT datac (1272:1272:1272) (1281:1281:1281)) - (PORT datad (1289:1289:1289) (1294:1294:1294)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (598:598:598) (633:633:633)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (415:415:415)) - (PORT datab (839:839:839) (862:862:862)) - (PORT datac (1562:1562:1562) (1555:1555:1555)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (677:677:677)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (613:613:613) (627:627:627)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1081:1081:1081) (1077:1077:1077)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (806:806:806) (805:805:805)) - (PORT datad (1609:1609:1609) (1578:1578:1578)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1314:1314:1314) (1360:1360:1360)) - (PORT datab (1187:1187:1187) (1205:1205:1205)) - (PORT datac (853:853:853) (859:859:859)) - (PORT datad (1083:1083:1083) (1098:1098:1098)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1148:1148:1148) (1204:1204:1204)) - (PORT datab (1090:1090:1090) (1150:1150:1150)) - (PORT datac (543:543:543) (565:565:565)) - (PORT datad (1569:1569:1569) (1616:1616:1616)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (965:965:965)) - (PORT datab (864:864:864) (896:896:896)) - (PORT datac (841:841:841) (877:877:877)) - (PORT datad (1188:1188:1188) (1242:1242:1242)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1354:1354:1354) (1373:1373:1373)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (584:584:584) (630:630:630)) - (PORT datad (616:616:616) (650:650:650)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) - (DELAY - (ABSOLUTE - (PORT datab (1114:1114:1114) (1151:1151:1151)) - (PORT datac (1301:1301:1301) (1377:1377:1377)) - (PORT datad (190:190:190) (223:223:223)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1353:1353:1353)) - (PORT datab (551:551:551) (570:570:570)) - (PORT datac (810:810:810) (824:824:824)) - (PORT datad (849:849:849) (850:850:850)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (953:953:953)) - (PORT datab (699:699:699) (719:719:719)) - (PORT datac (1041:1041:1041) (1078:1078:1078)) - (PORT datad (810:810:810) (816:816:816)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (728:728:728)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (2137:2137:2137) (2231:2231:2231)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (564:564:564) (579:579:579)) - (PORT datac (179:179:179) (218:218:218)) - (PORT datad (624:624:624) (668:668:668)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (409:409:409)) - (PORT datab (228:228:228) (268:268:268)) - (PORT datac (891:891:891) (924:924:924)) - (PORT datad (778:778:778) (782:782:782)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1327:1327:1327) (1395:1395:1395)) - (PORT datab (606:606:606) (624:624:624)) - (PORT datac (1604:1604:1604) (1594:1594:1594)) - (PORT datad (1332:1332:1332) (1391:1391:1391)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1332:1332:1332) (1395:1395:1395)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1220:1220:1220) (1288:1288:1288)) - (PORT datad (1332:1332:1332) (1391:1391:1391)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1505:1505:1505) (1528:1528:1528)) - (PORT datab (606:606:606) (623:623:623)) - (PORT datac (1605:1605:1605) (1594:1594:1594)) - (PORT datad (1666:1666:1666) (1703:1703:1703)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1507:1507:1507) (1528:1528:1528)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (1219:1219:1219) (1289:1289:1289)) - (PORT datad (1667:1667:1667) (1699:1699:1699)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT datab (1782:1782:1782) (1840:1840:1840)) - (PORT datac (1623:1623:1623) (1732:1732:1732)) - (PORT datad (1367:1367:1367) (1421:1421:1421)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1179:1179:1179)) - (PORT datab (683:683:683) (734:734:734)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (824:824:824) (862:862:862)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (696:696:696)) - (PORT datab (1115:1115:1115) (1173:1173:1173)) - (PORT datac (1249:1249:1249) (1271:1271:1271)) - (PORT datad (864:864:864) (897:897:897)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla83M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (954:954:954) (1048:1048:1048)) - (PORT datab (1410:1410:1410) (1485:1485:1485)) - (PORT datac (1262:1262:1262) (1303:1303:1303)) - (PORT datad (211:211:211) (243:243:243)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1903:1903:1903) (1982:1982:1982)) - (PORT datab (1495:1495:1495) (1600:1600:1600)) - (PORT datac (1370:1370:1370) (1425:1425:1425)) - (PORT datad (562:562:562) (590:590:590)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (936:936:936)) - (PORT datab (1395:1395:1395) (1443:1443:1443)) - (PORT datac (1396:1396:1396) (1464:1464:1464)) - (PORT datad (1184:1184:1184) (1234:1234:1234)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (873:873:873)) - (PORT datab (654:654:654) (689:689:689)) - (PORT datac (581:581:581) (627:627:627)) - (PORT datad (1036:1036:1036) (1049:1049:1049)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (913:913:913)) - (PORT datab (853:853:853) (885:885:885)) - (PORT datac (734:734:734) (757:757:757)) - (PORT datad (1072:1072:1072) (1090:1090:1090)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (977:977:977)) - (PORT datab (1312:1312:1312) (1339:1339:1339)) - (PORT datac (1751:1751:1751) (1781:1781:1781)) - (PORT datad (1355:1355:1355) (1406:1406:1406)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (1598:1598:1598) (1626:1626:1626)) - (PORT datac (733:733:733) (754:754:754)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (956:956:956)) - (PORT datab (1162:1162:1162) (1211:1211:1211)) - (PORT datac (817:817:817) (831:831:831)) - (PORT datad (1633:1633:1633) (1709:1709:1709)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1592:1592:1592) (1592:1592:1592)) - (PORT datab (1069:1069:1069) (1109:1109:1109)) - (PORT datac (604:604:604) (630:630:630)) - (PORT datad (1608:1608:1608) (1656:1656:1656)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (827:827:827) (838:838:838)) - (PORT datad (1607:1607:1607) (1659:1659:1659)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (923:923:923)) - (PORT datac (807:807:807) (833:833:833)) - (PORT datad (1031:1031:1031) (1073:1073:1073)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (944:944:944)) - (PORT datab (1092:1092:1092) (1109:1109:1109)) - (PORT datac (830:830:830) (831:831:831)) - (PORT datad (645:645:645) (690:690:690)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (206:206:206) (249:249:249)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2184:2184:2184) (2261:2261:2261)) - (PORT datab (1444:1444:1444) (1463:1463:1463)) - (PORT datac (1477:1477:1477) (1532:1532:1532)) - (PORT datad (2371:2371:2371) (2448:2448:2448)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (923:923:923)) - (PORT datab (649:649:649) (702:702:702)) - (PORT datac (1639:1639:1639) (1635:1635:1635)) - (PORT datad (1038:1038:1038) (1046:1046:1046)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1177:1177:1177)) - (PORT datac (1096:1096:1096) (1133:1133:1133)) - (PORT datad (879:879:879) (942:942:942)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1173:1173:1173)) - (PORT datad (880:880:880) (947:947:947)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1249:1249:1249) (1247:1247:1247)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1494:1494:1494) (1511:1511:1511)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1114:1114:1114)) - (PORT datab (1658:1658:1658) (1748:1748:1748)) - (PORT datad (1642:1642:1642) (1705:1705:1705)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1494:1494:1494) (1509:1509:1509)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (986:986:986) (1015:1015:1015)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (985:985:985) (1016:1016:1016)) - (PORT ena (1011:1011:1011) (1021:1021:1021)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (463:463:463)) - (PORT datab (690:690:690) (762:762:762)) - (PORT datad (231:231:231) (270:270:270)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (476:476:476)) - (PORT datab (334:334:334) (367:367:367)) - (PORT datad (605:605:605) (653:653:653)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1467:1467:1467) (1485:1485:1485)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1470:1470:1470) (1487:1487:1487)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (703:703:703)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (631:631:631) (649:649:649)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1172:1172:1172) (1191:1191:1191)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1170:1170:1170) (1191:1191:1191)) - (PORT ena (979:979:979) (971:971:971)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (478:478:478)) - (PORT datab (426:426:426) (468:468:468)) - (PORT datad (217:217:217) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (937:937:937) (963:963:963)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (936:936:936) (963:963:963)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (478:478:478) (511:511:511)) - (PORT datab (696:696:696) (733:733:733)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1472:1472:1472) (1486:1486:1486)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1364:1364:1364)) - (PORT datab (923:923:923) (944:944:944)) - (PORT datad (388:388:388) (413:413:413)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (369:369:369)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (609:609:609) (630:630:630)) - (PORT datad (598:598:598) (610:610:610)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (639:639:639) (662:662:662)) - (PORT datac (860:860:860) (871:871:871)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (907:907:907)) - (PORT datab (636:636:636) (661:661:661)) - (PORT datac (1864:1864:1864) (1958:1958:1958)) - (PORT datad (562:562:562) (575:575:575)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT datac (1315:1315:1315) (1300:1300:1300)) - (PORT datad (1081:1081:1081) (1091:1091:1091)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (898:898:898)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (876:876:876) (893:893:893)) - (PORT datad (322:322:322) (341:341:341)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) - (DELAY - (ABSOLUTE - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (1161:1161:1161) (1184:1184:1184)) - (PORT datad (812:812:812) (832:832:832)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (782:782:782)) - (PORT datab (844:844:844) (888:888:888)) - (PORT datac (822:822:822) (833:833:833)) - (PORT datad (616:616:616) (626:626:626)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (886:886:886)) - (PORT datab (785:785:785) (787:787:787)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (871:871:871) (921:921:921)) - (PORT datab (977:977:977) (1058:1058:1058)) - (PORT datac (1313:1313:1313) (1404:1404:1404)) - (PORT datad (550:550:550) (572:572:572)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (903:903:903)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (647:647:647) (670:670:670)) - (PORT datad (1082:1082:1082) (1119:1119:1119)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (866:866:866) (880:880:880)) - (PORT datac (2155:2155:2155) (2103:2103:2103)) - (PORT datad (1102:1102:1102) (1105:1105:1105)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) - (DELAY - (ABSOLUTE - (PORT datab (1215:1215:1215) (1288:1288:1288)) - (PORT datac (1012:1012:1012) (1021:1021:1021)) - (PORT datad (1676:1676:1676) (1698:1698:1698)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1183:1183:1183) (1291:1291:1291)) - (PORT datac (1379:1379:1379) (1462:1462:1462)) - (PORT datad (1949:1949:1949) (2061:2061:2061)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (274:274:274)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (861:861:861) (884:884:884)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) - (DELAY - (ABSOLUTE - (PORT datab (1057:1057:1057) (1075:1075:1075)) - (PORT datac (1012:1012:1012) (1024:1024:1024)) - (PORT datad (1178:1178:1178) (1252:1252:1252)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (813:813:813) (834:834:834)) - (PORT datab (536:536:536) (556:556:556)) - (PORT datac (647:647:647) (699:699:699)) - (PORT datad (1920:1920:1920) (2003:2003:2003)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (816:816:816) (843:843:843)) - (PORT datad (815:815:815) (860:860:860)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1243:1243:1243) (1347:1347:1347)) - (PORT datab (742:742:742) (820:820:820)) - (PORT datac (1318:1318:1318) (1367:1367:1367)) - (PORT datad (819:819:819) (850:850:850)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1271:1271:1271) (1341:1341:1341)) - (PORT datab (641:641:641) (696:696:696)) - (PORT datac (642:642:642) (694:694:694)) - (PORT datad (851:851:851) (894:894:894)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1716:1716:1716) (1784:1784:1784)) - (PORT datab (648:648:648) (675:675:675)) - (PORT datac (557:557:557) (579:579:579)) - (PORT datad (1053:1053:1053) (1059:1059:1059)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1642:1642:1642) (1687:1687:1687)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (861:861:861) (928:928:928)) - (PORT datad (1010:1010:1010) (1030:1030:1030)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT datab (857:857:857) (877:877:877)) - (PORT datac (352:352:352) (376:376:376)) - (PORT datad (316:316:316) (332:332:332)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (800:800:800) (834:834:834)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (625:625:625) (650:650:650)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1192:1192:1192)) - (PORT datab (1229:1229:1229) (1292:1292:1292)) - (PORT datac (1224:1224:1224) (1248:1248:1248)) - (PORT datad (1247:1247:1247) (1246:1246:1246)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT datab (1055:1055:1055) (1075:1075:1075)) - (PORT datac (1012:1012:1012) (1023:1023:1023)) - (PORT datad (1178:1178:1178) (1253:1253:1253)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (886:886:886) (892:892:892)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (260:260:260) (330:330:330)) - (PORT datab (937:937:937) (1002:1002:1002)) - (PORT datad (624:624:624) (648:648:648)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) - (DELAY - (ABSOLUTE - (PORT datab (1214:1214:1214) (1293:1293:1293)) - (PORT datac (1012:1012:1012) (1023:1023:1023)) - (PORT datad (1676:1676:1676) (1697:1697:1697)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (455:455:455) (484:484:484)) - (PORT datac (313:313:313) (331:331:331)) - (PORT datad (215:215:215) (284:284:284)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[11\]) - (DELAY - (ABSOLUTE - (PORT datac (1521:1521:1521) (1611:1611:1611)) - (PORT datad (628:628:628) (664:664:664)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (947:947:947)) - (PORT datab (886:886:886) (917:917:917)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (634:634:634) (652:652:652)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (884:884:884) (917:917:917)) - (PORT datac (1650:1650:1650) (1651:1651:1651)) - (PORT datad (1575:1575:1575) (1615:1615:1615)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT datac (657:657:657) (695:695:695)) + (PORT datad (609:609:609) (638:638:638)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12741,11 +11472,11 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) (DELAY (ABSOLUTE - (PORT dataa (1229:1229:1229) (1316:1316:1316)) - (PORT datab (1647:1647:1647) (1728:1728:1728)) - (PORT datad (893:893:893) (992:992:992)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (2470:2470:2470) (2664:2664:2664)) + (PORT datac (891:891:891) (959:959:959)) + (PORT datad (1997:1997:1997) (2087:2087:2087)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -12755,12 +11486,12 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~6) (DELAY (ABSOLUTE - (PORT dataa (659:659:659) (725:725:725)) - (PORT datab (648:648:648) (668:668:668)) - (PORT datac (628:628:628) (654:654:654)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (364:364:364) (394:394:394)) + (PORT datab (558:558:558) (580:580:580)) + (PORT datac (844:844:844) (879:879:879)) + (PORT datad (1124:1124:1124) (1141:1141:1141)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12771,12 +11502,12 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~7) (DELAY (ABSOLUTE - (PORT dataa (593:593:593) (609:609:609)) - (PORT datab (909:909:909) (956:956:956)) - (PORT datac (178:178:178) (217:217:217)) - (PORT datad (186:186:186) (218:218:218)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (1113:1113:1113) (1149:1149:1149)) + (PORT datab (1162:1162:1162) (1184:1184:1184)) + (PORT datac (794:794:794) (810:810:810)) + (PORT datad (642:642:642) (654:654:654)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12787,12 +11518,60 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~8) (DELAY (ABSOLUTE - (PORT dataa (355:355:355) (401:401:401)) - (PORT datab (402:402:402) (449:449:449)) - (PORT datac (820:820:820) (831:831:831)) - (PORT datad (752:752:752) (764:764:764)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (985:985:985) (1053:1053:1053)) + (PORT datab (1645:1645:1645) (1657:1657:1657)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1141:1141:1141) (1167:1167:1167)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1303:1303:1303)) + (PORT datab (1001:1001:1001) (1111:1111:1111)) + (PORT datac (655:655:655) (722:722:722)) + (PORT datad (1242:1242:1242) (1330:1330:1330)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (798:798:798)) + (PORT datab (653:653:653) (676:676:676)) + (PORT datac (834:834:834) (870:870:870)) + (PORT datad (1032:1032:1032) (1091:1091:1091)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (714:714:714) (749:749:749)) + (PORT datac (201:201:201) (236:236:236)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12803,12 +11582,10 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~11) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (662:662:662) (683:683:683)) - (PORT datad (340:340:340) (361:361:361)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (202:202:202) (246:246:246)) + (PORT datac (180:180:180) (218:218:218)) + (PORT datad (538:538:538) (562:562:562)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12819,12 +11596,12 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~12) (DELAY (ABSOLUTE - (PORT dataa (961:961:961) (1013:1013:1013)) - (PORT datab (967:967:967) (1028:1028:1028)) - (PORT datac (1321:1321:1321) (1338:1338:1338)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (1254:1254:1254) (1307:1307:1307)) + (PORT datab (845:845:845) (854:854:854)) + (PORT datac (835:835:835) (832:832:832)) + (PORT datad (874:874:874) (917:917:917)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12832,13 +11609,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[11\]) + (INSTANCE z80_\|address_latch_\|Q\[7\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1543:1543:1543)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1547:1547:1547)) - (PORT ena (2484:2484:2484) (2511:2511:2511)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2152:2152:2152) (2220:2220:2220)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -12850,25 +11627,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) (DELAY (ABSOLUTE - (PORT datab (470:470:470) (554:554:554)) - (PORT datad (546:546:546) (558:558:558)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (407:407:407) (434:434:434)) + (PORT datab (1814:1814:1814) (1895:1895:1895)) + (PORT datac (201:201:201) (236:236:236)) + (PORT datad (644:644:644) (699:699:699)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (INSTANCE z80_\|execute_\|fIOWrite\~0) (DELAY (ABSOLUTE - (PORT dataa (1101:1101:1101) (1125:1125:1125)) - (PORT datab (241:241:241) (280:280:280)) - (PORT datac (531:531:531) (534:534:534)) - (PORT datad (211:211:211) (243:243:243)) + (PORT dataa (1218:1218:1218) (1307:1307:1307)) + (PORT datab (2009:2009:2009) (2129:2129:2129)) + (PORT datac (1296:1296:1296) (1407:1407:1407)) + (PORT datad (2028:2028:2028) (2149:2149:2149)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (412:412:412)) + (PORT datab (213:213:213) (258:258:258)) + (PORT datac (1100:1100:1100) (1149:1149:1149)) + (PORT datad (1205:1205:1205) (1229:1229:1229)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -12878,325 +11675,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) (DELAY (ABSOLUTE - (PORT dataa (214:214:214) (265:265:265)) - (PORT datab (639:639:639) (662:662:662)) - (PORT datac (771:771:771) (809:809:809)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (425:425:425)) - (PORT datab (869:869:869) (876:876:876)) - (PORT datac (613:613:613) (636:636:636)) - (PORT datad (838:838:838) (883:883:883)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (892:892:892)) - (PORT datab (1629:1629:1629) (1659:1659:1659)) - (PORT datac (801:801:801) (804:804:804)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (727:727:727)) - (PORT datab (1163:1163:1163) (1238:1238:1238)) - (PORT datac (1317:1317:1317) (1383:1383:1383)) - (PORT datad (1177:1177:1177) (1218:1218:1218)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (675:675:675)) - (PORT datab (1149:1149:1149) (1207:1207:1207)) - (PORT datac (546:546:546) (569:569:569)) - (PORT datad (540:540:540) (557:557:557)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1351:1351:1351) (1376:1376:1376)) - (PORT datac (1969:1969:1969) (2008:2008:2008)) - (PORT datad (612:612:612) (623:623:623)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (691:691:691)) - (PORT datab (895:895:895) (991:991:991)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (904:904:904) (969:969:969)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1078:1078:1078) (1118:1118:1118)) - (PORT datab (877:877:877) (924:924:924)) - (PORT datac (1969:1969:1969) (2012:2012:2012)) - (PORT datad (1115:1115:1115) (1173:1173:1173)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (524:524:524) (547:547:547)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (870:870:870)) - (PORT datab (851:851:851) (899:899:899)) - (PORT datac (775:775:775) (808:808:808)) - (PORT datad (1274:1274:1274) (1316:1316:1316)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (335:335:335)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (1380:1380:1380) (1494:1494:1494)) - (PORT datad (889:889:889) (958:958:958)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (921:921:921) (956:956:956)) - (PORT datac (1664:1664:1664) (1793:1793:1793)) - (PORT datad (369:369:369) (393:393:393)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (599:599:599) (642:642:642)) - (PORT datac (331:331:331) (362:362:362)) - (PORT datad (1295:1295:1295) (1413:1413:1413)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (918:918:918)) - (PORT datab (1177:1177:1177) (1194:1194:1194)) - (PORT datac (842:842:842) (850:850:850)) - (PORT datad (848:848:848) (859:859:859)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1130:1130:1130)) - (PORT datab (637:637:637) (657:657:657)) - (PORT datac (1104:1104:1104) (1097:1097:1097)) - (PORT datad (1070:1070:1070) (1074:1074:1074)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1399:1399:1399)) - (PORT datab (803:803:803) (846:846:846)) - (PORT datac (1362:1362:1362) (1434:1434:1434)) - (PORT datad (634:634:634) (649:649:649)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (261:261:261) (318:318:318)) - (PORT datab (1093:1093:1093) (1122:1122:1122)) - (PORT datac (386:386:386) (431:431:431)) - (PORT datad (614:614:614) (629:629:629)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT datab (1164:1164:1164) (1272:1272:1272)) - (PORT datac (1188:1188:1188) (1298:1298:1298)) - (PORT datad (1142:1142:1142) (1245:1245:1245)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (218:218:218) (264:264:264)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (930:930:930) (1005:1005:1005)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datab (670:670:670) (725:725:725)) - (PORT datac (805:805:805) (823:823:823)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (865:865:865)) - (PORT datab (246:246:246) (287:287:287)) - (PORT datac (809:809:809) (835:835:835)) - (PORT datad (820:820:820) (826:826:826)) + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (1709:1709:1709) (1797:1797:1797)) + (PORT datac (549:549:549) (562:562:562)) + (PORT datad (173:173:173) (198:198:198)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13204,60 +11691,36 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) (DELAY (ABSOLUTE - (PORT dataa (887:887:887) (944:944:944)) - (PORT datab (863:863:863) (874:874:874)) - (PORT datac (516:516:516) (518:518:518)) - (PORT datad (815:815:815) (850:850:850)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (988:988:988) (1021:1021:1021)) + (PORT datac (1126:1126:1126) (1145:1145:1145)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (230:230:230) (272:272:272)) - (PORT datac (526:526:526) (532:532:532)) - (PORT datad (324:324:324) (346:346:346)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (619:619:619)) - (PORT datab (547:547:547) (561:561:561)) - (PORT datac (671:671:671) (706:706:706)) - (PORT datad (575:575:575) (586:586:586)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1002:1002:1002) (1072:1072:1072)) + (PORT datad (1126:1126:1126) (1143:1143:1143)) + (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1548:1548:1548)) + (PORT clk (1541:1541:1541) (1557:1557:1557)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13268,15 +11731,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) (DELAY (ABSOLUTE - (PORT dataa (1106:1106:1106) (1193:1193:1193)) - (PORT datab (918:918:918) (987:987:987)) - (PORT datac (1676:1676:1676) (1682:1682:1682)) - (PORT datad (1235:1235:1235) (1230:1230:1230)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (1546:1546:1546) (1602:1602:1602)) + (PORT datac (1206:1206:1206) (1268:1268:1268)) + (PORT datad (1073:1073:1073) (1099:1099:1099)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13284,61 +11745,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) (DELAY (ABSOLUTE - (PORT datab (1646:1646:1646) (1719:1719:1719)) - (PORT datac (619:619:619) (671:671:671)) - (PORT datad (338:338:338) (363:363:363)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1205:1205:1205) (1315:1315:1315)) - (PORT datab (1158:1158:1158) (1233:1233:1233)) - (PORT datac (801:801:801) (812:812:812)) - (PORT datad (548:548:548) (576:576:576)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (925:925:925)) - (PORT datab (1268:1268:1268) (1390:1390:1390)) - (PORT datac (1034:1034:1034) (1081:1081:1081)) - (PORT datad (1306:1306:1306) (1372:1372:1372)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (252:252:252)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1118:1118:1118) (1138:1138:1138)) - (PORT datad (3065:3065:3065) (3150:3150:3150)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (1543:1543:1543) (1602:1602:1602)) + (PORT datac (1215:1215:1215) (1279:1279:1279)) + (PORT datad (985:985:985) (1033:1033:1033)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13346,88 +11759,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~42) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) (DELAY (ABSOLUTE - (PORT dataa (888:888:888) (963:963:963)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1310:1310:1310) (1401:1401:1401)) - (PORT datad (1330:1330:1330) (1375:1375:1375)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1040:1040:1040)) - (PORT datab (575:575:575) (591:591:591)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT dataa (1169:1169:1169) (1196:1196:1196)) - (PORT datac (1218:1218:1218) (1241:1241:1241)) - (PORT datad (1390:1390:1390) (1409:1409:1409)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT datab (1254:1254:1254) (1277:1277:1277)) - (PORT datac (1273:1273:1273) (1283:1283:1283)) - (PORT datad (1391:1391:1391) (1411:1411:1411)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1268:1268:1268)) - (PORT datab (1448:1448:1448) (1562:1562:1562)) - (PORT datac (450:450:450) (488:488:488)) - (PORT datad (400:400:400) (427:427:427)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT datab (1254:1254:1254) (1276:1276:1276)) - (PORT datac (1273:1273:1273) (1282:1282:1282)) - (PORT datad (1390:1390:1390) (1410:1410:1410)) + (PORT datab (1542:1542:1542) (1602:1602:1602)) + (PORT datac (1217:1217:1217) (1279:1279:1279)) + (PORT datad (1074:1074:1074) (1100:1100:1100)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13436,11 +11773,705 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (719:719:719) (755:755:755)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1413:1413:1413) (1448:1448:1448)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT datab (1547:1547:1547) (1607:1607:1607)) + (PORT datac (1199:1199:1199) (1261:1261:1261)) + (PORT datad (990:990:990) (1037:1037:1037)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1413:1413:1413) (1447:1447:1447)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (916:916:916)) + (PORT datab (971:971:971) (1024:1024:1024)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT datab (1381:1381:1381) (1428:1428:1428)) + (PORT datac (1185:1185:1185) (1207:1207:1207)) + (PORT datad (589:589:589) (605:605:605)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (726:726:726) (753:753:753)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (407:407:407)) + (PORT datab (224:224:224) (272:272:272)) + (PORT datac (222:222:222) (301:301:301)) + (PORT datad (1218:1218:1218) (1299:1299:1299)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT datab (1209:1209:1209) (1234:1234:1234)) + (PORT datac (637:637:637) (665:665:665)) + (PORT datad (1346:1346:1346) (1393:1393:1393)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT datab (1212:1212:1212) (1239:1239:1239)) + (PORT datac (637:637:637) (665:665:665)) + (PORT datad (1342:1342:1342) (1391:1391:1391)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (725:725:725) (752:752:752)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (261:261:261) (314:314:314)) + (PORT datad (232:232:232) (270:270:270)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT datac (898:898:898) (941:941:941)) + (PORT datad (1326:1326:1326) (1381:1381:1381)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (770:770:770)) + (PORT datab (1175:1175:1175) (1215:1215:1215)) + (PORT datac (195:195:195) (238:238:238)) + (PORT datad (1436:1436:1436) (1519:1519:1519)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1192:1192:1192) (1227:1227:1227)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (765:765:765)) + (PORT datab (1172:1172:1172) (1214:1214:1214)) + (PORT datac (195:195:195) (237:237:237)) + (PORT datad (1438:1438:1438) (1518:1518:1518)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1193:1193:1193) (1225:1225:1225)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (505:505:505)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (640:640:640) (663:663:663)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (658:658:658)) + (PORT datab (950:950:950) (994:994:994)) + (PORT datad (672:672:672) (698:698:698)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (1673:1673:1673) (1678:1678:1678)) + (PORT ena (1499:1499:1499) (1507:1507:1507)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (674:674:674)) + (PORT datab (1409:1409:1409) (1424:1424:1424)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1144:1144:1144) (1180:1180:1180)) + (PORT datab (1171:1171:1171) (1213:1213:1213)) + (PORT datac (195:195:195) (238:238:238)) + (PORT datad (664:664:664) (715:715:715)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1225:1225:1225) (1263:1263:1263)) + (PORT ena (1220:1220:1220) (1214:1214:1214)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (962:962:962)) + (PORT datab (414:414:414) (473:473:473)) + (PORT datac (913:913:913) (963:963:963)) + (PORT datad (609:609:609) (629:629:629)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (973:973:973)) + (PORT datab (938:938:938) (1019:1019:1019)) + (PORT datac (1135:1135:1135) (1179:1179:1179)) + (PORT datad (378:378:378) (412:412:412)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT datab (929:929:929) (993:993:993)) + (PORT datac (1324:1324:1324) (1357:1357:1357)) + (PORT datad (891:891:891) (947:947:947)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1168:1168:1168) (1265:1265:1265)) + (PORT datab (1178:1178:1178) (1216:1216:1216)) + (PORT datac (195:195:195) (239:239:239)) + (PORT datad (671:671:671) (719:719:719)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (1674:1674:1674) (1676:1676:1676)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT dataa (1791:1791:1791) (1805:1805:1805)) + (PORT datab (916:916:916) (986:986:986)) + (PORT datad (905:905:905) (958:958:958)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1226:1226:1226) (1265:1265:1265)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (433:433:433) (465:465:465)) + (PORT datab (634:634:634) (665:665:665)) + (PORT datad (357:357:357) (410:410:410)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (1721:1721:1721) (1780:1780:1780)) + (PORT datab (1171:1171:1171) (1225:1225:1225)) + (PORT datad (792:792:792) (797:797:797)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1407:1407:1407) (1434:1434:1434)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (841:841:841) (868:868:868)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT datab (1032:1032:1032) (1065:1065:1065)) + (PORT datac (905:905:905) (951:951:951)) + (PORT datad (876:876:876) (937:937:937)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (468:468:468)) + (PORT datab (590:590:590) (630:630:630)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (530:530:530) (540:540:540)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (699:699:699)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (780:780:780) (810:810:810)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (397:397:397)) + (PORT datab (625:625:625) (654:654:654)) + (PORT datac (1393:1393:1393) (1416:1416:1416)) + (PORT datad (618:618:618) (673:673:673)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1402:1402:1402) (1441:1441:1441)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (264:264:264)) + (PORT datab (1232:1232:1232) (1270:1270:1270)) + (PORT datad (658:658:658) (688:688:688)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (671:671:671) (703:703:703)) + (PORT datac (1147:1147:1147) (1188:1188:1188)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1460:1460:1460) (1492:1492:1492)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1460:1460:1460) (1491:1491:1491)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (262:262:262) (315:315:315)) + (PORT datad (233:233:233) (271:271:271)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1185:1185:1185) (1213:1213:1213)) (PORT ena (816:816:816) (813:813:813)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13452,41 +12483,131 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1450:1450:1450) (1474:1474:1474)) - (PORT datab (244:244:244) (290:290:290)) - (PORT datad (1246:1246:1246) (1245:1245:1245)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1182:1182:1182) (1227:1227:1227)) + (PORT datab (1541:1541:1541) (1602:1602:1602)) + (PORT datad (1074:1074:1074) (1100:1100:1100)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT dataa (1168:1168:1168) (1197:1197:1197)) - (PORT datac (1221:1221:1221) (1244:1244:1244)) - (PORT datad (1391:1391:1391) (1414:1414:1414)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1483:1483:1483) (1519:1519:1519)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (688:688:688)) + (PORT datab (1088:1088:1088) (1097:1097:1097)) + (PORT datad (940:940:940) (980:980:980)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1236:1236:1236) (1247:1247:1247)) + (PORT ena (1220:1220:1220) (1214:1214:1214)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1237:1237:1237) (1246:1246:1246)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (696:696:696)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (367:367:367) (395:395:395)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1461:1461:1461) (1534:1534:1534)) + (PORT ena (1505:1505:1505) (1518:1518:1518)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (347:347:347) (372:372:372)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1021:1021:1021) (1037:1037:1037)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13496,14 +12617,217 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT datab (369:369:369) (407:407:407)) - (PORT datac (447:447:447) (483:483:483)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1458:1458:1458) (1530:1530:1530)) + (PORT ena (1407:1407:1407) (1382:1382:1382)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (499:499:499)) + (PORT datab (652:652:652) (676:676:676)) + (PORT datad (827:827:827) (837:837:837)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (1256:1256:1256)) + (PORT datab (919:919:919) (944:944:944)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (939:939:939) (964:964:964)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (491:491:491)) + (PORT datab (1133:1133:1133) (1178:1178:1178)) + (PORT datad (539:539:539) (559:559:559)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1719:1719:1719) (1765:1765:1765)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1719:1719:1719) (1768:1768:1768)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (470:470:470)) + (PORT datab (585:585:585) (623:623:623)) + (PORT datad (216:216:216) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (635:635:635)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (344:344:344) (368:368:368)) + (PORT datad (597:597:597) (607:607:607)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1235:1235:1235)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (1104:1104:1104) (1151:1151:1151)) + (PORT datad (820:820:820) (839:839:839)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1589:1589:1589) (1608:1608:1608)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1198:1198:1198)) + (PORT datab (697:697:697) (724:724:724)) + (PORT datad (1194:1194:1194) (1230:1230:1230)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (243:243:243) (325:325:325)) + (PORT datac (706:706:706) (737:737:737)) + (PORT datad (842:842:842) (876:876:876)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (985:985:985)) + (PORT datab (912:912:912) (985:985:985)) + (PORT datac (1500:1500:1500) (1547:1547:1547)) + (PORT datad (662:662:662) (730:730:730)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13518,24 +12842,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~0) - (DELAY - (ABSOLUTE - (PORT datab (663:663:663) (741:741:741)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~14) (DELAY (ABSOLUTE - (PORT datab (410:410:410) (485:485:485)) + (PORT datab (1393:1393:1393) (1462:1462:1462)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13549,9 +12861,9 @@ (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT datab (1265:1265:1265) (1315:1315:1315)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (265:265:265) (352:352:352)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13563,9 +12875,9 @@ (INSTANCE ula_\|video_\|vga_hc\~2) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datad (382:382:382) (409:409:409)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datac (830:830:830) (872:872:872)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13575,13 +12887,13 @@ (INSTANCE ula_\|video_\|vga_hc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) - (PORT asdata (1389:1389:1389) (1382:1382:1382)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL @@ -13589,8 +12901,8 @@ (INSTANCE ula_\|video_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datab (1519:1519:1519) (1605:1605:1605)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datad (660:660:660) (722:722:722)) + (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -13600,8 +12912,8 @@ (INSTANCE ula_\|video_\|vga_hc\~1) (DELAY (ABSOLUTE - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (382:382:382) (407:407:407)) + (PORT datab (230:230:230) (272:272:272)) + (PORT datad (560:560:560) (588:588:588)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13612,59 +12924,23 @@ (INSTANCE ula_\|video_\|vga_hc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) - (PORT asdata (663:663:663) (688:688:688)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~0) + (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT dataa (988:988:988) (1078:1078:1078)) - (PORT datab (705:705:705) (785:785:785)) - (PORT datac (1215:1215:1215) (1307:1307:1307)) - (PORT datad (682:682:682) (765:765:765)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1486:1486:1486)) - (PORT datab (644:644:644) (703:703:703)) - (PORT datac (1172:1172:1172) (1220:1220:1220)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1557:1557:1557) (1645:1645:1645)) - (PORT datab (1221:1221:1221) (1283:1283:1283)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (1160:1160:1160) (1229:1229:1229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (1071:1071:1071) (1110:1110:1110)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13674,8 +12950,8 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (310:310:310) (328:328:328)) - (PORT datad (203:203:203) (232:232:232)) + (PORT datac (830:830:830) (865:865:865)) + (PORT datad (903:903:903) (941:941:941)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13687,72 +12963,6 @@ (DELAY (ABSOLUTE (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT asdata (912:912:912) (917:917:917)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~2) - (DELAY - (ABSOLUTE - (PORT datab (703:703:703) (787:787:787)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (948:948:948) (966:966:966)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1069:1069:1069)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (871:871:871) (884:884:884)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13763,10 +12973,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~6) + (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (1202:1202:1202) (1248:1248:1248)) + (PORT datab (672:672:672) (727:727:727)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13775,12 +12985,88 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (590:590:590) (612:612:612)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT datab (410:410:410) (485:485:485)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT asdata (663:663:663) (679:679:679)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (693:693:693) (745:745:745)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (558:558:558) (581:581:581)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13794,9 +13080,9 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (408:408:408) (481:481:481)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (1094:1094:1094) (1127:1127:1127)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13808,8 +13094,8 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) - (PORT asdata (916:916:916) (926:926:926)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT asdata (662:662:662) (678:678:678)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13817,12 +13103,59 @@ (HOLD asdata (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1251:1251:1251) (1340:1340:1340)) + (PORT datab (983:983:983) (1062:1062:1062)) + (PORT datac (978:978:978) (1050:1050:1050)) + (PORT datad (282:282:282) (366:366:366)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (737:737:737)) + (PORT datab (1394:1394:1394) (1464:1464:1464)) + (PORT datad (941:941:941) (937:937:937)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (523:523:523)) + (PORT datab (684:684:684) (758:758:758)) + (PORT datac (646:646:646) (716:716:716)) + (PORT datad (570:570:570) (576:576:576)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (1410:1410:1410) (1451:1451:1451)) + (PORT dataa (684:684:684) (734:734:734)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13836,9 +13169,9 @@ (INSTANCE ula_\|video_\|vga_hc\~0) (DELAY (ABSOLUTE - (PORT dataa (344:344:344) (371:371:371)) - (PORT datad (377:377:377) (403:403:403)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datac (833:833:833) (875:875:875)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13848,13 +13181,13 @@ (INSTANCE ula_\|video_\|vga_hc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) - (PORT asdata (923:923:923) (933:933:933)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL @@ -13862,7 +13195,7 @@ (INSTANCE ula_\|video_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (424:424:424) (506:506:506)) + (PORT dataa (629:629:629) (686:686:686)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13876,8 +13209,8 @@ (INSTANCE ula_\|video_\|vga_hc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) - (PORT asdata (661:661:661) (685:685:685)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT asdata (516:516:516) (547:547:547)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13890,8 +13223,8 @@ (INSTANCE ula_\|video_\|vga_hc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1554:1554:1554)) - (PORT asdata (841:841:841) (851:851:851)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT asdata (869:869:869) (872:872:872)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13904,48 +13237,19 @@ (INSTANCE ula_\|video_\|Add1\~0) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1310:1310:1310)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (720:720:720) (795:795:795)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (755:755:755) (812:812:812)) - (PORT datab (720:720:720) (780:780:780)) - (PORT datad (327:327:327) (342:342:342)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~2) (DELAY (ABSOLUTE - (PORT dataa (471:471:471) (547:547:547)) + (PORT dataa (707:707:707) (782:782:782)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13959,9 +13263,9 @@ (INSTANCE ula_\|video_\|Add1\~4) (DELAY (ABSOLUTE - (PORT datab (448:448:448) (518:518:518)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (679:679:679) (747:747:747)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13973,9 +13277,9 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (753:753:753) (811:811:811)) - (PORT datab (340:340:340) (362:362:362)) - (PORT datad (681:681:681) (733:733:733)) + (PORT dataa (517:517:517) (564:564:564)) + (PORT datab (595:595:595) (609:609:609)) + (PORT datad (899:899:899) (922:922:922)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13988,7 +13292,7 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14002,7 +13306,7 @@ (INSTANCE ula_\|video_\|Add1\~6) (DELAY (ABSOLUTE - (PORT dataa (680:680:680) (744:744:744)) + (PORT dataa (712:712:712) (782:782:782)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -14016,12 +13320,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (756:756:756) (813:813:813)) - (PORT datab (721:721:721) (780:780:780)) - (PORT datad (306:306:306) (319:319:319)) + (PORT dataa (616:616:616) (648:648:648)) + (PORT datab (645:645:645) (692:692:692)) + (PORT datac (679:679:679) (747:747:747)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14031,13 +13336,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1361:1361:1361) (1352:1352:1352)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -14045,9 +13350,9 @@ (INSTANCE ula_\|video_\|Add1\~8) (DELAY (ABSOLUTE - (PORT dataa (436:436:436) (515:515:515)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (680:680:680) (762:762:762)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -14059,11 +13364,11 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) (DELAY (ABSOLUTE - (PORT dataa (755:755:755) (813:813:813)) - (PORT datab (715:715:715) (772:772:772)) - (PORT datad (329:329:329) (346:346:346)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (516:516:516) (565:565:565)) + (PORT datab (625:625:625) (643:643:643)) + (PORT datad (899:899:899) (921:921:921)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14074,7 +13379,7 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14088,9 +13393,9 @@ (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT datab (291:291:291) (377:377:377)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (690:690:690) (785:785:785)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -14102,12 +13407,13 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) (DELAY (ABSOLUTE - (PORT dataa (674:674:674) (714:714:714)) - (PORT datab (1413:1413:1413) (1416:1416:1416)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (616:616:616) (645:645:645)) + (PORT datab (645:645:645) (689:689:689)) + (PORT datac (698:698:698) (778:778:778)) + (PORT datad (175:175:175) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14117,13 +13423,13 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (884:884:884) (883:883:883)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -14131,9 +13437,9 @@ (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT dataa (440:440:440) (520:520:520)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (720:720:720) (789:789:789)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -14145,11 +13451,11 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (755:755:755) (813:813:813)) - (PORT datab (720:720:720) (781:781:781)) - (PORT datad (311:311:311) (325:325:325)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (519:519:519) (562:562:562)) + (PORT datab (588:588:588) (607:607:607)) + (PORT datad (902:902:902) (917:917:917)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14160,7 +13466,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14174,9 +13480,9 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT dataa (707:707:707) (766:766:766)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (691:691:691) (762:762:762)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -14188,9 +13494,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (753:753:753) (812:812:812)) - (PORT datab (597:597:597) (602:602:602)) - (PORT datad (680:680:680) (734:734:734)) + (PORT dataa (517:517:517) (566:566:566)) + (PORT datab (1177:1177:1177) (1178:1178:1178)) + (PORT datad (900:900:900) (920:920:920)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -14203,7 +13509,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14217,7 +13523,7 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (473:473:473) (538:538:538)) + (PORT datab (743:743:743) (817:817:817)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -14231,11 +13537,11 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (757:757:757) (813:813:813)) - (PORT datab (722:722:722) (780:780:780)) - (PORT datad (310:310:310) (326:326:326)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (517:517:517) (558:558:558)) + (PORT datab (998:998:998) (1000:1000:1000)) + (PORT datad (899:899:899) (916:916:916)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14246,7 +13552,47 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datad (650:650:650) (707:707:707)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (518:518:518) (565:565:565)) + (PORT datab (1005:1005:1005) (1007:1007:1007)) + (PORT datad (899:899:899) (922:922:922)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14260,10 +13606,10 @@ (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (384:384:384)) - (PORT datab (291:291:291) (377:377:377)) - (PORT datac (264:264:264) (345:345:345)) - (PORT datad (263:263:263) (335:335:335)) + (PORT dataa (272:272:272) (361:361:361)) + (PORT datab (270:270:270) (356:356:356)) + (PORT datac (263:263:263) (343:343:343)) + (PORT datad (244:244:244) (317:317:317)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14273,25 +13619,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~18) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT datad (398:398:398) (466:466:466)) + (PORT dataa (1173:1173:1173) (1262:1262:1262)) + (PORT datab (846:846:846) (922:922:922)) + (PORT datac (628:628:628) (679:679:679)) + (PORT datad (673:673:673) (746:746:746)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) + (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (755:755:755) (813:813:813)) - (PORT datab (711:711:711) (770:770:770)) - (PORT datad (331:331:331) (347:347:347)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (635:635:635) (701:701:701)) + (PORT datab (664:664:664) (725:725:725)) + (PORT datac (564:564:564) (582:582:582)) + (PORT datad (306:306:306) (321:321:321)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (518:518:518) (561:561:561)) + (PORT datab (553:553:553) (567:567:567)) + (PORT datad (900:900:900) (915:915:915)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14299,10 +13666,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[9\]) + (INSTANCE ula_\|video_\|vga_vc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14311,46 +13678,14 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1435:1435:1435) (1511:1511:1511)) - (PORT datab (1290:1290:1290) (1361:1361:1361)) - (PORT datac (1227:1227:1227) (1310:1310:1310)) - (PORT datad (1136:1136:1136) (1184:1184:1184)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (714:714:714)) - (PORT datab (744:744:744) (812:812:812)) - (PORT datac (716:716:716) (780:780:780)) - (PORT datad (316:316:316) (336:336:336)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (755:755:755) (813:813:813)) - (PORT datab (336:336:336) (364:364:364)) - (PORT datad (682:682:682) (730:730:730)) + (PORT dataa (516:516:516) (560:560:560)) + (PORT datab (566:566:566) (575:575:575)) + (PORT datad (899:899:899) (916:916:916)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -14363,7 +13698,7 @@ (INSTANCE ula_\|video_\|vga_vc\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -14386,10 +13721,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (1532:1532:1532) (1599:1599:1599)) - (PORT datab (1309:1309:1309) (1222:1222:1222)) - (PORT datac (1203:1203:1203) (1295:1295:1295)) - (PORT datad (1454:1454:1454) (1523:1523:1523)) + (PORT dataa (1420:1420:1420) (1497:1497:1497)) + (PORT datab (716:716:716) (801:801:801)) + (PORT datac (1844:1844:1844) (1733:1733:1733)) + (PORT datad (677:677:677) (732:732:732)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14402,10 +13737,10 @@ (INSTANCE z80_\|pla_decode_\|Equal79\~0) (DELAY (ABSOLUTE - (PORT dataa (1205:1205:1205) (1277:1277:1277)) - (PORT datab (947:947:947) (980:980:980)) - (PORT datac (1606:1606:1606) (1706:1706:1706)) - (PORT datad (1612:1612:1612) (1692:1692:1692)) + (PORT dataa (1251:1251:1251) (1348:1348:1348)) + (PORT datab (976:976:976) (1034:1034:1034)) + (PORT datac (1637:1637:1637) (1758:1758:1758)) + (PORT datad (1191:1191:1191) (1306:1306:1306)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -14413,30 +13748,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (267:267:267) (355:355:355)) - (PORT datab (828:828:828) (846:846:846)) - (PORT datac (2848:2848:2848) (2926:2926:2926)) - (PORT datad (997:997:997) (1010:1010:1010)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) (DELAY (ABSOLUTE - (PORT dataa (2853:2853:2853) (2937:2937:2937)) - (PORT datab (1022:1022:1022) (1050:1050:1050)) - (PORT datad (803:803:803) (811:811:811)) + (PORT dataa (1500:1500:1500) (1602:1602:1602)) + (PORT datab (361:361:361) (391:391:391)) + (PORT datad (665:665:665) (720:720:720)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -14449,11 +13768,11 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) (DELAY (ABSOLUTE - (PORT dataa (337:337:337) (453:453:453)) - (PORT datac (1158:1158:1158) (1272:1272:1272)) - (PORT datad (279:279:279) (363:363:363)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (357:357:357) (495:495:495)) + (PORT datab (2014:2014:2014) (2140:2140:2140)) + (PORT datad (275:275:275) (358:358:358)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14463,7 +13782,7 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (1270:1270:1270) (1279:1279:1279)) + (PORT inclk[0] (1586:1586:1586) (1625:1625:1625)) ) ) ) @@ -14472,9 +13791,9 @@ (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) + (PORT clk (1537:1537:1537) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1549:1549:1549) (1541:1541:1541)) + (PORT clrn (1552:1552:1552) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -14483,18 +13802,34 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (765:765:765)) + (PORT datab (266:266:266) (349:349:349)) + (PORT datac (204:204:204) (241:241:241)) + (PORT datad (1456:1456:1456) (1550:1550:1550)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|interrupts_\|iff1\~1) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (266:266:266) (350:350:350)) - (PORT datac (1580:1580:1580) (1636:1636:1636)) - (PORT datad (924:924:924) (968:968:968)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1287:1287:1287) (1330:1330:1330)) + (PORT datab (266:266:266) (349:349:349)) + (PORT datac (888:888:888) (913:913:913)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14504,11 +13839,11 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT dataa (342:342:342) (463:463:463)) - (PORT datac (1159:1159:1159) (1274:1274:1274)) - (PORT datad (285:285:285) (370:370:370)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (1431:1431:1431) (1492:1492:1492)) + (PORT datac (1518:1518:1518) (1551:1551:1551)) + (PORT datad (1267:1267:1267) (1335:1335:1335)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14518,9 +13853,9 @@ (INSTANCE z80_\|interrupts_\|iff1) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) + (PORT clk (1537:1537:1537) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1427:1427:1427) (1430:1430:1430)) + (PORT clrn (1403:1403:1403) (1412:1412:1412)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -14534,10 +13869,10 @@ (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (1257:1257:1257) (1348:1348:1348)) - (PORT datab (1289:1289:1289) (1358:1358:1358)) - (PORT datac (713:713:713) (778:778:778)) - (PORT datad (1135:1135:1135) (1184:1184:1184)) + (PORT dataa (1600:1600:1600) (1657:1657:1657)) + (PORT datab (843:843:843) (917:917:917)) + (PORT datac (633:633:633) (688:688:688)) + (PORT datad (427:427:427) (498:498:498)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14550,11 +13885,11 @@ (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT datab (743:743:743) (810:810:810)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (655:655:655) (666:666:666)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (565:565:565) (583:583:583)) + (PORT datad (436:436:436) (516:516:516)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14564,10 +13899,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT dataa (1513:1513:1513) (1645:1645:1645)) - (PORT datab (888:888:888) (917:917:917)) - (PORT datac (1865:1865:1865) (1978:1978:1978)) - (PORT datad (1421:1421:1421) (1479:1479:1479)) + (PORT dataa (1175:1175:1175) (1240:1240:1240)) + (PORT datab (630:630:630) (645:645:645)) + (PORT datac (1541:1541:1541) (1636:1636:1636)) + (PORT datad (848:848:848) (861:861:861)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -14580,9 +13915,9 @@ (INSTANCE z80_\|interrupts_\|int_armed) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1531:1531:1531) (1542:1542:1542)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (PORT clrn (1562:1562:1562) (1552:1552:1552)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -14591,59 +13926,33 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_inst44\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1408:1408:1408) (1517:1517:1517)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|interrupts_\|DFFE_inst44) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) - (PORT ena (957:957:957) (955:955:955)) + (PORT clk (1533:1533:1533) (1552:1552:1552)) + (PORT asdata (2158:2158:2158) (2284:2284:2284)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (1669:1669:1669) (1678:1678:1678)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (INSTANCE z80_\|execute_\|pc_inc_hold\~38) (DELAY (ABSOLUTE - (PORT dataa (337:337:337) (451:451:451)) - (PORT datab (305:305:305) (400:400:400)) - (PORT datac (251:251:251) (334:334:334)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (885:885:885)) - (PORT datab (954:954:954) (994:994:994)) - (PORT datac (922:922:922) (1000:1000:1000)) - (PORT datad (524:524:524) (533:533:533)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (355:355:355) (487:487:487)) + (PORT datac (1180:1180:1180) (1261:1261:1261)) + (PORT datad (269:269:269) (350:350:350)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14651,15 +13960,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) (DELAY (ABSOLUTE - (PORT dataa (1147:1147:1147) (1193:1193:1193)) - (PORT datab (426:426:426) (465:465:465)) - (PORT datac (1273:1273:1273) (1298:1298:1298)) - (PORT datad (1209:1209:1209) (1200:1200:1200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1671:1671:1671) (1790:1790:1790)) + (PORT datab (1251:1251:1251) (1347:1347:1347)) + (PORT datac (971:971:971) (1065:1065:1065)) + (PORT datad (862:862:862) (887:887:887)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14667,79 +13976,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (INSTANCE z80_\|execute_\|pc_inc_hold\~45) (DELAY (ABSOLUTE - (PORT dataa (1723:1723:1723) (1798:1798:1798)) - (PORT datab (1320:1320:1320) (1359:1359:1359)) - (PORT datac (1187:1187:1187) (1231:1231:1231)) - (PORT datad (1718:1718:1718) (1735:1735:1735)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT dataa (1089:1089:1089) (1139:1139:1139)) + (PORT datab (699:699:699) (765:765:765)) + (PORT datac (1191:1191:1191) (1271:1271:1271)) + (PORT datad (626:626:626) (668:668:668)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (875:875:875)) - (PORT datab (653:653:653) (676:676:676)) - (PORT datac (798:798:798) (819:819:819)) - (PORT datad (625:625:625) (660:660:660)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (198:198:198) (235:235:235)) - (PORT datac (812:812:812) (831:831:831)) - (PORT datad (1434:1434:1434) (1463:1463:1463)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (647:647:647) (702:702:702)) - (PORT datac (641:641:641) (699:699:699)) - (PORT datad (857:857:857) (884:884:884)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (741:741:741)) - (PORT datab (666:666:666) (737:737:737)) - (PORT datac (788:788:788) (800:800:800)) - (PORT datad (617:617:617) (630:630:630)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14747,15 +13992,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (INSTANCE z80_\|execute_\|pc_inc_hold\~44) (DELAY (ABSOLUTE - (PORT dataa (901:901:901) (949:949:949)) - (PORT datab (1469:1469:1469) (1501:1501:1501)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (300:300:300) (308:308:308)) + (PORT dataa (1090:1090:1090) (1140:1140:1140)) + (PORT datab (909:909:909) (981:981:981)) + (PORT datac (856:856:856) (898:898:898)) + (PORT datad (1096:1096:1096) (1107:1107:1107)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~46) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (372:372:372)) + (PORT datab (702:702:702) (770:770:770)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1101:1101:1101) (1112:1112:1112)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14763,13 +14024,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (INSTANCE z80_\|execute_\|pc_inc_hold\~37) (DELAY (ABSOLUTE - (PORT dataa (1151:1151:1151) (1227:1227:1227)) - (PORT datab (869:869:869) (891:891:891)) - (PORT datac (1143:1143:1143) (1157:1157:1157)) - (PORT datad (1572:1572:1572) (1594:1594:1594)) + (PORT dataa (1161:1161:1161) (1207:1207:1207)) + (PORT datab (884:884:884) (933:933:933)) + (PORT datac (1058:1058:1058) (1098:1098:1098)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~50) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (863:863:863)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1604:1604:1604) (1719:1719:1719)) + (PORT datad (2285:2285:2285) (2389:2389:2389)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (1151:1151:1151) (1219:1219:1219)) + (PORT datac (1080:1080:1080) (1126:1126:1126)) + (PORT datad (596:596:596) (629:629:629)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -14782,10 +14075,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) (DELAY (ABSOLUTE - (PORT dataa (916:916:916) (967:967:967)) - (PORT datab (1277:1277:1277) (1290:1290:1290)) - (PORT datac (1152:1152:1152) (1210:1210:1210)) - (PORT datad (1719:1719:1719) (1745:1745:1745)) + (PORT dataa (1685:1685:1685) (1750:1750:1750)) + (PORT datab (623:623:623) (672:672:672)) + (PORT datac (1663:1663:1663) (1743:1743:1743)) + (PORT datad (1164:1164:1164) (1212:1212:1212)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -14795,29 +14088,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) (DELAY (ABSOLUTE - (PORT dataa (1116:1116:1116) (1145:1145:1145)) - (PORT datab (721:721:721) (797:797:797)) - (PORT datac (563:563:563) (570:570:570)) - (PORT datad (1078:1078:1078) (1086:1086:1086)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (729:729:729) (825:825:825)) + (PORT datab (672:672:672) (761:761:761)) + (PORT datac (1148:1148:1148) (1186:1186:1186)) + (PORT datad (212:212:212) (247:247:247)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (INSTANCE z80_\|execute_\|pc_inc_hold\~31) (DELAY (ABSOLUTE - (PORT dataa (367:367:367) (402:402:402)) - (PORT datab (886:886:886) (944:944:944)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (181:181:181) (209:209:209)) + (PORT dataa (1112:1112:1112) (1165:1165:1165)) + (PORT datab (850:850:850) (866:866:866)) + (PORT datac (1208:1208:1208) (1236:1236:1236)) + (PORT datad (822:822:822) (834:834:834)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1168:1168:1168)) + (PORT datab (622:622:622) (673:673:673)) + (PORT datac (209:209:209) (250:250:250)) + (PORT datad (1641:1641:1641) (1711:1711:1711)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~34) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (193:193:193) (238:238:238)) + (PORT datad (180:180:180) (209:209:209)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -14827,15 +14152,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (INSTANCE z80_\|execute_\|pc_inc_hold\~51) (DELAY (ABSOLUTE - (PORT dataa (1117:1117:1117) (1146:1146:1146)) - (PORT datab (900:900:900) (910:910:910)) - (PORT datac (692:692:692) (761:761:761)) - (PORT datad (815:815:815) (820:820:820)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1149:1149:1149) (1191:1191:1191)) + (PORT datab (1399:1399:1399) (1505:1505:1505)) + (PORT datac (2514:2514:2514) (2618:2618:2618)) + (PORT datad (1497:1497:1497) (1611:1611:1611)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14843,47 +14168,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~41) + (INSTANCE z80_\|execute_\|pc_inc_hold\~30) (DELAY (ABSOLUTE - (PORT dataa (996:996:996) (1115:1115:1115)) - (PORT datab (993:993:993) (1093:1093:1093)) - (PORT datac (1204:1204:1204) (1289:1289:1289)) - (PORT datad (962:962:962) (1055:1055:1055)) + (PORT dataa (691:691:691) (738:738:738)) + (PORT datab (1144:1144:1144) (1210:1210:1210)) + (PORT datac (365:365:365) (393:393:393)) + (PORT datad (865:865:865) (890:890:890)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1521:1521:1521) (1648:1648:1648)) + (PORT datab (1395:1395:1395) (1501:1501:1501)) + (PORT datac (2518:2518:2518) (2621:2621:2621)) + (PORT datad (1054:1054:1054) (1086:1086:1086)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (406:406:406)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (619:619:619) (652:652:652)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1123:1123:1123)) + (PORT datab (643:643:643) (662:662:662)) + (PORT datac (625:625:625) (646:646:646)) + (PORT datad (1379:1379:1379) (1419:1419:1419)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~21) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (826:826:826)) - (PORT datab (1026:1026:1026) (1059:1059:1059)) - (PORT datac (706:706:706) (795:795:795)) - (PORT datad (1012:1012:1012) (1095:1095:1095)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~26) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (277:277:277)) - (PORT datab (215:215:215) (259:259:259)) - (PORT datac (614:614:614) (668:668:668)) - (PORT datad (608:608:608) (649:649:649)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14894,390 +14235,10 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) (DELAY (ABSOLUTE - (PORT dataa (968:968:968) (1041:1041:1041)) - (PORT datab (870:870:870) (888:888:888)) - (PORT datac (1021:1021:1021) (1043:1043:1043)) - (PORT datad (865:865:865) (864:864:864)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (406:406:406)) - (PORT datab (873:873:873) (907:907:907)) - (PORT datac (1040:1040:1040) (1071:1071:1071)) - (PORT datad (805:805:805) (851:851:851)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (1666:1666:1666) (1760:1760:1760)) - (PORT datac (935:935:935) (1001:1001:1001)) - (PORT datad (850:850:850) (850:850:850)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (663:663:663)) - (PORT datab (205:205:205) (248:248:248)) - (PORT datac (799:799:799) (823:823:823)) - (PORT datad (1427:1427:1427) (1479:1479:1479)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (192:192:192) (226:226:226)) - (PORT datad (793:793:793) (797:797:797)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (1124:1124:1124) (1152:1152:1152)) - (PORT datab (1101:1101:1101) (1127:1127:1127)) - (PORT datac (557:557:557) (566:566:566)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (1011:1011:1011)) - (PORT datac (737:737:737) (744:744:744)) - (PORT datad (913:913:913) (995:995:995)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1308:1308:1308)) - (PORT datab (1399:1399:1399) (1472:1472:1472)) - (PORT datac (1142:1142:1142) (1217:1217:1217)) - (PORT datad (1125:1125:1125) (1209:1209:1209)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~27) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (690:690:690)) - (PORT datab (1276:1276:1276) (1321:1321:1321)) - (PORT datac (777:777:777) (786:786:786)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (706:706:706)) - (PORT datab (939:939:939) (1032:1032:1032)) - (PORT datac (645:645:645) (689:689:689)) - (PORT datad (895:895:895) (965:965:965)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (674:674:674) (700:700:700)) - (PORT datac (1026:1026:1026) (1023:1023:1023)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1157:1157:1157)) - (PORT datab (843:843:843) (874:874:874)) - (PORT datac (597:597:597) (619:619:619)) - (PORT datad (826:826:826) (864:864:864)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1062:1062:1062)) - (PORT datab (675:675:675) (700:700:700)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1113:1113:1113)) - (PORT datab (993:993:993) (1093:1093:1093)) - (PORT datac (1024:1024:1024) (1036:1036:1036)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (870:870:870)) - (PORT datab (844:844:844) (880:880:880)) - (PORT datac (1079:1079:1079) (1127:1127:1127)) - (PORT datad (825:825:825) (861:861:861)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (458:458:458)) - (PORT datab (311:311:311) (410:410:410)) - (PORT datac (249:249:249) (330:330:330)) - (PORT datad (855:855:855) (894:894:894)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (403:403:403)) - (PORT datab (723:723:723) (798:798:798)) - (PORT datac (493:493:493) (502:502:502)) - (PORT datad (1632:1632:1632) (1662:1662:1662)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1106:1106:1106) (1130:1130:1130)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1085:1085:1085) (1108:1108:1108)) - (PORT datad (338:338:338) (359:359:359)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (606:606:606)) - (PORT datab (1180:1180:1180) (1235:1235:1235)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1247:1247:1247)) - (PORT datab (721:721:721) (797:797:797)) - (PORT datac (879:879:879) (927:927:927)) - (PORT datad (1718:1718:1718) (1745:1745:1745)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (402:402:402)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (1269:1269:1269) (1278:1278:1278)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1354:1354:1354) (1397:1397:1397)) - (PORT datab (695:695:695) (791:791:791)) - (PORT datac (726:726:726) (826:826:826)) - (PORT datad (1008:1008:1008) (1091:1091:1091)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (276:276:276)) - (PORT datab (542:542:542) (566:566:566)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (643:643:643) (689:689:689)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (279:279:279)) - (PORT datac (617:617:617) (670:670:670)) - (PORT datad (186:186:186) (218:218:218)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT dataa (769:769:769) (873:873:873)) - (PORT datab (1056:1056:1056) (1140:1140:1140)) - (PORT datac (663:663:663) (757:757:757)) - (PORT datad (1288:1288:1288) (1293:1293:1293)) + (PORT dataa (2071:2071:2071) (2185:2185:2185)) + (PORT datab (910:910:910) (981:981:981)) + (PORT datac (1397:1397:1397) (1483:1483:1483)) + (PORT datad (646:646:646) (677:677:677)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -15287,137 +14248,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (593:593:593) (644:644:644)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (1723:1723:1723) (1798:1798:1798)) - (PORT datab (1348:1348:1348) (1417:1417:1417)) - (PORT datac (1187:1187:1187) (1231:1231:1231)) - (PORT datad (1101:1101:1101) (1169:1169:1169)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT datab (847:847:847) (851:851:851)) - (PORT datac (996:996:996) (1014:1014:1014)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (279:279:279)) - (PORT datac (1266:1266:1266) (1273:1273:1273)) - (PORT datad (185:185:185) (217:217:217)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (169:169:169) (202:202:202)) - (PORT datad (587:587:587) (626:626:626)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (700:700:700)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (802:802:802) (827:827:827)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (529:529:529) (558:558:558)) - (PORT datab (204:204:204) (245:245:245)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (384:384:384)) - (PORT datab (800:800:800) (842:842:842)) - (PORT datad (837:837:837) (860:860:860)) + (PORT dataa (1333:1333:1333) (1437:1437:1437)) + (PORT datab (1764:1764:1764) (1881:1881:1881)) + (PORT datad (630:630:630) (685:685:685)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) (DELAY (ABSOLUTE - (PORT dataa (1134:1134:1134) (1199:1199:1199)) - (PORT datab (1163:1163:1163) (1206:1206:1206)) - (PORT datac (1177:1177:1177) (1255:1255:1255)) - (PORT datad (1003:1003:1003) (1008:1008:1008)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (216:216:216) (266:266:266)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (670:670:670) (716:716:716)) + (PORT datad (570:570:570) (590:590:590)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15425,45 +14278,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (INSTANCE z80_\|execute_\|pc_inc_hold\~43) (DELAY (ABSOLUTE - (PORT dataa (1188:1188:1188) (1225:1225:1225)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (631:631:631) (645:645:645)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1370:1370:1370) (1444:1444:1444)) - (PORT datab (239:239:239) (284:284:284)) - (PORT datac (2356:2356:2356) (2436:2436:2436)) - (PORT datad (1862:1862:1862) (1982:1982:1982)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (776:776:776)) - (PORT datab (1153:1153:1153) (1226:1226:1226)) - (PORT datac (1964:1964:1964) (2070:2070:2070)) - (PORT datad (726:726:726) (727:727:727)) + (PORT dataa (1409:1409:1409) (1454:1454:1454)) + (PORT datab (666:666:666) (697:697:697)) + (PORT datac (1989:1989:1989) (2085:2085:2085)) + (PORT datad (1246:1246:1246) (1294:1294:1294)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -15476,12 +14297,92 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) (DELAY (ABSOLUTE - (PORT dataa (1117:1117:1117) (1155:1155:1155)) - (PORT datab (883:883:883) (950:950:950)) - (PORT datac (1298:1298:1298) (1329:1329:1329)) - (PORT datad (826:826:826) (860:860:860)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (635:635:635) (682:682:682)) + (PORT datad (190:190:190) (223:223:223)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (421:421:421)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (637:637:637) (672:672:672)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (722:722:722)) + (PORT datab (699:699:699) (766:766:766)) + (PORT datac (639:639:639) (671:671:671)) + (PORT datad (1153:1153:1153) (1224:1224:1224)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1764:1764:1764)) + (PORT datab (1067:1067:1067) (1136:1136:1136)) + (PORT datac (612:612:612) (631:631:631)) + (PORT datad (973:973:973) (1058:1058:1058)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~39) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (264:264:264)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (623:623:623) (647:647:647)) + (PORT datad (565:565:565) (585:585:585)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~47) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (422:422:422)) + (PORT datab (212:212:212) (257:257:257)) + (PORT datac (620:620:620) (677:677:677)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15492,11 +14393,41 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (839:839:839) (841:841:841)) - (PORT datac (816:816:816) (848:848:848)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (881:881:881) (895:895:895)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (DELAY + (ABSOLUTE + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (636:636:636) (661:661:661)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (341:341:341) (376:376:376)) + (PORT datac (639:639:639) (674:674:674)) + (PORT datad (182:182:182) (213:213:213)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -15508,130 +14439,10 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (627:627:627) (644:644:644)) - (PORT datac (816:816:816) (843:843:843)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1309:1309:1309)) - (PORT datac (1245:1245:1245) (1243:1243:1243)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1021:1021:1021) (1037:1037:1037)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1882:1882:1882) (1962:1962:1962)) - (PORT datab (211:211:211) (255:255:255)) - (PORT datac (803:803:803) (846:846:846)) - (PORT datad (1265:1265:1265) (1277:1277:1277)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) - (DELAY - (ABSOLUTE - (PORT datab (820:820:820) (849:849:849)) - (PORT datad (1040:1040:1040) (1099:1099:1099)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (739:739:739)) - (PORT datab (1954:1954:1954) (2044:2044:2044)) - (PORT datac (799:799:799) (807:807:807)) - (PORT datad (1413:1413:1413) (1429:1429:1429)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1640:1640:1640) (1654:1654:1654)) - (PORT datab (1037:1037:1037) (1110:1110:1110)) - (PORT datac (347:347:347) (373:373:373)) - (PORT datad (921:921:921) (1022:1022:1022)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1360:1360:1360) (1425:1425:1425)) - (PORT datab (540:540:540) (561:561:561)) - (PORT datac (1156:1156:1156) (1231:1231:1231)) - (PORT datad (777:777:777) (800:800:800)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1285:1285:1285)) - (PORT datab (546:546:546) (574:574:574)) - (PORT datac (1293:1293:1293) (1341:1341:1341)) - (PORT datad (549:549:549) (563:563:563)) + (PORT dataa (676:676:676) (725:725:725)) + (PORT datab (911:911:911) (985:985:985)) + (PORT datac (1190:1190:1190) (1272:1272:1272)) + (PORT datad (188:188:188) (220:220:220)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -15641,111 +14452,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~54) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) (DELAY (ABSOLUTE - (PORT dataa (1181:1181:1181) (1204:1204:1204)) - (PORT datab (2164:2164:2164) (2257:2257:2257)) - (PORT datac (841:841:841) (881:881:881)) - (PORT datad (908:908:908) (981:981:981)) + (PORT dataa (868:868:868) (915:915:915)) + (PORT datab (682:682:682) (741:741:741)) + (PORT datac (965:965:965) (1027:1027:1027)) + (PORT datad (621:621:621) (668:668:668)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (684:684:684) (749:749:749)) + (PORT datac (972:972:972) (1033:1033:1033)) + (PORT datad (1668:1668:1668) (1690:1690:1690)) (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1315:1315:1315) (1336:1336:1336)) - (PORT datab (622:622:622) (670:670:670)) - (PORT datac (638:638:638) (664:664:664)) - (PORT datad (1121:1121:1121) (1173:1173:1173)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (1200:1200:1200) (1206:1206:1206)) - (PORT datac (834:834:834) (857:857:857)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1591:1591:1591) (1606:1606:1606)) - (PORT datab (877:877:877) (929:929:929)) - (PORT datac (861:861:861) (866:866:866)) - (PORT datad (1956:1956:1956) (1999:1999:1999)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1796:1796:1796) (1820:1820:1820)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (370:370:370) (412:412:412)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (560:560:560)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (523:523:523) (533:533:533)) - (PORT datad (885:885:885) (923:923:923)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (811:811:811) (847:847:847)) - (PORT datab (646:646:646) (665:665:665)) - (PORT datac (1084:1084:1084) (1128:1128:1128)) - (PORT datad (313:313:313) (333:333:333)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15753,14 +14484,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~39) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) (DELAY (ABSOLUTE - (PORT dataa (827:827:827) (838:838:838)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (534:534:534) (550:550:550)) - (PORT datad (186:186:186) (219:219:219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (340:340:340) (370:370:370)) + (PORT datac (638:638:638) (672:672:672)) + (PORT datad (357:357:357) (377:377:377)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -15769,577 +14500,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~47) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (545:545:545) (556:556:556)) - (PORT datad (598:598:598) (636:636:636)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (1696:1696:1696) (1806:1806:1806)) - (PORT datac (1608:1608:1608) (1655:1655:1655)) - (PORT datad (1487:1487:1487) (1516:1516:1516)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (994:994:994) (1047:1047:1047)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|db\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1697:1697:1697) (1800:1800:1800)) - (PORT datab (1937:1937:1937) (1973:1973:1973)) - (PORT datad (1488:1488:1488) (1516:1516:1516)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (1776:1776:1776) (1895:1895:1895)) - (PORT datac (1053:1053:1053) (1087:1087:1087)) - (PORT datad (1337:1337:1337) (1363:1363:1363)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (995:995:995) (1023:1023:1023)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT datab (1778:1778:1778) (1898:1898:1898)) - (PORT datac (1045:1045:1045) (1060:1060:1060)) - (PORT datad (1336:1336:1336) (1365:1365:1365)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT datab (1783:1783:1783) (1902:1902:1902)) - (PORT datac (1046:1046:1046) (1062:1062:1062)) - (PORT datad (1338:1338:1338) (1359:1359:1359)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (997:997:997) (1022:1022:1022)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT datab (1759:1759:1759) (1876:1876:1876)) - (PORT datac (1057:1057:1057) (1085:1085:1085)) - (PORT datad (1341:1341:1341) (1367:1367:1367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (329:329:329)) - (PORT datab (686:686:686) (717:717:717)) - (PORT datad (657:657:657) (694:694:694)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT datab (1091:1091:1091) (1107:1107:1107)) - (PORT datac (1723:1723:1723) (1842:1842:1842)) - (PORT datad (1341:1341:1341) (1360:1360:1360)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1551:1551:1551)) - (PORT asdata (995:995:995) (1021:1021:1021)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT datab (1088:1088:1088) (1109:1109:1109)) - (PORT datac (1731:1731:1731) (1850:1850:1850)) - (PORT datad (1336:1336:1336) (1365:1365:1365)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (400:400:400)) - (PORT datab (644:644:644) (664:664:664)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT datac (1902:1902:1902) (1994:1994:1994)) - (PORT datad (1021:1021:1021) (1040:1040:1040)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1528:1528:1528)) - (PORT datab (643:643:643) (724:724:724)) - (PORT datac (542:542:542) (566:566:566)) - (PORT datad (1270:1270:1270) (1300:1300:1300)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1011:1011:1011) (1075:1075:1075)) - (PORT datab (871:871:871) (890:890:890)) - (PORT datac (910:910:910) (962:962:962)) - (PORT datad (1141:1141:1141) (1166:1166:1166)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) - (DELAY - (ABSOLUTE - (PORT dataa (1412:1412:1412) (1433:1433:1433)) - (PORT datac (1203:1203:1203) (1332:1332:1332)) - (PORT datad (1325:1325:1325) (1407:1407:1407)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1413:1413:1413) (1428:1428:1428)) - (PORT datab (1397:1397:1397) (1483:1483:1483)) - (PORT datac (1314:1314:1314) (1347:1347:1347)) - (PORT datad (1320:1320:1320) (1382:1382:1382)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (685:685:685)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (872:872:872) (891:891:891)) - (PORT datad (857:857:857) (903:903:903)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (899:899:899)) - (PORT datab (1651:1651:1651) (1702:1702:1702)) - (PORT datac (866:866:866) (915:915:915)) - (PORT datad (1166:1166:1166) (1192:1192:1192)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1309:1309:1309) (1353:1353:1353)) - (PORT datab (1293:1293:1293) (1332:1332:1332)) - (PORT datac (3294:3294:3294) (3391:3391:3391)) - (PORT datad (683:683:683) (741:741:741)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1113:1113:1113)) - (PORT datab (920:920:920) (992:992:992)) - (PORT datad (1034:1034:1034) (1043:1043:1043)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1445:1445:1445) (1568:1568:1568)) - (PORT datab (1071:1071:1071) (1092:1092:1092)) - (PORT datac (1392:1392:1392) (1484:1484:1484)) - (PORT datad (1093:1093:1093) (1146:1146:1146)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (287:287:287)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (902:902:902) (934:934:934)) - (PORT datad (1058:1058:1058) (1090:1090:1090)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT datac (893:893:893) (974:974:974)) - (PORT datad (808:808:808) (814:814:814)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1250:1250:1250) (1341:1341:1341)) - (PORT datab (1685:1685:1685) (1758:1758:1758)) - (PORT datac (875:875:875) (893:893:893)) - (PORT datad (879:879:879) (929:929:929)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1207:1207:1207)) - (PORT datab (1447:1447:1447) (1535:1535:1535)) - (PORT datac (1400:1400:1400) (1504:1504:1504)) - (PORT datad (1166:1166:1166) (1255:1255:1255)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (328:328:328) (352:352:352)) - (PORT datad (931:931:931) (993:993:993)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (405:405:405)) - (PORT datab (540:540:540) (569:569:569)) - (PORT datac (552:552:552) (561:561:561)) - (PORT datad (650:650:650) (714:714:714)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (263:263:263)) - (PORT datab (222:222:222) (269:269:269)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (641:641:641) (662:662:662)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1345:1345:1345)) - (PORT datab (1682:1682:1682) (1762:1762:1762)) - (PORT datac (553:553:553) (578:578:578)) - (PORT datad (1132:1132:1132) (1191:1191:1191)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2256:2256:2256) (2343:2343:2343)) - (PORT datab (2177:2177:2177) (2301:2301:2301)) - (PORT datac (1405:1405:1405) (1455:1455:1455)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1096:1096:1096)) - (PORT datab (1388:1388:1388) (1480:1480:1480)) - (PORT datac (1724:1724:1724) (1821:1821:1821)) - (PORT datad (1700:1700:1700) (1777:1777:1777)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (948:948:948)) - (PORT datab (610:610:610) (654:654:654)) - (PORT datac (789:789:789) (812:812:812)) - (PORT datad (1506:1506:1506) (1605:1605:1605)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1128:1128:1128) (1176:1176:1176)) - (PORT datab (613:613:613) (677:677:677)) - (PORT datac (847:847:847) (883:883:883)) - (PORT datad (585:585:585) (633:633:633)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (953:953:953)) - (PORT datab (906:906:906) (934:934:934)) - (PORT datac (1271:1271:1271) (1286:1286:1286)) - (PORT datad (1262:1262:1262) (1280:1280:1280)) - (IOPATH dataa combout (341:341:341) (319:319:319)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (180:180:180) (207:207:207)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -16348,143 +14514,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (INSTANCE z80_\|execute_\|pc_inc_hold\~42) (DELAY (ABSOLUTE - (PORT dataa (359:359:359) (405:405:405)) - (PORT datab (684:684:684) (753:753:753)) - (PORT datac (552:552:552) (565:565:565)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1332:1332:1332) (1395:1395:1395)) - (PORT datab (881:881:881) (933:933:933)) - (PORT datac (1129:1129:1129) (1197:1197:1197)) - (PORT datad (1332:1332:1332) (1391:1391:1391)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1327:1327:1327) (1390:1390:1390)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (754:754:754) (766:766:766)) - (PORT datad (1330:1330:1330) (1387:1387:1387)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1514:1514:1514) (1568:1568:1568)) - (PORT datab (1498:1498:1498) (1595:1595:1595)) - (PORT datac (1147:1147:1147) (1177:1177:1177)) - (PORT datad (1404:1404:1404) (1426:1426:1426)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (383:383:383)) - (PORT datab (1248:1248:1248) (1338:1338:1338)) - (PORT datac (1162:1162:1162) (1271:1271:1271)) - (PORT datad (1038:1038:1038) (1031:1031:1031)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (925:925:925)) - (PORT datab (629:629:629) (665:665:665)) - (PORT datac (345:345:345) (377:377:377)) + (PORT datab (652:652:652) (687:687:687)) + (PORT datac (339:339:339) (370:370:370)) (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1011:1011:1011) (1017:1017:1017)) - (PORT datad (612:612:612) (665:665:665)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (999:999:999)) - (PORT datab (227:227:227) (269:269:269)) - (PORT datac (978:978:978) (1031:1031:1031)) - (PORT datad (640:640:640) (661:661:661)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (287:287:287)) - (PORT datab (936:936:936) (967:967:967)) - (PORT datac (187:187:187) (225:225:225)) - (PORT datad (186:186:186) (217:217:217)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16492,31 +14528,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal72\~2) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) (DELAY (ABSOLUTE - (PORT dataa (1000:1000:1000) (1085:1085:1085)) - (PORT datab (1001:1001:1001) (1073:1073:1073)) - (PORT datac (2236:2236:2236) (2302:2302:2302)) - (PORT datad (581:581:581) (621:621:621)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1117:1117:1117)) - (PORT datab (2183:2183:2183) (2322:2322:2322)) - (PORT datac (576:576:576) (621:621:621)) - (PORT datad (584:584:584) (612:612:612)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (1017:1017:1017) (1099:1099:1099)) + (PORT datab (1086:1086:1086) (1123:1123:1123)) + (PORT datac (1171:1171:1171) (1232:1232:1232)) + (PORT datad (1497:1497:1497) (1611:1611:1611)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16524,31 +14544,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (INSTANCE z80_\|execute_\|pc_inc_hold\~41) (DELAY (ABSOLUTE - (PORT dataa (1000:1000:1000) (1084:1084:1084)) - (PORT datab (999:999:999) (1067:1067:1067)) - (PORT datac (2234:2234:2234) (2302:2302:2302)) - (PORT datad (583:583:583) (619:619:619)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (227:227:227) (279:279:279)) + (PORT datab (627:627:627) (674:674:674)) + (PORT datac (208:208:208) (246:246:246)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~2) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) (DELAY (ABSOLUTE - (PORT dataa (1232:1232:1232) (1267:1267:1267)) - (PORT datab (1163:1163:1163) (1189:1189:1189)) - (PORT datac (864:864:864) (912:912:912)) - (PORT datad (1067:1067:1067) (1072:1072:1072)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (355:355:355) (494:494:494)) + (PORT datab (902:902:902) (935:935:935)) + (PORT datac (1178:1178:1178) (1261:1261:1261)) + (PORT datad (273:273:273) (355:355:355)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1166:1166:1166)) + (PORT datab (227:227:227) (270:270:270)) + (PORT datac (194:194:194) (242:242:242)) + (PORT datad (872:872:872) (923:923:923)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (1443:1443:1443) (1505:1505:1505)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1642:1642:1642) (1712:1712:1712)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16556,47 +14608,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~3) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) (DELAY (ABSOLUTE - (PORT dataa (1124:1124:1124) (1134:1134:1134)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (1006:1006:1006) (1002:1002:1002)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (661:661:661)) - (PORT datab (214:214:214) (257:257:257)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (1448:1448:1448) (1437:1437:1437)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (824:824:824)) - (PORT datab (645:645:645) (698:698:698)) - (PORT datac (863:863:863) (904:904:904)) - (PORT datad (643:643:643) (665:665:665)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT dataa (1110:1110:1110) (1166:1166:1166)) + (PORT datab (235:235:235) (278:278:278)) + (PORT datac (195:195:195) (241:241:241)) + (PORT datad (596:596:596) (630:630:630)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16604,15 +14624,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (888:888:888)) + (PORT datab (1133:1133:1133) (1145:1145:1145)) + (PORT datac (343:343:343) (372:372:372)) + (PORT datad (854:854:854) (886:886:886)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1221:1221:1221)) + (PORT datab (375:375:375) (398:398:398)) + (PORT datac (308:308:308) (325:325:325)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) (DELAY (ABSOLUTE (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (644:644:644) (687:687:687)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (626:626:626) (665:665:665)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (330:330:330) (348:348:348)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (715:715:715)) + (PORT datab (410:410:410) (440:440:440)) + (PORT datac (1131:1131:1131) (1156:1156:1156)) + (PORT datad (854:854:854) (887:887:887)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (719:719:719)) + (PORT datab (946:946:946) (985:985:985)) + (PORT datac (1123:1123:1123) (1165:1165:1165)) + (PORT datad (1721:1721:1721) (1778:1778:1778)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (395:395:395)) + (PORT datab (1129:1129:1129) (1184:1184:1184)) + (PORT datac (1040:1040:1040) (1054:1054:1054)) + (PORT datad (1204:1204:1204) (1229:1229:1229)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16620,77 +14720,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) (DELAY (ABSOLUTE - (PORT dataa (1412:1412:1412) (1431:1431:1431)) - (PORT datab (1345:1345:1345) (1422:1422:1422)) - (PORT datac (1567:1567:1567) (1628:1628:1628)) - (PORT datad (1325:1325:1325) (1407:1407:1407)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (701:701:701)) - (PORT datab (224:224:224) (272:272:272)) - (PORT datac (318:318:318) (349:349:349)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (396:396:396)) - (PORT datab (870:870:870) (878:878:878)) - (PORT datac (562:562:562) (572:572:572)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1413:1413:1413)) - (PORT datab (1157:1157:1157) (1246:1246:1246)) - (PORT datac (1129:1129:1129) (1208:1208:1208)) - (PORT datad (1170:1170:1170) (1285:1285:1285)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (247:247:247) (289:289:289)) - (PORT datac (1495:1495:1495) (1558:1558:1558)) - (PORT datad (539:539:539) (556:556:556)) + (PORT dataa (657:657:657) (717:717:717)) + (PORT datab (921:921:921) (959:959:959)) + (PORT datac (913:913:913) (949:949:949)) + (PORT datad (313:313:313) (331:331:331)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -16700,29 +14736,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) (DELAY (ABSOLUTE - (PORT dataa (1591:1591:1591) (1590:1590:1590)) - (PORT datab (638:638:638) (662:662:662)) - (PORT datac (827:827:827) (838:838:838)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (835:835:835)) - (PORT datab (854:854:854) (867:867:867)) - (PORT datac (1101:1101:1101) (1119:1119:1119)) - (PORT datad (516:516:516) (517:517:517)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (902:902:902) (981:981:981)) + (PORT datab (893:893:893) (932:932:932)) + (PORT datac (1434:1434:1434) (1470:1470:1470)) + (PORT datad (843:843:843) (890:890:890)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16730,79 +14752,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) (DELAY (ABSOLUTE - (PORT dataa (220:220:220) (264:264:264)) - (PORT datab (218:218:218) (258:258:258)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (932:932:932)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (830:830:830) (841:841:841)) - (PORT datad (858:858:858) (869:869:869)) + (PORT dataa (1466:1466:1466) (1512:1512:1512)) + (PORT datab (915:915:915) (968:968:968)) + (PORT datac (321:321:321) (356:356:356)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1116:1116:1116)) - (PORT datab (1112:1112:1112) (1172:1172:1172)) - (PORT datac (800:800:800) (828:828:828)) - (PORT datad (853:853:853) (887:887:887)) - (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (909:909:909)) - (PORT datab (1136:1136:1136) (1150:1150:1150)) - (PORT datac (1677:1677:1677) (1684:1684:1684)) - (PORT datad (1310:1310:1310) (1340:1340:1340)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (397:397:397) (421:421:421)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (1097:1097:1097) (1119:1119:1119)) - (PORT datad (1590:1590:1590) (1617:1617:1617)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16810,93 +14768,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) (DELAY (ABSOLUTE - (PORT dataa (589:589:589) (608:608:608)) - (PORT datab (253:253:253) (304:304:304)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (614:614:614)) - (PORT datab (221:221:221) (261:261:261)) + (PORT dataa (227:227:227) (280:280:280)) + (PORT datab (200:200:200) (239:239:239)) (PORT datac (170:170:170) (202:202:202)) - (PORT datad (811:811:811) (858:858:858)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (921:921:921)) - (PORT datab (2177:2177:2177) (2304:2304:2304)) - (PORT datac (1641:1641:1641) (1700:1700:1700)) - (PORT datad (863:863:863) (895:895:895)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (709:709:709)) - (PORT datab (2392:2392:2392) (2493:2493:2493)) - (PORT datac (1119:1119:1119) (1174:1174:1174)) - (PORT datad (644:644:644) (666:666:666)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (385:385:385)) - (PORT datab (375:375:375) (413:413:413)) - (PORT datac (603:603:603) (634:634:634)) - (PORT datad (807:807:807) (820:820:820)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (900:900:900)) - (PORT datab (585:585:585) (593:593:593)) - (PORT datac (883:883:883) (924:924:924)) - (PORT datad (822:822:822) (856:856:856)) + (PORT datad (588:588:588) (601:601:601)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -16906,93 +14784,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) (DELAY (ABSOLUTE - (PORT dataa (834:834:834) (856:856:856)) - (PORT datab (969:969:969) (1033:1033:1033)) - (PORT datac (889:889:889) (971:971:971)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (401:401:401)) - (PORT datab (874:874:874) (925:925:925)) - (PORT datac (553:553:553) (565:565:565)) - (PORT datad (612:612:612) (655:655:655)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (266:266:266)) - (PORT datab (223:223:223) (268:268:268)) - (PORT datac (786:786:786) (817:817:817)) - (PORT datad (602:602:602) (638:638:638)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (687:687:687)) - (PORT datab (691:691:691) (713:713:713)) - (PORT datac (200:200:200) (235:235:235)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) - (DELAY - (ABSOLUTE - (PORT dataa (2086:2086:2086) (2187:2187:2187)) - (PORT datab (359:359:359) (392:392:392)) - (PORT datac (1493:1493:1493) (1579:1579:1579)) - (PORT datad (645:645:645) (680:680:680)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (1188:1188:1188) (1234:1234:1234)) + (PORT datab (1144:1144:1144) (1214:1214:1214)) + (PORT datac (364:364:364) (396:396:396)) + (PORT datad (1141:1141:1141) (1188:1188:1188)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) (DELAY (ABSOLUTE - (PORT dataa (1656:1656:1656) (1755:1755:1755)) - (PORT datab (1175:1175:1175) (1283:1283:1283)) - (PORT datac (833:833:833) (859:859:859)) - (PORT datad (1180:1180:1180) (1288:1288:1288)) + (PORT dataa (1122:1122:1122) (1132:1132:1132)) + (PORT datab (1153:1153:1153) (1193:1193:1193)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (987:987:987)) + (PORT datab (921:921:921) (959:959:959)) + (PORT datac (635:635:635) (676:676:676)) + (PORT datad (1543:1543:1543) (1626:1626:1626)) (IOPATH dataa combout (341:341:341) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -17002,672 +14830,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) (DELAY (ABSOLUTE - (PORT dataa (654:654:654) (677:677:677)) - (PORT datab (1279:1279:1279) (1345:1345:1345)) - (PORT datac (1763:1763:1763) (1820:1820:1820)) - (PORT datad (1084:1084:1084) (1130:1130:1130)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1795:1795:1795) (1856:1856:1856)) - (PORT datab (1447:1447:1447) (1589:1589:1589)) - (PORT datac (1335:1335:1335) (1413:1413:1413)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1176:1176:1176)) - (PORT datab (1279:1279:1279) (1342:1342:1342)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1268:1268:1268) (1316:1316:1316)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (641:641:641)) - (PORT datab (949:949:949) (991:991:991)) - (PORT datac (518:518:518) (545:545:545)) - (PORT datad (1606:1606:1606) (1658:1658:1658)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (648:648:648)) - (PORT datab (1169:1169:1169) (1211:1211:1211)) - (PORT datac (1263:1263:1263) (1299:1299:1299)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (645:645:645)) - (PORT datab (1064:1064:1064) (1104:1104:1104)) - (PORT datac (578:578:578) (611:611:611)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1657:1657:1657) (1758:1758:1758)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (499:499:499) (509:509:509)) - (PORT datad (1160:1160:1160) (1211:1211:1211)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1087:1087:1087)) - (PORT datab (1091:1091:1091) (1095:1095:1095)) - (PORT datac (832:832:832) (857:857:857)) - (PORT datad (872:872:872) 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(863:863:863)) - (PORT datad (1062:1062:1062) (1056:1056:1056)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datac (982:982:982) (1011:1011:1011)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (957:957:957)) - (PORT datab (203:203:203) (244:244:244)) - (PORT datac (1134:1134:1134) (1181:1181:1181)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (915:915:915)) - (PORT datab (826:826:826) (838:838:838)) - (PORT datac (823:823:823) (835:835:835)) - (PORT datad (178:178:178) (207:207:207)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (939:939:939)) - (PORT datab (608:608:608) (664:664:664)) - (PORT datac (615:615:615) (622:622:622)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1432:1432:1432)) - (PORT datab (930:930:930) (980:980:980)) - (PORT datac (1089:1089:1089) (1144:1144:1144)) - (PORT datad (1381:1381:1381) (1460:1460:1460)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (938:938:938)) - (PORT datab (893:893:893) (937:937:937)) - (PORT datac (1244:1244:1244) (1266:1266:1266)) - (PORT datad (1083:1083:1083) (1130:1130:1130)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1099:1099:1099) (1132:1132:1132)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (850:850:850) (907:907:907)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (907:907:907)) - (PORT datab (849:849:849) (877:877:877)) - (PORT datac (1082:1082:1082) (1084:1084:1084)) - (PORT datad (325:325:325) (347:347:347)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (686:686:686) (728:728:728)) - (PORT datac (804:804:804) (841:841:841)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (671:671:671)) - (PORT datab (270:270:270) (355:355:355)) - (PORT datac (250:250:250) (333:333:333)) - (PORT datad (245:245:245) (317:317:317)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (950:950:950)) - (PORT datab (1212:1212:1212) (1290:1290:1290)) - (PORT datac (1040:1040:1040) (1051:1051:1051)) - (PORT datad (982:982:982) (1007:1007:1007)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1147:1147:1147) (1197:1197:1197)) - (PORT datac (1043:1043:1043) (1049:1049:1049)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (576:576:576)) - (PORT datab (648:648:648) (672:672:672)) - (PORT datac (911:911:911) (963:963:963)) - (PORT datad (772:772:772) (788:788:788)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (844:844:844)) - (PORT datab (829:829:829) (857:857:857)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1177:1177:1177)) - (PORT datab (1878:1878:1878) (1947:1947:1947)) - (PORT datac (1230:1230:1230) (1236:1236:1236)) - (PORT datad (1653:1653:1653) (1642:1642:1642)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (268:268:268)) - (PORT datab (1536:1536:1536) (1562:1562:1562)) - (PORT datac (558:558:558) (587:587:587)) - (PORT datad (1302:1302:1302) (1340:1340:1340)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (898:898:898)) - (PORT datab (604:604:604) (609:609:609)) - (PORT datac (550:550:550) (573:573:573)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (985:985:985) (997:997:997)) - (PORT datad (860:860:860) (877:877:877)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (731:731:731) (752:752:752)) - (PORT datab (1095:1095:1095) (1100:1100:1100)) - (PORT datac (1129:1129:1129) (1193:1193:1193)) - (PORT datad (837:837:837) (864:864:864)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1504:1504:1504) (1527:1527:1527)) - (PORT datab (1695:1695:1695) (1739:1739:1739)) - (PORT datac (1129:1129:1129) (1194:1194:1194)) - (PORT datad (846:846:846) (896:896:896)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1507:1507:1507) (1533:1533:1533)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (754:754:754) (764:764:764)) - (PORT datad (1667:1667:1667) (1700:1700:1700)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (974:974:974)) - (PORT datab (1446:1446:1446) (1588:1588:1588)) - (PORT datac (1759:1759:1759) (1881:1881:1881)) - (PORT datad (1106:1106:1106) (1187:1187:1187)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (316:316:316) (335:335:335)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (921:921:921)) - (PORT datab (1088:1088:1088) (1149:1149:1149)) - (PORT datac (1107:1107:1107) (1163:1163:1163)) - (PORT datad (1572:1572:1572) (1620:1620:1620)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (860:860:860)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (193:193:193) (226:226:226)) + (PORT dataa (457:457:457) (498:498:498)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (805:805:805) (826:826:826)) (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1316:1316:1316) (1362:1362:1362)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1263:1263:1263) (1304:1304:1304)) - (PORT datad (832:832:832) (856:856:856)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (969:969:969)) - (PORT datab (728:728:728) (814:814:814)) - (PORT datac (663:663:663) (736:736:736)) - (PORT datad (1060:1060:1060) (1070:1070:1070)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT datab (1293:1293:1293) (1323:1323:1323)) - (PORT datac (636:636:636) (678:678:678)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (653:653:653)) - (PORT datab (1332:1332:1332) (1373:1373:1373)) - (PORT datac (1033:1033:1033) (1061:1061:1061)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2034:2034:2034) (2049:2049:2049)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~4) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (695:695:695) (780:780:780)) - (PORT datad (856:856:856) (905:905:905)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (707:707:707)) - (PORT datab (914:914:914) (952:952:952)) - (PORT datac (1086:1086:1086) (1099:1099:1099)) - (PORT datad (895:895:895) (949:949:949)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT dataa (1333:1333:1333) (1437:1437:1437)) + (PORT datab (1163:1163:1163) (1169:1169:1169)) + (PORT datac (1430:1430:1430) (1469:1469:1469)) + (PORT datad (844:844:844) (894:894:894)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -17676,119 +14862,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~1) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) (DELAY (ABSOLUTE - (PORT dataa (848:848:848) (893:893:893)) - (PORT datab (1126:1126:1126) (1167:1167:1167)) - (PORT datac (576:576:576) (586:586:586)) - (PORT datad (884:884:884) (949:949:949)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1172:1172:1172)) - (PORT datac (805:805:805) (846:846:846)) - (PORT datad (819:819:819) (846:846:846)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (732:732:732) (834:834:834)) - (PORT datab (206:206:206) (249:249:249)) - (PORT datac (1365:1365:1365) (1390:1390:1390)) - (PORT datad (701:701:701) (778:778:778)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1657:1657:1657) (1756:1756:1756)) - (PORT datab (1146:1146:1146) (1224:1224:1224)) - (PORT datac (989:989:989) (1008:1008:1008)) - (PORT datad (1180:1180:1180) (1289:1289:1289)) + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (828:828:828) (830:830:830)) + (PORT datac (314:314:314) (333:333:333)) + (PORT datad (172:172:172) (197:197:197)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) - (DELAY - (ABSOLUTE - (PORT datab (632:632:632) (670:670:670)) - (PORT datac (613:613:613) (645:645:645)) - (PORT datad (873:873:873) (922:922:922)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (1282:1282:1282) (1286:1286:1286)) - (PORT datac (617:617:617) (675:675:675)) - (PORT datad (849:849:849) (894:894:894)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT datac (323:323:323) (347:347:347)) - (PORT datad (570:570:570) (595:595:595)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -17796,71 +14878,62 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~25) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) (DELAY (ABSOLUTE - (PORT dataa (570:570:570) (606:606:606)) - (PORT datad (312:312:312) (334:334:334)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (907:907:907) (937:937:937)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (590:590:590) (602:602:602)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (879:879:879) (889:889:889)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~0) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (335:335:335)) - (PORT datab (643:643:643) (660:660:660)) - (PORT datad (890:890:890) (955:955:955)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1157:1157:1157) (1220:1220:1220)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (563:563:563) (566:566:566)) + (PORT datad (559:559:559) (582:582:582)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1096:1096:1096) (1139:1139:1139)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (1061:1061:1061) (1099:1099:1099)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~1) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) (DELAY (ABSOLUTE - (PORT datab (377:377:377) (400:400:400)) - (PORT datac (215:215:215) (291:291:291)) - (PORT datad (421:421:421) (450:450:450)) + (PORT dataa (1618:1618:1618) (1736:1736:1736)) + (PORT datab (867:867:867) (905:905:905)) + (PORT datac (2517:2517:2517) (2622:2622:2622)) + (PORT datad (1493:1493:1493) (1607:1607:1607)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -17869,25 +14942,155 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) (DELAY (ABSOLUTE - (PORT datac (1491:1491:1491) (1572:1572:1572)) - (PORT datad (617:617:617) (665:665:665)) + (PORT dataa (592:592:592) (611:611:611)) + (PORT datab (580:580:580) (593:593:593)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1133:1133:1133) (1184:1184:1184)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~40) + (DELAY + (ABSOLUTE + (PORT datab (652:652:652) (686:686:686)) + (PORT datac (338:338:338) (369:369:369)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (277:277:277)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (1058:1058:1058) (1099:1099:1099)) + (PORT datad (1134:1134:1134) (1161:1161:1161)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1225:1225:1225)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (551:551:551) (564:564:564)) + (PORT datad (399:399:399) (430:430:430)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (169:169:169) (201:201:201)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1138:1138:1138)) + (PORT datab (1105:1105:1105) (1122:1122:1122)) + (PORT datac (1065:1065:1065) (1088:1088:1088)) + (PORT datad (1172:1172:1172) (1217:1217:1217)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (700:700:700) (784:784:784)) + (PORT datad (365:365:365) (386:386:386)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (958:958:958) (1001:1001:1001)) + (PORT datac (681:681:681) (720:720:720)) + (PORT datad (339:339:339) (361:361:361)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[0\]) (DELAY (ABSOLUTE - (PORT clk (1523:1523:1523) (1544:1544:1544)) + (PORT datac (1006:1006:1006) (1012:1012:1012)) + (PORT datad (924:924:924) (943:943:943)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (179:179:179) (207:207:207)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1547:1547:1547)) - (PORT ena (2452:2452:2452) (2480:2480:2480)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2096:2096:2096) (2133:2133:2133)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -17899,14 +15102,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) (DELAY (ABSOLUTE - (PORT dataa (645:645:645) (720:720:720)) - (PORT datab (653:653:653) (676:676:676)) - (PORT datac (1106:1106:1106) (1167:1167:1167)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (1158:1158:1158) (1184:1184:1184)) + (PORT datab (989:989:989) (1022:1022:1022)) + (PORT datac (696:696:696) (778:778:778)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (985:985:985) (1033:1033:1033)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (396:396:396)) + (PORT datab (697:697:697) (726:726:726)) + (PORT datad (1194:1194:1194) (1231:1231:1231)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (740:740:740) (774:774:774)) + (PORT datac (217:217:217) (294:294:294)) + (PORT datad (608:608:608) (657:657:657)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -17915,14 +15179,210 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~3) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (644:644:644) (685:685:685)) - (PORT datac (1659:1659:1659) (1785:1785:1785)) - (PORT datad (376:376:376) (395:395:395)) - (IOPATH dataa combout (303:303:303) (308:308:308)) + (PORT dataa (845:845:845) (905:905:905)) + (PORT datab (402:402:402) (425:425:425)) + (PORT datac (194:194:194) (227:227:227)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (244:244:244)) + (PORT datab (959:959:959) (1000:1000:1000)) + (PORT datac (683:683:683) (721:721:721)) + (PORT datad (341:341:341) (359:359:359)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (421:421:421)) + (PORT datad (345:345:345) (371:371:371)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT asdata (537:537:537) (568:568:568)) + (PORT clrn (1597:1597:1597) (1572:1572:1572)) + (PORT ena (2143:2143:2143) (2210:2210:2210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1069:1069:1069)) + (PORT datab (1154:1154:1154) (1178:1178:1178)) + (PORT datac (812:812:812) (866:866:866)) + (PORT datad (359:359:359) (383:383:383)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (443:443:443)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (236:236:236) (311:311:311)) + (PORT datad (327:327:327) (348:348:348)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (758:758:758)) + (PORT datab (962:962:962) (1001:1001:1001)) + (PORT datac (617:617:617) (670:670:670)) + (PORT datad (532:532:532) (544:544:544)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (579:579:579)) + (PORT datad (214:214:214) (247:247:247)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (220:220:220)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1597:1597:1597) (1572:1572:1572)) + (PORT ena (2146:2146:2146) (2210:2210:2210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (424:424:424)) + (PORT datab (1154:1154:1154) (1182:1182:1182)) + (PORT datac (966:966:966) (1033:1033:1033)) + (PORT datad (394:394:394) (449:449:449)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (441:441:441)) + (PORT datab (1103:1103:1103) (1121:1121:1121)) + (PORT datac (1068:1068:1068) (1079:1079:1079)) + (PORT datad (1177:1177:1177) (1222:1222:1222)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1182:1182:1182)) + (PORT datab (983:983:983) (1021:1021:1021)) + (PORT datac (960:960:960) (1025:1025:1025)) + (PORT datad (1127:1127:1127) (1138:1138:1138)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -17930,13 +15390,59 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1261:1261:1261) (1322:1322:1322)) - (PORT ena (841:841:841) (846:846:846)) + (PORT dataa (846:846:846) (907:907:907)) + (PORT datab (1376:1376:1376) (1400:1400:1400)) + (PORT datac (695:695:695) (778:778:778)) + (PORT datad (369:369:369) (389:389:389)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (331:331:331) (357:357:357)) + (PORT datad (244:244:244) (316:316:316)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1394:1394:1394) (1425:1425:1425)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1396:1396:1396) (1427:1427:1427)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -17947,27 +15453,53 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~12) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) (DELAY (ABSOLUTE - (PORT dataa (1209:1209:1209) (1282:1282:1282)) - (PORT datab (1379:1379:1379) (1450:1450:1450)) - (PORT datad (1863:1863:1863) (1920:1920:1920)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (413:413:413) (478:478:478)) + (PORT datab (593:593:593) (633:633:633)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1267:1267:1267) (1292:1292:1292)) - (PORT ena (942:942:942) (926:926:926)) + (PORT datad (815:815:815) (857:857:857)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1407:1407:1407) (1382:1382:1382)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1165:1165:1165) (1197:1197:1197)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -17977,12 +15509,27 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1268:1268:1268) (1294:1294:1294)) + (PORT dataa (617:617:617) (678:678:678)) + (PORT datab (842:842:842) (870:870:870)) + (PORT datad (643:643:643) (672:672:672)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1201:1201:1201) (1243:1243:1243)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -17993,14 +15540,169 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT datab (1779:1779:1779) (1898:1898:1898)) - (PORT datac (1045:1045:1045) (1061:1061:1061)) - (PORT datad (1611:1611:1611) (1668:1668:1668)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1200:1200:1200) (1247:1247:1247)) + (PORT ena (1220:1220:1220) (1214:1214:1214)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (705:705:705)) + (PORT datab (245:245:245) (328:328:328)) + (PORT datad (369:369:369) (400:400:400)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (812:812:812) (855:855:855)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1505:1505:1505) (1518:1518:1518)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1168:1168:1168) (1200:1200:1200)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (963:963:963)) + (PORT datab (606:606:606) (617:617:617)) + (PORT datac (548:548:548) (570:570:570)) + (PORT datad (1519:1519:1519) (1633:1633:1633)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (1020:1020:1020)) + (PORT datab (580:580:580) (595:595:595)) + (PORT datac (1000:1000:1000) (1021:1021:1021)) + (PORT datad (861:861:861) (896:896:896)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (681:681:681) (737:737:737)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (562:562:562)) + (PORT datab (612:612:612) (638:638:638)) + (PORT datac (854:854:854) (888:888:888)) + (PORT datad (607:607:607) (635:635:635)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (687:687:687)) + (PORT datab (643:643:643) (681:681:681)) + (PORT datac (1161:1161:1161) (1210:1210:1210)) + (PORT datad (581:581:581) (616:616:616)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (603:603:603) (634:634:634)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18008,43 +15710,54 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~9) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) (DELAY (ABSOLUTE - (PORT dataa (422:422:422) (475:475:475)) - (PORT datab (241:241:241) (324:324:324)) - (PORT datad (397:397:397) (430:430:430)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datab (1437:1437:1437) (1505:1505:1505)) + (PORT datac (1211:1211:1211) (1273:1273:1273)) + (PORT datad (849:849:849) (886:886:886)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT datab (1435:1435:1435) (1506:1506:1506)) + (PORT datac (1214:1214:1214) (1277:1277:1277)) + (PORT datad (841:841:841) (870:870:870)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT datab (1431:1431:1431) (1499:1499:1499)) + (PORT datac (1202:1202:1202) (1265:1265:1265)) + (PORT datad (842:842:842) (868:868:868)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1316:1316:1316) (1355:1355:1355)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1316:1316:1316) (1355:1355:1355)) - (PORT ena (979:979:979) (971:971:971)) + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1009:1009:1009) (1065:1065:1065)) + (PORT ena (990:990:990) (994:994:994)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18055,12 +15768,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~10) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) (DELAY (ABSOLUTE - (PORT dataa (422:422:422) (485:485:485)) - (PORT datab (426:426:426) (467:467:467)) - (PORT datad (215:215:215) (283:283:283)) + (PORT datab (1431:1431:1431) (1500:1500:1500)) + (PORT datac (1204:1204:1204) (1267:1267:1267)) + (PORT datad (851:851:851) (887:887:887)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1012:1012:1012) (1067:1067:1067)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (523:523:523)) + (PORT datab (490:490:490) (541:541:541)) + (PORT datad (217:217:217) (285:285:285)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -18069,29 +15812,41 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1513:1513:1513) (1542:1542:1542)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT datab (1436:1436:1436) (1501:1501:1501)) + (PORT datac (1209:1209:1209) (1271:1271:1271)) + (PORT datad (1072:1072:1072) (1103:1103:1103)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT datab (1436:1436:1436) (1506:1506:1506)) + (PORT datac (1213:1213:1213) (1276:1276:1276)) + (PORT datad (987:987:987) (1036:1036:1036)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1516:1516:1516) (1546:1546:1546)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1181:1181:1181) (1200:1200:1200)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18102,12 +15857,192 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~11) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) (DELAY (ABSOLUTE - (PORT dataa (383:383:383) (461:461:461)) - (PORT datab (660:660:660) (683:683:683)) - (PORT datad (628:628:628) (649:649:649)) + (PORT datab (1437:1437:1437) (1502:1502:1502)) + (PORT datac (1212:1212:1212) (1275:1275:1275)) + (PORT datad (1074:1074:1074) (1101:1101:1101)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1183:1183:1183) (1203:1203:1203)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT datab (1438:1438:1438) (1503:1503:1503)) + (PORT datac (1218:1218:1218) (1279:1279:1279)) + (PORT datad (985:985:985) (1032:1032:1032)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (988:988:988)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datad (882:882:882) (948:948:948)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT datab (1221:1221:1221) (1292:1292:1292)) + (PORT datac (894:894:894) (941:941:941)) + (PORT datad (886:886:886) (945:945:945)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1204:1204:1204) (1243:1243:1243)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (997:997:997)) + (PORT datab (1221:1221:1221) (1285:1285:1285)) + (PORT datad (879:879:879) (935:935:935)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1217:1217:1217)) + (PORT datab (204:204:204) (246:246:246)) + (PORT datac (1821:1821:1821) (1898:1898:1898)) + (PORT datad (203:203:203) (239:239:239)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (899:899:899)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (601:601:601) (662:662:662)) + (PORT datad (870:870:870) (912:912:912)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT dataa (1473:1473:1473) (1527:1527:1527)) + (PORT datac (833:833:833) (838:838:838)) + (PORT datad (1122:1122:1122) (1157:1157:1157)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (981:981:981) (1026:1026:1026)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1527:1527:1527)) + (PORT datac (835:835:835) (838:838:838)) + (PORT datad (1125:1125:1125) (1158:1158:1158)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1099:1099:1099)) + (PORT datab (1166:1166:1166) (1217:1217:1217)) + (PORT datad (239:239:239) (279:279:279)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -18116,13 +16051,37 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT datad (656:656:656) (709:709:709)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (DELAY + (ABSOLUTE + (PORT datab (1122:1122:1122) (1149:1149:1149)) + (PORT datac (1397:1397:1397) (1448:1448:1448)) + (PORT datad (822:822:822) (857:857:857)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) + (PORT ena (790:790:790) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18131,79 +16090,29 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (1196:1196:1196) (1229:1229:1229)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~13) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) (DELAY (ABSOLUTE - (PORT dataa (487:487:487) (523:523:523)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (666:666:666) (690:690:690)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1003:1003:1003) (1039:1039:1039)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1353:1353:1353)) - (PORT datab (1355:1355:1355) (1387:1387:1387)) - (PORT datad (389:389:389) (407:407:407)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (929:929:929) (987:987:987)) + (PORT datab (1220:1220:1220) (1288:1288:1288)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~14) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (332:332:332) (363:363:363)) - (PORT datac (640:640:640) (657:657:657)) - (PORT datad (601:601:601) (615:615:615)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (403:403:403) (454:454:454)) + (PORT datab (944:944:944) (1025:1025:1025)) + (PORT datac (1146:1146:1146) (1186:1186:1186)) + (PORT datad (666:666:666) (686:686:686)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18211,38 +16120,40 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) (DELAY (ABSOLUTE - (PORT datad (1178:1178:1178) (1226:1226:1226)) + (PORT datac (1438:1438:1438) (1484:1484:1484)) + (PORT datad (1123:1123:1123) (1155:1155:1155)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1170:1170:1170) (1265:1265:1265)) + (PORT datab (813:813:813) (832:832:832)) + (PORT datac (1134:1134:1134) (1171:1171:1171)) + (PORT datad (664:664:664) (713:713:713)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1262:1262:1262) (1321:1321:1321)) - (PORT ena (816:816:816) (813:813:813)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1504:1504:1504) (1545:1545:1545)) + (PORT ena (1131:1131:1131) (1098:1098:1098)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18253,12 +16164,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~8) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) (DELAY (ABSOLUTE - (PORT dataa (422:422:422) (483:483:483)) - (PORT datab (406:406:406) (433:433:433)) - (PORT datad (655:655:655) (713:713:713)) + (PORT datab (1121:1121:1121) (1148:1148:1148)) + (PORT datac (1398:1398:1398) (1447:1447:1447)) + (PORT datad (821:821:821) (856:856:856)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (453:453:453)) + (PORT datab (887:887:887) (923:923:923)) + (PORT datad (364:364:364) (388:388:388)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -18268,13 +16193,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~15) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (645:645:645) (696:696:696)) - (PORT datac (581:581:581) (606:606:606)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (408:408:408) (464:464:464)) + (PORT datab (1404:1404:1404) (1437:1437:1437)) + (PORT datac (1139:1139:1139) (1179:1179:1179)) + (PORT datad (663:663:663) (683:683:683)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -18284,13 +16209,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~21) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (634:634:634)) - (PORT datab (1979:1979:1979) (2129:2129:2129)) - (PORT datac (614:614:614) (631:631:631)) - (PORT datad (570:570:570) (584:584:584)) + (PORT dataa (1146:1146:1146) (1180:1180:1180)) + (PORT datab (815:815:815) (833:833:833)) + (PORT datac (1143:1143:1143) (1180:1180:1180)) + (PORT datad (671:671:671) (721:721:721)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -18298,25 +16223,1369 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|im2\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (180:180:180) (208:208:208)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1544:1544:1544)) + (PORT clk (1535:1535:1535) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1570:1570:1570) (1550:1550:1550)) - (PORT ena (1954:1954:1954) (1960:1960:1960)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1782:1782:1782) (1906:1906:1906)) + (PORT datab (973:973:973) (1022:1022:1022)) + (PORT datac (1471:1471:1471) (1489:1489:1489)) + (PORT datad (1978:1978:1978) (2013:2013:2013)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (660:660:660)) + (PORT datab (1249:1249:1249) (1275:1275:1275)) + (PORT datac (1822:1822:1822) (1900:1900:1900)) + (PORT datad (1106:1106:1106) (1134:1134:1134)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (687:687:687)) + (PORT datab (905:905:905) (971:971:971)) + (PORT datac (861:861:861) (888:888:888)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1153:1153:1153) (1178:1178:1178)) + (PORT datad (204:204:204) (241:241:241)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (713:713:713) (766:766:766)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (346:346:346) (370:370:370)) + (PORT datad (1145:1145:1145) (1176:1176:1176)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (DELAY + (ABSOLUTE + (PORT datab (922:922:922) (944:944:944)) + (PORT datac (595:595:595) (615:615:615)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (900:900:900)) + (PORT datac (1144:1144:1144) (1163:1163:1163)) + (PORT datad (832:832:832) (861:861:861)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1506:1506:1506) (1545:1545:1545)) + (PORT ena (1261:1261:1261) (1299:1299:1299)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (899:899:899)) + (PORT datac (1138:1138:1138) (1159:1159:1159)) + (PORT datad (835:835:835) (861:861:861)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1149:1149:1149)) + (PORT datab (1280:1280:1280) (1386:1386:1386)) + (PORT datad (842:842:842) (869:869:869)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (693:693:693)) + (PORT datab (1259:1259:1259) (1346:1346:1346)) + (PORT datac (1146:1146:1146) (1187:1187:1187)) + (PORT datad (374:374:374) (412:412:412)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (990:990:990) (1035:1035:1035)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (462:462:462)) + (PORT datab (1258:1258:1258) (1341:1341:1341)) + (PORT datac (1142:1142:1142) (1186:1186:1186)) + (PORT datad (664:664:664) (686:686:686)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (696:696:696)) + (PORT datab (1255:1255:1255) (1339:1339:1339)) + (PORT datac (1141:1141:1141) (1184:1184:1184)) + (PORT datad (375:375:375) (413:413:413)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (989:989:989) (1035:1035:1035)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (457:457:457)) + (PORT datab (1258:1258:1258) (1344:1344:1344)) + (PORT datac (1146:1146:1146) (1187:1187:1187)) + (PORT datad (666:666:666) (682:682:682)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (485:485:485)) + (PORT datab (1600:1600:1600) (1653:1653:1653)) + (PORT datad (1181:1181:1181) (1221:1221:1221)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (634:634:634)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (787:787:787) (785:785:785)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (653:653:653)) + (PORT datab (336:336:336) (368:368:368)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (626:626:626) (642:642:642)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (988:988:988)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (618:618:618) (661:661:661)) + (PORT datad (787:787:787) (791:791:791)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1064:1064:1064) (1103:1103:1103)) + (PORT datab (836:836:836) (868:868:868)) + (PORT datac (218:218:218) (261:261:261)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (671:671:671)) + (PORT datab (834:834:834) (892:892:892)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (874:874:874) (899:899:899)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1547:1547:1547) (1564:1564:1564)) + (PORT datab (851:851:851) (910:910:910)) + (PORT datac (1130:1130:1130) (1151:1151:1151)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1399:1399:1399)) + (PORT datac (1141:1141:1141) (1164:1164:1164)) + (PORT datad (832:832:832) (866:866:866)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1308:1308:1308) (1303:1303:1303)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1187:1187:1187) (1229:1229:1229)) + (PORT ena (990:990:990) (994:994:994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1186:1186:1186) (1227:1227:1227)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (460:460:460) (523:523:523)) + (PORT datab (492:492:492) (541:541:541)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1950:1950:1950) (1996:1996:1996)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (991:991:991)) + (PORT datab (1222:1222:1222) (1291:1291:1291)) + (PORT datad (879:879:879) (935:935:935)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (545:545:545) (579:579:579)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1716:1716:1716) (1767:1767:1767)) + (PORT ena (1261:1261:1261) (1299:1299:1299)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1151:1151:1151)) + (PORT datab (648:648:648) (728:728:728)) + (PORT datad (845:845:845) (876:876:876)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (2219:2219:2219) (2260:2260:2260)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (881:881:881)) + (PORT datab (1166:1166:1166) (1218:1218:1218)) + (PORT datad (240:240:240) (280:280:280)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1976:1976:1976) (2020:2020:2020)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1977:1977:1977) (2023:2023:2023)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (466:466:466)) + (PORT datab (1593:1593:1593) (1643:1643:1643)) + (PORT datad (1180:1180:1180) (1216:1216:1216)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1715:1715:1715) (1766:1766:1766)) + (PORT ena (1131:1131:1131) (1098:1098:1098)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1611:1611:1611) (1650:1650:1650)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (433:433:433)) + (PORT datab (886:886:886) (923:923:923)) + (PORT datad (859:859:859) (925:925:925)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (632:632:632) (649:649:649)) + (PORT datac (338:338:338) (358:358:358)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (2372:2372:2372) (2423:2423:2423)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (2371:2371:2371) (2423:2423:2423)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (986:986:986)) + (PORT datab (911:911:911) (986:986:986)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (672:672:672)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (596:596:596) (613:613:613)) + (PORT datad (313:313:313) (323:323:323)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (944:944:944)) + (PORT datab (543:543:543) (563:563:563)) + (PORT datac (1049:1049:1049) (1102:1102:1102)) + (PORT datad (1297:1297:1297) (1338:1338:1338)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (911:911:911)) + (PORT datac (1138:1138:1138) (1159:1159:1159)) + (PORT datad (844:844:844) (869:869:869)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (909:909:909)) + (PORT datac (1140:1140:1140) (1164:1164:1164)) + (PORT datad (844:844:844) (871:871:871)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (1391:1391:1391) (1443:1443:1443)) + (PORT ena (935:935:935) (924:924:924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1171:1171:1171) (1195:1195:1195)) + (PORT datab (835:835:835) (855:855:855)) + (PORT datac (1143:1143:1143) (1163:1163:1163)) + (PORT datad (844:844:844) (868:868:868)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (276:276:276)) + (PORT datab (409:409:409) (450:450:450)) + (PORT datad (382:382:382) (419:419:419)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1398:1398:1398)) + (PORT datac (1141:1141:1141) (1165:1165:1165)) + (PORT datad (832:832:832) (866:866:866)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datac (762:762:762) (815:815:815)) + (PORT datad (642:642:642) (666:666:666)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (292:292:292)) + (PORT datab (235:235:235) (277:277:277)) + (PORT datac (1097:1097:1097) (1113:1113:1113)) + (PORT datad (212:212:212) (246:246:246)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (508:508:508)) + (PORT datab (279:279:279) (364:364:364)) + (PORT datac (1332:1332:1332) (1337:1337:1337)) + (PORT datad (184:184:184) (216:216:216)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (951:951:951) (975:975:975)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (951:951:951) (974:974:974)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (978:978:978)) + (PORT datab (914:914:914) (989:989:989)) + (PORT datad (214:214:214) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1393:1393:1393) (1432:1432:1432)) + (PORT ena (990:990:990) (994:994:994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1390:1390:1390) (1429:1429:1429)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (517:517:517)) + (PORT datab (496:496:496) (537:537:537)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1278:1278:1278) (1308:1308:1308)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1278:1278:1278) (1306:1306:1306)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (458:458:458)) + (PORT datab (1599:1599:1599) (1646:1646:1646)) + (PORT datad (1181:1181:1181) (1215:1215:1215)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1228:1228:1228) (1277:1277:1277)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1070:1070:1070)) + (PORT datab (1167:1167:1167) (1216:1216:1216)) + (PORT datad (237:237:237) (277:277:277)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (810:810:810) (862:862:862)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1214:1214:1214) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1259:1259:1259) (1290:1290:1290)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (243:243:243) (289:289:289)) + (PORT datad (875:875:875) (901:901:901)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (689:689:689) (709:709:709)) + (PORT ena (1404:1404:1404) (1382:1382:1382)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1474:1474:1474) (1488:1488:1488)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1072:1072:1072)) + (PORT datab (1270:1270:1270) (1360:1360:1360)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (872:872:872)) + (PORT datab (1030:1030:1030) (1072:1072:1072)) + (PORT datac (803:803:803) (856:856:856)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (969:969:969) (986:986:986)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (986:986:986)) + (PORT datab (1221:1221:1221) (1292:1292:1292)) + (PORT datad (887:887:887) (945:945:945)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (429:429:429)) + (PORT datab (829:829:829) (880:880:880)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (558:558:558) (582:582:582)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (864:864:864)) + (PORT datab (867:867:867) (903:903:903)) + (PORT datac (808:808:808) (862:862:862)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1554:1554:1554)) + (PORT asdata (881:881:881) (888:888:888)) + (PORT ena (940:940:940) (926:926:926)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (288:288:288)) + (PORT datab (905:905:905) (941:941:941)) + (PORT datad (211:211:211) (245:245:245)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (288:288:288)) + (PORT datac (214:214:214) (290:290:290)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1135:1135:1135) (1153:1153:1153)) + (PORT datab (827:827:827) (837:837:837)) + (PORT datac (199:199:199) (234:234:234)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (733:733:733)) + (PORT datac (799:799:799) (817:817:817)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2152:2152:2152) (2220:2220:2220)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -18328,13 +17597,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) (DELAY (ABSOLUTE - (PORT dataa (341:341:341) (458:458:458)) - (PORT datac (1002:1002:1002) (1025:1025:1025)) - (PORT datad (283:283:283) (369:369:369)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (422:422:422) (513:513:513)) + (PORT datab (280:280:280) (369:369:369)) + (PORT datac (1329:1329:1329) (1334:1334:1334)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18342,14 +17613,431 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (456:456:456)) - (PORT datab (349:349:349) (381:381:381)) - (PORT datac (1043:1043:1043) (1054:1054:1054)) - (PORT datad (1085:1085:1085) (1095:1095:1095)) - (IOPATH dataa combout (301:301:301) (299:299:299)) + (PORT datac (248:248:248) (337:337:337)) + (PORT datad (324:324:324) (346:346:346)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (712:712:712) (756:756:756)) + (PORT datac (810:810:810) (842:842:842)) + (PORT datad (578:578:578) (586:586:586)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datab (355:355:355) (385:385:385)) + (PORT datac (880:880:880) (911:911:911)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (554:554:554) (561:561:561)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2096:2096:2096) (2133:2133:2133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (268:268:268) (364:364:364)) + (PORT datab (279:279:279) (374:374:374)) + (PORT datac (1335:1335:1335) (1349:1349:1349)) + (PORT datad (325:325:325) (343:343:343)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1106:1106:1106) (1145:1145:1145)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1107:1107:1107) (1146:1146:1146)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (980:980:980)) + (PORT datab (914:914:914) (982:982:982)) + (PORT datad (216:216:216) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1947:1947:1947) (2004:2004:2004)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (827:827:827)) + (PORT datab (1168:1168:1168) (1216:1216:1216)) + (PORT datad (240:240:240) (281:281:281)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1439:1439:1439) (1508:1508:1508)) + (PORT ena (1131:1131:1131) (1098:1098:1098)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (778:778:778) (850:850:850)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (433:433:433)) + (PORT datab (886:886:886) (923:923:923)) + (PORT datad (350:350:350) (406:406:406)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1005:1005:1005) (1055:1055:1055)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1994:1994:1994) (2075:2075:2075)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (641:641:641)) + (PORT datab (1599:1599:1599) (1649:1649:1649)) + (PORT datad (1179:1179:1179) (1219:1219:1219)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1439:1439:1439) (1506:1506:1506)) + (PORT ena (1261:1261:1261) (1299:1299:1299)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1147:1147:1147)) + (PORT datab (678:678:678) (753:753:753)) + (PORT datad (849:849:849) (878:878:878)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (653:653:653)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (599:599:599) (617:617:617)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (2176:2176:2176) (2269:2269:2269)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (2177:2177:2177) (2273:2273:2273)) + (PORT ena (990:990:990) (994:994:994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (524:524:524)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datad (454:454:454) (497:497:497)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (2201:2201:2201) (2285:2285:2285)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (990:990:990)) + (PORT datab (1220:1220:1220) (1290:1290:1290)) + (PORT datad (884:884:884) (941:941:941)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (837:837:837)) + (PORT datab (560:560:560) (597:597:597)) + (PORT datac (558:558:558) (555:555:555)) + (PORT datad (850:850:850) (877:877:877)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -18358,13 +18046,92 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[6\]\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) (DELAY (ABSOLUTE - (PORT datab (564:564:564) (591:591:591)) - (PORT datac (1262:1262:1262) (1278:1278:1278)) - (PORT datad (673:673:673) (695:695:695)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (837:837:837) (909:909:909)) + (PORT datab (396:396:396) (421:421:421)) + (PORT datac (848:848:848) (907:907:907)) + (PORT datad (1297:1297:1297) (1337:1337:1337)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1554:1554:1554)) + (PORT asdata (545:545:545) (579:579:579)) + (PORT ena (940:940:940) (926:926:926)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1897:1897:1897) (1987:1987:1987)) + (PORT datab (235:235:235) (281:281:281)) + (PORT datad (211:211:211) (246:246:246)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (287:287:287)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (354:354:354) (413:413:413)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1139:1139:1139) (1156:1156:1156)) + (PORT datab (545:545:545) (561:561:561)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18372,15 +18139,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~10) + (INSTANCE z80_\|address_latch_\|abusz\[10\]) (DELAY (ABSOLUTE - (PORT dataa (676:676:676) (722:722:722)) - (PORT datab (1065:1065:1065) (1094:1094:1094)) - (PORT datac (1265:1265:1265) (1291:1291:1291)) - (PORT datad (1301:1301:1301) (1340:1340:1340)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datac (200:200:200) (235:235:235)) + (PORT datad (869:869:869) (899:899:899)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18388,27 +18151,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) + (INSTANCE z80_\|address_latch_\|Q\[10\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (1311:1311:1311) (1355:1355:1355)) - (PORT datab (1295:1295:1295) (1335:1335:1335)) - (PORT datac (3295:3295:3295) (3389:3389:3389)) - (PORT datad (684:684:684) (742:742:742)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (531:531:531) (546:546:546)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~4) + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) (DELAY (ABSOLUTE - (PORT datac (853:853:853) (893:893:893)) - (PORT datad (1100:1100:1100) (1131:1131:1131)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2096:2096:2096) (2133:2133:2133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (368:368:368)) + (PORT datab (276:276:276) (370:370:370)) + (PORT datac (1338:1338:1338) (1352:1352:1352)) + (PORT datad (324:324:324) (345:345:345)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18416,15 +18195,102 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (INSTANCE z80_\|address_latch_\|abusz\[11\]) (DELAY (ABSOLUTE - (PORT dataa (1371:1371:1371) (1473:1473:1473)) - (PORT datab (218:218:218) (264:264:264)) - (PORT datac (627:627:627) (663:663:663)) - (PORT datad (1145:1145:1145) (1247:1247:1247)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT datab (602:602:602) (632:632:632)) + (PORT datad (924:924:924) (945:945:945)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2096:2096:2096) (2133:2133:2133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datac (568:568:568) (632:632:632)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1308:1308:1308) (1303:1303:1303)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (738:738:738) (772:772:772)) + (PORT ena (935:935:935) (924:924:924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (407:407:407) (446:446:446)) + (PORT datad (388:388:388) (422:422:422)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (335:335:335)) + (PORT datac (823:823:823) (870:870:870)) + (PORT datad (639:639:639) (664:664:664)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18432,15 +18298,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~12) + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) (DELAY (ABSOLUTE - (PORT dataa (1022:1022:1022) (1061:1061:1061)) - (PORT datab (670:670:670) (731:731:731)) - (PORT datac (878:878:878) (926:926:926)) - (PORT datad (1043:1043:1043) (1048:1048:1048)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (565:565:565) (577:577:577)) + (PORT datab (846:846:846) (883:883:883)) + (PORT datac (679:679:679) (728:728:728)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18448,15 +18314,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) (DELAY (ABSOLUTE - (PORT dataa (930:930:930) (982:982:982)) - (PORT datab (1567:1567:1567) (1604:1604:1604)) - (PORT datac (1865:1865:1865) (1960:1960:1960)) - (PORT datad (1072:1072:1072) (1090:1090:1090)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (612:612:612) (644:644:644)) + (PORT datab (820:820:820) (880:880:880)) + (PORT datac (393:393:393) (430:430:430)) + (PORT datad (1301:1301:1301) (1333:1333:1333)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (916:916:916)) + (PORT datab (223:223:223) (272:272:272)) + (PORT datac (1159:1159:1159) (1203:1203:1203)) + (PORT datad (607:607:607) (634:634:634)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1068:1068:1068)) + (PORT datab (2092:2092:2092) (2152:2152:2152)) + (PORT datac (686:686:686) (739:739:739)) + (PORT datad (1737:1737:1737) (1857:1857:1857)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18464,13 +18362,89 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) (DELAY (ABSOLUTE - (PORT dataa (560:560:560) (576:576:576)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (607:607:607) (623:623:623)) - (PORT datad (174:174:174) (200:200:200)) + (PORT datab (964:964:964) (1009:1009:1009)) + (PORT datac (1166:1166:1166) (1163:1163:1163)) + (PORT datad (680:680:680) (717:717:717)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (652:652:652) (711:711:711)) + (PORT datac (647:647:647) (707:707:707)) + (PORT datad (634:634:634) (661:661:661)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (713:713:713)) + (PORT datab (641:641:641) (708:708:708)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (575:575:575) (599:599:599)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1169:1169:1169)) + (PORT datab (1268:1268:1268) (1379:1379:1379)) + (PORT datac (613:613:613) (634:634:634)) + (PORT datad (1131:1131:1131) (1134:1134:1134)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2003:2003:2003) (2192:2192:2192)) + (PORT datab (1271:1271:1271) (1346:1346:1346)) + (PORT datac (994:994:994) (1035:1035:1035)) + (PORT datad (1461:1461:1461) (1531:1531:1531)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -18480,15 +18454,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~0) + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) (DELAY (ABSOLUTE - (PORT dataa (1121:1121:1121) (1188:1188:1188)) - (PORT datab (674:674:674) (710:710:710)) - (PORT datac (1115:1115:1115) (1130:1130:1130)) - (PORT datad (864:864:864) (912:912:912)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1013:1013:1013) (1048:1048:1048)) + (PORT datab (1598:1598:1598) (1713:1713:1713)) + (PORT datac (1145:1145:1145) (1147:1147:1147)) + (PORT datad (654:654:654) (698:698:698)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2564:2564:2564) (2702:2702:2702)) + (PORT datab (1558:1558:1558) (1680:1680:1680)) + (PORT datac (866:866:866) (908:908:908)) + (PORT datad (191:191:191) (224:224:224)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18496,15 +18486,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) (DELAY (ABSOLUTE - (PORT dataa (1129:1129:1129) (1167:1167:1167)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (203:203:203) (240:240:240)) - (PORT datad (850:850:850) (873:873:873)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (385:385:385) (411:411:411)) + (PORT datab (804:804:804) (851:851:851)) + (PORT datac (829:829:829) (862:862:862)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18512,24 +18502,56 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~1) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) (DELAY (ABSOLUTE - (PORT datab (197:197:197) (236:236:236)) - (PORT datad (1141:1141:1141) (1191:1191:1191)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (647:647:647) (668:668:668)) + (PORT datab (1164:1164:1164) (1226:1226:1226)) + (PORT datac (562:562:562) (562:562:562)) + (PORT datad (595:595:595) (626:626:626)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (616:616:616)) + (PORT datab (1125:1125:1125) (1173:1173:1173)) + (PORT datac (561:561:561) (579:579:579)) + (PORT datad (905:905:905) (952:952:952)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (332:332:332)) + (PORT datac (170:170:170) (202:202:202)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) (DELAY (ABSOLUTE - (PORT dataa (1119:1119:1119) (1184:1184:1184)) - (PORT datac (1121:1121:1121) (1138:1138:1138)) - (PORT datad (1141:1141:1141) (1194:1194:1194)) + (PORT dataa (263:263:263) (339:339:339)) + (PORT datac (1090:1090:1090) (1144:1144:1144)) + (PORT datad (902:902:902) (951:951:951)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -18541,9 +18563,9 @@ (INSTANCE z80_\|alu_\|op2_high\[1\]) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) + (PORT clk (1529:1529:1529) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18557,10 +18579,10 @@ (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) (DELAY (ABSOLUTE - (PORT dataa (1132:1132:1132) (1171:1171:1171)) - (PORT datac (632:632:632) (657:657:657)) - (PORT datad (877:877:877) (940:940:940)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT datab (968:968:968) (1010:1010:1010)) + (PORT datac (370:370:370) (404:404:404)) + (PORT datad (675:675:675) (715:715:715)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18571,7 +18593,7 @@ (INSTANCE z80_\|alu_\|op1_high\[1\]) (DELAY (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) + (PORT clk (1530:1530:1530) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -18584,15 +18606,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~3) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (885:885:885) (960:960:960)) - (PORT datab (1015:1015:1015) (1029:1029:1029)) - (PORT datac (911:911:911) (959:959:959)) - (PORT datad (861:861:861) (877:877:877)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (676:676:676) (733:733:733)) + (PORT datab (1128:1128:1128) (1182:1182:1182)) + (PORT datac (588:588:588) (620:620:620)) + (PORT datad (380:380:380) (439:439:439)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (340:340:340)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (556:556:556) (578:578:578)) + (PORT datad (900:900:900) (949:949:949)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1468:1468:1468) (1479:1479:1479)) + (PORT datab (1497:1497:1497) (1572:1572:1572)) + (PORT datac (1847:1847:1847) (1915:1915:1915)) + (PORT datad (402:402:402) (438:438:438)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1433:1433:1433) (1518:1518:1518)) + (PORT datab (1643:1643:1643) (1769:1769:1769)) + (PORT datac (1052:1052:1052) (1102:1102:1102)) + (PORT datad (1294:1294:1294) (1385:1385:1385)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (898:898:898)) + (PORT datab (943:943:943) (983:983:983)) + (PORT datac (858:858:858) (877:877:877)) + (PORT datad (654:654:654) (664:664:664)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18600,14 +18702,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~2) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) (DELAY (ABSOLUTE - (PORT dataa (673:673:673) (725:725:725)) - (PORT datab (1066:1066:1066) (1098:1098:1098)) - (PORT datac (1264:1264:1264) (1298:1298:1298)) - (PORT datad (1299:1299:1299) (1342:1342:1342)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (480:480:480) (518:518:518)) + (PORT datab (1187:1187:1187) (1249:1249:1249)) + (PORT datac (925:925:925) (1011:1011:1011)) + (PORT datad (1383:1383:1383) (1482:1482:1482)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -18616,373 +18718,720 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~9) + (INSTANCE z80_\|pla_decode_\|Equal61\~2) (DELAY (ABSOLUTE - (PORT dataa (1111:1111:1111) (1142:1142:1142)) - (PORT datab (878:878:878) (903:903:903)) - (PORT datad (1149:1149:1149) (1165:1165:1165)) + (PORT dataa (1746:1746:1746) (1869:1869:1869)) + (PORT datab (1375:1375:1375) (1426:1426:1426)) + (PORT datac (1591:1591:1591) (1672:1672:1672)) + (PORT datad (1495:1495:1495) (1627:1627:1627)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT datab (1828:1828:1828) (1926:1926:1926)) + (PORT datac (1699:1699:1699) (1792:1792:1792)) + (PORT datad (926:926:926) (994:994:994)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1872:1872:1872) (1889:1889:1889)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (880:880:880) (886:886:886)) + (PORT datad (803:803:803) (814:814:814)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1342:1342:1342) (1440:1440:1440)) + (PORT datab (1765:1765:1765) (1873:1873:1873)) + (PORT datac (1447:1447:1447) (1536:1536:1536)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1520:1520:1520) (1609:1609:1609)) + (PORT datab (925:925:925) (988:988:988)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (262:262:262)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1766:1766:1766) (1808:1808:1808)) + (PORT datab (836:836:836) (862:862:862)) + (PORT datac (1306:1306:1306) (1421:1421:1421)) + (PORT datad (2555:2555:2555) (2677:2677:2677)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (614:614:614)) + (PORT datab (246:246:246) (286:286:286)) + (PORT datac (221:221:221) (257:257:257)) + (PORT datad (904:904:904) (976:976:976)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1051:1051:1051) (1075:1075:1075)) + (PORT datab (1615:1615:1615) (1655:1655:1655)) + (PORT datac (1187:1187:1187) (1227:1227:1227)) + (PORT datad (1742:1742:1742) (1769:1769:1769)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (921:921:921)) + (PORT datab (941:941:941) (1014:1014:1014)) + (PORT datac (219:219:219) (254:254:254)) + (PORT datad (903:903:903) (974:974:974)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (258:258:258)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1272:1272:1272)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (2061:2061:2061) (2171:2171:2171)) + (PORT datad (1409:1409:1409) (1503:1503:1503)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (718:718:718)) + (PORT datab (1484:1484:1484) (1542:1542:1542)) + (PORT datac (1486:1486:1486) (1511:1511:1511)) + (PORT datad (640:640:640) (654:654:654)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (857:857:857)) + (PORT datab (1485:1485:1485) (1542:1542:1542)) + (PORT datac (1608:1608:1608) (1613:1613:1613)) + (PORT datad (1444:1444:1444) (1563:1563:1563)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (213:213:213) (257:257:257)) + (PORT datac (838:838:838) (870:870:870)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1070:1070:1070) (1092:1092:1092)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal72\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1402:1402:1402) (1477:1477:1477)) + (PORT datab (2359:2359:2359) (2492:2492:2492)) + (PORT datac (1132:1132:1132) (1171:1171:1171)) + (PORT datad (855:855:855) (857:857:857)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2002:2002:2002) (2149:2149:2149)) + (PORT datab (1120:1120:1120) (1189:1189:1189)) + (PORT datac (1350:1350:1350) (1403:1403:1403)) + (PORT datad (855:855:855) (872:872:872)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (975:975:975) (1049:1049:1049)) + (PORT datab (960:960:960) (1047:1047:1047)) + (PORT datac (1782:1782:1782) (1803:1803:1803)) + (PORT datad (1450:1450:1450) (1533:1533:1533)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1044:1044:1044) (1059:1059:1059)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (616:616:616) (640:640:640)) + (PORT datad (601:601:601) (613:613:613)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1518:1518:1518) (1586:1586:1586)) + (PORT datab (1962:1962:1962) (1991:1991:1991)) + (PORT datac (1263:1263:1263) (1313:1313:1313)) + (PORT datad (933:933:933) (1002:1002:1002)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT datab (864:864:864) (893:893:893)) + (PORT datac (819:819:819) (853:853:853)) + (PORT datad (811:811:811) (845:845:845)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2565:2565:2565) (2704:2704:2704)) + (PORT datac (1529:1529:1529) (1648:1648:1648)) + (PORT datad (1533:1533:1533) (1667:1667:1667)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (304:304:304)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (1176:1176:1176) (1212:1212:1212)) + (PORT datad (191:191:191) (224:224:224)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (859:859:859)) + (PORT datab (618:618:618) (647:647:647)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (802:802:802) (881:881:881)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (957:957:957)) + (PORT datac (824:824:824) (856:856:856)) + (PORT datad (647:647:647) (680:680:680)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (960:960:960)) + (PORT datab (362:362:362) (394:394:394)) + (PORT datac (591:591:591) (619:619:619)) + (PORT datad (338:338:338) (357:357:357)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) + (DELAY + (ABSOLUTE + (PORT datac (891:891:891) (933:933:933)) + (PORT datad (831:831:831) (843:843:843)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (649:649:649)) + (PORT datab (1105:1105:1105) (1114:1114:1114)) + (PORT datac (753:753:753) (781:781:781)) + (PORT datad (613:613:613) (631:631:631)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (942:942:942)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2002:2002:2002) (2062:2062:2062)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (1707:1707:1707) (1823:1823:1823)) + (PORT datad (1505:1505:1505) (1539:1539:1539)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1137:1137:1137) (1211:1211:1211)) + (PORT datab (1568:1568:1568) (1705:1705:1705)) + (PORT datac (2532:2532:2532) (2663:2663:2663)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1063:1063:1063)) + (PORT datab (1299:1299:1299) (1349:1349:1349)) + (PORT datac (890:890:890) (914:914:914)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (665:665:665)) + (PORT datab (2303:2303:2303) (2383:2383:2383)) + (PORT datac (2057:2057:2057) (2199:2199:2199)) + (PORT datad (1163:1163:1163) (1186:1186:1186)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (640:640:640)) + (PORT datab (608:608:608) (638:638:638)) + (PORT datac (549:549:549) (557:557:557)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1068:1068:1068)) + (PORT datab (2030:2030:2030) (2166:2166:2166)) + (PORT datac (821:821:821) (831:831:831)) + (PORT datad (2503:2503:2503) (2629:2629:2629)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1546:1546:1546) (1624:1624:1624)) + (PORT datab (938:938:938) (1017:1017:1017)) + (PORT datac (601:601:601) (662:662:662)) + (PORT datad (580:580:580) (585:585:585)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (920:920:920)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (666:666:666) (685:685:685)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (680:680:680)) + (PORT datab (1172:1172:1172) (1198:1198:1198)) + (PORT datac (636:636:636) (693:693:693)) + (PORT datad (307:307:307) (324:324:324)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (694:694:694)) + (PORT datab (806:806:806) (876:876:876)) + (PORT datac (1101:1101:1101) (1130:1130:1130)) + (PORT datad (589:589:589) (627:627:627)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (667:667:667)) + (PORT datab (654:654:654) (679:679:679)) + (PORT datac (936:936:936) (1033:1033:1033)) + (PORT datad (830:830:830) (861:861:861)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1518:1518:1518) (1588:1588:1588)) + (PORT datab (1051:1051:1051) (1075:1075:1075)) + (PORT datac (1263:1263:1263) (1316:1316:1316)) + (PORT datad (930:930:930) (999:999:999)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1452:1452:1452) (1482:1482:1482)) + (PORT datab (1142:1142:1142) (1181:1181:1181)) + (PORT datac (1196:1196:1196) (1287:1287:1287)) + (PORT datad (1139:1139:1139) (1160:1160:1160)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (646:646:646)) + (PORT datab (1014:1014:1014) (1076:1076:1076)) + (PORT datac (798:798:798) (807:807:807)) + (PORT datad (619:619:619) (632:632:632)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1787:1787:1787) (1827:1827:1827)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1789:1789:1789) (1828:1828:1828)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~70) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) (DELAY (ABSOLUTE - (PORT dataa (672:672:672) (700:700:700)) - (PORT datab (244:244:244) (326:326:326)) - (PORT datad (632:632:632) (651:651:651)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (230:230:230) (276:276:276)) + (PORT datab (1030:1030:1030) (1067:1067:1067)) + (PORT datac (871:871:871) (866:866:866)) + (PORT datad (599:599:599) (614:614:614)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (1972:1972:1972) (2034:2034:2034)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~72) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) (DELAY (ABSOLUTE - (PORT dataa (486:486:486) (521:521:521)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (664:664:664) (693:693:693)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (705:705:705) (732:732:732)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (1337:1337:1337) (1364:1364:1364)) - (PORT datab (845:845:845) (875:875:875)) - (PORT datad (387:387:387) (410:410:410)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1778:1778:1778) (1814:1814:1814)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (1773:1773:1773) (1809:1809:1809)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (473:473:473)) - (PORT datab (429:429:429) (472:472:472)) - (PORT datad (363:363:363) (425:425:425)) + (PORT dataa (583:583:583) (619:619:619)) + (PORT datab (225:225:225) (273:273:273)) + (PORT datac (824:824:824) (846:846:846)) + (PORT datad (1377:1377:1377) (1491:1491:1491)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (618:618:618)) - (PORT datab (648:648:648) (667:667:667)) - (PORT datac (603:603:603) (617:617:617)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1610:1610:1610) (1660:1660:1660)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1613:1613:1613) (1663:1663:1663)) - (PORT ena (1011:1011:1011) (1021:1021:1021)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (332:332:332)) - (PORT datab (688:688:688) (758:758:758)) - (PORT datad (231:231:231) (265:265:265)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1429:1429:1429) (1453:1453:1453)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1210:1210:1210) (1276:1276:1276)) - (PORT datab (1385:1385:1385) (1453:1453:1453)) - (PORT datad (1859:1859:1859) (1914:1914:1914)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1240:1240:1240) (1258:1258:1258)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1243:1243:1243) (1262:1262:1262)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (420:420:420) (474:474:474)) - (PORT datab (436:436:436) (465:465:465)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (647:647:647)) - (PORT datab (330:330:330) (359:359:359)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (589:589:589) (638:638:638)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (658:658:658)) - (PORT datab (1983:1983:1983) (2132:2132:2132)) - (PORT datac (585:585:585) (606:606:606)) - (PORT datad (569:569:569) (584:584:584)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1149:1149:1149)) - (PORT datab (1192:1192:1192) (1209:1209:1209)) - (PORT datac (954:954:954) (998:998:998)) - (PORT datad (1694:1694:1694) (1741:1741:1741)) - (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -18991,15 +19440,172 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) (DELAY (ABSOLUTE - (PORT dataa (685:685:685) (716:716:716)) - (PORT datab (248:248:248) (305:305:305)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (846:846:846) (858:858:858)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT dataa (780:780:780) (837:837:837)) + (PORT datab (827:827:827) (864:864:864)) + (PORT datac (762:762:762) (835:835:835)) + (PORT datad (767:767:767) (810:810:810)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1230:1230:1230) (1277:1277:1277)) + (PORT datab (699:699:699) (755:755:755)) + (PORT datac (917:917:917) (964:964:964)) + (PORT datad (1070:1070:1070) (1101:1101:1101)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (667:667:667)) + (PORT datab (653:653:653) (673:673:673)) + (PORT datac (935:935:935) (1036:1036:1036)) + (PORT datad (387:387:387) (408:408:408)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (1042:1042:1042)) + (PORT datab (1807:1807:1807) (1835:1835:1835)) + (PORT datac (1262:1262:1262) (1315:1315:1315)) + (PORT datad (1069:1069:1069) (1081:1081:1081)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2018:2018:2018) (2105:2105:2105)) + (PORT datab (2408:2408:2408) (2537:2537:2537)) + (PORT datac (1381:1381:1381) (1441:1441:1441)) + (PORT datad (1576:1576:1576) (1733:1733:1733)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1517:1517:1517) (1579:1579:1579)) + (PORT datab (385:385:385) (404:404:404)) + (PORT datac (1263:1263:1263) (1308:1308:1308)) + (PORT datad (871:871:871) (923:923:923)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1269:1269:1269)) + (PORT datab (340:340:340) (375:375:375)) + (PORT datac (1057:1057:1057) (1084:1084:1084)) + (PORT datad (337:337:337) (358:358:358)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (385:385:385)) + (PORT datab (643:643:643) (665:665:665)) + (PORT datac (169:169:169) (201:201:201)) + (PORT datad (616:616:616) (624:624:624)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (887:887:887)) + (PORT datab (1118:1118:1118) (1197:1197:1197)) + (PORT datac (848:848:848) (898:898:898)) + (PORT datad (364:364:364) (426:426:426)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19007,15 +19613,203 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) (DELAY (ABSOLUTE - (PORT dataa (857:857:857) (879:879:879)) - (PORT datab (1474:1474:1474) (1579:1579:1579)) - (PORT datac (1557:1557:1557) (1550:1550:1550)) - (PORT datad (1116:1116:1116) (1188:1188:1188)) - (IOPATH dataa combout (303:303:303) (299:299:299)) + (PORT dataa (2563:2563:2563) (2705:2705:2705)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1385:1385:1385) (1391:1391:1391)) + (PORT datad (1888:1888:1888) (1980:1980:1980)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (529:529:529)) + (PORT datab (452:452:452) (522:522:522)) + (PORT datac (877:877:877) (897:897:897)) + (PORT datad (660:660:660) (680:680:680)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (573:573:573)) + (PORT datab (633:633:633) (685:685:685)) + (PORT datac (619:619:619) (639:639:639)) + (PORT datad (630:630:630) (672:672:672)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (850:850:850)) + (PORT datab (621:621:621) (640:640:640)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (823:823:823)) + (PORT datab (610:610:610) (633:633:633)) + (PORT datac (1092:1092:1092) (1142:1142:1142)) + (PORT datad (895:895:895) (948:948:948)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (232:232:232) (287:287:287)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (432:432:432) (521:521:521)) + (PORT datab (682:682:682) (739:739:739)) + (PORT datac (877:877:877) (897:897:897)) + (PORT datad (660:660:660) (685:685:685)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (922:922:922)) + (PORT datab (224:224:224) (269:269:269)) + (PORT datac (826:826:826) (848:848:848)) + (PORT datad (904:904:904) (974:974:974)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (842:842:842)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (1821:1821:1821) (1815:1815:1815)) + (PORT datad (790:790:790) (826:826:826)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (706:706:706)) + (PORT datab (1772:1772:1772) (1798:1798:1798)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (823:823:823) (837:837:837)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (DELAY + (ABSOLUTE + (PORT dataa (2390:2390:2390) (2544:2544:2544)) + (PORT datab (1497:1497:1497) (1581:1581:1581)) + (PORT datac (874:874:874) (897:897:897)) + (PORT datad (1014:1014:1014) (1128:1128:1128)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (605:605:605)) + (PORT datab (974:974:974) (1056:1056:1056)) + (PORT datac (672:672:672) (715:715:715)) + (PORT datad (819:819:819) (820:820:820)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19023,14 +19817,330 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) (DELAY (ABSOLUTE - (PORT dataa (1200:1200:1200) (1276:1276:1276)) - (PORT datab (1069:1069:1069) (1086:1086:1086)) - (PORT datac (691:691:691) (782:782:782)) - (PORT datad (931:931:931) (959:959:959)) + (PORT dataa (987:987:987) (1039:1039:1039)) + (PORT datab (434:434:434) (474:474:474)) + (PORT datac (947:947:947) (1015:1015:1015)) + (PORT datad (1175:1175:1175) (1235:1235:1235)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (285:285:285)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (208:208:208) (238:238:238)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (278:278:278)) + (PORT datac (193:193:193) (235:235:235)) + (PORT datad (374:374:374) (396:396:396)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (639:639:639) (661:661:661)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (DELAY + (ABSOLUTE + (PORT datab (1269:1269:1269) (1380:1380:1380)) + (PORT datac (901:901:901) (917:917:917)) + (PORT datad (1177:1177:1177) (1191:1191:1191)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1340:1340:1340)) + (PORT datab (1007:1007:1007) (1075:1075:1075)) + (PORT datac (1456:1456:1456) (1496:1496:1496)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (DELAY + (ABSOLUTE + (PORT dataa (2050:2050:2050) (2087:2087:2087)) + (PORT datab (943:943:943) (1022:1022:1022)) + (PORT datac (1211:1211:1211) (1239:1239:1239)) + (PORT datad (1083:1083:1083) (1126:1126:1126)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (949:949:949)) + (PORT datab (1060:1060:1060) (1085:1085:1085)) + (PORT datac (892:892:892) (934:934:934)) + (PORT datad (568:568:568) (571:571:571)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1490:1490:1490) (1592:1592:1592)) + (PORT datab (438:438:438) (472:472:472)) + (PORT datac (945:945:945) (997:997:997)) + (PORT datad (1178:1178:1178) (1233:1233:1233)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1493:1493:1493) (1597:1597:1597)) + (PORT datab (234:234:234) (278:278:278)) + (PORT datac (2021:2021:2021) (2050:2050:2050)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (609:609:609) (638:638:638)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (258:258:258)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (817:817:817) (862:862:862)) + (PORT datad (554:554:554) (572:572:572)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1462:1462:1462) (1525:1525:1525)) + (PORT datab (1404:1404:1404) (1424:1424:1424)) + (PORT datac (1574:1574:1574) (1618:1618:1618)) + (PORT datad (1065:1065:1065) (1079:1079:1079)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (759:759:759)) + (PORT datab (699:699:699) (730:730:730)) + (PORT datac (1599:1599:1599) (1604:1604:1604)) + (PORT datad (1436:1436:1436) (1479:1479:1479)) (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1343:1343:1343) (1425:1425:1425)) + (PORT datab (1086:1086:1086) (1110:1110:1110)) + (PORT datac (1574:1574:1574) (1614:1614:1614)) + (PORT datad (1794:1794:1794) (1911:1911:1911)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (843:843:843) (880:880:880)) + (PORT datac (1602:1602:1602) (1608:1608:1608)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~42) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (867:867:867)) + (PORT datab (1092:1092:1092) (1116:1116:1116)) + (PORT datac (2113:2113:2113) (2219:2219:2219)) + (PORT datad (1789:1789:1789) (1904:1904:1904)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1016:1016:1016) (1027:1027:1027)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~41) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (702:702:702)) + (PORT datab (2051:2051:2051) (2134:2134:2134)) + (PORT datac (1486:1486:1486) (1540:1540:1540)) + (PORT datad (1327:1327:1327) (1454:1454:1454)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1519:1519:1519) (1580:1580:1580)) + (PORT datab (1960:1960:1960) (1986:1986:1986)) + (PORT datac (1263:1263:1263) (1313:1313:1313)) + (PORT datad (869:869:869) (922:922:922)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1748:1748:1748) (1872:1872:1872)) + (PORT datab (1028:1028:1028) (1083:1083:1083)) + (PORT datac (199:199:199) (235:235:235)) + (PORT datad (1506:1506:1506) (1541:1541:1541)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -19039,28 +20149,509 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) (DELAY (ABSOLUTE - (PORT dataa (528:528:528) (555:555:555)) - (PORT datab (634:634:634) (673:673:673)) - (PORT datac (635:635:635) (664:664:664)) + (PORT dataa (1165:1165:1165) (1194:1194:1194)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1359:1359:1359) (1382:1382:1382)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~44) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (841:841:841)) + (PORT datab (1818:1818:1818) (1968:1968:1968)) + (PORT datac (1306:1306:1306) (1386:1386:1386)) + (PORT datad (1794:1794:1794) (1911:1911:1911)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (699:699:699) (733:733:733)) + (PORT datac (862:862:862) (901:901:901)) + (PORT datad (693:693:693) (717:717:717)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (551:551:551)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (641:641:641) (659:659:659)) (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (620:620:620)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (603:603:603) (622:622:622)) + (PORT datad (345:345:345) (359:359:359)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (917:917:917) (956:956:956)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (317:317:317) (337:337:337)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1666:1666:1666) (1754:1754:1754)) + (PORT datab (1416:1416:1416) (1493:1493:1493)) + (PORT datac (639:639:639) (659:659:659)) + (PORT datad (847:847:847) (875:875:875)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1506:1506:1506)) + (PORT datab (849:849:849) (859:859:859)) + (PORT datac (836:836:836) (864:864:864)) + (PORT datad (1389:1389:1389) (1423:1423:1423)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (869:869:869)) + (PORT datab (1772:1772:1772) (1798:1798:1798)) + (PORT datac (618:618:618) (638:638:638)) + (PORT datad (822:822:822) (837:837:837)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1198:1198:1198) (1248:1248:1248)) + (PORT datab (223:223:223) (268:268:268)) + (PORT datac (914:914:914) (947:947:947)) + (PORT datad (607:607:607) (631:631:631)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (334:334:334)) + (PORT datab (944:944:944) (991:991:991)) + (PORT datac (535:535:535) (545:545:545)) + (PORT datad (1139:1139:1139) (1125:1125:1125)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (673:673:673)) + (PORT datab (1125:1125:1125) (1173:1173:1173)) + (PORT datac (583:583:583) (615:615:615)) + (PORT datad (389:389:389) (443:443:443)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (340:340:340)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (559:559:559) (583:583:583)) + (PORT datad (901:901:901) (948:948:948)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (511:511:511)) + (PORT datab (419:419:419) (499:499:499)) + (PORT datac (878:878:878) (901:901:901)) + (PORT datad (657:657:657) (678:678:678)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (638:638:638) (659:659:659)) + (PORT datac (355:355:355) (378:378:378)) + (PORT datad (830:830:830) (837:837:837)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (419:419:419)) + (PORT datab (653:653:653) (711:711:711)) + (PORT datac (647:647:647) (707:707:707)) + (PORT datad (635:635:635) (659:659:659)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (443:443:443)) + (PORT datab (239:239:239) (284:284:284)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (742:742:742)) + (PORT datab (1178:1178:1178) (1274:1274:1274)) + (PORT datac (855:855:855) (865:865:865)) + (PORT datad (674:674:674) (693:693:693)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1358:1358:1358)) + (PORT datab (1962:1962:1962) (1990:1990:1990)) + (PORT datac (1486:1486:1486) (1545:1545:1545)) + (PORT datad (1495:1495:1495) (1557:1557:1557)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1144:1144:1144) (1179:1179:1179)) + (PORT datab (609:609:609) (638:638:638)) + (PORT datac (820:820:820) (842:842:842)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datad (798:798:798) (805:805:805)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1175:1175:1175)) + (PORT datac (567:567:567) (576:576:576)) + (PORT datad (1627:1627:1627) (1703:1703:1703)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (927:927:927)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1829:1829:1829) (1911:1911:1911)) + (PORT datad (562:562:562) (570:570:570)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (415:415:415)) + (PORT datab (2086:2086:2086) (2229:2229:2229)) + (PORT datac (1314:1314:1314) (1402:1402:1402)) + (PORT datad (902:902:902) (968:968:968)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (462:462:462)) + (PORT datab (612:612:612) (633:633:633)) + (PORT datac (1175:1175:1175) (1235:1235:1235)) + (PORT datad (822:822:822) (844:844:844)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (597:597:597)) + (PORT datab (615:615:615) (638:638:638)) + (PORT datad (567:567:567) (574:574:574)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (685:685:685)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (807:807:807) (808:808:808)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1698:1698:1698) (1789:1789:1789)) + (PORT datab (919:919:919) (952:952:952)) + (PORT datac (888:888:888) (909:909:909)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_latch_\|abusz\[12\]) (DELAY (ABSOLUTE - (PORT datac (1514:1514:1514) (1609:1609:1609)) - (PORT datad (634:634:634) (666:666:666)) + (PORT datab (403:403:403) (448:448:448)) + (PORT datac (885:885:885) (915:915:915)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[12\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (314:314:314) (333:333:333)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -19070,10 +20661,10 @@ (INSTANCE z80_\|address_latch_\|Q\[12\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1547:1547:1547)) - (PORT ena (2484:2484:2484) (2511:2511:2511)) + (PORT clrn (1581:1581:1581) (1561:1561:1561)) + (PORT ena (2058:2058:2058) (2109:2109:2109)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -19088,24 +20679,101 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) (DELAY (ABSOLUTE - (PORT dataa (454:454:454) (536:536:536)) - (PORT datab (470:470:470) (552:552:552)) - (PORT datac (989:989:989) (1029:1029:1029)) - (PORT datad (547:547:547) (558:558:558)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (625:625:625) (638:638:638)) + (PORT datab (903:903:903) (926:926:926)) + (PORT datac (240:240:240) (327:327:327)) + (PORT datad (577:577:577) (639:639:639)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1308:1308:1308) (1303:1303:1303)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1458:1458:1458) (1466:1466:1466)) + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (1270:1270:1270) (1318:1318:1318)) + (PORT ena (935:935:935) (924:924:924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (460:460:460)) + (PORT datab (412:412:412) (448:448:448)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (717:717:717)) + (PORT datac (216:216:216) (293:293:293)) + (PORT datad (775:775:775) (807:807:807)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (418:418:418)) + (PORT datab (838:838:838) (875:875:875)) + (PORT datac (679:679:679) (721:721:721)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (2041:2041:2041) (2053:2053:2053)) (PORT ena (790:790:790) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -19117,310 +20785,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~22) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (328:328:328)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datad (898:898:898) (963:963:963)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (456:456:456) (489:489:489)) - (PORT datac (304:304:304) (327:327:327)) - (PORT datad (217:217:217) (286:286:286)) + (PORT dataa (409:409:409) (437:437:437)) + (PORT datab (1165:1165:1165) (1216:1216:1216)) + (PORT datad (739:739:739) (751:751:751)) + (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (720:720:720)) - (PORT datab (400:400:400) (436:436:436)) - (PORT datac (1663:1663:1663) (1792:1792:1792)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1226:1226:1226) (1262:1262:1262)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1210:1210:1210) (1280:1280:1280)) - (PORT datab (1382:1382:1382) (1450:1450:1450)) - (PORT datad (1863:1863:1863) (1919:1919:1919)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1226:1226:1226) (1243:1243:1243)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1226:1226:1226) (1243:1243:1243)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (474:474:474)) - (PORT datab (434:434:434) (463:463:463)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1280:1280:1280) (1315:1315:1315)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1280:1280:1280) (1315:1315:1315)) - (PORT ena (1011:1011:1011) (1021:1021:1021)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (989:989:989)) - (PORT datab (239:239:239) (321:321:321)) - (PORT datad (233:233:233) (270:270:270)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1276:1276:1276) (1306:1306:1306)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1275:1275:1275) (1303:1303:1303)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (700:700:700)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (631:631:631) (646:646:646)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1219:1219:1219) (1247:1247:1247)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1219:1219:1219) (1247:1247:1247)) - (PORT ena (979:979:979) (971:971:971)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (483:483:483)) - (PORT datab (424:424:424) (466:466:466)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (936:936:936) (959:959:959)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1355:1355:1355)) - (PORT datab (842:842:842) (875:875:875)) - (PORT datad (388:388:388) (408:408:408)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19431,9 +20803,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) + (PORT clk (1535:1535:1535) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1397:1397:1397) (1426:1426:1426)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -19447,9 +20819,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (914:914:914) (940:940:940)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (2041:2041:2041) (2050:2050:2050)) + (PORT ena (1236:1236:1236) (1273:1273:1273)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -19460,14 +20832,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~81) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) (DELAY (ABSOLUTE - (PORT dataa (488:488:488) (524:524:524)) - (PORT datab (456:456:456) (530:530:530)) - (PORT datad (666:666:666) (691:691:691)) + (PORT dataa (692:692:692) (780:780:780)) + (PORT datab (884:884:884) (909:909:909)) + (PORT datad (866:866:866) (902:902:902)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1376:1376:1376) (1427:1427:1427)) + (PORT ena (1214:1214:1214) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1376:1376:1376) (1429:1429:1429)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (945:945:945)) + (PORT datab (244:244:244) (290:290:290)) + (PORT datad (216:216:216) (284:284:284)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19475,147 +20894,211 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~82) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (823:823:823) (868:868:868)) - (PORT datab (609:609:609) (659:659:659)) - (PORT datac (595:595:595) (612:612:612)) - (PORT datad (597:597:597) (611:611:611)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datad (1394:1394:1394) (1418:1418:1418)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~83) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT dataa (617:617:617) (673:673:673)) - (PORT datab (571:571:571) (589:589:589)) - (PORT datac (881:881:881) (883:883:883)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1721:1721:1721) (1742:1742:1742)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~84) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) (DELAY (ABSOLUTE - (PORT dataa (2010:2010:2010) (2149:2149:2149)) - (PORT datab (585:585:585) (602:602:602)) - (PORT datac (1114:1114:1114) (1125:1125:1125)) - (PORT datad (809:809:809) (855:855:855)) - (IOPATH dataa combout (325:325:325) (320:320:320)) + (PORT dataa (392:392:392) (467:467:467)) + (PORT datab (1593:1593:1593) (1645:1645:1645)) + (PORT datad (1180:1180:1180) (1215:1215:1215)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (809:809:809) (810:810:810)) + (PORT datad (610:610:610) (622:622:622)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT dataa (1698:1698:1698) (1799:1799:1799)) - (PORT datac (1608:1608:1608) (1653:1653:1653)) - (PORT datad (1487:1487:1487) (1510:1510:1510)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1872:1872:1872) (1943:1943:1943)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1872:1872:1872) (1942:1942:1942)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (991:991:991)) + (PORT datab (912:912:912) (981:981:981)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1938:1938:1938) (1952:1952:1952)) + (PORT ena (990:990:990) (994:994:994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1936:1936:1936) (1952:1952:1952)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (519:519:519)) + (PORT datab (492:492:492) (537:537:537)) + (PORT datad (217:217:217) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1867:1867:1867) (1935:1935:1935)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (988:988:988)) + (PORT datab (1221:1221:1221) (1295:1295:1295)) + (PORT datad (887:887:887) (943:943:943)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) (DELAY (ABSOLUTE - (PORT dataa (1087:1087:1087) (1125:1125:1125)) - (PORT datab (1070:1070:1070) (1088:1088:1088)) - (PORT datac (1727:1727:1727) (1848:1848:1848)) - (PORT datad (1340:1340:1340) (1359:1359:1359)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT datab (1778:1778:1778) (1897:1897:1897)) - (PORT datac (880:880:880) (892:892:892)) - (PORT datad (1337:1337:1337) (1358:1358:1358)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1081:1081:1081)) - (PORT datac (1198:1198:1198) (1225:1225:1225)) - (PORT datad (1354:1354:1354) (1396:1396:1396)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT datab (1936:1936:1936) (2029:2029:2029)) - (PORT datac (750:750:750) (755:755:755)) - (PORT datad (1021:1021:1021) (1039:1039:1039)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1214:1214:1214)) - (PORT datac (1662:1662:1662) (1757:1757:1757)) - (PORT datad (1487:1487:1487) (1515:1515:1515)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1054:1054:1054) (1096:1096:1096)) - (PORT datab (611:611:611) (627:627:627)) - (PORT datac (1033:1033:1033) (1063:1063:1063)) - (PORT datad (1423:1423:1423) (1509:1509:1509)) + (PORT dataa (644:644:644) (697:697:697)) + (PORT datab (331:331:331) (360:360:360)) + (PORT datac (577:577:577) (594:594:594)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -19625,15 +21108,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) (DELAY (ABSOLUTE - (PORT dataa (671:671:671) (698:698:698)) - (PORT datab (356:356:356) (387:387:387)) - (PORT datac (868:868:868) (910:910:910)) - (PORT datad (564:564:564) (588:588:588)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (883:883:883) (947:947:947)) + (PORT datab (844:844:844) (916:916:916)) + (PORT datac (840:840:840) (851:851:851)) + (PORT datad (1298:1298:1298) (1335:1335:1335)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1356:1356:1356)) + (PORT datab (968:968:968) (1024:1024:1024)) + (PORT datac (891:891:891) (908:908:908)) + (PORT datad (1445:1445:1445) (1454:1454:1454)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1289:1289:1289) (1337:1337:1337)) + (PORT datab (1225:1225:1225) (1251:1251:1251)) + (PORT datac (904:904:904) (947:947:947)) + (PORT datad (928:928:928) (986:986:986)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (251:251:251)) + (PORT datab (249:249:249) (305:305:305)) + (PORT datac (1067:1067:1067) (1064:1064:1064)) + (PORT datad (949:949:949) (996:996:996)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1286:1286:1286) (1354:1354:1354)) + (PORT datab (933:933:933) (990:990:990)) + (PORT datac (372:372:372) (402:402:402)) + (PORT datad (1200:1200:1200) (1314:1314:1314)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1230:1230:1230)) + (PORT datab (1831:1831:1831) (1921:1921:1921)) + (PORT datac (881:881:881) (935:935:935)) + (PORT datad (1554:1554:1554) (1661:1661:1661)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19641,13 +21204,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) (DELAY (ABSOLUTE - (PORT dataa (1661:1661:1661) (1780:1780:1780)) - (PORT datab (576:576:576) (598:598:598)) - (PORT datac (1732:1732:1732) (1776:1776:1776)) - (PORT datad (2426:2426:2426) (2480:2480:2480)) + (PORT dataa (923:923:923) (987:987:987)) + (PORT datab (637:637:637) (672:672:672)) + (PORT datac (1395:1395:1395) (1470:1470:1470)) + (PORT datad (580:580:580) (617:617:617)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -19657,31 +21220,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (740:740:740) (757:757:757)) - (PORT datac (562:562:562) (592:592:592)) - (PORT datad (1035:1035:1035) (1038:1038:1038)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1523:1523:1523)) - (PORT datab (639:639:639) (720:720:720)) - (PORT datac (542:542:542) (563:563:563)) - (PORT datad (1266:1266:1266) (1295:1295:1295)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (204:204:204) (249:249:249)) + (PORT datac (935:935:935) (965:965:965)) + (PORT datad (241:241:241) (282:282:282)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19689,15 +21234,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) (DELAY (ABSOLUTE - (PORT dataa (838:838:838) (885:885:885)) - (PORT datab (384:384:384) (412:412:412)) - (PORT datac (335:335:335) (361:361:361)) - (PORT datad (1833:1833:1833) (1945:1945:1945)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1179:1179:1179) (1212:1212:1212)) + (PORT datab (290:290:290) (355:355:355)) + (PORT datac (254:254:254) (314:314:314)) + (PORT datad (246:246:246) (292:292:292)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19705,88 +21250,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) (DELAY (ABSOLUTE - (PORT dataa (1266:1266:1266) (1361:1361:1361)) - (PORT datab (1624:1624:1624) (1653:1653:1653)) - (PORT datac (566:566:566) (574:574:574)) - (PORT datad (2330:2330:2330) (2371:2371:2371)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (654:654:654)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (367:367:367) (380:380:380)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (359:359:359) (395:395:395)) + (PORT datac (927:927:927) (982:982:982)) + (PORT datad (676:676:676) (714:714:714)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (725:725:725) (773:773:773)) - (PORT datab (703:703:703) (750:750:750)) - (PORT datac (581:581:581) (620:620:620)) - (PORT datad (590:590:590) (603:603:603)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (813:813:813)) - (PORT datab (818:818:818) (831:831:831)) - (PORT datac (724:724:724) (732:732:732)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (904:904:904) (999:999:999)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (INSTANCE z80_\|alu_\|op1_high\[0\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) + (PORT clk (1530:1530:1530) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1021:1021:1021) (1037:1037:1037)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -19797,11 +21280,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) (DELAY (ABSOLUTE - (PORT datac (1742:1742:1742) (1862:1862:1862)) - (PORT datad (1338:1338:1338) (1358:1358:1358)) + (PORT dataa (636:636:636) (695:695:695)) + (PORT datab (1175:1175:1175) (1218:1218:1218)) + (PORT datac (649:649:649) (707:707:707)) + (PORT datad (660:660:660) (719:719:719)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19809,119 +21296,208 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (INSTANCE z80_\|alu_\|db_high\[0\]\~25) (DELAY (ABSOLUTE - (PORT dataa (871:871:871) (888:888:888)) - (PORT datab (1062:1062:1062) (1095:1095:1095)) - (PORT datac (1018:1018:1018) (1057:1057:1057)) - (PORT datad (1424:1424:1424) (1509:1509:1509)) + (PORT dataa (598:598:598) (629:629:629)) + (PORT datab (329:329:329) (356:356:356)) + (PORT datac (1163:1163:1163) (1203:1203:1203)) + (PORT datad (530:530:530) (548:548:548)) (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (679:679:679)) + (PORT datab (998:998:998) (1032:1032:1032)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (220:220:220) (263:263:263)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (555:555:555) (585:585:585)) + (PORT dataa (594:594:594) (621:621:621)) + (PORT datab (963:963:963) (1009:1009:1009)) + (PORT datac (864:864:864) (907:907:907)) + (PORT datad (337:337:337) (357:357:357)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (674:674:674) (713:713:713)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (963:963:963)) + (PORT datab (719:719:719) (762:762:762)) + (PORT datac (929:929:929) (980:980:980)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) (PORT ena (790:790:790) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) (DELAY (ABSOLUTE - (PORT datac (776:776:776) (789:789:789)) - (PORT datad (228:228:228) (267:267:267)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (647:647:647) (678:678:678)) + (PORT datab (640:640:640) (697:697:697)) + (PORT datac (608:608:608) (646:646:646)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (648:648:648)) + (PORT datab (935:935:935) (984:984:984)) + (PORT datac (1093:1093:1093) (1149:1149:1149)) + (PORT datad (575:575:575) (595:595:595)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (869:869:869) (913:913:913)) - (PORT datab (219:219:219) (259:259:259)) - (PORT datad (605:605:605) (619:619:619)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (263:263:263) (339:339:339)) + (PORT datac (171:171:171) (204:204:204)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) + (INSTANCE z80_\|alu_\|op2_low\[0\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT clk (1529:1529:1529) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (845:845:845) (899:899:899)) - (PORT datab (730:730:730) (810:810:810)) - (PORT datac (674:674:674) (748:748:748)) - (PORT datad (1031:1031:1031) (1033:1033:1033)) + (PORT dataa (431:431:431) (524:524:524)) + (PORT datac (650:650:650) (711:711:711)) + (PORT datad (658:658:658) (684:684:684)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (600:600:600)) + (PORT datab (826:826:826) (830:830:830)) + (PORT datac (805:805:805) (806:806:806)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (712:712:712)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (203:203:203) (240:240:240)) + (PORT datad (818:818:818) (831:831:831)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (676:676:676)) + (PORT datab (632:632:632) (684:684:684)) + (PORT datad (630:630:630) (672:672:672)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1124:1124:1124) (1174:1174:1174)) - (PORT datab (1092:1092:1092) (1102:1102:1102)) - (PORT datac (686:686:686) (764:764:764)) - (PORT datad (817:817:817) (856:856:856)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (613:613:613)) - (PORT datab (604:604:604) (630:630:630)) - (PORT datad (574:574:574) (583:583:583)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -19931,28 +21507,12 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (1400:1400:1400) (1433:1433:1433)) - (PORT datab (717:717:717) (793:793:793)) - (PORT datac (1095:1095:1095) (1134:1134:1134)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1115:1115:1115) (1150:1150:1150)) - (PORT datab (1184:1184:1184) (1256:1256:1256)) - (PORT datac (1025:1025:1025) (1066:1066:1066)) - (PORT datad (1151:1151:1151) (1166:1166:1166)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (683:683:683) (704:704:704)) + (PORT datab (860:860:860) (876:876:876)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (515:515:515) (526:526:526)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19960,28 +21520,128 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~16) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) (DELAY (ABSOLUTE - (PORT dataa (765:765:765) (794:794:794)) - (PORT datab (250:250:250) (309:309:309)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (845:845:845) (863:863:863)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT dataa (206:206:206) (252:252:252)) + (PORT datab (213:213:213) (257:257:257)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (690:690:690)) + (PORT datab (662:662:662) (696:696:696)) + (PORT datad (604:604:604) (655:655:655)) + (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (405:405:405)) + (PORT datab (638:638:638) (659:659:659)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (830:830:830) (837:837:837)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (410:410:410)) + (PORT datab (394:394:394) (423:423:423)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (368:368:368) (390:390:390)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT datac (1740:1740:1740) (1766:1766:1766)) + (PORT datad (822:822:822) (836:836:836)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (410:410:410)) + (PORT datab (234:234:234) (279:279:279)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (236:236:236) (281:281:281)) + (PORT datac (354:354:354) (379:379:379)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) + (PORT datad (1068:1068:1068) (1102:1102:1102)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -19992,12 +21652,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (934:934:934) (951:951:951)) - (PORT ena (790:790:790) (782:782:782)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1435:1435:1435) (1482:1482:1482)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20008,209 +21668,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~10) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (328:328:328)) - (PORT datab (938:938:938) (1006:1006:1006)) - (PORT datad (574:574:574) (588:588:588)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (330:330:330)) - (PORT datab (454:454:454) (489:489:489)) - (PORT datac (332:332:332) (350:350:350)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT datab (1937:1937:1937) (2030:2030:2030)) - (PORT datac (750:750:750) (755:755:755)) - (PORT datad (1021:1021:1021) (1040:1040:1040)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1243:1243:1243) (1278:1278:1278)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (910:910:910)) - (PORT datab (1657:1657:1657) (1747:1747:1747)) - (PORT datad (1246:1246:1246) (1263:1263:1263)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1245:1245:1245) (1281:1281:1281)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (694:694:694)) - (PORT datab (878:878:878) (942:942:942)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1597:1597:1597) (1712:1712:1712)) - (PORT datab (1294:1294:1294) (1374:1374:1374)) - (PORT datac (1166:1166:1166) (1167:1167:1167)) - (PORT datad (778:778:778) (803:803:803)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (949:949:949) (986:986:986)) - (PORT ena (1450:1450:1450) (1505:1505:1505)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1591:1591:1591) (1714:1714:1714)) - (PORT datab (1291:1291:1291) (1369:1369:1369)) - (PORT datac (1168:1168:1168) (1169:1169:1169)) - (PORT datad (777:777:777) (805:805:805)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (946:946:946) (983:983:983)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (351:351:351)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (582:582:582) (611:611:611)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (1026:1026:1026) (1085:1085:1085)) - (PORT datac (1202:1202:1202) (1229:1229:1229)) - (PORT datad (1355:1355:1355) (1394:1394:1394)) + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (1596:1596:1596) (1648:1648:1648)) + (PORT datad (1179:1179:1179) (1221:1221:1221)) (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1543:1543:1543)) - (PORT asdata (906:906:906) (928:928:928)) - (PORT ena (816:816:816) (813:813:813)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1647:1647:1647) (1718:1718:1718)) + (PORT ena (1214:1214:1214) (1210:1210:1210)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20219,26 +21697,13 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT datab (367:367:367) (405:405:405)) - (PORT datad (216:216:216) (249:249:249)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (687:687:687) (706:706:706)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1644:1644:1644) (1714:1714:1714)) (PORT ena (790:790:790) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -20250,13 +21715,91 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) (DELAY (ABSOLUTE - (PORT dataa (588:588:588) (622:622:622)) - (PORT datab (260:260:260) (308:308:308)) - (PORT datad (1121:1121:1121) (1150:1150:1150)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (902:902:902) (942:942:942)) + (PORT datab (245:245:245) (290:290:290)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1405:1405:1405) (1471:1471:1471)) + (PORT ena (1236:1236:1236) (1273:1273:1273)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (798:798:798)) + (PORT datab (884:884:884) (909:909:909)) + (PORT datad (866:866:866) (902:902:902)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1404:1404:1404) (1472:1472:1472)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1418:1418:1418)) + (PORT datab (1167:1167:1167) (1217:1217:1217)) + (PORT datad (238:238:238) (279:279:279)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -20265,90 +21808,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) (DELAY (ABSOLUTE - (PORT dataa (1266:1266:1266) (1361:1361:1361)) - (PORT datab (1626:1626:1626) (1652:1652:1652)) - (PORT datac (584:584:584) (621:621:621)) - (PORT datad (2332:2332:2332) (2373:2373:2373)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (926:926:926) (946:946:946)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT datab (1781:1781:1781) (1900:1900:1900)) - (PORT datac (881:881:881) (893:893:893)) - (PORT datad (1338:1338:1338) (1358:1358:1358)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (928:928:928) (949:949:949)) - (PORT ena (1472:1472:1472) (1481:1481:1481)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (283:283:283) (349:349:349)) - (PORT datab (701:701:701) (739:739:739)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (858:858:858)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (348:348:348) (375:375:375)) - (PORT datad (575:575:575) (582:582:582)) + (PORT dataa (820:820:820) (843:843:843)) + (PORT datab (1070:1070:1070) (1130:1130:1130)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (172:172:172) (198:198:198)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -20358,12 +21824,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1242:1242:1242) (1269:1269:1269)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1442:1442:1442) (1490:1490:1490)) + (PORT ena (990:990:990) (994:994:994)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20374,12 +21840,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1238:1238:1238) (1265:1265:1265)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1439:1439:1439) (1490:1490:1490)) + (PORT ena (973:973:973) (964:964:964)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20390,13 +21856,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) (DELAY (ABSOLUTE - (PORT dataa (384:384:384) (462:462:462)) - (PORT datab (696:696:696) (732:732:732)) - (PORT datad (659:659:659) (676:676:676)) - (IOPATH dataa combout (339:339:339) (367:367:367)) + (PORT dataa (466:466:466) (523:523:523)) + (PORT datab (492:492:492) (536:536:536)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -20405,28 +21871,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1249:1249:1249) (1287:1287:1287)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1246:1246:1246) (1284:1284:1284)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1377:1377:1377) (1423:1423:1423)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20437,57 +21887,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~20) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (PORT datab (705:705:705) (754:754:754)) - (PORT datad (682:682:682) (728:728:728)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (561:561:561) (568:568:568)) - (PORT datad (837:837:837) (833:833:833)) + (PORT dataa (938:938:938) (994:994:994)) + (PORT datab (1222:1222:1222) (1294:1294:1294)) + (PORT datad (881:881:881) (941:941:941)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (1530:1530:1530) (1642:1642:1642)) - (PORT datab (365:365:365) (386:386:386)) - (PORT datac (807:807:807) (824:824:824)) - (PORT datad (601:601:601) (615:615:615)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (897:897:897) (916:916:916)) - (PORT ena (816:816:816) (813:813:813)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1195:1195:1195) (1249:1249:1249)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1195:1195:1195) (1248:1248:1248)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20498,12 +21934,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) (DELAY (ABSOLUTE - (PORT dataa (858:858:858) (899:899:899)) - (PORT datab (246:246:246) (294:294:294)) - (PORT datad (1247:1247:1247) (1246:1246:1246)) + (PORT dataa (924:924:924) (985:985:985)) + (PORT datab (910:910:910) (988:988:988)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (410:410:410)) + (PORT datab (634:634:634) (661:661:661)) + (PORT datac (637:637:637) (673:673:673)) + (PORT datad (789:789:789) (853:853:853)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (1138:1138:1138) (1178:1178:1178)) + (PORT ena (935:935:935) (924:924:924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (407:407:407) (446:446:446)) + (PORT datad (387:387:387) (422:422:422)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -20513,12 +21996,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) + (PORT clk (1525:1525:1525) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1021:1021:1021) (1037:1037:1037)) + (PORT ena (1308:1308:1308) (1303:1303:1303)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20529,14 +22012,2644 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (860:860:860)) + (PORT datac (214:214:214) (289:289:289)) + (PORT datad (646:646:646) (672:672:672)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (634:634:634)) + (PORT datab (906:906:906) (933:933:933)) + (PORT datac (239:239:239) (322:322:322)) + (PORT datad (576:576:576) (636:636:636)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT datac (258:258:258) (345:345:345)) + (PORT datad (187:187:187) (220:220:220)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1405:1405:1405) (1477:1477:1477)) + (PORT ena (1261:1261:1261) (1299:1299:1299)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1151:1151:1151)) + (PORT datab (881:881:881) (915:915:915)) + (PORT datad (665:665:665) (744:744:744)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (2052:2052:2052) (2111:2111:2111)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1654:1654:1654)) + (PORT datab (1164:1164:1164) (1211:1211:1211)) + (PORT datad (231:231:231) (271:271:271)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1101:1101:1101) (1166:1166:1166)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1418:1418:1418) (1481:1481:1481)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (459:459:459)) + (PORT datab (1594:1594:1594) (1651:1651:1651)) + (PORT datad (1178:1178:1178) (1221:1221:1221)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1799:1799:1799) (1855:1855:1855)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1406:1406:1406) (1476:1476:1476)) + (PORT ena (1131:1131:1131) (1098:1098:1098)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (478:478:478)) + (PORT datab (881:881:881) (916:916:916)) + (PORT datad (364:364:364) (384:384:384)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (338:338:338) (368:368:368)) + (PORT datac (804:804:804) (808:808:808)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1448:1448:1448) (1498:1498:1498)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1448:1448:1448) (1501:1501:1501)) + (PORT ena (990:990:990) (994:994:994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (518:518:518)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (458:458:458) (504:504:504)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1721:1721:1721) (1779:1779:1779)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1723:1723:1723) (1782:1782:1782)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (989:989:989)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datad (883:883:883) (941:941:941)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1771:1771:1771) (1829:1829:1829)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (989:989:989)) + (PORT datab (1220:1220:1220) (1296:1296:1296)) + (PORT datad (884:884:884) (944:944:944)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (699:699:699)) + (PORT datab (825:825:825) (869:869:869)) + (PORT datac (606:606:606) (632:632:632)) + (PORT datad (842:842:842) (848:848:848)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (946:946:946)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datac (817:817:817) (863:863:863)) + (PORT datad (1298:1298:1298) (1332:1332:1332)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (1159:1159:1159) (1205:1205:1205)) + (PORT ena (935:935:935) (924:924:924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (459:459:459)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datad (386:386:386) (413:413:413)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1308:1308:1308) (1303:1303:1303)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (716:716:716)) + (PORT datab (379:379:379) (421:421:421)) + (PORT datac (215:215:215) (292:292:292)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (582:582:582)) + (PORT datab (844:844:844) (883:883:883)) + (PORT datac (682:682:682) (722:722:722)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT datab (383:383:383) (425:425:425)) + (PORT datac (886:886:886) (918:918:918)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (335:335:335) (352:352:352)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1561:1561:1561)) + (PORT ena (2058:2058:2058) (2109:2109:2109)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (DELAY + (ABSOLUTE + (PORT datac (258:258:258) (345:345:345)) + (PORT datad (869:869:869) (891:891:891)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (DELAY + (ABSOLUTE + (PORT datac (356:356:356) (377:377:377)) + (PORT datad (867:867:867) (889:889:889)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1561:1561:1561)) + (PORT ena (2058:2058:2058) (2109:2109:2109)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (385:385:385)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (245:245:245) (326:326:326)) + (PORT datad (866:866:866) (891:891:891)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1308:1308:1308) (1303:1303:1303)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (2284:2284:2284) (2422:2422:2422)) + (PORT ena (990:990:990) (994:994:994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (2284:2284:2284) (2422:2422:2422)) + (PORT ena (973:973:973) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (524:524:524)) + (PORT datab (491:491:491) (541:541:541)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1879:1879:1879) (1975:1975:1975)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (835:835:835)) + (PORT datab (1168:1168:1168) (1216:1216:1216)) + (PORT datad (239:239:239) (281:281:281)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1192:1192:1192) (1258:1258:1258)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (2131:2131:2131) (2211:2211:2211)) + (PORT ena (1131:1131:1131) (1098:1098:1098)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (460:460:460)) + (PORT datab (883:883:883) (917:917:917)) + (PORT datad (364:364:364) (384:384:384)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1453:1453:1453) (1497:1497:1497)) + (PORT ena (1283:1283:1283) (1283:1283:1283)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1453:1453:1453) (1497:1497:1497)) + (PORT ena (1193:1193:1193) (1176:1176:1176)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1353:1353:1353)) + (PORT datab (1218:1218:1218) (1255:1255:1255)) + (PORT datad (214:214:214) (282:282:282)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1461:1461:1461) (1468:1468:1468)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (2133:2133:2133) (2211:2211:2211)) + (PORT ena (1261:1261:1261) (1299:1299:1299)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1146:1146:1146)) + (PORT datab (681:681:681) (756:756:756)) + (PORT datad (848:848:848) (874:874:874)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (624:624:624)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (595:595:595) (612:612:612)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1205:1205:1205) (1270:1270:1270)) + (PORT ena (1388:1388:1388) (1427:1427:1427)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1205:1205:1205) (1270:1270:1270)) + (PORT ena (1400:1400:1400) (1413:1413:1413)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (985:985:985)) + (PORT datab (912:912:912) (982:982:982)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (2162:2162:2162) (2212:2212:2212)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (997:997:997)) + (PORT datab (1220:1220:1220) (1296:1296:1296)) + (PORT datad (879:879:879) (940:940:940)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (650:650:650)) + (PORT datab (632:632:632) (657:657:657)) + (PORT datac (489:489:489) (507:507:507)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (944:944:944)) + (PORT datab (672:672:672) (688:688:688)) + (PORT datac (786:786:786) (839:839:839)) + (PORT datad (1301:1301:1301) (1333:1333:1333)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT asdata (1132:1132:1132) (1183:1183:1183)) + (PORT ena (935:935:935) (924:924:924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (466:466:466)) + (PORT datab (218:218:218) (258:258:258)) + (PORT datad (382:382:382) (412:412:412)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (332:332:332)) + (PORT datab (670:670:670) (688:688:688)) + (PORT datad (645:645:645) (672:672:672)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (401:401:401)) + (PORT datab (712:712:712) (754:754:754)) + (PORT datac (808:808:808) (840:840:840)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (955:955:955)) + (PORT datac (361:361:361) (395:395:395)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (320:320:320) (331:331:331)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1561:1561:1561)) + (PORT ena (2058:2058:2058) (2109:2109:2109)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1169:1169:1169)) + (PORT datab (404:404:404) (477:477:477)) + (PORT datac (1110:1110:1110) (1117:1117:1117)) + (PORT datad (632:632:632) (663:663:663)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (214:214:214) (258:258:258)) + (PORT datac (232:232:232) (316:316:316)) + (PORT datad (339:339:339) (360:360:360)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (417:417:417)) + (PORT datab (712:712:712) (760:760:760)) + (PORT datac (814:814:814) (847:847:847)) + (PORT datad (550:550:550) (569:569:569)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (950:950:950)) + (PORT datab (664:664:664) (704:704:704)) + (PORT datac (792:792:792) (834:834:834)) + (PORT datad (1297:1297:1297) (1337:1337:1337)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1347:1347:1347)) + (PORT datab (973:973:973) (1026:1026:1026)) + (PORT datac (1877:1877:1877) (1946:1946:1946)) + (PORT datad (831:831:831) (844:844:844)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (256:256:256) (314:314:314)) + (PORT datac (1193:1193:1193) (1204:1204:1204)) + (PORT datad (945:945:945) (989:989:989)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (970:970:970)) + (PORT datab (1223:1223:1223) (1296:1296:1296)) + (PORT datac (905:905:905) (924:924:924)) + (PORT datad (1385:1385:1385) (1451:1451:1451)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (902:902:902)) + (PORT datab (661:661:661) (697:697:697)) + (PORT datac (670:670:670) (697:697:697)) + (PORT datad (675:675:675) (694:694:694)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1512:1512:1512) (1612:1612:1612)) + (PORT datab (1393:1393:1393) (1508:1508:1508)) + (PORT datac (1411:1411:1411) (1459:1459:1459)) + (PORT datad (835:835:835) (870:870:870)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (635:635:635)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (1083:1083:1083) (1127:1127:1127)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1199:1199:1199)) + (PORT datab (1007:1007:1007) (1063:1063:1063)) + (PORT datac (212:212:212) (252:252:252)) + (PORT datad (1995:1995:1995) (2085:2085:2085)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (260:260:260)) + (PORT datab (634:634:634) (650:650:650)) + (PORT datac (599:599:599) (616:616:616)) + (PORT datad (610:610:610) (626:626:626)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (701:701:701) (761:761:761)) + (PORT datac (1331:1331:1331) (1352:1352:1352)) + (PORT datad (1148:1148:1148) (1179:1179:1179)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1693:1693:1693) (1732:1732:1732)) + (PORT datab (1474:1474:1474) (1569:1569:1569)) + (PORT datac (2562:2562:2562) (2664:2664:2664)) + (PORT datad (1898:1898:1898) (2017:2017:2017)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1942:1942:1942) (2062:2062:2062)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (918:918:918) (965:965:965)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (664:664:664)) + (PORT datab (640:640:640) (658:658:658)) + (PORT datad (880:880:880) (936:936:936)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1199:1199:1199) (1286:1286:1286)) + (PORT datab (255:255:255) (340:340:340)) + (PORT datac (1353:1353:1353) (1415:1415:1415)) + (PORT datad (1199:1199:1199) (1262:1262:1262)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datad (1171:1171:1171) (1244:1244:1244)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (259:259:259)) + (PORT datac (882:882:882) (919:919:919)) + (PORT datad (1382:1382:1382) (1453:1453:1453)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (442:442:442)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (896:896:896) (932:932:932)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (511:511:511)) + (PORT datab (1166:1166:1166) (1210:1210:1210)) + (PORT datac (593:593:593) (646:646:646)) + (PORT datad (662:662:662) (719:719:719)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1208:1208:1208)) + (PORT datab (281:281:281) (344:344:344)) + (PORT datac (245:245:245) (304:304:304)) + (PORT datad (256:256:256) (301:301:301)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (378:378:378)) + (PORT datab (802:802:802) (831:831:831)) + (PORT datac (498:498:498) (504:504:504)) + (PORT datad (1104:1104:1104) (1147:1147:1147)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (639:639:639)) + (PORT datab (999:999:999) (1033:1033:1033)) + (PORT datac (589:589:589) (604:604:604)) + (PORT datad (221:221:221) (264:264:264)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (404:404:404)) + (PORT datab (893:893:893) (942:942:942)) + (PORT datac (1167:1167:1167) (1166:1166:1166)) + (PORT datad (680:680:680) (715:715:715)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (756:756:756)) + (PORT datab (1177:1177:1177) (1222:1222:1222)) + (PORT datac (613:613:613) (678:678:678)) + (PORT datad (666:666:666) (725:725:725)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (DELAY + (ABSOLUTE + (PORT datab (288:288:288) (350:350:350)) + (PORT datad (251:251:251) (296:296:296)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (347:347:347)) + (PORT datab (620:620:620) (638:638:638)) + (PORT datac (1141:1141:1141) (1167:1167:1167)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1287:1287:1287)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (996:996:996)) + (PORT datac (1660:1660:1660) (1742:1742:1742)) + (PORT datad (1418:1418:1418) (1445:1445:1445)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1168:1168:1168)) + (PORT datab (1129:1129:1129) (1182:1182:1182)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (241:241:241) (282:282:282)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (538:538:538)) + (PORT datab (879:879:879) (956:956:956)) + (PORT datac (959:959:959) (990:990:990)) + (PORT datad (594:594:594) (608:608:608)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1243:1243:1243)) + (PORT datab (609:609:609) (645:645:645)) + (PORT datac (193:193:193) (235:235:235)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (695:695:695)) + (PORT datab (912:912:912) (959:959:959)) + (PORT datac (854:854:854) (883:883:883)) + (PORT datad (1144:1144:1144) (1179:1179:1179)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (678:678:678)) + (PORT datab (961:961:961) (1023:1023:1023)) + (PORT datac (1152:1152:1152) (1178:1178:1178)) + (PORT datad (225:225:225) (270:270:270)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (279:279:279)) + (PORT datab (1448:1448:1448) (1517:1517:1517)) + (PORT datac (1115:1115:1115) (1163:1163:1163)) + (PORT datad (178:178:178) (206:206:206)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1261:1261:1261)) + (PORT datab (930:930:930) (959:959:959)) + (PORT datac (533:533:533) (553:553:553)) + (PORT datad (844:844:844) (856:856:856)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1548:1548:1548)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (235:235:235) (277:277:277)) + (PORT datad (1401:1401:1401) (1453:1453:1453)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (663:663:663)) + (PORT datab (615:615:615) (664:664:664)) + (PORT datac (664:664:664) (693:693:693)) + (PORT datad (680:680:680) (701:701:701)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datab (614:614:614) (644:644:644)) + (PORT datad (801:801:801) (877:877:877)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (665:665:665)) + (PORT datab (2306:2306:2306) (2385:2385:2385)) + (PORT datac (2054:2054:2054) (2198:2198:2198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (426:426:426)) + (PORT datab (1624:1624:1624) (1701:1701:1701)) + (PORT datac (829:829:829) (848:848:848)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (877:877:877)) + (PORT datab (360:360:360) (396:396:396)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (1002:1002:1002)) + (PORT datab (692:692:692) (710:710:710)) + (PORT datac (563:563:563) (586:586:586)) + (PORT datad (616:616:616) (630:630:630)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (957:957:957) (981:981:981)) + (PORT datac (645:645:645) (694:694:694)) + (PORT datad (656:656:656) (712:712:712)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (378:378:378)) + (PORT datab (209:209:209) (251:251:251)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (652:652:652) (692:692:692)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (904:904:904)) + (PORT datab (994:994:994) (1026:1026:1026)) + (PORT datac (1433:1433:1433) (1520:1520:1520)) + (PORT datad (1142:1142:1142) (1160:1160:1160)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (697:697:697)) + (PORT datab (936:936:936) (950:950:950)) + (PORT datac (1455:1455:1455) (1497:1497:1497)) + (PORT datad (1163:1163:1163) (1183:1183:1183)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (638:638:638)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (881:881:881) (909:909:909)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT datab (1639:1639:1639) (1704:1704:1704)) + (PORT datac (1440:1440:1440) (1481:1481:1481)) + (PORT datad (1160:1160:1160) (1199:1199:1199)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (500:500:500)) + (PORT datab (1223:1223:1223) (1282:1282:1282)) + (PORT datac (1145:1145:1145) (1179:1179:1179)) + (PORT datad (899:899:899) (938:938:938)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (917:917:917)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (870:870:870) (900:900:900)) + (PORT datad (616:616:616) (665:665:665)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (647:647:647)) + (PORT datab (247:247:247) (295:295:295)) + (PORT datac (1154:1154:1154) (1184:1184:1184)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (512:512:512)) + (PORT datab (1141:1141:1141) (1188:1188:1188)) + (PORT datad (1463:1463:1463) (1479:1479:1479)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (486:486:486)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1618:1618:1618) (1617:1617:1617)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) + (DELAY + (ABSOLUTE + (PORT datab (353:353:353) (390:390:390)) + (PORT datac (784:784:784) (794:794:794)) + (PORT datad (320:320:320) (341:341:341)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (970:970:970) (1022:1022:1022)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (970:970:970) (1022:1022:1022)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (336:336:336)) + (PORT datab (975:975:975) (1029:1029:1029)) + (PORT datad (845:845:845) (875:875:875)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (868:868:868) (877:877:877)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (869:869:869) (877:877:877)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (333:333:333)) + (PORT datab (260:260:260) (314:314:314)) + (PORT datad (229:229:229) (267:267:267)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (870:870:870)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datac (607:607:607) (626:626:626)) + (PORT datad (625:625:625) (639:639:639)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (895:895:895)) + (PORT datab (609:609:609) (627:627:627)) + (PORT datac (332:332:332) (359:359:359)) + (PORT datad (1115:1115:1115) (1138:1138:1138)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (957:957:957) (1002:1002:1002)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1331:1331:1331) (1374:1374:1374)) + (PORT datab (697:697:697) (731:731:731)) + (PORT datad (1194:1194:1194) (1238:1238:1238)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (669:669:669)) + (PORT datac (704:704:704) (742:742:742)) + (PORT datad (220:220:220) (290:290:290)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (401:401:401)) + (PORT datab (960:960:960) (999:999:999)) + (PORT datac (683:683:683) (718:718:718)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT datab (240:240:240) (286:286:286)) + (PORT datac (548:548:548) (560:560:560)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT asdata (870:870:870) (882:882:882)) + (PORT clrn (1597:1597:1597) (1572:1572:1572)) + (PORT ena (2143:2143:2143) (2210:2210:2210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (429:429:429)) + (PORT datab (1153:1153:1153) (1183:1183:1183)) + (PORT datac (963:963:963) (1032:1032:1032)) + (PORT datad (244:244:244) (316:316:316)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (392:392:392)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (340:340:340) (367:367:367)) + (PORT datad (324:324:324) (346:346:346)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (352:352:352)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (332:332:332) (358:358:358)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1239:1239:1239) (1260:1260:1260)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1236:1236:1236) (1256:1256:1256)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (258:258:258) (310:310:310)) + (PORT datad (228:228:228) (266:266:266)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (663:663:663)) + (PORT datab (1133:1133:1133) (1182:1182:1182)) + (PORT datad (630:630:630) (644:644:644)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1202:1202:1202) (1222:1222:1222)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1206:1206:1206) (1227:1227:1227)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (466:466:466)) + (PORT datab (591:591:591) (631:631:631)) + (PORT datad (218:218:218) (288:288:288)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1505:1505:1505) (1518:1518:1518)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (958:958:958) (967:967:967)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (960:960:960) (969:969:969)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (505:505:505)) + (PORT datab (668:668:668) (703:703:703)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (665:665:665)) + (PORT datab (920:920:920) (943:943:943)) + (PORT datac (213:213:213) (288:288:288)) + (PORT datad (335:335:335) (356:356:356)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (993:993:993) (1020:1020:1020)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (995:995:995) (1022:1022:1022)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (922:922:922)) + (PORT datab (965:965:965) (1021:1021:1021)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (984:984:984) (1006:1006:1006)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (982:982:982) (1003:1003:1003)) + (PORT ena (1220:1220:1220) (1214:1214:1214)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (700:700:700)) + (PORT datab (396:396:396) (436:436:436)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (875:875:875) (882:882:882)) + (PORT ena (1407:1407:1407) (1382:1382:1382)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (547:547:547)) + (PORT datad (825:825:825) (835:835:835)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (377:377:377)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1018:1018:1018) (1019:1019:1019)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) (DELAY (ABSOLUTE (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (242:242:242) (281:281:281)) - (PORT datad (414:414:414) (486:486:486)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (856:856:856) (875:875:875)) + (PORT datac (1094:1094:1094) (1126:1126:1126)) + (PORT datad (1162:1162:1162) (1190:1190:1190)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1359:1359:1359) (1370:1370:1370)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (911:911:911)) + (PORT datab (1236:1236:1236) (1275:1275:1275)) + (PORT datad (664:664:664) (688:688:688)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (624:624:624) (675:675:675)) + (PORT datac (704:704:704) (739:739:739)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (401:401:401)) + (PORT datab (959:959:959) (1001:1001:1001)) + (PORT datac (682:682:682) (721:721:721)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -20546,9 +24659,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[4\]) (DELAY (ABSOLUTE - (PORT datac (873:873:873) (909:909:909)) - (PORT datad (1286:1286:1286) (1372:1372:1372)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (238:238:238) (283:283:283)) + (PORT datad (529:529:529) (540:540:540)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -20558,10 +24671,10 @@ (INSTANCE z80_\|address_latch_\|Q\[4\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1542:1542:1542)) - (PORT asdata (538:538:538) (569:569:569)) - (PORT clrn (1569:1569:1569) (1549:1549:1549)) - (PORT ena (2195:2195:2195) (2230:2230:2230)) + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT asdata (852:852:852) (858:858:858)) + (PORT clrn (1597:1597:1597) (1572:1572:1572)) + (PORT ena (2143:2143:2143) (2210:2210:2210)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -20576,10 +24689,13 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) (DELAY (ABSOLUTE - (PORT datab (1084:1084:1084) (1121:1121:1121)) - (PORT datac (858:858:858) (982:982:982)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1155:1155:1155) (1182:1182:1182)) + (PORT datab (985:985:985) (1022:1022:1022)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -20588,71 +24704,12 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) (DELAY (ABSOLUTE - (PORT dataa (902:902:902) (956:956:956)) - (PORT datab (888:888:888) (1023:1023:1023)) - (PORT datac (1051:1051:1051) (1089:1089:1089)) - (PORT datad (673:673:673) (758:758:758)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT dataa (710:710:710) (770:770:770)) + (PORT datab (1162:1162:1162) (1199:1199:1199)) + (PORT datac (626:626:626) (647:647:647)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (928:928:928) (951:951:951)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1228:1228:1228) (1255:1255:1255)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (709:709:709) (761:761:761)) - (PORT datad (681:681:681) (734:734:734)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -20661,9 +24718,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1855:1855:1855) (1878:1878:1878)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (879:879:879) (891:891:891)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20677,9 +24734,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1852:1852:1852) (1873:1873:1873)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (878:878:878) (893:893:893)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20693,9 +24750,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) (DELAY (ABSOLUTE - (PORT dataa (391:391:391) (463:463:463)) - (PORT datab (702:702:702) (741:741:741)) - (PORT datad (662:662:662) (685:685:685)) + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (966:966:966) (1022:1022:1022)) + (PORT datad (843:843:843) (873:873:873)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -20705,12 +24762,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1010:1010:1010) (1031:1031:1031)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (692:692:692) (715:715:715)) + (PORT ena (1477:1477:1477) (1472:1472:1472)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20721,12 +24778,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1010:1010:1010) (1030:1030:1030)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (692:692:692) (713:713:713)) + (PORT ena (1247:1247:1247) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20737,71 +24794,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) (DELAY (ABSOLUTE - (PORT dataa (664:664:664) (695:695:695)) - (PORT datab (871:871:871) (938:938:938)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1202:1202:1202) (1230:1230:1230)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1543:1543:1543)) - (PORT asdata (954:954:954) (977:977:977)) - (PORT ena (1455:1455:1455) (1491:1491:1491)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (677:677:677)) - (PORT datab (648:648:648) (697:697:697)) - (PORT datad (581:581:581) (600:600:600)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1095:1095:1095) (1134:1134:1134)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (658:658:658) (679:679:679)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20809,12 +24809,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (544:544:544) (580:580:580)) - (PORT ena (1475:1475:1475) (1471:1471:1471)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1437:1437:1437) (1460:1460:1460)) + (PORT ena (1505:1505:1505) (1518:1518:1518)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20823,45 +24823,14 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (927:927:927) (940:940:940)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (996:996:996)) - (PORT datab (901:901:901) (917:917:917)) - (PORT datad (235:235:235) (274:274:274)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (725:725:725) (752:752:752)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1457:1457:1457) (1472:1472:1472)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20875,11 +24844,24 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) (DELAY (ABSOLUTE - (PORT dataa (279:279:279) (351:351:351)) - (PORT datab (931:931:931) (974:974:974)) - (PORT datad (813:813:813) (836:836:836)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (458:458:458) (494:494:494)) + (PORT datab (1132:1132:1132) (1177:1177:1177)) + (PORT datad (626:626:626) (636:636:636)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT datab (918:918:918) (940:940:940)) + (PORT datad (338:338:338) (359:359:359)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20887,12 +24869,28 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1543:1543:1543)) - (PORT asdata (953:953:953) (974:974:974)) - (PORT ena (816:816:816) (813:813:813)) + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1214:1214:1214) (1217:1217:1217)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1214:1214:1214) (1215:1215:1215)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20903,12 +24901,128 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) (DELAY (ABSOLUTE - (PORT datab (370:370:370) (407:407:407)) - (PORT datad (216:216:216) (248:248:248)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (409:409:409) (467:467:467)) + (PORT datab (592:592:592) (632:632:632)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1471:1471:1471) (1477:1477:1477)) + (PORT ena (1220:1220:1220) (1214:1214:1214)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (607:607:607) (622:622:622)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (693:693:693)) + (PORT datab (390:390:390) (429:429:429)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (853:853:853) (859:859:859)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1407:1407:1407) (1382:1382:1382)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1457:1457:1457) (1474:1474:1474)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (638:638:638)) + (PORT datab (836:836:836) (860:860:860)) + (PORT datad (645:645:645) (669:669:669)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20919,10 +25033,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) (DELAY (ABSOLUTE - (PORT dataa (809:809:809) (864:864:864)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (343:343:343) (369:369:369)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (638:638:638) (656:656:656)) + (PORT datab (1118:1118:1118) (1148:1148:1148)) + (PORT datac (339:339:339) (359:359:359)) + (PORT datad (587:587:587) (601:601:601)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -20935,11 +25049,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) (DELAY (ABSOLUTE - (PORT dataa (856:856:856) (889:889:889)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datad (823:823:823) (843:843:843)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (372:372:372) (394:394:394)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -20949,13 +25063,13 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) (DELAY (ABSOLUTE - (PORT dataa (1335:1335:1335) (1358:1358:1358)) - (PORT datab (582:582:582) (598:598:598)) - (PORT datac (348:348:348) (373:373:373)) - (PORT datad (1286:1286:1286) (1413:1413:1413)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (639:639:639) (699:699:699)) + (PORT datab (929:929:929) (992:992:992)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1608:1608:1608) (1611:1611:1611)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -20965,9 +25079,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (691:691:691) (714:714:714)) - (PORT ena (816:816:816) (813:813:813)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1227:1227:1227) (1243:1243:1243)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -20981,34 +25095,24 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (243:243:243) (289:289:289)) - (PORT datad (1247:1247:1247) (1245:1245:1245)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1190:1190:1190) (1197:1197:1197)) + (PORT datab (1236:1236:1236) (1275:1275:1275)) + (PORT datad (664:664:664) (688:688:688)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (194:194:194) (219:219:219)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1548:1548:1548)) + (PORT clk (1534:1534:1534) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1246:1246:1246) (1261:1261:1261)) + (PORT ena (811:811:811) (804:804:804)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21022,11 +25126,11 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) (DELAY (ABSOLUTE - (PORT dataa (381:381:381) (407:407:407)) - (PORT datac (391:391:391) (417:417:417)) + (PORT dataa (229:229:229) (275:275:275)) + (PORT datac (613:613:613) (632:632:632)) (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21036,11 +25140,11 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) (DELAY (ABSOLUTE - (PORT dataa (1278:1278:1278) (1351:1351:1351)) - (PORT datab (607:607:607) (636:636:636)) - (PORT datac (560:560:560) (589:589:589)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) + (PORT dataa (655:655:655) (670:670:670)) + (PORT datab (1331:1331:1331) (1335:1335:1335)) + (PORT datac (192:192:192) (224:224:224)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -21052,19 +25156,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[5\]) (DELAY (ABSOLUTE - (PORT datac (630:630:630) (659:659:659)) - (PORT datad (1287:1287:1287) (1376:1376:1376)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (194:194:194) (219:219:219)) + (PORT datac (653:653:653) (693:693:693)) + (PORT datad (834:834:834) (843:843:843)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21074,10 +25168,10 @@ (INSTANCE z80_\|address_latch_\|Q\[5\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1542:1542:1542)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1549:1549:1549)) - (PORT ena (2195:2195:2195) (2230:2230:2230)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2152:2152:2152) (2220:2220:2220)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -21089,15 +25183,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) (DELAY (ABSOLUTE - (PORT dataa (610:610:610) (686:686:686)) - (PORT datab (1118:1118:1118) (1165:1165:1165)) - (PORT datac (185:185:185) (228:228:228)) - (PORT datad (1060:1060:1060) (1086:1086:1086)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (369:369:369)) + (PORT dataa (920:920:920) (994:994:994)) + (PORT datab (1154:1154:1154) (1178:1178:1178)) + (PORT datac (960:960:960) (1026:1026:1026)) + (PORT datad (362:362:362) (387:387:387)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21108,10 +25202,10 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) (DELAY (ABSOLUTE - (PORT dataa (902:902:902) (957:957:957)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (607:607:607) (676:676:676)) - (PORT datad (864:864:864) (916:916:916)) + (PORT dataa (657:657:657) (687:687:687)) + (PORT datab (1161:1161:1161) (1198:1198:1198)) + (PORT datac (811:811:811) (865:865:865)) + (PORT datad (615:615:615) (643:643:643)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -21119,16 +25213,449 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1286:1286:1286)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1676:1676:1676) (1684:1684:1684)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1342:1342:1342) (1345:1345:1345)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (918:918:918)) + (PORT datab (966:966:966) (1020:1020:1020)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1896:1896:1896) (1881:1881:1881)) + (PORT ena (1477:1477:1477) (1472:1472:1472)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1893:1893:1893) (1878:1878:1878)) + (PORT ena (1247:1247:1247) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1133:1133:1133)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (654:654:654) (676:676:676)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (2168:2168:2168) (2154:2154:2154)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1053:1053:1053) (1073:1073:1073)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (470:470:470)) + (PORT datab (637:637:637) (669:669:669)) + (PORT datad (374:374:374) (432:432:432)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1463:1463:1463) (1454:1454:1454)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (771:771:771)) + (PORT datab (945:945:945) (995:995:995)) + (PORT datac (878:878:878) (894:894:894)) + (PORT datad (606:606:606) (625:625:625)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (2168:2168:2168) (2153:2153:2153)) + (PORT ena (1499:1499:1499) (1507:1507:1507)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1302:1302:1302) (1310:1310:1310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1608:1608:1608) (1628:1628:1628)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (503:503:503)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (640:640:640) (666:666:666)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT datab (1410:1410:1410) (1425:1425:1425)) + (PORT datad (563:563:563) (574:574:574)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1342:1342:1342) (1366:1366:1366)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1430:1430:1430) (1466:1466:1466)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (471:471:471)) + (PORT datab (584:584:584) (622:622:622)) + (PORT datad (835:835:835) (900:900:900)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (399:399:399)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (794:794:794) (791:791:791)) + (PORT datad (776:776:776) (774:774:774)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (625:625:625)) + (PORT datab (658:658:658) (716:716:716)) + (PORT datac (1393:1393:1393) (1416:1416:1416)) + (PORT datad (599:599:599) (618:618:618)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (967:967:967) (1025:1025:1025)) + (PORT ena (1201:1201:1201) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1322:1322:1322) (1350:1350:1350)) + (PORT datab (1232:1232:1232) (1270:1270:1270)) + (PORT datad (660:660:660) (687:687:687)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (673:673:673) (705:705:705)) + (PORT datac (668:668:668) (749:749:749)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) (DELAY (ABSOLUTE - (PORT dataa (617:617:617) (633:633:633)) - (PORT datab (1321:1321:1321) (1345:1345:1345)) - (PORT datac (579:579:579) (597:597:597)) - (PORT datad (1421:1421:1421) (1524:1524:1524)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (714:714:714) (760:760:760)) + (PORT datab (648:648:648) (689:689:689)) + (PORT datac (926:926:926) (965:965:965)) + (PORT datad (593:593:593) (644:644:644)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -21140,9 +25667,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[6\]) (DELAY (ABSOLUTE - (PORT datac (869:869:869) (887:887:887)) - (PORT datad (1213:1213:1213) (1311:1311:1311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datac (652:652:652) (694:694:694)) + (PORT datad (819:819:819) (838:838:838)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21152,10 +25679,10 @@ (INSTANCE z80_\|address_latch_\|Q\[6\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1548:1548:1548)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1564:1564:1564)) - (PORT ena (2593:2593:2593) (2662:2662:2662)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (2152:2152:2152) (2220:2220:2220)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -21167,15 +25694,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~2) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) (DELAY (ABSOLUTE - (PORT dataa (1451:1451:1451) (1567:1567:1567)) - (PORT datab (1363:1363:1363) (1443:1443:1443)) - (PORT datac (624:624:624) (674:674:674)) - (PORT datad (600:600:600) (635:635:635)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (628:628:628) (670:670:670)) + (PORT datab (632:632:632) (673:673:673)) + (PORT datac (811:811:811) (863:863:863)) + (PORT datad (1165:1165:1165) (1193:1193:1193)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21186,10 +25713,10 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (662:662:662)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (870:870:870) (916:916:916)) - (PORT datad (863:863:863) (916:916:916)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1158:1158:1158) (1194:1194:1194)) + (PORT datac (628:628:628) (651:651:651)) + (PORT datad (616:616:616) (644:644:644)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -21202,35 +25729,25 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) (DELAY (ABSOLUTE - (PORT datac (902:902:902) (967:967:967)) - (PORT datad (612:612:612) (627:627:627)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (423:423:423) (515:515:515)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1236:1236:1236) (1262:1262:1262)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]\~feeder) + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) (DELAY (ABSOLUTE - (PORT datad (883:883:883) (906:906:906)) + (PORT dataa (708:708:708) (752:752:752)) + (PORT datab (962:962:962) (1002:1002:1002)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (619:619:619) (645:645:645)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21240,40 +25757,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (776:776:776)) - (PORT datab (709:709:709) (761:761:761)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1520:1520:1520) (1559:1559:1559)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1212:1212:1212) (1251:1251:1251)) + (PORT ena (1477:1477:1477) (1472:1472:1472)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21282,14 +25768,61 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1211:1211:1211) (1254:1254:1254)) + (PORT ena (1247:1247:1247) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1137:1137:1137)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (656:656:656) (679:679:679)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1519:1519:1519) (1558:1558:1558)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1408:1408:1408) (1437:1437:1437)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1410:1410:1410) (1439:1439:1439)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21303,11 +25836,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) (DELAY (ABSOLUTE - (PORT dataa (387:387:387) (459:459:459)) - (PORT datab (701:701:701) (738:738:738)) - (PORT datad (659:659:659) (681:681:681)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (876:876:876) (924:924:924)) + (PORT datab (963:963:963) (1013:1013:1013)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21318,9 +25851,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1510:1510:1510) (1548:1548:1548)) - (PORT ena (812:812:812) (804:804:804)) + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (1934:1934:1934) (1968:1968:1968)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21329,71 +25862,24 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1624:1624:1624) (1645:1645:1645)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1509:1509:1509) (1548:1548:1548)) - (PORT ena (1472:1472:1472) (1481:1481:1481)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (281:281:281) (346:346:346)) - (PORT datab (700:700:700) (743:743:743)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (690:690:690) (730:730:730)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (626:626:626) (649:649:649)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) + (PORT clk (1528:1528:1528) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21404,12 +25890,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (949:949:949)) - (PORT datab (354:354:354) (387:387:387)) - (PORT datad (618:618:618) (674:674:674)) + (PORT dataa (435:435:435) (469:469:469)) + (PORT datab (636:636:636) (669:669:669)) + (PORT datad (370:370:370) (429:429:429)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -21419,17 +25905,33 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1450:1450:1450) (1505:1505:1505)) + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (1932:1932:1932) (1967:1967:1967)) + (PORT ena (1499:1499:1499) (1507:1507:1507)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1954:1954:1954) (1989:1989:1989)) + (PORT ena (1263:1263:1263) (1264:1264:1264)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -21438,9 +25940,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (686:686:686) (713:713:713)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1954:1954:1954) (1989:1989:1989)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21454,9 +25956,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) (DELAY (ABSOLUTE - (PORT dataa (274:274:274) (345:345:345)) - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (585:585:585) (613:613:613)) + (PORT dataa (459:459:459) (495:495:495)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (640:640:640) (664:664:664)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -21465,13 +25967,42 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (693:693:693) (730:730:730)) - (PORT ena (1447:1447:1447) (1426:1426:1426)) + (PORT datab (1411:1411:1411) (1427:1427:1427)) + (PORT datad (587:587:587) (598:598:598)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1731:1731:1731) (1772:1772:1772)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1730:1730:1730) (1774:1774:1774)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -21482,12 +26013,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) (DELAY (ABSOLUTE - (PORT dataa (344:344:344) (382:382:382)) - (PORT datad (632:632:632) (652:652:652)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (407:407:407) (467:467:467)) + (PORT datab (591:591:591) (631:631:631)) + (PORT datad (216:216:216) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21498,14 +26031,14 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (1766:1766:1766) (1777:1777:1777)) - (PORT ena (790:790:790) (782:782:782)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1463:1463:1463) (1454:1454:1454)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -21514,12 +26047,13 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) (DELAY (ABSOLUTE - (PORT dataa (591:591:591) (624:624:624)) - (PORT datab (258:258:258) (309:309:309)) - (PORT datad (619:619:619) (632:632:632)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (646:646:646) (738:738:738)) + (PORT datab (944:944:944) (996:996:996)) + (PORT datac (844:844:844) (845:845:845)) + (PORT datad (606:606:606) (623:623:623)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21529,10 +26063,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (368:368:368)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (558:558:558) (574:574:574)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (496:496:496) (503:503:503)) + (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -21545,11 +26079,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) (DELAY (ABSOLUTE - (PORT datab (606:606:606) (623:623:623)) - (PORT datac (594:594:594) (601:601:601)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (364:364:364) (385:385:385)) + (PORT datad (573:573:573) (586:586:586)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21559,73 +26093,12 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) (DELAY (ABSOLUTE - (PORT dataa (1283:1283:1283) (1398:1398:1398)) - (PORT datab (1613:1613:1613) (1619:1619:1619)) - (PORT datac (605:605:605) (623:623:623)) - (PORT datad (327:327:327) (344:344:344)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (659:659:659) (677:677:677)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (692:692:692)) - (PORT datab (247:247:247) (295:295:295)) - (PORT datad (1250:1250:1250) (1249:1249:1249)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1246:1246:1246) (1261:1261:1261)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (387:387:387)) - (PORT datac (390:390:390) (416:416:416)) - (PORT datad (215:215:215) (282:282:282)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (667:667:667) (723:723:723)) + (PORT datab (660:660:660) (704:704:704)) + (PORT datac (1391:1391:1391) (1414:1414:1414)) + (PORT datad (597:597:597) (618:618:618)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21633,51 +26106,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1279:1279:1279) (1348:1348:1348)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (561:561:561) (587:587:587)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT datac (614:614:614) (652:652:652)) - (PORT datad (1290:1290:1290) (1377:1377:1377)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (193:193:193) (218:218:218)) + (PORT dataa (1484:1484:1484) (1528:1528:1528)) + (PORT datab (1645:1645:1645) (1711:1711:1711)) + (PORT datac (872:872:872) (914:914:914)) + (PORT datad (1163:1163:1163) (1203:1203:1203)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) + (INSTANCE z80_\|interrupts_\|im2) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1542:1542:1542)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1549:1549:1549)) - (PORT ena (2195:2195:2195) (2230:2230:2230)) + (PORT clrn (1571:1571:1571) (1550:1550:1550)) + (PORT ena (1258:1258:1258) (1280:1280:1280)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -21689,799 +26140,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (INSTANCE z80_\|execute_\|ctl_mRead\~12) (DELAY (ABSOLUTE - (PORT datac (934:934:934) (978:978:978)) - (PORT datad (1211:1211:1211) (1308:1308:1308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1564:1564:1564)) - (PORT ena (2593:2593:2593) (2662:2662:2662)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (279:279:279)) - (PORT datab (1085:1085:1085) (1123:1123:1123)) - (PORT datac (656:656:656) (746:746:746)) - (PORT datad (389:389:389) (450:450:450)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (901:901:901) (912:912:912)) - (PORT datac (1660:1660:1660) (1788:1788:1788)) - (PORT datad (375:375:375) (399:399:399)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1696:1696:1696) (1727:1727:1727)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1696:1696:1696) (1730:1730:1730)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (471:471:471)) - (PORT datab (435:435:435) (466:466:466)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (924:924:924) (940:940:940)) - (PORT ena (1249:1249:1249) (1247:1247:1247)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1216:1216:1216)) - (PORT datab (1875:1875:1875) (1953:1953:1953)) - (PORT datad (1634:1634:1634) (1689:1689:1689)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (979:979:979) (1011:1011:1011)) - (PORT ena (979:979:979) (971:971:971)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (978:978:978) (1015:1015:1015)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (476:476:476)) - (PORT datab (428:428:428) (469:469:469)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1545:1545:1545) (1545:1545:1545)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1336:1336:1336) (1362:1362:1362)) - (PORT datab (1193:1193:1193) (1247:1247:1247)) - (PORT datad (392:392:392) (408:408:408)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (1157:1157:1157) (1167:1167:1167)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (516:516:516)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (665:665:665) (698:698:698)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1233:1233:1233) (1253:1253:1253)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1233:1233:1233) (1251:1251:1251)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (661:661:661) (684:684:684)) - (PORT datad (626:626:626) (645:645:645)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (661:661:661)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (316:316:316) (344:344:344)) - (PORT datad (566:566:566) (577:577:577)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1456:1456:1456) (1478:1478:1478)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1456:1456:1456) (1476:1476:1476)) - (PORT ena (1011:1011:1011) (1021:1021:1021)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (986:986:986)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (229:229:229) (266:266:266)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (661:661:661)) - (PORT datab (370:370:370) (393:393:393)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (795:795:795) (818:818:818)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (632:632:632)) - (PORT datab (1983:1983:1983) (2128:2128:2128)) - (PORT datac (541:541:541) (546:546:546)) - (PORT datad (569:569:569) (582:582:582)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (928:928:928)) - (PORT datab (875:875:875) (899:899:899)) - (PORT datac (1240:1240:1240) (1283:1283:1283)) - (PORT datad (1140:1140:1140) (1157:1157:1157)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1142:1142:1142)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (585:585:585) (607:607:607)) - (PORT datad (227:227:227) (273:273:273)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1171:1171:1171)) - (PORT datab (875:875:875) (926:926:926)) - (PORT datac (1191:1191:1191) (1288:1288:1288)) - (PORT datad (1037:1037:1037) (1115:1115:1115)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (750:750:750) (840:840:840)) - (PORT datab (908:908:908) (961:961:961)) - (PORT datac (1190:1190:1190) (1289:1289:1289)) - (PORT datad (1036:1036:1036) (1115:1115:1115)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (753:753:753) (844:844:844)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (206:206:206)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1231:1231:1231) (1328:1328:1328)) - (PORT datac (872:872:872) (894:894:894)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (1534:1534:1534) (1635:1635:1635)) - (PORT datac (1116:1116:1116) (1137:1137:1137)) - (PORT datad (1296:1296:1296) (1328:1328:1328)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1073:1073:1073) (1101:1101:1101)) - (PORT datab (913:913:913) (937:937:937)) - (PORT datac (919:919:919) (987:987:987)) - (PORT datad (234:234:234) (311:311:311)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (904:904:904)) - (PORT datab (606:606:606) (635:635:635)) - (PORT datac (816:816:816) (834:834:834)) - (PORT datad (819:819:819) (855:855:855)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (419:419:419) (468:468:468)) - (PORT datab (1085:1085:1085) (1112:1112:1112)) - (PORT datac (772:772:772) (787:787:787)) - (PORT datad (234:234:234) (274:274:274)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1545:1545:1545) (1647:1647:1647)) - (PORT datab (1017:1017:1017) (1086:1086:1086)) - (PORT datac (817:817:817) (844:844:844)) - (PORT datad (1826:1826:1826) (1840:1840:1840)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (847:847:847)) - (PORT datab (796:796:796) (840:840:840)) - (PORT datac (824:824:824) (850:850:850)) - (PORT datad (581:581:581) (591:591:591)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (403:403:403)) - (PORT datab (639:639:639) (656:656:656)) - (PORT datad (546:546:546) (556:556:556)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (666:666:666)) - (PORT datab (1369:1369:1369) (1415:1415:1415)) - (PORT datac (1087:1087:1087) (1124:1124:1124)) - (PORT datad (1100:1100:1100) (1103:1103:1103)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (254:254:254)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (899:899:899) (957:957:957)) - (PORT datad (229:229:229) (267:267:267)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1666:1666:1666) (1702:1702:1702)) - (PORT datab (1097:1097:1097) (1153:1153:1153)) - (PORT datac (1117:1117:1117) (1189:1189:1189)) - (PORT datad (2828:2828:2828) (2893:2893:2893)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (1631:1631:1631) (1675:1675:1675)) - (PORT datab (1017:1017:1017) (1087:1087:1087)) - (PORT datac (769:769:769) (779:779:779)) - (PORT datad (1777:1777:1777) (1826:1826:1826)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1548:1548:1548) (1653:1653:1653)) - (PORT datab (610:610:610) (655:655:655)) - (PORT datac (814:814:814) (842:842:842)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (696:696:696)) - (PORT datab (804:804:804) (830:830:830)) - (PORT datac (386:386:386) (427:427:427)) - (PORT datad (839:839:839) (856:856:856)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (868:868:868)) - (PORT datab (884:884:884) (930:930:930)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (231:231:231) (271:271:271)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1208:1208:1208)) - (PORT datab (1193:1193:1193) (1245:1245:1245)) - (PORT datac (823:823:823) (863:863:863)) - (PORT datad (1067:1067:1067) (1124:1124:1124)) + (PORT dataa (354:354:354) (492:492:492)) + (PORT datac (1227:1227:1227) (1295:1295:1295)) + (PORT datad (274:274:274) (356:356:356)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1654:1654:1654) (1773:1773:1773)) - (PORT datab (1786:1786:1786) (1844:1844:1844)) - (PORT datac (801:801:801) (813:813:813)) - (PORT datad (1365:1365:1365) (1419:1419:1419)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (712:712:712)) - (PORT datab (673:673:673) (691:691:691)) - (PORT datac (1202:1202:1202) (1209:1209:1209)) - (PORT datad (848:848:848) (897:897:897)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (2236:2236:2236) (2302:2302:2302)) - (PORT datad (581:581:581) (621:621:621)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -22489,291 +26154,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) (DELAY (ABSOLUTE - (PORT dataa (686:686:686) (713:713:713)) - (PORT datab (228:228:228) (268:268:268)) - (PORT datac (828:828:828) (850:850:850)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1549:1549:1549) (1648:1648:1648)) - (PORT datab (615:615:615) (649:649:649)) - (PORT datac (811:811:811) (841:841:841)) - (PORT datad (1821:1821:1821) (1838:1838:1838)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (640:640:640) (692:692:692)) - (PORT datac (806:806:806) (823:823:823)) - (PORT datad (632:632:632) (683:683:683)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) - (DELAY - (ABSOLUTE - (PORT datac (827:827:827) (853:853:853)) - (PORT datad (204:204:204) (234:234:234)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (946:946:946)) - (PORT datab (884:884:884) (906:906:906)) - (PORT datac (1650:1650:1650) (1728:1728:1728)) - (PORT datad (1132:1132:1132) (1178:1178:1178)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (895:895:895) (937:937:937)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (812:812:812) (850:850:850)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (538:538:538) (562:562:562)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1220:1220:1220)) - (PORT datab (855:855:855) (902:902:902)) - (PORT datad (1062:1062:1062) (1081:1081:1081)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (368:368:368)) - (PORT datab (877:877:877) (890:890:890)) - (PORT datac (1498:1498:1498) (1562:1562:1562)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (973:973:973)) - (PORT datab (900:900:900) (959:959:959)) - (PORT datac (1007:1007:1007) (1018:1018:1018)) - (PORT datad (1008:1008:1008) (1030:1030:1030)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (920:920:920)) - (PORT datab (1384:1384:1384) (1396:1396:1396)) - (PORT datac (215:215:215) (292:292:292)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1183:1183:1183)) - (PORT datab (833:833:833) (886:886:886)) - (PORT datac (986:986:986) (1032:1032:1032)) - (PORT datad (1047:1047:1047) (1094:1094:1094)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1031:1031:1031) (1055:1055:1055)) - (PORT datab (821:821:821) (852:852:852)) - (PORT datac (1064:1064:1064) (1128:1128:1128)) - (PORT datad (1042:1042:1042) (1102:1102:1102)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (917:917:917)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1075:1075:1075) (1098:1098:1098)) - (PORT datad (1428:1428:1428) (1508:1508:1508)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (684:684:684)) - (PORT datab (690:690:690) (711:711:711)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1500:1500:1500)) - (PORT datab (1662:1662:1662) (1684:1684:1684)) - (PORT datac (1606:1606:1606) (1632:1632:1632)) - (PORT datad (601:601:601) (635:635:635)) + (PORT dataa (356:356:356) (494:494:494)) + (PORT datab (716:716:716) (747:747:747)) + (PORT datac (192:192:192) (224:224:224)) + (PORT datad (1301:1301:1301) (1395:1395:1395)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (INSTANCE z80_\|alu_control_\|db\[7\]\~17) (DELAY (ABSOLUTE - (PORT dataa (864:864:864) (893:893:893)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (599:599:599) (634:634:634)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1519:1519:1519) (1574:1574:1574)) - (PORT datab (1443:1443:1443) (1467:1467:1467)) - (PORT datac (1148:1148:1148) (1178:1178:1178)) - (PORT datad (342:342:342) (363:363:363)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (881:881:881) (903:903:903)) + (PORT datab (928:928:928) (957:957:957)) + (PORT datac (631:631:631) (687:687:687)) + (PORT datad (632:632:632) (647:647:647)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -22782,143 +26186,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (INSTANCE z80_\|alu_control_\|db\[7\]\~16) (DELAY (ABSOLUTE - (PORT dataa (1237:1237:1237) (1328:1328:1328)) - (PORT datab (792:792:792) (812:812:812)) - (PORT datac (1586:1586:1586) (1627:1627:1627)) - (PORT datad (1780:1780:1780) (1830:1830:1830)) + (PORT dataa (841:841:841) (861:861:861)) + (PORT datab (852:852:852) (879:879:879)) + (PORT datac (900:900:900) (940:940:940)) + (PORT datad (639:639:639) (700:700:700)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (244:244:244) (291:291:291)) + (PORT datac (645:645:645) (698:698:698)) + (PORT datad (617:617:617) (628:628:628)) (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (539:539:539) (542:542:542)) - (PORT datad (611:611:611) (639:639:639)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (911:911:911)) - (PORT datab (684:684:684) (749:749:749)) - (PORT datac (594:594:594) (652:652:652)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1207:1207:1207)) - (PORT datab (1447:1447:1447) (1536:1536:1536)) - (PORT datac (1951:1951:1951) (2070:2070:2070)) - (PORT datad (1166:1166:1166) (1254:1254:1254)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (945:945:945)) - (PORT datab (226:226:226) (267:267:267)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (948:948:948) (1030:1030:1030)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1491:1491:1491) (1608:1608:1608)) - (PORT datab (856:856:856) (927:927:927)) - (PORT datac (1372:1372:1372) (1428:1428:1428)) - (PORT datad (563:563:563) (590:590:590)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) - (DELAY - (ABSOLUTE - (PORT dataa (913:913:913) (959:959:959)) - (PORT datab (820:820:820) (860:860:860)) - (PORT datac (1128:1128:1128) (1198:1198:1198)) - (PORT datad (1146:1146:1146) (1198:1198:1198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (960:960:960)) - (PORT datab (1138:1138:1138) (1208:1208:1208)) - (PORT datac (1128:1128:1128) (1199:1199:1199)) - (PORT datad (1171:1171:1171) (1285:1285:1285)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (1072:1072:1072)) - (PORT datab (917:917:917) (968:968:968)) - (PORT datac (881:881:881) (904:904:904)) - (PORT datad (2379:2379:2379) (2460:2460:2460)) - (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (738:738:738)) + (PORT datab (889:889:889) (932:932:932)) + (PORT datac (869:869:869) (862:862:862)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -22926,230 +26234,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (853:853:853) (863:863:863)) - (PORT datac (837:837:837) (883:883:883)) - (PORT datad (1625:1625:1625) (1671:1671:1671)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (665:665:665)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (539:539:539) (558:558:558)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1004:1004:1004) (1081:1081:1081)) - (PORT datab (1331:1331:1331) (1350:1350:1350)) - (PORT datac (1167:1167:1167) (1241:1241:1241)) - (PORT datad (1296:1296:1296) (1381:1381:1381)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1084:1084:1084)) - (PORT datab (1335:1335:1335) (1345:1345:1345)) - (PORT datac (859:859:859) (910:910:910)) - (PORT datad (2215:2215:2215) (2297:2297:2297)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (615:615:615)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (938:938:938) (991:991:991)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (611:611:611) (629:629:629)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) - (DELAY - (ABSOLUTE - (PORT datab (1120:1120:1120) (1154:1154:1154)) - (PORT datac (1197:1197:1197) (1192:1192:1192)) - (PORT datad (806:806:806) (838:838:838)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1121:1121:1121)) - (PORT datab (872:872:872) (919:919:919)) - (PORT datac (516:516:516) (526:526:526)) - (PORT datad (1080:1080:1080) (1085:1085:1085)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (683:683:683) (731:731:731)) - (PORT datac (793:793:793) (806:806:806)) + (PORT dataa (1252:1252:1252) (1344:1344:1344)) + (PORT datab (857:857:857) (911:911:911)) + (PORT datac (614:614:614) (652:652:652)) (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (661:661:661)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (2026:2026:2026) (2034:2034:2034)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (923:923:923)) - (PORT datab (209:209:209) (251:251:251)) - (PORT datad (550:550:550) (565:565:565)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (1563:1563:1563) (1570:1570:1570)) - (PORT datab (1404:1404:1404) (1478:1478:1478)) - (PORT datac (616:616:616) (628:628:628)) - (PORT datad (1609:1609:1609) (1666:1666:1666)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (722:722:722)) - (PORT datab (1063:1063:1063) (1095:1095:1095)) - (PORT datac (1261:1261:1261) (1291:1291:1291)) - (PORT datad (1295:1295:1295) (1334:1334:1334)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1174:1174:1174)) - (PORT datac (653:653:653) (694:694:694)) - (PORT datad (884:884:884) (949:949:949)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) (DELAY (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) + (PORT clk (1511:1511:1511) (1525:1525:1525)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) + (PORT ena (843:843:843) (856:856:856)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -23160,149 +26266,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~9) + (INSTANCE z80_\|pla_decode_\|Equal62\~3) (DELAY (ABSOLUTE - (PORT dataa (1069:1069:1069) (1092:1092:1092)) - (PORT datab (256:256:256) (342:342:342)) - (PORT datac (876:876:876) (895:895:895)) - (PORT datad (683:683:683) (775:775:775)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1232:1232:1232) (1327:1327:1327)) - (PORT datab (706:706:706) (741:741:741)) - (PORT datac (673:673:673) (709:709:709)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (958:958:958)) - (PORT datac (1505:1505:1505) (1609:1609:1609)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (656:656:656)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (1449:1449:1449) (1480:1480:1480)) - (PORT datad (626:626:626) (643:643:643)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (274:274:274)) - (PORT datab (345:345:345) (371:371:371)) - (PORT datac (816:816:816) (847:847:847)) - (PORT datad (824:824:824) (851:851:851)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1447:1447:1447)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (641:641:641) (682:682:682)) - (PORT datad (1053:1053:1053) (1066:1066:1066)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (904:904:904)) - (PORT datac (171:171:171) (204:204:204)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1241:1241:1241) (1256:1256:1256)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1386:1386:1386) (1432:1432:1432)) - (PORT datab (678:678:678) (744:744:744)) - (PORT datac (1028:1028:1028) (1055:1055:1055)) - (PORT datad (532:532:532) (548:548:548)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (206:206:206) (249:249:249)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (181:181:181) (210:210:210)) + (PORT dataa (1466:1466:1466) (1594:1594:1594)) + (PORT datab (1469:1469:1469) (1553:1553:1553)) + (PORT datac (1102:1102:1102) (1148:1148:1148)) + (PORT datad (647:647:647) (684:684:684)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -23312,15 +26282,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) (DELAY (ABSOLUTE - (PORT dataa (795:795:795) (815:815:815)) - (PORT datab (2151:2151:2151) (2249:2249:2249)) - (PORT datac (1587:1587:1587) (1632:1632:1632)) - (PORT datad (1778:1778:1778) (1826:1826:1826)) + (PORT dataa (1119:1119:1119) (1156:1156:1156)) + (PORT datab (747:747:747) (772:772:772)) + (PORT datac (1394:1394:1394) (1464:1464:1464)) + (PORT datad (1189:1189:1189) (1225:1225:1225)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (1006:1006:1006)) + (PORT datab (1150:1150:1150) (1220:1220:1220)) + (PORT datac (733:733:733) (829:829:829)) + (PORT datad (1883:1883:1883) (2044:2044:2044)) (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (802:802:802)) + (PORT datab (1392:1392:1392) (1509:1509:1509)) + (PORT datac (1112:1112:1112) (1157:1157:1157)) + (PORT datad (198:198:198) (235:235:235)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -23328,15 +26330,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) (DELAY (ABSOLUTE - (PORT dataa (1545:1545:1545) (1648:1648:1648)) - (PORT datab (346:346:346) (383:383:383)) - (PORT datac (575:575:575) (617:617:617)) - (PORT datad (1068:1068:1068) (1069:1069:1069)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (653:653:653) (668:668:668)) + (PORT datab (819:819:819) (840:840:840)) + (PORT datac (1123:1123:1123) (1137:1137:1137)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (696:696:696)) + (PORT datab (1031:1031:1031) (1083:1083:1083)) + (PORT datac (562:562:562) (584:584:584)) + (PORT datad (901:901:901) (957:957:957)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (741:741:741)) + (PORT datab (618:618:618) (633:633:633)) + (PORT datac (237:237:237) (315:315:315)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1120:1120:1120) (1156:1156:1156)) + (PORT datab (746:746:746) (770:770:770)) + (PORT datac (899:899:899) (956:956:956)) + (PORT datad (1169:1169:1169) (1206:1206:1206)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -23344,15 +26394,173 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) (DELAY (ABSOLUTE - (PORT dataa (1232:1232:1232) (1321:1321:1321)) - (PORT datab (1081:1081:1081) (1100:1100:1100)) - (PORT datac (816:816:816) (843:843:843)) - (PORT datad (1501:1501:1501) (1597:1597:1597)) - (IOPATH dataa combout (341:341:341) (319:319:319)) + (PORT dataa (1433:1433:1433) (1488:1488:1488)) + (PORT datab (677:677:677) (711:711:711)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1402:1402:1402) (1440:1440:1440)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1422:1422:1422) (1463:1463:1463)) + (PORT datab (746:746:746) (770:770:770)) + (PORT datac (1125:1125:1125) (1193:1193:1193)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (496:496:496)) + (PORT datab (268:268:268) (357:357:357)) + (PORT datac (230:230:230) (313:313:313)) + (PORT datad (609:609:609) (655:655:655)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (908:908:908)) + (PORT datab (730:730:730) (816:816:816)) + (PORT datad (395:395:395) (453:453:453)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (513:513:513)) + (PORT datab (390:390:390) (465:465:465)) + (PORT datac (675:675:675) (735:735:735)) + (PORT datad (679:679:679) (752:752:752)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (367:367:367)) + (PORT datab (598:598:598) (665:665:665)) + (PORT datac (245:245:245) (334:334:334)) + (PORT datad (371:371:371) (425:425:425)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (599:599:599)) + (PORT datab (914:914:914) (923:923:923)) + (PORT datac (565:565:565) (580:580:580)) + (PORT datad (307:307:307) (323:323:323)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1424:1424:1424) (1466:1466:1466)) + (PORT datab (1535:1535:1535) (1597:1597:1597)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1559:1559:1559)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1158:1158:1158)) + (PORT datab (675:675:675) (710:710:710)) + (PORT datac (900:900:900) (960:960:960)) + (PORT datad (1167:1167:1167) (1206:1206:1206)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1040:1040:1040)) + (PORT datab (271:271:271) (356:356:356)) + (PORT datac (1122:1122:1122) (1190:1190:1190)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -23360,47 +26568,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) (DELAY (ABSOLUTE (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (541:541:541) (561:561:561)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT datab (746:746:746) (769:769:769)) + (PORT datac (1390:1390:1390) (1425:1425:1425)) + (PORT datad (245:245:245) (316:316:316)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) (DELAY (ABSOLUTE - (PORT dataa (542:542:542) (562:562:562)) - (PORT datab (871:871:871) (931:931:931)) - (PORT datac (878:878:878) (913:913:913)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1518:1518:1518) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1283:1283:1283) (1287:1287:1287)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (1356:1356:1356) (1369:1369:1369)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (200:200:200) (237:237:237)) - (PORT datad (618:618:618) (631:631:631)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -23408,15 +26616,92 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (1085:1085:1085) (1134:1134:1134)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (545:545:545) (570:570:570)) + (PORT datab (213:213:213) (257:257:257)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (813:813:813) (826:826:826)) + (PORT datac (328:328:328) (358:358:358)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (381:381:381)) + (PORT datab (662:662:662) (697:697:697)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1161:1161:1161)) + (PORT datab (1154:1154:1154) (1224:1224:1224)) + (PORT datac (1392:1392:1392) (1427:1427:1427)) + (PORT datad (1169:1169:1169) (1209:1209:1209)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (998:998:998)) + (PORT datab (748:748:748) (772:772:772)) + (PORT datac (646:646:646) (675:675:675)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1374:1374:1374) (1429:1429:1429)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -23424,14 +26709,291 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[0\]\~1) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) (DELAY (ABSOLUTE - (PORT dataa (604:604:604) (640:640:640)) - (PORT datab (257:257:257) (345:345:345)) - (PORT datac (231:231:231) (314:314:314)) - (PORT datad (1113:1113:1113) (1159:1159:1159)) + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (341:341:341) (367:367:367)) + (PORT datac (1214:1214:1214) (1255:1255:1255)) + (PORT datad (677:677:677) (698:698:698)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (946:946:946)) + (PORT datab (2012:2012:2012) (2066:2066:2066)) + (PORT datac (919:919:919) (1015:1015:1015)) + (PORT datad (863:863:863) (877:877:877)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (447:447:447)) + (PORT datab (1195:1195:1195) (1198:1198:1198)) + (PORT datac (601:601:601) (607:607:607)) + (PORT datad (334:334:334) (359:359:359)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (855:855:855)) + (PORT datad (337:337:337) (354:354:354)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (278:278:278)) + (PORT datab (223:223:223) (271:271:271)) + (PORT datac (616:616:616) (645:645:645)) + (PORT datad (216:216:216) (258:258:258)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (621:621:621)) + (PORT datab (686:686:686) (701:701:701)) + (PORT datac (562:562:562) (583:583:583)) + (PORT datad (312:312:312) (322:322:322)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (661:661:661)) + (PORT datab (654:654:654) (674:674:674)) + (PORT datac (240:240:240) (317:317:317)) + (PORT datad (385:385:385) (407:407:407)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (692:692:692)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (610:610:610) (651:651:651)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1244:1244:1244) (1250:1250:1250)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1638:1638:1638) (1703:1703:1703)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (884:884:884) (949:949:949)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (747:747:747)) + (PORT datab (659:659:659) (717:717:717)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1816:1816:1816) (1911:1911:1911)) + (PORT datab (2014:2014:2014) (2068:2068:2068)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|flags_cond_true) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (663:663:663)) + (PORT datab (1772:1772:1772) (1863:1863:1863)) + (PORT datac (1815:1815:1815) (1893:1893:1893)) + (PORT datad (552:552:552) (570:570:570)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (230:230:230) (280:280:280)) + (PORT datac (563:563:563) (592:592:592)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (905:905:905)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (623:623:623) (650:650:650)) + (PORT datad (1193:1193:1193) (1247:1247:1247)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (658:658:658)) + (PORT datab (949:949:949) (994:994:994)) + (PORT datad (671:671:671) (699:699:699)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (694:694:694)) + (PORT datab (517:517:517) (537:537:537)) + (PORT datac (742:742:742) (744:744:744)) + (PORT datad (1107:1107:1107) (1107:1107:1107)) + (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -23440,264 +27002,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (852:852:852) (899:899:899)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (349:349:349) (376:376:376)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1545:1545:1545)) - (PORT asdata (544:544:544) (580:580:580)) - (PORT ena (1737:1737:1737) (1732:1732:1732)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (724:724:724)) - (PORT datab (1065:1065:1065) (1098:1098:1098)) - (PORT datac (1263:1263:1263) (1299:1299:1299)) - (PORT datad (1299:1299:1299) (1342:1342:1342)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (893:893:893)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datad (831:831:831) (833:833:833)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (892:892:892) (941:941:941)) - (PORT datac (578:578:578) (588:588:588)) - (PORT datad (1047:1047:1047) (1075:1075:1075)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (888:888:888)) - (PORT datab (864:864:864) (912:912:912)) - (PORT datac (656:656:656) (697:697:697)) - (PORT datad (1100:1100:1100) (1124:1124:1124)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (879:879:879) (943:943:943)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1118:1118:1118) (1145:1145:1145)) - (PORT datac (915:915:915) (980:980:980)) - (PORT datad (683:683:683) (777:777:777)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1413:1413:1413) (1443:1443:1443)) - (PORT datab (212:212:212) (257:257:257)) - (PORT datac (638:638:638) (679:679:679)) - (PORT datad (1056:1056:1056) (1068:1068:1068)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (816:816:816) (863:863:863)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1241:1241:1241) (1256:1256:1256)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datab (258:258:258) (345:345:345)) - (PORT datac (230:230:230) (313:313:313)) - (PORT datad (576:576:576) (596:596:596)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1149:1149:1149) (1194:1194:1194)) - (PORT datac (349:349:349) (375:375:375)) - (PORT datad (191:191:191) (225:225:225)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (224:224:224) (271:271:271)) - (PORT datac (817:817:817) (835:835:835)) - (PORT datad (570:570:570) (594:594:594)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) - (PORT datab (221:221:221) (267:267:267)) - (PORT datac (311:311:311) (335:335:335)) - (PORT datad (186:186:186) (218:218:218)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (905:905:905)) - (PORT datad (819:819:819) (855:855:855)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (578:578:578)) - (PORT datac (343:343:343) (364:364:364)) - (PORT datad (572:572:572) (594:594:594)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (545:545:545) (573:573:573)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (580:580:580) (606:606:606)) + (PORT datad (621:621:621) (643:643:643)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -23705,103 +27018,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) (DELAY (ABSOLUTE - (PORT dataa (383:383:383) (406:406:406)) - (PORT datab (228:228:228) (268:268:268)) - (PORT datac (186:186:186) (226:226:226)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (580:580:580)) - (PORT datab (371:371:371) (399:399:399)) - (PORT datac (187:187:187) (227:227:227)) - (PORT datad (312:312:312) (329:329:329)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (198:198:198) (242:242:242)) + (PORT datab (259:259:259) (310:310:310)) + (PORT datac (607:607:607) (617:617:617)) + (PORT datad (236:236:236) (276:276:276)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2034:2034:2034) (2049:2049:2049)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT datab (1292:1292:1292) (1323:1323:1323)) - (PORT datac (641:641:641) (682:682:682)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (983:983:983)) - (PORT datab (708:708:708) (787:787:787)) - (PORT datac (668:668:668) (731:731:731)) - (PORT datad (1067:1067:1067) (1080:1080:1080)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1217:1217:1217)) - (PORT datab (1106:1106:1106) (1121:1121:1121)) - (PORT datac (1267:1267:1267) (1309:1309:1309)) - (PORT datad (346:346:346) (366:366:366)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1209:1209:1209) (1217:1217:1217)) + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1881:1881:1881) (1885:1885:1885)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -23813,12 +27050,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1209:1209:1209) (1220:1220:1220)) - (PORT ena (942:942:942) (926:926:926)) + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (1836:1836:1836) (1841:1841:1841)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -23829,43 +27066,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~59) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) (DELAY (ABSOLUTE - (PORT dataa (422:422:422) (468:468:468)) - (PORT datab (438:438:438) (465:465:465)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (959:959:959) (984:984:984)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (1335:1335:1335) (1359:1359:1359)) - (PORT datab (861:861:861) (890:890:890)) - (PORT datad (388:388:388) (410:410:410)) + (PORT dataa (434:434:434) (465:465:465)) + (PORT datab (378:378:378) (448:448:448)) + (PORT datad (608:608:608) (629:629:629)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -23875,116 +27081,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (910:910:910) (930:930:930)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (522:522:522)) - (PORT datab (240:240:240) (321:321:321)) - (PORT datad (665:665:665) (689:689:689)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (906:906:906) (930:930:930)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1253:1253:1253) (1281:1281:1281)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (462:462:462)) - (PORT datab (657:657:657) (679:679:679)) - (PORT datad (631:631:631) (649:649:649)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1459:1459:1459) (1470:1470:1470)) - (PORT ena (962:962:962) (970:970:970)) + (PORT clk (1528:1528:1528) (1544:1544:1544)) + (PORT asdata (1836:1836:1836) (1841:1841:1841)) + (PORT ena (1499:1499:1499) (1507:1507:1507)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -23995,12 +27097,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1456:1456:1456) (1466:1466:1466)) - (PORT ena (979:979:979) (971:971:971)) + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (2122:2122:2122) (2138:2138:2138)) + (PORT ena (1207:1207:1207) (1190:1190:1190)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -24009,44 +27111,13 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (474:474:474)) - (PORT datab (428:428:428) (471:471:471)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (380:380:380) (404:404:404)) - (PORT datac (570:570:570) (578:578:578)) - (PORT datad (605:605:605) (619:619:619)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1705:1705:1705) (1727:1727:1727)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (2124:2124:2124) (2160:2160:2160)) (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -24058,14 +27129,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~15) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) (DELAY (ABSOLUTE - (PORT dataa (1209:1209:1209) (1276:1276:1276)) - (PORT datab (1384:1384:1384) (1452:1452:1452)) - (PORT datad (1859:1859:1859) (1915:1915:1915)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (462:462:462) (498:498:498)) + (PORT datab (667:667:667) (706:706:706)) + (PORT datad (632:632:632) (685:685:685)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24073,38 +27144,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) (DELAY (ABSOLUTE - (PORT datad (940:940:940) (972:972:972)) + (PORT datab (1411:1411:1411) (1423:1423:1423)) + (PORT datad (585:585:585) (594:594:594)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT asdata (1271:1271:1271) (1298:1298:1298)) - (PORT ena (1011:1011:1011) (1021:1021:1021)) + (PORT clk (1528:1528:1528) (1545:1545:1545)) + (PORT asdata (1880:1880:1880) (1884:1884:1884)) + (PORT ena (1220:1220:1220) (1214:1214:1214)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -24115,14 +27173,72 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~58) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) (DELAY (ABSOLUTE - (PORT dataa (382:382:382) (461:461:461)) - (PORT datab (691:691:691) (760:760:760)) - (PORT datad (232:232:232) (270:270:270)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (657:657:657) (709:709:709)) + (PORT datab (945:945:945) (994:994:994)) + (PORT datac (888:888:888) (910:910:910)) + (PORT datad (609:609:609) (625:625:625)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT asdata (1630:1630:1630) (1644:1644:1644)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (823:823:823) (864:864:864)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1266:1266:1266) (1269:1269:1269)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (473:473:473)) + (PORT datab (583:583:583) (621:621:621)) + (PORT datad (584:584:584) (628:628:628)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24130,13 +27246,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~65) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) (DELAY (ABSOLUTE - (PORT dataa (657:657:657) (711:711:711)) - (PORT datab (633:633:633) (654:654:654)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (329:329:329) (347:347:347)) + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (551:551:551) (556:556:556)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -24146,47 +27262,475 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~66) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (627:627:627)) - (PORT datab (602:602:602) (637:637:637)) - (PORT datac (1952:1952:1952) (2065:2065:2065)) - (PORT datad (568:568:568) (590:590:590)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (1532:1532:1532) (1549:1549:1549)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~11) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT dataa (1034:1034:1034) (1047:1047:1047)) - (PORT datab (1335:1335:1335) (1323:1323:1323)) - (PORT datac (1088:1088:1088) (1082:1082:1082)) - (PORT datad (1019:1019:1019) (1010:1010:1010)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1413:1413:1413) (1385:1385:1385)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1857:1857:1857) (1863:1863:1863)) + (PORT ena (1734:1734:1734) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~12) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (381:381:381)) - (PORT datab (252:252:252) (310:310:310)) - (PORT datac (1107:1107:1107) (1120:1120:1120)) - (PORT datad (845:845:845) (862:862:862)) + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (962:962:962) (1016:1016:1016)) + (PORT datad (847:847:847) (873:873:873)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (712:712:712) (740:740:740)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (712:712:712) (740:740:740)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (329:329:329)) + (PORT datab (263:263:263) (316:316:316)) + (PORT datad (234:234:234) (273:273:273)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (726:726:726)) + (PORT datab (635:635:635) (674:674:674)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1349:1349:1349) (1373:1373:1373)) + (PORT datab (623:623:623) (653:653:653)) + (PORT datac (643:643:643) (694:694:694)) + (PORT datad (308:308:308) (323:323:323)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1481:1481:1481) (1531:1531:1531)) + (PORT datab (1644:1644:1644) (1715:1715:1715)) + (PORT datac (1522:1522:1522) (1538:1538:1538)) + (PORT datad (1165:1165:1165) (1205:1205:1205)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (996:996:996)) + (PORT datab (878:878:878) (913:913:913)) + (PORT datac (923:923:923) (978:978:978)) + (PORT datad (879:879:879) (914:914:914)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (696:696:696) (721:721:721)) + (PORT datab (1150:1150:1150) (1186:1186:1186)) + (PORT datac (887:887:887) (975:975:975)) + (PORT datad (1184:1184:1184) (1219:1219:1219)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (943:943:943) (996:996:996)) + (PORT datac (648:648:648) (674:674:674)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1352:1352:1352)) + (PORT datab (933:933:933) (975:975:975)) + (PORT datac (1446:1446:1446) (1491:1491:1491)) + (PORT datad (926:926:926) (983:983:983)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (248:248:248)) + (PORT datab (986:986:986) (1033:1033:1033)) + (PORT datac (900:900:900) (933:933:933)) + (PORT datad (222:222:222) (267:267:267)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1695:1695:1695) (1783:1783:1783)) + (PORT datac (897:897:897) (925:925:925)) + (PORT datad (364:364:364) (385:385:385)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (926:926:926) (952:952:952)) + (PORT datad (237:237:237) (274:274:274)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1212:1212:1212)) + (PORT datab (286:286:286) (347:347:347)) + (PORT datac (254:254:254) (311:311:311)) + (PORT datad (254:254:254) (300:300:300)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (432:432:432) (525:525:525)) + (PORT datab (1170:1170:1170) (1217:1217:1217)) + (PORT datac (1156:1156:1156) (1212:1212:1212)) + (PORT datad (661:661:661) (724:724:724)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1535:1535:1535)) + (PORT asdata (672:672:672) (698:698:698)) + (PORT ena (1283:1283:1283) (1287:1287:1287)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (638:638:638)) + (PORT datab (368:368:368) (389:389:389)) + (PORT datad (1139:1139:1139) (1146:1146:1146)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (597:597:597)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (1124:1124:1124) (1146:1146:1146)) + (PORT datad (335:335:335) (355:355:355)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1345:1345:1345)) + (PORT datab (915:915:915) (937:937:937)) + (PORT datac (1123:1123:1123) (1144:1144:1144)) + (PORT datad (945:945:945) (995:995:995)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (964:964:964) (1020:1020:1020)) + (PORT datac (806:806:806) (813:813:813)) + (PORT datad (227:227:227) (273:273:273)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (999:999:999)) + (PORT datac (1663:1663:1663) (1739:1739:1739)) + (PORT datad (1415:1415:1415) (1442:1442:1442)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datac (902:902:902) (931:931:931)) + (PORT datad (239:239:239) (281:281:281)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1211:1211:1211)) + (PORT datab (286:286:286) (349:349:349)) + (PORT datac (255:255:255) (313:313:313)) + (PORT datad (248:248:248) (293:293:293)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (728:728:728)) + (PORT datab (1171:1171:1171) (1217:1217:1217)) + (PORT datac (615:615:615) (673:673:673)) + (PORT datad (661:661:661) (723:723:723)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1535:1535:1535)) + (PORT asdata (1127:1127:1127) (1132:1132:1132)) + (PORT ena (1283:1283:1283) (1287:1287:1287)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (578:578:578)) + (PORT datab (331:331:331) (362:362:362)) + (PORT datad (1138:1138:1138) (1145:1145:1145)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (703:703:703)) + (PORT datab (359:359:359) (389:389:389)) + (PORT datac (797:797:797) (800:800:800)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24194,29 +27738,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~5) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (1230:1230:1230) (1328:1328:1328)) - (PORT datab (899:899:899) (920:920:920)) - (PORT datac (671:671:671) (707:707:707)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (904:904:904)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1497:1497:1497) (1599:1599:1599)) - (PORT datad (1296:1296:1296) (1331:1331:1331)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (588:588:588) (619:619:619)) + (PORT datab (968:968:968) (1015:1015:1015)) + (PORT datac (371:371:371) (403:403:403)) + (PORT datad (863:863:863) (917:917:917)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24224,55 +27754,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~9) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) (DELAY (ABSOLUTE - (PORT dataa (632:632:632) (694:694:694)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (530:530:530) (546:546:546)) - (PORT datad (831:831:831) (855:855:855)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (911:911:911) (951:951:951)) - (PORT datac (601:601:601) (631:631:631)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1171:1171:1171)) - (PORT datab (641:641:641) (685:685:685)) - (PORT datac (796:796:796) (800:800:800)) - (PORT datad (822:822:822) (845:845:845)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (883:883:883) (950:950:950)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (681:681:681) (721:721:721)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24280,10 +27766,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) + (INSTANCE z80_\|alu_\|op1_low\[1\]) (DELAY (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) + (PORT clk (1530:1530:1530) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) (PORT ena (790:790:790) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -24299,40 +27785,65 @@ (INSTANCE z80_\|alu_control_\|out\[6\]\~0) (DELAY (ABSOLUTE - (PORT datab (261:261:261) (341:341:341)) - (PORT datac (243:243:243) (321:321:321)) + (PORT datab (264:264:264) (346:346:346)) + (PORT datac (235:235:235) (311:311:311)) (PORT datad (235:235:235) (303:303:303)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) (DELAY (ABSOLUTE - (PORT dataa (1199:1199:1199) (1324:1324:1324)) - (PORT datab (1140:1140:1140) (1190:1190:1190)) - (PORT datac (1052:1052:1052) (1072:1072:1072)) - (PORT datad (1114:1114:1114) (1181:1181:1181)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT datac (852:852:852) (861:861:861)) + (PORT datad (679:679:679) (700:700:700)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (732:732:732)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datad (621:621:621) (632:632:632)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~19) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (327:327:327)) - (PORT datab (645:645:645) (709:709:709)) - (PORT datac (1310:1310:1310) (1345:1345:1345)) - (PORT datad (556:556:556) (578:578:578)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1231:1231:1231)) + (PORT datab (681:681:681) (697:697:697)) + (PORT datac (1123:1123:1123) (1203:1203:1203)) + (PORT datad (667:667:667) (721:721:721)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -24342,13 +27853,139 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (1694:1694:1694) (1713:1713:1713)) - (PORT datab (869:869:869) (906:906:906)) - (PORT datac (1069:1069:1069) (1103:1103:1103)) - (PORT datad (1032:1032:1032) (1064:1064:1064)) + (PORT dataa (1196:1196:1196) (1252:1252:1252)) + (PORT datab (1640:1640:1640) (1708:1708:1708)) + (PORT datac (1440:1440:1440) (1482:1482:1482)) + (PORT datad (844:844:844) (890:890:890)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (686:686:686)) + (PORT datab (928:928:928) (956:956:956)) + (PORT datac (630:630:630) (688:688:688)) + (PORT datad (848:848:848) (847:847:847)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (856:856:856)) + (PORT datab (904:904:904) (946:946:946)) + (PORT datac (412:412:412) (479:479:479)) + (PORT datad (832:832:832) (862:862:862)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (712:712:712)) + (PORT datab (943:943:943) (996:996:996)) + (PORT datac (576:576:576) (598:598:598)) + (PORT datad (316:316:316) (337:337:337)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1305:1305:1305) (1357:1357:1357)) + (PORT datab (967:967:967) (1024:1024:1024)) + (PORT datac (922:922:922) (952:952:952)) + (PORT datad (1557:1557:1557) (1610:1610:1610)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (642:642:642)) + (PORT datab (987:987:987) (1034:1034:1034)) + (PORT datac (175:175:175) (210:210:210)) + (PORT datad (221:221:221) (266:266:266)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1693:1693:1693) (1778:1778:1778)) + (PORT datab (916:916:916) (942:942:942)) + (PORT datac (904:904:904) (929:929:929)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1446:1446:1446) (1487:1487:1487)) + (PORT datab (1129:1129:1129) (1183:1183:1183)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (234:234:234) (275:275:275)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (274:274:274)) + (PORT datab (246:246:246) (301:301:301)) + (PORT datac (617:617:617) (647:647:647)) + (PORT datad (845:845:845) (875:875:875)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -24358,5215 +27995,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~23) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) (DELAY (ABSOLUTE - (PORT dataa (920:920:920) (977:977:977)) - (PORT datab (825:825:825) (823:823:823)) - (PORT datac (1582:1582:1582) (1644:1644:1644)) - (PORT datad (631:631:631) (666:666:666)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (549:549:549) (580:580:580)) + (PORT datab (714:714:714) (753:753:753)) + (PORT datac (601:601:601) (608:608:608)) + (PORT datad (865:865:865) (915:915:915)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (718:718:718)) + (PORT datab (1128:1128:1128) (1175:1175:1175)) + (PORT datac (587:587:587) (617:617:617)) + (PORT datad (401:401:401) (459:459:459)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~24) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~1) (DELAY (ABSOLUTE - (PORT dataa (842:842:842) (859:859:859)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (1136:1136:1136) (1151:1151:1151)) + (PORT dataa (261:261:261) (336:336:336)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (559:559:559) (578:578:578)) + (PORT datad (903:903:903) (954:954:954)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (550:550:550) (568:568:568)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1255:1255:1255) (1269:1269:1269)) - (PORT datad (670:670:670) (691:691:691)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (208:208:208) (241:241:241)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (628:628:628)) - (PORT datab (261:261:261) (314:314:314)) - (PORT datad (1139:1139:1139) (1169:1169:1169)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (621:621:621) (646:646:646)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1450:1450:1450) (1505:1505:1505)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (937:937:937) (960:960:960)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (274:274:274) (344:344:344)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (585:585:585) (609:609:609)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (977:977:977) (1007:1007:1007)) - (PORT ena (1447:1447:1447) (1426:1426:1426)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (383:383:383)) - (PORT datad (632:632:632) (654:654:654)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1386:1386:1386) (1434:1434:1434)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1384:1384:1384) (1436:1436:1436)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (694:694:694)) - (PORT datab (241:241:241) (324:324:324)) - (PORT datad (850:850:850) (903:903:903)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (986:986:986) (1016:1016:1016)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (986:986:986) (1016:1016:1016)) - (PORT ena (1472:1472:1472) (1481:1481:1481)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (280:280:280) (343:343:343)) - (PORT datab (701:701:701) (738:738:738)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (641:641:641)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (627:627:627) (643:643:643)) - (PORT datad (305:305:305) (321:321:321)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1478:1478:1478) (1511:1511:1511)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1473:1473:1473) (1506:1506:1506)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (427:427:427) (490:490:490)) - (PORT datab (696:696:696) (732:732:732)) - (PORT datad (659:659:659) (676:676:676)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1248:1248:1248) (1264:1264:1264)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1252:1252:1252) (1268:1268:1268)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (774:774:774)) - (PORT datab (709:709:709) (762:762:762)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (874:874:874)) - (PORT datab (634:634:634) (660:660:660)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (866:866:866)) - (PORT datab (866:866:866) (899:899:899)) - (PORT datac (1506:1506:1506) (1607:1607:1607)) - (PORT datad (840:840:840) (838:838:838)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (708:708:708) (742:742:742)) - (PORT ena (983:983:983) (976:976:976)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1248:1248:1248) (1270:1270:1270)) - (PORT datab (1220:1220:1220) (1233:1233:1233)) - (PORT datad (397:397:397) (430:430:430)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datac (449:449:449) (487:487:487)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (906:906:906)) - (PORT datab (1448:1448:1448) (1568:1568:1568)) - (PORT datac (578:578:578) (601:601:601)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (890:890:890)) - (PORT datad (1216:1216:1216) (1314:1314:1314)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (181:181:181) (209:209:209)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1564:1564:1564)) - (PORT ena (2593:2593:2593) (2662:2662:2662)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datac (1019:1019:1019) (1059:1059:1059)) - (PORT datad (813:813:813) (852:852:852)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1291:1291:1291) (1308:1308:1308)) - (PORT datab (1274:1274:1274) (1276:1276:1276)) - (PORT datac (1361:1361:1361) (1410:1410:1410)) - (PORT datad (1277:1277:1277) (1313:1313:1313)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1021:1021:1021) (1037:1037:1037)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1527:1527:1527) (1548:1548:1548)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1527:1527:1527) (1547:1547:1547)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (459:459:459)) - (PORT datab (702:702:702) (734:734:734)) - (PORT datad (662:662:662) (679:679:679)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1226:1226:1226) (1246:1246:1246)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1229:1229:1229) (1249:1249:1249)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (332:332:332)) - (PORT datab (704:704:704) (754:754:754)) - (PORT datad (682:682:682) (728:728:728)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1640:1640:1640) (1677:1677:1677)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1637:1637:1637) (1675:1675:1675)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (697:697:697)) - (PORT datab (872:872:872) (936:936:936)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (537:537:537) (567:567:567)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (626:626:626)) - (PORT datab (642:642:642) (663:663:663)) - (PORT datad (233:233:233) (272:272:272)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (926:926:926) (946:946:946)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (926:926:926) (947:947:947)) - (PORT ena (1472:1472:1472) (1481:1481:1481)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (281:281:281) (346:346:346)) - (PORT datab (701:701:701) (738:738:738)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (943:943:943) (961:961:961)) - (PORT ena (1450:1450:1450) (1505:1505:1505)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (945:945:945) (963:963:963)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (349:349:349)) - (PORT datab (243:243:243) (324:324:324)) - (PORT datad (581:581:581) (608:608:608)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1543:1543:1543)) - (PORT asdata (1615:1615:1615) (1650:1650:1650)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT datab (369:369:369) (407:407:407)) - (PORT datad (217:217:217) (253:253:253)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (777:777:777) (846:846:846)) - (PORT datab (375:375:375) (400:400:400)) - (PORT datac (533:533:533) (549:549:549)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (865:865:865)) - (PORT datac (815:815:815) (815:815:815)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1536:1536:1536) (1645:1645:1645)) - (PORT datab (807:807:807) (836:836:836)) - (PORT datac (813:813:813) (827:827:827)) - (PORT datad (314:314:314) (324:324:324)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (538:538:538) (568:568:568)) - (PORT ena (983:983:983) (976:976:976)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1274:1274:1274)) - (PORT datab (1411:1411:1411) (1449:1449:1449)) - (PORT datad (396:396:396) (430:430:430)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (420:420:420) (500:500:500)) - (PORT datac (448:448:448) (484:484:484)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (268:268:268)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (632:632:632) (698:698:698)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (640:640:640) (681:681:681)) - (PORT datac (582:582:582) (597:597:597)) - (PORT datad (1422:1422:1422) (1523:1523:1523)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT datac (1493:1493:1493) (1574:1574:1574)) - (PORT datad (634:634:634) (649:649:649)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1547:1547:1547)) - (PORT ena (2452:2452:2452) (2480:2480:2480)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1308:1308:1308)) - (PORT datab (1275:1275:1275) (1277:1277:1277)) - (PORT datac (632:632:632) (697:697:697)) - (PORT datad (1277:1277:1277) (1313:1313:1313)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT datac (1492:1492:1492) (1575:1575:1575)) - (PORT datad (597:597:597) (613:613:613)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1547:1547:1547)) - (PORT ena (2452:2452:2452) (2480:2480:2480)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1317:1317:1317) (1359:1359:1359)) - (PORT datab (1272:1272:1272) (1275:1275:1275)) - (PORT datac (1255:1255:1255) (1271:1271:1271)) - (PORT datad (687:687:687) (748:748:748)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (269:269:269)) - (PORT datab (207:207:207) (250:250:250)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (956:956:956)) - (PORT datac (857:857:857) (988:988:988)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1021:1021:1021) (1037:1037:1037)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (537:537:537) (567:567:567)) - (PORT ena (983:983:983) (976:976:976)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1271:1271:1271)) - (PORT datab (1059:1059:1059) (1102:1102:1102)) - (PORT datad (396:396:396) (427:427:427)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (500:500:500)) - (PORT datac (448:448:448) (485:485:485)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (846:846:846)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (577:577:577) (601:601:601)) - (PORT datad (1420:1420:1420) (1528:1528:1528)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (691:691:691) (721:721:721)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (691:691:691) (718:718:718)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (458:458:458)) - (PORT datab (709:709:709) (762:762:762)) - (PORT datad (681:681:681) (733:733:733)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1403:1403:1403) (1428:1428:1428)) - (PORT datab (911:911:911) (951:951:951)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1191:1191:1191) (1214:1214:1214)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (1191:1191:1191) (1217:1217:1217)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (464:464:464)) - (PORT datab (696:696:696) (739:739:739)) - (PORT datad (658:658:658) (684:684:684)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1894:1894:1894) (1950:1950:1950)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (1191:1191:1191) (1205:1205:1205)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1896:1896:1896) (1952:1952:1952)) - (PORT ena (1472:1472:1472) (1481:1481:1481)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (687:687:687)) - (PORT datab (701:701:701) (738:738:738)) - (PORT datad (628:628:628) (654:654:654)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (283:283:283) (348:348:348)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (1406:1406:1406) (1420:1420:1420)) - (PORT ena (1450:1450:1450) (1505:1505:1505)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (1408:1408:1408) (1420:1420:1420)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (276:276:276) (349:349:349)) - (PORT datab (242:242:242) (323:323:323)) - (PORT datad (581:581:581) (608:608:608)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1211:1211:1211) (1188:1188:1188)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (944:944:944) (958:958:958)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (946:946:946) (960:960:960)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (698:698:698)) - (PORT datab (875:875:875) (937:937:937)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (632:632:632)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datac (346:346:346) (370:370:370)) - (PORT datad (821:821:821) (828:828:828)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (367:367:367)) - (PORT datab (650:650:650) (666:666:666)) - (PORT datac (598:598:598) (605:605:605)) - (PORT datad (171:171:171) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (411:411:411)) - (PORT datab (926:926:926) (946:946:946)) - (PORT datac (1242:1242:1242) (1334:1334:1334)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (601:601:601)) - (PORT datab (908:908:908) (946:946:946)) - (PORT datac (866:866:866) (891:891:891)) - (PORT datad (622:622:622) (645:645:645)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1608:1608:1608) (1681:1681:1681)) - (PORT datad (335:335:335) (359:359:359)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (742:742:742)) - (PORT datab (631:631:631) (649:649:649)) - (PORT datac (318:318:318) (348:348:348)) - (PORT datad (211:211:211) (245:245:245)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1115:1115:1115) (1153:1153:1153)) - (PORT datab (680:680:680) (703:703:703)) - (PORT datac (887:887:887) (911:911:911)) - (PORT datad (1148:1148:1148) (1170:1170:1170)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (254:254:254) (312:312:312)) - (PORT datac (1316:1316:1316) (1367:1367:1367)) - (PORT datad (844:844:844) (863:863:863)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (957:957:957)) - (PORT datab (701:701:701) (737:737:737)) - (PORT datac (1183:1183:1183) (1279:1279:1279)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (353:353:353) (383:383:383)) - (PORT datac (1397:1397:1397) (1462:1462:1462)) - (PORT datad (570:570:570) (584:584:584)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (615:615:615) (665:665:665)) - (PORT datac (1282:1282:1282) (1326:1326:1326)) - (PORT datad (597:597:597) (614:614:614)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (559:559:559) (584:584:584)) - (PORT datad (833:833:833) (857:857:857)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (889:889:889)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (631:631:631) (656:656:656)) - (PORT datad (878:878:878) (943:943:943)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1337:1337:1337)) - (PORT datab (1262:1262:1262) (1312:1312:1312)) - (PORT datac (247:247:247) (327:327:327)) - (PORT datad (248:248:248) (320:320:320)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (408:408:408)) - (PORT datab (887:887:887) (949:949:949)) - (PORT datac (1117:1117:1117) (1135:1135:1135)) - (PORT datad (1141:1141:1141) (1193:1193:1193)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (802:802:802)) - (PORT datab (706:706:706) (778:778:778)) - (PORT datac (813:813:813) (872:872:872)) - (PORT datad (864:864:864) (895:895:895)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (253:253:253)) - (PORT datab (228:228:228) (268:268:268)) - (PORT datac (316:316:316) (340:340:340)) - (PORT datad (189:189:189) (219:219:219)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (613:613:613)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (169:169:169) (202:202:202)) - (PORT datad (575:575:575) (584:584:584)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2034:2034:2034) (2049:2049:2049)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (983:983:983)) - (PORT datab (726:726:726) (806:806:806)) - (PORT datac (692:692:692) (769:769:769)) - (PORT datad (1067:1067:1067) (1080:1080:1080)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (689:689:689)) - (PORT datab (668:668:668) (729:729:729)) - (PORT datac (541:541:541) (565:565:565)) - (PORT datad (596:596:596) (609:609:609)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (658:658:658)) - (PORT datab (554:554:554) (576:576:576)) - (PORT datad (2091:2091:2091) (2174:2174:2174)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (607:607:607)) - (PORT datac (1366:1366:1366) (1433:1433:1433)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (606:606:606)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (998:998:998) (1028:1028:1028)) - (PORT datad (846:846:846) (862:862:862)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (709:709:709)) - (PORT datab (910:910:910) (948:948:948)) - (PORT datac (599:599:599) (629:629:629)) - (PORT datad (898:898:898) (951:951:951)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (905:905:905)) - (PORT datab (670:670:670) (700:700:700)) - (PORT datac (667:667:667) (722:722:722)) - (PORT datad (606:606:606) (633:633:633)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) - (DELAY - (ABSOLUTE - (PORT datac (669:669:669) (697:697:697)) - (PORT datad (216:216:216) (242:242:242)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (538:538:538) (556:556:556)) - (PORT datad (326:326:326) (349:349:349)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1626:1626:1626) (1670:1670:1670)) - (PORT datab (916:916:916) (984:984:984)) - (PORT datac (1201:1201:1201) (1290:1290:1290)) - (PORT datad (768:768:768) (777:777:777)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (473:473:473)) - (PORT datab (669:669:669) (718:718:718)) - (PORT datac (611:611:611) (625:625:625)) - (PORT datad (816:816:816) (864:864:864)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (607:607:607)) - (PORT datab (1060:1060:1060) (1078:1078:1078)) - (PORT datac (1045:1045:1045) (1063:1063:1063)) - (PORT datad (554:554:554) (572:572:572)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (262:262:262) (348:348:348)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (237:237:237) (313:313:313)) - (PORT datad (241:241:241) (312:312:312)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (718:718:718)) - (PORT datab (871:871:871) (886:886:886)) - (PORT datac (243:243:243) (323:323:323)) - (PORT datad (681:681:681) (774:774:774)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1340:1340:1340) (1402:1402:1402)) - (PORT datab (693:693:693) (788:788:788)) - (PORT datac (629:629:629) (675:675:675)) - (PORT datad (607:607:607) (652:652:652)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (865:865:865) (893:893:893)) - (PORT datad (619:619:619) (667:667:667)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1317:1317:1317)) - (PORT datab (845:845:845) (874:874:874)) - (PORT datac (315:315:315) (336:336:336)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1039:1039:1039)) - (PORT datab (854:854:854) (909:909:909)) - (PORT datac (1493:1493:1493) (1576:1576:1576)) - (PORT datad (2057:2057:2057) (2140:2140:2140)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (413:413:413)) - (PORT datab (683:683:683) (720:720:720)) - (PORT datac (191:191:191) (224:224:224)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (370:370:370)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1005:1005:1005) (1014:1014:1014)) - (PORT datad (182:182:182) (213:213:213)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1044:1044:1044) (1077:1077:1077)) - (PORT datab (1091:1091:1091) (1099:1099:1099)) - (PORT datac (614:614:614) (631:631:631)) - (PORT datad (218:218:218) (253:253:253)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (639:639:639)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (175:175:175) (208:208:208)) - (PORT datad (638:638:638) (663:663:663)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1154:1154:1154)) - (PORT datab (1186:1186:1186) (1208:1208:1208)) - (PORT datac (812:812:812) (859:859:859)) - (PORT datad (839:839:839) (882:882:882)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (919:919:919)) - (PORT datab (876:876:876) (899:899:899)) - (PORT datac (355:355:355) (384:384:384)) - (PORT datad (229:229:229) (274:274:274)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1322:1322:1322)) - (PORT datab (704:704:704) (739:739:739)) - (PORT datac (855:855:855) (907:907:907)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1368:1368:1368)) - (PORT datab (951:951:951) (969:969:969)) - (PORT datac (1419:1419:1419) (1506:1506:1506)) - (PORT datad (334:334:334) (352:352:352)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1119:1119:1119) (1183:1183:1183)) - (PORT datac (599:599:599) (629:629:629)) - (PORT datad (883:883:883) (909:909:909)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1169:1169:1169) (1238:1238:1238)) - (PORT datab (690:690:690) (719:719:719)) - (PORT datac (1120:1120:1120) (1138:1138:1138)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1117:1117:1117)) - (PORT datab (730:730:730) (810:810:810)) - (PORT datac (640:640:640) (708:708:708)) - (PORT datad (881:881:881) (924:924:924)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1219:1219:1219)) - (PORT datab (1097:1097:1097) (1113:1113:1113)) - (PORT datac (1267:1267:1267) (1306:1306:1306)) - (PORT datad (335:335:335) (355:355:355)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (498:498:498) (507:507:507)) - (PORT datad (837:837:837) (862:862:862)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1171:1171:1171)) - (PORT datab (670:670:670) (703:703:703)) - (PORT datac (642:642:642) (676:676:676)) - (PORT datad (877:877:877) (942:942:942)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1543:1543:1543) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1401:1401:1401) (1436:1436:1436)) - (PORT datab (734:734:734) (817:817:817)) - (PORT datac (671:671:671) (744:744:744)) - (PORT datad (1015:1015:1015) (1059:1059:1059)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (651:651:651)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (1116:1116:1116) (1131:1131:1131)) - (PORT datad (1142:1142:1142) (1189:1189:1189)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|alu_\|op2_low\[2\]) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) + (PORT clk (1529:1529:1529) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (765:765:765)) - (PORT datab (841:841:841) (900:900:900)) - (PORT datac (637:637:637) (704:704:704)) - (PORT datad (863:863:863) (891:891:891)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (699:699:699) (774:774:774)) - (PORT datac (1370:1370:1370) (1395:1395:1395)) - (PORT datad (706:706:706) (777:777:777)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (401:401:401)) - (PORT datab (220:220:220) (266:266:266)) - (PORT datac (186:186:186) (224:224:224)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (404:404:404)) - (PORT datab (222:222:222) (269:269:269)) - (PORT datac (327:327:327) (352:352:352)) - (PORT datad (208:208:208) (239:239:239)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (827:827:827)) - (PORT datab (379:379:379) (412:412:412)) - (PORT datac (385:385:385) (431:431:431)) - (PORT datad (828:828:828) (829:829:829)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1057:1057:1057)) - (PORT datab (923:923:923) (992:992:992)) - (PORT datac (1097:1097:1097) (1141:1141:1141)) - (PORT datad (1315:1315:1315) (1341:1341:1341)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1059:1059:1059) (1111:1111:1111)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1309:1309:1309) (1382:1382:1382)) - (PORT datad (1071:1071:1071) (1084:1084:1084)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (623:623:623) (647:647:647)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1313:1313:1313)) - (PORT datab (880:880:880) (933:933:933)) - (PORT datac (1111:1111:1111) (1131:1131:1131)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1495:1495:1495)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (802:802:802) (805:805:805)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1498:1498:1498)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (603:603:603) (632:632:632)) - (PORT datad (894:894:894) (957:957:957)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (924:924:924) (998:998:998)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (914:914:914)) - (PORT datab (1140:1140:1140) (1155:1155:1155)) - (PORT datac (242:242:242) (322:322:322)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1082:1082:1082)) - (PORT datab (1004:1004:1004) (1075:1075:1075)) - (PORT datac (2234:2234:2234) (2300:2300:2300)) - (PORT datad (579:579:579) (616:616:616)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1272:1272:1272) (1273:1273:1273)) - (PORT datab (1249:1249:1249) (1339:1339:1339)) - (PORT datac (1511:1511:1511) (1599:1599:1599)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1520:1520:1520) (1576:1576:1576)) - (PORT datab (587:587:587) (613:613:613)) - (PORT datac (1428:1428:1428) (1442:1442:1442)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (380:380:380)) - (PORT datab (238:238:238) (283:283:283)) - (PORT datac (365:365:365) (388:388:388)) - (PORT datad (309:309:309) (325:325:325)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (670:670:670)) - (PORT datab (256:256:256) (308:308:308)) - (PORT datac (785:785:785) (803:803:803)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (675:675:675)) - (PORT datab (870:870:870) (878:878:878)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1092:1092:1092) (1131:1131:1131)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (733:733:733)) - (PORT datab (1205:1205:1205) (1231:1231:1231)) - (PORT datac (1352:1352:1352) (1391:1391:1391)) - (PORT datad (1717:1717:1717) (1758:1758:1758)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1506:1506:1506) (1560:1560:1560)) - (PORT datab (1446:1446:1446) (1461:1461:1461)) - (PORT datac (1144:1144:1144) (1188:1188:1188)) - (PORT datad (1462:1462:1462) (1558:1558:1558)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1422:1422:1422)) - (PORT datab (2164:2164:2164) (2264:2264:2264)) - (PORT datac (1307:1307:1307) (1351:1351:1351)) - (PORT datad (1411:1411:1411) (1421:1421:1421)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (263:263:263) (345:345:345)) - (PORT datac (978:978:978) (982:982:982)) - (PORT datad (590:590:590) (605:605:605)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (936:936:936)) - (PORT datab (1207:1207:1207) (1229:1229:1229)) - (PORT datac (615:615:615) (672:672:672)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1208:1208:1208)) - (PORT datab (1447:1447:1447) (1536:1536:1536)) - (PORT datac (788:788:788) (797:797:797)) - (PORT datad (1166:1166:1166) (1255:1255:1255)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (2422:2422:2422) (2510:2510:2510)) - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1119:1119:1119) (1176:1176:1176)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (935:935:935)) - (PORT datab (653:653:653) (708:708:708)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (808:808:808) (836:836:836)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (565:565:565)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (791:791:791) (829:829:829)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (744:744:744)) - (PORT datab (1407:1407:1407) (1399:1399:1399)) - (PORT datac (1258:1258:1258) (1274:1274:1274)) - (PORT datad (587:587:587) (605:605:605)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (555:555:555) (557:557:557)) - (PORT datad (626:626:626) (649:649:649)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (658:658:658)) - (PORT datab (909:909:909) (947:947:947)) - (PORT datac (866:866:866) (871:871:871)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (921:921:921)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1609:1609:1609) (1684:1684:1684)) - (PORT datad (616:616:616) (639:639:639)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (930:930:930) (949:949:949)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (277:277:277) (352:352:352)) - (PORT datab (1032:1032:1032) (1071:1071:1071)) - (PORT datad (812:812:812) (835:835:835)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (998:998:998) (1014:1014:1014)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (998:998:998) (1014:1014:1014)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (690:690:690)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (854:854:854) (900:900:900)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (972:972:972) (984:984:984)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (930:930:930) (949:949:949)) - (PORT ena (1472:1472:1472) (1481:1481:1481)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (704:704:704)) - (PORT datab (699:699:699) (744:744:744)) - (PORT datad (627:627:627) (656:656:656)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (555:555:555) (568:568:568)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1450:1450:1450) (1505:1505:1505)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (930:930:930) (946:946:946)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (341:341:341)) - (PORT datab (673:673:673) (741:741:741)) - (PORT datad (578:578:578) (595:595:595)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1447:1447:1447) (1426:1426:1426)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (698:698:698)) - (PORT datab (372:372:372) (394:394:394)) - (PORT datac (303:303:303) (325:325:325)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (867:867:867)) - (PORT datab (338:338:338) (372:372:372)) - (PORT datac (597:597:597) (618:618:618)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (1042:1042:1042) (1068:1068:1068)) - (PORT datac (564:564:564) (581:581:581)) - (PORT datad (1831:1831:1831) (1943:1943:1943)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (535:535:535) (566:566:566)) - (PORT ena (983:983:983) (976:976:976)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1268:1268:1268)) - (PORT datab (898:898:898) (922:922:922)) - (PORT datad (401:401:401) (427:427:427)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (421:421:421) (504:504:504)) - (PORT datac (447:447:447) (483:483:483)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (689:689:689)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (579:579:579) (597:597:597)) - (PORT datad (1422:1422:1422) (1524:1524:1524)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1646:1646:1646)) - (PORT datac (624:624:624) (647:647:647)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1547:1547:1547)) - (PORT ena (2484:2484:2484) (2511:2511:2511)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (270:270:270)) - (PORT datab (1120:1120:1120) (1163:1163:1163)) - (PORT datac (701:701:701) (759:759:759)) - (PORT datad (1064:1064:1064) (1090:1090:1090)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (811:811:811)) - (PORT datab (819:819:819) (831:831:831)) - (PORT datac (724:724:724) (731:731:731)) - (PORT datad (190:190:190) (223:223:223)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (187:187:187) (230:230:230)) - (PORT datad (689:689:689) (751:751:751)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (333:333:333) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (640:640:640)) - (PORT datab (1448:1448:1448) (1569:1569:1569)) - (PORT datac (594:594:594) (617:617:617)) - (PORT datad (620:620:620) (655:655:655)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1480:1480:1480) (1490:1490:1490)) - (PORT ena (1265:1265:1265) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (1483:1483:1483) (1494:1494:1494)) - (PORT ena (1430:1430:1430) (1423:1423:1423)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (689:689:689)) - (PORT datab (882:882:882) (945:945:945)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (1693:1693:1693) (1706:1706:1706)) - (PORT ena (1258:1258:1258) (1246:1246:1246)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1543:1543:1543)) - (PORT asdata (1495:1495:1495) (1523:1523:1523)) - (PORT ena (1455:1455:1455) (1491:1491:1491)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (674:674:674)) - (PORT datab (420:420:420) (486:486:486)) - (PORT datad (584:584:584) (601:601:601)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1547:1547:1547)) - (PORT asdata (1513:1513:1513) (1527:1527:1527)) - (PORT ena (1205:1205:1205) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (276:276:276) (351:351:351)) - (PORT datab (841:841:841) (888:888:888)) - (PORT datad (812:812:812) (835:835:835)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1543:1543:1543)) - (PORT asdata (1495:1495:1495) (1522:1522:1522)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (433:433:433)) - (PORT datad (215:215:215) (248:248:248)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (221:221:221)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1475:1475:1475) (1471:1471:1471)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1543:1543:1543)) - (PORT asdata (1694:1694:1694) (1707:1707:1707)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1170:1170:1170)) - (PORT datab (902:902:902) (919:919:919)) - (PORT datad (234:234:234) (269:269:269)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (857:857:857)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (316:316:316) (335:335:335)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (955:955:955) (984:984:984)) - (PORT ena (1206:1206:1206) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1549:1549:1549)) - (PORT asdata (955:955:955) (984:984:984)) - (PORT ena (1202:1202:1202) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (733:733:733)) - (PORT datab (698:698:698) (738:738:738)) - (PORT datad (659:659:659) (682:682:682)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1253:1253:1253) (1283:1283:1283)) - (PORT ena (1208:1208:1208) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1549:1549:1549)) - (PORT asdata (1250:1250:1250) (1280:1280:1280)) - (PORT ena (1304:1304:1304) (1321:1321:1321)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (706:706:706) (758:758:758)) - (PORT datad (682:682:682) (733:733:733)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (869:869:869)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datad (624:624:624) (640:640:640)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (454:454:454)) - (PORT datab (556:556:556) (579:579:579)) - (PORT datac (1308:1308:1308) (1322:1322:1322)) - (PORT datad (1285:1285:1285) (1413:1413:1413)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1085:1085:1085) (1161:1161:1161)) - (PORT datab (238:238:238) (283:283:283)) - (PORT datac (1265:1265:1265) (1292:1292:1292)) - (PORT datad (630:630:630) (659:659:659)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (916:916:916) (955:955:955)) - (PORT datac (1654:1654:1654) (1669:1669:1669)) - (PORT datad (641:641:641) (654:654:654)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (683:683:683)) - (PORT datab (201:201:201) (240:240:240)) - (PORT datac (589:589:589) (604:604:604)) - (PORT datad (625:625:625) (649:649:649)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1147:1147:1147)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (550:550:550) (573:573:573)) - (PORT datad (227:227:227) (272:272:272)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (895:895:895)) - (PORT datac (1192:1192:1192) (1289:1289:1289)) - (PORT datad (872:872:872) (902:902:902)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1148:1148:1148)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (1500:1500:1500) (1597:1597:1597)) - (PORT datad (1296:1296:1296) (1328:1328:1328)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (704:704:704)) - (PORT datab (913:913:913) (947:947:947)) - (PORT datad (897:897:897) (951:951:951)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1119:1119:1119) (1186:1186:1186)) - (PORT datab (419:419:419) (499:499:499)) - (PORT datac (410:410:410) (474:474:474)) - (PORT datad (1116:1116:1116) (1154:1154:1154)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (383:383:383)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1116:1116:1116) (1130:1130:1130)) - (PORT datad (1142:1142:1142) (1188:1188:1188)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (705:705:705)) - (PORT datab (911:911:911) (948:948:948)) - (PORT datac (1087:1087:1087) (1143:1143:1143)) - (PORT datad (897:897:897) (950:950:950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (652:652:652) (682:682:682)) - (PORT datac (1121:1121:1121) (1139:1139:1139)) - (PORT datad (1141:1141:1141) (1194:1194:1194)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (778:778:778)) - (PORT datab (842:842:842) (905:905:905)) - (PORT datac (659:659:659) (737:737:737)) - (PORT datad (864:864:864) (895:895:895)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (732:732:732) (835:835:835)) - (PORT datab (207:207:207) (250:250:250)) - (PORT datac (1367:1367:1367) (1393:1393:1393)) - (PORT datad (700:700:700) (780:780:780)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (405:405:405)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (336:336:336) (354:354:354)) - (PORT datad (211:211:211) (243:243:243)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~1) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (323:323:323) (347:347:347)) - (PORT datad (209:209:209) (241:241:241)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (701:701:701) (738:738:738)) - (PORT datac (1182:1182:1182) (1286:1286:1286)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (877:877:877) (930:930:930)) - (PORT datac (1497:1497:1497) (1599:1599:1599)) - (PORT datad (1296:1296:1296) (1332:1332:1332)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (972:972:972)) - (PORT datab (687:687:687) (768:768:768)) - (PORT datac (701:701:701) (797:797:797)) - (PORT datad (1060:1060:1060) (1072:1072:1072)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (1296:1296:1296) (1324:1324:1324)) - (PORT datac (636:636:636) (674:674:674)) - (PORT datad (1295:1295:1295) (1334:1334:1334)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (625:625:625)) - (PORT datab (375:375:375) (401:401:401)) - (PORT datac (1265:1265:1265) (1308:1308:1308)) - (PORT datad (585:585:585) (622:622:622)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (562:562:562) (577:577:577)) - (PORT datab (1159:1159:1159) (1193:1193:1193)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (837:837:837) (863:863:863)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (666:666:666)) - (PORT datab (877:877:877) (899:899:899)) - (PORT datac (660:660:660) (683:683:683)) - (PORT datad (229:229:229) (274:274:274)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (748:748:748)) - (PORT datab (618:618:618) (653:653:653)) - (PORT datac (1588:1588:1588) (1650:1650:1650)) - (PORT datad (637:637:637) (672:672:672)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1038:1038:1038) (1069:1069:1069)) - (PORT datab (1084:1084:1084) (1091:1091:1091)) - (PORT datac (363:363:363) (385:385:385)) - (PORT datad (867:867:867) (885:885:885)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1302:1302:1302) (1309:1309:1309)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (599:599:599) (621:621:621)) - (PORT datad (830:830:830) (843:843:843)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (671:671:671)) - (PORT datab (674:674:674) (704:704:704)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (608:608:608) (656:656:656)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (468:468:468)) - (PORT datab (379:379:379) (409:409:409)) - (PORT datac (626:626:626) (663:663:663)) - (PORT datad (806:806:806) (822:822:822)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1855:1855:1855) (1936:1936:1936)) - (PORT datab (869:869:869) (900:900:900)) - (PORT datac (906:906:906) (997:997:997)) - (PORT datad (1380:1380:1380) (1413:1413:1413)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2662:2662:2662) (2766:2766:2766)) - (PORT datab (1312:1312:1312) (1351:1351:1351)) - (PORT datac (903:903:903) (964:964:964)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (622:622:622)) - (PORT datab (665:665:665) (698:698:698)) - (PORT datac (498:498:498) (506:506:506)) - (PORT datad (520:520:520) (530:530:530)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (889:889:889)) - (PORT datab (600:600:600) (626:626:626)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1212:1212:1212) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1085:1085:1085)) - (PORT datab (1004:1004:1004) (1076:1076:1076)) - (PORT datac (2235:2235:2235) (2300:2300:2300)) - (PORT datad (581:581:581) (617:617:617)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1166:1166:1166)) - (PORT datab (860:860:860) (890:890:890)) - (PORT datac (846:846:846) (887:887:887)) - (PORT datad (822:822:822) (852:852:852)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1972:1972:1972) (2001:2001:2001)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (855:855:855) (926:926:926)) - (PORT datad (345:345:345) (371:371:371)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (598:598:598) (623:623:623)) - (PORT datac (808:808:808) (848:848:848)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (579:579:579)) - (PORT datab (1124:1124:1124) (1210:1210:1210)) - (PORT datac (841:841:841) (877:877:877)) - (PORT datad (1189:1189:1189) (1241:1241:1241)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (927:927:927)) - (PORT datab (1423:1423:1423) (1516:1516:1516)) - (PORT datac (1251:1251:1251) (1370:1370:1370)) - (PORT datad (1095:1095:1095) (1172:1172:1172)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (881:881:881)) - (PORT datab (2176:2176:2176) (2167:2167:2167)) - (PORT datac (846:846:846) (882:882:882)) - (PORT datad (1155:1155:1155) (1203:1203:1203)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (642:642:642) (677:677:677)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (634:634:634)) - (PORT datab (886:886:886) (905:905:905)) - (PORT datac (673:673:673) (708:708:708)) - (PORT datad (861:861:861) (882:882:882)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) - (DELAY - (ABSOLUTE - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (234:234:234) (274:274:274)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (967:967:967)) - (PORT datac (829:829:829) (856:856:856)) - (PORT datad (826:826:826) (854:854:854)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1163:1163:1163)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (846:846:846) (883:883:883)) - (PORT datad (341:341:341) (369:369:369)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (766:766:766)) - (PORT datab (450:450:450) (538:538:538)) - (PORT datac (440:440:440) (518:518:518)) - (PORT datad (1128:1128:1128) (1193:1193:1193)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (801:801:801)) - (PORT datab (910:910:910) (1004:1004:1004)) - (PORT datac (630:630:630) (695:695:695)) - (PORT datad (691:691:691) (752:752:752)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (466:466:466)) - (PORT datab (889:889:889) (1019:1019:1019)) - (PORT datac (652:652:652) (741:741:741)) - (PORT datad (673:673:673) (756:756:756)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1547:1547:1547)) - (PORT ena (2452:2452:2452) (2480:2480:2480)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (726:726:726)) - (PORT datab (261:261:261) (347:347:347)) - (PORT datac (1102:1102:1102) (1161:1161:1161)) - (PORT datad (406:406:406) (462:462:462)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (653:653:653)) - (PORT datab (630:630:630) (649:649:649)) - (PORT datac (1411:1411:1411) (1515:1515:1515)) - (PORT datad (319:319:319) (337:337:337)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1162:1162:1162)) - (PORT datab (915:915:915) (941:941:941)) - (PORT datad (536:536:536) (550:550:550)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1572:1572:1572) (1552:1552:1552)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (913:913:913) (996:996:996)) - (PORT datac (846:846:846) (883:883:883)) - (PORT datad (224:224:224) (297:297:297)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (965:965:965)) - (PORT datab (860:860:860) (892:892:892)) - (PORT datac (828:828:828) (858:858:858)) - (PORT datad (1931:1931:1931) (1953:1953:1953)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (738:738:738)) - (PORT datab (372:372:372) (407:407:407)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (612:612:612) (645:645:645)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (924:924:924)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1091:1091:1091) (1124:1124:1124)) - (PORT datad (1930:1930:1930) (1951:1951:1951)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1290:1290:1290) (1411:1411:1411)) - (PORT datab (1421:1421:1421) (1514:1514:1514)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (400:400:400)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (240:240:240) (317:317:317)) - (PORT datad (818:818:818) (845:845:845)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~13) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (652:652:652)) - (PORT datab (368:368:368) (389:389:389)) - (PORT datac (613:613:613) (633:633:633)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (934:934:934)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (863:863:863) (921:921:921)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (1417:1417:1417) (1449:1449:1449)) - (PORT datad (2061:2061:2061) (2141:2141:2141)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|flags_cond_true) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1066:1066:1066) (1102:1102:1102)) - (PORT datab (879:879:879) (936:936:936)) - (PORT datac (814:814:814) (829:829:829)) - (PORT datad (1555:1555:1555) (1605:1605:1605)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (688:688:688) (721:721:721)) - (PORT datac (1019:1019:1019) (1028:1028:1028)) - (PORT datad (606:606:606) (622:622:622)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (262:262:262)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (546:546:546) (557:557:557)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) - (DELAY - (ABSOLUTE - (PORT dataa (1069:1069:1069) (1101:1101:1101)) - (PORT datac (939:939:939) (962:962:962)) - (PORT datad (1013:1013:1013) (1020:1020:1020)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1166:1166:1166) (1217:1217:1217)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (192:192:192) (224:224:224)) - (PORT datad (584:584:584) (609:609:609)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (262:262:262)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (856:856:856) (854:854:854)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (388:388:388)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (193:193:193) (225:225:225)) - (PORT datad (636:636:636) (687:687:687)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (657:657:657)) - (PORT datab (595:595:595) (612:612:612)) - (PORT datac (1556:1556:1556) (1674:1674:1674)) - (PORT datad (1289:1289:1289) (1314:1314:1314)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1750:1750:1750) (1793:1793:1793)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1549:1549:1549)) - (PORT asdata (1746:1746:1746) (1789:1789:1789)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (473:473:473)) - (PORT datab (435:435:435) (462:462:462)) - (PORT datad (357:357:357) (417:417:417)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1448:1448:1448) (1467:1467:1467)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1210:1210:1210) (1281:1281:1281)) - (PORT datab (1383:1383:1383) (1451:1451:1451)) - (PORT datad (1861:1861:1861) (1917:1917:1917)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1773:1773:1773) (1820:1820:1820)) - (PORT ena (962:962:962) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1771:1771:1771) (1826:1826:1826)) - (PORT ena (1525:1525:1525) (1527:1527:1527)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (483:483:483)) - (PORT datab (422:422:422) (469:469:469)) - (PORT datad (362:362:362) (420:420:420)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (931:931:931) (961:961:961)) - (PORT ena (1426:1426:1426) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (934:934:934) (964:964:964)) - (PORT ena (1446:1446:1446) (1437:1437:1437)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (510:510:510)) - (PORT datab (242:242:242) (325:325:325)) - (PORT datad (669:669:669) (698:698:698)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1739:1739:1739) (1780:1780:1780)) - (PORT ena (1201:1201:1201) (1191:1191:1191)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1553:1553:1553)) - (PORT asdata (1740:1740:1740) (1778:1778:1778)) - (PORT ena (1241:1241:1241) (1243:1243:1243)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (701:701:701)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (627:627:627) (646:646:646)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1551:1551:1551)) - (PORT asdata (1772:1772:1772) (1828:1828:1828)) - (PORT ena (942:942:942) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1336:1336:1336) (1363:1363:1363)) - (PORT datab (1101:1101:1101) (1115:1115:1115)) - (PORT datad (387:387:387) (412:412:412)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (673:673:673)) - (PORT datab (685:685:685) (705:705:705)) - (PORT datac (599:599:599) (618:618:618)) - (PORT datad (580:580:580) (603:603:603)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (883:883:883) (916:916:916)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1555:1555:1555)) - (PORT asdata (1445:1445:1445) (1463:1463:1463)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (454:454:454)) - (PORT datab (406:406:406) (433:433:433)) - (PORT datad (655:655:655) (713:713:713)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (711:711:711)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (2006:2006:2006) (2147:2147:2147)) - (PORT datab (588:588:588) (606:606:606)) - (PORT datac (558:558:558) (586:586:586)) - (PORT datad (853:853:853) (863:863:863)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (899:899:899) (925:925:925)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (933:933:933) (1003:1003:1003)) - (PORT datad (233:233:233) (291:291:291)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) @@ -29574,1684 +28075,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~8) + (INSTANCE z80_\|alu_\|db_low\[2\]\~5) (DELAY (ABSOLUTE - (PORT dataa (342:342:342) (372:372:372)) - (PORT datab (454:454:454) (485:485:485)) - (PORT datad (219:219:219) (289:289:289)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (277:277:277)) - (PORT datab (1084:1084:1084) (1121:1121:1121)) - (PORT datac (652:652:652) (743:743:743)) - (PORT datad (391:391:391) (453:453:453)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (651:651:651) (725:725:725)) - (PORT datad (1040:1040:1040) (1058:1058:1058)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (404:404:404) (441:441:441)) - (PORT datac (1657:1657:1657) (1782:1782:1782)) - (PORT datad (621:621:621) (656:656:656)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) - (DELAY - (ABSOLUTE - (PORT datac (1515:1515:1515) (1605:1605:1605)) - (PORT datad (972:972:972) (1033:1033:1033)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1547:1547:1547)) - (PORT ena (2484:2484:2484) (2511:2511:2511)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (1029:1029:1029) (1068:1068:1068)) - (PORT datab (450:450:450) (537:537:537)) - (PORT datac (649:649:649) (725:725:725)) - (PORT datad (1040:1040:1040) (1058:1058:1058)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (669:669:669) (700:700:700)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (616:616:616)) - (PORT datab (932:932:932) (1003:1003:1003)) - (PORT datad (232:232:232) (285:285:285)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (399:399:399)) - (PORT datab (460:460:460) (495:495:495)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (999:999:999) (1080:1080:1080)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (1664:1664:1664) (1792:1792:1792)) - (PORT datad (371:371:371) (397:397:397)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) - (DELAY - (ABSOLUTE - (PORT dataa (1555:1555:1555) (1647:1647:1647)) - (PORT datac (588:588:588) (634:634:634)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1547:1547:1547)) - (PORT ena (2484:2484:2484) (2511:2511:2511)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1028:1028:1028) (1069:1069:1069)) - (PORT datab (446:446:446) (536:536:536)) - (PORT datac (648:648:648) (724:724:724)) - (PORT datad (1040:1040:1040) (1059:1059:1059)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (376:376:376)) - (PORT datab (405:405:405) (475:475:475)) - (PORT datac (620:620:620) (644:644:644)) - (PORT datad (401:401:401) (457:457:457)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT datab (401:401:401) (476:476:476)) - (PORT datad (187:187:187) (220:220:220)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (711:711:711) (733:733:733)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (264:264:264) (336:336:336)) - (PORT datab (929:929:929) (995:995:995)) - (PORT datad (568:568:568) (588:588:588)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (455:455:455) (495:495:495)) - (PORT datac (216:216:216) (292:292:292)) - (PORT datad (306:306:306) (322:322:322)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (690:690:690)) - (PORT datab (404:404:404) (434:434:434)) - (PORT datac (1660:1660:1660) (1785:1785:1785)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) - (DELAY - (ABSOLUTE - (PORT datac (1491:1491:1491) (1572:1572:1572)) - (PORT datad (607:607:607) (645:645:645)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1547:1547:1547)) - (PORT ena (2452:2452:2452) (2480:2480:2480)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) - (DELAY - (ABSOLUTE - (PORT datac (616:616:616) (642:642:642)) - (PORT datad (375:375:375) (438:438:438)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (270:270:270)) - (PORT datab (1119:1119:1119) (1168:1168:1168)) - (PORT datac (655:655:655) (710:710:710)) - (PORT datad (1061:1061:1061) (1090:1090:1090)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (777:777:777)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (232:232:232) (315:315:315)) - (PORT datad (804:804:804) (817:817:817)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1547:1547:1547)) - (PORT asdata (949:949:949) (965:965:965)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (262:262:262) (334:334:334)) - (PORT datab (613:613:613) (631:631:631)) - (PORT datad (894:894:894) (962:962:962)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (986:986:986) (988:988:988)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (459:459:459) (492:492:492)) - (PORT datac (314:314:314) (336:336:336)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (691:691:691)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1664:1664:1664) (1793:1793:1793)) - (PORT datad (370:370:370) (393:393:393)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (715:715:715)) - (PORT datac (1492:1492:1492) (1576:1576:1576)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) - (DELAY - (ABSOLUTE - (PORT datab (1051:1051:1051) (1091:1091:1091)) - (PORT datac (334:334:334) (362:362:362)) - (PORT datad (1332:1332:1332) (1382:1382:1382)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (808:808:808)) - (PORT datab (1553:1553:1553) (1675:1675:1675)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1402:1402:1402) (1495:1495:1495)) - (PORT datab (858:858:858) (927:927:927)) - (PORT datac (1160:1160:1160) (1279:1279:1279)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1822:1822:1822) (1903:1903:1903)) - (PORT datab (1155:1155:1155) (1229:1229:1229)) - (PORT datac (1968:1968:1968) (2075:2075:2075)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (414:414:414)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (884:884:884) (926:926:926)) - (PORT datad (908:908:908) (941:941:941)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (619:619:619)) - (PORT datab (1154:1154:1154) (1227:1227:1227)) - (PORT datac (1964:1964:1964) (2069:2069:2069)) - (PORT datad (556:556:556) (583:583:583)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (957:957:957) (1028:1028:1028)) - (PORT datac (1216:1216:1216) (1233:1233:1233)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1080:1080:1080)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (1172:1172:1172) (1293:1293:1293)) - (PORT datad (1048:1048:1048) (1069:1069:1069)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1396:1396:1396) (1481:1481:1481)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1173:1173:1173) (1294:1294:1294)) - (PORT datad (1115:1115:1115) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (576:576:576) (657:657:657)) - (PORT sload (1915:1915:1915) (1964:1964:1964)) - (PORT ena (1897:1897:1897) (1898:1898:1898)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (1198:1198:1198) (1259:1259:1259)) - (PORT datad (2699:2699:2699) (2899:2899:2899)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT datab (276:276:276) (370:370:370)) - (PORT datac (671:671:671) (730:730:730)) - (PORT datad (328:328:328) (353:353:353)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (700:700:700)) - (PORT datab (317:317:317) (412:412:412)) - (PORT datac (934:934:934) (1001:1001:1001)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (761:761:761)) - (PORT datab (473:473:473) (546:546:546)) - (PORT datac (1085:1085:1085) (1155:1155:1155)) - (PORT datad (1203:1203:1203) (1255:1255:1255)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (786:786:786)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datad (1163:1163:1163) (1228:1228:1228)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (747:747:747) (828:828:828)) - (PORT datab (608:608:608) (625:625:625)) - (PORT datad (828:828:828) (841:841:841)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (747:747:747) (827:827:827)) - (PORT datab (424:424:424) (509:509:509)) - (PORT datac (950:950:950) (1011:1011:1011)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (702:702:702)) - (PORT datab (962:962:962) (1026:1026:1026)) - (PORT datac (896:896:896) (956:956:956)) - (PORT datad (401:401:401) (447:447:447)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1011:1011:1011)) - (PORT datab (980:980:980) (1038:1038:1038)) - (PORT datac (950:950:950) (1010:1010:1010)) - (PORT datad (740:740:740) (812:812:812)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (829:829:829)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (856:856:856) (932:932:932)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (248:248:248)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (580:580:580)) - (PORT datab (1554:1554:1554) (1672:1672:1672)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (956:956:956) (1024:1024:1024)) - (PORT sload (1915:1915:1915) (1964:1964:1964)) - (PORT ena (1897:1897:1897) (1898:1898:1898)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[14\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (3043:3043:3043) (3292:3292:3292)) - (PORT datac (1488:1488:1488) (1594:1594:1594)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (744:744:744)) - (PORT datab (861:861:861) (899:899:899)) - (PORT datac (615:615:615) (664:664:664)) - (PORT datad (909:909:909) (956:956:956)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (813:813:813)) - (PORT datab (276:276:276) (371:371:371)) - (PORT datac (672:672:672) (733:733:733)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT datac (1157:1157:1157) (1229:1229:1229)) - (PORT datad (440:440:440) (516:516:516)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (728:728:728)) - (PORT datab (567:567:567) (594:594:594)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (924:924:924) (976:976:976)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT datab (907:907:907) (922:922:922)) - (PORT datac (645:645:645) (710:710:710)) - (PORT datad (1137:1137:1137) (1178:1178:1178)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (757:757:757)) - (PORT datab (387:387:387) (414:414:414)) - (PORT datad (448:448:448) (529:529:529)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (1579:1579:1579) (1680:1680:1680)) - (PORT datad (353:353:353) (384:384:384)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1794:1794:1794) (1888:1888:1888)) - (PORT sload (1678:1678:1678) (1738:1738:1738)) - (PORT ena (2119:2119:2119) (2120:2120:2120)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (3321:3321:3321) (3558:3558:3558)) - (PORT datad (865:865:865) (930:930:930)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (574:574:574)) - (PORT datac (653:653:653) (707:707:707)) - (PORT datad (881:881:881) (925:925:925)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (622:622:622)) - (PORT datab (1084:1084:1084) (1160:1160:1160)) - (PORT datac (410:410:410) (481:481:481)) - (PORT datad (625:625:625) (645:645:645)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (754:754:754)) - (PORT datab (223:223:223) (261:261:261)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (1538:1538:1538) (1635:1635:1635)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (787:787:787) (862:862:862)) - (PORT sload (1678:1678:1678) (1738:1738:1738)) - (PORT ena (2119:2119:2119) (2120:2120:2120)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[11\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (3322:3322:3322) (3562:3562:3562)) - (PORT datad (1450:1450:1450) (1535:1535:1535)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (328:328:328)) - (PORT datab (908:908:908) (964:964:964)) - (PORT datac (214:214:214) (289:289:289)) - (PORT datad (801:801:801) (824:824:824)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (752:752:752)) - (PORT datac (951:951:951) (1030:1030:1030)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (721:721:721) (790:790:790)) - (PORT datab (961:961:961) (1034:1034:1034)) - (PORT datad (429:429:429) (504:504:504)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (983:983:983)) - (PORT datab (593:593:593) (618:618:618)) - (PORT datac (928:928:928) (986:986:986)) - (PORT datad (536:536:536) (551:551:551)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (269:269:269)) - (PORT datab (208:208:208) (251:251:251)) - (PORT datad (709:709:709) (792:792:792)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1558:1558:1558)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (433:433:433)) - (PORT datab (1576:1576:1576) (1677:1677:1677)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (768:768:768) (840:840:840)) - (PORT sload (1678:1678:1678) (1738:1738:1738)) - (PORT ena (2119:2119:2119) (2120:2120:2120)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (2452:2452:2452) (2613:2613:2613)) - (PORT datad (2501:2501:2501) (2606:2606:2606)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (1557:1557:1557) (1677:1677:1677)) - (PORT datad (315:315:315) (337:337:337)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1447:1447:1447) (1504:1504:1504)) - (PORT sload (1915:1915:1915) (1964:1964:1964)) - (PORT ena (1897:1897:1897) (1898:1898:1898)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~23) - (DELAY - (ABSOLUTE - (PORT datac (3017:3017:3017) (3263:3263:3263)) - (PORT datad (1455:1455:1455) (1525:1525:1525)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (1049:1049:1049)) - (PORT datab (1092:1092:1092) (1157:1157:1157)) - (PORT datad (871:871:871) (933:933:933)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT datab (316:316:316) (409:409:409)) - (PORT datac (627:627:627) (666:666:666)) - (PORT datad (941:941:941) (1006:1006:1006)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1054:1054:1054)) - (PORT datab (1196:1196:1196) (1252:1252:1252)) - (PORT datad (920:920:920) (987:987:987)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (746:746:746) (828:828:828)) - (PORT datab (424:424:424) (510:510:510)) - (PORT datac (909:909:909) (970:970:970)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datad (309:309:309) (323:323:323)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (890:890:890)) - (PORT datab (1427:1427:1427) (1485:1485:1485)) - (PORT datac (845:845:845) (897:897:897)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (219:219:219) (259:259:259)) - (PORT datad (1539:1539:1539) (1640:1640:1640)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (994:994:994) (1068:1068:1068)) - (PORT sload (1678:1678:1678) (1738:1738:1738)) - (PORT ena (2119:2119:2119) (2120:2120:2120)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~19) - (DELAY - (ABSOLUTE - (PORT datac (1651:1651:1651) (1732:1732:1732)) - (PORT datad (2405:2405:2405) (2560:2560:2560)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (240:240:240)) - (PORT datab (807:807:807) (828:828:828)) - (PORT datad (1725:1725:1725) (1791:1791:1791)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1539:1539:1539)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2675:2675:2675) (2768:2768:2768)) - (PORT sload (1762:1762:1762) (1828:1828:1828)) - (PORT ena (1696:1696:1696) (1694:1694:1694)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~20) - (DELAY - (ABSOLUTE - (PORT datac (846:846:846) (912:912:912)) - (PORT datad (2996:2996:2996) (3237:3237:3237)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (424:424:424) (512:512:512)) - (PORT datac (706:706:706) (785:785:785)) - (PORT datad (742:742:742) (817:817:817)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (573:573:573)) - (PORT datab (689:689:689) (742:742:742)) - (PORT datac (934:934:934) (1003:1003:1003)) - (PORT datad (879:879:879) (921:921:921)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1056:1056:1056)) - (PORT datab (926:926:926) (993:993:993)) - (PORT datac (615:615:615) (671:671:671)) - (PORT datad (550:550:550) (553:553:553)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (410:410:410)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (595:595:595) (609:609:609)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (692:692:692)) - (PORT datac (412:412:412) (484:484:484)) - (PORT datad (1058:1058:1058) (1119:1119:1119)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (703:703:703) (784:784:784)) - (PORT datac (942:942:942) (1017:1017:1017)) - (PORT datad (1108:1108:1108) (1175:1175:1175)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (574:574:574)) - (PORT datac (932:932:932) (1003:1003:1003)) - (PORT datad (577:577:577) (583:583:583)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (760:760:760)) - (PORT datab (373:373:373) (394:394:394)) - (PORT datad (314:314:314) (323:323:323)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (2022:2022:2022) (2086:2086:2086)) - (PORT datab (597:597:597) (612:612:612)) - (PORT datac (558:558:558) (607:607:607)) - (PORT datad (361:361:361) (419:419:419)) + (PORT dataa (460:460:460) (538:538:538)) + (PORT datab (638:638:638) (705:705:705)) + (PORT datac (1102:1102:1102) (1133:1133:1133)) + (PORT datad (662:662:662) (719:719:719)) (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -31259,149 +28089,15 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (619:619:619)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (833:833:833) (844:844:844)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (851:851:851) (897:897:897)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|DFF_inst5) + (INSTANCE z80_\|alu_\|result_lo\[2\]) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT clk (1518:1518:1518) (1535:1535:1535)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) + (PORT ena (1283:1283:1283) (1287:1287:1287)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (300:300:300)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) - (DELAY - (ABSOLUTE - (PORT clk (1543:1543:1543) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (567:567:567) (646:646:646)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (734:734:734)) - (PORT datab (1012:1012:1012) (1033:1033:1033)) - (PORT datac (1020:1020:1020) (1033:1033:1033)) - (PORT datad (853:853:853) (868:868:868)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~8) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (624:624:624)) - (PORT datab (1149:1149:1149) (1161:1161:1161)) - (PORT datac (923:923:923) (997:997:997)) - (PORT datad (820:820:820) (841:841:841)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~9) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (563:563:563)) - (PORT datab (379:379:379) (403:403:403)) - (PORT datac (793:793:793) (819:819:819)) - (PORT datad (627:627:627) (659:659:659)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1460:1460:1460) (1461:1461:1461)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK @@ -31411,143 +28107,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) + (INSTANCE z80_\|alu_\|db_low\[2\]\~6) (DELAY (ABSOLUTE - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1460:1460:1460) (1461:1461:1461)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (225:225:225) (296:296:296)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) - (DELAY - (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT asdata (567:567:567) (643:643:643)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|iorq\~0) - (DELAY - (ABSOLUTE - (PORT datab (249:249:249) (333:333:333)) - (PORT datad (223:223:223) (294:294:294)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (341:341:341)) - (PORT datad (795:795:795) (800:800:800)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (710:710:710)) - (PORT datab (841:841:841) (884:884:884)) - (PORT datac (619:619:619) (647:647:647)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1546:1546:1546) (1607:1607:1607)) - (PORT datab (940:940:940) (1007:1007:1007)) - (PORT datac (938:938:938) (970:970:970)) - (PORT datad (859:859:859) (900:900:900)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (554:554:554) (563:563:563)) - (PORT datac (876:876:876) (893:893:893)) - (PORT datad (569:569:569) (579:579:579)) + (PORT dataa (339:339:339) (368:368:368)) + (PORT datab (597:597:597) (636:636:636)) + (PORT datac (965:965:965) (999:999:999)) + (PORT datad (590:590:590) (645:645:645)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -31557,93 +28123,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~36) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) (DELAY (ABSOLUTE - (PORT dataa (1227:1227:1227) (1328:1328:1328)) - (PORT datab (611:611:611) (646:646:646)) - (PORT datac (891:891:891) (977:977:977)) - (PORT datad (785:785:785) (805:805:805)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1147:1147:1147) (1192:1192:1192)) - (PORT datab (429:429:429) (463:463:463)) - (PORT datac (1712:1712:1712) (1761:1761:1761)) - (PORT datad (1211:1211:1211) (1200:1200:1200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (670:670:670)) - (PORT datab (631:631:631) (690:690:690)) - (PORT datad (1881:1881:1881) (1830:1830:1830)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1214:1214:1214)) - (PORT datab (1426:1426:1426) (1516:1516:1516)) - (PORT datac (1076:1076:1076) (1125:1125:1125)) - (PORT datad (1419:1419:1419) (1527:1527:1527)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1757:1757:1757) (1786:1786:1786)) - (PORT datab (894:894:894) (910:910:910)) - (PORT datac (925:925:925) (1021:1021:1021)) - (PORT datad (1185:1185:1185) (1275:1275:1275)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1323:1323:1323)) - (PORT datab (857:857:857) (861:861:861)) - (PORT datac (928:928:928) (1025:1025:1025)) - (PORT datad (615:615:615) (646:646:646)) + (PORT dataa (222:222:222) (276:276:276)) + (PORT datab (653:653:653) (675:675:675)) + (PORT datac (916:916:916) (949:949:949)) + (PORT datad (220:220:220) (264:264:264)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (337:337:337)) + (PORT datab (596:596:596) (614:614:614)) + (PORT datac (585:585:585) (589:589:589)) + (PORT datad (896:896:896) (944:944:944)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (534:534:534)) + (PORT datab (695:695:695) (720:720:720)) + (PORT datac (877:877:877) (900:900:900)) + (PORT datad (417:417:417) (490:490:490)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (411:411:411)) + (PORT datab (395:395:395) (424:424:424)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (345:345:345) (368:368:368)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31651,13 +28203,137 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) (DELAY (ABSOLUTE - (PORT dataa (1056:1056:1056) (1091:1091:1091)) - (PORT datab (866:866:866) (878:878:878)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (176:176:176) (202:202:202)) + (PORT dataa (368:368:368) (407:407:407)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (354:354:354) (383:383:383)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1207:1207:1207)) + (PORT datab (281:281:281) (344:344:344)) + (PORT datac (244:244:244) (303:303:303)) + (PORT datad (255:255:255) (301:301:301)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1695:1695:1695) (1779:1779:1779)) + (PORT datac (887:887:887) (904:904:904)) + (PORT datad (883:883:883) (900:900:900)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (911:911:911) (960:960:960)) + (PORT datad (237:237:237) (277:277:277)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (711:711:711)) + (PORT datab (1166:1166:1166) (1213:1213:1213)) + (PORT datac (421:421:421) (493:493:493)) + (PORT datad (662:662:662) (719:719:719)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1116:1116:1116) (1164:1164:1164)) + (PORT datac (603:603:603) (622:622:622)) + (PORT datad (629:629:629) (654:654:654)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1347:1347:1347)) + (PORT datab (239:239:239) (295:295:295)) + (PORT datac (959:959:959) (993:993:993)) + (PORT datad (329:329:329) (348:348:348)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1295:1295:1295) (1347:1347:1347)) + (PORT datab (963:963:963) (1021:1021:1021)) + (PORT datac (1621:1621:1621) (1653:1653:1653)) + (PORT datad (867:867:867) (886:886:886)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (667:667:667)) + (PORT datab (983:983:983) (1034:1034:1034)) + (PORT datac (313:313:313) (343:343:343)) + (PORT datad (228:228:228) (273:273:273)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -31667,13 +28343,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~4) + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) (DELAY (ABSOLUTE - (PORT datab (644:644:644) (684:684:684)) - (PORT datac (815:815:815) (834:834:834)) - (PORT datad (587:587:587) (605:605:605)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (390:390:390) (465:465:465)) + (PORT datab (263:263:263) (345:345:345)) + (PORT datac (236:236:236) (312:312:312)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1227:1227:1227)) + (PORT datab (658:658:658) (671:671:671)) + (PORT datac (632:632:632) (691:691:691)) + (PORT datad (234:234:234) (310:310:310)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1213:1213:1213)) + (PORT datab (894:894:894) (942:942:942)) + (PORT datac (660:660:660) (687:687:687)) + (PORT datad (883:883:883) (901:901:901)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31681,15 +28391,153 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (INSTANCE z80_\|alu_control_\|db\[6\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1333:1333:1333) (1368:1368:1368)) - (PORT datab (977:977:977) (1007:1007:1007)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (223:223:223) (259:259:259)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (924:924:924) (933:933:933)) + (PORT datac (1121:1121:1121) (1153:1153:1153)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1018:1018:1018)) + (PORT datab (950:950:950) (1001:1001:1001)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (876:876:876) (911:911:911)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (714:714:714)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1597:1597:1597) (1627:1627:1627)) + (PORT datad (861:861:861) (875:875:875)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (655:655:655)) + (PORT datab (1245:1245:1245) (1272:1272:1272)) + (PORT datac (1147:1147:1147) (1195:1195:1195)) + (PORT datad (336:336:336) (365:365:365)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (348:348:348)) + (PORT datad (249:249:249) (295:295:295)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1571:1571:1571) (1550:1550:1550)) + (PORT ena (1258:1258:1258) (1280:1280:1280)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1260:1260:1260)) + (PORT datab (1208:1208:1208) (1291:1291:1291)) + (PORT datac (1222:1222:1222) (1290:1290:1290)) + (PORT datad (272:272:272) (349:349:349)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (485:485:485)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1143:1143:1143) (1174:1174:1174)) + (PORT datad (1174:1174:1174) (1212:1212:1212)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1051:1051:1051)) + (PORT datab (1152:1152:1152) (1212:1212:1212)) + (PORT datac (671:671:671) (716:716:716)) + (PORT datad (621:621:621) (670:670:670)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (864:864:864) (885:885:885)) + (PORT datac (946:946:946) (986:986:986)) + (PORT datad (214:214:214) (249:249:249)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31700,26 +28548,214 @@ (INSTANCE z80_\|execute_\|ctl_mRead\~37) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (647:647:647) (684:684:684)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1300:1300:1300) (1399:1399:1399)) + (PORT datab (2075:2075:2075) (2259:2259:2259)) + (PORT datac (822:822:822) (879:879:879)) + (PORT datad (913:913:913) (964:964:964)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1269:1269:1269) (1304:1304:1304)) + (PORT datac (1404:1404:1404) (1456:1456:1456)) + (PORT datad (913:913:913) (977:977:977)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (241:241:241) (281:281:281)) + (PORT datac (1941:1941:1941) (2072:2072:2072)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (914:914:914)) + (PORT datab (230:230:230) (277:277:277)) + (PORT datac (631:631:631) (653:653:653)) + (PORT datad (955:955:955) (999:999:999)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1051:1051:1051) (1095:1095:1095)) + (PORT datab (1067:1067:1067) (1105:1105:1105)) + (PORT datac (1033:1033:1033) (1064:1064:1064)) + (PORT datad (634:634:634) (644:644:644)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (1056:1056:1056)) + (PORT datab (1130:1130:1130) (1132:1132:1132)) + (PORT datac (939:939:939) (1031:1031:1031)) + (PORT datad (1060:1060:1060) (1062:1062:1062)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~38) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (940:940:940)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (539:539:539) (555:555:555)) + (PORT datad (545:545:545) (556:556:556)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (715:715:715)) + (PORT datab (898:898:898) (929:929:929)) + (PORT datac (1980:1980:1980) (2019:2019:2019)) + (PORT datad (830:830:830) (842:842:842)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~3) + (DELAY + (ABSOLUTE + (PORT datab (833:833:833) (894:894:894)) + (PORT datac (622:622:622) (675:675:675)) + (PORT datad (207:207:207) (239:239:239)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (279:279:279)) + (PORT datab (238:238:238) (284:284:284)) + (PORT datac (356:356:356) (385:385:385)) + (PORT datad (1060:1060:1060) (1062:1062:1062)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (787:787:787)) + (PORT datab (1609:1609:1609) (1627:1627:1627)) + (PORT datac (617:617:617) (649:649:649)) + (PORT datad (544:544:544) (562:562:562)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT datab (553:553:553) (575:575:575)) + (PORT datac (1318:1318:1318) (1317:1317:1317)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1048:1048:1048) (1070:1070:1070)) + (PORT datab (577:577:577) (591:591:591)) + (PORT datac (783:783:783) (785:785:785)) + (PORT datad (770:770:770) (770:770:770)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1554:1554:1554)) + (PORT clk (1535:1535:1535) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1433:1433:1433) (1418:1418:1418)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1291:1291:1291) (1310:1310:1310)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31734,7 +28770,7 @@ (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) (DELAY (ABSOLUTE - (PORT datad (361:361:361) (412:412:412)) + (PORT datad (815:815:815) (866:866:866)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31744,10 +28780,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_mrd) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) + (PORT clk (1540:1540:1540) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) + (PORT clrn (1588:1588:1588) (1565:1565:1565)) + (PORT ena (1172:1172:1172) (1151:1151:1151)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31762,10 +28798,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT asdata (574:574:574) (658:658:658)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) + (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT asdata (1226:1226:1226) (1290:1290:1290)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31780,22 +28816,150 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (350:350:350)) - (PORT datac (215:215:215) (291:291:291)) + (PORT dataa (909:909:909) (983:983:983)) + (PORT datad (215:215:215) (284:284:284)) (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~4) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (281:281:281)) + (PORT datab (702:702:702) (781:781:781)) + (PORT datac (856:856:856) (898:898:898)) + (PORT datad (1074:1074:1074) (1111:1111:1111)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1890:1890:1890) (1960:1960:1960)) + (PORT datab (1472:1472:1472) (1522:1522:1522)) + (PORT datac (1489:1489:1489) (1536:1536:1536)) + (PORT datad (1919:1919:1919) (1985:1985:1985)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1152:1152:1152)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (201:201:201) (236:236:236)) + (PORT datad (679:679:679) (747:747:747)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~9) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (891:891:891)) + (PORT datab (1170:1170:1170) (1227:1227:1227)) + (PORT datac (822:822:822) (840:840:840)) + (PORT datad (805:805:805) (814:814:814)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT asdata (1818:1818:1818) (1849:1849:1849)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) + (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1291:1291:1291) (1310:1310:1310)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (220:220:220) (290:290:290)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1291:1291:1291) (1310:1310:1310)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT asdata (581:581:581) (655:655:655)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT asdata (567:567:567) (645:645:645)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31805,12 +28969,107 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|iorq\~0) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (PORT datad (613:613:613) (663:663:663)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (941:941:941) (1024:1024:1024)) + (PORT datac (374:374:374) (401:401:401)) + (PORT datad (217:217:217) (243:243:243)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (913:913:913)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (1187:1187:1187) (1208:1208:1208)) + (PORT datad (1091:1091:1091) (1137:1137:1137)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1889:1889:1889) (1932:1932:1932)) + (PORT datab (1525:1525:1525) (1597:1597:1597)) + (PORT datac (2202:2202:2202) (2248:2248:2248)) + (PORT datad (210:210:210) (242:242:242)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (263:263:263)) + (PORT datab (336:336:336) (366:366:366)) + (PORT datac (586:586:586) (589:589:589)) + (PORT datad (351:351:351) (382:382:382)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1588:1588:1588) (1563:1563:1563)) + (PORT ena (1810:1810:1810) (1851:1851:1851)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) (DELAY (ABSOLUTE - (PORT datad (220:220:220) (290:290:290)) + (PORT datad (586:586:586) (642:642:642)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31820,10 +29079,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) + (PORT clk (1542:1542:1542) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31838,10 +29097,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT asdata (567:567:567) (646:646:646)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1460:1460:1460) (1461:1461:1461)) + (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT asdata (568:568:568) (646:646:646)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1291:1291:1291) (1310:1310:1310)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31856,11 +29115,11 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (341:341:341)) - (PORT datab (934:934:934) (977:977:977)) - (PORT datad (693:693:693) (763:763:763)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1456:1456:1456) (1520:1520:1520)) + (PORT datab (251:251:251) (336:336:336)) + (PORT datad (1485:1485:1485) (1574:1574:1574)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31871,96 +29130,693 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (586:586:586) (613:613:613)) - (PORT datad (204:204:204) (232:232:232)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (340:340:340) (376:376:376)) + (PORT datab (352:352:352) (391:391:391)) + (PORT datac (1027:1027:1027) (1030:1030:1030)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1747:1747:1747) (1852:1852:1852)) + (PORT datab (1597:1597:1597) (1730:1730:1730)) + (PORT datac (1200:1200:1200) (1265:1265:1265)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2395:2395:2395) (2551:2551:2551)) + (PORT datad (1014:1014:1014) (1128:1128:1128)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~5) + (DELAY + (ABSOLUTE + (PORT datab (1342:1342:1342) (1445:1445:1445)) + (PORT datac (2885:2885:2885) (3060:3060:3060)) + (PORT datad (2470:2470:2470) (2672:2672:2672)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (401:401:401)) + (PORT datab (883:883:883) (892:892:892)) + (PORT datac (957:957:957) (1029:1029:1029)) + (PORT datad (1073:1073:1073) (1058:1058:1058)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1027:1027:1027)) + (PORT datac (1189:1189:1189) (1270:1270:1270)) + (PORT datad (2029:2029:2029) (2154:2154:2154)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1470:1470:1470) (1514:1514:1514)) + (PORT datab (897:897:897) (976:976:976)) + (PORT datac (362:362:362) (383:383:383)) + (PORT datad (193:193:193) (218:218:218)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (736:736:736)) + (PORT datab (837:837:837) (873:873:873)) + (PORT datac (876:876:876) (891:891:891)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1311:1311:1311)) + (PORT datab (870:870:870) (881:881:881)) + (PORT datac (1299:1299:1299) (1298:1298:1298)) + (PORT datad (625:625:625) (681:681:681)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (242:242:242)) + (PORT datab (1100:1100:1100) (1104:1104:1104)) + (PORT datac (369:369:369) (395:395:395)) + (PORT datad (1798:1798:1798) (1887:1887:1887)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~7) + (DELAY + (ABSOLUTE + (PORT datab (916:916:916) (964:964:964)) + (PORT datac (850:850:850) (896:896:896)) + (PORT datad (781:781:781) (791:791:791)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1515:1515:1515) (1583:1583:1583)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1714:1714:1714) (1760:1760:1760)) + (PORT datad (881:881:881) (920:920:920)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1447:1447:1447) (1506:1506:1506)) + (PORT datab (1169:1169:1169) (1174:1174:1174)) + (PORT datac (894:894:894) (923:923:923)) + (PORT datad (781:781:781) (794:794:794)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1513:1513:1513) (1581:1581:1581)) + (PORT datab (1150:1150:1150) (1204:1204:1204)) + (PORT datac (1094:1094:1094) (1111:1111:1111)) + (PORT datad (616:616:616) (634:634:634)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1361:1361:1361)) + (PORT datab (869:869:869) (894:894:894)) + (PORT datac (1706:1706:1706) (1761:1761:1761)) + (PORT datad (263:263:263) (315:315:315)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1146:1146:1146) (1188:1188:1188)) + (PORT datab (214:214:214) (258:258:258)) + (PORT datac (192:192:192) (225:225:225)) + (PORT datad (621:621:621) (651:651:651)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (1051:1051:1051) (1068:1068:1068)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1104:1104:1104)) + (PORT datab (879:879:879) (888:888:888)) + (PORT datac (609:609:609) (624:624:624)) + (PORT datad (1198:1198:1198) (1221:1221:1221)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (927:927:927)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (583:583:583) (601:601:601)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (332:332:332) (351:351:351)) + (PORT datad (813:813:813) (840:840:840)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (906:906:906)) + (PORT datab (1043:1043:1043) (1098:1098:1098)) + (PORT datac (1093:1093:1093) (1111:1111:1111)) + (PORT datad (1130:1130:1130) (1132:1132:1132)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (247:247:247)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (605:605:605)) + (PORT datab (1113:1113:1113) (1136:1136:1136)) + (PORT datac (1714:1714:1714) (1760:1760:1760)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (726:726:726)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (612:612:612) (639:639:639)) + (PORT datad (196:196:196) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (930:930:930) (979:979:979)) + (PORT datac (1054:1054:1054) (1167:1167:1167)) + (PORT datad (1137:1137:1137) (1183:1183:1183)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (296:296:296)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|DFF_inst5) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1587:1587:1587) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (228:228:228) (301:301:301)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1587:1587:1587) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1547:1547:1547)) + (PORT asdata (568:568:568) (647:647:647)) + (PORT clrn (1587:1587:1587) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (342:342:342)) + (PORT datad (605:605:605) (631:631:631)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (2080:2080:2080) (2107:2107:2107)) - (PORT datab (1534:1534:1534) (1595:1595:1595)) - (PORT datac (3025:3025:3025) (3270:3270:3270)) - (PORT datad (2406:2406:2406) (2552:2552:2552)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1750:1750:1750) (1853:1853:1853)) + (PORT datab (1593:1593:1593) (1734:1734:1734)) + (PORT datac (1199:1199:1199) (1264:1264:1264)) + (PORT datad (1222:1222:1222) (1307:1307:1307)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1531:1531:1531)) - (PORT asdata (1663:1663:1663) (1726:1726:1726)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ExtRamWE\~0) (DELAY (ABSOLUTE - (PORT dataa (2564:2564:2564) (2687:2687:2687)) - (PORT datab (3045:3045:3045) (3292:3292:3292)) - (PORT datac (1748:1748:1748) (1787:1787:1787)) - (PORT datad (1758:1758:1758) (1816:1816:1816)) + (PORT dataa (1747:1747:1747) (1852:1852:1852)) + (PORT datab (1597:1597:1597) (1730:1730:1730)) + (PORT datac (1200:1200:1200) (1265:1265:1265)) + (PORT datad (1220:1220:1220) (1307:1307:1307)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1796:1796:1796) (1810:1810:1810)) + (PORT datab (849:849:849) (873:873:873)) + (PORT datad (335:335:335) (353:353:353)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (1028:1028:1028)) + (PORT datab (994:994:994) (1080:1080:1080)) + (PORT datac (1875:1875:1875) (2047:2047:2047)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1686:1686:1686) (1827:1827:1827)) + (PORT datab (974:974:974) (1024:1024:1024)) + (PORT datac (941:941:941) (1003:1003:1003)) + (PORT datad (1201:1201:1201) (1259:1259:1259)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1027:1027:1027)) + (PORT datab (994:994:994) (1080:1080:1080)) + (PORT datac (1875:1875:1875) (2047:2047:2047)) + (PORT datad (622:622:622) (660:660:660)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (603:603:603) (689:689:689)) + (PORT sload (1125:1125:1125) (1169:1169:1169)) + (PORT ena (1155:1155:1155) (1129:1129:1129)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1254:1254:1254)) + (PORT datad (2019:2019:2019) (2140:2140:2140)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1794:1794:1794) (1807:1807:1807)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datad (320:320:320) (334:334:334)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (590:590:590) (668:668:668)) + (PORT sload (1125:1125:1125) (1169:1169:1169)) + (PORT ena (1155:1155:1155) (1129:1129:1129)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (2045:2045:2045) (2178:2178:2178)) + (PORT datad (1147:1147:1147) (1202:1202:1202)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1796:1796:1796) (1810:1810:1810)) + (PORT datab (337:337:337) (371:371:371)) + (PORT datad (554:554:554) (561:561:561)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (577:577:577) (658:658:658)) + (PORT sload (1125:1125:1125) (1169:1169:1169)) + (PORT ena (1155:1155:1155) (1129:1129:1129)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (1641:1641:1641) (1729:1729:1729)) + (PORT datac (1584:1584:1584) (1634:1634:1634)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (330:330:330)) - (PORT datab (239:239:239) (293:293:293)) - (PORT datac (231:231:231) (277:277:277)) - (PORT datad (1159:1159:1159) (1236:1236:1236)) + (PORT dataa (697:697:697) (725:725:725)) + (PORT datab (261:261:261) (314:314:314)) + (PORT datac (366:366:366) (404:404:404)) + (PORT datad (1304:1304:1304) (1296:1296:1296)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -31973,11 +29829,23 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (3043:3043:3043) (3294:3294:3294)) - (PORT datac (1489:1489:1489) (1596:1596:1596)) - (PORT datad (1459:1459:1459) (1527:1527:1527)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (2037:2037:2037) (2174:2174:2174)) + (PORT datac (1153:1153:1153) (1208:1208:1208)) + (PORT datad (1144:1144:1144) (1203:1203:1203)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (971:971:971)) + (PORT datad (1987:1987:1987) (2083:2083:2083)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31987,9 +29855,9 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1767:1767:1767) (1835:1835:1835)) - (PORT datab (930:930:930) (981:981:981)) - (PORT datad (179:179:179) (207:207:207)) + (PORT dataa (854:854:854) (879:879:879)) + (PORT datab (373:373:373) (396:396:396)) + (PORT datad (334:334:334) (343:343:343)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -32001,11 +29869,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1539:1539:1539)) + (PORT clk (1548:1548:1548) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1241:1241:1241) (1302:1302:1302)) - (PORT sload (1762:1762:1762) (1828:1828:1828)) - (PORT ena (1696:1696:1696) (1694:1694:1694)) + (PORT asdata (1128:1128:1128) (1174:1174:1174)) + (PORT sload (1213:1213:1213) (1283:1283:1283)) + (PORT ena (1456:1456:1456) (1440:1440:1440)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32021,9 +29889,9 @@ (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) (DELAY (ABSOLUTE - (PORT datac (1069:1069:1069) (1165:1165:1165)) - (PORT datad (3272:3272:3272) (3493:3493:3493)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1793:1793:1793) (1909:1909:1909)) + (PORT datad (678:678:678) (733:733:733)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32033,11 +29901,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (602:602:602) (623:623:623)) - (PORT datab (1557:1557:1557) (1672:1672:1672)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (855:855:855) (880:880:880)) + (PORT datab (604:604:604) (620:620:620)) + (PORT datad (532:532:532) (544:544:544)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32047,11 +29915,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1532:1532:1532)) + (PORT clk (1548:1548:1548) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1231:1231:1231) (1285:1285:1285)) - (PORT sload (1915:1915:1915) (1964:1964:1964)) - (PORT ena (1897:1897:1897) (1898:1898:1898)) + (PORT asdata (992:992:992) (1045:1045:1045)) + (PORT sload (1213:1213:1213) (1283:1283:1283)) + (PORT ena (1456:1456:1456) (1440:1440:1440)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32067,8 +29935,8 @@ (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) (DELAY (ABSOLUTE - (PORT datac (2987:2987:2987) (3186:3186:3186)) - (PORT datad (1114:1114:1114) (1182:1182:1182)) + (PORT datac (1749:1749:1749) (1862:1862:1862)) + (PORT datad (642:642:642) (699:699:699)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32079,11 +29947,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1551:1551:1551) (1669:1669:1669)) - (PORT datad (808:808:808) (825:825:825)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (858:858:858) (887:887:887)) + (PORT datab (535:535:535) (551:551:551)) + (PORT datad (339:339:339) (355:355:355)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32093,11 +29961,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1532:1532:1532)) + (PORT clk (1548:1548:1548) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (708:708:708) (779:779:779)) - (PORT sload (1915:1915:1915) (1964:1964:1964)) - (PORT ena (1897:1897:1897) (1898:1898:1898)) + (PORT asdata (751:751:751) (807:807:807)) + (PORT sload (1213:1213:1213) (1283:1283:1283)) + (PORT ena (1456:1456:1456) (1440:1440:1440)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32113,9 +29981,9 @@ (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) (DELAY (ABSOLUTE - (PORT datab (2449:2449:2449) (2610:2610:2610)) - (PORT datad (1427:1427:1427) (1510:1510:1510)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datac (1754:1754:1754) (1872:1872:1872)) + (PORT datad (367:367:367) (429:429:429)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32125,11 +29993,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) (DELAY (ABSOLUTE - (PORT dataa (635:635:635) (687:687:687)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datad (1726:1726:1726) (1788:1788:1788)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (853:853:853) (880:880:880)) + (PORT datab (534:534:534) (559:559:559)) + (PORT datad (339:339:339) (357:357:357)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32139,11 +30007,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1539:1539:1539)) + (PORT clk (1548:1548:1548) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1202:1202:1202) (1325:1325:1325)) - (PORT sload (1762:1762:1762) (1828:1828:1828)) - (PORT ena (1696:1696:1696) (1694:1694:1694)) + (PORT asdata (979:979:979) (1031:1031:1031)) + (PORT sload (1213:1213:1213) (1283:1283:1283)) + (PORT ena (1456:1456:1456) (1440:1440:1440)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32159,9 +30027,9 @@ (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) (DELAY (ABSOLUTE - (PORT datac (1523:1523:1523) (1623:1623:1623)) - (PORT datad (2402:2402:2402) (2558:2558:2558)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (1758:1758:1758) (1874:1874:1874)) + (PORT datad (652:652:652) (710:710:710)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32171,11 +30039,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) (DELAY (ABSOLUTE - (PORT dataa (899:899:899) (942:942:942)) - (PORT datab (607:607:607) (637:637:637)) - (PORT datad (1442:1442:1442) (1506:1506:1506)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (1351:1351:1351) (1385:1385:1385)) + (PORT datab (337:337:337) (371:371:371)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32185,11 +30053,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1540:1540:1540)) + (PORT clk (1528:1528:1528) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1016:1016:1016) (1105:1105:1105)) - (PORT sload (1597:1597:1597) (1652:1652:1652)) - (PORT ena (1976:1976:1976) (1959:1959:1959)) + (PORT asdata (1019:1019:1019) (1078:1078:1078)) + (PORT sload (1150:1150:1150) (1218:1218:1218)) + (PORT ena (1176:1176:1176) (1166:1166:1166)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32205,10 +30073,10 @@ (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (351:351:351)) - (PORT datad (3273:3273:3273) (3495:3495:3495)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (2021:2021:2021) (2124:2124:2124)) + (PORT datac (676:676:676) (743:743:743)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -32217,11 +30085,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) (DELAY (ABSOLUTE - (PORT dataa (1767:1767:1767) (1834:1834:1834)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datad (595:595:595) (615:615:615)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datad (1323:1323:1323) (1343:1343:1343)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32231,11 +30099,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1539:1539:1539)) + (PORT clk (1528:1528:1528) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (953:953:953) (1016:1016:1016)) - (PORT sload (1762:1762:1762) (1828:1828:1828)) - (PORT ena (1696:1696:1696) (1694:1694:1694)) + (PORT asdata (1156:1156:1156) (1209:1209:1209)) + (PORT sload (1150:1150:1150) (1218:1218:1218)) + (PORT ena (1176:1176:1176) (1166:1166:1166)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32251,10 +30119,10 @@ (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) (DELAY (ABSOLUTE - (PORT datac (1274:1274:1274) (1343:1343:1343)) - (PORT datad (3270:3270:3270) (3522:3522:3522)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (696:696:696) (759:759:759)) + (PORT datac (1750:1750:1750) (1863:1863:1863)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -32263,11 +30131,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) (DELAY (ABSOLUTE - (PORT dataa (626:626:626) (680:680:680)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datad (1444:1444:1444) (1505:1505:1505)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (1354:1354:1354) (1387:1387:1387)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32277,11 +30145,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1540:1540:1540)) + (PORT clk (1528:1528:1528) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1250:1250:1250) (1311:1311:1311)) - (PORT sload (1597:1597:1597) (1652:1652:1652)) - (PORT ena (1976:1976:1976) (1959:1959:1959)) + (PORT asdata (1639:1639:1639) (1657:1657:1657)) + (PORT sload (1150:1150:1150) (1218:1218:1218)) + (PORT ena (1176:1176:1176) (1166:1166:1166)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32297,20 +30165,250 @@ (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) (DELAY (ABSOLUTE - (PORT datab (3322:3322:3322) (3557:3557:3557)) - (PORT datad (1225:1225:1225) (1301:1301:1301)) + (PORT datac (1748:1748:1748) (1867:1867:1867)) + (PORT datad (927:927:927) (1010:1010:1010)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (380:380:380)) + (PORT datab (1361:1361:1361) (1369:1369:1369)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) (DELAY (ABSOLUTE - (PORT d[0] (2302:2302:2302) (2397:2397:2397)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (597:597:597) (678:678:678)) + (PORT sload (1150:1150:1150) (1218:1218:1218)) + (PORT ena (1176:1176:1176) (1166:1166:1166)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (948:948:948) (1009:1009:1009)) + (PORT datad (2008:2008:2008) (2130:2130:2130)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1422:1422:1422)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datad (552:552:552) (561:561:561)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (591:591:591) (677:677:677)) + (PORT sload (1117:1117:1117) (1168:1168:1168)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) + (DELAY + (ABSOLUTE + (PORT datac (1757:1757:1757) (1868:1868:1868)) + (PORT datad (678:678:678) (737:737:737)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (567:567:567) (585:585:585)) + (PORT datad (1365:1365:1365) (1379:1379:1379)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (580:580:580) (668:668:668)) + (PORT sload (1117:1117:1117) (1168:1168:1168)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) + (DELAY + (ABSOLUTE + (PORT datac (910:910:910) (972:972:972)) + (PORT datad (1442:1442:1442) (1565:1565:1565)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datad (1362:1362:1362) (1374:1374:1374)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (913:913:913) (972:972:972)) + (PORT sload (1117:1117:1117) (1168:1168:1168)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (1010:1010:1010)) + (PORT datad (1442:1442:1442) (1566:1566:1566)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (375:375:375)) + (PORT datab (816:816:816) (834:834:834)) + (PORT datad (1561:1561:1561) (1571:1571:1571)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (583:583:583) (667:667:667)) + (PORT sload (1125:1125:1125) (1169:1169:1169)) + (PORT ena (1155:1155:1155) (1129:1129:1129)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1791:1791:1791) (1903:1903:1903)) + (PORT datad (854:854:854) (913:913:913)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1010:1010:1010) (1062:1062:1062)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -32319,23 +30417,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2750:2750:2750) (2950:2950:2950)) - (PORT d[1] (1649:1649:1649) (1795:1795:1795)) - (PORT d[2] (2825:2825:2825) (3063:3063:3063)) - (PORT d[3] (2361:2361:2361) (2579:2579:2579)) - (PORT d[4] (2246:2246:2246) (2414:2414:2414)) - (PORT d[5] (2774:2774:2774) (2984:2984:2984)) - (PORT d[6] (1739:1739:1739) (1845:1845:1845)) - (PORT d[7] (4071:4071:4071) (4237:4237:4237)) - (PORT d[8] (2438:2438:2438) (2584:2584:2584)) - (PORT d[9] (2822:2822:2822) (2973:2973:2973)) - (PORT d[10] (1896:1896:1896) (2024:2024:2024)) - (PORT d[11] (1897:1897:1897) (2054:2054:2054)) - (PORT d[12] (3374:3374:3374) (3534:3534:3534)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (1009:1009:1009) (1047:1047:1047)) + (PORT d[1] (2076:2076:2076) (2305:2305:2305)) + (PORT d[2] (1463:1463:1463) (1514:1514:1514)) + (PORT d[3] (2867:2867:2867) (3072:3072:3072)) + (PORT d[4] (2625:2625:2625) (2841:2841:2841)) + (PORT d[5] (3152:3152:3152) (3353:3353:3353)) + (PORT d[6] (1368:1368:1368) (1453:1453:1453)) + (PORT d[7] (2906:2906:2906) (3079:3079:3079)) + (PORT d[8] (997:997:997) (1014:1014:1014)) + (PORT d[9] (1597:1597:1597) (1654:1654:1654)) + (PORT d[10] (1607:1607:1607) (1695:1695:1695)) + (PORT d[11] (2235:2235:2235) (2380:2380:2380)) + (PORT d[12] (1610:1610:1610) (1712:1712:1712)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -32344,11 +30442,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2743:2743:2743) (2798:2798:2798)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (958:958:958) (934:934:934)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -32357,60 +30455,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (2884:2884:2884) (2919:2919:2919)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (1472:1472:1472) (1458:1458:1458)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1815:1815:1815) (1842:1842:1842)) + (PORT clk (1816:1816:1816) (1842:1842:1842)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -32421,49 +30519,49 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) + (PORT clk (1001:1001:1001) (1005:1005:1005)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) + (PORT clk (1002:1002:1002) (1006:1006:1006)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) + (PORT clk (1002:1002:1002) (1006:1006:1006)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) + (PORT clk (1002:1002:1002) (1006:1006:1006)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT asdata (1175:1175:1175) (1208:1208:1208)) + (PORT clk (1896:1896:1896) (1918:1918:1918)) + (PORT asdata (2035:2035:2035) (2085:2085:2085)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32473,11 +30571,11 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT asdata (559:559:559) (633:633:633)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT asdata (1451:1451:1451) (1488:1488:1488)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -32490,12 +30588,12 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (260:260:260) (326:326:326)) - (PORT datab (243:243:243) (296:296:296)) - (PORT datac (234:234:234) (282:282:282)) - (PORT datad (1156:1156:1156) (1233:1233:1233)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT dataa (697:697:697) (725:725:725)) + (PORT datab (262:262:262) (316:316:316)) + (PORT datac (367:367:367) (405:405:405)) + (PORT datad (1303:1303:1303) (1300:1300:1300)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32506,9 +30604,9 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (3047:3047:3047) (3294:3294:3294)) - (PORT datac (1489:1489:1489) (1599:1599:1599)) - (PORT datad (1458:1458:1458) (1529:1529:1529)) + (PORT datab (2042:2042:2042) (2178:2178:2178)) + (PORT datac (1154:1154:1154) (1211:1211:1211)) + (PORT datad (1145:1145:1145) (1206:1206:1206)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -32517,11 +30615,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1446:1446:1446) (1486:1486:1486)) - (PORT clk (1841:1841:1841) (1870:1870:1870)) + (PORT d[0] (991:991:991) (1045:1045:1045)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) ) ) (TIMINGCHECK @@ -32530,23 +30628,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2224:2224:2224) (2370:2370:2370)) - (PORT d[1] (2380:2380:2380) (2609:2609:2609)) - (PORT d[2] (2064:2064:2064) (2259:2259:2259)) - (PORT d[3] (3907:3907:3907) (4275:4275:4275)) - (PORT d[4] (1889:1889:1889) (2024:2024:2024)) - (PORT d[5] (4270:4270:4270) (4584:4584:4584)) - (PORT d[6] (2296:2296:2296) (2416:2416:2416)) - (PORT d[7] (2481:2481:2481) (2555:2555:2555)) - (PORT d[8] (3366:3366:3366) (3561:3561:3561)) - (PORT d[9] (2497:2497:2497) (2609:2609:2609)) - (PORT d[10] (1595:1595:1595) (1698:1698:1698)) - (PORT d[11] (2735:2735:2735) (2878:2878:2878)) - (PORT d[12] (1892:1892:1892) (1930:1930:1930)) - (PORT clk (1838:1838:1838) (1866:1866:1866)) + (PORT d[0] (1010:1010:1010) (1048:1048:1048)) + (PORT d[1] (2092:2092:2092) (2316:2316:2316)) + (PORT d[2] (3345:3345:3345) (3458:3458:3458)) + (PORT d[3] (2859:2859:2859) (3062:3062:3062)) + (PORT d[4] (2566:2566:2566) (2775:2775:2775)) + (PORT d[5] (3169:3169:3169) (3393:3393:3393)) + (PORT d[6] (1618:1618:1618) (1695:1695:1695)) + (PORT d[7] (2898:2898:2898) (3057:3057:3057)) + (PORT d[8] (1024:1024:1024) (1046:1046:1046)) + (PORT d[9] (3241:3241:3241) (3372:3372:3372)) + (PORT d[10] (1642:1642:1642) (1735:1735:1735)) + (PORT d[11] (1916:1916:1916) (2070:2070:2070)) + (PORT d[12] (1870:1870:1870) (1971:1971:1971)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) ) ) (TIMINGCHECK @@ -32555,11 +30653,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2111:2111:2111) (2135:2135:2135)) - (PORT clk (1838:1838:1838) (1866:1866:1866)) + (PORT d[0] (950:950:950) (925:925:925)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) ) ) (TIMINGCHECK @@ -32568,60 +30666,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1841:1841:1841) (1870:1870:1870)) - (PORT d[0] (2839:2839:2839) (2882:2882:2882)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (1713:1713:1713) (1683:1683:1683)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1842:1842:1842) (1871:1871:1871)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1842:1842:1842) (1871:1871:1871)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1842:1842:1842) (1871:1871:1871)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1842:1842:1842) (1871:1871:1871)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1801:1801:1801) (1829:1829:1829)) + (PORT clk (1814:1814:1814) (1840:1840:1840)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -32632,69 +30730,81 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (986:986:986) (992:992:992)) + (PORT clk (999:999:999) (1003:1003:1003)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (987:987:987) (993:993:993)) + (PORT clk (1000:1000:1000) (1004:1004:1004)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (987:987:987) (993:993:993)) + (PORT clk (1000:1000:1000) (1004:1004:1004)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (987:987:987) (993:993:993)) + (PORT clk (1000:1000:1000) (1004:1004:1004)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) (DELAY (ABSOLUTE - (PORT dataa (334:334:334) (454:454:454)) - (PORT datab (1274:1274:1274) (1334:1334:1334)) - (PORT datac (1165:1165:1165) (1244:1244:1244)) - (PORT datad (886:886:886) (912:912:912)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT asdata (1470:1470:1470) (1518:1518:1518)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT asdata (706:706:706) (770:770:770)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (260:260:260) (324:324:324)) - (PORT datab (243:243:243) (297:297:297)) - (PORT datac (234:234:234) (281:281:281)) - (PORT datad (1156:1156:1156) (1231:1231:1231)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (700:700:700) (726:726:726)) + (PORT datab (266:266:266) (319:319:319)) + (PORT datac (371:371:371) (404:404:404)) + (PORT datad (1304:1304:1304) (1295:1295:1295)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32705,22 +30815,22 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (3051:3051:3051) (3300:3300:3300)) - (PORT datac (1491:1491:1491) (1601:1601:1601)) - (PORT datad (1456:1456:1456) (1526:1526:1526)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (2038:2038:2038) (2171:2171:2171)) + (PORT datac (1153:1153:1153) (1206:1206:1206)) + (PORT datad (1143:1143:1143) (1202:1202:1202)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1690:1690:1690) (1725:1725:1725)) - (PORT clk (1846:1846:1846) (1875:1875:1875)) + (PORT d[0] (1184:1184:1184) (1228:1228:1228)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) ) ) (TIMINGCHECK @@ -32729,23 +30839,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1955:1955:1955) (2104:2104:2104)) - (PORT d[1] (2427:2427:2427) (2639:2639:2639)) - (PORT d[2] (2051:2051:2051) (2252:2252:2252)) - (PORT d[3] (3897:3897:3897) (4247:4247:4247)) - (PORT d[4] (1917:1917:1917) (2062:2062:2062)) - (PORT d[5] (4591:4591:4591) (4927:4927:4927)) - (PORT d[6] (2003:2003:2003) (2104:2104:2104)) - (PORT d[7] (2209:2209:2209) (2271:2271:2271)) - (PORT d[8] (3388:3388:3388) (3585:3585:3585)) - (PORT d[9] (2531:2531:2531) (2653:2653:2653)) - (PORT d[10] (2302:2302:2302) (2480:2480:2480)) - (PORT d[11] (2455:2455:2455) (2599:2599:2599)) - (PORT d[12] (1597:1597:1597) (1628:1628:1628)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (3973:3973:3973) (4187:4187:4187)) + (PORT d[1] (1695:1695:1695) (1858:1858:1858)) + (PORT d[2] (3329:3329:3329) (3462:3462:3462)) + (PORT d[3] (2153:2153:2153) (2276:2276:2276)) + (PORT d[4] (2142:2142:2142) (2252:2252:2252)) + (PORT d[5] (1659:1659:1659) (1777:1777:1777)) + (PORT d[6] (1754:1754:1754) (1804:1804:1804)) + (PORT d[7] (3063:3063:3063) (3210:3210:3210)) + (PORT d[8] (3317:3317:3317) (3546:3546:3546)) + (PORT d[9] (1753:1753:1753) (1814:1814:1814)) + (PORT d[10] (3216:3216:3216) (3426:3426:3426)) + (PORT d[11] (2090:2090:2090) (2212:2212:2212)) + (PORT d[12] (1771:1771:1771) (1834:1834:1834)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) ) ) (TIMINGCHECK @@ -32754,11 +30864,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2315:2315:2315) (2304:2304:2304)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (2235:2235:2235) (2268:2268:2268)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) ) ) (TIMINGCHECK @@ -32767,60 +30877,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (PORT d[0] (2609:2609:2609) (2654:2654:2654)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (2962:2962:2962) (3024:3024:3024)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) + (PORT clk (1846:1846:1846) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) + (PORT clk (1846:1846:1846) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) + (PORT clk (1846:1846:1846) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) + (PORT clk (1846:1846:1846) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1806:1806:1806) (1834:1834:1834)) + (PORT clk (1805:1805:1805) (1832:1832:1832)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -32831,51 +30941,67 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) + (PORT clk (990:990:990) (995:995:995)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) + (PORT clk (991:991:991) (996:996:996)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) + (PORT clk (991:991:991) (996:996:996)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) + (PORT clk (991:991:991) (996:996:996)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (616:616:616)) + (PORT datab (976:976:976) (1039:1039:1039)) + (PORT datac (828:828:828) (832:832:832)) + (PORT datad (1142:1142:1142) (1222:1222:1222)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (330:330:330)) - (PORT datab (237:237:237) (290:290:290)) - (PORT datac (230:230:230) (276:276:276)) - (PORT datad (1159:1159:1159) (1231:1231:1231)) + (PORT dataa (700:700:700) (731:731:731)) + (PORT datab (265:265:265) (319:319:319)) + (PORT datac (371:371:371) (408:408:408)) + (PORT datad (1303:1303:1303) (1299:1299:1299)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -32888,9 +31014,9 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (3049:3049:3049) (3294:3294:3294)) - (PORT datac (1491:1491:1491) (1597:1597:1597)) - (PORT datad (1456:1456:1456) (1526:1526:1526)) + (PORT datab (2046:2046:2046) (2179:2179:2179)) + (PORT datac (1157:1157:1157) (1209:1209:1209)) + (PORT datad (1148:1148:1148) (1203:1203:1203)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -32899,11 +31025,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1723:1723:1723) (1781:1781:1781)) - (PORT clk (1850:1850:1850) (1879:1879:1879)) + (PORT d[0] (1196:1196:1196) (1209:1209:1209)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) ) ) (TIMINGCHECK @@ -32912,23 +31038,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1942:1942:1942) (2071:2071:2071)) - (PORT d[1] (2685:2685:2685) (2897:2897:2897)) - (PORT d[2] (2105:2105:2105) (2287:2287:2287)) - (PORT d[3] (1498:1498:1498) (1596:1596:1596)) - (PORT d[4] (2201:2201:2201) (2359:2359:2359)) - (PORT d[5] (4593:4593:4593) (4932:4932:4932)) - (PORT d[6] (2285:2285:2285) (2384:2384:2384)) - (PORT d[7] (2181:2181:2181) (2235:2235:2235)) - (PORT d[8] (3077:3077:3077) (3253:3253:3253)) - (PORT d[9] (2859:2859:2859) (2985:2985:2985)) - (PORT d[10] (2256:2256:2256) (2432:2432:2432)) - (PORT d[11] (2437:2437:2437) (2584:2584:2584)) - (PORT d[12] (1584:1584:1584) (1596:1596:1596)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (4200:4200:4200) (4456:4456:4456)) + (PORT d[1] (2340:2340:2340) (2537:2537:2537)) + (PORT d[2] (3231:3231:3231) (3326:3326:3326)) + (PORT d[3] (2575:2575:2575) (2761:2761:2761)) + (PORT d[4] (2559:2559:2559) (2766:2766:2766)) + (PORT d[5] (2828:2828:2828) (3008:3008:3008)) + (PORT d[6] (1911:1911:1911) (2053:2053:2053)) + (PORT d[7] (2601:2601:2601) (2739:2739:2739)) + (PORT d[8] (3332:3332:3332) (3618:3618:3618)) + (PORT d[9] (2924:2924:2924) (3075:3075:3075)) + (PORT d[10] (5088:5088:5088) (5359:5359:5359)) + (PORT d[11] (1899:1899:1899) (2034:2034:2034)) + (PORT d[12] (2169:2169:2169) (2292:2292:2292)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) ) ) (TIMINGCHECK @@ -32937,11 +31063,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1709:1709:1709) (1705:1705:1705)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (2009:2009:2009) (1965:1965:1965)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) ) ) (TIMINGCHECK @@ -32950,60 +31076,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1879:1879:1879)) - (PORT d[0] (3209:3209:3209) (3224:3224:3224)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (2224:2224:2224) (2198:2198:2198)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1810:1810:1810) (1838:1838:1838)) + (PORT clk (1814:1814:1814) (1840:1840:1840)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -33014,53 +31140,53 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (1001:1001:1001)) + (PORT clk (999:999:999) (1003:1003:1003)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1002:1002:1002)) + (PORT clk (1000:1000:1000) (1004:1004:1004)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1002:1002:1002)) + (PORT clk (1000:1000:1000) (1004:1004:1004)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1002:1002:1002)) + (PORT clk (1000:1000:1000) (1004:1004:1004)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (INSTANCE D\[6\]\~91) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1262:1262:1262) (1265:1265:1265)) - (PORT datac (1164:1164:1164) (1242:1242:1242)) - (PORT datad (1242:1242:1242) (1287:1287:1287)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (837:837:837) (859:859:859)) + (PORT datab (1432:1432:1432) (1519:1519:1519)) + (PORT datac (318:318:318) (339:339:339)) + (PORT datad (1100:1100:1100) (1101:1101:1101)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33068,15 +31194,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (329:329:329)) - (PORT datab (240:240:240) (293:293:293)) - (PORT datac (230:230:230) (277:277:277)) - (PORT datad (1159:1159:1159) (1236:1236:1236)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (698:698:698) (723:723:723)) + (PORT datab (257:257:257) (310:310:310)) + (PORT datac (364:364:364) (402:402:402)) + (PORT datad (1304:1304:1304) (1295:1295:1295)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33091,17 +31217,27 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1044:1044:1044) (1098:1098:1098)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|vram_address\~0) (DELAY (ABSOLUTE - (PORT dataa (1190:1190:1190) (1270:1270:1270)) - (PORT datab (1481:1481:1481) (1552:1552:1552)) - (PORT datac (1186:1186:1186) (1249:1249:1249)) - (PORT datad (880:880:880) (934:934:934)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1253:1253:1253) (1340:1340:1340)) + (PORT datab (987:987:987) (1065:1065:1065)) + (PORT datac (971:971:971) (1042:1042:1042)) + (PORT datad (277:277:277) (361:361:361)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33112,14 +31248,14 @@ (INSTANCE ula_\|video_\|vram_address\[0\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) - (PORT asdata (1257:1257:1257) (1330:1330:1330)) - (PORT ena (936:936:936) (924:924:924)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -33128,9 +31264,9 @@ (INSTANCE ula_\|video_\|vram_address\[1\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) - (PORT asdata (1262:1262:1262) (1308:1308:1308)) - (PORT ena (936:936:936) (924:924:924)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) + (PORT asdata (1205:1205:1205) (1280:1280:1280)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33144,8 +31280,8 @@ (INSTANCE ula_\|video_\|vram_address\[2\]\~4) (DELAY (ABSOLUTE - (PORT datad (952:952:952) (1009:1009:1009)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (896:896:896) (972:972:972)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -33154,9 +31290,9 @@ (INSTANCE ula_\|video_\|vram_address\[2\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (936:936:936) (924:924:924)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33170,8 +31306,8 @@ (INSTANCE ula_\|video_\|Add3\~0) (DELAY (ABSOLUTE - (PORT datac (986:986:986) (1049:1049:1049)) - (PORT datad (952:952:952) (1009:1009:1009)) + (PORT datac (891:891:891) (968:968:968)) + (PORT datad (1442:1442:1442) (1493:1493:1493)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33182,9 +31318,9 @@ (INSTANCE ula_\|video_\|vram_address\[3\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (936:936:936) (924:924:924)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33198,10 +31334,10 @@ (INSTANCE ula_\|video_\|Add3\~1) (DELAY (ABSOLUTE - (PORT dataa (962:962:962) (1044:1044:1044)) - (PORT datac (983:983:983) (1044:1044:1044)) - (PORT datad (949:949:949) (1005:1005:1005)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (929:929:929) (1008:1008:1008)) + (PORT datac (1383:1383:1383) (1458:1458:1458)) + (PORT datad (1442:1442:1442) (1493:1493:1493)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33212,9 +31348,9 @@ (INSTANCE ula_\|video_\|vram_address\[4\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (936:936:936) (924:924:924)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33228,8 +31364,8 @@ (INSTANCE ula_\|video_\|Add4\~0) (DELAY (ABSOLUTE - (PORT dataa (982:982:982) (1046:1046:1046)) - (PORT datab (686:686:686) (762:762:762)) + (PORT dataa (697:697:697) (779:779:779)) + (PORT datab (721:721:721) (803:803:803)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -33243,7 +31379,7 @@ (INSTANCE ula_\|video_\|Add4\~2) (DELAY (ABSOLUTE - (PORT datab (738:738:738) (799:799:799)) + (PORT datab (644:644:644) (722:722:722)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -33257,7 +31393,7 @@ (INSTANCE ula_\|video_\|Add4\~4) (DELAY (ABSOLUTE - (PORT datab (1164:1164:1164) (1228:1228:1228)) + (PORT datab (706:706:706) (772:772:772)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -33271,9 +31407,9 @@ (INSTANCE ula_\|video_\|Add4\~6) (DELAY (ABSOLUTE - (PORT dataa (946:946:946) (1004:1004:1004)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (682:682:682) (766:766:766)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -33285,9 +31421,9 @@ (INSTANCE ula_\|video_\|vram_address\[5\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (936:936:936) (924:924:924)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33301,9 +31437,9 @@ (INSTANCE ula_\|video_\|Add4\~8) (DELAY (ABSOLUTE - (PORT datab (732:732:732) (799:799:799)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (700:700:700) (788:788:788)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -33315,9 +31451,9 @@ (INSTANCE ula_\|video_\|vram_address\[6\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (936:936:936) (924:924:924)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33331,7 +31467,7 @@ (INSTANCE ula_\|video_\|Add4\~10) (DELAY (ABSOLUTE - (PORT dataa (912:912:912) (974:974:974)) + (PORT dataa (980:980:980) (1052:1052:1052)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -33345,9 +31481,9 @@ (INSTANCE ula_\|video_\|vram_address\[7\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (936:936:936) (924:924:924)) + (PORT ena (1216:1216:1216) (1194:1194:1194)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33361,9 +31497,9 @@ (INSTANCE ula_\|video_\|Add4\~12) (DELAY (ABSOLUTE - (PORT dataa (716:716:716) (785:785:785)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (694:694:694) (766:766:766)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -33375,11 +31511,11 @@ (INSTANCE ula_\|video_\|Selector6\~0) (DELAY (ABSOLUTE - (PORT datab (1267:1267:1267) (1344:1344:1344)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (610:610:610) (638:638:638)) + (PORT datac (561:561:561) (582:582:582)) + (PORT datad (957:957:957) (1029:1029:1029)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -33389,12 +31525,12 @@ (INSTANCE ula_\|video_\|vram_address\[9\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1182:1182:1182) (1263:1263:1263)) - (PORT datab (1481:1481:1481) (1553:1553:1553)) - (PORT datac (1190:1190:1190) (1255:1255:1255)) - (PORT datad (876:876:876) (926:926:926)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1254:1254:1254) (1344:1344:1344)) + (PORT datab (987:987:987) (1066:1066:1066)) + (PORT datac (976:976:976) (1049:1049:1049)) + (PORT datad (282:282:282) (366:366:366)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33405,9 +31541,9 @@ (INSTANCE ula_\|video_\|vram_address\[8\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (964:964:964) (963:963:963)) + (PORT ena (820:820:820) (826:826:826)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33421,7 +31557,7 @@ (INSTANCE ula_\|video_\|Add4\~14) (DELAY (ABSOLUTE - (PORT datad (894:894:894) (944:944:944)) + (PORT datad (708:708:708) (780:780:780)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -33432,11 +31568,11 @@ (INSTANCE ula_\|video_\|Selector5\~0) (DELAY (ABSOLUTE - (PORT datab (1267:1267:1267) (1344:1344:1344)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (655:655:655) (677:677:677)) + (PORT datac (792:792:792) (807:807:807)) + (PORT datad (957:957:957) (1033:1033:1033)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -33446,9 +31582,9 @@ (INSTANCE ula_\|video_\|vram_address\[9\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (964:964:964) (963:963:963)) + (PORT ena (820:820:820) (826:826:826)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33462,13 +31598,13 @@ (INSTANCE ula_\|video_\|vram_address\[10\]\~2) (DELAY (ABSOLUTE - (PORT dataa (990:990:990) (1077:1077:1077)) - (PORT datab (707:707:707) (784:784:784)) - (PORT datac (1217:1217:1217) (1309:1309:1309)) - (PORT datad (684:684:684) (763:763:763)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1251:1251:1251) (1338:1338:1338)) + (PORT datab (981:981:981) (1058:1058:1058)) + (PORT datac (980:980:980) (1051:1051:1051)) + (PORT datad (285:285:285) (369:369:369)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -33478,11 +31614,11 @@ (INSTANCE ula_\|video_\|vram_address\[10\]\~3) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (914:914:914)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datad (685:685:685) (767:767:767)) + (PORT dataa (612:612:612) (644:644:644)) + (PORT datab (1014:1014:1014) (1089:1089:1089)) + (PORT datad (173:173:173) (198:198:198)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -33493,7 +31629,7 @@ (INSTANCE ula_\|video_\|vram_address\[10\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -33507,9 +31643,9 @@ (INSTANCE ula_\|video_\|Selector3\~0) (DELAY (ABSOLUTE - (PORT datac (1236:1236:1236) (1306:1306:1306)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (613:613:613) (639:639:639)) + (PORT datad (958:958:958) (1031:1031:1031)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -33519,9 +31655,9 @@ (INSTANCE ula_\|video_\|vram_address\[11\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (964:964:964) (963:963:963)) + (PORT ena (820:820:820) (826:826:826)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33535,10 +31671,10 @@ (INSTANCE ula_\|video_\|Selector2\~0) (DELAY (ABSOLUTE - (PORT datab (1265:1265:1265) (1339:1339:1339)) - (PORT datac (180:180:180) (217:217:217)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (618:618:618) (638:638:638)) + (PORT datad (957:957:957) (1029:1029:1029)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -33547,9 +31683,9 @@ (INSTANCE ula_\|video_\|vram_address\[12\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (964:964:964) (963:963:963)) + (PORT ena (820:820:820) (826:826:826)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -33558,2335 +31694,13 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1437:1437:1437) (1490:1490:1490)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1070:1070:1070) (1169:1169:1169)) - (PORT d[1] (1681:1681:1681) (1780:1780:1780)) - (PORT d[2] (3943:3943:3943) (4306:4306:4306)) - (PORT d[3] (3370:3370:3370) (3607:3607:3607)) - (PORT d[4] (2195:2195:2195) (2366:2366:2366)) - (PORT d[5] (1291:1291:1291) (1347:1347:1347)) - (PORT d[6] (1159:1159:1159) (1198:1198:1198)) - (PORT d[7] (2411:2411:2411) (2549:2549:2549)) - (PORT d[8] (1300:1300:1300) (1344:1344:1344)) - (PORT d[9] (4657:4657:4657) (4813:4813:4813)) - (PORT d[10] (1346:1346:1346) (1405:1405:1405)) - (PORT d[11] (3870:3870:3870) (4133:4133:4133)) - (PORT d[12] (2405:2405:2405) (2521:2521:2521)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1236:1236:1236) (1201:1201:1201)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (2344:2344:2344) (2351:2351:2351)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1811:1811:1811)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2793:2793:2793) (2865:2865:2865)) - (PORT clk (1824:1824:1824) (1817:1817:1817)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1890:1890:1890) (1975:1975:1975)) - (PORT d[1] (1853:1853:1853) (1980:1980:1980)) - (PORT d[2] (1877:1877:1877) (1979:1979:1979)) - (PORT d[3] (1831:1831:1831) (1958:1958:1958)) - (PORT d[4] (1887:1887:1887) (2020:2020:2020)) - (PORT d[5] (1789:1789:1789) (1891:1891:1891)) - (PORT d[6] (1827:1827:1827) (1976:1976:1976)) - (PORT d[7] (1903:1903:1903) (2052:2052:2052)) - (PORT d[8] (1937:1937:1937) (2078:2078:2078)) - (PORT d[9] (2001:2001:2001) (2080:2080:2080)) - (PORT d[10] (1913:1913:1913) (2004:2004:2004)) - (PORT d[11] (1995:1995:1995) (2079:2079:2079)) - (PORT d[12] (1853:1853:1853) (1938:1938:1938)) - (PORT clk (1820:1820:1820) (1813:1813:1813)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1817:1817:1817)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (1183:1183:1183) (1232:1232:1232)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1539:1539:1539)) - (PORT asdata (1229:1229:1229) (1298:1298:1298)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2734:2734:2734) (2902:2902:2902)) - (PORT d[1] (1554:1554:1554) (1624:1624:1624)) - (PORT d[2] (2906:2906:2906) (3199:3199:3199)) - (PORT d[3] (2577:2577:2577) (2806:2806:2806)) - (PORT d[4] (2301:2301:2301) (2516:2516:2516)) - (PORT d[5] (2281:2281:2281) (2370:2370:2370)) - (PORT d[6] (2395:2395:2395) (2549:2549:2549)) - (PORT d[7] (5032:5032:5032) (5213:5213:5213)) - (PORT d[8] (3015:3015:3015) (3200:3200:3200)) - (PORT d[9] (3266:3266:3266) (3388:3388:3388)) - (PORT d[10] (2595:2595:2595) (2786:2786:2786)) - (PORT d[11] (2498:2498:2498) (2719:2719:2719)) - (PORT d[12] (3618:3618:3618) (3771:3771:3771)) - (PORT clk (1869:1869:1869) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1894:1894:1894)) - (PORT d[0] (1977:1977:1977) (2015:2015:2015)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1857:1857:1857)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1020:1020:1020)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (756:756:756) (807:807:807)) - (PORT d[1] (3091:3091:3091) (3354:3354:3354)) - (PORT d[2] (2216:2216:2216) (2321:2321:2321)) - (PORT d[3] (1007:1007:1007) (1081:1081:1081)) - (PORT d[4] (3106:3106:3106) (3333:3333:3333)) - (PORT d[5] (952:952:952) (1005:1005:1005)) - (PORT d[6] (2909:2909:2909) (3077:3077:3077)) - (PORT d[7] (2643:2643:2643) (2771:2771:2771)) - (PORT d[8] (4036:4036:4036) (4289:4289:4289)) - (PORT d[9] (2994:2994:2994) (3081:3081:3081)) - (PORT d[10] (2883:2883:2883) (3100:3100:3100)) - (PORT d[11] (2224:2224:2224) (2440:2440:2440)) - (PORT d[12] (2093:2093:2093) (2182:2182:2182)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1875:1875:1875)) - (PORT d[0] (2328:2328:2328) (2271:2271:2271)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (262:262:262) (329:329:329)) - (PORT datab (240:240:240) (294:294:294)) - (PORT datac (233:233:233) (280:280:280)) - (PORT datad (1159:1159:1159) (1234:1234:1234)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1825:1825:1825) (1888:1888:1888)) - (PORT clk (1869:1869:1869) (1895:1895:1895)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2488:2488:2488) (2649:2649:2649)) - (PORT d[1] (1342:1342:1342) (1422:1422:1422)) - (PORT d[2] (3064:3064:3064) (3386:3386:3386)) - (PORT d[3] (2682:2682:2682) (2923:2923:2923)) - (PORT d[4] (2589:2589:2589) (2802:2802:2802)) - (PORT d[5] (2084:2084:2084) (2214:2214:2214)) - (PORT d[6] (2079:2079:2079) (2216:2216:2216)) - (PORT d[7] (2688:2688:2688) (2860:2860:2860)) - (PORT d[8] (2089:2089:2089) (2206:2206:2206)) - (PORT d[9] (3755:3755:3755) (3873:3873:3873)) - (PORT d[10] (2252:2252:2252) (2440:2440:2440)) - (PORT d[11] (3088:3088:3088) (3296:3296:3296)) - (PORT d[12] (3369:3369:3369) (3511:3511:3511)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2040:2040:2040) (2036:2036:2036)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (PORT d[0] (3206:3206:3206) (3169:3169:3169)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1820:1820:1820)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3716:3716:3716) (3827:3827:3827)) - (PORT clk (1834:1834:1834) (1826:1826:1826)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1906:1906:1906) (1974:1974:1974)) - (PORT d[1] (1975:1975:1975) (2071:2071:2071)) - (PORT d[2] (1843:1843:1843) (1910:1910:1910)) - (PORT d[3] (1921:1921:1921) (2093:2093:2093)) - (PORT d[4] (1842:1842:1842) (1948:1948:1948)) - (PORT d[5] (2185:2185:2185) (2276:2276:2276)) - (PORT d[6] (2004:2004:2004) (2062:2062:2062)) - (PORT d[7] (1990:1990:1990) (2045:2045:2045)) - (PORT d[8] (2083:2083:2083) (2151:2151:2151)) - (PORT d[9] (1957:1957:1957) (2011:2011:2011)) - (PORT d[10] (2156:2156:2156) (2259:2259:2259)) - (PORT d[11] (2033:2033:2033) (2085:2085:2085)) - (PORT d[12] (1888:1888:1888) (1962:1962:1962)) - (PORT clk (1830:1830:1830) (1822:1822:1822)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1834:1834:1834) (1826:1826:1826)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1822:1822:1822)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1185:1185:1185) (1235:1235:1235)) - (PORT datab (293:293:293) (387:387:387)) - (PORT datac (906:906:906) (923:923:923)) - (PORT datad (1542:1542:1542) (1632:1632:1632)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1213:1213:1213) (1276:1276:1276)) - (PORT datab (296:296:296) (391:391:391)) - (PORT datac (1537:1537:1537) (1619:1619:1619)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (944:944:944) (999:999:999)) - (PORT datab (973:973:973) (1028:1028:1028)) - (PORT datac (1048:1048:1048) (1061:1061:1061)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1836:1836:1836) (1933:1933:1933)) - (PORT datab (2139:2139:2139) (2274:2274:2274)) - (PORT datac (3267:3267:3267) (3490:3490:3490)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (768:768:768)) - (PORT datab (342:342:342) (371:371:371)) - (PORT datac (690:690:690) (731:731:731)) - (PORT datad (871:871:871) (885:885:885)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (748:748:748)) - (PORT datab (1200:1200:1200) (1287:1287:1287)) - (PORT datac (381:381:381) (440:440:440)) - (PORT datad (602:602:602) (624:624:624)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (1340:1340:1340) (1421:1421:1421)) - (PORT datab (1264:1264:1264) (1348:1348:1348)) - (PORT datac (809:809:809) (828:828:828)) - (PORT datad (567:567:567) (581:581:581)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1231:1231:1231)) - (PORT datab (1076:1076:1076) (1145:1145:1145)) - (PORT datac (1175:1175:1175) (1291:1291:1291)) - (PORT datad (1050:1050:1050) (1070:1070:1070)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (820:820:820)) - (PORT datab (1074:1074:1074) (1145:1145:1145)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (1034:1034:1034) (1031:1031:1031)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1249:1249:1249) (1323:1323:1323)) - (PORT datac (1163:1163:1163) (1182:1182:1182)) - (PORT datad (1015:1015:1015) (1049:1049:1049)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1643:1643:1643) (1675:1675:1675)) - (PORT datab (1036:1036:1036) (1059:1059:1059)) - (PORT datac (719:719:719) (796:796:796)) - (PORT datad (682:682:682) (735:735:735)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1181:1181:1181) (1193:1193:1193)) - (PORT datab (762:762:762) (777:777:777)) - (PORT datac (178:178:178) (214:214:214)) - (PORT datad (1218:1218:1218) (1303:1303:1303)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (616:616:616)) - (PORT datac (766:766:766) (785:785:785)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (913:913:913) (996:996:996)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (614:614:614) (662:662:662)) - (PORT datad (645:645:645) (672:672:672)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (742:742:742)) - (PORT datab (1114:1114:1114) (1131:1131:1131)) - (PORT datac (603:603:603) (638:638:638)) - (PORT datad (1017:1017:1017) (1024:1024:1024)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (1444:1444:1444) (1523:1523:1523)) - (PORT datab (1519:1519:1519) (1501:1501:1501)) - (PORT datac (1269:1269:1269) (1301:1301:1301)) - (PORT datad (1376:1376:1376) (1419:1419:1419)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (375:375:375) (412:412:412)) - (PORT datab (1193:1193:1193) (1257:1257:1257)) - (PORT datac (930:930:930) (1008:1008:1008)) - (PORT datad (1537:1537:1537) (1606:1606:1606)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT datac (286:286:286) (385:385:385)) - (PORT datad (290:290:290) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (462:462:462)) - (PORT datab (1365:1365:1365) (1430:1430:1430)) - (PORT datac (1361:1361:1361) (1424:1424:1424)) - (PORT datad (2078:2078:2078) (2122:2122:2122)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1155:1155:1155)) - (PORT datab (944:944:944) (984:984:984)) - (PORT datac (2031:2031:2031) (2073:2073:2073)) - (PORT datad (1173:1173:1173) (1234:1234:1234)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1115:1115:1115)) - (PORT datab (874:874:874) (914:914:914)) - (PORT datac (1269:1269:1269) (1301:1301:1301)) - (PORT datad (350:350:350) (369:369:369)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1410:1410:1410) (1467:1467:1467)) - (PORT datab (1304:1304:1304) (1363:1363:1363)) - (PORT datac (287:287:287) (385:385:385)) - (PORT datad (294:294:294) (384:384:384)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1243:1243:1243) (1347:1347:1347)) - (PORT datac (708:708:708) (786:786:786)) - (PORT datad (819:819:819) (851:851:851)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (571:571:571)) - (PORT datab (939:939:939) (1002:1002:1002)) - (PORT datac (1520:1520:1520) (1563:1563:1563)) - (PORT datad (617:617:617) (630:630:630)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (674:674:674)) - (PORT datab (1172:1172:1172) (1177:1177:1177)) - (PORT datac (559:559:559) (583:583:583)) - (PORT datad (1734:1734:1734) (1803:1803:1803)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1494:1494:1494) (1554:1554:1554)) - (PORT datab (1433:1433:1433) (1472:1472:1472)) - (PORT datac (645:645:645) (691:691:691)) - (PORT datad (1363:1363:1363) (1384:1384:1384)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (1286:1286:1286) (1330:1330:1330)) - (PORT datac (1601:1601:1601) (1583:1583:1583)) - (PORT datad (184:184:184) (213:213:213)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (585:585:585)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (1286:1286:1286) (1300:1300:1300)) - (PORT datad (793:793:793) (804:804:804)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (715:715:715)) - (PORT datab (613:613:613) (671:671:671)) - (PORT datac (1315:1315:1315) (1341:1341:1341)) - (PORT datad (786:786:786) (821:821:821)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1460:1460:1460) (1461:1461:1461)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|mwr_wr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (247:247:247) (331:331:331)) - (PORT datac (1001:1001:1001) (1001:1001:1001)) - (PORT datad (200:200:200) (228:228:228)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (2438:2438:2438) (2603:2603:2603)) - (PORT datab (1532:1532:1532) (1590:1590:1590)) - (PORT datac (3031:3031:3031) (3277:3277:3277)) - (PORT datad (1641:1641:1641) (1714:1714:1714)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1916:1916:1916) (1978:1978:1978)) - (PORT clk (1852:1852:1852) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1873:1873:1873) (1997:1997:1997)) - (PORT d[1] (2418:2418:2418) (2642:2642:2642)) - (PORT d[2] (2358:2358:2358) (2525:2525:2525)) - (PORT d[3] (1766:1766:1766) (1856:1856:1856)) - (PORT d[4] (2228:2228:2228) (2395:2395:2395)) - (PORT d[5] (4867:4867:4867) (5202:5202:5202)) - (PORT d[6] (2286:2286:2286) (2405:2405:2405)) - (PORT d[7] (2145:2145:2145) (2181:2181:2181)) - (PORT d[8] (3063:3063:3063) (3256:3256:3256)) - (PORT d[9] (2860:2860:2860) (2986:2986:2986)) - (PORT d[10] (1957:1957:1957) (2129:2129:2129)) - (PORT d[11] (2115:2115:2115) (2253:2253:2253)) - (PORT d[12] (1326:1326:1326) (1336:1336:1336)) - (PORT clk (1849:1849:1849) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1997:1997:1997) (2001:2001:2001)) - (PORT clk (1849:1849:1849) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1881:1881:1881)) - (PORT d[0] (2598:2598:2598) (2648:2648:2648)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2221:2221:2221) (2290:2290:2290)) - (PORT clk (1848:1848:1848) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2230:2230:2230) (2387:2387:2387)) - (PORT d[1] (2677:2677:2677) (2888:2888:2888)) - (PORT d[2] (2332:2332:2332) (2508:2508:2508)) - (PORT d[3] (3861:3861:3861) (4222:4222:4222)) - (PORT d[4] (2213:2213:2213) (2361:2361:2361)) - (PORT d[5] (4592:4592:4592) (4931:4931:4931)) - (PORT d[6] (2250:2250:2250) (2346:2346:2346)) - (PORT d[7] (2186:2186:2186) (2246:2246:2246)) - (PORT d[8] (3077:3077:3077) (3254:3254:3254)) - (PORT d[9] (2820:2820:2820) (2958:2958:2958)) - (PORT d[10] (2287:2287:2287) (2483:2483:2483)) - (PORT d[11] (2419:2419:2419) (2579:2579:2579)) - (PORT d[12] (1592:1592:1592) (1618:1618:1618)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2142:2142:2142) (2155:2155:2155)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (PORT d[0] (2736:2736:2736) (2801:2801:2801)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1808:1808:1808) (1836:1836:1836)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (449:449:449)) - (PORT datab (1559:1559:1559) (1659:1659:1659)) - (PORT datac (1154:1154:1154) (1232:1232:1232)) - (PORT datad (1236:1236:1236) (1282:1282:1282)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1516:1516:1516) (1557:1557:1557)) - (PORT clk (1862:1862:1862) (1890:1890:1890)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1349:1349:1349) (1426:1426:1426)) - (PORT d[1] (3088:3088:3088) (3380:3380:3380)) - (PORT d[2] (1614:1614:1614) (1742:1742:1742)) - (PORT d[3] (716:716:716) (752:752:752)) - (PORT d[4] (690:690:690) (712:712:712)) - (PORT d[5] (1567:1567:1567) (1646:1646:1646)) - (PORT d[6] (2951:2951:2951) (3127:3127:3127)) - (PORT d[7] (2306:2306:2306) (2405:2405:2405)) - (PORT d[8] (3749:3749:3749) (3997:3997:3997)) - (PORT d[9] (683:683:683) (703:703:703)) - (PORT d[10] (2557:2557:2557) (2734:2734:2734)) - (PORT d[11] (2221:2221:2221) (2437:2437:2437)) - (PORT d[12] (2651:2651:2651) (2759:2759:2759)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2155:2155:2155) (2125:2125:2125)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1862:1862:1862) (1890:1890:1890)) - (PORT d[0] (2528:2528:2528) (2531:2531:2531)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1891:1891:1891)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1891:1891:1891)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1891:1891:1891)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1891:1891:1891)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1849:1849:1849)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1007:1007:1007) (1012:1012:1012)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1013:1013:1013)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1013:1013:1013)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1013:1013:1013)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2782:2782:2782) (2893:2893:2893)) - (PORT clk (1847:1847:1847) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3769:3769:3769) (4062:4062:4062)) - (PORT d[1] (2110:2110:2110) (2313:2313:2313)) - (PORT d[2] (4028:4028:4028) (4262:4262:4262)) - (PORT d[3] (3288:3288:3288) (3576:3576:3576)) - (PORT d[4] (2875:2875:2875) (3086:3086:3086)) - (PORT d[5] (3978:3978:3978) (4258:4258:4258)) - (PORT d[6] (1674:1674:1674) (1737:1737:1737)) - (PORT d[7] (3086:3086:3086) (3210:3210:3210)) - (PORT d[8] (2487:2487:2487) (2660:2660:2660)) - (PORT d[9] (2841:2841:2841) (2939:2939:2939)) - (PORT d[10] (2619:2619:2619) (2772:2772:2772)) - (PORT d[11] (1523:1523:1523) (1634:1634:1634)) - (PORT d[12] (2196:2196:2196) (2275:2275:2275)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1414:1414:1414) (1358:1358:1358)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (PORT d[0] (1912:1912:1912) (1887:1887:1887)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (450:450:450)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1920:1920:1920) (1912:1912:1912)) - (PORT datad (927:927:927) (948:948:948)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (763:763:763) (795:795:795)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (752:752:752) (807:807:807)) - (PORT d[1] (1980:1980:1980) (2100:2100:2100)) - (PORT d[2] (1265:1265:1265) (1350:1350:1350)) - (PORT d[3] (3691:3691:3691) (3938:3938:3938)) - (PORT d[4] (2852:2852:2852) (3055:3055:3055)) - (PORT d[5] (993:993:993) (1050:1050:1050)) - (PORT d[6] (3172:3172:3172) (3392:3392:3392)) - (PORT d[7] (2679:2679:2679) (2847:2847:2847)) - (PORT d[8] (992:992:992) (1031:1031:1031)) - (PORT d[9] (2694:2694:2694) (2778:2778:2778)) - (PORT d[10] (1024:1024:1024) (1049:1049:1049)) - (PORT d[11] (2536:2536:2536) (2760:2760:2760)) - (PORT d[12] (2088:2088:2088) (2176:2176:2176)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (925:925:925) (873:873:873)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1492:1492:1492) (1454:1454:1454)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1812:1812:1812)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2181:2181:2181) (2249:2249:2249)) - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1889:1889:1889) (2010:2010:2010)) - (PORT d[1] (1977:1977:1977) (2066:2066:2066)) - (PORT d[2] (1895:1895:1895) (2016:2016:2016)) - (PORT d[3] (1998:1998:1998) (2161:2161:2161)) - (PORT d[4] (1954:1954:1954) (2048:2048:2048)) - (PORT d[5] (1860:1860:1860) (1976:1976:1976)) - (PORT d[6] (1803:1803:1803) (1917:1917:1917)) - (PORT d[7] (1874:1874:1874) (2004:2004:2004)) - (PORT d[8] (1905:1905:1905) (2030:2030:2030)) - (PORT d[9] (1897:1897:1897) (1993:1993:1993)) - (PORT d[10] (1919:1919:1919) (2028:2028:2028)) - (PORT d[11] (2055:2055:2055) (2124:2124:2124)) - (PORT d[12] (1883:1883:1883) (1964:1964:1964)) - (PORT clk (1821:1821:1821) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3781:3781:3781) (4085:4085:4085)) - (PORT d[1] (2394:2394:2394) (2582:2582:2582)) - (PORT d[2] (4316:4316:4316) (4556:4556:4556)) - (PORT d[3] (3594:3594:3594) (3934:3934:3934)) - (PORT d[4] (3187:3187:3187) (3407:3407:3407)) - (PORT d[5] (3991:3991:3991) (4287:4287:4287)) - (PORT d[6] (2552:2552:2552) (2688:2688:2688)) - (PORT d[7] (2791:2791:2791) (2891:2891:2891)) - (PORT d[8] (3649:3649:3649) (3866:3866:3866)) - (PORT d[9] (2181:2181:2181) (2268:2268:2268)) - (PORT d[10] (1576:1576:1576) (1657:1657:1657)) - (PORT d[11] (1540:1540:1540) (1655:1655:1655)) - (PORT d[12] (2184:2184:2184) (2245:2245:2245)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1874:1874:1874)) - (PORT d[0] (1287:1287:1287) (1295:1295:1295)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (757:757:757) (793:793:793)) - (PORT d[1] (681:681:681) (707:707:707)) - (PORT d[2] (1594:1594:1594) (1676:1676:1676)) - (PORT d[3] (3990:3990:3990) (4271:4271:4271)) - (PORT d[4] (2822:2822:2822) (3033:3033:3033)) - (PORT d[5] (669:669:669) (704:704:704)) - (PORT d[6] (3210:3210:3210) (3376:3376:3376)) - (PORT d[7] (2624:2624:2624) (2763:2763:2763)) - (PORT d[8] (994:994:994) (1014:1014:1014)) - (PORT d[9] (2605:2605:2605) (2661:2661:2661)) - (PORT d[10] (975:975:975) (995:995:995)) - (PORT d[11] (1466:1466:1466) (1525:1525:1525)) - (PORT d[12] (1745:1745:1745) (1803:1803:1803)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1882:1882:1882)) - (PORT d[0] (2643:2643:2643) (2567:2567:2567)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (737:737:737) (777:777:777)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (1548:1548:1548) (1620:1620:1620)) + (PORT clk (1864:1864:1864) (1891:1891:1891)) ) ) (TIMINGCHECK @@ -35898,20 +31712,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1086:1086:1086) (1161:1161:1161)) - (PORT d[1] (1972:1972:1972) (2085:2085:2085)) - (PORT d[2] (1308:1308:1308) (1401:1401:1401)) - (PORT d[3] (3687:3687:3687) (3934:3934:3934)) - (PORT d[4] (2501:2501:2501) (2677:2677:2677)) - (PORT d[5] (975:975:975) (1031:1031:1031)) - (PORT d[6] (899:899:899) (921:921:921)) - (PORT d[7] (2702:2702:2702) (2874:2874:2874)) - (PORT d[8] (1184:1184:1184) (1215:1215:1215)) - (PORT d[9] (2673:2673:2673) (2757:2757:2757)) - (PORT d[10] (1305:1305:1305) (1343:1343:1343)) - (PORT d[11] (2552:2552:2552) (2802:2802:2802)) - (PORT d[12] (2066:2066:2066) (2151:2151:2151)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (2599:2599:2599) (2697:2697:2697)) + (PORT d[1] (2358:2358:2358) (2589:2589:2589)) + (PORT d[2] (2326:2326:2326) (2476:2476:2476)) + (PORT d[3] (1990:1990:1990) (2063:2063:2063)) + (PORT d[4] (2926:2926:2926) (3182:3182:3182)) + (PORT d[5] (2089:2089:2089) (2294:2294:2294)) + (PORT d[6] (1566:1566:1566) (1667:1667:1667)) + (PORT d[7] (1626:1626:1626) (1711:1711:1711)) + (PORT d[8] (2773:2773:2773) (3020:3020:3020)) + (PORT d[9] (2077:2077:2077) (2186:2186:2186)) + (PORT d[10] (2124:2124:2124) (2247:2247:2247)) + (PORT d[11] (3187:3187:3187) (3328:3328:3328)) + (PORT d[12] (2201:2201:2201) (2298:2298:2298)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) ) ) (TIMINGCHECK @@ -35923,8 +31737,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1185:1185:1185) (1137:1137:1137)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (2768:2768:2768) (2740:2740:2740)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) ) ) (TIMINGCHECK @@ -35936,8 +31750,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2364:2364:2364) (2335:2335:2335)) + (PORT clk (1864:1864:1864) (1891:1891:1891)) + (PORT d[0] (2876:2876:2876) (2827:2827:2827)) ) ) ) @@ -35946,7 +31760,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1865:1865:1865) (1892:1892:1892)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -35956,7 +31770,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1865:1865:1865) (1892:1892:1892)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -35966,7 +31780,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1865:1865:1865) (1892:1892:1892)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -35976,7 +31790,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1865:1865:1865) (1892:1892:1892)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -35984,8165 +31798,6 @@ (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2801:2801:2801) (2875:2875:2875)) - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1884:1884:1884) (1984:1984:1984)) - (PORT d[1] (1973:1973:1973) (2056:2056:2056)) - (PORT d[2] (1910:1910:1910) (2035:2035:2035)) - (PORT d[3] (1986:1986:1986) (2169:2169:2169)) - (PORT d[4] (1904:1904:1904) (1986:1986:1986)) - (PORT d[5] (1829:1829:1829) (1940:1940:1940)) - (PORT d[6] (1825:1825:1825) (1963:1963:1963)) - (PORT d[7] (1843:1843:1843) (1968:1968:1968)) - (PORT d[8] (1952:1952:1952) (2098:2098:2098)) - (PORT d[9] (2014:2014:2014) (2111:2111:2111)) - (PORT d[10] (1915:1915:1915) (1994:1994:1994)) - (PORT d[11] (2051:2051:2051) (2121:2121:2121)) - (PORT d[12] (1934:1934:1934) (2039:2039:2039)) - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1815:1815:1815)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1183:1183:1183) (1234:1234:1234)) - (PORT datab (632:632:632) (641:641:641)) - (PORT datad (956:956:956) (963:963:963)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (917:917:917)) - (PORT datab (752:752:752) (824:824:824)) - (PORT datac (1032:1032:1032) (1031:1031:1031)) - (PORT datad (600:600:600) (616:616:616)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (775:775:775) (776:776:776)) - (PORT datab (883:883:883) (931:931:931)) - (PORT datac (1490:1490:1490) (1569:1569:1569)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE ula_\|pll_\|altpll_component\|auto_generated\|wire_pll1_clk\[2\]\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1896:1896:1896) (1878:1878:1878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (1341:1341:1341) (1428:1428:1428)) - (PORT datab (1265:1265:1265) (1351:1351:1351)) - (PORT datac (816:816:816) (842:842:842)) - (PORT datad (819:819:819) (827:827:827)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT datac (942:942:942) (1017:1017:1017)) - (PORT datad (1108:1108:1108) (1175:1175:1175)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (947:947:947) (1017:1017:1017)) - (PORT datab (916:916:916) (981:981:981)) - (PORT datac (804:804:804) (809:809:809)) - (PORT datad (680:680:680) (747:747:747)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (986:986:986) (1071:1071:1071)) - (PORT datab (707:707:707) (788:788:788)) - (PORT datac (190:190:190) (233:233:233)) - (PORT datad (197:197:197) (232:232:232)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (626:626:626)) - (PORT datad (716:716:716) (794:794:794)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT datab (981:981:981) (1050:1050:1050)) - (PORT datac (1154:1154:1154) (1218:1218:1218)) - (PORT datad (688:688:688) (763:763:763)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (1241:1241:1241) (1308:1308:1308)) - (PORT datab (471:471:471) (547:547:547)) - (PORT datac (1125:1125:1125) (1181:1181:1181)) - (PORT datad (936:936:936) (997:997:997)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~135) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1194:1194:1194)) - (PORT datab (1326:1326:1326) (1345:1345:1345)) - (PORT datad (319:319:319) (329:329:329)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (400:400:400)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (963:963:963)) - (PORT datab (240:240:240) (321:321:321)) - (PORT datac (863:863:863) (902:902:902)) - (PORT datad (550:550:550) (589:589:589)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (569:569:569)) - (PORT datac (930:930:930) (1000:1000:1000)) - (PORT datad (578:578:578) (583:583:583)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (829:829:829)) - (PORT datab (950:950:950) (1028:1028:1028)) - (PORT datac (919:919:919) (975:975:975)) - (PORT datad (578:578:578) (594:594:594)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (1031:1031:1031)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (799:799:799)) - (PORT datab (899:899:899) (976:976:976)) - (PORT datac (955:955:955) (1013:1013:1013)) - (PORT datad (920:920:920) (989:989:989)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (948:948:948) (1028:1028:1028)) - (PORT datab (950:950:950) (1028:1028:1028)) - (PORT datad (408:408:408) (475:475:475)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1050:1050:1050)) - (PORT datab (1191:1191:1191) (1247:1247:1247)) - (PORT datac (919:919:919) (978:978:978)) - (PORT datad (923:923:923) (989:989:989)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (224:224:224) (264:264:264)) - (PORT datad (198:198:198) (224:224:224)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (867:867:867)) - (PORT datab (242:242:242) (323:323:323)) - (PORT datac (213:213:213) (289:289:289)) - (PORT datad (2259:2259:2259) (2298:2298:2298)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (935:935:935) (1007:1007:1007)) - (PORT datab (974:974:974) (1034:1034:1034)) - (PORT datac (953:953:953) (1014:1014:1014)) - (PORT datad (853:853:853) (928:928:928)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (722:722:722) (792:792:792)) - (PORT datac (938:938:938) (1013:1013:1013)) - (PORT datad (1106:1106:1106) (1179:1179:1179)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (283:283:283) (376:376:376)) - (PORT datab (967:967:967) (1035:1035:1035)) - (PORT datad (555:555:555) (559:559:559)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~136) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (932:932:932)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datac (937:937:937) (1005:1005:1005)) - (PORT datad (1121:1121:1121) (1176:1176:1176)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (672:672:672)) - (PORT datab (581:581:581) (600:600:600)) - (PORT datac (935:935:935) (1002:1002:1002)) - (PORT datad (1118:1118:1118) (1174:1174:1174)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (541:541:541)) - (PORT datab (568:568:568) (583:583:583)) - (PORT datac (1188:1188:1188) (1247:1247:1247)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~137) - (DELAY - (ABSOLUTE - (PORT dataa (452:452:452) (524:524:524)) - (PORT datab (694:694:694) (763:763:763)) - (PORT datac (912:912:912) (972:972:972)) - (PORT datad (922:922:922) (987:987:987)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (581:581:581)) - (PORT datab (649:649:649) (670:670:670)) - (PORT datad (649:649:649) (674:674:674)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT datab (675:675:675) (743:743:743)) - (PORT datac (660:660:660) (730:730:730)) - (PORT datad (1140:1140:1140) (1181:1181:1181)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (760:760:760)) - (PORT datab (908:908:908) (924:924:924)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (704:704:704)) - (PORT datab (1918:1918:1918) (1961:1961:1961)) - (PORT datac (881:881:881) (922:922:922)) - (PORT datad (689:689:689) (743:743:743)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~115) - (DELAY - (ABSOLUTE - (PORT dataa (1223:1223:1223) (1287:1287:1287)) - (PORT datab (417:417:417) (492:492:492)) - (PORT datac (934:934:934) (1000:1000:1000)) - (PORT datad (1117:1117:1117) (1171:1171:1171)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (681:681:681)) - (PORT datab (351:351:351) (380:380:380)) - (PORT datac (252:252:252) (337:337:337)) - (PORT datad (849:849:849) (909:909:909)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~139) - (DELAY - (ABSOLUTE - (PORT dataa (533:533:533) (560:560:560)) - (PORT datab (686:686:686) (713:713:713)) - (PORT datad (430:430:430) (499:499:499)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (1005:1005:1005)) - (PORT datab (968:968:968) (1035:1035:1035)) - (PORT datac (396:396:396) (475:475:475)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~140) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (753:753:753)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datad (353:353:353) (368:368:368)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) - (DELAY - (ABSOLUTE - (PORT datab (970:970:970) (1042:1042:1042)) - (PORT datac (615:615:615) (685:685:685)) - (PORT datad (662:662:662) (730:730:730)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT datab (641:641:641) (702:702:702)) - (PORT datad (618:618:618) (687:687:687)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (1221:1221:1221) (1287:1287:1287)) - (PORT datab (797:797:797) (812:812:812)) - (PORT datac (605:605:605) (633:633:633)) - (PORT datad (621:621:621) (636:636:636)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (541:541:541)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (251:251:251) (336:336:336)) - (PORT datad (649:649:649) (670:670:670)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (259:259:259)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (454:454:454)) - (PORT datab (378:378:378) (449:449:449)) - (PORT datac (662:662:662) (712:712:712)) - (PORT datad (1308:1308:1308) (1337:1337:1337)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (587:587:587)) - (PORT datab (858:858:858) (870:870:870)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (605:605:605) (619:619:619)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1686:1686:1686) (1771:1771:1771)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3156:3156:3156) (3412:3412:3412)) - (PORT d[1] (2086:2086:2086) (2249:2249:2249)) - (PORT d[2] (2277:2277:2277) (2501:2501:2501)) - (PORT d[3] (2655:2655:2655) (2916:2916:2916)) - (PORT d[4] (2545:2545:2545) (2725:2725:2725)) - (PORT d[5] (3385:3385:3385) (3620:3620:3620)) - (PORT d[6] (2288:2288:2288) (2432:2432:2432)) - (PORT d[7] (3448:3448:3448) (3587:3587:3587)) - (PORT d[8] (2180:2180:2180) (2314:2314:2314)) - (PORT d[9] (2514:2514:2514) (2606:2606:2606)) - (PORT d[10] (1973:1973:1973) (2125:2125:2125)) - (PORT d[11] (1866:1866:1866) (2039:2039:2039)) - (PORT d[12] (2805:2805:2805) (2933:2933:2933)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2536:2536:2536) (2572:2572:2572)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2837:2837:2837) (2858:2858:2858)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2236:2236:2236) (2328:2328:2328)) - (PORT clk (1854:1854:1854) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3478:3478:3478) (3752:3752:3752)) - (PORT d[1] (2338:2338:2338) (2513:2513:2513)) - (PORT d[2] (3442:3442:3442) (3652:3652:3652)) - (PORT d[3] (2974:2974:2974) (3240:3240:3240)) - (PORT d[4] (2559:2559:2559) (2759:2759:2759)) - (PORT d[5] (3332:3332:3332) (3585:3585:3585)) - (PORT d[6] (1653:1653:1653) (1690:1690:1690)) - (PORT d[7] (3392:3392:3392) (3519:3519:3519)) - (PORT d[8] (2214:2214:2214) (2366:2366:2366)) - (PORT d[9] (3087:3087:3087) (3244:3244:3244)) - (PORT d[10] (2304:2304:2304) (2459:2459:2459)) - (PORT d[11] (1888:1888:1888) (2051:2051:2051)) - (PORT d[12] (2510:2510:2510) (2618:2618:2618)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2213:2213:2213) (2169:2169:2169)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (PORT d[0] (2987:2987:2987) (3061:3061:3061)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2325:2325:2325) (2449:2449:2449)) - (PORT clk (1859:1859:1859) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2821:2821:2821) (3028:3028:3028)) - (PORT d[1] (1761:1761:1761) (1901:1901:1901)) - (PORT d[2] (2589:2589:2589) (2822:2822:2822)) - (PORT d[3] (2293:2293:2293) (2500:2500:2500)) - (PORT d[4] (2233:2233:2233) (2385:2385:2385)) - (PORT d[5] (2754:2754:2754) (2940:2940:2940)) - (PORT d[6] (1973:1973:1973) (2089:2089:2089)) - (PORT d[7] (4338:4338:4338) (4519:4519:4519)) - (PORT d[8] (2439:2439:2439) (2603:2603:2603)) - (PORT d[9] (2832:2832:2832) (2960:2960:2960)) - (PORT d[10] (1943:1943:1943) (2072:2072:2072)) - (PORT d[11] (1888:1888:1888) (2044:2044:2044)) - (PORT d[12] (3386:3386:3386) (3561:3561:3561)) - (PORT clk (1856:1856:1856) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2461:2461:2461) (2505:2505:2505)) - (PORT clk (1856:1856:1856) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (PORT d[0] (2862:2862:2862) (2898:2898:2898)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1844:1844:1844)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1008:1008:1008)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1008:1008:1008)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2330:2330:2330) (2428:2428:2428)) - (PORT clk (1847:1847:1847) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3777:3777:3777) (4077:4077:4077)) - (PORT d[1] (2106:2106:2106) (2282:2282:2282)) - (PORT d[2] (4029:4029:4029) (4263:4263:4263)) - (PORT d[3] (3289:3289:3289) (3577:3577:3577)) - (PORT d[4] (3196:3196:3196) (3402:3402:3402)) - (PORT d[5] (4006:4006:4006) (4271:4271:4271)) - (PORT d[6] (1677:1677:1677) (1742:1742:1742)) - (PORT d[7] (2770:2770:2770) (2870:2870:2870)) - (PORT d[8] (2790:2790:2790) (2959:2959:2959)) - (PORT d[9] (1958:1958:1958) (2028:2028:2028)) - (PORT d[10] (1586:1586:1586) (1686:1686:1686)) - (PORT d[11] (1543:1543:1543) (1654:1654:1654)) - (PORT d[12] (2219:2219:2219) (2278:2278:2278)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2684:2684:2684) (2750:2750:2750)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (PORT d[0] (2795:2795:2795) (2869:2869:2869)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (454:454:454)) - (PORT datab (1807:1807:1807) (1871:1871:1871)) - (PORT datac (1164:1164:1164) (1244:1244:1244)) - (PORT datad (897:897:897) (902:902:902)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1644:1644:1644) (1680:1680:1680)) - (PORT datab (958:958:958) (1020:1020:1020)) - (PORT datac (1652:1652:1652) (1666:1666:1666)) - (PORT datad (1036:1036:1036) (1042:1042:1042)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (701:701:701) (747:747:747)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1101:1101:1101) (1196:1196:1196)) - (PORT d[1] (1660:1660:1660) (1757:1757:1757)) - (PORT d[2] (1572:1572:1572) (1662:1662:1662)) - (PORT d[3] (3352:3352:3352) (3609:3609:3609)) - (PORT d[4] (1935:1935:1935) (2121:2121:2121)) - (PORT d[5] (1245:1245:1245) (1290:1290:1290)) - (PORT d[6] (2884:2884:2884) (3078:3078:3078)) - (PORT d[7] (2644:2644:2644) (2789:2789:2789)) - (PORT d[8] (1335:1335:1335) (1404:1404:1404)) - (PORT d[9] (2946:2946:2946) (3033:3033:3033)) - (PORT d[10] (1319:1319:1319) (1372:1372:1372)) - (PORT d[11] (4115:4115:4115) (4370:4370:4370)) - (PORT d[12] (2424:2424:2424) (2536:2536:2536)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1770:1770:1770) (1755:1755:1755)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2353:2353:2353) (2374:2374:2374)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1812:1812:1812)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2801:2801:2801) (2863:2863:2863)) - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1878:1878:1878) (1981:1981:1981)) - (PORT d[1] (1942:1942:1942) (2016:2016:2016)) - (PORT d[2] (1879:1879:1879) (1981:1981:1981)) - (PORT d[3] (1937:1937:1937) (2126:2126:2126)) - (PORT d[4] (1929:1929:1929) (1985:1985:1985)) - (PORT d[5] (1847:1847:1847) (1943:1943:1943)) - (PORT d[6] (1878:1878:1878) (2040:2040:2040)) - (PORT d[7] (1835:1835:1835) (1939:1939:1939)) - (PORT d[8] (1985:1985:1985) (2141:2141:2141)) - (PORT d[9] (2009:2009:2009) (2101:2101:2101)) - (PORT d[10] (1921:1921:1921) (2031:2031:2031)) - (PORT d[11] (2034:2034:2034) (2104:2104:2104)) - (PORT d[12] (1855:1855:1855) (1959:1959:1959)) - (PORT clk (1821:1821:1821) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1819:1819:1819)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1076:1076:1076) (1125:1125:1125)) - (PORT d[1] (970:970:970) (1015:1015:1015)) - (PORT d[2] (1606:1606:1606) (1706:1706:1706)) - (PORT d[3] (3970:3970:3970) (4280:4280:4280)) - (PORT d[4] (2834:2834:2834) (3013:3013:3013)) - (PORT d[5] (986:986:986) (1022:1022:1022)) - (PORT d[6] (3210:3210:3210) (3401:3401:3401)) - (PORT d[7] (1156:1156:1156) (1173:1173:1173)) - (PORT d[8] (684:684:684) (705:705:705)) - (PORT d[9] (2371:2371:2371) (2428:2428:2428)) - (PORT d[10] (984:984:984) (1022:1022:1022)) - (PORT d[11] (1160:1160:1160) (1180:1180:1180)) - (PORT d[12] (2330:2330:2330) (2392:2392:2392)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (2568:2568:2568) (2644:2644:2644)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (772:772:772) (832:832:832)) - (PORT d[1] (1981:1981:1981) (2101:2101:2101)) - (PORT d[2] (1595:1595:1595) (1678:1678:1678)) - (PORT d[3] (3662:3662:3662) (3956:3956:3956)) - (PORT d[4] (2837:2837:2837) (3046:3046:3046)) - (PORT d[5] (994:994:994) (1048:1048:1048)) - (PORT d[6] (3173:3173:3173) (3369:3369:3369)) - (PORT d[7] (2355:2355:2355) (2498:2498:2498)) - (PORT d[8] (1008:1008:1008) (1031:1031:1031)) - (PORT d[9] (2661:2661:2661) (2723:2723:2723)) - (PORT d[10] (997:997:997) (1017:1017:1017)) - (PORT d[11] (1180:1180:1180) (1219:1219:1219)) - (PORT d[12] (2107:2107:2107) (2193:2193:2193)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (806:806:806) (831:831:831)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1563:1563:1563) (1673:1673:1673)) - (PORT clk (1870:1870:1870) (1897:1897:1897)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3010:3010:3010) (3153:3153:3153)) - (PORT d[1] (1389:1389:1389) (1482:1482:1482)) - (PORT d[2] (3335:3335:3335) (3662:3662:3662)) - (PORT d[3] (2633:2633:2633) (2845:2845:2845)) - (PORT d[4] (2624:2624:2624) (2835:2835:2835)) - (PORT d[5] (2096:2096:2096) (2244:2244:2244)) - (PORT d[6] (2314:2314:2314) (2459:2459:2459)) - (PORT d[7] (2921:2921:2921) (3086:3086:3086)) - (PORT d[8] (2997:2997:2997) (3182:3182:3182)) - (PORT d[9] (3518:3518:3518) (3626:3626:3626)) - (PORT d[10] (2557:2557:2557) (2764:2764:2764)) - (PORT d[11] (3049:3049:3049) (3278:3278:3278)) - (PORT d[12] (3354:3354:3354) (3501:3501:3501)) - (PORT clk (1867:1867:1867) (1893:1893:1893)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2046:2046:2046) (2047:2047:2047)) - (PORT clk (1867:1867:1867) (1893:1893:1893)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1897:1897:1897)) - (PORT d[0] (3234:3234:3234) (3180:3180:3180)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1822:1822:1822)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4219:4219:4219) (4349:4349:4349)) - (PORT clk (1835:1835:1835) (1828:1828:1828)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1848:1848:1848) (1928:1928:1928)) - (PORT d[1] (1917:1917:1917) (2024:2024:2024)) - (PORT d[2] (1801:1801:1801) (1863:1863:1863)) - (PORT d[3] (1926:1926:1926) (2102:2102:2102)) - (PORT d[4] (1854:1854:1854) (1944:1944:1944)) - (PORT d[5] (2062:2062:2062) (2141:2141:2141)) - (PORT d[6] (1926:1926:1926) (2012:2012:2012)) - (PORT d[7] (1860:1860:1860) (1913:1913:1913)) - (PORT d[8] (2063:2063:2063) (2165:2165:2165)) - (PORT d[9] (1974:1974:1974) (2023:2023:2023)) - (PORT d[10] (2136:2136:2136) (2259:2259:2259)) - (PORT d[11] (2097:2097:2097) (2159:2159:2159)) - (PORT d[12] (2054:2054:2054) (2156:2156:2156)) - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1828:1828:1828)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1827:1827:1827) (1824:1824:1824)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (375:375:375) (410:410:410)) - (PORT datab (670:670:670) (715:715:715)) - (PORT datac (999:999:999) (1090:1090:1090)) - (PORT datad (1438:1438:1438) (1506:1506:1506)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (917:917:917)) - (PORT datab (1031:1031:1031) (1121:1121:1121)) - (PORT datac (656:656:656) (672:672:672)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1502:1502:1502)) - (PORT datab (235:235:235) (279:279:279)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (2434:2434:2434) (2602:2602:2602)) - (PORT datab (1531:1531:1531) (1592:1592:1592)) - (PORT datac (3029:3029:3029) (3276:3276:3276)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (742:742:742) (811:811:811)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (209:209:209) (250:250:250)) - (PORT datad (540:540:540) (552:552:552)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1514:1514:1514) (1591:1591:1591)) - (PORT datab (1677:1677:1677) (1753:1753:1753)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|always0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2081:2081:2081) (2108:2108:2108)) - (PORT datab (3058:3058:3058) (3307:3307:3307)) - (PORT datac (2207:2207:2207) (2319:2319:2319)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|always0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2435:2435:2435) (2597:2597:2597)) - (PORT datab (1535:1535:1535) (1599:1599:1599)) - (PORT datac (3026:3026:3026) (3271:3271:3271)) - (PORT datad (171:171:171) (197:197:197)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|mclk_r\~0) - (DELAY - (ABSOLUTE - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1888:1888:1888) (1912:1912:1912)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (785:785:785)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~2) - (DELAY - (ABSOLUTE - (PORT datab (253:253:253) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) - (DELAY - (ABSOLUTE - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (176:176:176) (203:203:203)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1888:1888:1888) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (438:438:438) (506:506:506)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datac (304:304:304) (327:327:327)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1888:1888:1888) (1910:1910:1910)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~6) - (DELAY - (ABSOLUTE - (PORT datab (398:398:398) (468:468:468)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT datad (591:591:591) (603:603:603)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1887:1887:1887) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~8) - (DELAY - (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (277:277:277)) - (PORT datac (173:173:173) (206:206:206)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1888:1888:1888) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (468:468:468)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) - (DELAY - (ABSOLUTE - (PORT datac (317:317:317) (345:345:345)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1887:1887:1887) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~12) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (469:469:469)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) - (DELAY - (ABSOLUTE - (PORT datac (344:344:344) (371:371:371)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1887:1887:1887) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (487:487:487)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (345:345:345) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1887:1887:1887) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~16) - (DELAY - (ABSOLUTE - (PORT datab (675:675:675) (736:736:736)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) - (DELAY - (ABSOLUTE - (PORT datac (569:569:569) (588:588:588)) - (PORT datad (575:575:575) (582:582:582)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add0\~18) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (300:300:300)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) - (DELAY - (ABSOLUTE - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1888:1888:1888) (1911:1911:1911)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (466:466:466)) - (PORT datab (249:249:249) (332:332:332)) - (PORT datac (386:386:386) (448:448:448)) - (PORT datad (636:636:636) (694:694:694)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (509:509:509)) - (PORT datab (392:392:392) (463:463:463)) - (PORT datac (365:365:365) (426:426:426)) - (PORT datad (223:223:223) (294:294:294)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (249:249:249) (333:333:333)) - (PORT datac (667:667:667) (742:742:742)) - (PORT datad (310:310:310) (330:330:330)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (248:248:248) (334:334:334)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (253:253:253) (338:338:338)) - (PORT datac (225:225:225) (305:305:305)) - (PORT datad (227:227:227) (299:299:299)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) - (DELAY - (ABSOLUTE - (PORT datab (277:277:277) (368:368:368)) - (PORT datac (244:244:244) (323:323:323)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~7) - (DELAY - (ABSOLUTE - (PORT datab (277:277:277) (371:371:371)) - (IOPATH datab cout (446:446:446) (318:318:318)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~8) - (DELAY - (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~20) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (371:371:371)) - (PORT datab (276:276:276) (371:371:371)) - (PORT datac (1492:1492:1492) (1577:1577:1577)) - (PORT datad (207:207:207) (243:243:243)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1899:1899:1899) (1922:1922:1922)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (342:342:342)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~17) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (430:430:430)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (210:210:210) (251:251:251)) - (PORT datad (1502:1502:1502) (1581:1581:1581)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1899:1899:1899) (1922:1922:1922)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~19) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (376:376:376)) - (PORT datab (278:278:278) (369:369:369)) - (PORT datac (1492:1492:1492) (1581:1581:1581)) - (PORT datad (207:207:207) (243:243:243)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1899:1899:1899) (1922:1922:1922)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~14) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~16) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (430:430:430)) - (PORT datab (1519:1519:1519) (1611:1611:1611)) - (PORT datac (210:210:210) (251:251:251)) - (PORT datad (314:314:314) (331:331:331)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1899:1899:1899) (1922:1922:1922)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (251:251:251) (339:339:339)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (225:225:225) (306:306:306)) - (PORT datad (224:224:224) (296:296:296)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (479:479:479)) - (PORT datab (275:275:275) (370:370:370)) - (PORT datac (555:555:555) (562:562:562)) - (PORT datad (199:199:199) (234:234:234)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1546:1546:1546) (1630:1630:1630)) - (PORT datab (241:241:241) (286:286:286)) - (PORT datad (207:207:207) (243:243:243)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1899:1899:1899) (1922:1922:1922)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT datab (280:280:280) (375:375:375)) - (PORT datad (202:202:202) (237:237:237)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (396:396:396) (427:427:427)) - (PORT datac (247:247:247) (336:336:336)) - (PORT datad (1254:1254:1254) (1338:1338:1338)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) - (DELAY - (ABSOLUTE - (PORT datad (570:570:570) (576:576:576)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1282:1282:1282) (1381:1381:1381)) - (PORT datac (247:247:247) (338:338:338)) - (PORT datad (368:368:368) (391:391:391)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (720:720:720) (744:744:744)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT sload (1864:1864:1864) (1994:1994:1994)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT datab (248:248:248) (333:333:333)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (719:719:719) (743:743:743)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT sload (1864:1864:1864) (1994:1994:1994)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (719:719:719) (741:741:741)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT sload (1864:1864:1864) (1994:1994:1994)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (718:718:718) (741:741:741)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT sload (1864:1864:1864) (1994:1994:1994)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT datab (273:273:273) (358:358:358)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (716:716:716) (740:740:740)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT sload (1864:1864:1864) (1994:1994:1994)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (492:492:492)) - (PORT datab (278:278:278) (375:375:375)) - (PORT datac (365:365:365) (397:397:397)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE AUD_ADCDAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (414:414:414)) - (PORT datab (1407:1407:1407) (1533:1533:1533)) - (PORT datad (773:773:773) (762:762:762)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1879:1879:1879)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) - (DELAY - (ABSOLUTE - (PORT datac (1369:1369:1369) (1496:1496:1496)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1282:1282:1282) (1382:1382:1382)) - (PORT datac (246:246:246) (338:338:338)) - (PORT datad (370:370:370) (393:393:393)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT datac (1376:1376:1376) (1502:1502:1502)) - (PORT datad (220:220:220) (289:289:289)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) - (DELAY - (ABSOLUTE - (PORT datac (1377:1377:1377) (1500:1500:1500)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) - (DELAY - (ABSOLUTE - (PORT datac (1375:1375:1375) (1499:1499:1499)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datac (1374:1374:1374) (1504:1504:1504)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) - (DELAY - (ABSOLUTE - (PORT datac (1379:1379:1379) (1504:1504:1504)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) - (DELAY - (ABSOLUTE - (PORT datab (245:245:245) (327:327:327)) - (PORT datac (1374:1374:1374) (1505:1505:1505)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) - (DELAY - (ABSOLUTE - (PORT datac (1374:1374:1374) (1499:1499:1499)) - (PORT datad (220:220:220) (289:289:289)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) - (DELAY - (ABSOLUTE - (PORT datac (1365:1365:1365) (1498:1498:1498)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) - (DELAY - (ABSOLUTE - (PORT datab (247:247:247) (330:330:330)) - (PORT datac (1378:1378:1378) (1501:1501:1501)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (336:336:336)) - (PORT datac (1376:1376:1376) (1498:1498:1498)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) - (DELAY - (ABSOLUTE - (PORT datac (1373:1373:1373) (1504:1504:1504)) - (PORT datad (219:219:219) (287:287:287)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) - (DELAY - (ABSOLUTE - (PORT datab (1178:1178:1178) (1223:1223:1223)) - (PORT datad (244:244:244) (314:314:314)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT datad (539:539:539) (550:550:550)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (916:916:916)) - (PORT datab (1184:1184:1184) (1229:1229:1229)) - (PORT datad (374:374:374) (445:445:445)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ula_data\~0) - (DELAY - (ABSOLUTE - (PORT datac (882:882:882) (926:926:926)) - (PORT datad (688:688:688) (782:782:782)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1475:1475:1475) (1461:1461:1461)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datab (1979:1979:1979) (2103:2103:2103)) - (PORT datac (1378:1378:1378) (1504:1504:1504)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1574:1574:1574)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (733:733:733) (795:795:795)) - (PORT datab (1186:1186:1186) (1230:1230:1230)) - (PORT datac (2169:2169:2169) (2305:2305:2305)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1866:1866:1866) (1875:1875:1875)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (2767:2767:2767) (2833:2833:2833)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (484:484:484)) - (PORT datab (1187:1187:1187) (1230:1230:1230)) - (PORT datad (245:245:245) (318:318:318)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (869:869:869)) - (PORT datab (1523:1523:1523) (1602:1602:1602)) - (PORT datac (236:236:236) (312:312:312)) - (PORT datad (237:237:237) (306:306:306)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (3264:3264:3264) (3454:3454:3454)) - (PORT datab (834:834:834) (861:861:861)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (2277:2277:2277) (2436:2436:2436)) - (PORT datab (1152:1152:1152) (1241:1241:1241)) - (PORT datac (575:575:575) (625:625:625)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (749:749:749)) - (PORT datab (373:373:373) (397:397:397)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1420:1420:1420)) - (PORT datab (1261:1261:1261) (1344:1344:1344)) - (PORT datac (817:817:817) (836:836:836)) - (PORT datad (216:216:216) (242:242:242)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1326:1326:1326)) - (PORT datac (613:613:613) (660:660:660)) - (PORT datad (1021:1021:1021) (1046:1046:1046)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (723:723:723)) - (PORT datab (911:911:911) (985:985:985)) - (PORT datac (614:614:614) (663:663:663)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1411:1411:1411) (1467:1467:1467)) - (PORT datab (1304:1304:1304) (1367:1367:1367)) - (PORT datad (290:290:290) (379:379:379)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1178:1178:1178)) - (PORT datab (1110:1110:1110) (1162:1162:1162)) - (PORT datac (1334:1334:1334) (1413:1413:1413)) - (PORT datad (1423:1423:1423) (1553:1553:1553)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (278:278:278)) - (PORT datab (260:260:260) (307:307:307)) - (PORT datac (1341:1341:1341) (1384:1384:1384)) - (PORT datad (196:196:196) (229:229:229)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1365:1365:1365)) - (PORT datab (1052:1052:1052) (1078:1078:1078)) - (PORT datac (1010:1010:1010) (1021:1021:1021)) - (PORT datad (1083:1083:1083) (1107:1107:1107)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1073:1073:1073) (1153:1153:1153)) - (PORT datab (235:235:235) (279:279:279)) - (PORT datad (621:621:621) (652:652:652)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (1337:1337:1337) (1379:1379:1379)) - (PORT datac (1582:1582:1582) (1642:1642:1642)) - (PORT datad (554:554:554) (576:576:576)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (742:742:742)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (814:814:814) (825:825:825)) - (PORT datad (630:630:630) (664:664:664)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (874:874:874)) - (PORT datab (718:718:718) (793:793:793)) - (PORT datac (1586:1586:1586) (1641:1641:1641)) - (PORT datad (633:633:633) (664:664:664)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1047:1047:1047) (1081:1081:1081)) - (PORT datab (1091:1091:1091) (1104:1104:1104)) - (PORT datac (872:872:872) (886:886:886)) - (PORT datad (217:217:217) (252:252:252)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (861:861:861)) - (PORT datab (663:663:663) (677:677:677)) - (PORT datac (1259:1259:1259) (1274:1274:1274)) - (PORT datad (674:674:674) (700:700:700)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (286:286:286)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1248:1248:1248) (1322:1322:1322)) - (PORT datac (324:324:324) (358:358:358)) - (PORT datad (1015:1015:1015) (1046:1046:1046)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (749:749:749)) - (PORT datac (954:954:954) (1036:1036:1036)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (209:209:209) (251:251:251)) - (PORT datad (708:708:708) (792:792:792)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1558:1558:1558)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1277:1277:1277)) - (PORT datab (1000:1000:1000) (1059:1059:1059)) - (PORT datac (247:247:247) (330:330:330)) - (PORT datad (628:628:628) (690:690:690)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1256:1256:1256)) - (PORT datab (647:647:647) (714:714:714)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (717:717:717)) - (PORT datab (698:698:698) (764:764:764)) - (PORT datad (328:328:328) (350:350:350)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (377:377:377)) - (PORT datab (979:979:979) (1047:1047:1047)) - (PORT datad (323:323:323) (343:343:343)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (922:922:922)) - (PORT datab (1858:1858:1858) (1898:1898:1898)) - (PORT datac (214:214:214) (289:289:289)) - (PORT datad (540:540:540) (585:585:585)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT datab (669:669:669) (736:736:736)) - (PORT datac (662:662:662) (729:729:729)) - (PORT datad (1143:1143:1143) (1184:1184:1184)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (728:728:728)) - (PORT datab (962:962:962) (1017:1017:1017)) - (PORT datac (539:539:539) (561:561:561)) - (PORT datad (535:535:535) (543:543:543)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT datac (1158:1158:1158) (1230:1230:1230)) - (PORT datad (441:441:441) (517:517:517)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (269:269:269)) - (PORT datab (750:750:750) (833:833:833)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (732:732:732)) - (PORT datac (539:539:539) (565:565:565)) - (PORT datad (922:922:922) (980:980:980)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT datab (477:477:477) (560:560:560)) - (PORT datac (1160:1160:1160) (1233:1233:1233)) - (PORT datad (533:533:533) (544:544:544)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (750:750:750) (832:832:832)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (937:937:937)) - (PORT datab (240:240:240) (321:321:321)) - (PORT datac (214:214:214) (290:290:290)) - (PORT datad (865:865:865) (919:919:919)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (989:989:989) (1073:1073:1073)) - (PORT datab (232:232:232) (275:275:275)) - (PORT datad (197:197:197) (232:232:232)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (634:634:634)) - (PORT datad (704:704:704) (791:791:791)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1558:1558:1558)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT datab (1238:1238:1238) (1305:1305:1305)) - (PORT datac (957:957:957) (1037:1037:1037)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (413:413:413)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (709:709:709) (798:798:798)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1558:1558:1558)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1082:1082:1082) (1109:1109:1109)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datac (1831:1831:1831) (1886:1886:1886)) - (PORT datad (218:218:218) (288:288:288)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (636:636:636)) - (PORT datab (1146:1146:1146) (1216:1216:1216)) - (PORT datac (937:937:937) (1010:1010:1010)) - (PORT datad (958:958:958) (1027:1027:1027)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (266:266:266)) - (PORT datab (834:834:834) (847:847:847)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (684:684:684) (742:742:742)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (705:705:705)) - (PORT datab (370:370:370) (391:391:391)) - (PORT datac (288:288:288) (378:378:378)) - (PORT datad (644:644:644) (711:711:711)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~68) - (DELAY - (ABSOLUTE - (PORT datab (424:424:424) (511:511:511)) - (PORT datac (704:704:704) (785:785:785)) - (PORT datad (744:744:744) (818:818:818)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (770:770:770) (863:863:863)) - (PORT datab (977:977:977) (1041:1041:1041)) - (PORT datac (951:951:951) (1014:1014:1014)) - (PORT datad (856:856:856) (934:934:934)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT datac (906:906:906) (972:972:972)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (827:827:827)) - (PORT datab (209:209:209) (250:250:250)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (739:739:739)) - (PORT datab (856:856:856) (896:896:896)) - (PORT datac (614:614:614) (663:663:663)) - (PORT datad (913:913:913) (960:960:960)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (378:378:378) (402:402:402)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (764:764:764) (789:789:789)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (873:873:873)) - (PORT datab (3323:3323:3323) (3560:3560:3560)) - (PORT datac (1214:1214:1214) (1276:1276:1276)) - (PORT datad (697:697:697) (763:763:763)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2883:2883:2883) (2974:2974:2974)) - (PORT clk (1847:1847:1847) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3758:3758:3758) (4061:4061:4061)) - (PORT d[1] (2384:2384:2384) (2587:2587:2587)) - (PORT d[2] (4330:4330:4330) (4558:4558:4558)) - (PORT d[3] (3269:3269:3269) (3589:3589:3589)) - (PORT d[4] (3205:3205:3205) (3425:3425:3425)) - (PORT d[5] (3995:3995:3995) (4292:4292:4292)) - (PORT d[6] (1989:1989:1989) (2048:2048:2048)) - (PORT d[7] (2791:2791:2791) (2893:2893:2893)) - (PORT d[8] (2796:2796:2796) (2969:2969:2969)) - (PORT d[9] (2195:2195:2195) (2271:2271:2271)) - (PORT d[10] (1561:1561:1561) (1642:1642:1642)) - (PORT d[11] (1535:1535:1535) (1656:1656:1656)) - (PORT d[12] (2218:2218:2218) (2277:2277:2277)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2400:2400:2400) (2441:2441:2441)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (PORT d[0] (2793:2793:2793) (2846:2846:2846)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2603:2603:2603) (2673:2673:2673)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3512:3512:3512) (3767:3767:3767)) - (PORT d[1] (2119:2119:2119) (2309:2309:2309)) - (PORT d[2] (4014:4014:4014) (4236:4236:4236)) - (PORT d[3] (2955:2955:2955) (3243:3243:3243)) - (PORT d[4] (2861:2861:2861) (3093:3093:3093)) - (PORT d[5] (3688:3688:3688) (3954:3954:3954)) - (PORT d[6] (2564:2564:2564) (2723:2723:2723)) - (PORT d[7] (3150:3150:3150) (3265:3265:3265)) - (PORT d[8] (2216:2216:2216) (2371:2371:2371)) - (PORT d[9] (2566:2566:2566) (2692:2692:2692)) - (PORT d[10] (2606:2606:2606) (2782:2782:2782)) - (PORT d[11] (1719:1719:1719) (1828:1828:1828)) - (PORT d[12] (2503:2503:2503) (2607:2607:2607)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1951:1951:1951) (1908:1908:1908)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (2683:2683:2683) (2737:2737:2737)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (458:458:458)) - (PORT datab (909:909:909) (925:925:925)) - (PORT datac (1160:1160:1160) (1239:1239:1239)) - (PORT datad (1162:1162:1162) (1198:1198:1198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2002:2002:2002) (2075:2075:2075)) - (PORT clk (1849:1849:1849) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3172:3172:3172) (3423:3423:3423)) - (PORT d[1] (2108:2108:2108) (2273:2273:2273)) - (PORT d[2] (2307:2307:2307) (2529:2529:2529)) - (PORT d[3] (2676:2676:2676) (2915:2915:2915)) - (PORT d[4] (2225:2225:2225) (2399:2399:2399)) - (PORT d[5] (3373:3373:3373) (3628:3628:3628)) - (PORT d[6] (2284:2284:2284) (2423:2423:2423)) - (PORT d[7] (3683:3683:3683) (3819:3819:3819)) - (PORT d[8] (2176:2176:2176) (2310:2310:2310)) - (PORT d[9] (2801:2801:2801) (2942:2942:2942)) - (PORT d[10] (1977:1977:1977) (2131:2131:2131)) - (PORT d[11] (1870:1870:1870) (2044:2044:2044)) - (PORT d[12] (2810:2810:2810) (2943:2943:2943)) - (PORT clk (1846:1846:1846) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3043:3043:3043) (3118:3118:3118)) - (PORT clk (1846:1846:1846) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1878:1878:1878)) - (PORT d[0] (3443:3443:3443) (3502:3502:3502)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2297:2297:2297) (2367:2367:2367)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3490:3490:3490) (3747:3747:3747)) - (PORT d[1] (2348:2348:2348) (2530:2530:2530)) - (PORT d[2] (3734:3734:3734) (3971:3971:3971)) - (PORT d[3] (2975:2975:2975) (3240:3240:3240)) - (PORT d[4] (2538:2538:2538) (2736:2736:2736)) - (PORT d[5] (3674:3674:3674) (3955:3955:3955)) - (PORT d[6] (1674:1674:1674) (1708:1708:1708)) - (PORT d[7] (3384:3384:3384) (3498:3498:3498)) - (PORT d[8] (2215:2215:2215) (2370:2370:2370)) - (PORT d[9] (2556:2556:2556) (2660:2660:2660)) - (PORT d[10] (2283:2283:2283) (2436:2436:2436)) - (PORT d[11] (1880:1880:1880) (2047:2047:2047)) - (PORT d[12] (2509:2509:2509) (2617:2617:2617)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1745:1745:1745) (1723:1723:1723)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (3117:3117:3117) (3161:3161:3161)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (454:454:454)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (1468:1468:1468) (1509:1509:1509)) - (PORT datad (1175:1175:1175) (1195:1195:1195)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1006:1006:1006) (1049:1049:1049)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1319:1319:1319) (1370:1370:1370)) - (PORT d[1] (1987:1987:1987) (2086:2086:2086)) - (PORT d[2] (1577:1577:1577) (1693:1693:1693)) - (PORT d[3] (3669:3669:3669) (3950:3950:3950)) - (PORT d[4] (2882:2882:2882) (3117:3117:3117)) - (PORT d[5] (1257:1257:1257) (1296:1296:1296)) - (PORT d[6] (1113:1113:1113) (1136:1136:1136)) - (PORT d[7] (2674:2674:2674) (2839:2839:2839)) - (PORT d[8] (1304:1304:1304) (1352:1352:1352)) - (PORT d[9] (4662:4662:4662) (4844:4844:4844)) - (PORT d[10] (1312:1312:1312) (1359:1359:1359)) - (PORT d[11] (4146:4146:4146) (4423:4423:4423)) - (PORT d[12] (2646:2646:2646) (2740:2740:2740)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1748:1748:1748) (1732:1732:1732)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2336:2336:2336) (2359:2359:2359)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2778:2778:2778) (2873:2873:2873)) - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1877:1877:1877) (1980:1980:1980)) - (PORT d[1] (1864:1864:1864) (1967:1967:1967)) - (PORT d[2] (1900:1900:1900) (2034:2034:2034)) - (PORT d[3] (2011:2011:2011) (2198:2198:2198)) - (PORT d[4] (1926:1926:1926) (2025:2025:2025)) - (PORT d[5] (1855:1855:1855) (1968:1968:1968)) - (PORT d[6] (1789:1789:1789) (1915:1915:1915)) - (PORT d[7] (1864:1864:1864) (1990:1990:1990)) - (PORT d[8] (1957:1957:1957) (2108:2108:2108)) - (PORT d[9] (2036:2036:2036) (2135:2135:2135)) - (PORT d[10] (1892:1892:1892) (1976:1976:1976)) - (PORT d[11] (2020:2020:2020) (2088:2088:2088)) - (PORT d[12] (2073:2073:2073) (2152:2152:2152)) - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (740:740:740) (774:774:774)) - (PORT d[1] (3345:3345:3345) (3629:3629:3629)) - (PORT d[2] (1616:1616:1616) (1746:1746:1746)) - (PORT d[3] (3945:3945:3945) (4253:4253:4253)) - (PORT d[4] (3125:3125:3125) (3332:3332:3332)) - (PORT d[5] (1233:1233:1233) (1278:1278:1278)) - (PORT d[6] (3247:3247:3247) (3438:3438:3438)) - (PORT d[7] (2656:2656:2656) (2765:2765:2765)) - (PORT d[8] (1010:1010:1010) (1048:1048:1048)) - (PORT d[9] (2726:2726:2726) (2798:2798:2798)) - (PORT d[10] (1231:1231:1231) (1258:1258:1258)) - (PORT d[11] (1478:1478:1478) (1519:1519:1519)) - (PORT d[12] (2080:2080:2080) (2160:2160:2160)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1879:1879:1879)) - (PORT d[0] (1097:1097:1097) (1106:1106:1106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (997:997:997) (1055:1055:1055)) - (PORT clk (1858:1858:1858) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1395:1395:1395) (1508:1508:1508)) - (PORT d[1] (1654:1654:1654) (1743:1743:1743)) - (PORT d[2] (3652:3652:3652) (4014:4014:4014)) - (PORT d[3] (3377:3377:3377) (3599:3599:3599)) - (PORT d[4] (2253:2253:2253) (2433:2433:2433)) - (PORT d[5] (1303:1303:1303) (1382:1382:1382)) - (PORT d[6] (1184:1184:1184) (1230:1230:1230)) - (PORT d[7] (2668:2668:2668) (2822:2822:2822)) - (PORT d[8] (1474:1474:1474) (1538:1538:1538)) - (PORT d[9] (2957:2957:2957) (3060:3060:3060)) - (PORT d[10] (1955:1955:1955) (2037:2037:2037)) - (PORT d[11] (2657:2657:2657) (2887:2887:2887)) - (PORT d[12] (2384:2384:2384) (2498:2498:2498)) - (PORT clk (1855:1855:1855) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1531:1531:1531) (1523:1523:1523)) - (PORT clk (1855:1855:1855) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (PORT d[0] (2083:2083:2083) (2062:2062:2062)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1811:1811:1811)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3099:3099:3099) (3168:3168:3168)) - (PORT clk (1823:1823:1823) (1817:1817:1817)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1872:1872:1872) (2017:2017:2017)) - (PORT d[1] (1844:1844:1844) (1957:1957:1957)) - (PORT d[2] (1841:1841:1841) (1966:1966:1966)) - (PORT d[3] (1832:1832:1832) (1961:1961:1961)) - (PORT d[4] (1884:1884:1884) (1997:1997:1997)) - (PORT d[5] (1788:1788:1788) (1890:1890:1890)) - (PORT d[6] (1810:1810:1810) (1961:1961:1961)) - (PORT d[7] (1845:1845:1845) (1969:1969:1969)) - (PORT d[8] (1905:1905:1905) (2022:2022:2022)) - (PORT d[9] (1890:1890:1890) (1987:1987:1987)) - (PORT d[10] (1895:1895:1895) (1995:1995:1995)) - (PORT d[11] (1995:1995:1995) (2078:2078:2078)) - (PORT d[12] (1857:1857:1857) (1941:1941:1941)) - (PORT clk (1819:1819:1819) (1813:1813:1813)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (929:929:929)) - (PORT datab (1223:1223:1223) (1263:1263:1263)) - (PORT datac (267:267:267) (356:356:356)) - (PORT datad (1171:1171:1171) (1226:1226:1226)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (734:734:734) (784:784:784)) - (PORT d[1] (3090:3090:3090) (3353:3353:3353)) - (PORT d[2] (2189:2189:2189) (2293:2293:2293)) - (PORT d[3] (1005:1005:1005) (1060:1060:1060)) - (PORT d[4] (3388:3388:3388) (3635:3635:3635)) - (PORT d[5] (1292:1292:1292) (1358:1358:1358)) - (PORT d[6] (2882:2882:2882) (3040:3040:3040)) - (PORT d[7] (2332:2332:2332) (2441:2441:2441)) - (PORT d[8] (4009:4009:4009) (4256:4256:4256)) - (PORT d[9] (3026:3026:3026) (3124:3124:3124)) - (PORT d[10] (2857:2857:2857) (3068:3068:3068)) - (PORT d[11] (2243:2243:2243) (2459:2459:2459)) - (PORT d[12] (2401:2401:2401) (2507:2507:2507)) - (PORT clk (1847:1847:1847) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1873:1873:1873)) - (PORT d[0] (2265:2265:2265) (2316:2316:2316)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1836:1836:1836)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (509:509:509)) - (PORT datab (1216:1216:1216) (1243:1243:1243)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (1147:1147:1147) (1184:1184:1184)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (945:945:945) (1001:1001:1001)) - (PORT datab (974:974:974) (1025:1025:1025)) - (PORT datac (1035:1035:1035) (1021:1021:1021)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1834:1834:1834) (1929:1929:1929)) - (PORT datab (3299:3299:3299) (3522:3522:3522)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (2114:2114:2114) (2240:2240:2240)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1221:1221:1221) (1271:1271:1271)) - (PORT datab (1186:1186:1186) (1278:1278:1278)) - (PORT datac (1163:1163:1163) (1242:1242:1242)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (646:646:646)) - (PORT datac (671:671:671) (706:706:706)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1431:1431:1431)) - (PORT datab (1272:1272:1272) (1358:1358:1358)) - (PORT datac (203:203:203) (240:240:240)) - (PORT datad (815:815:815) (833:833:833)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (650:650:650) (697:697:697)) - (PORT datac (1155:1155:1155) (1213:1213:1213)) - (PORT datad (649:649:649) (676:676:676)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1613:1613:1613) (1667:1667:1667)) - (PORT datad (1599:1599:1599) (1670:1670:1670)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1211:1211:1211)) - (PORT datab (2629:2629:2629) (2707:2707:2707)) - (PORT datac (839:839:839) (855:855:855)) - (PORT datad (1895:1895:1895) (1903:1903:1903)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) - (DELAY - (ABSOLUTE - (PORT dataa (552:552:552) (576:576:576)) - (PORT datab (1794:1794:1794) (1841:1841:1841)) - (PORT datac (908:908:908) (961:961:961)) - (PORT datad (908:908:908) (963:963:963)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) - (PORT ena (1555:1555:1555) (1575:1575:1575)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (508:508:508)) - (PORT datab (1093:1093:1093) (1162:1162:1162)) - (PORT datac (622:622:622) (681:681:681)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1337:1337:1337) (1396:1396:1396)) - (PORT datab (630:630:630) (669:669:669)) - (PORT datac (1459:1459:1459) (1494:1494:1494)) - (PORT datad (930:930:930) (964:964:964)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (946:946:946)) - (PORT datab (1111:1111:1111) (1112:1112:1112)) - (PORT datac (990:990:990) (1004:1004:1004)) - (PORT datad (1053:1053:1053) (1045:1045:1045)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (953:953:953)) - (PORT datab (214:214:214) (258:258:258)) - (PORT datac (1040:1040:1040) (1049:1049:1049)) - (PORT datad (1055:1055:1055) (1058:1058:1058)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) - (DELAY - (ABSOLUTE - (PORT datab (652:652:652) (705:705:705)) - (PORT datad (586:586:586) (626:626:626)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (737:737:737)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (195:195:195) (219:219:219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1111:1111:1111) (1127:1127:1127)) - (PORT datac (727:727:727) (737:737:737)) - (PORT datad (1018:1018:1018) (1023:1023:1023)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (1011:1011:1011) (1018:1018:1018)) - (PORT datac (556:556:556) (578:578:578)) - (PORT datad (790:790:790) (799:799:799)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (773:773:773) (860:860:860)) - (PORT datab (974:974:974) (1036:1036:1036)) - (PORT datac (903:903:903) (968:968:968)) - (PORT datad (853:853:853) (930:930:930)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (985:985:985) (1048:1048:1048)) - (PORT datac (768:768:768) (788:788:788)) - (PORT datad (745:745:745) (820:820:820)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (333:333:333) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT datab (209:209:209) (252:252:252)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (527:527:527)) - (PORT datac (679:679:679) (761:761:761)) - (PORT datad (921:921:921) (988:988:988)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (797:797:797)) - (PORT datab (1091:1091:1091) (1157:1157:1157)) - (PORT datac (956:956:956) (1013:1013:1013)) - (PORT datad (873:873:873) (937:937:937)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (208:208:208) (251:251:251)) - (PORT datad (174:174:174) (201:201:201)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (477:477:477)) - (PORT datab (1426:1426:1426) (1483:1483:1483)) - (PORT datac (842:842:842) (895:895:895)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (754:754:754)) - (PORT datab (384:384:384) (413:413:413)) - (PORT datad (448:448:448) (529:529:529)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (752:752:752)) - (PORT datab (564:564:564) (570:570:570)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (456:456:456)) - (PORT datab (902:902:902) (959:959:959)) - (PORT datac (214:214:214) (290:290:290)) - (PORT datad (799:799:799) (821:821:821)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~134) - (DELAY - (ABSOLUTE - (PORT dataa (1218:1218:1218) (1285:1285:1285)) - (PORT datab (969:969:969) (1037:1037:1037)) - (PORT datad (556:556:556) (560:560:560)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT datac (888:888:888) (945:945:945)) - (PORT datad (677:677:677) (746:746:746)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (789:789:789)) - (PORT datab (346:346:346) (372:372:372)) - (PORT datac (187:187:187) (229:229:229)) - (PORT datad (955:955:955) (1025:1025:1025)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (451:451:451) (525:525:525)) - (PORT datab (335:335:335) (368:368:368)) - (PORT datac (509:509:509) (518:518:518)) - (PORT datad (627:627:627) (648:648:648)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (725:725:725)) - (PORT datad (315:315:315) (335:335:335)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datab (1238:1238:1238) (1305:1305:1305)) - (PORT datac (952:952:952) (1032:1032:1032)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (1208:1208:1208) (1279:1279:1279)) - (PORT datab (666:666:666) (735:735:735)) - (PORT datac (639:639:639) (711:711:711)) - (PORT datad (588:588:588) (642:642:642)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (987:987:987)) - (PORT datab (590:590:590) (617:617:617)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datad (703:703:703) (794:794:794)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1558:1558:1558)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (431:431:431) (500:500:500)) - (PORT datab (856:856:856) (895:895:895)) - (PORT datac (649:649:649) (699:699:699)) - (PORT datad (1107:1107:1107) (1152:1152:1152)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1086:1086:1086) (1158:1158:1158)) - (PORT datab (964:964:964) (1030:1030:1030)) - (PORT datac (613:613:613) (669:669:669)) - (PORT datad (941:941:941) (1011:1011:1011)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~77) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (317:317:317) (410:410:410)) - (PORT datac (613:613:613) (626:626:626)) - (PORT datad (586:586:586) (650:650:650)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1086:1086:1086) (1155:1155:1155)) - (PORT datab (968:968:968) (1034:1034:1034)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (727:727:727) (790:790:790)) - (PORT datab (1146:1146:1146) (1216:1216:1216)) - (PORT datac (942:942:942) (1011:1011:1011)) - (PORT datad (674:674:674) (744:744:744)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~75) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (794:794:794)) - (PORT datab (231:231:231) (274:274:274)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (960:960:960) (1026:1026:1026)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datab (318:318:318) (415:415:415)) - (PORT datac (623:623:623) (663:663:663)) - (PORT datad (331:331:331) (348:348:348)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (430:430:430) (517:517:517)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (768:768:768)) - (PORT datab (1167:1167:1167) (1221:1221:1221)) - (PORT datac (645:645:645) (710:710:710)) - (PORT datad (870:870:870) (885:885:885)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (763:763:763)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (645:645:645)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (2000:2000:2000) (2050:2050:2050)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (907:907:907)) - (PORT datab (331:331:331) (361:361:361)) - (PORT datac (535:535:535) (539:539:539)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2232:2232:2232) (2353:2353:2353)) - (PORT clk (1850:1850:1850) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2861:2861:2861) (3087:3087:3087)) - (PORT d[1] (1799:1799:1799) (1959:1959:1959)) - (PORT d[2] (2607:2607:2607) (2822:2822:2822)) - (PORT d[3] (2355:2355:2355) (2592:2592:2592)) - (PORT d[4] (1954:1954:1954) (2113:2113:2113)) - (PORT d[5] (3082:3082:3082) (3310:3310:3310)) - (PORT d[6] (1979:1979:1979) (2096:2096:2096)) - (PORT d[7] (4035:4035:4035) (4216:4216:4216)) - (PORT d[8] (2475:2475:2475) (2643:2643:2643)) - (PORT d[9] (2803:2803:2803) (2925:2925:2925)) - (PORT d[10] (1891:1891:1891) (2013:2013:2013)) - (PORT d[11] (1908:1908:1908) (2070:2070:2070)) - (PORT d[12] (3099:3099:3099) (3255:3255:3255)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2769:2769:2769) (2830:2830:2830)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1879:1879:1879)) - (PORT d[0] (3160:3160:3160) (3198:3198:3198)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1611:1611:1611) (1719:1719:1719)) - (PORT clk (1854:1854:1854) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1958:1958:1958) (2078:2078:2078)) - (PORT d[1] (2431:2431:2431) (2644:2644:2644)) - (PORT d[2] (2066:2066:2066) (2252:2252:2252)) - (PORT d[3] (1285:1285:1285) (1374:1374:1374)) - (PORT d[4] (2454:2454:2454) (2612:2612:2612)) - (PORT d[5] (4879:4879:4879) (5239:5239:5239)) - (PORT d[6] (1998:1998:1998) (2076:2076:2076)) - (PORT d[7] (1659:1659:1659) (1699:1699:1699)) - (PORT d[8] (2735:2735:2735) (2906:2906:2906)) - (PORT d[9] (3098:3098:3098) (3222:3222:3222)) - (PORT d[10] (1949:1949:1949) (2109:2109:2109)) - (PORT d[11] (2103:2103:2103) (2234:2234:2234)) - (PORT d[12] (1356:1356:1356) (1360:1360:1360)) - (PORT clk (1851:1851:1851) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1707:1707:1707) (1705:1705:1705)) - (PORT clk (1851:1851:1851) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (PORT d[0] (2993:2993:2993) (3013:3013:3013)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1841:1841:1841)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1630:1630:1630) (1719:1719:1719)) - (PORT clk (1853:1853:1853) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1928:1928:1928) (2049:2049:2049)) - (PORT d[1] (2688:2688:2688) (2914:2914:2914)) - (PORT d[2] (2053:2053:2053) (2250:2250:2250)) - (PORT d[3] (1511:1511:1511) (1575:1575:1575)) - (PORT d[4] (2207:2207:2207) (2372:2372:2372)) - (PORT d[5] (4876:4876:4876) (5216:5216:5216)) - (PORT d[6] (2220:2220:2220) (2290:2290:2290)) - (PORT d[7] (1905:1905:1905) (1937:1937:1937)) - (PORT d[8] (3080:3080:3080) (3260:3260:3260)) - (PORT d[9] (3097:3097:3097) (3212:3212:3212)) - (PORT d[10] (1944:1944:1944) (2100:2100:2100)) - (PORT d[11] (2115:2115:2115) (2280:2280:2280)) - (PORT d[12] (1121:1121:1121) (1135:1135:1135)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2198:2198:2198) (2190:2190:2190)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (PORT d[0] (2605:2605:2605) (2653:2653:2653)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1841:1841:1841)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1825:1825:1825) (1934:1934:1934)) - (PORT clk (1843:1843:1843) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2501:2501:2501) (2661:2661:2661)) - (PORT d[1] (2703:2703:2703) (2915:2915:2915)) - (PORT d[2] (2085:2085:2085) (2272:2272:2272)) - (PORT d[3] (3896:3896:3896) (4246:4246:4246)) - (PORT d[4] (1916:1916:1916) (2059:2059:2059)) - (PORT d[5] (4578:4578:4578) (4899:4899:4899)) - (PORT d[6] (2265:2265:2265) (2368:2368:2368)) - (PORT d[7] (2450:2450:2450) (2509:2509:2509)) - (PORT d[8] (3365:3365:3365) (3560:3560:3560)) - (PORT d[9] (2530:2530:2530) (2652:2652:2652)) - (PORT d[10] (2276:2276:2276) (2451:2451:2451)) - (PORT d[11] (2433:2433:2433) (2576:2576:2576)) - (PORT d[12] (1598:1598:1598) (1629:1629:1629)) - (PORT clk (1840:1840:1840) (1868:1868:1868)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2052:2052:2052) (2064:2064:2064)) - (PORT clk (1840:1840:1840) (1868:1868:1868)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1872:1872:1872)) - (PORT d[0] (2833:2833:2833) (2885:2885:2885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1831:1831:1831)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (995:995:995)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (995:995:995)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (458:458:458)) - (PORT datab (1530:1530:1530) (1550:1550:1550)) - (PORT datac (1164:1164:1164) (1242:1242:1242)) - (PORT datad (1166:1166:1166) (1192:1192:1192)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (453:453:453)) - (PORT datab (1744:1744:1744) (1831:1831:1831)) - (PORT datac (1431:1431:1431) (1493:1493:1493)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1057:1057:1057) (1115:1115:1115)) - (PORT d[1] (3332:3332:3332) (3598:3598:3598)) - (PORT d[2] (2180:2180:2180) (2297:2297:2297)) - (PORT d[3] (1004:1004:1004) (1059:1059:1059)) - (PORT d[4] (719:719:719) (767:767:767)) - (PORT d[5] (1251:1251:1251) (1322:1322:1322)) - (PORT d[6] (2900:2900:2900) (3050:3050:3050)) - (PORT d[7] (2353:2353:2353) (2464:2464:2464)) - (PORT d[8] (4005:4005:4005) (4249:4249:4249)) - (PORT d[9] (3027:3027:3027) (3125:3125:3125)) - (PORT d[10] (2849:2849:2849) (3047:3047:3047)) - (PORT d[11] (2235:2235:2235) (2437:2437:2437)) - (PORT d[12] (2418:2418:2418) (2498:2498:2498)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1875:1875:1875)) - (PORT d[0] (1374:1374:1374) (1384:1384:1384)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1828:1828:1828) (1920:1920:1920)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2719:2719:2719) (2866:2866:2866)) - (PORT d[1] (1363:1363:1363) (1442:1442:1442)) - (PORT d[2] (3376:3376:3376) (3692:3692:3692)) - (PORT d[3] (2726:2726:2726) (2952:2952:2952)) - (PORT d[4] (2561:2561:2561) (2773:2773:2773)) - (PORT d[5] (1820:1820:1820) (1944:1944:1944)) - (PORT d[6] (2637:2637:2637) (2778:2778:2778)) - (PORT d[7] (3221:3221:3221) (3388:3388:3388)) - (PORT d[8] (1892:1892:1892) (1953:1953:1953)) - (PORT d[9] (4089:4089:4089) (4235:4235:4235)) - (PORT d[10] (1920:1920:1920) (1999:1999:1999)) - (PORT d[11] (2239:2239:2239) (2469:2469:2469)) - (PORT d[12] (3062:3062:3062) (3188:3188:3188)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1763:1763:1763) (1744:1744:1744)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2924:2924:2924) (2955:2955:2955)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3423:3423:3423) (3527:3527:3527)) - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1877:1877:1877) (1996:1996:1996)) - (PORT d[1] (1804:1804:1804) (1928:1928:1928)) - (PORT d[2] (1809:1809:1809) (1887:1887:1887)) - (PORT d[3] (1978:1978:1978) (2151:2151:2151)) - (PORT d[4] (1882:1882:1882) (2016:2016:2016)) - (PORT d[5] (2114:2114:2114) (2191:2191:2191)) - (PORT d[6] (2030:2030:2030) (2109:2109:2109)) - (PORT d[7] (1862:1862:1862) (1936:1936:1936)) - (PORT d[8] (1896:1896:1896) (2033:2033:2033)) - (PORT d[9] (2025:2025:2025) (2102:2102:2102)) - (PORT d[10] (1898:1898:1898) (2004:2004:2004)) - (PORT d[11] (1937:1937:1937) (2003:2003:2003)) - (PORT d[12] (1900:1900:1900) (2016:2016:2016)) - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (750:750:750) (796:796:796)) - (PORT d[1] (3387:3387:3387) (3654:3654:3654)) - (PORT d[2] (1897:1897:1897) (2000:2000:2000)) - (PORT d[3] (1008:1008:1008) (1082:1082:1082)) - (PORT d[4] (3136:3136:3136) (3348:3348:3348)) - (PORT d[5] (951:951:951) (1004:1004:1004)) - (PORT d[6] (2888:2888:2888) (3054:3054:3054)) - (PORT d[7] (2677:2677:2677) (2789:2789:2789)) - (PORT d[8] (984:984:984) (1018:1018:1018)) - (PORT d[9] (2727:2727:2727) (2799:2799:2799)) - (PORT d[10] (2911:2911:2911) (3132:3132:3132)) - (PORT d[11] (2465:2465:2465) (2695:2695:2695)) - (PORT d[12] (2092:2092:2092) (2181:2181:2181)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1877:1877:1877)) - (PORT d[0] (2329:2329:2329) (2272:2272:2272)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1546:1546:1546) (1644:1644:1644)) - (PORT clk (1864:1864:1864) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1703:1703:1703) (1840:1840:1840)) - (PORT d[1] (1728:1728:1728) (1821:1821:1821)) - (PORT d[2] (3631:3631:3631) (3980:3980:3980)) - (PORT d[3] (2731:2731:2731) (2947:2947:2947)) - (PORT d[4] (2593:2593:2593) (2814:2814:2814)) - (PORT d[5] (1783:1783:1783) (1865:1865:1865)) - (PORT d[6] (2579:2579:2579) (2751:2751:2751)) - (PORT d[7] (2984:2984:2984) (3148:3148:3148)) - (PORT d[8] (2062:2062:2062) (2153:2153:2153)) - (PORT d[9] (4058:4058:4058) (4194:4194:4194)) - (PORT d[10] (2224:2224:2224) (2307:2307:2307)) - (PORT d[11] (3010:3010:3010) (3216:3216:3216)) - (PORT d[12] (3036:3036:3036) (3158:3158:3158)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1779:1779:1779) (1768:1768:1768)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1864:1864:1864) (1891:1891:1891)) - (PORT d[0] (2907:2907:2907) (2889:2889:2889)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1819:1819:1819) (1816:1816:1816)) @@ -44156,10 +31811,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (3428:3428:3428) (3539:3539:3539)) + (PORT d[0] (2147:2147:2147) (2193:2193:2193)) (PORT clk (1829:1829:1829) (1822:1822:1822)) ) ) @@ -44169,22 +31824,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1845:1845:1845) (1955:1955:1955)) - (PORT d[1] (1754:1754:1754) (1823:1823:1823)) - (PORT d[2] (1870:1870:1870) (1937:1937:1937)) - (PORT d[3] (1907:1907:1907) (2071:2071:2071)) - (PORT d[4] (1916:1916:1916) (2037:2037:2037)) - (PORT d[5] (2145:2145:2145) (2251:2251:2251)) - (PORT d[6] (1999:1999:1999) (2062:2062:2062)) - (PORT d[7] (1854:1854:1854) (1924:1924:1924)) - (PORT d[8] (2062:2062:2062) (2122:2122:2122)) - (PORT d[9] (1902:1902:1902) (1949:1949:1949)) - (PORT d[10] (1862:1862:1862) (1970:1970:1970)) - (PORT d[11] (1936:1936:1936) (2003:2003:2003)) - (PORT d[12] (1932:1932:1932) (2009:2009:2009)) + (PORT d[0] (4636:4636:4636) (4688:4688:4688)) + (PORT d[1] (4395:4395:4395) (4383:4383:4383)) + (PORT d[2] (4558:4558:4558) (4624:4624:4624)) + (PORT d[3] (4721:4721:4721) (4720:4720:4720)) + (PORT d[4] (4265:4265:4265) (4262:4262:4262)) + (PORT d[5] (4417:4417:4417) (4355:4355:4355)) + (PORT d[6] (4638:4638:4638) (4708:4708:4708)) + (PORT d[7] (4394:4394:4394) (4343:4343:4343)) + (PORT d[8] (4731:4731:4731) (4705:4705:4705)) + (PORT d[9] (4601:4601:4601) (4791:4791:4791)) + (PORT d[10] (4436:4436:4436) (4445:4445:4445)) + (PORT d[11] (4654:4654:4654) (4682:4682:4682)) + (PORT d[12] (4454:4454:4454) (4466:4466:4466)) (PORT clk (1825:1825:1825) (1818:1818:1818)) ) ) @@ -44194,7 +31849,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1829:1829:1829) (1822:1822:1822)) @@ -44203,7 +31858,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) (DELAY (ABSOLUTE (PORT clk (1830:1830:1830) (1823:1823:1823)) @@ -44213,7 +31868,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1830:1830:1830) (1823:1823:1823)) @@ -44223,7 +31878,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1830:1830:1830) (1823:1823:1823)) @@ -44233,7 +31888,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1830:1830:1830) (1823:1823:1823)) @@ -44243,7 +31898,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) (DELAY (ABSOLUTE (PORT clk (1821:1821:1821) (1818:1818:1818)) @@ -44257,13 +31912,494 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector2\~0) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (1183:1183:1183) (1233:1233:1233)) - (PORT datab (298:298:298) (393:393:393)) - (PORT datac (896:896:896) (920:920:920)) - (PORT datad (1713:1713:1713) (1749:1749:1749)) + (PORT datad (1203:1203:1203) (1298:1298:1298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1947:1947:1947)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT asdata (1724:1724:1724) (1774:1774:1774)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (726:726:726)) + (PORT datab (262:262:262) (315:315:315)) + (PORT datac (366:366:366) (405:405:405)) + (PORT datad (1303:1303:1303) (1300:1300:1300)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1513:1513:1513) (1593:1593:1593)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2905:2905:2905) (3002:3002:3002)) + (PORT d[1] (2381:2381:2381) (2621:2621:2621)) + (PORT d[2] (1221:1221:1221) (1275:1275:1275)) + (PORT d[3] (2017:2017:2017) (2080:2080:2080)) + (PORT d[4] (2910:2910:2910) (3179:3179:3179)) + (PORT d[5] (2405:2405:2405) (2631:2631:2631)) + (PORT d[6] (1533:1533:1533) (1608:1608:1608)) + (PORT d[7] (1282:1282:1282) (1365:1365:1365)) + (PORT d[8] (1697:1697:1697) (1794:1794:1794)) + (PORT d[9] (1564:1564:1564) (1639:1639:1639)) + (PORT d[10] (2164:2164:2164) (2311:2311:2311)) + (PORT d[11] (3205:3205:3205) (3345:3345:3345)) + (PORT d[12] (1922:1922:1922) (2027:2027:2027)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2709:2709:2709) (2650:2650:2650)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (3090:3090:3090) (3120:3120:3120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2167:2167:2167) (2208:2208:2208)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4624:4624:4624) (4660:4660:4660)) + (PORT d[1] (4162:4162:4162) (4152:4152:4152)) + (PORT d[2] (4263:4263:4263) (4325:4325:4325)) + (PORT d[3] (4486:4486:4486) (4524:4524:4524)) + (PORT d[4] (4333:4333:4333) (4346:4346:4346)) + (PORT d[5] (4356:4356:4356) (4399:4399:4399)) + (PORT d[6] (4459:4459:4459) (4542:4542:4542)) + (PORT d[7] (4161:4161:4161) (4129:4129:4129)) + (PORT d[8] (4409:4409:4409) (4389:4389:4389)) + (PORT d[9] (4581:4581:4581) (4772:4772:4772)) + (PORT d[10] (4418:4418:4418) (4409:4409:4409)) + (PORT d[11] (4535:4535:4535) (4594:4594:4594)) + (PORT d[12] (4450:4450:4450) (4459:4459:4459)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2533:2533:2533) (2623:2623:2623)) + (PORT d[1] (2220:2220:2220) (2418:2418:2418)) + (PORT d[2] (2325:2325:2325) (2498:2498:2498)) + (PORT d[3] (2178:2178:2178) (2338:2338:2338)) + (PORT d[4] (2896:2896:2896) (3148:3148:3148)) + (PORT d[5] (2277:2277:2277) (2465:2465:2465)) + (PORT d[6] (1866:1866:1866) (1991:1991:1991)) + (PORT d[7] (2226:2226:2226) (2303:2303:2303)) + (PORT d[8] (2742:2742:2742) (2980:2980:2980)) + (PORT d[9] (1744:1744:1744) (1855:1855:1855)) + (PORT d[10] (1754:1754:1754) (1834:1834:1834)) + (PORT d[11] (3116:3116:3116) (3240:3240:3240)) + (PORT d[12] (1285:1285:1285) (1359:1359:1359)) + (PORT clk (1869:1869:1869) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1894:1894:1894)) + (PORT d[0] (2187:2187:2187) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1021:1021:1021)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1348:1348:1348) (1400:1400:1400)) + (PORT datab (276:276:276) (364:364:364)) + (PORT datac (1381:1381:1381) (1421:1421:1421)) + (PORT datad (1657:1657:1657) (1684:1684:1684)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3643:3643:3643) (3885:3885:3885)) + (PORT d[1] (2602:2602:2602) (2837:2837:2837)) + (PORT d[2] (2449:2449:2449) (2542:2542:2542)) + (PORT d[3] (2141:2141:2141) (2296:2296:2296)) + (PORT d[4] (2227:2227:2227) (2405:2405:2405)) + (PORT d[5] (2065:2065:2065) (2249:2249:2249)) + (PORT d[6] (1926:1926:1926) (2066:2066:2066)) + (PORT d[7] (1993:1993:1993) (2107:2107:2107)) + (PORT d[8] (2992:2992:2992) (3233:3233:3233)) + (PORT d[9] (2617:2617:2617) (2763:2763:2763)) + (PORT d[10] (4742:4742:4742) (4968:4968:4968)) + (PORT d[11] (2083:2083:2083) (2222:2222:2222)) + (PORT d[12] (2446:2446:2446) (2592:2592:2592)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (3176:3176:3176) (3088:3088:3088)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1292:1292:1292)) + (PORT datab (1157:1157:1157) (1165:1165:1165)) + (PORT datac (1614:1614:1614) (1636:1636:1636)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (1434:1434:1434) (1498:1498:1498)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (624:624:624) (685:685:685)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -44273,15 +32409,38 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector2\~1) + (INSTANCE D\[6\]\~111) (DELAY (ABSOLUTE - (PORT dataa (1209:1209:1209) (1254:1254:1254)) - (PORT datab (298:298:298) (392:392:392)) - (PORT datac (1450:1450:1450) (1485:1485:1485)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (642:642:642) (683:683:683)) + (PORT datab (2010:2010:2010) (2117:2117:2117)) + (PORT datac (918:918:918) (1000:1000:1000)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE raw_loader_in\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (967:967:967)) + (PORT datac (1544:1544:1544) (1682:1682:1682)) + (PORT datad (1984:1984:1984) (2079:2079:2079)) + (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44289,15 +32448,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~41) + (INSTANCE D\[6\]\~100) (DELAY (ABSOLUTE - (PORT dataa (947:947:947) (997:997:997)) - (PORT datab (973:973:973) (1025:1025:1025)) - (PORT datac (1220:1220:1220) (1227:1227:1227)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (952:952:952) (1002:1002:1002)) + (PORT datab (1379:1379:1379) (1383:1383:1383)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44305,15 +32464,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~42) + (INSTANCE D\[6\]\~101) (DELAY (ABSOLUTE - (PORT dataa (1832:1832:1832) (1928:1928:1928)) - (PORT datab (2143:2143:2143) (2278:2278:2278)) - (PORT datac (3268:3268:3268) (3487:3487:3487)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (947:947:947) (995:995:995)) + (PORT datab (894:894:894) (965:965:965)) + (PORT datac (1645:1645:1645) (1669:1669:1669)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44321,45 +32480,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~48) + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) (DELAY (ABSOLUTE - (PORT dataa (695:695:695) (718:718:718)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (1323:1323:1323) (1333:1333:1333)) - (PORT datad (700:700:700) (766:766:766)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (749:749:749)) - (PORT datab (1199:1199:1199) (1289:1289:1289)) - (PORT datac (256:256:256) (334:334:334)) - (PORT datad (565:565:565) (577:577:577)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (1341:1341:1341) (1426:1426:1426)) - (PORT datab (227:227:227) (269:269:269)) - (PORT datac (1231:1231:1231) (1319:1319:1319)) - (PORT datad (876:876:876) (907:907:907)) + (PORT dataa (275:275:275) (336:336:336)) + (PORT datab (1389:1389:1389) (1429:1429:1429)) + (PORT datac (938:938:938) (1004:1004:1004)) + (PORT datad (830:830:830) (833:833:833)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -44368,13 +32495,45 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[0\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) (DELAY (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) + (PORT dataa (1684:1684:1684) (1826:1826:1826)) + (PORT datab (754:754:754) (857:857:857)) + (PORT datac (961:961:961) (1023:1023:1023)) + (PORT datad (1204:1204:1204) (1263:1263:1263)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (1041:1041:1041)) + (PORT datab (973:973:973) (1033:1033:1033)) + (PORT datac (961:961:961) (1024:1024:1024)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) + (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -44385,43 +32544,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~14) + (INSTANCE z80_\|bus_control_\|db\[6\]\~9) (DELAY (ABSOLUTE - (PORT dataa (691:691:691) (724:724:724)) - (PORT datac (926:926:926) (968:968:968)) - (PORT datad (1019:1019:1019) (1049:1049:1049)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1317:1317:1317)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (609:609:609) (655:655:655)) - (PORT datad (812:812:812) (820:820:820)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (1178:1178:1178) (1226:1226:1226)) + (PORT datac (224:224:224) (273:273:273)) + (PORT datad (210:210:210) (243:243:243)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[0\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) + (PORT datad (195:195:195) (219:219:219)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1191:1191:1191)) + (PORT datab (909:909:909) (972:972:972)) + (PORT datac (661:661:661) (712:712:712)) + (PORT datad (375:375:375) (392:392:392)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) + (PORT clrn (1577:1577:1577) (1557:1557:1557)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -44433,13 +32604,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) + (INSTANCE z80_\|pla_decode_\|Equal41\~0) (DELAY (ABSOLUTE - (PORT datab (2147:2147:2147) (2201:2201:2201)) - (PORT datac (1401:1401:1401) (1478:1478:1478)) - (PORT datad (1373:1373:1373) (1416:1416:1416)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT datac (1703:1703:1703) (1754:1754:1754)) + (PORT datad (1223:1223:1223) (1322:1322:1322)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44447,15 +32616,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) + (INSTANCE z80_\|pla_decode_\|Equal41\~1) (DELAY (ABSOLUTE - (PORT dataa (1244:1244:1244) (1350:1350:1350)) - (PORT datab (746:746:746) (828:828:828)) - (PORT datac (1316:1316:1316) (1365:1365:1365)) - (PORT datad (820:820:820) (852:852:852)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (1499:1499:1499) (1573:1573:1573)) + (PORT datab (2298:2298:2298) (2366:2366:2366)) + (PORT datac (2132:2132:2132) (2282:2282:2282)) + (PORT datad (1454:1454:1454) (1538:1538:1538)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (502:502:502)) + (PORT datab (1649:1649:1649) (1644:1644:1644)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1095:1095:1095) (1127:1127:1127)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (1962:1962:1962) (2070:2070:2070)) + (PORT datab (1125:1125:1125) (1133:1133:1133)) + (PORT datac (2059:2059:2059) (2181:2181:2181)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44463,61 +32664,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1363:1363:1363) (1373:1373:1373)) - (PORT datab (1624:1624:1624) (1610:1610:1610)) - (PORT datac (844:844:844) (876:876:876)) - (PORT datad (642:642:642) (674:674:674)) + (PORT dataa (1180:1180:1180) (1214:1214:1214)) + (PORT datab (292:292:292) (354:354:354)) + (PORT datac (259:259:259) (316:316:316)) + (PORT datad (245:245:245) (290:290:290)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) - (DELAY - (ABSOLUTE - (PORT datab (620:620:620) (671:671:671)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (560:560:560) (570:570:570)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (915:915:915)) - (PORT datab (649:649:649) (667:667:667)) - (PORT datac (845:845:845) (862:862:862)) - (PORT datad (823:823:823) (824:824:824)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (269:269:269)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (831:831:831) (890:890:890)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1202:1202:1202)) + (PORT datab (1172:1172:1172) (1221:1221:1221)) + (PORT datac (419:419:419) (491:491:491)) + (PORT datad (660:660:660) (723:723:723)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (1002:1002:1002)) + (PORT datac (1667:1667:1667) (1748:1748:1748)) + (PORT datad (900:900:900) (923:923:923)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (201:201:201) (240:240:240)) + (PORT datac (891:891:891) (913:913:913)) + (PORT datad (244:244:244) (286:286:286)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (390:390:390)) + (PORT datab (631:631:631) (659:659:659)) + (PORT datac (1160:1160:1160) (1204:1204:1204)) + (PORT datad (606:606:606) (623:623:623)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44525,13 +32740,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (INSTANCE z80_\|alu_\|db_high\[1\]\~20) (DELAY (ABSOLUTE - (PORT datab (1085:1085:1085) (1092:1092:1092)) - (PORT datac (1008:1008:1008) (1033:1033:1033)) - (PORT datad (215:215:215) (249:249:249)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (999:999:999) (1032:1032:1032)) + (PORT datac (582:582:582) (614:614:614)) + (PORT datad (221:221:221) (263:263:263)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44539,16 +32756,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~1) + (INSTANCE z80_\|alu_\|db\[5\]\~24) (DELAY (ABSOLUTE - (PORT dataa (1246:1246:1246) (1282:1282:1282)) - (PORT datab (668:668:668) (700:700:700)) - (PORT datac (1045:1045:1045) (1120:1120:1120)) - (PORT datad (212:212:212) (245:245:245)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1300:1300:1300) (1351:1351:1351)) + (PORT datab (940:940:940) (958:958:958)) + (PORT datac (1822:1822:1822) (1884:1884:1884)) + (PORT datad (931:931:931) (981:981:981)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (673:673:673)) + (PORT datab (255:255:255) (313:313:313)) + (PORT datac (175:175:175) (209:209:209)) + (PORT datad (945:945:945) (988:988:988)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (501:501:501)) + (PORT datab (1351:1351:1351) (1413:1413:1413)) + (PORT datac (1147:1147:1147) (1181:1181:1181)) + (PORT datad (1196:1196:1196) (1243:1243:1243)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -44558,10 +32807,10 @@ (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) (DELAY (ABSOLUTE - (PORT dataa (424:424:424) (475:475:475)) - (PORT datab (888:888:888) (902:902:902)) - (PORT datac (845:845:845) (884:884:884)) - (PORT datad (232:232:232) (267:267:267)) + (PORT dataa (556:556:556) (578:578:578)) + (PORT datab (623:623:623) (651:651:651)) + (PORT datac (663:663:663) (695:695:695)) + (PORT datad (679:679:679) (697:697:697)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -44574,7 +32823,7 @@ (INSTANCE z80_\|alu_flags_\|flags_yf) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1548:1548:1548)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -44587,47 +32836,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~27) + (INSTANCE z80_\|alu_control_\|db\[5\]\~13) (DELAY (ABSOLUTE - (PORT dataa (1342:1342:1342) (1406:1406:1406)) - (PORT datab (639:639:639) (699:699:699)) - (PORT datac (632:632:632) (679:679:679)) - (PORT datad (679:679:679) (760:760:760)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (644:644:644) (702:702:702)) + (PORT datab (900:900:900) (949:949:949)) + (PORT datac (666:666:666) (693:693:693)) + (PORT datad (888:888:888) (905:905:905)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~28) + (INSTANCE z80_\|alu_control_\|db\[5\]\~14) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (270:270:270)) - (PORT datab (635:635:635) (654:654:654)) - (PORT datac (865:865:865) (874:874:874)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (675:675:675) (703:703:703)) - (PORT datac (812:812:812) (848:848:848)) - (PORT datad (618:618:618) (669:669:669)) + (PORT dataa (969:969:969) (987:987:987)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (948:948:948) (982:982:982)) + (PORT datad (864:864:864) (880:880:880)) (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44635,13 +32868,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~68) + (INSTANCE z80_\|alu_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT dataa (2078:2078:2078) (2105:2105:2105)) - (PORT datab (1531:1531:1531) (1589:1589:1589)) - (PORT datac (3031:3031:3031) (3276:3276:3276)) - (PORT datad (2409:2409:2409) (2559:2559:2559)) + (PORT dataa (685:685:685) (717:717:717)) + (PORT datab (1197:1197:1197) (1212:1212:1212)) + (PORT datac (1119:1119:1119) (1150:1150:1150)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (1749:1749:1749) (1858:1858:1858)) + (PORT datab (1231:1231:1231) (1298:1298:1298)) + (PORT datac (1559:1559:1559) (1700:1700:1700)) + (PORT datad (1126:1126:1126) (1171:1171:1171)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -44649,12 +32898,487 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1190:1190:1190) (1230:1230:1230)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3686:3686:3686) (3900:3900:3900)) + (PORT d[1] (1735:1735:1735) (1904:1904:1904)) + (PORT d[2] (3045:3045:3045) (3164:3164:3164)) + (PORT d[3] (1901:1901:1901) (2003:2003:2003)) + (PORT d[4] (2206:2206:2206) (2342:2342:2342)) + (PORT d[5] (2677:2677:2677) (2865:2865:2865)) + (PORT d[6] (2060:2060:2060) (2133:2133:2133)) + (PORT d[7] (2769:2769:2769) (2894:2894:2894)) + (PORT d[8] (3033:3033:3033) (3241:3241:3241)) + (PORT d[9] (2831:2831:2831) (2926:2926:2926)) + (PORT d[10] (3516:3516:3516) (3751:3751:3751)) + (PORT d[11] (1807:1807:1807) (1907:1907:1907)) + (PORT d[12] (2081:2081:2081) (2168:2168:2168)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1939:1939:1939) (1956:1956:1956)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (2676:2676:2676) (2715:2715:2715)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1180:1180:1180) (1209:1209:1209)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3984:3984:3984) (4216:4216:4216)) + (PORT d[1] (1704:1704:1704) (1855:1855:1855)) + (PORT d[2] (3307:3307:3307) (3443:3443:3443)) + (PORT d[3] (1880:1880:1880) (1997:1997:1997)) + (PORT d[4] (1863:1863:1863) (1963:1963:1963)) + (PORT d[5] (1643:1643:1643) (1769:1769:1769)) + (PORT d[6] (1761:1761:1761) (1817:1817:1817)) + (PORT d[7] (3056:3056:3056) (3189:3189:3189)) + (PORT d[8] (3324:3324:3324) (3551:3551:3551)) + (PORT d[9] (2869:2869:2869) (2985:2985:2985)) + (PORT d[10] (3454:3454:3454) (3652:3652:3652)) + (PORT d[11] (1540:1540:1540) (1618:1618:1618)) + (PORT d[12] (1726:1726:1726) (1787:1787:1787)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1932:1932:1932) (1890:1890:1890)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (2406:2406:2406) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1218:1218:1218) (1268:1268:1268)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3686:3686:3686) (3901:3901:3901)) + (PORT d[1] (1692:1692:1692) (1858:1858:1858)) + (PORT d[2] (2977:2977:2977) (3118:3118:3118)) + (PORT d[3] (2124:2124:2124) (2230:2230:2230)) + (PORT d[4] (2237:2237:2237) (2352:2352:2352)) + (PORT d[5] (2684:2684:2684) (2875:2875:2875)) + (PORT d[6] (1801:1801:1801) (1880:1880:1880)) + (PORT d[7] (2772:2772:2772) (2901:2901:2901)) + (PORT d[8] (3346:3346:3346) (3575:3575:3575)) + (PORT d[9] (2889:2889:2889) (3004:3004:3004)) + (PORT d[10] (3484:3484:3484) (3709:3709:3709)) + (PORT d[11] (1816:1816:1816) (1924:1924:1924)) + (PORT d[12] (2023:2023:2023) (2090:2090:2090)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1889:1889:1889) (1883:1883:1883)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (2482:2482:2482) (2488:2488:2488)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1446:1446:1446) (1499:1499:1499)) + (PORT datab (1431:1431:1431) (1517:1517:1517)) + (PORT datac (1141:1141:1141) (1132:1132:1132)) + (PORT datad (1111:1111:1111) (1136:1136:1136)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1872:1872:1872) (1991:1991:1991)) + (PORT d[0] (1272:1272:1272) (1326:1326:1326)) (PORT clk (1855:1855:1855) (1883:1883:1883)) ) ) @@ -44667,19 +33391,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3467:3467:3467) (3745:3745:3745)) - (PORT d[1] (2402:2402:2402) (2573:2573:2573)) - (PORT d[2] (2265:2265:2265) (2486:2486:2486)) - (PORT d[3] (3297:3297:3297) (3609:3609:3609)) - (PORT d[4] (2871:2871:2871) (3081:3081:3081)) - (PORT d[5] (3662:3662:3662) (3924:3924:3924)) - (PORT d[6] (1692:1692:1692) (1738:1738:1738)) - (PORT d[7] (3122:3122:3122) (3233:3233:3233)) - (PORT d[8] (2503:2503:2503) (2661:2661:2661)) - (PORT d[9] (2575:2575:2575) (2676:2676:2676)) - (PORT d[10] (2638:2638:2638) (2792:2792:2792)) - (PORT d[11] (1527:1527:1527) (1657:1657:1657)) - (PORT d[12] (2496:2496:2496) (2590:2590:2590)) + (PORT d[0] (2887:2887:2887) (3004:3004:3004)) + (PORT d[1] (2662:2662:2662) (2916:2916:2916)) + (PORT d[2] (1218:1218:1218) (1257:1257:1257)) + (PORT d[3] (1701:1701:1701) (1750:1750:1750)) + (PORT d[4] (2885:2885:2885) (3119:3119:3119)) + (PORT d[5] (2382:2382:2382) (2607:2607:2607)) + (PORT d[6] (1263:1263:1263) (1339:1339:1339)) + (PORT d[7] (1323:1323:1323) (1404:1404:1404)) + (PORT d[8] (1739:1739:1739) (1814:1814:1814)) + (PORT d[9] (1262:1262:1262) (1335:1335:1335)) + (PORT d[10] (2409:2409:2409) (2560:2560:2560)) + (PORT d[11] (3166:3166:3166) (3381:3381:3381)) + (PORT d[12] (2205:2205:2205) (2307:2307:2307)) (PORT clk (1852:1852:1852) (1879:1879:1879)) ) ) @@ -44692,7 +33416,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2008:2008:2008) (1989:1989:1989)) + (PORT d[0] (1501:1501:1501) (1496:1496:1496)) (PORT clk (1852:1852:1852) (1879:1879:1879)) ) ) @@ -44706,7 +33430,7 @@ (DELAY (ABSOLUTE (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (3416:3416:3416) (3478:3478:3478)) + (PORT d[0] (2128:2128:2128) (2120:2120:2120)) ) ) ) @@ -44802,601 +33526,29 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2240:2240:2240) (2402:2402:2402)) - (PORT clk (1844:1844:1844) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2233:2233:2233) (2400:2400:2400)) - (PORT d[1] (2732:2732:2732) (2931:2931:2931)) - (PORT d[2] (4344:4344:4344) (4589:4589:4589)) - (PORT d[3] (3583:3583:3583) (3920:3920:3920)) - (PORT d[4] (1582:1582:1582) (1706:1706:1706)) - (PORT d[5] (4291:4291:4291) (4604:4604:4604)) - (PORT d[6] (2306:2306:2306) (2432:2432:2432)) - (PORT d[7] (2514:2514:2514) (2599:2599:2599)) - (PORT d[8] (3671:3671:3671) (3890:3890:3890)) - (PORT d[9] (2215:2215:2215) (2314:2314:2314)) - (PORT d[10] (1588:1588:1588) (1677:1677:1677)) - (PORT d[11] (1555:1555:1555) (1689:1689:1689)) - (PORT d[12] (1907:1907:1907) (1966:1966:1966)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2603:2603:2603) (2611:2611:2611)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (PORT d[0] (2332:2332:2332) (2359:2359:2359)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1804:1804:1804) (1832:1832:1832)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2843:2843:2843) (2980:2980:2980)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3108:3108:3108) (3310:3310:3310)) - (PORT d[1] (1731:1731:1731) (1868:1868:1868)) - (PORT d[2] (2866:2866:2866) (3091:3091:3091)) - (PORT d[3] (2300:2300:2300) (2508:2508:2508)) - (PORT d[4] (2242:2242:2242) (2408:2408:2408)) - (PORT d[5] (2741:2741:2741) (2938:2938:2938)) - (PORT d[6] (1992:1992:1992) (2098:2098:2098)) - (PORT d[7] (4304:4304:4304) (4466:4466:4466)) - (PORT d[8] (2436:2436:2436) (2597:2597:2597)) - (PORT d[9] (2798:2798:2798) (2942:2942:2942)) - (PORT d[10] (1927:1927:1927) (2075:2075:2075)) - (PORT d[11] (1917:1917:1917) (2087:2087:2087)) - (PORT d[12] (3449:3449:3449) (3586:3586:3586)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1980:1980:1980) (2014:2014:2014)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (2673:2673:2673) (2735:2735:2735)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1844:1844:1844)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1008:1008:1008)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1008:1008:1008)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2141:2141:2141) (2269:2269:2269)) - (PORT clk (1868:1868:1868) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2720:2720:2720) (2880:2880:2880)) - (PORT d[1] (1602:1602:1602) (1675:1675:1675)) - (PORT d[2] (3072:3072:3072) (3375:3375:3375)) - (PORT d[3] (2590:2590:2590) (2797:2797:2797)) - (PORT d[4] (2311:2311:2311) (2523:2523:2523)) - (PORT d[5] (2345:2345:2345) (2483:2483:2483)) - (PORT d[6] (2314:2314:2314) (2461:2461:2461)) - (PORT d[7] (2712:2712:2712) (2885:2885:2885)) - (PORT d[8] (3028:3028:3028) (3224:3224:3224)) - (PORT d[9] (3544:3544:3544) (3640:3640:3640)) - (PORT d[10] (2567:2567:2567) (2756:2756:2756)) - (PORT d[11] (2775:2775:2775) (2996:2996:2996)) - (PORT d[12] (3594:3594:3594) (3731:3731:3731)) - (PORT clk (1865:1865:1865) (1890:1890:1890)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2041:2041:2041) (2077:2077:2077)) - (PORT clk (1865:1865:1865) (1890:1890:1890)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1868:1868:1868) (1894:1894:1894)) - (PORT d[0] (2499:2499:2499) (2501:2501:2501)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1828:1828:1828) (1853:1853:1853)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1013:1013:1013) (1016:1016:1016)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1014:1014:1014) (1017:1017:1017)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1014:1014:1014) (1017:1017:1017)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1014:1014:1014) (1017:1017:1017)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) (DELAY (ABSOLUTE - (PORT dataa (2003:2003:2003) (2082:2082:2082)) - (PORT datab (1198:1198:1198) (1282:1282:1282)) - (PORT datac (2200:2200:2200) (2281:2281:2281)) - (PORT datad (305:305:305) (411:411:411)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1130:1130:1130) (1175:1175:1175)) + (PORT datab (1704:1704:1704) (1781:1781:1781)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1426:1426:1426) (1482:1482:1482)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (955:955:955)) - (PORT datab (943:943:943) (970:970:970)) - (PORT datac (1159:1159:1159) (1237:1237:1237)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1357:1357:1357) (1435:1435:1435)) - (PORT d[1] (2822:2822:2822) (3106:3106:3106)) - (PORT d[2] (1988:1988:1988) (2120:2120:2120)) - (PORT d[3] (404:404:404) (434:434:434)) - (PORT d[4] (655:655:655) (679:679:679)) - (PORT d[5] (1546:1546:1546) (1644:1644:1644)) - (PORT d[6] (2947:2947:2947) (3107:3107:3107)) - (PORT d[7] (2315:2315:2315) (2423:2423:2423)) - (PORT d[8] (4005:4005:4005) (4246:4246:4246)) - (PORT d[9] (910:910:910) (914:914:914)) - (PORT d[10] (2299:2299:2299) (2476:2476:2476)) - (PORT d[11] (2222:2222:2222) (2438:2438:2438)) - (PORT d[12] (1107:1107:1107) (1112:1112:1112)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (1700:1700:1700) (1735:1735:1735)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1581:1581:1581) (1671:1671:1671)) - (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (1607:1607:1607) (1720:1720:1720)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) ) ) (TIMINGCHECK @@ -45408,20 +33560,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1377:1377:1377) (1490:1490:1490)) - (PORT d[1] (2047:2047:2047) (2146:2146:2146)) - (PORT d[2] (2140:2140:2140) (2247:2247:2247)) - (PORT d[3] (3064:3064:3064) (3285:3285:3285)) - (PORT d[4] (2586:2586:2586) (2808:2808:2808)) - (PORT d[5] (1550:1550:1550) (1656:1656:1656)) - (PORT d[6] (2560:2560:2560) (2711:2711:2711)) - (PORT d[7] (2705:2705:2705) (2880:2880:2880)) - (PORT d[8] (1784:1784:1784) (1878:1878:1878)) - (PORT d[9] (4368:4368:4368) (4512:4512:4512)) - (PORT d[10] (1908:1908:1908) (1970:1970:1970)) - (PORT d[11] (3582:3582:3582) (3824:3824:3824)) - (PORT d[12] (2698:2698:2698) (2834:2834:2834)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (3186:3186:3186) (3300:3300:3300)) + (PORT d[1] (2007:2007:2007) (2188:2188:2188)) + (PORT d[2] (2193:2193:2193) (2290:2290:2290)) + (PORT d[3] (1861:1861:1861) (1989:1989:1989)) + (PORT d[4] (2485:2485:2485) (2606:2606:2606)) + (PORT d[5] (2236:2236:2236) (2402:2402:2402)) + (PORT d[6] (1711:1711:1711) (1755:1755:1755)) + (PORT d[7] (1687:1687:1687) (1776:1776:1776)) + (PORT d[8] (2608:2608:2608) (2791:2791:2791)) + (PORT d[9] (1955:1955:1955) (2077:2077:2077)) + (PORT d[10] (2011:2011:2011) (2111:2111:2111)) + (PORT d[11] (2425:2425:2425) (2555:2555:2555)) + (PORT d[12] (2552:2552:2552) (2625:2625:2625)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) ) ) (TIMINGCHECK @@ -45433,8 +33585,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1520:1520:1520) (1502:1502:1502)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (2563:2563:2563) (2536:2536:2536)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) ) ) (TIMINGCHECK @@ -45446,8 +33598,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (PORT d[0] (2914:2914:2914) (2928:2928:2928)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (PORT d[0] (3968:3968:3968) (4054:4054:4054)) ) ) ) @@ -45456,7 +33608,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -45466,7 +33618,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -45476,7 +33628,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -45486,7 +33638,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -45496,7 +33648,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1808:1808:1808) (1806:1806:1806)) + (PORT clk (1807:1807:1807) (1805:1805:1805)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -45510,8 +33662,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (3115:3115:3115) (3204:3204:3204)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) + (PORT d[0] (1738:1738:1738) (1727:1727:1727)) + (PORT clk (1817:1817:1817) (1811:1811:1811)) ) ) (TIMINGCHECK @@ -45523,20 +33675,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1862:1862:1862) (1985:1985:1985)) - (PORT d[1] (1922:1922:1922) (2028:2028:2028)) - (PORT d[2] (1880:1880:1880) (1998:1998:1998)) - (PORT d[3] (1835:1835:1835) (1959:1959:1959)) - (PORT d[4] (2160:2160:2160) (2252:2252:2252)) - (PORT d[5] (2115:2115:2115) (2201:2201:2201)) - (PORT d[6] (1788:1788:1788) (1890:1890:1890)) - (PORT d[7] (1904:1904:1904) (2023:2023:2023)) - (PORT d[8] (1919:1919:1919) (2043:2043:2043)) - (PORT d[9] (1950:1950:1950) (1997:1997:1997)) - (PORT d[10] (1889:1889:1889) (1990:1990:1990)) - (PORT d[11] (2026:2026:2026) (2123:2123:2123)) - (PORT d[12] (1894:1894:1894) (2005:2005:2005)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) + (PORT d[0] (4391:4391:4391) (4458:4458:4458)) + (PORT d[1] (4215:4215:4215) (4261:4261:4261)) + (PORT d[2] (4322:4322:4322) (4388:4388:4388)) + (PORT d[3] (4683:4683:4683) (4718:4718:4718)) + (PORT d[4] (4355:4355:4355) (4366:4366:4366)) + (PORT d[5] (4618:4618:4618) (4672:4672:4672)) + (PORT d[6] (4745:4745:4745) (4781:4781:4781)) + (PORT d[7] (4330:4330:4330) (4399:4399:4399)) + (PORT d[8] (4420:4420:4420) (4455:4455:4455)) + (PORT d[9] (4477:4477:4477) (4721:4721:4721)) + (PORT d[10] (4604:4604:4604) (4600:4600:4600)) + (PORT d[11] (4406:4406:4406) (4437:4437:4437)) + (PORT d[12] (4503:4503:4503) (4638:4638:4638)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) ) ) (TIMINGCHECK @@ -45548,7 +33700,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) + (PORT clk (1817:1817:1817) (1811:1811:1811)) ) ) ) @@ -45557,7 +33709,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -45567,7 +33719,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) ) ) ) @@ -45576,7 +33728,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -45586,7 +33738,104 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2857:2857:2857) (2972:2972:2972)) + (PORT d[1] (1730:1730:1730) (1897:1897:1897)) + (PORT d[2] (1950:1950:1950) (2070:2070:2070)) + (PORT d[3] (1897:1897:1897) (2023:2023:2023)) + (PORT d[4] (2739:2739:2739) (2895:2895:2895)) + (PORT d[5] (2232:2232:2232) (2412:2412:2412)) + (PORT d[6] (1964:1964:1964) (2031:2031:2031)) + (PORT d[7] (2136:2136:2136) (2268:2268:2268)) + (PORT d[8] (2383:2383:2383) (2561:2561:2561)) + (PORT d[9] (1973:1973:1973) (2079:2079:2079)) + (PORT d[10] (1681:1681:1681) (1740:1740:1740)) + (PORT d[11] (2036:2036:2036) (2101:2101:2101)) + (PORT d[12] (2509:2509:2509) (2578:2578:2578)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1882:1882:1882)) + (PORT d[0] (2716:2716:2716) (2794:2794:2794)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1009:1009:1009)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -45596,20 +33845,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1067:1067:1067) (1136:1136:1136)) - (PORT d[1] (3088:3088:3088) (3354:3354:3354)) - (PORT d[2] (1617:1617:1617) (1725:1725:1725)) - (PORT d[3] (731:731:731) (787:787:787)) - (PORT d[4] (954:954:954) (1000:1000:1000)) - (PORT d[5] (1258:1258:1258) (1337:1337:1337)) - (PORT d[6] (2620:2620:2620) (2771:2771:2771)) - (PORT d[7] (2318:2318:2318) (2444:2444:2444)) - (PORT d[8] (3182:3182:3182) (3425:3425:3425)) - (PORT d[9] (2995:2995:2995) (3074:3074:3074)) - (PORT d[10] (2620:2620:2620) (2823:2823:2823)) - (PORT d[11] (2195:2195:2195) (2412:2412:2412)) - (PORT d[12] (2418:2418:2418) (2498:2498:2498)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (3922:3922:3922) (4160:4160:4160)) + (PORT d[1] (2875:2875:2875) (3108:3108:3108)) + (PORT d[2] (2719:2719:2719) (2815:2815:2815)) + (PORT d[3] (2274:2274:2274) (2436:2436:2436)) + (PORT d[4] (2511:2511:2511) (2691:2691:2691)) + (PORT d[5] (2520:2520:2520) (2696:2696:2696)) + (PORT d[6] (1898:1898:1898) (2018:2018:2018)) + (PORT d[7] (2284:2284:2284) (2398:2398:2398)) + (PORT d[8] (3090:3090:3090) (3363:3363:3363)) + (PORT d[9] (2691:2691:2691) (2835:2835:2835)) + (PORT d[10] (4531:4531:4531) (4774:4774:4774)) + (PORT d[11] (1925:1925:1925) (2083:2083:2083)) + (PORT d[12] (2422:2422:2422) (2553:2553:2553)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -45621,1802 +33870,14 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1877:1877:1877)) - (PORT d[0] (2000:2000:2000) (1970:1970:1970)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (3644:3644:3644) (3567:3567:3567)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1567:1567:1567) (1645:1645:1645)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1398:1398:1398) (1514:1514:1514)) - (PORT d[1] (1369:1369:1369) (1449:1449:1449)) - (PORT d[2] (1873:1873:1873) (1979:1979:1979)) - (PORT d[3] (3065:3065:3065) (3286:3286:3286)) - (PORT d[4] (2873:2873:2873) (3117:3117:3117)) - (PORT d[5] (1501:1501:1501) (1584:1584:1584)) - (PORT d[6] (2596:2596:2596) (2749:2749:2749)) - (PORT d[7] (2678:2678:2678) (2847:2847:2847)) - (PORT d[8] (1638:1638:1638) (1702:1702:1702)) - (PORT d[9] (4352:4352:4352) (4493:4493:4493)) - (PORT d[10] (1927:1927:1927) (1983:1983:1983)) - (PORT d[11] (3583:3583:3583) (3825:3825:3825)) - (PORT d[12] (2720:2720:2720) (2857:2857:2857)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1498:1498:1498) (1468:1468:1468)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (2122:2122:2122) (2089:2089:2089)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1808:1808:1808)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3114:3114:3114) (3202:3202:3202)) - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1869:1869:1869) (1993:1993:1993)) - (PORT d[1] (1911:1911:1911) (1998:1998:1998)) - (PORT d[2] (1838:1838:1838) (1948:1948:1948)) - (PORT d[3] (1841:1841:1841) (1955:1955:1955)) - (PORT d[4] (1862:1862:1862) (1947:1947:1947)) - (PORT d[5] (1778:1778:1778) (1863:1863:1863)) - (PORT d[6] (1805:1805:1805) (1932:1932:1932)) - (PORT d[7] (1906:1906:1906) (2042:2042:2042)) - (PORT d[8] (1886:1886:1886) (2004:2004:2004)) - (PORT d[9] (2049:2049:2049) (2132:2132:2132)) - (PORT d[10] (1899:1899:1899) (2003:2003:2003)) - (PORT d[11] (2004:2004:2004) (2070:2070:2070)) - (PORT d[12] (1900:1900:1900) (1951:1951:1951)) - (PORT clk (1816:1816:1816) (1810:1810:1810)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (729:729:729)) - (PORT datab (980:980:980) (1046:1046:1046)) - (PORT datac (981:981:981) (1079:1079:1079)) - (PORT datad (1494:1494:1494) (1560:1560:1560)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1008:1008:1008) (1118:1118:1118)) - (PORT datab (990:990:990) (1033:1033:1033)) - (PORT datac (1405:1405:1405) (1485:1485:1485)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1054:1054:1054)) - (PORT datab (1203:1203:1203) (1265:1265:1265)) - (PORT datac (2674:2674:2674) (2864:2864:2864)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (963:963:963)) - (PORT datab (1209:1209:1209) (1309:1309:1309)) - (PORT datac (1393:1393:1393) (1460:1460:1460)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~80) - (DELAY - (ABSOLUTE - (PORT datac (920:920:920) (971:971:971)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (1345:1345:1345) (1423:1423:1423)) - (PORT datab (1270:1270:1270) (1356:1356:1356)) - (PORT datac (856:856:856) (891:891:891)) - (PORT datad (882:882:882) (932:932:932)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1057:1057:1057) (1093:1093:1093)) - (PORT datab (1130:1130:1130) (1180:1180:1180)) - (PORT datad (643:643:643) (672:672:672)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1317:1317:1317)) - (PORT datab (849:849:849) (874:874:874)) - (PORT datac (609:609:609) (655:655:655)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2309:2309:2309) (2384:2384:2384)) - (PORT datab (1876:1876:1876) (1946:1946:1946)) - (PORT datac (2012:2012:2012) (2093:2093:2093)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1470:1470:1470)) - (PORT datab (926:926:926) (979:979:979)) - (PORT datad (1299:1299:1299) (1369:1369:1369)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1042:1042:1042)) - (PORT datab (658:658:658) (709:709:709)) - (PORT datac (1161:1161:1161) (1181:1181:1181)) - (PORT datad (812:812:812) (831:831:831)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (1003:1003:1003)) - (PORT datab (692:692:692) (741:741:741)) - (PORT datac (814:814:814) (883:883:883)) - (PORT datad (595:595:595) (611:611:611)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (829:829:829)) - (PORT datab (654:654:654) (702:702:702)) - (PORT datac (847:847:847) (877:877:877)) - (PORT datad (1016:1016:1016) (1021:1021:1021)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (386:386:386)) - (PORT datab (378:378:378) (403:403:403)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (848:848:848) (859:859:859)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (710:710:710)) - (PORT datab (1037:1037:1037) (1110:1110:1110)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (526:526:526) (544:544:544)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1393:1393:1393)) - (PORT datab (639:639:639) (679:679:679)) - (PORT datac (1458:1458:1458) (1490:1490:1490)) - (PORT datad (931:931:931) (961:961:961)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (871:871:871)) - (PORT datab (701:701:701) (749:749:749)) - (PORT datac (1784:1784:1784) (1776:1776:1776)) - (PORT datad (1065:1065:1065) (1110:1110:1110)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (933:933:933)) - (PORT datab (1110:1110:1110) (1130:1130:1130)) - (PORT datac (394:394:394) (434:434:434)) - (PORT datad (649:649:649) (663:663:663)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1237:1237:1237) (1240:1240:1240)) - (PORT datab (1110:1110:1110) (1127:1127:1127)) - (PORT datac (1570:1570:1570) (1594:1594:1594)) - (PORT datad (1120:1120:1120) (1149:1149:1149)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (184:184:184) (214:214:214)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1036:1036:1036)) - (PORT datab (666:666:666) (723:723:723)) - (PORT datac (1566:1566:1566) (1597:1597:1597)) - (PORT datad (917:917:917) (1021:1021:1021)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (776:776:776)) - (PORT datab (579:579:579) (621:621:621)) - (PORT datac (1566:1566:1566) (1599:1599:1599)) - (PORT datad (633:633:633) (686:686:686)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (644:644:644) (675:675:675)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1244:1244:1244) (1351:1351:1351)) - (PORT datab (610:610:610) (644:644:644)) - (PORT datac (1314:1314:1314) (1364:1364:1364)) - (PORT datad (821:821:821) (854:854:854)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (600:600:600)) - (PORT datab (1147:1147:1147) (1203:1203:1203)) - (PORT datac (814:814:814) (852:852:852)) - (PORT datad (563:563:563) (570:570:570)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1515:1515:1515) (1575:1575:1575)) - (PORT datab (977:977:977) (1008:1008:1008)) - (PORT datac (1197:1197:1197) (1201:1201:1201)) - (PORT datad (224:224:224) (259:259:259)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (610:610:610)) - (PORT datab (1149:1149:1149) (1207:1207:1207)) - (PORT datac (622:622:622) (649:649:649)) - (PORT datad (313:313:313) (333:333:333)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1118:1118:1118)) - (PORT datab (1065:1065:1065) (1111:1111:1111)) - (PORT datac (618:618:618) (640:640:640)) - (PORT datad (1113:1113:1113) (1121:1121:1121)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (614:614:614)) - (PORT datab (552:552:552) (580:580:580)) - (PORT datac (1506:1506:1506) (1510:1510:1510)) - (PORT datad (562:562:562) (571:571:571)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (1772:1772:1772) (1843:1843:1843)) - (PORT datac (1452:1452:1452) (1508:1508:1508)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1189:1189:1189)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (871:871:871)) - (PORT datab (841:841:841) (869:869:869)) - (PORT datac (821:821:821) (836:836:836)) - (PORT datad (611:611:611) (624:624:624)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (730:730:730)) - (PORT datab (401:401:401) (447:447:447)) - (PORT datac (1010:1010:1010) (1010:1010:1010)) - (PORT datad (328:328:328) (350:350:350)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (896:896:896)) - (PORT datab (1519:1519:1519) (1518:1518:1518)) - (PORT datac (990:990:990) (1015:1015:1015)) - (PORT datad (1042:1042:1042) (1044:1044:1044)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~39) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (1360:1360:1360) (1346:1346:1346)) - (PORT datac (848:848:848) (871:871:871)) - (PORT datad (1063:1063:1063) (1077:1077:1077)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (693:693:693)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (585:585:585) (597:597:597)) - (PORT datad (1280:1280:1280) (1302:1302:1302)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (615:615:615) (678:678:678)) - (PORT datac (502:502:502) (513:513:513)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) - (DELAY - (ABSOLUTE - (PORT dataa (1073:1073:1073) (1082:1082:1082)) - (PORT datab (209:209:209) (251:251:251)) - (PORT datad (1048:1048:1048) (1107:1107:1107)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1717:1717:1717) (1872:1872:1872)) - (PORT clk (1845:1845:1845) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2866:2866:2866) (3100:3100:3100)) - (PORT d[1] (1783:1783:1783) (1946:1946:1946)) - (PORT d[2] (2319:2319:2319) (2548:2548:2548)) - (PORT d[3] (2686:2686:2686) (2943:2943:2943)) - (PORT d[4] (2219:2219:2219) (2386:2386:2386)) - (PORT d[5] (3067:3067:3067) (3274:3274:3274)) - (PORT d[6] (1984:1984:1984) (2106:2106:2106)) - (PORT d[7] (3718:3718:3718) (3875:3875:3875)) - (PORT d[8] (2163:2163:2163) (2306:2306:2306)) - (PORT d[9] (2792:2792:2792) (2914:2914:2914)) - (PORT d[10] (1958:1958:1958) (2089:2089:2089)) - (PORT d[11] (1863:1863:1863) (2018:2018:2018)) - (PORT d[12] (3127:3127:3127) (3282:3282:3282)) - (PORT clk (1842:1842:1842) (1870:1870:1870)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2255:2255:2255) (2277:2277:2277)) - (PORT clk (1842:1842:1842) (1870:1870:1870)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (PORT d[0] (2824:2824:2824) (2829:2829:2829)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1833:1833:1833)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1957:1957:1957) (2095:2095:2095)) - (PORT clk (1847:1847:1847) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3163:3163:3163) (3401:3401:3401)) - (PORT d[1] (2074:2074:2074) (2253:2253:2253)) - (PORT d[2] (3143:3143:3143) (3374:3374:3374)) - (PORT d[3] (2675:2675:2675) (2914:2914:2914)) - (PORT d[4] (2247:2247:2247) (2423:2423:2423)) - (PORT d[5] (3044:3044:3044) (3274:3274:3274)) - (PORT d[6] (2298:2298:2298) (2426:2426:2426)) - (PORT d[7] (3691:3691:3691) (3840:3840:3840)) - (PORT d[8] (2159:2159:2159) (2300:2300:2300)) - (PORT d[9] (2799:2799:2799) (2923:2923:2923)) - (PORT d[10] (1971:1971:1971) (2118:2118:2118)) - (PORT d[11] (1870:1870:1870) (2045:2045:2045)) - (PORT d[12] (3145:3145:3145) (3286:3286:3286)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2001:2001:2001) (2020:2020:2020)) - (PORT clk (1844:1844:1844) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (PORT d[0] (3172:3172:3172) (3231:3231:3231)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1702:1702:1702) (1734:1734:1734)) - (PORT clk (1842:1842:1842) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2225:2225:2225) (2392:2392:2392)) - (PORT d[1] (2702:2702:2702) (2914:2914:2914)) - (PORT d[2] (2046:2046:2046) (2229:2229:2229)) - (PORT d[3] (3577:3577:3577) (3925:3925:3925)) - (PORT d[4] (1902:1902:1902) (2026:2026:2026)) - (PORT d[5] (4291:4291:4291) (4608:4608:4608)) - (PORT d[6] (2278:2278:2278) (2399:2399:2399)) - (PORT d[7] (2491:2491:2491) (2574:2574:2574)) - (PORT d[8] (3361:3361:3361) (3559:3559:3559)) - (PORT d[9] (2511:2511:2511) (2611:2611:2611)) - (PORT d[10] (1570:1570:1570) (1669:1669:1669)) - (PORT d[11] (2719:2719:2719) (2859:2859:2859)) - (PORT d[12] (1901:1901:1901) (1951:1951:1951)) - (PORT clk (1839:1839:1839) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2118:2118:2118) (2156:2156:2156)) - (PORT clk (1839:1839:1839) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1871:1871:1871)) - (PORT d[0] (2799:2799:2799) (2874:2874:2874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1802:1802:1802) (1830:1830:1830)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (993:993:993)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (448:448:448)) - (PORT datab (1479:1479:1479) (1543:1543:1543)) - (PORT datac (1157:1157:1157) (1234:1234:1234)) - (PORT datad (924:924:924) (933:933:933)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1388:1388:1388) (1439:1439:1439)) - (PORT clk (1845:1845:1845) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2791:2791:2791) (2923:2923:2923)) - (PORT d[1] (2395:2395:2395) (2583:2583:2583)) - (PORT d[2] (4343:4343:4343) (4588:4588:4588)) - (PORT d[3] (3590:3590:3590) (3895:3895:3895)) - (PORT d[4] (3188:3188:3188) (3408:3408:3408)) - (PORT d[5] (4278:4278:4278) (4576:4576:4576)) - (PORT d[6] (2551:2551:2551) (2687:2687:2687)) - (PORT d[7] (2755:2755:2755) (2837:2837:2837)) - (PORT d[8] (3648:3648:3648) (3866:3866:3866)) - (PORT d[9] (2214:2214:2214) (2313:2313:2313)) - (PORT d[10] (1296:1296:1296) (1384:1384:1384)) - (PORT d[11] (1553:1553:1553) (1685:1685:1685)) - (PORT d[12] (1908:1908:1908) (1968:1968:1968)) - (PORT clk (1842:1842:1842) (1870:1870:1870)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2597:2597:2597) (2614:2614:2614)) - (PORT clk (1842:1842:1842) (1870:1870:1870)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (PORT d[0] (2254:2254:2254) (2277:2277:2277)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1833:1833:1833)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (997:997:997)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1508:1508:1508) (1581:1581:1581)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1156:1156:1156) (1234:1234:1234)) - (PORT datad (865:865:865) (853:853:853)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1359:1359:1359) (1473:1473:1473)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1428:1428:1428) (1520:1520:1520)) - (PORT d[1] (1667:1667:1667) (1746:1746:1746)) - (PORT d[2] (1866:1866:1866) (1993:1993:1993)) - (PORT d[3] (3031:3031:3031) (3271:3271:3271)) - (PORT d[4] (2605:2605:2605) (2825:2825:2825)) - (PORT d[5] (1481:1481:1481) (1557:1557:1557)) - (PORT d[6] (2624:2624:2624) (2778:2778:2778)) - (PORT d[7] (2650:2650:2650) (2811:2811:2811)) - (PORT d[8] (1630:1630:1630) (1680:1680:1680)) - (PORT d[9] (2982:2982:2982) (3092:3092:3092)) - (PORT d[10] (1818:1818:1818) (1873:1873:1873)) - (PORT d[11] (3866:3866:3866) (4125:4125:4125)) - (PORT d[12] (2746:2746:2746) (2888:2888:2888)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1490:1490:1490) (1464:1464:1464)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (2065:2065:2065) (2075:2075:2075)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1809:1809:1809)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3109:3109:3109) (3190:3190:3190)) - (PORT clk (1822:1822:1822) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1865:1865:1865) (2015:2015:2015)) - (PORT d[1] (1871:1871:1871) (1975:1975:1975)) - (PORT d[2] (1853:1853:1853) (1980:1980:1980)) - (PORT d[3] (1872:1872:1872) (2003:2003:2003)) - (PORT d[4] (1898:1898:1898) (2018:2018:2018)) - (PORT d[5] (1812:1812:1812) (1916:1916:1916)) - (PORT d[6] (1838:1838:1838) (1993:1993:1993)) - (PORT d[7] (1899:1899:1899) (2045:2045:2045)) - (PORT d[8] (2050:2050:2050) (2128:2128:2128)) - (PORT d[9] (2042:2042:2042) (2113:2113:2113)) - (PORT d[10] (1921:1921:1921) (2026:2026:2026)) - (PORT d[11] (1965:1965:1965) (2026:2026:2026)) - (PORT d[12] (1978:1978:1978) (2135:2135:2135)) - (PORT clk (1818:1818:1818) (1811:1811:1811)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1358:1358:1358) (1452:1452:1452)) - (PORT d[1] (2823:2823:2823) (3107:3107:3107)) - (PORT d[2] (1690:1690:1690) (1829:1829:1829)) - (PORT d[3] (645:645:645) (661:661:661)) - (PORT d[4] (656:656:656) (681:681:681)) - (PORT d[5] (1547:1547:1547) (1645:1645:1645)) - (PORT d[6] (2651:2651:2651) (2805:2805:2805)) - (PORT d[7] (2295:2295:2295) (2394:2394:2394)) - (PORT d[8] (3180:3180:3180) (3433:3433:3433)) - (PORT d[9] (912:912:912) (929:929:929)) - (PORT d[10] (2265:2265:2265) (2456:2456:2456)) - (PORT d[11] (2834:2834:2834) (2946:2946:2946)) - (PORT d[12] (1140:1140:1140) (1140:1140:1140)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (1672:1672:1672) (1718:1718:1718)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1858:1858:1858) (1884:1884:1884)) @@ -47426,7 +33887,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1820:1820:1820) (1846:1846:1846)) @@ -47440,7 +33901,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1005:1005:1005) (1009:1009:1009)) @@ -47449,7 +33910,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -47458,7 +33919,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -47468,7 +33929,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -47478,23 +33939,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1051:1051:1051) (1127:1127:1127)) - (PORT d[1] (2772:2772:2772) (3012:3012:3012)) - (PORT d[2] (1986:1986:1986) (2112:2112:2112)) - (PORT d[3] (968:968:968) (1019:1019:1019)) - (PORT d[4] (716:716:716) (762:762:762)) - (PORT d[5] (1259:1259:1259) (1338:1338:1338)) - (PORT d[6] (2992:2992:2992) (3153:3153:3153)) - (PORT d[7] (2336:2336:2336) (2449:2449:2449)) - (PORT d[8] (3743:3743:3743) (3972:3972:3972)) - (PORT d[9] (3302:3302:3302) (3404:3404:3404)) - (PORT d[10] (2592:2592:2592) (2790:2790:2790)) - (PORT d[11] (2210:2210:2210) (2410:2410:2410)) - (PORT d[12] (2380:2380:2380) (2492:2492:2492)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) + (PORT d[0] (1502:1502:1502) (1566:1566:1566)) + (PORT clk (1869:1869:1869) (1895:1895:1895)) ) ) (TIMINGCHECK @@ -47503,30 +33952,98 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1879:1879:1879)) - (PORT d[0] (2000:2000:2000) (1970:1970:1970)) + (PORT d[0] (2818:2818:2818) (2896:2896:2896)) + (PORT d[1] (2077:2077:2077) (2294:2294:2294)) + (PORT d[2] (2223:2223:2223) (2370:2370:2370)) + (PORT d[3] (2274:2274:2274) (2375:2375:2375)) + (PORT d[4] (2928:2928:2928) (3204:3204:3204)) + (PORT d[5] (2379:2379:2379) (2550:2550:2550)) + (PORT d[6] (1572:1572:1572) (1678:1678:1678)) + (PORT d[7] (1564:1564:1564) (1666:1666:1666)) + (PORT d[8] (2761:2761:2761) (2991:2991:2991)) + (PORT d[9] (2092:2092:2092) (2225:2225:2225)) + (PORT d[10] (1872:1872:1872) (1997:1997:1997)) + (PORT d[11] (2890:2890:2890) (3011:3011:3011)) + (PORT d[12] (1605:1605:1605) (1686:1686:1686)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2511:2511:2511) (2509:2509:2509)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (PORT d[0] (2908:2908:2908) (2850:2850:2850)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1880:1880:1880)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1820:1820:1820)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -47537,48 +34054,5896 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) + (PORT d[0] (2487:2487:2487) (2567:2567:2567)) + (PORT clk (1834:1834:1834) (1826:1826:1826)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4515:4515:4515) (4502:4502:4502)) + (PORT d[1] (4098:4098:4098) (4096:4096:4096)) + (PORT d[2] (4387:4387:4387) (4416:4416:4416)) + (PORT d[3] (4466:4466:4466) (4494:4494:4494)) + (PORT d[4] (4550:4550:4550) (4547:4547:4547)) + (PORT d[5] (4395:4395:4395) (4433:4433:4433)) + (PORT d[6] (4601:4601:4601) (4650:4650:4650)) + (PORT d[7] (4160:4160:4160) (4143:4143:4143)) + (PORT d[8] (4661:4661:4661) (4689:4689:4689)) + (PORT d[9] (4502:4502:4502) (4695:4695:4695)) + (PORT d[10] (4622:4622:4622) (4632:4632:4632)) + (PORT d[11] (4398:4398:4398) (4428:4428:4428)) + (PORT d[12] (4464:4464:4464) (4487:4487:4487)) + (PORT clk (1830:1830:1830) (1822:1822:1822)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1834:1834:1834) (1826:1826:1826)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1835:1835:1835) (1827:1827:1827)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1350:1350:1350) (1443:1443:1443)) + (PORT clk (1826:1826:1826) (1822:1822:1822)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1428:1428:1428) (1500:1500:1500)) + (PORT datab (969:969:969) (1047:1047:1047)) + (PORT datac (1170:1170:1170) (1197:1197:1197)) + (PORT datad (1685:1685:1685) (1714:1714:1714)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1516:1516:1516) (1602:1602:1602)) + (PORT datab (970:970:970) (1048:1048:1048)) + (PORT datac (1706:1706:1706) (1767:1767:1767)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (1206:1206:1206) (1299:1299:1299)) + (PORT datac (1658:1658:1658) (1693:1693:1693)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (1382:1382:1382) (1395:1395:1395)) + (PORT datab (1382:1382:1382) (1409:1409:1409)) + (PORT datac (842:842:842) (919:919:919)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~99) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (832:832:832)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1043:1043:1043)) + (PORT datab (1039:1039:1039) (1071:1071:1071)) + (PORT datac (240:240:240) (293:293:293)) + (PORT datad (948:948:948) (984:984:984)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (707:707:707) (729:729:729)) + (PORT datac (235:235:235) (309:309:309)) + (PORT datad (359:359:359) (384:384:384)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1004:1004:1004)) + (PORT datab (917:917:917) (967:967:967)) + (PORT datac (825:825:825) (825:825:825)) + (PORT datad (891:891:891) (919:919:919)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT asdata (598:598:598) (653:653:653)) + (PORT clrn (1571:1571:1571) (1550:1550:1550)) + (PORT ena (1479:1479:1479) (1488:1488:1488)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1333:1333:1333)) + (PORT datab (857:857:857) (877:877:877)) + (PORT datac (862:862:862) (884:884:884)) + (PORT datad (1897:1897:1897) (1952:1952:1952)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1586:1586:1586) (1563:1563:1563)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|use_ixiy) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1072:1072:1072)) + (PORT datac (930:930:930) (1012:1012:1012)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1192:1192:1192) (1230:1230:1230)) + (PORT datab (998:998:998) (1107:1107:1107)) + (PORT datac (657:657:657) (721:721:721)) + (PORT datad (1243:1243:1243) (1329:1329:1329)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (915:915:915)) + (PORT datab (667:667:667) (679:679:679)) + (PORT datac (904:904:904) (934:934:934)) + (PORT datad (360:360:360) (382:382:382)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1168:1168:1168) (1211:1211:1211)) + (PORT datab (1607:1607:1607) (1625:1625:1625)) + (PORT datac (614:614:614) (646:646:646)) + (PORT datad (1081:1081:1081) (1126:1126:1126)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1363:1363:1363)) + (PORT datab (469:469:469) (523:523:523)) + (PORT datac (1707:1707:1707) (1763:1763:1763)) + (PORT datad (264:264:264) (317:317:317)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (441:441:441)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1072:1072:1072) (1108:1108:1108)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1212:1212:1212)) + (PORT datab (568:568:568) (599:599:599)) + (PORT datac (1103:1103:1103) (1115:1115:1115)) + (PORT datad (317:317:317) (336:336:336)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (898:898:898)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (590:590:590) (597:597:597)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (275:275:275)) + (PORT datab (645:645:645) (670:670:670)) + (PORT datac (194:194:194) (238:238:238)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (914:914:914)) + (PORT datab (1115:1115:1115) (1147:1147:1147)) + (PORT datac (1402:1402:1402) (1464:1464:1464)) + (PORT datad (899:899:899) (942:942:942)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (895:895:895)) + (PORT datab (939:939:939) (994:994:994)) + (PORT datac (959:959:959) (1031:1031:1031)) + (PORT datad (1113:1113:1113) (1143:1143:1143)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (916:916:916)) + (PORT datab (876:876:876) (896:896:896)) + (PORT datac (1106:1106:1106) (1134:1134:1134)) + (PORT datad (326:326:326) (350:350:350)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1572:1572:1572) (1664:1664:1664)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (1885:1885:1885) (1936:1936:1936)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1249:1249:1249)) + (PORT datab (997:997:997) (1061:1061:1061)) + (PORT datac (1628:1628:1628) (1678:1678:1678)) + (PORT datad (1161:1161:1161) (1198:1198:1198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1424:1424:1424) (1425:1425:1425)) + (PORT datab (1116:1116:1116) (1146:1146:1146)) + (PORT datac (1040:1040:1040) (1082:1082:1082)) + (PORT datad (337:337:337) (357:357:357)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (594:594:594) (614:614:614)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (644:644:644)) + (PORT datab (1041:1041:1041) (1082:1082:1082)) + (PORT datac (571:571:571) (588:588:588)) + (PORT datad (598:598:598) (647:647:647)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~48) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (933:933:933)) + (PORT datab (1205:1205:1205) (1227:1227:1227)) + (PORT datac (1512:1512:1512) (1585:1585:1585)) + (PORT datad (674:674:674) (712:712:712)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1353:1353:1353) (1383:1383:1383)) + (PORT datab (852:852:852) (880:880:880)) + (PORT datac (1075:1075:1075) (1109:1109:1109)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (942:942:942)) + (PORT datab (941:941:941) (1018:1018:1018)) + (PORT datac (1551:1551:1551) (1591:1591:1591)) + (PORT datad (1215:1215:1215) (1217:1217:1217)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (909:909:909)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (806:806:806) (819:819:819)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (2068:2068:2068) (2159:2159:2159)) + (PORT datab (1202:1202:1202) (1215:1215:1215)) + (PORT datac (1137:1137:1137) (1179:1179:1179)) + (PORT datad (1150:1150:1150) (1187:1187:1187)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (2504:2504:2504) (2616:2616:2616)) + (PORT datab (576:576:576) (586:586:586)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (981:981:981) (1012:1012:1012)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1663:1663:1663) (1697:1697:1697)) + (PORT datab (833:833:833) (893:893:893)) + (PORT datac (1036:1036:1036) (1091:1091:1091)) + (PORT datad (770:770:770) (816:816:816)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1031:1031:1031) (1043:1043:1043)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (819:819:819) (869:869:869)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (888:888:888)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (821:821:821) (872:872:872)) + (PORT datad (195:195:195) (219:219:219)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT datab (974:974:974) (1035:1035:1035)) + (PORT datac (964:964:964) (1026:1026:1026)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1008:1008:1008) (1080:1080:1080)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1191:1191:1191) (1224:1224:1224)) + (PORT d[1] (2415:2415:2415) (2649:2649:2649)) + (PORT d[2] (1758:1758:1758) (1803:1803:1803)) + (PORT d[3] (1013:1013:1013) (1063:1063:1063)) + (PORT d[4] (2608:2608:2608) (2826:2826:2826)) + (PORT d[5] (3496:3496:3496) (3699:3699:3699)) + (PORT d[6] (1026:1026:1026) (1099:1099:1099)) + (PORT d[7] (3197:3197:3197) (3375:3375:3375)) + (PORT d[8] (1246:1246:1246) (1270:1270:1270)) + (PORT d[9] (1026:1026:1026) (1088:1088:1088)) + (PORT d[10] (1315:1315:1315) (1388:1388:1388)) + (PORT d[11] (2503:2503:2503) (2659:2659:2659)) + (PORT d[12] (1307:1307:1307) (1387:1387:1387)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (944:944:944) (900:900:900)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1721:1721:1721) (1677:1677:1677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (708:708:708) (754:754:754)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (966:966:966) (1010:1010:1010)) + (PORT d[1] (2966:2966:2966) (3237:3237:3237)) + (PORT d[2] (1238:1238:1238) (1256:1256:1256)) + (PORT d[3] (1302:1302:1302) (1383:1383:1383)) + (PORT d[4] (2581:2581:2581) (2796:2796:2796)) + (PORT d[5] (2980:2980:2980) (3208:3208:3208)) + (PORT d[6] (692:692:692) (727:727:727)) + (PORT d[7] (705:705:705) (744:744:744)) + (PORT d[8] (1011:1011:1011) (1032:1032:1032)) + (PORT d[9] (717:717:717) (757:757:757)) + (PORT d[10] (1036:1036:1036) (1102:1102:1102)) + (PORT d[11] (2544:2544:2544) (2757:2757:2757)) + (PORT d[12] (1267:1267:1267) (1319:1319:1319)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (967:967:967) (945:945:945)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (2089:2089:2089) (2073:2073:2073)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (752:752:752)) + (PORT datab (688:688:688) (754:754:754)) + (PORT datac (786:786:786) (795:795:795)) + (PORT datad (864:864:864) (896:896:896)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (700:700:700) (744:744:744)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3167:3167:3167) (3303:3303:3303)) + (PORT d[1] (2937:2937:2937) (3208:3208:3208)) + (PORT d[2] (967:967:967) (987:987:987)) + (PORT d[3] (1341:1341:1341) (1401:1401:1401)) + (PORT d[4] (2612:2612:2612) (2843:2843:2843)) + (PORT d[5] (2651:2651:2651) (2894:2894:2894)) + (PORT d[6] (960:960:960) (1001:1001:1001)) + (PORT d[7] (1270:1270:1270) (1343:1343:1343)) + (PORT d[8] (1442:1442:1442) (1513:1513:1513)) + (PORT d[9] (971:971:971) (1019:1019:1019)) + (PORT d[10] (1031:1031:1031) (1057:1057:1057)) + (PORT d[11] (2872:2872:2872) (3095:3095:3095)) + (PORT d[12] (969:969:969) (1020:1020:1020)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1245:1245:1245) (1221:1221:1221)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2049:2049:2049) (2003:2003:2003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (743:743:743) (772:772:772)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3188:3188:3188) (3327:3327:3327)) + (PORT d[1] (2678:2678:2678) (2951:2951:2951)) + (PORT d[2] (1298:1298:1298) (1309:1309:1309)) + (PORT d[3] (1348:1348:1348) (1402:1402:1402)) + (PORT d[4] (2616:2616:2616) (2850:2850:2850)) + (PORT d[5] (2675:2675:2675) (2903:2903:2903)) + (PORT d[6] (1230:1230:1230) (1289:1289:1289)) + (PORT d[7] (1132:1132:1132) (1148:1148:1148)) + (PORT d[8] (1470:1470:1470) (1552:1552:1552)) + (PORT d[9] (1550:1550:1550) (1617:1617:1617)) + (PORT d[10] (724:724:724) (767:767:767)) + (PORT d[11] (2854:2854:2854) (3086:3086:3086)) + (PORT d[12] (971:971:971) (1034:1034:1034)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1229:1229:1229) (1208:1208:1208)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (1822:1822:1822) (1811:1811:1811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1242:1242:1242) (1299:1299:1299)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (968:968:968) (1003:1003:1003)) + (PORT datad (1089:1089:1089) (1119:1119:1119)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (746:746:746) (776:776:776)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2906:2906:2906) (3003:3003:3003)) + (PORT d[1] (2374:2374:2374) (2624:2624:2624)) + (PORT d[2] (1590:1590:1590) (1604:1604:1604)) + (PORT d[3] (1983:1983:1983) (2059:2059:2059)) + (PORT d[4] (2920:2920:2920) (3176:3176:3176)) + (PORT d[5] (2692:2692:2692) (2903:2903:2903)) + (PORT d[6] (1267:1267:1267) (1350:1350:1350)) + (PORT d[7] (1307:1307:1307) (1395:1395:1395)) + (PORT d[8] (1742:1742:1742) (1842:1842:1842)) + (PORT d[9] (1557:1557:1557) (1621:1621:1621)) + (PORT d[10] (2161:2161:2161) (2306:2306:2306)) + (PORT d[11] (3233:3233:3233) (3375:3375:3375)) + (PORT d[12] (1281:1281:1281) (1357:1357:1357)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2941:2941:2941) (2895:2895:2895)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (3092:3092:3092) (3136:3136:3136)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1808:1808:1808) (1806:1806:1806)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2118:2118:2118) (2165:2165:2165)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4374:4374:4374) (4418:4418:4418)) + (PORT d[1] (4140:4140:4140) (4128:4128:4128)) + (PORT d[2] (4277:4277:4277) (4327:4327:4327)) + (PORT d[3] (4389:4389:4389) (4374:4374:4374)) + (PORT d[4] (4369:4369:4369) (4385:4385:4385)) + (PORT d[5] (4402:4402:4402) (4357:4357:4357)) + (PORT d[6] (4635:4635:4635) (4717:4717:4717)) + (PORT d[7] (4444:4444:4444) (4393:4393:4393)) + (PORT d[8] (4445:4445:4445) (4433:4433:4433)) + (PORT d[9] (4508:4508:4508) (4699:4699:4699)) + (PORT d[10] (4409:4409:4409) (4440:4440:4440)) + (PORT d[11] (4509:4509:4509) (4563:4563:4563)) + (PORT d[12] (4429:4429:4429) (4547:4547:4547)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2570:2570:2570) (2648:2648:2648)) + (PORT d[1] (2033:2033:2033) (2232:2232:2232)) + (PORT d[2] (2324:2324:2324) (2498:2498:2498)) + (PORT d[3] (2521:2521:2521) (2687:2687:2687)) + (PORT d[4] (2940:2940:2940) (3191:3191:3191)) + (PORT d[5] (2266:2266:2266) (2447:2447:2447)) + (PORT d[6] (1866:1866:1866) (1990:1990:1990)) + (PORT d[7] (2543:2543:2543) (2628:2628:2628)) + (PORT d[8] (2767:2767:2767) (2988:2988:2988)) + (PORT d[9] (1759:1759:1759) (1863:1863:1863)) + (PORT d[10] (1515:1515:1515) (1609:1609:1609)) + (PORT d[11] (3453:3453:3453) (3586:3586:3586)) + (PORT d[12] (1542:1542:1542) (1649:1649:1649)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (PORT d[0] (2191:2191:2191) (2247:2247:2247)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1511:1511:1511) (1554:1554:1554)) + (PORT d[1] (2684:2684:2684) (2948:2948:2948)) + (PORT d[2] (989:989:989) (1036:1036:1036)) + (PORT d[3] (1684:1684:1684) (1752:1752:1752)) + (PORT d[4] (2594:2594:2594) (2826:2826:2826)) + (PORT d[5] (2711:2711:2711) (2920:2920:2920)) + (PORT d[6] (973:973:973) (1031:1031:1031)) + (PORT d[7] (964:964:964) (1018:1018:1018)) + (PORT d[8] (1426:1426:1426) (1505:1505:1505)) + (PORT d[9] (1567:1567:1567) (1660:1660:1660)) + (PORT d[10] (2478:2478:2478) (2623:2623:2623)) + (PORT d[11] (2885:2885:2885) (3126:3126:3126)) + (PORT d[12] (1271:1271:1271) (1324:1324:1324)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT d[0] (872:872:872) (859:859:859)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (926:926:926) (931:931:931)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3174:3174:3174) (3295:3295:3295)) + (PORT d[1] (2670:2670:2670) (2938:2938:2938)) + (PORT d[2] (1591:1591:1591) (1604:1604:1604)) + (PORT d[3] (1700:1700:1700) (1749:1749:1749)) + (PORT d[4] (2908:2908:2908) (3176:3176:3176)) + (PORT d[5] (2711:2711:2711) (2920:2920:2920)) + (PORT d[6] (974:974:974) (1032:1032:1032)) + (PORT d[7] (1544:1544:1544) (1607:1607:1607)) + (PORT d[8] (3051:3051:3051) (3314:3314:3314)) + (PORT d[9] (996:996:996) (1062:1062:1062)) + (PORT d[10] (2482:2482:2482) (2620:2620:2620)) + (PORT d[11] (2859:2859:2859) (3096:3096:3096)) + (PORT d[12] (2233:2233:2233) (2338:2338:2338)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3083:3083:3083) (3081:3081:3081)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1803:1803:1803) (1787:1787:1787)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1809:1809:1809)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2405:2405:2405) (2433:2433:2433)) + (PORT clk (1822:1822:1822) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4622:4622:4622) (4649:4649:4649)) + (PORT d[1] (4242:4242:4242) (4320:4320:4320)) + (PORT d[2] (4251:4251:4251) (4295:4295:4295)) + (PORT d[3] (4399:4399:4399) (4422:4422:4422)) + (PORT d[4] (4340:4340:4340) (4354:4354:4354)) + (PORT d[5] (4534:4534:4534) (4546:4546:4546)) + (PORT d[6] (4731:4731:4731) (4801:4801:4801)) + (PORT d[7] (4488:4488:4488) (4531:4531:4531)) + (PORT d[8] (4436:4436:4436) (4436:4436:4436)) + (PORT d[9] (4525:4525:4525) (4711:4711:4711)) + (PORT d[10] (4473:4473:4473) (4495:4495:4495)) + (PORT d[11] (4414:4414:4414) (4386:4386:4386)) + (PORT d[12] (4391:4391:4391) (4381:4381:4381)) + (PORT clk (1818:1818:1818) (1811:1811:1811)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1815:1815:1815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1811:1811:1811)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (731:731:731)) + (PORT datab (1192:1192:1192) (1240:1240:1240)) + (PORT datac (825:825:825) (833:833:833)) + (PORT datad (890:890:890) (911:911:911)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1198:1198:1198)) + (PORT datab (1192:1192:1192) (1240:1240:1240)) + (PORT datac (1509:1509:1509) (1586:1586:1586)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~103) + (DELAY + (ABSOLUTE + (PORT dataa (1738:1738:1738) (1846:1846:1846)) + (PORT datab (1412:1412:1412) (1506:1506:1506)) + (PORT datac (648:648:648) (701:701:701)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_DAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (842:842:842) (859:859:859)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (386:386:386)) + (PORT datab (291:291:291) (382:382:382)) + (PORT datad (245:245:245) (325:325:325)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_CLK\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3358:3358:3358) (3700:3700:3700)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (297:297:297)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (302:302:302)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (309:309:309)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (342:342:342)) + (PORT datab (250:250:250) (335:335:335)) + (PORT datac (380:380:380) (441:441:441)) + (PORT datad (225:225:225) (298:298:298)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (299:299:299)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (228:228:228) (301:301:301)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (227:227:227) (299:299:299)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (226:226:226) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) + (DELAY + (ABSOLUTE + (PORT datab (208:208:208) (249:249:249)) + (PORT datad (227:227:227) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) + (DELAY + (ABSOLUTE + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (218:218:218) (295:295:295)) + (PORT datad (224:224:224) (296:296:296)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1562:1562:1562)) + (PORT ena (2016:2016:2016) (2055:2055:2055)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (387:387:387)) + (PORT datab (292:292:292) (383:383:383)) + (PORT datad (240:240:240) (317:317:317)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1562:1562:1562)) + (PORT ena (2016:2016:2016) (2055:2055:2055)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (382:382:382)) + (PORT datab (278:278:278) (373:373:373)) + (PORT datad (242:242:242) (321:321:321)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1562:1562:1562)) + (PORT ena (2016:2016:2016) (2055:2055:2055)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (480:480:480)) + (PORT datab (279:279:279) (374:374:374)) + (PORT datad (243:243:243) (322:322:322)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1562:1562:1562)) + (PORT ena (2016:2016:2016) (2055:2055:2055)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (275:275:275) (377:377:377)) + (PORT datab (288:288:288) (377:377:377)) + (PORT datac (3414:3414:3414) (3775:3775:3775)) + (PORT datad (251:251:251) (331:331:331)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT datab (289:289:289) (380:380:380)) + (PORT datac (247:247:247) (341:341:341)) + (PORT datad (248:248:248) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (264:264:264) (354:354:354)) + (PORT datac (1368:1368:1368) (1427:1427:1427)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT asdata (3957:3957:3957) (4311:4311:4311)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT ena (1226:1226:1226) (1215:1215:1215)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT asdata (560:560:560) (634:634:634)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT ena (1226:1226:1226) (1215:1215:1215)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT asdata (602:602:602) (685:685:685)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT ena (1226:1226:1226) (1215:1215:1215)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT asdata (588:588:588) (665:665:665)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT ena (1226:1226:1226) (1215:1215:1215)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT asdata (958:958:958) (1010:1010:1010)) + (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (PORT ena (1200:1200:1200) (1196:1196:1196)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT asdata (960:960:960) (1018:1018:1018)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT ena (1226:1226:1226) (1215:1215:1215)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT asdata (951:951:951) (1014:1014:1014)) + (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (PORT ena (1200:1200:1200) (1196:1196:1196)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT asdata (761:761:761) (840:840:840)) + (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (PORT ena (1200:1200:1200) (1196:1196:1196)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT asdata (791:791:791) (867:867:867)) + (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (PORT ena (1200:1200:1200) (1196:1196:1196)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1075:1075:1075)) + (PORT datab (675:675:675) (742:742:742)) + (PORT datac (757:757:757) (876:876:876)) + (PORT datad (781:781:781) (888:888:888)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1549:1549:1549)) + (PORT datab (937:937:937) (1037:1037:1037)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (763:763:763) (875:875:875)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT datab (1062:1062:1062) (1155:1155:1155)) + (PORT datad (785:785:785) (795:795:795)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (722:722:722)) + (PORT datab (288:288:288) (378:378:378)) + (PORT datad (833:833:833) (880:880:880)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (827:827:827)) + (PORT datab (669:669:669) (749:749:749)) + (PORT datac (655:655:655) (721:721:721)) + (PORT datad (438:438:438) (511:511:511)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) + (DELAY + (ABSOLUTE + (PORT datab (668:668:668) (736:736:736)) + (PORT datac (345:345:345) (369:369:369)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (255:255:255)) + (PORT datab (3434:3434:3434) (3812:3812:3812)) + (PORT datac (1368:1368:1368) (1428:1428:1428)) + (PORT datad (358:358:358) (390:390:390)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1562:1562:1562)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|extended) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1764:1764:1764) (1796:1796:1796)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (758:758:758)) + (PORT datab (664:664:664) (692:692:692)) + (PORT datac (260:260:260) (346:346:346)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (553:553:553)) + (PORT datac (1367:1367:1367) (1453:1453:1453)) + (PORT datad (841:841:841) (864:864:864)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1265:1265:1265)) + (PORT datac (641:641:641) (670:670:670)) + (PORT datad (910:910:910) (977:977:977)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (426:426:426)) + (PORT datac (615:615:615) (667:667:667)) + (PORT datad (726:726:726) (803:803:803)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (736:736:736)) + (PORT datab (663:663:663) (694:694:694)) + (PORT datad (1337:1337:1337) (1379:1379:1379)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (568:568:568)) + (PORT datab (663:663:663) (740:740:740)) + (PORT datac (606:606:606) (673:673:673)) + (PORT datad (259:259:259) (336:336:336)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datac (416:416:416) (498:498:498)) + (PORT datad (651:651:651) (725:725:725)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (616:616:616)) + (PORT datab (428:428:428) (507:507:507)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (848:848:848)) + (PORT datab (984:984:984) (1072:1072:1072)) + (PORT datad (962:962:962) (1042:1042:1042)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT datab (751:751:751) (858:858:858)) + (PORT datac (739:739:739) (840:840:840)) + (PORT datad (729:729:729) (835:835:835)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (394:394:394)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (963:963:963) (1041:1041:1041)) + (PORT datad (729:729:729) (834:834:834)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (827:827:827)) + (PORT datab (290:290:290) (378:378:378)) + (PORT datac (649:649:649) (725:725:725)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (655:655:655) (729:729:729)) + (PORT datac (395:395:395) (471:471:471)) + (PORT datad (657:657:657) (716:716:716)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (418:418:418)) + (PORT datab (223:223:223) (270:270:270)) + (PORT datac (658:658:658) (723:723:723)) + (PORT datad (433:433:433) (507:507:507)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (269:269:269)) + (PORT datab (622:622:622) (671:671:671)) + (PORT datad (962:962:962) (1038:1038:1038)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1230:1230:1230)) + (PORT datab (241:241:241) (321:321:321)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (548:548:548) (570:570:570)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1044:1044:1044)) + (PORT datac (902:902:902) (995:995:995)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1413:1413:1413) (1549:1549:1549)) + (PORT datab (696:696:696) (729:729:729)) + (PORT datac (959:959:959) (1041:1041:1041)) + (PORT datad (190:190:190) (224:224:224)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (981:981:981) (1070:1070:1070)) + (PORT datac (721:721:721) (830:830:830)) + (PORT datad (729:729:729) (838:838:838)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (908:908:908)) + (PORT datab (667:667:667) (685:685:685)) + (PORT datad (496:496:496) (512:512:512)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1414:1414:1414) (1542:1542:1542)) + (PORT datab (213:213:213) (258:258:258)) + (PORT datac (667:667:667) (692:692:692)) + (PORT datad (766:766:766) (872:872:872)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (818:818:818)) + (PORT datab (363:363:363) (394:394:394)) + (PORT datac (717:717:717) (819:819:819)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1555:1555:1555) (1666:1666:1666)) + (PORT datab (982:982:982) (1037:1037:1037)) + (PORT datad (518:518:518) (530:530:530)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~0) + (DELAY + (ABSOLUTE + (PORT datab (1469:1469:1469) (1606:1606:1606)) + (PORT datac (912:912:912) (975:975:975)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (425:425:425) (503:503:503)) + (PORT datac (1117:1117:1117) (1170:1170:1170)) + (PORT datad (651:651:651) (723:723:723)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (776:776:776)) + (PORT datab (412:412:412) (493:493:493)) + (PORT datac (606:606:606) (674:674:674)) + (PORT datad (261:261:261) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (569:569:569)) + (PORT datab (664:664:664) (741:741:741)) + (PORT datac (497:497:497) (515:515:515)) + (PORT datad (655:655:655) (724:724:724)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (615:615:615)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (768:768:768)) + (PORT datab (1230:1230:1230) (1291:1291:1291)) + (PORT datac (443:443:443) (506:506:506)) + (PORT datad (1066:1066:1066) (1109:1109:1109)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (844:844:844)) + (PORT datab (1400:1400:1400) (1489:1489:1489)) + (PORT datac (917:917:917) (988:988:988)) + (PORT datad (854:854:854) (921:921:921)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (279:279:279)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (739:739:739) (839:839:839)) + (PORT datad (1547:1547:1547) (1637:1637:1637)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (523:523:523) (533:533:533)) + (PORT datad (944:944:944) (998:998:998)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (729:729:729)) + (PORT datab (1120:1120:1120) (1195:1195:1195)) + (PORT datac (633:633:633) (694:694:694)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (745:745:745)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (484:484:484) (550:550:550)) + (PORT datab (1228:1228:1228) (1291:1291:1291)) + (PORT datac (741:741:741) (842:842:842)) + (PORT datad (842:842:842) (867:867:867)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (875:875:875)) + (PORT datab (913:913:913) (986:986:986)) + (PORT datac (1115:1115:1115) (1162:1162:1162)) + (PORT datad (710:710:710) (791:791:791)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (395:395:395)) + (PORT datac (700:700:700) (784:784:784)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (868:868:868)) + (PORT datab (912:912:912) (984:984:984)) + (PORT datac (659:659:659) (735:735:735)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (710:710:710)) + (PORT datab (496:496:496) (580:580:580)) + (PORT datac (396:396:396) (470:470:470)) + (PORT datad (601:601:601) (643:643:643)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (937:937:937)) + (PORT datab (941:941:941) (1038:1038:1038)) + (PORT datac (758:758:758) (878:878:878)) + (PORT datad (764:764:764) (871:871:871)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (932:932:932)) + (PORT datab (788:788:788) (904:904:904)) + (PORT datad (763:763:763) (876:876:876)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (935:935:935)) + (PORT datab (938:938:938) (1037:1037:1037)) + (PORT datac (757:757:757) (875:875:875)) + (PORT datad (764:764:764) (875:875:875)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (279:279:279)) + (PORT datab (941:941:941) (1039:1039:1039)) + (PORT datac (311:311:311) (337:337:337)) + (PORT datad (1387:1387:1387) (1504:1504:1504)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1544:1544:1544)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (932:932:932) (1003:1003:1003)) + (PORT datad (517:517:517) (528:528:528)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (398:398:398)) + (PORT datab (274:274:274) (359:359:359)) + (PORT datad (604:604:604) (617:617:617)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1387:1387:1387) (1447:1447:1447)) + (PORT datab (411:411:411) (471:471:471)) + (PORT datac (1375:1375:1375) (1408:1408:1408)) + (PORT datad (583:583:583) (631:631:631)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (804:804:804)) + (PORT datab (3348:3348:3348) (3488:3488:3488)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1705:1705:1705) (1713:1713:1713)) + (PORT datab (1225:1225:1225) (1301:1301:1301)) + (PORT datac (636:636:636) (675:675:675)) + (PORT datad (1144:1144:1144) (1160:1160:1160)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1628:1628:1628)) + (PORT datab (1226:1226:1226) (1302:1302:1302)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1240:1240:1240) (1368:1368:1368)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1042:1042:1042)) + (PORT datab (636:636:636) (676:676:676)) + (PORT datac (240:240:240) (293:293:293)) + (PORT datad (1667:1667:1667) (1728:1728:1728)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (912:912:912) (931:931:931)) + (PORT datac (945:945:945) (986:986:986)) + (PORT datad (219:219:219) (254:254:254)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (310:310:310)) + (PORT datab (705:705:705) (769:769:769)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (208:208:208) (240:240:240)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (220:220:220)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1557:1557:1557)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (284:284:284) (380:380:380)) + (PORT datac (903:903:903) (966:966:966)) + (PORT datad (928:928:928) (982:982:982)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1410:1410:1410) (1521:1521:1521)) + (PORT datab (897:897:897) (911:911:911)) + (PORT datac (924:924:924) (1011:1011:1011)) + (PORT datad (876:876:876) (894:894:894)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1572:1572:1572) (1710:1710:1710)) + (PORT datab (2337:2337:2337) (2410:2410:2410)) + (PORT datac (671:671:671) (718:718:718)) + (PORT datad (2748:2748:2748) (2873:2873:2873)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (232:232:232) (283:283:283)) + (PORT datac (195:195:195) (238:238:238)) + (PORT datad (371:371:371) (399:399:399)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (658:658:658)) + (PORT datab (427:427:427) (471:471:471)) + (PORT datac (543:543:543) (559:559:559)) + (PORT datad (1164:1164:1164) (1218:1218:1218)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1490:1490:1490) (1592:1592:1592)) + (PORT datab (438:438:438) (474:474:474)) + (PORT datac (943:943:943) (994:994:994)) + (PORT datad (211:211:211) (243:243:243)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1047:1047:1047)) + (PORT datab (1110:1110:1110) (1179:1179:1179)) + (PORT datac (1261:1261:1261) (1313:1313:1313)) + (PORT datad (1359:1359:1359) (1384:1384:1384)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1122:1122:1122)) + (PORT datab (961:961:961) (1050:1050:1050)) + (PORT datac (1264:1264:1264) (1310:1310:1310)) + (PORT datad (1206:1206:1206) (1270:1270:1270)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1505:1505:1505) (1526:1526:1526)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (868:868:868) (865:865:865)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1606:1606:1606) (1627:1627:1627)) + (PORT datab (831:831:831) (859:859:859)) + (PORT datad (1029:1029:1029) (1028:1028:1028)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1568:1568:1568) (1597:1597:1597)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (643:643:643) (684:684:684)) + (PORT datad (555:555:555) (558:558:558)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (650:650:650)) + (PORT datab (552:552:552) (565:565:565)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (372:372:372) (397:397:397)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~21) + (DELAY + (ABSOLUTE + (PORT dataa (2257:2257:2257) (2337:2337:2337)) + (PORT datab (1549:1549:1549) (1673:1673:1673)) + (PORT datac (902:902:902) (922:922:922)) + (PORT datad (1165:1165:1165) (1178:1178:1178)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT datab (230:230:230) (277:277:277)) + (PORT datac (343:343:343) (365:365:365)) + (PORT datad (369:369:369) (394:394:394)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1298:1298:1298) (1395:1395:1395)) + (PORT datab (927:927:927) (974:974:974)) + (PORT datac (1940:1940:1940) (2070:2070:2070)) + (PORT datad (2052:2052:2052) (2214:2214:2214)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (906:906:906)) + (PORT datab (230:230:230) (277:277:277)) + (PORT datac (196:196:196) (240:240:240)) + (PORT datad (370:370:370) (394:394:394)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1167:1167:1167)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (222:222:222) (268:268:268)) + (PORT datac (200:200:200) (236:236:236)) + (PORT datad (223:223:223) (250:250:250)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1938:1938:1938) (2062:2062:2062)) + (PORT datab (2594:2594:2594) (2695:2695:2695)) + (PORT datad (1436:1436:1436) (1528:1528:1528)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (720:720:720)) + (PORT datab (699:699:699) (758:758:758)) + (PORT datac (1095:1095:1095) (1090:1090:1090)) + (PORT datad (644:644:644) (692:692:692)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (611:611:611) (632:632:632)) + (PORT datad (777:777:777) (789:789:789)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (890:890:890)) + (PORT datab (332:332:332) (362:362:362)) + (PORT datac (372:372:372) (397:397:397)) + (PORT datad (604:604:604) (626:626:626)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1811:1811:1811) (1903:1903:1903)) + (PORT datab (921:921:921) (989:989:989)) + (PORT datac (923:923:923) (1008:1008:1008)) + (PORT datad (436:436:436) (468:468:468)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (966:966:966)) + (PORT datac (902:902:902) (921:921:921)) + (PORT datad (1383:1383:1383) (1455:1455:1455)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (444:444:444)) + (PORT datac (192:192:192) (225:225:225)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1242:1242:1242)) + (PORT datab (196:196:196) (236:236:236)) + (PORT datac (593:593:593) (604:604:604)) + (PORT datad (376:376:376) (396:396:396)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1240:1240:1240)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datad (877:877:877) (932:932:932)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2446:2446:2446) (2535:2535:2535)) + (PORT datab (1615:1615:1615) (1728:1728:1728)) + (PORT datac (1769:1769:1769) (1897:1897:1897)) + (PORT datad (1666:1666:1666) (1684:1684:1684)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1432:1432:1432) (1515:1515:1515)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1052:1052:1052) (1100:1100:1100)) + (PORT datad (1335:1335:1335) (1356:1356:1356)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1121:1121:1121) (1241:1241:1241)) + (PORT datac (884:884:884) (939:939:939)) + (PORT datad (957:957:957) (1022:1022:1022)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (935:935:935)) + (PORT datab (944:944:944) (1021:1021:1021)) + (PORT datac (588:588:588) (603:603:603)) + (PORT datad (537:537:537) (536:536:536)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (838:838:838) (860:860:860)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (195:195:195) (228:228:228)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1255:1255:1255)) + (PORT datab (257:257:257) (345:345:345)) + (PORT datac (214:214:214) (290:290:290)) + (PORT datad (580:580:580) (615:615:615)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (607:607:607)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (590:590:590) (613:613:613)) + (PORT datad (600:600:600) (615:615:615)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1706:1706:1706)) + (PORT datab (2568:2568:2568) (2670:2670:2670)) + (PORT datac (1057:1057:1057) (1083:1083:1083)) + (PORT datad (862:862:862) (898:898:898)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1089:1089:1089) (1120:1120:1120)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1186:1186:1186) (1228:1228:1228)) + (PORT datad (564:564:564) (579:579:579)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (920:920:920)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (237:237:237) (278:278:278)) + (PORT datad (594:594:594) (611:611:611)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1036:1036:1036)) + (PORT datab (263:263:263) (310:310:310)) + (PORT datac (1393:1393:1393) (1475:1475:1475)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (950:950:950)) + (PORT datab (1129:1129:1129) (1199:1199:1199)) + (PORT datac (889:889:889) (932:932:932)) + (PORT datad (1015:1015:1015) (1011:1011:1011)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (514:514:514)) + (PORT datab (896:896:896) (914:914:914)) + (PORT datac (922:922:922) (1007:1007:1007)) + (PORT datad (405:405:405) (434:434:434)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT datab (1062:1062:1062) (1088:1088:1088)) + (PORT datac (208:208:208) (250:250:250)) + (PORT datad (209:209:209) (241:241:241)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (524:524:524) (539:539:539)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (594:594:594) (613:613:613)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (567:567:567) (592:592:592)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (746:746:746)) + (PORT datab (661:661:661) (721:721:721)) + (PORT datac (883:883:883) (903:903:903)) + (PORT datad (893:893:893) (916:916:916)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1154:1154:1154) (1188:1188:1188)) + (PORT datad (629:629:629) (643:643:643)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (408:408:408)) + (PORT datab (644:644:644) (678:678:678)) + (PORT datac (871:871:871) (896:896:896)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (721:721:721)) + (PORT datab (956:956:956) (981:981:981)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (217:217:217) (250:250:250)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (772:772:772)) + (PORT datac (1115:1115:1115) (1160:1160:1160)) + (PORT datad (739:739:739) (827:827:827)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (871:871:871)) + (PORT datab (725:725:725) (810:810:810)) + (PORT datac (1118:1118:1118) (1161:1161:1161)) + (PORT datad (711:711:711) (788:788:788)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (915:915:915) (989:989:989)) + (PORT datac (1116:1116:1116) (1162:1162:1162)) + (PORT datad (329:329:329) (349:349:349)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (261:261:261)) + (PORT datab (199:199:199) (239:239:239)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (727:727:727) (814:814:814)) + (PORT datab (981:981:981) (1068:1068:1068)) + (PORT datac (722:722:722) (831:831:831)) + (PORT datad (729:729:729) (835:835:835)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (903:903:903)) + (PORT datab (736:736:736) (834:834:834)) + (PORT datac (710:710:710) (811:811:811)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (390:390:390)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (338:338:338) (357:357:357)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1230:1230:1230)) + (PORT datab (724:724:724) (793:793:793)) + (PORT datac (214:214:214) (291:291:291)) + (PORT datad (550:550:550) (572:572:572)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (1028:1028:1028)) + (PORT datab (779:779:779) (879:879:879)) + (PORT datac (1365:1365:1365) (1458:1458:1458)) + (PORT datad (1189:1189:1189) (1251:1251:1251)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~76) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (382:382:382)) + (PORT datab (281:281:281) (364:364:364)) + (PORT datac (928:928:928) (975:975:975)) + (PORT datad (1494:1494:1494) (1585:1585:1585)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT datac (740:740:740) (842:842:842)) + (PORT datad (1190:1190:1190) (1255:1255:1255)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (872:872:872)) + (PORT datab (728:728:728) (815:815:815)) + (PORT datac (884:884:884) (953:953:953)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (844:844:844)) + (PORT datab (1502:1502:1502) (1605:1605:1605)) + (PORT datac (916:916:916) (991:991:991)) + (PORT datad (852:852:852) (919:919:919)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~74) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (610:610:610)) + (PORT datab (344:344:344) (369:369:369)) + (PORT datac (1366:1366:1366) (1452:1452:1452)) + (PORT datad (1547:1547:1547) (1637:1637:1637)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (448:448:448) (513:513:513)) + (PORT datad (841:841:841) (864:864:864)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (571:571:571)) + (PORT datab (335:335:335) (364:364:364)) + (PORT datad (736:736:736) (824:824:824)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (758:758:758) (862:862:862)) + (PORT datab (729:729:729) (828:828:828)) + (PORT datac (335:335:335) (363:363:363)) + (PORT datad (1132:1132:1132) (1201:1201:1201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) + (DELAY + (ABSOLUTE + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (718:718:718) (814:814:814)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (455:455:455)) + (PORT datab (1124:1124:1124) (1199:1199:1199)) + (PORT datac (636:636:636) (698:698:698)) + (PORT datad (629:629:629) (680:680:680)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1665:1665:1665)) + (PORT datab (981:981:981) (1035:1035:1035)) + (PORT datad (515:515:515) (529:529:529)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (569:569:569)) + (PORT datac (607:607:607) (672:672:672)) + (PORT datad (260:260:260) (335:335:335)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (428:428:428)) + (PORT datab (848:848:848) (850:850:850)) + (PORT datad (734:734:734) (821:821:821)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~1) + (DELAY + (ABSOLUTE + (PORT datab (1472:1472:1472) (1607:1607:1607)) + (PORT datac (347:347:347) (411:411:411)) + (PORT datad (901:901:901) (962:962:962)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (220:220:220) (260:260:260)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~1) + (DELAY + (ABSOLUTE + (PORT datac (1076:1076:1076) (1171:1171:1171)) + (PORT datad (1031:1031:1031) (1115:1115:1115)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (1413:1413:1413) (1543:1543:1543)) + (PORT datab (788:788:788) (903:903:903)) + (PORT datac (960:960:960) (1037:1037:1037)) + (PORT datad (777:777:777) (882:882:882)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (675:675:675) (704:704:704)) + (PORT datac (604:604:604) (622:622:622)) + (PORT datad (901:901:901) (976:976:976)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) + (DELAY + (ABSOLUTE + (PORT datab (968:968:968) (1057:1057:1057)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT datac (654:654:654) (724:724:724)) + (PORT datad (637:637:637) (707:707:707)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT datab (654:654:654) (726:726:726)) + (PORT datac (693:693:693) (782:782:782)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (258:258:258)) + (PORT datab (473:473:473) (549:549:549)) + (PORT datac (637:637:637) (704:704:704)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (277:277:277)) + (PORT datab (665:665:665) (741:741:741)) + (PORT datad (650:650:650) (727:727:727)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (926:926:926)) + (PORT datab (223:223:223) (262:262:262)) + (PORT datac (337:337:337) (360:360:360)) + (PORT datad (543:543:543) (562:562:562)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (820:820:820)) + (PORT datad (946:946:946) (995:995:995)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1387:1387:1387) (1444:1444:1444)) + (PORT datab (598:598:598) (652:652:652)) + (PORT datac (1375:1375:1375) (1406:1406:1406)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (804:804:804)) + (PORT datab (3349:3349:3349) (3490:3490:3490)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (891:891:891) (902:902:902)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1236:1236:1236) (1280:1280:1280)) + (PORT d[1] (983:983:983) (1045:1045:1045)) + (PORT d[2] (962:962:962) (977:977:977)) + (PORT d[3] (1021:1021:1021) (1074:1074:1074)) + (PORT d[4] (2601:2601:2601) (2818:2818:2818)) + (PORT d[5] (1028:1028:1028) (1063:1063:1063)) + (PORT d[6] (994:994:994) (1056:1056:1056)) + (PORT d[7] (954:954:954) (1016:1016:1016)) + (PORT d[8] (1046:1046:1046) (1093:1093:1093)) + (PORT d[9] (998:998:998) (1055:1055:1055)) + (PORT d[10] (1047:1047:1047) (1121:1121:1121)) + (PORT d[11] (2576:2576:2576) (2762:2762:2762)) + (PORT d[12] (1307:1307:1307) (1386:1386:1386)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (951:951:951) (911:911:911)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1484:1484:1484) (1455:1455:1455)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (980:980:980) (991:991:991)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (706:706:706) (727:727:727)) + (PORT d[1] (2392:2392:2392) (2624:2624:2624)) + (PORT d[2] (1503:1503:1503) (1540:1540:1540)) + (PORT d[3] (981:981:981) (1040:1040:1040)) + (PORT d[4] (2591:2591:2591) (2807:2807:2807)) + (PORT d[5] (3468:3468:3468) (3668:3668:3668)) + (PORT d[6] (1271:1271:1271) (1334:1334:1334)) + (PORT d[7] (3191:3191:3191) (3366:3366:3366)) + (PORT d[8] (691:691:691) (713:713:713)) + (PORT d[9] (1603:1603:1603) (1661:1661:1661)) + (PORT d[10] (1346:1346:1346) (1434:1434:1434)) + (PORT d[11] (2230:2230:2230) (2413:2413:2413)) + (PORT d[12] (1570:1570:1570) (1649:1649:1649)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (671:671:671) (627:627:627)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (1485:1485:1485) (1441:1441:1441)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1101:1101:1101) (1111:1111:1111)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (986:986:986) (1014:1014:1014)) + (PORT d[1] (3450:3450:3450) (3742:3742:3742)) + (PORT d[2] (1249:1249:1249) (1290:1290:1290)) + (PORT d[3] (1284:1284:1284) (1331:1331:1331)) + (PORT d[4] (2575:2575:2575) (2806:2806:2806)) + (PORT d[5] (3485:3485:3485) (3709:3709:3709)) + (PORT d[6] (1317:1317:1317) (1415:1415:1415)) + (PORT d[7] (1218:1218:1218) (1279:1279:1279)) + (PORT d[8] (1003:1003:1003) (1027:1027:1027)) + (PORT d[9] (1567:1567:1567) (1623:1623:1623)) + (PORT d[10] (1356:1356:1356) (1454:1454:1454)) + (PORT d[11] (2251:2251:2251) (2436:2436:2436)) + (PORT d[12] (1606:1606:1606) (1702:1702:1702)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (963:963:963) (919:919:919)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (1702:1702:1702) (1655:1655:1655)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (409:409:409)) + (PORT datab (686:686:686) (752:752:752)) + (PORT datac (651:651:651) (716:716:716)) + (PORT datad (645:645:645) (655:655:655)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1183:1183:1183) (1208:1208:1208)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3642:3642:3642) (3824:3824:3824)) + (PORT d[1] (1366:1366:1366) (1493:1493:1493)) + (PORT d[2] (2003:2003:2003) (2099:2099:2099)) + (PORT d[3] (2459:2459:2459) (2585:2585:2585)) + (PORT d[4] (2200:2200:2200) (2332:2332:2332)) + (PORT d[5] (1345:1345:1345) (1450:1450:1450)) + (PORT d[6] (1456:1456:1456) (1487:1487:1487)) + (PORT d[7] (3346:3346:3346) (3494:3494:3494)) + (PORT d[8] (3607:3607:3607) (3856:3856:3856)) + (PORT d[9] (3167:3167:3167) (3306:3306:3306)) + (PORT d[10] (3154:3154:3154) (3327:3327:3327)) + (PORT d[11] (1793:1793:1793) (1891:1891:1891)) + (PORT d[12] (1416:1416:1416) (1454:1454:1454)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1620:1620:1620) (1580:1580:1580)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (2766:2766:2766) (2809:2809:2809)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1075:1075:1075)) + (PORT datab (1410:1410:1410) (1504:1504:1504)) + (PORT datac (532:532:532) (545:545:545)) + (PORT datad (1173:1173:1173) (1173:1173:1173)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1641:1641:1641) (1729:1729:1729)) (PORT clk (1857:1857:1857) (1885:1885:1885)) ) ) @@ -47588,22 +39953,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1690:1690:1690) (1807:1807:1807)) - (PORT d[1] (2046:2046:2046) (2145:2145:2145)) - (PORT d[2] (3364:3364:3364) (3706:3706:3706)) - (PORT d[3] (2988:2988:2988) (3217:3217:3217)) - (PORT d[4] (2266:2266:2266) (2486:2486:2486)) - (PORT d[5] (1749:1749:1749) (1820:1820:1820)) - (PORT d[6] (2313:2313:2313) (2470:2470:2470)) - (PORT d[7] (2955:2955:2955) (3126:3126:3126)) - (PORT d[8] (1762:1762:1762) (1854:1854:1854)) - (PORT d[9] (4063:4063:4063) (4204:4204:4204)) - (PORT d[10] (1916:1916:1916) (1991:1991:1991)) - (PORT d[11] (2215:2215:2215) (2437:2437:2437)) - (PORT d[12] (2676:2676:2676) (2810:2810:2810)) + (PORT d[0] (2872:2872:2872) (2966:2966:2966)) + (PORT d[1] (2017:2017:2017) (2182:2182:2182)) + (PORT d[2] (1954:1954:1954) (2061:2061:2061)) + (PORT d[3] (1897:1897:1897) (2022:2022:2022)) + (PORT d[4] (3021:3021:3021) (3172:3172:3172)) + (PORT d[5] (2229:2229:2229) (2391:2391:2391)) + (PORT d[6] (1711:1711:1711) (1774:1774:1774)) + (PORT d[7] (2133:2133:2133) (2250:2250:2250)) + (PORT d[8] (2427:2427:2427) (2610:2610:2610)) + (PORT d[9] (1679:1679:1679) (1785:1785:1785)) + (PORT d[10] (1442:1442:1442) (1508:1508:1508)) + (PORT d[11] (1723:1723:1723) (1780:1780:1780)) + (PORT d[12] (2286:2286:2286) (2347:2347:2347)) (PORT clk (1854:1854:1854) (1881:1881:1881)) ) ) @@ -47613,10 +39978,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1802:1802:1802) (1764:1764:1764)) + (PORT d[0] (2567:2567:2567) (2620:2620:2620)) (PORT clk (1854:1854:1854) (1881:1881:1881)) ) ) @@ -47626,17 +39991,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (2948:2948:2948) (2933:2933:2933)) + (PORT d[0] (3733:3733:3733) (3648:3648:3648)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1858:1858:1858) (1886:1886:1886)) @@ -47646,7 +40011,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1858:1858:1858) (1886:1886:1886)) @@ -47656,7 +40021,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1858:1858:1858) (1886:1886:1886)) @@ -47666,7 +40031,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1858:1858:1858) (1886:1886:1886)) @@ -47676,7 +40041,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1812:1812:1812) (1810:1810:1810)) @@ -47690,10 +40055,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (3414:3414:3414) (3505:3505:3505)) + (PORT d[0] (2034:2034:2034) (2028:2028:2028)) (PORT clk (1822:1822:1822) (1816:1816:1816)) ) ) @@ -47703,22 +40068,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1886:1886:1886) (1997:1997:1997)) - (PORT d[1] (1803:1803:1803) (1927:1927:1927)) - (PORT d[2] (1864:1864:1864) (1977:1977:1977)) - (PORT d[3] (1954:1954:1954) (2123:2123:2123)) - (PORT d[4] (1856:1856:1856) (1953:1953:1953)) - (PORT d[5] (1852:1852:1852) (1945:1945:1945)) - (PORT d[6] (2034:2034:2034) (2116:2116:2116)) - (PORT d[7] (1921:1921:1921) (2042:2042:2042)) - (PORT d[8] (2057:2057:2057) (2134:2134:2134)) - (PORT d[9] (2046:2046:2046) (2126:2126:2126)) - (PORT d[10] (1870:1870:1870) (1972:1972:1972)) - (PORT d[11] (2002:2002:2002) (2092:2092:2092)) - (PORT d[12] (1872:1872:1872) (1984:1984:1984)) + (PORT d[0] (4393:4393:4393) (4461:4461:4461)) + (PORT d[1] (4131:4131:4131) (4181:4181:4181)) + (PORT d[2] (4247:4247:4247) (4323:4323:4323)) + (PORT d[3] (4546:4546:4546) (4614:4614:4614)) + (PORT d[4] (4322:4322:4322) (4309:4309:4309)) + (PORT d[5] (4617:4617:4617) (4651:4651:4651)) + (PORT d[6] (4408:4408:4408) (4485:4485:4485)) + (PORT d[7] (4302:4302:4302) (4274:4274:4274)) + (PORT d[8] (4572:4572:4572) (4637:4637:4637)) + (PORT d[9] (4446:4446:4446) (4691:4691:4691)) + (PORT d[10] (4705:4705:4705) (4743:4743:4743)) + (PORT d[11] (4358:4358:4358) (4390:4390:4390)) + (PORT d[12] (4507:4507:4507) (4645:4645:4645)) (PORT clk (1818:1818:1818) (1812:1812:1812)) ) ) @@ -47728,7 +40093,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1822:1822:1822) (1816:1816:1816)) @@ -47737,7 +40102,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) (DELAY (ABSOLUTE (PORT clk (1823:1823:1823) (1817:1817:1817)) @@ -47747,7 +40112,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1823:1823:1823) (1817:1817:1817)) @@ -47757,7 +40122,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1823:1823:1823) (1817:1817:1817)) @@ -47767,7 +40132,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1823:1823:1823) (1817:1817:1817)) @@ -47777,7 +40142,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) (DELAY (ABSOLUTE (PORT clk (1814:1814:1814) (1812:1812:1812)) @@ -47790,15 +40155,426 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) (DELAY (ABSOLUTE - (PORT dataa (1012:1012:1012) (1121:1121:1121)) - (PORT datab (980:980:980) (1047:1047:1047)) - (PORT datac (900:900:900) (912:912:912)) - (PORT datad (1449:1449:1449) (1539:1539:1539)) - (IOPATH dataa combout (339:339:339) (367:367:367)) + (PORT d[0] (2840:2840:2840) (2949:2949:2949)) + (PORT d[1] (1732:1732:1732) (1897:1897:1897)) + (PORT d[2] (1932:1932:1932) (2053:2053:2053)) + (PORT d[3] (1899:1899:1899) (2019:2019:2019)) + (PORT d[4] (2772:2772:2772) (2916:2916:2916)) + (PORT d[5] (2232:2232:2232) (2415:2415:2415)) + (PORT d[6] (2007:2007:2007) (2069:2069:2069)) + (PORT d[7] (2130:2130:2130) (2260:2260:2260)) + (PORT d[8] (2390:2390:2390) (2571:2571:2571)) + (PORT d[9] (1959:1959:1959) (2082:2082:2082)) + (PORT d[10] (1985:1985:1985) (2067:2067:2067)) + (PORT d[11] (2017:2017:2017) (2091:2091:2091)) + (PORT d[12] (2566:2566:2566) (2656:2656:2656)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1884:1884:1884)) + (PORT d[0] (2730:2730:2730) (2796:2796:2796)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1622:1622:1622) (1706:1706:1706)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2870:2870:2870) (2964:2964:2964)) + (PORT d[1] (2048:2048:2048) (2231:2231:2231)) + (PORT d[2] (1893:1893:1893) (1990:1990:1990)) + (PORT d[3] (1883:1883:1883) (2014:2014:2014)) + (PORT d[4] (3037:3037:3037) (3174:3174:3174)) + (PORT d[5] (1957:1957:1957) (2122:2122:2122)) + (PORT d[6] (1728:1728:1728) (1783:1783:1783)) + (PORT d[7] (1821:1821:1821) (1856:1856:1856)) + (PORT d[8] (2421:2421:2421) (2612:2612:2612)) + (PORT d[9] (1968:1968:1968) (2080:2080:2080)) + (PORT d[10] (2002:2002:2002) (2089:2089:2089)) + (PORT d[11] (2528:2528:2528) (2597:2597:2597)) + (PORT d[12] (2240:2240:2240) (2309:2309:2309)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2519:2519:2519) (2503:2503:2503)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (3674:3674:3674) (3756:3756:3756)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2034:2034:2034) (2023:2023:2023)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4437:4437:4437) (4508:4508:4508)) + (PORT d[1] (4211:4211:4211) (4251:4251:4251)) + (PORT d[2] (4278:4278:4278) (4341:4341:4341)) + (PORT d[3] (4543:4543:4543) (4609:4609:4609)) + (PORT d[4] (4346:4346:4346) (4342:4342:4342)) + (PORT d[5] (4610:4610:4610) (4641:4641:4641)) + (PORT d[6] (4708:4708:4708) (4757:4757:4757)) + (PORT d[7] (4312:4312:4312) (4268:4268:4268)) + (PORT d[8] (4489:4489:4489) (4504:4504:4504)) + (PORT d[9] (4453:4453:4453) (4722:4722:4722)) + (PORT d[10] (4622:4622:4622) (4654:4654:4654)) + (PORT d[11] (4366:4366:4366) (4392:4392:4392)) + (PORT d[12] (4506:4506:4506) (4645:4645:4645)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1206:1206:1206) (1287:1287:1287)) + (PORT datab (1437:1437:1437) (1489:1489:1489)) + (PORT datac (1126:1126:1126) (1177:1177:1177)) + (PORT datad (1429:1429:1429) (1485:1485:1485)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3633:3633:3633) (3814:3814:3814)) + (PORT d[1] (2642:2642:2642) (2867:2867:2867)) + (PORT d[2] (1648:1648:1648) (1726:1726:1726)) + (PORT d[3] (2160:2160:2160) (2263:2263:2263)) + (PORT d[4] (2162:2162:2162) (2254:2254:2254)) + (PORT d[5] (1662:1662:1662) (1786:1786:1786)) + (PORT d[6] (1132:1132:1132) (1171:1171:1171)) + (PORT d[7] (1160:1160:1160) (1190:1190:1190)) + (PORT d[8] (2171:2171:2171) (2353:2353:2353)) + (PORT d[9] (2266:2266:2266) (2413:2413:2413)) + (PORT d[10] (2562:2562:2562) (2693:2693:2693)) + (PORT d[11] (915:915:915) (961:961:961)) + (PORT d[12] (1750:1750:1750) (1775:1775:1775)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (3453:3453:3453) (3330:3330:3330)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1208:1208:1208) (1217:1217:1217)) + (PORT datab (1079:1079:1079) (1088:1088:1088)) + (PORT datac (181:181:181) (219:219:219)) + (PORT datad (1384:1384:1384) (1408:1408:1408)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -47807,14 +40583,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) + (INSTANCE D\[0\]\~54) (DELAY (ABSOLUTE - (PORT dataa (1009:1009:1009) (1117:1117:1117)) - (PORT datab (1493:1493:1493) (1569:1569:1569)) - (PORT datac (1124:1124:1124) (1151:1151:1151)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (1502:1502:1502) (1614:1614:1614)) + (PORT datab (951:951:951) (1007:1007:1007)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (778:778:778)) + (PORT datab (1164:1164:1164) (1255:1255:1255)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1972:1972:1972) (2064:2064:2064)) + (PORT datab (1148:1148:1148) (1200:1200:1200)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (843:843:843) (868:868:868)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -47823,155 +40631,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~89) + (INSTANCE D\[0\]\~58) (DELAY (ABSOLUTE - (PORT dataa (2740:2740:2740) (2944:2944:2944)) - (PORT datab (1198:1198:1198) (1260:1260:1260)) - (PORT datac (979:979:979) (984:984:984)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (985:985:985)) - (PORT datab (1211:1211:1211) (1307:1307:1307)) - (PORT datac (887:887:887) (923:923:923)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1011:1011:1011)) - (PORT datac (193:193:193) (226:226:226)) + (PORT dataa (1975:1975:1975) (2066:2066:2066)) + (PORT datab (647:647:647) (708:708:708)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1634:1634:1634) (1673:1673:1673)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1431:1431:1431)) - (PORT datab (1271:1271:1271) (1357:1357:1357)) - (PORT datac (814:814:814) (834:834:834)) - (PORT datad (632:632:632) (690:690:690)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~8) + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) (DELAY (ABSOLUTE - (PORT dataa (623:623:623) (666:666:666)) - (PORT datac (1211:1211:1211) (1285:1285:1285)) - (PORT datad (1019:1019:1019) (1049:1049:1049)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (970:970:970)) - (PORT datab (645:645:645) (689:689:689)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (643:643:643) (668:668:668)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1412:1412:1412) (1468:1468:1468)) - (PORT datab (1305:1305:1305) (1363:1363:1363)) - (PORT datac (283:283:283) (380:380:380)) - (PORT datad (286:286:286) (376:376:376)) + (PORT dataa (977:977:977) (1044:1044:1044)) + (PORT datab (918:918:918) (964:964:964)) + (PORT datac (244:244:244) (297:297:297)) + (PORT datad (1588:1588:1588) (1606:1606:1606)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (691:691:691)) - (PORT datab (1094:1094:1094) (1129:1129:1129)) - (PORT datac (566:566:566) (581:581:581)) - (PORT datad (2821:2821:2821) (2883:2883:2883)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -47979,13 +40663,59 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) + (INSTANCE z80_\|data_pins_\|dout\[0\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1544:1544:1544)) - (PORT asdata (667:667:667) (689:689:689)) - (PORT clrn (1570:1570:1570) (1550:1550:1550)) - (PORT ena (1954:1954:1954) (1960:1960:1960)) + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (393:393:393) (423:423:423)) + (PORT datac (407:407:407) (468:468:468)) + (PORT datad (674:674:674) (692:692:692)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1004:1004:1004)) + (PORT datab (1377:1377:1377) (1376:1376:1376)) + (PORT datac (889:889:889) (939:939:939)) + (PORT datad (892:892:892) (894:894:894)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT asdata (1523:1523:1523) (1555:1555:1555)) + (PORT clrn (1576:1576:1576) (1555:1555:1555)) + (PORT ena (1506:1506:1506) (1484:1484:1484)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -47997,30 +40727,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (INSTANCE z80_\|pla_decode_\|Equal63\~0) (DELAY (ABSOLUTE - (PORT dataa (589:589:589) (616:616:616)) - (PORT datab (261:261:261) (343:343:343)) - (PORT datad (1208:1208:1208) (1318:1318:1318)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1988:1988:1988) (2128:2128:2128)) + (PORT datab (1534:1534:1534) (1633:1633:1633)) + (PORT datac (227:227:227) (272:272:272)) + (PORT datad (1108:1108:1108) (1149:1149:1149)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) (DELAY (ABSOLUTE - (PORT dataa (591:591:591) (619:619:619)) - (PORT datab (664:664:664) (698:698:698)) - (PORT datac (1041:1041:1041) (1120:1120:1120)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (1494:1494:1494) (1599:1599:1599)) + (PORT datab (1480:1480:1480) (1588:1588:1588)) + (PORT datac (1844:1844:1844) (1910:1910:1910)) + (PORT datad (400:400:400) (434:434:434)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (496:496:496)) + (PORT datab (712:712:712) (746:746:746)) + (PORT datac (1434:1434:1434) (1535:1535:1535)) + (PORT datad (1300:1300:1300) (1393:1393:1393)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (734:734:734)) + (PORT datac (1154:1154:1154) (1186:1186:1186)) + (PORT datad (918:918:918) (942:942:942)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48028,14 +40789,227 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (INSTANCE z80_\|alu_control_\|db\[6\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1181:1181:1181) (1193:1193:1193)) - (PORT datab (763:763:763) (777:777:777)) - (PORT datac (178:178:178) (214:214:214)) - (PORT datad (1218:1218:1218) (1304:1304:1304)) + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (661:661:661) (720:720:720)) + (PORT datac (871:871:871) (900:900:900)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (558:558:558)) + (PORT datab (903:903:903) (932:932:932)) + (PORT datac (591:591:591) (604:604:604)) + (PORT datad (1156:1156:1156) (1185:1185:1185)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (673:673:673)) + (PORT datab (955:955:955) (981:981:981)) + (PORT datac (646:646:646) (694:694:694)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (931:931:931)) + (PORT datab (243:243:243) (291:291:291)) + (PORT datac (626:626:626) (680:680:680)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (757:757:757) (859:859:859)) + (PORT datab (722:722:722) (821:821:821)) + (PORT datac (1142:1142:1142) (1227:1227:1227)) + (PORT datad (912:912:912) (978:978:978)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (707:707:707)) + (PORT datab (345:345:345) (371:371:371)) + (PORT datac (711:711:711) (812:812:812)) + (PORT datad (733:733:733) (834:834:834)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (904:904:904)) + (PORT datac (708:708:708) (801:801:801)) + (PORT datad (1136:1136:1136) (1221:1221:1221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (243:243:243)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (535:535:535)) + (PORT datab (659:659:659) (735:735:735)) + (PORT datad (723:723:723) (804:804:804)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~136) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (585:585:585)) + (PORT datab (451:451:451) (519:519:519)) + (PORT datad (651:651:651) (723:723:723)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (763:763:763)) + (PORT datab (663:663:663) (692:692:692)) + (PORT datad (833:833:833) (881:881:881)) (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (905:905:905)) + (PORT datab (628:628:628) (650:650:650)) + (PORT datad (616:616:616) (634:634:634)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (906:906:906)) + (PORT datab (874:874:874) (902:902:902)) + (PORT datac (610:610:610) (671:671:671)) + (PORT datad (657:657:657) (708:708:708)) + (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -48044,29 +41018,1781 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) (DELAY (ABSOLUTE - (PORT dataa (1058:1058:1058) (1089:1089:1089)) - (PORT datab (885:885:885) (952:952:952)) - (PORT datad (643:643:643) (667:667:667)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (822:822:822) (934:934:934)) + (PORT datab (697:697:697) (727:727:727)) + (PORT datac (960:960:960) (1039:1039:1039)) + (PORT datad (1384:1384:1384) (1501:1501:1501)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~21) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~128) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (649:649:649) (696:696:696)) - (PORT datac (1210:1210:1210) (1284:1284:1284)) - (PORT datad (1058:1058:1058) (1073:1073:1073)) + (PORT dataa (970:970:970) (1046:1046:1046)) + (PORT datab (788:788:788) (902:902:902)) + (PORT datac (903:903:903) (997:997:997)) + (PORT datad (767:767:767) (878:878:878)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (385:385:385)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (904:904:904) (977:977:977)) (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (636:636:636)) + (PORT datab (964:964:964) (1050:1050:1050)) + (PORT datad (568:568:568) (584:584:584)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1590:1590:1590) (1687:1687:1687)) + (PORT datac (744:744:744) (848:848:848)) + (PORT datad (713:713:713) (799:799:799)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (730:730:730)) + (PORT datab (1231:1231:1231) (1291:1291:1291)) + (PORT datac (920:920:920) (989:989:989)) + (PORT datad (331:331:331) (350:350:350)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (260:260:260)) + (PORT datab (965:965:965) (1053:1053:1053)) + (PORT datad (361:361:361) (388:388:388)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (1349:1349:1349) (1392:1392:1392)) + (PORT datab (1223:1223:1223) (1278:1278:1278)) + (PORT datac (216:216:216) (293:293:293)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (536:536:536)) + (PORT datab (659:659:659) (734:734:734)) + (PORT datad (725:725:725) (804:804:804)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (608:608:608)) + (PORT datab (728:728:728) (826:826:826)) + (PORT datac (1546:1546:1546) (1656:1656:1656)) + (PORT datad (580:580:580) (596:596:596)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (689:689:689)) + (PORT datab (745:745:745) (852:852:852)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~3) + (DELAY + (ABSOLUTE + (PORT datab (1510:1510:1510) (1603:1603:1603)) + (PORT datac (869:869:869) (961:961:961)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (453:453:453)) + (PORT datab (632:632:632) (659:659:659)) + (PORT datac (1349:1349:1349) (1408:1408:1408)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (903:903:903)) + (PORT datac (702:702:702) (794:794:794)) + (PORT datad (1130:1130:1130) (1214:1214:1214)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1266:1266:1266)) + (PORT datab (724:724:724) (824:824:824)) + (PORT datac (642:642:642) (670:670:670)) + (PORT datad (909:909:909) (977:977:977)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (411:411:411)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (605:605:605)) + (PORT datab (363:363:363) (394:394:394)) + (PORT datad (717:717:717) (811:811:811)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1168:1168:1168)) + (PORT datab (1142:1142:1142) (1214:1214:1214)) + (PORT datac (639:639:639) (698:698:698)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1616:1616:1616) (1662:1662:1662)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3349:3349:3349) (3565:3565:3565)) + (PORT d[1] (1605:1605:1605) (1743:1743:1743)) + (PORT d[2] (2398:2398:2398) (2522:2522:2522)) + (PORT d[3] (1878:1878:1878) (1993:1993:1993)) + (PORT d[4] (1904:1904:1904) (2011:2011:2011)) + (PORT d[5] (2072:2072:2072) (2262:2262:2262)) + (PORT d[6] (2267:2267:2267) (2352:2352:2352)) + (PORT d[7] (2156:2156:2156) (2268:2268:2268)) + (PORT d[8] (2927:2927:2927) (3117:3117:3117)) + (PORT d[9] (2257:2257:2257) (2323:2323:2323)) + (PORT d[10] (4015:4015:4015) (4256:4256:4256)) + (PORT d[11] (1788:1788:1788) (1883:1883:1883)) + (PORT d[12] (2324:2324:2324) (2423:2423:2423)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (2435:2435:2435) (2530:2530:2530)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1496:1496:1496) (1570:1570:1570)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3471:3471:3471) (3598:3598:3598)) + (PORT d[1] (1681:1681:1681) (1841:1841:1841)) + (PORT d[2] (1803:1803:1803) (1868:1868:1868)) + (PORT d[3] (2137:2137:2137) (2245:2245:2245)) + (PORT d[4] (2206:2206:2206) (2306:2306:2306)) + (PORT d[5] (1648:1648:1648) (1787:1787:1787)) + (PORT d[6] (1447:1447:1447) (1468:1468:1468)) + (PORT d[7] (1455:1455:1455) (1504:1504:1504)) + (PORT d[8] (2907:2907:2907) (3106:3106:3106)) + (PORT d[9] (2261:2261:2261) (2404:2404:2404)) + (PORT d[10] (2303:2303:2303) (2432:2432:2432)) + (PORT d[11] (2139:2139:2139) (2251:2251:2251)) + (PORT d[12] (2022:2022:2022) (2077:2077:2077)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2862:2862:2862) (2854:2854:2854)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT d[0] (4272:4272:4272) (4376:4376:4376)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1801:1801:1801)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1739:1739:1739) (1715:1715:1715)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4403:4403:4403) (4442:4442:4442)) + (PORT d[1] (4232:4232:4232) (4305:4305:4305)) + (PORT d[2] (4291:4291:4291) (4336:4336:4336)) + (PORT d[3] (4528:4528:4528) (4564:4564:4564)) + (PORT d[4] (4637:4637:4637) (4664:4664:4664)) + (PORT d[5] (4315:4315:4315) (4358:4358:4358)) + (PORT d[6] (4706:4706:4706) (4798:4798:4798)) + (PORT d[7] (4277:4277:4277) (4349:4349:4349)) + (PORT d[8] (4511:4511:4511) (4526:4526:4526)) + (PORT d[9] (4469:4469:4469) (4738:4738:4738)) + (PORT d[10] (4368:4368:4368) (4407:4407:4407)) + (PORT d[11] (4392:4392:4392) (4374:4374:4374)) + (PORT d[12] (4337:4337:4337) (4342:4342:4342)) + (PORT clk (1809:1809:1809) (1803:1803:1803)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4186:4186:4186) (4425:4425:4425)) + (PORT d[1] (2884:2884:2884) (3131:3131:3131)) + (PORT d[2] (2708:2708:2708) (2819:2819:2819)) + (PORT d[3] (2283:2283:2283) (2458:2458:2458)) + (PORT d[4] (2517:2517:2517) (2710:2710:2710)) + (PORT d[5] (2529:2529:2529) (2722:2722:2722)) + (PORT d[6] (1890:1890:1890) (2008:2008:2008)) + (PORT d[7] (2314:2314:2314) (2443:2443:2443)) + (PORT d[8] (3115:3115:3115) (3376:3376:3376)) + (PORT d[9] (2627:2627:2627) (2762:2762:2762)) + (PORT d[10] (4822:4822:4822) (5078:5078:5078)) + (PORT d[11] (1897:1897:1897) (2050:2050:2050)) + (PORT d[12] (2209:2209:2209) (2354:2354:2354)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1882:1882:1882)) + (PORT d[0] (3638:3638:3638) (3555:3555:3555)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1555:1555:1555) (1647:1647:1647)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3013:3013:3013) (3193:3193:3193)) + (PORT d[1] (2314:2314:2314) (2501:2501:2501)) + (PORT d[2] (2182:2182:2182) (2293:2293:2293)) + (PORT d[3] (1900:1900:1900) (2029:2029:2029)) + (PORT d[4] (2430:2430:2430) (2538:2538:2538)) + (PORT d[5] (1950:1950:1950) (2108:2108:2108)) + (PORT d[6] (1747:1747:1747) (1762:1762:1762)) + (PORT d[7] (2376:2376:2376) (2506:2506:2506)) + (PORT d[8] (2895:2895:2895) (3077:3077:3077)) + (PORT d[9] (1983:1983:1983) (2113:2113:2113)) + (PORT d[10] (2017:2017:2017) (2125:2125:2125)) + (PORT d[11] (2437:2437:2437) (2546:2546:2546)) + (PORT d[12] (2561:2561:2561) (2626:2626:2626)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2577:2577:2577) (2632:2632:2632)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (4055:4055:4055) (3952:3952:3952)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1804:1804:1804) (1802:1802:1802)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2048:2048:2048) (2021:2021:2021)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4402:4402:4402) (4453:4453:4453)) + (PORT d[1] (4222:4222:4222) (4285:4285:4285)) + (PORT d[2] (4296:4296:4296) (4356:4356:4356)) + (PORT d[3] (4467:4467:4467) (4510:4510:4510)) + (PORT d[4] (4361:4361:4361) (4378:4378:4378)) + (PORT d[5] (4645:4645:4645) (4676:4676:4676)) + (PORT d[6] (4445:4445:4445) (4533:4533:4533)) + (PORT d[7] (4329:4329:4329) (4398:4398:4398)) + (PORT d[8] (4517:4517:4517) (4536:4536:4536)) + (PORT d[9] (4456:4456:4456) (4702:4702:4702)) + (PORT d[10] (4317:4317:4317) (4323:4323:4323)) + (PORT d[11] (4684:4684:4684) (4714:4714:4714)) + (PORT d[12] (4438:4438:4438) (4553:4553:4553)) + (PORT clk (1810:1810:1810) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1806:1806:1806) (1804:1804:1804)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (1219:1219:1219)) + (PORT datab (947:947:947) (1002:1002:1002)) + (PORT datac (1385:1385:1385) (1418:1418:1418)) + (PORT datad (1436:1436:1436) (1475:1475:1475)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1314:1314:1314) (1369:1369:1369)) + (PORT datab (951:951:951) (1008:1008:1008)) + (PORT datac (1440:1440:1440) (1502:1502:1502)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (901:901:901) (939:939:939)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3349:3349:3349) (3527:3527:3527)) + (PORT d[1] (1734:1734:1734) (1904:1904:1904)) + (PORT d[2] (1993:1993:1993) (2068:2068:2068)) + (PORT d[3] (2163:2163:2163) (2257:2257:2257)) + (PORT d[4] (1834:1834:1834) (1918:1918:1918)) + (PORT d[5] (1363:1363:1363) (1460:1460:1460)) + (PORT d[6] (1449:1449:1449) (1474:1474:1474)) + (PORT d[7] (3354:3354:3354) (3503:3503:3503)) + (PORT d[8] (2447:2447:2447) (2653:2653:2653)) + (PORT d[9] (3517:3517:3517) (3682:3682:3682)) + (PORT d[10] (2917:2917:2917) (3102:3102:3102)) + (PORT d[11] (1485:1485:1485) (1553:1553:1553)) + (PORT d[12] (1460:1460:1460) (1502:1502:1502)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3345:3345:3345) (3355:3355:3355)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (1944:1944:1944) (1906:1906:1906)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1470:1470:1470) (1515:1515:1515)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3671:3671:3671) (3886:3886:3886)) + (PORT d[1] (1690:1690:1690) (1854:1854:1854)) + (PORT d[2] (3275:3275:3275) (3430:3430:3430)) + (PORT d[3] (2158:2158:2158) (2262:2262:2262)) + (PORT d[4] (2542:2542:2542) (2676:2676:2676)) + (PORT d[5] (1672:1672:1672) (1804:1804:1804)) + (PORT d[6] (1797:1797:1797) (1871:1871:1871)) + (PORT d[7] (1692:1692:1692) (1762:1762:1762)) + (PORT d[8] (3323:3323:3323) (3550:3550:3550)) + (PORT d[9] (2846:2846:2846) (2959:2959:2959)) + (PORT d[10] (3476:3476:3476) (3688:3688:3688)) + (PORT d[11] (1790:1790:1790) (1894:1894:1894)) + (PORT d[12] (1727:1727:1727) (1788:1788:1788)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1941:1941:1941) (1913:1913:1913)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1869:1869:1869)) + (PORT d[0] (2779:2779:2779) (2775:2775:2775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1828:1828:1828)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (986:986:986) (991:991:991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1247:1247:1247) (1305:1305:1305)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3351:3351:3351) (3542:3542:3542)) + (PORT d[1] (1331:1331:1331) (1442:1442:1442)) + (PORT d[2] (1949:1949:1949) (2052:2052:2052)) + (PORT d[3] (1549:1549:1549) (1617:1617:1617)) + (PORT d[4] (1868:1868:1868) (1957:1957:1957)) + (PORT d[5] (1641:1641:1641) (1721:1721:1721)) + (PORT d[6] (1178:1178:1178) (1228:1228:1228)) + (PORT d[7] (1451:1451:1451) (1507:1507:1507)) + (PORT d[8] (2507:2507:2507) (2697:2697:2697)) + (PORT d[9] (3505:3505:3505) (3649:3649:3649)) + (PORT d[10] (2878:2878:2878) (3044:3044:3044)) + (PORT d[11] (1237:1237:1237) (1307:1307:1307)) + (PORT d[12] (1108:1108:1108) (1125:1125:1125)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2872:2872:2872) (2909:2909:2909)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (3248:3248:3248) (3325:3325:3325)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1750:1750:1750) (1835:1835:1835)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3365:3365:3365) (3581:3581:3581)) + (PORT d[1] (1702:1702:1702) (1864:1864:1864)) + (PORT d[2] (2694:2694:2694) (2816:2816:2816)) + (PORT d[3] (2143:2143:2143) (2257:2257:2257)) + (PORT d[4] (2191:2191:2191) (2314:2314:2314)) + (PORT d[5] (2392:2392:2392) (2607:2607:2607)) + (PORT d[6] (2106:2106:2106) (2209:2209:2209)) + (PORT d[7] (2467:2467:2467) (2597:2597:2597)) + (PORT d[8] (3036:3036:3036) (3248:3248:3248)) + (PORT d[9] (2577:2577:2577) (2669:2669:2669)) + (PORT d[10] (3785:3785:3785) (4034:4034:4034)) + (PORT d[11] (1778:1778:1778) (1856:1856:1856)) + (PORT d[12] (2315:2315:2315) (2396:2396:2396)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2267:2267:2267) (2265:2265:2265)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (2685:2685:2685) (2695:2695:2695)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1829:1829:1829) (1854:1854:1854)) + (PORT datab (1177:1177:1177) (1181:1181:1181)) + (PORT datad (1696:1696:1696) (1748:1748:1748)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1535:1535:1535)) + (PORT datab (1484:1484:1484) (1501:1501:1501)) + (PORT datac (2124:2124:2124) (2189:2189:2189)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (777:777:777)) + (PORT datab (1164:1164:1164) (1255:1255:1255)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (916:916:916)) + (PORT datab (1551:1551:1551) (1605:1605:1605)) + (PORT datac (1462:1462:1462) (1538:1538:1538)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (1168:1168:1168) (1244:1244:1244)) + (PORT datab (1665:1665:1665) (1708:1708:1708)) + (PORT datac (1463:1463:1463) (1538:1538:1538)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1037:1037:1037)) + (PORT datab (1506:1506:1506) (1524:1524:1524)) + (PORT datac (236:236:236) (289:289:289)) + (PORT datad (1153:1153:1153) (1165:1165:1165)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (471:471:471)) + (PORT datab (388:388:388) (422:422:422)) + (PORT datad (671:671:671) (693:693:693)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1007:1007:1007)) + (PORT datab (922:922:922) (965:965:965)) + (PORT datac (888:888:888) (938:938:938)) + (PORT datad (898:898:898) (913:913:913)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48074,13 +42800,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) + (INSTANCE z80_\|ir_\|opcode\[4\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) + (PORT clrn (1571:1571:1571) (1550:1550:1550)) + (PORT ena (1479:1479:1479) (1488:1488:1488)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -48095,8 +42821,8 @@ (INSTANCE z80_\|pla_decode_\|Equal21\~0) (DELAY (ABSOLUTE - (PORT datac (2142:2142:2142) (2218:2218:2218)) - (PORT datad (2370:2370:2370) (2447:2447:2447)) + (PORT datac (1440:1440:1440) (1546:1546:1546)) + (PORT datad (1464:1464:1464) (1552:1552:1552)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48104,202 +42830,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) + (INSTANCE z80_\|execute_\|ctl_mRead\~5) (DELAY (ABSOLUTE - (PORT dataa (1396:1396:1396) (1416:1416:1416)) - (PORT datab (1608:1608:1608) (1686:1686:1686)) - (PORT datac (867:867:867) (892:892:892)) - (PORT datad (610:610:610) (651:651:651)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (457:457:457)) - (PORT datab (310:310:310) (406:406:406)) - (PORT datac (254:254:254) (338:338:338)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (266:266:266)) - (PORT datab (1113:1113:1113) (1135:1135:1135)) - (PORT datad (176:176:176) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1243:1243:1243) (1353:1353:1353)) - (PORT datab (607:607:607) (643:643:643)) - (PORT datac (716:716:716) (794:794:794)) - (PORT datad (822:822:822) (854:854:854)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (621:621:621)) - (PORT datab (555:555:555) (578:578:578)) - (PORT datac (1033:1033:1033) (1081:1081:1081)) - (PORT datad (1301:1301:1301) (1301:1301:1301)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1140:1140:1140) (1189:1189:1189)) - (PORT datab (723:723:723) (781:781:781)) - (PORT datac (1889:1889:1889) (1933:1933:1933)) - (PORT datad (817:817:817) (826:826:826)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (954:954:954) (987:987:987)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (684:684:684)) - (PORT datab (1252:1252:1252) (1353:1353:1353)) - (PORT datac (847:847:847) (869:869:869)) - (PORT datad (1302:1302:1302) (1301:1301:1301)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (908:908:908)) - (PORT datab (1620:1620:1620) (1666:1666:1666)) - (PORT datac (1058:1058:1058) (1088:1088:1088)) - (PORT datad (554:554:554) (558:558:558)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (619:619:619)) - (PORT datab (863:863:863) (908:908:908)) - (PORT datac (1140:1140:1140) (1140:1140:1140)) - (PORT datad (870:870:870) (920:920:920)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (562:562:562) (576:576:576)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (987:987:987) (1072:1072:1072)) - (PORT datab (708:708:708) (790:790:790)) - (PORT datac (937:937:937) (1010:1010:1010)) - (PORT datad (1112:1112:1112) (1181:1181:1181)) + (PORT dataa (1381:1381:1381) (1434:1434:1434)) + (PORT datab (981:981:981) (1038:1038:1038)) + (PORT datac (1636:1636:1636) (1757:1757:1757)) + (PORT datad (1217:1217:1217) (1298:1298:1298)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -48309,107 +42846,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~125) + (INSTANCE z80_\|execute_\|fIOWrite\~2) (DELAY (ABSOLUTE - (PORT dataa (426:426:426) (526:526:526)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datad (196:196:196) (231:231:231)) - (IOPATH dataa combout (325:325:325) (328:328:328)) + (PORT dataa (1286:1286:1286) (1367:1367:1367)) + (PORT datab (1528:1528:1528) (1599:1599:1599)) + (PORT datac (821:821:821) (830:830:830)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT datab (1536:1536:1536) (1647:1647:1647)) + (PORT datac (1349:1349:1349) (1441:1441:1441)) + (PORT datad (2442:2442:2442) (2633:2633:2633)) (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~126) - (DELAY - (ABSOLUTE - (PORT dataa (1197:1197:1197) (1273:1273:1273)) - (PORT datab (967:967:967) (1041:1041:1041)) - (PORT datad (616:616:616) (686:686:686)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (478:478:478) (557:557:557)) - (PORT datac (1064:1064:1064) (1124:1124:1124)) - (PORT datad (531:531:531) (541:541:541)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (385:385:385) (413:413:413)) - (PORT datad (710:710:710) (790:790:790)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (741:741:741)) - (PORT datab (1858:1858:1858) (1900:1900:1900)) - (PORT datac (215:215:215) (291:291:291)) - (PORT datad (861:861:861) (884:884:884)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48417,77 +42876,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~119) + (INSTANCE z80_\|execute_\|fIOWrite\~4) (DELAY (ABSOLUTE - (PORT dataa (730:730:730) (813:813:813)) - (PORT datab (647:647:647) (714:714:714)) - (PORT datac (1150:1150:1150) (1215:1215:1215)) - (PORT datad (627:627:627) (693:693:693)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~138) - (DELAY - (ABSOLUTE - (PORT dataa (1232:1232:1232) (1282:1282:1282)) - (PORT datab (272:272:272) (356:356:356)) + (PORT dataa (863:863:863) (915:915:915)) + (PORT datab (925:925:925) (953:953:953)) + (PORT datac (1717:1717:1717) (1764:1764:1764)) (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~120) + (INSTANCE z80_\|execute_\|fIOWrite\~5) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (389:389:389)) - (PORT datab (341:341:341) (372:372:372)) - (PORT datad (942:942:942) (1006:1006:1006)) + (PORT dataa (426:426:426) (455:455:455)) + (PORT datab (1184:1184:1184) (1238:1238:1238)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (360:360:360) (383:383:383)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1216:1216:1216)) - (PORT datab (470:470:470) (544:544:544)) - (PORT datac (653:653:653) (728:728:728)) - (PORT datad (936:936:936) (994:994:994)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (325:325:325)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48495,246 +42908,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~122) + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) (DELAY (ABSOLUTE - (PORT dataa (1245:1245:1245) (1305:1305:1305)) - (PORT datab (458:458:458) (533:533:533)) - (PORT datac (1297:1297:1297) (1311:1311:1311)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~123) - (DELAY - (ABSOLUTE - (PORT datab (656:656:656) (678:678:678)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (938:938:938)) - (PORT datab (414:414:414) (475:475:475)) - (PORT datac (825:825:825) (847:847:847)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT dataa (931:931:931) (953:953:953)) + (PORT datab (618:618:618) (660:660:660)) + (PORT datac (888:888:888) (936:936:936)) + (PORT datad (892:892:892) (905:905:905)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~129) + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (255:255:255)) - (PORT datab (729:729:729) (830:830:830)) - (PORT datad (349:349:349) (371:371:371)) + (PORT dataa (2004:2004:2004) (2054:2054:2054)) + (PORT datab (1141:1141:1141) (1140:1140:1140)) + (PORT datac (850:850:850) (856:856:856)) + (PORT datad (641:641:641) (681:681:681)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1558:1558:1558)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (990:990:990) (1077:1077:1077)) - (PORT datab (703:703:703) (790:790:790)) - (PORT datac (937:937:937) (1016:1016:1016)) - (PORT datad (1109:1109:1109) (1180:1180:1180)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~131) + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) (DELAY (ABSOLUTE - (PORT dataa (427:427:427) (524:524:524)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (195:195:195) (228:228:228)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (719:719:719)) - (PORT datab (890:890:890) (956:956:956)) - (PORT datac (943:943:943) (986:986:986)) - (PORT datad (825:825:825) (873:873:873)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (212:212:212) (262:262:262)) - (PORT datab (652:652:652) (678:678:678)) - (PORT datad (362:362:362) (380:380:380)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1555:1555:1555)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (764:764:764)) - (PORT datab (911:911:911) (925:925:925)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (746:746:746)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (2003:2003:2003) (2052:2052:2052)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (942:942:942)) - (PORT datab (608:608:608) (652:652:652)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (587:587:587) (601:601:601)) + (PORT dataa (201:201:201) (243:243:243)) + (PORT datab (596:596:596) (607:607:607)) + (PORT datac (532:532:532) (546:546:546)) + (PORT datad (180:180:180) (208:208:208)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -48742,643 +42954,15 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2443:2443:2443) (2617:2617:2617)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2845:2845:2845) (3069:3069:3069)) - (PORT d[1] (1764:1764:1764) (1918:1918:1918)) - (PORT d[2] (2808:2808:2808) (3034:3034:3034)) - (PORT d[3] (2278:2278:2278) (2485:2485:2485)) - (PORT d[4] (1916:1916:1916) (2070:2070:2070)) - (PORT d[5] (2492:2492:2492) (2660:2660:2660)) - (PORT d[6] (1998:1998:1998) (2117:2117:2117)) - (PORT d[7] (4337:4337:4337) (4519:4519:4519)) - (PORT d[8] (2440:2440:2440) (2604:2604:2604)) - (PORT d[9] (2745:2745:2745) (2859:2859:2859)) - (PORT d[10] (1916:1916:1916) (2043:2043:2043)) - (PORT d[11] (1893:1893:1893) (2055:2055:2055)) - (PORT d[12] (3387:3387:3387) (3562:3562:3562)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2686:2686:2686) (2720:2720:2720)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (2577:2577:2577) (2609:2609:2609)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2704:2704:2704) (2878:2878:2878)) - (PORT clk (1848:1848:1848) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2844:2844:2844) (3075:3075:3075)) - (PORT d[1] (1782:1782:1782) (1945:1945:1945)) - (PORT d[2] (2893:2893:2893) (3113:3113:3113)) - (PORT d[3] (2356:2356:2356) (2593:2593:2593)) - (PORT d[4] (2231:2231:2231) (2388:2388:2388)) - (PORT d[5] (3094:3094:3094) (3295:3295:3295)) - (PORT d[6] (1983:1983:1983) (2105:2105:2105)) - (PORT d[7] (3746:3746:3746) (3908:3908:3908)) - (PORT d[8] (2163:2163:2163) (2307:2307:2307)) - (PORT d[9] (2811:2811:2811) (2934:2934:2934)) - (PORT d[10] (1692:1692:1692) (1841:1841:1841)) - (PORT d[11] (1922:1922:1922) (2093:2093:2093)) - (PORT d[12] (3138:3138:3138) (3275:3275:3275)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2271:2271:2271) (2251:2251:2251)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (PORT d[0] (2571:2571:2571) (2579:2579:2579)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1808:1808:1808) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2982:2982:2982) (3193:3193:3193)) - (PORT clk (1853:1853:1853) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3490:3490:3490) (3749:3749:3749)) - (PORT d[1] (2107:2107:2107) (2306:2306:2306)) - (PORT d[2] (3412:3412:3412) (3618:3618:3618)) - (PORT d[3] (2985:2985:2985) (3269:3269:3269)) - (PORT d[4] (2532:2532:2532) (2723:2723:2723)) - (PORT d[5] (3358:3358:3358) (3590:3590:3590)) - (PORT d[6] (2289:2289:2289) (2433:2433:2433)) - (PORT d[7] (3420:3420:3420) (3554:3554:3554)) - (PORT d[8] (2178:2178:2178) (2310:2310:2310)) - (PORT d[9] (2507:2507:2507) (2596:2596:2596)) - (PORT d[10] (2318:2318:2318) (2495:2495:2495)) - (PORT d[11] (1859:1859:1859) (2017:2017:2017)) - (PORT d[12] (2797:2797:2797) (2911:2911:2911)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2292:2292:2292) (2242:2242:2242)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (PORT d[0] (2998:2998:2998) (3053:3053:3053)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1841:1841:1841)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2405:2405:2405) (2582:2582:2582)) - (PORT clk (1853:1853:1853) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2852:2852:2852) (3065:3065:3065)) - (PORT d[1] (1745:1745:1745) (1886:1886:1886)) - (PORT d[2] (2620:2620:2620) (2858:2858:2858)) - (PORT d[3] (2326:2326:2326) (2553:2553:2553)) - (PORT d[4] (2246:2246:2246) (2415:2415:2415)) - (PORT d[5] (2748:2748:2748) (2954:2954:2954)) - (PORT d[6] (1970:1970:1970) (2074:2074:2074)) - (PORT d[7] (4043:4043:4043) (4206:4206:4206)) - (PORT d[8] (2473:2473:2473) (2622:2622:2622)) - (PORT d[9] (2794:2794:2794) (2935:2935:2935)) - (PORT d[10] (1902:1902:1902) (2019:2019:2019)) - (PORT d[11] (1876:1876:1876) (2036:2036:2036)) - (PORT d[12] (3099:3099:3099) (3256:3256:3256)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2296:2296:2296) (2325:2325:2325)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1882:1882:1882)) - (PORT d[0] (2676:2676:2676) (2738:2738:2738)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1841:1841:1841)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1005:1005:1005)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) (DELAY (ABSOLUTE - (PORT dataa (1434:1434:1434) (1550:1550:1550)) - (PORT datab (630:630:630) (639:639:639)) - (PORT datac (944:944:944) (1042:1042:1042)) - (PORT datad (1158:1158:1158) (1200:1200:1200)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1458:1458:1458) (1510:1510:1510)) - (PORT datab (971:971:971) (1073:1073:1073)) - (PORT datac (1141:1141:1141) (1162:1162:1162)) - (PORT datad (171:171:171) (196:196:196)) + (PORT dataa (1573:1573:1573) (1667:1667:1667)) + (PORT datab (881:881:881) (895:895:895)) + (PORT datac (1465:1465:1465) (1505:1505:1505)) + (PORT datad (1073:1073:1073) (1063:1063:1063)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -49387,23 +42971,298 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) (DELAY (ABSOLUTE - (PORT d[0] (1074:1074:1074) (1153:1153:1153)) - (PORT d[1] (2831:2831:2831) (3099:3099:3099)) - (PORT d[2] (1986:1986:1986) (2118:2118:2118)) - (PORT d[3] (725:725:725) (773:773:773)) - (PORT d[4] (707:707:707) (738:738:738)) - (PORT d[5] (1585:1585:1585) (1671:1671:1671)) - (PORT d[6] (2942:2942:2942) (3097:3097:3097)) - (PORT d[7] (2027:2027:2027) (2127:2127:2127)) - (PORT d[8] (4009:4009:4009) (4252:4252:4252)) - (PORT d[9] (850:850:850) (860:860:860)) - (PORT d[10] (2565:2565:2565) (2755:2755:2755)) - (PORT d[11] (2245:2245:2245) (2463:2463:2463)) - (PORT d[12] (1365:1365:1365) (1359:1359:1359)) + (PORT dataa (637:637:637) (652:652:652)) + (PORT datab (877:877:877) (906:906:906)) + (PORT datac (864:864:864) (874:874:874)) + (PORT datad (1193:1193:1193) (1249:1249:1249)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1291:1291:1291) (1310:1310:1310)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (219:219:219) (289:289:289)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT asdata (567:567:567) (645:645:645)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (890:890:890)) + (PORT datab (351:351:351) (390:390:390)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (1754:1754:1754) (1854:1854:1854)) + (PORT datab (1594:1594:1594) (1729:1729:1729)) + (PORT datac (1191:1191:1191) (1256:1256:1256)) + (PORT datad (1224:1224:1224) (1308:1308:1308)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1170:1170:1170) (1220:1220:1220)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4199:4199:4199) (4456:4456:4456)) + (PORT d[1] (2869:2869:2869) (3121:3121:3121)) + (PORT d[2] (3253:3253:3253) (3349:3349:3349)) + (PORT d[3] (2536:2536:2536) (2717:2717:2717)) + (PORT d[4] (2232:2232:2232) (2420:2420:2420)) + (PORT d[5] (2568:2568:2568) (2749:2749:2749)) + (PORT d[6] (1862:1862:1862) (1979:1979:1979)) + (PORT d[7] (2324:2324:2324) (2461:2461:2461)) + (PORT d[8] (3106:3106:3106) (3383:3383:3383)) + (PORT d[9] (2915:2915:2915) (3048:3048:3048)) + (PORT d[10] (4807:4807:4807) (5077:5077:5077)) + (PORT d[11] (2186:2186:2186) (2342:2342:2342)) + (PORT d[12] (2200:2200:2200) (2338:2338:2338)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1968:1968:1968) (1944:1944:1944)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (2326:2326:2326) (2304:2304:2304)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1193:1193:1193) (1222:1222:1222)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4194:4194:4194) (4449:4449:4449)) + (PORT d[1] (2891:2891:2891) (3144:3144:3144)) + (PORT d[2] (2764:2764:2764) (2858:2858:2858)) + (PORT d[3] (2536:2536:2536) (2713:2713:2713)) + (PORT d[4] (2253:2253:2253) (2443:2443:2443)) + (PORT d[5] (2541:2541:2541) (2717:2717:2717)) + (PORT d[6] (1898:1898:1898) (2008:2008:2008)) + (PORT d[7] (2297:2297:2297) (2428:2428:2428)) + (PORT d[8] (3124:3124:3124) (3401:3401:3401)) + (PORT d[9] (2609:2609:2609) (2741:2741:2741)) + (PORT d[10] (4803:4803:4803) (5068:5068:5068)) + (PORT d[11] (1891:1891:1891) (2036:2036:2036)) + (PORT d[12] (2208:2208:2208) (2353:2353:2353)) (PORT clk (1855:1855:1855) (1880:1880:1880)) ) ) @@ -49413,27 +43272,70 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) (DELAY (ABSOLUTE + (PORT d[0] (2383:2383:2383) (2365:2365:2365)) (PORT clk (1855:1855:1855) (1880:1880:1880)) - (PORT d[0] (1957:1957:1957) (2005:2005:2005)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT d[0] (2857:2857:2857) (2839:2839:2839)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1881:1881:1881)) + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1818:1818:1818) (1843:1843:1843)) @@ -49447,7 +43349,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1003:1003:1003) (1006:1006:1006)) @@ -49456,7 +43358,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1004:1004:1004) (1007:1007:1007)) @@ -49465,7 +43367,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1004:1004:1004) (1007:1007:1007)) @@ -49475,7 +43377,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1004:1004:1004) (1007:1007:1007)) @@ -49485,11 +43387,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1576:1576:1576) (1686:1686:1686)) - (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT d[0] (880:880:880) (918:918:918)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -49498,23 +43400,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1682:1682:1682) (1816:1816:1816)) - (PORT d[1] (1727:1727:1727) (1820:1820:1820)) - (PORT d[2] (3374:3374:3374) (3700:3700:3700)) - (PORT d[3] (2567:2567:2567) (2757:2757:2757)) - (PORT d[4] (2574:2574:2574) (2781:2781:2781)) - (PORT d[5] (1826:1826:1826) (1959:1959:1959)) - (PORT d[6] (2273:2273:2273) (2406:2406:2406)) - (PORT d[7] (2968:2968:2968) (3135:3135:3135)) - (PORT d[8] (2077:2077:2077) (2192:2192:2192)) - (PORT d[9] (4076:4076:4076) (4203:4203:4203)) - (PORT d[10] (2233:2233:2233) (2334:2334:2334)) - (PORT d[11] (3066:3066:3066) (3278:3278:3278)) - (PORT d[12] (3337:3337:3337) (3464:3464:3464)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) + (PORT d[0] (1334:1334:1334) (1380:1380:1380)) + (PORT d[1] (2044:2044:2044) (2248:2248:2248)) + (PORT d[2] (3016:3016:3016) (3126:3126:3126)) + (PORT d[3] (2584:2584:2584) (2783:2783:2783)) + (PORT d[4] (2569:2569:2569) (2761:2761:2761)) + (PORT d[5] (2836:2836:2836) (3029:3029:3029)) + (PORT d[6] (1949:1949:1949) (2075:2075:2075)) + (PORT d[7] (2609:2609:2609) (2760:2760:2760)) + (PORT d[8] (3388:3388:3388) (3680:3680:3680)) + (PORT d[9] (2935:2935:2935) (3067:3067:3067)) + (PORT d[10] (5109:5109:5109) (5374:5374:5374)) + (PORT d[11] (1927:1927:1927) (2066:2066:2066)) + (PORT d[12] (1910:1910:1910) (2033:2033:2033)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -49523,11 +43425,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1744:1744:1744) (1745:1745:1745)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) + (PORT d[0] (1228:1228:1228) (1223:1223:1223)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -49536,17 +43438,2546 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1866:1866:1866) (1893:1893:1893)) - (PORT d[0] (2622:2622:2622) (2637:2637:2637)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2528:2528:2528) (2496:2496:2496)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1430:1430:1430) (1510:1510:1510)) + (PORT datab (977:977:977) (1037:1037:1037)) + (PORT datac (1084:1084:1084) (1106:1106:1106)) + (PORT datad (833:833:833) (863:863:863)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1183:1183:1183) (1216:1216:1216)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3355:3355:3355) (3572:3572:3572)) + (PORT d[1] (1697:1697:1697) (1865:1865:1865)) + (PORT d[2] (2991:2991:2991) (3133:3133:3133)) + (PORT d[3] (2197:2197:2197) (2290:2290:2290)) + (PORT d[4] (2502:2502:2502) (2653:2653:2653)) + (PORT d[5] (2405:2405:2405) (2601:2601:2601)) + (PORT d[6] (2102:2102:2102) (2200:2200:2200)) + (PORT d[7] (2478:2478:2478) (2588:2588:2588)) + (PORT d[8] (3018:3018:3018) (3244:3244:3244)) + (PORT d[9] (2534:2534:2534) (2624:2624:2624)) + (PORT d[10] (3776:3776:3776) (4011:4011:4011)) + (PORT d[11] (1726:1726:1726) (1804:1804:1804)) + (PORT d[12] (2323:2323:2323) (2409:2409:2409)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2206:2206:2206) (2199:2199:2199)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (2749:2749:2749) (2715:2715:2715)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1449:1449:1449) (1499:1499:1499)) + (PORT datab (1154:1154:1154) (1180:1180:1180)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1425:1425:1425) (1425:1425:1425)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1785:1785:1785) (1834:1834:1834)) + (PORT clk (1844:1844:1844) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3330:3330:3330) (3510:3510:3510)) + (PORT d[1] (2345:2345:2345) (2548:2548:2548)) + (PORT d[2] (2224:2224:2224) (2307:2307:2307)) + (PORT d[3] (1895:1895:1895) (2026:2026:2026)) + (PORT d[4] (2445:2445:2445) (2553:2553:2553)) + (PORT d[5] (1968:1968:1968) (2118:2118:2118)) + (PORT d[6] (1422:1422:1422) (1463:1463:1463)) + (PORT d[7] (1469:1469:1469) (1501:1501:1501)) + (PORT d[8] (2903:2903:2903) (3100:3100:3100)) + (PORT d[9] (1984:1984:1984) (2114:2114:2114)) + (PORT d[10] (1991:1991:1991) (2095:2095:2095)) + (PORT d[11] (1441:1441:1441) (1479:1479:1479)) + (PORT d[12] (2020:2020:2020) (2065:2065:2065)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2835:2835:2835) (2823:2823:2823)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1873:1873:1873)) + (PORT d[0] (3960:3960:3960) (4062:4062:4062)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1799:1799:1799) (1798:1798:1798)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1198:1198:1198) (1181:1181:1181)) + (PORT clk (1809:1809:1809) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4418:4418:4418) (4468:4468:4468)) + (PORT d[1] (4222:4222:4222) (4280:4280:4280)) + (PORT d[2] (4287:4287:4287) (4334:4334:4334)) + (PORT d[3] (4530:4530:4530) (4580:4580:4580)) + (PORT d[4] (4340:4340:4340) (4354:4354:4354)) + (PORT d[5] (4359:4359:4359) (4381:4381:4381)) + (PORT d[6] (4659:4659:4659) (4748:4748:4748)) + (PORT d[7] (4373:4373:4373) (4445:4445:4445)) + (PORT d[8] (4529:4529:4529) (4546:4546:4546)) + (PORT d[9] (4710:4710:4710) (4968:4968:4968)) + (PORT d[10] (4380:4380:4380) (4418:4418:4418)) + (PORT d[11] (4364:4364:4364) (4385:4385:4385)) + (PORT d[12] (4681:4681:4681) (4658:4658:4658)) + (PORT clk (1805:1805:1805) (1800:1800:1800)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1804:1804:1804)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2604:2604:2604) (2682:2682:2682)) + (PORT d[1] (2063:2063:2063) (2283:2283:2283)) + (PORT d[2] (2289:2289:2289) (2441:2441:2441)) + (PORT d[3] (2285:2285:2285) (2377:2377:2377)) + (PORT d[4] (2950:2950:2950) (3220:3220:3220)) + (PORT d[5] (2075:2075:2075) (2260:2260:2260)) + (PORT d[6] (1854:1854:1854) (1963:1963:1963)) + (PORT d[7] (2555:2555:2555) (2658:2658:2658)) + (PORT d[8] (2752:2752:2752) (3006:3006:3006)) + (PORT d[9] (1553:1553:1553) (1673:1673:1673)) + (PORT d[10] (1845:1845:1845) (1962:1962:1962)) + (PORT d[11] (2882:2882:2882) (3002:3002:3002)) + (PORT d[12] (1537:1537:1537) (1640:1640:1640)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1892:1892:1892)) + (PORT d[0] (2184:2184:2184) (2245:2245:2245)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1893:1893:1893)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1855:1855:1855)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1018:1018:1018)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1019:1019:1019)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1019:1019:1019)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1019:1019:1019)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3543:3543:3543) (3733:3733:3733)) + (PORT d[1] (1715:1715:1715) (1880:1880:1880)) + (PORT d[2] (2685:2685:2685) (2807:2807:2807)) + (PORT d[3] (2133:2133:2133) (2228:2228:2228)) + (PORT d[4] (1902:1902:1902) (2026:2026:2026)) + (PORT d[5] (2379:2379:2379) (2573:2573:2573)) + (PORT d[6] (2329:2329:2329) (2418:2418:2418)) + (PORT d[7] (2458:2458:2458) (2570:2570:2570)) + (PORT d[8] (2691:2691:2691) (2888:2888:2888)) + (PORT d[9] (2519:2519:2519) (2590:2590:2590)) + (PORT d[10] (3815:3815:3815) (4071:4071:4071)) + (PORT d[11] (1813:1813:1813) (1894:1894:1894)) + (PORT d[12] (2372:2372:2372) (2459:2459:2459)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (2529:2529:2529) (2434:2434:2434)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1649:1649:1649) (1736:1736:1736)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2915:2915:2915) (3030:3030:3030)) + (PORT d[1] (2366:2366:2366) (2611:2611:2611)) + (PORT d[2] (2597:2597:2597) (2777:2777:2777)) + (PORT d[3] (2017:2017:2017) (2075:2075:2075)) + (PORT d[4] (2919:2919:2919) (3173:3173:3173)) + (PORT d[5] (2370:2370:2370) (2578:2578:2578)) + (PORT d[6] (1866:1866:1866) (1962:1962:1962)) + (PORT d[7] (1642:1642:1642) (1751:1751:1751)) + (PORT d[8] (3027:3027:3027) (3282:3282:3282)) + (PORT d[9] (1219:1219:1219) (1304:1304:1304)) + (PORT d[10] (2155:2155:2155) (2296:2296:2296)) + (PORT d[11] (3694:3694:3694) (3833:3833:3833)) + (PORT d[12] (1894:1894:1894) (1995:1995:1995)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2802:2802:2802) (2787:2787:2787)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (3138:3138:3138) (3102:3102:3102)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1813:1813:1813)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2176:2176:2176) (2231:2231:2231)) + (PORT clk (1825:1825:1825) (1819:1819:1819)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4610:4610:4610) (4658:4658:4658)) + (PORT d[1] (4157:4157:4157) (4160:4160:4160)) + (PORT d[2] (4196:4196:4196) (4284:4284:4284)) + (PORT d[3] (4718:4718:4718) (4716:4716:4716)) + (PORT d[4] (4356:4356:4356) (4386:4386:4386)) + (PORT d[5] (4428:4428:4428) (4381:4381:4381)) + (PORT d[6] (4640:4640:4640) (4703:4703:4703)) + (PORT d[7] (4181:4181:4181) (4140:4140:4140)) + (PORT d[8] (4708:4708:4708) (4720:4720:4720)) + (PORT d[9] (4594:4594:4594) (4806:4806:4806)) + (PORT d[10] (4407:4407:4407) (4422:4422:4422)) + (PORT d[11] (4504:4504:4504) (4555:4555:4555)) + (PORT d[12] (4480:4480:4480) (4497:4497:4497)) + (PORT clk (1821:1821:1821) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1819:1819:1819)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1815:1815:1815)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1424:1424:1424) (1496:1496:1496)) + (PORT datab (973:973:973) (1052:1052:1052)) + (PORT datac (1431:1431:1431) (1467:1467:1467)) + (PORT datad (1389:1389:1389) (1443:1443:1443)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1500:1500:1500) (1615:1615:1615)) + (PORT datab (972:972:972) (1051:1051:1051)) + (PORT datac (1456:1456:1456) (1510:1510:1510)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (1480:1480:1480) (1579:1579:1579)) + (PORT datab (1206:1206:1206) (1296:1296:1296)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (1382:1382:1382) (1396:1396:1396)) + (PORT datab (885:885:885) (963:963:963)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1346:1346:1346) (1371:1371:1371)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~102) + (DELAY + (ABSOLUTE + (PORT datac (191:191:191) (224:224:224)) + (PORT datad (781:781:781) (792:792:792)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (1025:1025:1025)) + (PORT datab (229:229:229) (272:272:272)) + (PORT datac (239:239:239) (287:287:287)) + (PORT datad (858:858:858) (899:899:899)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (1164:1164:1164) (1192:1192:1192)) + (PORT datac (942:942:942) (1003:1003:1003)) + (PORT datad (367:367:367) (390:390:390)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (267:267:267) (355:355:355)) + (PORT datab (711:711:711) (731:731:731)) + (PORT datac (879:879:879) (883:883:883)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (546:546:546) (581:581:581)) + (PORT clrn (1579:1579:1579) (1558:1558:1558)) + (PORT ena (1501:1501:1501) (1488:1488:1488)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (814:814:814)) + (PORT datab (1235:1235:1235) (1355:1355:1355)) + (PORT datac (985:985:985) (1064:1064:1064)) + (PORT datad (1322:1322:1322) (1437:1437:1437)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (756:756:756)) + (PORT datab (994:994:994) (1104:1104:1104)) + (PORT datac (1148:1148:1148) (1191:1191:1191)) + (PORT datad (1194:1194:1194) (1254:1254:1254)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (717:717:717) (780:780:780)) + (PORT datab (376:376:376) (417:417:417)) + (PORT datac (1100:1100:1100) (1123:1123:1123)) + (PORT datad (1740:1740:1740) (1811:1811:1811)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (999:999:999) (1037:1037:1037)) + (PORT datab (1148:1148:1148) (1181:1181:1181)) + (PORT datac (1118:1118:1118) (1156:1156:1156)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1747:1747:1747) (1768:1768:1768)) + (PORT datab (1063:1063:1063) (1181:1181:1181)) + (PORT datac (1205:1205:1205) (1277:1277:1277)) + (PORT datad (1152:1152:1152) (1188:1188:1188)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1745:1745:1745) (1764:1764:1764)) + (PORT datab (372:372:372) (420:420:420)) + (PORT datac (1499:1499:1499) (1632:1632:1632)) + (PORT datad (1111:1111:1111) (1140:1140:1140)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (279:279:279)) + (PORT datab (1037:1037:1037) (1088:1088:1088)) + (PORT datac (1095:1095:1095) (1134:1134:1134)) + (PORT datad (1073:1073:1073) (1110:1110:1110)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (904:904:904)) + (PORT datab (1509:1509:1509) (1569:1569:1569)) + (PORT datac (829:829:829) (848:848:848)) + (PORT datad (860:860:860) (875:875:875)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT datac (1078:1078:1078) (1174:1174:1174)) + (PORT datad (1031:1031:1031) (1116:1116:1116)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (436:436:436)) + (PORT datab (968:968:968) (1056:1056:1056)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (280:280:280)) + (PORT datab (775:775:775) (874:874:874)) + (PORT datac (1366:1366:1366) (1453:1453:1453)) + (PORT datad (1546:1546:1546) (1637:1637:1637)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (379:379:379)) + (PORT datab (222:222:222) (260:260:260)) + (PORT datad (739:739:739) (824:824:824)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (2308:2308:2308) (2488:2488:2488)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datac (574:574:574) (621:621:621)) + (PORT datad (1325:1325:1325) (1345:1345:1345)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (965:965:965) (1048:1048:1048)) + (PORT datad (728:728:728) (839:839:839)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (622:622:622) (672:672:672)) + (PORT datad (961:961:961) (1040:1040:1040)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (568:568:568)) + (PORT datab (664:664:664) (740:740:740)) + (PORT datac (606:606:606) (671:671:671)) + (PORT datad (721:721:721) (799:799:799)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~131) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (538:538:538)) + (PORT datab (342:342:342) (377:377:377)) + (PORT datad (260:260:260) (338:338:338)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (908:908:908)) + (PORT datab (1091:1091:1091) (1095:1095:1095)) + (PORT datad (617:617:617) (636:636:636)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1224:1224:1224)) + (PORT datab (240:240:240) (321:321:321)) + (PORT datac (568:568:568) (626:626:626)) + (PORT datad (553:553:553) (572:572:572)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT datac (1077:1077:1077) (1170:1170:1170)) + (PORT datad (1031:1031:1031) (1112:1112:1112)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (285:285:285)) + (PORT datab (390:390:390) (410:410:410)) + (PORT datac (918:918:918) (988:988:988)) + (PORT datad (328:328:328) (348:348:348)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT datab (969:969:969) (1059:1059:1059)) + (PORT datad (338:338:338) (357:357:357)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (439:439:439)) + (PORT datab (969:969:969) (1059:1059:1059)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datac (559:559:559) (587:587:587)) + (PORT datad (556:556:556) (572:572:572)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1040:1040:1040)) + (PORT datab (793:793:793) (911:911:911)) + (PORT datac (907:907:907) (1000:1000:1000)) + (PORT datad (764:764:764) (871:871:871)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (395:395:395)) + (PORT datab (737:737:737) (825:825:825)) + (PORT datad (589:589:589) (600:600:600)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (262:262:262)) + (PORT datab (201:201:201) (241:241:241)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT datac (244:244:244) (324:324:324)) + (PORT datad (831:831:831) (879:879:879)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (764:764:764)) + (PORT datab (349:349:349) (382:382:382)) + (PORT datac (658:658:658) (727:727:727)) + (PORT datad (638:638:638) (705:705:705)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (471:471:471) (546:546:546)) + (PORT datac (352:352:352) (381:381:381)) + (PORT datad (197:197:197) (232:232:232)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (824:824:824)) + (PORT datab (493:493:493) (577:577:577)) + (PORT datac (572:572:572) (608:608:608)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (849:849:849)) + (PORT datab (773:773:773) (872:872:872)) + (PORT datad (959:959:959) (1036:1036:1036)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (370:370:370)) + (PORT datad (635:635:635) (675:675:675)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1664:1664:1664) (1689:1689:1689)) + (PORT datab (618:618:618) (678:678:678)) + (PORT datac (1058:1058:1058) (1128:1128:1128)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (634:634:634) (655:655:655)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (589:589:589) (603:603:603)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~104) + (DELAY + (ABSOLUTE + (PORT datab (1233:1233:1233) (1299:1299:1299)) + (PORT datac (655:655:655) (738:738:738)) + (PORT datad (1395:1395:1395) (1412:1412:1412)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (947:947:947) (974:974:974)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1333:1333:1333) (1379:1379:1379)) + (PORT d[1] (1965:1965:1965) (2168:2168:2168)) + (PORT d[2] (3064:3064:3064) (3182:3182:3182)) + (PORT d[3] (2837:2837:2837) (3038:3038:3038)) + (PORT d[4] (2548:2548:2548) (2738:2738:2738)) + (PORT d[5] (2841:2841:2841) (3039:3039:3039)) + (PORT d[6] (1923:1923:1923) (2045:2045:2045)) + (PORT d[7] (2590:2590:2590) (2742:2742:2742)) + (PORT d[8] (3415:3415:3415) (3712:3712:3712)) + (PORT d[9] (1607:1607:1607) (1686:1686:1686)) + (PORT d[10] (5088:5088:5088) (5355:5355:5355)) + (PORT d[11] (1909:1909:1909) (2057:2057:2057)) + (PORT d[12] (1909:1909:1909) (2032:2032:2032)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1221:1221:1221) (1217:1217:1217)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (2517:2517:2517) (2474:2474:2474)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1836:1836:1836)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (704:704:704) (727:727:727)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1274:1274:1274) (1301:1301:1301)) + (PORT d[1] (2099:2099:2099) (2330:2330:2330)) + (PORT d[2] (1248:1248:1248) (1286:1286:1286)) + (PORT d[3] (1307:1307:1307) (1357:1357:1357)) + (PORT d[4] (2610:2610:2610) (2833:2833:2833)) + (PORT d[5] (3471:3471:3471) (3676:3676:3676)) + (PORT d[6] (1323:1323:1323) (1420:1420:1420)) + (PORT d[7] (2887:2887:2887) (3061:3061:3061)) + (PORT d[8] (985:985:985) (1023:1023:1023)) + (PORT d[9] (1296:1296:1296) (1359:1359:1359)) + (PORT d[10] (1357:1357:1357) (1455:1455:1455)) + (PORT d[11] (2476:2476:2476) (2609:2609:2609)) + (PORT d[12] (1610:1610:1610) (1711:1711:1711)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (979:979:979) (953:953:953)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT d[0] (1492:1492:1492) (1460:1460:1460)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (947:947:947) (973:973:973)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1343:1343:1343) (1413:1413:1413)) + (PORT d[1] (3163:3163:3163) (3436:3436:3436)) + (PORT d[2] (3532:3532:3532) (3625:3625:3625)) + (PORT d[3] (2837:2837:2837) (3043:3043:3043)) + (PORT d[4] (2558:2558:2558) (2781:2781:2781)) + (PORT d[5] (2869:2869:2869) (3072:3072:3072)) + (PORT d[6] (1676:1676:1676) (1759:1759:1759)) + (PORT d[7] (1505:1505:1505) (1586:1586:1586)) + (PORT d[8] (3442:3442:3442) (3720:3720:3720)) + (PORT d[9] (3231:3231:3231) (3382:3382:3382)) + (PORT d[10] (5089:5089:5089) (5374:5374:5374)) + (PORT d[11] (1942:1942:1942) (2100:2100:2100)) + (PORT d[12] (1901:1901:1901) (2017:2017:2017)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1717:1717:1717) (1648:1648:1648)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2052:2052:2052) (2017:2017:2017)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1152:1152:1152) (1168:1168:1168)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3672:3672:3672) (3852:3852:3852)) + (PORT d[1] (1686:1686:1686) (1851:1851:1851)) + (PORT d[2] (1971:1971:1971) (2046:2046:2046)) + (PORT d[3] (2163:2163:2163) (2263:2263:2263)) + (PORT d[4] (2177:2177:2177) (2306:2306:2306)) + (PORT d[5] (1373:1373:1373) (1485:1485:1485)) + (PORT d[6] (1492:1492:1492) (1541:1541:1541)) + (PORT d[7] (1731:1731:1731) (1802:1802:1802)) + (PORT d[8] (3606:3606:3606) (3855:3855:3855)) + (PORT d[9] (3144:3144:3144) (3281:3281:3281)) + (PORT d[10] (3176:3176:3176) (3363:3363:3363)) + (PORT d[11] (2072:2072:2072) (2195:2195:2195)) + (PORT d[12] (1417:1417:1417) (1455:1455:1455)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1662:1662:1662) (1645:1645:1645)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (2686:2686:2686) (2681:2681:2681)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1035:1035:1035)) + (PORT datab (1190:1190:1190) (1238:1238:1238)) + (PORT datac (820:820:820) (836:836:836)) + (PORT datad (1047:1047:1047) (1047:1047:1047)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1168:1168:1168)) + (PORT datab (1602:1602:1602) (1692:1692:1692)) + (PORT datac (1163:1163:1163) (1158:1158:1158)) + (PORT datad (312:312:312) (328:328:328)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3036:3036:3036) (3209:3209:3209)) + (PORT d[1] (2901:2901:2901) (3127:3127:3127)) + (PORT d[2] (1663:1663:1663) (1761:1761:1761)) + (PORT d[3] (1512:1512:1512) (1583:1583:1583)) + (PORT d[4] (1858:1858:1858) (1967:1967:1967)) + (PORT d[5] (1341:1341:1341) (1451:1451:1451)) + (PORT d[6] (1141:1141:1141) (1162:1162:1162)) + (PORT d[7] (1474:1474:1474) (1532:1532:1532)) + (PORT d[8] (2472:2472:2472) (2678:2678:2678)) + (PORT d[9] (3827:3827:3827) (3998:3998:3998)) + (PORT d[10] (2576:2576:2576) (2725:2725:2725)) + (PORT d[11] (1801:1801:1801) (1882:1882:1882)) + (PORT d[12] (2041:2041:2041) (2064:2064:2064)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT d[0] (1267:1267:1267) (1274:1274:1274)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1634:1634:1634) (1680:1680:1680)) + (PORT clk (1866:1866:1866) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2598:2598:2598) (2696:2696:2696)) + (PORT d[1] (2070:2070:2070) (2298:2298:2298)) + (PORT d[2] (2574:2574:2574) (2730:2730:2730)) + (PORT d[3] (2266:2266:2266) (2351:2351:2351)) + (PORT d[4] (2949:2949:2949) (3214:3214:3214)) + (PORT d[5] (2088:2088:2088) (2293:2293:2293)) + (PORT d[6] (1571:1571:1571) (1677:1677:1677)) + (PORT d[7] (2825:2825:2825) (2918:2918:2918)) + (PORT d[8] (2797:2797:2797) (3045:3045:3045)) + (PORT d[9] (2076:2076:2076) (2185:2185:2185)) + (PORT d[10] (1851:1851:1851) (1973:1973:1973)) + (PORT d[11] (3686:3686:3686) (3803:3803:3803)) + (PORT d[12] (1884:1884:1884) (1967:1967:1967)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3175:3175:3175) (3145:3145:3145)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT d[0] (2870:2870:2870) (2913:2913:2913)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1867:1867:1867) (1894:1894:1894)) @@ -49556,7 +45987,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1867:1867:1867) (1894:1894:1894)) @@ -49566,7 +45997,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1867:1867:1867) (1894:1894:1894)) @@ -49576,7 +46007,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1867:1867:1867) (1894:1894:1894)) @@ -49586,7 +46017,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1821:1821:1821) (1818:1818:1818)) @@ -49600,10 +46031,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (3429:3429:3429) (3540:3540:3540)) + (PORT d[0] (2160:2160:2160) (2219:2219:2219)) (PORT clk (1831:1831:1831) (1824:1824:1824)) ) ) @@ -49613,22 +46044,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1949:1949:1949) (2016:2016:2016)) - (PORT d[1] (1950:1950:1950) (2044:2044:2044)) - (PORT d[2] (1829:1829:1829) (1895:1895:1895)) - (PORT d[3] (1934:1934:1934) (2094:2094:2094)) - (PORT d[4] (1894:1894:1894) (2013:2013:2013)) - (PORT d[5] (2135:2135:2135) (2220:2220:2220)) - (PORT d[6] (1755:1755:1755) (1823:1823:1823)) - (PORT d[7] (2039:2039:2039) (2156:2156:2156)) - (PORT d[8] (2023:2023:2023) (2092:2092:2092)) - (PORT d[9] (2052:2052:2052) (2088:2088:2088)) - (PORT d[10] (2154:2154:2154) (2264:2264:2264)) - (PORT d[11] (1929:1929:1929) (1995:1995:1995)) - (PORT d[12] (1888:1888:1888) (1961:1961:1961)) + (PORT d[0] (4537:4537:4537) (4504:4504:4504)) + (PORT d[1] (4325:4325:4325) (4356:4356:4356)) + (PORT d[2] (4543:4543:4543) (4609:4609:4609)) + (PORT d[3] (4478:4478:4478) (4499:4499:4499)) + (PORT d[4] (4324:4324:4324) (4305:4305:4305)) + (PORT d[5] (4367:4367:4367) (4410:4410:4410)) + (PORT d[6] (4631:4631:4631) (4697:4697:4697)) + (PORT d[7] (4151:4151:4151) (4116:4116:4116)) + (PORT d[8] (4445:4445:4445) (4476:4476:4476)) + (PORT d[9] (4629:4629:4629) (4823:4823:4823)) + (PORT d[10] (4475:4475:4475) (4482:4482:4482)) + (PORT d[11] (4668:4668:4668) (4671:4671:4671)) + (PORT d[12] (4491:4491:4491) (4515:4515:4515)) (PORT clk (1827:1827:1827) (1820:1820:1820)) ) ) @@ -49638,7 +46069,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1831:1831:1831) (1824:1824:1824)) @@ -49647,7 +46078,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) (DELAY (ABSOLUTE (PORT clk (1832:1832:1832) (1825:1825:1825)) @@ -49657,7 +46088,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1832:1832:1832) (1825:1825:1825)) @@ -49666,7 +46097,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1832:1832:1832) (1825:1825:1825)) @@ -49676,7 +46107,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1832:1832:1832) (1825:1825:1825)) @@ -49684,25 +46115,29 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1345:1345:1345) (1398:1398:1398)) + (PORT datab (279:279:279) (367:367:367)) + (PORT datac (1350:1350:1350) (1376:1376:1376)) + (PORT datad (1465:1465:1465) (1526:1526:1526)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (424:424:424) (453:453:453)) - (PORT d[1] (3375:3375:3375) (3656:3656:3656)) - (PORT d[2] (1906:1906:1906) (1993:1993:1993)) - (PORT d[3] (3983:3983:3983) (4280:4280:4280)) - (PORT d[4] (3107:3107:3107) (3335:3335:3335)) - (PORT d[5] (986:986:986) (1025:1025:1025)) - (PORT d[6] (3210:3210:3210) (3376:3376:3376)) - (PORT d[7] (641:641:641) (660:660:660)) - (PORT d[8] (980:980:980) (1013:1013:1013)) - (PORT d[9] (2712:2712:2712) (2800:2800:2800)) - (PORT d[10] (917:917:917) (948:948:948)) - (PORT d[11] (1477:1477:1477) (1518:1518:1518)) - (PORT d[12] (2076:2076:2076) (2144:2144:2144)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT d[0] (1584:1584:1584) (1645:1645:1645)) + (PORT clk (1870:1870:1870) (1897:1897:1897)) ) ) (TIMINGCHECK @@ -49711,30 +46146,98 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1880:1880:1880)) - (PORT d[0] (2635:2635:2635) (2563:2563:2563)) + (PORT d[0] (2320:2320:2320) (2387:2387:2387)) + (PORT d[1] (2054:2054:2054) (2261:2261:2261)) + (PORT d[2] (2320:2320:2320) (2490:2490:2490)) + (PORT d[3] (2275:2275:2275) (2437:2437:2437)) + (PORT d[4] (2932:2932:2932) (3188:3188:3188)) + (PORT d[5] (2382:2382:2382) (2576:2576:2576)) + (PORT d[6] (1862:1862:1862) (1984:1984:1984)) + (PORT d[7] (2524:2524:2524) (2619:2619:2619)) + (PORT d[8] (3132:3132:3132) (3396:3396:3396)) + (PORT d[9] (1782:1782:1782) (1897:1897:1897)) + (PORT d[10] (1810:1810:1810) (1908:1908:1908)) + (PORT d[11] (2927:2927:2927) (3048:3048:3048)) + (PORT d[12] (1876:1876:1876) (1989:1989:1989)) + (PORT clk (1867:1867:1867) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2203:2203:2203) (2195:2195:2195)) + (PORT clk (1867:1867:1867) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1897:1897:1897)) + (PORT d[0] (3171:3171:3171) (3110:3110:3110)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1881:1881:1881)) + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1898:1898:1898)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1822:1822:1822)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -49745,49 +46248,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1903:1903:1903) (2034:2034:2034)) - (PORT clk (1870:1870:1870) (1896:1896:1896)) + (PORT d[0] (2476:2476:2476) (2528:2528:2528)) + (PORT clk (1835:1835:1835) (1828:1828:1828)) ) ) (TIMINGCHECK @@ -49796,23 +46261,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2976:2976:2976) (3123:3123:3123)) - (PORT d[1] (1703:1703:1703) (1797:1797:1797)) - (PORT d[2] (3298:3298:3298) (3581:3581:3581)) - (PORT d[3] (2372:2372:2372) (2600:2600:2600)) - (PORT d[4] (2598:2598:2598) (2803:2803:2803)) - (PORT d[5] (2115:2115:2115) (2261:2261:2261)) - (PORT d[6] (2340:2340:2340) (2474:2474:2474)) - (PORT d[7] (2932:2932:2932) (3093:3093:3093)) - (PORT d[8] (2409:2409:2409) (2501:2501:2501)) - (PORT d[9] (3781:3781:3781) (3903:3903:3903)) - (PORT d[10] (2538:2538:2538) (2614:2614:2614)) - (PORT d[11] (2716:2716:2716) (2930:2930:2930)) - (PORT d[12] (3375:3375:3375) (3524:3524:3524)) - (PORT clk (1867:1867:1867) (1892:1892:1892)) + (PORT d[0] (4504:4504:4504) (4508:4508:4508)) + (PORT d[1] (4109:4109:4109) (4118:4118:4118)) + (PORT d[2] (4505:4505:4505) (4547:4547:4547)) + (PORT d[3] (4566:4566:4566) (4624:4624:4624)) + (PORT d[4] (4563:4563:4563) (4541:4541:4541)) + (PORT d[5] (4668:4668:4668) (4705:4705:4705)) + (PORT d[6] (4650:4650:4650) (4703:4703:4703)) + (PORT d[7] (4197:4197:4197) (4161:4161:4161)) + (PORT d[8] (4693:4693:4693) (4743:4743:4743)) + (PORT d[9] (4535:4535:4535) (4748:4748:4748)) + (PORT d[10] (4537:4537:4537) (4522:4522:4522)) + (PORT d[11] (4499:4499:4499) (4551:4551:4551)) + (PORT d[12] (4595:4595:4595) (4623:4623:4623)) + (PORT clk (1831:1831:1831) (1824:1824:1824)) ) ) (TIMINGCHECK @@ -49821,174 +46286,59 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (2067:2067:2067) (2070:2070:2070)) - (PORT clk (1867:1867:1867) (1892:1892:1892)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (PORT d[0] (3206:3206:3206) (3169:3169:3169)) + (PORT clk (1835:1835:1835) (1828:1828:1828)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1897:1897:1897)) + (PORT clk (1836:1836:1836) (1829:1829:1829)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1897:1897:1897)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1897:1897:1897)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1897:1897:1897)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1821:1821:1821)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3725:3725:3725) (3850:3850:3850)) - (PORT clk (1835:1835:1835) (1827:1827:1827)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1839:1839:1839) (1917:1917:1917)) - (PORT d[1] (1961:1961:1961) (2072:2072:2072)) - (PORT d[2] (2074:2074:2074) (2142:2142:2142)) - (PORT d[3] (1947:1947:1947) (2126:2126:2126)) - (PORT d[4] (1875:1875:1875) (1962:1962:1962)) - (PORT d[5] (1775:1775:1775) (1833:1833:1833)) - (PORT d[6] (2014:2014:2014) (2076:2076:2076)) - (PORT d[7] (1854:1854:1854) (1907:1907:1907)) - (PORT d[8] (2056:2056:2056) (2126:2126:2126)) - (PORT d[9] (1989:1989:1989) (2064:2064:2064)) - (PORT d[10] (2172:2172:2172) (2280:2280:2280)) - (PORT d[11] (2069:2069:2069) (2130:2130:2130)) - (PORT d[12] (2178:2178:2178) (2308:2308:2308)) - (PORT clk (1831:1831:1831) (1823:1823:1823)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1828:1828:1828)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1828:1828:1828)) + (PORT clk (1836:1836:1836) (1829:1829:1829)) (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1836:1836:1836) (1828:1828:1828)) + (PORT clk (1836:1836:1836) (1829:1829:1829)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1836:1836:1836) (1828:1828:1828)) + (PORT clk (1836:1836:1836) (1829:1829:1829)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1827:1827:1827) (1823:1823:1823)) + (PORT clk (1827:1827:1827) (1824:1824:1824)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -49998,14 +46348,111 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~0) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) (DELAY (ABSOLUTE - (PORT dataa (972:972:972) (1025:1025:1025)) - (PORT datab (587:587:587) (595:595:595)) - (PORT datac (928:928:928) (995:995:995)) - (PORT datad (1404:1404:1404) (1448:1448:1448)) + (PORT d[0] (987:987:987) (1035:1035:1035)) + (PORT d[1] (989:989:989) (1045:1045:1045)) + (PORT d[2] (1232:1232:1232) (1248:1248:1248)) + (PORT d[3] (1325:1325:1325) (1386:1386:1386)) + (PORT d[4] (2598:2598:2598) (2808:2808:2808)) + (PORT d[5] (2981:2981:2981) (3208:3208:3208)) + (PORT d[6] (983:983:983) (1027:1027:1027)) + (PORT d[7] (1279:1279:1279) (1356:1356:1356)) + (PORT d[8] (1032:1032:1032) (1055:1055:1055)) + (PORT d[9] (975:975:975) (1020:1020:1020)) + (PORT d[10] (1319:1319:1319) (1384:1384:1384)) + (PORT d[11] (2558:2558:2558) (2742:2742:2742)) + (PORT d[12] (1296:1296:1296) (1368:1368:1368)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (574:574:574) (581:581:581)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1284:1284:1284) (1294:1294:1294)) + (PORT datab (865:865:865) (914:914:914)) + (PORT datac (861:861:861) (866:866:866)) + (PORT datad (181:181:181) (211:211:211)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -50015,15 +46462,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~1) + (INSTANCE D\[2\]\~42) (DELAY (ABSOLUTE - (PORT dataa (960:960:960) (1034:1034:1034)) - (PORT datab (960:960:960) (1021:1021:1021)) - (PORT datac (1633:1633:1633) (1673:1673:1673)) + (PORT dataa (209:209:209) (255:255:255)) + (PORT datab (282:282:282) (370:370:370)) + (PORT datac (1627:1627:1627) (1645:1645:1645)) (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa combout (341:341:341) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (928:928:928) (981:981:981)) + (PORT datac (1193:1193:1193) (1255:1255:1255)) + (PORT datad (572:572:572) (583:583:583)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50031,47 +46494,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~60) + (INSTANCE D\[2\]\~45) (DELAY (ABSOLUTE - (PORT dataa (738:738:738) (809:809:809)) - (PORT datab (1620:1620:1620) (1630:1630:1630)) - (PORT datac (630:630:630) (680:680:680)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (1511:1511:1511) (1587:1587:1587)) - (PORT datab (3323:3323:3323) (3556:3556:3556)) - (PORT datac (1800:1800:1800) (1925:1925:1925)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (365:365:365) (410:410:410)) + (PORT datab (234:234:234) (278:278:278)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (338:338:338) (358:358:358)) - (PORT datad (701:701:701) (766:766:766)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50079,15 +46510,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~79) + (INSTANCE D\[2\]\~46) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (654:654:654)) - (PORT datab (262:262:262) (343:343:343)) - (PORT datac (665:665:665) (703:703:703)) - (PORT datad (1174:1174:1174) (1248:1248:1248)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (415:415:415) (501:501:501)) + (PORT datab (234:234:234) (278:278:278)) + (PORT datac (1139:1139:1139) (1183:1183:1183)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50095,12 +46526,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) (DELAY (ABSOLUTE - (PORT dataa (1346:1346:1346) (1423:1423:1423)) - (PORT datab (1270:1270:1270) (1356:1356:1356)) - (PORT datac (874:874:874) (907:907:907)) + (PORT dataa (978:978:978) (1031:1031:1031)) + (PORT datab (648:648:648) (673:673:673)) + (PORT datac (597:597:597) (612:612:612)) (PORT datad (194:194:194) (219:219:219)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (342:342:342) (342:342:342)) @@ -50111,12 +46542,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[4\]) + (INSTANCE z80_\|data_pins_\|dout\[2\]) (DELAY (ABSOLUTE - (PORT clk (1544:1544:1544) (1545:1545:1545)) + (PORT clk (1525:1525:1525) (1530:1530:1530)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1687:1687:1687) (1687:1687:1687)) + (PORT ena (1245:1245:1245) (1226:1226:1226)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -50127,29 +46558,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (INSTANCE z80_\|bus_control_\|db\[2\]\~12) (DELAY (ABSOLUTE - (PORT dataa (690:690:690) (723:723:723)) - (PORT datac (935:935:935) (1006:1006:1006)) - (PORT datad (1018:1018:1018) (1052:1052:1052)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (920:920:920) (962:962:962)) + (PORT datac (944:944:944) (990:990:990)) + (PORT datad (218:218:218) (253:253:253)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~19) + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) (DELAY (ABSOLUTE - (PORT dataa (1247:1247:1247) (1318:1318:1318)) - (PORT datab (405:405:405) (429:429:429)) - (PORT datac (609:609:609) (655:655:655)) + (PORT dataa (439:439:439) (507:507:507)) + (PORT datab (236:236:236) (280:280:280)) + (PORT datac (225:225:225) (274:274:274)) (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50157,13 +46588,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[4\]) + (INSTANCE z80_\|ir_\|opcode\[2\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1551:1551:1551)) - (PORT ena (1886:1886:1886) (1862:1862:1862)) + (PORT clrn (1577:1577:1577) (1557:1557:1557)) + (PORT ena (1231:1231:1231) (1217:1217:1217)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50175,13 +46606,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (INSTANCE z80_\|pla_decode_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT datab (997:997:997) (1067:1067:1067)) - (PORT datac (964:964:964) (1046:1046:1046)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (1460:1460:1460) (1533:1533:1533)) + (PORT datad (2264:2264:2264) (2327:2327:2327)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -50190,10 +46621,10 @@ (INSTANCE z80_\|pla_decode_\|Equal43\~0) (DELAY (ABSOLUTE - (PORT dataa (1131:1131:1131) (1155:1155:1155)) - (PORT datab (945:945:945) (984:984:984)) - (PORT datac (2031:2031:2031) (2073:2073:2073)) - (PORT datad (1149:1149:1149) (1168:1168:1168)) + (PORT dataa (944:944:944) (975:975:975)) + (PORT datab (940:940:940) (997:997:997)) + (PORT datac (1637:1637:1637) (1758:1758:1758)) + (PORT datad (1220:1220:1220) (1303:1303:1303)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -50206,9 +46637,9 @@ (INSTANCE z80_\|interrupts_\|test1\~2) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (193:193:193) (226:226:226)) + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (198:198:198) (235:235:235)) (PORT datad (195:195:195) (220:220:220)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) @@ -50222,13 +46653,13 @@ (INSTANCE z80_\|interrupts_\|test1\~3) (DELAY (ABSOLUTE - (PORT dataa (1541:1541:1541) (1599:1599:1599)) - (PORT datab (221:221:221) (259:259:259)) - (PORT datac (929:929:929) (980:980:980)) - (PORT datad (813:813:813) (828:828:828)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (845:845:845) (859:859:859)) + (PORT datab (2054:2054:2054) (2187:2187:2187)) + (PORT datac (1260:1260:1260) (1358:1358:1358)) + (PORT datad (1087:1087:1087) (1084:1084:1084)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50238,10 +46669,10 @@ (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1550:1550:1550)) + (PORT clk (1533:1533:1533) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) - (PORT ena (957:957:957) (955:955:955)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (1669:1669:1669) (1678:1678:1678)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50256,10 +46687,10 @@ (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (462:462:462)) - (PORT datab (927:927:927) (990:990:990)) - (PORT datac (886:886:886) (946:946:946)) - (PORT datad (284:284:284) (370:370:370)) + (PORT dataa (1217:1217:1217) (1308:1308:1308)) + (PORT datab (2052:2052:2052) (2184:2184:2184)) + (PORT datac (1270:1270:1270) (1384:1384:1384)) + (PORT datad (1880:1880:1880) (1934:1934:1934)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -50272,9 +46703,9 @@ (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1550:1550:1550)) + (PORT clk (1528:1528:1528) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1556:1556:1556)) + (PORT clrn (1587:1587:1587) (1563:1563:1563)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50288,8 +46719,8 @@ (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) (DELAY (ABSOLUTE - (PORT datab (876:876:876) (933:933:933)) - (PORT datad (222:222:222) (294:294:294)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datad (226:226:226) (299:299:299)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50300,10 +46731,10 @@ (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1540:1540:1540) (1556:1556:1556)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT ena (1939:1939:1939) (2030:2030:2030)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50318,10 +46749,10 @@ (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT datab (277:277:277) (363:363:363)) - (PORT datac (883:883:883) (919:919:919)) - (PORT datad (861:861:861) (914:914:914)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (267:267:267) (353:353:353)) + (PORT datac (1094:1094:1094) (1135:1135:1135)) + (PORT datad (1105:1105:1105) (1151:1151:1151)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50332,10 +46763,10 @@ (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1540:1540:1540) (1556:1556:1556)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT ena (1939:1939:1939) (2030:2030:2030)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50347,276 +46778,40 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (INSTANCE z80_\|resets_\|x3) (DELAY (ABSOLUTE - (PORT dataa (931:931:931) (976:976:976)) - (PORT datac (238:238:238) (316:316:316)) - (PORT datad (854:854:854) (913:913:913)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (273:273:273) (359:359:359)) - (PORT datac (896:896:896) (930:930:930)) - (PORT datad (857:857:857) (909:909:909)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1409:1409:1409) (1502:1502:1502)) - (PORT datac (1130:1130:1130) (1238:1238:1238)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (2393:2393:2393) (2551:2551:2551)) + (PORT datac (239:239:239) (317:317:317)) + (PORT datad (1364:1364:1364) (1506:1506:1506)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (553:553:553)) - (PORT datad (1353:1353:1353) (1343:1343:1343)) - (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) (DELAY (ABSOLUTE - (PORT dataa (237:237:237) (286:286:286)) - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (1692:1692:1692) (1732:1732:1732)) - (PORT datad (178:178:178) (207:207:207)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1883:1883:1883) (1869:1869:1869)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) (DELAY (ABSOLUTE - (PORT dataa (1187:1187:1187) (1211:1211:1211)) - (PORT datab (870:870:870) (913:913:913)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (804:804:804) (825:825:825)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (615:615:615)) - (PORT datab (1663:1663:1663) (1686:1686:1686)) - (PORT datac (1608:1608:1608) (1632:1632:1632)) - (PORT datad (1862:1862:1862) (1982:1982:1982)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1136:1136:1136)) - (PORT datab (895:895:895) (913:913:913)) - (PORT datac (770:770:770) (789:789:789)) - (PORT datad (1882:1882:1882) (1828:1828:1828)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT datab (1254:1254:1254) (1252:1252:1252)) - (PORT datac (1022:1022:1022) (1023:1023:1023)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (708:708:708)) - (PORT datab (662:662:662) (729:729:729)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (594:594:594) (623:623:623)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (273:273:273)) - (PORT datab (976:976:976) (1004:1004:1004)) - (PORT datac (200:200:200) (235:235:235)) - (PORT datad (225:225:225) (263:263:263)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (707:707:707)) - (PORT datab (1012:1012:1012) (1035:1035:1035)) - (PORT datac (1134:1134:1134) (1176:1176:1176)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1171:1171:1171) (1215:1215:1215)) - (PORT datab (1172:1172:1172) (1200:1200:1200)) - (PORT datac (808:808:808) (841:841:841)) - (PORT datad (1013:1013:1013) (1037:1037:1037)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (615:615:615) (675:675:675)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (628:628:628)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (822:822:822) (850:850:850)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (983:983:983)) - (PORT datad (855:855:855) (904:904:904)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT inclk[0] (1583:1583:1583) (1637:1637:1637)) ) ) ) @@ -50625,9 +46820,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1540:1540:1540) (1556:1556:1556)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50636,600 +46831,14 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT dataa (268:268:268) (355:355:355)) - (PORT datac (882:882:882) (925:925:925)) - (PORT datad (861:861:861) (912:912:912)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1342:1342:1342)) - (PORT datab (1341:1341:1341) (1354:1354:1354)) - (PORT datad (1140:1140:1140) (1170:1170:1170)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1309:1309:1309) (1308:1308:1308)) - (PORT datab (1370:1370:1370) (1434:1434:1434)) - (PORT datac (1021:1021:1021) (1027:1027:1027)) - (PORT datad (863:863:863) (907:907:907)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (883:883:883) (896:896:896)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (908:908:908) (954:954:954)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (669:669:669)) - (PORT datab (228:228:228) (269:269:269)) - (PORT datac (1182:1182:1182) (1214:1214:1214)) - (PORT datad (1533:1533:1533) (1549:1549:1549)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1250:1250:1250) (1287:1287:1287)) - (PORT datab (1336:1336:1336) (1389:1389:1389)) - (PORT datac (623:623:623) (646:646:646)) - (PORT datad (827:827:827) (852:852:852)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) - (DELAY - (ABSOLUTE - (PORT datab (972:972:972) (967:967:967)) - (PORT datac (1002:1002:1002) (1017:1017:1017)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) - (DELAY - (ABSOLUTE - (PORT dataa (772:772:772) (799:799:799)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (719:719:719) (715:715:715)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (864:864:864) (878:878:878)) - (PORT datac (641:641:641) (686:686:686)) - (PORT datad (1029:1029:1029) (1042:1042:1042)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (915:915:915)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1422:1422:1422) (1502:1502:1502)) - (PORT datab (1610:1610:1610) (1646:1646:1646)) - (PORT datac (1843:1843:1843) (1922:1922:1922)) - (PORT datad (1856:1856:1856) (1977:1977:1977)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1402:1402:1402) (1424:1424:1424)) - (PORT datab (910:910:910) (915:915:915)) - (PORT datac (1353:1353:1353) (1395:1395:1395)) - (PORT datad (884:884:884) (921:921:921)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1026:1026:1026) (1045:1045:1045)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (547:547:547) (561:561:561)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (709:709:709)) - (PORT datab (1068:1068:1068) (1131:1131:1131)) - (PORT datac (898:898:898) (964:964:964)) - (PORT datad (894:894:894) (928:928:928)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (270:270:270)) - (PORT datac (554:554:554) (562:562:562)) - (PORT datad (1116:1116:1116) (1165:1165:1165)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (870:870:870)) - (PORT datab (1318:1318:1318) (1363:1363:1363)) - (PORT datac (1109:1109:1109) (1133:1133:1133)) - (PORT datad (773:773:773) (782:782:782)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (212:212:212) (255:255:255)) - (PORT datac (647:647:647) (705:705:705)) - (PORT datad (1344:1344:1344) (1385:1385:1385)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1183:1183:1183) (1208:1208:1208)) - (PORT datab (1054:1054:1054) (1081:1081:1081)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (768:768:768) (780:780:780)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (877:877:877)) - (PORT datab (630:630:630) (686:686:686)) - (PORT datac (1037:1037:1037) (1054:1054:1054)) - (PORT datad (1882:1882:1882) (1827:1827:1827)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1205:1205:1205)) - (PORT datab (1090:1090:1090) (1109:1109:1109)) - (PORT datac (1964:1964:1964) (2005:2005:2005)) - (PORT datad (328:328:328) (351:351:351)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1348:1348:1348)) - (PORT datab (1154:1154:1154) (1232:1232:1232)) - (PORT datac (589:589:589) (640:640:640)) - (PORT datad (221:221:221) (291:291:291)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (1411:1411:1411) (1487:1487:1487)) - (PORT datab (968:968:968) (1045:1045:1045)) - (PORT datac (1266:1266:1266) (1241:1241:1241)) - (PORT datad (963:963:963) (1058:1058:1058)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1611:1611:1611) (1623:1623:1623)) - (PORT datab (922:922:922) (982:982:982)) - (PORT datac (841:841:841) (859:859:859)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (898:898:898)) - (PORT datab (262:262:262) (344:344:344)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (1067:1067:1067) (1075:1075:1075)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (263:263:263)) - (PORT datab (926:926:926) (990:990:990)) - (PORT datac (1335:1335:1335) (1386:1386:1386)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1038:1038:1038) (1038:1038:1038)) - (PORT datab (1021:1021:1021) (1074:1074:1074)) - (PORT datac (1715:1715:1715) (1807:1807:1807)) - (PORT datad (597:597:597) (612:612:612)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (684:684:684)) - (PORT datab (1188:1188:1188) (1238:1238:1238)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (1119:1119:1119) (1190:1190:1190)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1049:1049:1049) (1082:1082:1082)) - (PORT datab (1085:1085:1085) (1123:1123:1123)) - (PORT datac (1021:1021:1021) (1066:1066:1066)) - (PORT datad (824:824:824) (853:853:853)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~29) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (675:675:675)) - (PORT datab (1287:1287:1287) (1297:1297:1297)) - (PORT datac (555:555:555) (561:561:561)) - (PORT datad (541:541:541) (557:557:557)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (576:576:576)) - (PORT datab (977:977:977) (1055:1055:1055)) - (PORT datac (199:199:199) (235:235:235)) - (PORT datad (1036:1036:1036) (1046:1046:1046)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~34) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (834:834:834) (874:874:874)) - (PORT datac (537:537:537) (552:552:552)) - (PORT datad (839:839:839) (849:849:849)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~54) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (931:931:931)) - (PORT datab (1157:1157:1157) (1200:1200:1200)) - (PORT datac (1374:1374:1374) (1450:1450:1450)) - (PORT datad (1324:1324:1324) (1390:1390:1390)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1325:1325:1325)) - (PORT datab (874:874:874) (931:931:931)) - (PORT datac (1018:1018:1018) (1026:1026:1026)) - (PORT datad (846:846:846) (851:851:851)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (925:925:925)) - (PORT datab (555:555:555) (568:568:568)) - (PORT datac (982:982:982) (1004:1004:1004)) - (PORT datad (1050:1050:1050) (1102:1102:1102)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~35) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1353:1353:1353) (1420:1420:1420)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (308:308:308) (335:335:335)) - (PORT datad (783:783:783) (795:795:795)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (929:929:929) (968:968:968)) + (PORT dataa (1130:1130:1130) (1176:1176:1176)) (PORT datab (283:283:283) (372:372:372)) - (PORT datad (861:861:861) (911:911:911)) + (PORT datad (1106:1106:1106) (1160:1160:1160)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -51242,9 +46851,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1540:1540:1540) (1556:1556:1556)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51255,11 +46864,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) + (INSTANCE z80_\|execute_\|ctl_mWrite\~3) (DELAY (ABSOLUTE - (PORT datac (683:683:683) (788:788:788)) - (PORT datad (1012:1012:1012) (1098:1098:1098)) + (PORT datac (1051:1051:1051) (1164:1164:1164)) + (PORT datad (2030:2030:2030) (2123:2123:2123)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51267,15 +46876,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (INSTANCE z80_\|execute_\|nextM\~11) (DELAY (ABSOLUTE - (PORT dataa (681:681:681) (742:742:742)) - (PORT datab (1618:1618:1618) (1623:1623:1623)) - (PORT datac (1777:1777:1777) (1813:1813:1813)) - (PORT datad (1040:1040:1040) (1060:1060:1060)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (1463:1463:1463) (1520:1520:1520)) + (PORT datab (853:853:853) (881:881:881)) + (PORT datac (791:791:791) (801:801:801)) + (PORT datad (672:672:672) (691:691:691)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51283,13 +46892,719 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (INSTANCE z80_\|execute_\|nextM\~8) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (264:264:264)) - (PORT datab (1755:1755:1755) (1766:1766:1766)) - (PORT datac (813:813:813) (831:831:831)) - (PORT datad (209:209:209) (241:241:241)) + (PORT dataa (996:996:996) (1076:1076:1076)) + (PORT datab (661:661:661) (685:685:685)) + (PORT datac (956:956:956) (1008:1008:1008)) + (PORT datad (2243:2243:2243) (2327:2327:2327)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (910:910:910)) + (PORT datab (847:847:847) (857:857:857)) + (PORT datac (945:945:945) (997:997:997)) + (PORT datad (402:402:402) (435:435:435)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (725:725:725)) + (PORT datab (334:334:334) (363:363:363)) + (PORT datac (1475:1475:1475) (1542:1542:1542)) + (PORT datad (2078:2078:2078) (2128:2128:2128)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (429:429:429)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (2002:2002:2002) (2100:2100:2100)) + (PORT datab (880:880:880) (891:891:891)) + (PORT datac (1448:1448:1448) (1504:1504:1504)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (277:277:277)) + (PORT datab (236:236:236) (281:281:281)) + (PORT datac (354:354:354) (382:382:382)) + (PORT datad (1061:1061:1061) (1062:1062:1062)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (279:279:279)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (989:989:989) (1043:1043:1043)) + (PORT datad (780:780:780) (803:803:803)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT datab (1104:1104:1104) (1138:1138:1138)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (316:316:316) (336:336:336)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT datac (766:766:766) (771:771:771)) + (PORT datad (608:608:608) (623:623:623)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~5) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (252:252:252)) + (PORT datab (2053:2053:2053) (2084:2084:2084)) + (PORT datac (618:618:618) (675:675:675)) + (PORT datad (334:334:334) (341:341:341)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (843:843:843)) + (PORT datab (877:877:877) (909:909:909)) + (PORT datac (1022:1022:1022) (1035:1035:1035)) + (PORT datad (538:538:538) (551:551:551)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT datab (273:273:273) (358:358:358)) + (PORT datac (1093:1093:1093) (1130:1130:1130)) + (PORT datad (1107:1107:1107) (1155:1155:1155)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT ena (1939:1939:1939) (2030:2030:2030)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (1123:1123:1123) (1157:1157:1157)) + (PORT datac (246:246:246) (327:327:327)) + (PORT datad (1110:1110:1110) (1159:1159:1159)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT ena (1939:1939:1939) (2030:2030:2030)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT datab (265:265:265) (348:348:348)) + (PORT datac (1077:1077:1077) (1114:1114:1114)) + (PORT datad (1111:1111:1111) (1161:1161:1161)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT ena (1939:1939:1939) (2030:2030:2030)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (637:637:637)) + (PORT datab (872:872:872) (895:895:895)) + (PORT datac (589:589:589) (612:612:612)) + (PORT datad (914:914:914) (960:960:960)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal77\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1115:1115:1115)) + (PORT datab (1187:1187:1187) (1258:1258:1258)) + (PORT datac (655:655:655) (715:715:715)) + (PORT datad (1245:1245:1245) (1328:1328:1328)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (719:719:719)) + (PORT datab (1671:1671:1671) (1704:1704:1704)) + (PORT datac (864:864:864) (890:890:890)) + (PORT datad (857:857:857) (896:896:896)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~14) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (631:631:631) (681:681:681)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~41) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (442:442:442)) + (PORT datac (1069:1069:1069) (1104:1104:1104)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (992:992:992)) + (PORT datab (1106:1106:1106) (1172:1172:1172)) + (PORT datac (411:411:411) (452:452:452)) + (PORT datad (2503:2503:2503) (2629:2629:2629)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT dataa (2006:2006:2006) (2147:2147:2147)) + (PORT datab (771:771:771) (831:831:831)) + (PORT datac (960:960:960) (989:989:989)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (941:941:941)) + (PORT datab (355:355:355) (391:391:391)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (759:759:759) (760:760:760)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (403:403:403)) + (PORT datab (1048:1048:1048) (1080:1080:1080)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (1303:1303:1303) (1325:1325:1325)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1188:1188:1188)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (200:200:200) (237:237:237)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (871:871:871)) + (PORT datab (1589:1589:1589) (1720:1720:1720)) + (PORT datac (636:636:636) (653:653:653)) + (PORT datad (1694:1694:1694) (1790:1790:1790)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~7) + (DELAY + (ABSOLUTE + (PORT datab (867:867:867) (913:913:913)) + (PORT datac (893:893:893) (946:946:946)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1439:1439:1439) (1482:1482:1482)) + (PORT datab (885:885:885) (895:895:895)) + (PORT datac (878:878:878) (926:926:926)) + (PORT datad (632:632:632) (642:642:642)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1493:1493:1493) (1600:1600:1600)) + (PORT datab (1951:1951:1951) (2023:2023:2023)) + (PORT datac (1350:1350:1350) (1424:1424:1424)) + (PORT datad (1111:1111:1111) (1134:1134:1134)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (1125:1125:1125) (1164:1164:1164)) + (PORT datac (514:514:514) (525:525:525)) + (PORT datad (639:639:639) (676:676:676)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~11) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1215:1215:1215) (1255:1255:1255)) + (PORT datac (1013:1013:1013) (1058:1058:1058)) + (PORT datad (342:342:342) (364:364:364)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (655:655:655)) + (PORT datab (1046:1046:1046) (1078:1078:1078)) + (PORT datac (2017:2017:2017) (2052:2052:2052)) + (PORT datad (621:621:621) (635:635:635)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (662:662:662)) + (PORT datab (914:914:914) (975:975:975)) + (PORT datac (1817:1817:1817) (1894:1894:1894)) + (PORT datad (898:898:898) (912:912:912)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (403:403:403)) + (PORT datab (1223:1223:1223) (1259:1259:1259)) + (PORT datac (1402:1402:1402) (1465:1465:1465)) + (PORT datad (856:856:856) (854:854:854)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (886:886:886)) + (PORT datab (916:916:916) (944:944:944)) + (PORT datac (906:906:906) (930:930:930)) + (PORT datad (843:843:843) (882:882:882)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (960:960:960)) + (PORT datab (360:360:360) (395:395:395)) + (PORT datac (859:859:859) (902:902:902)) + (PORT datad (1107:1107:1107) (1120:1120:1120)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (602:602:602)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (896:896:896) (935:935:935)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1215:1215:1215)) + (PORT datac (627:627:627) (650:650:650)) + (PORT datad (1592:1592:1592) (1700:1700:1700)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (906:906:906)) + (PORT datab (1566:1566:1566) (1611:1611:1611)) + (PORT datac (868:868:868) (891:891:891)) + (PORT datad (1122:1122:1122) (1151:1151:1151)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (723:723:723)) + (PORT datab (660:660:660) (684:684:684)) + (PORT datac (2018:2018:2018) (1985:1985:1985)) + (PORT datad (954:954:954) (1028:1028:1028)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (643:643:643) (693:693:693)) + (PORT datad (661:661:661) (727:727:727)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~22) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (949:949:949)) + (PORT datab (904:904:904) (924:924:924)) + (PORT datac (888:888:888) (932:932:932)) + (PORT datad (623:623:623) (628:628:628)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1744:1744:1744) (1869:1869:1869)) + (PORT datab (1550:1550:1550) (1688:1688:1688)) + (PORT datac (1209:1209:1209) (1285:1285:1285)) + (PORT datad (1505:1505:1505) (1539:1539:1539)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~53) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (1045:1045:1045)) + (PORT datab (936:936:936) (1009:1009:1009)) + (PORT datac (649:649:649) (669:669:669)) + (PORT datad (1286:1286:1286) (1339:1339:1339)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -51299,30 +47614,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (INSTANCE z80_\|execute_\|setM1\~23) (DELAY (ABSOLUTE - (PORT dataa (876:876:876) (895:895:895)) - (PORT datab (1364:1364:1364) (1423:1423:1423)) - (PORT datac (809:809:809) (826:826:826)) - (PORT datad (1082:1082:1082) (1100:1100:1100)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~37) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (233:233:233) (277:277:277)) - (PORT datac (843:843:843) (853:853:853)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (363:363:363) (396:396:396)) + (PORT datac (1524:1524:1524) (1571:1571:1571)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51331,15 +47630,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~38) + (INSTANCE z80_\|execute_\|setM1\~18) (DELAY (ABSOLUTE - (PORT dataa (1117:1117:1117) (1159:1159:1159)) - (PORT datab (367:367:367) (389:389:389)) - (PORT datac (1299:1299:1299) (1330:1330:1330)) - (PORT datad (825:825:825) (862:862:862)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (372:372:372) (412:412:412)) + (PORT datab (990:990:990) (1020:1020:1020)) + (PORT datac (1523:1523:1523) (1602:1602:1602)) + (PORT datad (193:193:193) (219:219:219)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (644:644:644)) + (PORT datab (693:693:693) (758:758:758)) + (PORT datac (646:646:646) (704:704:704)) + (PORT datad (1320:1320:1320) (1419:1419:1419)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51347,15 +47662,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (INSTANCE z80_\|execute_\|setM1\~20) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (254:254:254)) - (PORT datab (1399:1399:1399) (1452:1452:1452)) - (PORT datac (552:552:552) (581:581:581)) - (PORT datad (1057:1057:1057) (1107:1107:1107)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (625:625:625) (675:675:675)) + (PORT datab (1180:1180:1180) (1218:1218:1218)) + (PORT datac (868:868:868) (922:922:922)) + (PORT datad (604:604:604) (625:625:625)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51363,45 +47678,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (INSTANCE z80_\|execute_\|setM1\~34) (DELAY (ABSOLUTE - (PORT dataa (582:582:582) (619:619:619)) - (PORT datab (1400:1400:1400) (1453:1453:1453)) - (PORT datac (638:638:638) (660:660:660)) - (PORT datad (1283:1283:1283) (1317:1317:1317)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (816:816:816) (843:843:843)) - (PORT datad (820:820:820) (827:827:827)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (813:813:813)) - (PORT datab (818:818:818) (831:831:831)) - (PORT datac (700:700:700) (760:760:760)) - (PORT datad (745:745:745) (752:752:752)) + (PORT dataa (612:612:612) (649:649:649)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (309:309:309) (334:334:334)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -51409,16 +47692,2289 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~52) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (312:312:312) (330:330:330)) + (PORT datad (970:970:970) (1032:1032:1032)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1167:1167:1167)) + (PORT datac (245:245:245) (326:326:326)) + (PORT datad (1111:1111:1111) (1159:1159:1159)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT ena (1939:1939:1939) (2030:2030:2030)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (DELAY + (ABSOLUTE + (PORT datac (984:984:984) (1073:1073:1073)) + (PORT datad (1348:1348:1348) (1490:1490:1490)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (497:497:497)) + (PORT datac (1177:1177:1177) (1261:1261:1261)) + (PORT datad (272:272:272) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (697:697:697)) + (PORT datab (1593:1593:1593) (1628:1628:1628)) + (PORT datad (638:638:638) (679:679:679)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1575:1575:1575) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1049:1049:1049)) + (PORT datab (1153:1153:1153) (1214:1214:1214)) + (PORT datac (671:671:671) (718:718:718)) + (PORT datad (624:624:624) (674:674:674)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1120:1120:1120) (1227:1227:1227)) + (PORT datab (994:994:994) (1058:1058:1058)) + (PORT datac (1165:1165:1165) (1211:1211:1211)) + (PORT datad (879:879:879) (933:933:933)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (432:432:432)) + (PORT datab (689:689:689) (742:742:742)) + (PORT datac (882:882:882) (943:943:943)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (1080:1080:1080) (1100:1100:1100)) + (PORT datad (647:647:647) (663:663:663)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (954:954:954) (979:979:979)) + (PORT datac (638:638:638) (653:653:653)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (309:309:309)) + (PORT datac (944:944:944) (985:985:985)) + (PORT datad (335:335:335) (356:356:356)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (285:285:285)) + (PORT datab (780:780:780) (881:881:881)) + (PORT datac (1368:1368:1368) (1458:1458:1458)) + (PORT datad (562:562:562) (568:568:568)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (659:659:659)) + (PORT datab (733:733:733) (831:831:831)) + (PORT datad (718:718:718) (812:812:812)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (849:849:849)) + (PORT datab (1176:1176:1176) (1266:1266:1266)) + (PORT datac (727:727:727) (821:821:821)) + (PORT datad (735:735:735) (837:837:837)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (208:208:208) (251:251:251)) + (PORT datad (184:184:184) (213:213:213)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1168:1168:1168)) + (PORT datab (1145:1145:1145) (1215:1215:1215)) + (PORT datac (215:215:215) (292:292:292)) + (PORT datad (361:361:361) (417:417:417)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~99) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (873:873:873)) + (PORT datab (729:729:729) (817:817:817)) + (PORT datac (885:885:885) (954:954:954)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (378:378:378)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (735:735:735) (822:822:822)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (850:850:850)) + (PORT datab (987:987:987) (1082:1082:1082)) + (PORT datad (938:938:938) (1011:1011:1011)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (743:743:743) (852:852:852)) + (PORT datab (723:723:723) (826:826:826)) + (PORT datac (1146:1146:1146) (1231:1231:1231)) + (PORT datad (910:910:910) (977:977:977)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~133) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (704:704:704)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (728:728:728) (824:824:824)) + (PORT datad (731:731:731) (831:831:831)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datad (322:322:322) (345:345:345)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (622:622:622)) + (PORT datab (422:422:422) (485:485:485)) + (PORT datac (556:556:556) (585:585:585)) + (PORT datad (616:616:616) (671:671:671)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (816:816:816)) + (PORT datab (729:729:729) (827:827:827)) + (PORT datac (720:720:720) (822:822:822)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (367:367:367) (395:395:395)) + (PORT datad (718:718:718) (814:814:814)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (1414:1414:1414) (1548:1548:1548)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (959:959:959) (1039:1039:1039)) + (PORT datad (204:204:204) (234:234:234)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (817:817:817)) + (PORT datab (665:665:665) (745:745:745)) + (PORT datac (658:658:658) (727:727:727)) + (PORT datad (433:433:433) (505:505:505)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (279:279:279)) + (PORT datab (412:412:412) (492:492:492)) + (PORT datac (628:628:628) (701:701:701)) + (PORT datad (406:406:406) (471:471:471)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~134) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (399:399:399)) + (PORT datab (380:380:380) (403:403:403)) + (PORT datad (833:833:833) (879:879:879)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (824:824:824)) + (PORT datab (602:602:602) (630:630:630)) + (PORT datac (616:616:616) (675:675:675)) + (PORT datad (531:531:531) (537:537:537)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~135) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (827:827:827)) + (PORT datab (274:274:274) (360:360:360)) + (PORT datad (1094:1094:1094) (1148:1148:1148)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (365:365:365) (407:407:407)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (1198:1198:1198) (1264:1264:1264)) + (PORT datac (618:618:618) (676:676:676)) + (PORT datad (777:777:777) (790:790:790)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (877:877:877)) + (PORT datab (222:222:222) (269:269:269)) + (PORT datac (638:638:638) (702:702:702)) + (PORT datad (324:324:324) (344:344:344)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (817:817:817)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (569:569:569) (605:605:605)) + (PORT datad (464:464:464) (535:535:535)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) + (DELAY + (ABSOLUTE + (PORT datab (562:562:562) (582:582:582)) + (PORT datad (867:867:867) (872:872:872)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1568:1568:1568) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (820:820:820)) + (PORT datab (654:654:654) (726:726:726)) + (PORT datac (638:638:638) (703:703:703)) + (PORT datad (802:802:802) (842:842:842)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (822:822:822)) + (PORT datab (225:225:225) (273:273:273)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (638:638:638) (709:709:709)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~137) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (821:821:821)) + (PORT datab (334:334:334) (362:362:362)) + (PORT datad (340:340:340) (370:370:370)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~138) + (DELAY + (ABSOLUTE + (PORT dataa (1042:1042:1042) (1147:1147:1147)) + (PORT datab (671:671:671) (712:712:712)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (DELAY + (ABSOLUTE + (PORT datab (1402:1402:1402) (1455:1455:1455)) + (PORT datac (1615:1615:1615) (1701:1701:1701)) + (PORT datad (1189:1189:1189) (1294:1294:1294)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (277:277:277)) + (PORT datab (1199:1199:1199) (1232:1232:1232)) + (PORT datac (1173:1173:1173) (1255:1255:1255)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (1123:1123:1123) (1183:1183:1183)) + (PORT datab (3290:3290:3290) (3477:3477:3477)) + (PORT datac (1148:1148:1148) (1200:1200:1200)) + (PORT datad (561:561:561) (572:572:572)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1048:1048:1048) (1087:1087:1087)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3996:3996:3996) (4212:4212:4212)) + (PORT d[1] (1700:1700:1700) (1852:1852:1852)) + (PORT d[2] (1685:1685:1685) (1760:1760:1760)) + (PORT d[3] (1880:1880:1880) (1986:1986:1986)) + (PORT d[4] (2151:2151:2151) (2275:2275:2275)) + (PORT d[5] (1351:1351:1351) (1462:1462:1462)) + (PORT d[6] (1496:1496:1496) (1550:1550:1550)) + (PORT d[7] (3357:3357:3357) (3515:3515:3515)) + (PORT d[8] (3629:3629:3629) (3880:3880:3880)) + (PORT d[9] (1469:1469:1469) (1530:1530:1530)) + (PORT d[10] (3184:3184:3184) (3384:3384:3384)) + (PORT d[11] (2096:2096:2096) (2225:2225:2225)) + (PORT d[12] (1735:1735:1735) (1780:1780:1780)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2569:2569:2569) (2625:2625:2625)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (2985:2985:2985) (3047:3047:3047)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (672:672:672) (698:698:698)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3032:3032:3032) (3215:3215:3215)) + (PORT d[1] (1378:1378:1378) (1491:1491:1491)) + (PORT d[2] (2016:2016:2016) (2093:2093:2093)) + (PORT d[3] (2186:2186:2186) (2283:2283:2283)) + (PORT d[4] (1556:1556:1556) (1641:1641:1641)) + (PORT d[5] (1392:1392:1392) (1479:1479:1479)) + (PORT d[6] (1191:1191:1191) (1221:1221:1221)) + (PORT d[7] (3356:3356:3356) (3523:3523:3523)) + (PORT d[8] (2486:2486:2486) (2673:2673:2673)) + (PORT d[9] (3482:3482:3482) (3624:3624:3624)) + (PORT d[10] (2885:2885:2885) (3060:3060:3060)) + (PORT d[11] (1777:1777:1777) (1854:1854:1854)) + (PORT d[12] (1425:1425:1425) (1448:1448:1448)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1966:1966:1966) (1924:1924:1924)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2989:2989:2989) (2983:2983:2983)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (988:988:988) (1034:1034:1034)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3012:3012:3012) (3174:3174:3174)) + (PORT d[1] (1364:1364:1364) (1477:1477:1477)) + (PORT d[2] (1640:1640:1640) (1735:1735:1735)) + (PORT d[3] (1512:1512:1512) (1577:1577:1577)) + (PORT d[4] (1911:1911:1911) (1988:1988:1988)) + (PORT d[5] (1627:1627:1627) (1743:1743:1743)) + (PORT d[6] (1358:1358:1358) (1370:1370:1370)) + (PORT d[7] (1444:1444:1444) (1493:1493:1493)) + (PORT d[8] (2152:2152:2152) (2337:2337:2337)) + (PORT d[9] (3818:3818:3818) (3964:3964:3964)) + (PORT d[10] (2602:2602:2602) (2756:2756:2756)) + (PORT d[11] (1824:1824:1824) (1907:1907:1907)) + (PORT d[12] (2034:2034:2034) (2077:2077:2077)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1660:1660:1660) (1642:1642:1642)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2201:2201:2201) (2225:2225:2225)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (653:653:653)) + (PORT datab (1345:1345:1345) (1422:1422:1422)) + (PORT datac (885:885:885) (921:921:921)) + (PORT datad (1162:1162:1162) (1219:1219:1219)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1287:1287:1287) (1355:1355:1355)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3658:3658:3658) (3886:3886:3886)) + (PORT d[1] (1696:1696:1696) (1864:1864:1864)) + (PORT d[2] (3022:3022:3022) (3145:3145:3145)) + (PORT d[3] (2178:2178:2178) (2273:2273:2273)) + (PORT d[4] (2261:2261:2261) (2381:2381:2381)) + (PORT d[5] (2406:2406:2406) (2602:2602:2602)) + (PORT d[6] (2067:2067:2067) (2147:2147:2147)) + (PORT d[7] (2761:2761:2761) (2873:2873:2873)) + (PORT d[8] (3032:3032:3032) (3240:3240:3240)) + (PORT d[9] (2561:2561:2561) (2657:2657:2657)) + (PORT d[10] (3754:3754:3754) (3977:3977:3977)) + (PORT d[11] (1812:1812:1812) (1889:1889:1889)) + (PORT d[12] (2036:2036:2036) (2121:2121:2121)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2791:2791:2791) (2784:2784:2784)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (2736:2736:2736) (2702:2702:2702)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1271:1271:1271)) + (PORT datab (935:935:935) (963:963:963)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1431:1431:1431) (1479:1479:1479)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3642:3642:3642) (3806:3806:3806)) + (PORT d[1] (2601:2601:2601) (2824:2824:2824)) + (PORT d[2] (1657:1657:1657) (1747:1747:1747)) + (PORT d[3] (2161:2161:2161) (2264:2264:2264)) + (PORT d[4] (1866:1866:1866) (1940:1940:1940)) + (PORT d[5] (1348:1348:1348) (1465:1465:1465)) + (PORT d[6] (1148:1148:1148) (1176:1176:1176)) + (PORT d[7] (1458:1458:1458) (1492:1492:1492)) + (PORT d[8] (2173:2173:2173) (2360:2360:2360)) + (PORT d[9] (3841:3841:3841) (3989:3989:3989)) + (PORT d[10] (2571:2571:2571) (2714:2714:2714)) + (PORT d[11] (2100:2100:2100) (2188:2188:2188)) + (PORT d[12] (2024:2024:2024) (2056:2056:2056)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (3353:3353:3353) (3478:3478:3478)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1472:1472:1472) (1543:1543:1543)) + (PORT clk (1846:1846:1846) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3349:3349:3349) (3537:3537:3537)) + (PORT d[1] (2304:2304:2304) (2505:2505:2505)) + (PORT d[2] (2195:2195:2195) (2287:2287:2287)) + (PORT d[3] (1835:1835:1835) (1941:1941:1941)) + (PORT d[4] (2157:2157:2157) (2255:2255:2255)) + (PORT d[5] (1649:1649:1649) (1788:1788:1788)) + (PORT d[6] (1483:1483:1483) (1506:1506:1506)) + (PORT d[7] (1491:1491:1491) (1524:1524:1524)) + (PORT d[8] (2907:2907:2907) (3105:3105:3105)) + (PORT d[9] (2279:2279:2279) (2414:2414:2414)) + (PORT d[10] (2285:2285:2285) (2382:2382:2382)) + (PORT d[11] (2475:2475:2475) (2611:2611:2611)) + (PORT d[12] (1976:1976:1976) (2027:2027:2027)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2840:2840:2840) (2830:2830:2830)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1875:1875:1875)) + (PORT d[0] (3982:3982:3982) (4087:4087:4087)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1800:1800:1800)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2301:2301:2301) (2290:2290:2290)) + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4340:4340:4340) (4420:4420:4420)) + (PORT d[1] (4239:4239:4239) (4282:4282:4282)) + (PORT d[2] (4257:4257:4257) (4315:4315:4315)) + (PORT d[3] (4538:4538:4538) (4588:4588:4588)) + (PORT d[4] (4287:4287:4287) (4306:4306:4306)) + (PORT d[5] (4351:4351:4351) (4371:4371:4371)) + (PORT d[6] (4481:4481:4481) (4572:4572:4572)) + (PORT d[7] (4342:4342:4342) (4398:4398:4398)) + (PORT d[8] (4597:4597:4597) (4592:4592:4592)) + (PORT d[9] (4469:4469:4469) (4739:4739:4739)) + (PORT d[10] (4352:4352:4352) (4394:4394:4394)) + (PORT d[11] (4350:4350:4350) (4370:4370:4370)) + (PORT d[12] (4626:4626:4626) (4608:4608:4608)) + (PORT clk (1807:1807:1807) (1802:1802:1802)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (944:944:944)) + (PORT datab (1682:1682:1682) (1751:1751:1751)) + (PORT datac (910:910:910) (950:950:950)) + (PORT datad (1193:1193:1193) (1243:1243:1243)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3603:3603:3603) (3780:3780:3780)) + (PORT d[1] (2612:2612:2612) (2820:2820:2820)) + (PORT d[2] (1542:1542:1542) (1613:1613:1613)) + (PORT d[3] (2126:2126:2126) (2248:2248:2248)) + (PORT d[4] (2158:2158:2158) (2252:2252:2252)) + (PORT d[5] (1643:1643:1643) (1776:1776:1776)) + (PORT d[6] (1395:1395:1395) (1417:1417:1417)) + (PORT d[7] (1473:1473:1473) (1509:1509:1509)) + (PORT d[8] (2157:2157:2157) (2322:2322:2322)) + (PORT d[9] (2292:2292:2292) (2444:2444:2444)) + (PORT d[10] (2276:2276:2276) (2402:2402:2402)) + (PORT d[11] (2115:2115:2115) (2225:2225:2225)) + (PORT d[12] (2288:2288:2288) (2338:2338:2338)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1873:1873:1873)) + (PORT d[0] (3448:3448:3448) (3327:3327:3327)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1836:1836:1836)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (276:276:276)) + (PORT datab (906:906:906) (941:941:941)) + (PORT datac (1129:1129:1129) (1177:1177:1177)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1549:1549:1549) (1631:1631:1631)) + (PORT clk (1862:1862:1862) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2520:2520:2520) (2617:2617:2617)) + (PORT d[1] (1962:1962:1962) (2122:2122:2122)) + (PORT d[2] (1955:1955:1955) (2077:2077:2077)) + (PORT d[3] (1876:1876:1876) (2000:2000:2000)) + (PORT d[4] (2723:2723:2723) (2864:2864:2864)) + (PORT d[5] (2232:2232:2232) (2416:2416:2416)) + (PORT d[6] (2043:2043:2043) (2115:2115:2115)) + (PORT d[7] (2404:2404:2404) (2531:2531:2531)) + (PORT d[8] (2398:2398:2398) (2577:2577:2577)) + (PORT d[9] (1996:1996:1996) (2101:2101:2101)) + (PORT d[10] (1691:1691:1691) (1769:1769:1769)) + (PORT d[11] (2047:2047:2047) (2128:2128:2128)) + (PORT d[12] (2520:2520:2520) (2605:2605:2605)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2655:2655:2655) (2640:2640:2640)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1888:1888:1888)) + (PORT d[0] (3407:3407:3407) (3339:3339:3339)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1813:1813:1813)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2066:2066:2066) (2077:2077:2077)) + (PORT clk (1827:1827:1827) (1819:1819:1819)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4618:4618:4618) (4692:4692:4692)) + (PORT d[1] (4233:4233:4233) (4271:4271:4271)) + (PORT d[2] (4532:4532:4532) (4592:4592:4592)) + (PORT d[3] (4449:4449:4449) (4489:4489:4489)) + (PORT d[4] (4330:4330:4330) (4336:4336:4336)) + (PORT d[5] (4590:4590:4590) (4607:4607:4607)) + (PORT d[6] (4724:4724:4724) (4801:4801:4801)) + (PORT d[7] (4565:4565:4565) (4613:4613:4613)) + (PORT d[8] (4569:4569:4569) (4629:4629:4629)) + (PORT d[9] (4484:4484:4484) (4751:4751:4751)) + (PORT d[10] (4377:4377:4377) (4395:4395:4395)) + (PORT d[11] (4636:4636:4636) (4682:4682:4682)) + (PORT d[12] (4604:4604:4604) (4754:4754:4754)) + (PORT clk (1823:1823:1823) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1827:1827:1827) (1819:1819:1819)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1815:1815:1815)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (946:946:946)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (1482:1482:1482) (1521:1521:1521)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (1613:1613:1613) (1669:1669:1669)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1616:1616:1616) (1701:1701:1701)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (1399:1399:1399) (1458:1458:1458)) + (PORT datac (1325:1325:1325) (1390:1390:1390)) + (PORT datad (341:341:341) (359:359:359)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (1628:1628:1628) (1657:1657:1657)) + (PORT datab (1397:1397:1397) (1455:1455:1455)) + (PORT datac (1102:1102:1102) (1179:1179:1179)) + (PORT datad (313:313:313) (331:331:331)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (975:975:975) (1040:1040:1040)) + (PORT datab (1658:1658:1658) (1724:1724:1724)) + (PORT datac (239:239:239) (291:291:291)) + (PORT datad (875:875:875) (896:896:896)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (310:310:310)) + (PORT datab (660:660:660) (727:727:727)) + (PORT datad (213:213:213) (248:248:248)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1009:1009:1009)) + (PORT datab (906:906:906) (952:952:952)) + (PORT datac (884:884:884) (932:932:932)) + (PORT datad (924:924:924) (947:947:947)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1571:1571:1571) (1550:1550:1550)) + (PORT ena (1479:1479:1479) (1488:1488:1488)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1561:1561:1561)) + (PORT datab (1173:1173:1173) (1201:1201:1201)) + (PORT datac (1193:1193:1193) (1280:1280:1280)) + (PORT datad (1406:1406:1406) (1444:1444:1444)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (970:970:970)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (896:896:896) (900:900:900)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (605:605:605) (641:641:641)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datad (1539:1539:1539) (1638:1638:1638)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (1391:1391:1391) (1424:1424:1424)) + (PORT datab (630:630:630) (671:671:671)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51428,11 +49984,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1531:1531:1531)) + (PORT clk (1528:1528:1528) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (765:765:765) (832:832:832)) - (PORT sload (1678:1678:1678) (1738:1738:1738)) - (PORT ena (2119:2119:2119) (2120:2120:2120)) + (PORT asdata (580:580:580) (654:654:654)) + (PORT sload (1117:1117:1117) (1168:1168:1168)) + (PORT ena (811:811:811) (804:804:804)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -51445,79 +50001,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~84) + (INSTANCE D\[0\]\~59) (DELAY (ABSOLUTE - (PORT dataa (698:698:698) (722:722:722)) - (PORT datab (3327:3327:3327) (3563:3563:3563)) - (PORT datac (1214:1214:1214) (1273:1273:1273)) - (PORT datad (695:695:695) (758:758:758)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (912:912:912)) - (PORT datab (1191:1191:1191) (1280:1280:1280)) - (PORT datac (707:707:707) (759:759:759)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (884:884:884) (914:914:914)) + (PORT datab (1147:1147:1147) (1200:1200:1200)) + (PORT datac (179:179:179) (216:216:216)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~85) + (INSTANCE D\[0\]\~60) (DELAY (ABSOLUTE - (PORT dataa (726:726:726) (766:766:766)) - (PORT datab (2222:2222:2222) (2368:2368:2368)) - (PORT datac (316:316:316) (341:341:341)) - (PORT datad (2998:2998:2998) (3240:3240:3240)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1270:1270:1270)) - (PORT datab (672:672:672) (750:750:750)) - (PORT datac (574:574:574) (611:611:611)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (2231:2231:2231) (2351:2351:2351)) - (PORT datab (236:236:236) (280:280:280)) - (PORT datac (3029:3029:3029) (3275:3275:3275)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (948:948:948) (996:996:996)) + (PORT datab (642:642:642) (701:701:701)) + (PORT datac (1642:1642:1642) (1669:1669:1669)) + (PORT datad (329:329:329) (345:345:345)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51525,15 +50031,73 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~59) + (INSTANCE D\[1\]\~61) (DELAY (ABSOLUTE - (PORT dataa (1511:1511:1511) (1588:1588:1588)) - (PORT datab (1676:1676:1676) (1756:1756:1756)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (1445:1445:1445) (1468:1468:1468)) + (PORT datac (831:831:831) (845:845:845)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (1402:1402:1402) (1476:1476:1476)) + (PORT datab (940:940:940) (1026:1026:1026)) + (PORT datac (962:962:962) (1081:1081:1081)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (413:413:413)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (500:500:500)) + (PORT datab (233:233:233) (277:277:277)) + (PORT datac (1139:1139:1139) (1183:1183:1183)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (260:260:260)) + (PORT datac (1325:1325:1325) (1392:1392:1392)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51541,32 +50105,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~87) + (INSTANCE D\[3\]\~76) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (3324:3324:3324) (3557:3557:3557)) - (PORT datac (1216:1216:1216) (1278:1278:1278)) - (PORT datad (701:701:701) (766:766:766)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1121:1121:1121) (1209:1209:1209)) + (PORT datab (1140:1140:1140) (1196:1196:1196)) + (PORT datac (1527:1527:1527) (1561:1561:1561)) + (PORT datad (328:328:328) (343:343:343)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~67) + (INSTANCE D\[4\]\~82) (DELAY (ABSOLUTE - (PORT dataa (921:921:921) (965:965:965)) - (PORT datab (1471:1471:1471) (1534:1534:1534)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (887:887:887) (917:917:917)) + (PORT datab (1549:1549:1549) (1602:1602:1602)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (1002:1002:1002)) + (PORT datab (1444:1444:1444) (1508:1508:1508)) + (PORT datac (1641:1641:1641) (1667:1667:1667)) + (PORT datad (330:330:330) (348:348:348)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~92) + (DELAY + (ABSOLUTE + (PORT datab (1379:1379:1379) (1383:1383:1383)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1000:1000:1000)) + (PORT datab (894:894:894) (967:967:967)) + (PORT datac (1642:1642:1642) (1672:1672:1672)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51576,12 +50184,12 @@ (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT dataa (935:935:935) (981:981:981)) - (PORT datab (271:271:271) (358:358:358)) - (PORT datac (252:252:252) (334:334:334)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (1365:1365:1365) (1505:1505:1505)) + (PORT datac (2335:2335:2335) (2467:2467:2467)) + (PORT datad (554:554:554) (564:564:564)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -51590,10 +50198,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1535:1535:1535) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1291:1291:1291) (1310:1310:1310)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51608,7 +50216,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (648:648:648) (726:726:726)) + (PORT datad (242:242:242) (312:312:312)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51618,10 +50226,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (1546:1546:1546) (1543:1543:1543)) + (PORT clk (1542:1542:1542) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (1235:1235:1235) (1231:1231:1231)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51636,10 +50244,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1543:1543:1543)) - (PORT asdata (890:890:890) (938:938:938)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1432:1432:1432) (1420:1420:1420)) + (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT asdata (565:565:565) (644:644:644)) + (PORT clrn (1591:1591:1591) (1566:1566:1566)) + (PORT ena (1321:1321:1321) (1347:1347:1347)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51654,9 +50262,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (575:575:575) (633:633:633)) - (PORT datab (251:251:251) (336:336:336)) - (PORT datad (224:224:224) (296:296:296)) + (PORT dataa (251:251:251) (340:340:340)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datad (216:216:216) (283:283:283)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -51669,9 +50277,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (260:260:260) (355:355:355)) - (PORT datab (207:207:207) (250:250:250)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (912:912:912) (985:985:985)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (182:182:182) (211:211:211)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -51679,6 +50287,15 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE ula_\|pll_\|altpll_component\|auto_generated\|wire_pll1_clk\[2\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1896:1896:1896) (1878:1878:1878)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|divider\[0\]\~15) @@ -51693,9 +50310,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51710,7 +50327,7 @@ (DELAY (ABSOLUTE (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (252:252:252) (337:337:337)) + (PORT datab (251:251:251) (337:337:337)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -51724,9 +50341,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51740,9 +50357,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (253:253:253) (343:343:343)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -51754,9 +50371,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51784,9 +50401,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51800,7 +50417,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) (DELAY (ABSOLUTE - (PORT datab (252:252:252) (339:339:339)) + (PORT datab (251:251:251) (337:337:337)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51814,9 +50431,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51830,8 +50447,8 @@ (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) (DELAY (ABSOLUTE - (PORT dataa (255:255:255) (344:344:344)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -51841,9 +50458,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51857,10 +50474,10 @@ (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (342:342:342)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (224:224:224) (302:302:302)) - (PORT datad (226:226:226) (298:298:298)) + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datac (223:223:223) (302:302:302)) + (PORT datad (225:225:225) (297:297:297)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -51873,11 +50490,11 @@ (INSTANCE ula_\|i2c_loader_\|WideAnd0) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (335:335:335)) - (PORT datac (223:223:223) (303:303:303)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (250:250:250) (334:334:334)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (225:225:225) (296:296:296)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51887,10 +50504,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1022:1022:1022) (977:977:977)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT ena (1428:1428:1428) (1403:1403:1403)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51905,7 +50522,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (267:267:267) (348:348:348)) + (PORT datad (245:245:245) (317:317:317)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51916,10 +50533,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1022:1022:1022) (977:977:977)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT ena (1428:1428:1428) (1403:1403:1403)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51934,9 +50551,9 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT dataa (297:297:297) (393:393:393)) - (PORT datad (246:246:246) (319:319:319)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT datab (333:333:333) (440:440:440)) + (PORT datad (247:247:247) (319:319:319)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51947,10 +50564,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1022:1022:1022) (977:977:977)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT ena (1428:1428:1428) (1403:1403:1403)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51960,13 +50577,36 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~5) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (709:709:709)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (307:307:307) (404:404:404)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|Mux42\~0) (DELAY (ABSOLUTE - (PORT datac (1131:1131:1131) (1182:1182:1182)) - (PORT datad (655:655:655) (717:717:717)) + (PORT datac (700:700:700) (774:774:774)) + (PORT datad (677:677:677) (746:746:746)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51974,27 +50614,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (INSTANCE ula_\|i2c_loader_\|nbyte\~4) (DELAY (ABSOLUTE - (PORT dataa (271:271:271) (370:370:370)) - (PORT datab (868:868:868) (936:936:936)) + (PORT dataa (286:286:286) (381:381:381)) + (PORT datab (336:336:336) (443:443:443)) + (PORT datad (634:634:634) (704:704:704)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1223:1223:1223)) - (PORT datab (760:760:760) (826:826:826)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52003,10 +50632,10 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datac (435:435:435) (510:510:510)) - (PORT datad (656:656:656) (720:720:720)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (290:290:290) (381:381:381)) + (PORT datac (578:578:578) (623:623:623)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -52024,13 +50653,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (446:446:446) (519:519:519)) - (PORT datab (1089:1089:1089) (1128:1128:1128)) - (PORT datac (426:426:426) (500:500:500)) - (PORT datad (508:508:508) (502:502:502)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (284:284:284) (379:379:379)) + (PORT datab (272:272:272) (359:359:359)) + (PORT datac (301:301:301) (403:403:403)) + (PORT datad (516:516:516) (513:513:513)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52040,13 +50669,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (239:239:239) (281:281:281)) - (PORT datac (724:724:724) (791:791:791)) - (PORT datad (329:329:329) (343:343:343)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (662:662:662) (747:747:747)) + (PORT datab (653:653:653) (670:670:670)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52056,23 +50685,23 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (691:691:691) (755:755:755)) - (PORT datac (786:786:786) (794:794:794)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (835:835:835) (857:857:857)) + (PORT datac (423:423:423) (492:492:492)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -52085,75 +50714,89 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT dataa (460:460:460) (536:536:536)) - (PORT datab (867:867:867) (935:935:935)) - (PORT datad (406:406:406) (471:471:471)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (677:677:677) (755:755:755)) + (PORT datab (713:713:713) (770:770:770)) + (PORT datac (253:253:253) (337:337:337)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (1125:1125:1125) (1171:1171:1171)) - (PORT datab (867:867:867) (936:936:936)) - (PORT datac (644:644:644) (709:709:709)) - (PORT datad (692:692:692) (746:746:746)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (844:844:844) (895:895:895)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (371:371:371)) - (PORT datab (804:804:804) (839:839:839)) - (PORT datac (211:211:211) (252:252:252)) - (PORT datad (652:652:652) (715:715:715)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (596:596:596) (620:620:620)) + (PORT datab (263:263:263) (314:314:314)) + (PORT datad (341:341:341) (360:360:360)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) + (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (1909:1909:1909) (1926:1926:1926)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) - (PORT ena (1122:1122:1122) (1112:1112:1112)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (389:389:389)) + (PORT datab (261:261:261) (350:350:350)) + (PORT datac (232:232:232) (318:318:318)) + (PORT datad (567:567:567) (616:616:616)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (710:710:710)) + (PORT datab (267:267:267) (356:356:356)) + (PORT datad (234:234:234) (311:311:311)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT ena (1191:1191:1191) (1184:1184:1184)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52168,10 +50811,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) (DELAY (ABSOLUTE - (PORT dataa (271:271:271) (370:370:370)) - (PORT datab (252:252:252) (337:337:337)) - (PORT datac (830:830:830) (890:890:890)) - (PORT datad (233:233:233) (308:308:308)) + (PORT dataa (259:259:259) (351:351:351)) + (PORT datab (249:249:249) (335:335:335)) + (PORT datac (602:602:602) (665:665:665)) + (PORT datad (238:238:238) (316:316:316)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -52184,12 +50827,12 @@ (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (361:361:361)) - (PORT datab (271:271:271) (356:356:356)) - (PORT datac (243:243:243) (322:322:322)) - (PORT datad (255:255:255) (328:328:328)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (361:361:361) (399:399:399)) + (PORT datab (370:370:370) (392:392:392)) + (PORT datac (920:920:920) (977:977:977)) + (PORT datad (327:327:327) (351:351:351)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52200,25 +50843,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (662:662:662)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datac (788:788:788) (805:805:805)) - (PORT datad (267:267:267) (348:348:348)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~2) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (410:410:410)) - (PORT datab (424:424:424) (454:454:454)) - (PORT datad (254:254:254) (328:328:328)) + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (562:562:562) (591:591:591)) + (PORT datad (443:443:443) (515:515:515)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -52242,231 +50869,18 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT dataa (272:272:272) (363:363:363)) - (PORT datac (436:436:436) (512:512:512)) - (PORT datad (770:770:770) (813:813:813)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (268:268:268)) - (PORT datac (1135:1135:1135) (1181:1181:1181)) - (PORT datad (659:659:659) (717:717:717)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT datab (274:274:274) (360:360:360)) - (PORT datac (512:512:512) (523:523:523)) - (PORT datad (385:385:385) (449:449:449)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT datab (609:609:609) (628:628:628)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1134:1134:1134) (1151:1151:1151)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT sload (864:864:864) (978:978:978)) - (PORT ena (1022:1022:1022) (977:977:977)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~5) - (DELAY - (ABSOLUTE - (PORT datab (869:869:869) (937:937:937)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1909:1909:1909) (1926:1926:1926)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) - (PORT ena (1122:1122:1122) (1112:1112:1112)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~0) - (DELAY - (ABSOLUTE - (PORT dataa (269:269:269) (370:370:370)) - (PORT datab (868:868:868) (936:936:936)) - (PORT datad (233:233:233) (308:308:308)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1909:1909:1909) (1926:1926:1926)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) - (PORT ena (1122:1122:1122) (1112:1112:1112)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) - (DELAY - (ABSOLUTE - (PORT datab (252:252:252) (337:337:337)) - (PORT datac (241:241:241) (332:332:332)) - (PORT datad (233:233:233) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) - (DELAY - (ABSOLUTE - (PORT dataa (264:264:264) (361:361:361)) - (PORT datab (343:343:343) (377:377:377)) - (PORT datac (509:509:509) (520:520:520)) - (PORT datad (253:253:253) (326:326:326)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (664:664:664)) - (PORT datab (282:282:282) (369:369:369)) - (PORT datac (174:174:174) (207:207:207)) - (PORT datad (267:267:267) (349:349:349)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (768:768:768)) - (PORT datab (625:625:625) (681:681:681)) - (PORT datac (722:722:722) (792:792:792)) - (PORT datad (1054:1054:1054) (1092:1092:1092)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (439:439:439) (519:519:519)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (595:595:595) (665:665:665)) - (PORT datab (889:889:889) (937:937:937)) - (PORT datac (602:602:602) (649:649:649)) - (PORT datad (732:732:732) (710:710:710)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (285:285:285) (380:380:380)) + (PORT datab (272:272:272) (356:356:356)) + (PORT datac (302:302:302) (404:404:404)) + (PORT datad (517:517:517) (510:510:510)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52476,10 +50890,10 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (862:862:862) (910:910:910)) - (PORT datab (623:623:623) (689:689:689)) - (PORT datac (768:768:768) (775:775:775)) - (PORT datad (176:176:176) (202:202:202)) + (PORT dataa (416:416:416) (489:489:489)) + (PORT datab (587:587:587) (640:640:640)) + (PORT datac (850:850:850) (859:859:859)) + (PORT datad (309:309:309) (325:325:325)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -52492,12 +50906,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2326:2326:2326) (2405:2405:2405)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sload (1723:1723:1723) (1708:1708:1708)) - (PORT ena (820:820:820) (825:825:825)) + (PORT asdata (1124:1124:1124) (1148:1148:1148)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sload (1067:1067:1067) (1036:1036:1036)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52514,9 +50928,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (393:393:393)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (297:297:297) (392:392:392)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52528,12 +50942,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2327:2327:2327) (2405:2405:2405)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sload (1723:1723:1723) (1708:1708:1708)) - (PORT ena (820:820:820) (825:825:825)) + (PORT asdata (1125:1125:1125) (1149:1149:1149)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sload (1067:1067:1067) (1036:1036:1036)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52550,7 +50964,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT datab (298:298:298) (393:393:393)) + (PORT datab (288:288:288) (380:380:380)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52564,11 +50978,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sload (1723:1723:1723) (1708:1708:1708)) - (PORT ena (820:820:820) (825:825:825)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sload (1067:1067:1067) (1036:1036:1036)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52585,7 +50999,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (294:294:294) (387:387:387)) + (PORT datab (306:306:306) (403:403:403)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52599,12 +51013,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2328:2328:2328) (2407:2407:2407)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sload (1723:1723:1723) (1708:1708:1708)) - (PORT ena (820:820:820) (825:825:825)) + (PORT asdata (1125:1125:1125) (1150:1150:1150)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sload (1067:1067:1067) (1036:1036:1036)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52621,10 +51035,10 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (669:669:669) (721:721:721)) - (PORT datab (460:460:460) (532:532:532)) - (PORT datac (402:402:402) (484:484:484)) - (PORT datad (404:404:404) (470:470:470)) + (PORT dataa (426:426:426) (508:508:508)) + (PORT datab (298:298:298) (392:392:392)) + (PORT datac (277:277:277) (365:365:365)) + (PORT datad (279:279:279) (363:363:363)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -52632,13 +51046,29 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (798:798:798)) + (PORT datab (261:261:261) (350:350:350)) + (PORT datac (704:704:704) (778:778:778)) + (PORT datad (260:260:260) (337:337:337)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) (DELAY (ABSOLUTE - (PORT datad (270:270:270) (351:351:351)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (308:308:308) (413:413:413)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -52648,11 +51078,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sload (1723:1723:1723) (1708:1708:1708)) - (PORT ena (820:820:820) (825:825:825)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sload (1067:1067:1067) (1036:1036:1036)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52669,25 +51099,57 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) (DELAY (ABSOLUTE - (PORT datab (201:201:201) (240:240:240)) - (PORT datac (175:175:175) (209:209:209)) - (PORT datad (414:414:414) (479:479:479)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (622:622:622) (640:640:640)) + (PORT datac (335:335:335) (357:357:357)) + (PORT datad (658:658:658) (710:710:710)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (286:286:286) (376:376:376)) + (PORT datac (231:231:231) (314:314:314)) + (PORT datad (487:487:487) (489:489:489)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (374:374:374)) + (PORT datab (266:266:266) (320:320:320)) + (PORT datac (261:261:261) (352:352:352)) + (PORT datad (421:421:421) (491:491:491)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (243:243:243)) - (PORT datab (429:429:429) (456:456:456)) - (PORT datad (596:596:596) (611:611:611)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) + (PORT dataa (343:343:343) (380:380:380)) + (PORT datab (590:590:590) (613:613:613)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52698,9 +51160,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52714,9 +51176,9 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (359:359:359)) - (PORT datab (819:819:819) (842:842:842)) - (PORT datad (268:268:268) (350:350:350)) + (PORT dataa (264:264:264) (356:356:356)) + (PORT datab (267:267:267) (321:321:321)) + (PORT datad (419:419:419) (488:488:488)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -52729,10 +51191,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Start) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1022:1022:1022) (977:977:977)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1192:1192:1192) (1154:1154:1154)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52744,14 +51206,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (INSTANCE ula_\|i2c_loader_\|nbyte\~0) (DELAY (ABSOLUTE - (PORT dataa (1172:1172:1172) (1221:1221:1221)) - (PORT datab (765:765:765) (833:833:833)) - (PORT datad (772:772:772) (817:817:817)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (330:330:330) (437:437:437)) + (PORT datad (630:630:630) (700:700:700)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52759,12 +51219,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -52777,28 +51237,92 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (277:277:277) (369:369:369)) - (PORT datac (433:433:433) (508:508:508)) - (PORT datad (766:766:766) (810:810:810)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (678:678:678) (749:749:749)) + (PORT datac (684:684:684) (733:733:733)) + (PORT datad (441:441:441) (514:514:514)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (632:632:632) (666:666:666)) - (PORT datab (424:424:424) (454:454:454)) - (PORT datad (314:314:314) (333:333:333)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) + (PORT dataa (1033:1033:1033) (1086:1086:1086)) + (PORT datab (486:486:486) (561:561:561)) + (PORT datac (255:255:255) (338:338:338)) + (PORT datad (669:669:669) (726:726:726)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (590:590:590) (648:648:648)) + (PORT datad (326:326:326) (348:348:348)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (387:387:387)) + (PORT datab (262:262:262) (314:314:314)) + (PORT datac (556:556:556) (578:578:578)) + (PORT datad (424:424:424) (491:491:491)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1900:1900:1900) (1919:1919:1919)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT ena (1160:1160:1160) (1135:1135:1135)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (707:707:707)) + (PORT datad (241:241:241) (319:319:319)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52806,18 +51330,111 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Stop) + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) (DELAY (ABSOLUTE (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT ena (1191:1191:1191) (1184:1184:1184)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (355:355:355)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datad (241:241:241) (319:319:319)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~27) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (793:793:793)) + (PORT datac (701:701:701) (775:775:775)) + (PORT datad (486:486:486) (488:488:488)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (753:753:753)) + (PORT datab (714:714:714) (770:770:770)) + (PORT datac (251:251:251) (332:332:332)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~26) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (798:798:798)) + (PORT datac (702:702:702) (777:777:777)) + (PORT datad (347:347:347) (368:368:368)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Data) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (578:578:578) (625:625:625)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT sload (875:875:875) (1003:1003:1003)) + (PORT ena (1192:1192:1192) (1154:1154:1154)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL @@ -52825,9 +51442,9 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~0) (DELAY (ABSOLUTE - (PORT datab (271:271:271) (356:356:356)) - (PORT datac (243:243:243) (323:323:323)) - (PORT datad (252:252:252) (325:325:325)) + (PORT datab (288:288:288) (379:379:379)) + (PORT datac (607:607:607) (657:657:657)) + (PORT datad (233:233:233) (310:310:310)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52839,10 +51456,10 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1938:1938:1938) (1962:1962:1962)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) - (PORT ena (1318:1318:1318) (1294:1294:1294)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT ena (1428:1428:1428) (1403:1403:1403)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52857,12 +51474,12 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (1125:1125:1125) (1171:1171:1171)) - (PORT datab (245:245:245) (328:328:328)) - (PORT datac (847:847:847) (898:898:898)) - (PORT datad (692:692:692) (746:746:746)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (661:661:661) (746:746:746)) + (PORT datab (330:330:330) (435:435:435)) + (PORT datac (260:260:260) (348:348:348)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52873,11 +51490,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (581:581:581) (616:616:616)) - (PORT datac (844:844:844) (893:893:893)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (650:650:650) (670:670:670)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (630:630:630) (699:699:699)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52888,9 +51505,9 @@ (DELAY (ABSOLUTE (PORT clk (1473:1473:1473) (1495:1495:1495)) - (PORT d (960:960:960) (1004:1004:1004)) - (PORT aload (1724:1724:1724) (1790:1790:1790)) - (PORT ena (697:697:697) (696:696:696)) + (PORT d (958:958:958) (1002:1002:1002)) + (PORT aload (1710:1710:1710) (1775:1775:1775)) + (PORT ena (885:885:885) (884:884:884)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -52907,10 +51524,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1938:1938:1938) (1962:1962:1962)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) - (PORT ena (1318:1318:1318) (1294:1294:1294)) + (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT ena (1428:1428:1428) (1403:1403:1403)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52920,18 +51537,74 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) + (DELAY + (ABSOLUTE + (PORT datac (887:887:887) (940:940:940)) + (PORT datad (610:610:610) (673:673:673)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|Mux35\~0) (DELAY (ABSOLUTE - (PORT dataa (667:667:667) (716:716:716)) - (PORT datab (461:461:461) (529:529:529)) - (PORT datac (402:402:402) (479:479:479)) - (PORT datad (403:403:403) (470:470:470)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (442:442:442) (520:520:520)) + (PORT datab (457:457:457) (520:520:520)) + (PORT datac (391:391:391) (449:449:449)) + (PORT datad (395:395:395) (456:456:456)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (409:409:409)) + (PORT datab (298:298:298) (389:389:389)) + (PORT datac (278:278:278) (370:370:370)) + (PORT datad (262:262:262) (338:338:338)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) + (DELAY + (ABSOLUTE + (PORT datac (274:274:274) (369:369:369)) + (PORT datad (260:260:260) (337:337:337)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (307:307:307) (404:404:404)) + (PORT datac (278:278:278) (370:370:370)) + (PORT datad (198:198:198) (224:224:224)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52941,11 +51614,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) (DELAY (ABSOLUTE - (PORT datab (756:756:756) (826:826:826)) - (PORT datac (403:403:403) (482:482:482)) - (PORT datad (404:404:404) (474:474:474)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (456:456:456) (520:520:520)) + (PORT datac (890:890:890) (943:943:943)) + (PORT datad (414:414:414) (478:478:478)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52955,11 +51628,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (665:665:665) (739:739:739)) - (PORT datac (1131:1131:1131) (1178:1178:1178)) - (PORT datad (654:654:654) (713:713:713)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (707:707:707) (795:795:795)) + (PORT datac (702:702:702) (777:777:777)) + (PORT datad (261:261:261) (341:341:341)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52969,13 +51642,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (217:217:217) (266:266:266)) - (PORT datab (764:764:764) (831:831:831)) - (PORT datac (211:211:211) (251:251:251)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (294:294:294) (393:393:393)) + (PORT datab (263:263:263) (313:313:313)) + (PORT datac (173:173:173) (205:205:205)) + (PORT datad (350:350:350) (370:370:370)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52985,11 +51658,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datab (804:804:804) (839:839:839)) - (PORT datad (652:652:652) (716:716:716)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT datab (447:447:447) (530:530:530)) + (PORT datac (557:557:557) (581:581:581)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53001,9 +51674,9 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sclr (1200:1200:1200) (1296:1296:1296)) - (PORT ena (945:945:945) (931:931:931)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sclr (1104:1104:1104) (1198:1198:1198)) + (PORT ena (1397:1397:1397) (1366:1366:1366)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53014,27 +51687,15 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) - (DELAY - (ABSOLUTE - (PORT datac (862:862:862) (909:909:909)) - (PORT datad (846:846:846) (891:891:891)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) (DELAY (ABSOLUTE - (PORT dataa (669:669:669) (718:718:718)) - (PORT datab (448:448:448) (516:516:516)) - (PORT datac (402:402:402) (480:480:480)) - (PORT datad (404:404:404) (469:469:469)) + (PORT dataa (305:305:305) (408:408:408)) + (PORT datab (305:305:305) (398:398:398)) + (PORT datac (278:278:278) (369:369:369)) + (PORT datad (262:262:262) (338:338:338)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -53047,13 +51708,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) (DELAY (ABSOLUTE - (PORT dataa (540:540:540) (561:561:561)) - (PORT datab (462:462:462) (530:530:530)) - (PORT datac (403:403:403) (480:480:480)) - (PORT datad (176:176:176) (202:202:202)) + (PORT dataa (374:374:374) (397:397:397)) + (PORT datab (373:373:373) (401:401:401)) + (PORT datac (390:390:390) (448:448:448)) + (PORT datad (413:413:413) (480:480:480)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53064,8 +51725,8 @@ (DELAY (ABSOLUTE (PORT dataa (247:247:247) (334:334:334)) - (PORT datac (724:724:724) (792:792:792)) - (PORT datad (175:175:175) (201:201:201)) + (PORT datac (893:893:893) (946:946:946)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53077,13 +51738,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) (DELAY (ABSOLUTE - (PORT dataa (662:662:662) (736:736:736)) - (PORT datab (760:760:760) (827:827:827)) - (PORT datac (189:189:189) (233:233:233)) - (PORT datad (656:656:656) (720:720:720)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (712:712:712) (775:775:775)) + (PORT datab (482:482:482) (560:560:560)) + (PORT datac (588:588:588) (650:650:650)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53093,10 +51754,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (804:804:804) (835:835:835)) - (PORT datac (1131:1131:1131) (1179:1179:1179)) - (PORT datad (651:651:651) (712:712:712)) + (PORT dataa (1032:1032:1032) (1083:1083:1083)) + (PORT datab (561:561:561) (587:587:587)) + (PORT datac (921:921:921) (976:976:976)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -53111,8 +51772,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT ena (1003:1003:1003) (1001:1001:1001)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT ena (1207:1207:1207) (1188:1188:1188)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53127,12 +51788,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (391:391:391)) - (PORT datab (296:296:296) (390:390:390)) - (PORT datac (410:410:410) (486:486:486)) - (PORT datad (267:267:267) (348:348:348)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (305:305:305) (410:410:410)) + (PORT datab (303:303:303) (399:399:399)) + (PORT datac (274:274:274) (364:364:364)) + (PORT datad (268:268:268) (349:349:349)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53143,13 +51804,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (382:382:382)) - (PORT datab (297:297:297) (390:390:390)) - (PORT datac (411:411:411) (483:483:483)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (445:445:445) (522:522:522)) + (PORT datab (419:419:419) (491:491:491)) + (PORT datac (308:308:308) (330:330:330)) + (PORT datad (197:197:197) (222:222:222)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53159,9 +51820,9 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datac (721:721:721) (791:791:791)) - (PORT datad (339:339:339) (359:359:359)) + (PORT dataa (248:248:248) (337:337:337)) + (PORT datac (886:886:886) (938:938:938)) + (PORT datad (176:176:176) (202:202:202)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53175,8 +51836,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT ena (1003:1003:1003) (1001:1001:1001)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT ena (1207:1207:1207) (1188:1188:1188)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53186,30 +51847,18 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) - (DELAY - (ABSOLUTE - (PORT datac (269:269:269) (358:358:358)) - (PORT datad (269:269:269) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (388:388:388)) - (PORT datab (297:297:297) (390:390:390)) - (PORT datac (269:269:269) (357:357:357)) - (PORT datad (269:269:269) (350:350:350)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (424:424:424) (505:505:505)) + (PORT datab (298:298:298) (389:389:389)) + (PORT datac (273:273:273) (368:368:368)) + (PORT datad (278:278:278) (358:358:358)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53219,12 +51868,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT dataa (213:213:213) (262:262:262)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (411:411:411) (481:481:481)) - (PORT datad (269:269:269) (350:350:350)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (441:441:441) (526:526:526)) + (PORT datab (454:454:454) (519:519:519)) + (PORT datac (501:501:501) (509:509:509)) + (PORT datad (352:352:352) (369:369:369)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53235,10 +51884,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) (DELAY (ABSOLUTE - (PORT dataa (749:749:749) (809:809:809)) - (PORT datab (245:245:245) (329:329:329)) - (PORT datac (723:723:723) (793:793:793)) - (PORT datad (322:322:322) (342:342:342)) + (PORT dataa (639:639:639) (715:715:715)) + (PORT datab (244:244:244) (327:327:327)) + (PORT datac (888:888:888) (940:940:940)) + (PORT datad (175:175:175) (200:200:200)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -53253,8 +51902,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT ena (1003:1003:1003) (1001:1001:1001)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT ena (1207:1207:1207) (1188:1188:1188)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53264,50 +51913,18 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (289:289:289) (388:388:388)) - (PORT datab (296:296:296) (390:390:390)) - (PORT datac (408:408:408) (482:482:482)) - (PORT datad (267:267:267) (348:348:348)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (259:259:259)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (410:410:410) (482:482:482)) - (PORT datad (267:267:267) (350:350:350)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) (DELAY (ABSOLUTE - (PORT dataa (745:745:745) (805:805:805)) - (PORT datab (245:245:245) (328:328:328)) - (PORT datac (716:716:716) (783:783:783)) - (PORT datad (340:340:340) (361:361:361)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (679:679:679) (734:734:734)) + (PORT datac (620:620:620) (667:667:667)) + (PORT datad (364:364:364) (423:423:423)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53319,8 +51936,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT ena (1003:1003:1003) (1001:1001:1001)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT ena (1410:1410:1410) (1399:1399:1399)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53335,9 +51952,9 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT dataa (366:366:366) (404:404:404)) - (PORT datab (811:811:811) (871:871:871)) - (PORT datad (386:386:386) (446:446:446)) + (PORT dataa (544:544:544) (558:558:558)) + (PORT datab (488:488:488) (559:559:559)) + (PORT datad (364:364:364) (420:420:420)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53349,10 +51966,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1587:1587:1587)) - (PORT sload (1416:1416:1416) (1505:1505:1505)) + (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT sload (1203:1203:1203) (1299:1299:1299)) (PORT ena (812:812:812) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -53370,10 +51987,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT dataa (380:380:380) (456:456:456)) - (PORT datac (719:719:719) (789:789:789)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT datab (642:642:642) (706:706:706)) + (PORT datac (893:893:893) (946:946:946)) + (PORT datad (198:198:198) (224:224:224)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53386,9 +52003,9 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sclr (1200:1200:1200) (1296:1296:1296)) - (PORT ena (1003:1003:1003) (1001:1001:1001)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sclr (1104:1104:1104) (1198:1198:1198)) + (PORT ena (1207:1207:1207) (1188:1188:1188)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53404,8 +52021,8 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) (DELAY (ABSOLUTE - (PORT datac (725:725:725) (794:794:794)) - (PORT datad (220:220:220) (289:289:289)) + (PORT datac (887:887:887) (939:939:939)) + (PORT datad (218:218:218) (287:287:287)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53418,9 +52035,9 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1586:1586:1586)) - (PORT sclr (1200:1200:1200) (1296:1296:1296)) - (PORT ena (945:945:945) (931:931:931)) + (PORT clrn (1579:1579:1579) (1574:1574:1574)) + (PORT sclr (1104:1104:1104) (1198:1198:1198)) + (PORT ena (1397:1397:1397) (1366:1366:1366)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53436,12 +52053,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (388:388:388) (459:459:459)) - (PORT datab (759:759:759) (829:829:829)) - (PORT datac (591:591:591) (650:650:650)) - (PORT datad (1052:1052:1052) (1089:1089:1089)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (683:683:683) (742:742:742)) + (PORT datab (416:416:416) (490:490:490)) + (PORT datac (558:558:558) (607:607:607)) + (PORT datad (384:384:384) (444:444:444)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53452,12 +52069,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (521:521:521) (542:542:542)) - (PORT datab (565:565:565) (583:583:583)) - (PORT datac (1097:1097:1097) (1134:1134:1134)) - (PORT datad (508:508:508) (500:500:500)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (537:537:537) (561:561:561)) + (PORT datab (327:327:327) (433:433:433)) + (PORT datac (345:345:345) (368:368:368)) + (PORT datad (517:517:517) (510:510:510)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53468,13 +52085,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~2) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (346:346:346)) - (PORT datab (732:732:732) (788:788:788)) - (PORT datac (1097:1097:1097) (1134:1134:1134)) - (PORT datad (180:180:180) (207:207:207)) + (PORT dataa (254:254:254) (345:345:345)) + (PORT datab (329:329:329) (434:434:434)) + (PORT datac (260:260:260) (345:345:345)) + (PORT datad (181:181:181) (208:208:208)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53485,12 +52102,12 @@ (DELAY (ABSOLUTE (PORT dataa (255:255:255) (348:348:348)) - (PORT datab (730:730:730) (791:791:791)) - (PORT datac (1094:1094:1094) (1137:1137:1137)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (324:324:324) (431:431:431)) + (PORT datac (261:261:261) (346:346:346)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53500,12 +52117,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (586:586:586) (621:621:621)) - (PORT datab (878:878:878) (934:934:934)) - (PORT datac (174:174:174) (208:208:208)) + (PORT dataa (663:663:663) (743:743:743)) + (PORT datab (802:802:802) (828:828:828)) + (PORT datac (173:173:173) (206:206:206)) (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53517,9 +52134,9 @@ (DELAY (ABSOLUTE (PORT clk (1475:1475:1475) (1497:1497:1497)) - (PORT d (692:692:692) (731:731:731)) - (PORT aload (1737:1737:1737) (1805:1805:1805)) - (PORT ena (1070:1070:1070) (1077:1077:1077)) + (PORT d (691:691:691) (730:730:730)) + (PORT aload (1726:1726:1726) (1792:1792:1792)) + (PORT ena (1272:1272:1272) (1294:1294:1294)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -53531,13 +52148,38 @@ (HOLD ena (posedge clk) (101:101:101)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|mclk_r\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|mclk_r) (DELAY (ABSOLUTE (PORT clk (1506:1506:1506) (1528:1528:1528)) - (PORT d (2318:2318:2318) (2289:2289:2289)) + (PORT d (2379:2379:2379) (2282:2282:2282)) (PORT clrn (1763:1763:1763) (1815:1815:1815)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -53548,13 +52190,472 @@ (HOLD d (posedge clk) (97:97:97)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (777:777:777)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (277:277:277)) + (PORT datac (174:174:174) (208:208:208)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (479:479:479)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datad (328:328:328) (343:343:343)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1915:1915:1915)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (391:391:391) (458:458:458)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT datac (345:345:345) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (337:337:337)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (281:281:281)) + (PORT datac (172:172:172) (204:204:204)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (337:337:337)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) + (DELAY + (ABSOLUTE + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (481:481:481)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (365:365:365) (427:427:427)) + (PORT datad (227:227:227) (300:300:300)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (427:427:427) (491:491:491)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT datad (338:338:338) (357:357:357)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (438:438:438) (507:507:507)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT datad (333:333:333) (348:348:348)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1915:1915:1915)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (467:467:467)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) + (DELAY + (ABSOLUTE + (PORT datab (376:376:376) (401:401:401)) + (PORT datac (380:380:380) (411:411:411)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (383:383:383) (442:442:442)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) + (DELAY + (ABSOLUTE + (PORT datad (337:337:337) (357:357:357)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (468:468:468)) + (PORT datab (423:423:423) (484:484:484)) + (PORT datac (392:392:392) (453:453:453)) + (PORT datad (393:393:393) (454:454:454)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (249:249:249) (333:333:333)) + (PORT datac (664:664:664) (736:736:736)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) + (DELAY + (ABSOLUTE + (PORT datad (198:198:198) (224:224:224)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) + (DELAY + (ABSOLUTE + (PORT datab (905:905:905) (938:938:938)) + (PORT datad (233:233:233) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|lrclk_r) (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1526:1526:1526)) - (PORT d (2852:2852:2852) (3007:3007:3007)) + (PORT d (2289:2289:2289) (2450:2450:2450)) (PORT clrn (1761:1761:1761) (1813:1813:1813)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -53571,7 +52672,7 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1527:1527:1527)) - (PORT d (3253:3253:3253) (3391:3391:3391)) + (PORT d (2528:2528:2528) (2663:2663:2663)) (PORT clrn (1762:1762:1762) (1814:1814:1814)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -53582,13 +52683,528 @@ (HOLD d (posedge clk) (97:97:97)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (334:334:334)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (235:235:235) (283:283:283)) + (PORT datac (873:873:873) (896:896:896)) + (PORT datad (241:241:241) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (2714:2714:2714) (2746:2746:2746)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (333:333:333)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (2713:2713:2713) (2746:2746:2746)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (2711:2711:2711) (2744:2744:2744)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (343:343:343)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (2711:2711:2711) (2744:2744:2744)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (343:343:343)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (223:223:223) (303:303:303)) + (PORT datad (227:227:227) (299:299:299)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (269:269:269) (360:360:360)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (2710:2710:2710) (2743:2743:2743)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (538:538:538)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (344:344:344)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~20) + (DELAY + (ABSOLUTE + (PORT dataa (470:470:470) (540:540:540)) + (PORT datab (903:903:903) (940:940:940)) + (PORT datac (205:205:205) (243:243:243)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (472:472:472)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~17) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (284:284:284)) + (PORT datab (234:234:234) (285:285:285)) + (PORT datac (875:875:875) (898:898:898)) + (PORT datad (338:338:338) (359:359:359)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT datab (253:253:253) (339:339:339)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~19) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (539:539:539)) + (PORT datab (906:906:906) (939:939:939)) + (PORT datac (206:206:206) (243:243:243)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT datad (362:362:362) (417:417:417)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (285:285:285)) + (PORT datab (235:235:235) (288:288:288)) + (PORT datac (875:875:875) (900:900:900)) + (PORT datad (339:339:339) (359:359:359)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datac (368:368:368) (430:430:430)) + (PORT datad (361:361:361) (415:415:415)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (353:353:353)) + (PORT datab (217:217:217) (263:263:263)) + (PORT datac (241:241:241) (328:328:328)) + (PORT datad (373:373:373) (399:399:399)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (938:938:938)) + (PORT datab (235:235:235) (286:286:286)) + (PORT datad (375:375:375) (401:401:401)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datac (382:382:382) (450:450:450)) + (PORT datad (371:371:371) (396:396:396)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) + (DELAY + (ABSOLUTE + (PORT datab (216:216:216) (262:262:262)) + (PORT datac (239:239:239) (326:326:326)) + (PORT datad (238:238:238) (316:316:316)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (283:283:283)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (869:869:869) (882:882:882)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|bclk_r) (DELAY (ABSOLUTE (PORT clk (1504:1504:1504) (1526:1526:1526)) - (PORT d (1496:1496:1496) (1579:1579:1579)) + (PORT d (2278:2278:2278) (2430:2430:2430)) (PORT clrn (1761:1761:1761) (1813:1813:1813)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -53599,14 +53215,654 @@ (HOLD d (posedge clk) (97:97:97)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outl\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (861:861:861) (917:917:917)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1754:1754:1754) (1860:1860:1860)) + (PORT datab (1594:1594:1594) (1730:1730:1730)) + (PORT datac (1193:1193:1193) (1255:1255:1255)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|always0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (777:777:777)) + (PORT datab (1248:1248:1248) (1347:1347:1347)) + (PORT datac (1200:1200:1200) (1266:1266:1266)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (2002:2002:2002) (1998:1998:1998)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (279:279:279)) + (PORT datab (216:216:216) (259:259:259)) + (PORT datac (241:241:241) (328:328:328)) + (PORT datad (239:239:239) (317:317:317)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE AUD_ADCDAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1354:1354:1354) (1417:1417:1417)) + (PORT datab (1297:1297:1297) (1385:1385:1385)) + (PORT datad (764:764:764) (757:757:757)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1877:1877:1877) (1887:1887:1887)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT datab (244:244:244) (327:327:327)) + (PORT datad (1250:1250:1250) (1334:1334:1334)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (234:234:234) (283:283:283)) + (PORT datac (872:872:872) (895:895:895)) + (PORT datad (240:240:240) (318:318:318)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) + (DELAY + (ABSOLUTE + (PORT datac (216:216:216) (293:293:293)) + (PORT datad (1250:1250:1250) (1341:1341:1341)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) + (DELAY + (ABSOLUTE + (PORT datab (245:245:245) (328:328:328)) + (PORT datad (1259:1259:1259) (1340:1340:1340)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) + (DELAY + (ABSOLUTE + (PORT datab (246:246:246) (330:330:330)) + (PORT datad (1269:1269:1269) (1352:1352:1352)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) + (DELAY + (ABSOLUTE + (PORT datab (245:245:245) (328:328:328)) + (PORT datad (1270:1270:1270) (1351:1351:1351)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (335:335:335)) + (PORT datad (1261:1261:1261) (1348:1348:1348)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) + (DELAY + (ABSOLUTE + (PORT datab (245:245:245) (328:328:328)) + (PORT datad (1246:1246:1246) (1335:1335:1335)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) + (DELAY + (ABSOLUTE + (PORT datac (216:216:216) (292:292:292)) + (PORT datad (1248:1248:1248) (1334:1334:1334)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) + (DELAY + (ABSOLUTE + (PORT datab (244:244:244) (327:327:327)) + (PORT datad (1249:1249:1249) (1344:1344:1344)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) + (DELAY + (ABSOLUTE + (PORT datac (218:218:218) (296:296:296)) + (PORT datad (1269:1269:1269) (1350:1350:1350)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (334:334:334)) + (PORT datad (1268:1268:1268) (1351:1351:1351)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) + (DELAY + (ABSOLUTE + (PORT datab (244:244:244) (327:327:327)) + (PORT datad (1265:1265:1265) (1355:1355:1355)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1406:1406:1406) (1457:1457:1457)) + (PORT datab (896:896:896) (935:935:935)) + (PORT datad (232:232:232) (306:306:306)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1405:1405:1405) (1456:1456:1456)) + (PORT datab (896:896:896) (934:934:934)) + (PORT datad (232:232:232) (306:306:306)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outr\~0) + (DELAY + (ABSOLUTE + (PORT datac (218:218:218) (296:296:296)) + (PORT datad (219:219:219) (289:289:289)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (2116:2116:2116) (2146:2146:2146)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) + (DELAY + (ABSOLUTE + (PORT datab (1303:1303:1303) (1391:1391:1391)) + (PORT datac (218:218:218) (295:295:295)) + (PORT datad (1337:1337:1337) (1421:1421:1421)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) + (DELAY + (ABSOLUTE + (PORT datab (1222:1222:1222) (1334:1334:1334)) + (PORT datac (217:217:217) (292:292:292)) + (PORT datad (1267:1267:1267) (1356:1356:1356)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (2122:2122:2122) (2190:2190:2190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|pcm_outl\[14\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1553:1553:1553)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1232:1232:1232) (1224:1224:1224)) + (PORT ena (2262:2262:2262) (2235:2235:2235)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53620,11 +53876,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (405:405:405) (486:486:486)) - (PORT datab (1177:1177:1177) (1229:1229:1229)) - (PORT datad (364:364:364) (429:429:429)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1212:1212:1212) (1296:1296:1296)) + (PORT datac (981:981:981) (1087:1087:1087)) + (PORT datad (656:656:656) (680:680:680)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53634,10 +53890,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1866:1866:1866) (1875:1875:1875)) + (PORT clk (1895:1895:1895) (1927:1927:1927)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (2767:2767:2767) (2833:2833:2833)) + (PORT clrn (1575:1575:1575) (1569:1569:1569)) + (PORT ena (1154:1154:1154) (1136:1136:1136)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53652,10 +53908,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) (DELAY (ABSOLUTE - (PORT datab (1178:1178:1178) (1229:1229:1229)) - (PORT datac (596:596:596) (646:646:646)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (216:216:216) (293:293:293)) + (PORT datad (656:656:656) (683:683:683)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -53664,10 +53920,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1866:1866:1866) (1875:1875:1875)) + (PORT clk (1528:1528:1528) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (2767:2767:2767) (2833:2833:2833)) + (PORT clrn (1575:1575:1575) (1569:1569:1569)) + (PORT ena (1190:1190:1190) (1184:1184:1184)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53682,10 +53938,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (1181:1181:1181) (1224:1224:1224)) - (PORT datac (360:360:360) (423:423:423)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (652:652:652) (681:681:681)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -53695,9 +53951,9 @@ (DELAY (ABSOLUTE (PORT clk (1508:1508:1508) (1530:1530:1530)) - (PORT d (1935:1935:1935) (2050:2050:2050)) + (PORT d (1487:1487:1487) (1588:1588:1588)) (PORT clrn (1765:1765:1765) (1817:1817:1817)) - (PORT ena (869:869:869) (872:872:872)) + (PORT ena (1717:1717:1717) (1806:1806:1806)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -53711,10 +53967,106 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[1\]\~feeder) + (INSTANCE ula_\|video_\|LessThan2\~0) (DELAY (ABSOLUTE - (PORT datad (566:566:566) (583:583:583)) + (PORT dataa (291:291:291) (381:381:381)) + (PORT datab (270:270:270) (353:353:353)) + (PORT datac (262:262:262) (341:341:341)) + (PORT datad (244:244:244) (316:316:316)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (348:348:348)) + (PORT datab (260:260:260) (342:342:342)) + (PORT datac (255:255:255) (332:332:332)) + (PORT datad (237:237:237) (307:307:307)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (540:540:540)) + (PORT datab (270:270:270) (354:354:354)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (356:356:356) (374:374:374)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (383:383:383)) + (PORT datab (241:241:241) (280:280:280)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (361:361:361)) + (PORT datab (261:261:261) (343:343:343)) + (PORT datad (247:247:247) (320:320:320)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~0) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (410:410:410) (484:484:484)) + (PORT datad (659:659:659) (717:717:717)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~1) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (260:260:260)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datad (348:348:348) (371:371:371)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53724,23 +54076,86 @@ (INSTANCE ula_\|border\[1\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1232:1232:1232) (1224:1224:1224)) + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT asdata (537:537:537) (568:568:568)) + (PORT ena (2116:2116:2116) (2146:2146:2146)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (453:453:453) (541:541:541)) + (PORT datab (461:461:461) (551:551:551)) + (PORT datac (424:424:424) (504:504:504)) + (PORT datad (416:416:416) (444:444:444)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (361:361:361)) + (PORT datab (273:273:273) (358:358:358)) + (PORT datad (236:236:236) (304:304:304)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (522:522:522)) + (PORT datab (461:461:461) (542:542:542)) + (PORT datac (543:543:543) (561:561:561)) + (PORT datad (646:646:646) (718:718:718)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (744:744:744)) + (PORT datab (483:483:483) (561:561:561)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (354:354:354) (367:367:367)) + (PORT datad (1472:1472:1472) (1505:1505:1505)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53750,10 +54165,10 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (1188:1188:1188) (1268:1268:1268)) - (PORT datab (1478:1478:1478) (1554:1554:1554)) - (PORT datac (1186:1186:1186) (1250:1250:1250)) - (PORT datad (876:876:876) (932:932:932)) + (PORT dataa (1252:1252:1252) (1343:1343:1343)) + (PORT datab (984:984:984) (1066:1066:1066)) + (PORT datac (973:973:973) (1043:1043:1043)) + (PORT datad (280:280:280) (364:364:364)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -53766,9 +54181,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1933:1933:1933)) + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1459:1459:1459) (1451:1451:1451)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53777,25 +54192,15 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (882:882:882) (914:914:914)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (882:882:882) (938:938:938)) - (PORT datab (1203:1203:1203) (1264:1264:1264)) - (PORT datac (934:934:934) (992:992:992)) - (PORT datad (1154:1154:1154) (1209:1209:1209)) + (PORT dataa (1252:1252:1252) (1342:1342:1342)) + (PORT datab (985:985:985) (1065:1065:1065)) + (PORT datac (974:974:974) (1042:1042:1042)) + (PORT datad (280:280:280) (364:364:364)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -53808,14 +54213,14 @@ (INSTANCE ula_\|video_\|attr\[1\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1187:1187:1187) (1160:1160:1160)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (1788:1788:1788) (1847:1847:1847)) + (PORT ena (1421:1421:1421) (1414:1414:1414)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -53824,7 +54229,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (659:659:659) (671:671:671)) + (PORT datad (1546:1546:1546) (1544:1544:1544)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53834,9 +54239,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1943:1943:1943) (1967:1967:1967)) + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1255:1255:1255) (1237:1237:1237)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53851,8 +54256,8 @@ (DELAY (ABSOLUTE (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1707:1707:1707) (1750:1750:1750)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT asdata (1012:1012:1012) (1085:1085:1085)) + (PORT ena (1421:1421:1421) (1414:1414:1414)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53861,226 +54266,12 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (615:615:615) (625:625:625)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Decoder0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1269:1269:1269)) - (PORT datab (1481:1481:1481) (1551:1551:1551)) - (PORT datac (1184:1184:1184) (1246:1246:1246)) - (PORT datad (879:879:879) (933:933:933)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1905:1905:1905) (1929:1929:1929)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2367:2367:2367) (2409:2409:2409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (2051:2051:2051) (2181:2181:2181)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (658:658:658) (671:671:671)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1913:1913:1913) (1931:1931:1931)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1292:1292:1292) (1300:1300:1300)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1250:1250:1250) (1315:1315:1315)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (633:633:633) (646:646:646)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1900:1900:1900) (1925:1925:1925)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2080:2080:2080) (2091:2091:2091)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1760:1760:1760) (1824:1824:1824)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (350:350:350) (366:366:366)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1899:1899:1899) (1923:1923:1923)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2317:2317:2317) (2356:2356:2356)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1559:1559:1559) (1597:1597:1597)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (505:505:505)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (408:408:408) (473:473:473)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (504:504:504)) - (PORT datab (389:389:389) (454:454:454)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (350:350:350) (366:366:366)) + (PORT datad (1196:1196:1196) (1239:1239:1239)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54090,9 +54281,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1870:1870:1870) (1882:1882:1882)) + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1769:1769:1769) (1807:1807:1807)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54106,9 +54297,9 @@ (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1450:1450:1450) (1514:1514:1514)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (1010:1010:1010) (1078:1078:1078)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54122,9 +54313,9 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT datad (1371:1371:1371) (1372:1372:1372)) + (PORT dataa (620:620:620) (643:643:643)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54133,7 +54324,7 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54147,8 +54338,8 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (670:670:670) (727:727:727)) - (PORT datab (603:603:603) (665:665:665)) + (PORT dataa (613:613:613) (667:667:667)) + (PORT datab (243:243:243) (325:325:325)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -54162,14 +54353,14 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (951:951:951) (969:969:969)) - (PORT ena (1738:1738:1738) (1717:1717:1717)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1236:1236:1236) (1237:1237:1237)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -54178,9 +54369,9 @@ (INSTANCE ula_\|video_\|frame\[2\]\~6) (DELAY (ABSOLUTE - (PORT datab (1070:1070:1070) (1118:1118:1118)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (244:244:244) (331:331:331)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54192,14 +54383,14 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (1933:1933:1933) (1957:1957:1957)) - (PORT asdata (1218:1218:1218) (1220:1220:1220)) - (PORT ena (1428:1428:1428) (1397:1397:1397)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1236:1236:1236) (1237:1237:1237)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -54208,9 +54399,9 @@ (INSTANCE ula_\|video_\|frame\[3\]\~8) (DELAY (ABSOLUTE - (PORT dataa (387:387:387) (466:466:466)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (242:242:242) (324:324:324)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54222,9 +54413,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1291:1291:1291) (1293:1293:1293)) + (PORT ena (1236:1236:1236) (1237:1237:1237)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54238,8 +54429,8 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT datad (226:226:226) (298:298:298)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (266:266:266) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -54249,14 +54440,14 @@ (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (661:661:661) (678:678:678)) - (PORT ena (1291:1291:1291) (1293:1293:1293)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1236:1236:1236) (1237:1237:1237)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -54265,7 +54456,7 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (223:223:223) (293:293:293)) + (PORT datad (372:372:372) (423:423:423)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54273,22 +54464,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) + (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (355:355:355) (369:369:369)) + (PORT datad (1154:1154:1154) (1160:1160:1160)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Decoder0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1340:1340:1340)) + (PORT datab (986:986:986) (1064:1064:1064)) + (PORT datac (973:973:973) (1044:1044:1044)) + (PORT datad (279:279:279) (363:363:363)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[2\]) + (INSTANCE ula_\|video_\|bits_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1900:1900:1900) (1924:1924:1924)) + (PORT clk (1915:1915:1915) (1933:1933:1933)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2302:2302:2302) (2299:2299:2299)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (609:609:609) (678:678:678)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1545:1545:1545) (1541:1541:1541)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54299,12 +54558,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[2\]) + (INSTANCE ula_\|video_\|bits\[4\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1781:1781:1781) (1841:1841:1841)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (997:997:997) (1070:1070:1070)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54313,12 +54572,188 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (937:937:937) (955:955:955)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (651:651:651) (725:725:725)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1201:1201:1201) (1243:1243:1243)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (1216:1216:1216) (1295:1295:1295)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (460:460:460)) + (PORT datab (288:288:288) (377:377:377)) + (PORT datad (636:636:636) (698:698:698)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (287:287:287) (374:374:374)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (883:883:883) (890:890:890)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (640:640:640) (711:711:711)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (354:354:354) (367:367:367)) + (PORT datad (1463:1463:1463) (1429:1429:1429)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54328,9 +54763,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1906:1906:1906) (1930:1930:1930)) + (PORT clk (1915:1915:1915) (1933:1933:1933)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2324:2324:2324) (2364:2364:2364)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54344,9 +54779,9 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1205:1205:1205) (1250:1250:1250)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (978:978:978) (1047:1047:1047)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54360,7 +54795,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (354:354:354) (367:367:367)) + (PORT datad (1470:1470:1470) (1502:1502:1502)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54370,9 +54805,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1882:1882:1882) (1892:1892:1892)) + (PORT clk (1915:1915:1915) (1933:1933:1933)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2649:2649:2649) (2699:2699:2699)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54386,7 +54821,7 @@ (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (830:830:830) (872:872:872)) + (PORT datad (642:642:642) (704:704:704)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54396,9 +54831,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1547:1547:1547)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1187:1187:1187) (1160:1160:1160)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54412,8 +54847,8 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datac (622:622:622) (631:631:631)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datad (1276:1276:1276) (1241:1241:1241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54422,9 +54857,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1915:1915:1915) (1933:1933:1933)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1525:1525:1525) (1521:1521:1521)) + (PORT ena (1455:1455:1455) (1444:1444:1444)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54438,9 +54873,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (970:970:970) (1049:1049:1049)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (1448:1448:1448) (1474:1474:1474)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54454,11 +54889,11 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (424:424:424) (506:506:506)) - (PORT datab (421:421:421) (487:487:487)) - (PORT datad (411:411:411) (475:475:475)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (286:286:286) (373:373:373)) + (PORT datad (633:633:633) (694:694:694)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54469,8 +54904,8 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (421:421:421) (505:505:505)) - (PORT datab (242:242:242) (325:325:325)) + (PORT dataa (243:243:243) (329:329:329)) + (PORT datab (287:287:287) (377:377:377)) (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -54484,12 +54919,12 @@ (INSTANCE ula_\|video_\|cindex\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (938:938:938) (1004:1004:1004)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (401:401:401) (477:477:477)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (337:337:337) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54500,195 +54935,25 @@ (INSTANCE ula_\|video_\|cindex\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (430:430:430) (498:498:498)) - (PORT datad (203:203:203) (231:231:231)) + (PORT dataa (245:245:245) (332:332:332)) + (PORT datad (347:347:347) (363:363:363)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (264:264:264) (352:352:352)) - (PORT datab (262:262:262) (344:344:344)) - (PORT datac (234:234:234) (309:309:309)) - (PORT datad (235:235:235) (303:303:303)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (517:517:517)) - (PORT datab (292:292:292) (378:378:378)) - (PORT datac (404:404:404) (473:473:473)) - (PORT datad (364:364:364) (384:384:384)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (518:518:518)) - (PORT datab (272:272:272) (357:357:357)) - (PORT datac (242:242:242) (322:322:322)) - (PORT datad (397:397:397) (464:464:464)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (759:759:759)) - (PORT datab (419:419:419) (499:499:499)) - (PORT datac (656:656:656) (726:726:726)) - (PORT datad (565:565:565) (593:593:593)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~1) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (762:762:762)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (883:883:883) (937:937:937)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (383:383:383)) - (PORT datab (271:271:271) (356:356:356)) - (PORT datac (264:264:264) (345:345:345)) - (PORT datad (264:264:264) (336:336:336)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (530:530:530)) - (PORT datab (290:290:290) (374:374:374)) - (PORT datac (203:203:203) (240:240:240)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (427:427:427) (487:487:487)) - (PORT datad (245:245:245) (317:317:317)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT datab (260:260:260) (342:342:342)) - (PORT datad (242:242:242) (314:314:314)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~0) - (DELAY - (ABSOLUTE - (PORT dataa (272:272:272) (360:360:360)) - (PORT datab (262:262:262) (344:344:344)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datad (632:632:632) (661:661:661)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (2218:2218:2218) (2345:2345:2345)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (1466:1466:1466) (1485:1485:1485)) - (PORT datad (578:578:578) (587:587:587)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (398:398:398) (453:453:453)) + (PORT datab (1490:1490:1490) (1585:1585:1585)) + (PORT datac (235:235:235) (278:278:278)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54699,7 +54964,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (614:614:614) (623:623:623)) + (PORT datad (1157:1157:1157) (1161:1161:1161)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54709,9 +54974,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1876:1876:1876) (1887:1887:1887)) + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2418:2418:2418) (2490:2490:2490)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54725,9 +54990,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (2042:2042:2042) (2159:2159:2159)) - (PORT ena (1470:1470:1470) (1471:1471:1471)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1216:1216:1216) (1269:1269:1269)) + (PORT ena (1638:1638:1638) (1616:1616:1616)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54741,11 +55006,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (659:659:659) (674:674:674)) - (PORT datab (641:641:641) (652:652:652)) - (PORT datad (632:632:632) (661:661:661)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (212:212:212) (261:261:261)) + (PORT datab (208:208:208) (249:249:249)) + (PORT datad (348:348:348) (371:371:371)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54756,11 +55021,11 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1497:1497:1497) (1525:1525:1525)) - (PORT datab (207:207:207) (250:250:250)) - (PORT datad (322:322:322) (343:343:343)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (269:269:269) (322:322:322)) + (PORT datac (391:391:391) (430:430:430)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54770,9 +55035,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1553:1553:1553)) - (PORT asdata (543:543:543) (576:576:576)) - (PORT ena (1232:1232:1232) (1224:1224:1224)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (956:956:956) (977:977:977)) + (PORT ena (812:812:812) (804:804:804)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54786,7 +55051,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (349:349:349) (365:365:365)) + (PORT datad (884:884:884) (889:889:889)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54796,9 +55061,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1882:1882:1882)) + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2092:2092:2092) (2167:2167:2167)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54812,9 +55077,9 @@ (INSTANCE ula_\|video_\|attr\[2\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1737:1737:1737) (1798:1798:1798)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (1208:1208:1208) (1265:1265:1265)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54828,7 +55093,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (634:634:634) (646:646:646)) + (PORT datad (935:935:935) (952:952:952)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54838,9 +55103,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1870:1870:1870) (1883:1883:1883)) + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1883:1883:1883) (1935:1935:1935)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54854,9 +55119,9 @@ (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1552:1552:1552) (1666:1666:1666)) - (PORT ena (1462:1462:1462) (1459:1459:1459)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (993:993:993) (1051:1051:1051)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54870,9 +55135,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (330:330:330)) - (PORT datad (205:205:205) (234:234:234)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54883,13 +55148,13 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (2045:2045:2045) (2150:2150:2150)) - (PORT datab (603:603:603) (623:623:623)) - (PORT datac (1467:1467:1467) (1486:1486:1486)) - (PORT datad (184:184:184) (215:215:215)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (2313:2313:2313) (2480:2480:2480)) + (PORT datab (411:411:411) (449:449:449)) + (PORT datac (384:384:384) (420:420:420)) + (PORT datad (547:547:547) (557:557:557)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54899,33 +55164,49 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1498:1498:1498) (1523:1523:1523)) - (PORT datab (209:209:209) (252:252:252)) - (PORT datad (322:322:322) (341:341:341)) + (PORT dataa (636:636:636) (662:662:662)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datad (378:378:378) (398:398:398)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (203:203:203) (231:231:231)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1553:1553:1553)) + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT asdata (1466:1466:1466) (1519:1519:1519)) + (PORT ena (2116:2116:2116) (2146:2146:2146)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1462:1462:1462) (1430:1430:1430)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1944:1944:1944) (1969:1969:1969)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1232:1232:1232) (1224:1224:1224)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54936,22 +55217,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (INSTANCE ula_\|video_\|attr\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (354:354:354) (367:367:367)) + (PORT datad (839:839:839) (888:888:888)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (INSTANCE ula_\|video_\|attr\[0\]) (DELAY (ABSOLUTE - (PORT clk (1876:1876:1876) (1888:1888:1888)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1535:1535:1535) (1569:1569:1569)) + (PORT ena (1421:1421:1421) (1414:1414:1414)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1276:1276:1276) (1242:1242:1242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1465:1465:1465) (1443:1443:1443)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54960,46 +55267,14 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1547:1547:1547)) - (PORT asdata (1221:1221:1221) (1279:1279:1279)) - (PORT ena (1187:1187:1187) (1160:1160:1160)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1874:1874:1874) (1882:1882:1882)) - (PORT asdata (1233:1233:1233) (1251:1251:1251)) - (PORT ena (1796:1796:1796) (1819:1819:1819)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1547:1547:1547)) - (PORT asdata (894:894:894) (950:950:950)) - (PORT ena (1187:1187:1187) (1160:1160:1160)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT asdata (965:965:965) (1040:1040:1040)) + (PORT ena (1428:1428:1428) (1418:1418:1418)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55013,9 +55288,9 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datad (351:351:351) (366:366:366)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datab (384:384:384) (459:459:459)) + (PORT datad (204:204:204) (232:232:232)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55026,13 +55301,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (2201:2201:2201) (2354:2354:2354)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (546:546:546) (551:551:551)) - (PORT datad (529:529:529) (539:539:539)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (399:399:399) (453:453:453)) + (PORT datab (1662:1662:1662) (1745:1745:1745)) + (PORT datac (233:233:233) (279:279:279)) + (PORT datad (334:334:334) (354:354:354)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55042,9 +55317,9 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (858:858:858) (859:859:859)) - (PORT datac (579:579:579) (582:582:582)) - (PORT datad (586:586:586) (589:589:589)) + (PORT dataa (269:269:269) (323:323:323)) + (PORT datac (391:391:391) (429:429:429)) + (PORT datad (340:340:340) (359:359:359)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -55056,11 +55331,11 @@ (INSTANCE ula_\|video_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (1553:1553:1553) (1640:1640:1640)) - (PORT datac (1191:1191:1191) (1249:1249:1249)) - (PORT datad (1156:1156:1156) (1225:1225:1225)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (681:681:681) (753:753:753)) + (PORT datab (282:282:282) (364:364:364)) + (PORT datad (645:645:645) (715:715:715)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55070,7 +55345,7 @@ (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -55084,11 +55359,11 @@ (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (377:377:377)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datad (204:204:204) (232:232:232)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1030:1030:1030) (1035:1035:1035)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datad (571:571:571) (575:575:575)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55100,7 +55375,7 @@ (DELAY (ABSOLUTE (PORT clk (1509:1509:1509) (1531:1531:1531)) - (PORT d (1706:1706:1706) (1786:1786:1786)) + (PORT d (1715:1715:1715) (1721:1721:1721)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -55114,7 +55389,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1539:1539:1539) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -55128,11 +55403,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (224:224:224) (268:268:268)) - (PORT datab (724:724:724) (792:792:792)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (620:620:620) (642:642:642)) + (PORT datab (1174:1174:1174) (1179:1179:1179)) + (PORT datad (691:691:691) (762:762:762)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55144,7 +55419,7 @@ (DELAY (ABSOLUTE (PORT clk (1507:1507:1507) (1529:1529:1529)) - (PORT d (1568:1568:1568) (1673:1673:1673)) + (PORT d (1805:1805:1805) (1839:1839:1839)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -55158,7 +55433,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (256:256:256) (332:332:332)) + (PORT datad (620:620:620) (667:667:667)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55168,10 +55443,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1537:1537:1537) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (1483:1483:1483) (1473:1473:1473)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55186,10 +55461,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (561:561:561) (635:635:635)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1230:1230:1230) (1213:1213:1213)) + (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT asdata (560:560:560) (634:634:634)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (1483:1483:1483) (1473:1473:1473)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55204,7 +55479,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (249:249:249) (324:324:324)) + (PORT datad (621:621:621) (666:666:666)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55215,9 +55490,9 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT dataa (675:675:675) (793:793:793)) - (PORT datad (252:252:252) (327:327:327)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT datac (1282:1282:1282) (1346:1346:1346)) + (PORT datad (621:621:621) (669:669:669)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55227,12 +55502,10 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT dataa (823:823:823) (851:851:851)) - (PORT datab (910:910:910) (958:958:958)) - (PORT datac (860:860:860) (898:898:898)) - (PORT datad (688:688:688) (779:779:779)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (1714:1714:1714) (1839:1839:1839)) + (PORT datac (3217:3217:3217) (3502:3502:3502)) + (PORT datad (1247:1247:1247) (1342:1342:1342)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55243,9 +55516,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1557:1557:1557)) + (PORT clk (1515:1515:1515) (1529:1529:1529)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1475:1475:1475) (1461:1461:1461)) + (PORT ena (2564:2564:2564) (2572:2572:2572)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) diff --git a/spectrum.qsf b/spectrum.qsf index 24aba4d..09136a5 100644 --- a/spectrum.qsf +++ b/spectrum.qsf @@ -281,8 +281,6 @@ set_location_assignment PIN_A5 -to GPIO_0[8] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] set_location_assignment PIN_D5 -to GPIO_0[9] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] -set_location_assignment PIN_B6 -to GPIO_0[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] #============================================================ # GPIO_1, GPIO_1 connect to GPIO Default @@ -461,4 +459,7 @@ set_global_assignment -name QIP_FILE pll_video.qip set_global_assignment -name SDC_FILE spectrum.sdc set_location_assignment PIN_A6 -to buzzer_out set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to buzzer_out +set_location_assignment PIN_B6 -to raw_loader_in +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to raw_loader_in +set_global_assignment -name QIP_FILE ram_video.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/spectrum.sv b/spectrum.sv index 683ccfa..2ed0853 100644 --- a/spectrum.sv +++ b/spectrum.sv @@ -18,7 +18,8 @@ module spectrum(output wire[7:0] LED, output wire VGA_VS, input wire[3:0] SW, // 0 = ROM selection, 1 = enable/disable interrupts, 2 = turbo speed output wire[33:0] GPIO_1, // Exports CPU chip pins, - output wire buzzer_out + output wire buzzer_out, + input wire raw_loader_in ); `default_nettype none @@ -93,7 +94,10 @@ assign io_we = nIORQ==0 && nRD==1 && nWR==0; always @(*) // always_comb begin case ({nIORQ,nRD,nWR}) - // -------------------------------- Memory read -------------------------------- + // -------------------------------- + + + // Memory read -------------------------------- 3'b101: begin casez (A[15:14]) 2'b00: D[7:0] = rom_data; @@ -139,13 +143,13 @@ wire[7:0] ram0_data; // "A" port is the CPU side, "B" port is the VGA image generator in the ULA ram16 ram0( .clock(CLOCK_50), - +// .clock_a(clk_cpu), .address_a(A[13:0]), .data_a(D), .q_a(ram0_data), .wren_a(RamWE), -// .wren_a(0), +// .clock_b(clk_vram), .address_b({1'b0, vram_address}), .data_b(8'b0), .q_b(vram_data), @@ -157,7 +161,7 @@ ram16 ram0( //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ wire[7:0] ram1_data; ram32 ram1( - .clock(clk_cpu), + .clock(clk_vram), .address(A[14:0]), .data(D), @@ -170,6 +174,7 @@ ram32 ram1( //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ wire clk_cpu; // Global CPU clock of 3.5 MHz assign LED[2:2] = SW[2:2]; // Glow red when in turbo mode (7.0 MHz) +assign LED[3:3] = raw_loader_in; // feedback from audio in wire [12:0] vram_address; // ULA video block requests a byte from the video RAM wire [7:0] vram_data; // ULA video block reads a byte from the video RAM wire vs_nintr; // Generates a vertical retrace interrupt @@ -213,6 +218,7 @@ ula ula_( .AUD_ADCDAT (AUD_ADCDAT), .beeper (beeper), .beep(buzzer_out), + .raw_loader_in(raw_loader_in), //-------- VGA connector -------------------- .VGA_R (VGA_R), diff --git a/ula/ula.sv b/ula/ula.sv index 5136cc4..ca8c33e 100644 --- a/ula/ula.sv +++ b/ula/ula.sv @@ -55,6 +55,7 @@ module ula input wire AUD_ADCDAT, output reg beeper, output reg beep, + input wire raw_loader_in, //-------- VGA connector -------------------- output wire [3:0] VGA_R, @@ -102,7 +103,8 @@ begin pcm_outl[12] <= pcm_inl[14] | pcm_inr[14]; pcm_outr[12] <= pcm_inl[14] | pcm_inr[14]; // Let us see the tape loading! - beep <= (pcm_inl[14] | pcm_inr[14]) ^ D[4] ^ D[3]; +// beep <= (pcm_inl[14] | pcm_inr[14] | raw_loader_in) ^ D[4] ^ D[3]; + beep <= raw_loader_in ^ D[4] ^ D[3]; end end @@ -172,7 +174,8 @@ begin ula_data = 8'hFF; // Regular IO at every odd address: line-in and keyboard if (A[0]==0) begin - ula_data = { 1'b1, pcm_inl[14] | pcm_inr[14], 1'b1, key_row[4:0] }; +// ula_data = { 1'b1, pcm_inl[14] | pcm_inr[14] | raw_loader_in, 1'b1, key_row[4:0] }; + ula_data = { 1'b1, raw_loader_in, 1'b1, key_row[4:0] }; end end